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drm/i915: move VLV DDR freq fetch into init_clock_gating
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
dc730512 312static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 320 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 321 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
b99ab663 324 .p1 = { .min = 2, .max = 3 },
5fdc9c49 325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 326};
327
6b4bf1c4
VS		 328static void vlv_clock(int refclk, intel_clock_t *clock)
329{
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
fb03ac01
VS		 332 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
333 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 334}
335
e0638cdf
PZ		 336/**
337 * Returns whether any output on the specified pipe is of the specified type
338 */
339static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
340{
341 struct drm_device *dev = crtc->dev;
342 struct intel_encoder *encoder;
343
344 for_each_encoder_on_crtc(dev, crtc, encoder)
345 if (encoder->type == type)
346 return true;
347
348 return false;
349}
350
1b894b59
CW		 351static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
352 int refclk)
2c07245f 353{
b91ad0ec 354 struct drm_device *dev = crtc->dev;
2c07245f 355 const intel_limit_t *limit;
b91ad0ec
ZW		 356
357 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 358 if (intel_is_dual_link_lvds(dev)) {
1b894b59 359 if (refclk == 100000)
b91ad0ec
ZW		 360 limit = &intel_limits_ironlake_dual_lvds_100m;
361 else
362 limit = &intel_limits_ironlake_dual_lvds;
363 } else {
1b894b59 364 if (refclk == 100000)
b91ad0ec
ZW		 365 limit = &intel_limits_ironlake_single_lvds_100m;
366 else
367 limit = &intel_limits_ironlake_single_lvds;
368 }
c6bb3538 369 } else
b91ad0ec 370 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 371
372 return limit;
373}
374
044c7c41
ML		 375static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
376{
377 struct drm_device *dev = crtc->dev;
044c7c41
ML		 378 const intel_limit_t *limit;
379
380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 381 if (intel_is_dual_link_lvds(dev))
e4b36699 382 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 383 else
e4b36699 384 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 385 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
386 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 387 limit = &intel_limits_g4x_hdmi;
044c7c41 388 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 389 limit = &intel_limits_g4x_sdvo;
044c7c41 390 } else /* The option is for other outputs */
e4b36699 391 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 392
393 return limit;
394}
395
1b894b59 396static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 397{
398 struct drm_device *dev = crtc->dev;
399 const intel_limit_t *limit;
400
bad720ff 401 if (HAS_PCH_SPLIT(dev))
1b894b59 402 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 403 else if (IS_G4X(dev)) {
044c7c41 404 limit = intel_g4x_limit(crtc);
f2b115e6 405 } else if (IS_PINEVIEW(dev)) {
2177832f 406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 407 limit = &intel_limits_pineview_lvds;
2177832f 408 else
f2b115e6 409 limit = &intel_limits_pineview_sdvo;
a0c4da24 410 } else if (IS_VALLEYVIEW(dev)) {
dc730512 411 limit = &intel_limits_vlv;
a6c45cf0
CW		 412 } else if (!IS_GEN2(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
414 limit = &intel_limits_i9xx_lvds;
415 else
416 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 417 } else {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 419 limit = &intel_limits_i8xx_lvds;
5d536e28 420 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 421 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 422 else
423 limit = &intel_limits_i8xx_dac;
79e53945
JB		 424 }
425 return limit;
426}
427
f2b115e6
AJ		 428/* m1 is reserved as 0 in Pineview, n is a ring counter */
429static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 430{
2177832f
SL		 431 clock->m = clock->m2 + 2;
432 clock->p = clock->p1 * clock->p2;
fb03ac01
VS		 433 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
434 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 435}
436
7429e9d4
DV		 437static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
438{
439 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
440}
441
ac58c3f0 442static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 443{
7429e9d4 444 clock->m = i9xx_dpll_compute_m(clock);
79e53945 445 clock->p = clock->p1 * clock->p2;
fb03ac01
VS		 446 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
447 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 448}
449
7c04d1d9 450#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 451/**
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
454 */
455
1b894b59
CW		 456static bool intel_PLL_is_valid(struct drm_device *dev,
457 const intel_limit_t *limit,
458 const intel_clock_t *clock)
79e53945 459{
f01b7962
VS		 460 if (clock->n < limit->n.min || limit->n.max < clock->n)
461 INTELPllInvalid("n out of range\n");
79e53945 462 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 463 INTELPllInvalid("p1 out of range\n");
79e53945 464 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 465 INTELPllInvalid("m2 out of range\n");
79e53945 466 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 467 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 468
469 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
470 if (clock->m1 <= clock->m2)
471 INTELPllInvalid("m1 <= m2\n");
472
473 if (!IS_VALLEYVIEW(dev)) {
474 if (clock->p < limit->p.min || limit->p.max < clock->p)
475 INTELPllInvalid("p out of range\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
478 }
479
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24 672{
f01b7962 673 struct drm_device *dev = crtc->dev;
6b4bf1c4 674 intel_clock_t clock;
69e4f900 675 unsigned int bestppm = 1000000;
27e639bf
VS		 676 /* min update 19.2 MHz */
677 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 678 bool found = false;
a0c4da24 679
6b4bf1c4
VS		 680 target *= 5; /* fast clock */
681
682 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 683
684 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 685 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 686 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 687 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 688 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 689 clock.p = clock.p1 * clock.p2;
a0c4da24 690 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
69e4f900
VS		 692 unsigned int ppm, diff;
693
6b4bf1c4
VS		 694 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
695 refclk * clock.m1);
696
697 vlv_clock(refclk, &clock);
43b0ac53 698
f01b7962
VS		 699 if (!intel_PLL_is_valid(dev, limit,
700 &clock))
43b0ac53
VS		 701 continue;
702
6b4bf1c4
VS		 703 diff = abs(clock.dot - target);
704 ppm = div_u64(1000000ULL * diff, target);
705
706 if (ppm < 100 && clock.p > best_clock->p) {
43b0ac53 707 bestppm = 0;
6b4bf1c4 708 *best_clock = clock;
49e497ef 709 found = true;
43b0ac53 710 }
6b4bf1c4 711
c686122c 712 if (bestppm >= 10 && ppm < bestppm - 10) {
69e4f900 713 bestppm = ppm;
6b4bf1c4 714 *best_clock = clock;
49e497ef 715 found = true;
a0c4da24
JB		 716 }
717 }
718 }
719 }
720 }
a0c4da24 721
49e497ef 722 return found;
a0c4da24 723}
a4fc5ed6 724
20ddf665
VS		 725bool intel_crtc_active(struct drm_crtc *crtc)
726{
727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
728
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
731 *
241bfc38 732 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 733 * as Haswell has gained clock readout/fastboot support.
734 *
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
737 */
738 return intel_crtc->active && crtc->fb &&
241bfc38 739 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 740}
741
a5c961d1
PZ		 742enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
743 enum pipe pipe)
744{
745 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
747
3b117c8f 748 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 749}
750
a928d536
PZ		 751static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
752{
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 u32 frame, frame_reg = PIPEFRAME(pipe);
755
756 frame = I915_READ(frame_reg);
757
758 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
760}
761
9d0498a2
JB		 762/**
763 * intel_wait_for_vblank - wait for vblank on a given pipe
764 * @dev: drm device
765 * @pipe: pipe to wait for
766 *
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
768 * mode setting code.
769 */
770void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 771{
9d0498a2 772 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 773 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 774
a928d536
PZ		 775 if (INTEL_INFO(dev)->gen >= 5) {
776 ironlake_wait_for_vblank(dev, pipe);
777 return;
778 }
779
300387c0
CW		 780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
782 *
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
789 * vblanks...
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
792 */
793 I915_WRITE(pipestat_reg,
794 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
795
9d0498a2 796 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 797 if (wait_for(I915_READ(pipestat_reg) &
798 PIPE_VBLANK_INTERRUPT_STATUS,
799 50))
9d0498a2
JB		 800 DRM_DEBUG_KMS("vblank wait timed out\n");
801}
802
fbf49ea2
VS		 803static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
804{
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 u32 reg = PIPEDSL(pipe);
807 u32 line1, line2;
808 u32 line_mask;
809
810 if (IS_GEN2(dev))
811 line_mask = DSL_LINEMASK_GEN2;
812 else
813 line_mask = DSL_LINEMASK_GEN3;
814
815 line1 = I915_READ(reg) & line_mask;
816 mdelay(5);
817 line2 = I915_READ(reg) & line_mask;
818
819 return line1 == line2;
820}
821
ab7ad7f6
KP		 822/*
823 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 824 * @dev: drm device
825 * @pipe: pipe to wait for
826 *
827 * After disabling a pipe, we can't wait for vblank in the usual way,
828 * spinning on the vblank interrupt status bit, since we won't actually
829 * see an interrupt when the pipe is disabled.
830 *
ab7ad7f6
KP		 831 * On Gen4 and above:
832 * wait for the pipe register state bit to turn off
833 *
834 * Otherwise:
835 * wait for the display line value to settle (it usually
836 * ends up stopping at the start of the next frame).
58e10eb9 837 *
9d0498a2 838 */
58e10eb9 839void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 840{
841 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 842 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
843 pipe);
ab7ad7f6
KP		 844
845 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 846 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 847
848 /* Wait for the Pipe State to go off */
58e10eb9
CW		 849 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
850 100))
284637d9 851 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 852 } else {
ab7ad7f6 853 /* Wait for the display line to settle */
fbf49ea2 854 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 855 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 856 }
79e53945
JB		 857}
858
b0ea7d37
DL		 859/*
860 * ibx_digital_port_connected - is the specified port connected?
861 * @dev_priv: i915 private structure
862 * @port: the port to test
863 *
864 * Returns true if @port is connected, false otherwise.
865 */
866bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
867 struct intel_digital_port *port)
868{
869 u32 bit;
870
c36346e3
DL		 871 if (HAS_PCH_IBX(dev_priv->dev)) {
872 switch(port->port) {
873 case PORT_B:
874 bit = SDE_PORTB_HOTPLUG;
875 break;
876 case PORT_C:
877 bit = SDE_PORTC_HOTPLUG;
878 break;
879 case PORT_D:
880 bit = SDE_PORTD_HOTPLUG;
881 break;
882 default:
883 return true;
884 }
885 } else {
886 switch(port->port) {
887 case PORT_B:
888 bit = SDE_PORTB_HOTPLUG_CPT;
889 break;
890 case PORT_C:
891 bit = SDE_PORTC_HOTPLUG_CPT;
892 break;
893 case PORT_D:
894 bit = SDE_PORTD_HOTPLUG_CPT;
895 break;
896 default:
897 return true;
898 }
b0ea7d37
DL		 899 }
900
901 return I915_READ(SDEISR) & bit;
902}
903
b24e7179
JB		 904static const char *state_string(bool enabled)
905{
906 return enabled ? "on" : "off";
907}
908
909/* Only for pre-ILK configs */
55607e8a
DV		 910void assert_pll(struct drm_i915_private *dev_priv,
911 enum pipe pipe, bool state)
b24e7179
JB		 912{
913 int reg;
914 u32 val;
915 bool cur_state;
916
917 reg = DPLL(pipe);
918 val = I915_READ(reg);
919 cur_state = !!(val & DPLL_VCO_ENABLE);
920 WARN(cur_state != state,
921 "PLL state assertion failure (expected %s, current %s)\n",
922 state_string(state), state_string(cur_state));
923}
b24e7179 924
23538ef1
JN		 925/* XXX: the dsi pll is shared between MIPI DSI ports */
926static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
927{
928 u32 val;
929 bool cur_state;
930
931 mutex_lock(&dev_priv->dpio_lock);
932 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
933 mutex_unlock(&dev_priv->dpio_lock);
934
935 cur_state = val & DSI_PLL_VCO_EN;
936 WARN(cur_state != state,
937 "DSI PLL state assertion failure (expected %s, current %s)\n",
938 state_string(state), state_string(cur_state));
939}
940#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
941#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
942
55607e8a 943struct intel_shared_dpll *
e2b78267
DV		 944intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
945{
946 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
947
a43f6e0f 948 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 949 return NULL;
950
a43f6e0f 951 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 952}
953
040484af 954/* For ILK+ */
55607e8a
DV		 955void assert_shared_dpll(struct drm_i915_private *dev_priv,
956 struct intel_shared_dpll *pll,
957 bool state)
040484af 958{
040484af 959 bool cur_state;
5358901f 960 struct intel_dpll_hw_state hw_state;
040484af 961
9d82aa17
ED		 962 if (HAS_PCH_LPT(dev_priv->dev)) {
963 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
964 return;
965 }
966
92b27b08 967 if (WARN (!pll,
46edb027 968 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 969 return;
ee7b9f93 970
5358901f 971 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 972 WARN(cur_state != state,
5358901f
DV		 973 "%s assertion failure (expected %s, current %s)\n",
974 pll->name, state_string(state), state_string(cur_state));
040484af 975}
040484af
JB		 976
977static void assert_fdi_tx(struct drm_i915_private *dev_priv,
978 enum pipe pipe, bool state)
979{
980 int reg;
981 u32 val;
982 bool cur_state;
ad80a810
PZ		 983 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
984 pipe);
040484af 985
affa9354
PZ		 986 if (HAS_DDI(dev_priv->dev)) {
987 /* DDI does not have a specific FDI_TX register */
ad80a810 988 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 989 val = I915_READ(reg);
ad80a810 990 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 991 } else {
992 reg = FDI_TX_CTL(pipe);
993 val = I915_READ(reg);
994 cur_state = !!(val & FDI_TX_ENABLE);
995 }
040484af
JB		 996 WARN(cur_state != state,
997 "FDI TX state assertion failure (expected %s, current %s)\n",
998 state_string(state), state_string(cur_state));
999}
1000#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1002
1003static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1004 enum pipe pipe, bool state)
1005{
1006 int reg;
1007 u32 val;
1008 bool cur_state;
1009
d63fa0dc
PZ		 1010 reg = FDI_RX_CTL(pipe);
1011 val = I915_READ(reg);
1012 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1013 WARN(cur_state != state,
1014 "FDI RX state assertion failure (expected %s, current %s)\n",
1015 state_string(state), state_string(cur_state));
1016}
1017#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1019
1020static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 /* ILK FDI PLL is always enabled */
1027 if (dev_priv->info->gen == 5)
1028 return;
1029
bf507ef7 1030 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1031 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1032 return;
1033
040484af
JB		 1034 reg = FDI_TX_CTL(pipe);
1035 val = I915_READ(reg);
1036 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1037}
1038
55607e8a
DV		 1039void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
040484af
JB		 1041{
1042 int reg;
1043 u32 val;
55607e8a 1044 bool cur_state;
040484af
JB		 1045
1046 reg = FDI_RX_CTL(pipe);
1047 val = I915_READ(reg);
55607e8a
DV		 1048 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1049 WARN(cur_state != state,
1050 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
040484af
JB		 1052}
1053
ea0760cf
JB		 1054static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1055 enum pipe pipe)
1056{
1057 int pp_reg, lvds_reg;
1058 u32 val;
1059 enum pipe panel_pipe = PIPE_A;
0de3b485 1060 bool locked = true;
ea0760cf
JB		 1061
1062 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063 pp_reg = PCH_PP_CONTROL;
1064 lvds_reg = PCH_LVDS;
1065 } else {
1066 pp_reg = PP_CONTROL;
1067 lvds_reg = LVDS;
1068 }
1069
1070 val = I915_READ(pp_reg);
1071 if (!(val & PANEL_POWER_ON) ||
1072 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1073 locked = false;
1074
1075 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1076 panel_pipe = PIPE_B;
1077
1078 WARN(panel_pipe == pipe && locked,
1079 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1080 pipe_name(pipe));
ea0760cf
JB		 1081}
1082
93ce0ba6
JN		 1083static void assert_cursor(struct drm_i915_private *dev_priv,
1084 enum pipe pipe, bool state)
1085{
1086 struct drm_device *dev = dev_priv->dev;
1087 bool cur_state;
1088
1089 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1090 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1091 else if (IS_845G(dev) || IS_I865G(dev))
1092 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1093 else
1094 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1095
1096 WARN(cur_state != state,
1097 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098 pipe_name(pipe), state_string(state), state_string(cur_state));
1099}
1100#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1102
b840d907
JB		 1103void assert_pipe(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool state)
b24e7179
JB		 1105{
1106 int reg;
1107 u32 val;
63d7bbe9 1108 bool cur_state;
702e7a56
PZ		 1109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110 pipe);
b24e7179 1111
8e636784
DV		 1112 /* if we need the pipe A quirk it must be always on */
1113 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114 state = true;
1115
b97186f0
PZ		 1116 if (!intel_display_power_enabled(dev_priv->dev,
1117 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1118 cur_state = false;
1119 } else {
1120 reg = PIPECONF(cpu_transcoder);
1121 val = I915_READ(reg);
1122 cur_state = !!(val & PIPECONF_ENABLE);
1123 }
1124
63d7bbe9
JB		 1125 WARN(cur_state != state,
1126 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1127 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1128}
1129
931872fc
CW		 1130static void assert_plane(struct drm_i915_private *dev_priv,
1131 enum plane plane, bool state)
b24e7179
JB		 1132{
1133 int reg;
1134 u32 val;
931872fc 1135 bool cur_state;
b24e7179
JB		 1136
1137 reg = DSPCNTR(plane);
1138 val = I915_READ(reg);
931872fc
CW		 1139 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140 WARN(cur_state != state,
1141 "plane %c assertion failure (expected %s, current %s)\n",
1142 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1143}
1144
931872fc
CW		 1145#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
b24e7179
JB		 1148static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149 enum pipe pipe)
1150{
653e1026 1151 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1152 int reg, i;
1153 u32 val;
1154 int cur_pipe;
1155
653e1026
VS		 1156 /* Primary planes are fixed to pipes on gen4+ */
1157 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1158 reg = DSPCNTR(pipe);
1159 val = I915_READ(reg);
1160 WARN((val & DISPLAY_PLANE_ENABLE),
1161 "plane %c assertion failure, should be disabled but not\n",
1162 plane_name(pipe));
19ec1358 1163 return;
28c05794 1164 }
19ec1358 1165
b24e7179 1166 /* Need to check both planes against the pipe */
08e2a7de 1167 for_each_pipe(i) {
b24e7179
JB		 1168 reg = DSPCNTR(i);
1169 val = I915_READ(reg);
1170 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1171 DISPPLANE_SEL_PIPE_SHIFT;
1172 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1173 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1175 }
1176}
1177
19332d7a
JB		 1178static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1179 enum pipe pipe)
1180{
20674eef 1181 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1182 int reg, i;
1183 u32 val;
1184
20674eef
VS		 1185 if (IS_VALLEYVIEW(dev)) {
1186 for (i = 0; i < dev_priv->num_plane; i++) {
1187 reg = SPCNTR(pipe, i);
1188 val = I915_READ(reg);
1189 WARN((val & SP_ENABLE),
1190 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191 sprite_name(pipe, i), pipe_name(pipe));
1192 }
1193 } else if (INTEL_INFO(dev)->gen >= 7) {
1194 reg = SPRCTL(pipe);
19332d7a 1195 val = I915_READ(reg);
20674eef 1196 WARN((val & SPRITE_ENABLE),
06da8da2 1197 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1198 plane_name(pipe), pipe_name(pipe));
1199 } else if (INTEL_INFO(dev)->gen >= 5) {
1200 reg = DVSCNTR(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & DVS_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1204 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1205 }
1206}
1207
92f2584a
JB		 1208static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1209{
1210 u32 val;
1211 bool enabled;
1212
9d82aa17
ED		 1213 if (HAS_PCH_LPT(dev_priv->dev)) {
1214 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1215 return;
1216 }
1217
92f2584a
JB		 1218 val = I915_READ(PCH_DREF_CONTROL);
1219 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1220 DREF_SUPERSPREAD_SOURCE_MASK));
1221 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1222}
1223
ab9412ba
DV		 1224static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe)
92f2584a
JB		 1226{
1227 int reg;
1228 u32 val;
1229 bool enabled;
1230
ab9412ba 1231 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1232 val = I915_READ(reg);
1233 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1234 WARN(enabled,
1235 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1236 pipe_name(pipe));
92f2584a
JB		 1237}
1238
4e634389
KP		 1239static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1241{
1242 if ((val & DP_PORT_EN) == 0)
1243 return false;
1244
1245 if (HAS_PCH_CPT(dev_priv->dev)) {
1246 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1247 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1248 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1249 return false;
1250 } else {
1251 if ((val & DP_PIPE_MASK) != (pipe << 30))
1252 return false;
1253 }
1254 return true;
1255}
1256
1519b995
KP		 1257static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1258 enum pipe pipe, u32 val)
1259{
dc0fa718 1260 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1261 return false;
1262
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1264 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1265 return false;
1266 } else {
dc0fa718 1267 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1268 return false;
1269 }
1270 return true;
1271}
1272
1273static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, u32 val)
1275{
1276 if ((val & LVDS_PORT_EN) == 0)
1277 return false;
1278
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1284 return false;
1285 }
1286 return true;
1287}
1288
1289static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, u32 val)
1291{
1292 if ((val & ADPA_DAC_ENABLE) == 0)
1293 return false;
1294 if (HAS_PCH_CPT(dev_priv->dev)) {
1295 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1296 return false;
1297 } else {
1298 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1299 return false;
1300 }
1301 return true;
1302}
1303
291906f1 1304static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1305 enum pipe pipe, int reg, u32 port_sel)
291906f1 1306{
47a05eca 1307 u32 val = I915_READ(reg);
4e634389 1308 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1309 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1310 reg, pipe_name(pipe));
de9a35ab 1311
75c5da27
DV		 1312 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1313 && (val & DP_PIPEB_SELECT),
de9a35ab 1314 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1315}
1316
1317static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, int reg)
1319{
47a05eca 1320 u32 val = I915_READ(reg);
b70ad586 1321 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1322 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1323 reg, pipe_name(pipe));
de9a35ab 1324
dc0fa718 1325 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1326 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1327 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1328}
1329
1330static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1331 enum pipe pipe)
1332{
1333 int reg;
1334 u32 val;
291906f1 1335
f0575e92
KP		 1336 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1337 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1338 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1339
1340 reg = PCH_ADPA;
1341 val = I915_READ(reg);
b70ad586 1342 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1343 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1344 pipe_name(pipe));
291906f1
JB		 1345
1346 reg = PCH_LVDS;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1 1351
e2debe91
PZ		 1352 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1353 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1354 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1355}
1356
40e9cf64
JB		 1357static void intel_init_dpio(struct drm_device *dev)
1358{
1359 struct drm_i915_private *dev_priv = dev->dev_private;
1360
1361 if (!IS_VALLEYVIEW(dev))
1362 return;
1363
1364 /*
1365 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1367 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368 * b. The other bits such as sfr settings / modesel may all be set
1369 * to 0.
1370 *
1371 * This should only be done on init and resume from S3 with both
1372 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1373 */
1374 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1375}
1376
426115cf 1377static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1378{
426115cf
DV		 1379 struct drm_device *dev = crtc->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 int reg = DPLL(crtc->pipe);
1382 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1383
426115cf 1384 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1385
1386 /* No really, not for ILK+ */
1387 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1388
1389 /* PLL is protected by panel, make sure we can write it */
1390 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1391 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1392
426115cf
DV		 1393 I915_WRITE(reg, dpll);
1394 POSTING_READ(reg);
1395 udelay(150);
1396
1397 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1398 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1399
1400 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1401 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1402
1403 /* We do this three times for luck */
426115cf 1404 I915_WRITE(reg, dpll);
87442f73
DV		 1405 POSTING_READ(reg);
1406 udelay(150); /* wait for warmup */
426115cf 1407 I915_WRITE(reg, dpll);
87442f73
DV		 1408 POSTING_READ(reg);
1409 udelay(150); /* wait for warmup */
426115cf 1410 I915_WRITE(reg, dpll);
87442f73
DV		 1411 POSTING_READ(reg);
1412 udelay(150); /* wait for warmup */
1413}
1414
66e3d5c0 1415static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1416{
66e3d5c0
DV		 1417 struct drm_device *dev = crtc->base.dev;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 int reg = DPLL(crtc->pipe);
1420 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1421
66e3d5c0 1422 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1423
63d7bbe9 1424 /* No really, not for ILK+ */
87442f73 1425 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1426
1427 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1428 if (IS_MOBILE(dev) && !IS_I830(dev))
1429 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1430
66e3d5c0
DV		 1431 I915_WRITE(reg, dpll);
1432
1433 /* Wait for the clocks to stabilize. */
1434 POSTING_READ(reg);
1435 udelay(150);
1436
1437 if (INTEL_INFO(dev)->gen >= 4) {
1438 I915_WRITE(DPLL_MD(crtc->pipe),
1439 crtc->config.dpll_hw_state.dpll_md);
1440 } else {
1441 /* The pixel multiplier can only be updated once the
1442 * DPLL is enabled and the clocks are stable.
1443 *
1444 * So write it again.
1445 */
1446 I915_WRITE(reg, dpll);
1447 }
63d7bbe9
JB		 1448
1449 /* We do this three times for luck */
66e3d5c0 1450 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1451 POSTING_READ(reg);
1452 udelay(150); /* wait for warmup */
66e3d5c0 1453 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1454 POSTING_READ(reg);
1455 udelay(150); /* wait for warmup */
66e3d5c0 1456 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1457 POSTING_READ(reg);
1458 udelay(150); /* wait for warmup */
1459}
1460
1461/**
50b44a44 1462 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1463 * @dev_priv: i915 private structure
1464 * @pipe: pipe PLL to disable
1465 *
1466 * Disable the PLL for @pipe, making sure the pipe is off first.
1467 *
1468 * Note! This is for pre-ILK only.
1469 */
50b44a44 1470static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1471{
63d7bbe9
JB		 1472 /* Don't disable pipe A or pipe A PLLs if needed */
1473 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1474 return;
1475
1476 /* Make sure the pipe isn't still relying on us */
1477 assert_pipe_disabled(dev_priv, pipe);
1478
50b44a44
DV		 1479 I915_WRITE(DPLL(pipe), 0);
1480 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1481}
1482
f6071166
JB		 1483static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1484{
1485 u32 val = 0;
1486
1487 /* Make sure the pipe isn't still relying on us */
1488 assert_pipe_disabled(dev_priv, pipe);
1489
1490 /* Leave integrated clock source enabled */
1491 if (pipe == PIPE_B)
1492 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1493 I915_WRITE(DPLL(pipe), val);
1494 POSTING_READ(DPLL(pipe));
1495}
1496
89b667f8
JB		 1497void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1498{
1499 u32 port_mask;
1500
1501 if (!port)
1502 port_mask = DPLL_PORTB_READY_MASK;
1503 else
1504 port_mask = DPLL_PORTC_READY_MASK;
1505
1506 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508 'B' + port, I915_READ(DPLL(0)));
1509}
1510
92f2584a 1511/**
e72f9fbf 1512 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1513 * @dev_priv: i915 private structure
1514 * @pipe: pipe PLL to enable
1515 *
1516 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517 * drives the transcoder clock.
1518 */
e2b78267 1519static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1520{
e2b78267
DV		 1521 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1523
48da64a8 1524 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1525 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1526 if (WARN_ON(pll == NULL))
48da64a8
CW		 1527 return;
1528
1529 if (WARN_ON(pll->refcount == 0))
1530 return;
ee7b9f93 1531
46edb027
DV		 1532 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533 pll->name, pll->active, pll->on,
e2b78267 1534 crtc->base.base.id);
92f2584a 1535
cdbd2316
DV		 1536 if (pll->active++) {
1537 WARN_ON(!pll->on);
e9d6944e 1538 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1539 return;
1540 }
f4a091c7 1541 WARN_ON(pll->on);
ee7b9f93 1542
46edb027 1543 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1544 pll->enable(dev_priv, pll);
ee7b9f93 1545 pll->on = true;
92f2584a
JB		 1546}
1547
e2b78267 1548static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1549{
e2b78267
DV		 1550 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1551 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1552
92f2584a
JB		 1553 /* PCH only available on ILK+ */
1554 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1555 if (WARN_ON(pll == NULL))
ee7b9f93 1556 return;
92f2584a 1557
48da64a8
CW		 1558 if (WARN_ON(pll->refcount == 0))
1559 return;
7a419866 1560
46edb027
DV		 1561 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562 pll->name, pll->active, pll->on,
e2b78267 1563 crtc->base.base.id);
7a419866 1564
48da64a8 1565 if (WARN_ON(pll->active == 0)) {
e9d6944e 1566 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1567 return;
1568 }
1569
e9d6944e 1570 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1571 WARN_ON(!pll->on);
cdbd2316 1572 if (--pll->active)
7a419866 1573 return;
ee7b9f93 1574
46edb027 1575 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1576 pll->disable(dev_priv, pll);
ee7b9f93 1577 pll->on = false;
92f2584a
JB		 1578}
1579
b8a4f404
PZ		 1580static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
040484af 1582{
23670b32 1583 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1586 uint32_t reg, val, pipeconf_val;
040484af
JB		 1587
1588 /* PCH only available on ILK+ */
1589 BUG_ON(dev_priv->info->gen < 5);
1590
1591 /* Make sure PCH DPLL is enabled */
e72f9fbf 1592 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1593 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
23670b32
DV		 1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
59c859d6 1606 }
23670b32 1607
ab9412ba 1608 reg = PCH_TRANSCONF(pipe);
040484af 1609 val = I915_READ(reg);
5f7f726d 1610 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
dfd07d72
DV		 1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1619 }
5f7f726d
PZ		 1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
040484af
JB		 1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1634}
1635
8fb033d7 1636static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1637 enum transcoder cpu_transcoder)
040484af 1638{
8fb033d7 1639 u32 val, pipeconf_val;
8fb033d7
PZ		 1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
8fb033d7 1644 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1647
223a6fdf
PZ		 1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
25f3ef11 1653 val = TRANS_ENABLE;
937bb610 1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1655
9a76b1c6
PZ		 1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
a35f2679 1658 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
ab9412ba
DV		 1662 I915_WRITE(LPT_TRANSCONF, val);
1663 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1664 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1665}
1666
b8a4f404
PZ		 1667static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
040484af 1669{
23670b32
DV		 1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
040484af
JB		 1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
291906f1
JB		 1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
ab9412ba 1680 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
040484af
JB		 1695}
1696
ab4d966c 1697static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1698{
8fb033d7
PZ		 1699 u32 val;
1700
ab9412ba 1701 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1702 val &= ~TRANS_ENABLE;
ab9412ba 1703 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1704 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1705 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1706 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1711 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1712}
1713
b24e7179 1714/**
309cfea8 1715 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
040484af 1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
040484af 1728static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1729 bool pch_port, bool dsi)
b24e7179 1730{
702e7a56
PZ		 1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1a240d4d 1733 enum pipe pch_transcoder;
b24e7179
JB		 1734 int reg;
1735 u32 val;
1736
58c6eaa2 1737 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1738 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1739 assert_sprites_disabled(dev_priv, pipe);
1740
681e5811 1741 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1742 pch_transcoder = TRANSCODER_A;
1743 else
1744 pch_transcoder = pipe;
1745
b24e7179
JB		 1746 /*
1747 * A pipe without a PLL won't actually be able to drive bits from
1748 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1749 * need the check.
1750 */
1751 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1752 if (dsi)
1753 assert_dsi_pll_enabled(dev_priv);
1754 else
1755 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1756 else {
1757 if (pch_port) {
1758 /* if driving the PCH, we need FDI enabled */
cc391bbb 1759 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1760 assert_fdi_tx_pll_enabled(dev_priv,
1761 (enum pipe) cpu_transcoder);
040484af
JB		 1762 }
1763 /* FIXME: assert CPU port conditions for SNB+ */
1764 }
b24e7179 1765
702e7a56 1766 reg = PIPECONF(cpu_transcoder);
b24e7179 1767 val = I915_READ(reg);
00d70b15
CW		 1768 if (val & PIPECONF_ENABLE)
1769 return;
1770
1771 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1772 intel_wait_for_vblank(dev_priv->dev, pipe);
1773}
1774
1775/**
309cfea8 1776 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1777 * @dev_priv: i915 private structure
1778 * @pipe: pipe to disable
1779 *
1780 * Disable @pipe, making sure that various hardware specific requirements
1781 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1782 *
1783 * @pipe should be %PIPE_A or %PIPE_B.
1784 *
1785 * Will wait until the pipe has shut down before returning.
1786 */
1787static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1788 enum pipe pipe)
1789{
702e7a56
PZ		 1790 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1791 pipe);
b24e7179
JB		 1792 int reg;
1793 u32 val;
1794
1795 /*
1796 * Make sure planes won't keep trying to pump pixels to us,
1797 * or we might hang the display.
1798 */
1799 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1800 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1801 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1802
1803 /* Don't disable pipe A or pipe A PLLs if needed */
1804 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1805 return;
1806
702e7a56 1807 reg = PIPECONF(cpu_transcoder);
b24e7179 1808 val = I915_READ(reg);
00d70b15
CW		 1809 if ((val & PIPECONF_ENABLE) == 0)
1810 return;
1811
1812 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1813 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1814}
1815
d74362c9
KP		 1816/*
1817 * Plane regs are double buffered, going from enabled->disabled needs a
1818 * trigger in order to latch. The display address reg provides this.
1819 */
1dba99f4
VS		 1820void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane)
d74362c9 1822{
1dba99f4
VS		 1823 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1824
1825 I915_WRITE(reg, I915_READ(reg));
1826 POSTING_READ(reg);
d74362c9
KP		 1827}
1828
b24e7179 1829/**
d1de00ef 1830 * intel_enable_primary_plane - enable the primary plane on a given pipe
b24e7179
JB		 1831 * @dev_priv: i915 private structure
1832 * @plane: plane to enable
1833 * @pipe: pipe being fed
1834 *
1835 * Enable @plane on @pipe, making sure that @pipe is running first.
1836 */
d1de00ef
VS		 1837static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1838 enum plane plane, enum pipe pipe)
b24e7179 1839{
939c2fe8
VS		 1840 struct intel_crtc *intel_crtc =
1841 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
b24e7179
JB		 1842 int reg;
1843 u32 val;
1844
1845 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846 assert_pipe_enabled(dev_priv, pipe);
1847
4c445e0e 1848 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
0037f71c 1849
4c445e0e 1850 intel_crtc->primary_enabled = true;
939c2fe8 1851
b24e7179
JB		 1852 reg = DSPCNTR(plane);
1853 val = I915_READ(reg);
00d70b15
CW		 1854 if (val & DISPLAY_PLANE_ENABLE)
1855 return;
1856
1857 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1dba99f4 1858 intel_flush_primary_plane(dev_priv, plane);
b24e7179
JB		 1859 intel_wait_for_vblank(dev_priv->dev, pipe);
1860}
1861
b24e7179 1862/**
d1de00ef 1863 * intel_disable_primary_plane - disable the primary plane
b24e7179
JB		 1864 * @dev_priv: i915 private structure
1865 * @plane: plane to disable
1866 * @pipe: pipe consuming the data
1867 *
1868 * Disable @plane; should be an independent operation.
1869 */
d1de00ef
VS		 1870static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1871 enum plane plane, enum pipe pipe)
b24e7179 1872{
939c2fe8
VS		 1873 struct intel_crtc *intel_crtc =
1874 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
b24e7179
JB		 1875 int reg;
1876 u32 val;
1877
4c445e0e 1878 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
0037f71c 1879
4c445e0e 1880 intel_crtc->primary_enabled = false;
939c2fe8 1881
b24e7179
JB		 1882 reg = DSPCNTR(plane);
1883 val = I915_READ(reg);
00d70b15
CW		 1884 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1885 return;
1886
1887 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1dba99f4 1888 intel_flush_primary_plane(dev_priv, plane);
b24e7179
JB		 1889 intel_wait_for_vblank(dev_priv->dev, pipe);
1890}
1891
693db184
CW		 1892static bool need_vtd_wa(struct drm_device *dev)
1893{
1894#ifdef CONFIG_INTEL_IOMMU
1895 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1896 return true;
1897#endif
1898 return false;
1899}
1900
127bd2ac 1901int
48b956c5 1902intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1903 struct drm_i915_gem_object *obj,
919926ae 1904 struct intel_ring_buffer *pipelined)
6b95a207 1905{
ce453d81 1906 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1907 u32 alignment;
1908 int ret;
1909
05394f39 1910 switch (obj->tiling_mode) {
6b95a207 1911 case I915_TILING_NONE:
534843da
CW		 1912 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1913 alignment = 128 * 1024;
a6c45cf0 1914 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1915 alignment = 4 * 1024;
1916 else
1917 alignment = 64 * 1024;
6b95a207
KH		 1918 break;
1919 case I915_TILING_X:
1920 /* pin() will align the object as required by fence */
1921 alignment = 0;
1922 break;
1923 case I915_TILING_Y:
80075d49 1924 WARN(1, "Y tiled bo slipped through, driver bug!\n");
6b95a207
KH		 1925 return -EINVAL;
1926 default:
1927 BUG();
1928 }
1929
693db184
CW		 1930 /* Note that the w/a also requires 64 PTE of padding following the
1931 * bo. We currently fill all unused PTE with the shadow page and so
1932 * we should always have valid PTE following the scanout preventing
1933 * the VT-d warning.
1934 */
1935 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1936 alignment = 256 * 1024;
1937
ce453d81 1938 dev_priv->mm.interruptible = false;
2da3b9b9 1939 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1940 if (ret)
ce453d81 1941 goto err_interruptible;
6b95a207
KH		 1942
1943 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1944 * fence, whereas 965+ only requires a fence if using
1945 * framebuffer compression. For simplicity, we always install
1946 * a fence as the cost is not that onerous.
1947 */
06d98131 1948 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1949 if (ret)
1950 goto err_unpin;
1690e1eb 1951
9a5a53b3 1952 i915_gem_object_pin_fence(obj);
6b95a207 1953
ce453d81 1954 dev_priv->mm.interruptible = true;
6b95a207 1955 return 0;
48b956c5
CW		 1956
1957err_unpin:
cc98b413 1958 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1959err_interruptible:
1960 dev_priv->mm.interruptible = true;
48b956c5 1961 return ret;
6b95a207
KH		 1962}
1963
1690e1eb
CW		 1964void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1965{
1966 i915_gem_object_unpin_fence(obj);
cc98b413 1967 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1968}
1969
c2c75131
DV		 1970/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1971 * is assumed to be a power-of-two. */
bc752862
CW		 1972unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1973 unsigned int tiling_mode,
1974 unsigned int cpp,
1975 unsigned int pitch)
c2c75131 1976{
bc752862
CW		 1977 if (tiling_mode != I915_TILING_NONE) {
1978 unsigned int tile_rows, tiles;
c2c75131 1979
bc752862
CW		 1980 tile_rows = *y / 8;
1981 *y %= 8;
c2c75131 1982
bc752862
CW		 1983 tiles = *x / (512/cpp);
1984 *x %= 512/cpp;
1985
1986 return tile_rows * pitch * 8 + tiles * 4096;
1987 } else {
1988 unsigned int offset;
1989
1990 offset = *y * pitch + *x * cpp;
1991 *y = 0;
1992 *x = (offset & 4095) / cpp;
1993 return offset & -4096;
1994 }
c2c75131
DV		 1995}
1996
17638cd6
JB		 1997static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1998 int x, int y)
81255565
JB		 1999{
2000 struct drm_device *dev = crtc->dev;
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2003 struct intel_framebuffer *intel_fb;
05394f39 2004 struct drm_i915_gem_object *obj;
81255565 2005 int plane = intel_crtc->plane;
e506a0c6 2006 unsigned long linear_offset;
81255565 2007 u32 dspcntr;
5eddb70b 2008 u32 reg;
81255565
JB		 2009
2010 switch (plane) {
2011 case 0:
2012 case 1:
2013 break;
2014 default:
84f44ce7 2015 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2016 return -EINVAL;
2017 }
2018
2019 intel_fb = to_intel_framebuffer(fb);
2020 obj = intel_fb->obj;
81255565 2021
5eddb70b
CW		 2022 reg = DSPCNTR(plane);
2023 dspcntr = I915_READ(reg);
81255565
JB		 2024 /* Mask out pixel format bits in case we change it */
2025 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2026 switch (fb->pixel_format) {
2027 case DRM_FORMAT_C8:
81255565
JB		 2028 dspcntr |= DISPPLANE_8BPP;
2029 break;
57779d06
VS		 2030 case DRM_FORMAT_XRGB1555:
2031 case DRM_FORMAT_ARGB1555:
2032 dspcntr |= DISPPLANE_BGRX555;
81255565 2033 break;
57779d06
VS		 2034 case DRM_FORMAT_RGB565:
2035 dspcntr |= DISPPLANE_BGRX565;
2036 break;
2037 case DRM_FORMAT_XRGB8888:
2038 case DRM_FORMAT_ARGB8888:
2039 dspcntr |= DISPPLANE_BGRX888;
2040 break;
2041 case DRM_FORMAT_XBGR8888:
2042 case DRM_FORMAT_ABGR8888:
2043 dspcntr |= DISPPLANE_RGBX888;
2044 break;
2045 case DRM_FORMAT_XRGB2101010:
2046 case DRM_FORMAT_ARGB2101010:
2047 dspcntr |= DISPPLANE_BGRX101010;
2048 break;
2049 case DRM_FORMAT_XBGR2101010:
2050 case DRM_FORMAT_ABGR2101010:
2051 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2052 break;
2053 default:
baba133a 2054 BUG();
81255565 2055 }
57779d06 2056
a6c45cf0 2057 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2058 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2059 dspcntr |= DISPPLANE_TILED;
2060 else
2061 dspcntr &= ~DISPPLANE_TILED;
2062 }
2063
de1aa629
VS		 2064 if (IS_G4X(dev))
2065 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2066
5eddb70b 2067 I915_WRITE(reg, dspcntr);
81255565 2068
e506a0c6 2069 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2070
c2c75131
DV		 2071 if (INTEL_INFO(dev)->gen >= 4) {
2072 intel_crtc->dspaddr_offset =
bc752862
CW		 2073 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2074 fb->bits_per_pixel / 8,
2075 fb->pitches[0]);
c2c75131
DV		 2076 linear_offset -= intel_crtc->dspaddr_offset;
2077 } else {
e506a0c6 2078 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2079 }
e506a0c6 2080
f343c5f6
BW		 2081 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2082 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2083 fb->pitches[0]);
01f2c773 2084 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2085 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2086 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2087 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2088 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2089 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2090 } else
f343c5f6 2091 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2092 POSTING_READ(reg);
81255565 2093
17638cd6
JB		 2094 return 0;
2095}
2096
2097static int ironlake_update_plane(struct drm_crtc *crtc,
2098 struct drm_framebuffer *fb, int x, int y)
2099{
2100 struct drm_device *dev = crtc->dev;
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103 struct intel_framebuffer *intel_fb;
2104 struct drm_i915_gem_object *obj;
2105 int plane = intel_crtc->plane;
e506a0c6 2106 unsigned long linear_offset;
17638cd6
JB		 2107 u32 dspcntr;
2108 u32 reg;
2109
2110 switch (plane) {
2111 case 0:
2112 case 1:
27f8227b 2113 case 2:
17638cd6
JB		 2114 break;
2115 default:
84f44ce7 2116 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2117 return -EINVAL;
2118 }
2119
2120 intel_fb = to_intel_framebuffer(fb);
2121 obj = intel_fb->obj;
2122
2123 reg = DSPCNTR(plane);
2124 dspcntr = I915_READ(reg);
2125 /* Mask out pixel format bits in case we change it */
2126 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2127 switch (fb->pixel_format) {
2128 case DRM_FORMAT_C8:
17638cd6
JB		 2129 dspcntr |= DISPPLANE_8BPP;
2130 break;
57779d06
VS		 2131 case DRM_FORMAT_RGB565:
2132 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2133 break;
57779d06
VS		 2134 case DRM_FORMAT_XRGB8888:
2135 case DRM_FORMAT_ARGB8888:
2136 dspcntr |= DISPPLANE_BGRX888;
2137 break;
2138 case DRM_FORMAT_XBGR8888:
2139 case DRM_FORMAT_ABGR8888:
2140 dspcntr |= DISPPLANE_RGBX888;
2141 break;
2142 case DRM_FORMAT_XRGB2101010:
2143 case DRM_FORMAT_ARGB2101010:
2144 dspcntr |= DISPPLANE_BGRX101010;
2145 break;
2146 case DRM_FORMAT_XBGR2101010:
2147 case DRM_FORMAT_ABGR2101010:
2148 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2149 break;
2150 default:
baba133a 2151 BUG();
17638cd6
JB		 2152 }
2153
2154 if (obj->tiling_mode != I915_TILING_NONE)
2155 dspcntr |= DISPPLANE_TILED;
2156 else
2157 dspcntr &= ~DISPPLANE_TILED;
2158
1f5d76db
PZ		 2159 if (IS_HASWELL(dev))
2160 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2161 else
2162 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2163
2164 I915_WRITE(reg, dspcntr);
2165
e506a0c6 2166 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2167 intel_crtc->dspaddr_offset =
bc752862
CW		 2168 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2169 fb->bits_per_pixel / 8,
2170 fb->pitches[0]);
c2c75131 2171 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2172
f343c5f6
BW		 2173 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2174 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2175 fb->pitches[0]);
01f2c773 2176 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2177 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2178 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2179 if (IS_HASWELL(dev)) {
2180 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2181 } else {
2182 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2183 I915_WRITE(DSPLINOFF(plane), linear_offset);
2184 }
17638cd6
JB		 2185 POSTING_READ(reg);
2186
2187 return 0;
2188}
2189
2190/* Assume fb object is pinned & idle & fenced and just update base pointers */
2191static int
2192intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2193 int x, int y, enum mode_set_atomic state)
2194{
2195 struct drm_device *dev = crtc->dev;
2196 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2197
6b8e6ed0
CW		 2198 if (dev_priv->display.disable_fbc)
2199 dev_priv->display.disable_fbc(dev);
3dec0095 2200 intel_increase_pllclock(crtc);
81255565 2201
6b8e6ed0 2202 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2203}
2204
96a02917
VS		 2205void intel_display_handle_reset(struct drm_device *dev)
2206{
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_crtc *crtc;
2209
2210 /*
2211 * Flips in the rings have been nuked by the reset,
2212 * so complete all pending flips so that user space
2213 * will get its events and not get stuck.
2214 *
2215 * Also update the base address of all primary
2216 * planes to the the last fb to make sure we're
2217 * showing the correct fb after a reset.
2218 *
2219 * Need to make two loops over the crtcs so that we
2220 * don't try to grab a crtc mutex before the
2221 * pending_flip_queue really got woken up.
2222 */
2223
2224 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226 enum plane plane = intel_crtc->plane;
2227
2228 intel_prepare_page_flip(dev, plane);
2229 intel_finish_page_flip_plane(dev, plane);
2230 }
2231
2232 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 mutex_lock(&crtc->mutex);
2236 if (intel_crtc->active)
2237 dev_priv->display.update_plane(crtc, crtc->fb,
2238 crtc->x, crtc->y);
2239 mutex_unlock(&crtc->mutex);
2240 }
2241}
2242
14667a4b
CW		 2243static int
2244intel_finish_fb(struct drm_framebuffer *old_fb)
2245{
2246 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2247 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2248 bool was_interruptible = dev_priv->mm.interruptible;
2249 int ret;
2250
14667a4b
CW		 2251 /* Big Hammer, we also need to ensure that any pending
2252 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2253 * current scanout is retired before unpinning the old
2254 * framebuffer.
2255 *
2256 * This should only fail upon a hung GPU, in which case we
2257 * can safely continue.
2258 */
2259 dev_priv->mm.interruptible = false;
2260 ret = i915_gem_object_finish_gpu(obj);
2261 dev_priv->mm.interruptible = was_interruptible;
2262
2263 return ret;
2264}
2265
198598d0
VS		 2266static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2267{
2268 struct drm_device *dev = crtc->dev;
2269 struct drm_i915_master_private *master_priv;
2270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271
2272 if (!dev->primary->master)
2273 return;
2274
2275 master_priv = dev->primary->master->driver_priv;
2276 if (!master_priv->sarea_priv)
2277 return;
2278
2279 switch (intel_crtc->pipe) {
2280 case 0:
2281 master_priv->sarea_priv->pipeA_x = x;
2282 master_priv->sarea_priv->pipeA_y = y;
2283 break;
2284 case 1:
2285 master_priv->sarea_priv->pipeB_x = x;
2286 master_priv->sarea_priv->pipeB_y = y;
2287 break;
2288 default:
2289 break;
2290 }
2291}
2292
5c3b82e2 2293static int
3c4fdcfb 2294intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2295 struct drm_framebuffer *fb)
79e53945
JB		 2296{
2297 struct drm_device *dev = crtc->dev;
6b8e6ed0 2298 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2300 struct drm_framebuffer *old_fb;
5c3b82e2 2301 int ret;
79e53945
JB		 2302
2303 /* no fb bound */
94352cf9 2304 if (!fb) {
a5071c2f 2305 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2306 return 0;
2307 }
2308
7eb552ae 2309 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2310 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2311 plane_name(intel_crtc->plane),
2312 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2313 return -EINVAL;
79e53945
JB		 2314 }
2315
5c3b82e2 2316 mutex_lock(&dev->struct_mutex);
265db958 2317 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2318 to_intel_framebuffer(fb)->obj,
919926ae 2319 NULL);
5c3b82e2
CW		 2320 if (ret != 0) {
2321 mutex_unlock(&dev->struct_mutex);
a5071c2f 2322 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2323 return ret;
2324 }
79e53945 2325
bb2043de
DL		 2326 /*
2327 * Update pipe size and adjust fitter if needed: the reason for this is
2328 * that in compute_mode_changes we check the native mode (not the pfit
2329 * mode) to see if we can flip rather than do a full mode set. In the
2330 * fastboot case, we'll flip, but if we don't update the pipesrc and
2331 * pfit state, we'll end up with a big fb scanned out into the wrong
2332 * sized surface.
2333 *
2334 * To fix this properly, we need to hoist the checks up into
2335 * compute_mode_changes (or above), check the actual pfit state and
2336 * whether the platform allows pfit disable with pipe active, and only
2337 * then update the pipesrc and pfit state, even on the flip path.
2338 */
4d6a3e63 2339 if (i915_fastboot) {
d7bf63f2
DL		 2340 const struct drm_display_mode *adjusted_mode =
2341 &intel_crtc->config.adjusted_mode;
2342
4d6a3e63 2343 I915_WRITE(PIPESRC(intel_crtc->pipe),
d7bf63f2
DL		 2344 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2345 (adjusted_mode->crtc_vdisplay - 1));
fd4daa9c 2346 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2347 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2348 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2349 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2350 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2351 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2352 }
2353 }
2354
94352cf9 2355 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2356 if (ret) {
94352cf9 2357 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2358 mutex_unlock(&dev->struct_mutex);
a5071c2f 2359 DRM_ERROR("failed to update base address\n");
4e6cfefc 2360 return ret;
79e53945 2361 }
3c4fdcfb 2362
94352cf9
DV		 2363 old_fb = crtc->fb;
2364 crtc->fb = fb;
6c4c86f5
DV		 2365 crtc->x = x;
2366 crtc->y = y;
94352cf9 2367
b7f1de28 2368 if (old_fb) {
d7697eea
DV		 2369 if (intel_crtc->active && old_fb != fb)
2370 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2371 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2372 }
652c393a 2373
6b8e6ed0 2374 intel_update_fbc(dev);
4906557e 2375 intel_edp_psr_update(dev);
5c3b82e2 2376 mutex_unlock(&dev->struct_mutex);
79e53945 2377
198598d0 2378 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2379
2380 return 0;
79e53945
JB		 2381}
2382
5e84e1a4
ZW		 2383static void intel_fdi_normal_train(struct drm_crtc *crtc)
2384{
2385 struct drm_device *dev = crtc->dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388 int pipe = intel_crtc->pipe;
2389 u32 reg, temp;
2390
2391 /* enable normal train */
2392 reg = FDI_TX_CTL(pipe);
2393 temp = I915_READ(reg);
61e499bf 2394 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2395 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2396 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2397 } else {
2398 temp &= ~FDI_LINK_TRAIN_NONE;
2399 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2400 }
5e84e1a4
ZW		 2401 I915_WRITE(reg, temp);
2402
2403 reg = FDI_RX_CTL(pipe);
2404 temp = I915_READ(reg);
2405 if (HAS_PCH_CPT(dev)) {
2406 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2407 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2408 } else {
2409 temp &= ~FDI_LINK_TRAIN_NONE;
2410 temp |= FDI_LINK_TRAIN_NONE;
2411 }
2412 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2413
2414 /* wait one idle pattern time */
2415 POSTING_READ(reg);
2416 udelay(1000);
357555c0
JB		 2417
2418 /* IVB wants error correction enabled */
2419 if (IS_IVYBRIDGE(dev))
2420 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2421 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2422}
2423
1fbc0d78 2424static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
1e833f40 2425{
1fbc0d78
DV		 2426 return crtc->base.enabled && crtc->active &&
2427 crtc->config.has_pch_encoder;
1e833f40
DV		 2428}
2429
01a415fd
DV		 2430static void ivb_modeset_global_resources(struct drm_device *dev)
2431{
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct intel_crtc *pipe_B_crtc =
2434 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2435 struct intel_crtc *pipe_C_crtc =
2436 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2437 uint32_t temp;
2438
1e833f40
DV		 2439 /*
2440 * When everything is off disable fdi C so that we could enable fdi B
2441 * with all lanes. Note that we don't care about enabled pipes without
2442 * an enabled pch encoder.
2443 */
2444 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2445 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2446 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2447 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2448
2449 temp = I915_READ(SOUTH_CHICKEN1);
2450 temp &= ~FDI_BC_BIFURCATION_SELECT;
2451 DRM_DEBUG_KMS("disabling fdi C rx\n");
2452 I915_WRITE(SOUTH_CHICKEN1, temp);
2453 }
2454}
2455
8db9d77b
ZW		 2456/* The FDI link training functions for ILK/Ibexpeak. */
2457static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2458{
2459 struct drm_device *dev = crtc->dev;
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2462 int pipe = intel_crtc->pipe;
0fc932b8 2463 int plane = intel_crtc->plane;
5eddb70b 2464 u32 reg, temp, tries;
8db9d77b 2465
0fc932b8
JB		 2466 /* FDI needs bits from pipe & plane first */
2467 assert_pipe_enabled(dev_priv, pipe);
2468 assert_plane_enabled(dev_priv, plane);
2469
e1a44743
AJ		 2470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2471 for train result */
5eddb70b
CW		 2472 reg = FDI_RX_IMR(pipe);
2473 temp = I915_READ(reg);
e1a44743
AJ		 2474 temp &= ~FDI_RX_SYMBOL_LOCK;
2475 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2476 I915_WRITE(reg, temp);
2477 I915_READ(reg);
e1a44743
AJ		 2478 udelay(150);
2479
8db9d77b 2480 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2481 reg = FDI_TX_CTL(pipe);
2482 temp = I915_READ(reg);
627eb5a3
DV		 2483 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2484 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2485 temp &= ~FDI_LINK_TRAIN_NONE;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2487 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2488
5eddb70b
CW		 2489 reg = FDI_RX_CTL(pipe);
2490 temp = I915_READ(reg);
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2493 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2494
2495 POSTING_READ(reg);
8db9d77b
ZW		 2496 udelay(150);
2497
5b2adf89 2498 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2499 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2500 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2501 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2502
5eddb70b 2503 reg = FDI_RX_IIR(pipe);
e1a44743 2504 for (tries = 0; tries < 5; tries++) {
5eddb70b 2505 temp = I915_READ(reg);
8db9d77b
ZW		 2506 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2507
2508 if ((temp & FDI_RX_BIT_LOCK)) {
2509 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2510 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2511 break;
2512 }
8db9d77b 2513 }
e1a44743 2514 if (tries == 5)
5eddb70b 2515 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2516
2517 /* Train 2 */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
8db9d77b
ZW		 2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2522 I915_WRITE(reg, temp);
8db9d77b 2523
5eddb70b
CW		 2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2528 I915_WRITE(reg, temp);
8db9d77b 2529
5eddb70b
CW		 2530 POSTING_READ(reg);
2531 udelay(150);
8db9d77b 2532
5eddb70b 2533 reg = FDI_RX_IIR(pipe);
e1a44743 2534 for (tries = 0; tries < 5; tries++) {
5eddb70b 2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2539 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2540 DRM_DEBUG_KMS("FDI train 2 done.\n");
2541 break;
2542 }
8db9d77b 2543 }
e1a44743 2544 if (tries == 5)
5eddb70b 2545 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2546
2547 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2548
8db9d77b
ZW		 2549}
2550
0206e353 2551static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2552 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2553 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2554 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2555 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2556};
2557
2558/* The FDI link training functions for SNB/Cougarpoint. */
2559static void gen6_fdi_link_train(struct drm_crtc *crtc)
2560{
2561 struct drm_device *dev = crtc->dev;
2562 struct drm_i915_private *dev_priv = dev->dev_private;
2563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2564 int pipe = intel_crtc->pipe;
fa37d39e 2565 u32 reg, temp, i, retry;
8db9d77b 2566
e1a44743
AJ		 2567 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2568 for train result */
5eddb70b
CW		 2569 reg = FDI_RX_IMR(pipe);
2570 temp = I915_READ(reg);
e1a44743
AJ		 2571 temp &= ~FDI_RX_SYMBOL_LOCK;
2572 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
e1a44743
AJ		 2576 udelay(150);
2577
8db9d77b 2578 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2579 reg = FDI_TX_CTL(pipe);
2580 temp = I915_READ(reg);
627eb5a3
DV		 2581 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2582 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_1;
2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586 /* SNB-B */
2587 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2588 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2589
d74cf324
DV		 2590 I915_WRITE(FDI_RX_MISC(pipe),
2591 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_1;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_BIT_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2623 DRM_DEBUG_KMS("FDI train 1 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2633
2634 /* Train 2 */
5eddb70b
CW		 2635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
8db9d77b
ZW		 2637 temp &= ~FDI_LINK_TRAIN_NONE;
2638 temp |= FDI_LINK_TRAIN_PATTERN_2;
2639 if (IS_GEN6(dev)) {
2640 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641 /* SNB-B */
2642 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2643 }
5eddb70b 2644 I915_WRITE(reg, temp);
8db9d77b 2645
5eddb70b
CW		 2646 reg = FDI_RX_CTL(pipe);
2647 temp = I915_READ(reg);
8db9d77b
ZW		 2648 if (HAS_PCH_CPT(dev)) {
2649 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2651 } else {
2652 temp &= ~FDI_LINK_TRAIN_NONE;
2653 temp |= FDI_LINK_TRAIN_PATTERN_2;
2654 }
5eddb70b
CW		 2655 I915_WRITE(reg, temp);
2656
2657 POSTING_READ(reg);
8db9d77b
ZW		 2658 udelay(150);
2659
0206e353 2660 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
8db9d77b
ZW		 2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2665 I915_WRITE(reg, temp);
2666
2667 POSTING_READ(reg);
8db9d77b
ZW		 2668 udelay(500);
2669
fa37d39e
SP		 2670 for (retry = 0; retry < 5; retry++) {
2671 reg = FDI_RX_IIR(pipe);
2672 temp = I915_READ(reg);
2673 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2674 if (temp & FDI_RX_SYMBOL_LOCK) {
2675 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2676 DRM_DEBUG_KMS("FDI train 2 done.\n");
2677 break;
2678 }
2679 udelay(50);
8db9d77b 2680 }
fa37d39e
SP		 2681 if (retry < 5)
2682 break;
8db9d77b
ZW		 2683 }
2684 if (i == 4)
5eddb70b 2685 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2686
2687 DRM_DEBUG_KMS("FDI train done.\n");
2688}
2689
357555c0
JB		 2690/* Manual link training for Ivy Bridge A0 parts */
2691static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2692{
2693 struct drm_device *dev = crtc->dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2696 int pipe = intel_crtc->pipe;
139ccd3f 2697 u32 reg, temp, i, j;
357555c0
JB		 2698
2699 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2700 for train result */
2701 reg = FDI_RX_IMR(pipe);
2702 temp = I915_READ(reg);
2703 temp &= ~FDI_RX_SYMBOL_LOCK;
2704 temp &= ~FDI_RX_BIT_LOCK;
2705 I915_WRITE(reg, temp);
2706
2707 POSTING_READ(reg);
2708 udelay(150);
2709
01a415fd
DV		 2710 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2711 I915_READ(FDI_RX_IIR(pipe)));
2712
139ccd3f
JB		 2713 /* Try each vswing and preemphasis setting twice before moving on */
2714 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2715 /* disable first in case we need to retry */
2716 reg = FDI_TX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2719 temp &= ~FDI_TX_ENABLE;
2720 I915_WRITE(reg, temp);
357555c0 2721
139ccd3f
JB		 2722 reg = FDI_RX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~FDI_LINK_TRAIN_AUTO;
2725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726 temp &= ~FDI_RX_ENABLE;
2727 I915_WRITE(reg, temp);
357555c0 2728
139ccd3f 2729 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2730 reg = FDI_TX_CTL(pipe);
2731 temp = I915_READ(reg);
139ccd3f
JB		 2732 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2733 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2734 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2736 temp |= snb_b_fdi_train_param[j/2];
2737 temp |= FDI_COMPOSITE_SYNC;
2738 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2739
139ccd3f
JB		 2740 I915_WRITE(FDI_RX_MISC(pipe),
2741 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2742
139ccd3f 2743 reg = FDI_RX_CTL(pipe);
357555c0 2744 temp = I915_READ(reg);
139ccd3f
JB		 2745 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2746 temp |= FDI_COMPOSITE_SYNC;
2747 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2748
139ccd3f
JB		 2749 POSTING_READ(reg);
2750 udelay(1); /* should be 0.5us */
357555c0 2751
139ccd3f
JB		 2752 for (i = 0; i < 4; i++) {
2753 reg = FDI_RX_IIR(pipe);
2754 temp = I915_READ(reg);
2755 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2756
139ccd3f
JB		 2757 if (temp & FDI_RX_BIT_LOCK ||
2758 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2759 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2760 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2761 i);
2762 break;
2763 }
2764 udelay(1); /* should be 0.5us */
2765 }
2766 if (i == 4) {
2767 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2768 continue;
2769 }
357555c0 2770
139ccd3f 2771 /* Train 2 */
357555c0
JB		 2772 reg = FDI_TX_CTL(pipe);
2773 temp = I915_READ(reg);
139ccd3f
JB		 2774 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2775 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2776 I915_WRITE(reg, temp);
2777
2778 reg = FDI_RX_CTL(pipe);
2779 temp = I915_READ(reg);
2780 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2781 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2782 I915_WRITE(reg, temp);
2783
2784 POSTING_READ(reg);
139ccd3f 2785 udelay(2); /* should be 1.5us */
357555c0 2786
139ccd3f
JB		 2787 for (i = 0; i < 4; i++) {
2788 reg = FDI_RX_IIR(pipe);
2789 temp = I915_READ(reg);
2790 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2791
139ccd3f
JB		 2792 if (temp & FDI_RX_SYMBOL_LOCK ||
2793 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2794 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2796 i);
2797 goto train_done;
2798 }
2799 udelay(2); /* should be 1.5us */
357555c0 2800 }
139ccd3f
JB		 2801 if (i == 4)
2802 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2803 }
357555c0 2804
139ccd3f 2805train_done:
357555c0
JB		 2806 DRM_DEBUG_KMS("FDI train done.\n");
2807}
2808
88cefb6c 2809static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2810{
88cefb6c 2811 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2812 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2813 int pipe = intel_crtc->pipe;
5eddb70b 2814 u32 reg, temp;
79e53945 2815
c64e311e 2816
c98e9dcf 2817 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2818 reg = FDI_RX_CTL(pipe);
2819 temp = I915_READ(reg);
627eb5a3
DV		 2820 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2821 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2823 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2824
2825 POSTING_READ(reg);
c98e9dcf
JB		 2826 udelay(200);
2827
2828 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2829 temp = I915_READ(reg);
2830 I915_WRITE(reg, temp | FDI_PCDCLK);
2831
2832 POSTING_READ(reg);
c98e9dcf
JB		 2833 udelay(200);
2834
20749730
PZ		 2835 /* Enable CPU FDI TX PLL, always on for Ironlake */
2836 reg = FDI_TX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2839 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2840
20749730
PZ		 2841 POSTING_READ(reg);
2842 udelay(100);
6be4a607 2843 }
0e23b99d
JB		 2844}
2845
88cefb6c
DV		 2846static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847{
2848 struct drm_device *dev = intel_crtc->base.dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 int pipe = intel_crtc->pipe;
2851 u32 reg, temp;
2852
2853 /* Switch from PCDclk to Rawclk */
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858 /* Disable CPU FDI TX PLL */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870 /* Wait for the clocks to turn off. */
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
0fc932b8
JB		 2875static void ironlake_fdi_disable(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 int pipe = intel_crtc->pipe;
2881 u32 reg, temp;
2882
2883 /* disable CPU FDI tx and PCH FDI rx */
2884 reg = FDI_TX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2887 POSTING_READ(reg);
2888
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 temp &= ~(0x7 << 16);
dfd07d72 2892 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2893 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2894
2895 POSTING_READ(reg);
2896 udelay(100);
2897
2898 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2899 if (HAS_PCH_IBX(dev)) {
2900 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2901 }
0fc932b8
JB		 2902
2903 /* still set train pattern 1 */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908 I915_WRITE(reg, temp);
2909
2910 reg = FDI_RX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 if (HAS_PCH_CPT(dev)) {
2913 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2914 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2915 } else {
2916 temp &= ~FDI_LINK_TRAIN_NONE;
2917 temp |= FDI_LINK_TRAIN_PATTERN_1;
2918 }
2919 /* BPC in FDI rx is consistent with that in PIPECONF */
2920 temp &= ~(0x07 << 16);
dfd07d72 2921 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2922 I915_WRITE(reg, temp);
2923
2924 POSTING_READ(reg);
2925 udelay(100);
2926}
2927
5bb61643
CW		 2928static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2929{
2930 struct drm_device *dev = crtc->dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2933 unsigned long flags;
2934 bool pending;
2935
10d83730
VS		 2936 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2937 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2938 return false;
2939
2940 spin_lock_irqsave(&dev->event_lock, flags);
2941 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2942 spin_unlock_irqrestore(&dev->event_lock, flags);
2943
2944 return pending;
2945}
2946
e6c3a2a6
CW		 2947static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2948{
0f91128d 2949 struct drm_device *dev = crtc->dev;
5bb61643 2950 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2951
2952 if (crtc->fb == NULL)
2953 return;
2954
2c10d571
DV		 2955 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2956
5bb61643
CW		 2957 wait_event(dev_priv->pending_flip_queue,
2958 !intel_crtc_has_pending_flip(crtc));
2959
0f91128d
CW		 2960 mutex_lock(&dev->struct_mutex);
2961 intel_finish_fb(crtc->fb);
2962 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2963}
2964
e615efe4
ED		 2965/* Program iCLKIP clock to the desired frequency */
2966static void lpt_program_iclkip(struct drm_crtc *crtc)
2967{
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2970 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2971 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2972 u32 temp;
2973
09153000
DV		 2974 mutex_lock(&dev_priv->dpio_lock);
2975
e615efe4
ED		 2976 /* It is necessary to ungate the pixclk gate prior to programming
2977 * the divisors, and gate it back when it is done.
2978 */
2979 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2980
2981 /* Disable SSCCTL */
2982 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2983 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2984 SBI_SSCCTL_DISABLE,
2985 SBI_ICLK);
e615efe4
ED		 2986
2987 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2988 if (clock == 20000) {
e615efe4
ED		 2989 auxdiv = 1;
2990 divsel = 0x41;
2991 phaseinc = 0x20;
2992 } else {
2993 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2994 * but the adjusted_mode->crtc_clock in in KHz. To get the
2995 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2996 * convert the virtual clock precision to KHz here for higher
2997 * precision.
2998 */
2999 u32 iclk_virtual_root_freq = 172800 * 1000;
3000 u32 iclk_pi_range = 64;
3001 u32 desired_divisor, msb_divisor_value, pi_value;
3002
12d7ceed 3003 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3004 msb_divisor_value = desired_divisor / iclk_pi_range;
3005 pi_value = desired_divisor % iclk_pi_range;
3006
3007 auxdiv = 0;
3008 divsel = msb_divisor_value - 2;
3009 phaseinc = pi_value;
3010 }
3011
3012 /* This should not happen with any sane values */
3013 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3014 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3015 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3016 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3017
3018 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3019 clock,
e615efe4
ED		 3020 auxdiv,
3021 divsel,
3022 phasedir,
3023 phaseinc);
3024
3025 /* Program SSCDIVINTPHASE6 */
988d6ee8 3026 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3027 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3028 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3029 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3030 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3031 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3032 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3033 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3034
3035 /* Program SSCAUXDIV */
988d6ee8 3036 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3037 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3038 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3039 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3040
3041 /* Enable modulator and associated divider */
988d6ee8 3042 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3043 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3044 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3045
3046 /* Wait for initialization time */
3047 udelay(24);
3048
3049 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3050
3051 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3052}
3053
275f01b2
DV		 3054static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3055 enum pipe pch_transcoder)
3056{
3057 struct drm_device *dev = crtc->base.dev;
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3060
3061 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3062 I915_READ(HTOTAL(cpu_transcoder)));
3063 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3064 I915_READ(HBLANK(cpu_transcoder)));
3065 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3066 I915_READ(HSYNC(cpu_transcoder)));
3067
3068 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3069 I915_READ(VTOTAL(cpu_transcoder)));
3070 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3071 I915_READ(VBLANK(cpu_transcoder)));
3072 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3073 I915_READ(VSYNC(cpu_transcoder)));
3074 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3075 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3076}
3077
1fbc0d78
DV		 3078static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3079{
3080 struct drm_i915_private *dev_priv = dev->dev_private;
3081 uint32_t temp;
3082
3083 temp = I915_READ(SOUTH_CHICKEN1);
3084 if (temp & FDI_BC_BIFURCATION_SELECT)
3085 return;
3086
3087 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3088 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3089
3090 temp |= FDI_BC_BIFURCATION_SELECT;
3091 DRM_DEBUG_KMS("enabling fdi C rx\n");
3092 I915_WRITE(SOUTH_CHICKEN1, temp);
3093 POSTING_READ(SOUTH_CHICKEN1);
3094}
3095
3096static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3097{
3098 struct drm_device *dev = intel_crtc->base.dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100
3101 switch (intel_crtc->pipe) {
3102 case PIPE_A:
3103 break;
3104 case PIPE_B:
3105 if (intel_crtc->config.fdi_lanes > 2)
3106 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3107 else
3108 cpt_enable_fdi_bc_bifurcation(dev);
3109
3110 break;
3111 case PIPE_C:
3112 cpt_enable_fdi_bc_bifurcation(dev);
3113
3114 break;
3115 default:
3116 BUG();
3117 }
3118}
3119
f67a559d
JB		 3120/*
3121 * Enable PCH resources required for PCH ports:
3122 * - PCH PLLs
3123 * - FDI training & RX/TX
3124 * - update transcoder timings
3125 * - DP transcoding bits
3126 * - transcoder
3127 */
3128static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3129{
3130 struct drm_device *dev = crtc->dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133 int pipe = intel_crtc->pipe;
ee7b9f93 3134 u32 reg, temp;
2c07245f 3135
ab9412ba 3136 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3137
1fbc0d78
DV		 3138 if (IS_IVYBRIDGE(dev))
3139 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3140
cd986abb
DV		 3141 /* Write the TU size bits before fdi link training, so that error
3142 * detection works. */
3143 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3144 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3145
c98e9dcf 3146 /* For PCH output, training FDI link */
674cf967 3147 dev_priv->display.fdi_link_train(crtc);
2c07245f 3148
3ad8a208
DV		 3149 /* We need to program the right clock selection before writing the pixel
3150 * mutliplier into the DPLL. */
303b81e0 3151 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3152 u32 sel;
4b645f14 3153
c98e9dcf 3154 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3155 temp |= TRANS_DPLL_ENABLE(pipe);
3156 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3157 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3158 temp |= sel;
3159 else
3160 temp &= ~sel;
c98e9dcf 3161 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3162 }
5eddb70b 3163
3ad8a208
DV		 3164 /* XXX: pch pll's can be enabled any time before we enable the PCH
3165 * transcoder, and we actually should do this to not upset any PCH
3166 * transcoder that already use the clock when we share it.
3167 *
3168 * Note that enable_shared_dpll tries to do the right thing, but
3169 * get_shared_dpll unconditionally resets the pll - we need that to have
3170 * the right LVDS enable sequence. */
3171 ironlake_enable_shared_dpll(intel_crtc);
3172
d9b6cb56
JB		 3173 /* set transcoder timing, panel must allow it */
3174 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3175 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3176
303b81e0 3177 intel_fdi_normal_train(crtc);
5e84e1a4 3178
c98e9dcf
JB		 3179 /* For PCH DP, enable TRANS_DP_CTL */
3180 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3181 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3182 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3183 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3184 reg = TRANS_DP_CTL(pipe);
3185 temp = I915_READ(reg);
3186 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3187 TRANS_DP_SYNC_MASK |
3188 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3189 temp |= (TRANS_DP_OUTPUT_ENABLE |
3190 TRANS_DP_ENH_FRAMING);
9325c9f0 3191 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3192
3193 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3194 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3195 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3196 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3197
3198 switch (intel_trans_dp_port_sel(crtc)) {
3199 case PCH_DP_B:
5eddb70b 3200 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3201 break;
3202 case PCH_DP_C:
5eddb70b 3203 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3204 break;
3205 case PCH_DP_D:
5eddb70b 3206 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3207 break;
3208 default:
e95d41e1 3209 BUG();
32f9d658 3210 }
2c07245f 3211
5eddb70b 3212 I915_WRITE(reg, temp);
6be4a607 3213 }
b52eb4dc 3214
b8a4f404 3215 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3216}
3217
1507e5bd
PZ		 3218static void lpt_pch_enable(struct drm_crtc *crtc)
3219{
3220 struct drm_device *dev = crtc->dev;
3221 struct drm_i915_private *dev_priv = dev->dev_private;
3222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3223 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3224
ab9412ba 3225 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3226
8c52b5e8 3227 lpt_program_iclkip(crtc);
1507e5bd 3228
0540e488 3229 /* Set transcoder timing. */
275f01b2 3230 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3231
937bb610 3232 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3233}
3234
e2b78267 3235static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3236{
e2b78267 3237 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3238
3239 if (pll == NULL)
3240 return;
3241
3242 if (pll->refcount == 0) {
46edb027 3243 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3244 return;
3245 }
3246
f4a091c7
DV		 3247 if (--pll->refcount == 0) {
3248 WARN_ON(pll->on);
3249 WARN_ON(pll->active);
3250 }
3251
a43f6e0f 3252 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3253}
3254
b89a1d39 3255static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3256{
e2b78267
DV		 3257 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3258 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3259 enum intel_dpll_id i;
ee7b9f93 3260
ee7b9f93 3261 if (pll) {
46edb027
DV		 3262 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3263 crtc->base.base.id, pll->name);
e2b78267 3264 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3265 }
3266
98b6bd99
DV		 3267 if (HAS_PCH_IBX(dev_priv->dev)) {
3268 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3269 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3270 pll = &dev_priv->shared_dplls[i];
98b6bd99 3271
46edb027
DV		 3272 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3273 crtc->base.base.id, pll->name);
98b6bd99
DV		 3274
3275 goto found;
3276 }
3277
e72f9fbf
DV		 3278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3279 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3280
3281 /* Only want to check enabled timings first */
3282 if (pll->refcount == 0)
3283 continue;
3284
b89a1d39
DV		 3285 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3286 sizeof(pll->hw_state)) == 0) {
46edb027 3287 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3288 crtc->base.base.id,
46edb027 3289 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3290
3291 goto found;
3292 }
3293 }
3294
3295 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3296 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3297 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3298 if (pll->refcount == 0) {
46edb027
DV		 3299 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3300 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3301 goto found;
3302 }
3303 }
3304
3305 return NULL;
3306
3307found:
a43f6e0f 3308 crtc->config.shared_dpll = i;
46edb027
DV		 3309 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3310 pipe_name(crtc->pipe));
ee7b9f93 3311
cdbd2316 3312 if (pll->active == 0) {
66e985c0
DV		 3313 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3314 sizeof(pll->hw_state));
3315
46edb027 3316 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3317 WARN_ON(pll->on);
e9d6944e 3318 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3319
15bdd4cf 3320 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3321 }
3322 pll->refcount++;
e04c7350 3323
ee7b9f93
JB		 3324 return pll;
3325}
3326
a1520318 3327static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3328{
3329 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3330 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3331 u32 temp;
3332
3333 temp = I915_READ(dslreg);
3334 udelay(500);
3335 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3336 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3337 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3338 }
3339}
3340
b074cec8
JB		 3341static void ironlake_pfit_enable(struct intel_crtc *crtc)
3342{
3343 struct drm_device *dev = crtc->base.dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 int pipe = crtc->pipe;
3346
fd4daa9c 3347 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3348 /* Force use of hard-coded filter coefficients
3349 * as some pre-programmed values are broken,
3350 * e.g. x201.
3351 */
3352 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3353 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3354 PF_PIPE_SEL_IVB(pipe));
3355 else
3356 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3357 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3358 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3359 }
3360}
3361
bb53d4ae
VS		 3362static void intel_enable_planes(struct drm_crtc *crtc)
3363{
3364 struct drm_device *dev = crtc->dev;
3365 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3366 struct intel_plane *intel_plane;
3367
3368 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3369 if (intel_plane->pipe == pipe)
3370 intel_plane_restore(&intel_plane->base);
3371}
3372
3373static void intel_disable_planes(struct drm_crtc *crtc)
3374{
3375 struct drm_device *dev = crtc->dev;
3376 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3377 struct intel_plane *intel_plane;
3378
3379 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3380 if (intel_plane->pipe == pipe)
3381 intel_plane_disable(&intel_plane->base);
3382}
3383
20bc8673 3384void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 3385{
3386 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3387
3388 if (!crtc->config.ips_enabled)
3389 return;
3390
3391 /* We can only enable IPS after we enable a plane and wait for a vblank.
3392 * We guarantee that the plane is enabled by calling intel_enable_ips
3393 * only after intel_enable_plane. And intel_enable_plane already waits
3394 * for a vblank, so all we need to do here is to enable the IPS bit. */
3395 assert_plane_enabled(dev_priv, crtc->plane);
3396 I915_WRITE(IPS_CTL, IPS_ENABLE);
5ade2c2f
PZ		 3397
3398 /* The bit only becomes 1 in the next vblank, so this wait here is
3399 * essentially intel_wait_for_vblank. If we don't have this and don't
3400 * wait for vblanks until the end of crtc_enable, then the HW state
3401 * readout code will complain that the expected IPS_CTL value is not the
3402 * one we read. */
3403 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3404 DRM_ERROR("Timed out waiting for IPS enable\n");
d77e4531
PZ		 3405}
3406
20bc8673 3407void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 3408{
3409 struct drm_device *dev = crtc->base.dev;
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411
3412 if (!crtc->config.ips_enabled)
3413 return;
3414
3415 assert_plane_enabled(dev_priv, crtc->plane);
3416 I915_WRITE(IPS_CTL, 0);
3417 POSTING_READ(IPS_CTL);
3418
3419 /* We need to wait for a vblank before we can disable the plane. */
3420 intel_wait_for_vblank(dev, crtc->pipe);
3421}
3422
3423/** Loads the palette/gamma unit for the CRTC with the prepared values */
3424static void intel_crtc_load_lut(struct drm_crtc *crtc)
3425{
3426 struct drm_device *dev = crtc->dev;
3427 struct drm_i915_private *dev_priv = dev->dev_private;
3428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3429 enum pipe pipe = intel_crtc->pipe;
3430 int palreg = PALETTE(pipe);
3431 int i;
3432 bool reenable_ips = false;
3433
3434 /* The clocks have to be on to load the palette. */
3435 if (!crtc->enabled || !intel_crtc->active)
3436 return;
3437
3438 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3440 assert_dsi_pll_enabled(dev_priv);
3441 else
3442 assert_pll_enabled(dev_priv, pipe);
3443 }
3444
3445 /* use legacy palette for Ironlake */
3446 if (HAS_PCH_SPLIT(dev))
3447 palreg = LGC_PALETTE(pipe);
3448
3449 /* Workaround : Do not read or write the pipe palette/gamma data while
3450 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3451 */
3452 if (intel_crtc->config.ips_enabled &&
3453 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3454 GAMMA_MODE_MODE_SPLIT)) {
3455 hsw_disable_ips(intel_crtc);
3456 reenable_ips = true;
3457 }
3458
3459 for (i = 0; i < 256; i++) {
3460 I915_WRITE(palreg + 4 * i,
3461 (intel_crtc->lut_r[i] << 16) |
3462 (intel_crtc->lut_g[i] << 8) |
3463 intel_crtc->lut_b[i]);
3464 }
3465
3466 if (reenable_ips)
3467 hsw_enable_ips(intel_crtc);
3468}
3469
f67a559d
JB		 3470static void ironlake_crtc_enable(struct drm_crtc *crtc)
3471{
3472 struct drm_device *dev = crtc->dev;
3473 struct drm_i915_private *dev_priv = dev->dev_private;
3474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3475 struct intel_encoder *encoder;
f67a559d
JB		 3476 int pipe = intel_crtc->pipe;
3477 int plane = intel_crtc->plane;
f67a559d 3478
08a48469
DV		 3479 WARN_ON(!crtc->enabled);
3480
f67a559d
JB		 3481 if (intel_crtc->active)
3482 return;
3483
3484 intel_crtc->active = true;
8664281b
PZ		 3485
3486 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3487 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3488
f6736a1a 3489 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3490 if (encoder->pre_enable)
3491 encoder->pre_enable(encoder);
f67a559d 3492
5bfe2ac0 3493 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3494 /* Note: FDI PLL enabling _must_ be done before we enable the
3495 * cpu pipes, hence this is separate from all the other fdi/pch
3496 * enabling. */
88cefb6c 3497 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3498 } else {
3499 assert_fdi_tx_disabled(dev_priv, pipe);
3500 assert_fdi_rx_disabled(dev_priv, pipe);
3501 }
f67a559d 3502
b074cec8 3503 ironlake_pfit_enable(intel_crtc);
f67a559d 3504
9c54c0dd
JB		 3505 /*
3506 * On ILK+ LUT must be loaded before the pipe is running but with
3507 * clocks enabled
3508 */
3509 intel_crtc_load_lut(crtc);
3510
f37fcc2a 3511 intel_update_watermarks(crtc);
5bfe2ac0 3512 intel_enable_pipe(dev_priv, pipe,
23538ef1 3513 intel_crtc->config.has_pch_encoder, false);
d1de00ef 3514 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3515 intel_enable_planes(crtc);
5c38d48c 3516 intel_crtc_update_cursor(crtc, true);
f67a559d 3517
5bfe2ac0 3518 if (intel_crtc->config.has_pch_encoder)
f67a559d 3519 ironlake_pch_enable(crtc);
c98e9dcf 3520
d1ebd816 3521 mutex_lock(&dev->struct_mutex);
bed4a673 3522 intel_update_fbc(dev);
d1ebd816
BW		 3523 mutex_unlock(&dev->struct_mutex);
3524
fa5c73b1
DV		 3525 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 encoder->enable(encoder);
61b77ddd
DV		 3527
3528 if (HAS_PCH_CPT(dev))
a1520318 3529 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3530
3531 /*
3532 * There seems to be a race in PCH platform hw (at least on some
3533 * outputs) where an enabled pipe still completes any pageflip right
3534 * away (as if the pipe is off) instead of waiting for vblank. As soon
3535 * as the first vblank happend, everything works as expected. Hence just
3536 * wait for one vblank before returning to avoid strange things
3537 * happening.
3538 */
3539 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3540}
3541
42db64ef
PZ		 3542/* IPS only exists on ULT machines and is tied to pipe A. */
3543static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3544{
f5adf94e 3545 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3546}
3547
dda9a66a
VS		 3548static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3549{
3550 struct drm_device *dev = crtc->dev;
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553 int pipe = intel_crtc->pipe;
3554 int plane = intel_crtc->plane;
3555
d1de00ef 3556 intel_enable_primary_plane(dev_priv, plane, pipe);
dda9a66a
VS		 3557 intel_enable_planes(crtc);
3558 intel_crtc_update_cursor(crtc, true);
3559
3560 hsw_enable_ips(intel_crtc);
3561
3562 mutex_lock(&dev->struct_mutex);
3563 intel_update_fbc(dev);
3564 mutex_unlock(&dev->struct_mutex);
3565}
3566
3567static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3568{
3569 struct drm_device *dev = crtc->dev;
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3572 int pipe = intel_crtc->pipe;
3573 int plane = intel_crtc->plane;
3574
3575 intel_crtc_wait_for_pending_flips(crtc);
3576 drm_vblank_off(dev, pipe);
3577
3578 /* FBC must be disabled before disabling the plane on HSW. */
3579 if (dev_priv->fbc.plane == plane)
3580 intel_disable_fbc(dev);
3581
3582 hsw_disable_ips(intel_crtc);
3583
3584 intel_crtc_update_cursor(crtc, false);
3585 intel_disable_planes(crtc);
d1de00ef 3586 intel_disable_primary_plane(dev_priv, plane, pipe);
dda9a66a
VS		 3587}
3588
e4916946
PZ		 3589/*
3590 * This implements the workaround described in the "notes" section of the mode
3591 * set sequence documentation. When going from no pipes or single pipe to
3592 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3593 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3594 */
3595static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3596{
3597 struct drm_device *dev = crtc->base.dev;
3598 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3599
3600 /* We want to get the other_active_crtc only if there's only 1 other
3601 * active crtc. */
3602 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3603 if (!crtc_it->active || crtc_it == crtc)
3604 continue;
3605
3606 if (other_active_crtc)
3607 return;
3608
3609 other_active_crtc = crtc_it;
3610 }
3611 if (!other_active_crtc)
3612 return;
3613
3614 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3615 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3616}
3617
4f771f10
PZ		 3618static void haswell_crtc_enable(struct drm_crtc *crtc)
3619{
3620 struct drm_device *dev = crtc->dev;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3623 struct intel_encoder *encoder;
3624 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3625
3626 WARN_ON(!crtc->enabled);
3627
3628 if (intel_crtc->active)
3629 return;
3630
3631 intel_crtc->active = true;
8664281b
PZ		 3632
3633 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3634 if (intel_crtc->config.has_pch_encoder)
3635 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3636
5bfe2ac0 3637 if (intel_crtc->config.has_pch_encoder)
04945641 3638 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3639
3640 for_each_encoder_on_crtc(dev, crtc, encoder)
3641 if (encoder->pre_enable)
3642 encoder->pre_enable(encoder);
3643
1f544388 3644 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3645
b074cec8 3646 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3647
3648 /*
3649 * On ILK+ LUT must be loaded before the pipe is running but with
3650 * clocks enabled
3651 */
3652 intel_crtc_load_lut(crtc);
3653
1f544388 3654 intel_ddi_set_pipe_settings(crtc);
8228c251 3655 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3656
f37fcc2a 3657 intel_update_watermarks(crtc);
5bfe2ac0 3658 intel_enable_pipe(dev_priv, pipe,
23538ef1 3659 intel_crtc->config.has_pch_encoder, false);
42db64ef 3660
5bfe2ac0 3661 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3662 lpt_pch_enable(crtc);
4f771f10 3663
8807e55b 3664 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3665 encoder->enable(encoder);
8807e55b
JN		 3666 intel_opregion_notify_encoder(encoder, true);
3667 }
4f771f10 3668
e4916946
PZ		 3669 /* If we change the relative order between pipe/planes enabling, we need
3670 * to change the workaround. */
3671 haswell_mode_set_planes_workaround(intel_crtc);
dda9a66a
VS		 3672 haswell_crtc_enable_planes(crtc);
3673
4f771f10
PZ		 3674 /*
3675 * There seems to be a race in PCH platform hw (at least on some
3676 * outputs) where an enabled pipe still completes any pageflip right
3677 * away (as if the pipe is off) instead of waiting for vblank. As soon
3678 * as the first vblank happend, everything works as expected. Hence just
3679 * wait for one vblank before returning to avoid strange things
3680 * happening.
3681 */
3682 intel_wait_for_vblank(dev, intel_crtc->pipe);
3683}
3684
3f8dce3a
DV		 3685static void ironlake_pfit_disable(struct intel_crtc *crtc)
3686{
3687 struct drm_device *dev = crtc->base.dev;
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 int pipe = crtc->pipe;
3690
3691 /* To avoid upsetting the power well on haswell only disable the pfit if
3692 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3693 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3694 I915_WRITE(PF_CTL(pipe), 0);
3695 I915_WRITE(PF_WIN_POS(pipe), 0);
3696 I915_WRITE(PF_WIN_SZ(pipe), 0);
3697 }
3698}
3699
6be4a607
JB		 3700static void ironlake_crtc_disable(struct drm_crtc *crtc)
3701{
3702 struct drm_device *dev = crtc->dev;
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3705 struct intel_encoder *encoder;
6be4a607
JB		 3706 int pipe = intel_crtc->pipe;
3707 int plane = intel_crtc->plane;
5eddb70b 3708 u32 reg, temp;
b52eb4dc 3709
ef9c3aee 3710
f7abfe8b
CW		 3711 if (!intel_crtc->active)
3712 return;
3713
ea9d758d
DV		 3714 for_each_encoder_on_crtc(dev, crtc, encoder)
3715 encoder->disable(encoder);
3716
e6c3a2a6 3717 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3718 drm_vblank_off(dev, pipe);
913d8d11 3719
5c3fe8b0 3720 if (dev_priv->fbc.plane == plane)
973d04f9 3721 intel_disable_fbc(dev);
2c07245f 3722
0d5b8c61 3723 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3724 intel_disable_planes(crtc);
d1de00ef 3725 intel_disable_primary_plane(dev_priv, plane, pipe);
0d5b8c61 3726
d925c59a
DV		 3727 if (intel_crtc->config.has_pch_encoder)
3728 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3729
b24e7179 3730 intel_disable_pipe(dev_priv, pipe);
32f9d658 3731
3f8dce3a 3732 ironlake_pfit_disable(intel_crtc);
2c07245f 3733
bf49ec8c
DV		 3734 for_each_encoder_on_crtc(dev, crtc, encoder)
3735 if (encoder->post_disable)
3736 encoder->post_disable(encoder);
2c07245f 3737
d925c59a
DV		 3738 if (intel_crtc->config.has_pch_encoder) {
3739 ironlake_fdi_disable(crtc);
913d8d11 3740
d925c59a
DV		 3741 ironlake_disable_pch_transcoder(dev_priv, pipe);
3742 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3743
d925c59a
DV		 3744 if (HAS_PCH_CPT(dev)) {
3745 /* disable TRANS_DP_CTL */
3746 reg = TRANS_DP_CTL(pipe);
3747 temp = I915_READ(reg);
3748 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3749 TRANS_DP_PORT_SEL_MASK);
3750 temp |= TRANS_DP_PORT_SEL_NONE;
3751 I915_WRITE(reg, temp);
3752
3753 /* disable DPLL_SEL */
3754 temp = I915_READ(PCH_DPLL_SEL);
11887397 3755 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3756 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3757 }
e3421a18 3758
d925c59a 3759 /* disable PCH DPLL */
e72f9fbf 3760 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3761
d925c59a
DV		 3762 ironlake_fdi_pll_disable(intel_crtc);
3763 }
6b383a7f 3764
f7abfe8b 3765 intel_crtc->active = false;
46ba614c 3766 intel_update_watermarks(crtc);
d1ebd816
BW		 3767
3768 mutex_lock(&dev->struct_mutex);
6b383a7f 3769 intel_update_fbc(dev);
d1ebd816 3770 mutex_unlock(&dev->struct_mutex);
6be4a607 3771}
1b3c7a47 3772
4f771f10 3773static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3774{
4f771f10
PZ		 3775 struct drm_device *dev = crtc->dev;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3778 struct intel_encoder *encoder;
3779 int pipe = intel_crtc->pipe;
3b117c8f 3780 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3781
4f771f10
PZ		 3782 if (!intel_crtc->active)
3783 return;
3784
dda9a66a
VS		 3785 haswell_crtc_disable_planes(crtc);
3786
8807e55b
JN		 3787 for_each_encoder_on_crtc(dev, crtc, encoder) {
3788 intel_opregion_notify_encoder(encoder, false);
4f771f10 3789 encoder->disable(encoder);
8807e55b 3790 }
4f771f10 3791
8664281b
PZ		 3792 if (intel_crtc->config.has_pch_encoder)
3793 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3794 intel_disable_pipe(dev_priv, pipe);
3795
ad80a810 3796 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3797
3f8dce3a 3798 ironlake_pfit_disable(intel_crtc);
4f771f10 3799
1f544388 3800 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3801
3802 for_each_encoder_on_crtc(dev, crtc, encoder)
3803 if (encoder->post_disable)
3804 encoder->post_disable(encoder);
3805
88adfff1 3806 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3807 lpt_disable_pch_transcoder(dev_priv);
8664281b 3808 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3809 intel_ddi_fdi_disable(crtc);
83616634 3810 }
4f771f10
PZ		 3811
3812 intel_crtc->active = false;
46ba614c 3813 intel_update_watermarks(crtc);
4f771f10
PZ		 3814
3815 mutex_lock(&dev->struct_mutex);
3816 intel_update_fbc(dev);
3817 mutex_unlock(&dev->struct_mutex);
3818}
3819
ee7b9f93
JB		 3820static void ironlake_crtc_off(struct drm_crtc *crtc)
3821{
3822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3823 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3824}
3825
6441ab5f
PZ		 3826static void haswell_crtc_off(struct drm_crtc *crtc)
3827{
3828 intel_ddi_put_crtc_pll(crtc);
3829}
3830
02e792fb
DV		 3831static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3832{
02e792fb 3833 if (!enable && intel_crtc->overlay) {
23f09ce3 3834 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3835 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3836
23f09ce3 3837 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3838 dev_priv->mm.interruptible = false;
3839 (void) intel_overlay_switch_off(intel_crtc->overlay);
3840 dev_priv->mm.interruptible = true;
23f09ce3 3841 mutex_unlock(&dev->struct_mutex);
02e792fb 3842 }
02e792fb 3843
5dcdbcb0
CW		 3844 /* Let userspace switch the overlay on again. In most cases userspace
3845 * has to recompute where to put it anyway.
3846 */
02e792fb
DV		 3847}
3848
61bc95c1
EE		 3849/**
3850 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3851 * cursor plane briefly if not already running after enabling the display
3852 * plane.
3853 * This workaround avoids occasional blank screens when self refresh is
3854 * enabled.
3855 */
3856static void
3857g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3858{
3859 u32 cntl = I915_READ(CURCNTR(pipe));
3860
3861 if ((cntl & CURSOR_MODE) == 0) {
3862 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3863
3864 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3865 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3866 intel_wait_for_vblank(dev_priv->dev, pipe);
3867 I915_WRITE(CURCNTR(pipe), cntl);
3868 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3869 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3870 }
3871}
3872
2dd24552
JB		 3873static void i9xx_pfit_enable(struct intel_crtc *crtc)
3874{
3875 struct drm_device *dev = crtc->base.dev;
3876 struct drm_i915_private *dev_priv = dev->dev_private;
3877 struct intel_crtc_config *pipe_config = &crtc->config;
3878
328d8e82 3879 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3880 return;
3881
2dd24552 3882 /*
c0b03411
DV		 3883 * The panel fitter should only be adjusted whilst the pipe is disabled,
3884 * according to register description and PRM.
2dd24552 3885 */
c0b03411
DV		 3886 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3887 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3888
b074cec8
JB		 3889 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3890 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3891
3892 /* Border color in case we don't scale up to the full screen. Black by
3893 * default, change to something else for debugging. */
3894 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3895}
3896
89b667f8
JB		 3897static void valleyview_crtc_enable(struct drm_crtc *crtc)
3898{
3899 struct drm_device *dev = crtc->dev;
3900 struct drm_i915_private *dev_priv = dev->dev_private;
3901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3902 struct intel_encoder *encoder;
3903 int pipe = intel_crtc->pipe;
3904 int plane = intel_crtc->plane;
23538ef1 3905 bool is_dsi;
89b667f8
JB		 3906
3907 WARN_ON(!crtc->enabled);
3908
3909 if (intel_crtc->active)
3910 return;
3911
3912 intel_crtc->active = true;
89b667f8 3913
89b667f8
JB		 3914 for_each_encoder_on_crtc(dev, crtc, encoder)
3915 if (encoder->pre_pll_enable)
3916 encoder->pre_pll_enable(encoder);
3917
23538ef1
JN		 3918 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3919
e9fd1c02
JN		 3920 if (!is_dsi)
3921 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3922
3923 for_each_encoder_on_crtc(dev, crtc, encoder)
3924 if (encoder->pre_enable)
3925 encoder->pre_enable(encoder);
3926
2dd24552
JB		 3927 i9xx_pfit_enable(intel_crtc);
3928
63cbb074
VS		 3929 intel_crtc_load_lut(crtc);
3930
f37fcc2a 3931 intel_update_watermarks(crtc);
23538ef1 3932 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
d1de00ef 3933 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3934 intel_enable_planes(crtc);
5c38d48c 3935 intel_crtc_update_cursor(crtc, true);
89b667f8 3936
89b667f8 3937 intel_update_fbc(dev);
5004945f
JN		 3938
3939 for_each_encoder_on_crtc(dev, crtc, encoder)
3940 encoder->enable(encoder);
89b667f8
JB		 3941}
3942
0b8765c6 3943static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3944{
3945 struct drm_device *dev = crtc->dev;
79e53945
JB		 3946 struct drm_i915_private *dev_priv = dev->dev_private;
3947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3948 struct intel_encoder *encoder;
79e53945 3949 int pipe = intel_crtc->pipe;
80824003 3950 int plane = intel_crtc->plane;
79e53945 3951
08a48469
DV		 3952 WARN_ON(!crtc->enabled);
3953
f7abfe8b
CW		 3954 if (intel_crtc->active)
3955 return;
3956
3957 intel_crtc->active = true;
6b383a7f 3958
9d6d9f19
MK		 3959 for_each_encoder_on_crtc(dev, crtc, encoder)
3960 if (encoder->pre_enable)
3961 encoder->pre_enable(encoder);
3962
f6736a1a
DV		 3963 i9xx_enable_pll(intel_crtc);
3964
2dd24552
JB		 3965 i9xx_pfit_enable(intel_crtc);
3966
63cbb074
VS		 3967 intel_crtc_load_lut(crtc);
3968
f37fcc2a 3969 intel_update_watermarks(crtc);
23538ef1 3970 intel_enable_pipe(dev_priv, pipe, false, false);
d1de00ef 3971 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3972 intel_enable_planes(crtc);
22e407d7 3973 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3974 if (IS_G4X(dev))
3975 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3976 intel_crtc_update_cursor(crtc, true);
79e53945 3977
0b8765c6
JB		 3978 /* Give the overlay scaler a chance to enable if it's on this pipe */
3979 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3980
f440eb13 3981 intel_update_fbc(dev);
ef9c3aee 3982
fa5c73b1
DV		 3983 for_each_encoder_on_crtc(dev, crtc, encoder)
3984 encoder->enable(encoder);
0b8765c6 3985}
79e53945 3986
87476d63
DV		 3987static void i9xx_pfit_disable(struct intel_crtc *crtc)
3988{
3989 struct drm_device *dev = crtc->base.dev;
3990 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3991
328d8e82
DV		 3992 if (!crtc->config.gmch_pfit.control)
3993 return;
87476d63 3994
328d8e82 3995 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3996
328d8e82
DV		 3997 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3998 I915_READ(PFIT_CONTROL));
3999 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 4000}
4001
0b8765c6
JB		 4002static void i9xx_crtc_disable(struct drm_crtc *crtc)
4003{
4004 struct drm_device *dev = crtc->dev;
4005 struct drm_i915_private *dev_priv = dev->dev_private;
4006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4007 struct intel_encoder *encoder;
0b8765c6
JB		 4008 int pipe = intel_crtc->pipe;
4009 int plane = intel_crtc->plane;
ef9c3aee 4010
f7abfe8b
CW		 4011 if (!intel_crtc->active)
4012 return;
4013
ea9d758d
DV		 4014 for_each_encoder_on_crtc(dev, crtc, encoder)
4015 encoder->disable(encoder);
4016
0b8765c6 4017 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 4018 intel_crtc_wait_for_pending_flips(crtc);
4019 drm_vblank_off(dev, pipe);
0b8765c6 4020
5c3fe8b0 4021 if (dev_priv->fbc.plane == plane)
973d04f9 4022 intel_disable_fbc(dev);
79e53945 4023
0d5b8c61
VS		 4024 intel_crtc_dpms_overlay(intel_crtc, false);
4025 intel_crtc_update_cursor(crtc, false);
bb53d4ae 4026 intel_disable_planes(crtc);
d1de00ef 4027 intel_disable_primary_plane(dev_priv, plane, pipe);
0d5b8c61 4028
b24e7179 4029 intel_disable_pipe(dev_priv, pipe);
24a1f16d 4030
87476d63 4031 i9xx_pfit_disable(intel_crtc);
24a1f16d 4032
89b667f8
JB		 4033 for_each_encoder_on_crtc(dev, crtc, encoder)
4034 if (encoder->post_disable)
4035 encoder->post_disable(encoder);
4036
f6071166
JB		 4037 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4038 vlv_disable_pll(dev_priv, pipe);
4039 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 4040 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 4041
f7abfe8b 4042 intel_crtc->active = false;
46ba614c 4043 intel_update_watermarks(crtc);
f37fcc2a 4044
6b383a7f 4045 intel_update_fbc(dev);
0b8765c6
JB		 4046}
4047
ee7b9f93
JB		 4048static void i9xx_crtc_off(struct drm_crtc *crtc)
4049{
4050}
4051
976f8a20
DV		 4052static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4053 bool enabled)
2c07245f
ZW		 4054{
4055 struct drm_device *dev = crtc->dev;
4056 struct drm_i915_master_private *master_priv;
4057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4058 int pipe = intel_crtc->pipe;
79e53945
JB		 4059
4060 if (!dev->primary->master)
4061 return;
4062
4063 master_priv = dev->primary->master->driver_priv;
4064 if (!master_priv->sarea_priv)
4065 return;
4066
79e53945
JB		 4067 switch (pipe) {
4068 case 0:
4069 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4070 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4071 break;
4072 case 1:
4073 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4074 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4075 break;
4076 default:
9db4a9c7 4077 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 4078 break;
4079 }
79e53945
JB		 4080}
4081
976f8a20
DV		 4082/**
4083 * Sets the power management mode of the pipe and plane.
4084 */
4085void intel_crtc_update_dpms(struct drm_crtc *crtc)
4086{
4087 struct drm_device *dev = crtc->dev;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 struct intel_encoder *intel_encoder;
4090 bool enable = false;
4091
4092 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4093 enable |= intel_encoder->connectors_active;
4094
4095 if (enable)
4096 dev_priv->display.crtc_enable(crtc);
4097 else
4098 dev_priv->display.crtc_disable(crtc);
4099
4100 intel_crtc_update_sarea(crtc, enable);
4101}
4102
cdd59983
CW		 4103static void intel_crtc_disable(struct drm_crtc *crtc)
4104{
cdd59983 4105 struct drm_device *dev = crtc->dev;
976f8a20 4106 struct drm_connector *connector;
ee7b9f93 4107 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 4108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 4109
976f8a20
DV		 4110 /* crtc should still be enabled when we disable it. */
4111 WARN_ON(!crtc->enabled);
4112
4113 dev_priv->display.crtc_disable(crtc);
c77bf565 4114 intel_crtc->eld_vld = false;
976f8a20 4115 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 4116 dev_priv->display.off(crtc);
4117
931872fc 4118 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 4119 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 4120 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 4121
4122 if (crtc->fb) {
4123 mutex_lock(&dev->struct_mutex);
1690e1eb 4124 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4125 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4126 crtc->fb = NULL;
4127 }
4128
4129 /* Update computed state. */
4130 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4131 if (!connector->encoder || !connector->encoder->crtc)
4132 continue;
4133
4134 if (connector->encoder->crtc != crtc)
4135 continue;
4136
4137 connector->dpms = DRM_MODE_DPMS_OFF;
4138 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4139 }
4140}
4141
ea5b213a 4142void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4143{
4ef69c7a 4144 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4145
ea5b213a
CW		 4146 drm_encoder_cleanup(encoder);
4147 kfree(intel_encoder);
7e7d76c3
JB		 4148}
4149
9237329d 4150/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4151 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4152 * state of the entire output pipe. */
9237329d 4153static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4154{
5ab432ef
DV		 4155 if (mode == DRM_MODE_DPMS_ON) {
4156 encoder->connectors_active = true;
4157
b2cabb0e 4158 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4159 } else {
4160 encoder->connectors_active = false;
4161
b2cabb0e 4162 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4163 }
79e53945
JB		 4164}
4165
0a91ca29
DV		 4166/* Cross check the actual hw state with our own modeset state tracking (and it's
4167 * internal consistency). */
b980514c 4168static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4169{
0a91ca29
DV		 4170 if (connector->get_hw_state(connector)) {
4171 struct intel_encoder *encoder = connector->encoder;
4172 struct drm_crtc *crtc;
4173 bool encoder_enabled;
4174 enum pipe pipe;
4175
4176 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4177 connector->base.base.id,
4178 drm_get_connector_name(&connector->base));
4179
4180 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4181 "wrong connector dpms state\n");
4182 WARN(connector->base.encoder != &encoder->base,
4183 "active connector not linked to encoder\n");
4184 WARN(!encoder->connectors_active,
4185 "encoder->connectors_active not set\n");
4186
4187 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4188 WARN(!encoder_enabled, "encoder not enabled\n");
4189 if (WARN_ON(!encoder->base.crtc))
4190 return;
4191
4192 crtc = encoder->base.crtc;
4193
4194 WARN(!crtc->enabled, "crtc not enabled\n");
4195 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4196 WARN(pipe != to_intel_crtc(crtc)->pipe,
4197 "encoder active on the wrong pipe\n");
4198 }
79e53945
JB		 4199}
4200
5ab432ef
DV		 4201/* Even simpler default implementation, if there's really no special case to
4202 * consider. */
4203void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4204{
5ab432ef
DV		 4205 /* All the simple cases only support two dpms states. */
4206 if (mode != DRM_MODE_DPMS_ON)
4207 mode = DRM_MODE_DPMS_OFF;
d4270e57 4208
5ab432ef
DV		 4209 if (mode == connector->dpms)
4210 return;
4211
4212 connector->dpms = mode;
4213
4214 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 4215 if (connector->encoder)
4216 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 4217
b980514c 4218 intel_modeset_check_state(connector->dev);
79e53945
JB		 4219}
4220
f0947c37
DV		 4221/* Simple connector->get_hw_state implementation for encoders that support only
4222 * one connector and no cloning and hence the encoder state determines the state
4223 * of the connector. */
4224bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4225{
24929352 4226 enum pipe pipe = 0;
f0947c37 4227 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4228
f0947c37 4229 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4230}
4231
1857e1da
DV		 4232static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4233 struct intel_crtc_config *pipe_config)
4234{
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236 struct intel_crtc *pipe_B_crtc =
4237 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4238
4239 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4240 pipe_name(pipe), pipe_config->fdi_lanes);
4241 if (pipe_config->fdi_lanes > 4) {
4242 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4243 pipe_name(pipe), pipe_config->fdi_lanes);
4244 return false;
4245 }
4246
4247 if (IS_HASWELL(dev)) {
4248 if (pipe_config->fdi_lanes > 2) {
4249 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4250 pipe_config->fdi_lanes);
4251 return false;
4252 } else {
4253 return true;
4254 }
4255 }
4256
4257 if (INTEL_INFO(dev)->num_pipes == 2)
4258 return true;
4259
4260 /* Ivybridge 3 pipe is really complicated */
4261 switch (pipe) {
4262 case PIPE_A:
4263 return true;
4264 case PIPE_B:
4265 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4266 pipe_config->fdi_lanes > 2) {
4267 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4268 pipe_name(pipe), pipe_config->fdi_lanes);
4269 return false;
4270 }
4271 return true;
4272 case PIPE_C:
1e833f40 4273 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4274 pipe_B_crtc->config.fdi_lanes <= 2) {
4275 if (pipe_config->fdi_lanes > 2) {
4276 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4277 pipe_name(pipe), pipe_config->fdi_lanes);
4278 return false;
4279 }
4280 } else {
4281 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4282 return false;
4283 }
4284 return true;
4285 default:
4286 BUG();
4287 }
4288}
4289
e29c22c0
DV		 4290#define RETRY 1
4291static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4292 struct intel_crtc_config *pipe_config)
877d48d5 4293{
1857e1da 4294 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4295 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4296 int lane, link_bw, fdi_dotclock;
e29c22c0 4297 bool setup_ok, needs_recompute = false;
877d48d5 4298
e29c22c0 4299retry:
877d48d5
DV		 4300 /* FDI is a binary signal running at ~2.7GHz, encoding
4301 * each output octet as 10 bits. The actual frequency
4302 * is stored as a divider into a 100MHz clock, and the
4303 * mode pixel clock is stored in units of 1KHz.
4304 * Hence the bw of each lane in terms of the mode signal
4305 * is:
4306 */
4307 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4308
241bfc38 4309 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4310
2bd89a07 4311 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4312 pipe_config->pipe_bpp);
4313
4314 pipe_config->fdi_lanes = lane;
4315
2bd89a07 4316 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4317 link_bw, &pipe_config->fdi_m_n);
1857e1da 4318
e29c22c0
DV		 4319 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4320 intel_crtc->pipe, pipe_config);
4321 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4322 pipe_config->pipe_bpp -= 2*3;
4323 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4324 pipe_config->pipe_bpp);
4325 needs_recompute = true;
4326 pipe_config->bw_constrained = true;
4327
4328 goto retry;
4329 }
4330
4331 if (needs_recompute)
4332 return RETRY;
4333
4334 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4335}
4336
42db64ef
PZ		 4337static void hsw_compute_ips_config(struct intel_crtc *crtc,
4338 struct intel_crtc_config *pipe_config)
4339{
3c4ca58c
PZ		 4340 pipe_config->ips_enabled = i915_enable_ips &&
4341 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4342 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4343}
4344
a43f6e0f 4345static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4346 struct intel_crtc_config *pipe_config)
79e53945 4347{
a43f6e0f 4348 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4349 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4350
ad3a4479 4351 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4352 if (INTEL_INFO(dev)->gen < 4) {
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 int clock_limit =
4355 dev_priv->display.get_display_clock_speed(dev);
4356
4357 /*
4358 * Enable pixel doubling when the dot clock
4359 * is > 90% of the (display) core speed.
4360 *
b397c96b
VS		 4361 * GDG double wide on either pipe,
4362 * otherwise pipe A only.
cf532bb2 4363 */
b397c96b 4364 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4365 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4366 clock_limit *= 2;
cf532bb2 4367 pipe_config->double_wide = true;
ad3a4479
VS		 4368 }
4369
241bfc38 4370 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4371 return -EINVAL;
2c07245f 4372 }
89749350 4373
1d1d0e27
VS		 4374 /*
4375 * Pipe horizontal size must be even in:
4376 * - DVO ganged mode
4377 * - LVDS dual channel mode
4378 * - Double wide pipe
4379 */
4380 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4381 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4382 pipe_config->pipe_src_w &= ~1;
4383
8693a824
DL		 4384 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4385 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4386 */
4387 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4388 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4389 return -EINVAL;
44f46b42 4390
bd080ee5 4391 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4392 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4393 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4394 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4395 * for lvds. */
4396 pipe_config->pipe_bpp = 8*3;
4397 }
4398
f5adf94e 4399 if (HAS_IPS(dev))
a43f6e0f
DV		 4400 hsw_compute_ips_config(crtc, pipe_config);
4401
4402 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4403 * clock survives for now. */
4404 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4405 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4406
877d48d5 4407 if (pipe_config->has_pch_encoder)
a43f6e0f 4408 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4409
e29c22c0 4410 return 0;
79e53945
JB		 4411}
4412
25eb05fc
JB		 4413static int valleyview_get_display_clock_speed(struct drm_device *dev)
4414{
4415 return 400000; /* FIXME */
4416}
4417
e70236a8
JB		 4418static int i945_get_display_clock_speed(struct drm_device *dev)
4419{
4420 return 400000;
4421}
79e53945 4422
e70236a8 4423static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4424{
e70236a8
JB		 4425 return 333000;
4426}
79e53945 4427
e70236a8
JB		 4428static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4429{
4430 return 200000;
4431}
79e53945 4432
257a7ffc
DV		 4433static int pnv_get_display_clock_speed(struct drm_device *dev)
4434{
4435 u16 gcfgc = 0;
4436
4437 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4438
4439 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4440 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4441 return 267000;
4442 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4443 return 333000;
4444 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4445 return 444000;
4446 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4447 return 200000;
4448 default:
4449 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4450 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4451 return 133000;
4452 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4453 return 167000;
4454 }
4455}
4456
e70236a8
JB		 4457static int i915gm_get_display_clock_speed(struct drm_device *dev)
4458{
4459 u16 gcfgc = 0;
79e53945 4460
e70236a8
JB		 4461 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4462
4463 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4464 return 133000;
4465 else {
4466 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4467 case GC_DISPLAY_CLOCK_333_MHZ:
4468 return 333000;
4469 default:
4470 case GC_DISPLAY_CLOCK_190_200_MHZ:
4471 return 190000;
79e53945 4472 }
e70236a8
JB		 4473 }
4474}
4475
4476static int i865_get_display_clock_speed(struct drm_device *dev)
4477{
4478 return 266000;
4479}
4480
4481static int i855_get_display_clock_speed(struct drm_device *dev)
4482{
4483 u16 hpllcc = 0;
4484 /* Assume that the hardware is in the high speed state. This
4485 * should be the default.
4486 */
4487 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4488 case GC_CLOCK_133_200:
4489 case GC_CLOCK_100_200:
4490 return 200000;
4491 case GC_CLOCK_166_250:
4492 return 250000;
4493 case GC_CLOCK_100_133:
79e53945 4494 return 133000;
e70236a8 4495 }
79e53945 4496
e70236a8
JB		 4497 /* Shouldn't happen */
4498 return 0;
4499}
79e53945 4500
e70236a8
JB		 4501static int i830_get_display_clock_speed(struct drm_device *dev)
4502{
4503 return 133000;
79e53945
JB		 4504}
4505
2c07245f 4506static void
a65851af 4507intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4508{
a65851af
VS		 4509 while (*num > DATA_LINK_M_N_MASK ||
4510 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4511 *num >>= 1;
4512 *den >>= 1;
4513 }
4514}
4515
a65851af
VS		 4516static void compute_m_n(unsigned int m, unsigned int n,
4517 uint32_t *ret_m, uint32_t *ret_n)
4518{
4519 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4520 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4521 intel_reduce_m_n_ratio(ret_m, ret_n);
4522}
4523
e69d0bc1
DV		 4524void
4525intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4526 int pixel_clock, int link_clock,
4527 struct intel_link_m_n *m_n)
2c07245f 4528{
e69d0bc1 4529 m_n->tu = 64;
a65851af
VS		 4530
4531 compute_m_n(bits_per_pixel * pixel_clock,
4532 link_clock * nlanes * 8,
4533 &m_n->gmch_m, &m_n->gmch_n);
4534
4535 compute_m_n(pixel_clock, link_clock,
4536 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4537}
4538
a7615030
CW		 4539static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4540{
72bbe58c
KP		 4541 if (i915_panel_use_ssc >= 0)
4542 return i915_panel_use_ssc != 0;
41aa3448 4543 return dev_priv->vbt.lvds_use_ssc
435793df 4544 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4545}
4546
c65d77d8
JB		 4547static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4548{
4549 struct drm_device *dev = crtc->dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 int refclk;
4552
a0c4da24 4553 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4554 refclk = 100000;
a0c4da24 4555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4556 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4557 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4558 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4559 refclk / 1000);
4560 } else if (!IS_GEN2(dev)) {
4561 refclk = 96000;
4562 } else {
4563 refclk = 48000;
4564 }
4565
4566 return refclk;
4567}
4568
7429e9d4 4569static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4570{
7df00d7a 4571 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4572}
f47709a9 4573
7429e9d4
DV		 4574static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4575{
4576 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4577}
4578
f47709a9 4579static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4580 intel_clock_t *reduced_clock)
4581{
f47709a9 4582 struct drm_device *dev = crtc->base.dev;
a7516a05 4583 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4584 int pipe = crtc->pipe;
a7516a05
JB		 4585 u32 fp, fp2 = 0;
4586
4587 if (IS_PINEVIEW(dev)) {
7429e9d4 4588 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4589 if (reduced_clock)
7429e9d4 4590 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4591 } else {
7429e9d4 4592 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4593 if (reduced_clock)
7429e9d4 4594 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4595 }
4596
4597 I915_WRITE(FP0(pipe), fp);
8bcc2795 4598 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4599
f47709a9
DV		 4600 crtc->lowfreq_avail = false;
4601 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4602 reduced_clock && i915_powersave) {
4603 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4604 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4605 crtc->lowfreq_avail = true;
a7516a05
JB		 4606 } else {
4607 I915_WRITE(FP1(pipe), fp);
8bcc2795 4608 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4609 }
4610}
4611
5e69f97f
CML		 4612static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4613 pipe)
89b667f8
JB		 4614{
4615 u32 reg_val;
4616
4617 /*
4618 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4619 * and set it to a reasonable value instead.
4620 */
5e69f97f 4621 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4622 reg_val &= 0xffffff00;
4623 reg_val |= 0x00000030;
5e69f97f 4624 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4625
5e69f97f 4626 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4627 reg_val &= 0x8cffffff;
4628 reg_val = 0x8c000000;
5e69f97f 4629 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4630
5e69f97f 4631 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4632 reg_val &= 0xffffff00;
5e69f97f 4633 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4634
5e69f97f 4635 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4636 reg_val &= 0x00ffffff;
4637 reg_val |= 0xb0000000;
5e69f97f 4638 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4639}
4640
b551842d
DV		 4641static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4642 struct intel_link_m_n *m_n)
4643{
4644 struct drm_device *dev = crtc->base.dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 int pipe = crtc->pipe;
4647
e3b95f1e
DV		 4648 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4649 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4650 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4651 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4652}
4653
4654static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4655 struct intel_link_m_n *m_n)
4656{
4657 struct drm_device *dev = crtc->base.dev;
4658 struct drm_i915_private *dev_priv = dev->dev_private;
4659 int pipe = crtc->pipe;
4660 enum transcoder transcoder = crtc->config.cpu_transcoder;
4661
4662 if (INTEL_INFO(dev)->gen >= 5) {
4663 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4664 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4665 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4666 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4667 } else {
e3b95f1e
DV		 4668 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4669 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4670 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4671 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4672 }
4673}
4674
03afc4a2
DV		 4675static void intel_dp_set_m_n(struct intel_crtc *crtc)
4676{
4677 if (crtc->config.has_pch_encoder)
4678 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4679 else
4680 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4681}
4682
f47709a9 4683static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4684{
f47709a9 4685 struct drm_device *dev = crtc->base.dev;
a0c4da24 4686 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4687 int pipe = crtc->pipe;
89b667f8 4688 u32 dpll, mdiv;
a0c4da24 4689 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4690 u32 coreclk, reg_val, dpll_md;
a0c4da24 4691
09153000
DV		 4692 mutex_lock(&dev_priv->dpio_lock);
4693
f47709a9
DV		 4694 bestn = crtc->config.dpll.n;
4695 bestm1 = crtc->config.dpll.m1;
4696 bestm2 = crtc->config.dpll.m2;
4697 bestp1 = crtc->config.dpll.p1;
4698 bestp2 = crtc->config.dpll.p2;
a0c4da24 4699
89b667f8
JB		 4700 /* See eDP HDMI DPIO driver vbios notes doc */
4701
4702 /* PLL B needs special handling */
4703 if (pipe)
5e69f97f 4704 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4705
4706 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4707 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4708
4709 /* Disable target IRef on PLL */
5e69f97f 4710 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4711 reg_val &= 0x00ffffff;
5e69f97f 4712 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4713
4714 /* Disable fast lock */
5e69f97f 4715 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4716
4717 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4718 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4719 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4720 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4721 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4722
4723 /*
4724 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4725 * but we don't support that).
4726 * Note: don't use the DAC post divider as it seems unstable.
4727 */
4728 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4729 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4730
a0c4da24 4731 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4732 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4733
89b667f8 4734 /* Set HBR and RBR LPF coefficients */
ff9a6750 4735 if (crtc->config.port_clock == 162000 ||
99750bd4 4736 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4737 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4738 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4739 0x009f0003);
89b667f8 4740 else
5e69f97f 4741 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4742 0x00d0000f);
4743
4744 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4745 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4746 /* Use SSC source */
4747 if (!pipe)
5e69f97f 4748 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4749 0x0df40000);
4750 else
5e69f97f 4751 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4752 0x0df70000);
4753 } else { /* HDMI or VGA */
4754 /* Use bend source */
4755 if (!pipe)
5e69f97f 4756 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4757 0x0df70000);
4758 else
5e69f97f 4759 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4760 0x0df40000);
4761 }
a0c4da24 4762
5e69f97f 4763 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4764 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4765 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4766 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4767 coreclk |= 0x01000000;
5e69f97f 4768 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4769
5e69f97f 4770 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4771
89b667f8
JB		 4772 /* Enable DPIO clock input */
4773 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4774 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4775 /* We should never disable this, set it here for state tracking */
4776 if (pipe == PIPE_B)
89b667f8 4777 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4778 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4779 crtc->config.dpll_hw_state.dpll = dpll;
4780
ef1b460d
DV		 4781 dpll_md = (crtc->config.pixel_multiplier - 1)
4782 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4783 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4784
89b667f8
JB		 4785 if (crtc->config.has_dp_encoder)
4786 intel_dp_set_m_n(crtc);
09153000
DV		 4787
4788 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4789}
4790
f47709a9
DV		 4791static void i9xx_update_pll(struct intel_crtc *crtc,
4792 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4793 int num_connectors)
4794{
f47709a9 4795 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4796 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4797 u32 dpll;
4798 bool is_sdvo;
f47709a9 4799 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4800
f47709a9 4801 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4802
f47709a9
DV		 4803 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4804 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4805
4806 dpll = DPLL_VGA_MODE_DIS;
4807
f47709a9 4808 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4809 dpll |= DPLLB_MODE_LVDS;
4810 else
4811 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4812
ef1b460d 4813 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4814 dpll |= (crtc->config.pixel_multiplier - 1)
4815 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4816 }
198a037f
DV		 4817
4818 if (is_sdvo)
4a33e48d 4819 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4820
f47709a9 4821 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4822 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4823
4824 /* compute bitmask from p1 value */
4825 if (IS_PINEVIEW(dev))
4826 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4827 else {
4828 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4829 if (IS_G4X(dev) && reduced_clock)
4830 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4831 }
4832 switch (clock->p2) {
4833 case 5:
4834 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4835 break;
4836 case 7:
4837 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4838 break;
4839 case 10:
4840 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4841 break;
4842 case 14:
4843 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4844 break;
4845 }
4846 if (INTEL_INFO(dev)->gen >= 4)
4847 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4848
09ede541 4849 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4850 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4851 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4852 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4853 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4854 else
4855 dpll |= PLL_REF_INPUT_DREFCLK;
4856
4857 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4858 crtc->config.dpll_hw_state.dpll = dpll;
4859
eb1cbe48 4860 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4861 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4862 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4863 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4864 }
66e3d5c0
DV		 4865
4866 if (crtc->config.has_dp_encoder)
4867 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4868}
4869
f47709a9 4870static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4871 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4872 int num_connectors)
4873{
f47709a9 4874 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4875 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4876 u32 dpll;
f47709a9 4877 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4878
f47709a9 4879 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4880
eb1cbe48
DV		 4881 dpll = DPLL_VGA_MODE_DIS;
4882
f47709a9 4883 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4884 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4885 } else {
4886 if (clock->p1 == 2)
4887 dpll |= PLL_P1_DIVIDE_BY_TWO;
4888 else
4889 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4890 if (clock->p2 == 4)
4891 dpll |= PLL_P2_DIVIDE_BY_4;
4892 }
4893
4a33e48d
DV		 4894 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4895 dpll |= DPLL_DVO_2X_MODE;
4896
f47709a9 4897 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4898 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4899 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4900 else
4901 dpll |= PLL_REF_INPUT_DREFCLK;
4902
4903 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4904 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4905}
4906
8a654f3b 4907static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4908{
4909 struct drm_device *dev = intel_crtc->base.dev;
4910 struct drm_i915_private *dev_priv = dev->dev_private;
4911 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4912 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4913 struct drm_display_mode *adjusted_mode =
4914 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4915 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4916
4917 /* We need to be careful not to changed the adjusted mode, for otherwise
4918 * the hw state checker will get angry at the mismatch. */
4919 crtc_vtotal = adjusted_mode->crtc_vtotal;
4920 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4921
4922 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4923 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4924 crtc_vtotal -= 1;
4925 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4926 vsyncshift = adjusted_mode->crtc_hsync_start
4927 - adjusted_mode->crtc_htotal / 2;
4928 } else {
4929 vsyncshift = 0;
4930 }
4931
4932 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4933 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4934
fe2b8f9d 4935 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4936 (adjusted_mode->crtc_hdisplay - 1) |
4937 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4938 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4939 (adjusted_mode->crtc_hblank_start - 1) |
4940 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4941 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4942 (adjusted_mode->crtc_hsync_start - 1) |
4943 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4944
fe2b8f9d 4945 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4946 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4947 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4948 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4949 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4950 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4951 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4952 (adjusted_mode->crtc_vsync_start - 1) |
4953 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4954
b5e508d4
PZ		 4955 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4956 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4957 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4958 * bits. */
4959 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4960 (pipe == PIPE_B || pipe == PIPE_C))
4961 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4962
b0e77b9c
PZ		 4963 /* pipesrc controls the size that is scaled from, which should
4964 * always be the user's requested size.
4965 */
4966 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4967 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4968 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4969}
4970
1bd1bd80
DV		 4971static void intel_get_pipe_timings(struct intel_crtc *crtc,
4972 struct intel_crtc_config *pipe_config)
4973{
4974 struct drm_device *dev = crtc->base.dev;
4975 struct drm_i915_private *dev_priv = dev->dev_private;
4976 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4977 uint32_t tmp;
4978
4979 tmp = I915_READ(HTOTAL(cpu_transcoder));
4980 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4981 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4982 tmp = I915_READ(HBLANK(cpu_transcoder));
4983 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4984 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4985 tmp = I915_READ(HSYNC(cpu_transcoder));
4986 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4987 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4988
4989 tmp = I915_READ(VTOTAL(cpu_transcoder));
4990 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4991 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4992 tmp = I915_READ(VBLANK(cpu_transcoder));
4993 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4994 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4995 tmp = I915_READ(VSYNC(cpu_transcoder));
4996 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4997 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4998
4999 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5000 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5001 pipe_config->adjusted_mode.crtc_vtotal += 1;
5002 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5003 }
5004
5005 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 5006 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5007 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5008
5009 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5010 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 5011}
5012
babea61d
JB		 5013static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5014 struct intel_crtc_config *pipe_config)
5015{
5016 struct drm_crtc *crtc = &intel_crtc->base;
5017
5018 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5019 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5020 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5021 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5022
5023 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5024 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5025 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5026 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5027
5028 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5029
241bfc38 5030 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 5031 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5032}
5033
84b046f3
DV		 5034static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5035{
5036 struct drm_device *dev = intel_crtc->base.dev;
5037 struct drm_i915_private *dev_priv = dev->dev_private;
5038 uint32_t pipeconf;
5039
9f11a9e4 5040 pipeconf = 0;
84b046f3 5041
67c72a12
DV		 5042 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5043 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5044 pipeconf |= PIPECONF_ENABLE;
5045
cf532bb2
VS		 5046 if (intel_crtc->config.double_wide)
5047 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 5048
ff9ce46e
DV		 5049 /* only g4x and later have fancy bpc/dither controls */
5050 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 5051 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5052 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5053 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 5054 PIPECONF_DITHER_TYPE_SP;
84b046f3 5055
ff9ce46e
DV		 5056 switch (intel_crtc->config.pipe_bpp) {
5057 case 18:
5058 pipeconf |= PIPECONF_6BPC;
5059 break;
5060 case 24:
5061 pipeconf |= PIPECONF_8BPC;
5062 break;
5063 case 30:
5064 pipeconf |= PIPECONF_10BPC;
5065 break;
5066 default:
5067 /* Case prevented by intel_choose_pipe_bpp_dither. */
5068 BUG();
84b046f3
DV		 5069 }
5070 }
5071
5072 if (HAS_PIPE_CXSR(dev)) {
5073 if (intel_crtc->lowfreq_avail) {
5074 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5075 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5076 } else {
5077 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 5078 }
5079 }
5080
84b046f3
DV		 5081 if (!IS_GEN2(dev) &&
5082 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5083 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5084 else
5085 pipeconf |= PIPECONF_PROGRESSIVE;
5086
9f11a9e4
DV		 5087 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5088 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 5089
84b046f3
DV		 5090 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5091 POSTING_READ(PIPECONF(intel_crtc->pipe));
5092}
5093
f564048e 5094static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5095 int x, int y,
94352cf9 5096 struct drm_framebuffer *fb)
79e53945
JB		 5097{
5098 struct drm_device *dev = crtc->dev;
5099 struct drm_i915_private *dev_priv = dev->dev_private;
5100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5101 int pipe = intel_crtc->pipe;
80824003 5102 int plane = intel_crtc->plane;
c751ce4f 5103 int refclk, num_connectors = 0;
652c393a 5104 intel_clock_t clock, reduced_clock;
84b046f3 5105 u32 dspcntr;
a16af721 5106 bool ok, has_reduced_clock = false;
e9fd1c02 5107 bool is_lvds = false, is_dsi = false;
5eddb70b 5108 struct intel_encoder *encoder;
d4906093 5109 const intel_limit_t *limit;
5c3b82e2 5110 int ret;
79e53945 5111
6c2b7c12 5112 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 5113 switch (encoder->type) {
79e53945
JB		 5114 case INTEL_OUTPUT_LVDS:
5115 is_lvds = true;
5116 break;
e9fd1c02
JN		 5117 case INTEL_OUTPUT_DSI:
5118 is_dsi = true;
5119 break;
79e53945 5120 }
43565a06 5121
c751ce4f 5122 num_connectors++;
79e53945
JB		 5123 }
5124
f2335330
JN		 5125 if (is_dsi)
5126 goto skip_dpll;
5127
5128 if (!intel_crtc->config.clock_set) {
5129 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5130
e9fd1c02
JN		 5131 /*
5132 * Returns a set of divisors for the desired target clock with
5133 * the given refclk, or FALSE. The returned values represent
5134 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5135 * 2) / p1 / p2.
5136 */
5137 limit = intel_limit(crtc, refclk);
5138 ok = dev_priv->display.find_dpll(limit, crtc,
5139 intel_crtc->config.port_clock,
5140 refclk, NULL, &clock);
f2335330 5141 if (!ok) {
e9fd1c02
JN		 5142 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5143 return -EINVAL;
5144 }
79e53945 5145
f2335330
JN		 5146 if (is_lvds && dev_priv->lvds_downclock_avail) {
5147 /*
5148 * Ensure we match the reduced clock's P to the target
5149 * clock. If the clocks don't match, we can't switch
5150 * the display clock by using the FP0/FP1. In such case
5151 * we will disable the LVDS downclock feature.
5152 */
5153 has_reduced_clock =
5154 dev_priv->display.find_dpll(limit, crtc,
5155 dev_priv->lvds_downclock,
5156 refclk, &clock,
5157 &reduced_clock);
5158 }
5159 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5160 intel_crtc->config.dpll.n = clock.n;
5161 intel_crtc->config.dpll.m1 = clock.m1;
5162 intel_crtc->config.dpll.m2 = clock.m2;
5163 intel_crtc->config.dpll.p1 = clock.p1;
5164 intel_crtc->config.dpll.p2 = clock.p2;
5165 }
7026d4ac 5166
e9fd1c02 5167 if (IS_GEN2(dev)) {
8a654f3b 5168 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5169 has_reduced_clock ? &reduced_clock : NULL,
5170 num_connectors);
e9fd1c02 5171 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5172 vlv_update_pll(intel_crtc);
e9fd1c02 5173 } else {
f47709a9 5174 i9xx_update_pll(intel_crtc,
eb1cbe48 5175 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5176 num_connectors);
e9fd1c02 5177 }
79e53945 5178
f2335330 5179skip_dpll:
79e53945
JB		 5180 /* Set up the display plane register */
5181 dspcntr = DISPPLANE_GAMMA_ENABLE;
5182
da6ecc5d
JB		 5183 if (!IS_VALLEYVIEW(dev)) {
5184 if (pipe == 0)
5185 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5186 else
5187 dspcntr |= DISPPLANE_SEL_PIPE_B;
5188 }
79e53945 5189
8a654f3b 5190 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5191
5192 /* pipesrc and dspsize control the size that is scaled from,
5193 * which should always be the user's requested size.
79e53945 5194 */
929c77fb 5195 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5196 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5197 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5198 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5199
84b046f3
DV		 5200 i9xx_set_pipeconf(intel_crtc);
5201
f564048e
EA		 5202 I915_WRITE(DSPCNTR(plane), dspcntr);
5203 POSTING_READ(DSPCNTR(plane));
5204
94352cf9 5205 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5206
f564048e
EA		 5207 return ret;
5208}
5209
2fa2fe9a
DV		 5210static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5211 struct intel_crtc_config *pipe_config)
5212{
5213 struct drm_device *dev = crtc->base.dev;
5214 struct drm_i915_private *dev_priv = dev->dev_private;
5215 uint32_t tmp;
5216
5217 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5218 if (!(tmp & PFIT_ENABLE))
5219 return;
2fa2fe9a 5220
06922821 5221 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5222 if (INTEL_INFO(dev)->gen < 4) {
5223 if (crtc->pipe != PIPE_B)
5224 return;
2fa2fe9a
DV		 5225 } else {
5226 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5227 return;
5228 }
5229
06922821 5230 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5231 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5232 if (INTEL_INFO(dev)->gen < 5)
5233 pipe_config->gmch_pfit.lvds_border_bits =
5234 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5235}
5236
acbec814
JB		 5237static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5238 struct intel_crtc_config *pipe_config)
5239{
5240 struct drm_device *dev = crtc->base.dev;
5241 struct drm_i915_private *dev_priv = dev->dev_private;
5242 int pipe = pipe_config->cpu_transcoder;
5243 intel_clock_t clock;
5244 u32 mdiv;
662c6ecb 5245 int refclk = 100000;
acbec814
JB		 5246
5247 mutex_lock(&dev_priv->dpio_lock);
5248 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5249 mutex_unlock(&dev_priv->dpio_lock);
5250
5251 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5252 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5253 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5254 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5255 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5256
f646628b 5257 vlv_clock(refclk, &clock);
acbec814 5258
f646628b
VS		 5259 /* clock.dot is the fast clock */
5260 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 5261}
5262
0e8ffe1b
DV		 5263static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5264 struct intel_crtc_config *pipe_config)
5265{
5266 struct drm_device *dev = crtc->base.dev;
5267 struct drm_i915_private *dev_priv = dev->dev_private;
5268 uint32_t tmp;
5269
e143a21c 5270 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5271 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5272
0e8ffe1b
DV		 5273 tmp = I915_READ(PIPECONF(crtc->pipe));
5274 if (!(tmp & PIPECONF_ENABLE))
5275 return false;
5276
42571aef
VS		 5277 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5278 switch (tmp & PIPECONF_BPC_MASK) {
5279 case PIPECONF_6BPC:
5280 pipe_config->pipe_bpp = 18;
5281 break;
5282 case PIPECONF_8BPC:
5283 pipe_config->pipe_bpp = 24;
5284 break;
5285 case PIPECONF_10BPC:
5286 pipe_config->pipe_bpp = 30;
5287 break;
5288 default:
5289 break;
5290 }
5291 }
5292
282740f7
VS		 5293 if (INTEL_INFO(dev)->gen < 4)
5294 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5295
1bd1bd80
DV		 5296 intel_get_pipe_timings(crtc, pipe_config);
5297
2fa2fe9a
DV		 5298 i9xx_get_pfit_config(crtc, pipe_config);
5299
6c49f241
DV		 5300 if (INTEL_INFO(dev)->gen >= 4) {
5301 tmp = I915_READ(DPLL_MD(crtc->pipe));
5302 pipe_config->pixel_multiplier =
5303 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5304 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5305 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5306 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5307 tmp = I915_READ(DPLL(crtc->pipe));
5308 pipe_config->pixel_multiplier =
5309 ((tmp & SDVO_MULTIPLIER_MASK)
5310 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5311 } else {
5312 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5313 * port and will be fixed up in the encoder->get_config
5314 * function. */
5315 pipe_config->pixel_multiplier = 1;
5316 }
8bcc2795
DV		 5317 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5318 if (!IS_VALLEYVIEW(dev)) {
5319 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5320 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5321 } else {
5322 /* Mask out read-only status bits. */
5323 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5324 DPLL_PORTC_READY_MASK |
5325 DPLL_PORTB_READY_MASK);
8bcc2795 5326 }
6c49f241 5327
acbec814
JB		 5328 if (IS_VALLEYVIEW(dev))
5329 vlv_crtc_clock_get(crtc, pipe_config);
5330 else
5331 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5332
0e8ffe1b
DV		 5333 return true;
5334}
5335
dde86e2d 5336static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5337{
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5340 struct intel_encoder *encoder;
74cfd7ac 5341 u32 val, final;
13d83a67 5342 bool has_lvds = false;
199e5d79 5343 bool has_cpu_edp = false;
199e5d79 5344 bool has_panel = false;
99eb6a01
KP		 5345 bool has_ck505 = false;
5346 bool can_ssc = false;
13d83a67
JB		 5347
5348 /* We need to take the global config into account */
199e5d79
KP		 5349 list_for_each_entry(encoder, &mode_config->encoder_list,
5350 base.head) {
5351 switch (encoder->type) {
5352 case INTEL_OUTPUT_LVDS:
5353 has_panel = true;
5354 has_lvds = true;
5355 break;
5356 case INTEL_OUTPUT_EDP:
5357 has_panel = true;
2de6905f 5358 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5359 has_cpu_edp = true;
5360 break;
13d83a67
JB		 5361 }
5362 }
5363
99eb6a01 5364 if (HAS_PCH_IBX(dev)) {
41aa3448 5365 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5366 can_ssc = has_ck505;
5367 } else {
5368 has_ck505 = false;
5369 can_ssc = true;
5370 }
5371
2de6905f
ID		 5372 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5373 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5374
5375 /* Ironlake: try to setup display ref clock before DPLL
5376 * enabling. This is only under driver's control after
5377 * PCH B stepping, previous chipset stepping should be
5378 * ignoring this setting.
5379 */
74cfd7ac
CW		 5380 val = I915_READ(PCH_DREF_CONTROL);
5381
5382 /* As we must carefully and slowly disable/enable each source in turn,
5383 * compute the final state we want first and check if we need to
5384 * make any changes at all.
5385 */
5386 final = val;
5387 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5388 if (has_ck505)
5389 final |= DREF_NONSPREAD_CK505_ENABLE;
5390 else
5391 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5392
5393 final &= ~DREF_SSC_SOURCE_MASK;
5394 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5395 final &= ~DREF_SSC1_ENABLE;
5396
5397 if (has_panel) {
5398 final |= DREF_SSC_SOURCE_ENABLE;
5399
5400 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5401 final |= DREF_SSC1_ENABLE;
5402
5403 if (has_cpu_edp) {
5404 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5405 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5406 else
5407 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5408 } else
5409 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5410 } else {
5411 final |= DREF_SSC_SOURCE_DISABLE;
5412 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5413 }
5414
5415 if (final == val)
5416 return;
5417
13d83a67 5418 /* Always enable nonspread source */
74cfd7ac 5419 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5420
99eb6a01 5421 if (has_ck505)
74cfd7ac 5422 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5423 else
74cfd7ac 5424 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5425
199e5d79 5426 if (has_panel) {
74cfd7ac
CW		 5427 val &= ~DREF_SSC_SOURCE_MASK;
5428 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5429
199e5d79 5430 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5431 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5432 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5433 val |= DREF_SSC1_ENABLE;
e77166b5 5434 } else
74cfd7ac 5435 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5436
5437 /* Get SSC going before enabling the outputs */
74cfd7ac 5438 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5439 POSTING_READ(PCH_DREF_CONTROL);
5440 udelay(200);
5441
74cfd7ac 5442 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5443
5444 /* Enable CPU source on CPU attached eDP */
199e5d79 5445 if (has_cpu_edp) {
99eb6a01 5446 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5447 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5448 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5449 }
13d83a67 5450 else
74cfd7ac 5451 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5452 } else
74cfd7ac 5453 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5454
74cfd7ac 5455 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5456 POSTING_READ(PCH_DREF_CONTROL);
5457 udelay(200);
5458 } else {
5459 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5460
74cfd7ac 5461 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5462
5463 /* Turn off CPU output */
74cfd7ac 5464 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5465
74cfd7ac 5466 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5467 POSTING_READ(PCH_DREF_CONTROL);
5468 udelay(200);
5469
5470 /* Turn off the SSC source */
74cfd7ac
CW		 5471 val &= ~DREF_SSC_SOURCE_MASK;
5472 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5473
5474 /* Turn off SSC1 */
74cfd7ac 5475 val &= ~DREF_SSC1_ENABLE;
199e5d79 5476
74cfd7ac 5477 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5478 POSTING_READ(PCH_DREF_CONTROL);
5479 udelay(200);
5480 }
74cfd7ac
CW		 5481
5482 BUG_ON(val != final);
13d83a67
JB		 5483}
5484
f31f2d55 5485static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5486{
f31f2d55 5487 uint32_t tmp;
dde86e2d 5488
0ff066a9
PZ		 5489 tmp = I915_READ(SOUTH_CHICKEN2);
5490 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5491 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5492
0ff066a9
PZ		 5493 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5494 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5495 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5496
0ff066a9
PZ		 5497 tmp = I915_READ(SOUTH_CHICKEN2);
5498 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5499 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5500
0ff066a9
PZ		 5501 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5502 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5503 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5504}
5505
5506/* WaMPhyProgramming:hsw */
5507static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5508{
5509 uint32_t tmp;
dde86e2d
PZ		 5510
5511 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5512 tmp &= ~(0xFF << 24);
5513 tmp |= (0x12 << 24);
5514 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5515
dde86e2d
PZ		 5516 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5517 tmp |= (1 << 11);
5518 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5519
5520 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5521 tmp |= (1 << 11);
5522 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5523
dde86e2d
PZ		 5524 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5525 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5526 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5527
5528 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5529 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5530 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5531
0ff066a9
PZ		 5532 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5533 tmp &= ~(7 << 13);
5534 tmp |= (5 << 13);
5535 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5536
0ff066a9
PZ		 5537 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5538 tmp &= ~(7 << 13);
5539 tmp |= (5 << 13);
5540 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5541
5542 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5543 tmp &= ~0xFF;
5544 tmp |= 0x1C;
5545 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5546
5547 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5548 tmp &= ~0xFF;
5549 tmp |= 0x1C;
5550 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5551
5552 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5553 tmp &= ~(0xFF << 16);
5554 tmp |= (0x1C << 16);
5555 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5556
5557 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5558 tmp &= ~(0xFF << 16);
5559 tmp |= (0x1C << 16);
5560 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5561
0ff066a9
PZ		 5562 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5563 tmp |= (1 << 27);
5564 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5565
0ff066a9
PZ		 5566 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5567 tmp |= (1 << 27);
5568 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5569
0ff066a9
PZ		 5570 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5571 tmp &= ~(0xF << 28);
5572 tmp |= (4 << 28);
5573 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5574
0ff066a9
PZ		 5575 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5576 tmp &= ~(0xF << 28);
5577 tmp |= (4 << 28);
5578 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5579}
5580
2fa86a1f
PZ		 5581/* Implements 3 different sequences from BSpec chapter "Display iCLK
5582 * Programming" based on the parameters passed:
5583 * - Sequence to enable CLKOUT_DP
5584 * - Sequence to enable CLKOUT_DP without spread
5585 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5586 */
5587static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5588 bool with_fdi)
f31f2d55
PZ		 5589{
5590 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5591 uint32_t reg, tmp;
5592
5593 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5594 with_spread = true;
5595 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5596 with_fdi, "LP PCH doesn't have FDI\n"))
5597 with_fdi = false;
f31f2d55
PZ		 5598
5599 mutex_lock(&dev_priv->dpio_lock);
5600
5601 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5602 tmp &= ~SBI_SSCCTL_DISABLE;
5603 tmp |= SBI_SSCCTL_PATHALT;
5604 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5605
5606 udelay(24);
5607
2fa86a1f
PZ		 5608 if (with_spread) {
5609 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5610 tmp &= ~SBI_SSCCTL_PATHALT;
5611 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5612
2fa86a1f
PZ		 5613 if (with_fdi) {
5614 lpt_reset_fdi_mphy(dev_priv);
5615 lpt_program_fdi_mphy(dev_priv);
5616 }
5617 }
dde86e2d 5618
2fa86a1f
PZ		 5619 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5620 SBI_GEN0 : SBI_DBUFF0;
5621 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5622 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5623 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5624
5625 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5626}
5627
47701c3b
PZ		 5628/* Sequence to disable CLKOUT_DP */
5629static void lpt_disable_clkout_dp(struct drm_device *dev)
5630{
5631 struct drm_i915_private *dev_priv = dev->dev_private;
5632 uint32_t reg, tmp;
5633
5634 mutex_lock(&dev_priv->dpio_lock);
5635
5636 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5637 SBI_GEN0 : SBI_DBUFF0;
5638 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5639 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5640 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5641
5642 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5643 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5644 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5645 tmp |= SBI_SSCCTL_PATHALT;
5646 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5647 udelay(32);
5648 }
5649 tmp |= SBI_SSCCTL_DISABLE;
5650 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5651 }
5652
5653 mutex_unlock(&dev_priv->dpio_lock);
5654}
5655
bf8fa3d3
PZ		 5656static void lpt_init_pch_refclk(struct drm_device *dev)
5657{
5658 struct drm_mode_config *mode_config = &dev->mode_config;
5659 struct intel_encoder *encoder;
5660 bool has_vga = false;
5661
5662 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5663 switch (encoder->type) {
5664 case INTEL_OUTPUT_ANALOG:
5665 has_vga = true;
5666 break;
5667 }
5668 }
5669
47701c3b
PZ		 5670 if (has_vga)
5671 lpt_enable_clkout_dp(dev, true, true);
5672 else
5673 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5674}
5675
dde86e2d
PZ		 5676/*
5677 * Initialize reference clocks when the driver loads
5678 */
5679void intel_init_pch_refclk(struct drm_device *dev)
5680{
5681 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5682 ironlake_init_pch_refclk(dev);
5683 else if (HAS_PCH_LPT(dev))
5684 lpt_init_pch_refclk(dev);
5685}
5686
d9d444cb
JB		 5687static int ironlake_get_refclk(struct drm_crtc *crtc)
5688{
5689 struct drm_device *dev = crtc->dev;
5690 struct drm_i915_private *dev_priv = dev->dev_private;
5691 struct intel_encoder *encoder;
d9d444cb
JB		 5692 int num_connectors = 0;
5693 bool is_lvds = false;
5694
6c2b7c12 5695 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5696 switch (encoder->type) {
5697 case INTEL_OUTPUT_LVDS:
5698 is_lvds = true;
5699 break;
d9d444cb
JB		 5700 }
5701 num_connectors++;
5702 }
5703
5704 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5705 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5706 dev_priv->vbt.lvds_ssc_freq);
5707 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5708 }
5709
5710 return 120000;
5711}
5712
6ff93609 5713static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5714{
c8203565 5715 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5717 int pipe = intel_crtc->pipe;
c8203565
PZ		 5718 uint32_t val;
5719
78114071 5720 val = 0;
c8203565 5721
965e0c48 5722 switch (intel_crtc->config.pipe_bpp) {
c8203565 5723 case 18:
dfd07d72 5724 val |= PIPECONF_6BPC;
c8203565
PZ		 5725 break;
5726 case 24:
dfd07d72 5727 val |= PIPECONF_8BPC;
c8203565
PZ		 5728 break;
5729 case 30:
dfd07d72 5730 val |= PIPECONF_10BPC;
c8203565
PZ		 5731 break;
5732 case 36:
dfd07d72 5733 val |= PIPECONF_12BPC;
c8203565
PZ		 5734 break;
5735 default:
cc769b62
PZ		 5736 /* Case prevented by intel_choose_pipe_bpp_dither. */
5737 BUG();
c8203565
PZ		 5738 }
5739
d8b32247 5740 if (intel_crtc->config.dither)
c8203565
PZ		 5741 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5742
6ff93609 5743 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5744 val |= PIPECONF_INTERLACED_ILK;
5745 else
5746 val |= PIPECONF_PROGRESSIVE;
5747
50f3b016 5748 if (intel_crtc->config.limited_color_range)
3685a8f3 5749 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5750
c8203565
PZ		 5751 I915_WRITE(PIPECONF(pipe), val);
5752 POSTING_READ(PIPECONF(pipe));
5753}
5754
86d3efce
VS		 5755/*
5756 * Set up the pipe CSC unit.
5757 *
5758 * Currently only full range RGB to limited range RGB conversion
5759 * is supported, but eventually this should handle various
5760 * RGB<->YCbCr scenarios as well.
5761 */
50f3b016 5762static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5763{
5764 struct drm_device *dev = crtc->dev;
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5767 int pipe = intel_crtc->pipe;
5768 uint16_t coeff = 0x7800; /* 1.0 */
5769
5770 /*
5771 * TODO: Check what kind of values actually come out of the pipe
5772 * with these coeff/postoff values and adjust to get the best
5773 * accuracy. Perhaps we even need to take the bpc value into
5774 * consideration.
5775 */
5776
50f3b016 5777 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5778 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5779
5780 /*
5781 * GY/GU and RY/RU should be the other way around according
5782 * to BSpec, but reality doesn't agree. Just set them up in
5783 * a way that results in the correct picture.
5784 */
5785 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5786 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5787
5788 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5789 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5790
5791 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5792 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5793
5794 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5795 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5796 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5797
5798 if (INTEL_INFO(dev)->gen > 6) {
5799 uint16_t postoff = 0;
5800
50f3b016 5801 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5802 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5803
5804 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5805 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5806 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5807
5808 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5809 } else {
5810 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5811
50f3b016 5812 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5813 mode |= CSC_BLACK_SCREEN_OFFSET;
5814
5815 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5816 }
5817}
5818
6ff93609 5819static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5820{
5821 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5823 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5824 uint32_t val;
5825
3eff4faa 5826 val = 0;
ee2b0b38 5827
d8b32247 5828 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5829 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5830
6ff93609 5831 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5832 val |= PIPECONF_INTERLACED_ILK;
5833 else
5834 val |= PIPECONF_PROGRESSIVE;
5835
702e7a56
PZ		 5836 I915_WRITE(PIPECONF(cpu_transcoder), val);
5837 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5838
5839 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5840 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5841}
5842
6591c6e4 5843static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5844 intel_clock_t *clock,
5845 bool *has_reduced_clock,
5846 intel_clock_t *reduced_clock)
5847{
5848 struct drm_device *dev = crtc->dev;
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5850 struct intel_encoder *intel_encoder;
5851 int refclk;
d4906093 5852 const intel_limit_t *limit;
a16af721 5853 bool ret, is_lvds = false;
79e53945 5854
6591c6e4
PZ		 5855 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5856 switch (intel_encoder->type) {
79e53945
JB		 5857 case INTEL_OUTPUT_LVDS:
5858 is_lvds = true;
5859 break;
79e53945
JB		 5860 }
5861 }
5862
d9d444cb 5863 refclk = ironlake_get_refclk(crtc);
79e53945 5864
d4906093
ML		 5865 /*
5866 * Returns a set of divisors for the desired target clock with the given
5867 * refclk, or FALSE. The returned values represent the clock equation:
5868 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5869 */
1b894b59 5870 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5871 ret = dev_priv->display.find_dpll(limit, crtc,
5872 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5873 refclk, NULL, clock);
6591c6e4
PZ		 5874 if (!ret)
5875 return false;
cda4b7d3 5876
ddc9003c 5877 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5878 /*
5879 * Ensure we match the reduced clock's P to the target clock.
5880 * If the clocks don't match, we can't switch the display clock
5881 * by using the FP0/FP1. In such case we will disable the LVDS
5882 * downclock feature.
5883 */
ee9300bb
DV		 5884 *has_reduced_clock =
5885 dev_priv->display.find_dpll(limit, crtc,
5886 dev_priv->lvds_downclock,
5887 refclk, clock,
5888 reduced_clock);
652c393a 5889 }
61e9653f 5890
6591c6e4
PZ		 5891 return true;
5892}
5893
d4b1931c
PZ		 5894int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5895{
5896 /*
5897 * Account for spread spectrum to avoid
5898 * oversubscribing the link. Max center spread
5899 * is 2.5%; use 5% for safety's sake.
5900 */
5901 u32 bps = target_clock * bpp * 21 / 20;
5902 return bps / (link_bw * 8) + 1;
5903}
5904
7429e9d4 5905static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5906{
7429e9d4 5907 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5908}
5909
de13a2e3 5910static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5911 u32 *fp,
9a7c7890 5912 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5913{
de13a2e3 5914 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5915 struct drm_device *dev = crtc->dev;
5916 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5917 struct intel_encoder *intel_encoder;
5918 uint32_t dpll;
6cc5f341 5919 int factor, num_connectors = 0;
09ede541 5920 bool is_lvds = false, is_sdvo = false;
79e53945 5921
de13a2e3
PZ		 5922 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5923 switch (intel_encoder->type) {
79e53945
JB		 5924 case INTEL_OUTPUT_LVDS:
5925 is_lvds = true;
5926 break;
5927 case INTEL_OUTPUT_SDVO:
7d57382e 5928 case INTEL_OUTPUT_HDMI:
79e53945 5929 is_sdvo = true;
79e53945 5930 break;
79e53945 5931 }
43565a06 5932
c751ce4f 5933 num_connectors++;
79e53945 5934 }
79e53945 5935
c1858123 5936 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5937 factor = 21;
5938 if (is_lvds) {
5939 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5940 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5941 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5942 factor = 25;
09ede541 5943 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5944 factor = 20;
c1858123 5945
7429e9d4 5946 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5947 *fp |= FP_CB_TUNE;
2c07245f 5948
9a7c7890
DV		 5949 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5950 *fp2 |= FP_CB_TUNE;
5951
5eddb70b 5952 dpll = 0;
2c07245f 5953
a07d6787
EA		 5954 if (is_lvds)
5955 dpll |= DPLLB_MODE_LVDS;
5956 else
5957 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5958
ef1b460d
DV		 5959 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5960 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5961
5962 if (is_sdvo)
4a33e48d 5963 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5964 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5965 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5966
a07d6787 5967 /* compute bitmask from p1 value */
7429e9d4 5968 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5969 /* also FPA1 */
7429e9d4 5970 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5971
7429e9d4 5972 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5973 case 5:
5974 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5975 break;
5976 case 7:
5977 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5978 break;
5979 case 10:
5980 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5981 break;
5982 case 14:
5983 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5984 break;
79e53945
JB		 5985 }
5986
b4c09f3b 5987 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5988 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5989 else
5990 dpll |= PLL_REF_INPUT_DREFCLK;
5991
959e16d6 5992 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5993}
5994
5995static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5996 int x, int y,
5997 struct drm_framebuffer *fb)
5998{
5999 struct drm_device *dev = crtc->dev;
6000 struct drm_i915_private *dev_priv = dev->dev_private;
6001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6002 int pipe = intel_crtc->pipe;
6003 int plane = intel_crtc->plane;
6004 int num_connectors = 0;
6005 intel_clock_t clock, reduced_clock;
cbbab5bd 6006 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 6007 bool ok, has_reduced_clock = false;
8b47047b 6008 bool is_lvds = false;
de13a2e3 6009 struct intel_encoder *encoder;
e2b78267 6010 struct intel_shared_dpll *pll;
de13a2e3 6011 int ret;
de13a2e3
PZ		 6012
6013 for_each_encoder_on_crtc(dev, crtc, encoder) {
6014 switch (encoder->type) {
6015 case INTEL_OUTPUT_LVDS:
6016 is_lvds = true;
6017 break;
de13a2e3
PZ		 6018 }
6019
6020 num_connectors++;
a07d6787 6021 }
79e53945 6022
5dc5298b
PZ		 6023 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6024 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 6025
ff9a6750 6026 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 6027 &has_reduced_clock, &reduced_clock);
ee9300bb 6028 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 6029 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6030 return -EINVAL;
79e53945 6031 }
f47709a9
DV		 6032 /* Compat-code for transition, will disappear. */
6033 if (!intel_crtc->config.clock_set) {
6034 intel_crtc->config.dpll.n = clock.n;
6035 intel_crtc->config.dpll.m1 = clock.m1;
6036 intel_crtc->config.dpll.m2 = clock.m2;
6037 intel_crtc->config.dpll.p1 = clock.p1;
6038 intel_crtc->config.dpll.p2 = clock.p2;
6039 }
79e53945 6040
5dc5298b 6041 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 6042 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 6043 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 6044 if (has_reduced_clock)
7429e9d4 6045 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 6046
7429e9d4 6047 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 6048 &fp, &reduced_clock,
6049 has_reduced_clock ? &fp2 : NULL);
6050
959e16d6 6051 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 6052 intel_crtc->config.dpll_hw_state.fp0 = fp;
6053 if (has_reduced_clock)
6054 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6055 else
6056 intel_crtc->config.dpll_hw_state.fp1 = fp;
6057
b89a1d39 6058 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 6059 if (pll == NULL) {
84f44ce7
VS		 6060 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6061 pipe_name(pipe));
4b645f14
JB		 6062 return -EINVAL;
6063 }
ee7b9f93 6064 } else
e72f9fbf 6065 intel_put_shared_dpll(intel_crtc);
79e53945 6066
03afc4a2
DV		 6067 if (intel_crtc->config.has_dp_encoder)
6068 intel_dp_set_m_n(intel_crtc);
79e53945 6069
bcd644e0
DV		 6070 if (is_lvds && has_reduced_clock && i915_powersave)
6071 intel_crtc->lowfreq_avail = true;
6072 else
6073 intel_crtc->lowfreq_avail = false;
e2b78267 6074
8a654f3b 6075 intel_set_pipe_timings(intel_crtc);
5eddb70b 6076
ca3a0ff8 6077 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6078 intel_cpu_transcoder_set_m_n(intel_crtc,
6079 &intel_crtc->config.fdi_m_n);
6080 }
2c07245f 6081
6ff93609 6082 ironlake_set_pipeconf(crtc);
79e53945 6083
a1f9e77e
PZ		 6084 /* Set up the display plane register */
6085 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6086 POSTING_READ(DSPCNTR(plane));
79e53945 6087
94352cf9 6088 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6089
1857e1da 6090 return ret;
79e53945
JB		 6091}
6092
eb14cb74
VS		 6093static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6094 struct intel_link_m_n *m_n)
6095{
6096 struct drm_device *dev = crtc->base.dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098 enum pipe pipe = crtc->pipe;
6099
6100 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6101 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6102 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6103 & ~TU_SIZE_MASK;
6104 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6105 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6106 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6107}
6108
6109static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6110 enum transcoder transcoder,
6111 struct intel_link_m_n *m_n)
72419203
DV		 6112{
6113 struct drm_device *dev = crtc->base.dev;
6114 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6115 enum pipe pipe = crtc->pipe;
72419203 6116
eb14cb74
VS		 6117 if (INTEL_INFO(dev)->gen >= 5) {
6118 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6119 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6120 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6121 & ~TU_SIZE_MASK;
6122 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6123 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6124 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6125 } else {
6126 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6127 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6128 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6129 & ~TU_SIZE_MASK;
6130 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6131 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6132 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6133 }
6134}
6135
6136void intel_dp_get_m_n(struct intel_crtc *crtc,
6137 struct intel_crtc_config *pipe_config)
6138{
6139 if (crtc->config.has_pch_encoder)
6140 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6141 else
6142 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6143 &pipe_config->dp_m_n);
6144}
72419203 6145
eb14cb74
VS		 6146static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6147 struct intel_crtc_config *pipe_config)
6148{
6149 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6150 &pipe_config->fdi_m_n);
72419203
DV		 6151}
6152
2fa2fe9a
DV		 6153static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6154 struct intel_crtc_config *pipe_config)
6155{
6156 struct drm_device *dev = crtc->base.dev;
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158 uint32_t tmp;
6159
6160 tmp = I915_READ(PF_CTL(crtc->pipe));
6161
6162 if (tmp & PF_ENABLE) {
fd4daa9c 6163 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6164 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6165 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6166
6167 /* We currently do not free assignements of panel fitters on
6168 * ivb/hsw (since we don't use the higher upscaling modes which
6169 * differentiates them) so just WARN about this case for now. */
6170 if (IS_GEN7(dev)) {
6171 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6172 PF_PIPE_SEL_IVB(crtc->pipe));
6173 }
2fa2fe9a 6174 }
79e53945
JB		 6175}
6176
0e8ffe1b
DV		 6177static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6178 struct intel_crtc_config *pipe_config)
6179{
6180 struct drm_device *dev = crtc->base.dev;
6181 struct drm_i915_private *dev_priv = dev->dev_private;
6182 uint32_t tmp;
6183
e143a21c 6184 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6185 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6186
0e8ffe1b
DV		 6187 tmp = I915_READ(PIPECONF(crtc->pipe));
6188 if (!(tmp & PIPECONF_ENABLE))
6189 return false;
6190
42571aef
VS		 6191 switch (tmp & PIPECONF_BPC_MASK) {
6192 case PIPECONF_6BPC:
6193 pipe_config->pipe_bpp = 18;
6194 break;
6195 case PIPECONF_8BPC:
6196 pipe_config->pipe_bpp = 24;
6197 break;
6198 case PIPECONF_10BPC:
6199 pipe_config->pipe_bpp = 30;
6200 break;
6201 case PIPECONF_12BPC:
6202 pipe_config->pipe_bpp = 36;
6203 break;
6204 default:
6205 break;
6206 }
6207
ab9412ba 6208 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6209 struct intel_shared_dpll *pll;
6210
88adfff1
DV		 6211 pipe_config->has_pch_encoder = true;
6212
627eb5a3
DV		 6213 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6214 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6215 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6216
6217 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6218
c0d43d62 6219 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6220 pipe_config->shared_dpll =
6221 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6222 } else {
6223 tmp = I915_READ(PCH_DPLL_SEL);
6224 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6225 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6226 else
6227 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6228 }
66e985c0
DV		 6229
6230 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6231
6232 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6233 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6234
6235 tmp = pipe_config->dpll_hw_state.dpll;
6236 pipe_config->pixel_multiplier =
6237 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6238 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6239
6240 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6241 } else {
6242 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6243 }
6244
1bd1bd80
DV		 6245 intel_get_pipe_timings(crtc, pipe_config);
6246
2fa2fe9a
DV		 6247 ironlake_get_pfit_config(crtc, pipe_config);
6248
0e8ffe1b
DV		 6249 return true;
6250}
6251
be256dc7
PZ		 6252static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6253{
6254 struct drm_device *dev = dev_priv->dev;
6255 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6256 struct intel_crtc *crtc;
6257 unsigned long irqflags;
bd633a7c 6258 uint32_t val;
be256dc7
PZ		 6259
6260 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6261 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6262 pipe_name(crtc->pipe));
6263
6264 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6265 WARN(plls->spll_refcount, "SPLL enabled\n");
6266 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6267 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6268 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6269 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6270 "CPU PWM1 enabled\n");
6271 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6272 "CPU PWM2 enabled\n");
6273 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6274 "PCH PWM1 enabled\n");
6275 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6276 "Utility pin enabled\n");
6277 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6278
6279 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6280 val = I915_READ(DEIMR);
6281 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6282 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6283 val = I915_READ(SDEIMR);
bd633a7c 6284 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6285 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6286 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6287}
6288
6289/*
6290 * This function implements pieces of two sequences from BSpec:
6291 * - Sequence for display software to disable LCPLL
6292 * - Sequence for display software to allow package C8+
6293 * The steps implemented here are just the steps that actually touch the LCPLL
6294 * register. Callers should take care of disabling all the display engine
6295 * functions, doing the mode unset, fixing interrupts, etc.
6296 */
6ff58d53
PZ		 6297static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6298 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6299{
6300 uint32_t val;
6301
6302 assert_can_disable_lcpll(dev_priv);
6303
6304 val = I915_READ(LCPLL_CTL);
6305
6306 if (switch_to_fclk) {
6307 val |= LCPLL_CD_SOURCE_FCLK;
6308 I915_WRITE(LCPLL_CTL, val);
6309
6310 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6311 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6312 DRM_ERROR("Switching to FCLK failed\n");
6313
6314 val = I915_READ(LCPLL_CTL);
6315 }
6316
6317 val |= LCPLL_PLL_DISABLE;
6318 I915_WRITE(LCPLL_CTL, val);
6319 POSTING_READ(LCPLL_CTL);
6320
6321 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6322 DRM_ERROR("LCPLL still locked\n");
6323
6324 val = I915_READ(D_COMP);
6325 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6326 mutex_lock(&dev_priv->rps.hw_lock);
6327 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6328 DRM_ERROR("Failed to disable D_COMP\n");
6329 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6330 POSTING_READ(D_COMP);
6331 ndelay(100);
6332
6333 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6334 DRM_ERROR("D_COMP RCOMP still in progress\n");
6335
6336 if (allow_power_down) {
6337 val = I915_READ(LCPLL_CTL);
6338 val |= LCPLL_POWER_DOWN_ALLOW;
6339 I915_WRITE(LCPLL_CTL, val);
6340 POSTING_READ(LCPLL_CTL);
6341 }
6342}
6343
6344/*
6345 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6346 * source.
6347 */
6ff58d53 6348static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6349{
6350 uint32_t val;
6351
6352 val = I915_READ(LCPLL_CTL);
6353
6354 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6355 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6356 return;
6357
215733fa
PZ		 6358 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6359 * we'll hang the machine! */
6360 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6361
be256dc7
PZ		 6362 if (val & LCPLL_POWER_DOWN_ALLOW) {
6363 val &= ~LCPLL_POWER_DOWN_ALLOW;
6364 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6365 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6366 }
6367
6368 val = I915_READ(D_COMP);
6369 val |= D_COMP_COMP_FORCE;
6370 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6371 mutex_lock(&dev_priv->rps.hw_lock);
6372 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6373 DRM_ERROR("Failed to enable D_COMP\n");
6374 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6375 POSTING_READ(D_COMP);
be256dc7
PZ		 6376
6377 val = I915_READ(LCPLL_CTL);
6378 val &= ~LCPLL_PLL_DISABLE;
6379 I915_WRITE(LCPLL_CTL, val);
6380
6381 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6382 DRM_ERROR("LCPLL not locked yet\n");
6383
6384 if (val & LCPLL_CD_SOURCE_FCLK) {
6385 val = I915_READ(LCPLL_CTL);
6386 val &= ~LCPLL_CD_SOURCE_FCLK;
6387 I915_WRITE(LCPLL_CTL, val);
6388
6389 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6390 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6391 DRM_ERROR("Switching back to LCPLL failed\n");
6392 }
215733fa
PZ		 6393
6394 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6395}
6396
c67a470b
PZ		 6397void hsw_enable_pc8_work(struct work_struct *__work)
6398{
6399 struct drm_i915_private *dev_priv =
6400 container_of(to_delayed_work(__work), struct drm_i915_private,
6401 pc8.enable_work);
6402 struct drm_device *dev = dev_priv->dev;
6403 uint32_t val;
6404
6405 if (dev_priv->pc8.enabled)
6406 return;
6407
6408 DRM_DEBUG_KMS("Enabling package C8+\n");
6409
6410 dev_priv->pc8.enabled = true;
6411
6412 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6413 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6414 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6415 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6416 }
6417
6418 lpt_disable_clkout_dp(dev);
6419 hsw_pc8_disable_interrupts(dev);
6420 hsw_disable_lcpll(dev_priv, true, true);
6421}
6422
6423static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6424{
6425 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6426 WARN(dev_priv->pc8.disable_count < 1,
6427 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6428
6429 dev_priv->pc8.disable_count--;
6430 if (dev_priv->pc8.disable_count != 0)
6431 return;
6432
6433 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6434 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6435}
6436
6437static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6438{
6439 struct drm_device *dev = dev_priv->dev;
6440 uint32_t val;
6441
6442 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6443 WARN(dev_priv->pc8.disable_count < 0,
6444 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6445
6446 dev_priv->pc8.disable_count++;
6447 if (dev_priv->pc8.disable_count != 1)
6448 return;
6449
6450 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6451 if (!dev_priv->pc8.enabled)
6452 return;
6453
6454 DRM_DEBUG_KMS("Disabling package C8+\n");
6455
6456 hsw_restore_lcpll(dev_priv);
6457 hsw_pc8_restore_interrupts(dev);
6458 lpt_init_pch_refclk(dev);
6459
6460 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6461 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6462 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6463 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6464 }
6465
6466 intel_prepare_ddi(dev);
6467 i915_gem_init_swizzling(dev);
6468 mutex_lock(&dev_priv->rps.hw_lock);
6469 gen6_update_ring_freq(dev);
6470 mutex_unlock(&dev_priv->rps.hw_lock);
6471 dev_priv->pc8.enabled = false;
6472}
6473
6474void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6475{
6476 mutex_lock(&dev_priv->pc8.lock);
6477 __hsw_enable_package_c8(dev_priv);
6478 mutex_unlock(&dev_priv->pc8.lock);
6479}
6480
6481void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6482{
6483 mutex_lock(&dev_priv->pc8.lock);
6484 __hsw_disable_package_c8(dev_priv);
6485 mutex_unlock(&dev_priv->pc8.lock);
6486}
6487
6488static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6489{
6490 struct drm_device *dev = dev_priv->dev;
6491 struct intel_crtc *crtc;
6492 uint32_t val;
6493
6494 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6495 if (crtc->base.enabled)
6496 return false;
6497
6498 /* This case is still possible since we have the i915.disable_power_well
6499 * parameter and also the KVMr or something else might be requesting the
6500 * power well. */
6501 val = I915_READ(HSW_PWR_WELL_DRIVER);
6502 if (val != 0) {
6503 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6504 return false;
6505 }
6506
6507 return true;
6508}
6509
6510/* Since we're called from modeset_global_resources there's no way to
6511 * symmetrically increase and decrease the refcount, so we use
6512 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6513 * or not.
6514 */
6515static void hsw_update_package_c8(struct drm_device *dev)
6516{
6517 struct drm_i915_private *dev_priv = dev->dev_private;
6518 bool allow;
6519
6520 if (!i915_enable_pc8)
6521 return;
6522
6523 mutex_lock(&dev_priv->pc8.lock);
6524
6525 allow = hsw_can_enable_package_c8(dev_priv);
6526
6527 if (allow == dev_priv->pc8.requirements_met)
6528 goto done;
6529
6530 dev_priv->pc8.requirements_met = allow;
6531
6532 if (allow)
6533 __hsw_enable_package_c8(dev_priv);
6534 else
6535 __hsw_disable_package_c8(dev_priv);
6536
6537done:
6538 mutex_unlock(&dev_priv->pc8.lock);
6539}
6540
6541static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6542{
6543 if (!dev_priv->pc8.gpu_idle) {
6544 dev_priv->pc8.gpu_idle = true;
6545 hsw_enable_package_c8(dev_priv);
6546 }
6547}
6548
6549static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6550{
6551 if (dev_priv->pc8.gpu_idle) {
6552 dev_priv->pc8.gpu_idle = false;
6553 hsw_disable_package_c8(dev_priv);
6554 }
be256dc7
PZ		 6555}
6556
6efdf354
ID		 6557#define for_each_power_domain(domain, mask) \
6558 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6559 if ((1 << (domain)) & (mask))
6560
6561static unsigned long get_pipe_power_domains(struct drm_device *dev,
6562 enum pipe pipe, bool pfit_enabled)
6563{
6564 unsigned long mask;
6565 enum transcoder transcoder;
6566
6567 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6568
6569 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6570 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6571 if (pfit_enabled)
6572 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6573
6574 return mask;
6575}
6576
baa70707
ID		 6577void intel_display_set_init_power(struct drm_device *dev, bool enable)
6578{
6579 struct drm_i915_private *dev_priv = dev->dev_private;
6580
6581 if (dev_priv->power_domains.init_power_on == enable)
6582 return;
6583
6584 if (enable)
6585 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6586 else
6587 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6588
6589 dev_priv->power_domains.init_power_on = enable;
6590}
6591
4f074129 6592static void modeset_update_power_wells(struct drm_device *dev)
d6dd9eb1 6593{
6efdf354 6594 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
d6dd9eb1 6595 struct intel_crtc *crtc;
d6dd9eb1 6596
6efdf354
ID		 6597 /*
6598 * First get all needed power domains, then put all unneeded, to avoid
6599 * any unnecessary toggling of the power wells.
6600 */
d6dd9eb1 6601 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6efdf354
ID		 6602 enum intel_display_power_domain domain;
6603
e7a639c4
DV		 6604 if (!crtc->base.enabled)
6605 continue;
d6dd9eb1 6606
6efdf354
ID		 6607 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6608 crtc->pipe,
6609 crtc->config.pch_pfit.enabled);
6610
6611 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6612 intel_display_power_get(dev, domain);
d6dd9eb1
DV		 6613 }
6614
6efdf354
ID		 6615 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6616 enum intel_display_power_domain domain;
6617
6618 for_each_power_domain(domain, crtc->enabled_power_domains)
6619 intel_display_power_put(dev, domain);
6620
6621 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6622 }
baa70707
ID		 6623
6624 intel_display_set_init_power(dev, false);
4f074129 6625}
c67a470b 6626
4f074129
ID		 6627static void haswell_modeset_global_resources(struct drm_device *dev)
6628{
6629 modeset_update_power_wells(dev);
c67a470b 6630 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6631}
6632
09b4ddf9 6633static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6634 int x, int y,
6635 struct drm_framebuffer *fb)
6636{
6637 struct drm_device *dev = crtc->dev;
6638 struct drm_i915_private *dev_priv = dev->dev_private;
6639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6640 int plane = intel_crtc->plane;
09b4ddf9 6641 int ret;
09b4ddf9 6642
ff9a6750 6643 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6644 return -EINVAL;
6645
03afc4a2
DV		 6646 if (intel_crtc->config.has_dp_encoder)
6647 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6648
6649 intel_crtc->lowfreq_avail = false;
09b4ddf9 6650
8a654f3b 6651 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6652
ca3a0ff8 6653 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6654 intel_cpu_transcoder_set_m_n(intel_crtc,
6655 &intel_crtc->config.fdi_m_n);
6656 }
09b4ddf9 6657
6ff93609 6658 haswell_set_pipeconf(crtc);
09b4ddf9 6659
50f3b016 6660 intel_set_pipe_csc(crtc);
86d3efce 6661
09b4ddf9 6662 /* Set up the display plane register */
86d3efce 6663 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6664 POSTING_READ(DSPCNTR(plane));
6665
6666 ret = intel_pipe_set_base(crtc, x, y, fb);
6667
1f803ee5 6668 return ret;
79e53945
JB		 6669}
6670
0e8ffe1b
DV		 6671static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6672 struct intel_crtc_config *pipe_config)
6673{
6674 struct drm_device *dev = crtc->base.dev;
6675 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6676 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6677 uint32_t tmp;
6678
e143a21c 6679 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6680 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6681
eccb140b
DV		 6682 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6683 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6684 enum pipe trans_edp_pipe;
6685 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6686 default:
6687 WARN(1, "unknown pipe linked to edp transcoder\n");
6688 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6689 case TRANS_DDI_EDP_INPUT_A_ON:
6690 trans_edp_pipe = PIPE_A;
6691 break;
6692 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6693 trans_edp_pipe = PIPE_B;
6694 break;
6695 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6696 trans_edp_pipe = PIPE_C;
6697 break;
6698 }
6699
6700 if (trans_edp_pipe == crtc->pipe)
6701 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6702 }
6703
b97186f0 6704 if (!intel_display_power_enabled(dev,
eccb140b 6705 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6706 return false;
6707
eccb140b 6708 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6709 if (!(tmp & PIPECONF_ENABLE))
6710 return false;
6711
88adfff1 6712 /*
f196e6be 6713 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6714 * DDI E. So just check whether this pipe is wired to DDI E and whether
6715 * the PCH transcoder is on.
6716 */
eccb140b 6717 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6718 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6719 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6720 pipe_config->has_pch_encoder = true;
6721
627eb5a3
DV		 6722 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6723 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6724 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6725
6726 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6727 }
6728
1bd1bd80
DV		 6729 intel_get_pipe_timings(crtc, pipe_config);
6730
2fa2fe9a
DV		 6731 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6732 if (intel_display_power_enabled(dev, pfit_domain))
6733 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6734
42db64ef
PZ		 6735 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6736 (I915_READ(IPS_CTL) & IPS_ENABLE);
6737
6c49f241
DV		 6738 pipe_config->pixel_multiplier = 1;
6739
0e8ffe1b
DV		 6740 return true;
6741}
6742
f564048e 6743static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6744 int x, int y,
94352cf9 6745 struct drm_framebuffer *fb)
f564048e
EA		 6746{
6747 struct drm_device *dev = crtc->dev;
6748 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6749 struct intel_encoder *encoder;
0b701d27 6750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6751 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6752 int pipe = intel_crtc->pipe;
f564048e
EA		 6753 int ret;
6754
0b701d27 6755 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6756
b8cecdf5
DV		 6757 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6758
79e53945 6759 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6760
9256aa19
DV		 6761 if (ret != 0)
6762 return ret;
6763
6764 for_each_encoder_on_crtc(dev, crtc, encoder) {
6765 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6766 encoder->base.base.id,
6767 drm_get_encoder_name(&encoder->base),
6768 mode->base.id, mode->name);
36f2d1f1 6769 encoder->mode_set(encoder);
9256aa19
DV		 6770 }
6771
6772 return 0;
79e53945
JB		 6773}
6774
1a91510d
JN		 6775static struct {
6776 int clock;
6777 u32 config;
6778} hdmi_audio_clock[] = {
6779 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
6780 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
6781 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
6782 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
6783 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
6784 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
6785 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
6786 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
6787 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
6788 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
6789};
6790
6791/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
6792static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
6793{
6794 int i;
6795
6796 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
6797 if (mode->clock == hdmi_audio_clock[i].clock)
6798 break;
6799 }
6800
6801 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
6802 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
6803 i = 1;
6804 }
6805
6806 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
6807 hdmi_audio_clock[i].clock,
6808 hdmi_audio_clock[i].config);
6809
6810 return hdmi_audio_clock[i].config;
6811}
6812
3a9627f4
WF		 6813static bool intel_eld_uptodate(struct drm_connector *connector,
6814 int reg_eldv, uint32_t bits_eldv,
6815 int reg_elda, uint32_t bits_elda,
6816 int reg_edid)
6817{
6818 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6819 uint8_t *eld = connector->eld;
6820 uint32_t i;
6821
6822 i = I915_READ(reg_eldv);
6823 i &= bits_eldv;
6824
6825 if (!eld[0])
6826 return !i;
6827
6828 if (!i)
6829 return false;
6830
6831 i = I915_READ(reg_elda);
6832 i &= ~bits_elda;
6833 I915_WRITE(reg_elda, i);
6834
6835 for (i = 0; i < eld[2]; i++)
6836 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6837 return false;
6838
6839 return true;
6840}
6841
e0dac65e 6842static void g4x_write_eld(struct drm_connector *connector,
34427052
JN		 6843 struct drm_crtc *crtc,
6844 struct drm_display_mode *mode)
e0dac65e
WF		 6845{
6846 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6847 uint8_t *eld = connector->eld;
6848 uint32_t eldv;
6849 uint32_t len;
6850 uint32_t i;
6851
6852 i = I915_READ(G4X_AUD_VID_DID);
6853
6854 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6855 eldv = G4X_ELDV_DEVCL_DEVBLC;
6856 else
6857 eldv = G4X_ELDV_DEVCTG;
6858
3a9627f4
WF		 6859 if (intel_eld_uptodate(connector,
6860 G4X_AUD_CNTL_ST, eldv,
6861 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6862 G4X_HDMIW_HDMIEDID))
6863 return;
6864
e0dac65e
WF		 6865 i = I915_READ(G4X_AUD_CNTL_ST);
6866 i &= ~(eldv | G4X_ELD_ADDR);
6867 len = (i >> 9) & 0x1f; /* ELD buffer size */
6868 I915_WRITE(G4X_AUD_CNTL_ST, i);
6869
6870 if (!eld[0])
6871 return;
6872
6873 len = min_t(uint8_t, eld[2], len);
6874 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6875 for (i = 0; i < len; i++)
6876 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6877
6878 i = I915_READ(G4X_AUD_CNTL_ST);
6879 i |= eldv;
6880 I915_WRITE(G4X_AUD_CNTL_ST, i);
6881}
6882
83358c85 6883static void haswell_write_eld(struct drm_connector *connector,
34427052
JN		 6884 struct drm_crtc *crtc,
6885 struct drm_display_mode *mode)
83358c85
WX		 6886{
6887 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6888 uint8_t *eld = connector->eld;
6889 struct drm_device *dev = crtc->dev;
7b9f35a6 6890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6891 uint32_t eldv;
6892 uint32_t i;
6893 int len;
6894 int pipe = to_intel_crtc(crtc)->pipe;
6895 int tmp;
6896
6897 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6898 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6899 int aud_config = HSW_AUD_CFG(pipe);
6900 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6901
6902
6903 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6904
6905 /* Audio output enable */
6906 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6907 tmp = I915_READ(aud_cntrl_st2);
6908 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6909 I915_WRITE(aud_cntrl_st2, tmp);
6910
6911 /* Wait for 1 vertical blank */
6912 intel_wait_for_vblank(dev, pipe);
6913
6914 /* Set ELD valid state */
6915 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6916 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6917 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6918 I915_WRITE(aud_cntrl_st2, tmp);
6919 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6920 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6921
6922 /* Enable HDMI mode */
6923 tmp = I915_READ(aud_config);
7e7cb34f 6924 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6925 /* clear N_programing_enable and N_value_index */
6926 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6927 I915_WRITE(aud_config, tmp);
6928
6929 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6930
6931 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6932 intel_crtc->eld_vld = true;
83358c85
WX		 6933
6934 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6935 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6936 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6937 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
1a91510d
JN		 6938 } else {
6939 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
6940 }
83358c85
WX		 6941
6942 if (intel_eld_uptodate(connector,
6943 aud_cntrl_st2, eldv,
6944 aud_cntl_st, IBX_ELD_ADDRESS,
6945 hdmiw_hdmiedid))
6946 return;
6947
6948 i = I915_READ(aud_cntrl_st2);
6949 i &= ~eldv;
6950 I915_WRITE(aud_cntrl_st2, i);
6951
6952 if (!eld[0])
6953 return;
6954
6955 i = I915_READ(aud_cntl_st);
6956 i &= ~IBX_ELD_ADDRESS;
6957 I915_WRITE(aud_cntl_st, i);
6958 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6959 DRM_DEBUG_DRIVER("port num:%d\n", i);
6960
6961 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6962 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6963 for (i = 0; i < len; i++)
6964 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6965
6966 i = I915_READ(aud_cntrl_st2);
6967 i |= eldv;
6968 I915_WRITE(aud_cntrl_st2, i);
6969
6970}
6971
e0dac65e 6972static void ironlake_write_eld(struct drm_connector *connector,
34427052
JN		 6973 struct drm_crtc *crtc,
6974 struct drm_display_mode *mode)
e0dac65e
WF		 6975{
6976 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6977 uint8_t *eld = connector->eld;
6978 uint32_t eldv;
6979 uint32_t i;
6980 int len;
6981 int hdmiw_hdmiedid;
b6daa025 6982 int aud_config;
e0dac65e
WF		 6983 int aud_cntl_st;
6984 int aud_cntrl_st2;
9b138a83 6985 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6986
b3f33cbf 6987 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6988 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6989 aud_config = IBX_AUD_CFG(pipe);
6990 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6991 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6992 } else {
9b138a83
WX		 6993 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6994 aud_config = CPT_AUD_CFG(pipe);
6995 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6996 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6997 }
6998
9b138a83 6999 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 7000
7001 i = I915_READ(aud_cntl_st);
9b138a83 7002 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 7003 if (!i) {
7004 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7005 /* operate blindly on all ports */
1202b4c6
WF		 7006 eldv = IBX_ELD_VALIDB;
7007 eldv |= IBX_ELD_VALIDB << 4;
7008 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 7009 } else {
2582a850 7010 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 7011 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 7012 }
7013
3a9627f4
WF		 7014 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7015 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7016 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025 7017 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
1a91510d
JN		 7018 } else {
7019 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7020 }
e0dac65e 7021
3a9627f4
WF		 7022 if (intel_eld_uptodate(connector,
7023 aud_cntrl_st2, eldv,
7024 aud_cntl_st, IBX_ELD_ADDRESS,
7025 hdmiw_hdmiedid))
7026 return;
7027
e0dac65e
WF		 7028 i = I915_READ(aud_cntrl_st2);
7029 i &= ~eldv;
7030 I915_WRITE(aud_cntrl_st2, i);
7031
7032 if (!eld[0])
7033 return;
7034
e0dac65e 7035 i = I915_READ(aud_cntl_st);
1202b4c6 7036 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 7037 I915_WRITE(aud_cntl_st, i);
7038
7039 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7040 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7041 for (i = 0; i < len; i++)
7042 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7043
7044 i = I915_READ(aud_cntrl_st2);
7045 i |= eldv;
7046 I915_WRITE(aud_cntrl_st2, i);
7047}
7048
7049void intel_write_eld(struct drm_encoder *encoder,
7050 struct drm_display_mode *mode)
7051{
7052 struct drm_crtc *crtc = encoder->crtc;
7053 struct drm_connector *connector;
7054 struct drm_device *dev = encoder->dev;
7055 struct drm_i915_private *dev_priv = dev->dev_private;
7056
7057 connector = drm_select_eld(encoder, mode);
7058 if (!connector)
7059 return;
7060
7061 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7062 connector->base.id,
7063 drm_get_connector_name(connector),
7064 connector->encoder->base.id,
7065 drm_get_encoder_name(connector->encoder));
7066
7067 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7068
7069 if (dev_priv->display.write_eld)
34427052 7070 dev_priv->display.write_eld(connector, crtc, mode);
e0dac65e
WF		 7071}
7072
560b85bb
CW		 7073static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7074{
7075 struct drm_device *dev = crtc->dev;
7076 struct drm_i915_private *dev_priv = dev->dev_private;
7077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7078 bool visible = base != 0;
7079 u32 cntl;
7080
7081 if (intel_crtc->cursor_visible == visible)
7082 return;
7083
9db4a9c7 7084 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 7085 if (visible) {
7086 /* On these chipsets we can only modify the base whilst
7087 * the cursor is disabled.
7088 */
9db4a9c7 7089 I915_WRITE(_CURABASE, base);
560b85bb
CW		 7090
7091 cntl &= ~(CURSOR_FORMAT_MASK);
7092 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7093 cntl |= CURSOR_ENABLE |
7094 CURSOR_GAMMA_ENABLE |
7095 CURSOR_FORMAT_ARGB;
7096 } else
7097 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 7098 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 7099
7100 intel_crtc->cursor_visible = visible;
7101}
7102
7103static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7104{
7105 struct drm_device *dev = crtc->dev;
7106 struct drm_i915_private *dev_priv = dev->dev_private;
7107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7108 int pipe = intel_crtc->pipe;
7109 bool visible = base != 0;
7110
7111 if (intel_crtc->cursor_visible != visible) {
548f245b 7112 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 7113 if (base) {
7114 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7115 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7116 cntl |= pipe << 28; /* Connect to correct pipe */
7117 } else {
7118 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7119 cntl |= CURSOR_MODE_DISABLE;
7120 }
9db4a9c7 7121 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 7122
7123 intel_crtc->cursor_visible = visible;
7124 }
7125 /* and commit changes on next vblank */
9db4a9c7 7126 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 7127}
7128
65a21cd6
JB		 7129static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7130{
7131 struct drm_device *dev = crtc->dev;
7132 struct drm_i915_private *dev_priv = dev->dev_private;
7133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7134 int pipe = intel_crtc->pipe;
7135 bool visible = base != 0;
7136
7137 if (intel_crtc->cursor_visible != visible) {
7138 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7139 if (base) {
7140 cntl &= ~CURSOR_MODE;
7141 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7142 } else {
7143 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7144 cntl |= CURSOR_MODE_DISABLE;
7145 }
1f5d76db 7146 if (IS_HASWELL(dev)) {
86d3efce 7147 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 7148 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7149 }
65a21cd6
JB		 7150 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7151
7152 intel_crtc->cursor_visible = visible;
7153 }
7154 /* and commit changes on next vblank */
7155 I915_WRITE(CURBASE_IVB(pipe), base);
7156}
7157
cda4b7d3 7158/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 7159static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7160 bool on)
cda4b7d3
CW		 7161{
7162 struct drm_device *dev = crtc->dev;
7163 struct drm_i915_private *dev_priv = dev->dev_private;
7164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7165 int pipe = intel_crtc->pipe;
7166 int x = intel_crtc->cursor_x;
7167 int y = intel_crtc->cursor_y;
d6e4db15 7168 u32 base = 0, pos = 0;
cda4b7d3
CW		 7169 bool visible;
7170
d6e4db15 7171 if (on)
cda4b7d3 7172 base = intel_crtc->cursor_addr;
cda4b7d3 7173
d6e4db15
VS		 7174 if (x >= intel_crtc->config.pipe_src_w)
7175 base = 0;
7176
7177 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7178 base = 0;
7179
7180 if (x < 0) {
efc9064e 7181 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7182 base = 0;
7183
7184 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7185 x = -x;
7186 }
7187 pos |= x << CURSOR_X_SHIFT;
7188
7189 if (y < 0) {
efc9064e 7190 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7191 base = 0;
7192
7193 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7194 y = -y;
7195 }
7196 pos |= y << CURSOR_Y_SHIFT;
7197
7198 visible = base != 0;
560b85bb 7199 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7200 return;
7201
0cd83aa9 7202 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 7203 I915_WRITE(CURPOS_IVB(pipe), pos);
7204 ivb_update_cursor(crtc, base);
7205 } else {
7206 I915_WRITE(CURPOS(pipe), pos);
7207 if (IS_845G(dev) || IS_I865G(dev))
7208 i845_update_cursor(crtc, base);
7209 else
7210 i9xx_update_cursor(crtc, base);
7211 }
cda4b7d3
CW		 7212}
7213
79e53945 7214static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7215 struct drm_file *file,
79e53945
JB		 7216 uint32_t handle,
7217 uint32_t width, uint32_t height)
7218{
7219 struct drm_device *dev = crtc->dev;
7220 struct drm_i915_private *dev_priv = dev->dev_private;
7221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7222 struct drm_i915_gem_object *obj;
cda4b7d3 7223 uint32_t addr;
3f8bc370 7224 int ret;
79e53945 7225
79e53945
JB		 7226 /* if we want to turn off the cursor ignore width and height */
7227 if (!handle) {
28c97730 7228 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7229 addr = 0;
05394f39 7230 obj = NULL;
5004417d 7231 mutex_lock(&dev->struct_mutex);
3f8bc370 7232 goto finish;
79e53945
JB		 7233 }
7234
7235 /* Currently we only support 64x64 cursors */
7236 if (width != 64 || height != 64) {
7237 DRM_ERROR("we currently only support 64x64 cursors\n");
7238 return -EINVAL;
7239 }
7240
05394f39 7241 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7242 if (&obj->base == NULL)
79e53945
JB		 7243 return -ENOENT;
7244
05394f39 7245 if (obj->base.size < width * height * 4) {
79e53945 7246 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7247 ret = -ENOMEM;
7248 goto fail;
79e53945
JB		 7249 }
7250
71acb5eb 7251 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7252 mutex_lock(&dev->struct_mutex);
b295d1b6 7253 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7254 unsigned alignment;
7255
d9e86c0e
CW		 7256 if (obj->tiling_mode) {
7257 DRM_ERROR("cursor cannot be tiled\n");
7258 ret = -EINVAL;
7259 goto fail_locked;
7260 }
7261
693db184
CW		 7262 /* Note that the w/a also requires 2 PTE of padding following
7263 * the bo. We currently fill all unused PTE with the shadow
7264 * page and so we should always have valid PTE following the
7265 * cursor preventing the VT-d warning.
7266 */
7267 alignment = 0;
7268 if (need_vtd_wa(dev))
7269 alignment = 64*1024;
7270
7271 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7272 if (ret) {
7273 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7274 goto fail_locked;
e7b526bb
CW		 7275 }
7276
d9e86c0e
CW		 7277 ret = i915_gem_object_put_fence(obj);
7278 if (ret) {
2da3b9b9 7279 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7280 goto fail_unpin;
7281 }
7282
f343c5f6 7283 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7284 } else {
6eeefaf3 7285 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7286 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7287 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7288 align);
71acb5eb
DA		 7289 if (ret) {
7290 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7291 goto fail_locked;
71acb5eb 7292 }
05394f39 7293 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7294 }
7295
a6c45cf0 7296 if (IS_GEN2(dev))
14b60391
JB		 7297 I915_WRITE(CURSIZE, (height << 12) | width);
7298
3f8bc370 7299 finish:
3f8bc370 7300 if (intel_crtc->cursor_bo) {
b295d1b6 7301 if (dev_priv->info->cursor_needs_physical) {
05394f39 7302 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7303 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7304 } else
cc98b413 7305 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7306 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7307 }
80824003 7308
7f9872e0 7309 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7310
7311 intel_crtc->cursor_addr = addr;
05394f39 7312 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7313 intel_crtc->cursor_width = width;
7314 intel_crtc->cursor_height = height;
7315
f2f5f771
VS		 7316 if (intel_crtc->active)
7317 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7318
79e53945 7319 return 0;
e7b526bb 7320fail_unpin:
cc98b413 7321 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7322fail_locked:
34b8686e 7323 mutex_unlock(&dev->struct_mutex);
bc9025bd 7324fail:
05394f39 7325 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7326 return ret;
79e53945
JB		 7327}
7328
7329static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7330{
79e53945 7331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7332
92e76c8c
VS		 7333 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7334 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
652c393a 7335
f2f5f771
VS		 7336 if (intel_crtc->active)
7337 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7338
7339 return 0;
b8c00ac5
DA		 7340}
7341
79e53945 7342static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7343 u16 *blue, uint32_t start, uint32_t size)
79e53945 7344{
7203425a 7345 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7347
7203425a 7348 for (i = start; i < end; i++) {
79e53945
JB		 7349 intel_crtc->lut_r[i] = red[i] >> 8;
7350 intel_crtc->lut_g[i] = green[i] >> 8;
7351 intel_crtc->lut_b[i] = blue[i] >> 8;
7352 }
7353
7354 intel_crtc_load_lut(crtc);
7355}
7356
79e53945
JB		 7357/* VESA 640x480x72Hz mode to set on the pipe */
7358static struct drm_display_mode load_detect_mode = {
7359 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7360 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7361};
7362
d2dff872
CW		 7363static struct drm_framebuffer *
7364intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7365 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7366 struct drm_i915_gem_object *obj)
7367{
7368 struct intel_framebuffer *intel_fb;
7369 int ret;
7370
7371 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7372 if (!intel_fb) {
7373 drm_gem_object_unreference_unlocked(&obj->base);
7374 return ERR_PTR(-ENOMEM);
7375 }
7376
dd4916c5
DV		 7377 ret = i915_mutex_lock_interruptible(dev);
7378 if (ret)
7379 goto err;
7380
d2dff872 7381 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 7382 mutex_unlock(&dev->struct_mutex);
7383 if (ret)
7384 goto err;
d2dff872
CW		 7385
7386 return &intel_fb->base;
dd4916c5
DV		 7387err:
7388 drm_gem_object_unreference_unlocked(&obj->base);
7389 kfree(intel_fb);
7390
7391 return ERR_PTR(ret);
d2dff872
CW		 7392}
7393
7394static u32
7395intel_framebuffer_pitch_for_width(int width, int bpp)
7396{
7397 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7398 return ALIGN(pitch, 64);
7399}
7400
7401static u32
7402intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7403{
7404 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7405 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7406}
7407
7408static struct drm_framebuffer *
7409intel_framebuffer_create_for_mode(struct drm_device *dev,
7410 struct drm_display_mode *mode,
7411 int depth, int bpp)
7412{
7413 struct drm_i915_gem_object *obj;
0fed39bd 7414 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7415
7416 obj = i915_gem_alloc_object(dev,
7417 intel_framebuffer_size_for_mode(mode, bpp));
7418 if (obj == NULL)
7419 return ERR_PTR(-ENOMEM);
7420
7421 mode_cmd.width = mode->hdisplay;
7422 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7423 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7424 bpp);
5ca0c34a 7425 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7426
7427 return intel_framebuffer_create(dev, &mode_cmd, obj);
7428}
7429
7430static struct drm_framebuffer *
7431mode_fits_in_fbdev(struct drm_device *dev,
7432 struct drm_display_mode *mode)
7433{
4520f53a 7434#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 7435 struct drm_i915_private *dev_priv = dev->dev_private;
7436 struct drm_i915_gem_object *obj;
7437 struct drm_framebuffer *fb;
7438
7439 if (dev_priv->fbdev == NULL)
7440 return NULL;
7441
7442 obj = dev_priv->fbdev->ifb.obj;
7443 if (obj == NULL)
7444 return NULL;
7445
7446 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7447 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7448 fb->bits_per_pixel))
d2dff872
CW		 7449 return NULL;
7450
01f2c773 7451 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7452 return NULL;
7453
7454 return fb;
4520f53a
DV		 7455#else
7456 return NULL;
7457#endif
d2dff872
CW		 7458}
7459
d2434ab7 7460bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7461 struct drm_display_mode *mode,
8261b191 7462 struct intel_load_detect_pipe *old)
79e53945
JB		 7463{
7464 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7465 struct intel_encoder *intel_encoder =
7466 intel_attached_encoder(connector);
79e53945 7467 struct drm_crtc *possible_crtc;
4ef69c7a 7468 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7469 struct drm_crtc *crtc = NULL;
7470 struct drm_device *dev = encoder->dev;
94352cf9 7471 struct drm_framebuffer *fb;
79e53945
JB		 7472 int i = -1;
7473
d2dff872
CW		 7474 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7475 connector->base.id, drm_get_connector_name(connector),
7476 encoder->base.id, drm_get_encoder_name(encoder));
7477
79e53945
JB		 7478 /*
7479 * Algorithm gets a little messy:
7a5e4805 7480 *
79e53945
JB		 7481 * - if the connector already has an assigned crtc, use it (but make
7482 * sure it's on first)
7a5e4805 7483 *
79e53945
JB		 7484 * - try to find the first unused crtc that can drive this connector,
7485 * and use that if we find one
79e53945
JB		 7486 */
7487
7488 /* See if we already have a CRTC for this connector */
7489 if (encoder->crtc) {
7490 crtc = encoder->crtc;
8261b191 7491
7b24056b
DV		 7492 mutex_lock(&crtc->mutex);
7493
24218aac 7494 old->dpms_mode = connector->dpms;
8261b191
CW		 7495 old->load_detect_temp = false;
7496
7497 /* Make sure the crtc and connector are running */
24218aac
DV		 7498 if (connector->dpms != DRM_MODE_DPMS_ON)
7499 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7500
7173188d 7501 return true;
79e53945
JB		 7502 }
7503
7504 /* Find an unused one (if possible) */
7505 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7506 i++;
7507 if (!(encoder->possible_crtcs & (1 << i)))
7508 continue;
7509 if (!possible_crtc->enabled) {
7510 crtc = possible_crtc;
7511 break;
7512 }
79e53945
JB		 7513 }
7514
7515 /*
7516 * If we didn't find an unused CRTC, don't use any.
7517 */
7518 if (!crtc) {
7173188d
CW		 7519 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7520 return false;
79e53945
JB		 7521 }
7522
7b24056b 7523 mutex_lock(&crtc->mutex);
fc303101
DV		 7524 intel_encoder->new_crtc = to_intel_crtc(crtc);
7525 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7526
7527 intel_crtc = to_intel_crtc(crtc);
24218aac 7528 old->dpms_mode = connector->dpms;
8261b191 7529 old->load_detect_temp = true;
d2dff872 7530 old->release_fb = NULL;
79e53945 7531
6492711d
CW		 7532 if (!mode)
7533 mode = &load_detect_mode;
79e53945 7534
d2dff872
CW		 7535 /* We need a framebuffer large enough to accommodate all accesses
7536 * that the plane may generate whilst we perform load detection.
7537 * We can not rely on the fbcon either being present (we get called
7538 * during its initialisation to detect all boot displays, or it may
7539 * not even exist) or that it is large enough to satisfy the
7540 * requested mode.
7541 */
94352cf9
DV		 7542 fb = mode_fits_in_fbdev(dev, mode);
7543 if (fb == NULL) {
d2dff872 7544 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7545 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7546 old->release_fb = fb;
d2dff872
CW		 7547 } else
7548 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7549 if (IS_ERR(fb)) {
d2dff872 7550 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7551 mutex_unlock(&crtc->mutex);
0e8b3d3e 7552 return false;
79e53945 7553 }
79e53945 7554
c0c36b94 7555 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7556 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7557 if (old->release_fb)
7558 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7559 mutex_unlock(&crtc->mutex);
0e8b3d3e 7560 return false;
79e53945 7561 }
7173188d 7562
79e53945 7563 /* let the connector get through one full cycle before testing */
9d0498a2 7564 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7565 return true;
79e53945
JB		 7566}
7567
d2434ab7 7568void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7569 struct intel_load_detect_pipe *old)
79e53945 7570{
d2434ab7
DV		 7571 struct intel_encoder *intel_encoder =
7572 intel_attached_encoder(connector);
4ef69c7a 7573 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7574 struct drm_crtc *crtc = encoder->crtc;
79e53945 7575
d2dff872
CW		 7576 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7577 connector->base.id, drm_get_connector_name(connector),
7578 encoder->base.id, drm_get_encoder_name(encoder));
7579
8261b191 7580 if (old->load_detect_temp) {
fc303101
DV		 7581 to_intel_connector(connector)->new_encoder = NULL;
7582 intel_encoder->new_crtc = NULL;
7583 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7584
36206361
DV		 7585 if (old->release_fb) {
7586 drm_framebuffer_unregister_private(old->release_fb);
7587 drm_framebuffer_unreference(old->release_fb);
7588 }
d2dff872 7589
67c96400 7590 mutex_unlock(&crtc->mutex);
0622a53c 7591 return;
79e53945
JB		 7592 }
7593
c751ce4f 7594 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7595 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7596 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7597
7598 mutex_unlock(&crtc->mutex);
79e53945
JB		 7599}
7600
da4a1efa
VS		 7601static int i9xx_pll_refclk(struct drm_device *dev,
7602 const struct intel_crtc_config *pipe_config)
7603{
7604 struct drm_i915_private *dev_priv = dev->dev_private;
7605 u32 dpll = pipe_config->dpll_hw_state.dpll;
7606
7607 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7608 return dev_priv->vbt.lvds_ssc_freq * 1000;
7609 else if (HAS_PCH_SPLIT(dev))
7610 return 120000;
7611 else if (!IS_GEN2(dev))
7612 return 96000;
7613 else
7614 return 48000;
7615}
7616
79e53945 7617/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7618static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7619 struct intel_crtc_config *pipe_config)
79e53945 7620{
f1f644dc 7621 struct drm_device *dev = crtc->base.dev;
79e53945 7622 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7623 int pipe = pipe_config->cpu_transcoder;
293623f7 7624 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7625 u32 fp;
7626 intel_clock_t clock;
da4a1efa 7627 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7628
7629 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7630 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7631 else
293623f7 7632 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7633
7634 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7635 if (IS_PINEVIEW(dev)) {
7636 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7637 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7638 } else {
7639 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7640 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7641 }
7642
a6c45cf0 7643 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7644 if (IS_PINEVIEW(dev))
7645 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7646 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7647 else
7648 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7649 DPLL_FPA01_P1_POST_DIV_SHIFT);
7650
7651 switch (dpll & DPLL_MODE_MASK) {
7652 case DPLLB_MODE_DAC_SERIAL:
7653 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7654 5 : 10;
7655 break;
7656 case DPLLB_MODE_LVDS:
7657 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7658 7 : 14;
7659 break;
7660 default:
28c97730 7661 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7662 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7663 return;
79e53945
JB		 7664 }
7665
ac58c3f0 7666 if (IS_PINEVIEW(dev))
da4a1efa 7667 pineview_clock(refclk, &clock);
ac58c3f0 7668 else
da4a1efa 7669 i9xx_clock(refclk, &clock);
79e53945
JB		 7670 } else {
7671 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7672
7673 if (is_lvds) {
7674 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7675 DPLL_FPA01_P1_POST_DIV_SHIFT);
7676 clock.p2 = 14;
79e53945
JB		 7677 } else {
7678 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7679 clock.p1 = 2;
7680 else {
7681 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7682 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7683 }
7684 if (dpll & PLL_P2_DIVIDE_BY_4)
7685 clock.p2 = 4;
7686 else
7687 clock.p2 = 2;
79e53945 7688 }
da4a1efa
VS		 7689
7690 i9xx_clock(refclk, &clock);
79e53945
JB		 7691 }
7692
18442d08
VS		 7693 /*
7694 * This value includes pixel_multiplier. We will use
241bfc38 7695 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7696 * encoder's get_config() function.
7697 */
7698 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7699}
7700
6878da05
VS		 7701int intel_dotclock_calculate(int link_freq,
7702 const struct intel_link_m_n *m_n)
f1f644dc 7703{
f1f644dc
JB		 7704 /*
7705 * The calculation for the data clock is:
1041a02f 7706 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7707 * But we want to avoid losing precison if possible, so:
1041a02f 7708 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7709 *
7710 * and the link clock is simpler:
1041a02f 7711 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7712 */
7713
6878da05
VS		 7714 if (!m_n->link_n)
7715 return 0;
f1f644dc 7716
6878da05
VS		 7717 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7718}
f1f644dc 7719
18442d08
VS		 7720static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7721 struct intel_crtc_config *pipe_config)
6878da05
VS		 7722{
7723 struct drm_device *dev = crtc->base.dev;
79e53945 7724
18442d08
VS		 7725 /* read out port_clock from the DPLL */
7726 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7727
f1f644dc 7728 /*
18442d08 7729 * This value does not include pixel_multiplier.
241bfc38 7730 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7731 * agree once we know their relationship in the encoder's
7732 * get_config() function.
79e53945 7733 */
241bfc38 7734 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7735 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7736 &pipe_config->fdi_m_n);
79e53945
JB		 7737}
7738
7739/** Returns the currently programmed mode of the given pipe. */
7740struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7741 struct drm_crtc *crtc)
7742{
548f245b 7743 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7745 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7746 struct drm_display_mode *mode;
f1f644dc 7747 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7748 int htot = I915_READ(HTOTAL(cpu_transcoder));
7749 int hsync = I915_READ(HSYNC(cpu_transcoder));
7750 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7751 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7752 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7753
7754 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7755 if (!mode)
7756 return NULL;
7757
f1f644dc
JB		 7758 /*
7759 * Construct a pipe_config sufficient for getting the clock info
7760 * back out of crtc_clock_get.
7761 *
7762 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7763 * to use a real value here instead.
7764 */
293623f7 7765 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7766 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7767 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7768 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7769 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7770 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7771
773ae034 7772 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7773 mode->hdisplay = (htot & 0xffff) + 1;
7774 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7775 mode->hsync_start = (hsync & 0xffff) + 1;
7776 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7777 mode->vdisplay = (vtot & 0xffff) + 1;
7778 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7779 mode->vsync_start = (vsync & 0xffff) + 1;
7780 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7781
7782 drm_mode_set_name(mode);
79e53945
JB		 7783
7784 return mode;
7785}
7786
3dec0095 7787static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7788{
7789 struct drm_device *dev = crtc->dev;
7790 drm_i915_private_t *dev_priv = dev->dev_private;
7791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7792 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7793 int dpll_reg = DPLL(pipe);
7794 int dpll;
652c393a 7795
bad720ff 7796 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7797 return;
7798
7799 if (!dev_priv->lvds_downclock_avail)
7800 return;
7801
dbdc6479 7802 dpll = I915_READ(dpll_reg);
652c393a 7803 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7804 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7805
8ac5a6d5 7806 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7807
7808 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7809 I915_WRITE(dpll_reg, dpll);
9d0498a2 7810 intel_wait_for_vblank(dev, pipe);
dbdc6479 7811
652c393a
JB		 7812 dpll = I915_READ(dpll_reg);
7813 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7814 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7815 }
652c393a
JB		 7816}
7817
7818static void intel_decrease_pllclock(struct drm_crtc *crtc)
7819{
7820 struct drm_device *dev = crtc->dev;
7821 drm_i915_private_t *dev_priv = dev->dev_private;
7822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7823
bad720ff 7824 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7825 return;
7826
7827 if (!dev_priv->lvds_downclock_avail)
7828 return;
7829
7830 /*
7831 * Since this is called by a timer, we should never get here in
7832 * the manual case.
7833 */
7834 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7835 int pipe = intel_crtc->pipe;
7836 int dpll_reg = DPLL(pipe);
7837 int dpll;
f6e5b160 7838
44d98a61 7839 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7840
8ac5a6d5 7841 assert_panel_unlocked(dev_priv, pipe);
652c393a 7842
dc257cf1 7843 dpll = I915_READ(dpll_reg);
652c393a
JB		 7844 dpll |= DISPLAY_RATE_SELECT_FPA1;
7845 I915_WRITE(dpll_reg, dpll);
9d0498a2 7846 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7847 dpll = I915_READ(dpll_reg);
7848 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7849 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7850 }
7851
7852}
7853
f047e395
CW		 7854void intel_mark_busy(struct drm_device *dev)
7855{
c67a470b
PZ		 7856 struct drm_i915_private *dev_priv = dev->dev_private;
7857
7858 hsw_package_c8_gpu_busy(dev_priv);
7859 i915_update_gfx_val(dev_priv);
f047e395
CW		 7860}
7861
7862void intel_mark_idle(struct drm_device *dev)
652c393a 7863{
c67a470b 7864 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7865 struct drm_crtc *crtc;
652c393a 7866
c67a470b
PZ		 7867 hsw_package_c8_gpu_idle(dev_priv);
7868
652c393a
JB		 7869 if (!i915_powersave)
7870 return;
7871
652c393a 7872 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7873 if (!crtc->fb)
7874 continue;
7875
725a5b54 7876 intel_decrease_pllclock(crtc);
652c393a 7877 }
b29c19b6
CW		 7878
7879 if (dev_priv->info->gen >= 6)
7880 gen6_rps_idle(dev->dev_private);
652c393a
JB		 7881}
7882
c65355bb
CW		 7883void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7884 struct intel_ring_buffer *ring)
652c393a 7885{
f047e395
CW		 7886 struct drm_device *dev = obj->base.dev;
7887 struct drm_crtc *crtc;
652c393a 7888
f047e395 7889 if (!i915_powersave)
acb87dfb
CW		 7890 return;
7891
652c393a
JB		 7892 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7893 if (!crtc->fb)
7894 continue;
7895
c65355bb
CW		 7896 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7897 continue;
7898
7899 intel_increase_pllclock(crtc);
7900 if (ring && intel_fbc_enabled(dev))
7901 ring->fbc_dirty = true;
652c393a
JB		 7902 }
7903}
7904
79e53945
JB		 7905static void intel_crtc_destroy(struct drm_crtc *crtc)
7906{
7907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7908 struct drm_device *dev = crtc->dev;
7909 struct intel_unpin_work *work;
7910 unsigned long flags;
7911
7912 spin_lock_irqsave(&dev->event_lock, flags);
7913 work = intel_crtc->unpin_work;
7914 intel_crtc->unpin_work = NULL;
7915 spin_unlock_irqrestore(&dev->event_lock, flags);
7916
7917 if (work) {
7918 cancel_work_sync(&work->work);
7919 kfree(work);
7920 }
79e53945 7921
40ccc72b
MK		 7922 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7923
79e53945 7924 drm_crtc_cleanup(crtc);
67e77c5a 7925
79e53945
JB		 7926 kfree(intel_crtc);
7927}
7928
6b95a207
KH		 7929static void intel_unpin_work_fn(struct work_struct *__work)
7930{
7931 struct intel_unpin_work *work =
7932 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7933 struct drm_device *dev = work->crtc->dev;
6b95a207 7934
b4a98e57 7935 mutex_lock(&dev->struct_mutex);
1690e1eb 7936 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7937 drm_gem_object_unreference(&work->pending_flip_obj->base);
7938 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7939
b4a98e57
CW		 7940 intel_update_fbc(dev);
7941 mutex_unlock(&dev->struct_mutex);
7942
7943 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7944 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7945
6b95a207
KH		 7946 kfree(work);
7947}
7948
1afe3e9d 7949static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7950 struct drm_crtc *crtc)
6b95a207
KH		 7951{
7952 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7954 struct intel_unpin_work *work;
6b95a207
KH		 7955 unsigned long flags;
7956
7957 /* Ignore early vblank irqs */
7958 if (intel_crtc == NULL)
7959 return;
7960
7961 spin_lock_irqsave(&dev->event_lock, flags);
7962 work = intel_crtc->unpin_work;
e7d841ca
CW		 7963
7964 /* Ensure we don't miss a work->pending update ... */
7965 smp_rmb();
7966
7967 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7968 spin_unlock_irqrestore(&dev->event_lock, flags);
7969 return;
7970 }
7971
e7d841ca
CW		 7972 /* and that the unpin work is consistent wrt ->pending. */
7973 smp_rmb();
7974
6b95a207 7975 intel_crtc->unpin_work = NULL;
6b95a207 7976
45a066eb
RC		 7977 if (work->event)
7978 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7979
0af7e4df
MK		 7980 drm_vblank_put(dev, intel_crtc->pipe);
7981
6b95a207
KH		 7982 spin_unlock_irqrestore(&dev->event_lock, flags);
7983
2c10d571 7984 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7985
7986 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7987
7988 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7989}
7990
1afe3e9d
JB		 7991void intel_finish_page_flip(struct drm_device *dev, int pipe)
7992{
7993 drm_i915_private_t *dev_priv = dev->dev_private;
7994 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7995
49b14a5c 7996 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7997}
7998
7999void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8000{
8001 drm_i915_private_t *dev_priv = dev->dev_private;
8002 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8003
49b14a5c 8004 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 8005}
8006
6b95a207
KH		 8007void intel_prepare_page_flip(struct drm_device *dev, int plane)
8008{
8009 drm_i915_private_t *dev_priv = dev->dev_private;
8010 struct intel_crtc *intel_crtc =
8011 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8012 unsigned long flags;
8013
e7d841ca
CW		 8014 /* NB: An MMIO update of the plane base pointer will also
8015 * generate a page-flip completion irq, i.e. every modeset
8016 * is also accompanied by a spurious intel_prepare_page_flip().
8017 */
6b95a207 8018 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 8019 if (intel_crtc->unpin_work)
8020 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 8021 spin_unlock_irqrestore(&dev->event_lock, flags);
8022}
8023
e7d841ca
CW		 8024inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8025{
8026 /* Ensure that the work item is consistent when activating it ... */
8027 smp_wmb();
8028 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8029 /* and that it is marked active as soon as the irq could fire. */
8030 smp_wmb();
8031}
8032
8c9f3aaf
JB		 8033static int intel_gen2_queue_flip(struct drm_device *dev,
8034 struct drm_crtc *crtc,
8035 struct drm_framebuffer *fb,
ed8d1975
KP		 8036 struct drm_i915_gem_object *obj,
8037 uint32_t flags)
8c9f3aaf
JB		 8038{
8039 struct drm_i915_private *dev_priv = dev->dev_private;
8040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 8041 u32 flip_mask;
6d90c952 8042 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8043 int ret;
8044
6d90c952 8045 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8046 if (ret)
83d4092b 8047 goto err;
8c9f3aaf 8048
6d90c952 8049 ret = intel_ring_begin(ring, 6);
8c9f3aaf 8050 if (ret)
83d4092b 8051 goto err_unpin;
8c9f3aaf
JB		 8052
8053 /* Can't queue multiple flips, so wait for the previous
8054 * one to finish before executing the next.
8055 */
8056 if (intel_crtc->plane)
8057 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8058 else
8059 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 8060 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8061 intel_ring_emit(ring, MI_NOOP);
8062 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8063 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8064 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 8065 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 8066 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 8067
8068 intel_mark_page_flip_active(intel_crtc);
09246732 8069 __intel_ring_advance(ring);
83d4092b
CW		 8070 return 0;
8071
8072err_unpin:
8073 intel_unpin_fb_obj(obj);
8074err:
8c9f3aaf
JB		 8075 return ret;
8076}
8077
8078static int intel_gen3_queue_flip(struct drm_device *dev,
8079 struct drm_crtc *crtc,
8080 struct drm_framebuffer *fb,
ed8d1975
KP		 8081 struct drm_i915_gem_object *obj,
8082 uint32_t flags)
8c9f3aaf
JB		 8083{
8084 struct drm_i915_private *dev_priv = dev->dev_private;
8085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 8086 u32 flip_mask;
6d90c952 8087 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8088 int ret;
8089
6d90c952 8090 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8091 if (ret)
83d4092b 8092 goto err;
8c9f3aaf 8093
6d90c952 8094 ret = intel_ring_begin(ring, 6);
8c9f3aaf 8095 if (ret)
83d4092b 8096 goto err_unpin;
8c9f3aaf
JB		 8097
8098 if (intel_crtc->plane)
8099 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8100 else
8101 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 8102 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8103 intel_ring_emit(ring, MI_NOOP);
8104 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8105 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8106 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 8107 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 8108 intel_ring_emit(ring, MI_NOOP);
8109
e7d841ca 8110 intel_mark_page_flip_active(intel_crtc);
09246732 8111 __intel_ring_advance(ring);
83d4092b
CW		 8112 return 0;
8113
8114err_unpin:
8115 intel_unpin_fb_obj(obj);
8116err:
8c9f3aaf
JB		 8117 return ret;
8118}
8119
8120static int intel_gen4_queue_flip(struct drm_device *dev,
8121 struct drm_crtc *crtc,
8122 struct drm_framebuffer *fb,
ed8d1975
KP		 8123 struct drm_i915_gem_object *obj,
8124 uint32_t flags)
8c9f3aaf
JB		 8125{
8126 struct drm_i915_private *dev_priv = dev->dev_private;
8127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8128 uint32_t pf, pipesrc;
6d90c952 8129 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8130 int ret;
8131
6d90c952 8132 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8133 if (ret)
83d4092b 8134 goto err;
8c9f3aaf 8135
6d90c952 8136 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8137 if (ret)
83d4092b 8138 goto err_unpin;
8c9f3aaf
JB		 8139
8140 /* i965+ uses the linear or tiled offsets from the
8141 * Display Registers (which do not change across a page-flip)
8142 * so we need only reprogram the base address.
8143 */
6d90c952
DV		 8144 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8145 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8146 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 8147 intel_ring_emit(ring,
f343c5f6 8148 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 8149 obj->tiling_mode);
8c9f3aaf
JB		 8150
8151 /* XXX Enabling the panel-fitter across page-flip is so far
8152 * untested on non-native modes, so ignore it for now.
8153 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8154 */
8155 pf = 0;
8156 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8157 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8158
8159 intel_mark_page_flip_active(intel_crtc);
09246732 8160 __intel_ring_advance(ring);
83d4092b
CW		 8161 return 0;
8162
8163err_unpin:
8164 intel_unpin_fb_obj(obj);
8165err:
8c9f3aaf
JB		 8166 return ret;
8167}
8168
8169static int intel_gen6_queue_flip(struct drm_device *dev,
8170 struct drm_crtc *crtc,
8171 struct drm_framebuffer *fb,
ed8d1975
KP		 8172 struct drm_i915_gem_object *obj,
8173 uint32_t flags)
8c9f3aaf
JB		 8174{
8175 struct drm_i915_private *dev_priv = dev->dev_private;
8176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 8177 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8178 uint32_t pf, pipesrc;
8179 int ret;
8180
6d90c952 8181 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8182 if (ret)
83d4092b 8183 goto err;
8c9f3aaf 8184
6d90c952 8185 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8186 if (ret)
83d4092b 8187 goto err_unpin;
8c9f3aaf 8188
6d90c952
DV		 8189 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8190 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8191 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8192 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8193
dc257cf1
DV		 8194 /* Contrary to the suggestions in the documentation,
8195 * "Enable Panel Fitter" does not seem to be required when page
8196 * flipping with a non-native mode, and worse causes a normal
8197 * modeset to fail.
8198 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8199 */
8200 pf = 0;
8c9f3aaf 8201 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8202 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8203
8204 intel_mark_page_flip_active(intel_crtc);
09246732 8205 __intel_ring_advance(ring);
83d4092b
CW		 8206 return 0;
8207
8208err_unpin:
8209 intel_unpin_fb_obj(obj);
8210err:
8c9f3aaf
JB		 8211 return ret;
8212}
8213
7c9017e5
JB		 8214static int intel_gen7_queue_flip(struct drm_device *dev,
8215 struct drm_crtc *crtc,
8216 struct drm_framebuffer *fb,
ed8d1975
KP		 8217 struct drm_i915_gem_object *obj,
8218 uint32_t flags)
7c9017e5
JB		 8219{
8220 struct drm_i915_private *dev_priv = dev->dev_private;
8221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8222 struct intel_ring_buffer *ring;
cb05d8de 8223 uint32_t plane_bit = 0;
ffe74d75
CW		 8224 int len, ret;
8225
8226 ring = obj->ring;
1c5fd085 8227 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8228 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8229
8230 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8231 if (ret)
83d4092b 8232 goto err;
7c9017e5 8233
cb05d8de
DV		 8234 switch(intel_crtc->plane) {
8235 case PLANE_A:
8236 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8237 break;
8238 case PLANE_B:
8239 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8240 break;
8241 case PLANE_C:
8242 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8243 break;
8244 default:
8245 WARN_ONCE(1, "unknown plane in flip command\n");
8246 ret = -ENODEV;
ab3951eb 8247 goto err_unpin;
cb05d8de
DV		 8248 }
8249
ffe74d75
CW		 8250 len = 4;
8251 if (ring->id == RCS)
8252 len += 6;
8253
8254 ret = intel_ring_begin(ring, len);
7c9017e5 8255 if (ret)
83d4092b 8256 goto err_unpin;
7c9017e5 8257
ffe74d75
CW		 8258 /* Unmask the flip-done completion message. Note that the bspec says that
8259 * we should do this for both the BCS and RCS, and that we must not unmask
8260 * more than one flip event at any time (or ensure that one flip message
8261 * can be sent by waiting for flip-done prior to queueing new flips).
8262 * Experimentation says that BCS works despite DERRMR masking all
8263 * flip-done completion events and that unmasking all planes at once
8264 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8265 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8266 */
8267 if (ring->id == RCS) {
8268 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8269 intel_ring_emit(ring, DERRMR);
8270 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8271 DERRMR_PIPEB_PRI_FLIP_DONE |
8272 DERRMR_PIPEC_PRI_FLIP_DONE));
8273 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8274 intel_ring_emit(ring, DERRMR);
8275 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8276 }
8277
cb05d8de 8278 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8279 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8280 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8281 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8282
8283 intel_mark_page_flip_active(intel_crtc);
09246732 8284 __intel_ring_advance(ring);
83d4092b
CW		 8285 return 0;
8286
8287err_unpin:
8288 intel_unpin_fb_obj(obj);
8289err:
7c9017e5
JB		 8290 return ret;
8291}
8292
8c9f3aaf
JB		 8293static int intel_default_queue_flip(struct drm_device *dev,
8294 struct drm_crtc *crtc,
8295 struct drm_framebuffer *fb,
ed8d1975
KP		 8296 struct drm_i915_gem_object *obj,
8297 uint32_t flags)
8c9f3aaf
JB		 8298{
8299 return -ENODEV;
8300}
8301
6b95a207
KH		 8302static int intel_crtc_page_flip(struct drm_crtc *crtc,
8303 struct drm_framebuffer *fb,
ed8d1975
KP		 8304 struct drm_pending_vblank_event *event,
8305 uint32_t page_flip_flags)
6b95a207
KH		 8306{
8307 struct drm_device *dev = crtc->dev;
8308 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8309 struct drm_framebuffer *old_fb = crtc->fb;
8310 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8312 struct intel_unpin_work *work;
8c9f3aaf 8313 unsigned long flags;
52e68630 8314 int ret;
6b95a207 8315
e6a595d2
VS		 8316 /* Can't change pixel format via MI display flips. */
8317 if (fb->pixel_format != crtc->fb->pixel_format)
8318 return -EINVAL;
8319
8320 /*
8321 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8322 * Note that pitch changes could also affect these register.
8323 */
8324 if (INTEL_INFO(dev)->gen > 3 &&
8325 (fb->offsets[0] != crtc->fb->offsets[0] ||
8326 fb->pitches[0] != crtc->fb->pitches[0]))
8327 return -EINVAL;
8328
b14c5679 8329 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8330 if (work == NULL)
8331 return -ENOMEM;
8332
6b95a207 8333 work->event = event;
b4a98e57 8334 work->crtc = crtc;
4a35f83b 8335 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8336 INIT_WORK(&work->work, intel_unpin_work_fn);
8337
7317c75e
JB		 8338 ret = drm_vblank_get(dev, intel_crtc->pipe);
8339 if (ret)
8340 goto free_work;
8341
6b95a207
KH		 8342 /* We borrow the event spin lock for protecting unpin_work */
8343 spin_lock_irqsave(&dev->event_lock, flags);
8344 if (intel_crtc->unpin_work) {
8345 spin_unlock_irqrestore(&dev->event_lock, flags);
8346 kfree(work);
7317c75e 8347 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8348
8349 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8350 return -EBUSY;
8351 }
8352 intel_crtc->unpin_work = work;
8353 spin_unlock_irqrestore(&dev->event_lock, flags);
8354
b4a98e57
CW		 8355 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8356 flush_workqueue(dev_priv->wq);
8357
79158103
CW		 8358 ret = i915_mutex_lock_interruptible(dev);
8359 if (ret)
8360 goto cleanup;
6b95a207 8361
75dfca80 8362 /* Reference the objects for the scheduled work. */
05394f39
CW		 8363 drm_gem_object_reference(&work->old_fb_obj->base);
8364 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8365
8366 crtc->fb = fb;
96b099fd 8367
e1f99ce6 8368 work->pending_flip_obj = obj;
e1f99ce6 8369
4e5359cd
SF		 8370 work->enable_stall_check = true;
8371
b4a98e57 8372 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8373 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8374
ed8d1975 8375 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8376 if (ret)
8377 goto cleanup_pending;
6b95a207 8378
7782de3b 8379 intel_disable_fbc(dev);
c65355bb 8380 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8381 mutex_unlock(&dev->struct_mutex);
8382
e5510fac
JB		 8383 trace_i915_flip_request(intel_crtc->plane, obj);
8384
6b95a207 8385 return 0;
96b099fd 8386
8c9f3aaf 8387cleanup_pending:
b4a98e57 8388 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8389 crtc->fb = old_fb;
05394f39
CW		 8390 drm_gem_object_unreference(&work->old_fb_obj->base);
8391 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8392 mutex_unlock(&dev->struct_mutex);
8393
79158103 8394cleanup:
96b099fd
CW		 8395 spin_lock_irqsave(&dev->event_lock, flags);
8396 intel_crtc->unpin_work = NULL;
8397 spin_unlock_irqrestore(&dev->event_lock, flags);
8398
7317c75e
JB		 8399 drm_vblank_put(dev, intel_crtc->pipe);
8400free_work:
96b099fd
CW		 8401 kfree(work);
8402
8403 return ret;
6b95a207
KH		 8404}
8405
f6e5b160 8406static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8407 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8408 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8409};
8410
50f56119
DV		 8411static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8412 struct drm_crtc *crtc)
8413{
8414 struct drm_device *dev;
8415 struct drm_crtc *tmp;
8416 int crtc_mask = 1;
47f1c6c9 8417
50f56119 8418 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8419
50f56119 8420 dev = crtc->dev;
47f1c6c9 8421
50f56119
DV		 8422 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8423 if (tmp == crtc)
8424 break;
8425 crtc_mask <<= 1;
8426 }
47f1c6c9 8427
50f56119
DV		 8428 if (encoder->possible_crtcs & crtc_mask)
8429 return true;
8430 return false;
47f1c6c9 8431}
79e53945 8432
9a935856
DV		 8433/**
8434 * intel_modeset_update_staged_output_state
8435 *
8436 * Updates the staged output configuration state, e.g. after we've read out the
8437 * current hw state.
8438 */
8439static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8440{
9a935856
DV		 8441 struct intel_encoder *encoder;
8442 struct intel_connector *connector;
f6e5b160 8443
9a935856
DV		 8444 list_for_each_entry(connector, &dev->mode_config.connector_list,
8445 base.head) {
8446 connector->new_encoder =
8447 to_intel_encoder(connector->base.encoder);
8448 }
f6e5b160 8449
9a935856
DV		 8450 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8451 base.head) {
8452 encoder->new_crtc =
8453 to_intel_crtc(encoder->base.crtc);
8454 }
f6e5b160
CW		 8455}
8456
9a935856
DV		 8457/**
8458 * intel_modeset_commit_output_state
8459 *
8460 * This function copies the stage display pipe configuration to the real one.
8461 */
8462static void intel_modeset_commit_output_state(struct drm_device *dev)
8463{
8464 struct intel_encoder *encoder;
8465 struct intel_connector *connector;
f6e5b160 8466
9a935856
DV		 8467 list_for_each_entry(connector, &dev->mode_config.connector_list,
8468 base.head) {
8469 connector->base.encoder = &connector->new_encoder->base;
8470 }
f6e5b160 8471
9a935856
DV		 8472 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8473 base.head) {
8474 encoder->base.crtc = &encoder->new_crtc->base;
8475 }
8476}
8477
050f7aeb
DV		 8478static void
8479connected_sink_compute_bpp(struct intel_connector * connector,
8480 struct intel_crtc_config *pipe_config)
8481{
8482 int bpp = pipe_config->pipe_bpp;
8483
8484 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8485 connector->base.base.id,
8486 drm_get_connector_name(&connector->base));
8487
8488 /* Don't use an invalid EDID bpc value */
8489 if (connector->base.display_info.bpc &&
8490 connector->base.display_info.bpc * 3 < bpp) {
8491 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8492 bpp, connector->base.display_info.bpc*3);
8493 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8494 }
8495
8496 /* Clamp bpp to 8 on screens without EDID 1.4 */
8497 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8498 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8499 bpp);
8500 pipe_config->pipe_bpp = 24;
8501 }
8502}
8503
4e53c2e0 8504static int
050f7aeb
DV		 8505compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8506 struct drm_framebuffer *fb,
8507 struct intel_crtc_config *pipe_config)
4e53c2e0 8508{
050f7aeb
DV		 8509 struct drm_device *dev = crtc->base.dev;
8510 struct intel_connector *connector;
4e53c2e0
DV		 8511 int bpp;
8512
d42264b1
DV		 8513 switch (fb->pixel_format) {
8514 case DRM_FORMAT_C8:
4e53c2e0
DV		 8515 bpp = 8*3; /* since we go through a colormap */
8516 break;
d42264b1
DV		 8517 case DRM_FORMAT_XRGB1555:
8518 case DRM_FORMAT_ARGB1555:
8519 /* checked in intel_framebuffer_init already */
8520 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8521 return -EINVAL;
8522 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8523 bpp = 6*3; /* min is 18bpp */
8524 break;
d42264b1
DV		 8525 case DRM_FORMAT_XBGR8888:
8526 case DRM_FORMAT_ABGR8888:
8527 /* checked in intel_framebuffer_init already */
8528 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8529 return -EINVAL;
8530 case DRM_FORMAT_XRGB8888:
8531 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8532 bpp = 8*3;
8533 break;
d42264b1
DV		 8534 case DRM_FORMAT_XRGB2101010:
8535 case DRM_FORMAT_ARGB2101010:
8536 case DRM_FORMAT_XBGR2101010:
8537 case DRM_FORMAT_ABGR2101010:
8538 /* checked in intel_framebuffer_init already */
8539 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8540 return -EINVAL;
4e53c2e0
DV		 8541 bpp = 10*3;
8542 break;
baba133a 8543 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8544 default:
8545 DRM_DEBUG_KMS("unsupported depth\n");
8546 return -EINVAL;
8547 }
8548
4e53c2e0
DV		 8549 pipe_config->pipe_bpp = bpp;
8550
8551 /* Clamp display bpp to EDID value */
8552 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8553 base.head) {
1b829e05
DV		 8554 if (!connector->new_encoder ||
8555 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8556 continue;
8557
050f7aeb 8558 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8559 }
8560
8561 return bpp;
8562}
8563
644db711
DV		 8564static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8565{
8566 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8567 "type: 0x%x flags: 0x%x\n",
1342830c 8568 mode->crtc_clock,
644db711
DV		 8569 mode->crtc_hdisplay, mode->crtc_hsync_start,
8570 mode->crtc_hsync_end, mode->crtc_htotal,
8571 mode->crtc_vdisplay, mode->crtc_vsync_start,
8572 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8573}
8574
c0b03411
DV		 8575static void intel_dump_pipe_config(struct intel_crtc *crtc,
8576 struct intel_crtc_config *pipe_config,
8577 const char *context)
8578{
8579 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8580 context, pipe_name(crtc->pipe));
8581
8582 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8583 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8584 pipe_config->pipe_bpp, pipe_config->dither);
8585 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8586 pipe_config->has_pch_encoder,
8587 pipe_config->fdi_lanes,
8588 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8589 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8590 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8591 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8592 pipe_config->has_dp_encoder,
8593 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8594 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8595 pipe_config->dp_m_n.tu);
c0b03411
DV		 8596 DRM_DEBUG_KMS("requested mode:\n");
8597 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8598 DRM_DEBUG_KMS("adjusted mode:\n");
8599 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8600 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8601 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8602 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8603 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8604 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8605 pipe_config->gmch_pfit.control,
8606 pipe_config->gmch_pfit.pgm_ratios,
8607 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8608 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8609 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8610 pipe_config->pch_pfit.size,
8611 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8612 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8613 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8614}
8615
accfc0c5
DV		 8616static bool check_encoder_cloning(struct drm_crtc *crtc)
8617{
8618 int num_encoders = 0;
8619 bool uncloneable_encoders = false;
8620 struct intel_encoder *encoder;
8621
8622 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8623 base.head) {
8624 if (&encoder->new_crtc->base != crtc)
8625 continue;
8626
8627 num_encoders++;
8628 if (!encoder->cloneable)
8629 uncloneable_encoders = true;
8630 }
8631
8632 return !(num_encoders > 1 && uncloneable_encoders);
8633}
8634
b8cecdf5
DV		 8635static struct intel_crtc_config *
8636intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8637 struct drm_framebuffer *fb,
b8cecdf5 8638 struct drm_display_mode *mode)
ee7b9f93 8639{
7758a113 8640 struct drm_device *dev = crtc->dev;
7758a113 8641 struct intel_encoder *encoder;
b8cecdf5 8642 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8643 int plane_bpp, ret = -EINVAL;
8644 bool retry = true;
ee7b9f93 8645
accfc0c5
DV		 8646 if (!check_encoder_cloning(crtc)) {
8647 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8648 return ERR_PTR(-EINVAL);
8649 }
8650
b8cecdf5
DV		 8651 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8652 if (!pipe_config)
7758a113
DV		 8653 return ERR_PTR(-ENOMEM);
8654
b8cecdf5
DV		 8655 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8656 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8657
e143a21c
DV		 8658 pipe_config->cpu_transcoder =
8659 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8660 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8661
2960bc9c
ID		 8662 /*
8663 * Sanitize sync polarity flags based on requested ones. If neither
8664 * positive or negative polarity is requested, treat this as meaning
8665 * negative polarity.
8666 */
8667 if (!(pipe_config->adjusted_mode.flags &
8668 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8669 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8670
8671 if (!(pipe_config->adjusted_mode.flags &
8672 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8673 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8674
050f7aeb
DV		 8675 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8676 * plane pixel format and any sink constraints into account. Returns the
8677 * source plane bpp so that dithering can be selected on mismatches
8678 * after encoders and crtc also have had their say. */
8679 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8680 fb, pipe_config);
4e53c2e0
DV		 8681 if (plane_bpp < 0)
8682 goto fail;
8683
e41a56be
VS		 8684 /*
8685 * Determine the real pipe dimensions. Note that stereo modes can
8686 * increase the actual pipe size due to the frame doubling and
8687 * insertion of additional space for blanks between the frame. This
8688 * is stored in the crtc timings. We use the requested mode to do this
8689 * computation to clearly distinguish it from the adjusted mode, which
8690 * can be changed by the connectors in the below retry loop.
8691 */
8692 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8693 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8694 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8695
e29c22c0 8696encoder_retry:
ef1b460d 8697 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8698 pipe_config->port_clock = 0;
ef1b460d 8699 pipe_config->pixel_multiplier = 1;
ff9a6750 8700
135c81b8 8701 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8702 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8703
7758a113
DV		 8704 /* Pass our mode to the connectors and the CRTC to give them a chance to
8705 * adjust it according to limitations or connector properties, and also
8706 * a chance to reject the mode entirely.
47f1c6c9 8707 */
7758a113
DV		 8708 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8709 base.head) {
47f1c6c9 8710
7758a113
DV		 8711 if (&encoder->new_crtc->base != crtc)
8712 continue;
7ae89233 8713
efea6e8e
DV		 8714 if (!(encoder->compute_config(encoder, pipe_config))) {
8715 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8716 goto fail;
8717 }
ee7b9f93 8718 }
47f1c6c9 8719
ff9a6750
DV		 8720 /* Set default port clock if not overwritten by the encoder. Needs to be
8721 * done afterwards in case the encoder adjusts the mode. */
8722 if (!pipe_config->port_clock)
241bfc38
DL		 8723 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8724 * pipe_config->pixel_multiplier;
ff9a6750 8725
a43f6e0f 8726 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8727 if (ret < 0) {
7758a113
DV		 8728 DRM_DEBUG_KMS("CRTC fixup failed\n");
8729 goto fail;
ee7b9f93 8730 }
e29c22c0
DV		 8731
8732 if (ret == RETRY) {
8733 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8734 ret = -EINVAL;
8735 goto fail;
8736 }
8737
8738 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8739 retry = false;
8740 goto encoder_retry;
8741 }
8742
4e53c2e0
DV		 8743 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8744 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8745 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8746
b8cecdf5 8747 return pipe_config;
7758a113 8748fail:
b8cecdf5 8749 kfree(pipe_config);
e29c22c0 8750 return ERR_PTR(ret);
ee7b9f93 8751}
47f1c6c9 8752
e2e1ed41
DV		 8753/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8754 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8755static void
8756intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8757 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8758{
8759 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8760 struct drm_device *dev = crtc->dev;
8761 struct intel_encoder *encoder;
8762 struct intel_connector *connector;
8763 struct drm_crtc *tmp_crtc;
79e53945 8764
e2e1ed41 8765 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8766
e2e1ed41
DV		 8767 /* Check which crtcs have changed outputs connected to them, these need
8768 * to be part of the prepare_pipes mask. We don't (yet) support global
8769 * modeset across multiple crtcs, so modeset_pipes will only have one
8770 * bit set at most. */
8771 list_for_each_entry(connector, &dev->mode_config.connector_list,
8772 base.head) {
8773 if (connector->base.encoder == &connector->new_encoder->base)
8774 continue;
79e53945 8775
e2e1ed41
DV		 8776 if (connector->base.encoder) {
8777 tmp_crtc = connector->base.encoder->crtc;
8778
8779 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8780 }
8781
8782 if (connector->new_encoder)
8783 *prepare_pipes |=
8784 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8785 }
8786
e2e1ed41
DV		 8787 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8788 base.head) {
8789 if (encoder->base.crtc == &encoder->new_crtc->base)
8790 continue;
8791
8792 if (encoder->base.crtc) {
8793 tmp_crtc = encoder->base.crtc;
8794
8795 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8796 }
8797
8798 if (encoder->new_crtc)
8799 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8800 }
8801
e2e1ed41
DV		 8802 /* Check for any pipes that will be fully disabled ... */
8803 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8804 base.head) {
8805 bool used = false;
22fd0fab 8806
e2e1ed41
DV		 8807 /* Don't try to disable disabled crtcs. */
8808 if (!intel_crtc->base.enabled)
8809 continue;
7e7d76c3 8810
e2e1ed41
DV		 8811 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8812 base.head) {
8813 if (encoder->new_crtc == intel_crtc)
8814 used = true;
8815 }
8816
8817 if (!used)
8818 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8819 }
8820
e2e1ed41
DV		 8821
8822 /* set_mode is also used to update properties on life display pipes. */
8823 intel_crtc = to_intel_crtc(crtc);
8824 if (crtc->enabled)
8825 *prepare_pipes |= 1 << intel_crtc->pipe;
8826
b6c5164d
DV		 8827 /*
8828 * For simplicity do a full modeset on any pipe where the output routing
8829 * changed. We could be more clever, but that would require us to be
8830 * more careful with calling the relevant encoder->mode_set functions.
8831 */
e2e1ed41
DV		 8832 if (*prepare_pipes)
8833 *modeset_pipes = *prepare_pipes;
8834
8835 /* ... and mask these out. */
8836 *modeset_pipes &= ~(*disable_pipes);
8837 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8838
8839 /*
8840 * HACK: We don't (yet) fully support global modesets. intel_set_config
8841 * obies this rule, but the modeset restore mode of
8842 * intel_modeset_setup_hw_state does not.
8843 */
8844 *modeset_pipes &= 1 << intel_crtc->pipe;
8845 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8846
8847 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8848 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8849}
79e53945 8850
ea9d758d 8851static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8852{
ea9d758d 8853 struct drm_encoder *encoder;
f6e5b160 8854 struct drm_device *dev = crtc->dev;
f6e5b160 8855
ea9d758d
DV		 8856 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8857 if (encoder->crtc == crtc)
8858 return true;
8859
8860 return false;
8861}
8862
8863static void
8864intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8865{
8866 struct intel_encoder *intel_encoder;
8867 struct intel_crtc *intel_crtc;
8868 struct drm_connector *connector;
8869
8870 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8871 base.head) {
8872 if (!intel_encoder->base.crtc)
8873 continue;
8874
8875 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8876
8877 if (prepare_pipes & (1 << intel_crtc->pipe))
8878 intel_encoder->connectors_active = false;
8879 }
8880
8881 intel_modeset_commit_output_state(dev);
8882
8883 /* Update computed state. */
8884 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8885 base.head) {
8886 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8887 }
8888
8889 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8890 if (!connector->encoder || !connector->encoder->crtc)
8891 continue;
8892
8893 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8894
8895 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8896 struct drm_property *dpms_property =
8897 dev->mode_config.dpms_property;
8898
ea9d758d 8899 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8900 drm_object_property_set_value(&connector->base,
68d34720
DV		 8901 dpms_property,
8902 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8903
8904 intel_encoder = to_intel_encoder(connector->encoder);
8905 intel_encoder->connectors_active = true;
8906 }
8907 }
8908
8909}
8910
3bd26263 8911static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8912{
3bd26263 8913 int diff;
f1f644dc
JB		 8914
8915 if (clock1 == clock2)
8916 return true;
8917
8918 if (!clock1 || !clock2)
8919 return false;
8920
8921 diff = abs(clock1 - clock2);
8922
8923 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8924 return true;
8925
8926 return false;
8927}
8928
25c5b266
DV		 8929#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8930 list_for_each_entry((intel_crtc), \
8931 &(dev)->mode_config.crtc_list, \
8932 base.head) \
0973f18f 8933 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8934
0e8ffe1b 8935static bool
2fa2fe9a
DV		 8936intel_pipe_config_compare(struct drm_device *dev,
8937 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8938 struct intel_crtc_config *pipe_config)
8939{
66e985c0
DV		 8940#define PIPE_CONF_CHECK_X(name) \
8941 if (current_config->name != pipe_config->name) { \
8942 DRM_ERROR("mismatch in " #name " " \
8943 "(expected 0x%08x, found 0x%08x)\n", \
8944 current_config->name, \
8945 pipe_config->name); \
8946 return false; \
8947 }
8948
08a24034
DV		 8949#define PIPE_CONF_CHECK_I(name) \
8950 if (current_config->name != pipe_config->name) { \
8951 DRM_ERROR("mismatch in " #name " " \
8952 "(expected %i, found %i)\n", \
8953 current_config->name, \
8954 pipe_config->name); \
8955 return false; \
88adfff1
DV		 8956 }
8957
1bd1bd80
DV		 8958#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8959 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8960 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8961 "(expected %i, found %i)\n", \
8962 current_config->name & (mask), \
8963 pipe_config->name & (mask)); \
8964 return false; \
8965 }
8966
5e550656
VS		 8967#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8968 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8969 DRM_ERROR("mismatch in " #name " " \
8970 "(expected %i, found %i)\n", \
8971 current_config->name, \
8972 pipe_config->name); \
8973 return false; \
8974 }
8975
bb760063
DV		 8976#define PIPE_CONF_QUIRK(quirk) \
8977 ((current_config->quirks | pipe_config->quirks) & (quirk))
8978
eccb140b
DV		 8979 PIPE_CONF_CHECK_I(cpu_transcoder);
8980
08a24034
DV		 8981 PIPE_CONF_CHECK_I(has_pch_encoder);
8982 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8983 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8984 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8985 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8986 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8987 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8988
eb14cb74
VS		 8989 PIPE_CONF_CHECK_I(has_dp_encoder);
8990 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8991 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8992 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8993 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8994 PIPE_CONF_CHECK_I(dp_m_n.tu);
8995
1bd1bd80
DV		 8996 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8997 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8998 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8999 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9000 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9001 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9002
9003 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9004 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9005 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9006 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9007 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9008 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9009
c93f54cf 9010 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 9011
1bd1bd80
DV		 9012 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9013 DRM_MODE_FLAG_INTERLACE);
9014
bb760063
DV		 9015 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9016 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9017 DRM_MODE_FLAG_PHSYNC);
9018 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9019 DRM_MODE_FLAG_NHSYNC);
9020 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9021 DRM_MODE_FLAG_PVSYNC);
9022 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9023 DRM_MODE_FLAG_NVSYNC);
9024 }
045ac3b5 9025
37327abd
VS		 9026 PIPE_CONF_CHECK_I(pipe_src_w);
9027 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 9028
2fa2fe9a
DV		 9029 PIPE_CONF_CHECK_I(gmch_pfit.control);
9030 /* pfit ratios are autocomputed by the hw on gen4+ */
9031 if (INTEL_INFO(dev)->gen < 4)
9032 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9033 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 9034 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9035 if (current_config->pch_pfit.enabled) {
9036 PIPE_CONF_CHECK_I(pch_pfit.pos);
9037 PIPE_CONF_CHECK_I(pch_pfit.size);
9038 }
2fa2fe9a 9039
42db64ef
PZ		 9040 PIPE_CONF_CHECK_I(ips_enabled);
9041
282740f7
VS		 9042 PIPE_CONF_CHECK_I(double_wide);
9043
c0d43d62 9044 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 9045 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 9046 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 9047 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9048 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 9049
42571aef
VS		 9050 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9051 PIPE_CONF_CHECK_I(pipe_bpp);
9052
d71b8d4a 9053 if (!IS_HASWELL(dev)) {
241bfc38 9054 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 9055 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9056 }
5e550656 9057
66e985c0 9058#undef PIPE_CONF_CHECK_X
08a24034 9059#undef PIPE_CONF_CHECK_I
1bd1bd80 9060#undef PIPE_CONF_CHECK_FLAGS
5e550656 9061#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 9062#undef PIPE_CONF_QUIRK
88adfff1 9063
0e8ffe1b
DV		 9064 return true;
9065}
9066
91d1b4bd
DV		 9067static void
9068check_connector_state(struct drm_device *dev)
8af6cf88 9069{
8af6cf88
DV		 9070 struct intel_connector *connector;
9071
9072 list_for_each_entry(connector, &dev->mode_config.connector_list,
9073 base.head) {
9074 /* This also checks the encoder/connector hw state with the
9075 * ->get_hw_state callbacks. */
9076 intel_connector_check_state(connector);
9077
9078 WARN(&connector->new_encoder->base != connector->base.encoder,
9079 "connector's staged encoder doesn't match current encoder\n");
9080 }
91d1b4bd
DV		 9081}
9082
9083static void
9084check_encoder_state(struct drm_device *dev)
9085{
9086 struct intel_encoder *encoder;
9087 struct intel_connector *connector;
8af6cf88
DV		 9088
9089 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9090 base.head) {
9091 bool enabled = false;
9092 bool active = false;
9093 enum pipe pipe, tracked_pipe;
9094
9095 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9096 encoder->base.base.id,
9097 drm_get_encoder_name(&encoder->base));
9098
9099 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9100 "encoder's stage crtc doesn't match current crtc\n");
9101 WARN(encoder->connectors_active && !encoder->base.crtc,
9102 "encoder's active_connectors set, but no crtc\n");
9103
9104 list_for_each_entry(connector, &dev->mode_config.connector_list,
9105 base.head) {
9106 if (connector->base.encoder != &encoder->base)
9107 continue;
9108 enabled = true;
9109 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9110 active = true;
9111 }
9112 WARN(!!encoder->base.crtc != enabled,
9113 "encoder's enabled state mismatch "
9114 "(expected %i, found %i)\n",
9115 !!encoder->base.crtc, enabled);
9116 WARN(active && !encoder->base.crtc,
9117 "active encoder with no crtc\n");
9118
9119 WARN(encoder->connectors_active != active,
9120 "encoder's computed active state doesn't match tracked active state "
9121 "(expected %i, found %i)\n", active, encoder->connectors_active);
9122
9123 active = encoder->get_hw_state(encoder, &pipe);
9124 WARN(active != encoder->connectors_active,
9125 "encoder's hw state doesn't match sw tracking "
9126 "(expected %i, found %i)\n",
9127 encoder->connectors_active, active);
9128
9129 if (!encoder->base.crtc)
9130 continue;
9131
9132 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9133 WARN(active && pipe != tracked_pipe,
9134 "active encoder's pipe doesn't match"
9135 "(expected %i, found %i)\n",
9136 tracked_pipe, pipe);
9137
9138 }
91d1b4bd
DV		 9139}
9140
9141static void
9142check_crtc_state(struct drm_device *dev)
9143{
9144 drm_i915_private_t *dev_priv = dev->dev_private;
9145 struct intel_crtc *crtc;
9146 struct intel_encoder *encoder;
9147 struct intel_crtc_config pipe_config;
8af6cf88
DV		 9148
9149 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9150 base.head) {
9151 bool enabled = false;
9152 bool active = false;
9153
045ac3b5
JB		 9154 memset(&pipe_config, 0, sizeof(pipe_config));
9155
8af6cf88
DV		 9156 DRM_DEBUG_KMS("[CRTC:%d]\n",
9157 crtc->base.base.id);
9158
9159 WARN(crtc->active && !crtc->base.enabled,
9160 "active crtc, but not enabled in sw tracking\n");
9161
9162 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9163 base.head) {
9164 if (encoder->base.crtc != &crtc->base)
9165 continue;
9166 enabled = true;
9167 if (encoder->connectors_active)
9168 active = true;
9169 }
6c49f241 9170
8af6cf88
DV		 9171 WARN(active != crtc->active,
9172 "crtc's computed active state doesn't match tracked active state "
9173 "(expected %i, found %i)\n", active, crtc->active);
9174 WARN(enabled != crtc->base.enabled,
9175 "crtc's computed enabled state doesn't match tracked enabled state "
9176 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9177
0e8ffe1b
DV		 9178 active = dev_priv->display.get_pipe_config(crtc,
9179 &pipe_config);
d62cf62a
DV		 9180
9181 /* hw state is inconsistent with the pipe A quirk */
9182 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9183 active = crtc->active;
9184
6c49f241
DV		 9185 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9186 base.head) {
3eaba51c 9187 enum pipe pipe;
6c49f241
DV		 9188 if (encoder->base.crtc != &crtc->base)
9189 continue;
3eaba51c
VS		 9190 if (encoder->get_config &&
9191 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9192 encoder->get_config(encoder, &pipe_config);
9193 }
9194
0e8ffe1b
DV		 9195 WARN(crtc->active != active,
9196 "crtc active state doesn't match with hw state "
9197 "(expected %i, found %i)\n", crtc->active, active);
9198
c0b03411
DV		 9199 if (active &&
9200 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9201 WARN(1, "pipe state doesn't match!\n");
9202 intel_dump_pipe_config(crtc, &pipe_config,
9203 "[hw state]");
9204 intel_dump_pipe_config(crtc, &crtc->config,
9205 "[sw state]");
9206 }
8af6cf88
DV		 9207 }
9208}
9209
91d1b4bd
DV		 9210static void
9211check_shared_dpll_state(struct drm_device *dev)
9212{
9213 drm_i915_private_t *dev_priv = dev->dev_private;
9214 struct intel_crtc *crtc;
9215 struct intel_dpll_hw_state dpll_hw_state;
9216 int i;
5358901f
DV		 9217
9218 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9219 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9220 int enabled_crtcs = 0, active_crtcs = 0;
9221 bool active;
9222
9223 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9224
9225 DRM_DEBUG_KMS("%s\n", pll->name);
9226
9227 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9228
9229 WARN(pll->active > pll->refcount,
9230 "more active pll users than references: %i vs %i\n",
9231 pll->active, pll->refcount);
9232 WARN(pll->active && !pll->on,
9233 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9234 WARN(pll->on && !pll->active,
9235 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9236 WARN(pll->on != active,
9237 "pll on state mismatch (expected %i, found %i)\n",
9238 pll->on, active);
9239
9240 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9241 base.head) {
9242 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9243 enabled_crtcs++;
9244 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9245 active_crtcs++;
9246 }
9247 WARN(pll->active != active_crtcs,
9248 "pll active crtcs mismatch (expected %i, found %i)\n",
9249 pll->active, active_crtcs);
9250 WARN(pll->refcount != enabled_crtcs,
9251 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9252 pll->refcount, enabled_crtcs);
66e985c0
DV		 9253
9254 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9255 sizeof(dpll_hw_state)),
9256 "pll hw state mismatch\n");
5358901f 9257 }
8af6cf88
DV		 9258}
9259
91d1b4bd
DV		 9260void
9261intel_modeset_check_state(struct drm_device *dev)
9262{
9263 check_connector_state(dev);
9264 check_encoder_state(dev);
9265 check_crtc_state(dev);
9266 check_shared_dpll_state(dev);
9267}
9268
18442d08
VS		 9269void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9270 int dotclock)
9271{
9272 /*
9273 * FDI already provided one idea for the dotclock.
9274 * Yell if the encoder disagrees.
9275 */
241bfc38 9276 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9277 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9278 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9279}
9280
f30da187
DV		 9281static int __intel_set_mode(struct drm_crtc *crtc,
9282 struct drm_display_mode *mode,
9283 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9284{
9285 struct drm_device *dev = crtc->dev;
dbf2b54e 9286 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9287 struct drm_display_mode *saved_mode, *saved_hwmode;
9288 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9289 struct intel_crtc *intel_crtc;
9290 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9291 int ret = 0;
a6778b3c 9292
a1e22653 9293 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9294 if (!saved_mode)
9295 return -ENOMEM;
3ac18232 9296 saved_hwmode = saved_mode + 1;
a6778b3c 9297
e2e1ed41 9298 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9299 &prepare_pipes, &disable_pipes);
9300
3ac18232
TG		 9301 *saved_hwmode = crtc->hwmode;
9302 *saved_mode = crtc->mode;
a6778b3c 9303
25c5b266
DV		 9304 /* Hack: Because we don't (yet) support global modeset on multiple
9305 * crtcs, we don't keep track of the new mode for more than one crtc.
9306 * Hence simply check whether any bit is set in modeset_pipes in all the
9307 * pieces of code that are not yet converted to deal with mutliple crtcs
9308 * changing their mode at the same time. */
25c5b266 9309 if (modeset_pipes) {
4e53c2e0 9310 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9311 if (IS_ERR(pipe_config)) {
9312 ret = PTR_ERR(pipe_config);
9313 pipe_config = NULL;
9314
3ac18232 9315 goto out;
25c5b266 9316 }
c0b03411
DV		 9317 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9318 "[modeset]");
25c5b266 9319 }
a6778b3c 9320
460da916
DV		 9321 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9322 intel_crtc_disable(&intel_crtc->base);
9323
ea9d758d
DV		 9324 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9325 if (intel_crtc->base.enabled)
9326 dev_priv->display.crtc_disable(&intel_crtc->base);
9327 }
a6778b3c 9328
6c4c86f5
DV		 9329 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9330 * to set it here already despite that we pass it down the callchain.
f6e5b160 9331 */
b8cecdf5 9332 if (modeset_pipes) {
25c5b266 9333 crtc->mode = *mode;
b8cecdf5
DV		 9334 /* mode_set/enable/disable functions rely on a correct pipe
9335 * config. */
9336 to_intel_crtc(crtc)->config = *pipe_config;
9337 }
7758a113 9338
ea9d758d
DV		 9339 /* Only after disabling all output pipelines that will be changed can we
9340 * update the the output configuration. */
9341 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9342
47fab737
DV		 9343 if (dev_priv->display.modeset_global_resources)
9344 dev_priv->display.modeset_global_resources(dev);
9345
a6778b3c
DV		 9346 /* Set up the DPLL and any encoders state that needs to adjust or depend
9347 * on the DPLL.
f6e5b160 9348 */
25c5b266 9349 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9350 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9351 x, y, fb);
9352 if (ret)
9353 goto done;
a6778b3c
DV		 9354 }
9355
9356 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9357 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9358 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9359
25c5b266
DV		 9360 if (modeset_pipes) {
9361 /* Store real post-adjustment hardware mode. */
b8cecdf5 9362 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9363
25c5b266
DV		 9364 /* Calculate and store various constants which
9365 * are later needed by vblank and swap-completion
9366 * timestamping. They are derived from true hwmode.
9367 */
9368 drm_calc_timestamping_constants(crtc);
9369 }
a6778b3c
DV		 9370
9371 /* FIXME: add subpixel order */
9372done:
c0c36b94 9373 if (ret && crtc->enabled) {
3ac18232
TG		 9374 crtc->hwmode = *saved_hwmode;
9375 crtc->mode = *saved_mode;
a6778b3c
DV		 9376 }
9377
3ac18232 9378out:
b8cecdf5 9379 kfree(pipe_config);
3ac18232 9380 kfree(saved_mode);
a6778b3c 9381 return ret;
f6e5b160
CW		 9382}
9383
e7457a9a
DL		 9384static int intel_set_mode(struct drm_crtc *crtc,
9385 struct drm_display_mode *mode,
9386 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9387{
9388 int ret;
9389
9390 ret = __intel_set_mode(crtc, mode, x, y, fb);
9391
9392 if (ret == 0)
9393 intel_modeset_check_state(crtc->dev);
9394
9395 return ret;
9396}
9397
c0c36b94
CW		 9398void intel_crtc_restore_mode(struct drm_crtc *crtc)
9399{
9400 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9401}
9402
25c5b266
DV		 9403#undef for_each_intel_crtc_masked
9404
d9e55608
DV		 9405static void intel_set_config_free(struct intel_set_config *config)
9406{
9407 if (!config)
9408 return;
9409
1aa4b628
DV		 9410 kfree(config->save_connector_encoders);
9411 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9412 kfree(config);
9413}
9414
85f9eb71
DV		 9415static int intel_set_config_save_state(struct drm_device *dev,
9416 struct intel_set_config *config)
9417{
85f9eb71
DV		 9418 struct drm_encoder *encoder;
9419 struct drm_connector *connector;
9420 int count;
9421
1aa4b628
DV		 9422 config->save_encoder_crtcs =
9423 kcalloc(dev->mode_config.num_encoder,
9424 sizeof(struct drm_crtc *), GFP_KERNEL);
9425 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9426 return -ENOMEM;
9427
1aa4b628
DV		 9428 config->save_connector_encoders =
9429 kcalloc(dev->mode_config.num_connector,
9430 sizeof(struct drm_encoder *), GFP_KERNEL);
9431 if (!config->save_connector_encoders)
85f9eb71
DV		 9432 return -ENOMEM;
9433
9434 /* Copy data. Note that driver private data is not affected.
9435 * Should anything bad happen only the expected state is
9436 * restored, not the drivers personal bookkeeping.
9437 */
85f9eb71
DV		 9438 count = 0;
9439 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9440 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9441 }
9442
9443 count = 0;
9444 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9445 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9446 }
9447
9448 return 0;
9449}
9450
9451static void intel_set_config_restore_state(struct drm_device *dev,
9452 struct intel_set_config *config)
9453{
9a935856
DV		 9454 struct intel_encoder *encoder;
9455 struct intel_connector *connector;
85f9eb71
DV		 9456 int count;
9457
85f9eb71 9458 count = 0;
9a935856
DV		 9459 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9460 encoder->new_crtc =
9461 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9462 }
9463
9464 count = 0;
9a935856
DV		 9465 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9466 connector->new_encoder =
9467 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9468 }
9469}
9470
e3de42b6 9471static bool
2e57f47d 9472is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9473{
9474 int i;
9475
2e57f47d
CW		 9476 if (set->num_connectors == 0)
9477 return false;
9478
9479 if (WARN_ON(set->connectors == NULL))
9480 return false;
9481
9482 for (i = 0; i < set->num_connectors; i++)
9483 if (set->connectors[i]->encoder &&
9484 set->connectors[i]->encoder->crtc == set->crtc &&
9485 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9486 return true;
9487
9488 return false;
9489}
9490
5e2b584e
DV		 9491static void
9492intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9493 struct intel_set_config *config)
9494{
9495
9496 /* We should be able to check here if the fb has the same properties
9497 * and then just flip_or_move it */
2e57f47d
CW		 9498 if (is_crtc_connector_off(set)) {
9499 config->mode_changed = true;
e3de42b6 9500 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9501 /* If we have no fb then treat it as a full mode set */
9502 if (set->crtc->fb == NULL) {
319d9827
JB		 9503 struct intel_crtc *intel_crtc =
9504 to_intel_crtc(set->crtc);
9505
9506 if (intel_crtc->active && i915_fastboot) {
9507 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9508 config->fb_changed = true;
9509 } else {
9510 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9511 config->mode_changed = true;
9512 }
5e2b584e
DV		 9513 } else if (set->fb == NULL) {
9514 config->mode_changed = true;
72f4901e
DV		 9515 } else if (set->fb->pixel_format !=
9516 set->crtc->fb->pixel_format) {
5e2b584e 9517 config->mode_changed = true;
e3de42b6 9518 } else {
5e2b584e 9519 config->fb_changed = true;
e3de42b6 9520 }
5e2b584e
DV		 9521 }
9522
835c5873 9523 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9524 config->fb_changed = true;
9525
9526 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9527 DRM_DEBUG_KMS("modes are different, full mode set\n");
9528 drm_mode_debug_printmodeline(&set->crtc->mode);
9529 drm_mode_debug_printmodeline(set->mode);
9530 config->mode_changed = true;
9531 }
a1d95703
CW		 9532
9533 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9534 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9535}
9536
2e431051 9537static int
9a935856
DV		 9538intel_modeset_stage_output_state(struct drm_device *dev,
9539 struct drm_mode_set *set,
9540 struct intel_set_config *config)
50f56119 9541{
85f9eb71 9542 struct drm_crtc *new_crtc;
9a935856
DV		 9543 struct intel_connector *connector;
9544 struct intel_encoder *encoder;
f3f08572 9545 int ro;
50f56119 9546
9abdda74 9547 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9548 * of connectors. For paranoia, double-check this. */
9549 WARN_ON(!set->fb && (set->num_connectors != 0));
9550 WARN_ON(set->fb && (set->num_connectors == 0));
9551
9a935856
DV		 9552 list_for_each_entry(connector, &dev->mode_config.connector_list,
9553 base.head) {
9554 /* Otherwise traverse passed in connector list and get encoders
9555 * for them. */
50f56119 9556 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9557 if (set->connectors[ro] == &connector->base) {
9558 connector->new_encoder = connector->encoder;
50f56119
DV		 9559 break;
9560 }
9561 }
9562
9a935856
DV		 9563 /* If we disable the crtc, disable all its connectors. Also, if
9564 * the connector is on the changing crtc but not on the new
9565 * connector list, disable it. */
9566 if ((!set->fb || ro == set->num_connectors) &&
9567 connector->base.encoder &&
9568 connector->base.encoder->crtc == set->crtc) {
9569 connector->new_encoder = NULL;
9570
9571 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9572 connector->base.base.id,
9573 drm_get_connector_name(&connector->base));
9574 }
9575
9576
9577 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9578 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9579 config->mode_changed = true;
50f56119
DV		 9580 }
9581 }
9a935856 9582 /* connector->new_encoder is now updated for all connectors. */
50f56119 9583
9a935856 9584 /* Update crtc of enabled connectors. */
9a935856
DV		 9585 list_for_each_entry(connector, &dev->mode_config.connector_list,
9586 base.head) {
9587 if (!connector->new_encoder)
50f56119
DV		 9588 continue;
9589
9a935856 9590 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9591
9592 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9593 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9594 new_crtc = set->crtc;
9595 }
9596
9597 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9598 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9599 new_crtc)) {
5e2b584e 9600 return -EINVAL;
50f56119 9601 }
9a935856
DV		 9602 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9603
9604 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9605 connector->base.base.id,
9606 drm_get_connector_name(&connector->base),
9607 new_crtc->base.id);
9608 }
9609
9610 /* Check for any encoders that needs to be disabled. */
9611 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9612 base.head) {
9613 list_for_each_entry(connector,
9614 &dev->mode_config.connector_list,
9615 base.head) {
9616 if (connector->new_encoder == encoder) {
9617 WARN_ON(!connector->new_encoder->new_crtc);
9618
9619 goto next_encoder;
9620 }
9621 }
9622 encoder->new_crtc = NULL;
9623next_encoder:
9624 /* Only now check for crtc changes so we don't miss encoders
9625 * that will be disabled. */
9626 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9627 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9628 config->mode_changed = true;
50f56119
DV		 9629 }
9630 }
9a935856 9631 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9632
2e431051
DV		 9633 return 0;
9634}
9635
9636static int intel_crtc_set_config(struct drm_mode_set *set)
9637{
9638 struct drm_device *dev;
2e431051
DV		 9639 struct drm_mode_set save_set;
9640 struct intel_set_config *config;
9641 int ret;
2e431051 9642
8d3e375e
DV		 9643 BUG_ON(!set);
9644 BUG_ON(!set->crtc);
9645 BUG_ON(!set->crtc->helper_private);
2e431051 9646
7e53f3a4
DV		 9647 /* Enforce sane interface api - has been abused by the fb helper. */
9648 BUG_ON(!set->mode && set->fb);
9649 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9650
2e431051
DV		 9651 if (set->fb) {
9652 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9653 set->crtc->base.id, set->fb->base.id,
9654 (int)set->num_connectors, set->x, set->y);
9655 } else {
9656 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9657 }
9658
9659 dev = set->crtc->dev;
9660
9661 ret = -ENOMEM;
9662 config = kzalloc(sizeof(*config), GFP_KERNEL);
9663 if (!config)
9664 goto out_config;
9665
9666 ret = intel_set_config_save_state(dev, config);
9667 if (ret)
9668 goto out_config;
9669
9670 save_set.crtc = set->crtc;
9671 save_set.mode = &set->crtc->mode;
9672 save_set.x = set->crtc->x;
9673 save_set.y = set->crtc->y;
9674 save_set.fb = set->crtc->fb;
9675
9676 /* Compute whether we need a full modeset, only an fb base update or no
9677 * change at all. In the future we might also check whether only the
9678 * mode changed, e.g. for LVDS where we only change the panel fitter in
9679 * such cases. */
9680 intel_set_config_compute_mode_changes(set, config);
9681
9a935856 9682 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9683 if (ret)
9684 goto fail;
9685
5e2b584e 9686 if (config->mode_changed) {
c0c36b94
CW		 9687 ret = intel_set_mode(set->crtc, set->mode,
9688 set->x, set->y, set->fb);
5e2b584e 9689 } else if (config->fb_changed) {
4878cae2
VS		 9690 intel_crtc_wait_for_pending_flips(set->crtc);
9691
4f660f49 9692 ret = intel_pipe_set_base(set->crtc,
94352cf9 9693 set->x, set->y, set->fb);
50f56119
DV		 9694 }
9695
2d05eae1 9696 if (ret) {
bf67dfeb
DV		 9697 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9698 set->crtc->base.id, ret);
50f56119 9699fail:
2d05eae1 9700 intel_set_config_restore_state(dev, config);
50f56119 9701
2d05eae1
CW		 9702 /* Try to restore the config */
9703 if (config->mode_changed &&
9704 intel_set_mode(save_set.crtc, save_set.mode,
9705 save_set.x, save_set.y, save_set.fb))
9706 DRM_ERROR("failed to restore config after modeset failure\n");
9707 }
50f56119 9708
d9e55608
DV		 9709out_config:
9710 intel_set_config_free(config);
50f56119
DV		 9711 return ret;
9712}
f6e5b160
CW		 9713
9714static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9715 .cursor_set = intel_crtc_cursor_set,
9716 .cursor_move = intel_crtc_cursor_move,
9717 .gamma_set = intel_crtc_gamma_set,
50f56119 9718 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9719 .destroy = intel_crtc_destroy,
9720 .page_flip = intel_crtc_page_flip,
9721};
9722
79f689aa
PZ		 9723static void intel_cpu_pll_init(struct drm_device *dev)
9724{
affa9354 9725 if (HAS_DDI(dev))
79f689aa
PZ		 9726 intel_ddi_pll_init(dev);
9727}
9728
5358901f
DV		 9729static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9730 struct intel_shared_dpll *pll,
9731 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9732{
5358901f 9733 uint32_t val;
ee7b9f93 9734
5358901f 9735 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9736 hw_state->dpll = val;
9737 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9738 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9739
9740 return val & DPLL_VCO_ENABLE;
9741}
9742
15bdd4cf
DV		 9743static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9744 struct intel_shared_dpll *pll)
9745{
9746 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9747 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9748}
9749
e7b903d2
DV		 9750static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9751 struct intel_shared_dpll *pll)
9752{
e7b903d2
DV		 9753 /* PCH refclock must be enabled first */
9754 assert_pch_refclk_enabled(dev_priv);
9755
15bdd4cf
DV		 9756 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9757
9758 /* Wait for the clocks to stabilize. */
9759 POSTING_READ(PCH_DPLL(pll->id));
9760 udelay(150);
9761
9762 /* The pixel multiplier can only be updated once the
9763 * DPLL is enabled and the clocks are stable.
9764 *
9765 * So write it again.
9766 */
9767 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9768 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9769 udelay(200);
9770}
9771
9772static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9773 struct intel_shared_dpll *pll)
9774{
9775 struct drm_device *dev = dev_priv->dev;
9776 struct intel_crtc *crtc;
e7b903d2
DV		 9777
9778 /* Make sure no transcoder isn't still depending on us. */
9779 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9780 if (intel_crtc_to_shared_dpll(crtc) == pll)
9781 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9782 }
9783
15bdd4cf
DV		 9784 I915_WRITE(PCH_DPLL(pll->id), 0);
9785 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9786 udelay(200);
9787}
9788
46edb027
DV		 9789static char *ibx_pch_dpll_names[] = {
9790 "PCH DPLL A",
9791 "PCH DPLL B",
9792};
9793
7c74ade1 9794static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9795{
e7b903d2 9796 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9797 int i;
9798
7c74ade1 9799 dev_priv->num_shared_dpll = 2;
ee7b9f93 9800
e72f9fbf 9801 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9802 dev_priv->shared_dplls[i].id = i;
9803 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9804 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9805 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9806 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9807 dev_priv->shared_dplls[i].get_hw_state =
9808 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9809 }
9810}
9811
7c74ade1
DV		 9812static void intel_shared_dpll_init(struct drm_device *dev)
9813{
e7b903d2 9814 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9815
9816 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9817 ibx_pch_dpll_init(dev);
9818 else
9819 dev_priv->num_shared_dpll = 0;
9820
9821 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9822 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9823 dev_priv->num_shared_dpll);
9824}
9825
b358d0a6 9826static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9827{
22fd0fab 9828 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9829 struct intel_crtc *intel_crtc;
9830 int i;
9831
955382f3 9832 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9833 if (intel_crtc == NULL)
9834 return;
9835
9836 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9837
9838 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9839 for (i = 0; i < 256; i++) {
9840 intel_crtc->lut_r[i] = i;
9841 intel_crtc->lut_g[i] = i;
9842 intel_crtc->lut_b[i] = i;
9843 }
9844
80824003
JB		 9845 /* Swap pipes & planes for FBC on pre-965 */
9846 intel_crtc->pipe = pipe;
9847 intel_crtc->plane = pipe;
e2e767ab 9848 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9849 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9850 intel_crtc->plane = !pipe;
80824003
JB		 9851 }
9852
22fd0fab
JB		 9853 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9854 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9855 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9856 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9857
79e53945 9858 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9859}
9860
08d7b3d1 9861int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9862 struct drm_file *file)
08d7b3d1 9863{
08d7b3d1 9864 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9865 struct drm_mode_object *drmmode_obj;
9866 struct intel_crtc *crtc;
08d7b3d1 9867
1cff8f6b
DV		 9868 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9869 return -ENODEV;
08d7b3d1 9870
c05422d5
DV		 9871 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9872 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9873
c05422d5 9874 if (!drmmode_obj) {
08d7b3d1
CW		 9875 DRM_ERROR("no such CRTC id\n");
9876 return -EINVAL;
9877 }
9878
c05422d5
DV		 9879 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9880 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9881
c05422d5 9882 return 0;
08d7b3d1
CW		 9883}
9884
66a9278e 9885static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9886{
66a9278e
DV		 9887 struct drm_device *dev = encoder->base.dev;
9888 struct intel_encoder *source_encoder;
79e53945 9889 int index_mask = 0;
79e53945
JB		 9890 int entry = 0;
9891
66a9278e
DV		 9892 list_for_each_entry(source_encoder,
9893 &dev->mode_config.encoder_list, base.head) {
9894
9895 if (encoder == source_encoder)
79e53945 9896 index_mask |= (1 << entry);
66a9278e
DV		 9897
9898 /* Intel hw has only one MUX where enocoders could be cloned. */
9899 if (encoder->cloneable && source_encoder->cloneable)
9900 index_mask |= (1 << entry);
9901
79e53945
JB		 9902 entry++;
9903 }
4ef69c7a 9904
79e53945
JB		 9905 return index_mask;
9906}
9907
4d302442
CW		 9908static bool has_edp_a(struct drm_device *dev)
9909{
9910 struct drm_i915_private *dev_priv = dev->dev_private;
9911
9912 if (!IS_MOBILE(dev))
9913 return false;
9914
9915 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9916 return false;
9917
9918 if (IS_GEN5(dev) &&
9919 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9920 return false;
9921
9922 return true;
9923}
9924
79e53945
JB		 9925static void intel_setup_outputs(struct drm_device *dev)
9926{
725e30ad 9927 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9928 struct intel_encoder *encoder;
cb0953d7 9929 bool dpd_is_edp = false;
79e53945 9930
c9093354 9931 intel_lvds_init(dev);
79e53945 9932
c40c0f5b 9933 if (!IS_ULT(dev))
79935fca 9934 intel_crt_init(dev);
cb0953d7 9935
affa9354 9936 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9937 int found;
9938
9939 /* Haswell uses DDI functions to detect digital outputs */
9940 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9941 /* DDI A only supports eDP */
9942 if (found)
9943 intel_ddi_init(dev, PORT_A);
9944
9945 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9946 * register */
9947 found = I915_READ(SFUSE_STRAP);
9948
9949 if (found & SFUSE_STRAP_DDIB_DETECTED)
9950 intel_ddi_init(dev, PORT_B);
9951 if (found & SFUSE_STRAP_DDIC_DETECTED)
9952 intel_ddi_init(dev, PORT_C);
9953 if (found & SFUSE_STRAP_DDID_DETECTED)
9954 intel_ddi_init(dev, PORT_D);
9955 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9956 int found;
270b3042
DV		 9957 dpd_is_edp = intel_dpd_is_edp(dev);
9958
9959 if (has_edp_a(dev))
9960 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9961
dc0fa718 9962 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9963 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9964 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9965 if (!found)
e2debe91 9966 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9967 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9968 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9969 }
9970
dc0fa718 9971 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9972 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9973
dc0fa718 9974 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9975 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9976
5eb08b69 9977 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9978 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9979
270b3042 9980 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9981 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9982 } else if (IS_VALLEYVIEW(dev)) {
585a94b8
AB		 9983 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9984 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9985 PORT_B);
9986 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9987 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9988 }
9989
6f6005a5
JB		 9990 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9991 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9992 PORT_C);
9993 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9994 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9995 PORT_C);
9996 }
19c03924 9997
3cfca973 9998 intel_dsi_init(dev);
103a196f 9999 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 10000 bool found = false;
7d57382e 10001
e2debe91 10002 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 10003 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 10004 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 10005 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10006 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 10007 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 10008 }
27185ae1 10009
e7281eab 10010 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 10011 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 10012 }
13520b05
KH		 10013
10014 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 10015
e2debe91 10016 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 10017 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 10018 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 10019 }
27185ae1 10020
e2debe91 10021 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 10022
b01f2c3a
JB		 10023 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10024 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 10025 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 10026 }
e7281eab 10027 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 10028 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 10029 }
27185ae1 10030
b01f2c3a 10031 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 10032 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 10033 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 10034 } else if (IS_GEN2(dev))
79e53945
JB		 10035 intel_dvo_init(dev);
10036
103a196f 10037 if (SUPPORTS_TV(dev))
79e53945
JB		 10038 intel_tv_init(dev);
10039
4ef69c7a
CW		 10040 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10041 encoder->base.possible_crtcs = encoder->crtc_mask;
10042 encoder->base.possible_clones =
66a9278e 10043 intel_encoder_clones(encoder);
79e53945 10044 }
47356eb6 10045
dde86e2d 10046 intel_init_pch_refclk(dev);
270b3042
DV		 10047
10048 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 10049}
10050
ddfe1567
CW		 10051void intel_framebuffer_fini(struct intel_framebuffer *fb)
10052{
10053 drm_framebuffer_cleanup(&fb->base);
80075d49 10054 WARN_ON(!fb->obj->framebuffer_references--);
ddfe1567
CW		 10055 drm_gem_object_unreference_unlocked(&fb->obj->base);
10056}
10057
79e53945
JB		 10058static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10059{
10060 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 10061
ddfe1567 10062 intel_framebuffer_fini(intel_fb);
79e53945
JB		 10063 kfree(intel_fb);
10064}
10065
10066static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 10067 struct drm_file *file,
79e53945
JB		 10068 unsigned int *handle)
10069{
10070 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 10071 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 10072
05394f39 10073 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 10074}
10075
10076static const struct drm_framebuffer_funcs intel_fb_funcs = {
10077 .destroy = intel_user_framebuffer_destroy,
10078 .create_handle = intel_user_framebuffer_create_handle,
10079};
10080
38651674
DA		 10081int intel_framebuffer_init(struct drm_device *dev,
10082 struct intel_framebuffer *intel_fb,
308e5bcb 10083 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 10084 struct drm_i915_gem_object *obj)
79e53945 10085{
53155c0a 10086 int aligned_height, tile_height;
a35cdaa0 10087 int pitch_limit;
79e53945
JB		 10088 int ret;
10089
dd4916c5
DV		 10090 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10091
c16ed4be
CW		 10092 if (obj->tiling_mode == I915_TILING_Y) {
10093 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 10094 return -EINVAL;
c16ed4be 10095 }
57cd6508 10096
c16ed4be
CW		 10097 if (mode_cmd->pitches[0] & 63) {
10098 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10099 mode_cmd->pitches[0]);
57cd6508 10100 return -EINVAL;
c16ed4be 10101 }
57cd6508 10102
a35cdaa0
CW		 10103 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10104 pitch_limit = 32*1024;
10105 } else if (INTEL_INFO(dev)->gen >= 4) {
10106 if (obj->tiling_mode)
10107 pitch_limit = 16*1024;
10108 else
10109 pitch_limit = 32*1024;
10110 } else if (INTEL_INFO(dev)->gen >= 3) {
10111 if (obj->tiling_mode)
10112 pitch_limit = 8*1024;
10113 else
10114 pitch_limit = 16*1024;
10115 } else
10116 /* XXX DSPC is limited to 4k tiled */
10117 pitch_limit = 8*1024;
10118
10119 if (mode_cmd->pitches[0] > pitch_limit) {
10120 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10121 obj->tiling_mode ? "tiled" : "linear",
10122 mode_cmd->pitches[0], pitch_limit);
5d7bd705 10123 return -EINVAL;
c16ed4be 10124 }
5d7bd705
VS		 10125
10126 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 10127 mode_cmd->pitches[0] != obj->stride) {
10128 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10129 mode_cmd->pitches[0], obj->stride);
5d7bd705 10130 return -EINVAL;
c16ed4be 10131 }
5d7bd705 10132
57779d06 10133 /* Reject formats not supported by any plane early. */
308e5bcb 10134 switch (mode_cmd->pixel_format) {
57779d06 10135 case DRM_FORMAT_C8:
04b3924d
VS		 10136 case DRM_FORMAT_RGB565:
10137 case DRM_FORMAT_XRGB8888:
10138 case DRM_FORMAT_ARGB8888:
57779d06
VS		 10139 break;
10140 case DRM_FORMAT_XRGB1555:
10141 case DRM_FORMAT_ARGB1555:
c16ed4be 10142 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 10143 DRM_DEBUG("unsupported pixel format: %s\n",
10144 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10145 return -EINVAL;
c16ed4be 10146 }
57779d06
VS		 10147 break;
10148 case DRM_FORMAT_XBGR8888:
10149 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 10150 case DRM_FORMAT_XRGB2101010:
10151 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 10152 case DRM_FORMAT_XBGR2101010:
10153 case DRM_FORMAT_ABGR2101010:
c16ed4be 10154 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 10155 DRM_DEBUG("unsupported pixel format: %s\n",
10156 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10157 return -EINVAL;
c16ed4be 10158 }
b5626747 10159 break;
04b3924d
VS		 10160 case DRM_FORMAT_YUYV:
10161 case DRM_FORMAT_UYVY:
10162 case DRM_FORMAT_YVYU:
10163 case DRM_FORMAT_VYUY:
c16ed4be 10164 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 10165 DRM_DEBUG("unsupported pixel format: %s\n",
10166 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10167 return -EINVAL;
c16ed4be 10168 }
57cd6508
CW		 10169 break;
10170 default:
4ee62c76
VS		 10171 DRM_DEBUG("unsupported pixel format: %s\n",
10172 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 10173 return -EINVAL;
10174 }
10175
90f9a336
VS		 10176 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10177 if (mode_cmd->offsets[0] != 0)
10178 return -EINVAL;
10179
53155c0a
DV		 10180 tile_height = IS_GEN2(dev) ? 16 : 8;
10181 aligned_height = ALIGN(mode_cmd->height,
10182 obj->tiling_mode ? tile_height : 1);
10183 /* FIXME drm helper for size checks (especially planar formats)? */
10184 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10185 return -EINVAL;
10186
c7d73f6a
DV		 10187 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10188 intel_fb->obj = obj;
80075d49 10189 intel_fb->obj->framebuffer_references++;
c7d73f6a 10190
79e53945
JB		 10191 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10192 if (ret) {
10193 DRM_ERROR("framebuffer init failed %d\n", ret);
10194 return ret;
10195 }
10196
79e53945
JB		 10197 return 0;
10198}
10199
79e53945
JB		 10200static struct drm_framebuffer *
10201intel_user_framebuffer_create(struct drm_device *dev,
10202 struct drm_file *filp,
308e5bcb 10203 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10204{
05394f39 10205 struct drm_i915_gem_object *obj;
79e53945 10206
308e5bcb
JB		 10207 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10208 mode_cmd->handles[0]));
c8725226 10209 if (&obj->base == NULL)
cce13ff7 10210 return ERR_PTR(-ENOENT);
79e53945 10211
d2dff872 10212 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10213}
10214
4520f53a 10215#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 10216static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 10217{
10218}
10219#endif
10220
79e53945 10221static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10222 .fb_create = intel_user_framebuffer_create,
0632fef6 10223 .output_poll_changed = intel_fbdev_output_poll_changed,
79e53945
JB		 10224};
10225
e70236a8
JB		 10226/* Set up chip specific display functions */
10227static void intel_init_display(struct drm_device *dev)
10228{
10229 struct drm_i915_private *dev_priv = dev->dev_private;
10230
ee9300bb
DV		 10231 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10232 dev_priv->display.find_dpll = g4x_find_best_dpll;
10233 else if (IS_VALLEYVIEW(dev))
10234 dev_priv->display.find_dpll = vlv_find_best_dpll;
10235 else if (IS_PINEVIEW(dev))
10236 dev_priv->display.find_dpll = pnv_find_best_dpll;
10237 else
10238 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10239
affa9354 10240 if (HAS_DDI(dev)) {
0e8ffe1b 10241 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10242 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10243 dev_priv->display.crtc_enable = haswell_crtc_enable;
10244 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10245 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10246 dev_priv->display.update_plane = ironlake_update_plane;
10247 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10248 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10249 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10250 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10251 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10252 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10253 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10254 } else if (IS_VALLEYVIEW(dev)) {
10255 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10256 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10257 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10258 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10259 dev_priv->display.off = i9xx_crtc_off;
10260 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10261 } else {
0e8ffe1b 10262 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10263 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10264 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10265 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10266 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10267 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10268 }
e70236a8 10269
e70236a8 10270 /* Returns the core display clock speed */
25eb05fc
JB		 10271 if (IS_VALLEYVIEW(dev))
10272 dev_priv->display.get_display_clock_speed =
10273 valleyview_get_display_clock_speed;
10274 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10275 dev_priv->display.get_display_clock_speed =
10276 i945_get_display_clock_speed;
10277 else if (IS_I915G(dev))
10278 dev_priv->display.get_display_clock_speed =
10279 i915_get_display_clock_speed;
257a7ffc 10280 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10281 dev_priv->display.get_display_clock_speed =
10282 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10283 else if (IS_PINEVIEW(dev))
10284 dev_priv->display.get_display_clock_speed =
10285 pnv_get_display_clock_speed;
e70236a8
JB		 10286 else if (IS_I915GM(dev))
10287 dev_priv->display.get_display_clock_speed =
10288 i915gm_get_display_clock_speed;
10289 else if (IS_I865G(dev))
10290 dev_priv->display.get_display_clock_speed =
10291 i865_get_display_clock_speed;
f0f8a9ce 10292 else if (IS_I85X(dev))
e70236a8
JB		 10293 dev_priv->display.get_display_clock_speed =
10294 i855_get_display_clock_speed;
10295 else /* 852, 830 */
10296 dev_priv->display.get_display_clock_speed =
10297 i830_get_display_clock_speed;
10298
7f8a8569 10299 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10300 if (IS_GEN5(dev)) {
674cf967 10301 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10302 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10303 } else if (IS_GEN6(dev)) {
674cf967 10304 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10305 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10306 } else if (IS_IVYBRIDGE(dev)) {
10307 /* FIXME: detect B0+ stepping and use auto training */
10308 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10309 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10310 dev_priv->display.modeset_global_resources =
10311 ivb_modeset_global_resources;
c82e4d26
ED		 10312 } else if (IS_HASWELL(dev)) {
10313 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10314 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10315 dev_priv->display.modeset_global_resources =
10316 haswell_modeset_global_resources;
a0e63c22 10317 }
6067aaea 10318 } else if (IS_G4X(dev)) {
e0dac65e 10319 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10320 }
8c9f3aaf
JB		 10321
10322 /* Default just returns -ENODEV to indicate unsupported */
10323 dev_priv->display.queue_flip = intel_default_queue_flip;
10324
10325 switch (INTEL_INFO(dev)->gen) {
10326 case 2:
10327 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10328 break;
10329
10330 case 3:
10331 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10332 break;
10333
10334 case 4:
10335 case 5:
10336 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10337 break;
10338
10339 case 6:
10340 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10341 break;
7c9017e5
JB		 10342 case 7:
10343 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10344 break;
8c9f3aaf 10345 }
e70236a8
JB		 10346}
10347
b690e96c
JB		 10348/*
10349 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10350 * resume, or other times. This quirk makes sure that's the case for
10351 * affected systems.
10352 */
0206e353 10353static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10354{
10355 struct drm_i915_private *dev_priv = dev->dev_private;
10356
10357 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10358 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10359}
10360
435793df
KP		 10361/*
10362 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10363 */
10364static void quirk_ssc_force_disable(struct drm_device *dev)
10365{
10366 struct drm_i915_private *dev_priv = dev->dev_private;
10367 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10368 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10369}
10370
4dca20ef 10371/*
5a15ab5b
CE		 10372 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10373 * brightness value
4dca20ef
CE		 10374 */
10375static void quirk_invert_brightness(struct drm_device *dev)
10376{
10377 struct drm_i915_private *dev_priv = dev->dev_private;
10378 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10379 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10380}
10381
e85843be
KM		 10382/*
10383 * Some machines (Dell XPS13) suffer broken backlight controls if
10384 * BLM_PCH_PWM_ENABLE is set.
10385 */
10386static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10387{
10388 struct drm_i915_private *dev_priv = dev->dev_private;
10389 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10390 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10391}
10392
b690e96c
JB		 10393struct intel_quirk {
10394 int device;
10395 int subsystem_vendor;
10396 int subsystem_device;
10397 void (*hook)(struct drm_device *dev);
10398};
10399
5f85f176
EE		 10400/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10401struct intel_dmi_quirk {
10402 void (*hook)(struct drm_device *dev);
10403 const struct dmi_system_id (*dmi_id_list)[];
10404};
10405
10406static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10407{
10408 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10409 return 1;
10410}
10411
10412static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10413 {
10414 .dmi_id_list = &(const struct dmi_system_id[]) {
10415 {
10416 .callback = intel_dmi_reverse_brightness,
10417 .ident = "NCR Corporation",
10418 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10419 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10420 },
10421 },
10422 { } /* terminating entry */
10423 },
10424 .hook = quirk_invert_brightness,
10425 },
10426};
10427
c43b5634 10428static struct intel_quirk intel_quirks[] = {
b690e96c 10429 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10430 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10431
b690e96c
JB		 10432 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10433 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10434
b690e96c
JB		 10435 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10436 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10437
a4945f95 10438 /* 830 needs to leave pipe A & dpll A up */
dcdaed6e 10439 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10440
10441 /* Lenovo U160 cannot use SSC on LVDS */
10442 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10443
10444 /* Sony Vaio Y cannot use SSC on LVDS */
10445 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10446
ee1452d7
JN		 10447 /*
10448 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10449 * seem to use inverted backlight PWM.
10450 */
10451 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10452
10453 /* Dell XPS13 HD Sandy Bridge */
10454 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10455 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10456 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10457};
10458
10459static void intel_init_quirks(struct drm_device *dev)
10460{
10461 struct pci_dev *d = dev->pdev;
10462 int i;
10463
10464 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10465 struct intel_quirk *q = &intel_quirks[i];
10466
10467 if (d->device == q->device &&
10468 (d->subsystem_vendor == q->subsystem_vendor ||
10469 q->subsystem_vendor == PCI_ANY_ID) &&
10470 (d->subsystem_device == q->subsystem_device ||
10471 q->subsystem_device == PCI_ANY_ID))
10472 q->hook(dev);
10473 }
5f85f176
EE		 10474 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10475 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10476 intel_dmi_quirks[i].hook(dev);
10477 }
b690e96c
JB		 10478}
10479
9cce37f4
JB		 10480/* Disable the VGA plane that we never use */
10481static void i915_disable_vga(struct drm_device *dev)
10482{
10483 struct drm_i915_private *dev_priv = dev->dev_private;
10484 u8 sr1;
766aa1c4 10485 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10486
10487 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10488 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10489 sr1 = inb(VGA_SR_DATA);
10490 outb(sr1 | 1<<5, VGA_SR_DATA);
10491 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10492 udelay(300);
10493
10494 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10495 POSTING_READ(vga_reg);
10496}
10497
f817586c
DV		 10498void intel_modeset_init_hw(struct drm_device *dev)
10499{
f6071166
JB		 10500 struct drm_i915_private *dev_priv = dev->dev_private;
10501
a8f78b58
ED		 10502 intel_prepare_ddi(dev);
10503
f817586c
DV		 10504 intel_init_clock_gating(dev);
10505
f6071166
JB		 10506 /* Enable the CRI clock source so we can get at the display */
10507 if (IS_VALLEYVIEW(dev))
10508 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10509 DPLL_INTEGRATED_CRI_CLK_VLV);
10510
40e9cf64
JB		 10511 intel_init_dpio(dev);
10512
79f5b2c7 10513 mutex_lock(&dev->struct_mutex);
8090c6b9 10514 intel_enable_gt_powersave(dev);
79f5b2c7 10515 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10516}
10517
7d708ee4
ID		 10518void intel_modeset_suspend_hw(struct drm_device *dev)
10519{
10520 intel_suspend_hw(dev);
10521}
10522
79e53945
JB		 10523void intel_modeset_init(struct drm_device *dev)
10524{
652c393a 10525 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10526 int i, j, ret;
79e53945
JB		 10527
10528 drm_mode_config_init(dev);
10529
10530 dev->mode_config.min_width = 0;
10531 dev->mode_config.min_height = 0;
10532
019d96cb
DA		 10533 dev->mode_config.preferred_depth = 24;
10534 dev->mode_config.prefer_shadow = 1;
10535
e6ecefaa 10536 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10537
b690e96c
JB		 10538 intel_init_quirks(dev);
10539
1fa61106
ED		 10540 intel_init_pm(dev);
10541
e3c74757
BW		 10542 if (INTEL_INFO(dev)->num_pipes == 0)
10543 return;
10544
e70236a8
JB		 10545 intel_init_display(dev);
10546
a6c45cf0
CW		 10547 if (IS_GEN2(dev)) {
10548 dev->mode_config.max_width = 2048;
10549 dev->mode_config.max_height = 2048;
10550 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10551 dev->mode_config.max_width = 4096;
10552 dev->mode_config.max_height = 4096;
79e53945 10553 } else {
a6c45cf0
CW		 10554 dev->mode_config.max_width = 8192;
10555 dev->mode_config.max_height = 8192;
79e53945 10556 }
5d4545ae 10557 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10558
28c97730 10559 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10560 INTEL_INFO(dev)->num_pipes,
10561 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10562
08e2a7de 10563 for_each_pipe(i) {
79e53945 10564 intel_crtc_init(dev, i);
7f1f3851
JB		 10565 for (j = 0; j < dev_priv->num_plane; j++) {
10566 ret = intel_plane_init(dev, i, j);
10567 if (ret)
06da8da2
VS		 10568 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10569 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10570 }
79e53945
JB		 10571 }
10572
79f689aa 10573 intel_cpu_pll_init(dev);
e72f9fbf 10574 intel_shared_dpll_init(dev);
ee7b9f93 10575
9cce37f4
JB		 10576 /* Just disable it once at startup */
10577 i915_disable_vga(dev);
79e53945 10578 intel_setup_outputs(dev);
11be49eb
CW		 10579
10580 /* Just in case the BIOS is doing something questionable. */
10581 intel_disable_fbc(dev);
2c7111db
CW		 10582}
10583
24929352
DV		 10584static void
10585intel_connector_break_all_links(struct intel_connector *connector)
10586{
10587 connector->base.dpms = DRM_MODE_DPMS_OFF;
10588 connector->base.encoder = NULL;
10589 connector->encoder->connectors_active = false;
10590 connector->encoder->base.crtc = NULL;
10591}
10592
7fad798e
DV		 10593static void intel_enable_pipe_a(struct drm_device *dev)
10594{
10595 struct intel_connector *connector;
10596 struct drm_connector *crt = NULL;
10597 struct intel_load_detect_pipe load_detect_temp;
10598
10599 /* We can't just switch on the pipe A, we need to set things up with a
10600 * proper mode and output configuration. As a gross hack, enable pipe A
10601 * by enabling the load detect pipe once. */
10602 list_for_each_entry(connector,
10603 &dev->mode_config.connector_list,
10604 base.head) {
10605 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10606 crt = &connector->base;
10607 break;
10608 }
10609 }
10610
10611 if (!crt)
10612 return;
10613
10614 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10615 intel_release_load_detect_pipe(crt, &load_detect_temp);
10616
652c393a 10617
7fad798e
DV		 10618}
10619
fa555837
DV		 10620static bool
10621intel_check_plane_mapping(struct intel_crtc *crtc)
10622{
7eb552ae
BW		 10623 struct drm_device *dev = crtc->base.dev;
10624 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10625 u32 reg, val;
10626
7eb552ae 10627 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10628 return true;
10629
10630 reg = DSPCNTR(!crtc->plane);
10631 val = I915_READ(reg);
10632
10633 if ((val & DISPLAY_PLANE_ENABLE) &&
10634 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10635 return false;
10636
10637 return true;
10638}
10639
24929352
DV		 10640static void intel_sanitize_crtc(struct intel_crtc *crtc)
10641{
10642 struct drm_device *dev = crtc->base.dev;
10643 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10644 u32 reg;
24929352 10645
24929352 10646 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10647 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10648 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10649
10650 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10651 * disable the crtc (and hence change the state) if it is wrong. Note
10652 * that gen4+ has a fixed plane -> pipe mapping. */
10653 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10654 struct intel_connector *connector;
10655 bool plane;
10656
24929352
DV		 10657 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10658 crtc->base.base.id);
10659
10660 /* Pipe has the wrong plane attached and the plane is active.
10661 * Temporarily change the plane mapping and disable everything
10662 * ... */
10663 plane = crtc->plane;
10664 crtc->plane = !plane;
10665 dev_priv->display.crtc_disable(&crtc->base);
10666 crtc->plane = plane;
10667
10668 /* ... and break all links. */
10669 list_for_each_entry(connector, &dev->mode_config.connector_list,
10670 base.head) {
10671 if (connector->encoder->base.crtc != &crtc->base)
10672 continue;
10673
10674 intel_connector_break_all_links(connector);
10675 }
10676
10677 WARN_ON(crtc->active);
10678 crtc->base.enabled = false;
10679 }
24929352 10680
7fad798e
DV		 10681 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10682 crtc->pipe == PIPE_A && !crtc->active) {
10683 /* BIOS forgot to enable pipe A, this mostly happens after
10684 * resume. Force-enable the pipe to fix this, the update_dpms
10685 * call below we restore the pipe to the right state, but leave
10686 * the required bits on. */
10687 intel_enable_pipe_a(dev);
10688 }
10689
24929352
DV		 10690 /* Adjust the state of the output pipe according to whether we
10691 * have active connectors/encoders. */
10692 intel_crtc_update_dpms(&crtc->base);
10693
10694 if (crtc->active != crtc->base.enabled) {
10695 struct intel_encoder *encoder;
10696
10697 /* This can happen either due to bugs in the get_hw_state
10698 * functions or because the pipe is force-enabled due to the
10699 * pipe A quirk. */
10700 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10701 crtc->base.base.id,
10702 crtc->base.enabled ? "enabled" : "disabled",
10703 crtc->active ? "enabled" : "disabled");
10704
10705 crtc->base.enabled = crtc->active;
10706
10707 /* Because we only establish the connector -> encoder ->
10708 * crtc links if something is active, this means the
10709 * crtc is now deactivated. Break the links. connector
10710 * -> encoder links are only establish when things are
10711 * actually up, hence no need to break them. */
10712 WARN_ON(crtc->active);
10713
10714 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10715 WARN_ON(encoder->connectors_active);
10716 encoder->base.crtc = NULL;
10717 }
10718 }
10719}
10720
10721static void intel_sanitize_encoder(struct intel_encoder *encoder)
10722{
10723 struct intel_connector *connector;
10724 struct drm_device *dev = encoder->base.dev;
10725
10726 /* We need to check both for a crtc link (meaning that the
10727 * encoder is active and trying to read from a pipe) and the
10728 * pipe itself being active. */
10729 bool has_active_crtc = encoder->base.crtc &&
10730 to_intel_crtc(encoder->base.crtc)->active;
10731
10732 if (encoder->connectors_active && !has_active_crtc) {
10733 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10734 encoder->base.base.id,
10735 drm_get_encoder_name(&encoder->base));
10736
10737 /* Connector is active, but has no active pipe. This is
10738 * fallout from our resume register restoring. Disable
10739 * the encoder manually again. */
10740 if (encoder->base.crtc) {
10741 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10742 encoder->base.base.id,
10743 drm_get_encoder_name(&encoder->base));
10744 encoder->disable(encoder);
10745 }
10746
10747 /* Inconsistent output/port/pipe state happens presumably due to
10748 * a bug in one of the get_hw_state functions. Or someplace else
10749 * in our code, like the register restore mess on resume. Clamp
10750 * things to off as a safer default. */
10751 list_for_each_entry(connector,
10752 &dev->mode_config.connector_list,
10753 base.head) {
10754 if (connector->encoder != encoder)
10755 continue;
10756
10757 intel_connector_break_all_links(connector);
10758 }
10759 }
10760 /* Enabled encoders without active connectors will be fixed in
10761 * the crtc fixup. */
10762}
10763
44cec740 10764void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10765{
10766 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10767 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10768
8dc8a27c
PZ		 10769 /* This function can be called both from intel_modeset_setup_hw_state or
10770 * at a very early point in our resume sequence, where the power well
10771 * structures are not yet restored. Since this function is at a very
10772 * paranoid "someone might have enabled VGA while we were not looking"
10773 * level, just check if the power well is enabled instead of trying to
10774 * follow the "don't touch the power well if we don't need it" policy
10775 * the rest of the driver uses. */
10776 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10777 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10778 return;
10779
e1553faa 10780 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
0fde901f 10781 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10782 i915_disable_vga(dev);
0fde901f
KM		 10783 }
10784}
10785
30e984df 10786static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10787{
10788 struct drm_i915_private *dev_priv = dev->dev_private;
10789 enum pipe pipe;
24929352
DV		 10790 struct intel_crtc *crtc;
10791 struct intel_encoder *encoder;
10792 struct intel_connector *connector;
5358901f 10793 int i;
24929352 10794
0e8ffe1b
DV		 10795 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10796 base.head) {
88adfff1 10797 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10798
0e8ffe1b
DV		 10799 crtc->active = dev_priv->display.get_pipe_config(crtc,
10800 &crtc->config);
24929352
DV		 10801
10802 crtc->base.enabled = crtc->active;
4c445e0e 10803 crtc->primary_enabled = crtc->active;
24929352
DV		 10804
10805 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10806 crtc->base.base.id,
10807 crtc->active ? "enabled" : "disabled");
10808 }
10809
5358901f 10810 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10811 if (HAS_DDI(dev))
6441ab5f
PZ		 10812 intel_ddi_setup_hw_pll_state(dev);
10813
5358901f
DV		 10814 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10815 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10816
10817 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10818 pll->active = 0;
10819 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10820 base.head) {
10821 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10822 pll->active++;
10823 }
10824 pll->refcount = pll->active;
10825
35c95375
DV		 10826 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10827 pll->name, pll->refcount, pll->on);
5358901f
DV		 10828 }
10829
24929352
DV		 10830 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10831 base.head) {
10832 pipe = 0;
10833
10834 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10835 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10836 encoder->base.crtc = &crtc->base;
510d5f2f 10837 if (encoder->get_config)
045ac3b5 10838 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10839 } else {
10840 encoder->base.crtc = NULL;
10841 }
10842
10843 encoder->connectors_active = false;
6f2bcceb 10844 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352
DV		 10845 encoder->base.base.id,
10846 drm_get_encoder_name(&encoder->base),
10847 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 10848 pipe_name(pipe));
24929352
DV		 10849 }
10850
10851 list_for_each_entry(connector, &dev->mode_config.connector_list,
10852 base.head) {
10853 if (connector->get_hw_state(connector)) {
10854 connector->base.dpms = DRM_MODE_DPMS_ON;
10855 connector->encoder->connectors_active = true;
10856 connector->base.encoder = &connector->encoder->base;
10857 } else {
10858 connector->base.dpms = DRM_MODE_DPMS_OFF;
10859 connector->base.encoder = NULL;
10860 }
10861 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10862 connector->base.base.id,
10863 drm_get_connector_name(&connector->base),
10864 connector->base.encoder ? "enabled" : "disabled");
10865 }
30e984df
DV		 10866}
10867
10868/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10869 * and i915 state tracking structures. */
10870void intel_modeset_setup_hw_state(struct drm_device *dev,
10871 bool force_restore)
10872{
10873 struct drm_i915_private *dev_priv = dev->dev_private;
10874 enum pipe pipe;
30e984df
DV		 10875 struct intel_crtc *crtc;
10876 struct intel_encoder *encoder;
35c95375 10877 int i;
30e984df
DV		 10878
10879 intel_modeset_readout_hw_state(dev);
24929352 10880
babea61d
JB		 10881 /*
10882 * Now that we have the config, copy it to each CRTC struct
10883 * Note that this could go away if we move to using crtc_config
10884 * checking everywhere.
10885 */
10886 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10887 base.head) {
10888 if (crtc->active && i915_fastboot) {
10889 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10890
10891 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10892 crtc->base.base.id);
10893 drm_mode_debug_printmodeline(&crtc->base.mode);
10894 }
10895 }
10896
24929352
DV		 10897 /* HW state is read out, now we need to sanitize this mess. */
10898 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10899 base.head) {
10900 intel_sanitize_encoder(encoder);
10901 }
10902
10903 for_each_pipe(pipe) {
10904 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10905 intel_sanitize_crtc(crtc);
c0b03411 10906 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10907 }
9a935856 10908
35c95375
DV		 10909 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10910 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10911
10912 if (!pll->on || pll->active)
10913 continue;
10914
10915 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10916
10917 pll->disable(dev_priv, pll);
10918 pll->on = false;
10919 }
10920
243e6a44
VS		 10921 if (IS_HASWELL(dev))
10922 ilk_wm_get_hw_state(dev);
10923
45e2b5f6 10924 if (force_restore) {
7d0bc1ea
VS		 10925 i915_redisable_vga(dev);
10926
f30da187
DV		 10927 /*
10928 * We need to use raw interfaces for restoring state to avoid
10929 * checking (bogus) intermediate states.
10930 */
45e2b5f6 10931 for_each_pipe(pipe) {
b5644d05
JB		 10932 struct drm_crtc *crtc =
10933 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10934
10935 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10936 crtc->fb);
45e2b5f6
DV		 10937 }
10938 } else {
10939 intel_modeset_update_staged_output_state(dev);
10940 }
8af6cf88
DV		 10941
10942 intel_modeset_check_state(dev);
2e938892
DV		 10943
10944 drm_mode_config_reset(dev);
2c7111db
CW		 10945}
10946
10947void intel_modeset_gem_init(struct drm_device *dev)
10948{
1833b134 10949 intel_modeset_init_hw(dev);
02e792fb
DV		 10950
10951 intel_setup_overlay(dev);
24929352 10952
45e2b5f6 10953 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10954}
10955
10956void intel_modeset_cleanup(struct drm_device *dev)
10957{
652c393a
JB		 10958 struct drm_i915_private *dev_priv = dev->dev_private;
10959 struct drm_crtc *crtc;
d9255d57 10960 struct drm_connector *connector;
652c393a 10961
fd0c0642
DV		 10962 /*
10963 * Interrupts and polling as the first thing to avoid creating havoc.
10964 * Too much stuff here (turning of rps, connectors, ...) would
10965 * experience fancy races otherwise.
10966 */
10967 drm_irq_uninstall(dev);
10968 cancel_work_sync(&dev_priv->hotplug_work);
10969 /*
10970 * Due to the hpd irq storm handling the hotplug work can re-arm the
10971 * poll handlers. Hence disable polling after hpd handling is shut down.
10972 */
f87ea761 10973 drm_kms_helper_poll_fini(dev);
fd0c0642 10974
652c393a
JB		 10975 mutex_lock(&dev->struct_mutex);
10976
723bfd70
JB		 10977 intel_unregister_dsm_handler();
10978
652c393a
JB		 10979 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10980 /* Skip inactive CRTCs */
10981 if (!crtc->fb)
10982 continue;
10983
3dec0095 10984 intel_increase_pllclock(crtc);
652c393a
JB		 10985 }
10986
973d04f9 10987 intel_disable_fbc(dev);
e70236a8 10988
8090c6b9 10989 intel_disable_gt_powersave(dev);
0cdab21f 10990
930ebb46
DV		 10991 ironlake_teardown_rc6(dev);
10992
69341a5e
KH		 10993 mutex_unlock(&dev->struct_mutex);
10994
1630fe75
CW		 10995 /* flush any delayed tasks or pending work */
10996 flush_scheduled_work();
10997
dc652f90
JN		 10998 /* destroy backlight, if any, before the connectors */
10999 intel_panel_destroy_backlight(dev);
11000
d9255d57
PZ		 11001 /* destroy the sysfs files before encoders/connectors */
11002 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
11003 drm_sysfs_connector_remove(connector);
11004
79e53945 11005 drm_mode_config_cleanup(dev);
4d7bb011
DV		 11006
11007 intel_cleanup_overlay(dev);
79e53945
JB		 11008}
11009
f1c79df3
ZW		 11010/*
11011 * Return which encoder is currently attached for connector.
11012 */
df0e9248 11013struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 11014{
df0e9248
CW		 11015 return &intel_attached_encoder(connector)->base;
11016}
f1c79df3 11017
df0e9248
CW		 11018void intel_connector_attach_encoder(struct intel_connector *connector,
11019 struct intel_encoder *encoder)
11020{
11021 connector->encoder = encoder;
11022 drm_mode_connector_attach_encoder(&connector->base,
11023 &encoder->base);
79e53945 11024}
28d52043
DA		 11025
11026/*
11027 * set vga decode state - true == enable VGA decode
11028 */
11029int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11030{
11031 struct drm_i915_private *dev_priv = dev->dev_private;
11032 u16 gmch_ctrl;
11033
11034 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11035 if (state)
11036 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11037 else
11038 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11039 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11040 return 0;
11041}
c4a1d9e4 11042
c4a1d9e4 11043struct intel_display_error_state {
ff57f1b0
PZ		 11044
11045 u32 power_well_driver;
11046
63b66e5b
CW		 11047 int num_transcoders;
11048
c4a1d9e4
CW		 11049 struct intel_cursor_error_state {
11050 u32 control;
11051 u32 position;
11052 u32 base;
11053 u32 size;
52331309 11054 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 11055
11056 struct intel_pipe_error_state {
c4a1d9e4 11057 u32 source;
52331309 11058 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 11059
11060 struct intel_plane_error_state {
11061 u32 control;
11062 u32 stride;
11063 u32 size;
11064 u32 pos;
11065 u32 addr;
11066 u32 surface;
11067 u32 tile_offset;
52331309 11068 } plane[I915_MAX_PIPES];
63b66e5b
CW		 11069
11070 struct intel_transcoder_error_state {
11071 enum transcoder cpu_transcoder;
11072
11073 u32 conf;
11074
11075 u32 htotal;
11076 u32 hblank;
11077 u32 hsync;
11078 u32 vtotal;
11079 u32 vblank;
11080 u32 vsync;
11081 } transcoder[4];
c4a1d9e4
CW		 11082};
11083
11084struct intel_display_error_state *
11085intel_display_capture_error_state(struct drm_device *dev)
11086{
0206e353 11087 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 11088 struct intel_display_error_state *error;
63b66e5b
CW		 11089 int transcoders[] = {
11090 TRANSCODER_A,
11091 TRANSCODER_B,
11092 TRANSCODER_C,
11093 TRANSCODER_EDP,
11094 };
c4a1d9e4
CW		 11095 int i;
11096
63b66e5b
CW		 11097 if (INTEL_INFO(dev)->num_pipes == 0)
11098 return NULL;
11099
9d1cb914 11100 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 11101 if (error == NULL)
11102 return NULL;
11103
ff57f1b0
PZ		 11104 if (HAS_POWER_WELL(dev))
11105 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11106
52331309 11107 for_each_pipe(i) {
9d1cb914
PZ		 11108 if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i)))
11109 continue;
11110
a18c4c3d
PZ		 11111 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11112 error->cursor[i].control = I915_READ(CURCNTR(i));
11113 error->cursor[i].position = I915_READ(CURPOS(i));
11114 error->cursor[i].base = I915_READ(CURBASE(i));
11115 } else {
11116 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11117 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11118 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11119 }
c4a1d9e4
CW		 11120
11121 error->plane[i].control = I915_READ(DSPCNTR(i));
11122 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 11123 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 11124 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 11125 error->plane[i].pos = I915_READ(DSPPOS(i));
11126 }
ca291363
PZ		 11127 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11128 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 11129 if (INTEL_INFO(dev)->gen >= 4) {
11130 error->plane[i].surface = I915_READ(DSPSURF(i));
11131 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11132 }
11133
c4a1d9e4 11134 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 11135 }
11136
11137 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11138 if (HAS_DDI(dev_priv->dev))
11139 error->num_transcoders++; /* Account for eDP. */
11140
11141 for (i = 0; i < error->num_transcoders; i++) {
11142 enum transcoder cpu_transcoder = transcoders[i];
11143
9d1cb914
PZ		 11144 if (!intel_display_power_enabled(dev,
11145 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
11146 continue;
11147
63b66e5b
CW		 11148 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11149
11150 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11151 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11152 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11153 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11154 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11155 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11156 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 11157 }
11158
11159 return error;
11160}
11161
edc3d884
MK		 11162#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11163
c4a1d9e4 11164void
edc3d884 11165intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 11166 struct drm_device *dev,
11167 struct intel_display_error_state *error)
11168{
11169 int i;
11170
63b66e5b
CW		 11171 if (!error)
11172 return;
11173
edc3d884 11174 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 11175 if (HAS_POWER_WELL(dev))
edc3d884 11176 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 11177 error->power_well_driver);
52331309 11178 for_each_pipe(i) {
edc3d884 11179 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 11180 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 11181
11182 err_printf(m, "Plane [%d]:\n", i);
11183 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11184 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11185 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11186 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11187 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11188 }
4b71a570 11189 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11190 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11191 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11192 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11193 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11194 }
11195
edc3d884
MK		 11196 err_printf(m, "Cursor [%d]:\n", i);
11197 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11198 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11199 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11200 }
63b66e5b
CW		 11201
11202 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 11203 err_printf(m, "CPU transcoder: %c\n",
63b66e5b
CW		 11204 transcoder_name(error->transcoder[i].cpu_transcoder));
11205 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11206 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11207 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11208 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11209 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11210 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11211 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11212 }
c4a1d9e4 11213}
Linux kernel - Deliverables
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