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drm/i915: update VLV PLL and DPIO code v11
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
75e53986 399 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
75e53986 427 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
e2fa6fba 453void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 454{
09153000 455 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 456
a0c4da24
JB		 457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
458 DRM_ERROR("DPIO idle wait timed out\n");
09153000 459 return;
a0c4da24
JB		 460 }
461
462 I915_WRITE(DPIO_DATA, val);
463 I915_WRITE(DPIO_REG, reg);
464 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
465 DPIO_BYTE);
466 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
467 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 468}
469
1b894b59
CW		 470static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
471 int refclk)
2c07245f 472{
b91ad0ec 473 struct drm_device *dev = crtc->dev;
2c07245f 474 const intel_limit_t *limit;
b91ad0ec
ZW		 475
476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 477 if (intel_is_dual_link_lvds(dev)) {
1b894b59 478 if (refclk == 100000)
b91ad0ec
ZW		 479 limit = &intel_limits_ironlake_dual_lvds_100m;
480 else
481 limit = &intel_limits_ironlake_dual_lvds;
482 } else {
1b894b59 483 if (refclk == 100000)
b91ad0ec
ZW		 484 limit = &intel_limits_ironlake_single_lvds_100m;
485 else
486 limit = &intel_limits_ironlake_single_lvds;
487 }
488 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 489 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 490 limit = &intel_limits_ironlake_display_port;
2c07245f 491 else
b91ad0ec 492 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 493
494 return limit;
495}
496
044c7c41
ML		 497static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
498{
499 struct drm_device *dev = crtc->dev;
044c7c41
ML		 500 const intel_limit_t *limit;
501
502 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 503 if (intel_is_dual_link_lvds(dev))
e4b36699 504 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 505 else
e4b36699 506 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 507 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
508 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 509 limit = &intel_limits_g4x_hdmi;
044c7c41 510 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 511 limit = &intel_limits_g4x_sdvo;
0206e353 512 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 513 limit = &intel_limits_g4x_display_port;
044c7c41 514 } else /* The option is for other outputs */
e4b36699 515 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 516
517 return limit;
518}
519
1b894b59 520static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 521{
522 struct drm_device *dev = crtc->dev;
523 const intel_limit_t *limit;
524
bad720ff 525 if (HAS_PCH_SPLIT(dev))
1b894b59 526 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 527 else if (IS_G4X(dev)) {
044c7c41 528 limit = intel_g4x_limit(crtc);
f2b115e6 529 } else if (IS_PINEVIEW(dev)) {
2177832f 530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 531 limit = &intel_limits_pineview_lvds;
2177832f 532 else
f2b115e6 533 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 534 } else if (IS_VALLEYVIEW(dev)) {
535 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
536 limit = &intel_limits_vlv_dac;
537 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
538 limit = &intel_limits_vlv_hdmi;
539 else
540 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 541 } else if (!IS_GEN2(dev)) {
542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_i9xx_lvds;
544 else
545 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 546 } else {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 548 limit = &intel_limits_i8xx_lvds;
79e53945 549 else
e4b36699 550 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 551 }
552 return limit;
553}
554
f2b115e6
AJ		 555/* m1 is reserved as 0 in Pineview, n is a ring counter */
556static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 557{
2177832f
SL		 558 clock->m = clock->m2 + 2;
559 clock->p = clock->p1 * clock->p2;
560 clock->vco = refclk * clock->m / clock->n;
561 clock->dot = clock->vco / clock->p;
562}
563
564static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
565{
f2b115e6
AJ		 566 if (IS_PINEVIEW(dev)) {
567 pineview_clock(refclk, clock);
2177832f
SL		 568 return;
569 }
79e53945
JB		 570 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / (clock->n + 2);
573 clock->dot = clock->vco / clock->p;
574}
575
79e53945
JB		 576/**
577 * Returns whether any output on the specified pipe is of the specified type
578 */
4ef69c7a 579bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 580{
4ef69c7a 581 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 582 struct intel_encoder *encoder;
583
6c2b7c12
DV		 584 for_each_encoder_on_crtc(dev, crtc, encoder)
585 if (encoder->type == type)
4ef69c7a
CW		 586 return true;
587
588 return false;
79e53945
JB		 589}
590
7c04d1d9 591#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 592/**
593 * Returns whether the given set of divisors are valid for a given refclk with
594 * the given connectors.
595 */
596
1b894b59
CW		 597static bool intel_PLL_is_valid(struct drm_device *dev,
598 const intel_limit_t *limit,
599 const intel_clock_t *clock)
79e53945 600{
79e53945 601 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 602 INTELPllInvalid("p1 out of range\n");
79e53945 603 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 604 INTELPllInvalid("p out of range\n");
79e53945 605 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 606 INTELPllInvalid("m2 out of range\n");
79e53945 607 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 608 INTELPllInvalid("m1 out of range\n");
f2b115e6 609 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 610 INTELPllInvalid("m1 <= m2\n");
79e53945 611 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 612 INTELPllInvalid("m out of range\n");
79e53945 613 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 614 INTELPllInvalid("n out of range\n");
79e53945 615 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 616 INTELPllInvalid("vco out of range\n");
79e53945
JB		 617 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
618 * connector, etc., rather than just a single range.
619 */
620 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 621 INTELPllInvalid("dot out of range\n");
79e53945
JB		 622
623 return true;
624}
625
d4906093
ML		 626static bool
627intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 628 int target, int refclk, intel_clock_t *match_clock,
629 intel_clock_t *best_clock)
d4906093 630
79e53945
JB		 631{
632 struct drm_device *dev = crtc->dev;
79e53945 633 intel_clock_t clock;
79e53945
JB		 634 int err = target;
635
a210b028 636 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 637 /*
a210b028
DV		 638 * For LVDS just rely on its current settings for dual-channel.
639 * We haven't figured out how to reliably set up different
640 * single/dual channel state, if we even can.
79e53945 641 */
1974cad0 642 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 643 clock.p2 = limit->p2.p2_fast;
644 else
645 clock.p2 = limit->p2.p2_slow;
646 } else {
647 if (target < limit->p2.dot_limit)
648 clock.p2 = limit->p2.p2_slow;
649 else
650 clock.p2 = limit->p2.p2_fast;
651 }
652
0206e353 653 memset(best_clock, 0, sizeof(*best_clock));
79e53945 654
42158660
ZY		 655 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
656 clock.m1++) {
657 for (clock.m2 = limit->m2.min;
658 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 659 /* m1 is always 0 in Pineview */
660 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 661 break;
662 for (clock.n = limit->n.min;
663 clock.n <= limit->n.max; clock.n++) {
664 for (clock.p1 = limit->p1.min;
665 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 666 int this_err;
667
2177832f 668 intel_clock(dev, refclk, &clock);
1b894b59
CW		 669 if (!intel_PLL_is_valid(dev, limit,
670 &clock))
79e53945 671 continue;
cec2f356
SP		 672 if (match_clock &&
673 clock.p != match_clock->p)
674 continue;
79e53945
JB		 675
676 this_err = abs(clock.dot - target);
677 if (this_err < err) {
678 *best_clock = clock;
679 err = this_err;
680 }
681 }
682 }
683 }
684 }
685
686 return (err != target);
687}
688
d4906093
ML		 689static bool
690intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 691 int target, int refclk, intel_clock_t *match_clock,
692 intel_clock_t *best_clock)
d4906093
ML		 693{
694 struct drm_device *dev = crtc->dev;
d4906093
ML		 695 intel_clock_t clock;
696 int max_n;
697 bool found;
6ba770dc
AJ		 698 /* approximately equals target * 0.00585 */
699 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 700 found = false;
701
702 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 703 int lvds_reg;
704
c619eed4 705 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 706 lvds_reg = PCH_LVDS;
707 else
708 lvds_reg = LVDS;
1974cad0 709 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 710 clock.p2 = limit->p2.p2_fast;
711 else
712 clock.p2 = limit->p2.p2_slow;
713 } else {
714 if (target < limit->p2.dot_limit)
715 clock.p2 = limit->p2.p2_slow;
716 else
717 clock.p2 = limit->p2.p2_fast;
718 }
719
720 memset(best_clock, 0, sizeof(*best_clock));
721 max_n = limit->n.max;
f77f13e2 722 /* based on hardware requirement, prefer smaller n to precision */
d4906093 723 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 724 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 725 for (clock.m1 = limit->m1.max;
726 clock.m1 >= limit->m1.min; clock.m1--) {
727 for (clock.m2 = limit->m2.max;
728 clock.m2 >= limit->m2.min; clock.m2--) {
729 for (clock.p1 = limit->p1.max;
730 clock.p1 >= limit->p1.min; clock.p1--) {
731 int this_err;
732
2177832f 733 intel_clock(dev, refclk, &clock);
1b894b59
CW		 734 if (!intel_PLL_is_valid(dev, limit,
735 &clock))
d4906093 736 continue;
cec2f356
SP		 737 if (match_clock &&
738 clock.p != match_clock->p)
739 continue;
1b894b59
CW		 740
741 this_err = abs(clock.dot - target);
d4906093
ML		 742 if (this_err < err_most) {
743 *best_clock = clock;
744 err_most = this_err;
745 max_n = clock.n;
746 found = true;
747 }
748 }
749 }
750 }
751 }
2c07245f
ZW		 752 return found;
753}
754
5eb08b69 755static bool
f2b115e6 756intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 757 int target, int refclk, intel_clock_t *match_clock,
758 intel_clock_t *best_clock)
5eb08b69
ZW		 759{
760 struct drm_device *dev = crtc->dev;
761 intel_clock_t clock;
4547668a 762
5eb08b69
ZW		 763 if (target < 200000) {
764 clock.n = 1;
765 clock.p1 = 2;
766 clock.p2 = 10;
767 clock.m1 = 12;
768 clock.m2 = 9;
769 } else {
770 clock.n = 2;
771 clock.p1 = 1;
772 clock.p2 = 10;
773 clock.m1 = 14;
774 clock.m2 = 8;
775 }
776 intel_clock(dev, refclk, &clock);
777 memcpy(best_clock, &clock, sizeof(intel_clock_t));
778 return true;
779}
780
a4fc5ed6
KP		 781/* DisplayPort has only two frequencies, 162MHz and 270MHz */
782static bool
783intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 784 int target, int refclk, intel_clock_t *match_clock,
785 intel_clock_t *best_clock)
a4fc5ed6 786{
5eddb70b
CW		 787 intel_clock_t clock;
788 if (target < 200000) {
789 clock.p1 = 2;
790 clock.p2 = 10;
791 clock.n = 2;
792 clock.m1 = 23;
793 clock.m2 = 8;
794 } else {
795 clock.p1 = 1;
796 clock.p2 = 10;
797 clock.n = 1;
798 clock.m1 = 14;
799 clock.m2 = 2;
800 }
801 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
802 clock.p = (clock.p1 * clock.p2);
803 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
804 clock.vco = 0;
805 memcpy(best_clock, &clock, sizeof(intel_clock_t));
806 return true;
a4fc5ed6 807}
a0c4da24
JB		 808static bool
809intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812{
813 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
814 u32 m, n, fastclk;
815 u32 updrate, minupdate, fracbits, p;
816 unsigned long bestppm, ppm, absppm;
817 int dotclk, flag;
818
af447bd3 819 flag = 0;
a0c4da24
JB		 820 dotclk = target * 1000;
821 bestppm = 1000000;
822 ppm = absppm = 0;
823 fastclk = dotclk / (2*100);
824 updrate = 0;
825 minupdate = 19200;
826 fracbits = 1;
827 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
828 bestm1 = bestm2 = bestp1 = bestp2 = 0;
829
830 /* based on hardware requirement, prefer smaller n to precision */
831 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
832 updrate = refclk / n;
833 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
834 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
835 if (p2 > 10)
836 p2 = p2 - 1;
837 p = p1 * p2;
838 /* based on hardware requirement, prefer bigger m1,m2 values */
839 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
840 m2 = (((2*(fastclk * p * n / m1 )) +
841 refclk) / (2*refclk));
842 m = m1 * m2;
843 vco = updrate * m;
844 if (vco >= limit->vco.min && vco < limit->vco.max) {
845 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
846 absppm = (ppm > 0) ? ppm : (-ppm);
847 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
848 bestppm = 0;
849 flag = 1;
850 }
851 if (absppm < bestppm - 10) {
852 bestppm = absppm;
853 flag = 1;
854 }
855 if (flag) {
856 bestn = n;
857 bestm1 = m1;
858 bestm2 = m2;
859 bestp1 = p1;
860 bestp2 = p2;
861 flag = 0;
862 }
863 }
864 }
865 }
866 }
867 }
868 best_clock->n = bestn;
869 best_clock->m1 = bestm1;
870 best_clock->m2 = bestm2;
871 best_clock->p1 = bestp1;
872 best_clock->p2 = bestp2;
873
874 return true;
875}
a4fc5ed6 876
a5c961d1
PZ		 877enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879{
880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882
3b117c8f 883 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 884}
885
a928d536
PZ		 886static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
887{
888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 frame, frame_reg = PIPEFRAME(pipe);
890
891 frame = I915_READ(frame_reg);
892
893 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
894 DRM_DEBUG_KMS("vblank wait timed out\n");
895}
896
9d0498a2
JB		 897/**
898 * intel_wait_for_vblank - wait for vblank on a given pipe
899 * @dev: drm device
900 * @pipe: pipe to wait for
901 *
902 * Wait for vblank to occur on a given pipe. Needed for various bits of
903 * mode setting code.
904 */
905void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 906{
9d0498a2 907 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 908 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 909
a928d536
PZ		 910 if (INTEL_INFO(dev)->gen >= 5) {
911 ironlake_wait_for_vblank(dev, pipe);
912 return;
913 }
914
300387c0
CW		 915 /* Clear existing vblank status. Note this will clear any other
916 * sticky status fields as well.
917 *
918 * This races with i915_driver_irq_handler() with the result
919 * that either function could miss a vblank event. Here it is not
920 * fatal, as we will either wait upon the next vblank interrupt or
921 * timeout. Generally speaking intel_wait_for_vblank() is only
922 * called during modeset at which time the GPU should be idle and
923 * should *not* be performing page flips and thus not waiting on
924 * vblanks...
925 * Currently, the result of us stealing a vblank from the irq
926 * handler is that a single frame will be skipped during swapbuffers.
927 */
928 I915_WRITE(pipestat_reg,
929 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
930
9d0498a2 931 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 932 if (wait_for(I915_READ(pipestat_reg) &
933 PIPE_VBLANK_INTERRUPT_STATUS,
934 50))
9d0498a2
JB		 935 DRM_DEBUG_KMS("vblank wait timed out\n");
936}
937
ab7ad7f6
KP		 938/*
939 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 940 * @dev: drm device
941 * @pipe: pipe to wait for
942 *
943 * After disabling a pipe, we can't wait for vblank in the usual way,
944 * spinning on the vblank interrupt status bit, since we won't actually
945 * see an interrupt when the pipe is disabled.
946 *
ab7ad7f6
KP		 947 * On Gen4 and above:
948 * wait for the pipe register state bit to turn off
949 *
950 * Otherwise:
951 * wait for the display line value to settle (it usually
952 * ends up stopping at the start of the next frame).
58e10eb9 953 *
9d0498a2 954 */
58e10eb9 955void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 956{
957 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 958 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
959 pipe);
ab7ad7f6
KP		 960
961 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 962 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 963
964 /* Wait for the Pipe State to go off */
58e10eb9
CW		 965 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
966 100))
284637d9 967 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 968 } else {
837ba00f 969 u32 last_line, line_mask;
58e10eb9 970 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 971 unsigned long timeout = jiffies + msecs_to_jiffies(100);
972
837ba00f
PZ		 973 if (IS_GEN2(dev))
974 line_mask = DSL_LINEMASK_GEN2;
975 else
976 line_mask = DSL_LINEMASK_GEN3;
977
ab7ad7f6
KP		 978 /* Wait for the display line to settle */
979 do {
837ba00f 980 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 981 mdelay(5);
837ba00f 982 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 983 time_after(timeout, jiffies));
984 if (time_after(jiffies, timeout))
284637d9 985 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 986 }
79e53945
JB		 987}
988
b0ea7d37
DL		 989/*
990 * ibx_digital_port_connected - is the specified port connected?
991 * @dev_priv: i915 private structure
992 * @port: the port to test
993 *
994 * Returns true if @port is connected, false otherwise.
995 */
996bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
997 struct intel_digital_port *port)
998{
999 u32 bit;
1000
c36346e3
DL		 1001 if (HAS_PCH_IBX(dev_priv->dev)) {
1002 switch(port->port) {
1003 case PORT_B:
1004 bit = SDE_PORTB_HOTPLUG;
1005 break;
1006 case PORT_C:
1007 bit = SDE_PORTC_HOTPLUG;
1008 break;
1009 case PORT_D:
1010 bit = SDE_PORTD_HOTPLUG;
1011 break;
1012 default:
1013 return true;
1014 }
1015 } else {
1016 switch(port->port) {
1017 case PORT_B:
1018 bit = SDE_PORTB_HOTPLUG_CPT;
1019 break;
1020 case PORT_C:
1021 bit = SDE_PORTC_HOTPLUG_CPT;
1022 break;
1023 case PORT_D:
1024 bit = SDE_PORTD_HOTPLUG_CPT;
1025 break;
1026 default:
1027 return true;
1028 }
b0ea7d37
DL		 1029 }
1030
1031 return I915_READ(SDEISR) & bit;
1032}
1033
b24e7179
JB		 1034static const char *state_string(bool enabled)
1035{
1036 return enabled ? "on" : "off";
1037}
1038
1039/* Only for pre-ILK configs */
1040static void assert_pll(struct drm_i915_private *dev_priv,
1041 enum pipe pipe, bool state)
1042{
1043 int reg;
1044 u32 val;
1045 bool cur_state;
1046
1047 reg = DPLL(pipe);
1048 val = I915_READ(reg);
1049 cur_state = !!(val & DPLL_VCO_ENABLE);
1050 WARN(cur_state != state,
1051 "PLL state assertion failure (expected %s, current %s)\n",
1052 state_string(state), state_string(cur_state));
1053}
1054#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1055#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1056
040484af
JB		 1057/* For ILK+ */
1058static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1059 struct intel_pch_pll *pll,
1060 struct intel_crtc *crtc,
1061 bool state)
040484af 1062{
040484af
JB		 1063 u32 val;
1064 bool cur_state;
1065
9d82aa17
ED		 1066 if (HAS_PCH_LPT(dev_priv->dev)) {
1067 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1068 return;
1069 }
1070
92b27b08
CW		 1071 if (WARN (!pll,
1072 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1073 return;
ee7b9f93 1074
92b27b08
CW		 1075 val = I915_READ(pll->pll_reg);
1076 cur_state = !!(val & DPLL_VCO_ENABLE);
1077 WARN(cur_state != state,
1078 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1079 pll->pll_reg, state_string(state), state_string(cur_state), val);
1080
1081 /* Make sure the selected PLL is correctly attached to the transcoder */
1082 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1083 u32 pch_dpll;
1084
1085 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1086 cur_state = pll->pll_reg == _PCH_DPLL_B;
1087 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 1088 "PLL[%d] not attached to this transcoder %c: %08x\n",
1089 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 1090 cur_state = !!(val >> (4*crtc->pipe + 3));
1091 WARN(cur_state != state,
4bb6f1f3 1092 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 1093 pll->pll_reg == _PCH_DPLL_B,
1094 state_string(state),
4bb6f1f3 1095 pipe_name(crtc->pipe),
92b27b08
CW		 1096 val);
1097 }
d3ccbe86 1098 }
040484af 1099}
92b27b08
CW		 1100#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1101#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1102
1103static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool state)
1105{
1106 int reg;
1107 u32 val;
1108 bool cur_state;
ad80a810
PZ		 1109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110 pipe);
040484af 1111
affa9354
PZ		 1112 if (HAS_DDI(dev_priv->dev)) {
1113 /* DDI does not have a specific FDI_TX register */
ad80a810 1114 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1115 val = I915_READ(reg);
ad80a810 1116 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1117 } else {
1118 reg = FDI_TX_CTL(pipe);
1119 val = I915_READ(reg);
1120 cur_state = !!(val & FDI_TX_ENABLE);
1121 }
040484af
JB		 1122 WARN(cur_state != state,
1123 "FDI TX state assertion failure (expected %s, current %s)\n",
1124 state_string(state), state_string(cur_state));
1125}
1126#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1127#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1128
1129static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1130 enum pipe pipe, bool state)
1131{
1132 int reg;
1133 u32 val;
1134 bool cur_state;
1135
d63fa0dc
PZ		 1136 reg = FDI_RX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1157 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
1171 reg = FDI_RX_CTL(pipe);
1172 val = I915_READ(reg);
1173 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1174}
1175
ea0760cf
JB		 1176static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1177 enum pipe pipe)
1178{
1179 int pp_reg, lvds_reg;
1180 u32 val;
1181 enum pipe panel_pipe = PIPE_A;
0de3b485 1182 bool locked = true;
ea0760cf
JB		 1183
1184 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1185 pp_reg = PCH_PP_CONTROL;
1186 lvds_reg = PCH_LVDS;
1187 } else {
1188 pp_reg = PP_CONTROL;
1189 lvds_reg = LVDS;
1190 }
1191
1192 val = I915_READ(pp_reg);
1193 if (!(val & PANEL_POWER_ON) ||
1194 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1195 locked = false;
1196
1197 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1198 panel_pipe = PIPE_B;
1199
1200 WARN(panel_pipe == pipe && locked,
1201 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1202 pipe_name(pipe));
ea0760cf
JB		 1203}
1204
b840d907
JB		 1205void assert_pipe(struct drm_i915_private *dev_priv,
1206 enum pipe pipe, bool state)
b24e7179
JB		 1207{
1208 int reg;
1209 u32 val;
63d7bbe9 1210 bool cur_state;
702e7a56
PZ		 1211 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1212 pipe);
b24e7179 1213
8e636784
DV		 1214 /* if we need the pipe A quirk it must be always on */
1215 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1216 state = true;
1217
15d199ea
PZ		 1218 if (!intel_using_power_well(dev_priv->dev) &&
1219 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1220 cur_state = false;
1221 } else {
1222 reg = PIPECONF(cpu_transcoder);
1223 val = I915_READ(reg);
1224 cur_state = !!(val & PIPECONF_ENABLE);
1225 }
1226
63d7bbe9
JB		 1227 WARN(cur_state != state,
1228 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1229 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1230}
1231
931872fc
CW		 1232static void assert_plane(struct drm_i915_private *dev_priv,
1233 enum plane plane, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
931872fc 1237 bool cur_state;
b24e7179
JB		 1238
1239 reg = DSPCNTR(plane);
1240 val = I915_READ(reg);
931872fc
CW		 1241 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1242 WARN(cur_state != state,
1243 "plane %c assertion failure (expected %s, current %s)\n",
1244 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1245}
1246
931872fc
CW		 1247#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1248#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1249
b24e7179
JB		 1250static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1251 enum pipe pipe)
1252{
1253 int reg, i;
1254 u32 val;
1255 int cur_pipe;
1256
19ec1358 1257 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1258 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1259 reg = DSPCNTR(pipe);
1260 val = I915_READ(reg);
1261 WARN((val & DISPLAY_PLANE_ENABLE),
1262 "plane %c assertion failure, should be disabled but not\n",
1263 plane_name(pipe));
19ec1358 1264 return;
28c05794 1265 }
19ec1358 1266
b24e7179
JB		 1267 /* Need to check both planes against the pipe */
1268 for (i = 0; i < 2; i++) {
1269 reg = DSPCNTR(i);
1270 val = I915_READ(reg);
1271 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1272 DISPPLANE_SEL_PIPE_SHIFT;
1273 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1274 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1275 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1276 }
1277}
1278
19332d7a
JB		 1279static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe)
1281{
1282 int reg, i;
1283 u32 val;
1284
1285 if (!IS_VALLEYVIEW(dev_priv->dev))
1286 return;
1287
1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < dev_priv->num_plane; i++) {
1290 reg = SPCNTR(pipe, i);
1291 val = I915_READ(reg);
1292 WARN((val & SP_ENABLE),
06da8da2
VS		 1293 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1294 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1295 }
1296}
1297
92f2584a
JB		 1298static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1299{
1300 u32 val;
1301 bool enabled;
1302
9d82aa17
ED		 1303 if (HAS_PCH_LPT(dev_priv->dev)) {
1304 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1305 return;
1306 }
1307
92f2584a
JB		 1308 val = I915_READ(PCH_DREF_CONTROL);
1309 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310 DREF_SUPERSPREAD_SOURCE_MASK));
1311 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1312}
1313
1314static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1315 enum pipe pipe)
1316{
1317 int reg;
1318 u32 val;
1319 bool enabled;
1320
1321 reg = TRANSCONF(pipe);
1322 val = I915_READ(reg);
1323 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1324 WARN(enabled,
1325 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326 pipe_name(pipe));
92f2584a
JB		 1327}
1328
4e634389
KP		 1329static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1331{
1332 if ((val & DP_PORT_EN) == 0)
1333 return false;
1334
1335 if (HAS_PCH_CPT(dev_priv->dev)) {
1336 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1339 return false;
1340 } else {
1341 if ((val & DP_PIPE_MASK) != (pipe << 30))
1342 return false;
1343 }
1344 return true;
1345}
1346
1519b995
KP		 1347static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1348 enum pipe pipe, u32 val)
1349{
dc0fa718 1350 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1351 return false;
1352
1353 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1354 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1355 return false;
1356 } else {
dc0fa718 1357 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1358 return false;
1359 }
1360 return true;
1361}
1362
1363static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 val)
1365{
1366 if ((val & LVDS_PORT_EN) == 0)
1367 return false;
1368
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1371 return false;
1372 } else {
1373 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1374 return false;
1375 }
1376 return true;
1377}
1378
1379static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1380 enum pipe pipe, u32 val)
1381{
1382 if ((val & ADPA_DAC_ENABLE) == 0)
1383 return false;
1384 if (HAS_PCH_CPT(dev_priv->dev)) {
1385 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1386 return false;
1387 } else {
1388 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1389 return false;
1390 }
1391 return true;
1392}
1393
291906f1 1394static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1395 enum pipe pipe, int reg, u32 port_sel)
291906f1 1396{
47a05eca 1397 u32 val = I915_READ(reg);
4e634389 1398 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1399 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1400 reg, pipe_name(pipe));
de9a35ab 1401
75c5da27
DV		 1402 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1403 && (val & DP_PIPEB_SELECT),
de9a35ab 1404 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1405}
1406
1407static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, int reg)
1409{
47a05eca 1410 u32 val = I915_READ(reg);
b70ad586 1411 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1412 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1413 reg, pipe_name(pipe));
de9a35ab 1414
dc0fa718 1415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1416 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1417 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1418}
1419
1420static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe)
1422{
1423 int reg;
1424 u32 val;
291906f1 1425
f0575e92
KP		 1426 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1427 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1429
1430 reg = PCH_ADPA;
1431 val = I915_READ(reg);
b70ad586 1432 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1433 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1434 pipe_name(pipe));
291906f1
JB		 1435
1436 reg = PCH_LVDS;
1437 val = I915_READ(reg);
b70ad586 1438 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1439 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1440 pipe_name(pipe));
291906f1 1441
e2debe91
PZ		 1442 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1443 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1444 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1445}
1446
63d7bbe9
JB		 1447/**
1448 * intel_enable_pll - enable a PLL
1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to enable
1451 *
1452 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1453 * make sure the PLL reg is writable first though, since the panel write
1454 * protect mechanism may be enabled.
1455 *
1456 * Note! This is for pre-ILK only.
7434a255
TR		 1457 *
1458 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1459 */
1460static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1461{
1462 int reg;
1463 u32 val;
1464
58c6eaa2
DV		 1465 assert_pipe_disabled(dev_priv, pipe);
1466
63d7bbe9 1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
988d6ee8
PZ		 1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1521 enum intel_sbi_destination destination)
a416edef 1522{
988d6ee8 1523 u32 tmp;
a416edef 1524
09153000 1525 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1526
39fb50f6 1527 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1528 100)) {
1529 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1530 return;
a416edef
ED		 1531 }
1532
988d6ee8
PZ		 1533 I915_WRITE(SBI_ADDR, (reg << 16));
1534 I915_WRITE(SBI_DATA, value);
1535
1536 if (destination == SBI_ICLK)
1537 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1538 else
1539 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1540 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1541
39fb50f6 1542 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1543 100)) {
1544 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1545 return;
a416edef 1546 }
a416edef
ED		 1547}
1548
1549static u32
988d6ee8
PZ		 1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1551 enum intel_sbi_destination destination)
a416edef 1552{
39fb50f6 1553 u32 value = 0;
09153000 1554 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1555
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1559 return 0;
a416edef
ED		 1560 }
1561
988d6ee8
PZ		 1562 I915_WRITE(SBI_ADDR, (reg << 16));
1563
1564 if (destination == SBI_ICLK)
1565 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1566 else
1567 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1568 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1569
39fb50f6 1570 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1571 100)) {
1572 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1573 return 0;
a416edef
ED		 1574 }
1575
09153000 1576 return I915_READ(SBI_DATA);
a416edef
ED		 1577}
1578
89b667f8
JB		 1579void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1580{
1581 u32 port_mask;
1582
1583 if (!port)
1584 port_mask = DPLL_PORTB_READY_MASK;
1585 else
1586 port_mask = DPLL_PORTC_READY_MASK;
1587
1588 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1589 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1590 'B' + port, I915_READ(DPLL(0)));
1591}
1592
92f2584a 1593/**
b6b4e185 1594 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1595 * @dev_priv: i915 private structure
1596 * @pipe: pipe PLL to enable
1597 *
1598 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1599 * drives the transcoder clock.
1600 */
b6b4e185 1601static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1602{
ee7b9f93 1603 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1604 struct intel_pch_pll *pll;
92f2584a
JB		 1605 int reg;
1606 u32 val;
1607
48da64a8 1608 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1609 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1610 pll = intel_crtc->pch_pll;
1611 if (pll == NULL)
1612 return;
1613
1614 if (WARN_ON(pll->refcount == 0))
1615 return;
ee7b9f93
JB		 1616
1617 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
92f2584a
JB		 1620
1621 /* PCH refclock must be enabled first */
1622 assert_pch_refclk_enabled(dev_priv);
1623
ee7b9f93 1624 if (pll->active++ && pll->on) {
92b27b08 1625 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1626 return;
1627 }
1628
1629 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1630
1631 reg = pll->pll_reg;
92f2584a
JB		 1632 val = I915_READ(reg);
1633 val |= DPLL_VCO_ENABLE;
1634 I915_WRITE(reg, val);
1635 POSTING_READ(reg);
1636 udelay(200);
ee7b9f93
JB		 1637
1638 pll->on = true;
92f2584a
JB		 1639}
1640
ee7b9f93 1641static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1642{
ee7b9f93
JB		 1643 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1644 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1645 int reg;
ee7b9f93 1646 u32 val;
4c609cb8 1647
92f2584a
JB		 1648 /* PCH only available on ILK+ */
1649 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1650 if (pll == NULL)
1651 return;
92f2584a 1652
48da64a8
CW		 1653 if (WARN_ON(pll->refcount == 0))
1654 return;
7a419866 1655
ee7b9f93
JB		 1656 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1657 pll->pll_reg, pll->active, pll->on,
1658 intel_crtc->base.base.id);
7a419866 1659
48da64a8 1660 if (WARN_ON(pll->active == 0)) {
92b27b08 1661 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1662 return;
1663 }
1664
ee7b9f93 1665 if (--pll->active) {
92b27b08 1666 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1667 return;
ee7b9f93
JB		 1668 }
1669
1670 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1671
1672 /* Make sure transcoder isn't still depending on us */
1673 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1674
ee7b9f93 1675 reg = pll->pll_reg;
92f2584a
JB		 1676 val = I915_READ(reg);
1677 val &= ~DPLL_VCO_ENABLE;
1678 I915_WRITE(reg, val);
1679 POSTING_READ(reg);
1680 udelay(200);
ee7b9f93
JB		 1681
1682 pll->on = false;
92f2584a
JB		 1683}
1684
b8a4f404
PZ		 1685static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1686 enum pipe pipe)
040484af 1687{
23670b32 1688 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1689 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1690 uint32_t reg, val, pipeconf_val;
040484af
JB		 1691
1692 /* PCH only available on ILK+ */
1693 BUG_ON(dev_priv->info->gen < 5);
1694
1695 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1696 assert_pch_pll_enabled(dev_priv,
1697 to_intel_crtc(crtc)->pch_pll,
1698 to_intel_crtc(crtc));
040484af
JB		 1699
1700 /* FDI must be feeding us bits for PCH ports */
1701 assert_fdi_tx_enabled(dev_priv, pipe);
1702 assert_fdi_rx_enabled(dev_priv, pipe);
1703
23670b32
DV		 1704 if (HAS_PCH_CPT(dev)) {
1705 /* Workaround: Set the timing override bit before enabling the
1706 * pch transcoder. */
1707 reg = TRANS_CHICKEN2(pipe);
1708 val = I915_READ(reg);
1709 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1710 I915_WRITE(reg, val);
59c859d6 1711 }
23670b32 1712
040484af
JB		 1713 reg = TRANSCONF(pipe);
1714 val = I915_READ(reg);
5f7f726d 1715 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1716
1717 if (HAS_PCH_IBX(dev_priv->dev)) {
1718 /*
1719 * make the BPC in transcoder be consistent with
1720 * that in pipeconf reg.
1721 */
dfd07d72
DV		 1722 val &= ~PIPECONF_BPC_MASK;
1723 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1724 }
5f7f726d
PZ		 1725
1726 val &= ~TRANS_INTERLACE_MASK;
1727 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1728 if (HAS_PCH_IBX(dev_priv->dev) &&
1729 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1730 val |= TRANS_LEGACY_INTERLACED_ILK;
1731 else
1732 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1733 else
1734 val |= TRANS_PROGRESSIVE;
1735
040484af
JB		 1736 I915_WRITE(reg, val | TRANS_ENABLE);
1737 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1738 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1739}
1740
8fb033d7 1741static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1742 enum transcoder cpu_transcoder)
040484af 1743{
8fb033d7 1744 u32 val, pipeconf_val;
8fb033d7
PZ		 1745
1746 /* PCH only available on ILK+ */
1747 BUG_ON(dev_priv->info->gen < 5);
1748
8fb033d7 1749 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1750 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1751 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1752
223a6fdf
PZ		 1753 /* Workaround: set timing override bit. */
1754 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1755 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1756 I915_WRITE(_TRANSA_CHICKEN2, val);
1757
25f3ef11 1758 val = TRANS_ENABLE;
937bb610 1759 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1760
9a76b1c6
PZ		 1761 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1762 PIPECONF_INTERLACED_ILK)
a35f2679 1763 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1764 else
1765 val |= TRANS_PROGRESSIVE;
1766
25f3ef11 1767 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1768 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1769 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1770}
1771
b8a4f404
PZ		 1772static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1773 enum pipe pipe)
040484af 1774{
23670b32
DV		 1775 struct drm_device *dev = dev_priv->dev;
1776 uint32_t reg, val;
040484af
JB		 1777
1778 /* FDI relies on the transcoder */
1779 assert_fdi_tx_disabled(dev_priv, pipe);
1780 assert_fdi_rx_disabled(dev_priv, pipe);
1781
291906f1
JB		 1782 /* Ports must be off as well */
1783 assert_pch_ports_disabled(dev_priv, pipe);
1784
040484af
JB		 1785 reg = TRANSCONF(pipe);
1786 val = I915_READ(reg);
1787 val &= ~TRANS_ENABLE;
1788 I915_WRITE(reg, val);
1789 /* wait for PCH transcoder off, transcoder state */
1790 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1791 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1792
1793 if (!HAS_PCH_IBX(dev)) {
1794 /* Workaround: Clear the timing override chicken bit again. */
1795 reg = TRANS_CHICKEN2(pipe);
1796 val = I915_READ(reg);
1797 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1798 I915_WRITE(reg, val);
1799 }
040484af
JB		 1800}
1801
ab4d966c 1802static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1803{
8fb033d7
PZ		 1804 u32 val;
1805
8a52fd9f 1806 val = I915_READ(_TRANSACONF);
8fb033d7 1807 val &= ~TRANS_ENABLE;
8a52fd9f 1808 I915_WRITE(_TRANSACONF, val);
8fb033d7 1809 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1810 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1811 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1812
1813 /* Workaround: clear timing override bit. */
1814 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1815 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1816 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1817}
1818
b24e7179 1819/**
309cfea8 1820 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1821 * @dev_priv: i915 private structure
1822 * @pipe: pipe to enable
040484af 1823 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1824 *
1825 * Enable @pipe, making sure that various hardware specific requirements
1826 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1827 *
1828 * @pipe should be %PIPE_A or %PIPE_B.
1829 *
1830 * Will wait until the pipe is actually running (i.e. first vblank) before
1831 * returning.
1832 */
040484af
JB		 1833static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1834 bool pch_port)
b24e7179 1835{
702e7a56
PZ		 1836 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1837 pipe);
1a240d4d 1838 enum pipe pch_transcoder;
b24e7179
JB		 1839 int reg;
1840 u32 val;
1841
58c6eaa2
DV		 1842 assert_planes_disabled(dev_priv, pipe);
1843 assert_sprites_disabled(dev_priv, pipe);
1844
681e5811 1845 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1846 pch_transcoder = TRANSCODER_A;
1847 else
1848 pch_transcoder = pipe;
1849
b24e7179
JB		 1850 /*
1851 * A pipe without a PLL won't actually be able to drive bits from
1852 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1853 * need the check.
1854 */
1855 if (!HAS_PCH_SPLIT(dev_priv->dev))
1856 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1857 else {
1858 if (pch_port) {
1859 /* if driving the PCH, we need FDI enabled */
cc391bbb 1860 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1861 assert_fdi_tx_pll_enabled(dev_priv,
1862 (enum pipe) cpu_transcoder);
040484af
JB		 1863 }
1864 /* FIXME: assert CPU port conditions for SNB+ */
1865 }
b24e7179 1866
702e7a56 1867 reg = PIPECONF(cpu_transcoder);
b24e7179 1868 val = I915_READ(reg);
00d70b15
CW		 1869 if (val & PIPECONF_ENABLE)
1870 return;
1871
1872 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1873 intel_wait_for_vblank(dev_priv->dev, pipe);
1874}
1875
1876/**
309cfea8 1877 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1878 * @dev_priv: i915 private structure
1879 * @pipe: pipe to disable
1880 *
1881 * Disable @pipe, making sure that various hardware specific requirements
1882 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1883 *
1884 * @pipe should be %PIPE_A or %PIPE_B.
1885 *
1886 * Will wait until the pipe has shut down before returning.
1887 */
1888static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1889 enum pipe pipe)
1890{
702e7a56
PZ		 1891 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1892 pipe);
b24e7179
JB		 1893 int reg;
1894 u32 val;
1895
1896 /*
1897 * Make sure planes won't keep trying to pump pixels to us,
1898 * or we might hang the display.
1899 */
1900 assert_planes_disabled(dev_priv, pipe);
19332d7a 1901 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1902
1903 /* Don't disable pipe A or pipe A PLLs if needed */
1904 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1905 return;
1906
702e7a56 1907 reg = PIPECONF(cpu_transcoder);
b24e7179 1908 val = I915_READ(reg);
00d70b15
CW		 1909 if ((val & PIPECONF_ENABLE) == 0)
1910 return;
1911
1912 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1913 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1914}
1915
d74362c9
KP		 1916/*
1917 * Plane regs are double buffered, going from enabled->disabled needs a
1918 * trigger in order to latch. The display address reg provides this.
1919 */
6f1d69b0 1920void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1921 enum plane plane)
1922{
14f86147
DL		 1923 if (dev_priv->info->gen >= 4)
1924 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1925 else
1926 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1927}
1928
b24e7179
JB		 1929/**
1930 * intel_enable_plane - enable a display plane on a given pipe
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to enable
1933 * @pipe: pipe being fed
1934 *
1935 * Enable @plane on @pipe, making sure that @pipe is running first.
1936 */
1937static void intel_enable_plane(struct drm_i915_private *dev_priv,
1938 enum plane plane, enum pipe pipe)
1939{
1940 int reg;
1941 u32 val;
1942
1943 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1944 assert_pipe_enabled(dev_priv, pipe);
1945
1946 reg = DSPCNTR(plane);
1947 val = I915_READ(reg);
00d70b15
CW		 1948 if (val & DISPLAY_PLANE_ENABLE)
1949 return;
1950
1951 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1952 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1953 intel_wait_for_vblank(dev_priv->dev, pipe);
1954}
1955
b24e7179
JB		 1956/**
1957 * intel_disable_plane - disable a display plane
1958 * @dev_priv: i915 private structure
1959 * @plane: plane to disable
1960 * @pipe: pipe consuming the data
1961 *
1962 * Disable @plane; should be an independent operation.
1963 */
1964static void intel_disable_plane(struct drm_i915_private *dev_priv,
1965 enum plane plane, enum pipe pipe)
1966{
1967 int reg;
1968 u32 val;
1969
1970 reg = DSPCNTR(plane);
1971 val = I915_READ(reg);
00d70b15
CW		 1972 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1973 return;
1974
1975 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1976 intel_flush_display_plane(dev_priv, plane);
1977 intel_wait_for_vblank(dev_priv->dev, pipe);
1978}
1979
693db184
CW		 1980static bool need_vtd_wa(struct drm_device *dev)
1981{
1982#ifdef CONFIG_INTEL_IOMMU
1983 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1984 return true;
1985#endif
1986 return false;
1987}
1988
127bd2ac 1989int
48b956c5 1990intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1991 struct drm_i915_gem_object *obj,
919926ae 1992 struct intel_ring_buffer *pipelined)
6b95a207 1993{
ce453d81 1994 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1995 u32 alignment;
1996 int ret;
1997
05394f39 1998 switch (obj->tiling_mode) {
6b95a207 1999 case I915_TILING_NONE:
534843da
CW		 2000 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2001 alignment = 128 * 1024;
a6c45cf0 2002 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2003 alignment = 4 * 1024;
2004 else
2005 alignment = 64 * 1024;
6b95a207
KH		 2006 break;
2007 case I915_TILING_X:
2008 /* pin() will align the object as required by fence */
2009 alignment = 0;
2010 break;
2011 case I915_TILING_Y:
8bb6e959
DV		 2012 /* Despite that we check this in framebuffer_init userspace can
2013 * screw us over and change the tiling after the fact. Only
2014 * pinned buffers can't change their tiling. */
2015 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 2016 return -EINVAL;
2017 default:
2018 BUG();
2019 }
2020
693db184
CW		 2021 /* Note that the w/a also requires 64 PTE of padding following the
2022 * bo. We currently fill all unused PTE with the shadow page and so
2023 * we should always have valid PTE following the scanout preventing
2024 * the VT-d warning.
2025 */
2026 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2027 alignment = 256 * 1024;
2028
ce453d81 2029 dev_priv->mm.interruptible = false;
2da3b9b9 2030 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2031 if (ret)
ce453d81 2032 goto err_interruptible;
6b95a207
KH		 2033
2034 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2035 * fence, whereas 965+ only requires a fence if using
2036 * framebuffer compression. For simplicity, we always install
2037 * a fence as the cost is not that onerous.
2038 */
06d98131 2039 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2040 if (ret)
2041 goto err_unpin;
1690e1eb 2042
9a5a53b3 2043 i915_gem_object_pin_fence(obj);
6b95a207 2044
ce453d81 2045 dev_priv->mm.interruptible = true;
6b95a207 2046 return 0;
48b956c5
CW		 2047
2048err_unpin:
2049 i915_gem_object_unpin(obj);
ce453d81
CW		 2050err_interruptible:
2051 dev_priv->mm.interruptible = true;
48b956c5 2052 return ret;
6b95a207
KH		 2053}
2054
1690e1eb
CW		 2055void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2056{
2057 i915_gem_object_unpin_fence(obj);
2058 i915_gem_object_unpin(obj);
2059}
2060
c2c75131
DV		 2061/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2062 * is assumed to be a power-of-two. */
bc752862
CW		 2063unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2064 unsigned int tiling_mode,
2065 unsigned int cpp,
2066 unsigned int pitch)
c2c75131 2067{
bc752862
CW		 2068 if (tiling_mode != I915_TILING_NONE) {
2069 unsigned int tile_rows, tiles;
c2c75131 2070
bc752862
CW		 2071 tile_rows = *y / 8;
2072 *y %= 8;
c2c75131 2073
bc752862
CW		 2074 tiles = *x / (512/cpp);
2075 *x %= 512/cpp;
2076
2077 return tile_rows * pitch * 8 + tiles * 4096;
2078 } else {
2079 unsigned int offset;
2080
2081 offset = *y * pitch + *x * cpp;
2082 *y = 0;
2083 *x = (offset & 4095) / cpp;
2084 return offset & -4096;
2085 }
c2c75131
DV		 2086}
2087
17638cd6
JB		 2088static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2089 int x, int y)
81255565
JB		 2090{
2091 struct drm_device *dev = crtc->dev;
2092 struct drm_i915_private *dev_priv = dev->dev_private;
2093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094 struct intel_framebuffer *intel_fb;
05394f39 2095 struct drm_i915_gem_object *obj;
81255565 2096 int plane = intel_crtc->plane;
e506a0c6 2097 unsigned long linear_offset;
81255565 2098 u32 dspcntr;
5eddb70b 2099 u32 reg;
81255565
JB		 2100
2101 switch (plane) {
2102 case 0:
2103 case 1:
2104 break;
2105 default:
84f44ce7 2106 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2107 return -EINVAL;
2108 }
2109
2110 intel_fb = to_intel_framebuffer(fb);
2111 obj = intel_fb->obj;
81255565 2112
5eddb70b
CW		 2113 reg = DSPCNTR(plane);
2114 dspcntr = I915_READ(reg);
81255565
JB		 2115 /* Mask out pixel format bits in case we change it */
2116 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2117 switch (fb->pixel_format) {
2118 case DRM_FORMAT_C8:
81255565
JB		 2119 dspcntr |= DISPPLANE_8BPP;
2120 break;
57779d06
VS		 2121 case DRM_FORMAT_XRGB1555:
2122 case DRM_FORMAT_ARGB1555:
2123 dspcntr |= DISPPLANE_BGRX555;
81255565 2124 break;
57779d06
VS		 2125 case DRM_FORMAT_RGB565:
2126 dspcntr |= DISPPLANE_BGRX565;
2127 break;
2128 case DRM_FORMAT_XRGB8888:
2129 case DRM_FORMAT_ARGB8888:
2130 dspcntr |= DISPPLANE_BGRX888;
2131 break;
2132 case DRM_FORMAT_XBGR8888:
2133 case DRM_FORMAT_ABGR8888:
2134 dspcntr |= DISPPLANE_RGBX888;
2135 break;
2136 case DRM_FORMAT_XRGB2101010:
2137 case DRM_FORMAT_ARGB2101010:
2138 dspcntr |= DISPPLANE_BGRX101010;
2139 break;
2140 case DRM_FORMAT_XBGR2101010:
2141 case DRM_FORMAT_ABGR2101010:
2142 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2143 break;
2144 default:
baba133a 2145 BUG();
81255565 2146 }
57779d06 2147
a6c45cf0 2148 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2149 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2150 dspcntr |= DISPPLANE_TILED;
2151 else
2152 dspcntr &= ~DISPPLANE_TILED;
2153 }
2154
5eddb70b 2155 I915_WRITE(reg, dspcntr);
81255565 2156
e506a0c6 2157 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2158
c2c75131
DV		 2159 if (INTEL_INFO(dev)->gen >= 4) {
2160 intel_crtc->dspaddr_offset =
bc752862
CW		 2161 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2162 fb->bits_per_pixel / 8,
2163 fb->pitches[0]);
c2c75131
DV		 2164 linear_offset -= intel_crtc->dspaddr_offset;
2165 } else {
e506a0c6 2166 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2167 }
e506a0c6
DV		 2168
2169 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2170 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2171 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2172 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2173 I915_MODIFY_DISPBASE(DSPSURF(plane),
2174 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2175 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2176 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2177 } else
e506a0c6 2178 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2179 POSTING_READ(reg);
81255565 2180
17638cd6
JB		 2181 return 0;
2182}
2183
2184static int ironlake_update_plane(struct drm_crtc *crtc,
2185 struct drm_framebuffer *fb, int x, int y)
2186{
2187 struct drm_device *dev = crtc->dev;
2188 struct drm_i915_private *dev_priv = dev->dev_private;
2189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2190 struct intel_framebuffer *intel_fb;
2191 struct drm_i915_gem_object *obj;
2192 int plane = intel_crtc->plane;
e506a0c6 2193 unsigned long linear_offset;
17638cd6
JB		 2194 u32 dspcntr;
2195 u32 reg;
2196
2197 switch (plane) {
2198 case 0:
2199 case 1:
27f8227b 2200 case 2:
17638cd6
JB		 2201 break;
2202 default:
84f44ce7 2203 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2204 return -EINVAL;
2205 }
2206
2207 intel_fb = to_intel_framebuffer(fb);
2208 obj = intel_fb->obj;
2209
2210 reg = DSPCNTR(plane);
2211 dspcntr = I915_READ(reg);
2212 /* Mask out pixel format bits in case we change it */
2213 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2214 switch (fb->pixel_format) {
2215 case DRM_FORMAT_C8:
17638cd6
JB		 2216 dspcntr |= DISPPLANE_8BPP;
2217 break;
57779d06
VS		 2218 case DRM_FORMAT_RGB565:
2219 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2220 break;
57779d06
VS		 2221 case DRM_FORMAT_XRGB8888:
2222 case DRM_FORMAT_ARGB8888:
2223 dspcntr |= DISPPLANE_BGRX888;
2224 break;
2225 case DRM_FORMAT_XBGR8888:
2226 case DRM_FORMAT_ABGR8888:
2227 dspcntr |= DISPPLANE_RGBX888;
2228 break;
2229 case DRM_FORMAT_XRGB2101010:
2230 case DRM_FORMAT_ARGB2101010:
2231 dspcntr |= DISPPLANE_BGRX101010;
2232 break;
2233 case DRM_FORMAT_XBGR2101010:
2234 case DRM_FORMAT_ABGR2101010:
2235 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2236 break;
2237 default:
baba133a 2238 BUG();
17638cd6
JB		 2239 }
2240
2241 if (obj->tiling_mode != I915_TILING_NONE)
2242 dspcntr |= DISPPLANE_TILED;
2243 else
2244 dspcntr &= ~DISPPLANE_TILED;
2245
2246 /* must disable */
2247 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2248
2249 I915_WRITE(reg, dspcntr);
2250
e506a0c6 2251 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2252 intel_crtc->dspaddr_offset =
bc752862
CW		 2253 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2254 fb->bits_per_pixel / 8,
2255 fb->pitches[0]);
c2c75131 2256 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2257
e506a0c6
DV		 2258 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2259 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2260 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2261 I915_MODIFY_DISPBASE(DSPSURF(plane),
2262 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2263 if (IS_HASWELL(dev)) {
2264 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2265 } else {
2266 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2267 I915_WRITE(DSPLINOFF(plane), linear_offset);
2268 }
17638cd6
JB		 2269 POSTING_READ(reg);
2270
2271 return 0;
2272}
2273
2274/* Assume fb object is pinned & idle & fenced and just update base pointers */
2275static int
2276intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2277 int x, int y, enum mode_set_atomic state)
2278{
2279 struct drm_device *dev = crtc->dev;
2280 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2281
6b8e6ed0
CW		 2282 if (dev_priv->display.disable_fbc)
2283 dev_priv->display.disable_fbc(dev);
3dec0095 2284 intel_increase_pllclock(crtc);
81255565 2285
6b8e6ed0 2286 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2287}
2288
96a02917
VS		 2289void intel_display_handle_reset(struct drm_device *dev)
2290{
2291 struct drm_i915_private *dev_priv = dev->dev_private;
2292 struct drm_crtc *crtc;
2293
2294 /*
2295 * Flips in the rings have been nuked by the reset,
2296 * so complete all pending flips so that user space
2297 * will get its events and not get stuck.
2298 *
2299 * Also update the base address of all primary
2300 * planes to the the last fb to make sure we're
2301 * showing the correct fb after a reset.
2302 *
2303 * Need to make two loops over the crtcs so that we
2304 * don't try to grab a crtc mutex before the
2305 * pending_flip_queue really got woken up.
2306 */
2307
2308 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2310 enum plane plane = intel_crtc->plane;
2311
2312 intel_prepare_page_flip(dev, plane);
2313 intel_finish_page_flip_plane(dev, plane);
2314 }
2315
2316 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318
2319 mutex_lock(&crtc->mutex);
2320 if (intel_crtc->active)
2321 dev_priv->display.update_plane(crtc, crtc->fb,
2322 crtc->x, crtc->y);
2323 mutex_unlock(&crtc->mutex);
2324 }
2325}
2326
14667a4b
CW		 2327static int
2328intel_finish_fb(struct drm_framebuffer *old_fb)
2329{
2330 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2331 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2332 bool was_interruptible = dev_priv->mm.interruptible;
2333 int ret;
2334
14667a4b
CW		 2335 /* Big Hammer, we also need to ensure that any pending
2336 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2337 * current scanout is retired before unpinning the old
2338 * framebuffer.
2339 *
2340 * This should only fail upon a hung GPU, in which case we
2341 * can safely continue.
2342 */
2343 dev_priv->mm.interruptible = false;
2344 ret = i915_gem_object_finish_gpu(obj);
2345 dev_priv->mm.interruptible = was_interruptible;
2346
2347 return ret;
2348}
2349
198598d0
VS		 2350static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2351{
2352 struct drm_device *dev = crtc->dev;
2353 struct drm_i915_master_private *master_priv;
2354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2355
2356 if (!dev->primary->master)
2357 return;
2358
2359 master_priv = dev->primary->master->driver_priv;
2360 if (!master_priv->sarea_priv)
2361 return;
2362
2363 switch (intel_crtc->pipe) {
2364 case 0:
2365 master_priv->sarea_priv->pipeA_x = x;
2366 master_priv->sarea_priv->pipeA_y = y;
2367 break;
2368 case 1:
2369 master_priv->sarea_priv->pipeB_x = x;
2370 master_priv->sarea_priv->pipeB_y = y;
2371 break;
2372 default:
2373 break;
2374 }
2375}
2376
5c3b82e2 2377static int
3c4fdcfb 2378intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2379 struct drm_framebuffer *fb)
79e53945
JB		 2380{
2381 struct drm_device *dev = crtc->dev;
6b8e6ed0 2382 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2384 struct drm_framebuffer *old_fb;
5c3b82e2 2385 int ret;
79e53945
JB		 2386
2387 /* no fb bound */
94352cf9 2388 if (!fb) {
a5071c2f 2389 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2390 return 0;
2391 }
2392
7eb552ae 2393 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2394 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2395 plane_name(intel_crtc->plane),
2396 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2397 return -EINVAL;
79e53945
JB		 2398 }
2399
5c3b82e2 2400 mutex_lock(&dev->struct_mutex);
265db958 2401 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2402 to_intel_framebuffer(fb)->obj,
919926ae 2403 NULL);
5c3b82e2
CW		 2404 if (ret != 0) {
2405 mutex_unlock(&dev->struct_mutex);
a5071c2f 2406 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2407 return ret;
2408 }
79e53945 2409
94352cf9 2410 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2411 if (ret) {
94352cf9 2412 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2413 mutex_unlock(&dev->struct_mutex);
a5071c2f 2414 DRM_ERROR("failed to update base address\n");
4e6cfefc 2415 return ret;
79e53945 2416 }
3c4fdcfb 2417
94352cf9
DV		 2418 old_fb = crtc->fb;
2419 crtc->fb = fb;
6c4c86f5
DV		 2420 crtc->x = x;
2421 crtc->y = y;
94352cf9 2422
b7f1de28
CW		 2423 if (old_fb) {
2424 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2425 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2426 }
652c393a 2427
6b8e6ed0 2428 intel_update_fbc(dev);
5c3b82e2 2429 mutex_unlock(&dev->struct_mutex);
79e53945 2430
198598d0 2431 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2432
2433 return 0;
79e53945
JB		 2434}
2435
5e84e1a4
ZW		 2436static void intel_fdi_normal_train(struct drm_crtc *crtc)
2437{
2438 struct drm_device *dev = crtc->dev;
2439 struct drm_i915_private *dev_priv = dev->dev_private;
2440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2441 int pipe = intel_crtc->pipe;
2442 u32 reg, temp;
2443
2444 /* enable normal train */
2445 reg = FDI_TX_CTL(pipe);
2446 temp = I915_READ(reg);
61e499bf 2447 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2448 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2449 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2450 } else {
2451 temp &= ~FDI_LINK_TRAIN_NONE;
2452 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2453 }
5e84e1a4
ZW		 2454 I915_WRITE(reg, temp);
2455
2456 reg = FDI_RX_CTL(pipe);
2457 temp = I915_READ(reg);
2458 if (HAS_PCH_CPT(dev)) {
2459 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2460 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2461 } else {
2462 temp &= ~FDI_LINK_TRAIN_NONE;
2463 temp |= FDI_LINK_TRAIN_NONE;
2464 }
2465 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2466
2467 /* wait one idle pattern time */
2468 POSTING_READ(reg);
2469 udelay(1000);
357555c0
JB		 2470
2471 /* IVB wants error correction enabled */
2472 if (IS_IVYBRIDGE(dev))
2473 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2474 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2475}
2476
01a415fd
DV		 2477static void ivb_modeset_global_resources(struct drm_device *dev)
2478{
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct intel_crtc *pipe_B_crtc =
2481 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2482 struct intel_crtc *pipe_C_crtc =
2483 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2484 uint32_t temp;
2485
2486 /* When everything is off disable fdi C so that we could enable fdi B
2487 * with all lanes. XXX: This misses the case where a pipe is not using
2488 * any pch resources and so doesn't need any fdi lanes. */
2489 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2490 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2491 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2492
2493 temp = I915_READ(SOUTH_CHICKEN1);
2494 temp &= ~FDI_BC_BIFURCATION_SELECT;
2495 DRM_DEBUG_KMS("disabling fdi C rx\n");
2496 I915_WRITE(SOUTH_CHICKEN1, temp);
2497 }
2498}
2499
8db9d77b
ZW		 2500/* The FDI link training functions for ILK/Ibexpeak. */
2501static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2502{
2503 struct drm_device *dev = crtc->dev;
2504 struct drm_i915_private *dev_priv = dev->dev_private;
2505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2506 int pipe = intel_crtc->pipe;
0fc932b8 2507 int plane = intel_crtc->plane;
5eddb70b 2508 u32 reg, temp, tries;
8db9d77b 2509
0fc932b8
JB		 2510 /* FDI needs bits from pipe & plane first */
2511 assert_pipe_enabled(dev_priv, pipe);
2512 assert_plane_enabled(dev_priv, plane);
2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521 I915_READ(reg);
e1a44743
AJ		 2522 udelay(150);
2523
8db9d77b 2524 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2525 reg = FDI_TX_CTL(pipe);
2526 temp = I915_READ(reg);
77ffb597
AJ		 2527 temp &= ~(7 << 19);
2528 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2531 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2532
5eddb70b
CW		 2533 reg = FDI_RX_CTL(pipe);
2534 temp = I915_READ(reg);
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2537 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2538
2539 POSTING_READ(reg);
8db9d77b
ZW		 2540 udelay(150);
2541
5b2adf89 2542 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2543 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2544 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2545 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2546
5eddb70b 2547 reg = FDI_RX_IIR(pipe);
e1a44743 2548 for (tries = 0; tries < 5; tries++) {
5eddb70b 2549 temp = I915_READ(reg);
8db9d77b
ZW		 2550 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2551
2552 if ((temp & FDI_RX_BIT_LOCK)) {
2553 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2554 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2555 break;
2556 }
8db9d77b 2557 }
e1a44743 2558 if (tries == 5)
5eddb70b 2559 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2560
2561 /* Train 2 */
5eddb70b
CW		 2562 reg = FDI_TX_CTL(pipe);
2563 temp = I915_READ(reg);
8db9d77b
ZW		 2564 temp &= ~FDI_LINK_TRAIN_NONE;
2565 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2566 I915_WRITE(reg, temp);
8db9d77b 2567
5eddb70b
CW		 2568 reg = FDI_RX_CTL(pipe);
2569 temp = I915_READ(reg);
8db9d77b
ZW		 2570 temp &= ~FDI_LINK_TRAIN_NONE;
2571 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2572 I915_WRITE(reg, temp);
8db9d77b 2573
5eddb70b
CW		 2574 POSTING_READ(reg);
2575 udelay(150);
8db9d77b 2576
5eddb70b 2577 reg = FDI_RX_IIR(pipe);
e1a44743 2578 for (tries = 0; tries < 5; tries++) {
5eddb70b 2579 temp = I915_READ(reg);
8db9d77b
ZW		 2580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2581
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
8db9d77b 2587 }
e1a44743 2588 if (tries == 5)
5eddb70b 2589 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2590
2591 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2592
8db9d77b
ZW		 2593}
2594
0206e353 2595static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2596 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2597 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2598 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2599 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2600};
2601
2602/* The FDI link training functions for SNB/Cougarpoint. */
2603static void gen6_fdi_link_train(struct drm_crtc *crtc)
2604{
2605 struct drm_device *dev = crtc->dev;
2606 struct drm_i915_private *dev_priv = dev->dev_private;
2607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2608 int pipe = intel_crtc->pipe;
fa37d39e 2609 u32 reg, temp, i, retry;
8db9d77b 2610
e1a44743
AJ		 2611 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2612 for train result */
5eddb70b
CW		 2613 reg = FDI_RX_IMR(pipe);
2614 temp = I915_READ(reg);
e1a44743
AJ		 2615 temp &= ~FDI_RX_SYMBOL_LOCK;
2616 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2617 I915_WRITE(reg, temp);
2618
2619 POSTING_READ(reg);
e1a44743
AJ		 2620 udelay(150);
2621
8db9d77b 2622 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
77ffb597
AJ		 2625 temp &= ~(7 << 19);
2626 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2627 temp &= ~FDI_LINK_TRAIN_NONE;
2628 temp |= FDI_LINK_TRAIN_PATTERN_1;
2629 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630 /* SNB-B */
2631 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2632 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2633
d74cf324
DV		 2634 I915_WRITE(FDI_RX_MISC(pipe),
2635 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2636
5eddb70b
CW		 2637 reg = FDI_RX_CTL(pipe);
2638 temp = I915_READ(reg);
8db9d77b
ZW		 2639 if (HAS_PCH_CPT(dev)) {
2640 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2641 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2642 } else {
2643 temp &= ~FDI_LINK_TRAIN_NONE;
2644 temp |= FDI_LINK_TRAIN_PATTERN_1;
2645 }
5eddb70b
CW		 2646 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2647
2648 POSTING_READ(reg);
8db9d77b
ZW		 2649 udelay(150);
2650
0206e353 2651 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2652 reg = FDI_TX_CTL(pipe);
2653 temp = I915_READ(reg);
8db9d77b
ZW		 2654 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2655 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2656 I915_WRITE(reg, temp);
2657
2658 POSTING_READ(reg);
8db9d77b
ZW		 2659 udelay(500);
2660
fa37d39e
SP		 2661 for (retry = 0; retry < 5; retry++) {
2662 reg = FDI_RX_IIR(pipe);
2663 temp = I915_READ(reg);
2664 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2665 if (temp & FDI_RX_BIT_LOCK) {
2666 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2667 DRM_DEBUG_KMS("FDI train 1 done.\n");
2668 break;
2669 }
2670 udelay(50);
8db9d77b 2671 }
fa37d39e
SP		 2672 if (retry < 5)
2673 break;
8db9d77b
ZW		 2674 }
2675 if (i == 4)
5eddb70b 2676 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2677
2678 /* Train 2 */
5eddb70b
CW		 2679 reg = FDI_TX_CTL(pipe);
2680 temp = I915_READ(reg);
8db9d77b
ZW		 2681 temp &= ~FDI_LINK_TRAIN_NONE;
2682 temp |= FDI_LINK_TRAIN_PATTERN_2;
2683 if (IS_GEN6(dev)) {
2684 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685 /* SNB-B */
2686 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2687 }
5eddb70b 2688 I915_WRITE(reg, temp);
8db9d77b 2689
5eddb70b
CW		 2690 reg = FDI_RX_CTL(pipe);
2691 temp = I915_READ(reg);
8db9d77b
ZW		 2692 if (HAS_PCH_CPT(dev)) {
2693 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2694 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2695 } else {
2696 temp &= ~FDI_LINK_TRAIN_NONE;
2697 temp |= FDI_LINK_TRAIN_PATTERN_2;
2698 }
5eddb70b
CW		 2699 I915_WRITE(reg, temp);
2700
2701 POSTING_READ(reg);
8db9d77b
ZW		 2702 udelay(150);
2703
0206e353 2704 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2705 reg = FDI_TX_CTL(pipe);
2706 temp = I915_READ(reg);
8db9d77b
ZW		 2707 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2709 I915_WRITE(reg, temp);
2710
2711 POSTING_READ(reg);
8db9d77b
ZW		 2712 udelay(500);
2713
fa37d39e
SP		 2714 for (retry = 0; retry < 5; retry++) {
2715 reg = FDI_RX_IIR(pipe);
2716 temp = I915_READ(reg);
2717 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2718 if (temp & FDI_RX_SYMBOL_LOCK) {
2719 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2720 DRM_DEBUG_KMS("FDI train 2 done.\n");
2721 break;
2722 }
2723 udelay(50);
8db9d77b 2724 }
fa37d39e
SP		 2725 if (retry < 5)
2726 break;
8db9d77b
ZW		 2727 }
2728 if (i == 4)
5eddb70b 2729 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2730
2731 DRM_DEBUG_KMS("FDI train done.\n");
2732}
2733
357555c0
JB		 2734/* Manual link training for Ivy Bridge A0 parts */
2735static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2736{
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int pipe = intel_crtc->pipe;
2741 u32 reg, temp, i;
2742
2743 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2744 for train result */
2745 reg = FDI_RX_IMR(pipe);
2746 temp = I915_READ(reg);
2747 temp &= ~FDI_RX_SYMBOL_LOCK;
2748 temp &= ~FDI_RX_BIT_LOCK;
2749 I915_WRITE(reg, temp);
2750
2751 POSTING_READ(reg);
2752 udelay(150);
2753
01a415fd
DV		 2754 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2755 I915_READ(FDI_RX_IIR(pipe)));
2756
357555c0
JB		 2757 /* enable CPU FDI TX and PCH FDI RX */
2758 reg = FDI_TX_CTL(pipe);
2759 temp = I915_READ(reg);
2760 temp &= ~(7 << 19);
2761 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2762 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2763 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2764 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2765 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2766 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2767 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2768
d74cf324
DV		 2769 I915_WRITE(FDI_RX_MISC(pipe),
2770 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2771
357555c0
JB		 2772 reg = FDI_RX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_AUTO;
2775 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2776 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2777 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2778 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2779
2780 POSTING_READ(reg);
2781 udelay(150);
2782
0206e353 2783 for (i = 0; i < 4; i++) {
357555c0
JB		 2784 reg = FDI_TX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2787 temp |= snb_b_fdi_train_param[i];
2788 I915_WRITE(reg, temp);
2789
2790 POSTING_READ(reg);
2791 udelay(500);
2792
2793 reg = FDI_RX_IIR(pipe);
2794 temp = I915_READ(reg);
2795 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2796
2797 if (temp & FDI_RX_BIT_LOCK ||
2798 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2799 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2800 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2801 break;
2802 }
2803 }
2804 if (i == 4)
2805 DRM_ERROR("FDI train 1 fail!\n");
2806
2807 /* Train 2 */
2808 reg = FDI_TX_CTL(pipe);
2809 temp = I915_READ(reg);
2810 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2811 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2812 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2813 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2814 I915_WRITE(reg, temp);
2815
2816 reg = FDI_RX_CTL(pipe);
2817 temp = I915_READ(reg);
2818 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2820 I915_WRITE(reg, temp);
2821
2822 POSTING_READ(reg);
2823 udelay(150);
2824
0206e353 2825 for (i = 0; i < 4; i++) {
357555c0
JB		 2826 reg = FDI_TX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2829 temp |= snb_b_fdi_train_param[i];
2830 I915_WRITE(reg, temp);
2831
2832 POSTING_READ(reg);
2833 udelay(500);
2834
2835 reg = FDI_RX_IIR(pipe);
2836 temp = I915_READ(reg);
2837 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2838
2839 if (temp & FDI_RX_SYMBOL_LOCK) {
2840 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2841 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2842 break;
2843 }
2844 }
2845 if (i == 4)
2846 DRM_ERROR("FDI train 2 fail!\n");
2847
2848 DRM_DEBUG_KMS("FDI train done.\n");
2849}
2850
88cefb6c 2851static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2852{
88cefb6c 2853 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2854 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2855 int pipe = intel_crtc->pipe;
5eddb70b 2856 u32 reg, temp;
79e53945 2857
c64e311e 2858
c98e9dcf 2859 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2860 reg = FDI_RX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2863 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2864 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2865 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2866
2867 POSTING_READ(reg);
c98e9dcf
JB		 2868 udelay(200);
2869
2870 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2871 temp = I915_READ(reg);
2872 I915_WRITE(reg, temp | FDI_PCDCLK);
2873
2874 POSTING_READ(reg);
c98e9dcf
JB		 2875 udelay(200);
2876
20749730
PZ		 2877 /* Enable CPU FDI TX PLL, always on for Ironlake */
2878 reg = FDI_TX_CTL(pipe);
2879 temp = I915_READ(reg);
2880 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2881 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2882
20749730
PZ		 2883 POSTING_READ(reg);
2884 udelay(100);
6be4a607 2885 }
0e23b99d
JB		 2886}
2887
88cefb6c
DV		 2888static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2889{
2890 struct drm_device *dev = intel_crtc->base.dev;
2891 struct drm_i915_private *dev_priv = dev->dev_private;
2892 int pipe = intel_crtc->pipe;
2893 u32 reg, temp;
2894
2895 /* Switch from PCDclk to Rawclk */
2896 reg = FDI_RX_CTL(pipe);
2897 temp = I915_READ(reg);
2898 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2899
2900 /* Disable CPU FDI TX PLL */
2901 reg = FDI_TX_CTL(pipe);
2902 temp = I915_READ(reg);
2903 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2904
2905 POSTING_READ(reg);
2906 udelay(100);
2907
2908 reg = FDI_RX_CTL(pipe);
2909 temp = I915_READ(reg);
2910 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2911
2912 /* Wait for the clocks to turn off. */
2913 POSTING_READ(reg);
2914 udelay(100);
2915}
2916
0fc932b8
JB		 2917static void ironlake_fdi_disable(struct drm_crtc *crtc)
2918{
2919 struct drm_device *dev = crtc->dev;
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2922 int pipe = intel_crtc->pipe;
2923 u32 reg, temp;
2924
2925 /* disable CPU FDI tx and PCH FDI rx */
2926 reg = FDI_TX_CTL(pipe);
2927 temp = I915_READ(reg);
2928 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2929 POSTING_READ(reg);
2930
2931 reg = FDI_RX_CTL(pipe);
2932 temp = I915_READ(reg);
2933 temp &= ~(0x7 << 16);
dfd07d72 2934 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2935 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2936
2937 POSTING_READ(reg);
2938 udelay(100);
2939
2940 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2941 if (HAS_PCH_IBX(dev)) {
2942 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2943 }
0fc932b8
JB		 2944
2945 /* still set train pattern 1 */
2946 reg = FDI_TX_CTL(pipe);
2947 temp = I915_READ(reg);
2948 temp &= ~FDI_LINK_TRAIN_NONE;
2949 temp |= FDI_LINK_TRAIN_PATTERN_1;
2950 I915_WRITE(reg, temp);
2951
2952 reg = FDI_RX_CTL(pipe);
2953 temp = I915_READ(reg);
2954 if (HAS_PCH_CPT(dev)) {
2955 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2956 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2957 } else {
2958 temp &= ~FDI_LINK_TRAIN_NONE;
2959 temp |= FDI_LINK_TRAIN_PATTERN_1;
2960 }
2961 /* BPC in FDI rx is consistent with that in PIPECONF */
2962 temp &= ~(0x07 << 16);
dfd07d72 2963 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2964 I915_WRITE(reg, temp);
2965
2966 POSTING_READ(reg);
2967 udelay(100);
2968}
2969
5bb61643
CW		 2970static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2971{
2972 struct drm_device *dev = crtc->dev;
2973 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2975 unsigned long flags;
2976 bool pending;
2977
10d83730
VS		 2978 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2979 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2980 return false;
2981
2982 spin_lock_irqsave(&dev->event_lock, flags);
2983 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2984 spin_unlock_irqrestore(&dev->event_lock, flags);
2985
2986 return pending;
2987}
2988
e6c3a2a6
CW		 2989static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2990{
0f91128d 2991 struct drm_device *dev = crtc->dev;
5bb61643 2992 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2993
2994 if (crtc->fb == NULL)
2995 return;
2996
2c10d571
DV		 2997 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2998
5bb61643
CW		 2999 wait_event(dev_priv->pending_flip_queue,
3000 !intel_crtc_has_pending_flip(crtc));
3001
0f91128d
CW		 3002 mutex_lock(&dev->struct_mutex);
3003 intel_finish_fb(crtc->fb);
3004 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 3005}
3006
e615efe4
ED		 3007/* Program iCLKIP clock to the desired frequency */
3008static void lpt_program_iclkip(struct drm_crtc *crtc)
3009{
3010 struct drm_device *dev = crtc->dev;
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3013 u32 temp;
3014
09153000
DV		 3015 mutex_lock(&dev_priv->dpio_lock);
3016
e615efe4
ED		 3017 /* It is necessary to ungate the pixclk gate prior to programming
3018 * the divisors, and gate it back when it is done.
3019 */
3020 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3021
3022 /* Disable SSCCTL */
3023 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3024 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3025 SBI_SSCCTL_DISABLE,
3026 SBI_ICLK);
e615efe4
ED		 3027
3028 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3029 if (crtc->mode.clock == 20000) {
3030 auxdiv = 1;
3031 divsel = 0x41;
3032 phaseinc = 0x20;
3033 } else {
3034 /* The iCLK virtual clock root frequency is in MHz,
3035 * but the crtc->mode.clock in in KHz. To get the divisors,
3036 * it is necessary to divide one by another, so we
3037 * convert the virtual clock precision to KHz here for higher
3038 * precision.
3039 */
3040 u32 iclk_virtual_root_freq = 172800 * 1000;
3041 u32 iclk_pi_range = 64;
3042 u32 desired_divisor, msb_divisor_value, pi_value;
3043
3044 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3045 msb_divisor_value = desired_divisor / iclk_pi_range;
3046 pi_value = desired_divisor % iclk_pi_range;
3047
3048 auxdiv = 0;
3049 divsel = msb_divisor_value - 2;
3050 phaseinc = pi_value;
3051 }
3052
3053 /* This should not happen with any sane values */
3054 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3055 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3056 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3057 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3058
3059 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3060 crtc->mode.clock,
3061 auxdiv,
3062 divsel,
3063 phasedir,
3064 phaseinc);
3065
3066 /* Program SSCDIVINTPHASE6 */
988d6ee8 3067 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3068 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3069 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3070 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3071 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3072 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3073 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3074 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3075
3076 /* Program SSCAUXDIV */
988d6ee8 3077 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3078 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3079 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3080 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3081
3082 /* Enable modulator and associated divider */
988d6ee8 3083 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3084 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3085 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3086
3087 /* Wait for initialization time */
3088 udelay(24);
3089
3090 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3091
3092 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3093}
3094
f67a559d
JB		 3095/*
3096 * Enable PCH resources required for PCH ports:
3097 * - PCH PLLs
3098 * - FDI training & RX/TX
3099 * - update transcoder timings
3100 * - DP transcoding bits
3101 * - transcoder
3102 */
3103static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3104{
3105 struct drm_device *dev = crtc->dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3108 int pipe = intel_crtc->pipe;
ee7b9f93 3109 u32 reg, temp;
2c07245f 3110
e7e164db
CW		 3111 assert_transcoder_disabled(dev_priv, pipe);
3112
cd986abb
DV		 3113 /* Write the TU size bits before fdi link training, so that error
3114 * detection works. */
3115 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3116 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3117
c98e9dcf 3118 /* For PCH output, training FDI link */
674cf967 3119 dev_priv->display.fdi_link_train(crtc);
2c07245f 3120
572deb37
DV		 3121 /* XXX: pch pll's can be enabled any time before we enable the PCH
3122 * transcoder, and we actually should do this to not upset any PCH
3123 * transcoder that already use the clock when we share it.
3124 *
3125 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3126 * unconditionally resets the pll - we need that to have the right LVDS
3127 * enable sequence. */
b6b4e185 3128 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3129
303b81e0 3130 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3131 u32 sel;
4b645f14 3132
c98e9dcf 3133 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3134 switch (pipe) {
3135 default:
3136 case 0:
3137 temp |= TRANSA_DPLL_ENABLE;
3138 sel = TRANSA_DPLLB_SEL;
3139 break;
3140 case 1:
3141 temp |= TRANSB_DPLL_ENABLE;
3142 sel = TRANSB_DPLLB_SEL;
3143 break;
3144 case 2:
3145 temp |= TRANSC_DPLL_ENABLE;
3146 sel = TRANSC_DPLLB_SEL;
3147 break;
d64311ab 3148 }
ee7b9f93
JB		 3149 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3150 temp |= sel;
3151 else
3152 temp &= ~sel;
c98e9dcf 3153 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3154 }
5eddb70b 3155
d9b6cb56
JB		 3156 /* set transcoder timing, panel must allow it */
3157 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3158 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3159 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3160 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3161
5eddb70b
CW		 3162 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3163 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3164 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3165 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3166
303b81e0 3167 intel_fdi_normal_train(crtc);
5e84e1a4 3168
c98e9dcf
JB		 3169 /* For PCH DP, enable TRANS_DP_CTL */
3170 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3171 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3172 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3173 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3174 reg = TRANS_DP_CTL(pipe);
3175 temp = I915_READ(reg);
3176 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3177 TRANS_DP_SYNC_MASK |
3178 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3179 temp |= (TRANS_DP_OUTPUT_ENABLE |
3180 TRANS_DP_ENH_FRAMING);
9325c9f0 3181 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3182
3183 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3184 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3185 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3186 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3187
3188 switch (intel_trans_dp_port_sel(crtc)) {
3189 case PCH_DP_B:
5eddb70b 3190 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3191 break;
3192 case PCH_DP_C:
5eddb70b 3193 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3194 break;
3195 case PCH_DP_D:
5eddb70b 3196 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3197 break;
3198 default:
e95d41e1 3199 BUG();
32f9d658 3200 }
2c07245f 3201
5eddb70b 3202 I915_WRITE(reg, temp);
6be4a607 3203 }
b52eb4dc 3204
b8a4f404 3205 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3206}
3207
1507e5bd
PZ		 3208static void lpt_pch_enable(struct drm_crtc *crtc)
3209{
3210 struct drm_device *dev = crtc->dev;
3211 struct drm_i915_private *dev_priv = dev->dev_private;
3212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3213 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3214
daed2dbb 3215 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3216
8c52b5e8 3217 lpt_program_iclkip(crtc);
1507e5bd 3218
0540e488 3219 /* Set transcoder timing. */
daed2dbb
PZ		 3220 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3221 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3222 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3223
daed2dbb
PZ		 3224 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3225 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3226 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3227 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3228
937bb610 3229 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3230}
3231
ee7b9f93
JB		 3232static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3233{
3234 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3235
3236 if (pll == NULL)
3237 return;
3238
3239 if (pll->refcount == 0) {
3240 WARN(1, "bad PCH PLL refcount\n");
3241 return;
3242 }
3243
3244 --pll->refcount;
3245 intel_crtc->pch_pll = NULL;
3246}
3247
3248static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3249{
3250 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3251 struct intel_pch_pll *pll;
3252 int i;
3253
3254 pll = intel_crtc->pch_pll;
3255 if (pll) {
3256 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3257 intel_crtc->base.base.id, pll->pll_reg);
3258 goto prepare;
3259 }
3260
98b6bd99
DV		 3261 if (HAS_PCH_IBX(dev_priv->dev)) {
3262 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3263 i = intel_crtc->pipe;
3264 pll = &dev_priv->pch_plls[i];
3265
3266 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3267 intel_crtc->base.base.id, pll->pll_reg);
3268
3269 goto found;
3270 }
3271
ee7b9f93
JB		 3272 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3273 pll = &dev_priv->pch_plls[i];
3274
3275 /* Only want to check enabled timings first */
3276 if (pll->refcount == 0)
3277 continue;
3278
3279 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3280 fp == I915_READ(pll->fp0_reg)) {
3281 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3282 intel_crtc->base.base.id,
3283 pll->pll_reg, pll->refcount, pll->active);
3284
3285 goto found;
3286 }
3287 }
3288
3289 /* Ok no matching timings, maybe there's a free one? */
3290 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3291 pll = &dev_priv->pch_plls[i];
3292 if (pll->refcount == 0) {
3293 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3294 intel_crtc->base.base.id, pll->pll_reg);
3295 goto found;
3296 }
3297 }
3298
3299 return NULL;
3300
3301found:
3302 intel_crtc->pch_pll = pll;
3303 pll->refcount++;
84f44ce7 3304 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3305prepare: /* separate function? */
3306 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3307
e04c7350
CW		 3308 /* Wait for the clocks to stabilize before rewriting the regs */
3309 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3310 POSTING_READ(pll->pll_reg);
3311 udelay(150);
e04c7350
CW		 3312
3313 I915_WRITE(pll->fp0_reg, fp);
3314 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3315 pll->on = false;
3316 return pll;
3317}
3318
d4270e57
JB		 3319void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3320{
3321 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3322 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3323 u32 temp;
3324
3325 temp = I915_READ(dslreg);
3326 udelay(500);
3327 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3328 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3329 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3330 }
3331}
3332
f67a559d
JB		 3333static void ironlake_crtc_enable(struct drm_crtc *crtc)
3334{
3335 struct drm_device *dev = crtc->dev;
3336 struct drm_i915_private *dev_priv = dev->dev_private;
3337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3338 struct intel_encoder *encoder;
f67a559d
JB		 3339 int pipe = intel_crtc->pipe;
3340 int plane = intel_crtc->plane;
3341 u32 temp;
f67a559d 3342
08a48469
DV		 3343 WARN_ON(!crtc->enabled);
3344
f67a559d
JB		 3345 if (intel_crtc->active)
3346 return;
3347
3348 intel_crtc->active = true;
3349 intel_update_watermarks(dev);
3350
3351 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3352 temp = I915_READ(PCH_LVDS);
3353 if ((temp & LVDS_PORT_EN) == 0)
3354 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3355 }
3356
f67a559d 3357
5bfe2ac0 3358 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3359 /* Note: FDI PLL enabling _must_ be done before we enable the
3360 * cpu pipes, hence this is separate from all the other fdi/pch
3361 * enabling. */
88cefb6c 3362 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3363 } else {
3364 assert_fdi_tx_disabled(dev_priv, pipe);
3365 assert_fdi_rx_disabled(dev_priv, pipe);
3366 }
f67a559d 3367
bf49ec8c
DV		 3368 for_each_encoder_on_crtc(dev, crtc, encoder)
3369 if (encoder->pre_enable)
3370 encoder->pre_enable(encoder);
f67a559d
JB		 3371
3372 /* Enable panel fitting for LVDS */
3373 if (dev_priv->pch_pf_size &&
547dc041
JN		 3374 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3375 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3376 /* Force use of hard-coded filter coefficients
3377 * as some pre-programmed values are broken,
3378 * e.g. x201.
3379 */
13888d78
PZ		 3380 if (IS_IVYBRIDGE(dev))
3381 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3382 PF_PIPE_SEL_IVB(pipe));
3383 else
3384 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3385 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3386 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3387 }
3388
9c54c0dd
JB		 3389 /*
3390 * On ILK+ LUT must be loaded before the pipe is running but with
3391 * clocks enabled
3392 */
3393 intel_crtc_load_lut(crtc);
3394
5bfe2ac0
DV		 3395 intel_enable_pipe(dev_priv, pipe,
3396 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3397 intel_enable_plane(dev_priv, plane, pipe);
3398
5bfe2ac0 3399 if (intel_crtc->config.has_pch_encoder)
f67a559d 3400 ironlake_pch_enable(crtc);
c98e9dcf 3401
d1ebd816 3402 mutex_lock(&dev->struct_mutex);
bed4a673 3403 intel_update_fbc(dev);
d1ebd816
BW		 3404 mutex_unlock(&dev->struct_mutex);
3405
6b383a7f 3406 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3407
fa5c73b1
DV		 3408 for_each_encoder_on_crtc(dev, crtc, encoder)
3409 encoder->enable(encoder);
61b77ddd
DV		 3410
3411 if (HAS_PCH_CPT(dev))
3412 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3413
3414 /*
3415 * There seems to be a race in PCH platform hw (at least on some
3416 * outputs) where an enabled pipe still completes any pageflip right
3417 * away (as if the pipe is off) instead of waiting for vblank. As soon
3418 * as the first vblank happend, everything works as expected. Hence just
3419 * wait for one vblank before returning to avoid strange things
3420 * happening.
3421 */
3422 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3423}
3424
4f771f10
PZ		 3425static void haswell_crtc_enable(struct drm_crtc *crtc)
3426{
3427 struct drm_device *dev = crtc->dev;
3428 struct drm_i915_private *dev_priv = dev->dev_private;
3429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3430 struct intel_encoder *encoder;
3431 int pipe = intel_crtc->pipe;
3432 int plane = intel_crtc->plane;
4f771f10
PZ		 3433
3434 WARN_ON(!crtc->enabled);
3435
3436 if (intel_crtc->active)
3437 return;
3438
3439 intel_crtc->active = true;
3440 intel_update_watermarks(dev);
3441
5bfe2ac0 3442 if (intel_crtc->config.has_pch_encoder)
04945641 3443 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3444
3445 for_each_encoder_on_crtc(dev, crtc, encoder)
3446 if (encoder->pre_enable)
3447 encoder->pre_enable(encoder);
3448
1f544388 3449 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3450
1f544388 3451 /* Enable panel fitting for eDP */
547dc041
JN		 3452 if (dev_priv->pch_pf_size &&
3453 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3454 /* Force use of hard-coded filter coefficients
3455 * as some pre-programmed values are broken,
3456 * e.g. x201.
3457 */
54075a7d
PZ		 3458 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3459 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3460 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3461 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3462 }
3463
3464 /*
3465 * On ILK+ LUT must be loaded before the pipe is running but with
3466 * clocks enabled
3467 */
3468 intel_crtc_load_lut(crtc);
3469
1f544388 3470 intel_ddi_set_pipe_settings(crtc);
8228c251 3471 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3472
5bfe2ac0
DV		 3473 intel_enable_pipe(dev_priv, pipe,
3474 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3475 intel_enable_plane(dev_priv, plane, pipe);
3476
5bfe2ac0 3477 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3478 lpt_pch_enable(crtc);
4f771f10
PZ		 3479
3480 mutex_lock(&dev->struct_mutex);
3481 intel_update_fbc(dev);
3482 mutex_unlock(&dev->struct_mutex);
3483
3484 intel_crtc_update_cursor(crtc, true);
3485
3486 for_each_encoder_on_crtc(dev, crtc, encoder)
3487 encoder->enable(encoder);
3488
4f771f10
PZ		 3489 /*
3490 * There seems to be a race in PCH platform hw (at least on some
3491 * outputs) where an enabled pipe still completes any pageflip right
3492 * away (as if the pipe is off) instead of waiting for vblank. As soon
3493 * as the first vblank happend, everything works as expected. Hence just
3494 * wait for one vblank before returning to avoid strange things
3495 * happening.
3496 */
3497 intel_wait_for_vblank(dev, intel_crtc->pipe);
3498}
3499
6be4a607
JB		 3500static void ironlake_crtc_disable(struct drm_crtc *crtc)
3501{
3502 struct drm_device *dev = crtc->dev;
3503 struct drm_i915_private *dev_priv = dev->dev_private;
3504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3505 struct intel_encoder *encoder;
6be4a607
JB		 3506 int pipe = intel_crtc->pipe;
3507 int plane = intel_crtc->plane;
5eddb70b 3508 u32 reg, temp;
b52eb4dc 3509
ef9c3aee 3510
f7abfe8b
CW		 3511 if (!intel_crtc->active)
3512 return;
3513
ea9d758d
DV		 3514 for_each_encoder_on_crtc(dev, crtc, encoder)
3515 encoder->disable(encoder);
3516
e6c3a2a6 3517 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3518 drm_vblank_off(dev, pipe);
6b383a7f 3519 intel_crtc_update_cursor(crtc, false);
5eddb70b 3520
b24e7179 3521 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3522
973d04f9
CW		 3523 if (dev_priv->cfb_plane == plane)
3524 intel_disable_fbc(dev);
2c07245f 3525
b24e7179 3526 intel_disable_pipe(dev_priv, pipe);
32f9d658 3527
6be4a607 3528 /* Disable PF */
9db4a9c7
JB		 3529 I915_WRITE(PF_CTL(pipe), 0);
3530 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3531
bf49ec8c
DV		 3532 for_each_encoder_on_crtc(dev, crtc, encoder)
3533 if (encoder->post_disable)
3534 encoder->post_disable(encoder);
2c07245f 3535
0fc932b8 3536 ironlake_fdi_disable(crtc);
249c0e64 3537
b8a4f404 3538 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3539
6be4a607
JB		 3540 if (HAS_PCH_CPT(dev)) {
3541 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3542 reg = TRANS_DP_CTL(pipe);
3543 temp = I915_READ(reg);
3544 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3545 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3546 I915_WRITE(reg, temp);
6be4a607
JB		 3547
3548 /* disable DPLL_SEL */
3549 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3550 switch (pipe) {
3551 case 0:
d64311ab 3552 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3553 break;
3554 case 1:
6be4a607 3555 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3556 break;
3557 case 2:
4b645f14 3558 /* C shares PLL A or B */
d64311ab 3559 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3560 break;
3561 default:
3562 BUG(); /* wtf */
3563 }
6be4a607 3564 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3565 }
e3421a18 3566
6be4a607 3567 /* disable PCH DPLL */
ee7b9f93 3568 intel_disable_pch_pll(intel_crtc);
8db9d77b 3569
88cefb6c 3570 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3571
f7abfe8b 3572 intel_crtc->active = false;
6b383a7f 3573 intel_update_watermarks(dev);
d1ebd816
BW		 3574
3575 mutex_lock(&dev->struct_mutex);
6b383a7f 3576 intel_update_fbc(dev);
d1ebd816 3577 mutex_unlock(&dev->struct_mutex);
6be4a607 3578}
1b3c7a47 3579
4f771f10 3580static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3581{
4f771f10
PZ		 3582 struct drm_device *dev = crtc->dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3585 struct intel_encoder *encoder;
3586 int pipe = intel_crtc->pipe;
3587 int plane = intel_crtc->plane;
3b117c8f 3588 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3589
4f771f10
PZ		 3590 if (!intel_crtc->active)
3591 return;
3592
3593 for_each_encoder_on_crtc(dev, crtc, encoder)
3594 encoder->disable(encoder);
3595
3596 intel_crtc_wait_for_pending_flips(crtc);
3597 drm_vblank_off(dev, pipe);
3598 intel_crtc_update_cursor(crtc, false);
3599
3600 intel_disable_plane(dev_priv, plane, pipe);
3601
3602 if (dev_priv->cfb_plane == plane)
3603 intel_disable_fbc(dev);
3604
3605 intel_disable_pipe(dev_priv, pipe);
3606
ad80a810 3607 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3608
f7708f78
PZ		 3609 /* XXX: Once we have proper panel fitter state tracking implemented with
3610 * hardware state read/check support we should switch to only disable
3611 * the panel fitter when we know it's used. */
3612 if (intel_using_power_well(dev)) {
3613 I915_WRITE(PF_CTL(pipe), 0);
3614 I915_WRITE(PF_WIN_SZ(pipe), 0);
3615 }
4f771f10 3616
1f544388 3617 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3618
3619 for_each_encoder_on_crtc(dev, crtc, encoder)
3620 if (encoder->post_disable)
3621 encoder->post_disable(encoder);
3622
88adfff1 3623 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3624 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3625 intel_ddi_fdi_disable(crtc);
83616634 3626 }
4f771f10
PZ		 3627
3628 intel_crtc->active = false;
3629 intel_update_watermarks(dev);
3630
3631 mutex_lock(&dev->struct_mutex);
3632 intel_update_fbc(dev);
3633 mutex_unlock(&dev->struct_mutex);
3634}
3635
ee7b9f93
JB		 3636static void ironlake_crtc_off(struct drm_crtc *crtc)
3637{
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3639 intel_put_pch_pll(intel_crtc);
3640}
3641
6441ab5f
PZ		 3642static void haswell_crtc_off(struct drm_crtc *crtc)
3643{
a5c961d1
PZ		 3644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3645
3646 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3647 * start using it. */
3b117c8f 3648 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3649
6441ab5f
PZ		 3650 intel_ddi_put_crtc_pll(crtc);
3651}
3652
02e792fb
DV		 3653static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3654{
02e792fb 3655 if (!enable && intel_crtc->overlay) {
23f09ce3 3656 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3657 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3658
23f09ce3 3659 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3660 dev_priv->mm.interruptible = false;
3661 (void) intel_overlay_switch_off(intel_crtc->overlay);
3662 dev_priv->mm.interruptible = true;
23f09ce3 3663 mutex_unlock(&dev->struct_mutex);
02e792fb 3664 }
02e792fb 3665
5dcdbcb0
CW		 3666 /* Let userspace switch the overlay on again. In most cases userspace
3667 * has to recompute where to put it anyway.
3668 */
02e792fb
DV		 3669}
3670
61bc95c1
EE		 3671/**
3672 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3673 * cursor plane briefly if not already running after enabling the display
3674 * plane.
3675 * This workaround avoids occasional blank screens when self refresh is
3676 * enabled.
3677 */
3678static void
3679g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3680{
3681 u32 cntl = I915_READ(CURCNTR(pipe));
3682
3683 if ((cntl & CURSOR_MODE) == 0) {
3684 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3685
3686 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3687 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3688 intel_wait_for_vblank(dev_priv->dev, pipe);
3689 I915_WRITE(CURCNTR(pipe), cntl);
3690 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3691 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3692 }
3693}
3694
89b667f8
JB		 3695static void valleyview_crtc_enable(struct drm_crtc *crtc)
3696{
3697 struct drm_device *dev = crtc->dev;
3698 struct drm_i915_private *dev_priv = dev->dev_private;
3699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3700 struct intel_encoder *encoder;
3701 int pipe = intel_crtc->pipe;
3702 int plane = intel_crtc->plane;
3703
3704 WARN_ON(!crtc->enabled);
3705
3706 if (intel_crtc->active)
3707 return;
3708
3709 intel_crtc->active = true;
3710 intel_update_watermarks(dev);
3711
3712 mutex_lock(&dev_priv->dpio_lock);
3713
3714 for_each_encoder_on_crtc(dev, crtc, encoder)
3715 if (encoder->pre_pll_enable)
3716 encoder->pre_pll_enable(encoder);
3717
3718 intel_enable_pll(dev_priv, pipe);
3719
3720 for_each_encoder_on_crtc(dev, crtc, encoder)
3721 if (encoder->pre_enable)
3722 encoder->pre_enable(encoder);
3723
3724 /* VLV wants encoder enabling _before_ the pipe is up. */
3725 for_each_encoder_on_crtc(dev, crtc, encoder)
3726 encoder->enable(encoder);
3727
3728 intel_enable_pipe(dev_priv, pipe, false);
3729 intel_enable_plane(dev_priv, plane, pipe);
3730
3731 intel_crtc_load_lut(crtc);
3732 intel_update_fbc(dev);
3733
3734 /* Give the overlay scaler a chance to enable if it's on this pipe */
3735 intel_crtc_dpms_overlay(intel_crtc, true);
3736 intel_crtc_update_cursor(crtc, true);
3737
3738 mutex_unlock(&dev_priv->dpio_lock);
3739}
3740
0b8765c6 3741static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3742{
3743 struct drm_device *dev = crtc->dev;
79e53945
JB		 3744 struct drm_i915_private *dev_priv = dev->dev_private;
3745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3746 struct intel_encoder *encoder;
79e53945 3747 int pipe = intel_crtc->pipe;
80824003 3748 int plane = intel_crtc->plane;
79e53945 3749
08a48469
DV		 3750 WARN_ON(!crtc->enabled);
3751
f7abfe8b
CW		 3752 if (intel_crtc->active)
3753 return;
3754
3755 intel_crtc->active = true;
6b383a7f
CW		 3756 intel_update_watermarks(dev);
3757
63d7bbe9 3758 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3759
3760 for_each_encoder_on_crtc(dev, crtc, encoder)
3761 if (encoder->pre_enable)
3762 encoder->pre_enable(encoder);
3763
040484af 3764 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3765 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3766 if (IS_G4X(dev))
3767 g4x_fixup_plane(dev_priv, pipe);
79e53945 3768
0b8765c6 3769 intel_crtc_load_lut(crtc);
bed4a673 3770 intel_update_fbc(dev);
79e53945 3771
0b8765c6
JB		 3772 /* Give the overlay scaler a chance to enable if it's on this pipe */
3773 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3774 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3775
fa5c73b1
DV		 3776 for_each_encoder_on_crtc(dev, crtc, encoder)
3777 encoder->enable(encoder);
0b8765c6 3778}
79e53945 3779
87476d63
DV		 3780static void i9xx_pfit_disable(struct intel_crtc *crtc)
3781{
3782 struct drm_device *dev = crtc->base.dev;
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3784 enum pipe pipe;
3785 uint32_t pctl = I915_READ(PFIT_CONTROL);
3786
3787 assert_pipe_disabled(dev_priv, crtc->pipe);
3788
3789 if (INTEL_INFO(dev)->gen >= 4)
3790 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3791 else
3792 pipe = PIPE_B;
3793
3794 if (pipe == crtc->pipe) {
3795 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3796 I915_WRITE(PFIT_CONTROL, 0);
3797 }
3798}
3799
0b8765c6
JB		 3800static void i9xx_crtc_disable(struct drm_crtc *crtc)
3801{
3802 struct drm_device *dev = crtc->dev;
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3805 struct intel_encoder *encoder;
0b8765c6
JB		 3806 int pipe = intel_crtc->pipe;
3807 int plane = intel_crtc->plane;
ef9c3aee 3808
f7abfe8b
CW		 3809 if (!intel_crtc->active)
3810 return;
3811
ea9d758d
DV		 3812 for_each_encoder_on_crtc(dev, crtc, encoder)
3813 encoder->disable(encoder);
3814
0b8765c6 3815 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3816 intel_crtc_wait_for_pending_flips(crtc);
3817 drm_vblank_off(dev, pipe);
0b8765c6 3818 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3819 intel_crtc_update_cursor(crtc, false);
0b8765c6 3820
973d04f9
CW		 3821 if (dev_priv->cfb_plane == plane)
3822 intel_disable_fbc(dev);
79e53945 3823
b24e7179 3824 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3825 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3826
87476d63 3827 i9xx_pfit_disable(intel_crtc);
24a1f16d 3828
89b667f8
JB		 3829 for_each_encoder_on_crtc(dev, crtc, encoder)
3830 if (encoder->post_disable)
3831 encoder->post_disable(encoder);
3832
63d7bbe9 3833 intel_disable_pll(dev_priv, pipe);
0b8765c6 3834
f7abfe8b 3835 intel_crtc->active = false;
6b383a7f
CW		 3836 intel_update_fbc(dev);
3837 intel_update_watermarks(dev);
0b8765c6
JB		 3838}
3839
ee7b9f93
JB		 3840static void i9xx_crtc_off(struct drm_crtc *crtc)
3841{
3842}
3843
976f8a20
DV		 3844static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3845 bool enabled)
2c07245f
ZW		 3846{
3847 struct drm_device *dev = crtc->dev;
3848 struct drm_i915_master_private *master_priv;
3849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3850 int pipe = intel_crtc->pipe;
79e53945
JB		 3851
3852 if (!dev->primary->master)
3853 return;
3854
3855 master_priv = dev->primary->master->driver_priv;
3856 if (!master_priv->sarea_priv)
3857 return;
3858
79e53945
JB		 3859 switch (pipe) {
3860 case 0:
3861 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3862 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3863 break;
3864 case 1:
3865 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3866 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3867 break;
3868 default:
9db4a9c7 3869 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3870 break;
3871 }
79e53945
JB		 3872}
3873
976f8a20
DV		 3874/**
3875 * Sets the power management mode of the pipe and plane.
3876 */
3877void intel_crtc_update_dpms(struct drm_crtc *crtc)
3878{
3879 struct drm_device *dev = crtc->dev;
3880 struct drm_i915_private *dev_priv = dev->dev_private;
3881 struct intel_encoder *intel_encoder;
3882 bool enable = false;
3883
3884 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3885 enable |= intel_encoder->connectors_active;
3886
3887 if (enable)
3888 dev_priv->display.crtc_enable(crtc);
3889 else
3890 dev_priv->display.crtc_disable(crtc);
3891
3892 intel_crtc_update_sarea(crtc, enable);
3893}
3894
cdd59983
CW		 3895static void intel_crtc_disable(struct drm_crtc *crtc)
3896{
cdd59983 3897 struct drm_device *dev = crtc->dev;
976f8a20 3898 struct drm_connector *connector;
ee7b9f93 3899 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3901
976f8a20
DV		 3902 /* crtc should still be enabled when we disable it. */
3903 WARN_ON(!crtc->enabled);
3904
7b9f35a6 3905 intel_crtc->eld_vld = false;
976f8a20
DV		 3906 dev_priv->display.crtc_disable(crtc);
3907 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3908 dev_priv->display.off(crtc);
3909
931872fc
CW		 3910 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3911 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3912
3913 if (crtc->fb) {
3914 mutex_lock(&dev->struct_mutex);
1690e1eb 3915 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3916 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3917 crtc->fb = NULL;
3918 }
3919
3920 /* Update computed state. */
3921 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3922 if (!connector->encoder || !connector->encoder->crtc)
3923 continue;
3924
3925 if (connector->encoder->crtc != crtc)
3926 continue;
3927
3928 connector->dpms = DRM_MODE_DPMS_OFF;
3929 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3930 }
3931}
3932
a261b246 3933void intel_modeset_disable(struct drm_device *dev)
79e53945 3934{
a261b246
DV		 3935 struct drm_crtc *crtc;
3936
3937 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3938 if (crtc->enabled)
3939 intel_crtc_disable(crtc);
3940 }
79e53945
JB		 3941}
3942
ea5b213a 3943void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3944{
4ef69c7a 3945 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3946
ea5b213a
CW		 3947 drm_encoder_cleanup(encoder);
3948 kfree(intel_encoder);
7e7d76c3
JB		 3949}
3950
5ab432ef
DV		 3951/* Simple dpms helper for encodres with just one connector, no cloning and only
3952 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3953 * state of the entire output pipe. */
3954void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3955{
5ab432ef
DV		 3956 if (mode == DRM_MODE_DPMS_ON) {
3957 encoder->connectors_active = true;
3958
b2cabb0e 3959 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3960 } else {
3961 encoder->connectors_active = false;
3962
b2cabb0e 3963 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3964 }
79e53945
JB		 3965}
3966
0a91ca29
DV		 3967/* Cross check the actual hw state with our own modeset state tracking (and it's
3968 * internal consistency). */
b980514c 3969static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3970{
0a91ca29
DV		 3971 if (connector->get_hw_state(connector)) {
3972 struct intel_encoder *encoder = connector->encoder;
3973 struct drm_crtc *crtc;
3974 bool encoder_enabled;
3975 enum pipe pipe;
3976
3977 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3978 connector->base.base.id,
3979 drm_get_connector_name(&connector->base));
3980
3981 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3982 "wrong connector dpms state\n");
3983 WARN(connector->base.encoder != &encoder->base,
3984 "active connector not linked to encoder\n");
3985 WARN(!encoder->connectors_active,
3986 "encoder->connectors_active not set\n");
3987
3988 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3989 WARN(!encoder_enabled, "encoder not enabled\n");
3990 if (WARN_ON(!encoder->base.crtc))
3991 return;
3992
3993 crtc = encoder->base.crtc;
3994
3995 WARN(!crtc->enabled, "crtc not enabled\n");
3996 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3997 WARN(pipe != to_intel_crtc(crtc)->pipe,
3998 "encoder active on the wrong pipe\n");
3999 }
79e53945
JB		 4000}
4001
5ab432ef
DV		 4002/* Even simpler default implementation, if there's really no special case to
4003 * consider. */
4004void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4005{
5ab432ef 4006 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4007
5ab432ef
DV		 4008 /* All the simple cases only support two dpms states. */
4009 if (mode != DRM_MODE_DPMS_ON)
4010 mode = DRM_MODE_DPMS_OFF;
d4270e57 4011
5ab432ef
DV		 4012 if (mode == connector->dpms)
4013 return;
4014
4015 connector->dpms = mode;
4016
4017 /* Only need to change hw state when actually enabled */
4018 if (encoder->base.crtc)
4019 intel_encoder_dpms(encoder, mode);
4020 else
8af6cf88 4021 WARN_ON(encoder->connectors_active != false);
0a91ca29 4022
b980514c 4023 intel_modeset_check_state(connector->dev);
79e53945
JB		 4024}
4025
f0947c37
DV		 4026/* Simple connector->get_hw_state implementation for encoders that support only
4027 * one connector and no cloning and hence the encoder state determines the state
4028 * of the connector. */
4029bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4030{
24929352 4031 enum pipe pipe = 0;
f0947c37 4032 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4033
f0947c37 4034 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4035}
4036
b8cecdf5
DV		 4037static bool intel_crtc_compute_config(struct drm_crtc *crtc,
4038 struct intel_crtc_config *pipe_config)
79e53945 4039{
2c07245f 4040 struct drm_device *dev = crtc->dev;
b8cecdf5 4041 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4042
bad720ff 4043 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4044 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4045 if (pipe_config->requested_mode.clock * 3
4046 > IRONLAKE_FDI_FREQ * 4)
2377b741 4047 return false;
2c07245f 4048 }
89749350 4049
f9bef081
DV		 4050 /* All interlaced capable intel hw wants timings in frames. Note though
4051 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4052 * timings, so we need to be careful not to clobber these.*/
7ae89233 4053 if (!pipe_config->timings_set)
f9bef081 4054 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4055
44f46b42
CW		 4056 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4057 * with a hsync front porch of 0.
4058 */
4059 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4060 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4061 return false;
4062
bd080ee5 4063 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4064 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4065 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4066 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4067 * for lvds. */
4068 pipe_config->pipe_bpp = 8*3;
4069 }
4070
79e53945
JB		 4071 return true;
4072}
4073
25eb05fc
JB		 4074static int valleyview_get_display_clock_speed(struct drm_device *dev)
4075{
4076 return 400000; /* FIXME */
4077}
4078
e70236a8
JB		 4079static int i945_get_display_clock_speed(struct drm_device *dev)
4080{
4081 return 400000;
4082}
79e53945 4083
e70236a8 4084static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4085{
e70236a8
JB		 4086 return 333000;
4087}
79e53945 4088
e70236a8
JB		 4089static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4090{
4091 return 200000;
4092}
79e53945 4093
e70236a8
JB		 4094static int i915gm_get_display_clock_speed(struct drm_device *dev)
4095{
4096 u16 gcfgc = 0;
79e53945 4097
e70236a8
JB		 4098 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4099
4100 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4101 return 133000;
4102 else {
4103 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4104 case GC_DISPLAY_CLOCK_333_MHZ:
4105 return 333000;
4106 default:
4107 case GC_DISPLAY_CLOCK_190_200_MHZ:
4108 return 190000;
79e53945 4109 }
e70236a8
JB		 4110 }
4111}
4112
4113static int i865_get_display_clock_speed(struct drm_device *dev)
4114{
4115 return 266000;
4116}
4117
4118static int i855_get_display_clock_speed(struct drm_device *dev)
4119{
4120 u16 hpllcc = 0;
4121 /* Assume that the hardware is in the high speed state. This
4122 * should be the default.
4123 */
4124 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4125 case GC_CLOCK_133_200:
4126 case GC_CLOCK_100_200:
4127 return 200000;
4128 case GC_CLOCK_166_250:
4129 return 250000;
4130 case GC_CLOCK_100_133:
79e53945 4131 return 133000;
e70236a8 4132 }
79e53945 4133
e70236a8
JB		 4134 /* Shouldn't happen */
4135 return 0;
4136}
79e53945 4137
e70236a8
JB		 4138static int i830_get_display_clock_speed(struct drm_device *dev)
4139{
4140 return 133000;
79e53945
JB		 4141}
4142
2c07245f 4143static void
e69d0bc1 4144intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4145{
4146 while (*num > 0xffffff || *den > 0xffffff) {
4147 *num >>= 1;
4148 *den >>= 1;
4149 }
4150}
4151
e69d0bc1
DV		 4152void
4153intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4154 int pixel_clock, int link_clock,
4155 struct intel_link_m_n *m_n)
2c07245f 4156{
e69d0bc1 4157 m_n->tu = 64;
22ed1113
CW		 4158 m_n->gmch_m = bits_per_pixel * pixel_clock;
4159 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4160 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4161 m_n->link_m = pixel_clock;
4162 m_n->link_n = link_clock;
e69d0bc1 4163 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4164}
4165
a7615030
CW		 4166static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4167{
72bbe58c
KP		 4168 if (i915_panel_use_ssc >= 0)
4169 return i915_panel_use_ssc != 0;
4170 return dev_priv->lvds_use_ssc
435793df 4171 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4172}
4173
a0c4da24
JB		 4174static int vlv_get_refclk(struct drm_crtc *crtc)
4175{
4176 struct drm_device *dev = crtc->dev;
4177 struct drm_i915_private *dev_priv = dev->dev_private;
4178 int refclk = 27000; /* for DP & HDMI */
4179
4180 return 100000; /* only one validated so far */
4181
4182 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4183 refclk = 96000;
4184 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4185 if (intel_panel_use_ssc(dev_priv))
4186 refclk = 100000;
4187 else
4188 refclk = 96000;
4189 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4190 refclk = 100000;
4191 }
4192
4193 return refclk;
4194}
4195
c65d77d8
JB		 4196static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4197{
4198 struct drm_device *dev = crtc->dev;
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4200 int refclk;
4201
a0c4da24
JB		 4202 if (IS_VALLEYVIEW(dev)) {
4203 refclk = vlv_get_refclk(crtc);
4204 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4205 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4206 refclk = dev_priv->lvds_ssc_freq * 1000;
4207 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4208 refclk / 1000);
4209 } else if (!IS_GEN2(dev)) {
4210 refclk = 96000;
4211 } else {
4212 refclk = 48000;
4213 }
4214
4215 return refclk;
4216}
4217
f47709a9 4218static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4219{
f47709a9
DV		 4220 unsigned dotclock = crtc->config.adjusted_mode.clock;
4221 struct dpll *clock = &crtc->config.dpll;
4222
c65d77d8
JB		 4223 /* SDVO TV has fixed PLL values depend on its clock range,
4224 this mirrors vbios setting. */
f47709a9 4225 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4226 clock->p1 = 2;
4227 clock->p2 = 10;
4228 clock->n = 3;
4229 clock->m1 = 16;
4230 clock->m2 = 8;
f47709a9 4231 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4232 clock->p1 = 1;
4233 clock->p2 = 10;
4234 clock->n = 6;
4235 clock->m1 = 12;
4236 clock->m2 = 8;
4237 }
f47709a9
DV		 4238
4239 crtc->config.clock_set = true;
c65d77d8
JB		 4240}
4241
f47709a9 4242static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4243 intel_clock_t *reduced_clock)
4244{
f47709a9 4245 struct drm_device *dev = crtc->base.dev;
a7516a05 4246 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4247 int pipe = crtc->pipe;
a7516a05 4248 u32 fp, fp2 = 0;
f47709a9 4249 struct dpll *clock = &crtc->config.dpll;
a7516a05
JB		 4250
4251 if (IS_PINEVIEW(dev)) {
4252 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4253 if (reduced_clock)
4254 fp2 = (1 << reduced_clock->n) << 16 |
4255 reduced_clock->m1 << 8 | reduced_clock->m2;
4256 } else {
4257 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4258 if (reduced_clock)
4259 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4260 reduced_clock->m2;
4261 }
4262
4263 I915_WRITE(FP0(pipe), fp);
4264
f47709a9
DV		 4265 crtc->lowfreq_avail = false;
4266 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4267 reduced_clock && i915_powersave) {
4268 I915_WRITE(FP1(pipe), fp2);
f47709a9 4269 crtc->lowfreq_avail = true;
a7516a05
JB		 4270 } else {
4271 I915_WRITE(FP1(pipe), fp);
4272 }
4273}
4274
89b667f8
JB		 4275static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4276{
4277 u32 reg_val;
4278
4279 /*
4280 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4281 * and set it to a reasonable value instead.
4282 */
4283 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4284 reg_val &= 0xffffff00;
4285 reg_val |= 0x00000030;
4286 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4287
4288 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4289 reg_val &= 0x8cffffff;
4290 reg_val = 0x8c000000;
4291 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4292
4293 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4294 reg_val &= 0xffffff00;
4295 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4296
4297 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4298 reg_val &= 0x00ffffff;
4299 reg_val |= 0xb0000000;
4300 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4301}
4302
03afc4a2
DV		 4303static void intel_dp_set_m_n(struct intel_crtc *crtc)
4304{
4305 if (crtc->config.has_pch_encoder)
4306 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4307 else
4308 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4309}
4310
f47709a9 4311static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4312{
f47709a9 4313 struct drm_device *dev = crtc->base.dev;
a0c4da24 4314 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4315 struct drm_display_mode *adjusted_mode =
4316 &crtc->config.adjusted_mode;
4317 struct intel_encoder *encoder;
f47709a9 4318 int pipe = crtc->pipe;
89b667f8 4319 u32 dpll, mdiv;
a0c4da24 4320 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8
JB		 4321 bool is_hdmi;
4322 u32 coreclk, reg_val, temp;
a0c4da24 4323
09153000
DV		 4324 mutex_lock(&dev_priv->dpio_lock);
4325
89b667f8 4326 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4327
f47709a9
DV		 4328 bestn = crtc->config.dpll.n;
4329 bestm1 = crtc->config.dpll.m1;
4330 bestm2 = crtc->config.dpll.m2;
4331 bestp1 = crtc->config.dpll.p1;
4332 bestp2 = crtc->config.dpll.p2;
a0c4da24 4333
89b667f8
JB		 4334 /* See eDP HDMI DPIO driver vbios notes doc */
4335
4336 /* PLL B needs special handling */
4337 if (pipe)
4338 vlv_pllb_recal_opamp(dev_priv);
4339
4340 /* Set up Tx target for periodic Rcomp update */
4341 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4342
4343 /* Disable target IRef on PLL */
4344 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4345 reg_val &= 0x00ffffff;
4346 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4347
4348 /* Disable fast lock */
4349 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4350
4351 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4352 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4353 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4354 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4355 mdiv |= (1 << DPIO_K_SHIFT);
89b667f8
JB		 4356 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4357 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4358 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4359 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4360 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4361
89b667f8
JB		 4362 mdiv |= DPIO_ENABLE_CALIBRATION;
4363 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4364
89b667f8
JB		 4365 /* Set HBR and RBR LPF coefficients */
4366 if (adjusted_mode->clock == 162000 ||
4367 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4368 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4369 0x005f0021);
4370 else
4371 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4372 0x00d0000f);
4373
4374 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4375 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4376 /* Use SSC source */
4377 if (!pipe)
4378 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4379 0x0df40000);
4380 else
4381 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4382 0x0df70000);
4383 } else { /* HDMI or VGA */
4384 /* Use bend source */
4385 if (!pipe)
4386 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4387 0x0df70000);
4388 else
4389 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4390 0x0df40000);
4391 }
a0c4da24 4392
89b667f8
JB		 4393 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4394 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4395 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4396 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4397 coreclk |= 0x01000000;
4398 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4399
89b667f8 4400 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4401
89b667f8
JB		 4402 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4403 if (encoder->pre_pll_enable)
4404 encoder->pre_pll_enable(encoder);
2a8f64ca 4405
89b667f8
JB		 4406 /* Enable DPIO clock input */
4407 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4408 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4409 if (pipe)
4410 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4411
89b667f8 4412 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4413 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4414 POSTING_READ(DPLL(pipe));
4415 udelay(150);
a0c4da24 4416
89b667f8
JB		 4417 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4418 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4419
4420 if (is_hdmi) {
6cc5f341 4421 temp = 0;
f47709a9
DV		 4422 if (crtc->config.pixel_multiplier > 1) {
4423 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4424 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4425 }
a0c4da24 4426
89b667f8
JB		 4427 I915_WRITE(DPLL_MD(pipe), temp);
4428 POSTING_READ(DPLL_MD(pipe));
2a8f64ca 4429 }
f47709a9 4430
89b667f8
JB		 4431 if (crtc->config.has_dp_encoder)
4432 intel_dp_set_m_n(crtc);
09153000
DV		 4433
4434 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4435}
4436
f47709a9
DV		 4437static void i9xx_update_pll(struct intel_crtc *crtc,
4438 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4439 int num_connectors)
4440{
f47709a9 4441 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4442 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4443 struct intel_encoder *encoder;
f47709a9 4444 int pipe = crtc->pipe;
eb1cbe48
DV		 4445 u32 dpll;
4446 bool is_sdvo;
f47709a9 4447 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4448
f47709a9 4449 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4450
f47709a9
DV		 4451 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4452 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4453
4454 dpll = DPLL_VGA_MODE_DIS;
4455
f47709a9 4456 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4457 dpll |= DPLLB_MODE_LVDS;
4458 else
4459 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4460
eb1cbe48 4461 if (is_sdvo) {
f47709a9 4462 if ((crtc->config.pixel_multiplier > 1) &&
6cc5f341 4463 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
f47709a9 4464 dpll |= (crtc->config.pixel_multiplier - 1)
6cc5f341 4465 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4466 }
4467 dpll |= DPLL_DVO_HIGH_SPEED;
4468 }
f47709a9 4469 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4470 dpll |= DPLL_DVO_HIGH_SPEED;
4471
4472 /* compute bitmask from p1 value */
4473 if (IS_PINEVIEW(dev))
4474 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4475 else {
4476 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4477 if (IS_G4X(dev) && reduced_clock)
4478 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4479 }
4480 switch (clock->p2) {
4481 case 5:
4482 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4483 break;
4484 case 7:
4485 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4486 break;
4487 case 10:
4488 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4489 break;
4490 case 14:
4491 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4492 break;
4493 }
4494 if (INTEL_INFO(dev)->gen >= 4)
4495 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4496
f47709a9 4497 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4498 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4499 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4500 /* XXX: just matching BIOS for now */
4501 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4502 dpll |= 3;
f47709a9 4503 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4504 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4505 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4506 else
4507 dpll |= PLL_REF_INPUT_DREFCLK;
4508
4509 dpll |= DPLL_VCO_ENABLE;
4510 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4511 POSTING_READ(DPLL(pipe));
4512 udelay(150);
4513
f47709a9 4514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4515 if (encoder->pre_pll_enable)
4516 encoder->pre_pll_enable(encoder);
eb1cbe48 4517
f47709a9
DV		 4518 if (crtc->config.has_dp_encoder)
4519 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4520
4521 I915_WRITE(DPLL(pipe), dpll);
4522
4523 /* Wait for the clocks to stabilize. */
4524 POSTING_READ(DPLL(pipe));
4525 udelay(150);
4526
4527 if (INTEL_INFO(dev)->gen >= 4) {
4528 u32 temp = 0;
4529 if (is_sdvo) {
6cc5f341 4530 temp = 0;
f47709a9
DV		 4531 if (crtc->config.pixel_multiplier > 1) {
4532 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4533 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4534 }
eb1cbe48
DV		 4535 }
4536 I915_WRITE(DPLL_MD(pipe), temp);
4537 } else {
4538 /* The pixel multiplier can only be updated once the
4539 * DPLL is enabled and the clocks are stable.
4540 *
4541 * So write it again.
4542 */
4543 I915_WRITE(DPLL(pipe), dpll);
4544 }
4545}
4546
f47709a9 4547static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4548 struct drm_display_mode *adjusted_mode,
f47709a9 4549 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4550 int num_connectors)
4551{
f47709a9 4552 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4553 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4554 struct intel_encoder *encoder;
f47709a9 4555 int pipe = crtc->pipe;
eb1cbe48 4556 u32 dpll;
f47709a9 4557 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4558
f47709a9 4559 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4560
eb1cbe48
DV		 4561 dpll = DPLL_VGA_MODE_DIS;
4562
f47709a9 4563 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4564 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4565 } else {
4566 if (clock->p1 == 2)
4567 dpll |= PLL_P1_DIVIDE_BY_TWO;
4568 else
4569 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4570 if (clock->p2 == 4)
4571 dpll |= PLL_P2_DIVIDE_BY_4;
4572 }
4573
f47709a9 4574 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4575 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4576 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4577 else
4578 dpll |= PLL_REF_INPUT_DREFCLK;
4579
4580 dpll |= DPLL_VCO_ENABLE;
4581 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4582 POSTING_READ(DPLL(pipe));
4583 udelay(150);
4584
f47709a9 4585 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4586 if (encoder->pre_pll_enable)
4587 encoder->pre_pll_enable(encoder);
eb1cbe48 4588
5b5896e4
DV		 4589 I915_WRITE(DPLL(pipe), dpll);
4590
4591 /* Wait for the clocks to stabilize. */
4592 POSTING_READ(DPLL(pipe));
4593 udelay(150);
4594
eb1cbe48
DV		 4595 /* The pixel multiplier can only be updated once the
4596 * DPLL is enabled and the clocks are stable.
4597 *
4598 * So write it again.
4599 */
4600 I915_WRITE(DPLL(pipe), dpll);
4601}
4602
b0e77b9c
PZ		 4603static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4604 struct drm_display_mode *mode,
4605 struct drm_display_mode *adjusted_mode)
4606{
4607 struct drm_device *dev = intel_crtc->base.dev;
4608 struct drm_i915_private *dev_priv = dev->dev_private;
4609 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4610 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
b0e77b9c
PZ		 4611 uint32_t vsyncshift;
4612
4613 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4614 /* the chip adds 2 halflines automatically */
4615 adjusted_mode->crtc_vtotal -= 1;
4616 adjusted_mode->crtc_vblank_end -= 1;
4617 vsyncshift = adjusted_mode->crtc_hsync_start
4618 - adjusted_mode->crtc_htotal / 2;
4619 } else {
4620 vsyncshift = 0;
4621 }
4622
4623 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4624 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4625
fe2b8f9d 4626 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4627 (adjusted_mode->crtc_hdisplay - 1) |
4628 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4629 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4630 (adjusted_mode->crtc_hblank_start - 1) |
4631 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4632 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4633 (adjusted_mode->crtc_hsync_start - 1) |
4634 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4635
fe2b8f9d 4636 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4637 (adjusted_mode->crtc_vdisplay - 1) |
4638 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4639 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4640 (adjusted_mode->crtc_vblank_start - 1) |
4641 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4642 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4643 (adjusted_mode->crtc_vsync_start - 1) |
4644 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4645
b5e508d4
PZ		 4646 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4647 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4648 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4649 * bits. */
4650 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4651 (pipe == PIPE_B || pipe == PIPE_C))
4652 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4653
b0e77b9c
PZ		 4654 /* pipesrc controls the size that is scaled from, which should
4655 * always be the user's requested size.
4656 */
4657 I915_WRITE(PIPESRC(pipe),
4658 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4659}
4660
84b046f3
DV		 4661static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4662{
4663 struct drm_device *dev = intel_crtc->base.dev;
4664 struct drm_i915_private *dev_priv = dev->dev_private;
4665 uint32_t pipeconf;
4666
4667 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4668
4669 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4670 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4671 * core speed.
4672 *
4673 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4674 * pipe == 0 check?
4675 */
4676 if (intel_crtc->config.requested_mode.clock >
4677 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4678 pipeconf |= PIPECONF_DOUBLE_WIDE;
4679 else
4680 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4681 }
4682
4683 /* default to 8bpc */
4684 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4685 if (intel_crtc->config.has_dp_encoder) {
4686 if (intel_crtc->config.dither) {
4687 pipeconf |= PIPECONF_6BPC |
4688 PIPECONF_DITHER_EN |
4689 PIPECONF_DITHER_TYPE_SP;
4690 }
4691 }
4692
4693 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4694 INTEL_OUTPUT_EDP)) {
4695 if (intel_crtc->config.dither) {
4696 pipeconf |= PIPECONF_6BPC |
4697 PIPECONF_ENABLE |
4698 I965_PIPECONF_ACTIVE;
4699 }
4700 }
4701
4702 if (HAS_PIPE_CXSR(dev)) {
4703 if (intel_crtc->lowfreq_avail) {
4704 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4705 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4706 } else {
4707 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4708 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4709 }
4710 }
4711
4712 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4713 if (!IS_GEN2(dev) &&
4714 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4715 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4716 else
4717 pipeconf |= PIPECONF_PROGRESSIVE;
4718
9c8e09b7
VS		 4719 if (IS_VALLEYVIEW(dev)) {
4720 if (intel_crtc->config.limited_color_range)
4721 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4722 else
4723 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4724 }
4725
84b046f3
DV		 4726 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4727 POSTING_READ(PIPECONF(intel_crtc->pipe));
4728}
4729
f564048e 4730static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4731 int x, int y,
94352cf9 4732 struct drm_framebuffer *fb)
79e53945
JB		 4733{
4734 struct drm_device *dev = crtc->dev;
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4737 struct drm_display_mode *adjusted_mode =
4738 &intel_crtc->config.adjusted_mode;
4739 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4740 int pipe = intel_crtc->pipe;
80824003 4741 int plane = intel_crtc->plane;
c751ce4f 4742 int refclk, num_connectors = 0;
652c393a 4743 intel_clock_t clock, reduced_clock;
84b046f3 4744 u32 dspcntr;
eb1cbe48 4745 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4746 bool is_lvds = false, is_tv = false;
5eddb70b 4747 struct intel_encoder *encoder;
d4906093 4748 const intel_limit_t *limit;
5c3b82e2 4749 int ret;
79e53945 4750
6c2b7c12 4751 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4752 switch (encoder->type) {
79e53945
JB		 4753 case INTEL_OUTPUT_LVDS:
4754 is_lvds = true;
4755 break;
4756 case INTEL_OUTPUT_SDVO:
7d57382e 4757 case INTEL_OUTPUT_HDMI:
79e53945 4758 is_sdvo = true;
5eddb70b 4759 if (encoder->needs_tv_clock)
e2f0ba97 4760 is_tv = true;
79e53945 4761 break;
79e53945
JB		 4762 case INTEL_OUTPUT_TVOUT:
4763 is_tv = true;
4764 break;
79e53945 4765 }
43565a06 4766
c751ce4f 4767 num_connectors++;
79e53945
JB		 4768 }
4769
c65d77d8 4770 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4771
d4906093
ML		 4772 /*
4773 * Returns a set of divisors for the desired target clock with the given
4774 * refclk, or FALSE. The returned values represent the clock equation:
4775 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4776 */
1b894b59 4777 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4778 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4779 &clock);
79e53945
JB		 4780 if (!ok) {
4781 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4782 return -EINVAL;
79e53945
JB		 4783 }
4784
cda4b7d3 4785 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4786 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4787
ddc9003c 4788 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4789 /*
4790 * Ensure we match the reduced clock's P to the target clock.
4791 * If the clocks don't match, we can't switch the display clock
4792 * by using the FP0/FP1. In such case we will disable the LVDS
4793 * downclock feature.
4794 */
ddc9003c 4795 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4796 dev_priv->lvds_downclock,
4797 refclk,
cec2f356 4798 &clock,
5eddb70b 4799 &reduced_clock);
7026d4ac 4800 }
f47709a9
DV		 4801 /* Compat-code for transition, will disappear. */
4802 if (!intel_crtc->config.clock_set) {
4803 intel_crtc->config.dpll.n = clock.n;
4804 intel_crtc->config.dpll.m1 = clock.m1;
4805 intel_crtc->config.dpll.m2 = clock.m2;
4806 intel_crtc->config.dpll.p1 = clock.p1;
4807 intel_crtc->config.dpll.p2 = clock.p2;
4808 }
7026d4ac 4809
c65d77d8 4810 if (is_sdvo && is_tv)
f47709a9 4811 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4812
eb1cbe48 4813 if (IS_GEN2(dev))
f47709a9 4814 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4815 has_reduced_clock ? &reduced_clock : NULL,
4816 num_connectors);
a0c4da24 4817 else if (IS_VALLEYVIEW(dev))
f47709a9 4818 vlv_update_pll(intel_crtc);
79e53945 4819 else
f47709a9 4820 i9xx_update_pll(intel_crtc,
eb1cbe48 4821 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4822 num_connectors);
79e53945 4823
79e53945
JB		 4824 /* Set up the display plane register */
4825 dspcntr = DISPPLANE_GAMMA_ENABLE;
4826
da6ecc5d
JB		 4827 if (!IS_VALLEYVIEW(dev)) {
4828 if (pipe == 0)
4829 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4830 else
4831 dspcntr |= DISPPLANE_SEL_PIPE_B;
4832 }
79e53945 4833
2582a850 4834 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4835 drm_mode_debug_printmodeline(mode);
4836
b0e77b9c 4837 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4838
4839 /* pipesrc and dspsize control the size that is scaled from,
4840 * which should always be the user's requested size.
79e53945 4841 */
929c77fb
EA		 4842 I915_WRITE(DSPSIZE(plane),
4843 ((mode->vdisplay - 1) << 16) |
4844 (mode->hdisplay - 1));
4845 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4846
84b046f3
DV		 4847 i9xx_set_pipeconf(intel_crtc);
4848
f564048e
EA		 4849 I915_WRITE(DSPCNTR(plane), dspcntr);
4850 POSTING_READ(DSPCNTR(plane));
4851
94352cf9 4852 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4853
4854 intel_update_watermarks(dev);
4855
f564048e
EA		 4856 return ret;
4857}
4858
0e8ffe1b
DV		 4859static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4860 struct intel_crtc_config *pipe_config)
4861{
4862 struct drm_device *dev = crtc->base.dev;
4863 struct drm_i915_private *dev_priv = dev->dev_private;
4864 uint32_t tmp;
4865
4866 tmp = I915_READ(PIPECONF(crtc->pipe));
4867 if (!(tmp & PIPECONF_ENABLE))
4868 return false;
4869
4870 return true;
4871}
4872
dde86e2d 4873static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4874{
4875 struct drm_i915_private *dev_priv = dev->dev_private;
4876 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4877 struct intel_encoder *encoder;
74cfd7ac 4878 u32 val, final;
13d83a67 4879 bool has_lvds = false;
199e5d79
KP		 4880 bool has_cpu_edp = false;
4881 bool has_pch_edp = false;
4882 bool has_panel = false;
99eb6a01
KP		 4883 bool has_ck505 = false;
4884 bool can_ssc = false;
13d83a67
JB		 4885
4886 /* We need to take the global config into account */
199e5d79
KP		 4887 list_for_each_entry(encoder, &mode_config->encoder_list,
4888 base.head) {
4889 switch (encoder->type) {
4890 case INTEL_OUTPUT_LVDS:
4891 has_panel = true;
4892 has_lvds = true;
4893 break;
4894 case INTEL_OUTPUT_EDP:
4895 has_panel = true;
4896 if (intel_encoder_is_pch_edp(&encoder->base))
4897 has_pch_edp = true;
4898 else
4899 has_cpu_edp = true;
4900 break;
13d83a67
JB		 4901 }
4902 }
4903
99eb6a01
KP		 4904 if (HAS_PCH_IBX(dev)) {
4905 has_ck505 = dev_priv->display_clock_mode;
4906 can_ssc = has_ck505;
4907 } else {
4908 has_ck505 = false;
4909 can_ssc = true;
4910 }
4911
4912 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4913 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4914 has_ck505);
13d83a67
JB		 4915
4916 /* Ironlake: try to setup display ref clock before DPLL
4917 * enabling. This is only under driver's control after
4918 * PCH B stepping, previous chipset stepping should be
4919 * ignoring this setting.
4920 */
74cfd7ac
CW		 4921 val = I915_READ(PCH_DREF_CONTROL);
4922
4923 /* As we must carefully and slowly disable/enable each source in turn,
4924 * compute the final state we want first and check if we need to
4925 * make any changes at all.
4926 */
4927 final = val;
4928 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4929 if (has_ck505)
4930 final |= DREF_NONSPREAD_CK505_ENABLE;
4931 else
4932 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4933
4934 final &= ~DREF_SSC_SOURCE_MASK;
4935 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4936 final &= ~DREF_SSC1_ENABLE;
4937
4938 if (has_panel) {
4939 final |= DREF_SSC_SOURCE_ENABLE;
4940
4941 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4942 final |= DREF_SSC1_ENABLE;
4943
4944 if (has_cpu_edp) {
4945 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4946 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4947 else
4948 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4949 } else
4950 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4951 } else {
4952 final |= DREF_SSC_SOURCE_DISABLE;
4953 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4954 }
4955
4956 if (final == val)
4957 return;
4958
13d83a67 4959 /* Always enable nonspread source */
74cfd7ac 4960 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4961
99eb6a01 4962 if (has_ck505)
74cfd7ac 4963 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4964 else
74cfd7ac 4965 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4966
199e5d79 4967 if (has_panel) {
74cfd7ac
CW		 4968 val &= ~DREF_SSC_SOURCE_MASK;
4969 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4970
199e5d79 4971 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4972 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4973 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4974 val |= DREF_SSC1_ENABLE;
e77166b5 4975 } else
74cfd7ac 4976 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4977
4978 /* Get SSC going before enabling the outputs */
74cfd7ac 4979 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4980 POSTING_READ(PCH_DREF_CONTROL);
4981 udelay(200);
4982
74cfd7ac 4983 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4984
4985 /* Enable CPU source on CPU attached eDP */
199e5d79 4986 if (has_cpu_edp) {
99eb6a01 4987 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4988 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4989 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4990 }
13d83a67 4991 else
74cfd7ac 4992 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4993 } else
74cfd7ac 4994 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4995
74cfd7ac 4996 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4997 POSTING_READ(PCH_DREF_CONTROL);
4998 udelay(200);
4999 } else {
5000 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5001
74cfd7ac 5002 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5003
5004 /* Turn off CPU output */
74cfd7ac 5005 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5006
74cfd7ac 5007 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5008 POSTING_READ(PCH_DREF_CONTROL);
5009 udelay(200);
5010
5011 /* Turn off the SSC source */
74cfd7ac
CW		 5012 val &= ~DREF_SSC_SOURCE_MASK;
5013 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5014
5015 /* Turn off SSC1 */
74cfd7ac 5016 val &= ~DREF_SSC1_ENABLE;
199e5d79 5017
74cfd7ac 5018 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5019 POSTING_READ(PCH_DREF_CONTROL);
5020 udelay(200);
5021 }
74cfd7ac
CW		 5022
5023 BUG_ON(val != final);
13d83a67
JB		 5024}
5025
dde86e2d
PZ		 5026/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5027static void lpt_init_pch_refclk(struct drm_device *dev)
5028{
5029 struct drm_i915_private *dev_priv = dev->dev_private;
5030 struct drm_mode_config *mode_config = &dev->mode_config;
5031 struct intel_encoder *encoder;
5032 bool has_vga = false;
5033 bool is_sdv = false;
5034 u32 tmp;
5035
5036 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5037 switch (encoder->type) {
5038 case INTEL_OUTPUT_ANALOG:
5039 has_vga = true;
5040 break;
5041 }
5042 }
5043
5044 if (!has_vga)
5045 return;
5046
c00db246
DV		 5047 mutex_lock(&dev_priv->dpio_lock);
5048
dde86e2d
PZ		 5049 /* XXX: Rip out SDV support once Haswell ships for real. */
5050 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5051 is_sdv = true;
5052
5053 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5054 tmp &= ~SBI_SSCCTL_DISABLE;
5055 tmp |= SBI_SSCCTL_PATHALT;
5056 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5057
5058 udelay(24);
5059
5060 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5061 tmp &= ~SBI_SSCCTL_PATHALT;
5062 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5063
5064 if (!is_sdv) {
5065 tmp = I915_READ(SOUTH_CHICKEN2);
5066 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5067 I915_WRITE(SOUTH_CHICKEN2, tmp);
5068
5069 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5070 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5071 DRM_ERROR("FDI mPHY reset assert timeout\n");
5072
5073 tmp = I915_READ(SOUTH_CHICKEN2);
5074 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5075 I915_WRITE(SOUTH_CHICKEN2, tmp);
5076
5077 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5078 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5079 100))
5080 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5081 }
5082
5083 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5084 tmp &= ~(0xFF << 24);
5085 tmp |= (0x12 << 24);
5086 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5087
dde86e2d
PZ		 5088 if (is_sdv) {
5089 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5090 tmp |= 0x7FFF;
5091 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5092 }
5093
5094 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5095 tmp |= (1 << 11);
5096 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5097
5098 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5099 tmp |= (1 << 11);
5100 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5101
5102 if (is_sdv) {
5103 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5104 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5105 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5106
5107 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5108 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5109 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5110
5111 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5112 tmp |= (0x3F << 8);
5113 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5114
5115 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5116 tmp |= (0x3F << 8);
5117 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5118 }
5119
5120 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5121 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5122 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5123
5124 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5125 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5126 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5127
5128 if (!is_sdv) {
5129 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5130 tmp &= ~(7 << 13);
5131 tmp |= (5 << 13);
5132 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5133
5134 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5135 tmp &= ~(7 << 13);
5136 tmp |= (5 << 13);
5137 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5138 }
5139
5140 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5141 tmp &= ~0xFF;
5142 tmp |= 0x1C;
5143 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5144
5145 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5146 tmp &= ~0xFF;
5147 tmp |= 0x1C;
5148 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5149
5150 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5151 tmp &= ~(0xFF << 16);
5152 tmp |= (0x1C << 16);
5153 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5154
5155 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5156 tmp &= ~(0xFF << 16);
5157 tmp |= (0x1C << 16);
5158 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5159
5160 if (!is_sdv) {
5161 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5162 tmp |= (1 << 27);
5163 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5164
5165 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5166 tmp |= (1 << 27);
5167 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5168
5169 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5170 tmp &= ~(0xF << 28);
5171 tmp |= (4 << 28);
5172 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5173
5174 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5175 tmp &= ~(0xF << 28);
5176 tmp |= (4 << 28);
5177 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5178 }
5179
5180 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5181 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5182 tmp |= SBI_DBUFF0_ENABLE;
5183 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5184
5185 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5186}
5187
5188/*
5189 * Initialize reference clocks when the driver loads
5190 */
5191void intel_init_pch_refclk(struct drm_device *dev)
5192{
5193 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5194 ironlake_init_pch_refclk(dev);
5195 else if (HAS_PCH_LPT(dev))
5196 lpt_init_pch_refclk(dev);
5197}
5198
d9d444cb
JB		 5199static int ironlake_get_refclk(struct drm_crtc *crtc)
5200{
5201 struct drm_device *dev = crtc->dev;
5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 struct intel_encoder *encoder;
d9d444cb
JB		 5204 struct intel_encoder *edp_encoder = NULL;
5205 int num_connectors = 0;
5206 bool is_lvds = false;
5207
6c2b7c12 5208 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5209 switch (encoder->type) {
5210 case INTEL_OUTPUT_LVDS:
5211 is_lvds = true;
5212 break;
5213 case INTEL_OUTPUT_EDP:
5214 edp_encoder = encoder;
5215 break;
5216 }
5217 num_connectors++;
5218 }
5219
5220 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5221 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5222 dev_priv->lvds_ssc_freq);
5223 return dev_priv->lvds_ssc_freq * 1000;
5224 }
5225
5226 return 120000;
5227}
5228
c8203565 5229static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5230 struct drm_display_mode *adjusted_mode,
c8203565 5231 bool dither)
79e53945 5232{
c8203565 5233 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5235 int pipe = intel_crtc->pipe;
c8203565
PZ		 5236 uint32_t val;
5237
5238 val = I915_READ(PIPECONF(pipe));
5239
dfd07d72 5240 val &= ~PIPECONF_BPC_MASK;
965e0c48 5241 switch (intel_crtc->config.pipe_bpp) {
c8203565 5242 case 18:
dfd07d72 5243 val |= PIPECONF_6BPC;
c8203565
PZ		 5244 break;
5245 case 24:
dfd07d72 5246 val |= PIPECONF_8BPC;
c8203565
PZ		 5247 break;
5248 case 30:
dfd07d72 5249 val |= PIPECONF_10BPC;
c8203565
PZ		 5250 break;
5251 case 36:
dfd07d72 5252 val |= PIPECONF_12BPC;
c8203565
PZ		 5253 break;
5254 default:
cc769b62
PZ		 5255 /* Case prevented by intel_choose_pipe_bpp_dither. */
5256 BUG();
c8203565
PZ		 5257 }
5258
5259 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5260 if (dither)
5261 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5262
5263 val &= ~PIPECONF_INTERLACE_MASK;
5264 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5265 val |= PIPECONF_INTERLACED_ILK;
5266 else
5267 val |= PIPECONF_PROGRESSIVE;
5268
50f3b016 5269 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5270 val |= PIPECONF_COLOR_RANGE_SELECT;
5271 else
5272 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5273
c8203565
PZ		 5274 I915_WRITE(PIPECONF(pipe), val);
5275 POSTING_READ(PIPECONF(pipe));
5276}
5277
86d3efce
VS		 5278/*
5279 * Set up the pipe CSC unit.
5280 *
5281 * Currently only full range RGB to limited range RGB conversion
5282 * is supported, but eventually this should handle various
5283 * RGB<->YCbCr scenarios as well.
5284 */
50f3b016 5285static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5286{
5287 struct drm_device *dev = crtc->dev;
5288 struct drm_i915_private *dev_priv = dev->dev_private;
5289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5290 int pipe = intel_crtc->pipe;
5291 uint16_t coeff = 0x7800; /* 1.0 */
5292
5293 /*
5294 * TODO: Check what kind of values actually come out of the pipe
5295 * with these coeff/postoff values and adjust to get the best
5296 * accuracy. Perhaps we even need to take the bpc value into
5297 * consideration.
5298 */
5299
50f3b016 5300 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5301 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5302
5303 /*
5304 * GY/GU and RY/RU should be the other way around according
5305 * to BSpec, but reality doesn't agree. Just set them up in
5306 * a way that results in the correct picture.
5307 */
5308 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5309 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5310
5311 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5312 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5313
5314 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5315 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5316
5317 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5318 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5319 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5320
5321 if (INTEL_INFO(dev)->gen > 6) {
5322 uint16_t postoff = 0;
5323
50f3b016 5324 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5325 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5326
5327 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5328 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5329 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5330
5331 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5332 } else {
5333 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5334
50f3b016 5335 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5336 mode |= CSC_BLACK_SCREEN_OFFSET;
5337
5338 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5339 }
5340}
5341
ee2b0b38
PZ		 5342static void haswell_set_pipeconf(struct drm_crtc *crtc,
5343 struct drm_display_mode *adjusted_mode,
5344 bool dither)
5345{
5346 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5348 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5349 uint32_t val;
5350
702e7a56 5351 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5352
5353 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5354 if (dither)
5355 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5356
5357 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5358 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5359 val |= PIPECONF_INTERLACED_ILK;
5360 else
5361 val |= PIPECONF_PROGRESSIVE;
5362
702e7a56
PZ		 5363 I915_WRITE(PIPECONF(cpu_transcoder), val);
5364 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5365}
5366
6591c6e4
PZ		 5367static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5368 struct drm_display_mode *adjusted_mode,
5369 intel_clock_t *clock,
5370 bool *has_reduced_clock,
5371 intel_clock_t *reduced_clock)
5372{
5373 struct drm_device *dev = crtc->dev;
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375 struct intel_encoder *intel_encoder;
5376 int refclk;
d4906093 5377 const intel_limit_t *limit;
6591c6e4 5378 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5379
6591c6e4
PZ		 5380 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5381 switch (intel_encoder->type) {
79e53945
JB		 5382 case INTEL_OUTPUT_LVDS:
5383 is_lvds = true;
5384 break;
5385 case INTEL_OUTPUT_SDVO:
7d57382e 5386 case INTEL_OUTPUT_HDMI:
79e53945 5387 is_sdvo = true;
6591c6e4 5388 if (intel_encoder->needs_tv_clock)
e2f0ba97 5389 is_tv = true;
79e53945 5390 break;
79e53945
JB		 5391 case INTEL_OUTPUT_TVOUT:
5392 is_tv = true;
5393 break;
79e53945
JB		 5394 }
5395 }
5396
d9d444cb 5397 refclk = ironlake_get_refclk(crtc);
79e53945 5398
d4906093
ML		 5399 /*
5400 * Returns a set of divisors for the desired target clock with the given
5401 * refclk, or FALSE. The returned values represent the clock equation:
5402 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5403 */
1b894b59 5404 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5405 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5406 clock);
5407 if (!ret)
5408 return false;
cda4b7d3 5409
ddc9003c 5410 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5411 /*
5412 * Ensure we match the reduced clock's P to the target clock.
5413 * If the clocks don't match, we can't switch the display clock
5414 * by using the FP0/FP1. In such case we will disable the LVDS
5415 * downclock feature.
5416 */
6591c6e4
PZ		 5417 *has_reduced_clock = limit->find_pll(limit, crtc,
5418 dev_priv->lvds_downclock,
5419 refclk,
5420 clock,
5421 reduced_clock);
652c393a 5422 }
61e9653f
DV		 5423
5424 if (is_sdvo && is_tv)
f47709a9 5425 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5426
5427 return true;
5428}
5429
01a415fd
DV		 5430static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5431{
5432 struct drm_i915_private *dev_priv = dev->dev_private;
5433 uint32_t temp;
5434
5435 temp = I915_READ(SOUTH_CHICKEN1);
5436 if (temp & FDI_BC_BIFURCATION_SELECT)
5437 return;
5438
5439 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5440 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5441
5442 temp |= FDI_BC_BIFURCATION_SELECT;
5443 DRM_DEBUG_KMS("enabling fdi C rx\n");
5444 I915_WRITE(SOUTH_CHICKEN1, temp);
5445 POSTING_READ(SOUTH_CHICKEN1);
5446}
5447
5448static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5449{
5450 struct drm_device *dev = intel_crtc->base.dev;
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452 struct intel_crtc *pipe_B_crtc =
5453 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5454
84f44ce7
VS		 5455 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5456 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd 5457 if (intel_crtc->fdi_lanes > 4) {
84f44ce7
VS		 5458 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5459 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5460 /* Clamp lanes to avoid programming the hw with bogus values. */
5461 intel_crtc->fdi_lanes = 4;
5462
5463 return false;
5464 }
5465
7eb552ae 5466 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5467 return true;
5468
5469 switch (intel_crtc->pipe) {
5470 case PIPE_A:
5471 return true;
5472 case PIPE_B:
5473 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5474 intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5475 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5476 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5477 /* Clamp lanes to avoid programming the hw with bogus values. */
5478 intel_crtc->fdi_lanes = 2;
5479
5480 return false;
5481 }
5482
5483 if (intel_crtc->fdi_lanes > 2)
5484 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5485 else
5486 cpt_enable_fdi_bc_bifurcation(dev);
5487
5488 return true;
5489 case PIPE_C:
5490 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5491 if (intel_crtc->fdi_lanes > 2) {
84f44ce7
VS		 5492 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5493 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
01a415fd
DV		 5494 /* Clamp lanes to avoid programming the hw with bogus values. */
5495 intel_crtc->fdi_lanes = 2;
5496
5497 return false;
5498 }
5499 } else {
5500 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5501 return false;
5502 }
5503
5504 cpt_enable_fdi_bc_bifurcation(dev);
5505
5506 return true;
5507 default:
5508 BUG();
5509 }
5510}
5511
d4b1931c
PZ		 5512int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5513{
5514 /*
5515 * Account for spread spectrum to avoid
5516 * oversubscribing the link. Max center spread
5517 * is 2.5%; use 5% for safety's sake.
5518 */
5519 u32 bps = target_clock * bpp * 21 / 20;
5520 return bps / (link_bw * 8) + 1;
5521}
5522
6cf86a5e
DV		 5523void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5524 struct intel_link_m_n *m_n)
79e53945 5525{
6cf86a5e
DV		 5526 struct drm_device *dev = crtc->base.dev;
5527 struct drm_i915_private *dev_priv = dev->dev_private;
5528 int pipe = crtc->pipe;
5529
5530 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5531 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5532 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5533 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5534}
5535
5536void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5537 struct intel_link_m_n *m_n)
5538{
5539 struct drm_device *dev = crtc->base.dev;
79e53945 5540 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5541 int pipe = crtc->pipe;
3b117c8f 5542 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5543
5544 if (INTEL_INFO(dev)->gen >= 5) {
5545 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5546 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5547 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5548 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5549 } else {
5550 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5551 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5552 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5553 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5554 }
5555}
5556
5557static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5558{
5559 struct drm_device *dev = crtc->dev;
79e53945 5560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5561 struct drm_display_mode *adjusted_mode =
5562 &intel_crtc->config.adjusted_mode;
e69d0bc1 5563 struct intel_link_m_n m_n = {0};
6cc5f341 5564 int target_clock, lane, link_bw;
61e9653f 5565
6cf86a5e
DV		 5566 /* FDI is a binary signal running at ~2.7GHz, encoding
5567 * each output octet as 10 bits. The actual frequency
5568 * is stored as a divider into a 100MHz clock, and the
5569 * mode pixel clock is stored in units of 1KHz.
5570 * Hence the bw of each lane in terms of the mode signal
5571 * is:
5572 */
5573 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5574
df92b1e6
DV		 5575 if (intel_crtc->config.pixel_target_clock)
5576 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5577 else
5578 target_clock = adjusted_mode->clock;
5579
6cf86a5e
DV		 5580 lane = ironlake_get_lanes_required(target_clock, link_bw,
5581 intel_crtc->config.pipe_bpp);
2c07245f 5582
8febb297
EA		 5583 intel_crtc->fdi_lanes = lane;
5584
6cc5f341
DV		 5585 if (intel_crtc->config.pixel_multiplier > 1)
5586 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5587 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5588 link_bw, &m_n);
8febb297 5589
6cf86a5e 5590 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5591}
5592
de13a2e3 5593static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9a7c7890
DV		 5594 intel_clock_t *clock, u32 *fp,
5595 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5596{
de13a2e3 5597 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5598 struct drm_device *dev = crtc->dev;
5599 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5600 struct intel_encoder *intel_encoder;
5601 uint32_t dpll;
6cc5f341 5602 int factor, num_connectors = 0;
de13a2e3 5603 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5604
de13a2e3
PZ		 5605 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5606 switch (intel_encoder->type) {
79e53945
JB		 5607 case INTEL_OUTPUT_LVDS:
5608 is_lvds = true;
5609 break;
5610 case INTEL_OUTPUT_SDVO:
7d57382e 5611 case INTEL_OUTPUT_HDMI:
79e53945 5612 is_sdvo = true;
de13a2e3 5613 if (intel_encoder->needs_tv_clock)
e2f0ba97 5614 is_tv = true;
79e53945 5615 break;
79e53945
JB		 5616 case INTEL_OUTPUT_TVOUT:
5617 is_tv = true;
5618 break;
79e53945 5619 }
43565a06 5620
c751ce4f 5621 num_connectors++;
79e53945 5622 }
79e53945 5623
c1858123 5624 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5625 factor = 21;
5626 if (is_lvds) {
5627 if ((intel_panel_use_ssc(dev_priv) &&
5628 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5629 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5630 factor = 25;
5631 } else if (is_sdvo && is_tv)
5632 factor = 20;
c1858123 5633
de13a2e3 5634 if (clock->m < factor * clock->n)
7d0ac5b7 5635 *fp |= FP_CB_TUNE;
2c07245f 5636
9a7c7890
DV		 5637 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5638 *fp2 |= FP_CB_TUNE;
5639
5eddb70b 5640 dpll = 0;
2c07245f 5641
a07d6787
EA		 5642 if (is_lvds)
5643 dpll |= DPLLB_MODE_LVDS;
5644 else
5645 dpll |= DPLLB_MODE_DAC_SERIAL;
5646 if (is_sdvo) {
6cc5f341
DV		 5647 if (intel_crtc->config.pixel_multiplier > 1) {
5648 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5649 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5650 }
a07d6787
EA		 5651 dpll |= DPLL_DVO_HIGH_SPEED;
5652 }
8b47047b
DV		 5653 if (intel_crtc->config.has_dp_encoder &&
5654 intel_crtc->config.has_pch_encoder)
a07d6787 5655 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5656
a07d6787 5657 /* compute bitmask from p1 value */
de13a2e3 5658 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5659 /* also FPA1 */
de13a2e3 5660 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5661
de13a2e3 5662 switch (clock->p2) {
a07d6787
EA		 5663 case 5:
5664 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5665 break;
5666 case 7:
5667 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5668 break;
5669 case 10:
5670 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5671 break;
5672 case 14:
5673 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5674 break;
79e53945
JB		 5675 }
5676
43565a06
KH		 5677 if (is_sdvo && is_tv)
5678 dpll |= PLL_REF_INPUT_TVCLKINBC;
5679 else if (is_tv)
79e53945 5680 /* XXX: just matching BIOS for now */
43565a06 5681 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5682 dpll |= 3;
a7615030 5683 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5684 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5685 else
5686 dpll |= PLL_REF_INPUT_DREFCLK;
5687
de13a2e3
PZ		 5688 return dpll;
5689}
5690
5691static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5692 int x, int y,
5693 struct drm_framebuffer *fb)
5694{
5695 struct drm_device *dev = crtc->dev;
5696 struct drm_i915_private *dev_priv = dev->dev_private;
5697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5698 struct drm_display_mode *adjusted_mode =
5699 &intel_crtc->config.adjusted_mode;
5700 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5701 int pipe = intel_crtc->pipe;
5702 int plane = intel_crtc->plane;
5703 int num_connectors = 0;
5704 intel_clock_t clock, reduced_clock;
5705 u32 dpll, fp = 0, fp2 = 0;
e2f12b07 5706 bool ok, has_reduced_clock = false;
8b47047b 5707 bool is_lvds = false;
de13a2e3 5708 struct intel_encoder *encoder;
de13a2e3 5709 int ret;
01a415fd 5710 bool dither, fdi_config_ok;
de13a2e3
PZ		 5711
5712 for_each_encoder_on_crtc(dev, crtc, encoder) {
5713 switch (encoder->type) {
5714 case INTEL_OUTPUT_LVDS:
5715 is_lvds = true;
5716 break;
de13a2e3
PZ		 5717 }
5718
5719 num_connectors++;
a07d6787 5720 }
79e53945 5721
5dc5298b
PZ		 5722 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5723 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5724
3b117c8f 5725 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5726
de13a2e3
PZ		 5727 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5728 &has_reduced_clock, &reduced_clock);
5729 if (!ok) {
5730 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5731 return -EINVAL;
79e53945 5732 }
f47709a9
DV		 5733 /* Compat-code for transition, will disappear. */
5734 if (!intel_crtc->config.clock_set) {
5735 intel_crtc->config.dpll.n = clock.n;
5736 intel_crtc->config.dpll.m1 = clock.m1;
5737 intel_crtc->config.dpll.m2 = clock.m2;
5738 intel_crtc->config.dpll.p1 = clock.p1;
5739 intel_crtc->config.dpll.p2 = clock.p2;
5740 }
79e53945 5741
de13a2e3
PZ		 5742 /* Ensure that the cursor is valid for the new mode before changing... */
5743 intel_crtc_update_cursor(crtc, true);
5744
5745 /* determine panel color depth */
4e53c2e0 5746 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5747 if (is_lvds && dev_priv->lvds_dither)
5748 dither = true;
5749
5750 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5751 if (has_reduced_clock)
5752 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5753 reduced_clock.m2;
5754
9a7c7890
DV		 5755 dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
5756 has_reduced_clock ? &fp2 : NULL);
79e53945 5757
84f44ce7 5758 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5759 drm_mode_debug_printmodeline(mode);
5760
5dc5298b 5761 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5762 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5763 struct intel_pch_pll *pll;
4b645f14 5764
ee7b9f93
JB		 5765 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5766 if (pll == NULL) {
84f44ce7
VS		 5767 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5768 pipe_name(pipe));
4b645f14
JB		 5769 return -EINVAL;
5770 }
ee7b9f93
JB		 5771 } else
5772 intel_put_pch_pll(intel_crtc);
79e53945 5773
03afc4a2
DV		 5774 if (intel_crtc->config.has_dp_encoder)
5775 intel_dp_set_m_n(intel_crtc);
79e53945 5776
dafd226c
DV		 5777 for_each_encoder_on_crtc(dev, crtc, encoder)
5778 if (encoder->pre_pll_enable)
5779 encoder->pre_pll_enable(encoder);
79e53945 5780
ee7b9f93
JB		 5781 if (intel_crtc->pch_pll) {
5782 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5783
32f9d658 5784 /* Wait for the clocks to stabilize. */
ee7b9f93 5785 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5786 udelay(150);
5787
8febb297
EA		 5788 /* The pixel multiplier can only be updated once the
5789 * DPLL is enabled and the clocks are stable.
5790 *
5791 * So write it again.
5792 */
ee7b9f93 5793 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5794 }
79e53945 5795
5eddb70b 5796 intel_crtc->lowfreq_avail = false;
ee7b9f93 5797 if (intel_crtc->pch_pll) {
4b645f14 5798 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5799 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5800 intel_crtc->lowfreq_avail = true;
4b645f14 5801 } else {
ee7b9f93 5802 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5803 }
5804 }
5805
b0e77b9c 5806 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5807
01a415fd
DV		 5808 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5809 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5810 intel_crtc->fdi_lanes = 0;
5811 if (intel_crtc->config.has_pch_encoder)
5812 ironlake_fdi_set_m_n(crtc);
2c07245f 5813
01a415fd 5814 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5815
c8203565 5816 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5817
a1f9e77e
PZ		 5818 /* Set up the display plane register */
5819 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5820 POSTING_READ(DSPCNTR(plane));
79e53945 5821
94352cf9 5822 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5823
5824 intel_update_watermarks(dev);
5825
1f8eeabf
ED		 5826 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5827
01a415fd 5828 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5829}
5830
0e8ffe1b
DV		 5831static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5832 struct intel_crtc_config *pipe_config)
5833{
5834 struct drm_device *dev = crtc->base.dev;
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5836 uint32_t tmp;
5837
5838 tmp = I915_READ(PIPECONF(crtc->pipe));
5839 if (!(tmp & PIPECONF_ENABLE))
5840 return false;
5841
88adfff1
DV		 5842 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5843 pipe_config->has_pch_encoder = true;
5844
0e8ffe1b
DV		 5845 return true;
5846}
5847
d6dd9eb1
DV		 5848static void haswell_modeset_global_resources(struct drm_device *dev)
5849{
5850 struct drm_i915_private *dev_priv = dev->dev_private;
5851 bool enable = false;
5852 struct intel_crtc *crtc;
5853 struct intel_encoder *encoder;
5854
5855 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5856 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5857 enable = true;
5858 /* XXX: Should check for edp transcoder here, but thanks to init
5859 * sequence that's not yet available. Just in case desktop eDP
5860 * on PORT D is possible on haswell, too. */
5861 }
5862
5863 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5864 base.head) {
5865 if (encoder->type != INTEL_OUTPUT_EDP &&
5866 encoder->connectors_active)
5867 enable = true;
5868 }
5869
5870 /* Even the eDP panel fitter is outside the always-on well. */
5871 if (dev_priv->pch_pf_size)
5872 enable = true;
5873
5874 intel_set_power_well(dev, enable);
5875}
5876
09b4ddf9 5877static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5878 int x, int y,
5879 struct drm_framebuffer *fb)
5880{
5881 struct drm_device *dev = crtc->dev;
5882 struct drm_i915_private *dev_priv = dev->dev_private;
5883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5884 struct drm_display_mode *adjusted_mode =
5885 &intel_crtc->config.adjusted_mode;
5886 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5887 int pipe = intel_crtc->pipe;
5888 int plane = intel_crtc->plane;
5889 int num_connectors = 0;
8b47047b 5890 bool is_cpu_edp = false;
09b4ddf9 5891 struct intel_encoder *encoder;
09b4ddf9
PZ		 5892 int ret;
5893 bool dither;
5894
5895 for_each_encoder_on_crtc(dev, crtc, encoder) {
5896 switch (encoder->type) {
09b4ddf9 5897 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5898 if (!intel_encoder_is_pch_edp(&encoder->base))
5899 is_cpu_edp = true;
5900 break;
5901 }
5902
5903 num_connectors++;
5904 }
5905
bba2181c 5906 if (is_cpu_edp)
3b117c8f 5907 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5908 else
3b117c8f 5909 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5910
5dc5298b
PZ		 5911 /* We are not sure yet this won't happen. */
5912 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5913 INTEL_PCH_TYPE(dev));
5914
5915 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5916 num_connectors, pipe_name(pipe));
5917
3b117c8f 5918 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5919 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5920
5921 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5922
6441ab5f
PZ		 5923 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5924 return -EINVAL;
5925
09b4ddf9
PZ		 5926 /* Ensure that the cursor is valid for the new mode before changing... */
5927 intel_crtc_update_cursor(crtc, true);
5928
5929 /* determine panel color depth */
4e53c2e0 5930 dither = intel_crtc->config.dither;
09b4ddf9 5931
84f44ce7 5932 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5933 drm_mode_debug_printmodeline(mode);
5934
03afc4a2
DV		 5935 if (intel_crtc->config.has_dp_encoder)
5936 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5937
5938 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5939
5940 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5941
6cf86a5e
DV		 5942 if (intel_crtc->config.has_pch_encoder)
5943 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5944
ee2b0b38 5945 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5946
50f3b016 5947 intel_set_pipe_csc(crtc);
86d3efce 5948
09b4ddf9 5949 /* Set up the display plane register */
86d3efce 5950 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5951 POSTING_READ(DSPCNTR(plane));
5952
5953 ret = intel_pipe_set_base(crtc, x, y, fb);
5954
5955 intel_update_watermarks(dev);
5956
5957 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5958
1f803ee5 5959 return ret;
79e53945
JB		 5960}
5961
0e8ffe1b
DV		 5962static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5963 struct intel_crtc_config *pipe_config)
5964{
5965 struct drm_device *dev = crtc->base.dev;
5966 struct drm_i915_private *dev_priv = dev->dev_private;
5967 uint32_t tmp;
5968
3b117c8f 5969 tmp = I915_READ(PIPECONF(crtc->config.cpu_transcoder));
0e8ffe1b
DV		 5970 if (!(tmp & PIPECONF_ENABLE))
5971 return false;
5972
88adfff1
DV		 5973 /*
5974 * aswell has only FDI/PCH transcoder A. It is which is connected to
5975 * DDI E. So just check whether this pipe is wired to DDI E and whether
5976 * the PCH transcoder is on.
5977 */
5978 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
5979 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5980 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5981 pipe_config->has_pch_encoder = true;
5982
5983
0e8ffe1b
DV		 5984 return true;
5985}
5986
f564048e 5987static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5988 int x, int y,
94352cf9 5989 struct drm_framebuffer *fb)
f564048e
EA		 5990{
5991 struct drm_device *dev = crtc->dev;
5992 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5993 struct drm_encoder_helper_funcs *encoder_funcs;
5994 struct intel_encoder *encoder;
0b701d27 5995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5996 struct drm_display_mode *adjusted_mode =
5997 &intel_crtc->config.adjusted_mode;
5998 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5999 int pipe = intel_crtc->pipe;
f564048e
EA		 6000 int ret;
6001
0b701d27 6002 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6003
b8cecdf5
DV		 6004 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6005
79e53945 6006 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6007
9256aa19
DV		 6008 if (ret != 0)
6009 return ret;
6010
6011 for_each_encoder_on_crtc(dev, crtc, encoder) {
6012 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6013 encoder->base.base.id,
6014 drm_get_encoder_name(&encoder->base),
6015 mode->base.id, mode->name);
6cc5f341
DV		 6016 if (encoder->mode_set) {
6017 encoder->mode_set(encoder);
6018 } else {
6019 encoder_funcs = encoder->base.helper_private;
6020 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6021 }
9256aa19
DV		 6022 }
6023
6024 return 0;
79e53945
JB		 6025}
6026
3a9627f4
WF		 6027static bool intel_eld_uptodate(struct drm_connector *connector,
6028 int reg_eldv, uint32_t bits_eldv,
6029 int reg_elda, uint32_t bits_elda,
6030 int reg_edid)
6031{
6032 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6033 uint8_t *eld = connector->eld;
6034 uint32_t i;
6035
6036 i = I915_READ(reg_eldv);
6037 i &= bits_eldv;
6038
6039 if (!eld[0])
6040 return !i;
6041
6042 if (!i)
6043 return false;
6044
6045 i = I915_READ(reg_elda);
6046 i &= ~bits_elda;
6047 I915_WRITE(reg_elda, i);
6048
6049 for (i = 0; i < eld[2]; i++)
6050 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6051 return false;
6052
6053 return true;
6054}
6055
e0dac65e
WF		 6056static void g4x_write_eld(struct drm_connector *connector,
6057 struct drm_crtc *crtc)
6058{
6059 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6060 uint8_t *eld = connector->eld;
6061 uint32_t eldv;
6062 uint32_t len;
6063 uint32_t i;
6064
6065 i = I915_READ(G4X_AUD_VID_DID);
6066
6067 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6068 eldv = G4X_ELDV_DEVCL_DEVBLC;
6069 else
6070 eldv = G4X_ELDV_DEVCTG;
6071
3a9627f4
WF		 6072 if (intel_eld_uptodate(connector,
6073 G4X_AUD_CNTL_ST, eldv,
6074 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6075 G4X_HDMIW_HDMIEDID))
6076 return;
6077
e0dac65e
WF		 6078 i = I915_READ(G4X_AUD_CNTL_ST);
6079 i &= ~(eldv | G4X_ELD_ADDR);
6080 len = (i >> 9) & 0x1f; /* ELD buffer size */
6081 I915_WRITE(G4X_AUD_CNTL_ST, i);
6082
6083 if (!eld[0])
6084 return;
6085
6086 len = min_t(uint8_t, eld[2], len);
6087 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6088 for (i = 0; i < len; i++)
6089 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6090
6091 i = I915_READ(G4X_AUD_CNTL_ST);
6092 i |= eldv;
6093 I915_WRITE(G4X_AUD_CNTL_ST, i);
6094}
6095
83358c85
WX		 6096static void haswell_write_eld(struct drm_connector *connector,
6097 struct drm_crtc *crtc)
6098{
6099 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6100 uint8_t *eld = connector->eld;
6101 struct drm_device *dev = crtc->dev;
7b9f35a6 6102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6103 uint32_t eldv;
6104 uint32_t i;
6105 int len;
6106 int pipe = to_intel_crtc(crtc)->pipe;
6107 int tmp;
6108
6109 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6110 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6111 int aud_config = HSW_AUD_CFG(pipe);
6112 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6113
6114
6115 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6116
6117 /* Audio output enable */
6118 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6119 tmp = I915_READ(aud_cntrl_st2);
6120 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6121 I915_WRITE(aud_cntrl_st2, tmp);
6122
6123 /* Wait for 1 vertical blank */
6124 intel_wait_for_vblank(dev, pipe);
6125
6126 /* Set ELD valid state */
6127 tmp = I915_READ(aud_cntrl_st2);
6128 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6129 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6130 I915_WRITE(aud_cntrl_st2, tmp);
6131 tmp = I915_READ(aud_cntrl_st2);
6132 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6133
6134 /* Enable HDMI mode */
6135 tmp = I915_READ(aud_config);
6136 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6137 /* clear N_programing_enable and N_value_index */
6138 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6139 I915_WRITE(aud_config, tmp);
6140
6141 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6142
6143 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6144 intel_crtc->eld_vld = true;
83358c85
WX		 6145
6146 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6147 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6148 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6149 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6150 } else
6151 I915_WRITE(aud_config, 0);
6152
6153 if (intel_eld_uptodate(connector,
6154 aud_cntrl_st2, eldv,
6155 aud_cntl_st, IBX_ELD_ADDRESS,
6156 hdmiw_hdmiedid))
6157 return;
6158
6159 i = I915_READ(aud_cntrl_st2);
6160 i &= ~eldv;
6161 I915_WRITE(aud_cntrl_st2, i);
6162
6163 if (!eld[0])
6164 return;
6165
6166 i = I915_READ(aud_cntl_st);
6167 i &= ~IBX_ELD_ADDRESS;
6168 I915_WRITE(aud_cntl_st, i);
6169 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6170 DRM_DEBUG_DRIVER("port num:%d\n", i);
6171
6172 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6173 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6174 for (i = 0; i < len; i++)
6175 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6176
6177 i = I915_READ(aud_cntrl_st2);
6178 i |= eldv;
6179 I915_WRITE(aud_cntrl_st2, i);
6180
6181}
6182
e0dac65e
WF		 6183static void ironlake_write_eld(struct drm_connector *connector,
6184 struct drm_crtc *crtc)
6185{
6186 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6187 uint8_t *eld = connector->eld;
6188 uint32_t eldv;
6189 uint32_t i;
6190 int len;
6191 int hdmiw_hdmiedid;
b6daa025 6192 int aud_config;
e0dac65e
WF		 6193 int aud_cntl_st;
6194 int aud_cntrl_st2;
9b138a83 6195 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6196
b3f33cbf 6197 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6198 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6199 aud_config = IBX_AUD_CFG(pipe);
6200 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6201 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6202 } else {
9b138a83
WX		 6203 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6204 aud_config = CPT_AUD_CFG(pipe);
6205 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6206 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6207 }
6208
9b138a83 6209 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6210
6211 i = I915_READ(aud_cntl_st);
9b138a83 6212 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6213 if (!i) {
6214 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6215 /* operate blindly on all ports */
1202b4c6
WF		 6216 eldv = IBX_ELD_VALIDB;
6217 eldv |= IBX_ELD_VALIDB << 4;
6218 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6219 } else {
2582a850 6220 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6221 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6222 }
6223
3a9627f4
WF		 6224 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6225 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6226 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6227 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6228 } else
6229 I915_WRITE(aud_config, 0);
e0dac65e 6230
3a9627f4
WF		 6231 if (intel_eld_uptodate(connector,
6232 aud_cntrl_st2, eldv,
6233 aud_cntl_st, IBX_ELD_ADDRESS,
6234 hdmiw_hdmiedid))
6235 return;
6236
e0dac65e
WF		 6237 i = I915_READ(aud_cntrl_st2);
6238 i &= ~eldv;
6239 I915_WRITE(aud_cntrl_st2, i);
6240
6241 if (!eld[0])
6242 return;
6243
e0dac65e 6244 i = I915_READ(aud_cntl_st);
1202b4c6 6245 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6246 I915_WRITE(aud_cntl_st, i);
6247
6248 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6249 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6250 for (i = 0; i < len; i++)
6251 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6252
6253 i = I915_READ(aud_cntrl_st2);
6254 i |= eldv;
6255 I915_WRITE(aud_cntrl_st2, i);
6256}
6257
6258void intel_write_eld(struct drm_encoder *encoder,
6259 struct drm_display_mode *mode)
6260{
6261 struct drm_crtc *crtc = encoder->crtc;
6262 struct drm_connector *connector;
6263 struct drm_device *dev = encoder->dev;
6264 struct drm_i915_private *dev_priv = dev->dev_private;
6265
6266 connector = drm_select_eld(encoder, mode);
6267 if (!connector)
6268 return;
6269
6270 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6271 connector->base.id,
6272 drm_get_connector_name(connector),
6273 connector->encoder->base.id,
6274 drm_get_encoder_name(connector->encoder));
6275
6276 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6277
6278 if (dev_priv->display.write_eld)
6279 dev_priv->display.write_eld(connector, crtc);
6280}
6281
79e53945
JB		 6282/** Loads the palette/gamma unit for the CRTC with the prepared values */
6283void intel_crtc_load_lut(struct drm_crtc *crtc)
6284{
6285 struct drm_device *dev = crtc->dev;
6286 struct drm_i915_private *dev_priv = dev->dev_private;
6287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6288 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6289 int i;
6290
6291 /* The clocks have to be on to load the palette. */
aed3f09d 6292 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6293 return;
6294
f2b115e6 6295 /* use legacy palette for Ironlake */
bad720ff 6296 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6297 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6298
79e53945
JB		 6299 for (i = 0; i < 256; i++) {
6300 I915_WRITE(palreg + 4 * i,
6301 (intel_crtc->lut_r[i] << 16) |
6302 (intel_crtc->lut_g[i] << 8) |
6303 intel_crtc->lut_b[i]);
6304 }
6305}
6306
560b85bb
CW		 6307static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6308{
6309 struct drm_device *dev = crtc->dev;
6310 struct drm_i915_private *dev_priv = dev->dev_private;
6311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6312 bool visible = base != 0;
6313 u32 cntl;
6314
6315 if (intel_crtc->cursor_visible == visible)
6316 return;
6317
9db4a9c7 6318 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6319 if (visible) {
6320 /* On these chipsets we can only modify the base whilst
6321 * the cursor is disabled.
6322 */
9db4a9c7 6323 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6324
6325 cntl &= ~(CURSOR_FORMAT_MASK);
6326 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6327 cntl |= CURSOR_ENABLE |
6328 CURSOR_GAMMA_ENABLE |
6329 CURSOR_FORMAT_ARGB;
6330 } else
6331 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6332 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6333
6334 intel_crtc->cursor_visible = visible;
6335}
6336
6337static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6338{
6339 struct drm_device *dev = crtc->dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6342 int pipe = intel_crtc->pipe;
6343 bool visible = base != 0;
6344
6345 if (intel_crtc->cursor_visible != visible) {
548f245b 6346 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6347 if (base) {
6348 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6349 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6350 cntl |= pipe << 28; /* Connect to correct pipe */
6351 } else {
6352 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6353 cntl |= CURSOR_MODE_DISABLE;
6354 }
9db4a9c7 6355 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6356
6357 intel_crtc->cursor_visible = visible;
6358 }
6359 /* and commit changes on next vblank */
9db4a9c7 6360 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6361}
6362
65a21cd6
JB		 6363static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6364{
6365 struct drm_device *dev = crtc->dev;
6366 struct drm_i915_private *dev_priv = dev->dev_private;
6367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6368 int pipe = intel_crtc->pipe;
6369 bool visible = base != 0;
6370
6371 if (intel_crtc->cursor_visible != visible) {
6372 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6373 if (base) {
6374 cntl &= ~CURSOR_MODE;
6375 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6376 } else {
6377 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6378 cntl |= CURSOR_MODE_DISABLE;
6379 }
86d3efce
VS		 6380 if (IS_HASWELL(dev))
6381 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6382 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6383
6384 intel_crtc->cursor_visible = visible;
6385 }
6386 /* and commit changes on next vblank */
6387 I915_WRITE(CURBASE_IVB(pipe), base);
6388}
6389
cda4b7d3 6390/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6391static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6392 bool on)
cda4b7d3
CW		 6393{
6394 struct drm_device *dev = crtc->dev;
6395 struct drm_i915_private *dev_priv = dev->dev_private;
6396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6397 int pipe = intel_crtc->pipe;
6398 int x = intel_crtc->cursor_x;
6399 int y = intel_crtc->cursor_y;
560b85bb 6400 u32 base, pos;
cda4b7d3
CW		 6401 bool visible;
6402
6403 pos = 0;
6404
6b383a7f 6405 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6406 base = intel_crtc->cursor_addr;
6407 if (x > (int) crtc->fb->width)
6408 base = 0;
6409
6410 if (y > (int) crtc->fb->height)
6411 base = 0;
6412 } else
6413 base = 0;
6414
6415 if (x < 0) {
6416 if (x + intel_crtc->cursor_width < 0)
6417 base = 0;
6418
6419 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6420 x = -x;
6421 }
6422 pos |= x << CURSOR_X_SHIFT;
6423
6424 if (y < 0) {
6425 if (y + intel_crtc->cursor_height < 0)
6426 base = 0;
6427
6428 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6429 y = -y;
6430 }
6431 pos |= y << CURSOR_Y_SHIFT;
6432
6433 visible = base != 0;
560b85bb 6434 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6435 return;
6436
0cd83aa9 6437 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6438 I915_WRITE(CURPOS_IVB(pipe), pos);
6439 ivb_update_cursor(crtc, base);
6440 } else {
6441 I915_WRITE(CURPOS(pipe), pos);
6442 if (IS_845G(dev) || IS_I865G(dev))
6443 i845_update_cursor(crtc, base);
6444 else
6445 i9xx_update_cursor(crtc, base);
6446 }
cda4b7d3
CW		 6447}
6448
79e53945 6449static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6450 struct drm_file *file,
79e53945
JB		 6451 uint32_t handle,
6452 uint32_t width, uint32_t height)
6453{
6454 struct drm_device *dev = crtc->dev;
6455 struct drm_i915_private *dev_priv = dev->dev_private;
6456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6457 struct drm_i915_gem_object *obj;
cda4b7d3 6458 uint32_t addr;
3f8bc370 6459 int ret;
79e53945 6460
79e53945
JB		 6461 /* if we want to turn off the cursor ignore width and height */
6462 if (!handle) {
28c97730 6463 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6464 addr = 0;
05394f39 6465 obj = NULL;
5004417d 6466 mutex_lock(&dev->struct_mutex);
3f8bc370 6467 goto finish;
79e53945
JB		 6468 }
6469
6470 /* Currently we only support 64x64 cursors */
6471 if (width != 64 || height != 64) {
6472 DRM_ERROR("we currently only support 64x64 cursors\n");
6473 return -EINVAL;
6474 }
6475
05394f39 6476 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6477 if (&obj->base == NULL)
79e53945
JB		 6478 return -ENOENT;
6479
05394f39 6480 if (obj->base.size < width * height * 4) {
79e53945 6481 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6482 ret = -ENOMEM;
6483 goto fail;
79e53945
JB		 6484 }
6485
71acb5eb 6486 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6487 mutex_lock(&dev->struct_mutex);
b295d1b6 6488 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6489 unsigned alignment;
6490
d9e86c0e
CW		 6491 if (obj->tiling_mode) {
6492 DRM_ERROR("cursor cannot be tiled\n");
6493 ret = -EINVAL;
6494 goto fail_locked;
6495 }
6496
693db184
CW		 6497 /* Note that the w/a also requires 2 PTE of padding following
6498 * the bo. We currently fill all unused PTE with the shadow
6499 * page and so we should always have valid PTE following the
6500 * cursor preventing the VT-d warning.
6501 */
6502 alignment = 0;
6503 if (need_vtd_wa(dev))
6504 alignment = 64*1024;
6505
6506 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6507 if (ret) {
6508 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6509 goto fail_locked;
e7b526bb
CW		 6510 }
6511
d9e86c0e
CW		 6512 ret = i915_gem_object_put_fence(obj);
6513 if (ret) {
2da3b9b9 6514 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6515 goto fail_unpin;
6516 }
6517
05394f39 6518 addr = obj->gtt_offset;
71acb5eb 6519 } else {
6eeefaf3 6520 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6521 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6522 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6523 align);
71acb5eb
DA		 6524 if (ret) {
6525 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6526 goto fail_locked;
71acb5eb 6527 }
05394f39 6528 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6529 }
6530
a6c45cf0 6531 if (IS_GEN2(dev))
14b60391
JB		 6532 I915_WRITE(CURSIZE, (height << 12) | width);
6533
3f8bc370 6534 finish:
3f8bc370 6535 if (intel_crtc->cursor_bo) {
b295d1b6 6536 if (dev_priv->info->cursor_needs_physical) {
05394f39 6537 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6538 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6539 } else
6540 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6541 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6542 }
80824003 6543
7f9872e0 6544 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6545
6546 intel_crtc->cursor_addr = addr;
05394f39 6547 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6548 intel_crtc->cursor_width = width;
6549 intel_crtc->cursor_height = height;
6550
6b383a7f 6551 intel_crtc_update_cursor(crtc, true);
3f8bc370 6552
79e53945 6553 return 0;
e7b526bb 6554fail_unpin:
05394f39 6555 i915_gem_object_unpin(obj);
7f9872e0 6556fail_locked:
34b8686e 6557 mutex_unlock(&dev->struct_mutex);
bc9025bd 6558fail:
05394f39 6559 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6560 return ret;
79e53945
JB		 6561}
6562
6563static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6564{
79e53945 6565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6566
cda4b7d3
CW		 6567 intel_crtc->cursor_x = x;
6568 intel_crtc->cursor_y = y;
652c393a 6569
6b383a7f 6570 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6571
6572 return 0;
6573}
6574
6575/** Sets the color ramps on behalf of RandR */
6576void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6577 u16 blue, int regno)
6578{
6579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6580
6581 intel_crtc->lut_r[regno] = red >> 8;
6582 intel_crtc->lut_g[regno] = green >> 8;
6583 intel_crtc->lut_b[regno] = blue >> 8;
6584}
6585
b8c00ac5
DA		 6586void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6587 u16 *blue, int regno)
6588{
6589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6590
6591 *red = intel_crtc->lut_r[regno] << 8;
6592 *green = intel_crtc->lut_g[regno] << 8;
6593 *blue = intel_crtc->lut_b[regno] << 8;
6594}
6595
79e53945 6596static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6597 u16 *blue, uint32_t start, uint32_t size)
79e53945 6598{
7203425a 6599 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6601
7203425a 6602 for (i = start; i < end; i++) {
79e53945
JB		 6603 intel_crtc->lut_r[i] = red[i] >> 8;
6604 intel_crtc->lut_g[i] = green[i] >> 8;
6605 intel_crtc->lut_b[i] = blue[i] >> 8;
6606 }
6607
6608 intel_crtc_load_lut(crtc);
6609}
6610
79e53945
JB		 6611/* VESA 640x480x72Hz mode to set on the pipe */
6612static struct drm_display_mode load_detect_mode = {
6613 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6614 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6615};
6616
d2dff872
CW		 6617static struct drm_framebuffer *
6618intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6619 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6620 struct drm_i915_gem_object *obj)
6621{
6622 struct intel_framebuffer *intel_fb;
6623 int ret;
6624
6625 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6626 if (!intel_fb) {
6627 drm_gem_object_unreference_unlocked(&obj->base);
6628 return ERR_PTR(-ENOMEM);
6629 }
6630
6631 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6632 if (ret) {
6633 drm_gem_object_unreference_unlocked(&obj->base);
6634 kfree(intel_fb);
6635 return ERR_PTR(ret);
6636 }
6637
6638 return &intel_fb->base;
6639}
6640
6641static u32
6642intel_framebuffer_pitch_for_width(int width, int bpp)
6643{
6644 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6645 return ALIGN(pitch, 64);
6646}
6647
6648static u32
6649intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6650{
6651 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6652 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6653}
6654
6655static struct drm_framebuffer *
6656intel_framebuffer_create_for_mode(struct drm_device *dev,
6657 struct drm_display_mode *mode,
6658 int depth, int bpp)
6659{
6660 struct drm_i915_gem_object *obj;
0fed39bd 6661 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6662
6663 obj = i915_gem_alloc_object(dev,
6664 intel_framebuffer_size_for_mode(mode, bpp));
6665 if (obj == NULL)
6666 return ERR_PTR(-ENOMEM);
6667
6668 mode_cmd.width = mode->hdisplay;
6669 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6670 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6671 bpp);
5ca0c34a 6672 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6673
6674 return intel_framebuffer_create(dev, &mode_cmd, obj);
6675}
6676
6677static struct drm_framebuffer *
6678mode_fits_in_fbdev(struct drm_device *dev,
6679 struct drm_display_mode *mode)
6680{
6681 struct drm_i915_private *dev_priv = dev->dev_private;
6682 struct drm_i915_gem_object *obj;
6683 struct drm_framebuffer *fb;
6684
6685 if (dev_priv->fbdev == NULL)
6686 return NULL;
6687
6688 obj = dev_priv->fbdev->ifb.obj;
6689 if (obj == NULL)
6690 return NULL;
6691
6692 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6693 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6694 fb->bits_per_pixel))
d2dff872
CW		 6695 return NULL;
6696
01f2c773 6697 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6698 return NULL;
6699
6700 return fb;
6701}
6702
d2434ab7 6703bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6704 struct drm_display_mode *mode,
8261b191 6705 struct intel_load_detect_pipe *old)
79e53945
JB		 6706{
6707 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6708 struct intel_encoder *intel_encoder =
6709 intel_attached_encoder(connector);
79e53945 6710 struct drm_crtc *possible_crtc;
4ef69c7a 6711 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6712 struct drm_crtc *crtc = NULL;
6713 struct drm_device *dev = encoder->dev;
94352cf9 6714 struct drm_framebuffer *fb;
79e53945
JB		 6715 int i = -1;
6716
d2dff872
CW		 6717 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6718 connector->base.id, drm_get_connector_name(connector),
6719 encoder->base.id, drm_get_encoder_name(encoder));
6720
79e53945
JB		 6721 /*
6722 * Algorithm gets a little messy:
7a5e4805 6723 *
79e53945
JB		 6724 * - if the connector already has an assigned crtc, use it (but make
6725 * sure it's on first)
7a5e4805 6726 *
79e53945
JB		 6727 * - try to find the first unused crtc that can drive this connector,
6728 * and use that if we find one
79e53945
JB		 6729 */
6730
6731 /* See if we already have a CRTC for this connector */
6732 if (encoder->crtc) {
6733 crtc = encoder->crtc;
8261b191 6734
7b24056b
DV		 6735 mutex_lock(&crtc->mutex);
6736
24218aac 6737 old->dpms_mode = connector->dpms;
8261b191
CW		 6738 old->load_detect_temp = false;
6739
6740 /* Make sure the crtc and connector are running */
24218aac
DV		 6741 if (connector->dpms != DRM_MODE_DPMS_ON)
6742 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6743
7173188d 6744 return true;
79e53945
JB		 6745 }
6746
6747 /* Find an unused one (if possible) */
6748 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6749 i++;
6750 if (!(encoder->possible_crtcs & (1 << i)))
6751 continue;
6752 if (!possible_crtc->enabled) {
6753 crtc = possible_crtc;
6754 break;
6755 }
79e53945
JB		 6756 }
6757
6758 /*
6759 * If we didn't find an unused CRTC, don't use any.
6760 */
6761 if (!crtc) {
7173188d
CW		 6762 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6763 return false;
79e53945
JB		 6764 }
6765
7b24056b 6766 mutex_lock(&crtc->mutex);
fc303101
DV		 6767 intel_encoder->new_crtc = to_intel_crtc(crtc);
6768 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6769
6770 intel_crtc = to_intel_crtc(crtc);
24218aac 6771 old->dpms_mode = connector->dpms;
8261b191 6772 old->load_detect_temp = true;
d2dff872 6773 old->release_fb = NULL;
79e53945 6774
6492711d
CW		 6775 if (!mode)
6776 mode = &load_detect_mode;
79e53945 6777
d2dff872
CW		 6778 /* We need a framebuffer large enough to accommodate all accesses
6779 * that the plane may generate whilst we perform load detection.
6780 * We can not rely on the fbcon either being present (we get called
6781 * during its initialisation to detect all boot displays, or it may
6782 * not even exist) or that it is large enough to satisfy the
6783 * requested mode.
6784 */
94352cf9
DV		 6785 fb = mode_fits_in_fbdev(dev, mode);
6786 if (fb == NULL) {
d2dff872 6787 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6788 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6789 old->release_fb = fb;
d2dff872
CW		 6790 } else
6791 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6792 if (IS_ERR(fb)) {
d2dff872 6793 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6794 mutex_unlock(&crtc->mutex);
0e8b3d3e 6795 return false;
79e53945 6796 }
79e53945 6797
c0c36b94 6798 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6799 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6800 if (old->release_fb)
6801 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6802 mutex_unlock(&crtc->mutex);
0e8b3d3e 6803 return false;
79e53945 6804 }
7173188d 6805
79e53945 6806 /* let the connector get through one full cycle before testing */
9d0498a2 6807 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6808 return true;
79e53945
JB		 6809}
6810
d2434ab7 6811void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6812 struct intel_load_detect_pipe *old)
79e53945 6813{
d2434ab7
DV		 6814 struct intel_encoder *intel_encoder =
6815 intel_attached_encoder(connector);
4ef69c7a 6816 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6817 struct drm_crtc *crtc = encoder->crtc;
79e53945 6818
d2dff872
CW		 6819 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6820 connector->base.id, drm_get_connector_name(connector),
6821 encoder->base.id, drm_get_encoder_name(encoder));
6822
8261b191 6823 if (old->load_detect_temp) {
fc303101
DV		 6824 to_intel_connector(connector)->new_encoder = NULL;
6825 intel_encoder->new_crtc = NULL;
6826 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6827
36206361
DV		 6828 if (old->release_fb) {
6829 drm_framebuffer_unregister_private(old->release_fb);
6830 drm_framebuffer_unreference(old->release_fb);
6831 }
d2dff872 6832
67c96400 6833 mutex_unlock(&crtc->mutex);
0622a53c 6834 return;
79e53945
JB		 6835 }
6836
c751ce4f 6837 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6838 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6839 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6840
6841 mutex_unlock(&crtc->mutex);
79e53945
JB		 6842}
6843
6844/* Returns the clock of the currently programmed mode of the given pipe. */
6845static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6846{
6847 struct drm_i915_private *dev_priv = dev->dev_private;
6848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6849 int pipe = intel_crtc->pipe;
548f245b 6850 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6851 u32 fp;
6852 intel_clock_t clock;
6853
6854 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6855 fp = I915_READ(FP0(pipe));
79e53945 6856 else
39adb7a5 6857 fp = I915_READ(FP1(pipe));
79e53945
JB		 6858
6859 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6860 if (IS_PINEVIEW(dev)) {
6861 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6862 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6863 } else {
6864 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6865 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6866 }
6867
a6c45cf0 6868 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6869 if (IS_PINEVIEW(dev))
6870 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6871 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6872 else
6873 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6874 DPLL_FPA01_P1_POST_DIV_SHIFT);
6875
6876 switch (dpll & DPLL_MODE_MASK) {
6877 case DPLLB_MODE_DAC_SERIAL:
6878 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6879 5 : 10;
6880 break;
6881 case DPLLB_MODE_LVDS:
6882 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6883 7 : 14;
6884 break;
6885 default:
28c97730 6886 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6887 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6888 return 0;
6889 }
6890
6891 /* XXX: Handle the 100Mhz refclk */
2177832f 6892 intel_clock(dev, 96000, &clock);
79e53945
JB		 6893 } else {
6894 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6895
6896 if (is_lvds) {
6897 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6898 DPLL_FPA01_P1_POST_DIV_SHIFT);
6899 clock.p2 = 14;
6900
6901 if ((dpll & PLL_REF_INPUT_MASK) ==
6902 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6903 /* XXX: might not be 66MHz */
2177832f 6904 intel_clock(dev, 66000, &clock);
79e53945 6905 } else
2177832f 6906 intel_clock(dev, 48000, &clock);
79e53945
JB		 6907 } else {
6908 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6909 clock.p1 = 2;
6910 else {
6911 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6912 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6913 }
6914 if (dpll & PLL_P2_DIVIDE_BY_4)
6915 clock.p2 = 4;
6916 else
6917 clock.p2 = 2;
6918
2177832f 6919 intel_clock(dev, 48000, &clock);
79e53945
JB		 6920 }
6921 }
6922
6923 /* XXX: It would be nice to validate the clocks, but we can't reuse
6924 * i830PllIsValid() because it relies on the xf86_config connector
6925 * configuration being accurate, which it isn't necessarily.
6926 */
6927
6928 return clock.dot;
6929}
6930
6931/** Returns the currently programmed mode of the given pipe. */
6932struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6933 struct drm_crtc *crtc)
6934{
548f245b 6935 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6937 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6938 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6939 int htot = I915_READ(HTOTAL(cpu_transcoder));
6940 int hsync = I915_READ(HSYNC(cpu_transcoder));
6941 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6942 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6943
6944 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6945 if (!mode)
6946 return NULL;
6947
6948 mode->clock = intel_crtc_clock_get(dev, crtc);
6949 mode->hdisplay = (htot & 0xffff) + 1;
6950 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6951 mode->hsync_start = (hsync & 0xffff) + 1;
6952 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6953 mode->vdisplay = (vtot & 0xffff) + 1;
6954 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6955 mode->vsync_start = (vsync & 0xffff) + 1;
6956 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6957
6958 drm_mode_set_name(mode);
79e53945
JB		 6959
6960 return mode;
6961}
6962
3dec0095 6963static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6964{
6965 struct drm_device *dev = crtc->dev;
6966 drm_i915_private_t *dev_priv = dev->dev_private;
6967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6968 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6969 int dpll_reg = DPLL(pipe);
6970 int dpll;
652c393a 6971
bad720ff 6972 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6973 return;
6974
6975 if (!dev_priv->lvds_downclock_avail)
6976 return;
6977
dbdc6479 6978 dpll = I915_READ(dpll_reg);
652c393a 6979 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6980 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6981
8ac5a6d5 6982 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6983
6984 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6985 I915_WRITE(dpll_reg, dpll);
9d0498a2 6986 intel_wait_for_vblank(dev, pipe);
dbdc6479 6987
652c393a
JB		 6988 dpll = I915_READ(dpll_reg);
6989 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6990 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6991 }
652c393a
JB		 6992}
6993
6994static void intel_decrease_pllclock(struct drm_crtc *crtc)
6995{
6996 struct drm_device *dev = crtc->dev;
6997 drm_i915_private_t *dev_priv = dev->dev_private;
6998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6999
bad720ff 7000 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7001 return;
7002
7003 if (!dev_priv->lvds_downclock_avail)
7004 return;
7005
7006 /*
7007 * Since this is called by a timer, we should never get here in
7008 * the manual case.
7009 */
7010 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7011 int pipe = intel_crtc->pipe;
7012 int dpll_reg = DPLL(pipe);
7013 int dpll;
f6e5b160 7014
44d98a61 7015 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7016
8ac5a6d5 7017 assert_panel_unlocked(dev_priv, pipe);
652c393a 7018
dc257cf1 7019 dpll = I915_READ(dpll_reg);
652c393a
JB		 7020 dpll |= DISPLAY_RATE_SELECT_FPA1;
7021 I915_WRITE(dpll_reg, dpll);
9d0498a2 7022 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7023 dpll = I915_READ(dpll_reg);
7024 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7025 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7026 }
7027
7028}
7029
f047e395
CW		 7030void intel_mark_busy(struct drm_device *dev)
7031{
f047e395
CW		 7032 i915_update_gfx_val(dev->dev_private);
7033}
7034
7035void intel_mark_idle(struct drm_device *dev)
652c393a 7036{
652c393a 7037 struct drm_crtc *crtc;
652c393a
JB		 7038
7039 if (!i915_powersave)
7040 return;
7041
652c393a 7042 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7043 if (!crtc->fb)
7044 continue;
7045
725a5b54 7046 intel_decrease_pllclock(crtc);
652c393a 7047 }
652c393a
JB		 7048}
7049
725a5b54 7050void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7051{
f047e395
CW		 7052 struct drm_device *dev = obj->base.dev;
7053 struct drm_crtc *crtc;
652c393a 7054
f047e395 7055 if (!i915_powersave)
acb87dfb
CW		 7056 return;
7057
652c393a
JB		 7058 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7059 if (!crtc->fb)
7060 continue;
7061
f047e395 7062 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7063 intel_increase_pllclock(crtc);
652c393a
JB		 7064 }
7065}
7066
79e53945
JB		 7067static void intel_crtc_destroy(struct drm_crtc *crtc)
7068{
7069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7070 struct drm_device *dev = crtc->dev;
7071 struct intel_unpin_work *work;
7072 unsigned long flags;
7073
7074 spin_lock_irqsave(&dev->event_lock, flags);
7075 work = intel_crtc->unpin_work;
7076 intel_crtc->unpin_work = NULL;
7077 spin_unlock_irqrestore(&dev->event_lock, flags);
7078
7079 if (work) {
7080 cancel_work_sync(&work->work);
7081 kfree(work);
7082 }
79e53945
JB		 7083
7084 drm_crtc_cleanup(crtc);
67e77c5a 7085
79e53945
JB		 7086 kfree(intel_crtc);
7087}
7088
6b95a207
KH		 7089static void intel_unpin_work_fn(struct work_struct *__work)
7090{
7091 struct intel_unpin_work *work =
7092 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7093 struct drm_device *dev = work->crtc->dev;
6b95a207 7094
b4a98e57 7095 mutex_lock(&dev->struct_mutex);
1690e1eb 7096 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7097 drm_gem_object_unreference(&work->pending_flip_obj->base);
7098 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7099
b4a98e57
CW		 7100 intel_update_fbc(dev);
7101 mutex_unlock(&dev->struct_mutex);
7102
7103 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7104 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7105
6b95a207
KH		 7106 kfree(work);
7107}
7108
1afe3e9d 7109static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7110 struct drm_crtc *crtc)
6b95a207
KH		 7111{
7112 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7114 struct intel_unpin_work *work;
6b95a207
KH		 7115 unsigned long flags;
7116
7117 /* Ignore early vblank irqs */
7118 if (intel_crtc == NULL)
7119 return;
7120
7121 spin_lock_irqsave(&dev->event_lock, flags);
7122 work = intel_crtc->unpin_work;
e7d841ca
CW		 7123
7124 /* Ensure we don't miss a work->pending update ... */
7125 smp_rmb();
7126
7127 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7128 spin_unlock_irqrestore(&dev->event_lock, flags);
7129 return;
7130 }
7131
e7d841ca
CW		 7132 /* and that the unpin work is consistent wrt ->pending. */
7133 smp_rmb();
7134
6b95a207 7135 intel_crtc->unpin_work = NULL;
6b95a207 7136
45a066eb
RC		 7137 if (work->event)
7138 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7139
0af7e4df
MK		 7140 drm_vblank_put(dev, intel_crtc->pipe);
7141
6b95a207
KH		 7142 spin_unlock_irqrestore(&dev->event_lock, flags);
7143
2c10d571 7144 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7145
7146 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7147
7148 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7149}
7150
1afe3e9d
JB		 7151void intel_finish_page_flip(struct drm_device *dev, int pipe)
7152{
7153 drm_i915_private_t *dev_priv = dev->dev_private;
7154 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7155
49b14a5c 7156 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7157}
7158
7159void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7160{
7161 drm_i915_private_t *dev_priv = dev->dev_private;
7162 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7163
49b14a5c 7164 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7165}
7166
6b95a207
KH		 7167void intel_prepare_page_flip(struct drm_device *dev, int plane)
7168{
7169 drm_i915_private_t *dev_priv = dev->dev_private;
7170 struct intel_crtc *intel_crtc =
7171 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7172 unsigned long flags;
7173
e7d841ca
CW		 7174 /* NB: An MMIO update of the plane base pointer will also
7175 * generate a page-flip completion irq, i.e. every modeset
7176 * is also accompanied by a spurious intel_prepare_page_flip().
7177 */
6b95a207 7178 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7179 if (intel_crtc->unpin_work)
7180 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7181 spin_unlock_irqrestore(&dev->event_lock, flags);
7182}
7183
e7d841ca
CW		 7184inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7185{
7186 /* Ensure that the work item is consistent when activating it ... */
7187 smp_wmb();
7188 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7189 /* and that it is marked active as soon as the irq could fire. */
7190 smp_wmb();
7191}
7192
8c9f3aaf
JB		 7193static int intel_gen2_queue_flip(struct drm_device *dev,
7194 struct drm_crtc *crtc,
7195 struct drm_framebuffer *fb,
7196 struct drm_i915_gem_object *obj)
7197{
7198 struct drm_i915_private *dev_priv = dev->dev_private;
7199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7200 u32 flip_mask;
6d90c952 7201 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7202 int ret;
7203
6d90c952 7204 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7205 if (ret)
83d4092b 7206 goto err;
8c9f3aaf 7207
6d90c952 7208 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7209 if (ret)
83d4092b 7210 goto err_unpin;
8c9f3aaf
JB		 7211
7212 /* Can't queue multiple flips, so wait for the previous
7213 * one to finish before executing the next.
7214 */
7215 if (intel_crtc->plane)
7216 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7217 else
7218 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7219 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7220 intel_ring_emit(ring, MI_NOOP);
7221 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7222 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7223 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7224 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7225 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7226
7227 intel_mark_page_flip_active(intel_crtc);
6d90c952 7228 intel_ring_advance(ring);
83d4092b
CW		 7229 return 0;
7230
7231err_unpin:
7232 intel_unpin_fb_obj(obj);
7233err:
8c9f3aaf
JB		 7234 return ret;
7235}
7236
7237static int intel_gen3_queue_flip(struct drm_device *dev,
7238 struct drm_crtc *crtc,
7239 struct drm_framebuffer *fb,
7240 struct drm_i915_gem_object *obj)
7241{
7242 struct drm_i915_private *dev_priv = dev->dev_private;
7243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7244 u32 flip_mask;
6d90c952 7245 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7246 int ret;
7247
6d90c952 7248 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7249 if (ret)
83d4092b 7250 goto err;
8c9f3aaf 7251
6d90c952 7252 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7253 if (ret)
83d4092b 7254 goto err_unpin;
8c9f3aaf
JB		 7255
7256 if (intel_crtc->plane)
7257 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7258 else
7259 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7260 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7261 intel_ring_emit(ring, MI_NOOP);
7262 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7263 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7264 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7265 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7266 intel_ring_emit(ring, MI_NOOP);
7267
e7d841ca 7268 intel_mark_page_flip_active(intel_crtc);
6d90c952 7269 intel_ring_advance(ring);
83d4092b
CW		 7270 return 0;
7271
7272err_unpin:
7273 intel_unpin_fb_obj(obj);
7274err:
8c9f3aaf
JB		 7275 return ret;
7276}
7277
7278static int intel_gen4_queue_flip(struct drm_device *dev,
7279 struct drm_crtc *crtc,
7280 struct drm_framebuffer *fb,
7281 struct drm_i915_gem_object *obj)
7282{
7283 struct drm_i915_private *dev_priv = dev->dev_private;
7284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7285 uint32_t pf, pipesrc;
6d90c952 7286 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7287 int ret;
7288
6d90c952 7289 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7290 if (ret)
83d4092b 7291 goto err;
8c9f3aaf 7292
6d90c952 7293 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7294 if (ret)
83d4092b 7295 goto err_unpin;
8c9f3aaf
JB		 7296
7297 /* i965+ uses the linear or tiled offsets from the
7298 * Display Registers (which do not change across a page-flip)
7299 * so we need only reprogram the base address.
7300 */
6d90c952
DV		 7301 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7302 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7303 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7304 intel_ring_emit(ring,
7305 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7306 obj->tiling_mode);
8c9f3aaf
JB		 7307
7308 /* XXX Enabling the panel-fitter across page-flip is so far
7309 * untested on non-native modes, so ignore it for now.
7310 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7311 */
7312 pf = 0;
7313 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7314 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7315
7316 intel_mark_page_flip_active(intel_crtc);
6d90c952 7317 intel_ring_advance(ring);
83d4092b
CW		 7318 return 0;
7319
7320err_unpin:
7321 intel_unpin_fb_obj(obj);
7322err:
8c9f3aaf
JB		 7323 return ret;
7324}
7325
7326static int intel_gen6_queue_flip(struct drm_device *dev,
7327 struct drm_crtc *crtc,
7328 struct drm_framebuffer *fb,
7329 struct drm_i915_gem_object *obj)
7330{
7331 struct drm_i915_private *dev_priv = dev->dev_private;
7332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7333 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7334 uint32_t pf, pipesrc;
7335 int ret;
7336
6d90c952 7337 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7338 if (ret)
83d4092b 7339 goto err;
8c9f3aaf 7340
6d90c952 7341 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7342 if (ret)
83d4092b 7343 goto err_unpin;
8c9f3aaf 7344
6d90c952
DV		 7345 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7346 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7347 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7348 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7349
dc257cf1
DV		 7350 /* Contrary to the suggestions in the documentation,
7351 * "Enable Panel Fitter" does not seem to be required when page
7352 * flipping with a non-native mode, and worse causes a normal
7353 * modeset to fail.
7354 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7355 */
7356 pf = 0;
8c9f3aaf 7357 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7358 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7359
7360 intel_mark_page_flip_active(intel_crtc);
6d90c952 7361 intel_ring_advance(ring);
83d4092b
CW		 7362 return 0;
7363
7364err_unpin:
7365 intel_unpin_fb_obj(obj);
7366err:
8c9f3aaf
JB		 7367 return ret;
7368}
7369
7c9017e5
JB		 7370/*
7371 * On gen7 we currently use the blit ring because (in early silicon at least)
7372 * the render ring doesn't give us interrpts for page flip completion, which
7373 * means clients will hang after the first flip is queued. Fortunately the
7374 * blit ring generates interrupts properly, so use it instead.
7375 */
7376static int intel_gen7_queue_flip(struct drm_device *dev,
7377 struct drm_crtc *crtc,
7378 struct drm_framebuffer *fb,
7379 struct drm_i915_gem_object *obj)
7380{
7381 struct drm_i915_private *dev_priv = dev->dev_private;
7382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7383 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7384 uint32_t plane_bit = 0;
7c9017e5
JB		 7385 int ret;
7386
7387 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7388 if (ret)
83d4092b 7389 goto err;
7c9017e5 7390
cb05d8de
DV		 7391 switch(intel_crtc->plane) {
7392 case PLANE_A:
7393 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7394 break;
7395 case PLANE_B:
7396 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7397 break;
7398 case PLANE_C:
7399 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7400 break;
7401 default:
7402 WARN_ONCE(1, "unknown plane in flip command\n");
7403 ret = -ENODEV;
ab3951eb 7404 goto err_unpin;
cb05d8de
DV		 7405 }
7406
7c9017e5
JB		 7407 ret = intel_ring_begin(ring, 4);
7408 if (ret)
83d4092b 7409 goto err_unpin;
7c9017e5 7410
cb05d8de 7411 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7412 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7413 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7414 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7415
7416 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7417 intel_ring_advance(ring);
83d4092b
CW		 7418 return 0;
7419
7420err_unpin:
7421 intel_unpin_fb_obj(obj);
7422err:
7c9017e5
JB		 7423 return ret;
7424}
7425
8c9f3aaf
JB		 7426static int intel_default_queue_flip(struct drm_device *dev,
7427 struct drm_crtc *crtc,
7428 struct drm_framebuffer *fb,
7429 struct drm_i915_gem_object *obj)
7430{
7431 return -ENODEV;
7432}
7433
6b95a207
KH		 7434static int intel_crtc_page_flip(struct drm_crtc *crtc,
7435 struct drm_framebuffer *fb,
7436 struct drm_pending_vblank_event *event)
7437{
7438 struct drm_device *dev = crtc->dev;
7439 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7440 struct drm_framebuffer *old_fb = crtc->fb;
7441 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7443 struct intel_unpin_work *work;
8c9f3aaf 7444 unsigned long flags;
52e68630 7445 int ret;
6b95a207 7446
e6a595d2
VS		 7447 /* Can't change pixel format via MI display flips. */
7448 if (fb->pixel_format != crtc->fb->pixel_format)
7449 return -EINVAL;
7450
7451 /*
7452 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7453 * Note that pitch changes could also affect these register.
7454 */
7455 if (INTEL_INFO(dev)->gen > 3 &&
7456 (fb->offsets[0] != crtc->fb->offsets[0] ||
7457 fb->pitches[0] != crtc->fb->pitches[0]))
7458 return -EINVAL;
7459
6b95a207
KH		 7460 work = kzalloc(sizeof *work, GFP_KERNEL);
7461 if (work == NULL)
7462 return -ENOMEM;
7463
6b95a207 7464 work->event = event;
b4a98e57 7465 work->crtc = crtc;
4a35f83b 7466 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7467 INIT_WORK(&work->work, intel_unpin_work_fn);
7468
7317c75e
JB		 7469 ret = drm_vblank_get(dev, intel_crtc->pipe);
7470 if (ret)
7471 goto free_work;
7472
6b95a207
KH		 7473 /* We borrow the event spin lock for protecting unpin_work */
7474 spin_lock_irqsave(&dev->event_lock, flags);
7475 if (intel_crtc->unpin_work) {
7476 spin_unlock_irqrestore(&dev->event_lock, flags);
7477 kfree(work);
7317c75e 7478 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7479
7480 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7481 return -EBUSY;
7482 }
7483 intel_crtc->unpin_work = work;
7484 spin_unlock_irqrestore(&dev->event_lock, flags);
7485
b4a98e57
CW		 7486 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7487 flush_workqueue(dev_priv->wq);
7488
79158103
CW		 7489 ret = i915_mutex_lock_interruptible(dev);
7490 if (ret)
7491 goto cleanup;
6b95a207 7492
75dfca80 7493 /* Reference the objects for the scheduled work. */
05394f39
CW		 7494 drm_gem_object_reference(&work->old_fb_obj->base);
7495 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7496
7497 crtc->fb = fb;
96b099fd 7498
e1f99ce6 7499 work->pending_flip_obj = obj;
e1f99ce6 7500
4e5359cd
SF		 7501 work->enable_stall_check = true;
7502
b4a98e57 7503 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7504 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7505
8c9f3aaf
JB		 7506 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7507 if (ret)
7508 goto cleanup_pending;
6b95a207 7509
7782de3b 7510 intel_disable_fbc(dev);
f047e395 7511 intel_mark_fb_busy(obj);
6b95a207
KH		 7512 mutex_unlock(&dev->struct_mutex);
7513
e5510fac
JB		 7514 trace_i915_flip_request(intel_crtc->plane, obj);
7515
6b95a207 7516 return 0;
96b099fd 7517
8c9f3aaf 7518cleanup_pending:
b4a98e57 7519 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7520 crtc->fb = old_fb;
05394f39
CW		 7521 drm_gem_object_unreference(&work->old_fb_obj->base);
7522 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7523 mutex_unlock(&dev->struct_mutex);
7524
79158103 7525cleanup:
96b099fd
CW		 7526 spin_lock_irqsave(&dev->event_lock, flags);
7527 intel_crtc->unpin_work = NULL;
7528 spin_unlock_irqrestore(&dev->event_lock, flags);
7529
7317c75e
JB		 7530 drm_vblank_put(dev, intel_crtc->pipe);
7531free_work:
96b099fd
CW		 7532 kfree(work);
7533
7534 return ret;
6b95a207
KH		 7535}
7536
f6e5b160 7537static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7538 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7539 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7540};
7541
6ed0f796 7542bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7543{
6ed0f796
DV		 7544 struct intel_encoder *other_encoder;
7545 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7546
6ed0f796
DV		 7547 if (WARN_ON(!crtc))
7548 return false;
7549
7550 list_for_each_entry(other_encoder,
7551 &crtc->dev->mode_config.encoder_list,
7552 base.head) {
7553
7554 if (&other_encoder->new_crtc->base != crtc ||
7555 encoder == other_encoder)
7556 continue;
7557 else
7558 return true;
f47166d2
CW		 7559 }
7560
6ed0f796
DV		 7561 return false;
7562}
47f1c6c9 7563
50f56119
DV		 7564static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7565 struct drm_crtc *crtc)
7566{
7567 struct drm_device *dev;
7568 struct drm_crtc *tmp;
7569 int crtc_mask = 1;
47f1c6c9 7570
50f56119 7571 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7572
50f56119 7573 dev = crtc->dev;
47f1c6c9 7574
50f56119
DV		 7575 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7576 if (tmp == crtc)
7577 break;
7578 crtc_mask <<= 1;
7579 }
47f1c6c9 7580
50f56119
DV		 7581 if (encoder->possible_crtcs & crtc_mask)
7582 return true;
7583 return false;
47f1c6c9 7584}
79e53945 7585
9a935856
DV		 7586/**
7587 * intel_modeset_update_staged_output_state
7588 *
7589 * Updates the staged output configuration state, e.g. after we've read out the
7590 * current hw state.
7591 */
7592static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7593{
9a935856
DV		 7594 struct intel_encoder *encoder;
7595 struct intel_connector *connector;
f6e5b160 7596
9a935856
DV		 7597 list_for_each_entry(connector, &dev->mode_config.connector_list,
7598 base.head) {
7599 connector->new_encoder =
7600 to_intel_encoder(connector->base.encoder);
7601 }
f6e5b160 7602
9a935856
DV		 7603 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7604 base.head) {
7605 encoder->new_crtc =
7606 to_intel_crtc(encoder->base.crtc);
7607 }
f6e5b160
CW		 7608}
7609
9a935856
DV		 7610/**
7611 * intel_modeset_commit_output_state
7612 *
7613 * This function copies the stage display pipe configuration to the real one.
7614 */
7615static void intel_modeset_commit_output_state(struct drm_device *dev)
7616{
7617 struct intel_encoder *encoder;
7618 struct intel_connector *connector;
f6e5b160 7619
9a935856
DV		 7620 list_for_each_entry(connector, &dev->mode_config.connector_list,
7621 base.head) {
7622 connector->base.encoder = &connector->new_encoder->base;
7623 }
f6e5b160 7624
9a935856
DV		 7625 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7626 base.head) {
7627 encoder->base.crtc = &encoder->new_crtc->base;
7628 }
7629}
7630
4e53c2e0
DV		 7631static int
7632pipe_config_set_bpp(struct drm_crtc *crtc,
7633 struct drm_framebuffer *fb,
7634 struct intel_crtc_config *pipe_config)
7635{
7636 struct drm_device *dev = crtc->dev;
7637 struct drm_connector *connector;
7638 int bpp;
7639
d42264b1
DV		 7640 switch (fb->pixel_format) {
7641 case DRM_FORMAT_C8:
4e53c2e0
DV		 7642 bpp = 8*3; /* since we go through a colormap */
7643 break;
d42264b1
DV		 7644 case DRM_FORMAT_XRGB1555:
7645 case DRM_FORMAT_ARGB1555:
7646 /* checked in intel_framebuffer_init already */
7647 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7648 return -EINVAL;
7649 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7650 bpp = 6*3; /* min is 18bpp */
7651 break;
d42264b1
DV		 7652 case DRM_FORMAT_XBGR8888:
7653 case DRM_FORMAT_ABGR8888:
7654 /* checked in intel_framebuffer_init already */
7655 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7656 return -EINVAL;
7657 case DRM_FORMAT_XRGB8888:
7658 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7659 bpp = 8*3;
7660 break;
d42264b1
DV		 7661 case DRM_FORMAT_XRGB2101010:
7662 case DRM_FORMAT_ARGB2101010:
7663 case DRM_FORMAT_XBGR2101010:
7664 case DRM_FORMAT_ABGR2101010:
7665 /* checked in intel_framebuffer_init already */
7666 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7667 return -EINVAL;
4e53c2e0
DV		 7668 bpp = 10*3;
7669 break;
baba133a 7670 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7671 default:
7672 DRM_DEBUG_KMS("unsupported depth\n");
7673 return -EINVAL;
7674 }
7675
4e53c2e0
DV		 7676 pipe_config->pipe_bpp = bpp;
7677
7678 /* Clamp display bpp to EDID value */
7679 list_for_each_entry(connector, &dev->mode_config.connector_list,
7680 head) {
7681 if (connector->encoder && connector->encoder->crtc != crtc)
7682 continue;
7683
7684 /* Don't use an invalid EDID bpc value */
7685 if (connector->display_info.bpc &&
7686 connector->display_info.bpc * 3 < bpp) {
7687 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7688 bpp, connector->display_info.bpc*3);
7689 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7690 }
7691 }
7692
7693 return bpp;
7694}
7695
b8cecdf5
DV		 7696static struct intel_crtc_config *
7697intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7698 struct drm_framebuffer *fb,
b8cecdf5 7699 struct drm_display_mode *mode)
ee7b9f93 7700{
7758a113 7701 struct drm_device *dev = crtc->dev;
7758a113
DV		 7702 struct drm_encoder_helper_funcs *encoder_funcs;
7703 struct intel_encoder *encoder;
b8cecdf5 7704 struct intel_crtc_config *pipe_config;
4e53c2e0 7705 int plane_bpp;
ee7b9f93 7706
b8cecdf5
DV		 7707 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7708 if (!pipe_config)
7758a113
DV		 7709 return ERR_PTR(-ENOMEM);
7710
b8cecdf5
DV		 7711 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7712 drm_mode_copy(&pipe_config->requested_mode, mode);
7713
4e53c2e0
DV		 7714 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7715 if (plane_bpp < 0)
7716 goto fail;
7717
7758a113
DV		 7718 /* Pass our mode to the connectors and the CRTC to give them a chance to
7719 * adjust it according to limitations or connector properties, and also
7720 * a chance to reject the mode entirely.
47f1c6c9 7721 */
7758a113
DV		 7722 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7723 base.head) {
47f1c6c9 7724
7758a113
DV		 7725 if (&encoder->new_crtc->base != crtc)
7726 continue;
7ae89233
DV		 7727
7728 if (encoder->compute_config) {
7729 if (!(encoder->compute_config(encoder, pipe_config))) {
7730 DRM_DEBUG_KMS("Encoder config failure\n");
7731 goto fail;
7732 }
7733
7734 continue;
7735 }
7736
7758a113 7737 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7738 if (!(encoder_funcs->mode_fixup(&encoder->base,
7739 &pipe_config->requested_mode,
7740 &pipe_config->adjusted_mode))) {
7758a113
DV		 7741 DRM_DEBUG_KMS("Encoder fixup failed\n");
7742 goto fail;
7743 }
ee7b9f93 7744 }
47f1c6c9 7745
b8cecdf5 7746 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7747 DRM_DEBUG_KMS("CRTC fixup failed\n");
7748 goto fail;
ee7b9f93 7749 }
7758a113 7750 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7751
4e53c2e0
DV		 7752 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7753 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7754 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7755
b8cecdf5 7756 return pipe_config;
7758a113 7757fail:
b8cecdf5 7758 kfree(pipe_config);
7758a113 7759 return ERR_PTR(-EINVAL);
ee7b9f93 7760}
47f1c6c9 7761
e2e1ed41
DV		 7762/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7763 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7764static void
7765intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7766 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7767{
7768 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7769 struct drm_device *dev = crtc->dev;
7770 struct intel_encoder *encoder;
7771 struct intel_connector *connector;
7772 struct drm_crtc *tmp_crtc;
79e53945 7773
e2e1ed41 7774 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7775
e2e1ed41
DV		 7776 /* Check which crtcs have changed outputs connected to them, these need
7777 * to be part of the prepare_pipes mask. We don't (yet) support global
7778 * modeset across multiple crtcs, so modeset_pipes will only have one
7779 * bit set at most. */
7780 list_for_each_entry(connector, &dev->mode_config.connector_list,
7781 base.head) {
7782 if (connector->base.encoder == &connector->new_encoder->base)
7783 continue;
79e53945 7784
e2e1ed41
DV		 7785 if (connector->base.encoder) {
7786 tmp_crtc = connector->base.encoder->crtc;
7787
7788 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7789 }
7790
7791 if (connector->new_encoder)
7792 *prepare_pipes |=
7793 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7794 }
7795
e2e1ed41
DV		 7796 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7797 base.head) {
7798 if (encoder->base.crtc == &encoder->new_crtc->base)
7799 continue;
7800
7801 if (encoder->base.crtc) {
7802 tmp_crtc = encoder->base.crtc;
7803
7804 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7805 }
7806
7807 if (encoder->new_crtc)
7808 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7809 }
7810
e2e1ed41
DV		 7811 /* Check for any pipes that will be fully disabled ... */
7812 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7813 base.head) {
7814 bool used = false;
22fd0fab 7815
e2e1ed41
DV		 7816 /* Don't try to disable disabled crtcs. */
7817 if (!intel_crtc->base.enabled)
7818 continue;
7e7d76c3 7819
e2e1ed41
DV		 7820 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7821 base.head) {
7822 if (encoder->new_crtc == intel_crtc)
7823 used = true;
7824 }
7825
7826 if (!used)
7827 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7828 }
7829
e2e1ed41
DV		 7830
7831 /* set_mode is also used to update properties on life display pipes. */
7832 intel_crtc = to_intel_crtc(crtc);
7833 if (crtc->enabled)
7834 *prepare_pipes |= 1 << intel_crtc->pipe;
7835
b6c5164d
DV		 7836 /*
7837 * For simplicity do a full modeset on any pipe where the output routing
7838 * changed. We could be more clever, but that would require us to be
7839 * more careful with calling the relevant encoder->mode_set functions.
7840 */
e2e1ed41
DV		 7841 if (*prepare_pipes)
7842 *modeset_pipes = *prepare_pipes;
7843
7844 /* ... and mask these out. */
7845 *modeset_pipes &= ~(*disable_pipes);
7846 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7847
7848 /*
7849 * HACK: We don't (yet) fully support global modesets. intel_set_config
7850 * obies this rule, but the modeset restore mode of
7851 * intel_modeset_setup_hw_state does not.
7852 */
7853 *modeset_pipes &= 1 << intel_crtc->pipe;
7854 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7855
7856 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7857 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7858}
79e53945 7859
ea9d758d 7860static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7861{
ea9d758d 7862 struct drm_encoder *encoder;
f6e5b160 7863 struct drm_device *dev = crtc->dev;
f6e5b160 7864
ea9d758d
DV		 7865 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7866 if (encoder->crtc == crtc)
7867 return true;
7868
7869 return false;
7870}
7871
7872static void
7873intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7874{
7875 struct intel_encoder *intel_encoder;
7876 struct intel_crtc *intel_crtc;
7877 struct drm_connector *connector;
7878
7879 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7880 base.head) {
7881 if (!intel_encoder->base.crtc)
7882 continue;
7883
7884 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7885
7886 if (prepare_pipes & (1 << intel_crtc->pipe))
7887 intel_encoder->connectors_active = false;
7888 }
7889
7890 intel_modeset_commit_output_state(dev);
7891
7892 /* Update computed state. */
7893 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7894 base.head) {
7895 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7896 }
7897
7898 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7899 if (!connector->encoder || !connector->encoder->crtc)
7900 continue;
7901
7902 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7903
7904 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7905 struct drm_property *dpms_property =
7906 dev->mode_config.dpms_property;
7907
ea9d758d 7908 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7909 drm_object_property_set_value(&connector->base,
68d34720
DV		 7910 dpms_property,
7911 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7912
7913 intel_encoder = to_intel_encoder(connector->encoder);
7914 intel_encoder->connectors_active = true;
7915 }
7916 }
7917
7918}
7919
25c5b266
DV		 7920#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7921 list_for_each_entry((intel_crtc), \
7922 &(dev)->mode_config.crtc_list, \
7923 base.head) \
7924 if (mask & (1 <<(intel_crtc)->pipe)) \
7925
0e8ffe1b
DV		 7926static bool
7927intel_pipe_config_compare(struct intel_crtc_config *current_config,
7928 struct intel_crtc_config *pipe_config)
7929{
88adfff1
DV		 7930 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7931 DRM_ERROR("mismatch in has_pch_encoder "
7932 "(expected %i, found %i)\n",
7933 current_config->has_pch_encoder,
7934 pipe_config->has_pch_encoder);
7935 return false;
7936 }
7937
0e8ffe1b
DV		 7938 return true;
7939}
7940
b980514c 7941void
8af6cf88
DV		 7942intel_modeset_check_state(struct drm_device *dev)
7943{
0e8ffe1b 7944 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7945 struct intel_crtc *crtc;
7946 struct intel_encoder *encoder;
7947 struct intel_connector *connector;
0e8ffe1b 7948 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7949
7950 list_for_each_entry(connector, &dev->mode_config.connector_list,
7951 base.head) {
7952 /* This also checks the encoder/connector hw state with the
7953 * ->get_hw_state callbacks. */
7954 intel_connector_check_state(connector);
7955
7956 WARN(&connector->new_encoder->base != connector->base.encoder,
7957 "connector's staged encoder doesn't match current encoder\n");
7958 }
7959
7960 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7961 base.head) {
7962 bool enabled = false;
7963 bool active = false;
7964 enum pipe pipe, tracked_pipe;
7965
7966 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7967 encoder->base.base.id,
7968 drm_get_encoder_name(&encoder->base));
7969
7970 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7971 "encoder's stage crtc doesn't match current crtc\n");
7972 WARN(encoder->connectors_active && !encoder->base.crtc,
7973 "encoder's active_connectors set, but no crtc\n");
7974
7975 list_for_each_entry(connector, &dev->mode_config.connector_list,
7976 base.head) {
7977 if (connector->base.encoder != &encoder->base)
7978 continue;
7979 enabled = true;
7980 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7981 active = true;
7982 }
7983 WARN(!!encoder->base.crtc != enabled,
7984 "encoder's enabled state mismatch "
7985 "(expected %i, found %i)\n",
7986 !!encoder->base.crtc, enabled);
7987 WARN(active && !encoder->base.crtc,
7988 "active encoder with no crtc\n");
7989
7990 WARN(encoder->connectors_active != active,
7991 "encoder's computed active state doesn't match tracked active state "
7992 "(expected %i, found %i)\n", active, encoder->connectors_active);
7993
7994 active = encoder->get_hw_state(encoder, &pipe);
7995 WARN(active != encoder->connectors_active,
7996 "encoder's hw state doesn't match sw tracking "
7997 "(expected %i, found %i)\n",
7998 encoder->connectors_active, active);
7999
8000 if (!encoder->base.crtc)
8001 continue;
8002
8003 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8004 WARN(active && pipe != tracked_pipe,
8005 "active encoder's pipe doesn't match"
8006 "(expected %i, found %i)\n",
8007 tracked_pipe, pipe);
8008
8009 }
8010
8011 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8012 base.head) {
8013 bool enabled = false;
8014 bool active = false;
8015
8016 DRM_DEBUG_KMS("[CRTC:%d]\n",
8017 crtc->base.base.id);
8018
8019 WARN(crtc->active && !crtc->base.enabled,
8020 "active crtc, but not enabled in sw tracking\n");
8021
8022 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8023 base.head) {
8024 if (encoder->base.crtc != &crtc->base)
8025 continue;
8026 enabled = true;
8027 if (encoder->connectors_active)
8028 active = true;
8029 }
8030 WARN(active != crtc->active,
8031 "crtc's computed active state doesn't match tracked active state "
8032 "(expected %i, found %i)\n", active, crtc->active);
8033 WARN(enabled != crtc->base.enabled,
8034 "crtc's computed enabled state doesn't match tracked enabled state "
8035 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8036
88adfff1 8037 memset(&pipe_config, 0, sizeof(pipe_config));
0e8ffe1b
DV		 8038 active = dev_priv->display.get_pipe_config(crtc,
8039 &pipe_config);
8040 WARN(crtc->active != active,
8041 "crtc active state doesn't match with hw state "
8042 "(expected %i, found %i)\n", crtc->active, active);
8043
8044 WARN(active &&
8045 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8046 "pipe state doesn't match!\n");
8af6cf88
DV		 8047 }
8048}
8049
f30da187
DV		 8050static int __intel_set_mode(struct drm_crtc *crtc,
8051 struct drm_display_mode *mode,
8052 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8053{
8054 struct drm_device *dev = crtc->dev;
dbf2b54e 8055 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8056 struct drm_display_mode *saved_mode, *saved_hwmode;
8057 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8058 struct intel_crtc *intel_crtc;
8059 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8060 int ret = 0;
a6778b3c 8061
3ac18232 8062 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8063 if (!saved_mode)
8064 return -ENOMEM;
3ac18232 8065 saved_hwmode = saved_mode + 1;
a6778b3c 8066
e2e1ed41 8067 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8068 &prepare_pipes, &disable_pipes);
8069
3ac18232
TG		 8070 *saved_hwmode = crtc->hwmode;
8071 *saved_mode = crtc->mode;
a6778b3c 8072
25c5b266
DV		 8073 /* Hack: Because we don't (yet) support global modeset on multiple
8074 * crtcs, we don't keep track of the new mode for more than one crtc.
8075 * Hence simply check whether any bit is set in modeset_pipes in all the
8076 * pieces of code that are not yet converted to deal with mutliple crtcs
8077 * changing their mode at the same time. */
25c5b266 8078 if (modeset_pipes) {
4e53c2e0 8079 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8080 if (IS_ERR(pipe_config)) {
8081 ret = PTR_ERR(pipe_config);
8082 pipe_config = NULL;
8083
3ac18232 8084 goto out;
25c5b266 8085 }
25c5b266 8086 }
a6778b3c 8087
460da916
DV		 8088 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8089 intel_crtc_disable(&intel_crtc->base);
8090
ea9d758d
DV		 8091 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8092 if (intel_crtc->base.enabled)
8093 dev_priv->display.crtc_disable(&intel_crtc->base);
8094 }
a6778b3c 8095
6c4c86f5
DV		 8096 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8097 * to set it here already despite that we pass it down the callchain.
f6e5b160 8098 */
b8cecdf5 8099 if (modeset_pipes) {
3b117c8f 8100 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8101 crtc->mode = *mode;
b8cecdf5
DV		 8102 /* mode_set/enable/disable functions rely on a correct pipe
8103 * config. */
8104 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8105 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8106 }
7758a113 8107
ea9d758d
DV		 8108 /* Only after disabling all output pipelines that will be changed can we
8109 * update the the output configuration. */
8110 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8111
47fab737
DV		 8112 if (dev_priv->display.modeset_global_resources)
8113 dev_priv->display.modeset_global_resources(dev);
8114
a6778b3c
DV		 8115 /* Set up the DPLL and any encoders state that needs to adjust or depend
8116 * on the DPLL.
f6e5b160 8117 */
25c5b266 8118 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8119 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8120 x, y, fb);
8121 if (ret)
8122 goto done;
a6778b3c
DV		 8123 }
8124
8125 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8126 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8127 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8128
25c5b266
DV		 8129 if (modeset_pipes) {
8130 /* Store real post-adjustment hardware mode. */
b8cecdf5 8131 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8132
25c5b266
DV		 8133 /* Calculate and store various constants which
8134 * are later needed by vblank and swap-completion
8135 * timestamping. They are derived from true hwmode.
8136 */
8137 drm_calc_timestamping_constants(crtc);
8138 }
a6778b3c
DV		 8139
8140 /* FIXME: add subpixel order */
8141done:
c0c36b94 8142 if (ret && crtc->enabled) {
3ac18232
TG		 8143 crtc->hwmode = *saved_hwmode;
8144 crtc->mode = *saved_mode;
a6778b3c
DV		 8145 }
8146
3ac18232 8147out:
b8cecdf5 8148 kfree(pipe_config);
3ac18232 8149 kfree(saved_mode);
a6778b3c 8150 return ret;
f6e5b160
CW		 8151}
8152
f30da187
DV		 8153int intel_set_mode(struct drm_crtc *crtc,
8154 struct drm_display_mode *mode,
8155 int x, int y, struct drm_framebuffer *fb)
8156{
8157 int ret;
8158
8159 ret = __intel_set_mode(crtc, mode, x, y, fb);
8160
8161 if (ret == 0)
8162 intel_modeset_check_state(crtc->dev);
8163
8164 return ret;
8165}
8166
c0c36b94
CW		 8167void intel_crtc_restore_mode(struct drm_crtc *crtc)
8168{
8169 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8170}
8171
25c5b266
DV		 8172#undef for_each_intel_crtc_masked
8173
d9e55608
DV		 8174static void intel_set_config_free(struct intel_set_config *config)
8175{
8176 if (!config)
8177 return;
8178
1aa4b628
DV		 8179 kfree(config->save_connector_encoders);
8180 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8181 kfree(config);
8182}
8183
85f9eb71
DV		 8184static int intel_set_config_save_state(struct drm_device *dev,
8185 struct intel_set_config *config)
8186{
85f9eb71
DV		 8187 struct drm_encoder *encoder;
8188 struct drm_connector *connector;
8189 int count;
8190
1aa4b628
DV		 8191 config->save_encoder_crtcs =
8192 kcalloc(dev->mode_config.num_encoder,
8193 sizeof(struct drm_crtc *), GFP_KERNEL);
8194 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8195 return -ENOMEM;
8196
1aa4b628
DV		 8197 config->save_connector_encoders =
8198 kcalloc(dev->mode_config.num_connector,
8199 sizeof(struct drm_encoder *), GFP_KERNEL);
8200 if (!config->save_connector_encoders)
85f9eb71
DV		 8201 return -ENOMEM;
8202
8203 /* Copy data. Note that driver private data is not affected.
8204 * Should anything bad happen only the expected state is
8205 * restored, not the drivers personal bookkeeping.
8206 */
85f9eb71
DV		 8207 count = 0;
8208 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8209 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8210 }
8211
8212 count = 0;
8213 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8214 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8215 }
8216
8217 return 0;
8218}
8219
8220static void intel_set_config_restore_state(struct drm_device *dev,
8221 struct intel_set_config *config)
8222{
9a935856
DV		 8223 struct intel_encoder *encoder;
8224 struct intel_connector *connector;
85f9eb71
DV		 8225 int count;
8226
85f9eb71 8227 count = 0;
9a935856
DV		 8228 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8229 encoder->new_crtc =
8230 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8231 }
8232
8233 count = 0;
9a935856
DV		 8234 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8235 connector->new_encoder =
8236 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8237 }
8238}
8239
5e2b584e
DV		 8240static void
8241intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8242 struct intel_set_config *config)
8243{
8244
8245 /* We should be able to check here if the fb has the same properties
8246 * and then just flip_or_move it */
8247 if (set->crtc->fb != set->fb) {
8248 /* If we have no fb then treat it as a full mode set */
8249 if (set->crtc->fb == NULL) {
8250 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8251 config->mode_changed = true;
8252 } else if (set->fb == NULL) {
8253 config->mode_changed = true;
72f4901e
DV		 8254 } else if (set->fb->pixel_format !=
8255 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8256 config->mode_changed = true;
8257 } else
8258 config->fb_changed = true;
8259 }
8260
835c5873 8261 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8262 config->fb_changed = true;
8263
8264 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8265 DRM_DEBUG_KMS("modes are different, full mode set\n");
8266 drm_mode_debug_printmodeline(&set->crtc->mode);
8267 drm_mode_debug_printmodeline(set->mode);
8268 config->mode_changed = true;
8269 }
8270}
8271
2e431051 8272static int
9a935856
DV		 8273intel_modeset_stage_output_state(struct drm_device *dev,
8274 struct drm_mode_set *set,
8275 struct intel_set_config *config)
50f56119 8276{
85f9eb71 8277 struct drm_crtc *new_crtc;
9a935856
DV		 8278 struct intel_connector *connector;
8279 struct intel_encoder *encoder;
2e431051 8280 int count, ro;
50f56119 8281
9abdda74 8282 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8283 * of connectors. For paranoia, double-check this. */
8284 WARN_ON(!set->fb && (set->num_connectors != 0));
8285 WARN_ON(set->fb && (set->num_connectors == 0));
8286
50f56119 8287 count = 0;
9a935856
DV		 8288 list_for_each_entry(connector, &dev->mode_config.connector_list,
8289 base.head) {
8290 /* Otherwise traverse passed in connector list and get encoders
8291 * for them. */
50f56119 8292 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8293 if (set->connectors[ro] == &connector->base) {
8294 connector->new_encoder = connector->encoder;
50f56119
DV		 8295 break;
8296 }
8297 }
8298
9a935856
DV		 8299 /* If we disable the crtc, disable all its connectors. Also, if
8300 * the connector is on the changing crtc but not on the new
8301 * connector list, disable it. */
8302 if ((!set->fb || ro == set->num_connectors) &&
8303 connector->base.encoder &&
8304 connector->base.encoder->crtc == set->crtc) {
8305 connector->new_encoder = NULL;
8306
8307 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8308 connector->base.base.id,
8309 drm_get_connector_name(&connector->base));
8310 }
8311
8312
8313 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8314 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8315 config->mode_changed = true;
50f56119
DV		 8316 }
8317 }
9a935856 8318 /* connector->new_encoder is now updated for all connectors. */
50f56119 8319
9a935856 8320 /* Update crtc of enabled connectors. */
50f56119 8321 count = 0;
9a935856
DV		 8322 list_for_each_entry(connector, &dev->mode_config.connector_list,
8323 base.head) {
8324 if (!connector->new_encoder)
50f56119
DV		 8325 continue;
8326
9a935856 8327 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8328
8329 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8330 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8331 new_crtc = set->crtc;
8332 }
8333
8334 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8335 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8336 new_crtc)) {
5e2b584e 8337 return -EINVAL;
50f56119 8338 }
9a935856
DV		 8339 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8340
8341 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8342 connector->base.base.id,
8343 drm_get_connector_name(&connector->base),
8344 new_crtc->base.id);
8345 }
8346
8347 /* Check for any encoders that needs to be disabled. */
8348 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8349 base.head) {
8350 list_for_each_entry(connector,
8351 &dev->mode_config.connector_list,
8352 base.head) {
8353 if (connector->new_encoder == encoder) {
8354 WARN_ON(!connector->new_encoder->new_crtc);
8355
8356 goto next_encoder;
8357 }
8358 }
8359 encoder->new_crtc = NULL;
8360next_encoder:
8361 /* Only now check for crtc changes so we don't miss encoders
8362 * that will be disabled. */
8363 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8364 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8365 config->mode_changed = true;
50f56119
DV		 8366 }
8367 }
9a935856 8368 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8369
2e431051
DV		 8370 return 0;
8371}
8372
8373static int intel_crtc_set_config(struct drm_mode_set *set)
8374{
8375 struct drm_device *dev;
2e431051
DV		 8376 struct drm_mode_set save_set;
8377 struct intel_set_config *config;
8378 int ret;
2e431051 8379
8d3e375e
DV		 8380 BUG_ON(!set);
8381 BUG_ON(!set->crtc);
8382 BUG_ON(!set->crtc->helper_private);
2e431051 8383
7e53f3a4
DV		 8384 /* Enforce sane interface api - has been abused by the fb helper. */
8385 BUG_ON(!set->mode && set->fb);
8386 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8387
2e431051
DV		 8388 if (set->fb) {
8389 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8390 set->crtc->base.id, set->fb->base.id,
8391 (int)set->num_connectors, set->x, set->y);
8392 } else {
8393 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8394 }
8395
8396 dev = set->crtc->dev;
8397
8398 ret = -ENOMEM;
8399 config = kzalloc(sizeof(*config), GFP_KERNEL);
8400 if (!config)
8401 goto out_config;
8402
8403 ret = intel_set_config_save_state(dev, config);
8404 if (ret)
8405 goto out_config;
8406
8407 save_set.crtc = set->crtc;
8408 save_set.mode = &set->crtc->mode;
8409 save_set.x = set->crtc->x;
8410 save_set.y = set->crtc->y;
8411 save_set.fb = set->crtc->fb;
8412
8413 /* Compute whether we need a full modeset, only an fb base update or no
8414 * change at all. In the future we might also check whether only the
8415 * mode changed, e.g. for LVDS where we only change the panel fitter in
8416 * such cases. */
8417 intel_set_config_compute_mode_changes(set, config);
8418
9a935856 8419 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8420 if (ret)
8421 goto fail;
8422
5e2b584e 8423 if (config->mode_changed) {
87f1faa6 8424 if (set->mode) {
50f56119
DV		 8425 DRM_DEBUG_KMS("attempting to set mode from"
8426 " userspace\n");
8427 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8428 }
8429
c0c36b94
CW		 8430 ret = intel_set_mode(set->crtc, set->mode,
8431 set->x, set->y, set->fb);
8432 if (ret) {
8433 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8434 set->crtc->base.id, ret);
87f1faa6
DV		 8435 goto fail;
8436 }
5e2b584e 8437 } else if (config->fb_changed) {
4878cae2
VS		 8438 intel_crtc_wait_for_pending_flips(set->crtc);
8439
4f660f49 8440 ret = intel_pipe_set_base(set->crtc,
94352cf9 8441 set->x, set->y, set->fb);
50f56119
DV		 8442 }
8443
d9e55608
DV		 8444 intel_set_config_free(config);
8445
50f56119
DV		 8446 return 0;
8447
8448fail:
85f9eb71 8449 intel_set_config_restore_state(dev, config);
50f56119
DV		 8450
8451 /* Try to restore the config */
5e2b584e 8452 if (config->mode_changed &&
c0c36b94
CW		 8453 intel_set_mode(save_set.crtc, save_set.mode,
8454 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8455 DRM_ERROR("failed to restore config after modeset failure\n");
8456
d9e55608
DV		 8457out_config:
8458 intel_set_config_free(config);
50f56119
DV		 8459 return ret;
8460}
f6e5b160
CW		 8461
8462static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8463 .cursor_set = intel_crtc_cursor_set,
8464 .cursor_move = intel_crtc_cursor_move,
8465 .gamma_set = intel_crtc_gamma_set,
50f56119 8466 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8467 .destroy = intel_crtc_destroy,
8468 .page_flip = intel_crtc_page_flip,
8469};
8470
79f689aa
PZ		 8471static void intel_cpu_pll_init(struct drm_device *dev)
8472{
affa9354 8473 if (HAS_DDI(dev))
79f689aa
PZ		 8474 intel_ddi_pll_init(dev);
8475}
8476
ee7b9f93
JB		 8477static void intel_pch_pll_init(struct drm_device *dev)
8478{
8479 drm_i915_private_t *dev_priv = dev->dev_private;
8480 int i;
8481
8482 if (dev_priv->num_pch_pll == 0) {
8483 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8484 return;
8485 }
8486
8487 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8488 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8489 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8490 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8491 }
8492}
8493
b358d0a6 8494static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8495{
22fd0fab 8496 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8497 struct intel_crtc *intel_crtc;
8498 int i;
8499
8500 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8501 if (intel_crtc == NULL)
8502 return;
8503
8504 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8505
8506 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8507 for (i = 0; i < 256; i++) {
8508 intel_crtc->lut_r[i] = i;
8509 intel_crtc->lut_g[i] = i;
8510 intel_crtc->lut_b[i] = i;
8511 }
8512
80824003
JB		 8513 /* Swap pipes & planes for FBC on pre-965 */
8514 intel_crtc->pipe = pipe;
8515 intel_crtc->plane = pipe;
3b117c8f 8516 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8517 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8518 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8519 intel_crtc->plane = !pipe;
80824003
JB		 8520 }
8521
22fd0fab
JB		 8522 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8523 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8524 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8525 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8526
79e53945 8527 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8528}
8529
08d7b3d1 8530int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8531 struct drm_file *file)
08d7b3d1 8532{
08d7b3d1 8533 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8534 struct drm_mode_object *drmmode_obj;
8535 struct intel_crtc *crtc;
08d7b3d1 8536
1cff8f6b
DV		 8537 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8538 return -ENODEV;
08d7b3d1 8539
c05422d5
DV		 8540 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8541 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8542
c05422d5 8543 if (!drmmode_obj) {
08d7b3d1
CW		 8544 DRM_ERROR("no such CRTC id\n");
8545 return -EINVAL;
8546 }
8547
c05422d5
DV		 8548 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8549 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8550
c05422d5 8551 return 0;
08d7b3d1
CW		 8552}
8553
66a9278e 8554static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8555{
66a9278e
DV		 8556 struct drm_device *dev = encoder->base.dev;
8557 struct intel_encoder *source_encoder;
79e53945 8558 int index_mask = 0;
79e53945
JB		 8559 int entry = 0;
8560
66a9278e
DV		 8561 list_for_each_entry(source_encoder,
8562 &dev->mode_config.encoder_list, base.head) {
8563
8564 if (encoder == source_encoder)
79e53945 8565 index_mask |= (1 << entry);
66a9278e
DV		 8566
8567 /* Intel hw has only one MUX where enocoders could be cloned. */
8568 if (encoder->cloneable && source_encoder->cloneable)
8569 index_mask |= (1 << entry);
8570
79e53945
JB		 8571 entry++;
8572 }
4ef69c7a 8573
79e53945
JB		 8574 return index_mask;
8575}
8576
4d302442
CW		 8577static bool has_edp_a(struct drm_device *dev)
8578{
8579 struct drm_i915_private *dev_priv = dev->dev_private;
8580
8581 if (!IS_MOBILE(dev))
8582 return false;
8583
8584 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8585 return false;
8586
8587 if (IS_GEN5(dev) &&
8588 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8589 return false;
8590
8591 return true;
8592}
8593
79e53945
JB		 8594static void intel_setup_outputs(struct drm_device *dev)
8595{
725e30ad 8596 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8597 struct intel_encoder *encoder;
cb0953d7 8598 bool dpd_is_edp = false;
f3cfcba6 8599 bool has_lvds;
79e53945 8600
f3cfcba6 8601 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8602 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8603 /* disable the panel fitter on everything but LVDS */
8604 I915_WRITE(PFIT_CONTROL, 0);
8605 }
79e53945 8606
c40c0f5b 8607 if (!IS_ULT(dev))
79935fca 8608 intel_crt_init(dev);
cb0953d7 8609
affa9354 8610 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8611 int found;
8612
8613 /* Haswell uses DDI functions to detect digital outputs */
8614 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8615 /* DDI A only supports eDP */
8616 if (found)
8617 intel_ddi_init(dev, PORT_A);
8618
8619 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8620 * register */
8621 found = I915_READ(SFUSE_STRAP);
8622
8623 if (found & SFUSE_STRAP_DDIB_DETECTED)
8624 intel_ddi_init(dev, PORT_B);
8625 if (found & SFUSE_STRAP_DDIC_DETECTED)
8626 intel_ddi_init(dev, PORT_C);
8627 if (found & SFUSE_STRAP_DDID_DETECTED)
8628 intel_ddi_init(dev, PORT_D);
8629 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8630 int found;
270b3042
DV		 8631 dpd_is_edp = intel_dpd_is_edp(dev);
8632
8633 if (has_edp_a(dev))
8634 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8635
dc0fa718 8636 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8637 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8638 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8639 if (!found)
e2debe91 8640 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8641 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8642 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8643 }
8644
dc0fa718 8645 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8646 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8647
dc0fa718 8648 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8649 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8650
5eb08b69 8651 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8652 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8653
270b3042 8654 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8655 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8656 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8657 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8658 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8659 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8660
dc0fa718 8661 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8662 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8663 PORT_B);
67cfc203
VS		 8664 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8665 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8666 }
103a196f 8667 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8668 bool found = false;
7d57382e 8669
e2debe91 8670 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8671 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8672 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8673 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8674 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8675 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8676 }
27185ae1 8677
b01f2c3a
JB		 8678 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8679 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8680 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8681 }
725e30ad 8682 }
13520b05
KH		 8683
8684 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8685
e2debe91 8686 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8687 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8688 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8689 }
27185ae1 8690
e2debe91 8691 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8692
b01f2c3a
JB		 8693 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8694 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8695 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8696 }
8697 if (SUPPORTS_INTEGRATED_DP(dev)) {
8698 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8699 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8700 }
725e30ad 8701 }
27185ae1 8702
b01f2c3a
JB		 8703 if (SUPPORTS_INTEGRATED_DP(dev) &&
8704 (I915_READ(DP_D) & DP_DETECTED)) {
8705 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8706 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8707 }
bad720ff 8708 } else if (IS_GEN2(dev))
79e53945
JB		 8709 intel_dvo_init(dev);
8710
103a196f 8711 if (SUPPORTS_TV(dev))
79e53945
JB		 8712 intel_tv_init(dev);
8713
4ef69c7a
CW		 8714 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8715 encoder->base.possible_crtcs = encoder->crtc_mask;
8716 encoder->base.possible_clones =
66a9278e 8717 intel_encoder_clones(encoder);
79e53945 8718 }
47356eb6 8719
dde86e2d 8720 intel_init_pch_refclk(dev);
270b3042
DV		 8721
8722 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8723}
8724
8725static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8726{
8727 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8728
8729 drm_framebuffer_cleanup(fb);
05394f39 8730 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8731
8732 kfree(intel_fb);
8733}
8734
8735static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8736 struct drm_file *file,
79e53945
JB		 8737 unsigned int *handle)
8738{
8739 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8740 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8741
05394f39 8742 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8743}
8744
8745static const struct drm_framebuffer_funcs intel_fb_funcs = {
8746 .destroy = intel_user_framebuffer_destroy,
8747 .create_handle = intel_user_framebuffer_create_handle,
8748};
8749
38651674
DA		 8750int intel_framebuffer_init(struct drm_device *dev,
8751 struct intel_framebuffer *intel_fb,
308e5bcb 8752 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8753 struct drm_i915_gem_object *obj)
79e53945 8754{
79e53945
JB		 8755 int ret;
8756
c16ed4be
CW		 8757 if (obj->tiling_mode == I915_TILING_Y) {
8758 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8759 return -EINVAL;
c16ed4be 8760 }
57cd6508 8761
c16ed4be
CW		 8762 if (mode_cmd->pitches[0] & 63) {
8763 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8764 mode_cmd->pitches[0]);
57cd6508 8765 return -EINVAL;
c16ed4be 8766 }
57cd6508 8767
5d7bd705 8768 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8769 if (mode_cmd->pitches[0] > 32768) {
8770 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8771 mode_cmd->pitches[0]);
5d7bd705 8772 return -EINVAL;
c16ed4be 8773 }
5d7bd705
VS		 8774
8775 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8776 mode_cmd->pitches[0] != obj->stride) {
8777 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8778 mode_cmd->pitches[0], obj->stride);
5d7bd705 8779 return -EINVAL;
c16ed4be 8780 }
5d7bd705 8781
57779d06 8782 /* Reject formats not supported by any plane early. */
308e5bcb 8783 switch (mode_cmd->pixel_format) {
57779d06 8784 case DRM_FORMAT_C8:
04b3924d
VS		 8785 case DRM_FORMAT_RGB565:
8786 case DRM_FORMAT_XRGB8888:
8787 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8788 break;
8789 case DRM_FORMAT_XRGB1555:
8790 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8791 if (INTEL_INFO(dev)->gen > 3) {
8792 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8793 return -EINVAL;
c16ed4be 8794 }
57779d06
VS		 8795 break;
8796 case DRM_FORMAT_XBGR8888:
8797 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8798 case DRM_FORMAT_XRGB2101010:
8799 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8800 case DRM_FORMAT_XBGR2101010:
8801 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8802 if (INTEL_INFO(dev)->gen < 4) {
8803 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8804 return -EINVAL;
c16ed4be 8805 }
b5626747 8806 break;
04b3924d
VS		 8807 case DRM_FORMAT_YUYV:
8808 case DRM_FORMAT_UYVY:
8809 case DRM_FORMAT_YVYU:
8810 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8811 if (INTEL_INFO(dev)->gen < 5) {
8812 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8813 return -EINVAL;
c16ed4be 8814 }
57cd6508
CW		 8815 break;
8816 default:
c16ed4be 8817 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8818 return -EINVAL;
8819 }
8820
90f9a336
VS		 8821 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8822 if (mode_cmd->offsets[0] != 0)
8823 return -EINVAL;
8824
c7d73f6a
DV		 8825 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8826 intel_fb->obj = obj;
8827
79e53945
JB		 8828 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8829 if (ret) {
8830 DRM_ERROR("framebuffer init failed %d\n", ret);
8831 return ret;
8832 }
8833
79e53945
JB		 8834 return 0;
8835}
8836
79e53945
JB		 8837static struct drm_framebuffer *
8838intel_user_framebuffer_create(struct drm_device *dev,
8839 struct drm_file *filp,
308e5bcb 8840 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8841{
05394f39 8842 struct drm_i915_gem_object *obj;
79e53945 8843
308e5bcb
JB		 8844 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8845 mode_cmd->handles[0]));
c8725226 8846 if (&obj->base == NULL)
cce13ff7 8847 return ERR_PTR(-ENOENT);
79e53945 8848
d2dff872 8849 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8850}
8851
79e53945 8852static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8853 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8854 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8855};
8856
e70236a8
JB		 8857/* Set up chip specific display functions */
8858static void intel_init_display(struct drm_device *dev)
8859{
8860 struct drm_i915_private *dev_priv = dev->dev_private;
8861
affa9354 8862 if (HAS_DDI(dev)) {
0e8ffe1b 8863 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8864 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8865 dev_priv->display.crtc_enable = haswell_crtc_enable;
8866 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8867 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8868 dev_priv->display.update_plane = ironlake_update_plane;
8869 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8870 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8871 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8872 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8873 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8874 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8875 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 8876 } else if (IS_VALLEYVIEW(dev)) {
8877 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8878 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8879 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8880 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8881 dev_priv->display.off = i9xx_crtc_off;
8882 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8883 } else {
0e8ffe1b 8884 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8885 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8886 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8887 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8888 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8889 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8890 }
e70236a8 8891
e70236a8 8892 /* Returns the core display clock speed */
25eb05fc
JB		 8893 if (IS_VALLEYVIEW(dev))
8894 dev_priv->display.get_display_clock_speed =
8895 valleyview_get_display_clock_speed;
8896 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8897 dev_priv->display.get_display_clock_speed =
8898 i945_get_display_clock_speed;
8899 else if (IS_I915G(dev))
8900 dev_priv->display.get_display_clock_speed =
8901 i915_get_display_clock_speed;
f2b115e6 8902 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8903 dev_priv->display.get_display_clock_speed =
8904 i9xx_misc_get_display_clock_speed;
8905 else if (IS_I915GM(dev))
8906 dev_priv->display.get_display_clock_speed =
8907 i915gm_get_display_clock_speed;
8908 else if (IS_I865G(dev))
8909 dev_priv->display.get_display_clock_speed =
8910 i865_get_display_clock_speed;
f0f8a9ce 8911 else if (IS_I85X(dev))
e70236a8
JB		 8912 dev_priv->display.get_display_clock_speed =
8913 i855_get_display_clock_speed;
8914 else /* 852, 830 */
8915 dev_priv->display.get_display_clock_speed =
8916 i830_get_display_clock_speed;
8917
7f8a8569 8918 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8919 if (IS_GEN5(dev)) {
674cf967 8920 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8921 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8922 } else if (IS_GEN6(dev)) {
674cf967 8923 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8924 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8925 } else if (IS_IVYBRIDGE(dev)) {
8926 /* FIXME: detect B0+ stepping and use auto training */
8927 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8928 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8929 dev_priv->display.modeset_global_resources =
8930 ivb_modeset_global_resources;
c82e4d26
ED		 8931 } else if (IS_HASWELL(dev)) {
8932 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8933 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8934 dev_priv->display.modeset_global_resources =
8935 haswell_modeset_global_resources;
a0e63c22 8936 }
6067aaea 8937 } else if (IS_G4X(dev)) {
e0dac65e 8938 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8939 }
8c9f3aaf
JB		 8940
8941 /* Default just returns -ENODEV to indicate unsupported */
8942 dev_priv->display.queue_flip = intel_default_queue_flip;
8943
8944 switch (INTEL_INFO(dev)->gen) {
8945 case 2:
8946 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8947 break;
8948
8949 case 3:
8950 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8951 break;
8952
8953 case 4:
8954 case 5:
8955 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8956 break;
8957
8958 case 6:
8959 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8960 break;
7c9017e5
JB		 8961 case 7:
8962 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8963 break;
8c9f3aaf 8964 }
e70236a8
JB		 8965}
8966
b690e96c
JB		 8967/*
8968 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8969 * resume, or other times. This quirk makes sure that's the case for
8970 * affected systems.
8971 */
0206e353 8972static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8973{
8974 struct drm_i915_private *dev_priv = dev->dev_private;
8975
8976 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8977 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8978}
8979
435793df
KP		 8980/*
8981 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8982 */
8983static void quirk_ssc_force_disable(struct drm_device *dev)
8984{
8985 struct drm_i915_private *dev_priv = dev->dev_private;
8986 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8987 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8988}
8989
4dca20ef 8990/*
5a15ab5b
CE		 8991 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8992 * brightness value
4dca20ef
CE		 8993 */
8994static void quirk_invert_brightness(struct drm_device *dev)
8995{
8996 struct drm_i915_private *dev_priv = dev->dev_private;
8997 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8998 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8999}
9000
b690e96c
JB		 9001struct intel_quirk {
9002 int device;
9003 int subsystem_vendor;
9004 int subsystem_device;
9005 void (*hook)(struct drm_device *dev);
9006};
9007
5f85f176
EE		 9008/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9009struct intel_dmi_quirk {
9010 void (*hook)(struct drm_device *dev);
9011 const struct dmi_system_id (*dmi_id_list)[];
9012};
9013
9014static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9015{
9016 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9017 return 1;
9018}
9019
9020static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9021 {
9022 .dmi_id_list = &(const struct dmi_system_id[]) {
9023 {
9024 .callback = intel_dmi_reverse_brightness,
9025 .ident = "NCR Corporation",
9026 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9027 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9028 },
9029 },
9030 { } /* terminating entry */
9031 },
9032 .hook = quirk_invert_brightness,
9033 },
9034};
9035
c43b5634 9036static struct intel_quirk intel_quirks[] = {
b690e96c 9037 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9038 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9039
b690e96c
JB		 9040 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9041 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9042
b690e96c
JB		 9043 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9044 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9045
ccd0d36e 9046 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9047 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9048 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9049
9050 /* Lenovo U160 cannot use SSC on LVDS */
9051 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9052
9053 /* Sony Vaio Y cannot use SSC on LVDS */
9054 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9055
9056 /* Acer Aspire 5734Z must invert backlight brightness */
9057 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9058
9059 /* Acer/eMachines G725 */
9060 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9061
9062 /* Acer/eMachines e725 */
9063 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9064
9065 /* Acer/Packard Bell NCL20 */
9066 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9067
9068 /* Acer Aspire 4736Z */
9069 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9070};
9071
9072static void intel_init_quirks(struct drm_device *dev)
9073{
9074 struct pci_dev *d = dev->pdev;
9075 int i;
9076
9077 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9078 struct intel_quirk *q = &intel_quirks[i];
9079
9080 if (d->device == q->device &&
9081 (d->subsystem_vendor == q->subsystem_vendor ||
9082 q->subsystem_vendor == PCI_ANY_ID) &&
9083 (d->subsystem_device == q->subsystem_device ||
9084 q->subsystem_device == PCI_ANY_ID))
9085 q->hook(dev);
9086 }
5f85f176
EE		 9087 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9088 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9089 intel_dmi_quirks[i].hook(dev);
9090 }
b690e96c
JB		 9091}
9092
9cce37f4
JB		 9093/* Disable the VGA plane that we never use */
9094static void i915_disable_vga(struct drm_device *dev)
9095{
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097 u8 sr1;
766aa1c4 9098 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9099
9100 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9101 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9102 sr1 = inb(VGA_SR_DATA);
9103 outb(sr1 | 1<<5, VGA_SR_DATA);
9104 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9105 udelay(300);
9106
9107 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9108 POSTING_READ(vga_reg);
9109}
9110
f817586c
DV		 9111void intel_modeset_init_hw(struct drm_device *dev)
9112{
fa42e23c 9113 intel_init_power_well(dev);
0232e927 9114
a8f78b58
ED		 9115 intel_prepare_ddi(dev);
9116
f817586c
DV		 9117 intel_init_clock_gating(dev);
9118
79f5b2c7 9119 mutex_lock(&dev->struct_mutex);
8090c6b9 9120 intel_enable_gt_powersave(dev);
79f5b2c7 9121 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9122}
9123
79e53945
JB		 9124void intel_modeset_init(struct drm_device *dev)
9125{
652c393a 9126 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9127 int i, j, ret;
79e53945
JB		 9128
9129 drm_mode_config_init(dev);
9130
9131 dev->mode_config.min_width = 0;
9132 dev->mode_config.min_height = 0;
9133
019d96cb
DA		 9134 dev->mode_config.preferred_depth = 24;
9135 dev->mode_config.prefer_shadow = 1;
9136
e6ecefaa 9137 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9138
b690e96c
JB		 9139 intel_init_quirks(dev);
9140
1fa61106
ED		 9141 intel_init_pm(dev);
9142
e3c74757
BW		 9143 if (INTEL_INFO(dev)->num_pipes == 0)
9144 return;
9145
e70236a8
JB		 9146 intel_init_display(dev);
9147
a6c45cf0
CW		 9148 if (IS_GEN2(dev)) {
9149 dev->mode_config.max_width = 2048;
9150 dev->mode_config.max_height = 2048;
9151 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9152 dev->mode_config.max_width = 4096;
9153 dev->mode_config.max_height = 4096;
79e53945 9154 } else {
a6c45cf0
CW		 9155 dev->mode_config.max_width = 8192;
9156 dev->mode_config.max_height = 8192;
79e53945 9157 }
5d4545ae 9158 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9159
28c97730 9160 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9161 INTEL_INFO(dev)->num_pipes,
9162 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9163
7eb552ae 9164 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9165 intel_crtc_init(dev, i);
7f1f3851
JB		 9166 for (j = 0; j < dev_priv->num_plane; j++) {
9167 ret = intel_plane_init(dev, i, j);
9168 if (ret)
06da8da2
VS		 9169 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9170 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9171 }
79e53945
JB		 9172 }
9173
79f689aa 9174 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9175 intel_pch_pll_init(dev);
9176
9cce37f4
JB		 9177 /* Just disable it once at startup */
9178 i915_disable_vga(dev);
79e53945 9179 intel_setup_outputs(dev);
11be49eb
CW		 9180
9181 /* Just in case the BIOS is doing something questionable. */
9182 intel_disable_fbc(dev);
2c7111db
CW		 9183}
9184
24929352
DV		 9185static void
9186intel_connector_break_all_links(struct intel_connector *connector)
9187{
9188 connector->base.dpms = DRM_MODE_DPMS_OFF;
9189 connector->base.encoder = NULL;
9190 connector->encoder->connectors_active = false;
9191 connector->encoder->base.crtc = NULL;
9192}
9193
7fad798e
DV		 9194static void intel_enable_pipe_a(struct drm_device *dev)
9195{
9196 struct intel_connector *connector;
9197 struct drm_connector *crt = NULL;
9198 struct intel_load_detect_pipe load_detect_temp;
9199
9200 /* We can't just switch on the pipe A, we need to set things up with a
9201 * proper mode and output configuration. As a gross hack, enable pipe A
9202 * by enabling the load detect pipe once. */
9203 list_for_each_entry(connector,
9204 &dev->mode_config.connector_list,
9205 base.head) {
9206 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9207 crt = &connector->base;
9208 break;
9209 }
9210 }
9211
9212 if (!crt)
9213 return;
9214
9215 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9216 intel_release_load_detect_pipe(crt, &load_detect_temp);
9217
652c393a 9218
7fad798e
DV		 9219}
9220
fa555837
DV		 9221static bool
9222intel_check_plane_mapping(struct intel_crtc *crtc)
9223{
7eb552ae
BW		 9224 struct drm_device *dev = crtc->base.dev;
9225 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9226 u32 reg, val;
9227
7eb552ae 9228 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9229 return true;
9230
9231 reg = DSPCNTR(!crtc->plane);
9232 val = I915_READ(reg);
9233
9234 if ((val & DISPLAY_PLANE_ENABLE) &&
9235 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9236 return false;
9237
9238 return true;
9239}
9240
24929352
DV		 9241static void intel_sanitize_crtc(struct intel_crtc *crtc)
9242{
9243 struct drm_device *dev = crtc->base.dev;
9244 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9245 u32 reg;
24929352 9246
24929352 9247 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9248 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9249 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9250
9251 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9252 * disable the crtc (and hence change the state) if it is wrong. Note
9253 * that gen4+ has a fixed plane -> pipe mapping. */
9254 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9255 struct intel_connector *connector;
9256 bool plane;
9257
24929352
DV		 9258 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9259 crtc->base.base.id);
9260
9261 /* Pipe has the wrong plane attached and the plane is active.
9262 * Temporarily change the plane mapping and disable everything
9263 * ... */
9264 plane = crtc->plane;
9265 crtc->plane = !plane;
9266 dev_priv->display.crtc_disable(&crtc->base);
9267 crtc->plane = plane;
9268
9269 /* ... and break all links. */
9270 list_for_each_entry(connector, &dev->mode_config.connector_list,
9271 base.head) {
9272 if (connector->encoder->base.crtc != &crtc->base)
9273 continue;
9274
9275 intel_connector_break_all_links(connector);
9276 }
9277
9278 WARN_ON(crtc->active);
9279 crtc->base.enabled = false;
9280 }
24929352 9281
7fad798e
DV		 9282 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9283 crtc->pipe == PIPE_A && !crtc->active) {
9284 /* BIOS forgot to enable pipe A, this mostly happens after
9285 * resume. Force-enable the pipe to fix this, the update_dpms
9286 * call below we restore the pipe to the right state, but leave
9287 * the required bits on. */
9288 intel_enable_pipe_a(dev);
9289 }
9290
24929352
DV		 9291 /* Adjust the state of the output pipe according to whether we
9292 * have active connectors/encoders. */
9293 intel_crtc_update_dpms(&crtc->base);
9294
9295 if (crtc->active != crtc->base.enabled) {
9296 struct intel_encoder *encoder;
9297
9298 /* This can happen either due to bugs in the get_hw_state
9299 * functions or because the pipe is force-enabled due to the
9300 * pipe A quirk. */
9301 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9302 crtc->base.base.id,
9303 crtc->base.enabled ? "enabled" : "disabled",
9304 crtc->active ? "enabled" : "disabled");
9305
9306 crtc->base.enabled = crtc->active;
9307
9308 /* Because we only establish the connector -> encoder ->
9309 * crtc links if something is active, this means the
9310 * crtc is now deactivated. Break the links. connector
9311 * -> encoder links are only establish when things are
9312 * actually up, hence no need to break them. */
9313 WARN_ON(crtc->active);
9314
9315 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9316 WARN_ON(encoder->connectors_active);
9317 encoder->base.crtc = NULL;
9318 }
9319 }
9320}
9321
9322static void intel_sanitize_encoder(struct intel_encoder *encoder)
9323{
9324 struct intel_connector *connector;
9325 struct drm_device *dev = encoder->base.dev;
9326
9327 /* We need to check both for a crtc link (meaning that the
9328 * encoder is active and trying to read from a pipe) and the
9329 * pipe itself being active. */
9330 bool has_active_crtc = encoder->base.crtc &&
9331 to_intel_crtc(encoder->base.crtc)->active;
9332
9333 if (encoder->connectors_active && !has_active_crtc) {
9334 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9335 encoder->base.base.id,
9336 drm_get_encoder_name(&encoder->base));
9337
9338 /* Connector is active, but has no active pipe. This is
9339 * fallout from our resume register restoring. Disable
9340 * the encoder manually again. */
9341 if (encoder->base.crtc) {
9342 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9343 encoder->base.base.id,
9344 drm_get_encoder_name(&encoder->base));
9345 encoder->disable(encoder);
9346 }
9347
9348 /* Inconsistent output/port/pipe state happens presumably due to
9349 * a bug in one of the get_hw_state functions. Or someplace else
9350 * in our code, like the register restore mess on resume. Clamp
9351 * things to off as a safer default. */
9352 list_for_each_entry(connector,
9353 &dev->mode_config.connector_list,
9354 base.head) {
9355 if (connector->encoder != encoder)
9356 continue;
9357
9358 intel_connector_break_all_links(connector);
9359 }
9360 }
9361 /* Enabled encoders without active connectors will be fixed in
9362 * the crtc fixup. */
9363}
9364
44cec740 9365void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9366{
9367 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9368 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9369
9370 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9371 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9372 i915_disable_vga(dev);
0fde901f
KM		 9373 }
9374}
9375
24929352
DV		 9376/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9377 * and i915 state tracking structures. */
45e2b5f6
DV		 9378void intel_modeset_setup_hw_state(struct drm_device *dev,
9379 bool force_restore)
24929352
DV		 9380{
9381 struct drm_i915_private *dev_priv = dev->dev_private;
9382 enum pipe pipe;
9383 u32 tmp;
b5644d05 9384 struct drm_plane *plane;
24929352
DV		 9385 struct intel_crtc *crtc;
9386 struct intel_encoder *encoder;
9387 struct intel_connector *connector;
9388
affa9354 9389 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9390 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9391
9392 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9393 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9394 case TRANS_DDI_EDP_INPUT_A_ON:
9395 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9396 pipe = PIPE_A;
9397 break;
9398 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9399 pipe = PIPE_B;
9400 break;
9401 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9402 pipe = PIPE_C;
9403 break;
aaa148ec
DL		 9404 default:
9405 /* A bogus value has been programmed, disable
9406 * the transcoder */
9407 WARN(1, "Bogus eDP source %08x\n", tmp);
9408 intel_ddi_disable_transcoder_func(dev_priv,
9409 TRANSCODER_EDP);
9410 goto setup_pipes;
e28d54cb
PZ		 9411 }
9412
9413 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9414 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9415
9416 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9417 pipe_name(pipe));
9418 }
9419 }
9420
aaa148ec 9421setup_pipes:
0e8ffe1b
DV		 9422 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9423 base.head) {
3b117c8f 9424 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9425 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9426 crtc->config.cpu_transcoder = tmp;
9427
0e8ffe1b
DV		 9428 crtc->active = dev_priv->display.get_pipe_config(crtc,
9429 &crtc->config);
24929352
DV		 9430
9431 crtc->base.enabled = crtc->active;
9432
9433 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9434 crtc->base.base.id,
9435 crtc->active ? "enabled" : "disabled");
9436 }
9437
affa9354 9438 if (HAS_DDI(dev))
6441ab5f
PZ		 9439 intel_ddi_setup_hw_pll_state(dev);
9440
24929352
DV		 9441 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9442 base.head) {
9443 pipe = 0;
9444
9445 if (encoder->get_hw_state(encoder, &pipe)) {
9446 encoder->base.crtc =
9447 dev_priv->pipe_to_crtc_mapping[pipe];
9448 } else {
9449 encoder->base.crtc = NULL;
9450 }
9451
9452 encoder->connectors_active = false;
9453 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9454 encoder->base.base.id,
9455 drm_get_encoder_name(&encoder->base),
9456 encoder->base.crtc ? "enabled" : "disabled",
9457 pipe);
9458 }
9459
9460 list_for_each_entry(connector, &dev->mode_config.connector_list,
9461 base.head) {
9462 if (connector->get_hw_state(connector)) {
9463 connector->base.dpms = DRM_MODE_DPMS_ON;
9464 connector->encoder->connectors_active = true;
9465 connector->base.encoder = &connector->encoder->base;
9466 } else {
9467 connector->base.dpms = DRM_MODE_DPMS_OFF;
9468 connector->base.encoder = NULL;
9469 }
9470 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9471 connector->base.base.id,
9472 drm_get_connector_name(&connector->base),
9473 connector->base.encoder ? "enabled" : "disabled");
9474 }
9475
9476 /* HW state is read out, now we need to sanitize this mess. */
9477 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9478 base.head) {
9479 intel_sanitize_encoder(encoder);
9480 }
9481
9482 for_each_pipe(pipe) {
9483 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9484 intel_sanitize_crtc(crtc);
9485 }
9a935856 9486
45e2b5f6 9487 if (force_restore) {
f30da187
DV		 9488 /*
9489 * We need to use raw interfaces for restoring state to avoid
9490 * checking (bogus) intermediate states.
9491 */
45e2b5f6 9492 for_each_pipe(pipe) {
b5644d05
JB		 9493 struct drm_crtc *crtc =
9494 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9495
9496 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9497 crtc->fb);
45e2b5f6 9498 }
b5644d05
JB		 9499 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9500 intel_plane_restore(plane);
0fde901f
KM		 9501
9502 i915_redisable_vga(dev);
45e2b5f6
DV		 9503 } else {
9504 intel_modeset_update_staged_output_state(dev);
9505 }
8af6cf88
DV		 9506
9507 intel_modeset_check_state(dev);
2e938892
DV		 9508
9509 drm_mode_config_reset(dev);
2c7111db
CW		 9510}
9511
9512void intel_modeset_gem_init(struct drm_device *dev)
9513{
1833b134 9514 intel_modeset_init_hw(dev);
02e792fb
DV		 9515
9516 intel_setup_overlay(dev);
24929352 9517
45e2b5f6 9518 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9519}
9520
9521void intel_modeset_cleanup(struct drm_device *dev)
9522{
652c393a
JB		 9523 struct drm_i915_private *dev_priv = dev->dev_private;
9524 struct drm_crtc *crtc;
9525 struct intel_crtc *intel_crtc;
9526
f87ea761 9527 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9528 mutex_lock(&dev->struct_mutex);
9529
723bfd70
JB		 9530 intel_unregister_dsm_handler();
9531
9532
652c393a
JB		 9533 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9534 /* Skip inactive CRTCs */
9535 if (!crtc->fb)
9536 continue;
9537
9538 intel_crtc = to_intel_crtc(crtc);
3dec0095 9539 intel_increase_pllclock(crtc);
652c393a
JB		 9540 }
9541
973d04f9 9542 intel_disable_fbc(dev);
e70236a8 9543
8090c6b9 9544 intel_disable_gt_powersave(dev);
0cdab21f 9545
930ebb46
DV		 9546 ironlake_teardown_rc6(dev);
9547
69341a5e
KH		 9548 mutex_unlock(&dev->struct_mutex);
9549
6c0d9350
DV		 9550 /* Disable the irq before mode object teardown, for the irq might
9551 * enqueue unpin/hotplug work. */
9552 drm_irq_uninstall(dev);
9553 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9554 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9555
1630fe75
CW		 9556 /* flush any delayed tasks or pending work */
9557 flush_scheduled_work();
9558
dc652f90
JN		 9559 /* destroy backlight, if any, before the connectors */
9560 intel_panel_destroy_backlight(dev);
9561
79e53945 9562 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9563
9564 intel_cleanup_overlay(dev);
79e53945
JB		 9565}
9566
f1c79df3
ZW		 9567/*
9568 * Return which encoder is currently attached for connector.
9569 */
df0e9248 9570struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9571{
df0e9248
CW		 9572 return &intel_attached_encoder(connector)->base;
9573}
f1c79df3 9574
df0e9248
CW		 9575void intel_connector_attach_encoder(struct intel_connector *connector,
9576 struct intel_encoder *encoder)
9577{
9578 connector->encoder = encoder;
9579 drm_mode_connector_attach_encoder(&connector->base,
9580 &encoder->base);
79e53945 9581}
28d52043
DA		 9582
9583/*
9584 * set vga decode state - true == enable VGA decode
9585 */
9586int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9587{
9588 struct drm_i915_private *dev_priv = dev->dev_private;
9589 u16 gmch_ctrl;
9590
9591 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9592 if (state)
9593 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9594 else
9595 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9596 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9597 return 0;
9598}
c4a1d9e4
CW		 9599
9600#ifdef CONFIG_DEBUG_FS
9601#include <linux/seq_file.h>
9602
9603struct intel_display_error_state {
9604 struct intel_cursor_error_state {
9605 u32 control;
9606 u32 position;
9607 u32 base;
9608 u32 size;
52331309 9609 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9610
9611 struct intel_pipe_error_state {
9612 u32 conf;
9613 u32 source;
9614
9615 u32 htotal;
9616 u32 hblank;
9617 u32 hsync;
9618 u32 vtotal;
9619 u32 vblank;
9620 u32 vsync;
52331309 9621 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9622
9623 struct intel_plane_error_state {
9624 u32 control;
9625 u32 stride;
9626 u32 size;
9627 u32 pos;
9628 u32 addr;
9629 u32 surface;
9630 u32 tile_offset;
52331309 9631 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9632};
9633
9634struct intel_display_error_state *
9635intel_display_capture_error_state(struct drm_device *dev)
9636{
0206e353 9637 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9638 struct intel_display_error_state *error;
702e7a56 9639 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9640 int i;
9641
9642 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9643 if (error == NULL)
9644 return NULL;
9645
52331309 9646 for_each_pipe(i) {
702e7a56
PZ		 9647 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9648
a18c4c3d
PZ		 9649 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9650 error->cursor[i].control = I915_READ(CURCNTR(i));
9651 error->cursor[i].position = I915_READ(CURPOS(i));
9652 error->cursor[i].base = I915_READ(CURBASE(i));
9653 } else {
9654 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9655 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9656 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9657 }
c4a1d9e4
CW		 9658
9659 error->plane[i].control = I915_READ(DSPCNTR(i));
9660 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9661 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9662 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9663 error->plane[i].pos = I915_READ(DSPPOS(i));
9664 }
ca291363
PZ		 9665 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9666 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9667 if (INTEL_INFO(dev)->gen >= 4) {
9668 error->plane[i].surface = I915_READ(DSPSURF(i));
9669 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9670 }
9671
702e7a56 9672 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9673 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9674 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9675 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9676 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9677 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9678 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9679 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9680 }
9681
9682 return error;
9683}
9684
9685void
9686intel_display_print_error_state(struct seq_file *m,
9687 struct drm_device *dev,
9688 struct intel_display_error_state *error)
9689{
9690 int i;
9691
7eb552ae 9692 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9693 for_each_pipe(i) {
c4a1d9e4
CW		 9694 seq_printf(m, "Pipe [%d]:\n", i);
9695 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9696 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9697 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9698 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9699 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9700 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9701 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9702 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9703
9704 seq_printf(m, "Plane [%d]:\n", i);
9705 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9706 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9707 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9708 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9709 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9710 }
4b71a570 9711 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9712 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9713 if (INTEL_INFO(dev)->gen >= 4) {
9714 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9715 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9716 }
9717
9718 seq_printf(m, "Cursor [%d]:\n", i);
9719 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9720 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9721 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9722 }
9723}
9724#endif
Linux kernel - Deliverables
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