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drm/i915: forcewake debugfs fix
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
c1c7af60
JB		 27#include <linux/module.h>
28#include <linux/input.h>
79e53945 29#include <linux/i2c.h>
7662c8bd 30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
9cce37f4 32#include <linux/vgaarb.h>
79e53945
JB		 33#include "drmP.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
e5510fac 37#include "i915_trace.h"
ab2c0672 38#include "drm_dp_helper.h"
79e53945
JB		 39
40#include "drm_crtc_helper.h"
41
32f9d658
ZW		 42#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
79e53945 44bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 45static void intel_update_watermarks(struct drm_device *dev);
3dec0095 46static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 47static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 48
49typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59} intel_clock_t;
60
61typedef struct {
62 int min, max;
63} intel_range_t;
64
65typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68} intel_p2_t;
69
70#define INTEL_P2_NUM 2
d4906093
ML		 71typedef struct intel_limit intel_limit_t;
72struct intel_limit {
79e53945
JB		 73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
d4906093
ML		 75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77};
79e53945 78
2377b741
JB		 79/* FDI */
80#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
81
d4906093
ML		 82static bool
83intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
84 int target, int refclk, intel_clock_t *best_clock);
85static bool
86intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *best_clock);
79e53945 88
a4fc5ed6
KP		 89static bool
90intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
91 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 92static bool
f2b115e6
AJ		 93intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 95
021357ac
CW		 96static inline u32 /* units of 100MHz */
97intel_fdi_link_freq(struct drm_device *dev)
98{
8b99e68c
CW		 99 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
021357ac
CW		 104}
105
e4b36699 106static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 107 .dot = { .min = 25000, .max = 350000 },
108 .vco = { .min = 930000, .max = 1400000 },
109 .n = { .min = 3, .max = 16 },
110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
d4906093 117 .find_pll = intel_find_best_PLL,
e4b36699
KP		 118};
119
120static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 930000, .max = 1400000 },
123 .n = { .min = 3, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
d4906093 131 .find_pll = intel_find_best_PLL,
e4b36699 132};
273e27ca 133
e4b36699 134static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 10, .max = 22 },
140 .m2 = { .min = 5, .max = 9 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
d4906093 145 .find_pll = intel_find_best_PLL,
e4b36699
KP		 146};
147
148static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 149 .dot = { .min = 20000, .max = 400000 },
150 .vco = { .min = 1400000, .max = 2800000 },
151 .n = { .min = 1, .max = 6 },
152 .m = { .min = 70, .max = 120 },
153 .m1 = { .min = 10, .max = 22 },
154 .m2 = { .min = 5, .max = 9 },
155 .p = { .min = 7, .max = 98 },
156 .p1 = { .min = 1, .max = 8 },
157 .p2 = { .dot_limit = 112000,
158 .p2_slow = 14, .p2_fast = 7 },
d4906093 159 .find_pll = intel_find_best_PLL,
e4b36699
KP		 160};
161
273e27ca 162
e4b36699 163static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 164 .dot = { .min = 25000, .max = 270000 },
165 .vco = { .min = 1750000, .max = 3500000},
166 .n = { .min = 1, .max = 4 },
167 .m = { .min = 104, .max = 138 },
168 .m1 = { .min = 17, .max = 23 },
169 .m2 = { .min = 5, .max = 11 },
170 .p = { .min = 10, .max = 30 },
171 .p1 = { .min = 1, .max = 3},
172 .p2 = { .dot_limit = 270000,
173 .p2_slow = 10,
174 .p2_fast = 10
044c7c41 175 },
d4906093 176 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 177};
178
179static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 180 .dot = { .min = 22000, .max = 400000 },
181 .vco = { .min = 1750000, .max = 3500000},
182 .n = { .min = 1, .max = 4 },
183 .m = { .min = 104, .max = 138 },
184 .m1 = { .min = 16, .max = 23 },
185 .m2 = { .min = 5, .max = 11 },
186 .p = { .min = 5, .max = 80 },
187 .p1 = { .min = 1, .max = 8},
188 .p2 = { .dot_limit = 165000,
189 .p2_slow = 10, .p2_fast = 5 },
d4906093 190 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 191};
192
193static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 194 .dot = { .min = 20000, .max = 115000 },
195 .vco = { .min = 1750000, .max = 3500000 },
196 .n = { .min = 1, .max = 3 },
197 .m = { .min = 104, .max = 138 },
198 .m1 = { .min = 17, .max = 23 },
199 .m2 = { .min = 5, .max = 11 },
200 .p = { .min = 28, .max = 112 },
201 .p1 = { .min = 2, .max = 8 },
202 .p2 = { .dot_limit = 0,
203 .p2_slow = 14, .p2_fast = 14
044c7c41 204 },
d4906093 205 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 209 .dot = { .min = 80000, .max = 224000 },
210 .vco = { .min = 1750000, .max = 3500000 },
211 .n = { .min = 1, .max = 3 },
212 .m = { .min = 104, .max = 138 },
213 .m1 = { .min = 17, .max = 23 },
214 .m2 = { .min = 5, .max = 11 },
215 .p = { .min = 14, .max = 42 },
216 .p1 = { .min = 2, .max = 6 },
217 .p2 = { .dot_limit = 0,
218 .p2_slow = 7, .p2_fast = 7
044c7c41 219 },
d4906093 220 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 221};
222
223static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 224 .dot = { .min = 161670, .max = 227000 },
225 .vco = { .min = 1750000, .max = 3500000},
226 .n = { .min = 1, .max = 2 },
227 .m = { .min = 97, .max = 108 },
228 .m1 = { .min = 0x10, .max = 0x12 },
229 .m2 = { .min = 0x05, .max = 0x06 },
230 .p = { .min = 10, .max = 20 },
231 .p1 = { .min = 1, .max = 2},
232 .p2 = { .dot_limit = 0,
233 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 234 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 235};
236
f2b115e6 237static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 238 .dot = { .min = 20000, .max = 400000},
239 .vco = { .min = 1700000, .max = 3500000 },
240 /* Pineview's Ncounter is a ring counter */
241 .n = { .min = 3, .max = 6 },
242 .m = { .min = 2, .max = 256 },
243 /* Pineview only has one combined m divider, which we treat as m2. */
244 .m1 = { .min = 0, .max = 0 },
245 .m2 = { .min = 0, .max = 254 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8 },
248 .p2 = { .dot_limit = 200000,
249 .p2_slow = 10, .p2_fast = 5 },
6115707b 250 .find_pll = intel_find_best_PLL,
e4b36699
KP		 251};
252
f2b115e6 253static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 400000 },
255 .vco = { .min = 1700000, .max = 3500000 },
256 .n = { .min = 3, .max = 6 },
257 .m = { .min = 2, .max = 256 },
258 .m1 = { .min = 0, .max = 0 },
259 .m2 = { .min = 0, .max = 254 },
260 .p = { .min = 7, .max = 112 },
261 .p1 = { .min = 1, .max = 8 },
262 .p2 = { .dot_limit = 112000,
263 .p2_slow = 14, .p2_fast = 14 },
6115707b 264 .find_pll = intel_find_best_PLL,
e4b36699
KP		 265};
266
273e27ca
EA		 267/* Ironlake / Sandybridge
268 *
269 * We calculate clock using (register_value + 2) for N/M1/M2, so here
270 * the range value for them is (actual_value - 2).
271 */
b91ad0ec 272static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 5 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 10, .p2_fast = 5 },
4547668a 283 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 284};
285
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 3 },
290 .m = { .min = 79, .max = 118 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297 .find_pll = intel_g4x_find_best_PLL,
298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 56 },
308 .p1 = { .min = 2, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 311 .find_pll = intel_g4x_find_best_PLL,
312};
313
273e27ca 314/* LVDS 100mhz refclk limits. */
b91ad0ec 315static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 2 },
319 .m = { .min = 79, .max = 126 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2,.max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 326 .find_pll = intel_g4x_find_best_PLL,
327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 126 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 42 },
337 .p1 = { .min = 2,.max = 6 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 340 .find_pll = intel_g4x_find_best_PLL,
341};
342
343static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000},
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 81, .max = 90 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 10, .max = 20 },
351 .p1 = { .min = 1, .max = 2},
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 10, .p2_fast = 10 },
4547668a 354 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 355};
356
1b894b59
CW		 357static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 int refclk)
2c07245f 359{
b91ad0ec
ZW		 360 struct drm_device *dev = crtc->dev;
361 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 362 const intel_limit_t *limit;
b91ad0ec
ZW		 363
364 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 365 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
366 LVDS_CLKB_POWER_UP) {
367 /* LVDS dual channel */
1b894b59 368 if (refclk == 100000)
b91ad0ec
ZW		 369 limit = &intel_limits_ironlake_dual_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_dual_lvds;
372 } else {
1b894b59 373 if (refclk == 100000)
b91ad0ec
ZW		 374 limit = &intel_limits_ironlake_single_lvds_100m;
375 else
376 limit = &intel_limits_ironlake_single_lvds;
377 }
378 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 379 HAS_eDP)
380 limit = &intel_limits_ironlake_display_port;
2c07245f 381 else
b91ad0ec 382 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 383
384 return limit;
385}
386
044c7c41
ML		 387static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
388{
389 struct drm_device *dev = crtc->dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 const intel_limit_t *limit;
392
393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
394 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
395 LVDS_CLKB_POWER_UP)
396 /* LVDS with dual channel */
e4b36699 397 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 398 else
399 /* LVDS with dual channel */
e4b36699 400 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 401 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
402 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 403 limit = &intel_limits_g4x_hdmi;
044c7c41 404 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 405 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 406 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 407 limit = &intel_limits_g4x_display_port;
044c7c41 408 } else /* The option is for other outputs */
e4b36699 409 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 410
411 return limit;
412}
413
1b894b59 414static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 415{
416 struct drm_device *dev = crtc->dev;
417 const intel_limit_t *limit;
418
bad720ff 419 if (HAS_PCH_SPLIT(dev))
1b894b59 420 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 421 else if (IS_G4X(dev)) {
044c7c41 422 limit = intel_g4x_limit(crtc);
f2b115e6 423 } else if (IS_PINEVIEW(dev)) {
2177832f 424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 425 limit = &intel_limits_pineview_lvds;
2177832f 426 else
f2b115e6 427 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 428 } else if (!IS_GEN2(dev)) {
429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
430 limit = &intel_limits_i9xx_lvds;
431 else
432 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 433 } else {
434 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 435 limit = &intel_limits_i8xx_lvds;
79e53945 436 else
e4b36699 437 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 438 }
439 return limit;
440}
441
f2b115e6
AJ		 442/* m1 is reserved as 0 in Pineview, n is a ring counter */
443static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 444{
2177832f
SL		 445 clock->m = clock->m2 + 2;
446 clock->p = clock->p1 * clock->p2;
447 clock->vco = refclk * clock->m / clock->n;
448 clock->dot = clock->vco / clock->p;
449}
450
451static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
452{
f2b115e6
AJ		 453 if (IS_PINEVIEW(dev)) {
454 pineview_clock(refclk, clock);
2177832f
SL		 455 return;
456 }
79e53945
JB		 457 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
458 clock->p = clock->p1 * clock->p2;
459 clock->vco = refclk * clock->m / (clock->n + 2);
460 clock->dot = clock->vco / clock->p;
461}
462
79e53945
JB		 463/**
464 * Returns whether any output on the specified pipe is of the specified type
465 */
4ef69c7a 466bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 467{
4ef69c7a
CW		 468 struct drm_device *dev = crtc->dev;
469 struct drm_mode_config *mode_config = &dev->mode_config;
470 struct intel_encoder *encoder;
471
472 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
473 if (encoder->base.crtc == crtc && encoder->type == type)
474 return true;
475
476 return false;
79e53945
JB		 477}
478
7c04d1d9 479#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 480/**
481 * Returns whether the given set of divisors are valid for a given refclk with
482 * the given connectors.
483 */
484
1b894b59
CW		 485static bool intel_PLL_is_valid(struct drm_device *dev,
486 const intel_limit_t *limit,
487 const intel_clock_t *clock)
79e53945 488{
79e53945
JB		 489 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
490 INTELPllInvalid ("p1 out of range\n");
491 if (clock->p < limit->p.min || limit->p.max < clock->p)
492 INTELPllInvalid ("p out of range\n");
493 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
494 INTELPllInvalid ("m2 out of range\n");
495 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
496 INTELPllInvalid ("m1 out of range\n");
f2b115e6 497 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 498 INTELPllInvalid ("m1 <= m2\n");
499 if (clock->m < limit->m.min || limit->m.max < clock->m)
500 INTELPllInvalid ("m out of range\n");
501 if (clock->n < limit->n.min || limit->n.max < clock->n)
502 INTELPllInvalid ("n out of range\n");
503 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
504 INTELPllInvalid ("vco out of range\n");
505 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
506 * connector, etc., rather than just a single range.
507 */
508 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
509 INTELPllInvalid ("dot out of range\n");
510
511 return true;
512}
513
d4906093
ML		 514static bool
515intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
516 int target, int refclk, intel_clock_t *best_clock)
517
79e53945
JB		 518{
519 struct drm_device *dev = crtc->dev;
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 intel_clock_t clock;
79e53945
JB		 522 int err = target;
523
bc5e5718 524 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 525 (I915_READ(LVDS)) != 0) {
79e53945
JB		 526 /*
527 * For LVDS, if the panel is on, just rely on its current
528 * settings for dual-channel. We haven't figured out how to
529 * reliably set up different single/dual channel state, if we
530 * even can.
531 */
532 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
533 LVDS_CLKB_POWER_UP)
534 clock.p2 = limit->p2.p2_fast;
535 else
536 clock.p2 = limit->p2.p2_slow;
537 } else {
538 if (target < limit->p2.dot_limit)
539 clock.p2 = limit->p2.p2_slow;
540 else
541 clock.p2 = limit->p2.p2_fast;
542 }
543
544 memset (best_clock, 0, sizeof (*best_clock));
545
42158660
ZY		 546 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
547 clock.m1++) {
548 for (clock.m2 = limit->m2.min;
549 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 550 /* m1 is always 0 in Pineview */
551 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 552 break;
553 for (clock.n = limit->n.min;
554 clock.n <= limit->n.max; clock.n++) {
555 for (clock.p1 = limit->p1.min;
556 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 557 int this_err;
558
2177832f 559 intel_clock(dev, refclk, &clock);
1b894b59
CW		 560 if (!intel_PLL_is_valid(dev, limit,
561 &clock))
79e53945
JB		 562 continue;
563
564 this_err = abs(clock.dot - target);
565 if (this_err < err) {
566 *best_clock = clock;
567 err = this_err;
568 }
569 }
570 }
571 }
572 }
573
574 return (err != target);
575}
576
d4906093
ML		 577static bool
578intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *best_clock)
580{
581 struct drm_device *dev = crtc->dev;
582 struct drm_i915_private *dev_priv = dev->dev_private;
583 intel_clock_t clock;
584 int max_n;
585 bool found;
6ba770dc
AJ		 586 /* approximately equals target * 0.00585 */
587 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 588 found = false;
589
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 591 int lvds_reg;
592
c619eed4 593 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 594 lvds_reg = PCH_LVDS;
595 else
596 lvds_reg = LVDS;
597 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 598 LVDS_CLKB_POWER_UP)
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610 max_n = limit->n.max;
f77f13e2 611 /* based on hardware requirement, prefer smaller n to precision */
d4906093 612 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 613 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 614 for (clock.m1 = limit->m1.max;
615 clock.m1 >= limit->m1.min; clock.m1--) {
616 for (clock.m2 = limit->m2.max;
617 clock.m2 >= limit->m2.min; clock.m2--) {
618 for (clock.p1 = limit->p1.max;
619 clock.p1 >= limit->p1.min; clock.p1--) {
620 int this_err;
621
2177832f 622 intel_clock(dev, refclk, &clock);
1b894b59
CW		 623 if (!intel_PLL_is_valid(dev, limit,
624 &clock))
d4906093 625 continue;
1b894b59
CW		 626
627 this_err = abs(clock.dot - target);
d4906093
ML		 628 if (this_err < err_most) {
629 *best_clock = clock;
630 err_most = this_err;
631 max_n = clock.n;
632 found = true;
633 }
634 }
635 }
636 }
637 }
2c07245f
ZW		 638 return found;
639}
640
5eb08b69 641static bool
f2b115e6
AJ		 642intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
643 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 644{
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
4547668a 647
5eb08b69
ZW		 648 if (target < 200000) {
649 clock.n = 1;
650 clock.p1 = 2;
651 clock.p2 = 10;
652 clock.m1 = 12;
653 clock.m2 = 9;
654 } else {
655 clock.n = 2;
656 clock.p1 = 1;
657 clock.p2 = 10;
658 clock.m1 = 14;
659 clock.m2 = 8;
660 }
661 intel_clock(dev, refclk, &clock);
662 memcpy(best_clock, &clock, sizeof(intel_clock_t));
663 return true;
664}
665
a4fc5ed6
KP		 666/* DisplayPort has only two frequencies, 162MHz and 270MHz */
667static bool
668intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *best_clock)
670{
5eddb70b
CW		 671 intel_clock_t clock;
672 if (target < 200000) {
673 clock.p1 = 2;
674 clock.p2 = 10;
675 clock.n = 2;
676 clock.m1 = 23;
677 clock.m2 = 8;
678 } else {
679 clock.p1 = 1;
680 clock.p2 = 10;
681 clock.n = 1;
682 clock.m1 = 14;
683 clock.m2 = 2;
684 }
685 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
686 clock.p = (clock.p1 * clock.p2);
687 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
688 clock.vco = 0;
689 memcpy(best_clock, &clock, sizeof(intel_clock_t));
690 return true;
a4fc5ed6
KP		 691}
692
9d0498a2
JB		 693/**
694 * intel_wait_for_vblank - wait for vblank on a given pipe
695 * @dev: drm device
696 * @pipe: pipe to wait for
697 *
698 * Wait for vblank to occur on a given pipe. Needed for various bits of
699 * mode setting code.
700 */
701void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 702{
9d0498a2 703 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 704 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 705
300387c0
CW		 706 /* Clear existing vblank status. Note this will clear any other
707 * sticky status fields as well.
708 *
709 * This races with i915_driver_irq_handler() with the result
710 * that either function could miss a vblank event. Here it is not
711 * fatal, as we will either wait upon the next vblank interrupt or
712 * timeout. Generally speaking intel_wait_for_vblank() is only
713 * called during modeset at which time the GPU should be idle and
714 * should *not* be performing page flips and thus not waiting on
715 * vblanks...
716 * Currently, the result of us stealing a vblank from the irq
717 * handler is that a single frame will be skipped during swapbuffers.
718 */
719 I915_WRITE(pipestat_reg,
720 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
721
9d0498a2 722 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 723 if (wait_for(I915_READ(pipestat_reg) &
724 PIPE_VBLANK_INTERRUPT_STATUS,
725 50))
9d0498a2
JB		 726 DRM_DEBUG_KMS("vblank wait timed out\n");
727}
728
ab7ad7f6
KP		 729/*
730 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 731 * @dev: drm device
732 * @pipe: pipe to wait for
733 *
734 * After disabling a pipe, we can't wait for vblank in the usual way,
735 * spinning on the vblank interrupt status bit, since we won't actually
736 * see an interrupt when the pipe is disabled.
737 *
ab7ad7f6
KP		 738 * On Gen4 and above:
739 * wait for the pipe register state bit to turn off
740 *
741 * Otherwise:
742 * wait for the display line value to settle (it usually
743 * ends up stopping at the start of the next frame).
58e10eb9 744 *
9d0498a2 745 */
58e10eb9 746void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 749
750 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 751 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 752
753 /* Wait for the Pipe State to go off */
58e10eb9
CW		 754 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
755 100))
ab7ad7f6
KP		 756 DRM_DEBUG_KMS("pipe_off wait timed out\n");
757 } else {
758 u32 last_line;
58e10eb9 759 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 760 unsigned long timeout = jiffies + msecs_to_jiffies(100);
761
762 /* Wait for the display line to settle */
763 do {
58e10eb9 764 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 765 mdelay(5);
58e10eb9 766 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 767 time_after(timeout, jiffies));
768 if (time_after(jiffies, timeout))
769 DRM_DEBUG_KMS("pipe_off wait timed out\n");
770 }
79e53945
JB		 771}
772
b24e7179
JB		 773static const char *state_string(bool enabled)
774{
775 return enabled ? "on" : "off";
776}
777
778/* Only for pre-ILK configs */
779static void assert_pll(struct drm_i915_private *dev_priv,
780 enum pipe pipe, bool state)
781{
782 int reg;
783 u32 val;
784 bool cur_state;
785
786 reg = DPLL(pipe);
787 val = I915_READ(reg);
788 cur_state = !!(val & DPLL_VCO_ENABLE);
789 WARN(cur_state != state,
790 "PLL state assertion failure (expected %s, current %s)\n",
791 state_string(state), state_string(cur_state));
792}
793#define assert_pll_enabled(d, p) assert_pll(d, p, true)
794#define assert_pll_disabled(d, p) assert_pll(d, p, false)
795
040484af
JB		 796/* For ILK+ */
797static void assert_pch_pll(struct drm_i915_private *dev_priv,
798 enum pipe pipe, bool state)
799{
800 int reg;
801 u32 val;
802 bool cur_state;
803
804 reg = PCH_DPLL(pipe);
805 val = I915_READ(reg);
806 cur_state = !!(val & DPLL_VCO_ENABLE);
807 WARN(cur_state != state,
808 "PCH PLL state assertion failure (expected %s, current %s)\n",
809 state_string(state), state_string(cur_state));
810}
811#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
812#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
813
814static void assert_fdi_tx(struct drm_i915_private *dev_priv,
815 enum pipe pipe, bool state)
816{
817 int reg;
818 u32 val;
819 bool cur_state;
820
821 reg = FDI_TX_CTL(pipe);
822 val = I915_READ(reg);
823 cur_state = !!(val & FDI_TX_ENABLE);
824 WARN(cur_state != state,
825 "FDI TX state assertion failure (expected %s, current %s)\n",
826 state_string(state), state_string(cur_state));
827}
828#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
829#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
830
831static void assert_fdi_rx(struct drm_i915_private *dev_priv,
832 enum pipe pipe, bool state)
833{
834 int reg;
835 u32 val;
836 bool cur_state;
837
838 reg = FDI_RX_CTL(pipe);
839 val = I915_READ(reg);
840 cur_state = !!(val & FDI_RX_ENABLE);
841 WARN(cur_state != state,
842 "FDI RX state assertion failure (expected %s, current %s)\n",
843 state_string(state), state_string(cur_state));
844}
845#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
846#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
847
848static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
849 enum pipe pipe)
850{
851 int reg;
852 u32 val;
853
854 /* ILK FDI PLL is always enabled */
855 if (dev_priv->info->gen == 5)
856 return;
857
858 reg = FDI_TX_CTL(pipe);
859 val = I915_READ(reg);
860 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
861}
862
863static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 reg = FDI_RX_CTL(pipe);
870 val = I915_READ(reg);
871 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
872}
873
ea0760cf
JB		 874static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
875 enum pipe pipe)
876{
877 int pp_reg, lvds_reg;
878 u32 val;
879 enum pipe panel_pipe = PIPE_A;
880 bool locked = locked;
881
882 if (HAS_PCH_SPLIT(dev_priv->dev)) {
883 pp_reg = PCH_PP_CONTROL;
884 lvds_reg = PCH_LVDS;
885 } else {
886 pp_reg = PP_CONTROL;
887 lvds_reg = LVDS;
888 }
889
890 val = I915_READ(pp_reg);
891 if (!(val & PANEL_POWER_ON) ||
892 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
893 locked = false;
894
895 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
896 panel_pipe = PIPE_B;
897
898 WARN(panel_pipe == pipe && locked,
899 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 900 pipe_name(pipe));
ea0760cf
JB		 901}
902
63d7bbe9
JB		 903static void assert_pipe(struct drm_i915_private *dev_priv,
904 enum pipe pipe, bool state)
b24e7179
JB		 905{
906 int reg;
907 u32 val;
63d7bbe9 908 bool cur_state;
b24e7179
JB		 909
910 reg = PIPECONF(pipe);
911 val = I915_READ(reg);
63d7bbe9
JB		 912 cur_state = !!(val & PIPECONF_ENABLE);
913 WARN(cur_state != state,
914 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 915 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 916}
63d7bbe9
JB		 917#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
918#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 919
920static void assert_plane_enabled(struct drm_i915_private *dev_priv,
921 enum plane plane)
922{
923 int reg;
924 u32 val;
925
926 reg = DSPCNTR(plane);
927 val = I915_READ(reg);
928 WARN(!(val & DISPLAY_PLANE_ENABLE),
929 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 930 plane_name(plane));
b24e7179
JB		 931}
932
933static void assert_planes_disabled(struct drm_i915_private *dev_priv,
934 enum pipe pipe)
935{
936 int reg, i;
937 u32 val;
938 int cur_pipe;
939
19ec1358
JB		 940 /* Planes are fixed to pipes on ILK+ */
941 if (HAS_PCH_SPLIT(dev_priv->dev))
942 return;
943
b24e7179
JB		 944 /* Need to check both planes against the pipe */
945 for (i = 0; i < 2; i++) {
946 reg = DSPCNTR(i);
947 val = I915_READ(reg);
948 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
949 DISPPLANE_SEL_PIPE_SHIFT;
950 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 951 "plane %c assertion failure, should be off on pipe %c but is still active\n",
952 plane_name(i), pipe_name(pipe));
b24e7179
JB		 953 }
954}
955
92f2584a
JB		 956static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
957{
958 u32 val;
959 bool enabled;
960
961 val = I915_READ(PCH_DREF_CONTROL);
962 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
963 DREF_SUPERSPREAD_SOURCE_MASK));
964 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
965}
966
967static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
968 enum pipe pipe)
969{
970 int reg;
971 u32 val;
972 bool enabled;
973
974 reg = TRANSCONF(pipe);
975 val = I915_READ(reg);
976 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 977 WARN(enabled,
978 "transcoder assertion failed, should be off on pipe %c but is still active\n",
979 pipe_name(pipe));
92f2584a
JB		 980}
981
291906f1
JB		 982static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
983 enum pipe pipe, int reg)
984{
47a05eca
JB		 985 u32 val = I915_READ(reg);
986 WARN(DP_PIPE_ENABLED(val, pipe),
291906f1 987 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 988 reg, pipe_name(pipe));
291906f1
JB		 989}
990
991static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
992 enum pipe pipe, int reg)
993{
47a05eca
JB		 994 u32 val = I915_READ(reg);
995 WARN(HDMI_PIPE_ENABLED(val, pipe),
291906f1 996 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 997 reg, pipe_name(pipe));
291906f1
JB		 998}
999
1000static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1001 enum pipe pipe)
1002{
1003 int reg;
1004 u32 val;
291906f1
JB		 1005
1006 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1007 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1008 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1009
1010 reg = PCH_ADPA;
1011 val = I915_READ(reg);
47a05eca 1012 WARN(ADPA_PIPE_ENABLED(val, pipe),
291906f1 1013 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1014 pipe_name(pipe));
291906f1
JB		 1015
1016 reg = PCH_LVDS;
1017 val = I915_READ(reg);
47a05eca 1018 WARN(LVDS_PIPE_ENABLED(val, pipe),
291906f1 1019 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1020 pipe_name(pipe));
291906f1
JB		 1021
1022 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1023 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1024 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1025}
1026
63d7bbe9
JB		 1027/**
1028 * intel_enable_pll - enable a PLL
1029 * @dev_priv: i915 private structure
1030 * @pipe: pipe PLL to enable
1031 *
1032 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1033 * make sure the PLL reg is writable first though, since the panel write
1034 * protect mechanism may be enabled.
1035 *
1036 * Note! This is for pre-ILK only.
1037 */
1038static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1039{
1040 int reg;
1041 u32 val;
1042
1043 /* No really, not for ILK+ */
1044 BUG_ON(dev_priv->info->gen >= 5);
1045
1046 /* PLL is protected by panel, make sure we can write it */
1047 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1048 assert_panel_unlocked(dev_priv, pipe);
1049
1050 reg = DPLL(pipe);
1051 val = I915_READ(reg);
1052 val |= DPLL_VCO_ENABLE;
1053
1054 /* We do this three times for luck */
1055 I915_WRITE(reg, val);
1056 POSTING_READ(reg);
1057 udelay(150); /* wait for warmup */
1058 I915_WRITE(reg, val);
1059 POSTING_READ(reg);
1060 udelay(150); /* wait for warmup */
1061 I915_WRITE(reg, val);
1062 POSTING_READ(reg);
1063 udelay(150); /* wait for warmup */
1064}
1065
1066/**
1067 * intel_disable_pll - disable a PLL
1068 * @dev_priv: i915 private structure
1069 * @pipe: pipe PLL to disable
1070 *
1071 * Disable the PLL for @pipe, making sure the pipe is off first.
1072 *
1073 * Note! This is for pre-ILK only.
1074 */
1075static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1076{
1077 int reg;
1078 u32 val;
1079
1080 /* Don't disable pipe A or pipe A PLLs if needed */
1081 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1082 return;
1083
1084 /* Make sure the pipe isn't still relying on us */
1085 assert_pipe_disabled(dev_priv, pipe);
1086
1087 reg = DPLL(pipe);
1088 val = I915_READ(reg);
1089 val &= ~DPLL_VCO_ENABLE;
1090 I915_WRITE(reg, val);
1091 POSTING_READ(reg);
1092}
1093
92f2584a
JB		 1094/**
1095 * intel_enable_pch_pll - enable PCH PLL
1096 * @dev_priv: i915 private structure
1097 * @pipe: pipe PLL to enable
1098 *
1099 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1100 * drives the transcoder clock.
1101 */
1102static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1103 enum pipe pipe)
1104{
1105 int reg;
1106 u32 val;
1107
1108 /* PCH only available on ILK+ */
1109 BUG_ON(dev_priv->info->gen < 5);
1110
1111 /* PCH refclock must be enabled first */
1112 assert_pch_refclk_enabled(dev_priv);
1113
1114 reg = PCH_DPLL(pipe);
1115 val = I915_READ(reg);
1116 val |= DPLL_VCO_ENABLE;
1117 I915_WRITE(reg, val);
1118 POSTING_READ(reg);
1119 udelay(200);
1120}
1121
1122static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124{
1125 int reg;
1126 u32 val;
1127
1128 /* PCH only available on ILK+ */
1129 BUG_ON(dev_priv->info->gen < 5);
1130
1131 /* Make sure transcoder isn't still depending on us */
1132 assert_transcoder_disabled(dev_priv, pipe);
1133
1134 reg = PCH_DPLL(pipe);
1135 val = I915_READ(reg);
1136 val &= ~DPLL_VCO_ENABLE;
1137 I915_WRITE(reg, val);
1138 POSTING_READ(reg);
1139 udelay(200);
1140}
1141
040484af
JB		 1142static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1143 enum pipe pipe)
1144{
1145 int reg;
1146 u32 val;
1147
1148 /* PCH only available on ILK+ */
1149 BUG_ON(dev_priv->info->gen < 5);
1150
1151 /* Make sure PCH DPLL is enabled */
1152 assert_pch_pll_enabled(dev_priv, pipe);
1153
1154 /* FDI must be feeding us bits for PCH ports */
1155 assert_fdi_tx_enabled(dev_priv, pipe);
1156 assert_fdi_rx_enabled(dev_priv, pipe);
1157
1158 reg = TRANSCONF(pipe);
1159 val = I915_READ(reg);
1160 /*
1161 * make the BPC in transcoder be consistent with
1162 * that in pipeconf reg.
1163 */
1164 val &= ~PIPE_BPC_MASK;
1165 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1166 I915_WRITE(reg, val | TRANS_ENABLE);
1167 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1168 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1169}
1170
1171static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
1173{
1174 int reg;
1175 u32 val;
1176
1177 /* FDI relies on the transcoder */
1178 assert_fdi_tx_disabled(dev_priv, pipe);
1179 assert_fdi_rx_disabled(dev_priv, pipe);
1180
291906f1
JB		 1181 /* Ports must be off as well */
1182 assert_pch_ports_disabled(dev_priv, pipe);
1183
040484af
JB		 1184 reg = TRANSCONF(pipe);
1185 val = I915_READ(reg);
1186 val &= ~TRANS_ENABLE;
1187 I915_WRITE(reg, val);
1188 /* wait for PCH transcoder off, transcoder state */
1189 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1190 DRM_ERROR("failed to disable transcoder\n");
1191}
1192
b24e7179 1193/**
309cfea8 1194 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1195 * @dev_priv: i915 private structure
1196 * @pipe: pipe to enable
040484af 1197 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1198 *
1199 * Enable @pipe, making sure that various hardware specific requirements
1200 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1201 *
1202 * @pipe should be %PIPE_A or %PIPE_B.
1203 *
1204 * Will wait until the pipe is actually running (i.e. first vblank) before
1205 * returning.
1206 */
040484af
JB		 1207static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1208 bool pch_port)
b24e7179
JB		 1209{
1210 int reg;
1211 u32 val;
1212
1213 /*
1214 * A pipe without a PLL won't actually be able to drive bits from
1215 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1216 * need the check.
1217 */
1218 if (!HAS_PCH_SPLIT(dev_priv->dev))
1219 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1220 else {
1221 if (pch_port) {
1222 /* if driving the PCH, we need FDI enabled */
1223 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1224 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1225 }
1226 /* FIXME: assert CPU port conditions for SNB+ */
1227 }
b24e7179
JB		 1228
1229 reg = PIPECONF(pipe);
1230 val = I915_READ(reg);
00d70b15
CW		 1231 if (val & PIPECONF_ENABLE)
1232 return;
1233
1234 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1235 intel_wait_for_vblank(dev_priv->dev, pipe);
1236}
1237
1238/**
309cfea8 1239 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1240 * @dev_priv: i915 private structure
1241 * @pipe: pipe to disable
1242 *
1243 * Disable @pipe, making sure that various hardware specific requirements
1244 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1245 *
1246 * @pipe should be %PIPE_A or %PIPE_B.
1247 *
1248 * Will wait until the pipe has shut down before returning.
1249 */
1250static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1251 enum pipe pipe)
1252{
1253 int reg;
1254 u32 val;
1255
1256 /*
1257 * Make sure planes won't keep trying to pump pixels to us,
1258 * or we might hang the display.
1259 */
1260 assert_planes_disabled(dev_priv, pipe);
1261
1262 /* Don't disable pipe A or pipe A PLLs if needed */
1263 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1264 return;
1265
1266 reg = PIPECONF(pipe);
1267 val = I915_READ(reg);
00d70b15
CW		 1268 if ((val & PIPECONF_ENABLE) == 0)
1269 return;
1270
1271 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1272 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1273}
1274
1275/**
1276 * intel_enable_plane - enable a display plane on a given pipe
1277 * @dev_priv: i915 private structure
1278 * @plane: plane to enable
1279 * @pipe: pipe being fed
1280 *
1281 * Enable @plane on @pipe, making sure that @pipe is running first.
1282 */
1283static void intel_enable_plane(struct drm_i915_private *dev_priv,
1284 enum plane plane, enum pipe pipe)
1285{
1286 int reg;
1287 u32 val;
1288
1289 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1290 assert_pipe_enabled(dev_priv, pipe);
1291
1292 reg = DSPCNTR(plane);
1293 val = I915_READ(reg);
00d70b15
CW		 1294 if (val & DISPLAY_PLANE_ENABLE)
1295 return;
1296
1297 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1298 intel_wait_for_vblank(dev_priv->dev, pipe);
1299}
1300
1301/*
1302 * Plane regs are double buffered, going from enabled->disabled needs a
1303 * trigger in order to latch. The display address reg provides this.
1304 */
1305static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1306 enum plane plane)
1307{
1308 u32 reg = DSPADDR(plane);
1309 I915_WRITE(reg, I915_READ(reg));
1310}
1311
1312/**
1313 * intel_disable_plane - disable a display plane
1314 * @dev_priv: i915 private structure
1315 * @plane: plane to disable
1316 * @pipe: pipe consuming the data
1317 *
1318 * Disable @plane; should be an independent operation.
1319 */
1320static void intel_disable_plane(struct drm_i915_private *dev_priv,
1321 enum plane plane, enum pipe pipe)
1322{
1323 int reg;
1324 u32 val;
1325
1326 reg = DSPCNTR(plane);
1327 val = I915_READ(reg);
00d70b15
CW		 1328 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1329 return;
1330
1331 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1332 intel_flush_display_plane(dev_priv, plane);
1333 intel_wait_for_vblank(dev_priv->dev, pipe);
1334}
1335
47a05eca
JB		 1336static void disable_pch_dp(struct drm_i915_private *dev_priv,
1337 enum pipe pipe, int reg)
1338{
1339 u32 val = I915_READ(reg);
1340 if (DP_PIPE_ENABLED(val, pipe))
1341 I915_WRITE(reg, val & ~DP_PORT_EN);
1342}
1343
1344static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, int reg)
1346{
1347 u32 val = I915_READ(reg);
1348 if (HDMI_PIPE_ENABLED(val, pipe))
1349 I915_WRITE(reg, val & ~PORT_ENABLE);
1350}
1351
1352/* Disable any ports connected to this transcoder */
1353static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1354 enum pipe pipe)
1355{
1356 u32 reg, val;
1357
1358 val = I915_READ(PCH_PP_CONTROL);
1359 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1360
1361 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1362 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1363 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1364
1365 reg = PCH_ADPA;
1366 val = I915_READ(reg);
1367 if (ADPA_PIPE_ENABLED(val, pipe))
1368 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1369
1370 reg = PCH_LVDS;
1371 val = I915_READ(reg);
1372 if (LVDS_PIPE_ENABLED(val, pipe)) {
1373 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1374 POSTING_READ(reg);
1375 udelay(100);
1376 }
1377
1378 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1379 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1380 disable_pch_hdmi(dev_priv, pipe, HDMID);
1381}
1382
80824003
JB		 1383static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1384{
1385 struct drm_device *dev = crtc->dev;
1386 struct drm_i915_private *dev_priv = dev->dev_private;
1387 struct drm_framebuffer *fb = crtc->fb;
1388 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1389 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB		 1390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1391 int plane, i;
1392 u32 fbc_ctl, fbc_ctl2;
1393
bed4a673 1394 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1395 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW		 1396 intel_crtc->plane == dev_priv->cfb_plane &&
1397 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1398 return;
1399
1400 i8xx_disable_fbc(dev);
1401
80824003
JB		 1402 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1403
1404 if (fb->pitch < dev_priv->cfb_pitch)
1405 dev_priv->cfb_pitch = fb->pitch;
1406
1407 /* FBC_CTL wants 64B units */
1408 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1409 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB		 1410 dev_priv->cfb_plane = intel_crtc->plane;
1411 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1412
1413 /* Clear old tags */
1414 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1415 I915_WRITE(FBC_TAG + (i * 4), 0);
1416
1417 /* Set it up... */
1418 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
05394f39 1419 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1420 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1421 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1422 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1423
1424 /* enable it... */
1425 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1426 if (IS_I945GM(dev))
49677901 1427 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB		 1428 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1429 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
05394f39 1430 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1431 fbc_ctl |= dev_priv->cfb_fence;
1432 I915_WRITE(FBC_CONTROL, fbc_ctl);
1433
28c97730 1434 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1435 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB		 1436}
1437
1438void i8xx_disable_fbc(struct drm_device *dev)
1439{
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441 u32 fbc_ctl;
1442
1443 /* Disable compression */
1444 fbc_ctl = I915_READ(FBC_CONTROL);
a5cad620
CW		 1445 if ((fbc_ctl & FBC_CTL_EN) == 0)
1446 return;
1447
80824003
JB		 1448 fbc_ctl &= ~FBC_CTL_EN;
1449 I915_WRITE(FBC_CONTROL, fbc_ctl);
1450
1451 /* Wait for compressing bit to clear */
481b6af3 1452 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
913d8d11
CW		 1453 DRM_DEBUG_KMS("FBC idle timed out\n");
1454 return;
9517a92f 1455 }
80824003 1456
28c97730 1457 DRM_DEBUG_KMS("disabled FBC\n");
80824003
JB		 1458}
1459
ee5382ae 1460static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1461{
80824003
JB		 1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1465}
1466
74dff282
JB		 1467static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1468{
1469 struct drm_device *dev = crtc->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 struct drm_framebuffer *fb = crtc->fb;
1472 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1473 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1475 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1476 unsigned long stall_watermark = 200;
1477 u32 dpfc_ctl;
1478
bed4a673
CW		 1479 dpfc_ctl = I915_READ(DPFC_CONTROL);
1480 if (dpfc_ctl & DPFC_CTL_EN) {
1481 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1482 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW		 1483 dev_priv->cfb_plane == intel_crtc->plane &&
1484 dev_priv->cfb_y == crtc->y)
1485 return;
1486
1487 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1488 intel_wait_for_vblank(dev, intel_crtc->pipe);
1489 }
1490
74dff282 1491 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1492 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1493 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1494 dev_priv->cfb_y = crtc->y;
74dff282
JB		 1495
1496 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
05394f39 1497 if (obj->tiling_mode != I915_TILING_NONE) {
74dff282
JB		 1498 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1499 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1500 } else {
1501 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1502 }
1503
74dff282
JB		 1504 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1505 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1506 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1507 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1508
1509 /* enable it... */
1510 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1511
28c97730 1512 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1513}
1514
1515void g4x_disable_fbc(struct drm_device *dev)
1516{
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518 u32 dpfc_ctl;
1519
1520 /* Disable compression */
1521 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1522 if (dpfc_ctl & DPFC_CTL_EN) {
1523 dpfc_ctl &= ~DPFC_CTL_EN;
1524 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1525
bed4a673
CW		 1526 DRM_DEBUG_KMS("disabled FBC\n");
1527 }
74dff282
JB		 1528}
1529
ee5382ae 1530static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1531{
74dff282
JB		 1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533
1534 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1535}
1536
4efe0708
JB		 1537static void sandybridge_blit_fbc_update(struct drm_device *dev)
1538{
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540 u32 blt_ecoskpd;
1541
1542 /* Make sure blitter notifies FBC of writes */
fcca7926 1543 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1544 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1545 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1546 GEN6_BLITTER_LOCK_SHIFT;
1547 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1548 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1549 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1550 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1551 GEN6_BLITTER_LOCK_SHIFT);
1552 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1553 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1554 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1555}
1556
b52eb4dc
ZY		 1557static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1558{
1559 struct drm_device *dev = crtc->dev;
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 struct drm_framebuffer *fb = crtc->fb;
1562 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1563 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1565 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1566 unsigned long stall_watermark = 200;
1567 u32 dpfc_ctl;
1568
bed4a673
CW		 1569 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1570 if (dpfc_ctl & DPFC_CTL_EN) {
1571 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1572 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1573 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1574 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW		 1575 dev_priv->cfb_y == crtc->y)
1576 return;
1577
1578 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1579 intel_wait_for_vblank(dev, intel_crtc->pipe);
1580 }
1581
b52eb4dc 1582 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1583 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1584 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1585 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1586 dev_priv->cfb_y = crtc->y;
b52eb4dc 1587
b52eb4dc
ZY		 1588 dpfc_ctl &= DPFC_RESERVED;
1589 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
05394f39 1590 if (obj->tiling_mode != I915_TILING_NONE) {
b52eb4dc
ZY		 1591 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1592 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1593 } else {
1594 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1595 }
1596
b52eb4dc
ZY		 1597 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1598 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1599 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1600 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1601 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1602 /* enable it... */
bed4a673 1603 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1604
9c04f015
YL		 1605 if (IS_GEN6(dev)) {
1606 I915_WRITE(SNB_DPFC_CTL_SA,
1607 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1608 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1609 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1610 }
1611
b52eb4dc
ZY		 1612 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1613}
1614
1615void ironlake_disable_fbc(struct drm_device *dev)
1616{
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 u32 dpfc_ctl;
1619
1620 /* Disable compression */
1621 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1622 if (dpfc_ctl & DPFC_CTL_EN) {
1623 dpfc_ctl &= ~DPFC_CTL_EN;
1624 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1625
bed4a673
CW		 1626 DRM_DEBUG_KMS("disabled FBC\n");
1627 }
b52eb4dc
ZY		 1628}
1629
1630static bool ironlake_fbc_enabled(struct drm_device *dev)
1631{
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1635}
1636
ee5382ae
AJ		 1637bool intel_fbc_enabled(struct drm_device *dev)
1638{
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640
1641 if (!dev_priv->display.fbc_enabled)
1642 return false;
1643
1644 return dev_priv->display.fbc_enabled(dev);
1645}
1646
1647void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1648{
1649 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1650
1651 if (!dev_priv->display.enable_fbc)
1652 return;
1653
1654 dev_priv->display.enable_fbc(crtc, interval);
1655}
1656
1657void intel_disable_fbc(struct drm_device *dev)
1658{
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661 if (!dev_priv->display.disable_fbc)
1662 return;
1663
1664 dev_priv->display.disable_fbc(dev);
1665}
1666
80824003
JB		 1667/**
1668 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1669 * @dev: the drm_device
80824003
JB		 1670 *
1671 * Set up the framebuffer compression hardware at mode set time. We
1672 * enable it if possible:
1673 * - plane A only (on pre-965)
1674 * - no pixel mulitply/line duplication
1675 * - no alpha buffer discard
1676 * - no dual wide
1677 * - framebuffer <= 2048 in width, 1536 in height
1678 *
1679 * We can't assume that any compression will take place (worst case),
1680 * so the compressed buffer has to be the same size as the uncompressed
1681 * one. It also must reside (along with the line length buffer) in
1682 * stolen memory.
1683 *
1684 * We need to enable/disable FBC on a global basis.
1685 */
bed4a673 1686static void intel_update_fbc(struct drm_device *dev)
80824003 1687{
80824003 1688 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1689 struct drm_crtc *crtc = NULL, *tmp_crtc;
1690 struct intel_crtc *intel_crtc;
1691 struct drm_framebuffer *fb;
80824003 1692 struct intel_framebuffer *intel_fb;
05394f39 1693 struct drm_i915_gem_object *obj;
9c928d16
JB		 1694
1695 DRM_DEBUG_KMS("\n");
80824003
JB		 1696
1697 if (!i915_powersave)
1698 return;
1699
ee5382ae 1700 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1701 return;
1702
80824003
JB		 1703 /*
1704 * If FBC is already on, we just have to verify that we can
1705 * keep it that way...
1706 * Need to disable if:
9c928d16 1707 * - more than one pipe is active
80824003
JB		 1708 * - changing FBC params (stride, fence, mode)
1709 * - new fb is too large to fit in compressed buffer
1710 * - going to an unsupported config (interlace, pixel multiply, etc.)
1711 */
9c928d16 1712 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1713 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1714 if (crtc) {
1715 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1716 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1717 goto out_disable;
1718 }
1719 crtc = tmp_crtc;
1720 }
9c928d16 1721 }
bed4a673
CW		 1722
1723 if (!crtc || crtc->fb == NULL) {
1724 DRM_DEBUG_KMS("no output, disabling\n");
1725 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1726 goto out_disable;
1727 }
bed4a673
CW		 1728
1729 intel_crtc = to_intel_crtc(crtc);
1730 fb = crtc->fb;
1731 intel_fb = to_intel_framebuffer(fb);
05394f39 1732 obj = intel_fb->obj;
bed4a673 1733
05394f39 1734 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1735 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1736 "compression\n");
b5e50c3f 1737 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1738 goto out_disable;
1739 }
bed4a673
CW		 1740 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1741 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1742 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1743 "disabling\n");
b5e50c3f 1744 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1745 goto out_disable;
1746 }
bed4a673
CW		 1747 if ((crtc->mode.hdisplay > 2048) ||
1748 (crtc->mode.vdisplay > 1536)) {
28c97730 1749 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1750 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1751 goto out_disable;
1752 }
bed4a673 1753 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1754 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1755 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1756 goto out_disable;
1757 }
05394f39 1758 if (obj->tiling_mode != I915_TILING_X) {
28c97730 1759 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
b5e50c3f 1760 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1761 goto out_disable;
1762 }
1763
c924b934
JW		 1764 /* If the kernel debugger is active, always disable compression */
1765 if (in_dbg_master())
1766 goto out_disable;
1767
bed4a673 1768 intel_enable_fbc(crtc, 500);
80824003
JB		 1769 return;
1770
1771out_disable:
80824003 1772 /* Multiple disables should be harmless */
a939406f
CW		 1773 if (intel_fbc_enabled(dev)) {
1774 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1775 intel_disable_fbc(dev);
a939406f 1776 }
80824003
JB		 1777}
1778
127bd2ac 1779int
48b956c5 1780intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1781 struct drm_i915_gem_object *obj,
919926ae 1782 struct intel_ring_buffer *pipelined)
6b95a207 1783{
ce453d81 1784 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1785 u32 alignment;
1786 int ret;
1787
05394f39 1788 switch (obj->tiling_mode) {
6b95a207 1789 case I915_TILING_NONE:
534843da
CW		 1790 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1791 alignment = 128 * 1024;
a6c45cf0 1792 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1793 alignment = 4 * 1024;
1794 else
1795 alignment = 64 * 1024;
6b95a207
KH		 1796 break;
1797 case I915_TILING_X:
1798 /* pin() will align the object as required by fence */
1799 alignment = 0;
1800 break;
1801 case I915_TILING_Y:
1802 /* FIXME: Is this true? */
1803 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1804 return -EINVAL;
1805 default:
1806 BUG();
1807 }
1808
ce453d81 1809 dev_priv->mm.interruptible = false;
75e9e915 1810 ret = i915_gem_object_pin(obj, alignment, true);
48b956c5 1811 if (ret)
ce453d81 1812 goto err_interruptible;
6b95a207 1813
48b956c5
CW		 1814 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1815 if (ret)
1816 goto err_unpin;
7213342d 1817
6b95a207
KH		 1818 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1819 * fence, whereas 965+ only requires a fence if using
1820 * framebuffer compression. For simplicity, we always install
1821 * a fence as the cost is not that onerous.
1822 */
05394f39 1823 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1824 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1825 if (ret)
1826 goto err_unpin;
6b95a207
KH		 1827 }
1828
ce453d81 1829 dev_priv->mm.interruptible = true;
6b95a207 1830 return 0;
48b956c5
CW		 1831
1832err_unpin:
1833 i915_gem_object_unpin(obj);
ce453d81
CW		 1834err_interruptible:
1835 dev_priv->mm.interruptible = true;
48b956c5 1836 return ret;
6b95a207
KH		 1837}
1838
81255565
JB		 1839/* Assume fb object is pinned & idle & fenced and just update base pointers */
1840static int
1841intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
21c74a8e 1842 int x, int y, enum mode_set_atomic state)
81255565
JB		 1843{
1844 struct drm_device *dev = crtc->dev;
1845 struct drm_i915_private *dev_priv = dev->dev_private;
1846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1847 struct intel_framebuffer *intel_fb;
05394f39 1848 struct drm_i915_gem_object *obj;
81255565
JB		 1849 int plane = intel_crtc->plane;
1850 unsigned long Start, Offset;
81255565 1851 u32 dspcntr;
5eddb70b 1852 u32 reg;
81255565
JB		 1853
1854 switch (plane) {
1855 case 0:
1856 case 1:
1857 break;
1858 default:
1859 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1860 return -EINVAL;
1861 }
1862
1863 intel_fb = to_intel_framebuffer(fb);
1864 obj = intel_fb->obj;
81255565 1865
5eddb70b
CW		 1866 reg = DSPCNTR(plane);
1867 dspcntr = I915_READ(reg);
81255565
JB		 1868 /* Mask out pixel format bits in case we change it */
1869 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1870 switch (fb->bits_per_pixel) {
1871 case 8:
1872 dspcntr |= DISPPLANE_8BPP;
1873 break;
1874 case 16:
1875 if (fb->depth == 15)
1876 dspcntr |= DISPPLANE_15_16BPP;
1877 else
1878 dspcntr |= DISPPLANE_16BPP;
1879 break;
1880 case 24:
1881 case 32:
1882 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1883 break;
1884 default:
1885 DRM_ERROR("Unknown color depth\n");
1886 return -EINVAL;
1887 }
a6c45cf0 1888 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1889 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1890 dspcntr |= DISPPLANE_TILED;
1891 else
1892 dspcntr &= ~DISPPLANE_TILED;
1893 }
1894
4e6cfefc 1895 if (HAS_PCH_SPLIT(dev))
81255565
JB		 1896 /* must disable */
1897 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1898
5eddb70b 1899 I915_WRITE(reg, dspcntr);
81255565 1900
05394f39 1901 Start = obj->gtt_offset;
81255565
JB		 1902 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1903
4e6cfefc
CW		 1904 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1905 Start, Offset, x, y, fb->pitch);
5eddb70b 1906 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1907 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 1908 I915_WRITE(DSPSURF(plane), Start);
1909 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1910 I915_WRITE(DSPADDR(plane), Offset);
1911 } else
1912 I915_WRITE(DSPADDR(plane), Start + Offset);
1913 POSTING_READ(reg);
81255565 1914
bed4a673 1915 intel_update_fbc(dev);
3dec0095 1916 intel_increase_pllclock(crtc);
81255565
JB		 1917
1918 return 0;
1919}
1920
5c3b82e2 1921static int
3c4fdcfb
KH		 1922intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1923 struct drm_framebuffer *old_fb)
79e53945
JB		 1924{
1925 struct drm_device *dev = crtc->dev;
79e53945
JB		 1926 struct drm_i915_master_private *master_priv;
1927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1928 int ret;
79e53945
JB		 1929
1930 /* no fb bound */
1931 if (!crtc->fb) {
28c97730 1932 DRM_DEBUG_KMS("No FB bound\n");
5c3b82e2
CW		 1933 return 0;
1934 }
1935
265db958 1936 switch (intel_crtc->plane) {
5c3b82e2
CW		 1937 case 0:
1938 case 1:
1939 break;
1940 default:
5c3b82e2 1941 return -EINVAL;
79e53945
JB		 1942 }
1943
5c3b82e2 1944 mutex_lock(&dev->struct_mutex);
265db958
CW		 1945 ret = intel_pin_and_fence_fb_obj(dev,
1946 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1947 NULL);
5c3b82e2
CW		 1948 if (ret != 0) {
1949 mutex_unlock(&dev->struct_mutex);
1950 return ret;
1951 }
79e53945 1952
265db958 1953 if (old_fb) {
e6c3a2a6 1954 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1955 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 1956
e6c3a2a6 1957 wait_event(dev_priv->pending_flip_queue,
01eec727 1958 atomic_read(&dev_priv->mm.wedged) ||
05394f39 1959 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 1960
1961 /* Big Hammer, we also need to ensure that any pending
1962 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1963 * current scanout is retired before unpinning the old
1964 * framebuffer.
01eec727
CW		 1965 *
1966 * This should only fail upon a hung GPU, in which case we
1967 * can safely continue.
85345517 1968 */
ce453d81 1969 ret = i915_gem_object_flush_gpu(obj);
01eec727 1970 (void) ret;
265db958
CW		 1971 }
1972
21c74a8e
JW		 1973 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1974 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 1975 if (ret) {
265db958 1976 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 1977 mutex_unlock(&dev->struct_mutex);
4e6cfefc 1978 return ret;
79e53945 1979 }
3c4fdcfb 1980
b7f1de28
CW		 1981 if (old_fb) {
1982 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 1983 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 1984 }
652c393a 1985
5c3b82e2 1986 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 1987
1988 if (!dev->primary->master)
5c3b82e2 1989 return 0;
79e53945
JB		 1990
1991 master_priv = dev->primary->master->driver_priv;
1992 if (!master_priv->sarea_priv)
5c3b82e2 1993 return 0;
79e53945 1994
265db958 1995 if (intel_crtc->pipe) {
79e53945
JB		 1996 master_priv->sarea_priv->pipeB_x = x;
1997 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 1998 } else {
1999 master_priv->sarea_priv->pipeA_x = x;
2000 master_priv->sarea_priv->pipeA_y = y;
79e53945 2001 }
5c3b82e2
CW		 2002
2003 return 0;
79e53945
JB		 2004}
2005
5eddb70b 2006static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2007{
2008 struct drm_device *dev = crtc->dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 u32 dpa_ctl;
2011
28c97730 2012 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2013 dpa_ctl = I915_READ(DP_A);
2014 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2015
2016 if (clock < 200000) {
2017 u32 temp;
2018 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2019 /* workaround for 160Mhz:
2020 1) program 0x4600c bits 15:0 = 0x8124
2021 2) program 0x46010 bit 0 = 1
2022 3) program 0x46034 bit 24 = 1
2023 4) program 0x64000 bit 14 = 1
2024 */
2025 temp = I915_READ(0x4600c);
2026 temp &= 0xffff0000;
2027 I915_WRITE(0x4600c, temp | 0x8124);
2028
2029 temp = I915_READ(0x46010);
2030 I915_WRITE(0x46010, temp | 1);
2031
2032 temp = I915_READ(0x46034);
2033 I915_WRITE(0x46034, temp | (1 << 24));
2034 } else {
2035 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2036 }
2037 I915_WRITE(DP_A, dpa_ctl);
2038
5eddb70b 2039 POSTING_READ(DP_A);
32f9d658
ZW		 2040 udelay(500);
2041}
2042
5e84e1a4
ZW		 2043static void intel_fdi_normal_train(struct drm_crtc *crtc)
2044{
2045 struct drm_device *dev = crtc->dev;
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2048 int pipe = intel_crtc->pipe;
2049 u32 reg, temp;
2050
2051 /* enable normal train */
2052 reg = FDI_TX_CTL(pipe);
2053 temp = I915_READ(reg);
2054 temp &= ~FDI_LINK_TRAIN_NONE;
2055 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2056 I915_WRITE(reg, temp);
2057
2058 reg = FDI_RX_CTL(pipe);
2059 temp = I915_READ(reg);
2060 if (HAS_PCH_CPT(dev)) {
2061 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2062 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2063 } else {
2064 temp &= ~FDI_LINK_TRAIN_NONE;
2065 temp |= FDI_LINK_TRAIN_NONE;
2066 }
2067 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2068
2069 /* wait one idle pattern time */
2070 POSTING_READ(reg);
2071 udelay(1000);
2072}
2073
8db9d77b
ZW		 2074/* The FDI link training functions for ILK/Ibexpeak. */
2075static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2076{
2077 struct drm_device *dev = crtc->dev;
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080 int pipe = intel_crtc->pipe;
0fc932b8 2081 int plane = intel_crtc->plane;
5eddb70b 2082 u32 reg, temp, tries;
8db9d77b 2083
0fc932b8
JB		 2084 /* FDI needs bits from pipe & plane first */
2085 assert_pipe_enabled(dev_priv, pipe);
2086 assert_plane_enabled(dev_priv, plane);
2087
e1a44743
AJ		 2088 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2089 for train result */
5eddb70b
CW		 2090 reg = FDI_RX_IMR(pipe);
2091 temp = I915_READ(reg);
e1a44743
AJ		 2092 temp &= ~FDI_RX_SYMBOL_LOCK;
2093 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2094 I915_WRITE(reg, temp);
2095 I915_READ(reg);
e1a44743
AJ		 2096 udelay(150);
2097
8db9d77b 2098 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2099 reg = FDI_TX_CTL(pipe);
2100 temp = I915_READ(reg);
77ffb597
AJ		 2101 temp &= ~(7 << 19);
2102 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2103 temp &= ~FDI_LINK_TRAIN_NONE;
2104 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2105 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2106
5eddb70b
CW		 2107 reg = FDI_RX_CTL(pipe);
2108 temp = I915_READ(reg);
8db9d77b
ZW		 2109 temp &= ~FDI_LINK_TRAIN_NONE;
2110 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2111 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2112
2113 POSTING_READ(reg);
8db9d77b
ZW		 2114 udelay(150);
2115
5b2adf89 2116 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2117 if (HAS_PCH_IBX(dev)) {
2118 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2119 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2120 FDI_RX_PHASE_SYNC_POINTER_EN);
2121 }
5b2adf89 2122
5eddb70b 2123 reg = FDI_RX_IIR(pipe);
e1a44743 2124 for (tries = 0; tries < 5; tries++) {
5eddb70b 2125 temp = I915_READ(reg);
8db9d77b
ZW		 2126 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2127
2128 if ((temp & FDI_RX_BIT_LOCK)) {
2129 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2130 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2131 break;
2132 }
8db9d77b 2133 }
e1a44743 2134 if (tries == 5)
5eddb70b 2135 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2136
2137 /* Train 2 */
5eddb70b
CW		 2138 reg = FDI_TX_CTL(pipe);
2139 temp = I915_READ(reg);
8db9d77b
ZW		 2140 temp &= ~FDI_LINK_TRAIN_NONE;
2141 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2142 I915_WRITE(reg, temp);
8db9d77b 2143
5eddb70b
CW		 2144 reg = FDI_RX_CTL(pipe);
2145 temp = I915_READ(reg);
8db9d77b
ZW		 2146 temp &= ~FDI_LINK_TRAIN_NONE;
2147 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2148 I915_WRITE(reg, temp);
8db9d77b 2149
5eddb70b
CW		 2150 POSTING_READ(reg);
2151 udelay(150);
8db9d77b 2152
5eddb70b 2153 reg = FDI_RX_IIR(pipe);
e1a44743 2154 for (tries = 0; tries < 5; tries++) {
5eddb70b 2155 temp = I915_READ(reg);
8db9d77b
ZW		 2156 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2157
2158 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2159 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2160 DRM_DEBUG_KMS("FDI train 2 done.\n");
2161 break;
2162 }
8db9d77b 2163 }
e1a44743 2164 if (tries == 5)
5eddb70b 2165 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2166
2167 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2168
8db9d77b
ZW		 2169}
2170
311bd68e 2171static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2172 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2173 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2174 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2175 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2176};
2177
2178/* The FDI link training functions for SNB/Cougarpoint. */
2179static void gen6_fdi_link_train(struct drm_crtc *crtc)
2180{
2181 struct drm_device *dev = crtc->dev;
2182 struct drm_i915_private *dev_priv = dev->dev_private;
2183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2184 int pipe = intel_crtc->pipe;
5eddb70b 2185 u32 reg, temp, i;
8db9d77b 2186
e1a44743
AJ		 2187 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2188 for train result */
5eddb70b
CW		 2189 reg = FDI_RX_IMR(pipe);
2190 temp = I915_READ(reg);
e1a44743
AJ		 2191 temp &= ~FDI_RX_SYMBOL_LOCK;
2192 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2193 I915_WRITE(reg, temp);
2194
2195 POSTING_READ(reg);
e1a44743
AJ		 2196 udelay(150);
2197
8db9d77b 2198 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2199 reg = FDI_TX_CTL(pipe);
2200 temp = I915_READ(reg);
77ffb597
AJ		 2201 temp &= ~(7 << 19);
2202 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2203 temp &= ~FDI_LINK_TRAIN_NONE;
2204 temp |= FDI_LINK_TRAIN_PATTERN_1;
2205 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2206 /* SNB-B */
2207 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2208 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2209
5eddb70b
CW		 2210 reg = FDI_RX_CTL(pipe);
2211 temp = I915_READ(reg);
8db9d77b
ZW		 2212 if (HAS_PCH_CPT(dev)) {
2213 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2214 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2215 } else {
2216 temp &= ~FDI_LINK_TRAIN_NONE;
2217 temp |= FDI_LINK_TRAIN_PATTERN_1;
2218 }
5eddb70b
CW		 2219 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2220
2221 POSTING_READ(reg);
8db9d77b
ZW		 2222 udelay(150);
2223
8db9d77b 2224 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2225 reg = FDI_TX_CTL(pipe);
2226 temp = I915_READ(reg);
8db9d77b
ZW		 2227 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2228 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2229 I915_WRITE(reg, temp);
2230
2231 POSTING_READ(reg);
8db9d77b
ZW		 2232 udelay(500);
2233
5eddb70b
CW		 2234 reg = FDI_RX_IIR(pipe);
2235 temp = I915_READ(reg);
8db9d77b
ZW		 2236 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2237
2238 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2239 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2240 DRM_DEBUG_KMS("FDI train 1 done.\n");
2241 break;
2242 }
2243 }
2244 if (i == 4)
5eddb70b 2245 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2246
2247 /* Train 2 */
5eddb70b
CW		 2248 reg = FDI_TX_CTL(pipe);
2249 temp = I915_READ(reg);
8db9d77b
ZW		 2250 temp &= ~FDI_LINK_TRAIN_NONE;
2251 temp |= FDI_LINK_TRAIN_PATTERN_2;
2252 if (IS_GEN6(dev)) {
2253 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2254 /* SNB-B */
2255 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2256 }
5eddb70b 2257 I915_WRITE(reg, temp);
8db9d77b 2258
5eddb70b
CW		 2259 reg = FDI_RX_CTL(pipe);
2260 temp = I915_READ(reg);
8db9d77b
ZW		 2261 if (HAS_PCH_CPT(dev)) {
2262 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2263 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2264 } else {
2265 temp &= ~FDI_LINK_TRAIN_NONE;
2266 temp |= FDI_LINK_TRAIN_PATTERN_2;
2267 }
5eddb70b
CW		 2268 I915_WRITE(reg, temp);
2269
2270 POSTING_READ(reg);
8db9d77b
ZW		 2271 udelay(150);
2272
2273 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2274 reg = FDI_TX_CTL(pipe);
2275 temp = I915_READ(reg);
8db9d77b
ZW		 2276 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2277 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2278 I915_WRITE(reg, temp);
2279
2280 POSTING_READ(reg);
8db9d77b
ZW		 2281 udelay(500);
2282
5eddb70b
CW		 2283 reg = FDI_RX_IIR(pipe);
2284 temp = I915_READ(reg);
8db9d77b
ZW		 2285 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2286
2287 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2288 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2289 DRM_DEBUG_KMS("FDI train 2 done.\n");
2290 break;
2291 }
2292 }
2293 if (i == 4)
5eddb70b 2294 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2295
2296 DRM_DEBUG_KMS("FDI train done.\n");
2297}
2298
0e23b99d 2299static void ironlake_fdi_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2300{
2301 struct drm_device *dev = crtc->dev;
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2304 int pipe = intel_crtc->pipe;
5eddb70b 2305 u32 reg, temp;
79e53945 2306
c64e311e 2307 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2308 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2309 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2310
c98e9dcf 2311 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2312 reg = FDI_RX_CTL(pipe);
2313 temp = I915_READ(reg);
2314 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2315 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2316 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2317 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2318
2319 POSTING_READ(reg);
c98e9dcf
JB		 2320 udelay(200);
2321
2322 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2323 temp = I915_READ(reg);
2324 I915_WRITE(reg, temp | FDI_PCDCLK);
2325
2326 POSTING_READ(reg);
c98e9dcf
JB		 2327 udelay(200);
2328
2329 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2330 reg = FDI_TX_CTL(pipe);
2331 temp = I915_READ(reg);
c98e9dcf 2332 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2333 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2334
2335 POSTING_READ(reg);
c98e9dcf 2336 udelay(100);
6be4a607 2337 }
0e23b99d
JB		 2338}
2339
0fc932b8
JB		 2340static void ironlake_fdi_disable(struct drm_crtc *crtc)
2341{
2342 struct drm_device *dev = crtc->dev;
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2345 int pipe = intel_crtc->pipe;
2346 u32 reg, temp;
2347
2348 /* disable CPU FDI tx and PCH FDI rx */
2349 reg = FDI_TX_CTL(pipe);
2350 temp = I915_READ(reg);
2351 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2352 POSTING_READ(reg);
2353
2354 reg = FDI_RX_CTL(pipe);
2355 temp = I915_READ(reg);
2356 temp &= ~(0x7 << 16);
2357 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2358 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2359
2360 POSTING_READ(reg);
2361 udelay(100);
2362
2363 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2364 if (HAS_PCH_IBX(dev)) {
2365 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2366 I915_WRITE(FDI_RX_CHICKEN(pipe),
2367 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18
JB		 2368 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2369 }
0fc932b8
JB		 2370
2371 /* still set train pattern 1 */
2372 reg = FDI_TX_CTL(pipe);
2373 temp = I915_READ(reg);
2374 temp &= ~FDI_LINK_TRAIN_NONE;
2375 temp |= FDI_LINK_TRAIN_PATTERN_1;
2376 I915_WRITE(reg, temp);
2377
2378 reg = FDI_RX_CTL(pipe);
2379 temp = I915_READ(reg);
2380 if (HAS_PCH_CPT(dev)) {
2381 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2382 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2383 } else {
2384 temp &= ~FDI_LINK_TRAIN_NONE;
2385 temp |= FDI_LINK_TRAIN_PATTERN_1;
2386 }
2387 /* BPC in FDI rx is consistent with that in PIPECONF */
2388 temp &= ~(0x07 << 16);
2389 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2390 I915_WRITE(reg, temp);
2391
2392 POSTING_READ(reg);
2393 udelay(100);
2394}
2395
6b383a7f
CW		 2396/*
2397 * When we disable a pipe, we need to clear any pending scanline wait events
2398 * to avoid hanging the ring, which we assume we are waiting on.
2399 */
2400static void intel_clear_scanline_wait(struct drm_device *dev)
2401{
2402 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2403 struct intel_ring_buffer *ring;
6b383a7f
CW		 2404 u32 tmp;
2405
2406 if (IS_GEN2(dev))
2407 /* Can't break the hang on i8xx */
2408 return;
2409
1ec14ad3 2410 ring = LP_RING(dev_priv);
8168bd48
CW		 2411 tmp = I915_READ_CTL(ring);
2412 if (tmp & RING_WAIT)
2413 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2414}
2415
e6c3a2a6
CW		 2416static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2417{
05394f39 2418 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2419 struct drm_i915_private *dev_priv;
2420
2421 if (crtc->fb == NULL)
2422 return;
2423
05394f39 2424 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2425 dev_priv = crtc->dev->dev_private;
2426 wait_event(dev_priv->pending_flip_queue,
05394f39 2427 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2428}
2429
040484af
JB		 2430static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2431{
2432 struct drm_device *dev = crtc->dev;
2433 struct drm_mode_config *mode_config = &dev->mode_config;
2434 struct intel_encoder *encoder;
2435
2436 /*
2437 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2438 * must be driven by its own crtc; no sharing is possible.
2439 */
2440 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2441 if (encoder->base.crtc != crtc)
2442 continue;
2443
2444 switch (encoder->type) {
2445 case INTEL_OUTPUT_EDP:
2446 if (!intel_encoder_is_pch_edp(&encoder->base))
2447 return false;
2448 continue;
2449 }
2450 }
2451
2452 return true;
2453}
2454
f67a559d
JB		 2455/*
2456 * Enable PCH resources required for PCH ports:
2457 * - PCH PLLs
2458 * - FDI training & RX/TX
2459 * - update transcoder timings
2460 * - DP transcoding bits
2461 * - transcoder
2462 */
2463static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2464{
2465 struct drm_device *dev = crtc->dev;
2466 struct drm_i915_private *dev_priv = dev->dev_private;
2467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468 int pipe = intel_crtc->pipe;
5eddb70b 2469 u32 reg, temp;
2c07245f 2470
c98e9dcf
JB		 2471 /* For PCH output, training FDI link */
2472 if (IS_GEN6(dev))
2473 gen6_fdi_link_train(crtc);
2474 else
2475 ironlake_fdi_link_train(crtc);
2c07245f 2476
92f2584a 2477 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2478
c98e9dcf
JB		 2479 if (HAS_PCH_CPT(dev)) {
2480 /* Be sure PCH DPLL SEL is set */
2481 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2482 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2483 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2484 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2485 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2486 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2487 }
5eddb70b 2488
d9b6cb56
JB		 2489 /* set transcoder timing, panel must allow it */
2490 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2491 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2492 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2493 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2494
5eddb70b
CW		 2495 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2496 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2497 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2498
5e84e1a4
ZW		 2499 intel_fdi_normal_train(crtc);
2500
c98e9dcf
JB		 2501 /* For PCH DP, enable TRANS_DP_CTL */
2502 if (HAS_PCH_CPT(dev) &&
2503 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5eddb70b
CW		 2504 reg = TRANS_DP_CTL(pipe);
2505 temp = I915_READ(reg);
2506 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2507 TRANS_DP_SYNC_MASK |
2508 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2509 temp |= (TRANS_DP_OUTPUT_ENABLE |
2510 TRANS_DP_ENH_FRAMING);
220cad3c 2511 temp |= TRANS_DP_8BPC;
c98e9dcf
JB		 2512
2513 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2514 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2515 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2516 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2517
2518 switch (intel_trans_dp_port_sel(crtc)) {
2519 case PCH_DP_B:
5eddb70b 2520 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2521 break;
2522 case PCH_DP_C:
5eddb70b 2523 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2524 break;
2525 case PCH_DP_D:
5eddb70b 2526 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2527 break;
2528 default:
2529 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2530 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2531 break;
32f9d658 2532 }
2c07245f 2533
5eddb70b 2534 I915_WRITE(reg, temp);
6be4a607 2535 }
b52eb4dc 2536
040484af 2537 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2538}
2539
2540static void ironlake_crtc_enable(struct drm_crtc *crtc)
2541{
2542 struct drm_device *dev = crtc->dev;
2543 struct drm_i915_private *dev_priv = dev->dev_private;
2544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2545 int pipe = intel_crtc->pipe;
2546 int plane = intel_crtc->plane;
2547 u32 temp;
2548 bool is_pch_port;
2549
2550 if (intel_crtc->active)
2551 return;
2552
2553 intel_crtc->active = true;
2554 intel_update_watermarks(dev);
2555
2556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2557 temp = I915_READ(PCH_LVDS);
2558 if ((temp & LVDS_PORT_EN) == 0)
2559 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2560 }
2561
2562 is_pch_port = intel_crtc_driving_pch(crtc);
2563
2564 if (is_pch_port)
2565 ironlake_fdi_enable(crtc);
2566 else
2567 ironlake_fdi_disable(crtc);
2568
2569 /* Enable panel fitting for LVDS */
2570 if (dev_priv->pch_pf_size &&
2571 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2572 /* Force use of hard-coded filter coefficients
2573 * as some pre-programmed values are broken,
2574 * e.g. x201.
2575 */
9db4a9c7
JB		 2576 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2577 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2578 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2579 }
2580
2581 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2582 intel_enable_plane(dev_priv, plane, pipe);
2583
2584 if (is_pch_port)
2585 ironlake_pch_enable(crtc);
c98e9dcf 2586
6be4a607 2587 intel_crtc_load_lut(crtc);
d1ebd816
BW		 2588
2589 mutex_lock(&dev->struct_mutex);
bed4a673 2590 intel_update_fbc(dev);
d1ebd816
BW		 2591 mutex_unlock(&dev->struct_mutex);
2592
6b383a7f 2593 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2594}
2595
2596static void ironlake_crtc_disable(struct drm_crtc *crtc)
2597{
2598 struct drm_device *dev = crtc->dev;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 int pipe = intel_crtc->pipe;
2602 int plane = intel_crtc->plane;
5eddb70b 2603 u32 reg, temp;
b52eb4dc 2604
f7abfe8b
CW		 2605 if (!intel_crtc->active)
2606 return;
2607
e6c3a2a6 2608 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2609 drm_vblank_off(dev, pipe);
6b383a7f 2610 intel_crtc_update_cursor(crtc, false);
5eddb70b 2611
b24e7179 2612 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2613
6be4a607
JB		 2614 if (dev_priv->cfb_plane == plane &&
2615 dev_priv->display.disable_fbc)
2616 dev_priv->display.disable_fbc(dev);
2c07245f 2617
b24e7179 2618 intel_disable_pipe(dev_priv, pipe);
32f9d658 2619
6be4a607 2620 /* Disable PF */
9db4a9c7
JB		 2621 I915_WRITE(PF_CTL(pipe), 0);
2622 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2623
0fc932b8 2624 ironlake_fdi_disable(crtc);
2c07245f 2625
47a05eca
JB		 2626 /* This is a horrible layering violation; we should be doing this in
2627 * the connector/encoder ->prepare instead, but we don't always have
2628 * enough information there about the config to know whether it will
2629 * actually be necessary or just cause undesired flicker.
2630 */
2631 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2632
040484af 2633 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2634
6be4a607
JB		 2635 if (HAS_PCH_CPT(dev)) {
2636 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2637 reg = TRANS_DP_CTL(pipe);
2638 temp = I915_READ(reg);
2639 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2640 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2641 I915_WRITE(reg, temp);
6be4a607
JB		 2642
2643 /* disable DPLL_SEL */
2644 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2645 switch (pipe) {
2646 case 0:
2647 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2648 break;
2649 case 1:
6be4a607 2650 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2651 break;
2652 case 2:
2653 /* FIXME: manage transcoder PLLs? */
2654 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2655 break;
2656 default:
2657 BUG(); /* wtf */
2658 }
6be4a607 2659 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2660 }
e3421a18 2661
6be4a607 2662 /* disable PCH DPLL */
92f2584a 2663 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2664
6be4a607 2665 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2666 reg = FDI_RX_CTL(pipe);
2667 temp = I915_READ(reg);
2668 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2669
6be4a607 2670 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2671 reg = FDI_TX_CTL(pipe);
2672 temp = I915_READ(reg);
2673 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2674
2675 POSTING_READ(reg);
6be4a607 2676 udelay(100);
8db9d77b 2677
5eddb70b
CW		 2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2681
6be4a607 2682 /* Wait for the clocks to turn off. */
5eddb70b 2683 POSTING_READ(reg);
6be4a607 2684 udelay(100);
6b383a7f 2685
f7abfe8b 2686 intel_crtc->active = false;
6b383a7f 2687 intel_update_watermarks(dev);
d1ebd816
BW		 2688
2689 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 2690 intel_update_fbc(dev);
2691 intel_clear_scanline_wait(dev);
d1ebd816 2692 mutex_unlock(&dev->struct_mutex);
6be4a607 2693}
1b3c7a47 2694
6be4a607
JB		 2695static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2696{
2697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2698 int pipe = intel_crtc->pipe;
2699 int plane = intel_crtc->plane;
8db9d77b 2700
6be4a607
JB		 2701 /* XXX: When our outputs are all unaware of DPMS modes other than off
2702 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2703 */
2704 switch (mode) {
2705 case DRM_MODE_DPMS_ON:
2706 case DRM_MODE_DPMS_STANDBY:
2707 case DRM_MODE_DPMS_SUSPEND:
2708 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2709 ironlake_crtc_enable(crtc);
2710 break;
1b3c7a47 2711
6be4a607
JB		 2712 case DRM_MODE_DPMS_OFF:
2713 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2714 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2715 break;
2716 }
2717}
2718
02e792fb
DV		 2719static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2720{
02e792fb 2721 if (!enable && intel_crtc->overlay) {
23f09ce3 2722 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2723 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2724
23f09ce3 2725 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2726 dev_priv->mm.interruptible = false;
2727 (void) intel_overlay_switch_off(intel_crtc->overlay);
2728 dev_priv->mm.interruptible = true;
23f09ce3 2729 mutex_unlock(&dev->struct_mutex);
02e792fb 2730 }
02e792fb 2731
5dcdbcb0
CW		 2732 /* Let userspace switch the overlay on again. In most cases userspace
2733 * has to recompute where to put it anyway.
2734 */
02e792fb
DV		 2735}
2736
0b8765c6 2737static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2738{
2739 struct drm_device *dev = crtc->dev;
79e53945
JB		 2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2742 int pipe = intel_crtc->pipe;
80824003 2743 int plane = intel_crtc->plane;
79e53945 2744
f7abfe8b
CW		 2745 if (intel_crtc->active)
2746 return;
2747
2748 intel_crtc->active = true;
6b383a7f
CW		 2749 intel_update_watermarks(dev);
2750
63d7bbe9 2751 intel_enable_pll(dev_priv, pipe);
040484af 2752 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2753 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2754
0b8765c6 2755 intel_crtc_load_lut(crtc);
bed4a673 2756 intel_update_fbc(dev);
79e53945 2757
0b8765c6
JB		 2758 /* Give the overlay scaler a chance to enable if it's on this pipe */
2759 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2760 intel_crtc_update_cursor(crtc, true);
0b8765c6 2761}
79e53945 2762
0b8765c6
JB		 2763static void i9xx_crtc_disable(struct drm_crtc *crtc)
2764{
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768 int pipe = intel_crtc->pipe;
2769 int plane = intel_crtc->plane;
b690e96c 2770
f7abfe8b
CW		 2771 if (!intel_crtc->active)
2772 return;
2773
0b8765c6 2774 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2775 intel_crtc_wait_for_pending_flips(crtc);
2776 drm_vblank_off(dev, pipe);
0b8765c6 2777 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2778 intel_crtc_update_cursor(crtc, false);
0b8765c6
JB		 2779
2780 if (dev_priv->cfb_plane == plane &&
2781 dev_priv->display.disable_fbc)
2782 dev_priv->display.disable_fbc(dev);
79e53945 2783
b24e7179 2784 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2785 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2786 intel_disable_pll(dev_priv, pipe);
0b8765c6 2787
f7abfe8b 2788 intel_crtc->active = false;
6b383a7f
CW		 2789 intel_update_fbc(dev);
2790 intel_update_watermarks(dev);
2791 intel_clear_scanline_wait(dev);
0b8765c6
JB		 2792}
2793
2794static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2795{
2796 /* XXX: When our outputs are all unaware of DPMS modes other than off
2797 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2798 */
2799 switch (mode) {
2800 case DRM_MODE_DPMS_ON:
2801 case DRM_MODE_DPMS_STANDBY:
2802 case DRM_MODE_DPMS_SUSPEND:
2803 i9xx_crtc_enable(crtc);
2804 break;
2805 case DRM_MODE_DPMS_OFF:
2806 i9xx_crtc_disable(crtc);
79e53945
JB		 2807 break;
2808 }
2c07245f
ZW		 2809}
2810
2811/**
2812 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 2813 */
2814static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2815{
2816 struct drm_device *dev = crtc->dev;
e70236a8 2817 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 2818 struct drm_i915_master_private *master_priv;
2819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2820 int pipe = intel_crtc->pipe;
2821 bool enabled;
2822
032d2a0d
CW		 2823 if (intel_crtc->dpms_mode == mode)
2824 return;
2825
65655d4a 2826 intel_crtc->dpms_mode = mode;
debcaddc 2827
e70236a8 2828 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 2829
2830 if (!dev->primary->master)
2831 return;
2832
2833 master_priv = dev->primary->master->driver_priv;
2834 if (!master_priv->sarea_priv)
2835 return;
2836
2837 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2838
2839 switch (pipe) {
2840 case 0:
2841 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2842 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2843 break;
2844 case 1:
2845 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2846 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2847 break;
2848 default:
9db4a9c7 2849 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 2850 break;
2851 }
79e53945
JB		 2852}
2853
cdd59983
CW		 2854static void intel_crtc_disable(struct drm_crtc *crtc)
2855{
2856 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2857 struct drm_device *dev = crtc->dev;
2858
2859 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2860
2861 if (crtc->fb) {
2862 mutex_lock(&dev->struct_mutex);
2863 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2864 mutex_unlock(&dev->struct_mutex);
2865 }
2866}
2867
7e7d76c3
JB		 2868/* Prepare for a mode set.
2869 *
2870 * Note we could be a lot smarter here. We need to figure out which outputs
2871 * will be enabled, which disabled (in short, how the config will changes)
2872 * and perform the minimum necessary steps to accomplish that, e.g. updating
2873 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2874 * panel fitting is in the proper state, etc.
2875 */
2876static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 2877{
7e7d76c3 2878 i9xx_crtc_disable(crtc);
79e53945
JB		 2879}
2880
7e7d76c3 2881static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 2882{
7e7d76c3 2883 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 2884}
2885
2886static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2887{
7e7d76c3 2888 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 2889}
2890
2891static void ironlake_crtc_commit(struct drm_crtc *crtc)
2892{
7e7d76c3 2893 ironlake_crtc_enable(crtc);
79e53945
JB		 2894}
2895
2896void intel_encoder_prepare (struct drm_encoder *encoder)
2897{
2898 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2899 /* lvds has its own version of prepare see intel_lvds_prepare */
2900 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2901}
2902
2903void intel_encoder_commit (struct drm_encoder *encoder)
2904{
2905 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2906 /* lvds has its own version of commit see intel_lvds_commit */
2907 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2908}
2909
ea5b213a
CW		 2910void intel_encoder_destroy(struct drm_encoder *encoder)
2911{
4ef69c7a 2912 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 2913
ea5b213a
CW		 2914 drm_encoder_cleanup(encoder);
2915 kfree(intel_encoder);
2916}
2917
79e53945
JB		 2918static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2919 struct drm_display_mode *mode,
2920 struct drm_display_mode *adjusted_mode)
2921{
2c07245f 2922 struct drm_device *dev = crtc->dev;
89749350 2923
bad720ff 2924 if (HAS_PCH_SPLIT(dev)) {
2c07245f 2925 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 2926 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2927 return false;
2c07245f 2928 }
89749350
CW		 2929
2930 /* XXX some encoders set the crtcinfo, others don't.
2931 * Obviously we need some form of conflict resolution here...
2932 */
2933 if (adjusted_mode->crtc_htotal == 0)
2934 drm_mode_set_crtcinfo(adjusted_mode, 0);
2935
79e53945
JB		 2936 return true;
2937}
2938
e70236a8
JB		 2939static int i945_get_display_clock_speed(struct drm_device *dev)
2940{
2941 return 400000;
2942}
79e53945 2943
e70236a8 2944static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 2945{
e70236a8
JB		 2946 return 333000;
2947}
79e53945 2948
e70236a8
JB		 2949static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2950{
2951 return 200000;
2952}
79e53945 2953
e70236a8
JB		 2954static int i915gm_get_display_clock_speed(struct drm_device *dev)
2955{
2956 u16 gcfgc = 0;
79e53945 2957
e70236a8
JB		 2958 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2959
2960 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2961 return 133000;
2962 else {
2963 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2964 case GC_DISPLAY_CLOCK_333_MHZ:
2965 return 333000;
2966 default:
2967 case GC_DISPLAY_CLOCK_190_200_MHZ:
2968 return 190000;
79e53945 2969 }
e70236a8
JB		 2970 }
2971}
2972
2973static int i865_get_display_clock_speed(struct drm_device *dev)
2974{
2975 return 266000;
2976}
2977
2978static int i855_get_display_clock_speed(struct drm_device *dev)
2979{
2980 u16 hpllcc = 0;
2981 /* Assume that the hardware is in the high speed state. This
2982 * should be the default.
2983 */
2984 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2985 case GC_CLOCK_133_200:
2986 case GC_CLOCK_100_200:
2987 return 200000;
2988 case GC_CLOCK_166_250:
2989 return 250000;
2990 case GC_CLOCK_100_133:
79e53945 2991 return 133000;
e70236a8 2992 }
79e53945 2993
e70236a8
JB		 2994 /* Shouldn't happen */
2995 return 0;
2996}
79e53945 2997
e70236a8
JB		 2998static int i830_get_display_clock_speed(struct drm_device *dev)
2999{
3000 return 133000;
79e53945
JB		 3001}
3002
2c07245f
ZW		 3003struct fdi_m_n {
3004 u32 tu;
3005 u32 gmch_m;
3006 u32 gmch_n;
3007 u32 link_m;
3008 u32 link_n;
3009};
3010
3011static void
3012fdi_reduce_ratio(u32 *num, u32 *den)
3013{
3014 while (*num > 0xffffff || *den > 0xffffff) {
3015 *num >>= 1;
3016 *den >>= 1;
3017 }
3018}
3019
2c07245f 3020static void
f2b115e6
AJ		 3021ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3022 int link_clock, struct fdi_m_n *m_n)
2c07245f 3023{
2c07245f
ZW		 3024 m_n->tu = 64; /* default size */
3025
22ed1113
CW		 3026 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3027 m_n->gmch_m = bits_per_pixel * pixel_clock;
3028 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3029 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3030
22ed1113
CW		 3031 m_n->link_m = pixel_clock;
3032 m_n->link_n = link_clock;
2c07245f
ZW		 3033 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3034}
3035
3036
7662c8bd
SL		 3037struct intel_watermark_params {
3038 unsigned long fifo_size;
3039 unsigned long max_wm;
3040 unsigned long default_wm;
3041 unsigned long guard_size;
3042 unsigned long cacheline_size;
3043};
3044
f2b115e6 3045/* Pineview has different values for various configs */
d210246a 3046static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3047 PINEVIEW_DISPLAY_FIFO,
3048 PINEVIEW_MAX_WM,
3049 PINEVIEW_DFT_WM,
3050 PINEVIEW_GUARD_WM,
3051 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3052};
d210246a 3053static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3054 PINEVIEW_DISPLAY_FIFO,
3055 PINEVIEW_MAX_WM,
3056 PINEVIEW_DFT_HPLLOFF_WM,
3057 PINEVIEW_GUARD_WM,
3058 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3059};
d210246a 3060static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3061 PINEVIEW_CURSOR_FIFO,
3062 PINEVIEW_CURSOR_MAX_WM,
3063 PINEVIEW_CURSOR_DFT_WM,
3064 PINEVIEW_CURSOR_GUARD_WM,
3065 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3066};
d210246a 3067static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3068 PINEVIEW_CURSOR_FIFO,
3069 PINEVIEW_CURSOR_MAX_WM,
3070 PINEVIEW_CURSOR_DFT_WM,
3071 PINEVIEW_CURSOR_GUARD_WM,
3072 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3073};
d210246a 3074static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3075 G4X_FIFO_SIZE,
3076 G4X_MAX_WM,
3077 G4X_MAX_WM,
3078 2,
3079 G4X_FIFO_LINE_SIZE,
3080};
d210246a 3081static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3082 I965_CURSOR_FIFO,
3083 I965_CURSOR_MAX_WM,
3084 I965_CURSOR_DFT_WM,
3085 2,
3086 G4X_FIFO_LINE_SIZE,
3087};
d210246a 3088static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3089 I965_CURSOR_FIFO,
3090 I965_CURSOR_MAX_WM,
3091 I965_CURSOR_DFT_WM,
3092 2,
3093 I915_FIFO_LINE_SIZE,
3094};
d210246a 3095static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3096 I945_FIFO_SIZE,
7662c8bd
SL		 3097 I915_MAX_WM,
3098 1,
dff33cfc
JB		 3099 2,
3100 I915_FIFO_LINE_SIZE
7662c8bd 3101};
d210246a 3102static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3103 I915_FIFO_SIZE,
7662c8bd
SL		 3104 I915_MAX_WM,
3105 1,
dff33cfc 3106 2,
7662c8bd
SL		 3107 I915_FIFO_LINE_SIZE
3108};
d210246a 3109static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3110 I855GM_FIFO_SIZE,
3111 I915_MAX_WM,
3112 1,
dff33cfc 3113 2,
7662c8bd
SL		 3114 I830_FIFO_LINE_SIZE
3115};
d210246a 3116static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3117 I830_FIFO_SIZE,
3118 I915_MAX_WM,
3119 1,
dff33cfc 3120 2,
7662c8bd
SL		 3121 I830_FIFO_LINE_SIZE
3122};
3123
d210246a 3124static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3125 ILK_DISPLAY_FIFO,
3126 ILK_DISPLAY_MAXWM,
3127 ILK_DISPLAY_DFTWM,
3128 2,
3129 ILK_FIFO_LINE_SIZE
3130};
d210246a 3131static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3132 ILK_CURSOR_FIFO,
3133 ILK_CURSOR_MAXWM,
3134 ILK_CURSOR_DFTWM,
3135 2,
3136 ILK_FIFO_LINE_SIZE
3137};
d210246a 3138static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3139 ILK_DISPLAY_SR_FIFO,
3140 ILK_DISPLAY_MAX_SRWM,
3141 ILK_DISPLAY_DFT_SRWM,
3142 2,
3143 ILK_FIFO_LINE_SIZE
3144};
d210246a 3145static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3146 ILK_CURSOR_SR_FIFO,
3147 ILK_CURSOR_MAX_SRWM,
3148 ILK_CURSOR_DFT_SRWM,
3149 2,
3150 ILK_FIFO_LINE_SIZE
3151};
3152
d210246a 3153static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3154 SNB_DISPLAY_FIFO,
3155 SNB_DISPLAY_MAXWM,
3156 SNB_DISPLAY_DFTWM,
3157 2,
3158 SNB_FIFO_LINE_SIZE
3159};
d210246a 3160static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3161 SNB_CURSOR_FIFO,
3162 SNB_CURSOR_MAXWM,
3163 SNB_CURSOR_DFTWM,
3164 2,
3165 SNB_FIFO_LINE_SIZE
3166};
d210246a 3167static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3168 SNB_DISPLAY_SR_FIFO,
3169 SNB_DISPLAY_MAX_SRWM,
3170 SNB_DISPLAY_DFT_SRWM,
3171 2,
3172 SNB_FIFO_LINE_SIZE
3173};
d210246a 3174static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3175 SNB_CURSOR_SR_FIFO,
3176 SNB_CURSOR_MAX_SRWM,
3177 SNB_CURSOR_DFT_SRWM,
3178 2,
3179 SNB_FIFO_LINE_SIZE
3180};
3181
3182
dff33cfc
JB		 3183/**
3184 * intel_calculate_wm - calculate watermark level
3185 * @clock_in_khz: pixel clock
3186 * @wm: chip FIFO params
3187 * @pixel_size: display pixel size
3188 * @latency_ns: memory latency for the platform
3189 *
3190 * Calculate the watermark level (the level at which the display plane will
3191 * start fetching from memory again). Each chip has a different display
3192 * FIFO size and allocation, so the caller needs to figure that out and pass
3193 * in the correct intel_watermark_params structure.
3194 *
3195 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3196 * on the pixel size. When it reaches the watermark level, it'll start
3197 * fetching FIFO line sized based chunks from memory until the FIFO fills
3198 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3199 * will occur, and a display engine hang could result.
3200 */
7662c8bd 3201static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3202 const struct intel_watermark_params *wm,
3203 int fifo_size,
7662c8bd
SL		 3204 int pixel_size,
3205 unsigned long latency_ns)
3206{
390c4dd4 3207 long entries_required, wm_size;
dff33cfc 3208
d660467c
JB		 3209 /*
3210 * Note: we need to make sure we don't overflow for various clock &
3211 * latency values.
3212 * clocks go from a few thousand to several hundred thousand.
3213 * latency is usually a few thousand
3214 */
3215 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3216 1000;
8de9b311 3217 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3218
28c97730 3219 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
dff33cfc 3220
d210246a 3221 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3222
28c97730 3223 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
7662c8bd 3224
390c4dd4
JB		 3225 /* Don't promote wm_size to unsigned... */
3226 if (wm_size > (long)wm->max_wm)
7662c8bd 3227 wm_size = wm->max_wm;
c3add4b6 3228 if (wm_size <= 0)
7662c8bd
SL		 3229 wm_size = wm->default_wm;
3230 return wm_size;
3231}
3232
3233struct cxsr_latency {
3234 int is_desktop;
95534263 3235 int is_ddr3;
7662c8bd
SL		 3236 unsigned long fsb_freq;
3237 unsigned long mem_freq;
3238 unsigned long display_sr;
3239 unsigned long display_hpll_disable;
3240 unsigned long cursor_sr;
3241 unsigned long cursor_hpll_disable;
3242};
3243
403c89ff 3244static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3245 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3246 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3247 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3248 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3249 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3250
3251 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3252 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3253 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3254 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3255 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3256
3257 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3258 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3259 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3260 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3261 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3262
3263 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3264 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3265 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3266 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3267 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3268
3269 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3270 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3271 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3272 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3273 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3274
3275 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3276 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3277 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3278 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3279 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3280};
3281
403c89ff
CW		 3282static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3283 int is_ddr3,
3284 int fsb,
3285 int mem)
7662c8bd 3286{
403c89ff 3287 const struct cxsr_latency *latency;
7662c8bd 3288 int i;
7662c8bd
SL		 3289
3290 if (fsb == 0 || mem == 0)
3291 return NULL;
3292
3293 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3294 latency = &cxsr_latency_table[i];
3295 if (is_desktop == latency->is_desktop &&
95534263 3296 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3297 fsb == latency->fsb_freq && mem == latency->mem_freq)
3298 return latency;
7662c8bd 3299 }
decbbcda 3300
28c97730 3301 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3302
3303 return NULL;
7662c8bd
SL		 3304}
3305
f2b115e6 3306static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3307{
3308 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3309
3310 /* deactivate cxsr */
3e33d94d 3311 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3312}
3313
bcc24fb4
JB		 3314/*
3315 * Latency for FIFO fetches is dependent on several factors:
3316 * - memory configuration (speed, channels)
3317 * - chipset
3318 * - current MCH state
3319 * It can be fairly high in some situations, so here we assume a fairly
3320 * pessimal value. It's a tradeoff between extra memory fetches (if we
3321 * set this value too high, the FIFO will fetch frequently to stay full)
3322 * and power consumption (set it too low to save power and we might see
3323 * FIFO underruns and display "flicker").
3324 *
3325 * A value of 5us seems to be a good balance; safe for very low end
3326 * platforms but not overly aggressive on lower latency configs.
3327 */
69e302a9 3328static const int latency_ns = 5000;
7662c8bd 3329
e70236a8 3330static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3331{
3332 struct drm_i915_private *dev_priv = dev->dev_private;
3333 uint32_t dsparb = I915_READ(DSPARB);
3334 int size;
3335
8de9b311
CW		 3336 size = dsparb & 0x7f;
3337 if (plane)
3338 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3339
28c97730 3340 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3341 plane ? "B" : "A", size);
dff33cfc
JB		 3342
3343 return size;
3344}
7662c8bd 3345
e70236a8
JB		 3346static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3347{
3348 struct drm_i915_private *dev_priv = dev->dev_private;
3349 uint32_t dsparb = I915_READ(DSPARB);
3350 int size;
3351
8de9b311
CW		 3352 size = dsparb & 0x1ff;
3353 if (plane)
3354 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3355 size >>= 1; /* Convert to cachelines */
dff33cfc 3356
28c97730 3357 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3358 plane ? "B" : "A", size);
dff33cfc
JB		 3359
3360 return size;
3361}
7662c8bd 3362
e70236a8
JB		 3363static int i845_get_fifo_size(struct drm_device *dev, int plane)
3364{
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 uint32_t dsparb = I915_READ(DSPARB);
3367 int size;
3368
3369 size = dsparb & 0x7f;
3370 size >>= 2; /* Convert to cachelines */
3371
28c97730 3372 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3373 plane ? "B" : "A",
3374 size);
e70236a8
JB		 3375
3376 return size;
3377}
3378
3379static int i830_get_fifo_size(struct drm_device *dev, int plane)
3380{
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 uint32_t dsparb = I915_READ(DSPARB);
3383 int size;
3384
3385 size = dsparb & 0x7f;
3386 size >>= 1; /* Convert to cachelines */
3387
28c97730 3388 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3389 plane ? "B" : "A", size);
e70236a8
JB		 3390
3391 return size;
3392}
3393
d210246a
CW		 3394static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3395{
3396 struct drm_crtc *crtc, *enabled = NULL;
3397
3398 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3399 if (crtc->enabled && crtc->fb) {
3400 if (enabled)
3401 return NULL;
3402 enabled = crtc;
3403 }
3404 }
3405
3406 return enabled;
3407}
3408
3409static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3410{
3411 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3412 struct drm_crtc *crtc;
403c89ff 3413 const struct cxsr_latency *latency;
d4294342
ZY		 3414 u32 reg;
3415 unsigned long wm;
d4294342 3416
403c89ff 3417 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3418 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3419 if (!latency) {
3420 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3421 pineview_disable_cxsr(dev);
3422 return;
3423 }
3424
d210246a
CW		 3425 crtc = single_enabled_crtc(dev);
3426 if (crtc) {
3427 int clock = crtc->mode.clock;
3428 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3429
3430 /* Display SR */
d210246a
CW		 3431 wm = intel_calculate_wm(clock, &pineview_display_wm,
3432 pineview_display_wm.fifo_size,
d4294342
ZY		 3433 pixel_size, latency->display_sr);
3434 reg = I915_READ(DSPFW1);
3435 reg &= ~DSPFW_SR_MASK;
3436 reg |= wm << DSPFW_SR_SHIFT;
3437 I915_WRITE(DSPFW1, reg);
3438 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3439
3440 /* cursor SR */
d210246a
CW		 3441 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3442 pineview_display_wm.fifo_size,
d4294342
ZY		 3443 pixel_size, latency->cursor_sr);
3444 reg = I915_READ(DSPFW3);
3445 reg &= ~DSPFW_CURSOR_SR_MASK;
3446 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3447 I915_WRITE(DSPFW3, reg);
3448
3449 /* Display HPLL off SR */
d210246a
CW		 3450 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3451 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3452 pixel_size, latency->display_hpll_disable);
3453 reg = I915_READ(DSPFW3);
3454 reg &= ~DSPFW_HPLL_SR_MASK;
3455 reg |= wm & DSPFW_HPLL_SR_MASK;
3456 I915_WRITE(DSPFW3, reg);
3457
3458 /* cursor HPLL off SR */
d210246a
CW		 3459 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3460 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3461 pixel_size, latency->cursor_hpll_disable);
3462 reg = I915_READ(DSPFW3);
3463 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3464 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3465 I915_WRITE(DSPFW3, reg);
3466 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3467
3468 /* activate cxsr */
3e33d94d
CW		 3469 I915_WRITE(DSPFW3,
3470 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3471 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3472 } else {
3473 pineview_disable_cxsr(dev);
3474 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3475 }
3476}
3477
417ae147
CW		 3478static bool g4x_compute_wm0(struct drm_device *dev,
3479 int plane,
3480 const struct intel_watermark_params *display,
3481 int display_latency_ns,
3482 const struct intel_watermark_params *cursor,
3483 int cursor_latency_ns,
3484 int *plane_wm,
3485 int *cursor_wm)
3486{
3487 struct drm_crtc *crtc;
3488 int htotal, hdisplay, clock, pixel_size;
3489 int line_time_us, line_count;
3490 int entries, tlb_miss;
3491
3492 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3493 if (crtc->fb == NULL || !crtc->enabled) {
3494 *cursor_wm = cursor->guard_size;
3495 *plane_wm = display->guard_size;
417ae147 3496 return false;
5c72d064 3497 }
417ae147
CW		 3498
3499 htotal = crtc->mode.htotal;
3500 hdisplay = crtc->mode.hdisplay;
3501 clock = crtc->mode.clock;
3502 pixel_size = crtc->fb->bits_per_pixel / 8;
3503
3504 /* Use the small buffer method to calculate plane watermark */
3505 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3506 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3507 if (tlb_miss > 0)
3508 entries += tlb_miss;
3509 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3510 *plane_wm = entries + display->guard_size;
3511 if (*plane_wm > (int)display->max_wm)
3512 *plane_wm = display->max_wm;
3513
3514 /* Use the large buffer method to calculate cursor watermark */
3515 line_time_us = ((htotal * 1000) / clock);
3516 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3517 entries = line_count * 64 * pixel_size;
3518 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3519 if (tlb_miss > 0)
3520 entries += tlb_miss;
3521 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3522 *cursor_wm = entries + cursor->guard_size;
3523 if (*cursor_wm > (int)cursor->max_wm)
3524 *cursor_wm = (int)cursor->max_wm;
3525
3526 return true;
3527}
3528
3529/*
3530 * Check the wm result.
3531 *
3532 * If any calculated watermark values is larger than the maximum value that
3533 * can be programmed into the associated watermark register, that watermark
3534 * must be disabled.
3535 */
3536static bool g4x_check_srwm(struct drm_device *dev,
3537 int display_wm, int cursor_wm,
3538 const struct intel_watermark_params *display,
3539 const struct intel_watermark_params *cursor)
652c393a 3540{
417ae147
CW		 3541 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3542 display_wm, cursor_wm);
652c393a 3543
417ae147
CW		 3544 if (display_wm > display->max_wm) {
3545 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3546 display_wm, display->max_wm);
3547 return false;
3548 }
0e442c60 3549
417ae147
CW		 3550 if (cursor_wm > cursor->max_wm) {
3551 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3552 cursor_wm, cursor->max_wm);
3553 return false;
3554 }
0e442c60 3555
417ae147
CW		 3556 if (!(display_wm || cursor_wm)) {
3557 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3558 return false;
3559 }
0e442c60 3560
417ae147
CW		 3561 return true;
3562}
0e442c60 3563
417ae147 3564static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3565 int plane,
3566 int latency_ns,
417ae147
CW		 3567 const struct intel_watermark_params *display,
3568 const struct intel_watermark_params *cursor,
3569 int *display_wm, int *cursor_wm)
3570{
d210246a
CW		 3571 struct drm_crtc *crtc;
3572 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3573 unsigned long line_time_us;
3574 int line_count, line_size;
3575 int small, large;
3576 int entries;
0e442c60 3577
417ae147
CW		 3578 if (!latency_ns) {
3579 *display_wm = *cursor_wm = 0;
3580 return false;
3581 }
0e442c60 3582
d210246a
CW		 3583 crtc = intel_get_crtc_for_plane(dev, plane);
3584 hdisplay = crtc->mode.hdisplay;
3585 htotal = crtc->mode.htotal;
3586 clock = crtc->mode.clock;
3587 pixel_size = crtc->fb->bits_per_pixel / 8;
3588
417ae147
CW		 3589 line_time_us = (htotal * 1000) / clock;
3590 line_count = (latency_ns / line_time_us + 1000) / 1000;
3591 line_size = hdisplay * pixel_size;
0e442c60 3592
417ae147
CW		 3593 /* Use the minimum of the small and large buffer method for primary */
3594 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3595 large = line_count * line_size;
0e442c60 3596
417ae147
CW		 3597 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3598 *display_wm = entries + display->guard_size;
4fe5e611 3599
417ae147
CW		 3600 /* calculate the self-refresh watermark for display cursor */
3601 entries = line_count * pixel_size * 64;
3602 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3603 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3604
417ae147
CW		 3605 return g4x_check_srwm(dev,
3606 *display_wm, *cursor_wm,
3607 display, cursor);
3608}
4fe5e611 3609
7ccb4a53 3610#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 3611
3612static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 3613{
3614 static const int sr_latency_ns = 12000;
3615 struct drm_i915_private *dev_priv = dev->dev_private;
3616 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 3617 int plane_sr, cursor_sr;
3618 unsigned int enabled = 0;
417ae147
CW		 3619
3620 if (g4x_compute_wm0(dev, 0,
3621 &g4x_wm_info, latency_ns,
3622 &g4x_cursor_wm_info, latency_ns,
3623 &planea_wm, &cursora_wm))
d210246a 3624 enabled |= 1;
417ae147
CW		 3625
3626 if (g4x_compute_wm0(dev, 1,
3627 &g4x_wm_info, latency_ns,
3628 &g4x_cursor_wm_info, latency_ns,
3629 &planeb_wm, &cursorb_wm))
d210246a 3630 enabled |= 2;
417ae147
CW		 3631
3632 plane_sr = cursor_sr = 0;
d210246a
CW		 3633 if (single_plane_enabled(enabled) &&
3634 g4x_compute_srwm(dev, ffs(enabled) - 1,
3635 sr_latency_ns,
417ae147
CW		 3636 &g4x_wm_info,
3637 &g4x_cursor_wm_info,
3638 &plane_sr, &cursor_sr))
0e442c60 3639 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 3640 else
3641 I915_WRITE(FW_BLC_SELF,
3642 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 3643
308977ac
CW		 3644 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3645 planea_wm, cursora_wm,
3646 planeb_wm, cursorb_wm,
3647 plane_sr, cursor_sr);
0e442c60 3648
417ae147
CW		 3649 I915_WRITE(DSPFW1,
3650 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 3651 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 3652 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3653 planea_wm);
3654 I915_WRITE(DSPFW2,
3655 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 3656 (cursora_wm << DSPFW_CURSORA_SHIFT));
3657 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 3658 I915_WRITE(DSPFW3,
3659 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 3660 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 3661}
3662
d210246a 3663static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 3664{
3665 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3666 struct drm_crtc *crtc;
3667 int srwm = 1;
4fe5e611 3668 int cursor_sr = 16;
1dc7546d
JB		 3669
3670 /* Calc sr entries for one plane configs */
d210246a
CW		 3671 crtc = single_enabled_crtc(dev);
3672 if (crtc) {
1dc7546d 3673 /* self-refresh has much higher latency */
69e302a9 3674 static const int sr_latency_ns = 12000;
d210246a
CW		 3675 int clock = crtc->mode.clock;
3676 int htotal = crtc->mode.htotal;
3677 int hdisplay = crtc->mode.hdisplay;
3678 int pixel_size = crtc->fb->bits_per_pixel / 8;
3679 unsigned long line_time_us;
3680 int entries;
1dc7546d 3681
d210246a 3682 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 3683
3684 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3685 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3686 pixel_size * hdisplay;
3687 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 3688 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 3689 if (srwm < 0)
3690 srwm = 1;
1b07e04e 3691 srwm &= 0x1ff;
308977ac
CW		 3692 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3693 entries, srwm);
4fe5e611 3694
d210246a 3695 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3696 pixel_size * 64;
d210246a 3697 entries = DIV_ROUND_UP(entries,
8de9b311 3698 i965_cursor_wm_info.cacheline_size);
4fe5e611 3699 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 3700 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 3701
3702 if (cursor_sr > i965_cursor_wm_info.max_wm)
3703 cursor_sr = i965_cursor_wm_info.max_wm;
3704
3705 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3706 "cursor %d\n", srwm, cursor_sr);
3707
a6c45cf0 3708 if (IS_CRESTLINE(dev))
adcdbc66 3709 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 3710 } else {
3711 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3712 if (IS_CRESTLINE(dev))
adcdbc66
JB		 3713 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3714 & ~FW_BLC_SELF_EN);
1dc7546d 3715 }
7662c8bd 3716
1dc7546d
JB		 3717 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3718 srwm);
7662c8bd
SL		 3719
3720 /* 965 has limitations... */
417ae147
CW		 3721 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3722 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 3723 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 3724 /* update cursor SR watermark */
3725 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 3726}
3727
d210246a 3728static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 3729{
3730 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3731 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 3732 uint32_t fwater_lo;
3733 uint32_t fwater_hi;
d210246a
CW		 3734 int cwm, srwm = 1;
3735 int fifo_size;
dff33cfc 3736 int planea_wm, planeb_wm;
d210246a 3737 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 3738
72557b4f 3739 if (IS_I945GM(dev))
d210246a 3740 wm_info = &i945_wm_info;
a6c45cf0 3741 else if (!IS_GEN2(dev))
d210246a 3742 wm_info = &i915_wm_info;
7662c8bd 3743 else
d210246a
CW		 3744 wm_info = &i855_wm_info;
3745
3746 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3747 crtc = intel_get_crtc_for_plane(dev, 0);
3748 if (crtc->enabled && crtc->fb) {
3749 planea_wm = intel_calculate_wm(crtc->mode.clock,
3750 wm_info, fifo_size,
3751 crtc->fb->bits_per_pixel / 8,
3752 latency_ns);
3753 enabled = crtc;
3754 } else
3755 planea_wm = fifo_size - wm_info->guard_size;
3756
3757 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3758 crtc = intel_get_crtc_for_plane(dev, 1);
3759 if (crtc->enabled && crtc->fb) {
3760 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3761 wm_info, fifo_size,
3762 crtc->fb->bits_per_pixel / 8,
3763 latency_ns);
3764 if (enabled == NULL)
3765 enabled = crtc;
3766 else
3767 enabled = NULL;
3768 } else
3769 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 3770
28c97730 3771 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 3772
3773 /*
3774 * Overlay gets an aggressive default since video jitter is bad.
3775 */
3776 cwm = 2;
3777
18b2190c
AL		 3778 /* Play safe and disable self-refresh before adjusting watermarks. */
3779 if (IS_I945G(dev) || IS_I945GM(dev))
3780 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3781 else if (IS_I915GM(dev))
3782 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3783
dff33cfc 3784 /* Calc sr entries for one plane configs */
d210246a 3785 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 3786 /* self-refresh has much higher latency */
69e302a9 3787 static const int sr_latency_ns = 6000;
d210246a
CW		 3788 int clock = enabled->mode.clock;
3789 int htotal = enabled->mode.htotal;
3790 int hdisplay = enabled->mode.hdisplay;
3791 int pixel_size = enabled->fb->bits_per_pixel / 8;
3792 unsigned long line_time_us;
3793 int entries;
dff33cfc 3794
d210246a 3795 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 3796
3797 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3798 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3799 pixel_size * hdisplay;
3800 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3801 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3802 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 3803 if (srwm < 0)
3804 srwm = 1;
ee980b80
LP		 3805
3806 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 3807 I915_WRITE(FW_BLC_SELF,
3808 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3809 else if (IS_I915GM(dev))
ee980b80 3810 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 3811 }
3812
28c97730 3813 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 3814 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 3815
dff33cfc
JB		 3816 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3817 fwater_hi = (cwm & 0x1f);
3818
3819 /* Set request length to 8 cachelines per fetch */
3820 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3821 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 3822
3823 I915_WRITE(FW_BLC, fwater_lo);
3824 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 3825
d210246a
CW		 3826 if (HAS_FW_BLC(dev)) {
3827 if (enabled) {
3828 if (IS_I945G(dev) || IS_I945GM(dev))
3829 I915_WRITE(FW_BLC_SELF,
3830 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3831 else if (IS_I915GM(dev))
3832 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3833 DRM_DEBUG_KMS("memory self refresh enabled\n");
3834 } else
3835 DRM_DEBUG_KMS("memory self refresh disabled\n");
3836 }
7662c8bd
SL		 3837}
3838
d210246a 3839static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 3840{
3841 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3842 struct drm_crtc *crtc;
3843 uint32_t fwater_lo;
dff33cfc 3844 int planea_wm;
7662c8bd 3845
d210246a
CW		 3846 crtc = single_enabled_crtc(dev);
3847 if (crtc == NULL)
3848 return;
7662c8bd 3849
d210246a
CW		 3850 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3851 dev_priv->display.get_fifo_size(dev, 0),
3852 crtc->fb->bits_per_pixel / 8,
3853 latency_ns);
3854 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 3855 fwater_lo |= (3<<8) | planea_wm;
3856
28c97730 3857 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 3858
3859 I915_WRITE(FW_BLC, fwater_lo);
3860}
3861
7f8a8569 3862#define ILK_LP0_PLANE_LATENCY 700
c936f44d 3863#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 3864
4ed765f9
CW		 3865static bool ironlake_compute_wm0(struct drm_device *dev,
3866 int pipe,
1398261a 3867 const struct intel_watermark_params *display,
a0fa62d3 3868 int display_latency_ns,
1398261a 3869 const struct intel_watermark_params *cursor,
a0fa62d3 3870 int cursor_latency_ns,
4ed765f9
CW		 3871 int *plane_wm,
3872 int *cursor_wm)
7f8a8569 3873{
c936f44d 3874 struct drm_crtc *crtc;
db66e37d
CW		 3875 int htotal, hdisplay, clock, pixel_size;
3876 int line_time_us, line_count;
3877 int entries, tlb_miss;
c936f44d 3878
4ed765f9
CW		 3879 crtc = intel_get_crtc_for_pipe(dev, pipe);
3880 if (crtc->fb == NULL || !crtc->enabled)
3881 return false;
7f8a8569 3882
4ed765f9
CW		 3883 htotal = crtc->mode.htotal;
3884 hdisplay = crtc->mode.hdisplay;
3885 clock = crtc->mode.clock;
3886 pixel_size = crtc->fb->bits_per_pixel / 8;
3887
3888 /* Use the small buffer method to calculate plane watermark */
a0fa62d3 3889 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
db66e37d
CW		 3890 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3891 if (tlb_miss > 0)
3892 entries += tlb_miss;
1398261a
YL		 3893 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3894 *plane_wm = entries + display->guard_size;
3895 if (*plane_wm > (int)display->max_wm)
3896 *plane_wm = display->max_wm;
4ed765f9
CW		 3897
3898 /* Use the large buffer method to calculate cursor watermark */
3899 line_time_us = ((htotal * 1000) / clock);
a0fa62d3 3900 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4ed765f9 3901 entries = line_count * 64 * pixel_size;
db66e37d
CW		 3902 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3903 if (tlb_miss > 0)
3904 entries += tlb_miss;
1398261a
YL		 3905 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3906 *cursor_wm = entries + cursor->guard_size;
3907 if (*cursor_wm > (int)cursor->max_wm)
3908 *cursor_wm = (int)cursor->max_wm;
7f8a8569 3909
4ed765f9
CW		 3910 return true;
3911}
c936f44d 3912
1398261a
YL		 3913/*
3914 * Check the wm result.
3915 *
3916 * If any calculated watermark values is larger than the maximum value that
3917 * can be programmed into the associated watermark register, that watermark
3918 * must be disabled.
1398261a 3919 */
b79d4990
JB		 3920static bool ironlake_check_srwm(struct drm_device *dev, int level,
3921 int fbc_wm, int display_wm, int cursor_wm,
3922 const struct intel_watermark_params *display,
3923 const struct intel_watermark_params *cursor)
1398261a
YL		 3924{
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926
3927 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3928 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3929
3930 if (fbc_wm > SNB_FBC_MAX_SRWM) {
3931 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 3932 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 3933
3934 /* fbc has it's own way to disable FBC WM */
3935 I915_WRITE(DISP_ARB_CTL,
3936 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3937 return false;
3938 }
3939
b79d4990 3940 if (display_wm > display->max_wm) {
1398261a 3941 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 3942 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 3943 return false;
3944 }
3945
b79d4990 3946 if (cursor_wm > cursor->max_wm) {
1398261a 3947 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 3948 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 3949 return false;
3950 }
3951
3952 if (!(fbc_wm || display_wm || cursor_wm)) {
3953 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3954 return false;
3955 }
3956
3957 return true;
3958}
3959
3960/*
3961 * Compute watermark values of WM[1-3],
3962 */
d210246a
CW		 3963static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
3964 int latency_ns,
b79d4990
JB		 3965 const struct intel_watermark_params *display,
3966 const struct intel_watermark_params *cursor,
3967 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 3968{
d210246a 3969 struct drm_crtc *crtc;
1398261a 3970 unsigned long line_time_us;
d210246a 3971 int hdisplay, htotal, pixel_size, clock;
b79d4990 3972 int line_count, line_size;
1398261a
YL		 3973 int small, large;
3974 int entries;
1398261a
YL		 3975
3976 if (!latency_ns) {
3977 *fbc_wm = *display_wm = *cursor_wm = 0;
3978 return false;
3979 }
3980
d210246a
CW		 3981 crtc = intel_get_crtc_for_plane(dev, plane);
3982 hdisplay = crtc->mode.hdisplay;
3983 htotal = crtc->mode.htotal;
3984 clock = crtc->mode.clock;
3985 pixel_size = crtc->fb->bits_per_pixel / 8;
3986
1398261a
YL		 3987 line_time_us = (htotal * 1000) / clock;
3988 line_count = (latency_ns / line_time_us + 1000) / 1000;
3989 line_size = hdisplay * pixel_size;
3990
3991 /* Use the minimum of the small and large buffer method for primary */
3992 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3993 large = line_count * line_size;
3994
b79d4990
JB		 3995 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3996 *display_wm = entries + display->guard_size;
1398261a
YL		 3997
3998 /*
b79d4990 3999 * Spec says:
1398261a
YL		 4000 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4001 */
4002 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4003
4004 /* calculate the self-refresh watermark for display cursor */
4005 entries = line_count * pixel_size * 64;
b79d4990
JB		 4006 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4007 *cursor_wm = entries + cursor->guard_size;
1398261a 4008
b79d4990
JB		 4009 return ironlake_check_srwm(dev, level,
4010 *fbc_wm, *display_wm, *cursor_wm,
4011 display, cursor);
4012}
4013
d210246a 4014static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4015{
4016 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4017 int fbc_wm, plane_wm, cursor_wm;
4018 unsigned int enabled;
b79d4990
JB		 4019
4020 enabled = 0;
4021 if (ironlake_compute_wm0(dev, 0,
4022 &ironlake_display_wm_info,
4023 ILK_LP0_PLANE_LATENCY,
4024 &ironlake_cursor_wm_info,
4025 ILK_LP0_CURSOR_LATENCY,
4026 &plane_wm, &cursor_wm)) {
4027 I915_WRITE(WM0_PIPEA_ILK,
4028 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4029 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4030 " plane %d, " "cursor: %d\n",
4031 plane_wm, cursor_wm);
d210246a 4032 enabled |= 1;
b79d4990
JB		 4033 }
4034
4035 if (ironlake_compute_wm0(dev, 1,
4036 &ironlake_display_wm_info,
4037 ILK_LP0_PLANE_LATENCY,
4038 &ironlake_cursor_wm_info,
4039 ILK_LP0_CURSOR_LATENCY,
4040 &plane_wm, &cursor_wm)) {
4041 I915_WRITE(WM0_PIPEB_ILK,
4042 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4043 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4044 " plane %d, cursor: %d\n",
4045 plane_wm, cursor_wm);
d210246a 4046 enabled |= 2;
b79d4990
JB		 4047 }
4048
4049 /*
4050 * Calculate and update the self-refresh watermark only when one
4051 * display plane is used.
4052 */
4053 I915_WRITE(WM3_LP_ILK, 0);
4054 I915_WRITE(WM2_LP_ILK, 0);
4055 I915_WRITE(WM1_LP_ILK, 0);
4056
d210246a 4057 if (!single_plane_enabled(enabled))
b79d4990 4058 return;
d210246a 4059 enabled = ffs(enabled) - 1;
b79d4990
JB		 4060
4061 /* WM1 */
d210246a
CW		 4062 if (!ironlake_compute_srwm(dev, 1, enabled,
4063 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4064 &ironlake_display_srwm_info,
4065 &ironlake_cursor_srwm_info,
4066 &fbc_wm, &plane_wm, &cursor_wm))
4067 return;
4068
4069 I915_WRITE(WM1_LP_ILK,
4070 WM1_LP_SR_EN |
4071 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4072 (fbc_wm << WM1_LP_FBC_SHIFT) |
4073 (plane_wm << WM1_LP_SR_SHIFT) |
4074 cursor_wm);
4075
4076 /* WM2 */
d210246a
CW		 4077 if (!ironlake_compute_srwm(dev, 2, enabled,
4078 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4079 &ironlake_display_srwm_info,
4080 &ironlake_cursor_srwm_info,
4081 &fbc_wm, &plane_wm, &cursor_wm))
4082 return;
4083
4084 I915_WRITE(WM2_LP_ILK,
4085 WM2_LP_EN |
4086 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4087 (fbc_wm << WM1_LP_FBC_SHIFT) |
4088 (plane_wm << WM1_LP_SR_SHIFT) |
4089 cursor_wm);
4090
4091 /*
4092 * WM3 is unsupported on ILK, probably because we don't have latency
4093 * data for that power state
4094 */
1398261a
YL		 4095}
4096
d210246a 4097static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4098{
4099 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4100 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4101 int fbc_wm, plane_wm, cursor_wm;
4102 unsigned int enabled;
1398261a
YL		 4103
4104 enabled = 0;
4105 if (ironlake_compute_wm0(dev, 0,
4106 &sandybridge_display_wm_info, latency,
4107 &sandybridge_cursor_wm_info, latency,
4108 &plane_wm, &cursor_wm)) {
4109 I915_WRITE(WM0_PIPEA_ILK,
4110 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4111 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4112 " plane %d, " "cursor: %d\n",
4113 plane_wm, cursor_wm);
d210246a 4114 enabled |= 1;
1398261a
YL		 4115 }
4116
4117 if (ironlake_compute_wm0(dev, 1,
4118 &sandybridge_display_wm_info, latency,
4119 &sandybridge_cursor_wm_info, latency,
4120 &plane_wm, &cursor_wm)) {
4121 I915_WRITE(WM0_PIPEB_ILK,
4122 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4123 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4124 " plane %d, cursor: %d\n",
4125 plane_wm, cursor_wm);
d210246a 4126 enabled |= 2;
1398261a
YL		 4127 }
4128
4129 /*
4130 * Calculate and update the self-refresh watermark only when one
4131 * display plane is used.
4132 *
4133 * SNB support 3 levels of watermark.
4134 *
4135 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4136 * and disabled in the descending order
4137 *
4138 */
4139 I915_WRITE(WM3_LP_ILK, 0);
4140 I915_WRITE(WM2_LP_ILK, 0);
4141 I915_WRITE(WM1_LP_ILK, 0);
4142
d210246a 4143 if (!single_plane_enabled(enabled))
1398261a 4144 return;
d210246a 4145 enabled = ffs(enabled) - 1;
1398261a
YL		 4146
4147 /* WM1 */
d210246a
CW		 4148 if (!ironlake_compute_srwm(dev, 1, enabled,
4149 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4150 &sandybridge_display_srwm_info,
4151 &sandybridge_cursor_srwm_info,
4152 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4153 return;
4154
4155 I915_WRITE(WM1_LP_ILK,
4156 WM1_LP_SR_EN |
4157 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4158 (fbc_wm << WM1_LP_FBC_SHIFT) |
4159 (plane_wm << WM1_LP_SR_SHIFT) |
4160 cursor_wm);
4161
4162 /* WM2 */
d210246a
CW		 4163 if (!ironlake_compute_srwm(dev, 2, enabled,
4164 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4165 &sandybridge_display_srwm_info,
4166 &sandybridge_cursor_srwm_info,
4167 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4168 return;
4169
4170 I915_WRITE(WM2_LP_ILK,
4171 WM2_LP_EN |
4172 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4173 (fbc_wm << WM1_LP_FBC_SHIFT) |
4174 (plane_wm << WM1_LP_SR_SHIFT) |
4175 cursor_wm);
4176
4177 /* WM3 */
d210246a
CW		 4178 if (!ironlake_compute_srwm(dev, 3, enabled,
4179 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4180 &sandybridge_display_srwm_info,
4181 &sandybridge_cursor_srwm_info,
4182 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4183 return;
4184
4185 I915_WRITE(WM3_LP_ILK,
4186 WM3_LP_EN |
4187 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4188 (fbc_wm << WM1_LP_FBC_SHIFT) |
4189 (plane_wm << WM1_LP_SR_SHIFT) |
4190 cursor_wm);
4191}
4192
7662c8bd
SL		 4193/**
4194 * intel_update_watermarks - update FIFO watermark values based on current modes
4195 *
4196 * Calculate watermark values for the various WM regs based on current mode
4197 * and plane configuration.
4198 *
4199 * There are several cases to deal with here:
4200 * - normal (i.e. non-self-refresh)
4201 * - self-refresh (SR) mode
4202 * - lines are large relative to FIFO size (buffer can hold up to 2)
4203 * - lines are small relative to FIFO size (buffer can hold more than 2
4204 * lines), so need to account for TLB latency
4205 *
4206 * The normal calculation is:
4207 * watermark = dotclock * bytes per pixel * latency
4208 * where latency is platform & configuration dependent (we assume pessimal
4209 * values here).
4210 *
4211 * The SR calculation is:
4212 * watermark = (trunc(latency/line time)+1) * surface width *
4213 * bytes per pixel
4214 * where
4215 * line time = htotal / dotclock
fa143215 4216 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4217 * and latency is assumed to be high, as above.
4218 *
4219 * The final value programmed to the register should always be rounded up,
4220 * and include an extra 2 entries to account for clock crossings.
4221 *
4222 * We don't use the sprite, so we can ignore that. And on Crestline we have
4223 * to set the non-SR watermarks to 8.
5eddb70b 4224 */
7662c8bd
SL		 4225static void intel_update_watermarks(struct drm_device *dev)
4226{
e70236a8 4227 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4228
d210246a
CW		 4229 if (dev_priv->display.update_wm)
4230 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4231}
4232
a7615030
CW		 4233static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4234{
4235 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4236}
4237
f564048e
EA		 4238static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4239 struct drm_display_mode *mode,
4240 struct drm_display_mode *adjusted_mode,
4241 int x, int y,
4242 struct drm_framebuffer *old_fb)
4243{
4244 struct drm_device *dev = crtc->dev;
4245 struct drm_i915_private *dev_priv = dev->dev_private;
4246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4247 int pipe = intel_crtc->pipe;
4248 int plane = intel_crtc->plane;
f564048e
EA		 4249 int refclk, num_connectors = 0;
4250 intel_clock_t clock, reduced_clock;
4251 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4252 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4253 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
f564048e
EA		 4254 struct drm_mode_config *mode_config = &dev->mode_config;
4255 struct intel_encoder *encoder;
4256 const intel_limit_t *limit;
4257 int ret;
fae14981 4258 u32 temp;
f564048e 4259 u32 lvds_sync = 0;
f564048e 4260
f564048e
EA		 4261 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4262 if (encoder->base.crtc != crtc)
4263 continue;
4264
4265 switch (encoder->type) {
4266 case INTEL_OUTPUT_LVDS:
4267 is_lvds = true;
4268 break;
4269 case INTEL_OUTPUT_SDVO:
4270 case INTEL_OUTPUT_HDMI:
4271 is_sdvo = true;
4272 if (encoder->needs_tv_clock)
4273 is_tv = true;
4274 break;
4275 case INTEL_OUTPUT_DVO:
4276 is_dvo = true;
4277 break;
4278 case INTEL_OUTPUT_TVOUT:
4279 is_tv = true;
4280 break;
4281 case INTEL_OUTPUT_ANALOG:
4282 is_crt = true;
4283 break;
4284 case INTEL_OUTPUT_DISPLAYPORT:
4285 is_dp = true;
4286 break;
f564048e
EA		 4287 }
4288
4289 num_connectors++;
4290 }
4291
4292 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4293 refclk = dev_priv->lvds_ssc_freq * 1000;
4294 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4295 refclk / 1000);
4296 } else if (!IS_GEN2(dev)) {
4297 refclk = 96000;
f564048e
EA		 4298 } else {
4299 refclk = 48000;
4300 }
4301
4302 /*
4303 * Returns a set of divisors for the desired target clock with the given
4304 * refclk, or FALSE. The returned values represent the clock equation:
4305 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4306 */
4307 limit = intel_limit(crtc, refclk);
4308 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4309 if (!ok) {
4310 DRM_ERROR("Couldn't find PLL settings for mode!\n");
f564048e
EA		 4311 return -EINVAL;
4312 }
4313
4314 /* Ensure that the cursor is valid for the new mode before changing... */
4315 intel_crtc_update_cursor(crtc, true);
4316
4317 if (is_lvds && dev_priv->lvds_downclock_avail) {
4318 has_reduced_clock = limit->find_pll(limit, crtc,
4319 dev_priv->lvds_downclock,
4320 refclk,
4321 &reduced_clock);
4322 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4323 /*
4324 * If the different P is found, it means that we can't
4325 * switch the display clock by using the FP0/FP1.
4326 * In such case we will disable the LVDS downclock
4327 * feature.
4328 */
4329 DRM_DEBUG_KMS("Different P is found for "
4330 "LVDS clock/downclock\n");
4331 has_reduced_clock = 0;
4332 }
4333 }
4334 /* SDVO TV has fixed PLL values depend on its clock range,
4335 this mirrors vbios setting. */
4336 if (is_sdvo && is_tv) {
4337 if (adjusted_mode->clock >= 100000
4338 && adjusted_mode->clock < 140500) {
4339 clock.p1 = 2;
4340 clock.p2 = 10;
4341 clock.n = 3;
4342 clock.m1 = 16;
4343 clock.m2 = 8;
4344 } else if (adjusted_mode->clock >= 140500
4345 && adjusted_mode->clock <= 200000) {
4346 clock.p1 = 1;
4347 clock.p2 = 10;
4348 clock.n = 6;
4349 clock.m1 = 12;
4350 clock.m2 = 8;
4351 }
4352 }
4353
f564048e
EA		 4354 if (IS_PINEVIEW(dev)) {
4355 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4356 if (has_reduced_clock)
4357 fp2 = (1 << reduced_clock.n) << 16 |
4358 reduced_clock.m1 << 8 | reduced_clock.m2;
4359 } else {
4360 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4361 if (has_reduced_clock)
4362 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4363 reduced_clock.m2;
4364 }
4365
929c77fb 4366 dpll = DPLL_VGA_MODE_DIS;
f564048e
EA		 4367
4368 if (!IS_GEN2(dev)) {
4369 if (is_lvds)
4370 dpll |= DPLLB_MODE_LVDS;
4371 else
4372 dpll |= DPLLB_MODE_DAC_SERIAL;
4373 if (is_sdvo) {
4374 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4375 if (pixel_multiplier > 1) {
4376 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4377 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
f564048e
EA		 4378 }
4379 dpll |= DPLL_DVO_HIGH_SPEED;
4380 }
929c77fb 4381 if (is_dp)
f564048e
EA		 4382 dpll |= DPLL_DVO_HIGH_SPEED;
4383
4384 /* compute bitmask from p1 value */
4385 if (IS_PINEVIEW(dev))
4386 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4387 else {
4388 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
f564048e
EA		 4389 if (IS_G4X(dev) && has_reduced_clock)
4390 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4391 }
4392 switch (clock.p2) {
4393 case 5:
4394 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4395 break;
4396 case 7:
4397 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4398 break;
4399 case 10:
4400 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4401 break;
4402 case 14:
4403 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4404 break;
4405 }
929c77fb 4406 if (INTEL_INFO(dev)->gen >= 4)
f564048e
EA		 4407 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4408 } else {
4409 if (is_lvds) {
4410 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4411 } else {
4412 if (clock.p1 == 2)
4413 dpll |= PLL_P1_DIVIDE_BY_TWO;
4414 else
4415 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4416 if (clock.p2 == 4)
4417 dpll |= PLL_P2_DIVIDE_BY_4;
4418 }
4419 }
4420
4421 if (is_sdvo && is_tv)
4422 dpll |= PLL_REF_INPUT_TVCLKINBC;
4423 else if (is_tv)
4424 /* XXX: just matching BIOS for now */
4425 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4426 dpll |= 3;
4427 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4428 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4429 else
4430 dpll |= PLL_REF_INPUT_DREFCLK;
4431
4432 /* setup pipeconf */
4433 pipeconf = I915_READ(PIPECONF(pipe));
4434
4435 /* Set up the display plane register */
4436 dspcntr = DISPPLANE_GAMMA_ENABLE;
4437
4438 /* Ironlake's plane is forced to pipe, bit 24 is to
4439 enable color space conversion */
929c77fb
EA		 4440 if (pipe == 0)
4441 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4442 else
4443 dspcntr |= DISPPLANE_SEL_PIPE_B;
f564048e
EA		 4444
4445 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4446 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4447 * core speed.
4448 *
4449 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4450 * pipe == 0 check?
4451 */
4452 if (mode->clock >
4453 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4454 pipeconf |= PIPECONF_DOUBLE_WIDE;
4455 else
4456 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4457 }
4458
929c77fb 4459 dpll |= DPLL_VCO_ENABLE;
f564048e
EA		 4460
4461 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4462 drm_mode_debug_printmodeline(mode);
4463
fae14981
EA		 4464 I915_WRITE(FP0(pipe), fp);
4465 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
f564048e 4466
fae14981 4467 POSTING_READ(DPLL(pipe));
c713bb08 4468 udelay(150);
f564048e 4469
f564048e
EA		 4470 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4471 * This is an exception to the general rule that mode_set doesn't turn
4472 * things on.
4473 */
4474 if (is_lvds) {
fae14981 4475 temp = I915_READ(LVDS);
f564048e
EA		 4476 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4477 if (pipe == 1) {
929c77fb 4478 temp |= LVDS_PIPEB_SELECT;
f564048e 4479 } else {
929c77fb 4480 temp &= ~LVDS_PIPEB_SELECT;
f564048e
EA		 4481 }
4482 /* set the corresponsding LVDS_BORDER bit */
4483 temp |= dev_priv->lvds_border_bits;
4484 /* Set the B0-B3 data pairs corresponding to whether we're going to
4485 * set the DPLLs for dual-channel mode or not.
4486 */
4487 if (clock.p2 == 7)
4488 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4489 else
4490 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4491
4492 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4493 * appropriately here, but we need to look more thoroughly into how
4494 * panels behave in the two modes.
4495 */
929c77fb
EA		 4496 /* set the dithering flag on LVDS as needed */
4497 if (INTEL_INFO(dev)->gen >= 4) {
f564048e
EA		 4498 if (dev_priv->lvds_dither)
4499 temp |= LVDS_ENABLE_DITHER;
4500 else
4501 temp &= ~LVDS_ENABLE_DITHER;
4502 }
4503 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4504 lvds_sync |= LVDS_HSYNC_POLARITY;
4505 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4506 lvds_sync |= LVDS_VSYNC_POLARITY;
4507 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4508 != lvds_sync) {
4509 char flags[2] = "-+";
4510 DRM_INFO("Changing LVDS panel from "
4511 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4512 flags[!(temp & LVDS_HSYNC_POLARITY)],
4513 flags[!(temp & LVDS_VSYNC_POLARITY)],
4514 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4515 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4516 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4517 temp |= lvds_sync;
4518 }
fae14981 4519 I915_WRITE(LVDS, temp);
f564048e
EA		 4520 }
4521
929c77fb 4522 if (is_dp) {
f564048e 4523 intel_dp_set_m_n(crtc, mode, adjusted_mode);
f564048e
EA		 4524 }
4525
fae14981 4526 I915_WRITE(DPLL(pipe), dpll);
f564048e 4527
c713bb08 4528 /* Wait for the clocks to stabilize. */
fae14981 4529 POSTING_READ(DPLL(pipe));
c713bb08 4530 udelay(150);
f564048e 4531
c713bb08
EA		 4532 if (INTEL_INFO(dev)->gen >= 4) {
4533 temp = 0;
4534 if (is_sdvo) {
4535 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4536 if (temp > 1)
4537 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4538 else
4539 temp = 0;
f564048e 4540 }
c713bb08
EA		 4541 I915_WRITE(DPLL_MD(pipe), temp);
4542 } else {
4543 /* The pixel multiplier can only be updated once the
4544 * DPLL is enabled and the clocks are stable.
4545 *
4546 * So write it again.
4547 */
fae14981 4548 I915_WRITE(DPLL(pipe), dpll);
f564048e
EA		 4549 }
4550
4551 intel_crtc->lowfreq_avail = false;
4552 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 4553 I915_WRITE(FP1(pipe), fp2);
f564048e
EA		 4554 intel_crtc->lowfreq_avail = true;
4555 if (HAS_PIPE_CXSR(dev)) {
4556 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4557 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4558 }
4559 } else {
fae14981 4560 I915_WRITE(FP1(pipe), fp);
f564048e
EA		 4561 if (HAS_PIPE_CXSR(dev)) {
4562 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4563 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4564 }
4565 }
4566
4567 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4568 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4569 /* the chip adds 2 halflines automatically */
4570 adjusted_mode->crtc_vdisplay -= 1;
4571 adjusted_mode->crtc_vtotal -= 1;
4572 adjusted_mode->crtc_vblank_start -= 1;
4573 adjusted_mode->crtc_vblank_end -= 1;
4574 adjusted_mode->crtc_vsync_end -= 1;
4575 adjusted_mode->crtc_vsync_start -= 1;
4576 } else
4577 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4578
4579 I915_WRITE(HTOTAL(pipe),
4580 (adjusted_mode->crtc_hdisplay - 1) |
4581 ((adjusted_mode->crtc_htotal - 1) << 16));
4582 I915_WRITE(HBLANK(pipe),
4583 (adjusted_mode->crtc_hblank_start - 1) |
4584 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4585 I915_WRITE(HSYNC(pipe),
4586 (adjusted_mode->crtc_hsync_start - 1) |
4587 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4588
4589 I915_WRITE(VTOTAL(pipe),
4590 (adjusted_mode->crtc_vdisplay - 1) |
4591 ((adjusted_mode->crtc_vtotal - 1) << 16));
4592 I915_WRITE(VBLANK(pipe),
4593 (adjusted_mode->crtc_vblank_start - 1) |
4594 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4595 I915_WRITE(VSYNC(pipe),
4596 (adjusted_mode->crtc_vsync_start - 1) |
4597 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4598
4599 /* pipesrc and dspsize control the size that is scaled from,
4600 * which should always be the user's requested size.
4601 */
929c77fb
EA		 4602 I915_WRITE(DSPSIZE(plane),
4603 ((mode->vdisplay - 1) << 16) |
4604 (mode->hdisplay - 1));
4605 I915_WRITE(DSPPOS(plane), 0);
f564048e
EA		 4606 I915_WRITE(PIPESRC(pipe),
4607 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4608
f564048e
EA		 4609 I915_WRITE(PIPECONF(pipe), pipeconf);
4610 POSTING_READ(PIPECONF(pipe));
929c77fb 4611 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4612
4613 intel_wait_for_vblank(dev, pipe);
4614
f564048e
EA		 4615 I915_WRITE(DSPCNTR(plane), dspcntr);
4616 POSTING_READ(DSPCNTR(plane));
4617
4618 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4619
4620 intel_update_watermarks(dev);
4621
f564048e
EA		 4622 return ret;
4623}
4624
4625static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4626 struct drm_display_mode *mode,
4627 struct drm_display_mode *adjusted_mode,
4628 int x, int y,
4629 struct drm_framebuffer *old_fb)
79e53945
JB		 4630{
4631 struct drm_device *dev = crtc->dev;
4632 struct drm_i915_private *dev_priv = dev->dev_private;
4633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4634 int pipe = intel_crtc->pipe;
80824003 4635 int plane = intel_crtc->plane;
c751ce4f 4636 int refclk, num_connectors = 0;
652c393a 4637 intel_clock_t clock, reduced_clock;
5eddb70b 4638 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4639 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4640 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 4641 struct intel_encoder *has_edp_encoder = NULL;
79e53945 4642 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4643 struct intel_encoder *encoder;
d4906093 4644 const intel_limit_t *limit;
5c3b82e2 4645 int ret;
2c07245f 4646 struct fdi_m_n m_n = {0};
fae14981 4647 u32 temp;
aa9b500d 4648 u32 lvds_sync = 0;
8febb297 4649 int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
79e53945 4650
5eddb70b
CW		 4651 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4652 if (encoder->base.crtc != crtc)
79e53945
JB		 4653 continue;
4654
5eddb70b 4655 switch (encoder->type) {
79e53945
JB		 4656 case INTEL_OUTPUT_LVDS:
4657 is_lvds = true;
4658 break;
4659 case INTEL_OUTPUT_SDVO:
7d57382e 4660 case INTEL_OUTPUT_HDMI:
79e53945 4661 is_sdvo = true;
5eddb70b 4662 if (encoder->needs_tv_clock)
e2f0ba97 4663 is_tv = true;
79e53945 4664 break;
79e53945
JB		 4665 case INTEL_OUTPUT_TVOUT:
4666 is_tv = true;
4667 break;
4668 case INTEL_OUTPUT_ANALOG:
4669 is_crt = true;
4670 break;
a4fc5ed6
KP		 4671 case INTEL_OUTPUT_DISPLAYPORT:
4672 is_dp = true;
4673 break;
32f9d658 4674 case INTEL_OUTPUT_EDP:
5eddb70b 4675 has_edp_encoder = encoder;
32f9d658 4676 break;
79e53945 4677 }
43565a06 4678
c751ce4f 4679 num_connectors++;
79e53945
JB		 4680 }
4681
a7615030 4682 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4683 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4684 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4685 refclk / 1000);
a07d6787 4686 } else {
79e53945 4687 refclk = 96000;
8febb297
EA		 4688 if (!has_edp_encoder ||
4689 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 4690 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 4691 }
4692
d4906093
ML		 4693 /*
4694 * Returns a set of divisors for the desired target clock with the given
4695 * refclk, or FALSE. The returned values represent the clock equation:
4696 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4697 */
1b894b59 4698 limit = intel_limit(crtc, refclk);
d4906093 4699 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4700 if (!ok) {
4701 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4702 return -EINVAL;
79e53945
JB		 4703 }
4704
cda4b7d3 4705 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4706 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4707
ddc9003c
ZY		 4708 if (is_lvds && dev_priv->lvds_downclock_avail) {
4709 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4710 dev_priv->lvds_downclock,
4711 refclk,
4712 &reduced_clock);
18f9ed12
ZY		 4713 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4714 /*
4715 * If the different P is found, it means that we can't
4716 * switch the display clock by using the FP0/FP1.
4717 * In such case we will disable the LVDS downclock
4718 * feature.
4719 */
4720 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4721 "LVDS clock/downclock\n");
18f9ed12
ZY		 4722 has_reduced_clock = 0;
4723 }
652c393a 4724 }
7026d4ac
ZW		 4725 /* SDVO TV has fixed PLL values depend on its clock range,
4726 this mirrors vbios setting. */
4727 if (is_sdvo && is_tv) {
4728 if (adjusted_mode->clock >= 100000
5eddb70b 4729 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4730 clock.p1 = 2;
4731 clock.p2 = 10;
4732 clock.n = 3;
4733 clock.m1 = 16;
4734 clock.m2 = 8;
4735 } else if (adjusted_mode->clock >= 140500
5eddb70b 4736 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4737 clock.p1 = 1;
4738 clock.p2 = 10;
4739 clock.n = 6;
4740 clock.m1 = 12;
4741 clock.m2 = 8;
4742 }
4743 }
4744
2c07245f 4745 /* FDI link */
8febb297
EA		 4746 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4747 lane = 0;
4748 /* CPU eDP doesn't require FDI link, so just set DP M/N
4749 according to current link config */
4750 if (has_edp_encoder &&
4751 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4752 target_clock = mode->clock;
4753 intel_edp_link_config(has_edp_encoder,
4754 &lane, &link_bw);
4755 } else {
4756 /* [e]DP over FDI requires target mode clock
4757 instead of link clock */
4758 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 4759 target_clock = mode->clock;
8febb297
EA		 4760 else
4761 target_clock = adjusted_mode->clock;
4762
4763 /* FDI is a binary signal running at ~2.7GHz, encoding
4764 * each output octet as 10 bits. The actual frequency
4765 * is stored as a divider into a 100MHz clock, and the
4766 * mode pixel clock is stored in units of 1KHz.
4767 * Hence the bw of each lane in terms of the mode signal
4768 * is:
4769 */
4770 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4771 }
58a27471 4772
8febb297
EA		 4773 /* determine panel color depth */
4774 temp = I915_READ(PIPECONF(pipe));
4775 temp &= ~PIPE_BPC_MASK;
4776 if (is_lvds) {
4777 /* the BPC will be 6 if it is 18-bit LVDS panel */
4778 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4779 temp |= PIPE_8BPC;
4780 else
4781 temp |= PIPE_6BPC;
4782 } else if (has_edp_encoder) {
4783 switch (dev_priv->edp.bpp/3) {
4784 case 8:
e5a95eb7 4785 temp |= PIPE_8BPC;
58a27471 4786 break;
8febb297
EA		 4787 case 10:
4788 temp |= PIPE_10BPC;
58a27471 4789 break;
8febb297
EA		 4790 case 6:
4791 temp |= PIPE_6BPC;
58a27471 4792 break;
8febb297
EA		 4793 case 12:
4794 temp |= PIPE_12BPC;
58a27471 4795 break;
77ffb597 4796 }
8febb297
EA		 4797 } else
4798 temp |= PIPE_8BPC;
4799 I915_WRITE(PIPECONF(pipe), temp);
77ffb597 4800
8febb297
EA		 4801 switch (temp & PIPE_BPC_MASK) {
4802 case PIPE_8BPC:
4803 bpp = 24;
4804 break;
4805 case PIPE_10BPC:
4806 bpp = 30;
4807 break;
4808 case PIPE_6BPC:
4809 bpp = 18;
4810 break;
4811 case PIPE_12BPC:
4812 bpp = 36;
4813 break;
4814 default:
4815 DRM_ERROR("unknown pipe bpc value\n");
4816 bpp = 24;
4817 }
77ffb597 4818
8febb297
EA		 4819 if (!lane) {
4820 /*
4821 * Account for spread spectrum to avoid
4822 * oversubscribing the link. Max center spread
4823 * is 2.5%; use 5% for safety's sake.
4824 */
4825 u32 bps = target_clock * bpp * 21 / 20;
4826 lane = bps / (link_bw * 8) + 1;
5eb08b69 4827 }
2c07245f 4828
8febb297
EA		 4829 intel_crtc->fdi_lanes = lane;
4830
4831 if (pixel_multiplier > 1)
4832 link_bw *= pixel_multiplier;
4833 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4834
c038e51e
ZW		 4835 /* Ironlake: try to setup display ref clock before DPLL
4836 * enabling. This is only under driver's control after
4837 * PCH B stepping, previous chipset stepping should be
4838 * ignoring this setting.
4839 */
8febb297
EA		 4840 temp = I915_READ(PCH_DREF_CONTROL);
4841 /* Always enable nonspread source */
4842 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4843 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4844 temp &= ~DREF_SSC_SOURCE_MASK;
4845 temp |= DREF_SSC_SOURCE_ENABLE;
4846 I915_WRITE(PCH_DREF_CONTROL, temp);
4847
4848 POSTING_READ(PCH_DREF_CONTROL);
4849 udelay(200);
fc9a2228 4850
8febb297
EA		 4851 if (has_edp_encoder) {
4852 if (intel_panel_use_ssc(dev_priv)) {
4853 temp |= DREF_SSC1_ENABLE;
fc9a2228 4854 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 4855
fc9a2228
CW		 4856 POSTING_READ(PCH_DREF_CONTROL);
4857 udelay(200);
4858 }
8febb297
EA		 4859 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4860
4861 /* Enable CPU source on CPU attached eDP */
4862 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4863 if (intel_panel_use_ssc(dev_priv))
4864 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4865 else
4866 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4867 } else {
4868 /* Enable SSC on PCH eDP if needed */
4869 if (intel_panel_use_ssc(dev_priv)) {
4870 DRM_ERROR("enabling SSC on PCH\n");
4871 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4872 }
4873 }
4874 I915_WRITE(PCH_DREF_CONTROL, temp);
4875 POSTING_READ(PCH_DREF_CONTROL);
4876 udelay(200);
fc9a2228 4877 }
c038e51e 4878
a07d6787
EA		 4879 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4880 if (has_reduced_clock)
4881 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4882 reduced_clock.m2;
79e53945 4883
c1858123 4884 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4885 factor = 21;
4886 if (is_lvds) {
4887 if ((intel_panel_use_ssc(dev_priv) &&
4888 dev_priv->lvds_ssc_freq == 100) ||
4889 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4890 factor = 25;
4891 } else if (is_sdvo && is_tv)
4892 factor = 20;
c1858123 4893
8febb297
EA		 4894 if (clock.m1 < factor * clock.n)
4895 fp |= FP_CB_TUNE;
c1858123 4896
5eddb70b 4897 dpll = 0;
2c07245f 4898
a07d6787
EA		 4899 if (is_lvds)
4900 dpll |= DPLLB_MODE_LVDS;
4901 else
4902 dpll |= DPLLB_MODE_DAC_SERIAL;
4903 if (is_sdvo) {
4904 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4905 if (pixel_multiplier > 1) {
4906 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4907 }
a07d6787
EA		 4908 dpll |= DPLL_DVO_HIGH_SPEED;
4909 }
4910 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4911 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4912
a07d6787
EA		 4913 /* compute bitmask from p1 value */
4914 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4915 /* also FPA1 */
4916 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4917
4918 switch (clock.p2) {
4919 case 5:
4920 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4921 break;
4922 case 7:
4923 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4924 break;
4925 case 10:
4926 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4927 break;
4928 case 14:
4929 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4930 break;
79e53945
JB		 4931 }
4932
43565a06
KH		 4933 if (is_sdvo && is_tv)
4934 dpll |= PLL_REF_INPUT_TVCLKINBC;
4935 else if (is_tv)
79e53945 4936 /* XXX: just matching BIOS for now */
43565a06 4937 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4938 dpll |= 3;
a7615030 4939 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4940 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4941 else
4942 dpll |= PLL_REF_INPUT_DREFCLK;
4943
4944 /* setup pipeconf */
5eddb70b 4945 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4946
4947 /* Set up the display plane register */
4948 dspcntr = DISPPLANE_GAMMA_ENABLE;
4949
28c97730 4950 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4951 drm_mode_debug_printmodeline(mode);
4952
5c5313c8
JB		 4953 /* PCH eDP needs FDI, but CPU eDP does not */
4954 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 4955 I915_WRITE(PCH_FP0(pipe), fp);
4956 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4957
fae14981 4958 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 4959 udelay(150);
4960 }
4961
8db9d77b
ZW		 4962 /* enable transcoder DPLL */
4963 if (HAS_PCH_CPT(dev)) {
4964 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 4965 switch (pipe) {
4966 case 0:
5eddb70b 4967 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 4968 break;
4969 case 1:
5eddb70b 4970 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 4971 break;
4972 case 2:
4973 /* FIXME: manage transcoder PLLs? */
4974 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
4975 break;
4976 default:
4977 BUG();
4978 }
8db9d77b 4979 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 4980
4981 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 4982 udelay(150);
4983 }
4984
79e53945
JB		 4985 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4986 * This is an exception to the general rule that mode_set doesn't turn
4987 * things on.
4988 */
4989 if (is_lvds) {
fae14981 4990 temp = I915_READ(PCH_LVDS);
5eddb70b 4991 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 4992 if (pipe == 1) {
4993 if (HAS_PCH_CPT(dev))
5eddb70b 4994 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 4995 else
5eddb70b 4996 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 4997 } else {
4998 if (HAS_PCH_CPT(dev))
5eddb70b 4999 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5000 else
5eddb70b 5001 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5002 }
a3e17eb8 5003 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5004 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5005 /* Set the B0-B3 data pairs corresponding to whether we're going to
5006 * set the DPLLs for dual-channel mode or not.
5007 */
5008 if (clock.p2 == 7)
5eddb70b 5009 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5010 else
5eddb70b 5011 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5012
5013 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5014 * appropriately here, but we need to look more thoroughly into how
5015 * panels behave in the two modes.
5016 */
aa9b500d
BF		 5017 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5018 lvds_sync |= LVDS_HSYNC_POLARITY;
5019 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5020 lvds_sync |= LVDS_VSYNC_POLARITY;
5021 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5022 != lvds_sync) {
5023 char flags[2] = "-+";
5024 DRM_INFO("Changing LVDS panel from "
5025 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5026 flags[!(temp & LVDS_HSYNC_POLARITY)],
5027 flags[!(temp & LVDS_VSYNC_POLARITY)],
5028 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5029 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5030 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5031 temp |= lvds_sync;
5032 }
fae14981 5033 I915_WRITE(PCH_LVDS, temp);
79e53945 5034 }
434ed097
JB		 5035
5036 /* set the dithering flag and clear for anything other than a panel. */
8febb297
EA		 5037 pipeconf &= ~PIPECONF_DITHER_EN;
5038 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5039 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5040 pipeconf |= PIPECONF_DITHER_EN;
5041 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097
JB		 5042 }
5043
5c5313c8 5044 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5045 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5046 } else {
8db9d77b 5047 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5048 I915_WRITE(TRANSDATA_M1(pipe), 0);
5049 I915_WRITE(TRANSDATA_N1(pipe), 0);
5050 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5051 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5052 }
79e53945 5053
8febb297
EA		 5054 if (!has_edp_encoder ||
5055 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5056 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5057
32f9d658 5058 /* Wait for the clocks to stabilize. */
fae14981 5059 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5060 udelay(150);
5061
8febb297
EA		 5062 /* The pixel multiplier can only be updated once the
5063 * DPLL is enabled and the clocks are stable.
5064 *
5065 * So write it again.
5066 */
fae14981 5067 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5068 }
79e53945 5069
5eddb70b 5070 intel_crtc->lowfreq_avail = false;
652c393a 5071 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5072 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5073 intel_crtc->lowfreq_avail = true;
5074 if (HAS_PIPE_CXSR(dev)) {
28c97730 5075 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5076 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5077 }
5078 } else {
fae14981 5079 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5080 if (HAS_PIPE_CXSR(dev)) {
28c97730 5081 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5082 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5083 }
5084 }
5085
734b4157
KH		 5086 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5087 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5088 /* the chip adds 2 halflines automatically */
5089 adjusted_mode->crtc_vdisplay -= 1;
5090 adjusted_mode->crtc_vtotal -= 1;
5091 adjusted_mode->crtc_vblank_start -= 1;
5092 adjusted_mode->crtc_vblank_end -= 1;
5093 adjusted_mode->crtc_vsync_end -= 1;
5094 adjusted_mode->crtc_vsync_start -= 1;
5095 } else
5096 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5097
5eddb70b
CW		 5098 I915_WRITE(HTOTAL(pipe),
5099 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5100 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5101 I915_WRITE(HBLANK(pipe),
5102 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5103 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5104 I915_WRITE(HSYNC(pipe),
5105 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5106 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5107
5108 I915_WRITE(VTOTAL(pipe),
5109 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5110 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5111 I915_WRITE(VBLANK(pipe),
5112 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5113 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5114 I915_WRITE(VSYNC(pipe),
5115 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5116 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5117
8febb297
EA		 5118 /* pipesrc controls the size that is scaled from, which should
5119 * always be the user's requested size.
79e53945 5120 */
5eddb70b
CW		 5121 I915_WRITE(PIPESRC(pipe),
5122 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5123
8febb297
EA		 5124 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5125 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5126 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5127 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5128
8febb297
EA		 5129 if (has_edp_encoder &&
5130 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5131 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5132 }
5133
5eddb70b
CW		 5134 I915_WRITE(PIPECONF(pipe), pipeconf);
5135 POSTING_READ(PIPECONF(pipe));
79e53945 5136
9d0498a2 5137 intel_wait_for_vblank(dev, pipe);
79e53945 5138
f00a3ddf 5139 if (IS_GEN5(dev)) {
553bd149
ZW		 5140 /* enable address swizzle for tiling buffer */
5141 temp = I915_READ(DISP_ARB_CTL);
5142 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5143 }
5144
5eddb70b 5145 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5146 POSTING_READ(DSPCNTR(plane));
79e53945 5147
5c3b82e2 5148 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5149
5150 intel_update_watermarks(dev);
5151
1f803ee5 5152 return ret;
79e53945
JB		 5153}
5154
f564048e
EA		 5155static int intel_crtc_mode_set(struct drm_crtc *crtc,
5156 struct drm_display_mode *mode,
5157 struct drm_display_mode *adjusted_mode,
5158 int x, int y,
5159 struct drm_framebuffer *old_fb)
5160{
5161 struct drm_device *dev = crtc->dev;
5162 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5164 int pipe = intel_crtc->pipe;
f564048e
EA		 5165 int ret;
5166
0b701d27
EA		 5167 drm_vblank_pre_modeset(dev, pipe);
5168
f564048e
EA		 5169 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5170 x, y, old_fb);
5171
0b701d27
EA		 5172 drm_vblank_post_modeset(dev, pipe);
5173
f564048e
EA		 5174 return ret;
5175}
5176
79e53945
JB		 5177/** Loads the palette/gamma unit for the CRTC with the prepared values */
5178void intel_crtc_load_lut(struct drm_crtc *crtc)
5179{
5180 struct drm_device *dev = crtc->dev;
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5183 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5184 int i;
5185
5186 /* The clocks have to be on to load the palette. */
5187 if (!crtc->enabled)
5188 return;
5189
f2b115e6 5190 /* use legacy palette for Ironlake */
bad720ff 5191 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5192 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5193
79e53945
JB		 5194 for (i = 0; i < 256; i++) {
5195 I915_WRITE(palreg + 4 * i,
5196 (intel_crtc->lut_r[i] << 16) |
5197 (intel_crtc->lut_g[i] << 8) |
5198 intel_crtc->lut_b[i]);
5199 }
5200}
5201
560b85bb
CW		 5202static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5203{
5204 struct drm_device *dev = crtc->dev;
5205 struct drm_i915_private *dev_priv = dev->dev_private;
5206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5207 bool visible = base != 0;
5208 u32 cntl;
5209
5210 if (intel_crtc->cursor_visible == visible)
5211 return;
5212
9db4a9c7 5213 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5214 if (visible) {
5215 /* On these chipsets we can only modify the base whilst
5216 * the cursor is disabled.
5217 */
9db4a9c7 5218 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5219
5220 cntl &= ~(CURSOR_FORMAT_MASK);
5221 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5222 cntl |= CURSOR_ENABLE |
5223 CURSOR_GAMMA_ENABLE |
5224 CURSOR_FORMAT_ARGB;
5225 } else
5226 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5227 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5228
5229 intel_crtc->cursor_visible = visible;
5230}
5231
5232static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5233{
5234 struct drm_device *dev = crtc->dev;
5235 struct drm_i915_private *dev_priv = dev->dev_private;
5236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237 int pipe = intel_crtc->pipe;
5238 bool visible = base != 0;
5239
5240 if (intel_crtc->cursor_visible != visible) {
548f245b 5241 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5242 if (base) {
5243 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5244 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5245 cntl |= pipe << 28; /* Connect to correct pipe */
5246 } else {
5247 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5248 cntl |= CURSOR_MODE_DISABLE;
5249 }
9db4a9c7 5250 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5251
5252 intel_crtc->cursor_visible = visible;
5253 }
5254 /* and commit changes on next vblank */
9db4a9c7 5255 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5256}
5257
cda4b7d3 5258/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5259static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5260 bool on)
cda4b7d3
CW		 5261{
5262 struct drm_device *dev = crtc->dev;
5263 struct drm_i915_private *dev_priv = dev->dev_private;
5264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5265 int pipe = intel_crtc->pipe;
5266 int x = intel_crtc->cursor_x;
5267 int y = intel_crtc->cursor_y;
560b85bb 5268 u32 base, pos;
cda4b7d3
CW		 5269 bool visible;
5270
5271 pos = 0;
5272
6b383a7f 5273 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5274 base = intel_crtc->cursor_addr;
5275 if (x > (int) crtc->fb->width)
5276 base = 0;
5277
5278 if (y > (int) crtc->fb->height)
5279 base = 0;
5280 } else
5281 base = 0;
5282
5283 if (x < 0) {
5284 if (x + intel_crtc->cursor_width < 0)
5285 base = 0;
5286
5287 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5288 x = -x;
5289 }
5290 pos |= x << CURSOR_X_SHIFT;
5291
5292 if (y < 0) {
5293 if (y + intel_crtc->cursor_height < 0)
5294 base = 0;
5295
5296 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5297 y = -y;
5298 }
5299 pos |= y << CURSOR_Y_SHIFT;
5300
5301 visible = base != 0;
560b85bb 5302 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5303 return;
5304
9db4a9c7 5305 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5306 if (IS_845G(dev) || IS_I865G(dev))
5307 i845_update_cursor(crtc, base);
5308 else
5309 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5310
5311 if (visible)
5312 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5313}
5314
79e53945 5315static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5316 struct drm_file *file,
79e53945
JB		 5317 uint32_t handle,
5318 uint32_t width, uint32_t height)
5319{
5320 struct drm_device *dev = crtc->dev;
5321 struct drm_i915_private *dev_priv = dev->dev_private;
5322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5323 struct drm_i915_gem_object *obj;
cda4b7d3 5324 uint32_t addr;
3f8bc370 5325 int ret;
79e53945 5326
28c97730 5327 DRM_DEBUG_KMS("\n");
79e53945
JB		 5328
5329 /* if we want to turn off the cursor ignore width and height */
5330 if (!handle) {
28c97730 5331 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5332 addr = 0;
05394f39 5333 obj = NULL;
5004417d 5334 mutex_lock(&dev->struct_mutex);
3f8bc370 5335 goto finish;
79e53945
JB		 5336 }
5337
5338 /* Currently we only support 64x64 cursors */
5339 if (width != 64 || height != 64) {
5340 DRM_ERROR("we currently only support 64x64 cursors\n");
5341 return -EINVAL;
5342 }
5343
05394f39 5344 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5345 if (&obj->base == NULL)
79e53945
JB		 5346 return -ENOENT;
5347
05394f39 5348 if (obj->base.size < width * height * 4) {
79e53945 5349 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5350 ret = -ENOMEM;
5351 goto fail;
79e53945
JB		 5352 }
5353
71acb5eb 5354 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5355 mutex_lock(&dev->struct_mutex);
b295d1b6 5356 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5357 if (obj->tiling_mode) {
5358 DRM_ERROR("cursor cannot be tiled\n");
5359 ret = -EINVAL;
5360 goto fail_locked;
5361 }
5362
05394f39 5363 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
71acb5eb
DA		 5364 if (ret) {
5365 DRM_ERROR("failed to pin cursor bo\n");
7f9872e0 5366 goto fail_locked;
71acb5eb 5367 }
e7b526bb 5368
05394f39 5369 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
e7b526bb
CW		 5370 if (ret) {
5371 DRM_ERROR("failed to move cursor bo into the GTT\n");
5372 goto fail_unpin;
5373 }
5374
d9e86c0e
CW		 5375 ret = i915_gem_object_put_fence(obj);
5376 if (ret) {
5377 DRM_ERROR("failed to move cursor bo into the GTT\n");
5378 goto fail_unpin;
5379 }
5380
05394f39 5381 addr = obj->gtt_offset;
71acb5eb 5382 } else {
6eeefaf3 5383 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5384 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5385 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5386 align);
71acb5eb
DA		 5387 if (ret) {
5388 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5389 goto fail_locked;
71acb5eb 5390 }
05394f39 5391 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5392 }
5393
a6c45cf0 5394 if (IS_GEN2(dev))
14b60391
JB		 5395 I915_WRITE(CURSIZE, (height << 12) | width);
5396
3f8bc370 5397 finish:
3f8bc370 5398 if (intel_crtc->cursor_bo) {
b295d1b6 5399 if (dev_priv->info->cursor_needs_physical) {
05394f39 5400 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5401 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5402 } else
5403 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5404 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5405 }
80824003 5406
7f9872e0 5407 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5408
5409 intel_crtc->cursor_addr = addr;
05394f39 5410 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5411 intel_crtc->cursor_width = width;
5412 intel_crtc->cursor_height = height;
5413
6b383a7f 5414 intel_crtc_update_cursor(crtc, true);
3f8bc370 5415
79e53945 5416 return 0;
e7b526bb 5417fail_unpin:
05394f39 5418 i915_gem_object_unpin(obj);
7f9872e0 5419fail_locked:
34b8686e 5420 mutex_unlock(&dev->struct_mutex);
bc9025bd 5421fail:
05394f39 5422 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5423 return ret;
79e53945
JB		 5424}
5425
5426static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5427{
79e53945 5428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5429
cda4b7d3
CW		 5430 intel_crtc->cursor_x = x;
5431 intel_crtc->cursor_y = y;
652c393a 5432
6b383a7f 5433 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5434
5435 return 0;
5436}
5437
5438/** Sets the color ramps on behalf of RandR */
5439void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5440 u16 blue, int regno)
5441{
5442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5443
5444 intel_crtc->lut_r[regno] = red >> 8;
5445 intel_crtc->lut_g[regno] = green >> 8;
5446 intel_crtc->lut_b[regno] = blue >> 8;
5447}
5448
b8c00ac5
DA		 5449void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5450 u16 *blue, int regno)
5451{
5452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5453
5454 *red = intel_crtc->lut_r[regno] << 8;
5455 *green = intel_crtc->lut_g[regno] << 8;
5456 *blue = intel_crtc->lut_b[regno] << 8;
5457}
5458
79e53945 5459static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5460 u16 *blue, uint32_t start, uint32_t size)
79e53945 5461{
7203425a 5462 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5464
7203425a 5465 for (i = start; i < end; i++) {
79e53945
JB		 5466 intel_crtc->lut_r[i] = red[i] >> 8;
5467 intel_crtc->lut_g[i] = green[i] >> 8;
5468 intel_crtc->lut_b[i] = blue[i] >> 8;
5469 }
5470
5471 intel_crtc_load_lut(crtc);
5472}
5473
5474/**
5475 * Get a pipe with a simple mode set on it for doing load-based monitor
5476 * detection.
5477 *
5478 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5479 * its requirements. The pipe will be connected to no other encoders.
79e53945 5480 *
c751ce4f 5481 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5482 * configured for it. In the future, it could choose to temporarily disable
5483 * some outputs to free up a pipe for its use.
5484 *
5485 * \return crtc, or NULL if no pipes are available.
5486 */
5487
5488/* VESA 640x480x72Hz mode to set on the pipe */
5489static struct drm_display_mode load_detect_mode = {
5490 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5491 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5492};
5493
d2dff872
CW		 5494static struct drm_framebuffer *
5495intel_framebuffer_create(struct drm_device *dev,
5496 struct drm_mode_fb_cmd *mode_cmd,
5497 struct drm_i915_gem_object *obj)
5498{
5499 struct intel_framebuffer *intel_fb;
5500 int ret;
5501
5502 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5503 if (!intel_fb) {
5504 drm_gem_object_unreference_unlocked(&obj->base);
5505 return ERR_PTR(-ENOMEM);
5506 }
5507
5508 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5509 if (ret) {
5510 drm_gem_object_unreference_unlocked(&obj->base);
5511 kfree(intel_fb);
5512 return ERR_PTR(ret);
5513 }
5514
5515 return &intel_fb->base;
5516}
5517
5518static u32
5519intel_framebuffer_pitch_for_width(int width, int bpp)
5520{
5521 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5522 return ALIGN(pitch, 64);
5523}
5524
5525static u32
5526intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5527{
5528 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5529 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5530}
5531
5532static struct drm_framebuffer *
5533intel_framebuffer_create_for_mode(struct drm_device *dev,
5534 struct drm_display_mode *mode,
5535 int depth, int bpp)
5536{
5537 struct drm_i915_gem_object *obj;
5538 struct drm_mode_fb_cmd mode_cmd;
5539
5540 obj = i915_gem_alloc_object(dev,
5541 intel_framebuffer_size_for_mode(mode, bpp));
5542 if (obj == NULL)
5543 return ERR_PTR(-ENOMEM);
5544
5545 mode_cmd.width = mode->hdisplay;
5546 mode_cmd.height = mode->vdisplay;
5547 mode_cmd.depth = depth;
5548 mode_cmd.bpp = bpp;
5549 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5550
5551 return intel_framebuffer_create(dev, &mode_cmd, obj);
5552}
5553
5554static struct drm_framebuffer *
5555mode_fits_in_fbdev(struct drm_device *dev,
5556 struct drm_display_mode *mode)
5557{
5558 struct drm_i915_private *dev_priv = dev->dev_private;
5559 struct drm_i915_gem_object *obj;
5560 struct drm_framebuffer *fb;
5561
5562 if (dev_priv->fbdev == NULL)
5563 return NULL;
5564
5565 obj = dev_priv->fbdev->ifb.obj;
5566 if (obj == NULL)
5567 return NULL;
5568
5569 fb = &dev_priv->fbdev->ifb.base;
5570 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5571 fb->bits_per_pixel))
5572 return NULL;
5573
5574 if (obj->base.size < mode->vdisplay * fb->pitch)
5575 return NULL;
5576
5577 return fb;
5578}
5579
7173188d
CW		 5580bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5581 struct drm_connector *connector,
5582 struct drm_display_mode *mode,
8261b191 5583 struct intel_load_detect_pipe *old)
79e53945
JB		 5584{
5585 struct intel_crtc *intel_crtc;
5586 struct drm_crtc *possible_crtc;
4ef69c7a 5587 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5588 struct drm_crtc *crtc = NULL;
5589 struct drm_device *dev = encoder->dev;
d2dff872 5590 struct drm_framebuffer *old_fb;
79e53945
JB		 5591 int i = -1;
5592
d2dff872
CW		 5593 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5594 connector->base.id, drm_get_connector_name(connector),
5595 encoder->base.id, drm_get_encoder_name(encoder));
5596
79e53945
JB		 5597 /*
5598 * Algorithm gets a little messy:
7a5e4805 5599 *
79e53945
JB		 5600 * - if the connector already has an assigned crtc, use it (but make
5601 * sure it's on first)
7a5e4805 5602 *
79e53945
JB		 5603 * - try to find the first unused crtc that can drive this connector,
5604 * and use that if we find one
79e53945
JB		 5605 */
5606
5607 /* See if we already have a CRTC for this connector */
5608 if (encoder->crtc) {
5609 crtc = encoder->crtc;
8261b191 5610
79e53945 5611 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5612 old->dpms_mode = intel_crtc->dpms_mode;
5613 old->load_detect_temp = false;
5614
5615 /* Make sure the crtc and connector are running */
79e53945 5616 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5617 struct drm_encoder_helper_funcs *encoder_funcs;
5618 struct drm_crtc_helper_funcs *crtc_funcs;
5619
79e53945
JB		 5620 crtc_funcs = crtc->helper_private;
5621 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5622
5623 encoder_funcs = encoder->helper_private;
79e53945
JB		 5624 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5625 }
8261b191 5626
7173188d 5627 return true;
79e53945
JB		 5628 }
5629
5630 /* Find an unused one (if possible) */
5631 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5632 i++;
5633 if (!(encoder->possible_crtcs & (1 << i)))
5634 continue;
5635 if (!possible_crtc->enabled) {
5636 crtc = possible_crtc;
5637 break;
5638 }
79e53945
JB		 5639 }
5640
5641 /*
5642 * If we didn't find an unused CRTC, don't use any.
5643 */
5644 if (!crtc) {
7173188d
CW		 5645 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5646 return false;
79e53945
JB		 5647 }
5648
5649 encoder->crtc = crtc;
c1c43977 5650 connector->encoder = encoder;
79e53945
JB		 5651
5652 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5653 old->dpms_mode = intel_crtc->dpms_mode;
5654 old->load_detect_temp = true;
d2dff872 5655 old->release_fb = NULL;
79e53945 5656
6492711d
CW		 5657 if (!mode)
5658 mode = &load_detect_mode;
79e53945 5659
d2dff872
CW		 5660 old_fb = crtc->fb;
5661
5662 /* We need a framebuffer large enough to accommodate all accesses
5663 * that the plane may generate whilst we perform load detection.
5664 * We can not rely on the fbcon either being present (we get called
5665 * during its initialisation to detect all boot displays, or it may
5666 * not even exist) or that it is large enough to satisfy the
5667 * requested mode.
5668 */
5669 crtc->fb = mode_fits_in_fbdev(dev, mode);
5670 if (crtc->fb == NULL) {
5671 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5672 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5673 old->release_fb = crtc->fb;
5674 } else
5675 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5676 if (IS_ERR(crtc->fb)) {
5677 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5678 crtc->fb = old_fb;
5679 return false;
5680 }
5681
5682 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5683 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5684 if (old->release_fb)
5685 old->release_fb->funcs->destroy(old->release_fb);
5686 crtc->fb = old_fb;
6492711d 5687 return false;
79e53945 5688 }
7173188d 5689
79e53945 5690 /* let the connector get through one full cycle before testing */
9d0498a2 5691 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5692
7173188d 5693 return true;
79e53945
JB		 5694}
5695
c1c43977 5696void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5697 struct drm_connector *connector,
5698 struct intel_load_detect_pipe *old)
79e53945 5699{
4ef69c7a 5700 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5701 struct drm_device *dev = encoder->dev;
5702 struct drm_crtc *crtc = encoder->crtc;
5703 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5704 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5705
d2dff872
CW		 5706 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5707 connector->base.id, drm_get_connector_name(connector),
5708 encoder->base.id, drm_get_encoder_name(encoder));
5709
8261b191 5710 if (old->load_detect_temp) {
c1c43977 5711 connector->encoder = NULL;
79e53945 5712 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5713
5714 if (old->release_fb)
5715 old->release_fb->funcs->destroy(old->release_fb);
5716
0622a53c 5717 return;
79e53945
JB		 5718 }
5719
c751ce4f 5720 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5721 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5722 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5723 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5724 }
5725}
5726
5727/* Returns the clock of the currently programmed mode of the given pipe. */
5728static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5729{
5730 struct drm_i915_private *dev_priv = dev->dev_private;
5731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5732 int pipe = intel_crtc->pipe;
548f245b 5733 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5734 u32 fp;
5735 intel_clock_t clock;
5736
5737 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5738 fp = I915_READ(FP0(pipe));
79e53945 5739 else
39adb7a5 5740 fp = I915_READ(FP1(pipe));
79e53945
JB		 5741
5742 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5743 if (IS_PINEVIEW(dev)) {
5744 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5745 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5746 } else {
5747 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5748 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5749 }
5750
a6c45cf0 5751 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5752 if (IS_PINEVIEW(dev))
5753 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5754 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5755 else
5756 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5757 DPLL_FPA01_P1_POST_DIV_SHIFT);
5758
5759 switch (dpll & DPLL_MODE_MASK) {
5760 case DPLLB_MODE_DAC_SERIAL:
5761 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5762 5 : 10;
5763 break;
5764 case DPLLB_MODE_LVDS:
5765 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5766 7 : 14;
5767 break;
5768 default:
28c97730 5769 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5770 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5771 return 0;
5772 }
5773
5774 /* XXX: Handle the 100Mhz refclk */
2177832f 5775 intel_clock(dev, 96000, &clock);
79e53945
JB		 5776 } else {
5777 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5778
5779 if (is_lvds) {
5780 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5781 DPLL_FPA01_P1_POST_DIV_SHIFT);
5782 clock.p2 = 14;
5783
5784 if ((dpll & PLL_REF_INPUT_MASK) ==
5785 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5786 /* XXX: might not be 66MHz */
2177832f 5787 intel_clock(dev, 66000, &clock);
79e53945 5788 } else
2177832f 5789 intel_clock(dev, 48000, &clock);
79e53945
JB		 5790 } else {
5791 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5792 clock.p1 = 2;
5793 else {
5794 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5795 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5796 }
5797 if (dpll & PLL_P2_DIVIDE_BY_4)
5798 clock.p2 = 4;
5799 else
5800 clock.p2 = 2;
5801
2177832f 5802 intel_clock(dev, 48000, &clock);
79e53945
JB		 5803 }
5804 }
5805
5806 /* XXX: It would be nice to validate the clocks, but we can't reuse
5807 * i830PllIsValid() because it relies on the xf86_config connector
5808 * configuration being accurate, which it isn't necessarily.
5809 */
5810
5811 return clock.dot;
5812}
5813
5814/** Returns the currently programmed mode of the given pipe. */
5815struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5816 struct drm_crtc *crtc)
5817{
548f245b 5818 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5820 int pipe = intel_crtc->pipe;
5821 struct drm_display_mode *mode;
548f245b
JB		 5822 int htot = I915_READ(HTOTAL(pipe));
5823 int hsync = I915_READ(HSYNC(pipe));
5824 int vtot = I915_READ(VTOTAL(pipe));
5825 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5826
5827 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5828 if (!mode)
5829 return NULL;
5830
5831 mode->clock = intel_crtc_clock_get(dev, crtc);
5832 mode->hdisplay = (htot & 0xffff) + 1;
5833 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5834 mode->hsync_start = (hsync & 0xffff) + 1;
5835 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5836 mode->vdisplay = (vtot & 0xffff) + 1;
5837 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5838 mode->vsync_start = (vsync & 0xffff) + 1;
5839 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5840
5841 drm_mode_set_name(mode);
5842 drm_mode_set_crtcinfo(mode, 0);
5843
5844 return mode;
5845}
5846
652c393a
JB		 5847#define GPU_IDLE_TIMEOUT 500 /* ms */
5848
5849/* When this timer fires, we've been idle for awhile */
5850static void intel_gpu_idle_timer(unsigned long arg)
5851{
5852 struct drm_device *dev = (struct drm_device *)arg;
5853 drm_i915_private_t *dev_priv = dev->dev_private;
5854
ff7ea4c0
CW		 5855 if (!list_empty(&dev_priv->mm.active_list)) {
5856 /* Still processing requests, so just re-arm the timer. */
5857 mod_timer(&dev_priv->idle_timer, jiffies +
5858 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5859 return;
5860 }
652c393a 5861
ff7ea4c0 5862 dev_priv->busy = false;
01dfba93 5863 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5864}
5865
652c393a
JB		 5866#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5867
5868static void intel_crtc_idle_timer(unsigned long arg)
5869{
5870 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5871 struct drm_crtc *crtc = &intel_crtc->base;
5872 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5873 struct intel_framebuffer *intel_fb;
652c393a 5874
ff7ea4c0
CW		 5875 intel_fb = to_intel_framebuffer(crtc->fb);
5876 if (intel_fb && intel_fb->obj->active) {
5877 /* The framebuffer is still being accessed by the GPU. */
5878 mod_timer(&intel_crtc->idle_timer, jiffies +
5879 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5880 return;
5881 }
652c393a 5882
ff7ea4c0 5883 intel_crtc->busy = false;
01dfba93 5884 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5885}
5886
3dec0095 5887static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5888{
5889 struct drm_device *dev = crtc->dev;
5890 drm_i915_private_t *dev_priv = dev->dev_private;
5891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5892 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5893 int dpll_reg = DPLL(pipe);
5894 int dpll;
652c393a 5895
bad720ff 5896 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5897 return;
5898
5899 if (!dev_priv->lvds_downclock_avail)
5900 return;
5901
dbdc6479 5902 dpll = I915_READ(dpll_reg);
652c393a 5903 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5904 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 5905
5906 /* Unlock panel regs */
dbdc6479
JB		 5907 I915_WRITE(PP_CONTROL,
5908 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 5909
5910 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5911 I915_WRITE(dpll_reg, dpll);
9d0498a2 5912 intel_wait_for_vblank(dev, pipe);
dbdc6479 5913
652c393a
JB		 5914 dpll = I915_READ(dpll_reg);
5915 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5916 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5917
5918 /* ...and lock them again */
5919 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5920 }
5921
5922 /* Schedule downclock */
3dec0095
DV		 5923 mod_timer(&intel_crtc->idle_timer, jiffies +
5924 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5925}
5926
5927static void intel_decrease_pllclock(struct drm_crtc *crtc)
5928{
5929 struct drm_device *dev = crtc->dev;
5930 drm_i915_private_t *dev_priv = dev->dev_private;
5931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5932 int pipe = intel_crtc->pipe;
9db4a9c7 5933 int dpll_reg = DPLL(pipe);
652c393a
JB		 5934 int dpll = I915_READ(dpll_reg);
5935
bad720ff 5936 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5937 return;
5938
5939 if (!dev_priv->lvds_downclock_avail)
5940 return;
5941
5942 /*
5943 * Since this is called by a timer, we should never get here in
5944 * the manual case.
5945 */
5946 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 5947 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 5948
5949 /* Unlock panel regs */
4a655f04
JB		 5950 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5951 PANEL_UNLOCK_REGS);
652c393a
JB		 5952
5953 dpll |= DISPLAY_RATE_SELECT_FPA1;
5954 I915_WRITE(dpll_reg, dpll);
9d0498a2 5955 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5956 dpll = I915_READ(dpll_reg);
5957 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5958 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5959
5960 /* ...and lock them again */
5961 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5962 }
5963
5964}
5965
5966/**
5967 * intel_idle_update - adjust clocks for idleness
5968 * @work: work struct
5969 *
5970 * Either the GPU or display (or both) went idle. Check the busy status
5971 * here and adjust the CRTC and GPU clocks as necessary.
5972 */
5973static void intel_idle_update(struct work_struct *work)
5974{
5975 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5976 idle_work);
5977 struct drm_device *dev = dev_priv->dev;
5978 struct drm_crtc *crtc;
5979 struct intel_crtc *intel_crtc;
5980
5981 if (!i915_powersave)
5982 return;
5983
5984 mutex_lock(&dev->struct_mutex);
5985
7648fa99
JB		 5986 i915_update_gfx_val(dev_priv);
5987
652c393a
JB		 5988 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5989 /* Skip inactive CRTCs */
5990 if (!crtc->fb)
5991 continue;
5992
5993 intel_crtc = to_intel_crtc(crtc);
5994 if (!intel_crtc->busy)
5995 intel_decrease_pllclock(crtc);
5996 }
5997
45ac22c8 5998
652c393a
JB		 5999 mutex_unlock(&dev->struct_mutex);
6000}
6001
6002/**
6003 * intel_mark_busy - mark the GPU and possibly the display busy
6004 * @dev: drm device
6005 * @obj: object we're operating on
6006 *
6007 * Callers can use this function to indicate that the GPU is busy processing
6008 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6009 * buffer), we'll also mark the display as busy, so we know to increase its
6010 * clock frequency.
6011 */
05394f39 6012void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6013{
6014 drm_i915_private_t *dev_priv = dev->dev_private;
6015 struct drm_crtc *crtc = NULL;
6016 struct intel_framebuffer *intel_fb;
6017 struct intel_crtc *intel_crtc;
6018
5e17ee74
ZW		 6019 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6020 return;
6021
18b2190c 6022 if (!dev_priv->busy)
28cf798f 6023 dev_priv->busy = true;
18b2190c 6024 else
28cf798f
CW		 6025 mod_timer(&dev_priv->idle_timer, jiffies +
6026 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6027
6028 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6029 if (!crtc->fb)
6030 continue;
6031
6032 intel_crtc = to_intel_crtc(crtc);
6033 intel_fb = to_intel_framebuffer(crtc->fb);
6034 if (intel_fb->obj == obj) {
6035 if (!intel_crtc->busy) {
6036 /* Non-busy -> busy, upclock */
3dec0095 6037 intel_increase_pllclock(crtc);
652c393a
JB		 6038 intel_crtc->busy = true;
6039 } else {
6040 /* Busy -> busy, put off timer */
6041 mod_timer(&intel_crtc->idle_timer, jiffies +
6042 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6043 }
6044 }
6045 }
6046}
6047
79e53945
JB		 6048static void intel_crtc_destroy(struct drm_crtc *crtc)
6049{
6050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6051 struct drm_device *dev = crtc->dev;
6052 struct intel_unpin_work *work;
6053 unsigned long flags;
6054
6055 spin_lock_irqsave(&dev->event_lock, flags);
6056 work = intel_crtc->unpin_work;
6057 intel_crtc->unpin_work = NULL;
6058 spin_unlock_irqrestore(&dev->event_lock, flags);
6059
6060 if (work) {
6061 cancel_work_sync(&work->work);
6062 kfree(work);
6063 }
79e53945
JB		 6064
6065 drm_crtc_cleanup(crtc);
67e77c5a 6066
79e53945
JB		 6067 kfree(intel_crtc);
6068}
6069
6b95a207
KH		 6070static void intel_unpin_work_fn(struct work_struct *__work)
6071{
6072 struct intel_unpin_work *work =
6073 container_of(__work, struct intel_unpin_work, work);
6074
6075 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6076 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6077 drm_gem_object_unreference(&work->pending_flip_obj->base);
6078 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6079
6b95a207
KH		 6080 mutex_unlock(&work->dev->struct_mutex);
6081 kfree(work);
6082}
6083
1afe3e9d 6084static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6085 struct drm_crtc *crtc)
6b95a207
KH		 6086{
6087 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6089 struct intel_unpin_work *work;
05394f39 6090 struct drm_i915_gem_object *obj;
6b95a207 6091 struct drm_pending_vblank_event *e;
49b14a5c 6092 struct timeval tnow, tvbl;
6b95a207
KH		 6093 unsigned long flags;
6094
6095 /* Ignore early vblank irqs */
6096 if (intel_crtc == NULL)
6097 return;
6098
49b14a5c
MK		 6099 do_gettimeofday(&tnow);
6100
6b95a207
KH		 6101 spin_lock_irqsave(&dev->event_lock, flags);
6102 work = intel_crtc->unpin_work;
6103 if (work == NULL || !work->pending) {
6104 spin_unlock_irqrestore(&dev->event_lock, flags);
6105 return;
6106 }
6107
6108 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6109
6110 if (work->event) {
6111 e = work->event;
49b14a5c 6112 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6113
6114 /* Called before vblank count and timestamps have
6115 * been updated for the vblank interval of flip
6116 * completion? Need to increment vblank count and
6117 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6118 * to account for this. We assume this happened if we
6119 * get called over 0.9 frame durations after the last
6120 * timestamped vblank.
6121 *
6122 * This calculation can not be used with vrefresh rates
6123 * below 5Hz (10Hz to be on the safe side) without
6124 * promoting to 64 integers.
0af7e4df 6125 */
49b14a5c
MK		 6126 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6127 9 * crtc->framedur_ns) {
0af7e4df 6128 e->event.sequence++;
49b14a5c
MK		 6129 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6130 crtc->framedur_ns);
0af7e4df
MK		 6131 }
6132
49b14a5c
MK		 6133 e->event.tv_sec = tvbl.tv_sec;
6134 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6135
6b95a207
KH		 6136 list_add_tail(&e->base.link,
6137 &e->base.file_priv->event_list);
6138 wake_up_interruptible(&e->base.file_priv->event_wait);
6139 }
6140
0af7e4df
MK		 6141 drm_vblank_put(dev, intel_crtc->pipe);
6142
6b95a207
KH		 6143 spin_unlock_irqrestore(&dev->event_lock, flags);
6144
05394f39 6145 obj = work->old_fb_obj;
d9e86c0e 6146
e59f2bac 6147 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6148 &obj->pending_flip.counter);
6149 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6150 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6151
6b95a207 6152 schedule_work(&work->work);
e5510fac
JB		 6153
6154 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6155}
6156
1afe3e9d
JB		 6157void intel_finish_page_flip(struct drm_device *dev, int pipe)
6158{
6159 drm_i915_private_t *dev_priv = dev->dev_private;
6160 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6161
49b14a5c 6162 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6163}
6164
6165void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6166{
6167 drm_i915_private_t *dev_priv = dev->dev_private;
6168 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6169
49b14a5c 6170 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6171}
6172
6b95a207
KH		 6173void intel_prepare_page_flip(struct drm_device *dev, int plane)
6174{
6175 drm_i915_private_t *dev_priv = dev->dev_private;
6176 struct intel_crtc *intel_crtc =
6177 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6178 unsigned long flags;
6179
6180 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6181 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6182 if ((++intel_crtc->unpin_work->pending) > 1)
6183 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6184 } else {
6185 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6186 }
6b95a207
KH		 6187 spin_unlock_irqrestore(&dev->event_lock, flags);
6188}
6189
6190static int intel_crtc_page_flip(struct drm_crtc *crtc,
6191 struct drm_framebuffer *fb,
6192 struct drm_pending_vblank_event *event)
6193{
6194 struct drm_device *dev = crtc->dev;
6195 struct drm_i915_private *dev_priv = dev->dev_private;
6196 struct intel_framebuffer *intel_fb;
05394f39 6197 struct drm_i915_gem_object *obj;
6b95a207
KH		 6198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6199 struct intel_unpin_work *work;
be9a3dbf 6200 unsigned long flags, offset;
52e68630 6201 int pipe = intel_crtc->pipe;
20f0cd55 6202 u32 pf, pipesrc;
52e68630 6203 int ret;
6b95a207
KH		 6204
6205 work = kzalloc(sizeof *work, GFP_KERNEL);
6206 if (work == NULL)
6207 return -ENOMEM;
6208
6b95a207
KH		 6209 work->event = event;
6210 work->dev = crtc->dev;
6211 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6212 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6213 INIT_WORK(&work->work, intel_unpin_work_fn);
6214
6215 /* We borrow the event spin lock for protecting unpin_work */
6216 spin_lock_irqsave(&dev->event_lock, flags);
6217 if (intel_crtc->unpin_work) {
6218 spin_unlock_irqrestore(&dev->event_lock, flags);
6219 kfree(work);
468f0b44
CW		 6220
6221 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6222 return -EBUSY;
6223 }
6224 intel_crtc->unpin_work = work;
6225 spin_unlock_irqrestore(&dev->event_lock, flags);
6226
6227 intel_fb = to_intel_framebuffer(fb);
6228 obj = intel_fb->obj;
6229
468f0b44 6230 mutex_lock(&dev->struct_mutex);
1ec14ad3 6231 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
96b099fd
CW		 6232 if (ret)
6233 goto cleanup_work;
6b95a207 6234
75dfca80 6235 /* Reference the objects for the scheduled work. */
05394f39
CW		 6236 drm_gem_object_reference(&work->old_fb_obj->base);
6237 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6238
6239 crtc->fb = fb;
96b099fd
CW		 6240
6241 ret = drm_vblank_get(dev, intel_crtc->pipe);
6242 if (ret)
6243 goto cleanup_objs;
6244
c7f9f9a8
CW		 6245 if (IS_GEN3(dev) || IS_GEN2(dev)) {
6246 u32 flip_mask;
48b956c5 6247
c7f9f9a8
CW		 6248 /* Can't queue multiple flips, so wait for the previous
6249 * one to finish before executing the next.
6250 */
e1f99ce6
CW		 6251 ret = BEGIN_LP_RING(2);
6252 if (ret)
6253 goto cleanup_objs;
6254
c7f9f9a8
CW		 6255 if (intel_crtc->plane)
6256 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6257 else
6258 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6259 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6260 OUT_RING(MI_NOOP);
6146b3d6
DV		 6261 ADVANCE_LP_RING();
6262 }
83f7fd05 6263
e1f99ce6 6264 work->pending_flip_obj = obj;
e1f99ce6 6265
4e5359cd
SF		 6266 work->enable_stall_check = true;
6267
be9a3dbf 6268 /* Offset into the new buffer for cases of shared fbs between CRTCs */
52e68630 6269 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
be9a3dbf 6270
e1f99ce6
CW		 6271 ret = BEGIN_LP_RING(4);
6272 if (ret)
6273 goto cleanup_objs;
6274
6275 /* Block clients from rendering to the new back buffer until
6276 * the flip occurs and the object is no longer visible.
6277 */
05394f39 6278 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6
CW		 6279
6280 switch (INTEL_INFO(dev)->gen) {
52e68630 6281 case 2:
1afe3e9d
JB		 6282 OUT_RING(MI_DISPLAY_FLIP |
6283 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6284 OUT_RING(fb->pitch);
05394f39 6285 OUT_RING(obj->gtt_offset + offset);
52e68630
CW		 6286 OUT_RING(MI_NOOP);
6287 break;
6288
6289 case 3:
1afe3e9d
JB		 6290 OUT_RING(MI_DISPLAY_FLIP_I915 |
6291 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6292 OUT_RING(fb->pitch);
05394f39 6293 OUT_RING(obj->gtt_offset + offset);
22fd0fab 6294 OUT_RING(MI_NOOP);
52e68630
CW		 6295 break;
6296
6297 case 4:
6298 case 5:
6299 /* i965+ uses the linear or tiled offsets from the
6300 * Display Registers (which do not change across a page-flip)
6301 * so we need only reprogram the base address.
6302 */
69d0b96c
DV		 6303 OUT_RING(MI_DISPLAY_FLIP |
6304 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6305 OUT_RING(fb->pitch);
05394f39 6306 OUT_RING(obj->gtt_offset | obj->tiling_mode);
52e68630
CW		 6307
6308 /* XXX Enabling the panel-fitter across page-flip is so far
6309 * untested on non-native modes, so ignore it for now.
6310 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6311 */
6312 pf = 0;
9db4a9c7 6313 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
52e68630
CW		 6314 OUT_RING(pf | pipesrc);
6315 break;
6316
6317 case 6:
6318 OUT_RING(MI_DISPLAY_FLIP |
6319 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
05394f39
CW		 6320 OUT_RING(fb->pitch | obj->tiling_mode);
6321 OUT_RING(obj->gtt_offset);
52e68630 6322
9db4a9c7
JB		 6323 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6324 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
52e68630
CW		 6325 OUT_RING(pf | pipesrc);
6326 break;
22fd0fab 6327 }
6b95a207
KH		 6328 ADVANCE_LP_RING();
6329
6330 mutex_unlock(&dev->struct_mutex);
6331
e5510fac
JB		 6332 trace_i915_flip_request(intel_crtc->plane, obj);
6333
6b95a207 6334 return 0;
96b099fd
CW		 6335
6336cleanup_objs:
05394f39
CW		 6337 drm_gem_object_unreference(&work->old_fb_obj->base);
6338 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6339cleanup_work:
6340 mutex_unlock(&dev->struct_mutex);
6341
6342 spin_lock_irqsave(&dev->event_lock, flags);
6343 intel_crtc->unpin_work = NULL;
6344 spin_unlock_irqrestore(&dev->event_lock, flags);
6345
6346 kfree(work);
6347
6348 return ret;
6b95a207
KH		 6349}
6350
47f1c6c9
CW		 6351static void intel_sanitize_modesetting(struct drm_device *dev,
6352 int pipe, int plane)
6353{
6354 struct drm_i915_private *dev_priv = dev->dev_private;
6355 u32 reg, val;
6356
6357 if (HAS_PCH_SPLIT(dev))
6358 return;
6359
6360 /* Who knows what state these registers were left in by the BIOS or
6361 * grub?
6362 *
6363 * If we leave the registers in a conflicting state (e.g. with the
6364 * display plane reading from the other pipe than the one we intend
6365 * to use) then when we attempt to teardown the active mode, we will
6366 * not disable the pipes and planes in the correct order -- leaving
6367 * a plane reading from a disabled pipe and possibly leading to
6368 * undefined behaviour.
6369 */
6370
6371 reg = DSPCNTR(plane);
6372 val = I915_READ(reg);
6373
6374 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6375 return;
6376 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6377 return;
6378
6379 /* This display plane is active and attached to the other CPU pipe. */
6380 pipe = !pipe;
6381
6382 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6383 intel_disable_plane(dev_priv, plane, pipe);
6384 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6385}
79e53945 6386
f6e5b160
CW		 6387static void intel_crtc_reset(struct drm_crtc *crtc)
6388{
6389 struct drm_device *dev = crtc->dev;
6390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6391
6392 /* Reset flags back to the 'unknown' status so that they
6393 * will be correctly set on the initial modeset.
6394 */
6395 intel_crtc->dpms_mode = -1;
6396
6397 /* We need to fix up any BIOS configuration that conflicts with
6398 * our expectations.
6399 */
6400 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6401}
6402
6403static struct drm_crtc_helper_funcs intel_helper_funcs = {
6404 .dpms = intel_crtc_dpms,
6405 .mode_fixup = intel_crtc_mode_fixup,
6406 .mode_set = intel_crtc_mode_set,
6407 .mode_set_base = intel_pipe_set_base,
6408 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6409 .load_lut = intel_crtc_load_lut,
6410 .disable = intel_crtc_disable,
6411};
6412
6413static const struct drm_crtc_funcs intel_crtc_funcs = {
6414 .reset = intel_crtc_reset,
6415 .cursor_set = intel_crtc_cursor_set,
6416 .cursor_move = intel_crtc_cursor_move,
6417 .gamma_set = intel_crtc_gamma_set,
6418 .set_config = drm_crtc_helper_set_config,
6419 .destroy = intel_crtc_destroy,
6420 .page_flip = intel_crtc_page_flip,
6421};
6422
b358d0a6 6423static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6424{
22fd0fab 6425 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6426 struct intel_crtc *intel_crtc;
6427 int i;
6428
6429 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6430 if (intel_crtc == NULL)
6431 return;
6432
6433 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6434
6435 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6436 for (i = 0; i < 256; i++) {
6437 intel_crtc->lut_r[i] = i;
6438 intel_crtc->lut_g[i] = i;
6439 intel_crtc->lut_b[i] = i;
6440 }
6441
80824003
JB		 6442 /* Swap pipes & planes for FBC on pre-965 */
6443 intel_crtc->pipe = pipe;
6444 intel_crtc->plane = pipe;
e2e767ab 6445 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6446 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6447 intel_crtc->plane = !pipe;
80824003
JB		 6448 }
6449
22fd0fab
JB		 6450 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6451 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6452 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6453 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6454
5d1d0cc8 6455 intel_crtc_reset(&intel_crtc->base);
04dbff52 6456 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7e7d76c3
JB		 6457
6458 if (HAS_PCH_SPLIT(dev)) {
6459 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6460 intel_helper_funcs.commit = ironlake_crtc_commit;
6461 } else {
6462 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6463 intel_helper_funcs.commit = i9xx_crtc_commit;
6464 }
6465
79e53945
JB		 6466 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6467
652c393a
JB		 6468 intel_crtc->busy = false;
6469
6470 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6471 (unsigned long)intel_crtc);
79e53945
JB		 6472}
6473
08d7b3d1 6474int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6475 struct drm_file *file)
08d7b3d1
CW		 6476{
6477 drm_i915_private_t *dev_priv = dev->dev_private;
6478 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6479 struct drm_mode_object *drmmode_obj;
6480 struct intel_crtc *crtc;
08d7b3d1
CW		 6481
6482 if (!dev_priv) {
6483 DRM_ERROR("called with no initialization\n");
6484 return -EINVAL;
6485 }
6486
c05422d5
DV		 6487 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6488 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6489
c05422d5 6490 if (!drmmode_obj) {
08d7b3d1
CW		 6491 DRM_ERROR("no such CRTC id\n");
6492 return -EINVAL;
6493 }
6494
c05422d5
DV		 6495 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6496 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6497
c05422d5 6498 return 0;
08d7b3d1
CW		 6499}
6500
c5e4df33 6501static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6502{
4ef69c7a 6503 struct intel_encoder *encoder;
79e53945 6504 int index_mask = 0;
79e53945
JB		 6505 int entry = 0;
6506
4ef69c7a
CW		 6507 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6508 if (type_mask & encoder->clone_mask)
79e53945
JB		 6509 index_mask |= (1 << entry);
6510 entry++;
6511 }
4ef69c7a 6512
79e53945
JB		 6513 return index_mask;
6514}
6515
4d302442
CW		 6516static bool has_edp_a(struct drm_device *dev)
6517{
6518 struct drm_i915_private *dev_priv = dev->dev_private;
6519
6520 if (!IS_MOBILE(dev))
6521 return false;
6522
6523 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6524 return false;
6525
6526 if (IS_GEN5(dev) &&
6527 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6528 return false;
6529
6530 return true;
6531}
6532
79e53945
JB		 6533static void intel_setup_outputs(struct drm_device *dev)
6534{
725e30ad 6535 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6536 struct intel_encoder *encoder;
cb0953d7 6537 bool dpd_is_edp = false;
c5d1b51d 6538 bool has_lvds = false;
79e53945 6539
541998a1 6540 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 6541 has_lvds = intel_lvds_init(dev);
6542 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6543 /* disable the panel fitter on everything but LVDS */
6544 I915_WRITE(PFIT_CONTROL, 0);
6545 }
79e53945 6546
bad720ff 6547 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6548 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6549
4d302442 6550 if (has_edp_a(dev))
32f9d658
ZW		 6551 intel_dp_init(dev, DP_A);
6552
cb0953d7
AJ		 6553 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6554 intel_dp_init(dev, PCH_DP_D);
6555 }
6556
6557 intel_crt_init(dev);
6558
6559 if (HAS_PCH_SPLIT(dev)) {
6560 int found;
6561
30ad48b7 6562 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 6563 /* PCH SDVOB multiplex with HDMIB */
6564 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 6565 if (!found)
6566 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6567 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6568 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6569 }
6570
6571 if (I915_READ(HDMIC) & PORT_DETECTED)
6572 intel_hdmi_init(dev, HDMIC);
6573
6574 if (I915_READ(HDMID) & PORT_DETECTED)
6575 intel_hdmi_init(dev, HDMID);
6576
5eb08b69
ZW		 6577 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6578 intel_dp_init(dev, PCH_DP_C);
6579
cb0953d7 6580 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6581 intel_dp_init(dev, PCH_DP_D);
6582
103a196f 6583 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6584 bool found = false;
7d57382e 6585
725e30ad 6586 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6587 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 6588 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 6589 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6590 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6591 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6592 }
27185ae1 6593
b01f2c3a
JB		 6594 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6595 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6596 intel_dp_init(dev, DP_B);
b01f2c3a 6597 }
725e30ad 6598 }
13520b05
KH		 6599
6600 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6601
b01f2c3a
JB		 6602 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6603 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 6604 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 6605 }
27185ae1
ML		 6606
6607 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6608
b01f2c3a
JB		 6609 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6610 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6611 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6612 }
6613 if (SUPPORTS_INTEGRATED_DP(dev)) {
6614 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6615 intel_dp_init(dev, DP_C);
b01f2c3a 6616 }
725e30ad 6617 }
27185ae1 6618
b01f2c3a
JB		 6619 if (SUPPORTS_INTEGRATED_DP(dev) &&
6620 (I915_READ(DP_D) & DP_DETECTED)) {
6621 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6622 intel_dp_init(dev, DP_D);
b01f2c3a 6623 }
bad720ff 6624 } else if (IS_GEN2(dev))
79e53945
JB		 6625 intel_dvo_init(dev);
6626
103a196f 6627 if (SUPPORTS_TV(dev))
79e53945
JB		 6628 intel_tv_init(dev);
6629
4ef69c7a
CW		 6630 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6631 encoder->base.possible_crtcs = encoder->crtc_mask;
6632 encoder->base.possible_clones =
6633 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6634 }
47356eb6
CW		 6635
6636 intel_panel_setup_backlight(dev);
2c7111db
CW		 6637
6638 /* disable all the possible outputs/crtcs before entering KMS mode */
6639 drm_helper_disable_unused_functions(dev);
79e53945
JB		 6640}
6641
6642static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6643{
6644 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6645
6646 drm_framebuffer_cleanup(fb);
05394f39 6647 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6648
6649 kfree(intel_fb);
6650}
6651
6652static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6653 struct drm_file *file,
79e53945
JB		 6654 unsigned int *handle)
6655{
6656 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6657 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6658
05394f39 6659 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6660}
6661
6662static const struct drm_framebuffer_funcs intel_fb_funcs = {
6663 .destroy = intel_user_framebuffer_destroy,
6664 .create_handle = intel_user_framebuffer_create_handle,
6665};
6666
38651674
DA		 6667int intel_framebuffer_init(struct drm_device *dev,
6668 struct intel_framebuffer *intel_fb,
6669 struct drm_mode_fb_cmd *mode_cmd,
05394f39 6670 struct drm_i915_gem_object *obj)
79e53945 6671{
79e53945
JB		 6672 int ret;
6673
05394f39 6674 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6675 return -EINVAL;
6676
6677 if (mode_cmd->pitch & 63)
6678 return -EINVAL;
6679
6680 switch (mode_cmd->bpp) {
6681 case 8:
6682 case 16:
6683 case 24:
6684 case 32:
6685 break;
6686 default:
6687 return -EINVAL;
6688 }
6689
79e53945
JB		 6690 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6691 if (ret) {
6692 DRM_ERROR("framebuffer init failed %d\n", ret);
6693 return ret;
6694 }
6695
6696 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6697 intel_fb->obj = obj;
79e53945
JB		 6698 return 0;
6699}
6700
79e53945
JB		 6701static struct drm_framebuffer *
6702intel_user_framebuffer_create(struct drm_device *dev,
6703 struct drm_file *filp,
6704 struct drm_mode_fb_cmd *mode_cmd)
6705{
05394f39 6706 struct drm_i915_gem_object *obj;
79e53945 6707
05394f39 6708 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 6709 if (&obj->base == NULL)
cce13ff7 6710 return ERR_PTR(-ENOENT);
79e53945 6711
d2dff872 6712 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6713}
6714
79e53945 6715static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6716 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6717 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6718};
6719
05394f39 6720static struct drm_i915_gem_object *
aa40d6bb 6721intel_alloc_context_page(struct drm_device *dev)
9ea8d059 6722{
05394f39 6723 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 6724 int ret;
6725
2c34b850
BW		 6726 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6727
aa40d6bb
ZN		 6728 ctx = i915_gem_alloc_object(dev, 4096);
6729 if (!ctx) {
9ea8d059
CW		 6730 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6731 return NULL;
6732 }
6733
75e9e915 6734 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 6735 if (ret) {
6736 DRM_ERROR("failed to pin power context: %d\n", ret);
6737 goto err_unref;
6738 }
6739
aa40d6bb 6740 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 6741 if (ret) {
6742 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6743 goto err_unpin;
6744 }
9ea8d059 6745
aa40d6bb 6746 return ctx;
9ea8d059
CW		 6747
6748err_unpin:
aa40d6bb 6749 i915_gem_object_unpin(ctx);
9ea8d059 6750err_unref:
05394f39 6751 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 6752 mutex_unlock(&dev->struct_mutex);
6753 return NULL;
6754}
6755
7648fa99
JB		 6756bool ironlake_set_drps(struct drm_device *dev, u8 val)
6757{
6758 struct drm_i915_private *dev_priv = dev->dev_private;
6759 u16 rgvswctl;
6760
6761 rgvswctl = I915_READ16(MEMSWCTL);
6762 if (rgvswctl & MEMCTL_CMD_STS) {
6763 DRM_DEBUG("gpu busy, RCS change rejected\n");
6764 return false; /* still busy with another command */
6765 }
6766
6767 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6768 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6769 I915_WRITE16(MEMSWCTL, rgvswctl);
6770 POSTING_READ16(MEMSWCTL);
6771
6772 rgvswctl |= MEMCTL_CMD_STS;
6773 I915_WRITE16(MEMSWCTL, rgvswctl);
6774
6775 return true;
6776}
6777
f97108d1
JB		 6778void ironlake_enable_drps(struct drm_device *dev)
6779{
6780 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 6781 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 6782 u8 fmax, fmin, fstart, vstart;
f97108d1 6783
ea056c14
JB		 6784 /* Enable temp reporting */
6785 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6786 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6787
f97108d1
JB		 6788 /* 100ms RC evaluation intervals */
6789 I915_WRITE(RCUPEI, 100000);
6790 I915_WRITE(RCDNEI, 100000);
6791
6792 /* Set max/min thresholds to 90ms and 80ms respectively */
6793 I915_WRITE(RCBMAXAVG, 90000);
6794 I915_WRITE(RCBMINAVG, 80000);
6795
6796 I915_WRITE(MEMIHYST, 1);
6797
6798 /* Set up min, max, and cur for interrupt handling */
6799 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6800 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6801 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6802 MEMMODE_FSTART_SHIFT;
7648fa99 6803
f97108d1
JB		 6804 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6805 PXVFREQ_PX_SHIFT;
6806
80dbf4b7 6807 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 6808 dev_priv->fstart = fstart;
6809
80dbf4b7 6810 dev_priv->max_delay = fstart;
f97108d1
JB		 6811 dev_priv->min_delay = fmin;
6812 dev_priv->cur_delay = fstart;
6813
80dbf4b7
JB		 6814 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6815 fmax, fmin, fstart);
7648fa99 6816
f97108d1
JB		 6817 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6818
6819 /*
6820 * Interrupts will be enabled in ironlake_irq_postinstall
6821 */
6822
6823 I915_WRITE(VIDSTART, vstart);
6824 POSTING_READ(VIDSTART);
6825
6826 rgvmodectl |= MEMMODE_SWMODE_EN;
6827 I915_WRITE(MEMMODECTL, rgvmodectl);
6828
481b6af3 6829 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 6830 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 6831 msleep(1);
6832
7648fa99 6833 ironlake_set_drps(dev, fstart);
f97108d1 6834
7648fa99
JB		 6835 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6836 I915_READ(0x112e0);
6837 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6838 dev_priv->last_count2 = I915_READ(0x112f4);
6839 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 6840}
6841
6842void ironlake_disable_drps(struct drm_device *dev)
6843{
6844 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 6845 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 6846
6847 /* Ack interrupts, disable EFC interrupt */
6848 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6849 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6850 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6851 I915_WRITE(DEIIR, DE_PCU_EVENT);
6852 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6853
6854 /* Go back to the starting frequency */
7648fa99 6855 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 6856 msleep(1);
6857 rgvswctl |= MEMCTL_CMD_STS;
6858 I915_WRITE(MEMSWCTL, rgvswctl);
6859 msleep(1);
6860
6861}
6862
3b8d8d91
JB		 6863void gen6_set_rps(struct drm_device *dev, u8 val)
6864{
6865 struct drm_i915_private *dev_priv = dev->dev_private;
6866 u32 swreq;
6867
6868 swreq = (val & 0x3ff) << 25;
6869 I915_WRITE(GEN6_RPNSWREQ, swreq);
6870}
6871
6872void gen6_disable_rps(struct drm_device *dev)
6873{
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875
6876 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6877 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6878 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 6879
6880 spin_lock_irq(&dev_priv->rps_lock);
6881 dev_priv->pm_iir = 0;
6882 spin_unlock_irq(&dev_priv->rps_lock);
6883
3b8d8d91
JB		 6884 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6885}
6886
7648fa99
JB		 6887static unsigned long intel_pxfreq(u32 vidfreq)
6888{
6889 unsigned long freq;
6890 int div = (vidfreq & 0x3f0000) >> 16;
6891 int post = (vidfreq & 0x3000) >> 12;
6892 int pre = (vidfreq & 0x7);
6893
6894 if (!pre)
6895 return 0;
6896
6897 freq = ((div * 133333) / ((1<<post) * pre));
6898
6899 return freq;
6900}
6901
6902void intel_init_emon(struct drm_device *dev)
6903{
6904 struct drm_i915_private *dev_priv = dev->dev_private;
6905 u32 lcfuse;
6906 u8 pxw[16];
6907 int i;
6908
6909 /* Disable to program */
6910 I915_WRITE(ECR, 0);
6911 POSTING_READ(ECR);
6912
6913 /* Program energy weights for various events */
6914 I915_WRITE(SDEW, 0x15040d00);
6915 I915_WRITE(CSIEW0, 0x007f0000);
6916 I915_WRITE(CSIEW1, 0x1e220004);
6917 I915_WRITE(CSIEW2, 0x04000004);
6918
6919 for (i = 0; i < 5; i++)
6920 I915_WRITE(PEW + (i * 4), 0);
6921 for (i = 0; i < 3; i++)
6922 I915_WRITE(DEW + (i * 4), 0);
6923
6924 /* Program P-state weights to account for frequency power adjustment */
6925 for (i = 0; i < 16; i++) {
6926 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6927 unsigned long freq = intel_pxfreq(pxvidfreq);
6928 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6929 PXVFREQ_PX_SHIFT;
6930 unsigned long val;
6931
6932 val = vid * vid;
6933 val *= (freq / 1000);
6934 val *= 255;
6935 val /= (127*127*900);
6936 if (val > 0xff)
6937 DRM_ERROR("bad pxval: %ld\n", val);
6938 pxw[i] = val;
6939 }
6940 /* Render standby states get 0 weight */
6941 pxw[14] = 0;
6942 pxw[15] = 0;
6943
6944 for (i = 0; i < 4; i++) {
6945 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6946 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6947 I915_WRITE(PXW + (i * 4), val);
6948 }
6949
6950 /* Adjust magic regs to magic values (more experimental results) */
6951 I915_WRITE(OGW0, 0);
6952 I915_WRITE(OGW1, 0);
6953 I915_WRITE(EG0, 0x00007f00);
6954 I915_WRITE(EG1, 0x0000000e);
6955 I915_WRITE(EG2, 0x000e0000);
6956 I915_WRITE(EG3, 0x68000300);
6957 I915_WRITE(EG4, 0x42000000);
6958 I915_WRITE(EG5, 0x00140031);
6959 I915_WRITE(EG6, 0);
6960 I915_WRITE(EG7, 0);
6961
6962 for (i = 0; i < 8; i++)
6963 I915_WRITE(PXWL + (i * 4), 0);
6964
6965 /* Enable PMON + select events */
6966 I915_WRITE(ECR, 0x80000019);
6967
6968 lcfuse = I915_READ(LCFUSE02);
6969
6970 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6971}
6972
3b8d8d91 6973void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 6974{
a6044e23
JB		 6975 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6976 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 6977 u32 pcu_mbox, rc6_mask = 0;
a6044e23 6978 int cur_freq, min_freq, max_freq;
8fd26859
CW		 6979 int i;
6980
6981 /* Here begins a magic sequence of register writes to enable
6982 * auto-downclocking.
6983 *
6984 * Perhaps there might be some value in exposing these to
6985 * userspace...
6986 */
6987 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 6988 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 6989 gen6_gt_force_wake_get(dev_priv);
8fd26859 6990
3b8d8d91 6991 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 6992 I915_WRITE(GEN6_RC_CONTROL, 0);
6993
6994 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6995 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6996 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6997 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6998 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6999
7000 for (i = 0; i < I915_NUM_RINGS; i++)
7001 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7002
7003 I915_WRITE(GEN6_RC_SLEEP, 0);
7004 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7005 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7006 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7007 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7008
7df8721b
JB		 7009 if (i915_enable_rc6)
7010 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7011 GEN6_RC_CTL_RC6_ENABLE;
7012
8fd26859 7013 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7014 rc6_mask |
9c3d2f7f 7015 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7016 GEN6_RC_CTL_HW_ENABLE);
7017
3b8d8d91 7018 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7019 GEN6_FREQUENCY(10) |
7020 GEN6_OFFSET(0) |
7021 GEN6_AGGRESSIVE_TURBO);
7022 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7023 GEN6_FREQUENCY(12));
7024
7025 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7026 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7027 18 << 24 |
7028 6 << 16);
ccab5c82
JB		 7029 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7030 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7031 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7032 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7033 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7034 I915_WRITE(GEN6_RP_CONTROL,
7035 GEN6_RP_MEDIA_TURBO |
7036 GEN6_RP_USE_NORMAL_FREQ |
7037 GEN6_RP_MEDIA_IS_GFX |
7038 GEN6_RP_ENABLE |
ccab5c82
JB		 7039 GEN6_RP_UP_BUSY_AVG |
7040 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7041
7042 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7043 500))
7044 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7045
7046 I915_WRITE(GEN6_PCODE_DATA, 0);
7047 I915_WRITE(GEN6_PCODE_MAILBOX,
7048 GEN6_PCODE_READY |
7049 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7050 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7051 500))
7052 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7053
a6044e23
JB		 7054 min_freq = (rp_state_cap & 0xff0000) >> 16;
7055 max_freq = rp_state_cap & 0xff;
7056 cur_freq = (gt_perf_status & 0xff00) >> 8;
7057
7058 /* Check for overclock support */
7059 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7060 500))
7061 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7062 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7063 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7064 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7065 500))
7066 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7067 if (pcu_mbox & (1<<31)) { /* OC supported */
7068 max_freq = pcu_mbox & 0xff;
e281fcaa 7069 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7070 }
7071
7072 /* In units of 100MHz */
7073 dev_priv->max_delay = max_freq;
7074 dev_priv->min_delay = min_freq;
7075 dev_priv->cur_delay = cur_freq;
7076
8fd26859
CW		 7077 /* requires MSI enabled */
7078 I915_WRITE(GEN6_PMIER,
7079 GEN6_PM_MBOX_EVENT |
7080 GEN6_PM_THERMAL_EVENT |
7081 GEN6_PM_RP_DOWN_TIMEOUT |
7082 GEN6_PM_RP_UP_THRESHOLD |
7083 GEN6_PM_RP_DOWN_THRESHOLD |
7084 GEN6_PM_RP_UP_EI_EXPIRED |
7085 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7086 spin_lock_irq(&dev_priv->rps_lock);
7087 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7088 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7089 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7090 /* enable all PM interrupts */
7091 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7092
fcca7926 7093 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7094 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7095}
7096
0cdab21f 7097void intel_enable_clock_gating(struct drm_device *dev)
652c393a
JB		 7098{
7099 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7100 int pipe;
652c393a
JB		 7101
7102 /*
7103 * Disable clock gating reported to work incorrectly according to the
7104 * specs, but enable as much else as we can.
7105 */
bad720ff 7106 if (HAS_PCH_SPLIT(dev)) {
8956c8bb
EA		 7107 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7108
f00a3ddf 7109 if (IS_GEN5(dev)) {
8956c8bb 7110 /* Required for FBC */
1ffa325b
JB		 7111 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7112 DPFCRUNIT_CLOCK_GATE_DISABLE |
7113 DPFDUNIT_CLOCK_GATE_DISABLE;
8956c8bb
EA		 7114 /* Required for CxSR */
7115 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7116
7117 I915_WRITE(PCH_3DCGDIS0,
7118 MARIUNIT_CLOCK_GATE_DISABLE |
7119 SVSMUNIT_CLOCK_GATE_DISABLE);
06f37751
EA		 7120 I915_WRITE(PCH_3DCGDIS1,
7121 VFMUNIT_CLOCK_GATE_DISABLE);
8956c8bb
EA		 7122 }
7123
7124 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7f8a8569 7125
382b0936
JB		 7126 /*
7127 * On Ibex Peak and Cougar Point, we need to disable clock
7128 * gating for the panel power sequencer or it will fail to
7129 * start up when no ports are active.
7130 */
7131 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7132
7f8a8569
ZW		 7133 /*
7134 * According to the spec the following bits should be set in
7135 * order to enable memory self-refresh
7136 * The bit 22/21 of 0x42004
7137 * The bit 5 of 0x42020
7138 * The bit 15 of 0x45000
7139 */
f00a3ddf 7140 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7141 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7142 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7143 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7144 I915_WRITE(ILK_DSPCLK_GATE,
7145 (I915_READ(ILK_DSPCLK_GATE) |
7146 ILK_DPARB_CLK_GATE));
7147 I915_WRITE(DISP_ARB_CTL,
7148 (I915_READ(DISP_ARB_CTL) |
7149 DISP_FBC_WM_DIS));
1398261a
YL		 7150 I915_WRITE(WM3_LP_ILK, 0);
7151 I915_WRITE(WM2_LP_ILK, 0);
7152 I915_WRITE(WM1_LP_ILK, 0);
7f8a8569 7153 }
b52eb4dc
ZY		 7154 /*
7155 * Based on the document from hardware guys the following bits
7156 * should be set unconditionally in order to enable FBC.
7157 * The bit 22 of 0x42000
7158 * The bit 22 of 0x42004
7159 * The bit 7,8,9 of 0x42020.
7160 */
7161 if (IS_IRONLAKE_M(dev)) {
7162 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7163 I915_READ(ILK_DISPLAY_CHICKEN1) |
7164 ILK_FBCQ_DIS);
7165 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7166 I915_READ(ILK_DISPLAY_CHICKEN2) |
7167 ILK_DPARB_GATE);
7168 I915_WRITE(ILK_DSPCLK_GATE,
7169 I915_READ(ILK_DSPCLK_GATE) |
7170 ILK_DPFC_DIS1 |
7171 ILK_DPFC_DIS2 |
7172 ILK_CLK_FBC);
7173 }
de6e2eaf 7174
67e92af0
EA		 7175 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7176 I915_READ(ILK_DISPLAY_CHICKEN2) |
7177 ILK_ELPIN_409_SELECT);
7178
de6e2eaf
EA		 7179 if (IS_GEN5(dev)) {
7180 I915_WRITE(_3D_CHICKEN2,
7181 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7182 _3D_CHICKEN2_WM_READ_PIPELINED);
7183 }
8fd26859 7184
1398261a
YL		 7185 if (IS_GEN6(dev)) {
7186 I915_WRITE(WM3_LP_ILK, 0);
7187 I915_WRITE(WM2_LP_ILK, 0);
7188 I915_WRITE(WM1_LP_ILK, 0);
7189
7190 /*
7191 * According to the spec the following bits should be
7192 * set in order to enable memory self-refresh and fbc:
7193 * The bit21 and bit22 of 0x42000
7194 * The bit21 and bit22 of 0x42004
7195 * The bit5 and bit7 of 0x42020
7196 * The bit14 of 0x70180
7197 * The bit14 of 0x71180
7198 */
7199 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7200 I915_READ(ILK_DISPLAY_CHICKEN1) |
7201 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7202 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7203 I915_READ(ILK_DISPLAY_CHICKEN2) |
7204 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7205 I915_WRITE(ILK_DSPCLK_GATE,
7206 I915_READ(ILK_DSPCLK_GATE) |
7207 ILK_DPARB_CLK_GATE |
7208 ILK_DPFD_CLK_GATE);
7209
9db4a9c7
JB		 7210 for_each_pipe(pipe)
7211 I915_WRITE(DSPCNTR(pipe),
7212 I915_READ(DSPCNTR(pipe)) |
7213 DISPPLANE_TRICKLE_FEED_DISABLE);
1398261a 7214 }
c03342fa 7215 } else if (IS_G4X(dev)) {
652c393a
JB		 7216 uint32_t dspclk_gate;
7217 I915_WRITE(RENCLK_GATE_D1, 0);
7218 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7219 GS_UNIT_CLOCK_GATE_DISABLE |
7220 CL_UNIT_CLOCK_GATE_DISABLE);
7221 I915_WRITE(RAMCLK_GATE_D, 0);
7222 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7223 OVRUNIT_CLOCK_GATE_DISABLE |
7224 OVCUNIT_CLOCK_GATE_DISABLE;
7225 if (IS_GM45(dev))
7226 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7227 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
a6c45cf0 7228 } else if (IS_CRESTLINE(dev)) {
652c393a
JB		 7229 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7230 I915_WRITE(RENCLK_GATE_D2, 0);
7231 I915_WRITE(DSPCLK_GATE_D, 0);
7232 I915_WRITE(RAMCLK_GATE_D, 0);
7233 I915_WRITE16(DEUC, 0);
a6c45cf0 7234 } else if (IS_BROADWATER(dev)) {
652c393a
JB		 7235 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7236 I965_RCC_CLOCK_GATE_DISABLE |
7237 I965_RCPB_CLOCK_GATE_DISABLE |
7238 I965_ISC_CLOCK_GATE_DISABLE |
7239 I965_FBC_CLOCK_GATE_DISABLE);
7240 I915_WRITE(RENCLK_GATE_D2, 0);
a6c45cf0 7241 } else if (IS_GEN3(dev)) {
652c393a
JB		 7242 u32 dstate = I915_READ(D_STATE);
7243
7244 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7245 DSTATE_DOT_CLOCK_GATING;
7246 I915_WRITE(D_STATE, dstate);
f0f8a9ce 7247 } else if (IS_I85X(dev) || IS_I865G(dev)) {
652c393a
JB		 7248 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7249 } else if (IS_I830(dev)) {
7250 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7251 }
7252}
7253
ac668088 7254static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7255{
7256 struct drm_i915_private *dev_priv = dev->dev_private;
7257
7258 if (dev_priv->renderctx) {
ac668088
CW		 7259 i915_gem_object_unpin(dev_priv->renderctx);
7260 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7261 dev_priv->renderctx = NULL;
7262 }
7263
7264 if (dev_priv->pwrctx) {
ac668088
CW		 7265 i915_gem_object_unpin(dev_priv->pwrctx);
7266 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7267 dev_priv->pwrctx = NULL;
7268 }
7269}
7270
7271static void ironlake_disable_rc6(struct drm_device *dev)
7272{
7273 struct drm_i915_private *dev_priv = dev->dev_private;
7274
7275 if (I915_READ(PWRCTXA)) {
7276 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7277 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7278 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7279 50);
0cdab21f
CW		 7280
7281 I915_WRITE(PWRCTXA, 0);
7282 POSTING_READ(PWRCTXA);
7283
ac668088
CW		 7284 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7285 POSTING_READ(RSTDBYCTL);
0cdab21f 7286 }
ac668088 7287
99507307 7288 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7289}
7290
ac668088 7291static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7292{
7293 struct drm_i915_private *dev_priv = dev->dev_private;
7294
ac668088
CW		 7295 if (dev_priv->renderctx == NULL)
7296 dev_priv->renderctx = intel_alloc_context_page(dev);
7297 if (!dev_priv->renderctx)
7298 return -ENOMEM;
7299
7300 if (dev_priv->pwrctx == NULL)
7301 dev_priv->pwrctx = intel_alloc_context_page(dev);
7302 if (!dev_priv->pwrctx) {
7303 ironlake_teardown_rc6(dev);
7304 return -ENOMEM;
7305 }
7306
7307 return 0;
d5bb081b
JB		 7308}
7309
7310void ironlake_enable_rc6(struct drm_device *dev)
7311{
7312 struct drm_i915_private *dev_priv = dev->dev_private;
7313 int ret;
7314
ac668088
CW		 7315 /* rc6 disabled by default due to repeated reports of hanging during
7316 * boot and resume.
7317 */
7318 if (!i915_enable_rc6)
7319 return;
7320
2c34b850 7321 mutex_lock(&dev->struct_mutex);
ac668088 7322 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 7323 if (ret) {
7324 mutex_unlock(&dev->struct_mutex);
ac668088 7325 return;
2c34b850 7326 }
ac668088 7327
d5bb081b
JB		 7328 /*
7329 * GPU can automatically power down the render unit if given a page
7330 * to save state.
7331 */
7332 ret = BEGIN_LP_RING(6);
7333 if (ret) {
ac668088 7334 ironlake_teardown_rc6(dev);
2c34b850 7335 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7336 return;
7337 }
ac668088 7338
d5bb081b
JB		 7339 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7340 OUT_RING(MI_SET_CONTEXT);
7341 OUT_RING(dev_priv->renderctx->gtt_offset |
7342 MI_MM_SPACE_GTT |
7343 MI_SAVE_EXT_STATE_EN |
7344 MI_RESTORE_EXT_STATE_EN |
7345 MI_RESTORE_INHIBIT);
7346 OUT_RING(MI_SUSPEND_FLUSH);
7347 OUT_RING(MI_NOOP);
7348 OUT_RING(MI_FLUSH);
7349 ADVANCE_LP_RING();
7350
4a246cfc
BW		 7351 /*
7352 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7353 * does an implicit flush, combined with MI_FLUSH above, it should be
7354 * safe to assume that renderctx is valid
7355 */
7356 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7357 if (ret) {
7358 DRM_ERROR("failed to enable ironlake power power savings\n");
7359 ironlake_teardown_rc6(dev);
7360 mutex_unlock(&dev->struct_mutex);
7361 return;
7362 }
7363
d5bb081b
JB		 7364 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7365 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 7366 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7367}
7368
ac668088 7369
e70236a8
JB		 7370/* Set up chip specific display functions */
7371static void intel_init_display(struct drm_device *dev)
7372{
7373 struct drm_i915_private *dev_priv = dev->dev_private;
7374
7375 /* We always want a DPMS function */
f564048e 7376 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7377 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e
EA		 7378 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7379 } else {
e70236a8 7380 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e
EA		 7381 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7382 }
e70236a8 7383
ee5382ae 7384 if (I915_HAS_FBC(dev)) {
9c04f015 7385 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 7386 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7387 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7388 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7389 } else if (IS_GM45(dev)) {
74dff282
JB		 7390 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7391 dev_priv->display.enable_fbc = g4x_enable_fbc;
7392 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 7393 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 7394 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7395 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7396 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7397 }
74dff282 7398 /* 855GM needs testing */
e70236a8
JB		 7399 }
7400
7401 /* Returns the core display clock speed */
f2b115e6 7402 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 7403 dev_priv->display.get_display_clock_speed =
7404 i945_get_display_clock_speed;
7405 else if (IS_I915G(dev))
7406 dev_priv->display.get_display_clock_speed =
7407 i915_get_display_clock_speed;
f2b115e6 7408 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7409 dev_priv->display.get_display_clock_speed =
7410 i9xx_misc_get_display_clock_speed;
7411 else if (IS_I915GM(dev))
7412 dev_priv->display.get_display_clock_speed =
7413 i915gm_get_display_clock_speed;
7414 else if (IS_I865G(dev))
7415 dev_priv->display.get_display_clock_speed =
7416 i865_get_display_clock_speed;
f0f8a9ce 7417 else if (IS_I85X(dev))
e70236a8
JB		 7418 dev_priv->display.get_display_clock_speed =
7419 i855_get_display_clock_speed;
7420 else /* 852, 830 */
7421 dev_priv->display.get_display_clock_speed =
7422 i830_get_display_clock_speed;
7423
7424 /* For FIFO watermark updates */
7f8a8569 7425 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7426 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7427 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7428 dev_priv->display.update_wm = ironlake_update_wm;
7429 else {
7430 DRM_DEBUG_KMS("Failed to get proper latency. "
7431 "Disable CxSR\n");
7432 dev_priv->display.update_wm = NULL;
1398261a
YL		 7433 }
7434 } else if (IS_GEN6(dev)) {
7435 if (SNB_READ_WM0_LATENCY()) {
7436 dev_priv->display.update_wm = sandybridge_update_wm;
7437 } else {
7438 DRM_DEBUG_KMS("Failed to read display plane latency. "
7439 "Disable CxSR\n");
7440 dev_priv->display.update_wm = NULL;
7f8a8569
ZW		 7441 }
7442 } else
7443 dev_priv->display.update_wm = NULL;
7444 } else if (IS_PINEVIEW(dev)) {
d4294342 7445 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 7446 dev_priv->is_ddr3,
d4294342
ZY		 7447 dev_priv->fsb_freq,
7448 dev_priv->mem_freq)) {
7449 DRM_INFO("failed to find known CxSR latency "
95534263 7450 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 7451 "disabling CxSR\n",
95534263 7452 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 7453 dev_priv->fsb_freq, dev_priv->mem_freq);
7454 /* Disable CxSR and never update its watermark again */
7455 pineview_disable_cxsr(dev);
7456 dev_priv->display.update_wm = NULL;
7457 } else
7458 dev_priv->display.update_wm = pineview_update_wm;
7459 } else if (IS_G4X(dev))
e70236a8 7460 dev_priv->display.update_wm = g4x_update_wm;
a6c45cf0 7461 else if (IS_GEN4(dev))
e70236a8 7462 dev_priv->display.update_wm = i965_update_wm;
a6c45cf0 7463 else if (IS_GEN3(dev)) {
e70236a8
JB		 7464 dev_priv->display.update_wm = i9xx_update_wm;
7465 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8f4695ed
AJ		 7466 } else if (IS_I85X(dev)) {
7467 dev_priv->display.update_wm = i9xx_update_wm;
7468 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
e70236a8 7469 } else {
8f4695ed
AJ		 7470 dev_priv->display.update_wm = i830_update_wm;
7471 if (IS_845G(dev))
e70236a8
JB		 7472 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7473 else
7474 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8
JB		 7475 }
7476}
7477
b690e96c
JB		 7478/*
7479 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7480 * resume, or other times. This quirk makes sure that's the case for
7481 * affected systems.
7482 */
7483static void quirk_pipea_force (struct drm_device *dev)
7484{
7485 struct drm_i915_private *dev_priv = dev->dev_private;
7486
7487 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7488 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7489}
7490
7491struct intel_quirk {
7492 int device;
7493 int subsystem_vendor;
7494 int subsystem_device;
7495 void (*hook)(struct drm_device *dev);
7496};
7497
7498struct intel_quirk intel_quirks[] = {
7499 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7500 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7501 /* HP Mini needs pipe A force quirk (LP: #322104) */
7502 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7503
7504 /* Thinkpad R31 needs pipe A force quirk */
7505 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7506 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7507 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7508
7509 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7510 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7511 /* ThinkPad X40 needs pipe A force quirk */
7512
7513 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7514 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7515
7516 /* 855 & before need to leave pipe A & dpll A up */
7517 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7518 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7519};
7520
7521static void intel_init_quirks(struct drm_device *dev)
7522{
7523 struct pci_dev *d = dev->pdev;
7524 int i;
7525
7526 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7527 struct intel_quirk *q = &intel_quirks[i];
7528
7529 if (d->device == q->device &&
7530 (d->subsystem_vendor == q->subsystem_vendor ||
7531 q->subsystem_vendor == PCI_ANY_ID) &&
7532 (d->subsystem_device == q->subsystem_device ||
7533 q->subsystem_device == PCI_ANY_ID))
7534 q->hook(dev);
7535 }
7536}
7537
9cce37f4
JB		 7538/* Disable the VGA plane that we never use */
7539static void i915_disable_vga(struct drm_device *dev)
7540{
7541 struct drm_i915_private *dev_priv = dev->dev_private;
7542 u8 sr1;
7543 u32 vga_reg;
7544
7545 if (HAS_PCH_SPLIT(dev))
7546 vga_reg = CPU_VGACNTRL;
7547 else
7548 vga_reg = VGACNTRL;
7549
7550 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7551 outb(1, VGA_SR_INDEX);
7552 sr1 = inb(VGA_SR_DATA);
7553 outb(sr1 | 1<<5, VGA_SR_DATA);
7554 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7555 udelay(300);
7556
7557 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7558 POSTING_READ(vga_reg);
7559}
7560
79e53945
JB		 7561void intel_modeset_init(struct drm_device *dev)
7562{
652c393a 7563 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 7564 int i;
7565
7566 drm_mode_config_init(dev);
7567
7568 dev->mode_config.min_width = 0;
7569 dev->mode_config.min_height = 0;
7570
7571 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7572
b690e96c
JB		 7573 intel_init_quirks(dev);
7574
e70236a8
JB		 7575 intel_init_display(dev);
7576
a6c45cf0
CW		 7577 if (IS_GEN2(dev)) {
7578 dev->mode_config.max_width = 2048;
7579 dev->mode_config.max_height = 2048;
7580 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7581 dev->mode_config.max_width = 4096;
7582 dev->mode_config.max_height = 4096;
79e53945 7583 } else {
a6c45cf0
CW		 7584 dev->mode_config.max_width = 8192;
7585 dev->mode_config.max_height = 8192;
79e53945 7586 }
35c3047a 7587 dev->mode_config.fb_base = dev->agp->base;
79e53945 7588
28c97730 7589 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7590 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7591
a3524f1b 7592 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 7593 intel_crtc_init(dev, i);
7594 }
7595
2c7111db
CW		 7596 /* Just disable it once at startup */
7597 i915_disable_vga(dev);
79e53945 7598 intel_setup_outputs(dev);
652c393a 7599
0cdab21f 7600 intel_enable_clock_gating(dev);
652c393a 7601
7648fa99 7602 if (IS_IRONLAKE_M(dev)) {
f97108d1 7603 ironlake_enable_drps(dev);
7648fa99
JB		 7604 intel_init_emon(dev);
7605 }
f97108d1 7606
3b8d8d91
JB		 7607 if (IS_GEN6(dev))
7608 gen6_enable_rps(dev_priv);
7609
652c393a
JB		 7610 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7611 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7612 (unsigned long)dev);
2c7111db
CW		 7613}
7614
7615void intel_modeset_gem_init(struct drm_device *dev)
7616{
7617 if (IS_IRONLAKE_M(dev))
7618 ironlake_enable_rc6(dev);
02e792fb
DV		 7619
7620 intel_setup_overlay(dev);
79e53945
JB		 7621}
7622
7623void intel_modeset_cleanup(struct drm_device *dev)
7624{
652c393a
JB		 7625 struct drm_i915_private *dev_priv = dev->dev_private;
7626 struct drm_crtc *crtc;
7627 struct intel_crtc *intel_crtc;
7628
f87ea761 7629 drm_kms_helper_poll_fini(dev);
652c393a
JB		 7630 mutex_lock(&dev->struct_mutex);
7631
723bfd70
JB		 7632 intel_unregister_dsm_handler();
7633
7634
652c393a
JB		 7635 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7636 /* Skip inactive CRTCs */
7637 if (!crtc->fb)
7638 continue;
7639
7640 intel_crtc = to_intel_crtc(crtc);
3dec0095 7641 intel_increase_pllclock(crtc);
652c393a
JB		 7642 }
7643
e70236a8
JB		 7644 if (dev_priv->display.disable_fbc)
7645 dev_priv->display.disable_fbc(dev);
7646
f97108d1
JB		 7647 if (IS_IRONLAKE_M(dev))
7648 ironlake_disable_drps(dev);
3b8d8d91
JB		 7649 if (IS_GEN6(dev))
7650 gen6_disable_rps(dev);
f97108d1 7651
d5bb081b
JB		 7652 if (IS_IRONLAKE_M(dev))
7653 ironlake_disable_rc6(dev);
0cdab21f 7654
69341a5e
KH		 7655 mutex_unlock(&dev->struct_mutex);
7656
6c0d9350
DV		 7657 /* Disable the irq before mode object teardown, for the irq might
7658 * enqueue unpin/hotplug work. */
7659 drm_irq_uninstall(dev);
7660 cancel_work_sync(&dev_priv->hotplug_work);
7661
3dec0095
DV		 7662 /* Shut off idle work before the crtcs get freed. */
7663 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7664 intel_crtc = to_intel_crtc(crtc);
7665 del_timer_sync(&intel_crtc->idle_timer);
7666 }
7667 del_timer_sync(&dev_priv->idle_timer);
7668 cancel_work_sync(&dev_priv->idle_work);
7669
79e53945
JB		 7670 drm_mode_config_cleanup(dev);
7671}
7672
f1c79df3
ZW		 7673/*
7674 * Return which encoder is currently attached for connector.
7675 */
df0e9248 7676struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7677{
df0e9248
CW		 7678 return &intel_attached_encoder(connector)->base;
7679}
f1c79df3 7680
df0e9248
CW		 7681void intel_connector_attach_encoder(struct intel_connector *connector,
7682 struct intel_encoder *encoder)
7683{
7684 connector->encoder = encoder;
7685 drm_mode_connector_attach_encoder(&connector->base,
7686 &encoder->base);
79e53945 7687}
28d52043
DA		 7688
7689/*
7690 * set vga decode state - true == enable VGA decode
7691 */
7692int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7693{
7694 struct drm_i915_private *dev_priv = dev->dev_private;
7695 u16 gmch_ctrl;
7696
7697 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7698 if (state)
7699 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7700 else
7701 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7702 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7703 return 0;
7704}
c4a1d9e4
CW		 7705
7706#ifdef CONFIG_DEBUG_FS
7707#include <linux/seq_file.h>
7708
7709struct intel_display_error_state {
7710 struct intel_cursor_error_state {
7711 u32 control;
7712 u32 position;
7713 u32 base;
7714 u32 size;
7715 } cursor[2];
7716
7717 struct intel_pipe_error_state {
7718 u32 conf;
7719 u32 source;
7720
7721 u32 htotal;
7722 u32 hblank;
7723 u32 hsync;
7724 u32 vtotal;
7725 u32 vblank;
7726 u32 vsync;
7727 } pipe[2];
7728
7729 struct intel_plane_error_state {
7730 u32 control;
7731 u32 stride;
7732 u32 size;
7733 u32 pos;
7734 u32 addr;
7735 u32 surface;
7736 u32 tile_offset;
7737 } plane[2];
7738};
7739
7740struct intel_display_error_state *
7741intel_display_capture_error_state(struct drm_device *dev)
7742{
7743 drm_i915_private_t *dev_priv = dev->dev_private;
7744 struct intel_display_error_state *error;
7745 int i;
7746
7747 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7748 if (error == NULL)
7749 return NULL;
7750
7751 for (i = 0; i < 2; i++) {
7752 error->cursor[i].control = I915_READ(CURCNTR(i));
7753 error->cursor[i].position = I915_READ(CURPOS(i));
7754 error->cursor[i].base = I915_READ(CURBASE(i));
7755
7756 error->plane[i].control = I915_READ(DSPCNTR(i));
7757 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7758 error->plane[i].size = I915_READ(DSPSIZE(i));
7759 error->plane[i].pos= I915_READ(DSPPOS(i));
7760 error->plane[i].addr = I915_READ(DSPADDR(i));
7761 if (INTEL_INFO(dev)->gen >= 4) {
7762 error->plane[i].surface = I915_READ(DSPSURF(i));
7763 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7764 }
7765
7766 error->pipe[i].conf = I915_READ(PIPECONF(i));
7767 error->pipe[i].source = I915_READ(PIPESRC(i));
7768 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7769 error->pipe[i].hblank = I915_READ(HBLANK(i));
7770 error->pipe[i].hsync = I915_READ(HSYNC(i));
7771 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7772 error->pipe[i].vblank = I915_READ(VBLANK(i));
7773 error->pipe[i].vsync = I915_READ(VSYNC(i));
7774 }
7775
7776 return error;
7777}
7778
7779void
7780intel_display_print_error_state(struct seq_file *m,
7781 struct drm_device *dev,
7782 struct intel_display_error_state *error)
7783{
7784 int i;
7785
7786 for (i = 0; i < 2; i++) {
7787 seq_printf(m, "Pipe [%d]:\n", i);
7788 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7789 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7790 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7791 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7792 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7793 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7794 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7795 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7796
7797 seq_printf(m, "Plane [%d]:\n", i);
7798 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7799 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7800 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7801 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7802 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7803 if (INTEL_INFO(dev)->gen >= 4) {
7804 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7805 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7806 }
7807
7808 seq_printf(m, "Cursor [%d]:\n", i);
7809 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7810 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7811 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7812 }
7813}
7814#endif
Linux kernel - Deliverables
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