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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
42 | #include <drm/drm_plane_helper.h> |
43 | #include <drm/drm_rect.h> | |
c0f372b3 | 44 | #include <linux/dma_remapping.h> |
79e53945 | 45 | |
465c120c MR |
46 | /* Primary plane formats supported by all gen */ |
47 | #define COMMON_PRIMARY_FORMATS \ | |
48 | DRM_FORMAT_C8, \ | |
49 | DRM_FORMAT_RGB565, \ | |
50 | DRM_FORMAT_XRGB8888, \ | |
51 | DRM_FORMAT_ARGB8888 | |
52 | ||
53 | /* Primary plane formats for gen <= 3 */ | |
54 | static const uint32_t intel_primary_formats_gen2[] = { | |
55 | COMMON_PRIMARY_FORMATS, | |
56 | DRM_FORMAT_XRGB1555, | |
57 | DRM_FORMAT_ARGB1555, | |
58 | }; | |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
61 | static const uint32_t intel_primary_formats_gen4[] = { | |
62 | COMMON_PRIMARY_FORMATS, \ | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_ABGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_ARGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | DRM_FORMAT_ABGR2101010, | |
69 | }; | |
70 | ||
3d7d6510 MR |
71 | /* Cursor formats */ |
72 | static const uint32_t intel_cursor_formats[] = { | |
73 | DRM_FORMAT_ARGB8888, | |
74 | }; | |
75 | ||
6b383a7f | 76 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 77 | |
f1f644dc JB |
78 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
79 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
80 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
81 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 82 | |
e7457a9a DL |
83 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
84 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
85 | static int intel_framebuffer_init(struct drm_device *dev, |
86 | struct intel_framebuffer *ifb, | |
87 | struct drm_mode_fb_cmd2 *mode_cmd, | |
88 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
89 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
90 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 91 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
92 | struct intel_link_m_n *m_n, |
93 | struct intel_link_m_n *m2_n2); | |
29407aab | 94 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
95 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
96 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f VS |
97 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
98 | const struct intel_crtc_config *pipe_config); | |
99 | static void chv_prepare_pll(struct intel_crtc *crtc, | |
100 | const struct intel_crtc_config *pipe_config); | |
ea2c67bb MR |
101 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
102 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
e7457a9a | 103 | |
0e32b39c DA |
104 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
105 | { | |
106 | if (!connector->mst_port) | |
107 | return connector->encoder; | |
108 | else | |
109 | return &connector->mst_port->mst_encoders[pipe]->base; | |
110 | } | |
111 | ||
79e53945 | 112 | typedef struct { |
0206e353 | 113 | int min, max; |
79e53945 JB |
114 | } intel_range_t; |
115 | ||
116 | typedef struct { | |
0206e353 AJ |
117 | int dot_limit; |
118 | int p2_slow, p2_fast; | |
79e53945 JB |
119 | } intel_p2_t; |
120 | ||
d4906093 ML |
121 | typedef struct intel_limit intel_limit_t; |
122 | struct intel_limit { | |
0206e353 AJ |
123 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
124 | intel_p2_t p2; | |
d4906093 | 125 | }; |
79e53945 | 126 | |
d2acd215 DV |
127 | int |
128 | intel_pch_rawclk(struct drm_device *dev) | |
129 | { | |
130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
131 | ||
132 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
133 | ||
134 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
135 | } | |
136 | ||
021357ac CW |
137 | static inline u32 /* units of 100MHz */ |
138 | intel_fdi_link_freq(struct drm_device *dev) | |
139 | { | |
8b99e68c CW |
140 | if (IS_GEN5(dev)) { |
141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
142 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
143 | } else | |
144 | return 27; | |
021357ac CW |
145 | } |
146 | ||
5d536e28 | 147 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 148 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 149 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 150 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
151 | .m = { .min = 96, .max = 140 }, |
152 | .m1 = { .min = 18, .max = 26 }, | |
153 | .m2 = { .min = 6, .max = 16 }, | |
154 | .p = { .min = 4, .max = 128 }, | |
155 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
156 | .p2 = { .dot_limit = 165000, |
157 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
158 | }; |
159 | ||
5d536e28 DV |
160 | static const intel_limit_t intel_limits_i8xx_dvo = { |
161 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 162 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 163 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
164 | .m = { .min = 96, .max = 140 }, |
165 | .m1 = { .min = 18, .max = 26 }, | |
166 | .m2 = { .min = 6, .max = 16 }, | |
167 | .p = { .min = 4, .max = 128 }, | |
168 | .p1 = { .min = 2, .max = 33 }, | |
169 | .p2 = { .dot_limit = 165000, | |
170 | .p2_slow = 4, .p2_fast = 4 }, | |
171 | }; | |
172 | ||
e4b36699 | 173 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 174 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 175 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 176 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
177 | .m = { .min = 96, .max = 140 }, |
178 | .m1 = { .min = 18, .max = 26 }, | |
179 | .m2 = { .min = 6, .max = 16 }, | |
180 | .p = { .min = 4, .max = 128 }, | |
181 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
182 | .p2 = { .dot_limit = 165000, |
183 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 184 | }; |
273e27ca | 185 | |
e4b36699 | 186 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
187 | .dot = { .min = 20000, .max = 400000 }, |
188 | .vco = { .min = 1400000, .max = 2800000 }, | |
189 | .n = { .min = 1, .max = 6 }, | |
190 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
191 | .m1 = { .min = 8, .max = 18 }, |
192 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
193 | .p = { .min = 5, .max = 80 }, |
194 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
195 | .p2 = { .dot_limit = 200000, |
196 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
200 | .dot = { .min = 20000, .max = 400000 }, |
201 | .vco = { .min = 1400000, .max = 2800000 }, | |
202 | .n = { .min = 1, .max = 6 }, | |
203 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
204 | .m1 = { .min = 8, .max = 18 }, |
205 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
206 | .p = { .min = 7, .max = 98 }, |
207 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
208 | .p2 = { .dot_limit = 112000, |
209 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
210 | }; |
211 | ||
273e27ca | 212 | |
e4b36699 | 213 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
214 | .dot = { .min = 25000, .max = 270000 }, |
215 | .vco = { .min = 1750000, .max = 3500000}, | |
216 | .n = { .min = 1, .max = 4 }, | |
217 | .m = { .min = 104, .max = 138 }, | |
218 | .m1 = { .min = 17, .max = 23 }, | |
219 | .m2 = { .min = 5, .max = 11 }, | |
220 | .p = { .min = 10, .max = 30 }, | |
221 | .p1 = { .min = 1, .max = 3}, | |
222 | .p2 = { .dot_limit = 270000, | |
223 | .p2_slow = 10, | |
224 | .p2_fast = 10 | |
044c7c41 | 225 | }, |
e4b36699 KP |
226 | }; |
227 | ||
228 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
229 | .dot = { .min = 22000, .max = 400000 }, |
230 | .vco = { .min = 1750000, .max = 3500000}, | |
231 | .n = { .min = 1, .max = 4 }, | |
232 | .m = { .min = 104, .max = 138 }, | |
233 | .m1 = { .min = 16, .max = 23 }, | |
234 | .m2 = { .min = 5, .max = 11 }, | |
235 | .p = { .min = 5, .max = 80 }, | |
236 | .p1 = { .min = 1, .max = 8}, | |
237 | .p2 = { .dot_limit = 165000, | |
238 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
239 | }; |
240 | ||
241 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
242 | .dot = { .min = 20000, .max = 115000 }, |
243 | .vco = { .min = 1750000, .max = 3500000 }, | |
244 | .n = { .min = 1, .max = 3 }, | |
245 | .m = { .min = 104, .max = 138 }, | |
246 | .m1 = { .min = 17, .max = 23 }, | |
247 | .m2 = { .min = 5, .max = 11 }, | |
248 | .p = { .min = 28, .max = 112 }, | |
249 | .p1 = { .min = 2, .max = 8 }, | |
250 | .p2 = { .dot_limit = 0, | |
251 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 252 | }, |
e4b36699 KP |
253 | }; |
254 | ||
255 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
256 | .dot = { .min = 80000, .max = 224000 }, |
257 | .vco = { .min = 1750000, .max = 3500000 }, | |
258 | .n = { .min = 1, .max = 3 }, | |
259 | .m = { .min = 104, .max = 138 }, | |
260 | .m1 = { .min = 17, .max = 23 }, | |
261 | .m2 = { .min = 5, .max = 11 }, | |
262 | .p = { .min = 14, .max = 42 }, | |
263 | .p1 = { .min = 2, .max = 6 }, | |
264 | .p2 = { .dot_limit = 0, | |
265 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 266 | }, |
e4b36699 KP |
267 | }; |
268 | ||
f2b115e6 | 269 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
270 | .dot = { .min = 20000, .max = 400000}, |
271 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 272 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
273 | .n = { .min = 3, .max = 6 }, |
274 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 275 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
276 | .m1 = { .min = 0, .max = 0 }, |
277 | .m2 = { .min = 0, .max = 254 }, | |
278 | .p = { .min = 5, .max = 80 }, | |
279 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
280 | .p2 = { .dot_limit = 200000, |
281 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
282 | }; |
283 | ||
f2b115e6 | 284 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
285 | .dot = { .min = 20000, .max = 400000 }, |
286 | .vco = { .min = 1700000, .max = 3500000 }, | |
287 | .n = { .min = 3, .max = 6 }, | |
288 | .m = { .min = 2, .max = 256 }, | |
289 | .m1 = { .min = 0, .max = 0 }, | |
290 | .m2 = { .min = 0, .max = 254 }, | |
291 | .p = { .min = 7, .max = 112 }, | |
292 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
293 | .p2 = { .dot_limit = 112000, |
294 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
295 | }; |
296 | ||
273e27ca EA |
297 | /* Ironlake / Sandybridge |
298 | * | |
299 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
300 | * the range value for them is (actual_value - 2). | |
301 | */ | |
b91ad0ec | 302 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 350000 }, |
304 | .vco = { .min = 1760000, .max = 3510000 }, | |
305 | .n = { .min = 1, .max = 5 }, | |
306 | .m = { .min = 79, .max = 127 }, | |
307 | .m1 = { .min = 12, .max = 22 }, | |
308 | .m2 = { .min = 5, .max = 9 }, | |
309 | .p = { .min = 5, .max = 80 }, | |
310 | .p1 = { .min = 1, .max = 8 }, | |
311 | .p2 = { .dot_limit = 225000, | |
312 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
313 | }; |
314 | ||
b91ad0ec | 315 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
316 | .dot = { .min = 25000, .max = 350000 }, |
317 | .vco = { .min = 1760000, .max = 3510000 }, | |
318 | .n = { .min = 1, .max = 3 }, | |
319 | .m = { .min = 79, .max = 118 }, | |
320 | .m1 = { .min = 12, .max = 22 }, | |
321 | .m2 = { .min = 5, .max = 9 }, | |
322 | .p = { .min = 28, .max = 112 }, | |
323 | .p1 = { .min = 2, .max = 8 }, | |
324 | .p2 = { .dot_limit = 225000, | |
325 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
326 | }; |
327 | ||
328 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
329 | .dot = { .min = 25000, .max = 350000 }, |
330 | .vco = { .min = 1760000, .max = 3510000 }, | |
331 | .n = { .min = 1, .max = 3 }, | |
332 | .m = { .min = 79, .max = 127 }, | |
333 | .m1 = { .min = 12, .max = 22 }, | |
334 | .m2 = { .min = 5, .max = 9 }, | |
335 | .p = { .min = 14, .max = 56 }, | |
336 | .p1 = { .min = 2, .max = 8 }, | |
337 | .p2 = { .dot_limit = 225000, | |
338 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
339 | }; |
340 | ||
273e27ca | 341 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 342 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
343 | .dot = { .min = 25000, .max = 350000 }, |
344 | .vco = { .min = 1760000, .max = 3510000 }, | |
345 | .n = { .min = 1, .max = 2 }, | |
346 | .m = { .min = 79, .max = 126 }, | |
347 | .m1 = { .min = 12, .max = 22 }, | |
348 | .m2 = { .min = 5, .max = 9 }, | |
349 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 350 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
351 | .p2 = { .dot_limit = 225000, |
352 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
353 | }; |
354 | ||
355 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
356 | .dot = { .min = 25000, .max = 350000 }, |
357 | .vco = { .min = 1760000, .max = 3510000 }, | |
358 | .n = { .min = 1, .max = 3 }, | |
359 | .m = { .min = 79, .max = 126 }, | |
360 | .m1 = { .min = 12, .max = 22 }, | |
361 | .m2 = { .min = 5, .max = 9 }, | |
362 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 363 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
364 | .p2 = { .dot_limit = 225000, |
365 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
366 | }; |
367 | ||
dc730512 | 368 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
369 | /* |
370 | * These are the data rate limits (measured in fast clocks) | |
371 | * since those are the strictest limits we have. The fast | |
372 | * clock and actual rate limits are more relaxed, so checking | |
373 | * them would make no difference. | |
374 | */ | |
375 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 376 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 377 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
378 | .m1 = { .min = 2, .max = 3 }, |
379 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 380 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 381 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
382 | }; |
383 | ||
ef9348c8 CML |
384 | static const intel_limit_t intel_limits_chv = { |
385 | /* | |
386 | * These are the data rate limits (measured in fast clocks) | |
387 | * since those are the strictest limits we have. The fast | |
388 | * clock and actual rate limits are more relaxed, so checking | |
389 | * them would make no difference. | |
390 | */ | |
391 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
392 | .vco = { .min = 4860000, .max = 6700000 }, | |
393 | .n = { .min = 1, .max = 1 }, | |
394 | .m1 = { .min = 2, .max = 2 }, | |
395 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
396 | .p1 = { .min = 2, .max = 4 }, | |
397 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
398 | }; | |
399 | ||
6b4bf1c4 VS |
400 | static void vlv_clock(int refclk, intel_clock_t *clock) |
401 | { | |
402 | clock->m = clock->m1 * clock->m2; | |
403 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
404 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
405 | return; | |
fb03ac01 VS |
406 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
407 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
408 | } |
409 | ||
e0638cdf PZ |
410 | /** |
411 | * Returns whether any output on the specified pipe is of the specified type | |
412 | */ | |
4093561b | 413 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 414 | { |
409ee761 | 415 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
416 | struct intel_encoder *encoder; |
417 | ||
409ee761 | 418 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
419 | if (encoder->type == type) |
420 | return true; | |
421 | ||
422 | return false; | |
423 | } | |
424 | ||
d0737e1d ACO |
425 | /** |
426 | * Returns whether any output on the specified pipe will have the specified | |
427 | * type after a staged modeset is complete, i.e., the same as | |
428 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
429 | * encoder->crtc. | |
430 | */ | |
431 | static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type) | |
432 | { | |
433 | struct drm_device *dev = crtc->base.dev; | |
434 | struct intel_encoder *encoder; | |
435 | ||
436 | for_each_intel_encoder(dev, encoder) | |
437 | if (encoder->new_crtc == crtc && encoder->type == type) | |
438 | return true; | |
439 | ||
440 | return false; | |
441 | } | |
442 | ||
409ee761 | 443 | static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc, |
1b894b59 | 444 | int refclk) |
2c07245f | 445 | { |
409ee761 | 446 | struct drm_device *dev = crtc->base.dev; |
2c07245f | 447 | const intel_limit_t *limit; |
b91ad0ec | 448 | |
d0737e1d | 449 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 450 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 451 | if (refclk == 100000) |
b91ad0ec ZW |
452 | limit = &intel_limits_ironlake_dual_lvds_100m; |
453 | else | |
454 | limit = &intel_limits_ironlake_dual_lvds; | |
455 | } else { | |
1b894b59 | 456 | if (refclk == 100000) |
b91ad0ec ZW |
457 | limit = &intel_limits_ironlake_single_lvds_100m; |
458 | else | |
459 | limit = &intel_limits_ironlake_single_lvds; | |
460 | } | |
c6bb3538 | 461 | } else |
b91ad0ec | 462 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
463 | |
464 | return limit; | |
465 | } | |
466 | ||
409ee761 | 467 | static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc) |
044c7c41 | 468 | { |
409ee761 | 469 | struct drm_device *dev = crtc->base.dev; |
044c7c41 ML |
470 | const intel_limit_t *limit; |
471 | ||
d0737e1d | 472 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 473 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 474 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 475 | else |
e4b36699 | 476 | limit = &intel_limits_g4x_single_channel_lvds; |
d0737e1d ACO |
477 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) || |
478 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 479 | limit = &intel_limits_g4x_hdmi; |
d0737e1d | 480 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 481 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 482 | } else /* The option is for other outputs */ |
e4b36699 | 483 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
484 | |
485 | return limit; | |
486 | } | |
487 | ||
409ee761 | 488 | static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk) |
79e53945 | 489 | { |
409ee761 | 490 | struct drm_device *dev = crtc->base.dev; |
79e53945 JB |
491 | const intel_limit_t *limit; |
492 | ||
bad720ff | 493 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 494 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 495 | else if (IS_G4X(dev)) { |
044c7c41 | 496 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 497 | } else if (IS_PINEVIEW(dev)) { |
d0737e1d | 498 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 499 | limit = &intel_limits_pineview_lvds; |
2177832f | 500 | else |
f2b115e6 | 501 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
502 | } else if (IS_CHERRYVIEW(dev)) { |
503 | limit = &intel_limits_chv; | |
a0c4da24 | 504 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 505 | limit = &intel_limits_vlv; |
a6c45cf0 | 506 | } else if (!IS_GEN2(dev)) { |
d0737e1d | 507 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
508 | limit = &intel_limits_i9xx_lvds; |
509 | else | |
510 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 511 | } else { |
d0737e1d | 512 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
e4b36699 | 513 | limit = &intel_limits_i8xx_lvds; |
d0737e1d | 514 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 515 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
516 | else |
517 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
518 | } |
519 | return limit; | |
520 | } | |
521 | ||
f2b115e6 AJ |
522 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
523 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 524 | { |
2177832f SL |
525 | clock->m = clock->m2 + 2; |
526 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
527 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
528 | return; | |
fb03ac01 VS |
529 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
530 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
531 | } |
532 | ||
7429e9d4 DV |
533 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
534 | { | |
535 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
536 | } | |
537 | ||
ac58c3f0 | 538 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 539 | { |
7429e9d4 | 540 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 541 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
542 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
543 | return; | |
fb03ac01 VS |
544 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
545 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
546 | } |
547 | ||
ef9348c8 CML |
548 | static void chv_clock(int refclk, intel_clock_t *clock) |
549 | { | |
550 | clock->m = clock->m1 * clock->m2; | |
551 | clock->p = clock->p1 * clock->p2; | |
552 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
553 | return; | |
554 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
555 | clock->n << 22); | |
556 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
557 | } | |
558 | ||
7c04d1d9 | 559 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
560 | /** |
561 | * Returns whether the given set of divisors are valid for a given refclk with | |
562 | * the given connectors. | |
563 | */ | |
564 | ||
1b894b59 CW |
565 | static bool intel_PLL_is_valid(struct drm_device *dev, |
566 | const intel_limit_t *limit, | |
567 | const intel_clock_t *clock) | |
79e53945 | 568 | { |
f01b7962 VS |
569 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
570 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 571 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 572 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 573 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 574 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 575 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 576 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
577 | |
578 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
579 | if (clock->m1 <= clock->m2) | |
580 | INTELPllInvalid("m1 <= m2\n"); | |
581 | ||
582 | if (!IS_VALLEYVIEW(dev)) { | |
583 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
584 | INTELPllInvalid("p out of range\n"); | |
585 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
586 | INTELPllInvalid("m out of range\n"); | |
587 | } | |
588 | ||
79e53945 | 589 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 590 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
591 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
592 | * connector, etc., rather than just a single range. | |
593 | */ | |
594 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 595 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
596 | |
597 | return true; | |
598 | } | |
599 | ||
d4906093 | 600 | static bool |
a919ff14 | 601 | i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
cec2f356 SP |
602 | int target, int refclk, intel_clock_t *match_clock, |
603 | intel_clock_t *best_clock) | |
79e53945 | 604 | { |
a919ff14 | 605 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 606 | intel_clock_t clock; |
79e53945 JB |
607 | int err = target; |
608 | ||
d0737e1d | 609 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 610 | /* |
a210b028 DV |
611 | * For LVDS just rely on its current settings for dual-channel. |
612 | * We haven't figured out how to reliably set up different | |
613 | * single/dual channel state, if we even can. | |
79e53945 | 614 | */ |
1974cad0 | 615 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
616 | clock.p2 = limit->p2.p2_fast; |
617 | else | |
618 | clock.p2 = limit->p2.p2_slow; | |
619 | } else { | |
620 | if (target < limit->p2.dot_limit) | |
621 | clock.p2 = limit->p2.p2_slow; | |
622 | else | |
623 | clock.p2 = limit->p2.p2_fast; | |
624 | } | |
625 | ||
0206e353 | 626 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 627 | |
42158660 ZY |
628 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
629 | clock.m1++) { | |
630 | for (clock.m2 = limit->m2.min; | |
631 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 632 | if (clock.m2 >= clock.m1) |
42158660 ZY |
633 | break; |
634 | for (clock.n = limit->n.min; | |
635 | clock.n <= limit->n.max; clock.n++) { | |
636 | for (clock.p1 = limit->p1.min; | |
637 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
638 | int this_err; |
639 | ||
ac58c3f0 DV |
640 | i9xx_clock(refclk, &clock); |
641 | if (!intel_PLL_is_valid(dev, limit, | |
642 | &clock)) | |
643 | continue; | |
644 | if (match_clock && | |
645 | clock.p != match_clock->p) | |
646 | continue; | |
647 | ||
648 | this_err = abs(clock.dot - target); | |
649 | if (this_err < err) { | |
650 | *best_clock = clock; | |
651 | err = this_err; | |
652 | } | |
653 | } | |
654 | } | |
655 | } | |
656 | } | |
657 | ||
658 | return (err != target); | |
659 | } | |
660 | ||
661 | static bool | |
a919ff14 | 662 | pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
663 | int target, int refclk, intel_clock_t *match_clock, |
664 | intel_clock_t *best_clock) | |
79e53945 | 665 | { |
a919ff14 | 666 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 667 | intel_clock_t clock; |
79e53945 JB |
668 | int err = target; |
669 | ||
d0737e1d | 670 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 671 | /* |
a210b028 DV |
672 | * For LVDS just rely on its current settings for dual-channel. |
673 | * We haven't figured out how to reliably set up different | |
674 | * single/dual channel state, if we even can. | |
79e53945 | 675 | */ |
1974cad0 | 676 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
677 | clock.p2 = limit->p2.p2_fast; |
678 | else | |
679 | clock.p2 = limit->p2.p2_slow; | |
680 | } else { | |
681 | if (target < limit->p2.dot_limit) | |
682 | clock.p2 = limit->p2.p2_slow; | |
683 | else | |
684 | clock.p2 = limit->p2.p2_fast; | |
685 | } | |
686 | ||
0206e353 | 687 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 688 | |
42158660 ZY |
689 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
690 | clock.m1++) { | |
691 | for (clock.m2 = limit->m2.min; | |
692 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
693 | for (clock.n = limit->n.min; |
694 | clock.n <= limit->n.max; clock.n++) { | |
695 | for (clock.p1 = limit->p1.min; | |
696 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
697 | int this_err; |
698 | ||
ac58c3f0 | 699 | pineview_clock(refclk, &clock); |
1b894b59 CW |
700 | if (!intel_PLL_is_valid(dev, limit, |
701 | &clock)) | |
79e53945 | 702 | continue; |
cec2f356 SP |
703 | if (match_clock && |
704 | clock.p != match_clock->p) | |
705 | continue; | |
79e53945 JB |
706 | |
707 | this_err = abs(clock.dot - target); | |
708 | if (this_err < err) { | |
709 | *best_clock = clock; | |
710 | err = this_err; | |
711 | } | |
712 | } | |
713 | } | |
714 | } | |
715 | } | |
716 | ||
717 | return (err != target); | |
718 | } | |
719 | ||
d4906093 | 720 | static bool |
a919ff14 | 721 | g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
722 | int target, int refclk, intel_clock_t *match_clock, |
723 | intel_clock_t *best_clock) | |
d4906093 | 724 | { |
a919ff14 | 725 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
726 | intel_clock_t clock; |
727 | int max_n; | |
728 | bool found; | |
6ba770dc AJ |
729 | /* approximately equals target * 0.00585 */ |
730 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
731 | found = false; |
732 | ||
d0737e1d | 733 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 734 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
735 | clock.p2 = limit->p2.p2_fast; |
736 | else | |
737 | clock.p2 = limit->p2.p2_slow; | |
738 | } else { | |
739 | if (target < limit->p2.dot_limit) | |
740 | clock.p2 = limit->p2.p2_slow; | |
741 | else | |
742 | clock.p2 = limit->p2.p2_fast; | |
743 | } | |
744 | ||
745 | memset(best_clock, 0, sizeof(*best_clock)); | |
746 | max_n = limit->n.max; | |
f77f13e2 | 747 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 748 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 749 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
750 | for (clock.m1 = limit->m1.max; |
751 | clock.m1 >= limit->m1.min; clock.m1--) { | |
752 | for (clock.m2 = limit->m2.max; | |
753 | clock.m2 >= limit->m2.min; clock.m2--) { | |
754 | for (clock.p1 = limit->p1.max; | |
755 | clock.p1 >= limit->p1.min; clock.p1--) { | |
756 | int this_err; | |
757 | ||
ac58c3f0 | 758 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
759 | if (!intel_PLL_is_valid(dev, limit, |
760 | &clock)) | |
d4906093 | 761 | continue; |
1b894b59 CW |
762 | |
763 | this_err = abs(clock.dot - target); | |
d4906093 ML |
764 | if (this_err < err_most) { |
765 | *best_clock = clock; | |
766 | err_most = this_err; | |
767 | max_n = clock.n; | |
768 | found = true; | |
769 | } | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
2c07245f ZW |
774 | return found; |
775 | } | |
776 | ||
a0c4da24 | 777 | static bool |
a919ff14 | 778 | vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
779 | int target, int refclk, intel_clock_t *match_clock, |
780 | intel_clock_t *best_clock) | |
a0c4da24 | 781 | { |
a919ff14 | 782 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 783 | intel_clock_t clock; |
69e4f900 | 784 | unsigned int bestppm = 1000000; |
27e639bf VS |
785 | /* min update 19.2 MHz */ |
786 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 787 | bool found = false; |
a0c4da24 | 788 | |
6b4bf1c4 VS |
789 | target *= 5; /* fast clock */ |
790 | ||
791 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
792 | |
793 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 794 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 795 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 796 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 797 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 798 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 799 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 800 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
801 | unsigned int ppm, diff; |
802 | ||
6b4bf1c4 VS |
803 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
804 | refclk * clock.m1); | |
805 | ||
806 | vlv_clock(refclk, &clock); | |
43b0ac53 | 807 | |
f01b7962 VS |
808 | if (!intel_PLL_is_valid(dev, limit, |
809 | &clock)) | |
43b0ac53 VS |
810 | continue; |
811 | ||
6b4bf1c4 VS |
812 | diff = abs(clock.dot - target); |
813 | ppm = div_u64(1000000ULL * diff, target); | |
814 | ||
815 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 816 | bestppm = 0; |
6b4bf1c4 | 817 | *best_clock = clock; |
49e497ef | 818 | found = true; |
43b0ac53 | 819 | } |
6b4bf1c4 | 820 | |
c686122c | 821 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 822 | bestppm = ppm; |
6b4bf1c4 | 823 | *best_clock = clock; |
49e497ef | 824 | found = true; |
a0c4da24 JB |
825 | } |
826 | } | |
827 | } | |
828 | } | |
829 | } | |
a0c4da24 | 830 | |
49e497ef | 831 | return found; |
a0c4da24 | 832 | } |
a4fc5ed6 | 833 | |
ef9348c8 | 834 | static bool |
a919ff14 | 835 | chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ef9348c8 CML |
836 | int target, int refclk, intel_clock_t *match_clock, |
837 | intel_clock_t *best_clock) | |
838 | { | |
a919ff14 | 839 | struct drm_device *dev = crtc->base.dev; |
ef9348c8 CML |
840 | intel_clock_t clock; |
841 | uint64_t m2; | |
842 | int found = false; | |
843 | ||
844 | memset(best_clock, 0, sizeof(*best_clock)); | |
845 | ||
846 | /* | |
847 | * Based on hardware doc, the n always set to 1, and m1 always | |
848 | * set to 2. If requires to support 200Mhz refclk, we need to | |
849 | * revisit this because n may not 1 anymore. | |
850 | */ | |
851 | clock.n = 1, clock.m1 = 2; | |
852 | target *= 5; /* fast clock */ | |
853 | ||
854 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
855 | for (clock.p2 = limit->p2.p2_fast; | |
856 | clock.p2 >= limit->p2.p2_slow; | |
857 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
858 | ||
859 | clock.p = clock.p1 * clock.p2; | |
860 | ||
861 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
862 | clock.n) << 22, refclk * clock.m1); | |
863 | ||
864 | if (m2 > INT_MAX/clock.m1) | |
865 | continue; | |
866 | ||
867 | clock.m2 = m2; | |
868 | ||
869 | chv_clock(refclk, &clock); | |
870 | ||
871 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
872 | continue; | |
873 | ||
874 | /* based on hardware requirement, prefer bigger p | |
875 | */ | |
876 | if (clock.p > best_clock->p) { | |
877 | *best_clock = clock; | |
878 | found = true; | |
879 | } | |
880 | } | |
881 | } | |
882 | ||
883 | return found; | |
884 | } | |
885 | ||
20ddf665 VS |
886 | bool intel_crtc_active(struct drm_crtc *crtc) |
887 | { | |
888 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
889 | ||
890 | /* Be paranoid as we can arrive here with only partial | |
891 | * state retrieved from the hardware during setup. | |
892 | * | |
241bfc38 | 893 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
894 | * as Haswell has gained clock readout/fastboot support. |
895 | * | |
66e514c1 | 896 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
897 | * properly reconstruct framebuffers. |
898 | */ | |
f4510a27 | 899 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 900 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
901 | } |
902 | ||
a5c961d1 PZ |
903 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
904 | enum pipe pipe) | |
905 | { | |
906 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
907 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
908 | ||
3b117c8f | 909 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
910 | } |
911 | ||
fbf49ea2 VS |
912 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
913 | { | |
914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
915 | u32 reg = PIPEDSL(pipe); | |
916 | u32 line1, line2; | |
917 | u32 line_mask; | |
918 | ||
919 | if (IS_GEN2(dev)) | |
920 | line_mask = DSL_LINEMASK_GEN2; | |
921 | else | |
922 | line_mask = DSL_LINEMASK_GEN3; | |
923 | ||
924 | line1 = I915_READ(reg) & line_mask; | |
925 | mdelay(5); | |
926 | line2 = I915_READ(reg) & line_mask; | |
927 | ||
928 | return line1 == line2; | |
929 | } | |
930 | ||
ab7ad7f6 KP |
931 | /* |
932 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 933 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
934 | * |
935 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
936 | * spinning on the vblank interrupt status bit, since we won't actually | |
937 | * see an interrupt when the pipe is disabled. | |
938 | * | |
ab7ad7f6 KP |
939 | * On Gen4 and above: |
940 | * wait for the pipe register state bit to turn off | |
941 | * | |
942 | * Otherwise: | |
943 | * wait for the display line value to settle (it usually | |
944 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 945 | * |
9d0498a2 | 946 | */ |
575f7ab7 | 947 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 948 | { |
575f7ab7 | 949 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 950 | struct drm_i915_private *dev_priv = dev->dev_private; |
575f7ab7 VS |
951 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
952 | enum pipe pipe = crtc->pipe; | |
ab7ad7f6 KP |
953 | |
954 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 955 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
956 | |
957 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
958 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
959 | 100)) | |
284637d9 | 960 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 961 | } else { |
ab7ad7f6 | 962 | /* Wait for the display line to settle */ |
fbf49ea2 | 963 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 964 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 965 | } |
79e53945 JB |
966 | } |
967 | ||
b0ea7d37 DL |
968 | /* |
969 | * ibx_digital_port_connected - is the specified port connected? | |
970 | * @dev_priv: i915 private structure | |
971 | * @port: the port to test | |
972 | * | |
973 | * Returns true if @port is connected, false otherwise. | |
974 | */ | |
975 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
976 | struct intel_digital_port *port) | |
977 | { | |
978 | u32 bit; | |
979 | ||
c36346e3 | 980 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 981 | switch (port->port) { |
c36346e3 DL |
982 | case PORT_B: |
983 | bit = SDE_PORTB_HOTPLUG; | |
984 | break; | |
985 | case PORT_C: | |
986 | bit = SDE_PORTC_HOTPLUG; | |
987 | break; | |
988 | case PORT_D: | |
989 | bit = SDE_PORTD_HOTPLUG; | |
990 | break; | |
991 | default: | |
992 | return true; | |
993 | } | |
994 | } else { | |
eba905b2 | 995 | switch (port->port) { |
c36346e3 DL |
996 | case PORT_B: |
997 | bit = SDE_PORTB_HOTPLUG_CPT; | |
998 | break; | |
999 | case PORT_C: | |
1000 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1001 | break; | |
1002 | case PORT_D: | |
1003 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1004 | break; | |
1005 | default: | |
1006 | return true; | |
1007 | } | |
b0ea7d37 DL |
1008 | } |
1009 | ||
1010 | return I915_READ(SDEISR) & bit; | |
1011 | } | |
1012 | ||
b24e7179 JB |
1013 | static const char *state_string(bool enabled) |
1014 | { | |
1015 | return enabled ? "on" : "off"; | |
1016 | } | |
1017 | ||
1018 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1019 | void assert_pll(struct drm_i915_private *dev_priv, |
1020 | enum pipe pipe, bool state) | |
b24e7179 JB |
1021 | { |
1022 | int reg; | |
1023 | u32 val; | |
1024 | bool cur_state; | |
1025 | ||
1026 | reg = DPLL(pipe); | |
1027 | val = I915_READ(reg); | |
1028 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1029 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1030 | "PLL state assertion failure (expected %s, current %s)\n", |
1031 | state_string(state), state_string(cur_state)); | |
1032 | } | |
b24e7179 | 1033 | |
23538ef1 JN |
1034 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1035 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1036 | { | |
1037 | u32 val; | |
1038 | bool cur_state; | |
1039 | ||
1040 | mutex_lock(&dev_priv->dpio_lock); | |
1041 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1042 | mutex_unlock(&dev_priv->dpio_lock); | |
1043 | ||
1044 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1045 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1046 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1047 | state_string(state), state_string(cur_state)); | |
1048 | } | |
1049 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1050 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1051 | ||
55607e8a | 1052 | struct intel_shared_dpll * |
e2b78267 DV |
1053 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1054 | { | |
1055 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1056 | ||
a43f6e0f | 1057 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1058 | return NULL; |
1059 | ||
a43f6e0f | 1060 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1061 | } |
1062 | ||
040484af | 1063 | /* For ILK+ */ |
55607e8a DV |
1064 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1065 | struct intel_shared_dpll *pll, | |
1066 | bool state) | |
040484af | 1067 | { |
040484af | 1068 | bool cur_state; |
5358901f | 1069 | struct intel_dpll_hw_state hw_state; |
040484af | 1070 | |
92b27b08 | 1071 | if (WARN (!pll, |
46edb027 | 1072 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1073 | return; |
ee7b9f93 | 1074 | |
5358901f | 1075 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1076 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1077 | "%s assertion failure (expected %s, current %s)\n", |
1078 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1079 | } |
040484af JB |
1080 | |
1081 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1082 | enum pipe pipe, bool state) | |
1083 | { | |
1084 | int reg; | |
1085 | u32 val; | |
1086 | bool cur_state; | |
ad80a810 PZ |
1087 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1088 | pipe); | |
040484af | 1089 | |
affa9354 PZ |
1090 | if (HAS_DDI(dev_priv->dev)) { |
1091 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1092 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1093 | val = I915_READ(reg); |
ad80a810 | 1094 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1095 | } else { |
1096 | reg = FDI_TX_CTL(pipe); | |
1097 | val = I915_READ(reg); | |
1098 | cur_state = !!(val & FDI_TX_ENABLE); | |
1099 | } | |
e2c719b7 | 1100 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1101 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1102 | state_string(state), state_string(cur_state)); | |
1103 | } | |
1104 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1105 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1106 | ||
1107 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1108 | enum pipe pipe, bool state) | |
1109 | { | |
1110 | int reg; | |
1111 | u32 val; | |
1112 | bool cur_state; | |
1113 | ||
d63fa0dc PZ |
1114 | reg = FDI_RX_CTL(pipe); |
1115 | val = I915_READ(reg); | |
1116 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1117 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1118 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1119 | state_string(state), state_string(cur_state)); | |
1120 | } | |
1121 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1122 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1123 | ||
1124 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1125 | enum pipe pipe) | |
1126 | { | |
1127 | int reg; | |
1128 | u32 val; | |
1129 | ||
1130 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1131 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1132 | return; |
1133 | ||
bf507ef7 | 1134 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1135 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1136 | return; |
1137 | ||
040484af JB |
1138 | reg = FDI_TX_CTL(pipe); |
1139 | val = I915_READ(reg); | |
e2c719b7 | 1140 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1141 | } |
1142 | ||
55607e8a DV |
1143 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1144 | enum pipe pipe, bool state) | |
040484af JB |
1145 | { |
1146 | int reg; | |
1147 | u32 val; | |
55607e8a | 1148 | bool cur_state; |
040484af JB |
1149 | |
1150 | reg = FDI_RX_CTL(pipe); | |
1151 | val = I915_READ(reg); | |
55607e8a | 1152 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1153 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1154 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1155 | state_string(state), state_string(cur_state)); | |
040484af JB |
1156 | } |
1157 | ||
b680c37a DV |
1158 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1159 | enum pipe pipe) | |
ea0760cf | 1160 | { |
bedd4dba JN |
1161 | struct drm_device *dev = dev_priv->dev; |
1162 | int pp_reg; | |
ea0760cf JB |
1163 | u32 val; |
1164 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1165 | bool locked = true; |
ea0760cf | 1166 | |
bedd4dba JN |
1167 | if (WARN_ON(HAS_DDI(dev))) |
1168 | return; | |
1169 | ||
1170 | if (HAS_PCH_SPLIT(dev)) { | |
1171 | u32 port_sel; | |
1172 | ||
ea0760cf | 1173 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1174 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1175 | ||
1176 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1177 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1178 | panel_pipe = PIPE_B; | |
1179 | /* XXX: else fix for eDP */ | |
1180 | } else if (IS_VALLEYVIEW(dev)) { | |
1181 | /* presumably write lock depends on pipe, not port select */ | |
1182 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1183 | panel_pipe = pipe; | |
ea0760cf JB |
1184 | } else { |
1185 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1186 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1187 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1188 | } |
1189 | ||
1190 | val = I915_READ(pp_reg); | |
1191 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1192 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1193 | locked = false; |
1194 | ||
e2c719b7 | 1195 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1196 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1197 | pipe_name(pipe)); |
ea0760cf JB |
1198 | } |
1199 | ||
93ce0ba6 JN |
1200 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1201 | enum pipe pipe, bool state) | |
1202 | { | |
1203 | struct drm_device *dev = dev_priv->dev; | |
1204 | bool cur_state; | |
1205 | ||
d9d82081 | 1206 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1207 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1208 | else |
5efb3e28 | 1209 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1210 | |
e2c719b7 | 1211 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1212 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1213 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1214 | } | |
1215 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1216 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1217 | ||
b840d907 JB |
1218 | void assert_pipe(struct drm_i915_private *dev_priv, |
1219 | enum pipe pipe, bool state) | |
b24e7179 JB |
1220 | { |
1221 | int reg; | |
1222 | u32 val; | |
63d7bbe9 | 1223 | bool cur_state; |
702e7a56 PZ |
1224 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1225 | pipe); | |
b24e7179 | 1226 | |
b6b5d049 VS |
1227 | /* if we need the pipe quirk it must be always on */ |
1228 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1229 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1230 | state = true; |
1231 | ||
f458ebbc | 1232 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1233 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1234 | cur_state = false; |
1235 | } else { | |
1236 | reg = PIPECONF(cpu_transcoder); | |
1237 | val = I915_READ(reg); | |
1238 | cur_state = !!(val & PIPECONF_ENABLE); | |
1239 | } | |
1240 | ||
e2c719b7 | 1241 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1242 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1243 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1244 | } |
1245 | ||
931872fc CW |
1246 | static void assert_plane(struct drm_i915_private *dev_priv, |
1247 | enum plane plane, bool state) | |
b24e7179 JB |
1248 | { |
1249 | int reg; | |
1250 | u32 val; | |
931872fc | 1251 | bool cur_state; |
b24e7179 JB |
1252 | |
1253 | reg = DSPCNTR(plane); | |
1254 | val = I915_READ(reg); | |
931872fc | 1255 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1256 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1257 | "plane %c assertion failure (expected %s, current %s)\n", |
1258 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1259 | } |
1260 | ||
931872fc CW |
1261 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1262 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1263 | ||
b24e7179 JB |
1264 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1265 | enum pipe pipe) | |
1266 | { | |
653e1026 | 1267 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1268 | int reg, i; |
1269 | u32 val; | |
1270 | int cur_pipe; | |
1271 | ||
653e1026 VS |
1272 | /* Primary planes are fixed to pipes on gen4+ */ |
1273 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1274 | reg = DSPCNTR(pipe); |
1275 | val = I915_READ(reg); | |
e2c719b7 | 1276 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1277 | "plane %c assertion failure, should be disabled but not\n", |
1278 | plane_name(pipe)); | |
19ec1358 | 1279 | return; |
28c05794 | 1280 | } |
19ec1358 | 1281 | |
b24e7179 | 1282 | /* Need to check both planes against the pipe */ |
055e393f | 1283 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1284 | reg = DSPCNTR(i); |
1285 | val = I915_READ(reg); | |
1286 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1287 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1288 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1289 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1290 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1291 | } |
1292 | } | |
1293 | ||
19332d7a JB |
1294 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe) | |
1296 | { | |
20674eef | 1297 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1298 | int reg, sprite; |
19332d7a JB |
1299 | u32 val; |
1300 | ||
7feb8b88 DL |
1301 | if (INTEL_INFO(dev)->gen >= 9) { |
1302 | for_each_sprite(pipe, sprite) { | |
1303 | val = I915_READ(PLANE_CTL(pipe, sprite)); | |
e2c719b7 | 1304 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1305 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1306 | sprite, pipe_name(pipe)); | |
1307 | } | |
1308 | } else if (IS_VALLEYVIEW(dev)) { | |
1fe47785 DL |
1309 | for_each_sprite(pipe, sprite) { |
1310 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1311 | val = I915_READ(reg); |
e2c719b7 | 1312 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1313 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1314 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1315 | } |
1316 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1317 | reg = SPRCTL(pipe); | |
19332d7a | 1318 | val = I915_READ(reg); |
e2c719b7 | 1319 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1320 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1321 | plane_name(pipe), pipe_name(pipe)); |
1322 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1323 | reg = DVSCNTR(pipe); | |
19332d7a | 1324 | val = I915_READ(reg); |
e2c719b7 | 1325 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1326 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1327 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1328 | } |
1329 | } | |
1330 | ||
08c71e5e VS |
1331 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1332 | { | |
e2c719b7 | 1333 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1334 | drm_crtc_vblank_put(crtc); |
1335 | } | |
1336 | ||
89eff4be | 1337 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1338 | { |
1339 | u32 val; | |
1340 | bool enabled; | |
1341 | ||
e2c719b7 | 1342 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1343 | |
92f2584a JB |
1344 | val = I915_READ(PCH_DREF_CONTROL); |
1345 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1346 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1347 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1348 | } |
1349 | ||
ab9412ba DV |
1350 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1351 | enum pipe pipe) | |
92f2584a JB |
1352 | { |
1353 | int reg; | |
1354 | u32 val; | |
1355 | bool enabled; | |
1356 | ||
ab9412ba | 1357 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1358 | val = I915_READ(reg); |
1359 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1360 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1361 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1362 | pipe_name(pipe)); | |
92f2584a JB |
1363 | } |
1364 | ||
4e634389 KP |
1365 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1366 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1367 | { |
1368 | if ((val & DP_PORT_EN) == 0) | |
1369 | return false; | |
1370 | ||
1371 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1372 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1373 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1374 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1375 | return false; | |
44f37d1f CML |
1376 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1377 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1378 | return false; | |
f0575e92 KP |
1379 | } else { |
1380 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1381 | return false; | |
1382 | } | |
1383 | return true; | |
1384 | } | |
1385 | ||
1519b995 KP |
1386 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1387 | enum pipe pipe, u32 val) | |
1388 | { | |
dc0fa718 | 1389 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1390 | return false; |
1391 | ||
1392 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1393 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1394 | return false; |
44f37d1f CML |
1395 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1396 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1397 | return false; | |
1519b995 | 1398 | } else { |
dc0fa718 | 1399 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1400 | return false; |
1401 | } | |
1402 | return true; | |
1403 | } | |
1404 | ||
1405 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1406 | enum pipe pipe, u32 val) | |
1407 | { | |
1408 | if ((val & LVDS_PORT_EN) == 0) | |
1409 | return false; | |
1410 | ||
1411 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1412 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1413 | return false; | |
1414 | } else { | |
1415 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1416 | return false; | |
1417 | } | |
1418 | return true; | |
1419 | } | |
1420 | ||
1421 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1422 | enum pipe pipe, u32 val) | |
1423 | { | |
1424 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1425 | return false; | |
1426 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1427 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1428 | return false; | |
1429 | } else { | |
1430 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1431 | return false; | |
1432 | } | |
1433 | return true; | |
1434 | } | |
1435 | ||
291906f1 | 1436 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1437 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1438 | { |
47a05eca | 1439 | u32 val = I915_READ(reg); |
e2c719b7 | 1440 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1441 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1442 | reg, pipe_name(pipe)); |
de9a35ab | 1443 | |
e2c719b7 | 1444 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1445 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1446 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1447 | } |
1448 | ||
1449 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1450 | enum pipe pipe, int reg) | |
1451 | { | |
47a05eca | 1452 | u32 val = I915_READ(reg); |
e2c719b7 | 1453 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1454 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1455 | reg, pipe_name(pipe)); |
de9a35ab | 1456 | |
e2c719b7 | 1457 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1458 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1459 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1460 | } |
1461 | ||
1462 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1463 | enum pipe pipe) | |
1464 | { | |
1465 | int reg; | |
1466 | u32 val; | |
291906f1 | 1467 | |
f0575e92 KP |
1468 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1469 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1470 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1471 | |
1472 | reg = PCH_ADPA; | |
1473 | val = I915_READ(reg); | |
e2c719b7 | 1474 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1475 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1476 | pipe_name(pipe)); |
291906f1 JB |
1477 | |
1478 | reg = PCH_LVDS; | |
1479 | val = I915_READ(reg); | |
e2c719b7 | 1480 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1481 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1482 | pipe_name(pipe)); |
291906f1 | 1483 | |
e2debe91 PZ |
1484 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1485 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1486 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1487 | } |
1488 | ||
40e9cf64 JB |
1489 | static void intel_init_dpio(struct drm_device *dev) |
1490 | { | |
1491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1492 | ||
1493 | if (!IS_VALLEYVIEW(dev)) | |
1494 | return; | |
1495 | ||
a09caddd CML |
1496 | /* |
1497 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1498 | * CHV x1 PHY (DP/HDMI D) | |
1499 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1500 | */ | |
1501 | if (IS_CHERRYVIEW(dev)) { | |
1502 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1503 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1504 | } else { | |
1505 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1506 | } | |
5382f5f3 JB |
1507 | } |
1508 | ||
d288f65f VS |
1509 | static void vlv_enable_pll(struct intel_crtc *crtc, |
1510 | const struct intel_crtc_config *pipe_config) | |
87442f73 | 1511 | { |
426115cf DV |
1512 | struct drm_device *dev = crtc->base.dev; |
1513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1514 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1515 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1516 | |
426115cf | 1517 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1518 | |
1519 | /* No really, not for ILK+ */ | |
1520 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1521 | ||
1522 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1523 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1524 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1525 | |
426115cf DV |
1526 | I915_WRITE(reg, dpll); |
1527 | POSTING_READ(reg); | |
1528 | udelay(150); | |
1529 | ||
1530 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1531 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1532 | ||
d288f65f | 1533 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1534 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1535 | |
1536 | /* We do this three times for luck */ | |
426115cf | 1537 | I915_WRITE(reg, dpll); |
87442f73 DV |
1538 | POSTING_READ(reg); |
1539 | udelay(150); /* wait for warmup */ | |
426115cf | 1540 | I915_WRITE(reg, dpll); |
87442f73 DV |
1541 | POSTING_READ(reg); |
1542 | udelay(150); /* wait for warmup */ | |
426115cf | 1543 | I915_WRITE(reg, dpll); |
87442f73 DV |
1544 | POSTING_READ(reg); |
1545 | udelay(150); /* wait for warmup */ | |
1546 | } | |
1547 | ||
d288f65f VS |
1548 | static void chv_enable_pll(struct intel_crtc *crtc, |
1549 | const struct intel_crtc_config *pipe_config) | |
9d556c99 CML |
1550 | { |
1551 | struct drm_device *dev = crtc->base.dev; | |
1552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1553 | int pipe = crtc->pipe; | |
1554 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1555 | u32 tmp; |
1556 | ||
1557 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1558 | ||
1559 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1560 | ||
1561 | mutex_lock(&dev_priv->dpio_lock); | |
1562 | ||
1563 | /* Enable back the 10bit clock to display controller */ | |
1564 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1565 | tmp |= DPIO_DCLKP_EN; | |
1566 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1567 | ||
1568 | /* | |
1569 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1570 | */ | |
1571 | udelay(1); | |
1572 | ||
1573 | /* Enable PLL */ | |
d288f65f | 1574 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1575 | |
1576 | /* Check PLL is locked */ | |
a11b0703 | 1577 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1578 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1579 | ||
a11b0703 | 1580 | /* not sure when this should be written */ |
d288f65f | 1581 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1582 | POSTING_READ(DPLL_MD(pipe)); |
1583 | ||
9d556c99 CML |
1584 | mutex_unlock(&dev_priv->dpio_lock); |
1585 | } | |
1586 | ||
1c4e0274 VS |
1587 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1588 | { | |
1589 | struct intel_crtc *crtc; | |
1590 | int count = 0; | |
1591 | ||
1592 | for_each_intel_crtc(dev, crtc) | |
1593 | count += crtc->active && | |
409ee761 | 1594 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1595 | |
1596 | return count; | |
1597 | } | |
1598 | ||
66e3d5c0 | 1599 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1600 | { |
66e3d5c0 DV |
1601 | struct drm_device *dev = crtc->base.dev; |
1602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1603 | int reg = DPLL(crtc->pipe); | |
1604 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1605 | |
66e3d5c0 | 1606 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1607 | |
63d7bbe9 | 1608 | /* No really, not for ILK+ */ |
3d13ef2e | 1609 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1610 | |
1611 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1612 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1613 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1614 | |
1c4e0274 VS |
1615 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1616 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1617 | /* | |
1618 | * It appears to be important that we don't enable this | |
1619 | * for the current pipe before otherwise configuring the | |
1620 | * PLL. No idea how this should be handled if multiple | |
1621 | * DVO outputs are enabled simultaneosly. | |
1622 | */ | |
1623 | dpll |= DPLL_DVO_2X_MODE; | |
1624 | I915_WRITE(DPLL(!crtc->pipe), | |
1625 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1626 | } | |
66e3d5c0 DV |
1627 | |
1628 | /* Wait for the clocks to stabilize. */ | |
1629 | POSTING_READ(reg); | |
1630 | udelay(150); | |
1631 | ||
1632 | if (INTEL_INFO(dev)->gen >= 4) { | |
1633 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1634 | crtc->config.dpll_hw_state.dpll_md); | |
1635 | } else { | |
1636 | /* The pixel multiplier can only be updated once the | |
1637 | * DPLL is enabled and the clocks are stable. | |
1638 | * | |
1639 | * So write it again. | |
1640 | */ | |
1641 | I915_WRITE(reg, dpll); | |
1642 | } | |
63d7bbe9 JB |
1643 | |
1644 | /* We do this three times for luck */ | |
66e3d5c0 | 1645 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1646 | POSTING_READ(reg); |
1647 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1648 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1649 | POSTING_READ(reg); |
1650 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1651 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1652 | POSTING_READ(reg); |
1653 | udelay(150); /* wait for warmup */ | |
1654 | } | |
1655 | ||
1656 | /** | |
50b44a44 | 1657 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1658 | * @dev_priv: i915 private structure |
1659 | * @pipe: pipe PLL to disable | |
1660 | * | |
1661 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1662 | * | |
1663 | * Note! This is for pre-ILK only. | |
1664 | */ | |
1c4e0274 | 1665 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1666 | { |
1c4e0274 VS |
1667 | struct drm_device *dev = crtc->base.dev; |
1668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1669 | enum pipe pipe = crtc->pipe; | |
1670 | ||
1671 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1672 | if (IS_I830(dev) && | |
409ee761 | 1673 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1674 | intel_num_dvo_pipes(dev) == 1) { |
1675 | I915_WRITE(DPLL(PIPE_B), | |
1676 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1677 | I915_WRITE(DPLL(PIPE_A), | |
1678 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1679 | } | |
1680 | ||
b6b5d049 VS |
1681 | /* Don't disable pipe or pipe PLLs if needed */ |
1682 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1683 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1684 | return; |
1685 | ||
1686 | /* Make sure the pipe isn't still relying on us */ | |
1687 | assert_pipe_disabled(dev_priv, pipe); | |
1688 | ||
50b44a44 DV |
1689 | I915_WRITE(DPLL(pipe), 0); |
1690 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1691 | } |
1692 | ||
f6071166 JB |
1693 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1694 | { | |
1695 | u32 val = 0; | |
1696 | ||
1697 | /* Make sure the pipe isn't still relying on us */ | |
1698 | assert_pipe_disabled(dev_priv, pipe); | |
1699 | ||
e5cbfbfb ID |
1700 | /* |
1701 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1702 | * The latter is needed for VGA hotplug / manual detection. | |
1703 | */ | |
f6071166 | 1704 | if (pipe == PIPE_B) |
e5cbfbfb | 1705 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1706 | I915_WRITE(DPLL(pipe), val); |
1707 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1708 | |
1709 | } | |
1710 | ||
1711 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1712 | { | |
d752048d | 1713 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1714 | u32 val; |
1715 | ||
a11b0703 VS |
1716 | /* Make sure the pipe isn't still relying on us */ |
1717 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1718 | |
a11b0703 | 1719 | /* Set PLL en = 0 */ |
d17ec4ce | 1720 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1721 | if (pipe != PIPE_A) |
1722 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1723 | I915_WRITE(DPLL(pipe), val); | |
1724 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1725 | |
1726 | mutex_lock(&dev_priv->dpio_lock); | |
1727 | ||
1728 | /* Disable 10bit clock to display controller */ | |
1729 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1730 | val &= ~DPIO_DCLKP_EN; | |
1731 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1732 | ||
61407f6d VS |
1733 | /* disable left/right clock distribution */ |
1734 | if (pipe != PIPE_B) { | |
1735 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1736 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1737 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1738 | } else { | |
1739 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1740 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1741 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1742 | } | |
1743 | ||
d752048d | 1744 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1745 | } |
1746 | ||
e4607fcf CML |
1747 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1748 | struct intel_digital_port *dport) | |
89b667f8 JB |
1749 | { |
1750 | u32 port_mask; | |
00fc31b7 | 1751 | int dpll_reg; |
89b667f8 | 1752 | |
e4607fcf CML |
1753 | switch (dport->port) { |
1754 | case PORT_B: | |
89b667f8 | 1755 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1756 | dpll_reg = DPLL(0); |
e4607fcf CML |
1757 | break; |
1758 | case PORT_C: | |
89b667f8 | 1759 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1760 | dpll_reg = DPLL(0); |
1761 | break; | |
1762 | case PORT_D: | |
1763 | port_mask = DPLL_PORTD_READY_MASK; | |
1764 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1765 | break; |
1766 | default: | |
1767 | BUG(); | |
1768 | } | |
89b667f8 | 1769 | |
00fc31b7 | 1770 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1771 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1772 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1773 | } |
1774 | ||
b14b1055 DV |
1775 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1776 | { | |
1777 | struct drm_device *dev = crtc->base.dev; | |
1778 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1779 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1780 | ||
be19f0ff CW |
1781 | if (WARN_ON(pll == NULL)) |
1782 | return; | |
1783 | ||
3e369b76 | 1784 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1785 | if (pll->active == 0) { |
1786 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1787 | WARN_ON(pll->on); | |
1788 | assert_shared_dpll_disabled(dev_priv, pll); | |
1789 | ||
1790 | pll->mode_set(dev_priv, pll); | |
1791 | } | |
1792 | } | |
1793 | ||
92f2584a | 1794 | /** |
85b3894f | 1795 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1796 | * @dev_priv: i915 private structure |
1797 | * @pipe: pipe PLL to enable | |
1798 | * | |
1799 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1800 | * drives the transcoder clock. | |
1801 | */ | |
85b3894f | 1802 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1803 | { |
3d13ef2e DL |
1804 | struct drm_device *dev = crtc->base.dev; |
1805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1806 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1807 | |
87a875bb | 1808 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1809 | return; |
1810 | ||
3e369b76 | 1811 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1812 | return; |
ee7b9f93 | 1813 | |
74dd6928 | 1814 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1815 | pll->name, pll->active, pll->on, |
e2b78267 | 1816 | crtc->base.base.id); |
92f2584a | 1817 | |
cdbd2316 DV |
1818 | if (pll->active++) { |
1819 | WARN_ON(!pll->on); | |
e9d6944e | 1820 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1821 | return; |
1822 | } | |
f4a091c7 | 1823 | WARN_ON(pll->on); |
ee7b9f93 | 1824 | |
bd2bb1b9 PZ |
1825 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1826 | ||
46edb027 | 1827 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1828 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1829 | pll->on = true; |
92f2584a JB |
1830 | } |
1831 | ||
f6daaec2 | 1832 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1833 | { |
3d13ef2e DL |
1834 | struct drm_device *dev = crtc->base.dev; |
1835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1836 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1837 | |
92f2584a | 1838 | /* PCH only available on ILK+ */ |
3d13ef2e | 1839 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1840 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1841 | return; |
92f2584a | 1842 | |
3e369b76 | 1843 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1844 | return; |
7a419866 | 1845 | |
46edb027 DV |
1846 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1847 | pll->name, pll->active, pll->on, | |
e2b78267 | 1848 | crtc->base.base.id); |
7a419866 | 1849 | |
48da64a8 | 1850 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1851 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1852 | return; |
1853 | } | |
1854 | ||
e9d6944e | 1855 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1856 | WARN_ON(!pll->on); |
cdbd2316 | 1857 | if (--pll->active) |
7a419866 | 1858 | return; |
ee7b9f93 | 1859 | |
46edb027 | 1860 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1861 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1862 | pll->on = false; |
bd2bb1b9 PZ |
1863 | |
1864 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1865 | } |
1866 | ||
b8a4f404 PZ |
1867 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1868 | enum pipe pipe) | |
040484af | 1869 | { |
23670b32 | 1870 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1871 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1872 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1873 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1874 | |
1875 | /* PCH only available on ILK+ */ | |
55522f37 | 1876 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1877 | |
1878 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1879 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1880 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1881 | |
1882 | /* FDI must be feeding us bits for PCH ports */ | |
1883 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1884 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1885 | ||
23670b32 DV |
1886 | if (HAS_PCH_CPT(dev)) { |
1887 | /* Workaround: Set the timing override bit before enabling the | |
1888 | * pch transcoder. */ | |
1889 | reg = TRANS_CHICKEN2(pipe); | |
1890 | val = I915_READ(reg); | |
1891 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1892 | I915_WRITE(reg, val); | |
59c859d6 | 1893 | } |
23670b32 | 1894 | |
ab9412ba | 1895 | reg = PCH_TRANSCONF(pipe); |
040484af | 1896 | val = I915_READ(reg); |
5f7f726d | 1897 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1898 | |
1899 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1900 | /* | |
1901 | * make the BPC in transcoder be consistent with | |
1902 | * that in pipeconf reg. | |
1903 | */ | |
dfd07d72 DV |
1904 | val &= ~PIPECONF_BPC_MASK; |
1905 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1906 | } |
5f7f726d PZ |
1907 | |
1908 | val &= ~TRANS_INTERLACE_MASK; | |
1909 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1910 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1911 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1912 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1913 | else | |
1914 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1915 | else |
1916 | val |= TRANS_PROGRESSIVE; | |
1917 | ||
040484af JB |
1918 | I915_WRITE(reg, val | TRANS_ENABLE); |
1919 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1920 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1921 | } |
1922 | ||
8fb033d7 | 1923 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1924 | enum transcoder cpu_transcoder) |
040484af | 1925 | { |
8fb033d7 | 1926 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1927 | |
1928 | /* PCH only available on ILK+ */ | |
55522f37 | 1929 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 1930 | |
8fb033d7 | 1931 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1932 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1933 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1934 | |
223a6fdf PZ |
1935 | /* Workaround: set timing override bit. */ |
1936 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1937 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1938 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1939 | ||
25f3ef11 | 1940 | val = TRANS_ENABLE; |
937bb610 | 1941 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1942 | |
9a76b1c6 PZ |
1943 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1944 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1945 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1946 | else |
1947 | val |= TRANS_PROGRESSIVE; | |
1948 | ||
ab9412ba DV |
1949 | I915_WRITE(LPT_TRANSCONF, val); |
1950 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1951 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1952 | } |
1953 | ||
b8a4f404 PZ |
1954 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1955 | enum pipe pipe) | |
040484af | 1956 | { |
23670b32 DV |
1957 | struct drm_device *dev = dev_priv->dev; |
1958 | uint32_t reg, val; | |
040484af JB |
1959 | |
1960 | /* FDI relies on the transcoder */ | |
1961 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1962 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1963 | ||
291906f1 JB |
1964 | /* Ports must be off as well */ |
1965 | assert_pch_ports_disabled(dev_priv, pipe); | |
1966 | ||
ab9412ba | 1967 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1968 | val = I915_READ(reg); |
1969 | val &= ~TRANS_ENABLE; | |
1970 | I915_WRITE(reg, val); | |
1971 | /* wait for PCH transcoder off, transcoder state */ | |
1972 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1973 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1974 | |
1975 | if (!HAS_PCH_IBX(dev)) { | |
1976 | /* Workaround: Clear the timing override chicken bit again. */ | |
1977 | reg = TRANS_CHICKEN2(pipe); | |
1978 | val = I915_READ(reg); | |
1979 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1980 | I915_WRITE(reg, val); | |
1981 | } | |
040484af JB |
1982 | } |
1983 | ||
ab4d966c | 1984 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1985 | { |
8fb033d7 PZ |
1986 | u32 val; |
1987 | ||
ab9412ba | 1988 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1989 | val &= ~TRANS_ENABLE; |
ab9412ba | 1990 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1991 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1992 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1993 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1994 | |
1995 | /* Workaround: clear timing override bit. */ | |
1996 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1997 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1998 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1999 | } |
2000 | ||
b24e7179 | 2001 | /** |
309cfea8 | 2002 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2003 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2004 | * |
0372264a | 2005 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2006 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2007 | */ |
e1fdc473 | 2008 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2009 | { |
0372264a PZ |
2010 | struct drm_device *dev = crtc->base.dev; |
2011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2012 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2013 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2014 | pipe); | |
1a240d4d | 2015 | enum pipe pch_transcoder; |
b24e7179 JB |
2016 | int reg; |
2017 | u32 val; | |
2018 | ||
58c6eaa2 | 2019 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2020 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2021 | assert_sprites_disabled(dev_priv, pipe); |
2022 | ||
681e5811 | 2023 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2024 | pch_transcoder = TRANSCODER_A; |
2025 | else | |
2026 | pch_transcoder = pipe; | |
2027 | ||
b24e7179 JB |
2028 | /* |
2029 | * A pipe without a PLL won't actually be able to drive bits from | |
2030 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2031 | * need the check. | |
2032 | */ | |
2033 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
409ee761 | 2034 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2035 | assert_dsi_pll_enabled(dev_priv); |
2036 | else | |
2037 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2038 | else { |
30421c4f | 2039 | if (crtc->config.has_pch_encoder) { |
040484af | 2040 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2041 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2042 | assert_fdi_tx_pll_enabled(dev_priv, |
2043 | (enum pipe) cpu_transcoder); | |
040484af JB |
2044 | } |
2045 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2046 | } | |
b24e7179 | 2047 | |
702e7a56 | 2048 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2049 | val = I915_READ(reg); |
7ad25d48 | 2050 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2051 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2052 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2053 | return; |
7ad25d48 | 2054 | } |
00d70b15 CW |
2055 | |
2056 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2057 | POSTING_READ(reg); |
b24e7179 JB |
2058 | } |
2059 | ||
2060 | /** | |
309cfea8 | 2061 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2062 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2063 | * |
575f7ab7 VS |
2064 | * Disable the pipe of @crtc, making sure that various hardware |
2065 | * specific requirements are met, if applicable, e.g. plane | |
2066 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2067 | * |
2068 | * Will wait until the pipe has shut down before returning. | |
2069 | */ | |
575f7ab7 | 2070 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2071 | { |
575f7ab7 VS |
2072 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
2073 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
2074 | enum pipe pipe = crtc->pipe; | |
b24e7179 JB |
2075 | int reg; |
2076 | u32 val; | |
2077 | ||
2078 | /* | |
2079 | * Make sure planes won't keep trying to pump pixels to us, | |
2080 | * or we might hang the display. | |
2081 | */ | |
2082 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2083 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2084 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2085 | |
702e7a56 | 2086 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2087 | val = I915_READ(reg); |
00d70b15 CW |
2088 | if ((val & PIPECONF_ENABLE) == 0) |
2089 | return; | |
2090 | ||
67adc644 VS |
2091 | /* |
2092 | * Double wide has implications for planes | |
2093 | * so best keep it disabled when not needed. | |
2094 | */ | |
2095 | if (crtc->config.double_wide) | |
2096 | val &= ~PIPECONF_DOUBLE_WIDE; | |
2097 | ||
2098 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2099 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2100 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2101 | val &= ~PIPECONF_ENABLE; |
2102 | ||
2103 | I915_WRITE(reg, val); | |
2104 | if ((val & PIPECONF_ENABLE) == 0) | |
2105 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2106 | } |
2107 | ||
d74362c9 KP |
2108 | /* |
2109 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2110 | * trigger in order to latch. The display address reg provides this. | |
2111 | */ | |
1dba99f4 VS |
2112 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2113 | enum plane plane) | |
d74362c9 | 2114 | { |
3d13ef2e DL |
2115 | struct drm_device *dev = dev_priv->dev; |
2116 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2117 | |
2118 | I915_WRITE(reg, I915_READ(reg)); | |
2119 | POSTING_READ(reg); | |
d74362c9 KP |
2120 | } |
2121 | ||
b24e7179 | 2122 | /** |
262ca2b0 | 2123 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2124 | * @plane: plane to be enabled |
2125 | * @crtc: crtc for the plane | |
b24e7179 | 2126 | * |
fdd508a6 | 2127 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2128 | */ |
fdd508a6 VS |
2129 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2130 | struct drm_crtc *crtc) | |
b24e7179 | 2131 | { |
fdd508a6 VS |
2132 | struct drm_device *dev = plane->dev; |
2133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2135 | |
2136 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2137 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2138 | |
98ec7739 VS |
2139 | if (intel_crtc->primary_enabled) |
2140 | return; | |
0037f71c | 2141 | |
4c445e0e | 2142 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2143 | |
fdd508a6 VS |
2144 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2145 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2146 | |
2147 | /* | |
2148 | * BDW signals flip done immediately if the plane | |
2149 | * is disabled, even if the plane enable is already | |
2150 | * armed to occur at the next vblank :( | |
2151 | */ | |
2152 | if (IS_BROADWELL(dev)) | |
2153 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2154 | } |
2155 | ||
b24e7179 | 2156 | /** |
262ca2b0 | 2157 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2158 | * @plane: plane to be disabled |
2159 | * @crtc: crtc for the plane | |
b24e7179 | 2160 | * |
fdd508a6 | 2161 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2162 | */ |
fdd508a6 VS |
2163 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2164 | struct drm_crtc *crtc) | |
b24e7179 | 2165 | { |
fdd508a6 VS |
2166 | struct drm_device *dev = plane->dev; |
2167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2168 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2169 | ||
32b7eeec MR |
2170 | if (WARN_ON(!intel_crtc->active)) |
2171 | return; | |
b24e7179 | 2172 | |
98ec7739 VS |
2173 | if (!intel_crtc->primary_enabled) |
2174 | return; | |
0037f71c | 2175 | |
4c445e0e | 2176 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2177 | |
fdd508a6 VS |
2178 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2179 | crtc->x, crtc->y); | |
b24e7179 JB |
2180 | } |
2181 | ||
693db184 CW |
2182 | static bool need_vtd_wa(struct drm_device *dev) |
2183 | { | |
2184 | #ifdef CONFIG_INTEL_IOMMU | |
2185 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2186 | return true; | |
2187 | #endif | |
2188 | return false; | |
2189 | } | |
2190 | ||
a57ce0b2 JB |
2191 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2192 | { | |
2193 | int tile_height; | |
2194 | ||
2195 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2196 | return ALIGN(height, tile_height); | |
2197 | } | |
2198 | ||
127bd2ac | 2199 | int |
850c4cdc TU |
2200 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2201 | struct drm_framebuffer *fb, | |
a4872ba6 | 2202 | struct intel_engine_cs *pipelined) |
6b95a207 | 2203 | { |
850c4cdc | 2204 | struct drm_device *dev = fb->dev; |
ce453d81 | 2205 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2206 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 KH |
2207 | u32 alignment; |
2208 | int ret; | |
2209 | ||
ebcdd39e MR |
2210 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2211 | ||
05394f39 | 2212 | switch (obj->tiling_mode) { |
6b95a207 | 2213 | case I915_TILING_NONE: |
1fada4cc DL |
2214 | if (INTEL_INFO(dev)->gen >= 9) |
2215 | alignment = 256 * 1024; | |
2216 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2217 | alignment = 128 * 1024; |
a6c45cf0 | 2218 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2219 | alignment = 4 * 1024; |
2220 | else | |
2221 | alignment = 64 * 1024; | |
6b95a207 KH |
2222 | break; |
2223 | case I915_TILING_X: | |
1fada4cc DL |
2224 | if (INTEL_INFO(dev)->gen >= 9) |
2225 | alignment = 256 * 1024; | |
2226 | else { | |
2227 | /* pin() will align the object as required by fence */ | |
2228 | alignment = 0; | |
2229 | } | |
6b95a207 KH |
2230 | break; |
2231 | case I915_TILING_Y: | |
80075d49 | 2232 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2233 | return -EINVAL; |
2234 | default: | |
2235 | BUG(); | |
2236 | } | |
2237 | ||
693db184 CW |
2238 | /* Note that the w/a also requires 64 PTE of padding following the |
2239 | * bo. We currently fill all unused PTE with the shadow page and so | |
2240 | * we should always have valid PTE following the scanout preventing | |
2241 | * the VT-d warning. | |
2242 | */ | |
2243 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2244 | alignment = 256 * 1024; | |
2245 | ||
d6dd6843 PZ |
2246 | /* |
2247 | * Global gtt pte registers are special registers which actually forward | |
2248 | * writes to a chunk of system memory. Which means that there is no risk | |
2249 | * that the register values disappear as soon as we call | |
2250 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2251 | * pin/unpin/fence and not more. | |
2252 | */ | |
2253 | intel_runtime_pm_get(dev_priv); | |
2254 | ||
ce453d81 | 2255 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2256 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2257 | if (ret) |
ce453d81 | 2258 | goto err_interruptible; |
6b95a207 KH |
2259 | |
2260 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2261 | * fence, whereas 965+ only requires a fence if using | |
2262 | * framebuffer compression. For simplicity, we always install | |
2263 | * a fence as the cost is not that onerous. | |
2264 | */ | |
06d98131 | 2265 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2266 | if (ret) |
2267 | goto err_unpin; | |
1690e1eb | 2268 | |
9a5a53b3 | 2269 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2270 | |
ce453d81 | 2271 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2272 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2273 | return 0; |
48b956c5 CW |
2274 | |
2275 | err_unpin: | |
cc98b413 | 2276 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2277 | err_interruptible: |
2278 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2279 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2280 | return ret; |
6b95a207 KH |
2281 | } |
2282 | ||
1690e1eb CW |
2283 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2284 | { | |
ebcdd39e MR |
2285 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2286 | ||
1690e1eb | 2287 | i915_gem_object_unpin_fence(obj); |
cc98b413 | 2288 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2289 | } |
2290 | ||
c2c75131 DV |
2291 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2292 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2293 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2294 | unsigned int tiling_mode, | |
2295 | unsigned int cpp, | |
2296 | unsigned int pitch) | |
c2c75131 | 2297 | { |
bc752862 CW |
2298 | if (tiling_mode != I915_TILING_NONE) { |
2299 | unsigned int tile_rows, tiles; | |
c2c75131 | 2300 | |
bc752862 CW |
2301 | tile_rows = *y / 8; |
2302 | *y %= 8; | |
c2c75131 | 2303 | |
bc752862 CW |
2304 | tiles = *x / (512/cpp); |
2305 | *x %= 512/cpp; | |
2306 | ||
2307 | return tile_rows * pitch * 8 + tiles * 4096; | |
2308 | } else { | |
2309 | unsigned int offset; | |
2310 | ||
2311 | offset = *y * pitch + *x * cpp; | |
2312 | *y = 0; | |
2313 | *x = (offset & 4095) / cpp; | |
2314 | return offset & -4096; | |
2315 | } | |
c2c75131 DV |
2316 | } |
2317 | ||
46f297fb JB |
2318 | int intel_format_to_fourcc(int format) |
2319 | { | |
2320 | switch (format) { | |
2321 | case DISPPLANE_8BPP: | |
2322 | return DRM_FORMAT_C8; | |
2323 | case DISPPLANE_BGRX555: | |
2324 | return DRM_FORMAT_XRGB1555; | |
2325 | case DISPPLANE_BGRX565: | |
2326 | return DRM_FORMAT_RGB565; | |
2327 | default: | |
2328 | case DISPPLANE_BGRX888: | |
2329 | return DRM_FORMAT_XRGB8888; | |
2330 | case DISPPLANE_RGBX888: | |
2331 | return DRM_FORMAT_XBGR8888; | |
2332 | case DISPPLANE_BGRX101010: | |
2333 | return DRM_FORMAT_XRGB2101010; | |
2334 | case DISPPLANE_RGBX101010: | |
2335 | return DRM_FORMAT_XBGR2101010; | |
2336 | } | |
2337 | } | |
2338 | ||
484b41dd | 2339 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2340 | struct intel_plane_config *plane_config) |
2341 | { | |
2342 | struct drm_device *dev = crtc->base.dev; | |
2343 | struct drm_i915_gem_object *obj = NULL; | |
2344 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2345 | u32 base = plane_config->base; | |
2346 | ||
ff2652ea CW |
2347 | if (plane_config->size == 0) |
2348 | return false; | |
2349 | ||
46f297fb JB |
2350 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2351 | plane_config->size); | |
2352 | if (!obj) | |
484b41dd | 2353 | return false; |
46f297fb JB |
2354 | |
2355 | if (plane_config->tiled) { | |
2356 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2357 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2358 | } |
2359 | ||
66e514c1 DA |
2360 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2361 | mode_cmd.width = crtc->base.primary->fb->width; | |
2362 | mode_cmd.height = crtc->base.primary->fb->height; | |
2363 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2364 | |
2365 | mutex_lock(&dev->struct_mutex); | |
2366 | ||
66e514c1 | 2367 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2368 | &mode_cmd, obj)) { |
46f297fb JB |
2369 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2370 | goto out_unref_obj; | |
2371 | } | |
2372 | ||
a071fa00 | 2373 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
46f297fb | 2374 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2375 | |
2376 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2377 | return true; | |
46f297fb JB |
2378 | |
2379 | out_unref_obj: | |
2380 | drm_gem_object_unreference(&obj->base); | |
2381 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2382 | return false; |
2383 | } | |
2384 | ||
2385 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2386 | struct intel_plane_config *plane_config) | |
2387 | { | |
2388 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2389 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2390 | struct drm_crtc *c; |
2391 | struct intel_crtc *i; | |
2ff8fde1 | 2392 | struct drm_i915_gem_object *obj; |
484b41dd | 2393 | |
66e514c1 | 2394 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2395 | return; |
2396 | ||
2397 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2398 | return; | |
2399 | ||
66e514c1 DA |
2400 | kfree(intel_crtc->base.primary->fb); |
2401 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2402 | |
2403 | /* | |
2404 | * Failed to alloc the obj, check to see if we should share | |
2405 | * an fb with another CRTC instead | |
2406 | */ | |
70e1e0ec | 2407 | for_each_crtc(dev, c) { |
484b41dd JB |
2408 | i = to_intel_crtc(c); |
2409 | ||
2410 | if (c == &intel_crtc->base) | |
2411 | continue; | |
2412 | ||
2ff8fde1 MR |
2413 | if (!i->active) |
2414 | continue; | |
2415 | ||
2416 | obj = intel_fb_obj(c->primary->fb); | |
2417 | if (obj == NULL) | |
484b41dd JB |
2418 | continue; |
2419 | ||
2ff8fde1 | 2420 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
d9ceb816 JB |
2421 | if (obj->tiling_mode != I915_TILING_NONE) |
2422 | dev_priv->preserve_bios_swizzle = true; | |
2423 | ||
66e514c1 DA |
2424 | drm_framebuffer_reference(c->primary->fb); |
2425 | intel_crtc->base.primary->fb = c->primary->fb; | |
2ff8fde1 | 2426 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
484b41dd JB |
2427 | break; |
2428 | } | |
2429 | } | |
46f297fb JB |
2430 | } |
2431 | ||
29b9bde6 DV |
2432 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2433 | struct drm_framebuffer *fb, | |
2434 | int x, int y) | |
81255565 JB |
2435 | { |
2436 | struct drm_device *dev = crtc->dev; | |
2437 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2438 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2439 | struct drm_i915_gem_object *obj; |
81255565 | 2440 | int plane = intel_crtc->plane; |
e506a0c6 | 2441 | unsigned long linear_offset; |
81255565 | 2442 | u32 dspcntr; |
f45651ba | 2443 | u32 reg = DSPCNTR(plane); |
48404c1e | 2444 | int pixel_size; |
f45651ba | 2445 | |
fdd508a6 VS |
2446 | if (!intel_crtc->primary_enabled) { |
2447 | I915_WRITE(reg, 0); | |
2448 | if (INTEL_INFO(dev)->gen >= 4) | |
2449 | I915_WRITE(DSPSURF(plane), 0); | |
2450 | else | |
2451 | I915_WRITE(DSPADDR(plane), 0); | |
2452 | POSTING_READ(reg); | |
2453 | return; | |
2454 | } | |
2455 | ||
c9ba6fad VS |
2456 | obj = intel_fb_obj(fb); |
2457 | if (WARN_ON(obj == NULL)) | |
2458 | return; | |
2459 | ||
2460 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2461 | ||
f45651ba VS |
2462 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2463 | ||
fdd508a6 | 2464 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2465 | |
2466 | if (INTEL_INFO(dev)->gen < 4) { | |
2467 | if (intel_crtc->pipe == PIPE_B) | |
2468 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2469 | ||
2470 | /* pipesrc and dspsize control the size that is scaled from, | |
2471 | * which should always be the user's requested size. | |
2472 | */ | |
2473 | I915_WRITE(DSPSIZE(plane), | |
2474 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
2475 | (intel_crtc->config.pipe_src_w - 1)); | |
2476 | I915_WRITE(DSPPOS(plane), 0); | |
c14b0485 VS |
2477 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2478 | I915_WRITE(PRIMSIZE(plane), | |
2479 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
2480 | (intel_crtc->config.pipe_src_w - 1)); | |
2481 | I915_WRITE(PRIMPOS(plane), 0); | |
2482 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2483 | } |
81255565 | 2484 | |
57779d06 VS |
2485 | switch (fb->pixel_format) { |
2486 | case DRM_FORMAT_C8: | |
81255565 JB |
2487 | dspcntr |= DISPPLANE_8BPP; |
2488 | break; | |
57779d06 VS |
2489 | case DRM_FORMAT_XRGB1555: |
2490 | case DRM_FORMAT_ARGB1555: | |
2491 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2492 | break; |
57779d06 VS |
2493 | case DRM_FORMAT_RGB565: |
2494 | dspcntr |= DISPPLANE_BGRX565; | |
2495 | break; | |
2496 | case DRM_FORMAT_XRGB8888: | |
2497 | case DRM_FORMAT_ARGB8888: | |
2498 | dspcntr |= DISPPLANE_BGRX888; | |
2499 | break; | |
2500 | case DRM_FORMAT_XBGR8888: | |
2501 | case DRM_FORMAT_ABGR8888: | |
2502 | dspcntr |= DISPPLANE_RGBX888; | |
2503 | break; | |
2504 | case DRM_FORMAT_XRGB2101010: | |
2505 | case DRM_FORMAT_ARGB2101010: | |
2506 | dspcntr |= DISPPLANE_BGRX101010; | |
2507 | break; | |
2508 | case DRM_FORMAT_XBGR2101010: | |
2509 | case DRM_FORMAT_ABGR2101010: | |
2510 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2511 | break; |
2512 | default: | |
baba133a | 2513 | BUG(); |
81255565 | 2514 | } |
57779d06 | 2515 | |
f45651ba VS |
2516 | if (INTEL_INFO(dev)->gen >= 4 && |
2517 | obj->tiling_mode != I915_TILING_NONE) | |
2518 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2519 | |
de1aa629 VS |
2520 | if (IS_G4X(dev)) |
2521 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2522 | ||
b9897127 | 2523 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2524 | |
c2c75131 DV |
2525 | if (INTEL_INFO(dev)->gen >= 4) { |
2526 | intel_crtc->dspaddr_offset = | |
bc752862 | 2527 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2528 | pixel_size, |
bc752862 | 2529 | fb->pitches[0]); |
c2c75131 DV |
2530 | linear_offset -= intel_crtc->dspaddr_offset; |
2531 | } else { | |
e506a0c6 | 2532 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2533 | } |
e506a0c6 | 2534 | |
48404c1e SJ |
2535 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2536 | dspcntr |= DISPPLANE_ROTATE_180; | |
2537 | ||
2538 | x += (intel_crtc->config.pipe_src_w - 1); | |
2539 | y += (intel_crtc->config.pipe_src_h - 1); | |
2540 | ||
2541 | /* Finding the last pixel of the last line of the display | |
2542 | data and adding to linear_offset*/ | |
2543 | linear_offset += | |
2544 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2545 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2546 | } | |
2547 | ||
2548 | I915_WRITE(reg, dspcntr); | |
2549 | ||
f343c5f6 BW |
2550 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2551 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2552 | fb->pitches[0]); | |
01f2c773 | 2553 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2554 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2555 | I915_WRITE(DSPSURF(plane), |
2556 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2557 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2558 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2559 | } else |
f343c5f6 | 2560 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2561 | POSTING_READ(reg); |
17638cd6 JB |
2562 | } |
2563 | ||
29b9bde6 DV |
2564 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2565 | struct drm_framebuffer *fb, | |
2566 | int x, int y) | |
17638cd6 JB |
2567 | { |
2568 | struct drm_device *dev = crtc->dev; | |
2569 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2570 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2571 | struct drm_i915_gem_object *obj; |
17638cd6 | 2572 | int plane = intel_crtc->plane; |
e506a0c6 | 2573 | unsigned long linear_offset; |
17638cd6 | 2574 | u32 dspcntr; |
f45651ba | 2575 | u32 reg = DSPCNTR(plane); |
48404c1e | 2576 | int pixel_size; |
f45651ba | 2577 | |
fdd508a6 VS |
2578 | if (!intel_crtc->primary_enabled) { |
2579 | I915_WRITE(reg, 0); | |
2580 | I915_WRITE(DSPSURF(plane), 0); | |
2581 | POSTING_READ(reg); | |
2582 | return; | |
2583 | } | |
2584 | ||
c9ba6fad VS |
2585 | obj = intel_fb_obj(fb); |
2586 | if (WARN_ON(obj == NULL)) | |
2587 | return; | |
2588 | ||
2589 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2590 | ||
f45651ba VS |
2591 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2592 | ||
fdd508a6 | 2593 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2594 | |
2595 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2596 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2597 | |
57779d06 VS |
2598 | switch (fb->pixel_format) { |
2599 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2600 | dspcntr |= DISPPLANE_8BPP; |
2601 | break; | |
57779d06 VS |
2602 | case DRM_FORMAT_RGB565: |
2603 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2604 | break; |
57779d06 VS |
2605 | case DRM_FORMAT_XRGB8888: |
2606 | case DRM_FORMAT_ARGB8888: | |
2607 | dspcntr |= DISPPLANE_BGRX888; | |
2608 | break; | |
2609 | case DRM_FORMAT_XBGR8888: | |
2610 | case DRM_FORMAT_ABGR8888: | |
2611 | dspcntr |= DISPPLANE_RGBX888; | |
2612 | break; | |
2613 | case DRM_FORMAT_XRGB2101010: | |
2614 | case DRM_FORMAT_ARGB2101010: | |
2615 | dspcntr |= DISPPLANE_BGRX101010; | |
2616 | break; | |
2617 | case DRM_FORMAT_XBGR2101010: | |
2618 | case DRM_FORMAT_ABGR2101010: | |
2619 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2620 | break; |
2621 | default: | |
baba133a | 2622 | BUG(); |
17638cd6 JB |
2623 | } |
2624 | ||
2625 | if (obj->tiling_mode != I915_TILING_NONE) | |
2626 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2627 | |
f45651ba | 2628 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2629 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2630 | |
b9897127 | 2631 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2632 | intel_crtc->dspaddr_offset = |
bc752862 | 2633 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2634 | pixel_size, |
bc752862 | 2635 | fb->pitches[0]); |
c2c75131 | 2636 | linear_offset -= intel_crtc->dspaddr_offset; |
48404c1e SJ |
2637 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2638 | dspcntr |= DISPPLANE_ROTATE_180; | |
2639 | ||
2640 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
2641 | x += (intel_crtc->config.pipe_src_w - 1); | |
2642 | y += (intel_crtc->config.pipe_src_h - 1); | |
2643 | ||
2644 | /* Finding the last pixel of the last line of the display | |
2645 | data and adding to linear_offset*/ | |
2646 | linear_offset += | |
2647 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2648 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2649 | } | |
2650 | } | |
2651 | ||
2652 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2653 | |
f343c5f6 BW |
2654 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2655 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2656 | fb->pitches[0]); | |
01f2c773 | 2657 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2658 | I915_WRITE(DSPSURF(plane), |
2659 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2660 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2661 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2662 | } else { | |
2663 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2664 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2665 | } | |
17638cd6 | 2666 | POSTING_READ(reg); |
17638cd6 JB |
2667 | } |
2668 | ||
70d21f0e DL |
2669 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
2670 | struct drm_framebuffer *fb, | |
2671 | int x, int y) | |
2672 | { | |
2673 | struct drm_device *dev = crtc->dev; | |
2674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2675 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2676 | struct intel_framebuffer *intel_fb; | |
2677 | struct drm_i915_gem_object *obj; | |
2678 | int pipe = intel_crtc->pipe; | |
2679 | u32 plane_ctl, stride; | |
2680 | ||
2681 | if (!intel_crtc->primary_enabled) { | |
2682 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
2683 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
2684 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
2685 | return; | |
2686 | } | |
2687 | ||
2688 | plane_ctl = PLANE_CTL_ENABLE | | |
2689 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
2690 | PLANE_CTL_PIPE_CSC_ENABLE; | |
2691 | ||
2692 | switch (fb->pixel_format) { | |
2693 | case DRM_FORMAT_RGB565: | |
2694 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
2695 | break; | |
2696 | case DRM_FORMAT_XRGB8888: | |
2697 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2698 | break; | |
2699 | case DRM_FORMAT_XBGR8888: | |
2700 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2701 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2702 | break; | |
2703 | case DRM_FORMAT_XRGB2101010: | |
2704 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2705 | break; | |
2706 | case DRM_FORMAT_XBGR2101010: | |
2707 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2708 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2709 | break; | |
2710 | default: | |
2711 | BUG(); | |
2712 | } | |
2713 | ||
2714 | intel_fb = to_intel_framebuffer(fb); | |
2715 | obj = intel_fb->obj; | |
2716 | ||
2717 | /* | |
2718 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
2719 | * linear buffers or in number of tiles for tiled buffers. | |
2720 | */ | |
2721 | switch (obj->tiling_mode) { | |
2722 | case I915_TILING_NONE: | |
2723 | stride = fb->pitches[0] >> 6; | |
2724 | break; | |
2725 | case I915_TILING_X: | |
2726 | plane_ctl |= PLANE_CTL_TILED_X; | |
2727 | stride = fb->pitches[0] >> 9; | |
2728 | break; | |
2729 | default: | |
2730 | BUG(); | |
2731 | } | |
2732 | ||
2733 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
1447dde0 SJ |
2734 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) |
2735 | plane_ctl |= PLANE_CTL_ROTATE_180; | |
70d21f0e DL |
2736 | |
2737 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); | |
2738 | ||
2739 | DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n", | |
2740 | i915_gem_obj_ggtt_offset(obj), | |
2741 | x, y, fb->width, fb->height, | |
2742 | fb->pitches[0]); | |
2743 | ||
2744 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
2745 | I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); | |
2746 | I915_WRITE(PLANE_SIZE(pipe, 0), | |
2747 | (intel_crtc->config.pipe_src_h - 1) << 16 | | |
2748 | (intel_crtc->config.pipe_src_w - 1)); | |
2749 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
2750 | I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj)); | |
2751 | ||
2752 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
2753 | } | |
2754 | ||
17638cd6 JB |
2755 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2756 | static int | |
2757 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2758 | int x, int y, enum mode_set_atomic state) | |
2759 | { | |
2760 | struct drm_device *dev = crtc->dev; | |
2761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2762 | |
6b8e6ed0 CW |
2763 | if (dev_priv->display.disable_fbc) |
2764 | dev_priv->display.disable_fbc(dev); | |
81255565 | 2765 | |
29b9bde6 DV |
2766 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2767 | ||
2768 | return 0; | |
81255565 JB |
2769 | } |
2770 | ||
7514747d | 2771 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 2772 | { |
96a02917 VS |
2773 | struct drm_crtc *crtc; |
2774 | ||
70e1e0ec | 2775 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2777 | enum plane plane = intel_crtc->plane; | |
2778 | ||
2779 | intel_prepare_page_flip(dev, plane); | |
2780 | intel_finish_page_flip_plane(dev, plane); | |
2781 | } | |
7514747d VS |
2782 | } |
2783 | ||
2784 | static void intel_update_primary_planes(struct drm_device *dev) | |
2785 | { | |
2786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2787 | struct drm_crtc *crtc; | |
96a02917 | 2788 | |
70e1e0ec | 2789 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2790 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2791 | ||
51fd371b | 2792 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2793 | /* |
2794 | * FIXME: Once we have proper support for primary planes (and | |
2795 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2796 | * a NULL crtc->primary->fb. |
947fdaad | 2797 | */ |
f4510a27 | 2798 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2799 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2800 | crtc->primary->fb, |
262ca2b0 MR |
2801 | crtc->x, |
2802 | crtc->y); | |
51fd371b | 2803 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2804 | } |
2805 | } | |
2806 | ||
7514747d VS |
2807 | void intel_prepare_reset(struct drm_device *dev) |
2808 | { | |
f98ce92f VS |
2809 | struct drm_i915_private *dev_priv = to_i915(dev); |
2810 | struct intel_crtc *crtc; | |
2811 | ||
7514747d VS |
2812 | /* no reset support for gen2 */ |
2813 | if (IS_GEN2(dev)) | |
2814 | return; | |
2815 | ||
2816 | /* reset doesn't touch the display */ | |
2817 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
2818 | return; | |
2819 | ||
2820 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
2821 | |
2822 | /* | |
2823 | * Disabling the crtcs gracefully seems nicer. Also the | |
2824 | * g33 docs say we should at least disable all the planes. | |
2825 | */ | |
2826 | for_each_intel_crtc(dev, crtc) { | |
2827 | if (crtc->active) | |
2828 | dev_priv->display.crtc_disable(&crtc->base); | |
2829 | } | |
7514747d VS |
2830 | } |
2831 | ||
2832 | void intel_finish_reset(struct drm_device *dev) | |
2833 | { | |
2834 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2835 | ||
2836 | /* | |
2837 | * Flips in the rings will be nuked by the reset, | |
2838 | * so complete all pending flips so that user space | |
2839 | * will get its events and not get stuck. | |
2840 | */ | |
2841 | intel_complete_page_flips(dev); | |
2842 | ||
2843 | /* no reset support for gen2 */ | |
2844 | if (IS_GEN2(dev)) | |
2845 | return; | |
2846 | ||
2847 | /* reset doesn't touch the display */ | |
2848 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
2849 | /* | |
2850 | * Flips in the rings have been nuked by the reset, | |
2851 | * so update the base address of all primary | |
2852 | * planes to the the last fb to make sure we're | |
2853 | * showing the correct fb after a reset. | |
2854 | */ | |
2855 | intel_update_primary_planes(dev); | |
2856 | return; | |
2857 | } | |
2858 | ||
2859 | /* | |
2860 | * The display has been reset as well, | |
2861 | * so need a full re-initialization. | |
2862 | */ | |
2863 | intel_runtime_pm_disable_interrupts(dev_priv); | |
2864 | intel_runtime_pm_enable_interrupts(dev_priv); | |
2865 | ||
2866 | intel_modeset_init_hw(dev); | |
2867 | ||
2868 | spin_lock_irq(&dev_priv->irq_lock); | |
2869 | if (dev_priv->display.hpd_irq_setup) | |
2870 | dev_priv->display.hpd_irq_setup(dev); | |
2871 | spin_unlock_irq(&dev_priv->irq_lock); | |
2872 | ||
2873 | intel_modeset_setup_hw_state(dev, true); | |
2874 | ||
2875 | intel_hpd_init(dev_priv); | |
2876 | ||
2877 | drm_modeset_unlock_all(dev); | |
2878 | } | |
2879 | ||
14667a4b CW |
2880 | static int |
2881 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2882 | { | |
2ff8fde1 | 2883 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
2884 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2885 | bool was_interruptible = dev_priv->mm.interruptible; | |
2886 | int ret; | |
2887 | ||
14667a4b CW |
2888 | /* Big Hammer, we also need to ensure that any pending |
2889 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2890 | * current scanout is retired before unpinning the old | |
2891 | * framebuffer. | |
2892 | * | |
2893 | * This should only fail upon a hung GPU, in which case we | |
2894 | * can safely continue. | |
2895 | */ | |
2896 | dev_priv->mm.interruptible = false; | |
2897 | ret = i915_gem_object_finish_gpu(obj); | |
2898 | dev_priv->mm.interruptible = was_interruptible; | |
2899 | ||
2900 | return ret; | |
2901 | } | |
2902 | ||
7d5e3799 CW |
2903 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2904 | { | |
2905 | struct drm_device *dev = crtc->dev; | |
2906 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2907 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
2908 | bool pending; |
2909 | ||
2910 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2911 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2912 | return false; | |
2913 | ||
5e2d7afc | 2914 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 2915 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 2916 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
2917 | |
2918 | return pending; | |
2919 | } | |
2920 | ||
e30e8f75 GP |
2921 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
2922 | { | |
2923 | struct drm_device *dev = crtc->base.dev; | |
2924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2925 | const struct drm_display_mode *adjusted_mode; | |
2926 | ||
2927 | if (!i915.fastboot) | |
2928 | return; | |
2929 | ||
2930 | /* | |
2931 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2932 | * that in compute_mode_changes we check the native mode (not the pfit | |
2933 | * mode) to see if we can flip rather than do a full mode set. In the | |
2934 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2935 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2936 | * sized surface. | |
2937 | * | |
2938 | * To fix this properly, we need to hoist the checks up into | |
2939 | * compute_mode_changes (or above), check the actual pfit state and | |
2940 | * whether the platform allows pfit disable with pipe active, and only | |
2941 | * then update the pipesrc and pfit state, even on the flip path. | |
2942 | */ | |
2943 | ||
2944 | adjusted_mode = &crtc->config.adjusted_mode; | |
2945 | ||
2946 | I915_WRITE(PIPESRC(crtc->pipe), | |
2947 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
2948 | (adjusted_mode->crtc_vdisplay - 1)); | |
2949 | if (!crtc->config.pch_pfit.enabled && | |
409ee761 ACO |
2950 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2951 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
2952 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
2953 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
2954 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
2955 | } | |
2956 | crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; | |
2957 | crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
2958 | } | |
2959 | ||
5e84e1a4 ZW |
2960 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2961 | { | |
2962 | struct drm_device *dev = crtc->dev; | |
2963 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2964 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2965 | int pipe = intel_crtc->pipe; | |
2966 | u32 reg, temp; | |
2967 | ||
2968 | /* enable normal train */ | |
2969 | reg = FDI_TX_CTL(pipe); | |
2970 | temp = I915_READ(reg); | |
61e499bf | 2971 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2972 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2973 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2974 | } else { |
2975 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2976 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2977 | } |
5e84e1a4 ZW |
2978 | I915_WRITE(reg, temp); |
2979 | ||
2980 | reg = FDI_RX_CTL(pipe); | |
2981 | temp = I915_READ(reg); | |
2982 | if (HAS_PCH_CPT(dev)) { | |
2983 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2984 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2985 | } else { | |
2986 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2987 | temp |= FDI_LINK_TRAIN_NONE; | |
2988 | } | |
2989 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2990 | ||
2991 | /* wait one idle pattern time */ | |
2992 | POSTING_READ(reg); | |
2993 | udelay(1000); | |
357555c0 JB |
2994 | |
2995 | /* IVB wants error correction enabled */ | |
2996 | if (IS_IVYBRIDGE(dev)) | |
2997 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2998 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2999 | } |
3000 | ||
1fbc0d78 | 3001 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 3002 | { |
1fbc0d78 DV |
3003 | return crtc->base.enabled && crtc->active && |
3004 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
3005 | } |
3006 | ||
01a415fd DV |
3007 | static void ivb_modeset_global_resources(struct drm_device *dev) |
3008 | { | |
3009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3010 | struct intel_crtc *pipe_B_crtc = | |
3011 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
3012 | struct intel_crtc *pipe_C_crtc = | |
3013 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
3014 | uint32_t temp; | |
3015 | ||
1e833f40 DV |
3016 | /* |
3017 | * When everything is off disable fdi C so that we could enable fdi B | |
3018 | * with all lanes. Note that we don't care about enabled pipes without | |
3019 | * an enabled pch encoder. | |
3020 | */ | |
3021 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
3022 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
3023 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
3024 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3025 | ||
3026 | temp = I915_READ(SOUTH_CHICKEN1); | |
3027 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
3028 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
3029 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3030 | } | |
3031 | } | |
3032 | ||
8db9d77b ZW |
3033 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3034 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3035 | { | |
3036 | struct drm_device *dev = crtc->dev; | |
3037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3038 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3039 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3040 | u32 reg, temp, tries; |
8db9d77b | 3041 | |
1c8562f6 | 3042 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3043 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3044 | |
e1a44743 AJ |
3045 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3046 | for train result */ | |
5eddb70b CW |
3047 | reg = FDI_RX_IMR(pipe); |
3048 | temp = I915_READ(reg); | |
e1a44743 AJ |
3049 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3050 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3051 | I915_WRITE(reg, temp); |
3052 | I915_READ(reg); | |
e1a44743 AJ |
3053 | udelay(150); |
3054 | ||
8db9d77b | 3055 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3056 | reg = FDI_TX_CTL(pipe); |
3057 | temp = I915_READ(reg); | |
627eb5a3 DV |
3058 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3059 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
3060 | temp &= ~FDI_LINK_TRAIN_NONE; |
3061 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3062 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3063 | |
5eddb70b CW |
3064 | reg = FDI_RX_CTL(pipe); |
3065 | temp = I915_READ(reg); | |
8db9d77b ZW |
3066 | temp &= ~FDI_LINK_TRAIN_NONE; |
3067 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3068 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3069 | ||
3070 | POSTING_READ(reg); | |
8db9d77b ZW |
3071 | udelay(150); |
3072 | ||
5b2adf89 | 3073 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3074 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3075 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3076 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3077 | |
5eddb70b | 3078 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3079 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3080 | temp = I915_READ(reg); |
8db9d77b ZW |
3081 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3082 | ||
3083 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3084 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3085 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3086 | break; |
3087 | } | |
8db9d77b | 3088 | } |
e1a44743 | 3089 | if (tries == 5) |
5eddb70b | 3090 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3091 | |
3092 | /* Train 2 */ | |
5eddb70b CW |
3093 | reg = FDI_TX_CTL(pipe); |
3094 | temp = I915_READ(reg); | |
8db9d77b ZW |
3095 | temp &= ~FDI_LINK_TRAIN_NONE; |
3096 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3097 | I915_WRITE(reg, temp); |
8db9d77b | 3098 | |
5eddb70b CW |
3099 | reg = FDI_RX_CTL(pipe); |
3100 | temp = I915_READ(reg); | |
8db9d77b ZW |
3101 | temp &= ~FDI_LINK_TRAIN_NONE; |
3102 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3103 | I915_WRITE(reg, temp); |
8db9d77b | 3104 | |
5eddb70b CW |
3105 | POSTING_READ(reg); |
3106 | udelay(150); | |
8db9d77b | 3107 | |
5eddb70b | 3108 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3109 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3110 | temp = I915_READ(reg); |
8db9d77b ZW |
3111 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3112 | ||
3113 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3114 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3115 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3116 | break; | |
3117 | } | |
8db9d77b | 3118 | } |
e1a44743 | 3119 | if (tries == 5) |
5eddb70b | 3120 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3121 | |
3122 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3123 | |
8db9d77b ZW |
3124 | } |
3125 | ||
0206e353 | 3126 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3127 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3128 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3129 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3130 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3131 | }; | |
3132 | ||
3133 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3134 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3135 | { | |
3136 | struct drm_device *dev = crtc->dev; | |
3137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3138 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3139 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3140 | u32 reg, temp, i, retry; |
8db9d77b | 3141 | |
e1a44743 AJ |
3142 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3143 | for train result */ | |
5eddb70b CW |
3144 | reg = FDI_RX_IMR(pipe); |
3145 | temp = I915_READ(reg); | |
e1a44743 AJ |
3146 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3147 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3148 | I915_WRITE(reg, temp); |
3149 | ||
3150 | POSTING_READ(reg); | |
e1a44743 AJ |
3151 | udelay(150); |
3152 | ||
8db9d77b | 3153 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3154 | reg = FDI_TX_CTL(pipe); |
3155 | temp = I915_READ(reg); | |
627eb5a3 DV |
3156 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3157 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
3158 | temp &= ~FDI_LINK_TRAIN_NONE; |
3159 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3160 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3161 | /* SNB-B */ | |
3162 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3163 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3164 | |
d74cf324 DV |
3165 | I915_WRITE(FDI_RX_MISC(pipe), |
3166 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3167 | ||
5eddb70b CW |
3168 | reg = FDI_RX_CTL(pipe); |
3169 | temp = I915_READ(reg); | |
8db9d77b ZW |
3170 | if (HAS_PCH_CPT(dev)) { |
3171 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3172 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3173 | } else { | |
3174 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3175 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3176 | } | |
5eddb70b CW |
3177 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3178 | ||
3179 | POSTING_READ(reg); | |
8db9d77b ZW |
3180 | udelay(150); |
3181 | ||
0206e353 | 3182 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3183 | reg = FDI_TX_CTL(pipe); |
3184 | temp = I915_READ(reg); | |
8db9d77b ZW |
3185 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3186 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3187 | I915_WRITE(reg, temp); |
3188 | ||
3189 | POSTING_READ(reg); | |
8db9d77b ZW |
3190 | udelay(500); |
3191 | ||
fa37d39e SP |
3192 | for (retry = 0; retry < 5; retry++) { |
3193 | reg = FDI_RX_IIR(pipe); | |
3194 | temp = I915_READ(reg); | |
3195 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3196 | if (temp & FDI_RX_BIT_LOCK) { | |
3197 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3198 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3199 | break; | |
3200 | } | |
3201 | udelay(50); | |
8db9d77b | 3202 | } |
fa37d39e SP |
3203 | if (retry < 5) |
3204 | break; | |
8db9d77b ZW |
3205 | } |
3206 | if (i == 4) | |
5eddb70b | 3207 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3208 | |
3209 | /* Train 2 */ | |
5eddb70b CW |
3210 | reg = FDI_TX_CTL(pipe); |
3211 | temp = I915_READ(reg); | |
8db9d77b ZW |
3212 | temp &= ~FDI_LINK_TRAIN_NONE; |
3213 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3214 | if (IS_GEN6(dev)) { | |
3215 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3216 | /* SNB-B */ | |
3217 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3218 | } | |
5eddb70b | 3219 | I915_WRITE(reg, temp); |
8db9d77b | 3220 | |
5eddb70b CW |
3221 | reg = FDI_RX_CTL(pipe); |
3222 | temp = I915_READ(reg); | |
8db9d77b ZW |
3223 | if (HAS_PCH_CPT(dev)) { |
3224 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3225 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3226 | } else { | |
3227 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3228 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3229 | } | |
5eddb70b CW |
3230 | I915_WRITE(reg, temp); |
3231 | ||
3232 | POSTING_READ(reg); | |
8db9d77b ZW |
3233 | udelay(150); |
3234 | ||
0206e353 | 3235 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3236 | reg = FDI_TX_CTL(pipe); |
3237 | temp = I915_READ(reg); | |
8db9d77b ZW |
3238 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3239 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3240 | I915_WRITE(reg, temp); |
3241 | ||
3242 | POSTING_READ(reg); | |
8db9d77b ZW |
3243 | udelay(500); |
3244 | ||
fa37d39e SP |
3245 | for (retry = 0; retry < 5; retry++) { |
3246 | reg = FDI_RX_IIR(pipe); | |
3247 | temp = I915_READ(reg); | |
3248 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3249 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3250 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3251 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3252 | break; | |
3253 | } | |
3254 | udelay(50); | |
8db9d77b | 3255 | } |
fa37d39e SP |
3256 | if (retry < 5) |
3257 | break; | |
8db9d77b ZW |
3258 | } |
3259 | if (i == 4) | |
5eddb70b | 3260 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3261 | |
3262 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3263 | } | |
3264 | ||
357555c0 JB |
3265 | /* Manual link training for Ivy Bridge A0 parts */ |
3266 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3267 | { | |
3268 | struct drm_device *dev = crtc->dev; | |
3269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3270 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3271 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3272 | u32 reg, temp, i, j; |
357555c0 JB |
3273 | |
3274 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3275 | for train result */ | |
3276 | reg = FDI_RX_IMR(pipe); | |
3277 | temp = I915_READ(reg); | |
3278 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3279 | temp &= ~FDI_RX_BIT_LOCK; | |
3280 | I915_WRITE(reg, temp); | |
3281 | ||
3282 | POSTING_READ(reg); | |
3283 | udelay(150); | |
3284 | ||
01a415fd DV |
3285 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3286 | I915_READ(FDI_RX_IIR(pipe))); | |
3287 | ||
139ccd3f JB |
3288 | /* Try each vswing and preemphasis setting twice before moving on */ |
3289 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3290 | /* disable first in case we need to retry */ | |
3291 | reg = FDI_TX_CTL(pipe); | |
3292 | temp = I915_READ(reg); | |
3293 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3294 | temp &= ~FDI_TX_ENABLE; | |
3295 | I915_WRITE(reg, temp); | |
357555c0 | 3296 | |
139ccd3f JB |
3297 | reg = FDI_RX_CTL(pipe); |
3298 | temp = I915_READ(reg); | |
3299 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3300 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3301 | temp &= ~FDI_RX_ENABLE; | |
3302 | I915_WRITE(reg, temp); | |
357555c0 | 3303 | |
139ccd3f | 3304 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3305 | reg = FDI_TX_CTL(pipe); |
3306 | temp = I915_READ(reg); | |
139ccd3f JB |
3307 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3308 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3309 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3310 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3311 | temp |= snb_b_fdi_train_param[j/2]; |
3312 | temp |= FDI_COMPOSITE_SYNC; | |
3313 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3314 | |
139ccd3f JB |
3315 | I915_WRITE(FDI_RX_MISC(pipe), |
3316 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3317 | |
139ccd3f | 3318 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3319 | temp = I915_READ(reg); |
139ccd3f JB |
3320 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3321 | temp |= FDI_COMPOSITE_SYNC; | |
3322 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3323 | |
139ccd3f JB |
3324 | POSTING_READ(reg); |
3325 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3326 | |
139ccd3f JB |
3327 | for (i = 0; i < 4; i++) { |
3328 | reg = FDI_RX_IIR(pipe); | |
3329 | temp = I915_READ(reg); | |
3330 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3331 | |
139ccd3f JB |
3332 | if (temp & FDI_RX_BIT_LOCK || |
3333 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3334 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3335 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3336 | i); | |
3337 | break; | |
3338 | } | |
3339 | udelay(1); /* should be 0.5us */ | |
3340 | } | |
3341 | if (i == 4) { | |
3342 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3343 | continue; | |
3344 | } | |
357555c0 | 3345 | |
139ccd3f | 3346 | /* Train 2 */ |
357555c0 JB |
3347 | reg = FDI_TX_CTL(pipe); |
3348 | temp = I915_READ(reg); | |
139ccd3f JB |
3349 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3350 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3351 | I915_WRITE(reg, temp); | |
3352 | ||
3353 | reg = FDI_RX_CTL(pipe); | |
3354 | temp = I915_READ(reg); | |
3355 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3356 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3357 | I915_WRITE(reg, temp); |
3358 | ||
3359 | POSTING_READ(reg); | |
139ccd3f | 3360 | udelay(2); /* should be 1.5us */ |
357555c0 | 3361 | |
139ccd3f JB |
3362 | for (i = 0; i < 4; i++) { |
3363 | reg = FDI_RX_IIR(pipe); | |
3364 | temp = I915_READ(reg); | |
3365 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3366 | |
139ccd3f JB |
3367 | if (temp & FDI_RX_SYMBOL_LOCK || |
3368 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3369 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3370 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3371 | i); | |
3372 | goto train_done; | |
3373 | } | |
3374 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3375 | } |
139ccd3f JB |
3376 | if (i == 4) |
3377 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3378 | } |
357555c0 | 3379 | |
139ccd3f | 3380 | train_done: |
357555c0 JB |
3381 | DRM_DEBUG_KMS("FDI train done.\n"); |
3382 | } | |
3383 | ||
88cefb6c | 3384 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3385 | { |
88cefb6c | 3386 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3387 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3388 | int pipe = intel_crtc->pipe; |
5eddb70b | 3389 | u32 reg, temp; |
79e53945 | 3390 | |
c64e311e | 3391 | |
c98e9dcf | 3392 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3393 | reg = FDI_RX_CTL(pipe); |
3394 | temp = I915_READ(reg); | |
627eb5a3 DV |
3395 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3396 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3397 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3398 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3399 | ||
3400 | POSTING_READ(reg); | |
c98e9dcf JB |
3401 | udelay(200); |
3402 | ||
3403 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3404 | temp = I915_READ(reg); |
3405 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3406 | ||
3407 | POSTING_READ(reg); | |
c98e9dcf JB |
3408 | udelay(200); |
3409 | ||
20749730 PZ |
3410 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3411 | reg = FDI_TX_CTL(pipe); | |
3412 | temp = I915_READ(reg); | |
3413 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3414 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3415 | |
20749730 PZ |
3416 | POSTING_READ(reg); |
3417 | udelay(100); | |
6be4a607 | 3418 | } |
0e23b99d JB |
3419 | } |
3420 | ||
88cefb6c DV |
3421 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3422 | { | |
3423 | struct drm_device *dev = intel_crtc->base.dev; | |
3424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3425 | int pipe = intel_crtc->pipe; | |
3426 | u32 reg, temp; | |
3427 | ||
3428 | /* Switch from PCDclk to Rawclk */ | |
3429 | reg = FDI_RX_CTL(pipe); | |
3430 | temp = I915_READ(reg); | |
3431 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3432 | ||
3433 | /* Disable CPU FDI TX PLL */ | |
3434 | reg = FDI_TX_CTL(pipe); | |
3435 | temp = I915_READ(reg); | |
3436 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3437 | ||
3438 | POSTING_READ(reg); | |
3439 | udelay(100); | |
3440 | ||
3441 | reg = FDI_RX_CTL(pipe); | |
3442 | temp = I915_READ(reg); | |
3443 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3444 | ||
3445 | /* Wait for the clocks to turn off. */ | |
3446 | POSTING_READ(reg); | |
3447 | udelay(100); | |
3448 | } | |
3449 | ||
0fc932b8 JB |
3450 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3451 | { | |
3452 | struct drm_device *dev = crtc->dev; | |
3453 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3454 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3455 | int pipe = intel_crtc->pipe; | |
3456 | u32 reg, temp; | |
3457 | ||
3458 | /* disable CPU FDI tx and PCH FDI rx */ | |
3459 | reg = FDI_TX_CTL(pipe); | |
3460 | temp = I915_READ(reg); | |
3461 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3462 | POSTING_READ(reg); | |
3463 | ||
3464 | reg = FDI_RX_CTL(pipe); | |
3465 | temp = I915_READ(reg); | |
3466 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3467 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3468 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3469 | ||
3470 | POSTING_READ(reg); | |
3471 | udelay(100); | |
3472 | ||
3473 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3474 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3475 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3476 | |
3477 | /* still set train pattern 1 */ | |
3478 | reg = FDI_TX_CTL(pipe); | |
3479 | temp = I915_READ(reg); | |
3480 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3481 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3482 | I915_WRITE(reg, temp); | |
3483 | ||
3484 | reg = FDI_RX_CTL(pipe); | |
3485 | temp = I915_READ(reg); | |
3486 | if (HAS_PCH_CPT(dev)) { | |
3487 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3488 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3489 | } else { | |
3490 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3491 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3492 | } | |
3493 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3494 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3495 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3496 | I915_WRITE(reg, temp); |
3497 | ||
3498 | POSTING_READ(reg); | |
3499 | udelay(100); | |
3500 | } | |
3501 | ||
5dce5b93 CW |
3502 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3503 | { | |
3504 | struct intel_crtc *crtc; | |
3505 | ||
3506 | /* Note that we don't need to be called with mode_config.lock here | |
3507 | * as our list of CRTC objects is static for the lifetime of the | |
3508 | * device and so cannot disappear as we iterate. Similarly, we can | |
3509 | * happily treat the predicates as racy, atomic checks as userspace | |
3510 | * cannot claim and pin a new fb without at least acquring the | |
3511 | * struct_mutex and so serialising with us. | |
3512 | */ | |
d3fcc808 | 3513 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3514 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3515 | continue; | |
3516 | ||
3517 | if (crtc->unpin_work) | |
3518 | intel_wait_for_vblank(dev, crtc->pipe); | |
3519 | ||
3520 | return true; | |
3521 | } | |
3522 | ||
3523 | return false; | |
3524 | } | |
3525 | ||
d6bbafa1 CW |
3526 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3527 | { | |
3528 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3529 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3530 | ||
3531 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3532 | smp_rmb(); | |
3533 | intel_crtc->unpin_work = NULL; | |
3534 | ||
3535 | if (work->event) | |
3536 | drm_send_vblank_event(intel_crtc->base.dev, | |
3537 | intel_crtc->pipe, | |
3538 | work->event); | |
3539 | ||
3540 | drm_crtc_vblank_put(&intel_crtc->base); | |
3541 | ||
3542 | wake_up_all(&dev_priv->pending_flip_queue); | |
3543 | queue_work(dev_priv->wq, &work->work); | |
3544 | ||
3545 | trace_i915_flip_complete(intel_crtc->plane, | |
3546 | work->pending_flip_obj); | |
3547 | } | |
3548 | ||
46a55d30 | 3549 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3550 | { |
0f91128d | 3551 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3552 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3553 | |
2c10d571 | 3554 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3555 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3556 | !intel_crtc_has_pending_flip(crtc), | |
3557 | 60*HZ) == 0)) { | |
3558 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3559 | |
5e2d7afc | 3560 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3561 | if (intel_crtc->unpin_work) { |
3562 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3563 | page_flip_completed(intel_crtc); | |
3564 | } | |
5e2d7afc | 3565 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3566 | } |
5bb61643 | 3567 | |
975d568a CW |
3568 | if (crtc->primary->fb) { |
3569 | mutex_lock(&dev->struct_mutex); | |
3570 | intel_finish_fb(crtc->primary->fb); | |
3571 | mutex_unlock(&dev->struct_mutex); | |
3572 | } | |
e6c3a2a6 CW |
3573 | } |
3574 | ||
e615efe4 ED |
3575 | /* Program iCLKIP clock to the desired frequency */ |
3576 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3577 | { | |
3578 | struct drm_device *dev = crtc->dev; | |
3579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3580 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3581 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3582 | u32 temp; | |
3583 | ||
09153000 DV |
3584 | mutex_lock(&dev_priv->dpio_lock); |
3585 | ||
e615efe4 ED |
3586 | /* It is necessary to ungate the pixclk gate prior to programming |
3587 | * the divisors, and gate it back when it is done. | |
3588 | */ | |
3589 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3590 | ||
3591 | /* Disable SSCCTL */ | |
3592 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3593 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3594 | SBI_SSCCTL_DISABLE, | |
3595 | SBI_ICLK); | |
e615efe4 ED |
3596 | |
3597 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3598 | if (clock == 20000) { |
e615efe4 ED |
3599 | auxdiv = 1; |
3600 | divsel = 0x41; | |
3601 | phaseinc = 0x20; | |
3602 | } else { | |
3603 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3604 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3605 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3606 | * convert the virtual clock precision to KHz here for higher |
3607 | * precision. | |
3608 | */ | |
3609 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3610 | u32 iclk_pi_range = 64; | |
3611 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3612 | ||
12d7ceed | 3613 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3614 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3615 | pi_value = desired_divisor % iclk_pi_range; | |
3616 | ||
3617 | auxdiv = 0; | |
3618 | divsel = msb_divisor_value - 2; | |
3619 | phaseinc = pi_value; | |
3620 | } | |
3621 | ||
3622 | /* This should not happen with any sane values */ | |
3623 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3624 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3625 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3626 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3627 | ||
3628 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3629 | clock, |
e615efe4 ED |
3630 | auxdiv, |
3631 | divsel, | |
3632 | phasedir, | |
3633 | phaseinc); | |
3634 | ||
3635 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3636 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3637 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3638 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3639 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3640 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3641 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3642 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3643 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3644 | |
3645 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3646 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3647 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3648 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3649 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3650 | |
3651 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3652 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3653 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3654 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3655 | |
3656 | /* Wait for initialization time */ | |
3657 | udelay(24); | |
3658 | ||
3659 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3660 | |
3661 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3662 | } |
3663 | ||
275f01b2 DV |
3664 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3665 | enum pipe pch_transcoder) | |
3666 | { | |
3667 | struct drm_device *dev = crtc->base.dev; | |
3668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3669 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3670 | ||
3671 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3672 | I915_READ(HTOTAL(cpu_transcoder))); | |
3673 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3674 | I915_READ(HBLANK(cpu_transcoder))); | |
3675 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3676 | I915_READ(HSYNC(cpu_transcoder))); | |
3677 | ||
3678 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3679 | I915_READ(VTOTAL(cpu_transcoder))); | |
3680 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3681 | I915_READ(VBLANK(cpu_transcoder))); | |
3682 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3683 | I915_READ(VSYNC(cpu_transcoder))); | |
3684 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3685 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3686 | } | |
3687 | ||
1fbc0d78 DV |
3688 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3689 | { | |
3690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3691 | uint32_t temp; | |
3692 | ||
3693 | temp = I915_READ(SOUTH_CHICKEN1); | |
3694 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3695 | return; | |
3696 | ||
3697 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3698 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3699 | ||
3700 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3701 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3702 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3703 | POSTING_READ(SOUTH_CHICKEN1); | |
3704 | } | |
3705 | ||
3706 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3707 | { | |
3708 | struct drm_device *dev = intel_crtc->base.dev; | |
3709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3710 | ||
3711 | switch (intel_crtc->pipe) { | |
3712 | case PIPE_A: | |
3713 | break; | |
3714 | case PIPE_B: | |
3715 | if (intel_crtc->config.fdi_lanes > 2) | |
3716 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3717 | else | |
3718 | cpt_enable_fdi_bc_bifurcation(dev); | |
3719 | ||
3720 | break; | |
3721 | case PIPE_C: | |
3722 | cpt_enable_fdi_bc_bifurcation(dev); | |
3723 | ||
3724 | break; | |
3725 | default: | |
3726 | BUG(); | |
3727 | } | |
3728 | } | |
3729 | ||
f67a559d JB |
3730 | /* |
3731 | * Enable PCH resources required for PCH ports: | |
3732 | * - PCH PLLs | |
3733 | * - FDI training & RX/TX | |
3734 | * - update transcoder timings | |
3735 | * - DP transcoding bits | |
3736 | * - transcoder | |
3737 | */ | |
3738 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3739 | { |
3740 | struct drm_device *dev = crtc->dev; | |
3741 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3743 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3744 | u32 reg, temp; |
2c07245f | 3745 | |
ab9412ba | 3746 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3747 | |
1fbc0d78 DV |
3748 | if (IS_IVYBRIDGE(dev)) |
3749 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3750 | ||
cd986abb DV |
3751 | /* Write the TU size bits before fdi link training, so that error |
3752 | * detection works. */ | |
3753 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3754 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3755 | ||
c98e9dcf | 3756 | /* For PCH output, training FDI link */ |
674cf967 | 3757 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3758 | |
3ad8a208 DV |
3759 | /* We need to program the right clock selection before writing the pixel |
3760 | * mutliplier into the DPLL. */ | |
303b81e0 | 3761 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3762 | u32 sel; |
4b645f14 | 3763 | |
c98e9dcf | 3764 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3765 | temp |= TRANS_DPLL_ENABLE(pipe); |
3766 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3767 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3768 | temp |= sel; |
3769 | else | |
3770 | temp &= ~sel; | |
c98e9dcf | 3771 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3772 | } |
5eddb70b | 3773 | |
3ad8a208 DV |
3774 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3775 | * transcoder, and we actually should do this to not upset any PCH | |
3776 | * transcoder that already use the clock when we share it. | |
3777 | * | |
3778 | * Note that enable_shared_dpll tries to do the right thing, but | |
3779 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3780 | * the right LVDS enable sequence. */ | |
85b3894f | 3781 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3782 | |
d9b6cb56 JB |
3783 | /* set transcoder timing, panel must allow it */ |
3784 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3785 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3786 | |
303b81e0 | 3787 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3788 | |
c98e9dcf | 3789 | /* For PCH DP, enable TRANS_DP_CTL */ |
0a88818d | 3790 | if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) { |
dfd07d72 | 3791 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3792 | reg = TRANS_DP_CTL(pipe); |
3793 | temp = I915_READ(reg); | |
3794 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3795 | TRANS_DP_SYNC_MASK | |
3796 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3797 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3798 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3799 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3800 | |
3801 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3802 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3803 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3804 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3805 | |
3806 | switch (intel_trans_dp_port_sel(crtc)) { | |
3807 | case PCH_DP_B: | |
5eddb70b | 3808 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3809 | break; |
3810 | case PCH_DP_C: | |
5eddb70b | 3811 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3812 | break; |
3813 | case PCH_DP_D: | |
5eddb70b | 3814 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3815 | break; |
3816 | default: | |
e95d41e1 | 3817 | BUG(); |
32f9d658 | 3818 | } |
2c07245f | 3819 | |
5eddb70b | 3820 | I915_WRITE(reg, temp); |
6be4a607 | 3821 | } |
b52eb4dc | 3822 | |
b8a4f404 | 3823 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3824 | } |
3825 | ||
1507e5bd PZ |
3826 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3827 | { | |
3828 | struct drm_device *dev = crtc->dev; | |
3829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3830 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3831 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3832 | |
ab9412ba | 3833 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3834 | |
8c52b5e8 | 3835 | lpt_program_iclkip(crtc); |
1507e5bd | 3836 | |
0540e488 | 3837 | /* Set transcoder timing. */ |
275f01b2 | 3838 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3839 | |
937bb610 | 3840 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3841 | } |
3842 | ||
716c2e55 | 3843 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3844 | { |
e2b78267 | 3845 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3846 | |
3847 | if (pll == NULL) | |
3848 | return; | |
3849 | ||
3e369b76 | 3850 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 3851 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
3852 | return; |
3853 | } | |
3854 | ||
3e369b76 ACO |
3855 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
3856 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
3857 | WARN_ON(pll->on); |
3858 | WARN_ON(pll->active); | |
3859 | } | |
3860 | ||
a43f6e0f | 3861 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3862 | } |
3863 | ||
716c2e55 | 3864 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3865 | { |
e2b78267 | 3866 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 3867 | struct intel_shared_dpll *pll; |
e2b78267 | 3868 | enum intel_dpll_id i; |
ee7b9f93 | 3869 | |
98b6bd99 DV |
3870 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3871 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3872 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3873 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3874 | |
46edb027 DV |
3875 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3876 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3877 | |
8bd31e67 | 3878 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 3879 | |
98b6bd99 DV |
3880 | goto found; |
3881 | } | |
3882 | ||
e72f9fbf DV |
3883 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3884 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3885 | |
3886 | /* Only want to check enabled timings first */ | |
8bd31e67 | 3887 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
3888 | continue; |
3889 | ||
8bd31e67 ACO |
3890 | if (memcmp(&crtc->new_config->dpll_hw_state, |
3891 | &pll->new_config->hw_state, | |
3892 | sizeof(pll->new_config->hw_state)) == 0) { | |
3893 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 3894 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
3895 | pll->new_config->crtc_mask, |
3896 | pll->active); | |
ee7b9f93 JB |
3897 | goto found; |
3898 | } | |
3899 | } | |
3900 | ||
3901 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3902 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3903 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 3904 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
3905 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3906 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3907 | goto found; |
3908 | } | |
3909 | } | |
3910 | ||
3911 | return NULL; | |
3912 | ||
3913 | found: | |
8bd31e67 ACO |
3914 | if (pll->new_config->crtc_mask == 0) |
3915 | pll->new_config->hw_state = crtc->new_config->dpll_hw_state; | |
f2a69f44 | 3916 | |
8bd31e67 | 3917 | crtc->new_config->shared_dpll = i; |
46edb027 DV |
3918 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3919 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3920 | |
8bd31e67 | 3921 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 3922 | |
ee7b9f93 JB |
3923 | return pll; |
3924 | } | |
3925 | ||
8bd31e67 ACO |
3926 | /** |
3927 | * intel_shared_dpll_start_config - start a new PLL staged config | |
3928 | * @dev_priv: DRM device | |
3929 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
3930 | * | |
3931 | * Starts a new PLL staged config, copying the current config but | |
3932 | * releasing the references of pipes specified in clear_pipes. | |
3933 | */ | |
3934 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
3935 | unsigned clear_pipes) | |
3936 | { | |
3937 | struct intel_shared_dpll *pll; | |
3938 | enum intel_dpll_id i; | |
3939 | ||
3940 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3941 | pll = &dev_priv->shared_dplls[i]; | |
3942 | ||
3943 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
3944 | GFP_KERNEL); | |
3945 | if (!pll->new_config) | |
3946 | goto cleanup; | |
3947 | ||
3948 | pll->new_config->crtc_mask &= ~clear_pipes; | |
3949 | } | |
3950 | ||
3951 | return 0; | |
3952 | ||
3953 | cleanup: | |
3954 | while (--i >= 0) { | |
3955 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 3956 | kfree(pll->new_config); |
8bd31e67 ACO |
3957 | pll->new_config = NULL; |
3958 | } | |
3959 | ||
3960 | return -ENOMEM; | |
3961 | } | |
3962 | ||
3963 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
3964 | { | |
3965 | struct intel_shared_dpll *pll; | |
3966 | enum intel_dpll_id i; | |
3967 | ||
3968 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3969 | pll = &dev_priv->shared_dplls[i]; | |
3970 | ||
3971 | WARN_ON(pll->new_config == &pll->config); | |
3972 | ||
3973 | pll->config = *pll->new_config; | |
3974 | kfree(pll->new_config); | |
3975 | pll->new_config = NULL; | |
3976 | } | |
3977 | } | |
3978 | ||
3979 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
3980 | { | |
3981 | struct intel_shared_dpll *pll; | |
3982 | enum intel_dpll_id i; | |
3983 | ||
3984 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3985 | pll = &dev_priv->shared_dplls[i]; | |
3986 | ||
3987 | WARN_ON(pll->new_config == &pll->config); | |
3988 | ||
3989 | kfree(pll->new_config); | |
3990 | pll->new_config = NULL; | |
3991 | } | |
3992 | } | |
3993 | ||
a1520318 | 3994 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3995 | { |
3996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3997 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3998 | u32 temp; |
3999 | ||
4000 | temp = I915_READ(dslreg); | |
4001 | udelay(500); | |
4002 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4003 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4004 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4005 | } |
4006 | } | |
4007 | ||
bd2e244f JB |
4008 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
4009 | { | |
4010 | struct drm_device *dev = crtc->base.dev; | |
4011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4012 | int pipe = crtc->pipe; | |
4013 | ||
4014 | if (crtc->config.pch_pfit.enabled) { | |
4015 | I915_WRITE(PS_CTL(pipe), PS_ENABLE); | |
4016 | I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
4017 | I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
4018 | } | |
4019 | } | |
4020 | ||
b074cec8 JB |
4021 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4022 | { | |
4023 | struct drm_device *dev = crtc->base.dev; | |
4024 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4025 | int pipe = crtc->pipe; | |
4026 | ||
fd4daa9c | 4027 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
4028 | /* Force use of hard-coded filter coefficients |
4029 | * as some pre-programmed values are broken, | |
4030 | * e.g. x201. | |
4031 | */ | |
4032 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4033 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4034 | PF_PIPE_SEL_IVB(pipe)); | |
4035 | else | |
4036 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
4037 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
4038 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
4039 | } |
4040 | } | |
4041 | ||
4a3b8769 | 4042 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4043 | { |
4044 | struct drm_device *dev = crtc->dev; | |
4045 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4046 | struct drm_plane *plane; |
bb53d4ae VS |
4047 | struct intel_plane *intel_plane; |
4048 | ||
af2b653b MR |
4049 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4050 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4051 | if (intel_plane->pipe == pipe) |
4052 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4053 | } |
bb53d4ae VS |
4054 | } |
4055 | ||
4a3b8769 | 4056 | static void intel_disable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4057 | { |
4058 | struct drm_device *dev = crtc->dev; | |
4059 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4060 | struct drm_plane *plane; |
bb53d4ae VS |
4061 | struct intel_plane *intel_plane; |
4062 | ||
af2b653b MR |
4063 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4064 | intel_plane = to_intel_plane(plane); | |
bb53d4ae | 4065 | if (intel_plane->pipe == pipe) |
cf4c7c12 | 4066 | plane->funcs->disable_plane(plane); |
af2b653b | 4067 | } |
bb53d4ae VS |
4068 | } |
4069 | ||
20bc8673 | 4070 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4071 | { |
cea165c3 VS |
4072 | struct drm_device *dev = crtc->base.dev; |
4073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
4074 | |
4075 | if (!crtc->config.ips_enabled) | |
4076 | return; | |
4077 | ||
cea165c3 VS |
4078 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4079 | intel_wait_for_vblank(dev, crtc->pipe); | |
4080 | ||
d77e4531 | 4081 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4082 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4083 | mutex_lock(&dev_priv->rps.hw_lock); |
4084 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4085 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4086 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4087 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4088 | * mailbox." Moreover, the mailbox may return a bogus state, |
4089 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4090 | */ |
4091 | } else { | |
4092 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4093 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4094 | * is essentially intel_wait_for_vblank. If we don't have this | |
4095 | * and don't wait for vblanks until the end of crtc_enable, then | |
4096 | * the HW state readout code will complain that the expected | |
4097 | * IPS_CTL value is not the one we read. */ | |
4098 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4099 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4100 | } | |
d77e4531 PZ |
4101 | } |
4102 | ||
20bc8673 | 4103 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4104 | { |
4105 | struct drm_device *dev = crtc->base.dev; | |
4106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4107 | ||
4108 | if (!crtc->config.ips_enabled) | |
4109 | return; | |
4110 | ||
4111 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4112 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4113 | mutex_lock(&dev_priv->rps.hw_lock); |
4114 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4115 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4116 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4117 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4118 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4119 | } else { |
2a114cc1 | 4120 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4121 | POSTING_READ(IPS_CTL); |
4122 | } | |
d77e4531 PZ |
4123 | |
4124 | /* We need to wait for a vblank before we can disable the plane. */ | |
4125 | intel_wait_for_vblank(dev, crtc->pipe); | |
4126 | } | |
4127 | ||
4128 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4129 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4130 | { | |
4131 | struct drm_device *dev = crtc->dev; | |
4132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4134 | enum pipe pipe = intel_crtc->pipe; | |
4135 | int palreg = PALETTE(pipe); | |
4136 | int i; | |
4137 | bool reenable_ips = false; | |
4138 | ||
4139 | /* The clocks have to be on to load the palette. */ | |
4140 | if (!crtc->enabled || !intel_crtc->active) | |
4141 | return; | |
4142 | ||
4143 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
409ee761 | 4144 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4145 | assert_dsi_pll_enabled(dev_priv); |
4146 | else | |
4147 | assert_pll_enabled(dev_priv, pipe); | |
4148 | } | |
4149 | ||
4150 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4151 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4152 | palreg = LGC_PALETTE(pipe); |
4153 | ||
4154 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4155 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4156 | */ | |
41e6fc4c | 4157 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
4158 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4159 | GAMMA_MODE_MODE_SPLIT)) { | |
4160 | hsw_disable_ips(intel_crtc); | |
4161 | reenable_ips = true; | |
4162 | } | |
4163 | ||
4164 | for (i = 0; i < 256; i++) { | |
4165 | I915_WRITE(palreg + 4 * i, | |
4166 | (intel_crtc->lut_r[i] << 16) | | |
4167 | (intel_crtc->lut_g[i] << 8) | | |
4168 | intel_crtc->lut_b[i]); | |
4169 | } | |
4170 | ||
4171 | if (reenable_ips) | |
4172 | hsw_enable_ips(intel_crtc); | |
4173 | } | |
4174 | ||
d3eedb1a VS |
4175 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4176 | { | |
4177 | if (!enable && intel_crtc->overlay) { | |
4178 | struct drm_device *dev = intel_crtc->base.dev; | |
4179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4180 | ||
4181 | mutex_lock(&dev->struct_mutex); | |
4182 | dev_priv->mm.interruptible = false; | |
4183 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4184 | dev_priv->mm.interruptible = true; | |
4185 | mutex_unlock(&dev->struct_mutex); | |
4186 | } | |
4187 | ||
4188 | /* Let userspace switch the overlay on again. In most cases userspace | |
4189 | * has to recompute where to put it anyway. | |
4190 | */ | |
4191 | } | |
4192 | ||
d3eedb1a | 4193 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4194 | { |
4195 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4197 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4198 | |
fdd508a6 | 4199 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4a3b8769 | 4200 | intel_enable_sprite_planes(crtc); |
a5c4d7bc | 4201 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 4202 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4203 | |
4204 | hsw_enable_ips(intel_crtc); | |
4205 | ||
4206 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4207 | intel_fbc_update(dev); |
a5c4d7bc | 4208 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4209 | |
4210 | /* | |
4211 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4212 | * to compute the mask of flip planes precisely. For the time being | |
4213 | * consider this a flip from a NULL plane. | |
4214 | */ | |
4215 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4216 | } |
4217 | ||
d3eedb1a | 4218 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4219 | { |
4220 | struct drm_device *dev = crtc->dev; | |
4221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4222 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4223 | int pipe = intel_crtc->pipe; | |
4224 | int plane = intel_crtc->plane; | |
4225 | ||
4226 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc VS |
4227 | |
4228 | if (dev_priv->fbc.plane == plane) | |
7ff0ebcc | 4229 | intel_fbc_disable(dev); |
a5c4d7bc VS |
4230 | |
4231 | hsw_disable_ips(intel_crtc); | |
4232 | ||
d3eedb1a | 4233 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc | 4234 | intel_crtc_update_cursor(crtc, false); |
4a3b8769 | 4235 | intel_disable_sprite_planes(crtc); |
fdd508a6 | 4236 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4237 | |
f99d7069 DV |
4238 | /* |
4239 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4240 | * to compute the mask of flip planes precisely. For the time being | |
4241 | * consider this a flip to a NULL plane. | |
4242 | */ | |
4243 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4244 | } |
4245 | ||
f67a559d JB |
4246 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4247 | { | |
4248 | struct drm_device *dev = crtc->dev; | |
4249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4250 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4251 | struct intel_encoder *encoder; |
f67a559d | 4252 | int pipe = intel_crtc->pipe; |
f67a559d | 4253 | |
08a48469 DV |
4254 | WARN_ON(!crtc->enabled); |
4255 | ||
f67a559d JB |
4256 | if (intel_crtc->active) |
4257 | return; | |
4258 | ||
b14b1055 DV |
4259 | if (intel_crtc->config.has_pch_encoder) |
4260 | intel_prepare_shared_dpll(intel_crtc); | |
4261 | ||
29407aab DV |
4262 | if (intel_crtc->config.has_dp_encoder) |
4263 | intel_dp_set_m_n(intel_crtc); | |
4264 | ||
4265 | intel_set_pipe_timings(intel_crtc); | |
4266 | ||
4267 | if (intel_crtc->config.has_pch_encoder) { | |
4268 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4269 | &intel_crtc->config.fdi_m_n, NULL); |
29407aab DV |
4270 | } |
4271 | ||
4272 | ironlake_set_pipeconf(crtc); | |
4273 | ||
f67a559d | 4274 | intel_crtc->active = true; |
8664281b | 4275 | |
a72e4c9f DV |
4276 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4277 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4278 | |
f6736a1a | 4279 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4280 | if (encoder->pre_enable) |
4281 | encoder->pre_enable(encoder); | |
f67a559d | 4282 | |
5bfe2ac0 | 4283 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
4284 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4285 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4286 | * enabling. */ | |
88cefb6c | 4287 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4288 | } else { |
4289 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4290 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4291 | } | |
f67a559d | 4292 | |
b074cec8 | 4293 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4294 | |
9c54c0dd JB |
4295 | /* |
4296 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4297 | * clocks enabled | |
4298 | */ | |
4299 | intel_crtc_load_lut(crtc); | |
4300 | ||
f37fcc2a | 4301 | intel_update_watermarks(crtc); |
e1fdc473 | 4302 | intel_enable_pipe(intel_crtc); |
f67a559d | 4303 | |
5bfe2ac0 | 4304 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 4305 | ironlake_pch_enable(crtc); |
c98e9dcf | 4306 | |
f9b61ff6 DV |
4307 | assert_vblank_disabled(crtc); |
4308 | drm_crtc_vblank_on(crtc); | |
4309 | ||
fa5c73b1 DV |
4310 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4311 | encoder->enable(encoder); | |
61b77ddd DV |
4312 | |
4313 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4314 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4315 | |
d3eedb1a | 4316 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4317 | } |
4318 | ||
42db64ef PZ |
4319 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4320 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4321 | { | |
f5adf94e | 4322 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4323 | } |
4324 | ||
e4916946 PZ |
4325 | /* |
4326 | * This implements the workaround described in the "notes" section of the mode | |
4327 | * set sequence documentation. When going from no pipes or single pipe to | |
4328 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4329 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4330 | */ | |
4331 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4332 | { | |
4333 | struct drm_device *dev = crtc->base.dev; | |
4334 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4335 | ||
4336 | /* We want to get the other_active_crtc only if there's only 1 other | |
4337 | * active crtc. */ | |
d3fcc808 | 4338 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4339 | if (!crtc_it->active || crtc_it == crtc) |
4340 | continue; | |
4341 | ||
4342 | if (other_active_crtc) | |
4343 | return; | |
4344 | ||
4345 | other_active_crtc = crtc_it; | |
4346 | } | |
4347 | if (!other_active_crtc) | |
4348 | return; | |
4349 | ||
4350 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4351 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4352 | } | |
4353 | ||
4f771f10 PZ |
4354 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4355 | { | |
4356 | struct drm_device *dev = crtc->dev; | |
4357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4358 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4359 | struct intel_encoder *encoder; | |
4360 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
4361 | |
4362 | WARN_ON(!crtc->enabled); | |
4363 | ||
4364 | if (intel_crtc->active) | |
4365 | return; | |
4366 | ||
df8ad70c DV |
4367 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4368 | intel_enable_shared_dpll(intel_crtc); | |
4369 | ||
229fca97 DV |
4370 | if (intel_crtc->config.has_dp_encoder) |
4371 | intel_dp_set_m_n(intel_crtc); | |
4372 | ||
4373 | intel_set_pipe_timings(intel_crtc); | |
4374 | ||
ebb69c95 CT |
4375 | if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) { |
4376 | I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder), | |
4377 | intel_crtc->config.pixel_multiplier - 1); | |
4378 | } | |
4379 | ||
229fca97 DV |
4380 | if (intel_crtc->config.has_pch_encoder) { |
4381 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4382 | &intel_crtc->config.fdi_m_n, NULL); |
229fca97 DV |
4383 | } |
4384 | ||
4385 | haswell_set_pipeconf(crtc); | |
4386 | ||
4387 | intel_set_pipe_csc(crtc); | |
4388 | ||
4f771f10 | 4389 | intel_crtc->active = true; |
8664281b | 4390 | |
a72e4c9f | 4391 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4392 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4393 | if (encoder->pre_enable) | |
4394 | encoder->pre_enable(encoder); | |
4395 | ||
4fe9467d | 4396 | if (intel_crtc->config.has_pch_encoder) { |
a72e4c9f DV |
4397 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4398 | true); | |
4fe9467d ID |
4399 | dev_priv->display.fdi_link_train(crtc); |
4400 | } | |
4401 | ||
1f544388 | 4402 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4403 | |
bd2e244f JB |
4404 | if (IS_SKYLAKE(dev)) |
4405 | skylake_pfit_enable(intel_crtc); | |
4406 | else | |
4407 | ironlake_pfit_enable(intel_crtc); | |
4f771f10 PZ |
4408 | |
4409 | /* | |
4410 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4411 | * clocks enabled | |
4412 | */ | |
4413 | intel_crtc_load_lut(crtc); | |
4414 | ||
1f544388 | 4415 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4416 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4417 | |
f37fcc2a | 4418 | intel_update_watermarks(crtc); |
e1fdc473 | 4419 | intel_enable_pipe(intel_crtc); |
42db64ef | 4420 | |
5bfe2ac0 | 4421 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4422 | lpt_pch_enable(crtc); |
4f771f10 | 4423 | |
0e32b39c DA |
4424 | if (intel_crtc->config.dp_encoder_is_mst) |
4425 | intel_ddi_set_vc_payload_alloc(crtc, true); | |
4426 | ||
f9b61ff6 DV |
4427 | assert_vblank_disabled(crtc); |
4428 | drm_crtc_vblank_on(crtc); | |
4429 | ||
8807e55b | 4430 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4431 | encoder->enable(encoder); |
8807e55b JN |
4432 | intel_opregion_notify_encoder(encoder, true); |
4433 | } | |
4f771f10 | 4434 | |
e4916946 PZ |
4435 | /* If we change the relative order between pipe/planes enabling, we need |
4436 | * to change the workaround. */ | |
4437 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4438 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4439 | } |
4440 | ||
bd2e244f JB |
4441 | static void skylake_pfit_disable(struct intel_crtc *crtc) |
4442 | { | |
4443 | struct drm_device *dev = crtc->base.dev; | |
4444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4445 | int pipe = crtc->pipe; | |
4446 | ||
4447 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4448 | * it's in use. The hw state code will make sure we get this right. */ | |
4449 | if (crtc->config.pch_pfit.enabled) { | |
4450 | I915_WRITE(PS_CTL(pipe), 0); | |
4451 | I915_WRITE(PS_WIN_POS(pipe), 0); | |
4452 | I915_WRITE(PS_WIN_SZ(pipe), 0); | |
4453 | } | |
4454 | } | |
4455 | ||
3f8dce3a DV |
4456 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4457 | { | |
4458 | struct drm_device *dev = crtc->base.dev; | |
4459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4460 | int pipe = crtc->pipe; | |
4461 | ||
4462 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4463 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4464 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4465 | I915_WRITE(PF_CTL(pipe), 0); |
4466 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4467 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4468 | } | |
4469 | } | |
4470 | ||
6be4a607 JB |
4471 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4472 | { | |
4473 | struct drm_device *dev = crtc->dev; | |
4474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4475 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4476 | struct intel_encoder *encoder; |
6be4a607 | 4477 | int pipe = intel_crtc->pipe; |
5eddb70b | 4478 | u32 reg, temp; |
b52eb4dc | 4479 | |
f7abfe8b CW |
4480 | if (!intel_crtc->active) |
4481 | return; | |
4482 | ||
d3eedb1a | 4483 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4484 | |
ea9d758d DV |
4485 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4486 | encoder->disable(encoder); | |
4487 | ||
f9b61ff6 DV |
4488 | drm_crtc_vblank_off(crtc); |
4489 | assert_vblank_disabled(crtc); | |
4490 | ||
d925c59a | 4491 | if (intel_crtc->config.has_pch_encoder) |
a72e4c9f | 4492 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 4493 | |
575f7ab7 | 4494 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4495 | |
3f8dce3a | 4496 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4497 | |
bf49ec8c DV |
4498 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4499 | if (encoder->post_disable) | |
4500 | encoder->post_disable(encoder); | |
2c07245f | 4501 | |
d925c59a DV |
4502 | if (intel_crtc->config.has_pch_encoder) { |
4503 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4504 | |
d925c59a | 4505 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4506 | |
d925c59a DV |
4507 | if (HAS_PCH_CPT(dev)) { |
4508 | /* disable TRANS_DP_CTL */ | |
4509 | reg = TRANS_DP_CTL(pipe); | |
4510 | temp = I915_READ(reg); | |
4511 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4512 | TRANS_DP_PORT_SEL_MASK); | |
4513 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4514 | I915_WRITE(reg, temp); | |
4515 | ||
4516 | /* disable DPLL_SEL */ | |
4517 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4518 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4519 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4520 | } |
e3421a18 | 4521 | |
d925c59a | 4522 | /* disable PCH DPLL */ |
e72f9fbf | 4523 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4524 | |
d925c59a DV |
4525 | ironlake_fdi_pll_disable(intel_crtc); |
4526 | } | |
6b383a7f | 4527 | |
f7abfe8b | 4528 | intel_crtc->active = false; |
46ba614c | 4529 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4530 | |
4531 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4532 | intel_fbc_update(dev); |
d1ebd816 | 4533 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4534 | } |
1b3c7a47 | 4535 | |
4f771f10 | 4536 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4537 | { |
4f771f10 PZ |
4538 | struct drm_device *dev = crtc->dev; |
4539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4540 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4541 | struct intel_encoder *encoder; |
3b117c8f | 4542 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4543 | |
4f771f10 PZ |
4544 | if (!intel_crtc->active) |
4545 | return; | |
4546 | ||
d3eedb1a | 4547 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4548 | |
8807e55b JN |
4549 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4550 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4551 | encoder->disable(encoder); |
8807e55b | 4552 | } |
4f771f10 | 4553 | |
f9b61ff6 DV |
4554 | drm_crtc_vblank_off(crtc); |
4555 | assert_vblank_disabled(crtc); | |
4556 | ||
8664281b | 4557 | if (intel_crtc->config.has_pch_encoder) |
a72e4c9f DV |
4558 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4559 | false); | |
575f7ab7 | 4560 | intel_disable_pipe(intel_crtc); |
4f771f10 | 4561 | |
a4bf214f VS |
4562 | if (intel_crtc->config.dp_encoder_is_mst) |
4563 | intel_ddi_set_vc_payload_alloc(crtc, false); | |
4564 | ||
ad80a810 | 4565 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4566 | |
bd2e244f JB |
4567 | if (IS_SKYLAKE(dev)) |
4568 | skylake_pfit_disable(intel_crtc); | |
4569 | else | |
4570 | ironlake_pfit_disable(intel_crtc); | |
4f771f10 | 4571 | |
1f544388 | 4572 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4573 | |
88adfff1 | 4574 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4575 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 4576 | intel_ddi_fdi_disable(crtc); |
83616634 | 4577 | } |
4f771f10 | 4578 | |
97b040aa ID |
4579 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4580 | if (encoder->post_disable) | |
4581 | encoder->post_disable(encoder); | |
4582 | ||
4f771f10 | 4583 | intel_crtc->active = false; |
46ba614c | 4584 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4585 | |
4586 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4587 | intel_fbc_update(dev); |
4f771f10 | 4588 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
4589 | |
4590 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4591 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4592 | } |
4593 | ||
ee7b9f93 JB |
4594 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4595 | { | |
4596 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4597 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4598 | } |
4599 | ||
6441ab5f | 4600 | |
2dd24552 JB |
4601 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4602 | { | |
4603 | struct drm_device *dev = crtc->base.dev; | |
4604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4605 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4606 | ||
328d8e82 | 4607 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4608 | return; |
4609 | ||
2dd24552 | 4610 | /* |
c0b03411 DV |
4611 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4612 | * according to register description and PRM. | |
2dd24552 | 4613 | */ |
c0b03411 DV |
4614 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4615 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4616 | |
b074cec8 JB |
4617 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4618 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4619 | |
4620 | /* Border color in case we don't scale up to the full screen. Black by | |
4621 | * default, change to something else for debugging. */ | |
4622 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4623 | } |
4624 | ||
d05410f9 DA |
4625 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4626 | { | |
4627 | switch (port) { | |
4628 | case PORT_A: | |
4629 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4630 | case PORT_B: | |
4631 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4632 | case PORT_C: | |
4633 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4634 | case PORT_D: | |
4635 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4636 | default: | |
4637 | WARN_ON_ONCE(1); | |
4638 | return POWER_DOMAIN_PORT_OTHER; | |
4639 | } | |
4640 | } | |
4641 | ||
77d22dca ID |
4642 | #define for_each_power_domain(domain, mask) \ |
4643 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4644 | if ((1 << (domain)) & (mask)) | |
4645 | ||
319be8ae ID |
4646 | enum intel_display_power_domain |
4647 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4648 | { | |
4649 | struct drm_device *dev = intel_encoder->base.dev; | |
4650 | struct intel_digital_port *intel_dig_port; | |
4651 | ||
4652 | switch (intel_encoder->type) { | |
4653 | case INTEL_OUTPUT_UNKNOWN: | |
4654 | /* Only DDI platforms should ever use this output type */ | |
4655 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4656 | case INTEL_OUTPUT_DISPLAYPORT: | |
4657 | case INTEL_OUTPUT_HDMI: | |
4658 | case INTEL_OUTPUT_EDP: | |
4659 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4660 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4661 | case INTEL_OUTPUT_DP_MST: |
4662 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4663 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4664 | case INTEL_OUTPUT_ANALOG: |
4665 | return POWER_DOMAIN_PORT_CRT; | |
4666 | case INTEL_OUTPUT_DSI: | |
4667 | return POWER_DOMAIN_PORT_DSI; | |
4668 | default: | |
4669 | return POWER_DOMAIN_PORT_OTHER; | |
4670 | } | |
4671 | } | |
4672 | ||
4673 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4674 | { |
319be8ae ID |
4675 | struct drm_device *dev = crtc->dev; |
4676 | struct intel_encoder *intel_encoder; | |
4677 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4678 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4679 | unsigned long mask; |
4680 | enum transcoder transcoder; | |
4681 | ||
4682 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4683 | ||
4684 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4685 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
fabf6e51 DV |
4686 | if (intel_crtc->config.pch_pfit.enabled || |
4687 | intel_crtc->config.pch_pfit.force_thru) | |
77d22dca ID |
4688 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4689 | ||
319be8ae ID |
4690 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4691 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4692 | ||
77d22dca ID |
4693 | return mask; |
4694 | } | |
4695 | ||
77d22dca ID |
4696 | static void modeset_update_crtc_power_domains(struct drm_device *dev) |
4697 | { | |
4698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4699 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4700 | struct intel_crtc *crtc; | |
4701 | ||
4702 | /* | |
4703 | * First get all needed power domains, then put all unneeded, to avoid | |
4704 | * any unnecessary toggling of the power wells. | |
4705 | */ | |
d3fcc808 | 4706 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4707 | enum intel_display_power_domain domain; |
4708 | ||
4709 | if (!crtc->base.enabled) | |
4710 | continue; | |
4711 | ||
319be8ae | 4712 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4713 | |
4714 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4715 | intel_display_power_get(dev_priv, domain); | |
4716 | } | |
4717 | ||
50f6e502 VS |
4718 | if (dev_priv->display.modeset_global_resources) |
4719 | dev_priv->display.modeset_global_resources(dev); | |
4720 | ||
d3fcc808 | 4721 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4722 | enum intel_display_power_domain domain; |
4723 | ||
4724 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4725 | intel_display_power_put(dev_priv, domain); | |
4726 | ||
4727 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4728 | } | |
4729 | ||
4730 | intel_display_set_init_power(dev_priv, false); | |
4731 | } | |
4732 | ||
dfcab17e | 4733 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4734 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4735 | { |
586f49dc | 4736 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4737 | |
586f49dc JB |
4738 | /* Obtain SKU information */ |
4739 | mutex_lock(&dev_priv->dpio_lock); | |
4740 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4741 | CCK_FUSE_HPLL_FREQ_MASK; | |
4742 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4743 | |
dfcab17e | 4744 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4745 | } |
4746 | ||
f8bf63fd VS |
4747 | static void vlv_update_cdclk(struct drm_device *dev) |
4748 | { | |
4749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4750 | ||
4751 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
43dc52c3 | 4752 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
f8bf63fd VS |
4753 | dev_priv->vlv_cdclk_freq); |
4754 | ||
4755 | /* | |
4756 | * Program the gmbus_freq based on the cdclk frequency. | |
4757 | * BSpec erroneously claims we should aim for 4MHz, but | |
4758 | * in fact 1MHz is the correct frequency. | |
4759 | */ | |
6be1e3d3 | 4760 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); |
f8bf63fd VS |
4761 | } |
4762 | ||
30a970c6 JB |
4763 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4764 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4765 | { | |
4766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4767 | u32 val, cmd; | |
4768 | ||
d197b7d3 | 4769 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 4770 | |
dfcab17e | 4771 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 4772 | cmd = 2; |
dfcab17e | 4773 | else if (cdclk == 266667) |
30a970c6 JB |
4774 | cmd = 1; |
4775 | else | |
4776 | cmd = 0; | |
4777 | ||
4778 | mutex_lock(&dev_priv->rps.hw_lock); | |
4779 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4780 | val &= ~DSPFREQGUAR_MASK; | |
4781 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4782 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4783 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4784 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4785 | 50)) { | |
4786 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4787 | } | |
4788 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4789 | ||
dfcab17e | 4790 | if (cdclk == 400000) { |
6bcda4f0 | 4791 | u32 divider; |
30a970c6 | 4792 | |
6bcda4f0 | 4793 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
4794 | |
4795 | mutex_lock(&dev_priv->dpio_lock); | |
4796 | /* adjust cdclk divider */ | |
4797 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 4798 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
4799 | val |= divider; |
4800 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
4801 | |
4802 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
4803 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
4804 | 50)) | |
4805 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
4806 | mutex_unlock(&dev_priv->dpio_lock); |
4807 | } | |
4808 | ||
4809 | mutex_lock(&dev_priv->dpio_lock); | |
4810 | /* adjust self-refresh exit latency value */ | |
4811 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4812 | val &= ~0x7f; | |
4813 | ||
4814 | /* | |
4815 | * For high bandwidth configs, we set a higher latency in the bunit | |
4816 | * so that the core display fetch happens in time to avoid underruns. | |
4817 | */ | |
dfcab17e | 4818 | if (cdclk == 400000) |
30a970c6 JB |
4819 | val |= 4500 / 250; /* 4.5 usec */ |
4820 | else | |
4821 | val |= 3000 / 250; /* 3.0 usec */ | |
4822 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4823 | mutex_unlock(&dev_priv->dpio_lock); | |
4824 | ||
f8bf63fd | 4825 | vlv_update_cdclk(dev); |
30a970c6 JB |
4826 | } |
4827 | ||
383c5a6a VS |
4828 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
4829 | { | |
4830 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4831 | u32 val, cmd; | |
4832 | ||
4833 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
4834 | ||
4835 | switch (cdclk) { | |
4836 | case 400000: | |
4837 | cmd = 3; | |
4838 | break; | |
4839 | case 333333: | |
4840 | case 320000: | |
4841 | cmd = 2; | |
4842 | break; | |
4843 | case 266667: | |
4844 | cmd = 1; | |
4845 | break; | |
4846 | case 200000: | |
4847 | cmd = 0; | |
4848 | break; | |
4849 | default: | |
5f77eeb0 | 4850 | MISSING_CASE(cdclk); |
383c5a6a VS |
4851 | return; |
4852 | } | |
4853 | ||
4854 | mutex_lock(&dev_priv->rps.hw_lock); | |
4855 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4856 | val &= ~DSPFREQGUAR_MASK_CHV; | |
4857 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
4858 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4859 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4860 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
4861 | 50)) { | |
4862 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4863 | } | |
4864 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4865 | ||
4866 | vlv_update_cdclk(dev); | |
4867 | } | |
4868 | ||
30a970c6 JB |
4869 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4870 | int max_pixclk) | |
4871 | { | |
6bcda4f0 | 4872 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
29dc7ef3 | 4873 | |
d49a340d VS |
4874 | /* FIXME: Punit isn't quite ready yet */ |
4875 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
4876 | return 400000; | |
4877 | ||
30a970c6 JB |
4878 | /* |
4879 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4880 | * 200MHz | |
4881 | * 267MHz | |
29dc7ef3 | 4882 | * 320/333MHz (depends on HPLL freq) |
30a970c6 JB |
4883 | * 400MHz |
4884 | * So we check to see whether we're above 90% of the lower bin and | |
4885 | * adjust if needed. | |
e37c67a1 VS |
4886 | * |
4887 | * We seem to get an unstable or solid color picture at 200MHz. | |
4888 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
4889 | * are off. | |
30a970c6 | 4890 | */ |
29dc7ef3 | 4891 | if (max_pixclk > freq_320*9/10) |
dfcab17e VS |
4892 | return 400000; |
4893 | else if (max_pixclk > 266667*9/10) | |
29dc7ef3 | 4894 | return freq_320; |
e37c67a1 | 4895 | else if (max_pixclk > 0) |
dfcab17e | 4896 | return 266667; |
e37c67a1 VS |
4897 | else |
4898 | return 200000; | |
30a970c6 JB |
4899 | } |
4900 | ||
2f2d7aa1 VS |
4901 | /* compute the max pixel clock for new configuration */ |
4902 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4903 | { |
4904 | struct drm_device *dev = dev_priv->dev; | |
4905 | struct intel_crtc *intel_crtc; | |
4906 | int max_pixclk = 0; | |
4907 | ||
d3fcc808 | 4908 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4909 | if (intel_crtc->new_enabled) |
30a970c6 | 4910 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4911 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4912 | } |
4913 | ||
4914 | return max_pixclk; | |
4915 | } | |
4916 | ||
4917 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4918 | unsigned *prepare_pipes) |
30a970c6 JB |
4919 | { |
4920 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4921 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4922 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4923 | |
d60c4473 ID |
4924 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4925 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4926 | return; |
4927 | ||
2f2d7aa1 | 4928 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4929 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4930 | if (intel_crtc->base.enabled) |
4931 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4932 | } | |
4933 | ||
4934 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4935 | { | |
4936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4937 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4938 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4939 | ||
383c5a6a | 4940 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
738c05c0 ID |
4941 | /* |
4942 | * FIXME: We can end up here with all power domains off, yet | |
4943 | * with a CDCLK frequency other than the minimum. To account | |
4944 | * for this take the PIPE-A power domain, which covers the HW | |
4945 | * blocks needed for the following programming. This can be | |
4946 | * removed once it's guaranteed that we get here either with | |
4947 | * the minimum CDCLK set, or the required power domains | |
4948 | * enabled. | |
4949 | */ | |
4950 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
4951 | ||
383c5a6a VS |
4952 | if (IS_CHERRYVIEW(dev)) |
4953 | cherryview_set_cdclk(dev, req_cdclk); | |
4954 | else | |
4955 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 ID |
4956 | |
4957 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); | |
383c5a6a | 4958 | } |
30a970c6 JB |
4959 | } |
4960 | ||
89b667f8 JB |
4961 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4962 | { | |
4963 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 4964 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
4965 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4966 | struct intel_encoder *encoder; | |
4967 | int pipe = intel_crtc->pipe; | |
23538ef1 | 4968 | bool is_dsi; |
89b667f8 JB |
4969 | |
4970 | WARN_ON(!crtc->enabled); | |
4971 | ||
4972 | if (intel_crtc->active) | |
4973 | return; | |
4974 | ||
409ee761 | 4975 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 4976 | |
1ae0d137 VS |
4977 | if (!is_dsi) { |
4978 | if (IS_CHERRYVIEW(dev)) | |
d288f65f | 4979 | chv_prepare_pll(intel_crtc, &intel_crtc->config); |
1ae0d137 | 4980 | else |
d288f65f | 4981 | vlv_prepare_pll(intel_crtc, &intel_crtc->config); |
1ae0d137 | 4982 | } |
5b18e57c DV |
4983 | |
4984 | if (intel_crtc->config.has_dp_encoder) | |
4985 | intel_dp_set_m_n(intel_crtc); | |
4986 | ||
4987 | intel_set_pipe_timings(intel_crtc); | |
4988 | ||
c14b0485 VS |
4989 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
4990 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4991 | ||
4992 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
4993 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
4994 | } | |
4995 | ||
5b18e57c DV |
4996 | i9xx_set_pipeconf(intel_crtc); |
4997 | ||
89b667f8 | 4998 | intel_crtc->active = true; |
89b667f8 | 4999 | |
a72e4c9f | 5000 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5001 | |
89b667f8 JB |
5002 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5003 | if (encoder->pre_pll_enable) | |
5004 | encoder->pre_pll_enable(encoder); | |
5005 | ||
9d556c99 CML |
5006 | if (!is_dsi) { |
5007 | if (IS_CHERRYVIEW(dev)) | |
d288f65f | 5008 | chv_enable_pll(intel_crtc, &intel_crtc->config); |
9d556c99 | 5009 | else |
d288f65f | 5010 | vlv_enable_pll(intel_crtc, &intel_crtc->config); |
9d556c99 | 5011 | } |
89b667f8 JB |
5012 | |
5013 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5014 | if (encoder->pre_enable) | |
5015 | encoder->pre_enable(encoder); | |
5016 | ||
2dd24552 JB |
5017 | i9xx_pfit_enable(intel_crtc); |
5018 | ||
63cbb074 VS |
5019 | intel_crtc_load_lut(crtc); |
5020 | ||
f37fcc2a | 5021 | intel_update_watermarks(crtc); |
e1fdc473 | 5022 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5023 | |
4b3a9526 VS |
5024 | assert_vblank_disabled(crtc); |
5025 | drm_crtc_vblank_on(crtc); | |
5026 | ||
f9b61ff6 DV |
5027 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5028 | encoder->enable(encoder); | |
5029 | ||
9ab0460b | 5030 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5031 | |
56b80e1f | 5032 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5033 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5034 | } |
5035 | ||
f13c2ef3 DV |
5036 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5037 | { | |
5038 | struct drm_device *dev = crtc->base.dev; | |
5039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5040 | ||
5041 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
5042 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
5043 | } | |
5044 | ||
0b8765c6 | 5045 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5046 | { |
5047 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5048 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5050 | struct intel_encoder *encoder; |
79e53945 | 5051 | int pipe = intel_crtc->pipe; |
79e53945 | 5052 | |
08a48469 DV |
5053 | WARN_ON(!crtc->enabled); |
5054 | ||
f7abfe8b CW |
5055 | if (intel_crtc->active) |
5056 | return; | |
5057 | ||
f13c2ef3 DV |
5058 | i9xx_set_pll_dividers(intel_crtc); |
5059 | ||
5b18e57c DV |
5060 | if (intel_crtc->config.has_dp_encoder) |
5061 | intel_dp_set_m_n(intel_crtc); | |
5062 | ||
5063 | intel_set_pipe_timings(intel_crtc); | |
5064 | ||
5b18e57c DV |
5065 | i9xx_set_pipeconf(intel_crtc); |
5066 | ||
f7abfe8b | 5067 | intel_crtc->active = true; |
6b383a7f | 5068 | |
4a3436e8 | 5069 | if (!IS_GEN2(dev)) |
a72e4c9f | 5070 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5071 | |
9d6d9f19 MK |
5072 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5073 | if (encoder->pre_enable) | |
5074 | encoder->pre_enable(encoder); | |
5075 | ||
f6736a1a DV |
5076 | i9xx_enable_pll(intel_crtc); |
5077 | ||
2dd24552 JB |
5078 | i9xx_pfit_enable(intel_crtc); |
5079 | ||
63cbb074 VS |
5080 | intel_crtc_load_lut(crtc); |
5081 | ||
f37fcc2a | 5082 | intel_update_watermarks(crtc); |
e1fdc473 | 5083 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5084 | |
4b3a9526 VS |
5085 | assert_vblank_disabled(crtc); |
5086 | drm_crtc_vblank_on(crtc); | |
5087 | ||
f9b61ff6 DV |
5088 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5089 | encoder->enable(encoder); | |
5090 | ||
9ab0460b | 5091 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5092 | |
4a3436e8 VS |
5093 | /* |
5094 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5095 | * So don't enable underrun reporting before at least some planes | |
5096 | * are enabled. | |
5097 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5098 | * but leave the pipe running. | |
5099 | */ | |
5100 | if (IS_GEN2(dev)) | |
a72e4c9f | 5101 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5102 | |
56b80e1f | 5103 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5104 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5105 | } |
79e53945 | 5106 | |
87476d63 DV |
5107 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5108 | { | |
5109 | struct drm_device *dev = crtc->base.dev; | |
5110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5111 | |
328d8e82 DV |
5112 | if (!crtc->config.gmch_pfit.control) |
5113 | return; | |
87476d63 | 5114 | |
328d8e82 | 5115 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5116 | |
328d8e82 DV |
5117 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5118 | I915_READ(PFIT_CONTROL)); | |
5119 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5120 | } |
5121 | ||
0b8765c6 JB |
5122 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5123 | { | |
5124 | struct drm_device *dev = crtc->dev; | |
5125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5126 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5127 | struct intel_encoder *encoder; |
0b8765c6 | 5128 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5129 | |
f7abfe8b CW |
5130 | if (!intel_crtc->active) |
5131 | return; | |
5132 | ||
4a3436e8 VS |
5133 | /* |
5134 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5135 | * So diasble underrun reporting before all the planes get disabled. | |
5136 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5137 | * but leave the pipe running. | |
5138 | */ | |
5139 | if (IS_GEN2(dev)) | |
a72e4c9f | 5140 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5141 | |
564ed191 ID |
5142 | /* |
5143 | * Vblank time updates from the shadow to live plane control register | |
5144 | * are blocked if the memory self-refresh mode is active at that | |
5145 | * moment. So to make sure the plane gets truly disabled, disable | |
5146 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5147 | * will be checked/applied by the HW only at the next frame start | |
5148 | * event which is after the vblank start event, so we need to have a | |
5149 | * wait-for-vblank between disabling the plane and the pipe. | |
5150 | */ | |
5151 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5152 | intel_crtc_disable_planes(crtc); |
5153 | ||
6304cd91 VS |
5154 | /* |
5155 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5156 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5157 | * We also need to wait on all gmch platforms because of the |
5158 | * self-refresh mode constraint explained above. | |
6304cd91 | 5159 | */ |
564ed191 | 5160 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5161 | |
4b3a9526 VS |
5162 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5163 | encoder->disable(encoder); | |
5164 | ||
f9b61ff6 DV |
5165 | drm_crtc_vblank_off(crtc); |
5166 | assert_vblank_disabled(crtc); | |
5167 | ||
575f7ab7 | 5168 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5169 | |
87476d63 | 5170 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5171 | |
89b667f8 JB |
5172 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5173 | if (encoder->post_disable) | |
5174 | encoder->post_disable(encoder); | |
5175 | ||
409ee761 | 5176 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5177 | if (IS_CHERRYVIEW(dev)) |
5178 | chv_disable_pll(dev_priv, pipe); | |
5179 | else if (IS_VALLEYVIEW(dev)) | |
5180 | vlv_disable_pll(dev_priv, pipe); | |
5181 | else | |
1c4e0274 | 5182 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5183 | } |
0b8765c6 | 5184 | |
4a3436e8 | 5185 | if (!IS_GEN2(dev)) |
a72e4c9f | 5186 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5187 | |
f7abfe8b | 5188 | intel_crtc->active = false; |
46ba614c | 5189 | intel_update_watermarks(crtc); |
f37fcc2a | 5190 | |
efa9624e | 5191 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 5192 | intel_fbc_update(dev); |
efa9624e | 5193 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5194 | } |
5195 | ||
ee7b9f93 JB |
5196 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5197 | { | |
5198 | } | |
5199 | ||
b04c5bd6 BF |
5200 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5201 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5202 | { |
5203 | struct drm_device *dev = crtc->dev; | |
5204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5206 | enum intel_display_power_domain domain; |
5207 | unsigned long domains; | |
976f8a20 | 5208 | |
0e572fe7 DV |
5209 | if (enable) { |
5210 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5211 | domains = get_crtc_power_domains(crtc); |
5212 | for_each_power_domain(domain, domains) | |
5213 | intel_display_power_get(dev_priv, domain); | |
5214 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5215 | |
5216 | dev_priv->display.crtc_enable(crtc); | |
5217 | } | |
5218 | } else { | |
5219 | if (intel_crtc->active) { | |
5220 | dev_priv->display.crtc_disable(crtc); | |
5221 | ||
e1e9fb84 DV |
5222 | domains = intel_crtc->enabled_power_domains; |
5223 | for_each_power_domain(domain, domains) | |
5224 | intel_display_power_put(dev_priv, domain); | |
5225 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
5226 | } |
5227 | } | |
b04c5bd6 BF |
5228 | } |
5229 | ||
5230 | /** | |
5231 | * Sets the power management mode of the pipe and plane. | |
5232 | */ | |
5233 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
5234 | { | |
5235 | struct drm_device *dev = crtc->dev; | |
5236 | struct intel_encoder *intel_encoder; | |
5237 | bool enable = false; | |
5238 | ||
5239 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
5240 | enable |= intel_encoder->connectors_active; | |
5241 | ||
5242 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
5243 | } |
5244 | ||
cdd59983 CW |
5245 | static void intel_crtc_disable(struct drm_crtc *crtc) |
5246 | { | |
cdd59983 | 5247 | struct drm_device *dev = crtc->dev; |
976f8a20 | 5248 | struct drm_connector *connector; |
ee7b9f93 | 5249 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 5250 | |
976f8a20 DV |
5251 | /* crtc should still be enabled when we disable it. */ |
5252 | WARN_ON(!crtc->enabled); | |
5253 | ||
5254 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
5255 | dev_priv->display.off(crtc); |
5256 | ||
455a6808 | 5257 | crtc->primary->funcs->disable_plane(crtc->primary); |
976f8a20 DV |
5258 | |
5259 | /* Update computed state. */ | |
5260 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5261 | if (!connector->encoder || !connector->encoder->crtc) | |
5262 | continue; | |
5263 | ||
5264 | if (connector->encoder->crtc != crtc) | |
5265 | continue; | |
5266 | ||
5267 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5268 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5269 | } |
5270 | } | |
5271 | ||
ea5b213a | 5272 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5273 | { |
4ef69c7a | 5274 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5275 | |
ea5b213a CW |
5276 | drm_encoder_cleanup(encoder); |
5277 | kfree(intel_encoder); | |
7e7d76c3 JB |
5278 | } |
5279 | ||
9237329d | 5280 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5281 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5282 | * state of the entire output pipe. */ | |
9237329d | 5283 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5284 | { |
5ab432ef DV |
5285 | if (mode == DRM_MODE_DPMS_ON) { |
5286 | encoder->connectors_active = true; | |
5287 | ||
b2cabb0e | 5288 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5289 | } else { |
5290 | encoder->connectors_active = false; | |
5291 | ||
b2cabb0e | 5292 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5293 | } |
79e53945 JB |
5294 | } |
5295 | ||
0a91ca29 DV |
5296 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5297 | * internal consistency). */ | |
b980514c | 5298 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5299 | { |
0a91ca29 DV |
5300 | if (connector->get_hw_state(connector)) { |
5301 | struct intel_encoder *encoder = connector->encoder; | |
5302 | struct drm_crtc *crtc; | |
5303 | bool encoder_enabled; | |
5304 | enum pipe pipe; | |
5305 | ||
5306 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5307 | connector->base.base.id, | |
c23cc417 | 5308 | connector->base.name); |
0a91ca29 | 5309 | |
0e32b39c DA |
5310 | /* there is no real hw state for MST connectors */ |
5311 | if (connector->mst_port) | |
5312 | return; | |
5313 | ||
e2c719b7 | 5314 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 5315 | "wrong connector dpms state\n"); |
e2c719b7 | 5316 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 5317 | "active connector not linked to encoder\n"); |
0a91ca29 | 5318 | |
36cd7444 | 5319 | if (encoder) { |
e2c719b7 | 5320 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
5321 | "encoder->connectors_active not set\n"); |
5322 | ||
5323 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
5324 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
5325 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 5326 | return; |
0a91ca29 | 5327 | |
36cd7444 | 5328 | crtc = encoder->base.crtc; |
0a91ca29 | 5329 | |
e2c719b7 RC |
5330 | I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n"); |
5331 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
5332 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
5333 | "encoder active on the wrong pipe\n"); |
5334 | } | |
0a91ca29 | 5335 | } |
79e53945 JB |
5336 | } |
5337 | ||
5ab432ef DV |
5338 | /* Even simpler default implementation, if there's really no special case to |
5339 | * consider. */ | |
5340 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5341 | { |
5ab432ef DV |
5342 | /* All the simple cases only support two dpms states. */ |
5343 | if (mode != DRM_MODE_DPMS_ON) | |
5344 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5345 | |
5ab432ef DV |
5346 | if (mode == connector->dpms) |
5347 | return; | |
5348 | ||
5349 | connector->dpms = mode; | |
5350 | ||
5351 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5352 | if (connector->encoder) |
5353 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5354 | |
b980514c | 5355 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5356 | } |
5357 | ||
f0947c37 DV |
5358 | /* Simple connector->get_hw_state implementation for encoders that support only |
5359 | * one connector and no cloning and hence the encoder state determines the state | |
5360 | * of the connector. */ | |
5361 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5362 | { |
24929352 | 5363 | enum pipe pipe = 0; |
f0947c37 | 5364 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5365 | |
f0947c37 | 5366 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5367 | } |
5368 | ||
1857e1da DV |
5369 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5370 | struct intel_crtc_config *pipe_config) | |
5371 | { | |
5372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5373 | struct intel_crtc *pipe_B_crtc = | |
5374 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5375 | ||
5376 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5377 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5378 | if (pipe_config->fdi_lanes > 4) { | |
5379 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5380 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5381 | return false; | |
5382 | } | |
5383 | ||
bafb6553 | 5384 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5385 | if (pipe_config->fdi_lanes > 2) { |
5386 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5387 | pipe_config->fdi_lanes); | |
5388 | return false; | |
5389 | } else { | |
5390 | return true; | |
5391 | } | |
5392 | } | |
5393 | ||
5394 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5395 | return true; | |
5396 | ||
5397 | /* Ivybridge 3 pipe is really complicated */ | |
5398 | switch (pipe) { | |
5399 | case PIPE_A: | |
5400 | return true; | |
5401 | case PIPE_B: | |
5402 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5403 | pipe_config->fdi_lanes > 2) { | |
5404 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5405 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5406 | return false; | |
5407 | } | |
5408 | return true; | |
5409 | case PIPE_C: | |
1e833f40 | 5410 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5411 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5412 | if (pipe_config->fdi_lanes > 2) { | |
5413 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5414 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5415 | return false; | |
5416 | } | |
5417 | } else { | |
5418 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5419 | return false; | |
5420 | } | |
5421 | return true; | |
5422 | default: | |
5423 | BUG(); | |
5424 | } | |
5425 | } | |
5426 | ||
e29c22c0 DV |
5427 | #define RETRY 1 |
5428 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5429 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5430 | { |
1857e1da | 5431 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5432 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5433 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5434 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5435 | |
e29c22c0 | 5436 | retry: |
877d48d5 DV |
5437 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5438 | * each output octet as 10 bits. The actual frequency | |
5439 | * is stored as a divider into a 100MHz clock, and the | |
5440 | * mode pixel clock is stored in units of 1KHz. | |
5441 | * Hence the bw of each lane in terms of the mode signal | |
5442 | * is: | |
5443 | */ | |
5444 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5445 | ||
241bfc38 | 5446 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5447 | |
2bd89a07 | 5448 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5449 | pipe_config->pipe_bpp); |
5450 | ||
5451 | pipe_config->fdi_lanes = lane; | |
5452 | ||
2bd89a07 | 5453 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5454 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5455 | |
e29c22c0 DV |
5456 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5457 | intel_crtc->pipe, pipe_config); | |
5458 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5459 | pipe_config->pipe_bpp -= 2*3; | |
5460 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5461 | pipe_config->pipe_bpp); | |
5462 | needs_recompute = true; | |
5463 | pipe_config->bw_constrained = true; | |
5464 | ||
5465 | goto retry; | |
5466 | } | |
5467 | ||
5468 | if (needs_recompute) | |
5469 | return RETRY; | |
5470 | ||
5471 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5472 | } |
5473 | ||
42db64ef PZ |
5474 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5475 | struct intel_crtc_config *pipe_config) | |
5476 | { | |
d330a953 | 5477 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5478 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5479 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5480 | } |
5481 | ||
a43f6e0f | 5482 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5483 | struct intel_crtc_config *pipe_config) |
79e53945 | 5484 | { |
a43f6e0f | 5485 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 5486 | struct drm_i915_private *dev_priv = dev->dev_private; |
b8cecdf5 | 5487 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5488 | |
ad3a4479 | 5489 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 5490 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
5491 | int clock_limit = |
5492 | dev_priv->display.get_display_clock_speed(dev); | |
5493 | ||
5494 | /* | |
5495 | * Enable pixel doubling when the dot clock | |
5496 | * is > 90% of the (display) core speed. | |
5497 | * | |
b397c96b VS |
5498 | * GDG double wide on either pipe, |
5499 | * otherwise pipe A only. | |
cf532bb2 | 5500 | */ |
b397c96b | 5501 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5502 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5503 | clock_limit *= 2; |
cf532bb2 | 5504 | pipe_config->double_wide = true; |
ad3a4479 VS |
5505 | } |
5506 | ||
241bfc38 | 5507 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5508 | return -EINVAL; |
2c07245f | 5509 | } |
89749350 | 5510 | |
1d1d0e27 VS |
5511 | /* |
5512 | * Pipe horizontal size must be even in: | |
5513 | * - DVO ganged mode | |
5514 | * - LVDS dual channel mode | |
5515 | * - Double wide pipe | |
5516 | */ | |
409ee761 | 5517 | if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
5518 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
5519 | pipe_config->pipe_src_w &= ~1; | |
5520 | ||
8693a824 DL |
5521 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5522 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5523 | */ |
5524 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5525 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5526 | return -EINVAL; |
44f46b42 | 5527 | |
bd080ee5 | 5528 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5529 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5530 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5531 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5532 | * for lvds. */ | |
5533 | pipe_config->pipe_bpp = 8*3; | |
5534 | } | |
5535 | ||
f5adf94e | 5536 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5537 | hsw_compute_ips_config(crtc, pipe_config); |
5538 | ||
877d48d5 | 5539 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5540 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5541 | |
e29c22c0 | 5542 | return 0; |
79e53945 JB |
5543 | } |
5544 | ||
25eb05fc JB |
5545 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5546 | { | |
d197b7d3 | 5547 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
5548 | u32 val; |
5549 | int divider; | |
5550 | ||
d49a340d VS |
5551 | /* FIXME: Punit isn't quite ready yet */ |
5552 | if (IS_CHERRYVIEW(dev)) | |
5553 | return 400000; | |
5554 | ||
6bcda4f0 VS |
5555 | if (dev_priv->hpll_freq == 0) |
5556 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
5557 | ||
d197b7d3 VS |
5558 | mutex_lock(&dev_priv->dpio_lock); |
5559 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5560 | mutex_unlock(&dev_priv->dpio_lock); | |
5561 | ||
5562 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5563 | ||
7d007f40 VS |
5564 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5565 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5566 | "cdclk change in progress\n"); | |
5567 | ||
6bcda4f0 | 5568 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
5569 | } |
5570 | ||
e70236a8 JB |
5571 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5572 | { | |
5573 | return 400000; | |
5574 | } | |
79e53945 | 5575 | |
e70236a8 | 5576 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5577 | { |
e70236a8 JB |
5578 | return 333000; |
5579 | } | |
79e53945 | 5580 | |
e70236a8 JB |
5581 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5582 | { | |
5583 | return 200000; | |
5584 | } | |
79e53945 | 5585 | |
257a7ffc DV |
5586 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5587 | { | |
5588 | u16 gcfgc = 0; | |
5589 | ||
5590 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5591 | ||
5592 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5593 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5594 | return 267000; | |
5595 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5596 | return 333000; | |
5597 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5598 | return 444000; | |
5599 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5600 | return 200000; | |
5601 | default: | |
5602 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5603 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5604 | return 133000; | |
5605 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5606 | return 167000; | |
5607 | } | |
5608 | } | |
5609 | ||
e70236a8 JB |
5610 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5611 | { | |
5612 | u16 gcfgc = 0; | |
79e53945 | 5613 | |
e70236a8 JB |
5614 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5615 | ||
5616 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5617 | return 133000; | |
5618 | else { | |
5619 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5620 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5621 | return 333000; | |
5622 | default: | |
5623 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5624 | return 190000; | |
79e53945 | 5625 | } |
e70236a8 JB |
5626 | } |
5627 | } | |
5628 | ||
5629 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5630 | { | |
5631 | return 266000; | |
5632 | } | |
5633 | ||
5634 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5635 | { | |
5636 | u16 hpllcc = 0; | |
5637 | /* Assume that the hardware is in the high speed state. This | |
5638 | * should be the default. | |
5639 | */ | |
5640 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5641 | case GC_CLOCK_133_200: | |
5642 | case GC_CLOCK_100_200: | |
5643 | return 200000; | |
5644 | case GC_CLOCK_166_250: | |
5645 | return 250000; | |
5646 | case GC_CLOCK_100_133: | |
79e53945 | 5647 | return 133000; |
e70236a8 | 5648 | } |
79e53945 | 5649 | |
e70236a8 JB |
5650 | /* Shouldn't happen */ |
5651 | return 0; | |
5652 | } | |
79e53945 | 5653 | |
e70236a8 JB |
5654 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5655 | { | |
5656 | return 133000; | |
79e53945 JB |
5657 | } |
5658 | ||
2c07245f | 5659 | static void |
a65851af | 5660 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5661 | { |
a65851af VS |
5662 | while (*num > DATA_LINK_M_N_MASK || |
5663 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5664 | *num >>= 1; |
5665 | *den >>= 1; | |
5666 | } | |
5667 | } | |
5668 | ||
a65851af VS |
5669 | static void compute_m_n(unsigned int m, unsigned int n, |
5670 | uint32_t *ret_m, uint32_t *ret_n) | |
5671 | { | |
5672 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5673 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5674 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5675 | } | |
5676 | ||
e69d0bc1 DV |
5677 | void |
5678 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5679 | int pixel_clock, int link_clock, | |
5680 | struct intel_link_m_n *m_n) | |
2c07245f | 5681 | { |
e69d0bc1 | 5682 | m_n->tu = 64; |
a65851af VS |
5683 | |
5684 | compute_m_n(bits_per_pixel * pixel_clock, | |
5685 | link_clock * nlanes * 8, | |
5686 | &m_n->gmch_m, &m_n->gmch_n); | |
5687 | ||
5688 | compute_m_n(pixel_clock, link_clock, | |
5689 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5690 | } |
5691 | ||
a7615030 CW |
5692 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5693 | { | |
d330a953 JN |
5694 | if (i915.panel_use_ssc >= 0) |
5695 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5696 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5697 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5698 | } |
5699 | ||
409ee761 | 5700 | static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors) |
c65d77d8 | 5701 | { |
409ee761 | 5702 | struct drm_device *dev = crtc->base.dev; |
c65d77d8 JB |
5703 | struct drm_i915_private *dev_priv = dev->dev_private; |
5704 | int refclk; | |
5705 | ||
a0c4da24 | 5706 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5707 | refclk = 100000; |
d0737e1d | 5708 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5709 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5710 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5711 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5712 | } else if (!IS_GEN2(dev)) { |
5713 | refclk = 96000; | |
5714 | } else { | |
5715 | refclk = 48000; | |
5716 | } | |
5717 | ||
5718 | return refclk; | |
5719 | } | |
5720 | ||
7429e9d4 | 5721 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5722 | { |
7df00d7a | 5723 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5724 | } |
f47709a9 | 5725 | |
7429e9d4 DV |
5726 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5727 | { | |
5728 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5729 | } |
5730 | ||
f47709a9 | 5731 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5732 | intel_clock_t *reduced_clock) |
5733 | { | |
f47709a9 | 5734 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5735 | u32 fp, fp2 = 0; |
5736 | ||
5737 | if (IS_PINEVIEW(dev)) { | |
e1f234bd | 5738 | fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); |
a7516a05 | 5739 | if (reduced_clock) |
7429e9d4 | 5740 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5741 | } else { |
e1f234bd | 5742 | fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); |
a7516a05 | 5743 | if (reduced_clock) |
7429e9d4 | 5744 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5745 | } |
5746 | ||
e1f234bd | 5747 | crtc->new_config->dpll_hw_state.fp0 = fp; |
a7516a05 | 5748 | |
f47709a9 | 5749 | crtc->lowfreq_avail = false; |
e1f234bd | 5750 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
d330a953 | 5751 | reduced_clock && i915.powersave) { |
e1f234bd | 5752 | crtc->new_config->dpll_hw_state.fp1 = fp2; |
f47709a9 | 5753 | crtc->lowfreq_avail = true; |
a7516a05 | 5754 | } else { |
e1f234bd | 5755 | crtc->new_config->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5756 | } |
5757 | } | |
5758 | ||
5e69f97f CML |
5759 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5760 | pipe) | |
89b667f8 JB |
5761 | { |
5762 | u32 reg_val; | |
5763 | ||
5764 | /* | |
5765 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5766 | * and set it to a reasonable value instead. | |
5767 | */ | |
ab3c759a | 5768 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5769 | reg_val &= 0xffffff00; |
5770 | reg_val |= 0x00000030; | |
ab3c759a | 5771 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5772 | |
ab3c759a | 5773 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5774 | reg_val &= 0x8cffffff; |
5775 | reg_val = 0x8c000000; | |
ab3c759a | 5776 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5777 | |
ab3c759a | 5778 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5779 | reg_val &= 0xffffff00; |
ab3c759a | 5780 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5781 | |
ab3c759a | 5782 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5783 | reg_val &= 0x00ffffff; |
5784 | reg_val |= 0xb0000000; | |
ab3c759a | 5785 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5786 | } |
5787 | ||
b551842d DV |
5788 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5789 | struct intel_link_m_n *m_n) | |
5790 | { | |
5791 | struct drm_device *dev = crtc->base.dev; | |
5792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5793 | int pipe = crtc->pipe; | |
5794 | ||
e3b95f1e DV |
5795 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5796 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5797 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5798 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5799 | } |
5800 | ||
5801 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
5802 | struct intel_link_m_n *m_n, |
5803 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
5804 | { |
5805 | struct drm_device *dev = crtc->base.dev; | |
5806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5807 | int pipe = crtc->pipe; | |
5808 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5809 | ||
5810 | if (INTEL_INFO(dev)->gen >= 5) { | |
5811 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5812 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5813 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5814 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
5815 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
5816 | * for gen < 8) and if DRRS is supported (to make sure the | |
5817 | * registers are not unnecessarily accessed). | |
5818 | */ | |
5819 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
5820 | crtc->config.has_drrs) { | |
5821 | I915_WRITE(PIPE_DATA_M2(transcoder), | |
5822 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
5823 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
5824 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
5825 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
5826 | } | |
b551842d | 5827 | } else { |
e3b95f1e DV |
5828 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5829 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5830 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5831 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5832 | } |
5833 | } | |
5834 | ||
f769cd24 | 5835 | void intel_dp_set_m_n(struct intel_crtc *crtc) |
03afc4a2 DV |
5836 | { |
5837 | if (crtc->config.has_pch_encoder) | |
5838 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5839 | else | |
f769cd24 VK |
5840 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, |
5841 | &crtc->config.dp_m2_n2); | |
03afc4a2 DV |
5842 | } |
5843 | ||
d288f65f VS |
5844 | static void vlv_update_pll(struct intel_crtc *crtc, |
5845 | struct intel_crtc_config *pipe_config) | |
bdd4b6a6 DV |
5846 | { |
5847 | u32 dpll, dpll_md; | |
5848 | ||
5849 | /* | |
5850 | * Enable DPIO clock input. We should never disable the reference | |
5851 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5852 | * on it. | |
5853 | */ | |
5854 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5855 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5856 | /* We should never disable this, set it here for state tracking */ | |
5857 | if (crtc->pipe == PIPE_B) | |
5858 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5859 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 5860 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 5861 | |
d288f65f | 5862 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 5863 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 5864 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
5865 | } |
5866 | ||
d288f65f VS |
5867 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5868 | const struct intel_crtc_config *pipe_config) | |
a0c4da24 | 5869 | { |
f47709a9 | 5870 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5871 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5872 | int pipe = crtc->pipe; |
bdd4b6a6 | 5873 | u32 mdiv; |
a0c4da24 | 5874 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5875 | u32 coreclk, reg_val; |
a0c4da24 | 5876 | |
09153000 DV |
5877 | mutex_lock(&dev_priv->dpio_lock); |
5878 | ||
d288f65f VS |
5879 | bestn = pipe_config->dpll.n; |
5880 | bestm1 = pipe_config->dpll.m1; | |
5881 | bestm2 = pipe_config->dpll.m2; | |
5882 | bestp1 = pipe_config->dpll.p1; | |
5883 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 5884 | |
89b667f8 JB |
5885 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5886 | ||
5887 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5888 | if (pipe == PIPE_B) |
5e69f97f | 5889 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5890 | |
5891 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5892 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5893 | |
5894 | /* Disable target IRef on PLL */ | |
ab3c759a | 5895 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5896 | reg_val &= 0x00ffffff; |
ab3c759a | 5897 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5898 | |
5899 | /* Disable fast lock */ | |
ab3c759a | 5900 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5901 | |
5902 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5903 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5904 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5905 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5906 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5907 | |
5908 | /* | |
5909 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5910 | * but we don't support that). | |
5911 | * Note: don't use the DAC post divider as it seems unstable. | |
5912 | */ | |
5913 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5914 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5915 | |
a0c4da24 | 5916 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5917 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5918 | |
89b667f8 | 5919 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 5920 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
5921 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
5922 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 5923 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5924 | 0x009f0003); |
89b667f8 | 5925 | else |
ab3c759a | 5926 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5927 | 0x00d0000f); |
5928 | ||
0a88818d | 5929 | if (crtc->config.has_dp_encoder) { |
89b667f8 | 5930 | /* Use SSC source */ |
bdd4b6a6 | 5931 | if (pipe == PIPE_A) |
ab3c759a | 5932 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5933 | 0x0df40000); |
5934 | else | |
ab3c759a | 5935 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5936 | 0x0df70000); |
5937 | } else { /* HDMI or VGA */ | |
5938 | /* Use bend source */ | |
bdd4b6a6 | 5939 | if (pipe == PIPE_A) |
ab3c759a | 5940 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5941 | 0x0df70000); |
5942 | else | |
ab3c759a | 5943 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5944 | 0x0df40000); |
5945 | } | |
a0c4da24 | 5946 | |
ab3c759a | 5947 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 5948 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
5949 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
5950 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 5951 | coreclk |= 0x01000000; |
ab3c759a | 5952 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5953 | |
ab3c759a | 5954 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5955 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5956 | } |
5957 | ||
d288f65f VS |
5958 | static void chv_update_pll(struct intel_crtc *crtc, |
5959 | struct intel_crtc_config *pipe_config) | |
1ae0d137 | 5960 | { |
d288f65f | 5961 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
5962 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
5963 | DPLL_VCO_ENABLE; | |
5964 | if (crtc->pipe != PIPE_A) | |
d288f65f | 5965 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 5966 | |
d288f65f VS |
5967 | pipe_config->dpll_hw_state.dpll_md = |
5968 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
5969 | } |
5970 | ||
d288f65f VS |
5971 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5972 | const struct intel_crtc_config *pipe_config) | |
9d556c99 CML |
5973 | { |
5974 | struct drm_device *dev = crtc->base.dev; | |
5975 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5976 | int pipe = crtc->pipe; | |
5977 | int dpll_reg = DPLL(crtc->pipe); | |
5978 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5979 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5980 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5981 | int refclk; | |
5982 | ||
d288f65f VS |
5983 | bestn = pipe_config->dpll.n; |
5984 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
5985 | bestm1 = pipe_config->dpll.m1; | |
5986 | bestm2 = pipe_config->dpll.m2 >> 22; | |
5987 | bestp1 = pipe_config->dpll.p1; | |
5988 | bestp2 = pipe_config->dpll.p2; | |
9d556c99 CML |
5989 | |
5990 | /* | |
5991 | * Enable Refclk and SSC | |
5992 | */ | |
a11b0703 | 5993 | I915_WRITE(dpll_reg, |
d288f65f | 5994 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
5995 | |
5996 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5997 | |
9d556c99 CML |
5998 | /* p1 and p2 divider */ |
5999 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6000 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6001 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6002 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6003 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6004 | ||
6005 | /* Feedback post-divider - m2 */ | |
6006 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6007 | ||
6008 | /* Feedback refclk divider - n and m1 */ | |
6009 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6010 | DPIO_CHV_M1_DIV_BY_2 | | |
6011 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6012 | ||
6013 | /* M2 fraction division */ | |
6014 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
6015 | ||
6016 | /* M2 fraction division enable */ | |
6017 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
6018 | DPIO_CHV_FRAC_DIV_EN | | |
6019 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
6020 | ||
6021 | /* Loop filter */ | |
409ee761 | 6022 | refclk = i9xx_get_refclk(crtc, 0); |
9d556c99 CML |
6023 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | |
6024 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
6025 | if (refclk == 100000) | |
6026 | intcoeff = 11; | |
6027 | else if (refclk == 38400) | |
6028 | intcoeff = 10; | |
6029 | else | |
6030 | intcoeff = 9; | |
6031 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
6032 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
6033 | ||
6034 | /* AFC Recal */ | |
6035 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6036 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6037 | DPIO_AFC_RECAL); | |
6038 | ||
6039 | mutex_unlock(&dev_priv->dpio_lock); | |
6040 | } | |
6041 | ||
d288f65f VS |
6042 | /** |
6043 | * vlv_force_pll_on - forcibly enable just the PLL | |
6044 | * @dev_priv: i915 private structure | |
6045 | * @pipe: pipe PLL to enable | |
6046 | * @dpll: PLL configuration | |
6047 | * | |
6048 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6049 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6050 | * be enabled. | |
6051 | */ | |
6052 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
6053 | const struct dpll *dpll) | |
6054 | { | |
6055 | struct intel_crtc *crtc = | |
6056 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
6057 | struct intel_crtc_config pipe_config = { | |
6058 | .pixel_multiplier = 1, | |
6059 | .dpll = *dpll, | |
6060 | }; | |
6061 | ||
6062 | if (IS_CHERRYVIEW(dev)) { | |
6063 | chv_update_pll(crtc, &pipe_config); | |
6064 | chv_prepare_pll(crtc, &pipe_config); | |
6065 | chv_enable_pll(crtc, &pipe_config); | |
6066 | } else { | |
6067 | vlv_update_pll(crtc, &pipe_config); | |
6068 | vlv_prepare_pll(crtc, &pipe_config); | |
6069 | vlv_enable_pll(crtc, &pipe_config); | |
6070 | } | |
6071 | } | |
6072 | ||
6073 | /** | |
6074 | * vlv_force_pll_off - forcibly disable just the PLL | |
6075 | * @dev_priv: i915 private structure | |
6076 | * @pipe: pipe PLL to disable | |
6077 | * | |
6078 | * Disable the PLL for @pipe. To be used in cases where we need | |
6079 | * the PLL enabled even when @pipe is not going to be enabled. | |
6080 | */ | |
6081 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
6082 | { | |
6083 | if (IS_CHERRYVIEW(dev)) | |
6084 | chv_disable_pll(to_i915(dev), pipe); | |
6085 | else | |
6086 | vlv_disable_pll(to_i915(dev), pipe); | |
6087 | } | |
6088 | ||
f47709a9 DV |
6089 | static void i9xx_update_pll(struct intel_crtc *crtc, |
6090 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
6091 | int num_connectors) |
6092 | { | |
f47709a9 | 6093 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6094 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
6095 | u32 dpll; |
6096 | bool is_sdvo; | |
d0737e1d | 6097 | struct dpll *clock = &crtc->new_config->dpll; |
eb1cbe48 | 6098 | |
f47709a9 | 6099 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 6100 | |
d0737e1d ACO |
6101 | is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) || |
6102 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
6103 | |
6104 | dpll = DPLL_VGA_MODE_DIS; | |
6105 | ||
d0737e1d | 6106 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6107 | dpll |= DPLLB_MODE_LVDS; |
6108 | else | |
6109 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6110 | |
ef1b460d | 6111 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
d0737e1d | 6112 | dpll |= (crtc->new_config->pixel_multiplier - 1) |
198a037f | 6113 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6114 | } |
198a037f DV |
6115 | |
6116 | if (is_sdvo) | |
4a33e48d | 6117 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6118 | |
0a88818d | 6119 | if (crtc->new_config->has_dp_encoder) |
4a33e48d | 6120 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6121 | |
6122 | /* compute bitmask from p1 value */ | |
6123 | if (IS_PINEVIEW(dev)) | |
6124 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
6125 | else { | |
6126 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6127 | if (IS_G4X(dev) && reduced_clock) | |
6128 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
6129 | } | |
6130 | switch (clock->p2) { | |
6131 | case 5: | |
6132 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6133 | break; | |
6134 | case 7: | |
6135 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6136 | break; | |
6137 | case 10: | |
6138 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6139 | break; | |
6140 | case 14: | |
6141 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6142 | break; | |
6143 | } | |
6144 | if (INTEL_INFO(dev)->gen >= 4) | |
6145 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
6146 | ||
d0737e1d | 6147 | if (crtc->new_config->sdvo_tv_clock) |
eb1cbe48 | 6148 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
d0737e1d | 6149 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6150 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6151 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6152 | else | |
6153 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6154 | ||
6155 | dpll |= DPLL_VCO_ENABLE; | |
d0737e1d | 6156 | crtc->new_config->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6157 | |
eb1cbe48 | 6158 | if (INTEL_INFO(dev)->gen >= 4) { |
d0737e1d | 6159 | u32 dpll_md = (crtc->new_config->pixel_multiplier - 1) |
ef1b460d | 6160 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d0737e1d | 6161 | crtc->new_config->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6162 | } |
6163 | } | |
6164 | ||
f47709a9 | 6165 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 6166 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6167 | int num_connectors) |
6168 | { | |
f47709a9 | 6169 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6170 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 6171 | u32 dpll; |
d0737e1d | 6172 | struct dpll *clock = &crtc->new_config->dpll; |
eb1cbe48 | 6173 | |
f47709a9 | 6174 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 6175 | |
eb1cbe48 DV |
6176 | dpll = DPLL_VGA_MODE_DIS; |
6177 | ||
d0737e1d | 6178 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6179 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6180 | } else { | |
6181 | if (clock->p1 == 2) | |
6182 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6183 | else | |
6184 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6185 | if (clock->p2 == 4) | |
6186 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6187 | } | |
6188 | ||
d0737e1d | 6189 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
6190 | dpll |= DPLL_DVO_2X_MODE; |
6191 | ||
d0737e1d | 6192 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6193 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6194 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6195 | else | |
6196 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6197 | ||
6198 | dpll |= DPLL_VCO_ENABLE; | |
d0737e1d | 6199 | crtc->new_config->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6200 | } |
6201 | ||
8a654f3b | 6202 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
6203 | { |
6204 | struct drm_device *dev = intel_crtc->base.dev; | |
6205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6206 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 6207 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
6208 | struct drm_display_mode *adjusted_mode = |
6209 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
6210 | uint32_t crtc_vtotal, crtc_vblank_end; |
6211 | int vsyncshift = 0; | |
4d8a62ea DV |
6212 | |
6213 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6214 | * the hw state checker will get angry at the mismatch. */ | |
6215 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6216 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6217 | |
609aeaca | 6218 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6219 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6220 | crtc_vtotal -= 1; |
6221 | crtc_vblank_end -= 1; | |
609aeaca | 6222 | |
409ee761 | 6223 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6224 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6225 | else | |
6226 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6227 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6228 | if (vsyncshift < 0) |
6229 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6230 | } |
6231 | ||
6232 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 6233 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6234 | |
fe2b8f9d | 6235 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6236 | (adjusted_mode->crtc_hdisplay - 1) | |
6237 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6238 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6239 | (adjusted_mode->crtc_hblank_start - 1) | |
6240 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6241 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6242 | (adjusted_mode->crtc_hsync_start - 1) | |
6243 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6244 | ||
fe2b8f9d | 6245 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6246 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6247 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6248 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6249 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6250 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6251 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6252 | (adjusted_mode->crtc_vsync_start - 1) | |
6253 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6254 | ||
b5e508d4 PZ |
6255 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6256 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6257 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6258 | * bits. */ | |
6259 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
6260 | (pipe == PIPE_B || pipe == PIPE_C)) | |
6261 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6262 | ||
b0e77b9c PZ |
6263 | /* pipesrc controls the size that is scaled from, which should |
6264 | * always be the user's requested size. | |
6265 | */ | |
6266 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
6267 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
6268 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
6269 | } |
6270 | ||
1bd1bd80 DV |
6271 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
6272 | struct intel_crtc_config *pipe_config) | |
6273 | { | |
6274 | struct drm_device *dev = crtc->base.dev; | |
6275 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6276 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
6277 | uint32_t tmp; | |
6278 | ||
6279 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
6280 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
6281 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
6282 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
6283 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
6284 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
6285 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
6286 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
6287 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
6288 | ||
6289 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
6290 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
6291 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
6292 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
6293 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
6294 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
6295 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
6296 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
6297 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
6298 | ||
6299 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
6300 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
6301 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
6302 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
6303 | } | |
6304 | ||
6305 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6306 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6307 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6308 | ||
6309 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
6310 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6311 | } |
6312 | ||
f6a83288 DV |
6313 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
6314 | struct intel_crtc_config *pipe_config) | |
babea61d | 6315 | { |
f6a83288 DV |
6316 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
6317 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
6318 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
6319 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 6320 | |
f6a83288 DV |
6321 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
6322 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
6323 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
6324 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 6325 | |
f6a83288 | 6326 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 6327 | |
f6a83288 DV |
6328 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
6329 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
6330 | } |
6331 | ||
84b046f3 DV |
6332 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6333 | { | |
6334 | struct drm_device *dev = intel_crtc->base.dev; | |
6335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6336 | uint32_t pipeconf; | |
6337 | ||
9f11a9e4 | 6338 | pipeconf = 0; |
84b046f3 | 6339 | |
b6b5d049 VS |
6340 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
6341 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
6342 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 6343 | |
cf532bb2 VS |
6344 | if (intel_crtc->config.double_wide) |
6345 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 6346 | |
ff9ce46e DV |
6347 | /* only g4x and later have fancy bpc/dither controls */ |
6348 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
6349 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6350 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
6351 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 6352 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6353 | |
ff9ce46e DV |
6354 | switch (intel_crtc->config.pipe_bpp) { |
6355 | case 18: | |
6356 | pipeconf |= PIPECONF_6BPC; | |
6357 | break; | |
6358 | case 24: | |
6359 | pipeconf |= PIPECONF_8BPC; | |
6360 | break; | |
6361 | case 30: | |
6362 | pipeconf |= PIPECONF_10BPC; | |
6363 | break; | |
6364 | default: | |
6365 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6366 | BUG(); | |
84b046f3 DV |
6367 | } |
6368 | } | |
6369 | ||
6370 | if (HAS_PIPE_CXSR(dev)) { | |
6371 | if (intel_crtc->lowfreq_avail) { | |
6372 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6373 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6374 | } else { | |
6375 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6376 | } |
6377 | } | |
6378 | ||
efc2cfff VS |
6379 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6380 | if (INTEL_INFO(dev)->gen < 4 || | |
409ee761 | 6381 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
6382 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6383 | else | |
6384 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6385 | } else | |
84b046f3 DV |
6386 | pipeconf |= PIPECONF_PROGRESSIVE; |
6387 | ||
9f11a9e4 DV |
6388 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
6389 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 6390 | |
84b046f3 DV |
6391 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6392 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6393 | } | |
6394 | ||
d6dfee7a | 6395 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc) |
79e53945 | 6396 | { |
c7653199 | 6397 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 6398 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 6399 | int refclk, num_connectors = 0; |
652c393a | 6400 | intel_clock_t clock, reduced_clock; |
a16af721 | 6401 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6402 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6403 | struct intel_encoder *encoder; |
d4906093 | 6404 | const intel_limit_t *limit; |
79e53945 | 6405 | |
d0737e1d ACO |
6406 | for_each_intel_encoder(dev, encoder) { |
6407 | if (encoder->new_crtc != crtc) | |
6408 | continue; | |
6409 | ||
5eddb70b | 6410 | switch (encoder->type) { |
79e53945 JB |
6411 | case INTEL_OUTPUT_LVDS: |
6412 | is_lvds = true; | |
6413 | break; | |
e9fd1c02 JN |
6414 | case INTEL_OUTPUT_DSI: |
6415 | is_dsi = true; | |
6416 | break; | |
6847d71b PZ |
6417 | default: |
6418 | break; | |
79e53945 | 6419 | } |
43565a06 | 6420 | |
c751ce4f | 6421 | num_connectors++; |
79e53945 JB |
6422 | } |
6423 | ||
f2335330 | 6424 | if (is_dsi) |
5b18e57c | 6425 | return 0; |
f2335330 | 6426 | |
d0737e1d | 6427 | if (!crtc->new_config->clock_set) { |
409ee761 | 6428 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 6429 | |
e9fd1c02 JN |
6430 | /* |
6431 | * Returns a set of divisors for the desired target clock with | |
6432 | * the given refclk, or FALSE. The returned values represent | |
6433 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6434 | * 2) / p1 / p2. | |
6435 | */ | |
409ee761 | 6436 | limit = intel_limit(crtc, refclk); |
c7653199 | 6437 | ok = dev_priv->display.find_dpll(limit, crtc, |
d0737e1d | 6438 | crtc->new_config->port_clock, |
e9fd1c02 | 6439 | refclk, NULL, &clock); |
f2335330 | 6440 | if (!ok) { |
e9fd1c02 JN |
6441 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6442 | return -EINVAL; | |
6443 | } | |
79e53945 | 6444 | |
f2335330 JN |
6445 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6446 | /* | |
6447 | * Ensure we match the reduced clock's P to the target | |
6448 | * clock. If the clocks don't match, we can't switch | |
6449 | * the display clock by using the FP0/FP1. In such case | |
6450 | * we will disable the LVDS downclock feature. | |
6451 | */ | |
6452 | has_reduced_clock = | |
c7653199 | 6453 | dev_priv->display.find_dpll(limit, crtc, |
f2335330 JN |
6454 | dev_priv->lvds_downclock, |
6455 | refclk, &clock, | |
6456 | &reduced_clock); | |
6457 | } | |
6458 | /* Compat-code for transition, will disappear. */ | |
d0737e1d ACO |
6459 | crtc->new_config->dpll.n = clock.n; |
6460 | crtc->new_config->dpll.m1 = clock.m1; | |
6461 | crtc->new_config->dpll.m2 = clock.m2; | |
6462 | crtc->new_config->dpll.p1 = clock.p1; | |
6463 | crtc->new_config->dpll.p2 = clock.p2; | |
f47709a9 | 6464 | } |
7026d4ac | 6465 | |
e9fd1c02 | 6466 | if (IS_GEN2(dev)) { |
c7653199 | 6467 | i8xx_update_pll(crtc, |
2a8f64ca VP |
6468 | has_reduced_clock ? &reduced_clock : NULL, |
6469 | num_connectors); | |
9d556c99 | 6470 | } else if (IS_CHERRYVIEW(dev)) { |
d0737e1d | 6471 | chv_update_pll(crtc, crtc->new_config); |
e9fd1c02 | 6472 | } else if (IS_VALLEYVIEW(dev)) { |
d0737e1d | 6473 | vlv_update_pll(crtc, crtc->new_config); |
e9fd1c02 | 6474 | } else { |
c7653199 | 6475 | i9xx_update_pll(crtc, |
eb1cbe48 | 6476 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6477 | num_connectors); |
e9fd1c02 | 6478 | } |
79e53945 | 6479 | |
c8f7a0db | 6480 | return 0; |
f564048e EA |
6481 | } |
6482 | ||
2fa2fe9a DV |
6483 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6484 | struct intel_crtc_config *pipe_config) | |
6485 | { | |
6486 | struct drm_device *dev = crtc->base.dev; | |
6487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6488 | uint32_t tmp; | |
6489 | ||
dc9e7dec VS |
6490 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6491 | return; | |
6492 | ||
2fa2fe9a | 6493 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6494 | if (!(tmp & PFIT_ENABLE)) |
6495 | return; | |
2fa2fe9a | 6496 | |
06922821 | 6497 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6498 | if (INTEL_INFO(dev)->gen < 4) { |
6499 | if (crtc->pipe != PIPE_B) | |
6500 | return; | |
2fa2fe9a DV |
6501 | } else { |
6502 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6503 | return; | |
6504 | } | |
6505 | ||
06922821 | 6506 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6507 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6508 | if (INTEL_INFO(dev)->gen < 5) | |
6509 | pipe_config->gmch_pfit.lvds_border_bits = | |
6510 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6511 | } | |
6512 | ||
acbec814 JB |
6513 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6514 | struct intel_crtc_config *pipe_config) | |
6515 | { | |
6516 | struct drm_device *dev = crtc->base.dev; | |
6517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6518 | int pipe = pipe_config->cpu_transcoder; | |
6519 | intel_clock_t clock; | |
6520 | u32 mdiv; | |
662c6ecb | 6521 | int refclk = 100000; |
acbec814 | 6522 | |
f573de5a SK |
6523 | /* In case of MIPI DPLL will not even be used */ |
6524 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
6525 | return; | |
6526 | ||
acbec814 | 6527 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 6528 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6529 | mutex_unlock(&dev_priv->dpio_lock); |
6530 | ||
6531 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6532 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6533 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6534 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6535 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6536 | ||
f646628b | 6537 | vlv_clock(refclk, &clock); |
acbec814 | 6538 | |
f646628b VS |
6539 | /* clock.dot is the fast clock */ |
6540 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6541 | } |
6542 | ||
1ad292b5 JB |
6543 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6544 | struct intel_plane_config *plane_config) | |
6545 | { | |
6546 | struct drm_device *dev = crtc->base.dev; | |
6547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6548 | u32 val, base, offset; | |
6549 | int pipe = crtc->pipe, plane = crtc->plane; | |
6550 | int fourcc, pixel_format; | |
6551 | int aligned_height; | |
6552 | ||
66e514c1 DA |
6553 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6554 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6555 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6556 | return; | |
6557 | } | |
6558 | ||
6559 | val = I915_READ(DSPCNTR(plane)); | |
6560 | ||
6561 | if (INTEL_INFO(dev)->gen >= 4) | |
6562 | if (val & DISPPLANE_TILED) | |
6563 | plane_config->tiled = true; | |
6564 | ||
6565 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6566 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6567 | crtc->base.primary->fb->pixel_format = fourcc; |
6568 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6569 | drm_format_plane_cpp(fourcc, 0) * 8; |
6570 | ||
6571 | if (INTEL_INFO(dev)->gen >= 4) { | |
6572 | if (plane_config->tiled) | |
6573 | offset = I915_READ(DSPTILEOFF(plane)); | |
6574 | else | |
6575 | offset = I915_READ(DSPLINOFF(plane)); | |
6576 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6577 | } else { | |
6578 | base = I915_READ(DSPADDR(plane)); | |
6579 | } | |
6580 | plane_config->base = base; | |
6581 | ||
6582 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6583 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6584 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6585 | |
6586 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 6587 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 6588 | |
66e514c1 | 6589 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6590 | plane_config->tiled); |
6591 | ||
1267a26b FF |
6592 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
6593 | aligned_height); | |
1ad292b5 JB |
6594 | |
6595 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6596 | pipe, plane, crtc->base.primary->fb->width, |
6597 | crtc->base.primary->fb->height, | |
6598 | crtc->base.primary->fb->bits_per_pixel, base, | |
6599 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6600 | plane_config->size); |
6601 | ||
6602 | } | |
6603 | ||
70b23a98 VS |
6604 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6605 | struct intel_crtc_config *pipe_config) | |
6606 | { | |
6607 | struct drm_device *dev = crtc->base.dev; | |
6608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6609 | int pipe = pipe_config->cpu_transcoder; | |
6610 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6611 | intel_clock_t clock; | |
6612 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6613 | int refclk = 100000; | |
6614 | ||
6615 | mutex_lock(&dev_priv->dpio_lock); | |
6616 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6617 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6618 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6619 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6620 | mutex_unlock(&dev_priv->dpio_lock); | |
6621 | ||
6622 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6623 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6624 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6625 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6626 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6627 | ||
6628 | chv_clock(refclk, &clock); | |
6629 | ||
6630 | /* clock.dot is the fast clock */ | |
6631 | pipe_config->port_clock = clock.dot / 5; | |
6632 | } | |
6633 | ||
0e8ffe1b DV |
6634 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6635 | struct intel_crtc_config *pipe_config) | |
6636 | { | |
6637 | struct drm_device *dev = crtc->base.dev; | |
6638 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6639 | uint32_t tmp; | |
6640 | ||
f458ebbc DV |
6641 | if (!intel_display_power_is_enabled(dev_priv, |
6642 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
6643 | return false; |
6644 | ||
e143a21c | 6645 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6646 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6647 | |
0e8ffe1b DV |
6648 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6649 | if (!(tmp & PIPECONF_ENABLE)) | |
6650 | return false; | |
6651 | ||
42571aef VS |
6652 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6653 | switch (tmp & PIPECONF_BPC_MASK) { | |
6654 | case PIPECONF_6BPC: | |
6655 | pipe_config->pipe_bpp = 18; | |
6656 | break; | |
6657 | case PIPECONF_8BPC: | |
6658 | pipe_config->pipe_bpp = 24; | |
6659 | break; | |
6660 | case PIPECONF_10BPC: | |
6661 | pipe_config->pipe_bpp = 30; | |
6662 | break; | |
6663 | default: | |
6664 | break; | |
6665 | } | |
6666 | } | |
6667 | ||
b5a9fa09 DV |
6668 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6669 | pipe_config->limited_color_range = true; | |
6670 | ||
282740f7 VS |
6671 | if (INTEL_INFO(dev)->gen < 4) |
6672 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6673 | ||
1bd1bd80 DV |
6674 | intel_get_pipe_timings(crtc, pipe_config); |
6675 | ||
2fa2fe9a DV |
6676 | i9xx_get_pfit_config(crtc, pipe_config); |
6677 | ||
6c49f241 DV |
6678 | if (INTEL_INFO(dev)->gen >= 4) { |
6679 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6680 | pipe_config->pixel_multiplier = | |
6681 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6682 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6683 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6684 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6685 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6686 | pipe_config->pixel_multiplier = | |
6687 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6688 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6689 | } else { | |
6690 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6691 | * port and will be fixed up in the encoder->get_config | |
6692 | * function. */ | |
6693 | pipe_config->pixel_multiplier = 1; | |
6694 | } | |
8bcc2795 DV |
6695 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6696 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
6697 | /* |
6698 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
6699 | * on 830. Filter it out here so that we don't | |
6700 | * report errors due to that. | |
6701 | */ | |
6702 | if (IS_I830(dev)) | |
6703 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
6704 | ||
8bcc2795 DV |
6705 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
6706 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6707 | } else { |
6708 | /* Mask out read-only status bits. */ | |
6709 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6710 | DPLL_PORTC_READY_MASK | | |
6711 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6712 | } |
6c49f241 | 6713 | |
70b23a98 VS |
6714 | if (IS_CHERRYVIEW(dev)) |
6715 | chv_crtc_clock_get(crtc, pipe_config); | |
6716 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6717 | vlv_crtc_clock_get(crtc, pipe_config); |
6718 | else | |
6719 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6720 | |
0e8ffe1b DV |
6721 | return true; |
6722 | } | |
6723 | ||
dde86e2d | 6724 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6725 | { |
6726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 6727 | struct intel_encoder *encoder; |
74cfd7ac | 6728 | u32 val, final; |
13d83a67 | 6729 | bool has_lvds = false; |
199e5d79 | 6730 | bool has_cpu_edp = false; |
199e5d79 | 6731 | bool has_panel = false; |
99eb6a01 KP |
6732 | bool has_ck505 = false; |
6733 | bool can_ssc = false; | |
13d83a67 JB |
6734 | |
6735 | /* We need to take the global config into account */ | |
b2784e15 | 6736 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
6737 | switch (encoder->type) { |
6738 | case INTEL_OUTPUT_LVDS: | |
6739 | has_panel = true; | |
6740 | has_lvds = true; | |
6741 | break; | |
6742 | case INTEL_OUTPUT_EDP: | |
6743 | has_panel = true; | |
2de6905f | 6744 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6745 | has_cpu_edp = true; |
6746 | break; | |
6847d71b PZ |
6747 | default: |
6748 | break; | |
13d83a67 JB |
6749 | } |
6750 | } | |
6751 | ||
99eb6a01 | 6752 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6753 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6754 | can_ssc = has_ck505; |
6755 | } else { | |
6756 | has_ck505 = false; | |
6757 | can_ssc = true; | |
6758 | } | |
6759 | ||
2de6905f ID |
6760 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6761 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6762 | |
6763 | /* Ironlake: try to setup display ref clock before DPLL | |
6764 | * enabling. This is only under driver's control after | |
6765 | * PCH B stepping, previous chipset stepping should be | |
6766 | * ignoring this setting. | |
6767 | */ | |
74cfd7ac CW |
6768 | val = I915_READ(PCH_DREF_CONTROL); |
6769 | ||
6770 | /* As we must carefully and slowly disable/enable each source in turn, | |
6771 | * compute the final state we want first and check if we need to | |
6772 | * make any changes at all. | |
6773 | */ | |
6774 | final = val; | |
6775 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6776 | if (has_ck505) | |
6777 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6778 | else | |
6779 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6780 | ||
6781 | final &= ~DREF_SSC_SOURCE_MASK; | |
6782 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6783 | final &= ~DREF_SSC1_ENABLE; | |
6784 | ||
6785 | if (has_panel) { | |
6786 | final |= DREF_SSC_SOURCE_ENABLE; | |
6787 | ||
6788 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6789 | final |= DREF_SSC1_ENABLE; | |
6790 | ||
6791 | if (has_cpu_edp) { | |
6792 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6793 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6794 | else | |
6795 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6796 | } else | |
6797 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6798 | } else { | |
6799 | final |= DREF_SSC_SOURCE_DISABLE; | |
6800 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6801 | } | |
6802 | ||
6803 | if (final == val) | |
6804 | return; | |
6805 | ||
13d83a67 | 6806 | /* Always enable nonspread source */ |
74cfd7ac | 6807 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6808 | |
99eb6a01 | 6809 | if (has_ck505) |
74cfd7ac | 6810 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6811 | else |
74cfd7ac | 6812 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6813 | |
199e5d79 | 6814 | if (has_panel) { |
74cfd7ac CW |
6815 | val &= ~DREF_SSC_SOURCE_MASK; |
6816 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6817 | |
199e5d79 | 6818 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6819 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6820 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6821 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6822 | } else |
74cfd7ac | 6823 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6824 | |
6825 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6826 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6827 | POSTING_READ(PCH_DREF_CONTROL); |
6828 | udelay(200); | |
6829 | ||
74cfd7ac | 6830 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6831 | |
6832 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6833 | if (has_cpu_edp) { |
99eb6a01 | 6834 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6835 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6836 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6837 | } else |
74cfd7ac | 6838 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6839 | } else |
74cfd7ac | 6840 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6841 | |
74cfd7ac | 6842 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6843 | POSTING_READ(PCH_DREF_CONTROL); |
6844 | udelay(200); | |
6845 | } else { | |
6846 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6847 | ||
74cfd7ac | 6848 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6849 | |
6850 | /* Turn off CPU output */ | |
74cfd7ac | 6851 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6852 | |
74cfd7ac | 6853 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6854 | POSTING_READ(PCH_DREF_CONTROL); |
6855 | udelay(200); | |
6856 | ||
6857 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6858 | val &= ~DREF_SSC_SOURCE_MASK; |
6859 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6860 | |
6861 | /* Turn off SSC1 */ | |
74cfd7ac | 6862 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6863 | |
74cfd7ac | 6864 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6865 | POSTING_READ(PCH_DREF_CONTROL); |
6866 | udelay(200); | |
6867 | } | |
74cfd7ac CW |
6868 | |
6869 | BUG_ON(val != final); | |
13d83a67 JB |
6870 | } |
6871 | ||
f31f2d55 | 6872 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6873 | { |
f31f2d55 | 6874 | uint32_t tmp; |
dde86e2d | 6875 | |
0ff066a9 PZ |
6876 | tmp = I915_READ(SOUTH_CHICKEN2); |
6877 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6878 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6879 | |
0ff066a9 PZ |
6880 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6881 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6882 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6883 | |
0ff066a9 PZ |
6884 | tmp = I915_READ(SOUTH_CHICKEN2); |
6885 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6886 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6887 | |
0ff066a9 PZ |
6888 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6889 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6890 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6891 | } |
6892 | ||
6893 | /* WaMPhyProgramming:hsw */ | |
6894 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6895 | { | |
6896 | uint32_t tmp; | |
dde86e2d PZ |
6897 | |
6898 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6899 | tmp &= ~(0xFF << 24); | |
6900 | tmp |= (0x12 << 24); | |
6901 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6902 | ||
dde86e2d PZ |
6903 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6904 | tmp |= (1 << 11); | |
6905 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6906 | ||
6907 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6908 | tmp |= (1 << 11); | |
6909 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6910 | ||
dde86e2d PZ |
6911 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6912 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6913 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6914 | ||
6915 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6916 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6917 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6918 | ||
0ff066a9 PZ |
6919 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6920 | tmp &= ~(7 << 13); | |
6921 | tmp |= (5 << 13); | |
6922 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6923 | |
0ff066a9 PZ |
6924 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6925 | tmp &= ~(7 << 13); | |
6926 | tmp |= (5 << 13); | |
6927 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6928 | |
6929 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6930 | tmp &= ~0xFF; | |
6931 | tmp |= 0x1C; | |
6932 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6933 | ||
6934 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6935 | tmp &= ~0xFF; | |
6936 | tmp |= 0x1C; | |
6937 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6938 | ||
6939 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6940 | tmp &= ~(0xFF << 16); | |
6941 | tmp |= (0x1C << 16); | |
6942 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6943 | ||
6944 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6945 | tmp &= ~(0xFF << 16); | |
6946 | tmp |= (0x1C << 16); | |
6947 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6948 | ||
0ff066a9 PZ |
6949 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6950 | tmp |= (1 << 27); | |
6951 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6952 | |
0ff066a9 PZ |
6953 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6954 | tmp |= (1 << 27); | |
6955 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6956 | |
0ff066a9 PZ |
6957 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6958 | tmp &= ~(0xF << 28); | |
6959 | tmp |= (4 << 28); | |
6960 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6961 | |
0ff066a9 PZ |
6962 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6963 | tmp &= ~(0xF << 28); | |
6964 | tmp |= (4 << 28); | |
6965 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6966 | } |
6967 | ||
2fa86a1f PZ |
6968 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6969 | * Programming" based on the parameters passed: | |
6970 | * - Sequence to enable CLKOUT_DP | |
6971 | * - Sequence to enable CLKOUT_DP without spread | |
6972 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6973 | */ | |
6974 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6975 | bool with_fdi) | |
f31f2d55 PZ |
6976 | { |
6977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6978 | uint32_t reg, tmp; |
6979 | ||
6980 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6981 | with_spread = true; | |
6982 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6983 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6984 | with_fdi = false; | |
f31f2d55 PZ |
6985 | |
6986 | mutex_lock(&dev_priv->dpio_lock); | |
6987 | ||
6988 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6989 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6990 | tmp |= SBI_SSCCTL_PATHALT; | |
6991 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6992 | ||
6993 | udelay(24); | |
6994 | ||
2fa86a1f PZ |
6995 | if (with_spread) { |
6996 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6997 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6998 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6999 | |
2fa86a1f PZ |
7000 | if (with_fdi) { |
7001 | lpt_reset_fdi_mphy(dev_priv); | |
7002 | lpt_program_fdi_mphy(dev_priv); | |
7003 | } | |
7004 | } | |
dde86e2d | 7005 | |
2fa86a1f PZ |
7006 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
7007 | SBI_GEN0 : SBI_DBUFF0; | |
7008 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7009 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7010 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
7011 | |
7012 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
7013 | } |
7014 | ||
47701c3b PZ |
7015 | /* Sequence to disable CLKOUT_DP */ |
7016 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
7017 | { | |
7018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7019 | uint32_t reg, tmp; | |
7020 | ||
7021 | mutex_lock(&dev_priv->dpio_lock); | |
7022 | ||
7023 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
7024 | SBI_GEN0 : SBI_DBUFF0; | |
7025 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7026 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7027 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7028 | ||
7029 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7030 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7031 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7032 | tmp |= SBI_SSCCTL_PATHALT; | |
7033 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7034 | udelay(32); | |
7035 | } | |
7036 | tmp |= SBI_SSCCTL_DISABLE; | |
7037 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7038 | } | |
7039 | ||
7040 | mutex_unlock(&dev_priv->dpio_lock); | |
7041 | } | |
7042 | ||
bf8fa3d3 PZ |
7043 | static void lpt_init_pch_refclk(struct drm_device *dev) |
7044 | { | |
bf8fa3d3 PZ |
7045 | struct intel_encoder *encoder; |
7046 | bool has_vga = false; | |
7047 | ||
b2784e15 | 7048 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
7049 | switch (encoder->type) { |
7050 | case INTEL_OUTPUT_ANALOG: | |
7051 | has_vga = true; | |
7052 | break; | |
6847d71b PZ |
7053 | default: |
7054 | break; | |
bf8fa3d3 PZ |
7055 | } |
7056 | } | |
7057 | ||
47701c3b PZ |
7058 | if (has_vga) |
7059 | lpt_enable_clkout_dp(dev, true, true); | |
7060 | else | |
7061 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
7062 | } |
7063 | ||
dde86e2d PZ |
7064 | /* |
7065 | * Initialize reference clocks when the driver loads | |
7066 | */ | |
7067 | void intel_init_pch_refclk(struct drm_device *dev) | |
7068 | { | |
7069 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7070 | ironlake_init_pch_refclk(dev); | |
7071 | else if (HAS_PCH_LPT(dev)) | |
7072 | lpt_init_pch_refclk(dev); | |
7073 | } | |
7074 | ||
d9d444cb JB |
7075 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
7076 | { | |
7077 | struct drm_device *dev = crtc->dev; | |
7078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7079 | struct intel_encoder *encoder; | |
d9d444cb JB |
7080 | int num_connectors = 0; |
7081 | bool is_lvds = false; | |
7082 | ||
d0737e1d ACO |
7083 | for_each_intel_encoder(dev, encoder) { |
7084 | if (encoder->new_crtc != to_intel_crtc(crtc)) | |
7085 | continue; | |
7086 | ||
d9d444cb JB |
7087 | switch (encoder->type) { |
7088 | case INTEL_OUTPUT_LVDS: | |
7089 | is_lvds = true; | |
7090 | break; | |
6847d71b PZ |
7091 | default: |
7092 | break; | |
d9d444cb JB |
7093 | } |
7094 | num_connectors++; | |
7095 | } | |
7096 | ||
7097 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 7098 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 7099 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 7100 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
7101 | } |
7102 | ||
7103 | return 120000; | |
7104 | } | |
7105 | ||
6ff93609 | 7106 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7107 | { |
c8203565 | 7108 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
7109 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7110 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7111 | uint32_t val; |
7112 | ||
78114071 | 7113 | val = 0; |
c8203565 | 7114 | |
965e0c48 | 7115 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 7116 | case 18: |
dfd07d72 | 7117 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7118 | break; |
7119 | case 24: | |
dfd07d72 | 7120 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7121 | break; |
7122 | case 30: | |
dfd07d72 | 7123 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7124 | break; |
7125 | case 36: | |
dfd07d72 | 7126 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7127 | break; |
7128 | default: | |
cc769b62 PZ |
7129 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7130 | BUG(); | |
c8203565 PZ |
7131 | } |
7132 | ||
d8b32247 | 7133 | if (intel_crtc->config.dither) |
c8203565 PZ |
7134 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7135 | ||
6ff93609 | 7136 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7137 | val |= PIPECONF_INTERLACED_ILK; |
7138 | else | |
7139 | val |= PIPECONF_PROGRESSIVE; | |
7140 | ||
50f3b016 | 7141 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 7142 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7143 | |
c8203565 PZ |
7144 | I915_WRITE(PIPECONF(pipe), val); |
7145 | POSTING_READ(PIPECONF(pipe)); | |
7146 | } | |
7147 | ||
86d3efce VS |
7148 | /* |
7149 | * Set up the pipe CSC unit. | |
7150 | * | |
7151 | * Currently only full range RGB to limited range RGB conversion | |
7152 | * is supported, but eventually this should handle various | |
7153 | * RGB<->YCbCr scenarios as well. | |
7154 | */ | |
50f3b016 | 7155 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
7156 | { |
7157 | struct drm_device *dev = crtc->dev; | |
7158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7159 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7160 | int pipe = intel_crtc->pipe; | |
7161 | uint16_t coeff = 0x7800; /* 1.0 */ | |
7162 | ||
7163 | /* | |
7164 | * TODO: Check what kind of values actually come out of the pipe | |
7165 | * with these coeff/postoff values and adjust to get the best | |
7166 | * accuracy. Perhaps we even need to take the bpc value into | |
7167 | * consideration. | |
7168 | */ | |
7169 | ||
50f3b016 | 7170 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
7171 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
7172 | ||
7173 | /* | |
7174 | * GY/GU and RY/RU should be the other way around according | |
7175 | * to BSpec, but reality doesn't agree. Just set them up in | |
7176 | * a way that results in the correct picture. | |
7177 | */ | |
7178 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
7179 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
7180 | ||
7181 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
7182 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
7183 | ||
7184 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
7185 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
7186 | ||
7187 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
7188 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
7189 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
7190 | ||
7191 | if (INTEL_INFO(dev)->gen > 6) { | |
7192 | uint16_t postoff = 0; | |
7193 | ||
50f3b016 | 7194 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 7195 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
7196 | |
7197 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
7198 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
7199 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
7200 | ||
7201 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
7202 | } else { | |
7203 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
7204 | ||
50f3b016 | 7205 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
7206 | mode |= CSC_BLACK_SCREEN_OFFSET; |
7207 | ||
7208 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
7209 | } | |
7210 | } | |
7211 | ||
6ff93609 | 7212 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7213 | { |
756f85cf PZ |
7214 | struct drm_device *dev = crtc->dev; |
7215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 7216 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 7217 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 7218 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
7219 | uint32_t val; |
7220 | ||
3eff4faa | 7221 | val = 0; |
ee2b0b38 | 7222 | |
756f85cf | 7223 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
7224 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7225 | ||
6ff93609 | 7226 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7227 | val |= PIPECONF_INTERLACED_ILK; |
7228 | else | |
7229 | val |= PIPECONF_PROGRESSIVE; | |
7230 | ||
702e7a56 PZ |
7231 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
7232 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
7233 | |
7234 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
7235 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 7236 | |
3cdf122c | 7237 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
7238 | val = 0; |
7239 | ||
7240 | switch (intel_crtc->config.pipe_bpp) { | |
7241 | case 18: | |
7242 | val |= PIPEMISC_DITHER_6_BPC; | |
7243 | break; | |
7244 | case 24: | |
7245 | val |= PIPEMISC_DITHER_8_BPC; | |
7246 | break; | |
7247 | case 30: | |
7248 | val |= PIPEMISC_DITHER_10_BPC; | |
7249 | break; | |
7250 | case 36: | |
7251 | val |= PIPEMISC_DITHER_12_BPC; | |
7252 | break; | |
7253 | default: | |
7254 | /* Case prevented by pipe_config_set_bpp. */ | |
7255 | BUG(); | |
7256 | } | |
7257 | ||
7258 | if (intel_crtc->config.dither) | |
7259 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
7260 | ||
7261 | I915_WRITE(PIPEMISC(pipe), val); | |
7262 | } | |
ee2b0b38 PZ |
7263 | } |
7264 | ||
6591c6e4 | 7265 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
7266 | intel_clock_t *clock, |
7267 | bool *has_reduced_clock, | |
7268 | intel_clock_t *reduced_clock) | |
7269 | { | |
7270 | struct drm_device *dev = crtc->dev; | |
7271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a919ff14 | 7272 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6591c6e4 | 7273 | int refclk; |
d4906093 | 7274 | const intel_limit_t *limit; |
a16af721 | 7275 | bool ret, is_lvds = false; |
79e53945 | 7276 | |
d0737e1d | 7277 | is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7278 | |
d9d444cb | 7279 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 7280 | |
d4906093 ML |
7281 | /* |
7282 | * Returns a set of divisors for the desired target clock with the given | |
7283 | * refclk, or FALSE. The returned values represent the clock equation: | |
7284 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
7285 | */ | |
409ee761 | 7286 | limit = intel_limit(intel_crtc, refclk); |
a919ff14 | 7287 | ret = dev_priv->display.find_dpll(limit, intel_crtc, |
d0737e1d | 7288 | intel_crtc->new_config->port_clock, |
ee9300bb | 7289 | refclk, NULL, clock); |
6591c6e4 PZ |
7290 | if (!ret) |
7291 | return false; | |
cda4b7d3 | 7292 | |
ddc9003c | 7293 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
7294 | /* |
7295 | * Ensure we match the reduced clock's P to the target clock. | |
7296 | * If the clocks don't match, we can't switch the display clock | |
7297 | * by using the FP0/FP1. In such case we will disable the LVDS | |
7298 | * downclock feature. | |
7299 | */ | |
ee9300bb | 7300 | *has_reduced_clock = |
a919ff14 | 7301 | dev_priv->display.find_dpll(limit, intel_crtc, |
ee9300bb DV |
7302 | dev_priv->lvds_downclock, |
7303 | refclk, clock, | |
7304 | reduced_clock); | |
652c393a | 7305 | } |
61e9653f | 7306 | |
6591c6e4 PZ |
7307 | return true; |
7308 | } | |
7309 | ||
d4b1931c PZ |
7310 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7311 | { | |
7312 | /* | |
7313 | * Account for spread spectrum to avoid | |
7314 | * oversubscribing the link. Max center spread | |
7315 | * is 2.5%; use 5% for safety's sake. | |
7316 | */ | |
7317 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7318 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7319 | } |
7320 | ||
7429e9d4 | 7321 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7322 | { |
7429e9d4 | 7323 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7324 | } |
7325 | ||
de13a2e3 | 7326 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 7327 | u32 *fp, |
9a7c7890 | 7328 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7329 | { |
de13a2e3 | 7330 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7331 | struct drm_device *dev = crtc->dev; |
7332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
7333 | struct intel_encoder *intel_encoder; |
7334 | uint32_t dpll; | |
6cc5f341 | 7335 | int factor, num_connectors = 0; |
09ede541 | 7336 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7337 | |
d0737e1d ACO |
7338 | for_each_intel_encoder(dev, intel_encoder) { |
7339 | if (intel_encoder->new_crtc != to_intel_crtc(crtc)) | |
7340 | continue; | |
7341 | ||
de13a2e3 | 7342 | switch (intel_encoder->type) { |
79e53945 JB |
7343 | case INTEL_OUTPUT_LVDS: |
7344 | is_lvds = true; | |
7345 | break; | |
7346 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7347 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7348 | is_sdvo = true; |
79e53945 | 7349 | break; |
6847d71b PZ |
7350 | default: |
7351 | break; | |
79e53945 | 7352 | } |
43565a06 | 7353 | |
c751ce4f | 7354 | num_connectors++; |
79e53945 | 7355 | } |
79e53945 | 7356 | |
c1858123 | 7357 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7358 | factor = 21; |
7359 | if (is_lvds) { | |
7360 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7361 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7362 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7363 | factor = 25; |
d0737e1d | 7364 | } else if (intel_crtc->new_config->sdvo_tv_clock) |
8febb297 | 7365 | factor = 20; |
c1858123 | 7366 | |
d0737e1d | 7367 | if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor)) |
7d0ac5b7 | 7368 | *fp |= FP_CB_TUNE; |
2c07245f | 7369 | |
9a7c7890 DV |
7370 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7371 | *fp2 |= FP_CB_TUNE; | |
7372 | ||
5eddb70b | 7373 | dpll = 0; |
2c07245f | 7374 | |
a07d6787 EA |
7375 | if (is_lvds) |
7376 | dpll |= DPLLB_MODE_LVDS; | |
7377 | else | |
7378 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7379 | |
d0737e1d | 7380 | dpll |= (intel_crtc->new_config->pixel_multiplier - 1) |
ef1b460d | 7381 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
7382 | |
7383 | if (is_sdvo) | |
4a33e48d | 7384 | dpll |= DPLL_SDVO_HIGH_SPEED; |
d0737e1d | 7385 | if (intel_crtc->new_config->has_dp_encoder) |
4a33e48d | 7386 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7387 | |
a07d6787 | 7388 | /* compute bitmask from p1 value */ |
d0737e1d | 7389 | dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7390 | /* also FPA1 */ |
d0737e1d | 7391 | dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7392 | |
d0737e1d | 7393 | switch (intel_crtc->new_config->dpll.p2) { |
a07d6787 EA |
7394 | case 5: |
7395 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7396 | break; | |
7397 | case 7: | |
7398 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7399 | break; | |
7400 | case 10: | |
7401 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7402 | break; | |
7403 | case 14: | |
7404 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7405 | break; | |
79e53945 JB |
7406 | } |
7407 | ||
b4c09f3b | 7408 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7409 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7410 | else |
7411 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7412 | ||
959e16d6 | 7413 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7414 | } |
7415 | ||
3fb37703 | 7416 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc) |
de13a2e3 | 7417 | { |
c7653199 | 7418 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 7419 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 7420 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7421 | bool ok, has_reduced_clock = false; |
8b47047b | 7422 | bool is_lvds = false; |
e2b78267 | 7423 | struct intel_shared_dpll *pll; |
de13a2e3 | 7424 | |
409ee761 | 7425 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7426 | |
5dc5298b PZ |
7427 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7428 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7429 | |
c7653199 | 7430 | ok = ironlake_compute_clocks(&crtc->base, &clock, |
de13a2e3 | 7431 | &has_reduced_clock, &reduced_clock); |
d0737e1d | 7432 | if (!ok && !crtc->new_config->clock_set) { |
de13a2e3 PZ |
7433 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7434 | return -EINVAL; | |
79e53945 | 7435 | } |
f47709a9 | 7436 | /* Compat-code for transition, will disappear. */ |
d0737e1d ACO |
7437 | if (!crtc->new_config->clock_set) { |
7438 | crtc->new_config->dpll.n = clock.n; | |
7439 | crtc->new_config->dpll.m1 = clock.m1; | |
7440 | crtc->new_config->dpll.m2 = clock.m2; | |
7441 | crtc->new_config->dpll.p1 = clock.p1; | |
7442 | crtc->new_config->dpll.p2 = clock.p2; | |
f47709a9 | 7443 | } |
79e53945 | 7444 | |
5dc5298b | 7445 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
d0737e1d ACO |
7446 | if (crtc->new_config->has_pch_encoder) { |
7447 | fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); | |
cbbab5bd | 7448 | if (has_reduced_clock) |
7429e9d4 | 7449 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7450 | |
c7653199 | 7451 | dpll = ironlake_compute_dpll(crtc, |
cbbab5bd DV |
7452 | &fp, &reduced_clock, |
7453 | has_reduced_clock ? &fp2 : NULL); | |
7454 | ||
d0737e1d ACO |
7455 | crtc->new_config->dpll_hw_state.dpll = dpll; |
7456 | crtc->new_config->dpll_hw_state.fp0 = fp; | |
66e985c0 | 7457 | if (has_reduced_clock) |
d0737e1d | 7458 | crtc->new_config->dpll_hw_state.fp1 = fp2; |
66e985c0 | 7459 | else |
d0737e1d | 7460 | crtc->new_config->dpll_hw_state.fp1 = fp; |
66e985c0 | 7461 | |
c7653199 | 7462 | pll = intel_get_shared_dpll(crtc); |
ee7b9f93 | 7463 | if (pll == NULL) { |
84f44ce7 | 7464 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 7465 | pipe_name(crtc->pipe)); |
4b645f14 JB |
7466 | return -EINVAL; |
7467 | } | |
3fb37703 | 7468 | } |
79e53945 | 7469 | |
d330a953 | 7470 | if (is_lvds && has_reduced_clock && i915.powersave) |
c7653199 | 7471 | crtc->lowfreq_avail = true; |
bcd644e0 | 7472 | else |
c7653199 | 7473 | crtc->lowfreq_avail = false; |
e2b78267 | 7474 | |
c8f7a0db | 7475 | return 0; |
79e53945 JB |
7476 | } |
7477 | ||
eb14cb74 VS |
7478 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7479 | struct intel_link_m_n *m_n) | |
7480 | { | |
7481 | struct drm_device *dev = crtc->base.dev; | |
7482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7483 | enum pipe pipe = crtc->pipe; | |
7484 | ||
7485 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7486 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7487 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7488 | & ~TU_SIZE_MASK; | |
7489 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7490 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7491 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7492 | } | |
7493 | ||
7494 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7495 | enum transcoder transcoder, | |
b95af8be VK |
7496 | struct intel_link_m_n *m_n, |
7497 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
7498 | { |
7499 | struct drm_device *dev = crtc->base.dev; | |
7500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7501 | enum pipe pipe = crtc->pipe; |
72419203 | 7502 | |
eb14cb74 VS |
7503 | if (INTEL_INFO(dev)->gen >= 5) { |
7504 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7505 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7506 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7507 | & ~TU_SIZE_MASK; | |
7508 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7509 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7510 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
7511 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
7512 | * gen < 8) and if DRRS is supported (to make sure the | |
7513 | * registers are not unnecessarily read). | |
7514 | */ | |
7515 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
7516 | crtc->config.has_drrs) { | |
7517 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); | |
7518 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
7519 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
7520 | & ~TU_SIZE_MASK; | |
7521 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
7522 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
7523 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7524 | } | |
eb14cb74 VS |
7525 | } else { |
7526 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7527 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7528 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7529 | & ~TU_SIZE_MASK; | |
7530 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7531 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7532 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7533 | } | |
7534 | } | |
7535 | ||
7536 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7537 | struct intel_crtc_config *pipe_config) | |
7538 | { | |
7539 | if (crtc->config.has_pch_encoder) | |
7540 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7541 | else | |
7542 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
7543 | &pipe_config->dp_m_n, |
7544 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 7545 | } |
72419203 | 7546 | |
eb14cb74 VS |
7547 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7548 | struct intel_crtc_config *pipe_config) | |
7549 | { | |
7550 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 7551 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
7552 | } |
7553 | ||
bd2e244f JB |
7554 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
7555 | struct intel_crtc_config *pipe_config) | |
7556 | { | |
7557 | struct drm_device *dev = crtc->base.dev; | |
7558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7559 | uint32_t tmp; | |
7560 | ||
7561 | tmp = I915_READ(PS_CTL(crtc->pipe)); | |
7562 | ||
7563 | if (tmp & PS_ENABLE) { | |
7564 | pipe_config->pch_pfit.enabled = true; | |
7565 | pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); | |
7566 | pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); | |
7567 | } | |
7568 | } | |
7569 | ||
2fa2fe9a DV |
7570 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7571 | struct intel_crtc_config *pipe_config) | |
7572 | { | |
7573 | struct drm_device *dev = crtc->base.dev; | |
7574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7575 | uint32_t tmp; | |
7576 | ||
7577 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7578 | ||
7579 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7580 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7581 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7582 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7583 | |
7584 | /* We currently do not free assignements of panel fitters on | |
7585 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7586 | * differentiates them) so just WARN about this case for now. */ | |
7587 | if (IS_GEN7(dev)) { | |
7588 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7589 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7590 | } | |
2fa2fe9a | 7591 | } |
79e53945 JB |
7592 | } |
7593 | ||
4c6baa59 JB |
7594 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7595 | struct intel_plane_config *plane_config) | |
7596 | { | |
7597 | struct drm_device *dev = crtc->base.dev; | |
7598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7599 | u32 val, base, offset; | |
7600 | int pipe = crtc->pipe, plane = crtc->plane; | |
7601 | int fourcc, pixel_format; | |
7602 | int aligned_height; | |
7603 | ||
66e514c1 DA |
7604 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7605 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7606 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7607 | return; | |
7608 | } | |
7609 | ||
7610 | val = I915_READ(DSPCNTR(plane)); | |
7611 | ||
7612 | if (INTEL_INFO(dev)->gen >= 4) | |
7613 | if (val & DISPPLANE_TILED) | |
7614 | plane_config->tiled = true; | |
7615 | ||
7616 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7617 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7618 | crtc->base.primary->fb->pixel_format = fourcc; |
7619 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7620 | drm_format_plane_cpp(fourcc, 0) * 8; |
7621 | ||
7622 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7623 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7624 | offset = I915_READ(DSPOFFSET(plane)); | |
7625 | } else { | |
7626 | if (plane_config->tiled) | |
7627 | offset = I915_READ(DSPTILEOFF(plane)); | |
7628 | else | |
7629 | offset = I915_READ(DSPLINOFF(plane)); | |
7630 | } | |
7631 | plane_config->base = base; | |
7632 | ||
7633 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7634 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7635 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7636 | |
7637 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 7638 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 7639 | |
66e514c1 | 7640 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7641 | plane_config->tiled); |
7642 | ||
1267a26b FF |
7643 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
7644 | aligned_height); | |
4c6baa59 JB |
7645 | |
7646 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7647 | pipe, plane, crtc->base.primary->fb->width, |
7648 | crtc->base.primary->fb->height, | |
7649 | crtc->base.primary->fb->bits_per_pixel, base, | |
7650 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7651 | plane_config->size); |
7652 | } | |
7653 | ||
0e8ffe1b DV |
7654 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7655 | struct intel_crtc_config *pipe_config) | |
7656 | { | |
7657 | struct drm_device *dev = crtc->base.dev; | |
7658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7659 | uint32_t tmp; | |
7660 | ||
f458ebbc DV |
7661 | if (!intel_display_power_is_enabled(dev_priv, |
7662 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
7663 | return false; |
7664 | ||
e143a21c | 7665 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7666 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7667 | |
0e8ffe1b DV |
7668 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7669 | if (!(tmp & PIPECONF_ENABLE)) | |
7670 | return false; | |
7671 | ||
42571aef VS |
7672 | switch (tmp & PIPECONF_BPC_MASK) { |
7673 | case PIPECONF_6BPC: | |
7674 | pipe_config->pipe_bpp = 18; | |
7675 | break; | |
7676 | case PIPECONF_8BPC: | |
7677 | pipe_config->pipe_bpp = 24; | |
7678 | break; | |
7679 | case PIPECONF_10BPC: | |
7680 | pipe_config->pipe_bpp = 30; | |
7681 | break; | |
7682 | case PIPECONF_12BPC: | |
7683 | pipe_config->pipe_bpp = 36; | |
7684 | break; | |
7685 | default: | |
7686 | break; | |
7687 | } | |
7688 | ||
b5a9fa09 DV |
7689 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7690 | pipe_config->limited_color_range = true; | |
7691 | ||
ab9412ba | 7692 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7693 | struct intel_shared_dpll *pll; |
7694 | ||
88adfff1 DV |
7695 | pipe_config->has_pch_encoder = true; |
7696 | ||
627eb5a3 DV |
7697 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7698 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7699 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7700 | |
7701 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7702 | |
c0d43d62 | 7703 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7704 | pipe_config->shared_dpll = |
7705 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7706 | } else { |
7707 | tmp = I915_READ(PCH_DPLL_SEL); | |
7708 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7709 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7710 | else | |
7711 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7712 | } | |
66e985c0 DV |
7713 | |
7714 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7715 | ||
7716 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7717 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7718 | |
7719 | tmp = pipe_config->dpll_hw_state.dpll; | |
7720 | pipe_config->pixel_multiplier = | |
7721 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7722 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7723 | |
7724 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7725 | } else { |
7726 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7727 | } |
7728 | ||
1bd1bd80 DV |
7729 | intel_get_pipe_timings(crtc, pipe_config); |
7730 | ||
2fa2fe9a DV |
7731 | ironlake_get_pfit_config(crtc, pipe_config); |
7732 | ||
0e8ffe1b DV |
7733 | return true; |
7734 | } | |
7735 | ||
be256dc7 PZ |
7736 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7737 | { | |
7738 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 7739 | struct intel_crtc *crtc; |
be256dc7 | 7740 | |
d3fcc808 | 7741 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 7742 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7743 | pipe_name(crtc->pipe)); |
7744 | ||
e2c719b7 RC |
7745 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
7746 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
7747 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
7748 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
7749 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
7750 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 7751 | "CPU PWM1 enabled\n"); |
c5107b87 | 7752 | if (IS_HASWELL(dev)) |
e2c719b7 | 7753 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 7754 | "CPU PWM2 enabled\n"); |
e2c719b7 | 7755 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 7756 | "PCH PWM1 enabled\n"); |
e2c719b7 | 7757 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 7758 | "Utility pin enabled\n"); |
e2c719b7 | 7759 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 7760 | |
9926ada1 PZ |
7761 | /* |
7762 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7763 | * interrupts remain enabled. We used to check for that, but since it's | |
7764 | * gen-specific and since we only disable LCPLL after we fully disable | |
7765 | * the interrupts, the check below should be enough. | |
7766 | */ | |
e2c719b7 | 7767 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
7768 | } |
7769 | ||
9ccd5aeb PZ |
7770 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
7771 | { | |
7772 | struct drm_device *dev = dev_priv->dev; | |
7773 | ||
7774 | if (IS_HASWELL(dev)) | |
7775 | return I915_READ(D_COMP_HSW); | |
7776 | else | |
7777 | return I915_READ(D_COMP_BDW); | |
7778 | } | |
7779 | ||
3c4c9b81 PZ |
7780 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7781 | { | |
7782 | struct drm_device *dev = dev_priv->dev; | |
7783 | ||
7784 | if (IS_HASWELL(dev)) { | |
7785 | mutex_lock(&dev_priv->rps.hw_lock); | |
7786 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7787 | val)) | |
f475dadf | 7788 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
7789 | mutex_unlock(&dev_priv->rps.hw_lock); |
7790 | } else { | |
9ccd5aeb PZ |
7791 | I915_WRITE(D_COMP_BDW, val); |
7792 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 7793 | } |
be256dc7 PZ |
7794 | } |
7795 | ||
7796 | /* | |
7797 | * This function implements pieces of two sequences from BSpec: | |
7798 | * - Sequence for display software to disable LCPLL | |
7799 | * - Sequence for display software to allow package C8+ | |
7800 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7801 | * register. Callers should take care of disabling all the display engine | |
7802 | * functions, doing the mode unset, fixing interrupts, etc. | |
7803 | */ | |
6ff58d53 PZ |
7804 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7805 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7806 | { |
7807 | uint32_t val; | |
7808 | ||
7809 | assert_can_disable_lcpll(dev_priv); | |
7810 | ||
7811 | val = I915_READ(LCPLL_CTL); | |
7812 | ||
7813 | if (switch_to_fclk) { | |
7814 | val |= LCPLL_CD_SOURCE_FCLK; | |
7815 | I915_WRITE(LCPLL_CTL, val); | |
7816 | ||
7817 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7818 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7819 | DRM_ERROR("Switching to FCLK failed\n"); | |
7820 | ||
7821 | val = I915_READ(LCPLL_CTL); | |
7822 | } | |
7823 | ||
7824 | val |= LCPLL_PLL_DISABLE; | |
7825 | I915_WRITE(LCPLL_CTL, val); | |
7826 | POSTING_READ(LCPLL_CTL); | |
7827 | ||
7828 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7829 | DRM_ERROR("LCPLL still locked\n"); | |
7830 | ||
9ccd5aeb | 7831 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 7832 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 7833 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7834 | ndelay(100); |
7835 | ||
9ccd5aeb PZ |
7836 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
7837 | 1)) | |
be256dc7 PZ |
7838 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
7839 | ||
7840 | if (allow_power_down) { | |
7841 | val = I915_READ(LCPLL_CTL); | |
7842 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7843 | I915_WRITE(LCPLL_CTL, val); | |
7844 | POSTING_READ(LCPLL_CTL); | |
7845 | } | |
7846 | } | |
7847 | ||
7848 | /* | |
7849 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7850 | * source. | |
7851 | */ | |
6ff58d53 | 7852 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7853 | { |
7854 | uint32_t val; | |
7855 | ||
7856 | val = I915_READ(LCPLL_CTL); | |
7857 | ||
7858 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7859 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7860 | return; | |
7861 | ||
a8a8bd54 PZ |
7862 | /* |
7863 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7864 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7865 | * | |
7866 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7867 | * the runtime PM resume sequence, so we can't just call | |
7868 | * gen6_gt_force_wake_get() because that function calls | |
7869 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7870 | * while we are on the resume sequence. So to solve this problem we have | |
7871 | * to call special forcewake code that doesn't touch runtime PM and | |
7872 | * doesn't enable the forcewake delayed work. | |
7873 | */ | |
d2e40e27 | 7874 | spin_lock_irq(&dev_priv->uncore.lock); |
a8a8bd54 PZ |
7875 | if (dev_priv->uncore.forcewake_count++ == 0) |
7876 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
d2e40e27 | 7877 | spin_unlock_irq(&dev_priv->uncore.lock); |
215733fa | 7878 | |
be256dc7 PZ |
7879 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7880 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7881 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7882 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7883 | } |
7884 | ||
9ccd5aeb | 7885 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
7886 | val |= D_COMP_COMP_FORCE; |
7887 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7888 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7889 | |
7890 | val = I915_READ(LCPLL_CTL); | |
7891 | val &= ~LCPLL_PLL_DISABLE; | |
7892 | I915_WRITE(LCPLL_CTL, val); | |
7893 | ||
7894 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7895 | DRM_ERROR("LCPLL not locked yet\n"); | |
7896 | ||
7897 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7898 | val = I915_READ(LCPLL_CTL); | |
7899 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7900 | I915_WRITE(LCPLL_CTL, val); | |
7901 | ||
7902 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7903 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7904 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7905 | } | |
215733fa | 7906 | |
a8a8bd54 | 7907 | /* See the big comment above. */ |
d2e40e27 | 7908 | spin_lock_irq(&dev_priv->uncore.lock); |
a8a8bd54 PZ |
7909 | if (--dev_priv->uncore.forcewake_count == 0) |
7910 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
d2e40e27 | 7911 | spin_unlock_irq(&dev_priv->uncore.lock); |
be256dc7 PZ |
7912 | } |
7913 | ||
765dab67 PZ |
7914 | /* |
7915 | * Package states C8 and deeper are really deep PC states that can only be | |
7916 | * reached when all the devices on the system allow it, so even if the graphics | |
7917 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7918 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7919 | * | |
7920 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7921 | * well is disabled and most interrupts are disabled, and these are also | |
7922 | * requirements for runtime PM. When these conditions are met, we manually do | |
7923 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7924 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7925 | * hang the machine. | |
7926 | * | |
7927 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7928 | * the state of some registers, so when we come back from PC8+ we need to | |
7929 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7930 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7931 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7932 | * because of the runtime PM support). | |
7933 | * | |
7934 | * For more, read "Display Sequences for Package C8" on the hardware | |
7935 | * documentation. | |
7936 | */ | |
a14cb6fc | 7937 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7938 | { |
c67a470b PZ |
7939 | struct drm_device *dev = dev_priv->dev; |
7940 | uint32_t val; | |
7941 | ||
c67a470b PZ |
7942 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7943 | ||
c67a470b PZ |
7944 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7945 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7946 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7947 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7948 | } | |
7949 | ||
7950 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7951 | hsw_disable_lcpll(dev_priv, true, true); |
7952 | } | |
7953 | ||
a14cb6fc | 7954 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7955 | { |
7956 | struct drm_device *dev = dev_priv->dev; | |
7957 | uint32_t val; | |
7958 | ||
c67a470b PZ |
7959 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7960 | ||
7961 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7962 | lpt_init_pch_refclk(dev); |
7963 | ||
7964 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7965 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7966 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7967 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7968 | } | |
7969 | ||
7970 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7971 | } |
7972 | ||
797d0259 | 7973 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc) |
09b4ddf9 | 7974 | { |
c7653199 | 7975 | if (!intel_ddi_pll_select(crtc)) |
6441ab5f | 7976 | return -EINVAL; |
716c2e55 | 7977 | |
c7653199 | 7978 | crtc->lowfreq_avail = false; |
644cef34 | 7979 | |
c8f7a0db | 7980 | return 0; |
79e53945 JB |
7981 | } |
7982 | ||
96b7dfb7 S |
7983 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
7984 | enum port port, | |
7985 | struct intel_crtc_config *pipe_config) | |
7986 | { | |
3148ade7 | 7987 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
7988 | |
7989 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
7990 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
7991 | ||
7992 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
7993 | case SKL_DPLL0: |
7994 | /* | |
7995 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
7996 | * of the shared DPLL framework and thus needs to be read out | |
7997 | * separately | |
7998 | */ | |
7999 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
8000 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
8001 | break; | |
96b7dfb7 S |
8002 | case SKL_DPLL1: |
8003 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
8004 | break; | |
8005 | case SKL_DPLL2: | |
8006 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
8007 | break; | |
8008 | case SKL_DPLL3: | |
8009 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
8010 | break; | |
96b7dfb7 S |
8011 | } |
8012 | } | |
8013 | ||
7d2c8175 DL |
8014 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8015 | enum port port, | |
8016 | struct intel_crtc_config *pipe_config) | |
8017 | { | |
8018 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
8019 | ||
8020 | switch (pipe_config->ddi_pll_sel) { | |
8021 | case PORT_CLK_SEL_WRPLL1: | |
8022 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
8023 | break; | |
8024 | case PORT_CLK_SEL_WRPLL2: | |
8025 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
8026 | break; | |
8027 | } | |
8028 | } | |
8029 | ||
26804afd DV |
8030 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
8031 | struct intel_crtc_config *pipe_config) | |
8032 | { | |
8033 | struct drm_device *dev = crtc->base.dev; | |
8034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 8035 | struct intel_shared_dpll *pll; |
26804afd DV |
8036 | enum port port; |
8037 | uint32_t tmp; | |
8038 | ||
8039 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
8040 | ||
8041 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
8042 | ||
96b7dfb7 S |
8043 | if (IS_SKYLAKE(dev)) |
8044 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
8045 | else | |
8046 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 8047 | |
d452c5b6 DV |
8048 | if (pipe_config->shared_dpll >= 0) { |
8049 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8050 | ||
8051 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8052 | &pipe_config->dpll_hw_state)); | |
8053 | } | |
8054 | ||
26804afd DV |
8055 | /* |
8056 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
8057 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
8058 | * the PCH transcoder is on. | |
8059 | */ | |
ca370455 DL |
8060 | if (INTEL_INFO(dev)->gen < 9 && |
8061 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
8062 | pipe_config->has_pch_encoder = true; |
8063 | ||
8064 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
8065 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8066 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
8067 | ||
8068 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
8069 | } | |
8070 | } | |
8071 | ||
0e8ffe1b DV |
8072 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
8073 | struct intel_crtc_config *pipe_config) | |
8074 | { | |
8075 | struct drm_device *dev = crtc->base.dev; | |
8076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 8077 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
8078 | uint32_t tmp; |
8079 | ||
f458ebbc | 8080 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
8081 | POWER_DOMAIN_PIPE(crtc->pipe))) |
8082 | return false; | |
8083 | ||
e143a21c | 8084 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
8085 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8086 | ||
eccb140b DV |
8087 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8088 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8089 | enum pipe trans_edp_pipe; | |
8090 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8091 | default: | |
8092 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8093 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8094 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8095 | trans_edp_pipe = PIPE_A; | |
8096 | break; | |
8097 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8098 | trans_edp_pipe = PIPE_B; | |
8099 | break; | |
8100 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8101 | trans_edp_pipe = PIPE_C; | |
8102 | break; | |
8103 | } | |
8104 | ||
8105 | if (trans_edp_pipe == crtc->pipe) | |
8106 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8107 | } | |
8108 | ||
f458ebbc | 8109 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 8110 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
8111 | return false; |
8112 | ||
eccb140b | 8113 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
8114 | if (!(tmp & PIPECONF_ENABLE)) |
8115 | return false; | |
8116 | ||
26804afd | 8117 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 8118 | |
1bd1bd80 DV |
8119 | intel_get_pipe_timings(crtc, pipe_config); |
8120 | ||
2fa2fe9a | 8121 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f JB |
8122 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
8123 | if (IS_SKYLAKE(dev)) | |
8124 | skylake_get_pfit_config(crtc, pipe_config); | |
8125 | else | |
8126 | ironlake_get_pfit_config(crtc, pipe_config); | |
8127 | } | |
88adfff1 | 8128 | |
e59150dc JB |
8129 | if (IS_HASWELL(dev)) |
8130 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
8131 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 8132 | |
ebb69c95 CT |
8133 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
8134 | pipe_config->pixel_multiplier = | |
8135 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
8136 | } else { | |
8137 | pipe_config->pixel_multiplier = 1; | |
8138 | } | |
6c49f241 | 8139 | |
0e8ffe1b DV |
8140 | return true; |
8141 | } | |
8142 | ||
560b85bb CW |
8143 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8144 | { | |
8145 | struct drm_device *dev = crtc->dev; | |
8146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8148 | uint32_t cntl = 0, size = 0; |
560b85bb | 8149 | |
dc41c154 VS |
8150 | if (base) { |
8151 | unsigned int width = intel_crtc->cursor_width; | |
8152 | unsigned int height = intel_crtc->cursor_height; | |
8153 | unsigned int stride = roundup_pow_of_two(width) * 4; | |
8154 | ||
8155 | switch (stride) { | |
8156 | default: | |
8157 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8158 | width, stride); | |
8159 | stride = 256; | |
8160 | /* fallthrough */ | |
8161 | case 256: | |
8162 | case 512: | |
8163 | case 1024: | |
8164 | case 2048: | |
8165 | break; | |
4b0e333e CW |
8166 | } |
8167 | ||
dc41c154 VS |
8168 | cntl |= CURSOR_ENABLE | |
8169 | CURSOR_GAMMA_ENABLE | | |
8170 | CURSOR_FORMAT_ARGB | | |
8171 | CURSOR_STRIDE(stride); | |
8172 | ||
8173 | size = (height << 12) | width; | |
4b0e333e | 8174 | } |
560b85bb | 8175 | |
dc41c154 VS |
8176 | if (intel_crtc->cursor_cntl != 0 && |
8177 | (intel_crtc->cursor_base != base || | |
8178 | intel_crtc->cursor_size != size || | |
8179 | intel_crtc->cursor_cntl != cntl)) { | |
8180 | /* On these chipsets we can only modify the base/size/stride | |
8181 | * whilst the cursor is disabled. | |
8182 | */ | |
8183 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8184 | POSTING_READ(_CURACNTR); |
dc41c154 | 8185 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8186 | } |
560b85bb | 8187 | |
99d1f387 | 8188 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 8189 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
8190 | intel_crtc->cursor_base = base; |
8191 | } | |
4726e0b0 | 8192 | |
dc41c154 VS |
8193 | if (intel_crtc->cursor_size != size) { |
8194 | I915_WRITE(CURSIZE, size); | |
8195 | intel_crtc->cursor_size = size; | |
4b0e333e | 8196 | } |
560b85bb | 8197 | |
4b0e333e | 8198 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8199 | I915_WRITE(_CURACNTR, cntl); |
8200 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8201 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8202 | } |
560b85bb CW |
8203 | } |
8204 | ||
560b85bb | 8205 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8206 | { |
8207 | struct drm_device *dev = crtc->dev; | |
8208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8210 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8211 | uint32_t cntl; |
8212 | ||
8213 | cntl = 0; | |
8214 | if (base) { | |
8215 | cntl = MCURSOR_GAMMA_ENABLE; | |
8216 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8217 | case 64: |
8218 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8219 | break; | |
8220 | case 128: | |
8221 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8222 | break; | |
8223 | case 256: | |
8224 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8225 | break; | |
8226 | default: | |
5f77eeb0 | 8227 | MISSING_CASE(intel_crtc->cursor_width); |
4726e0b0 | 8228 | return; |
65a21cd6 | 8229 | } |
4b0e333e | 8230 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
8231 | |
8232 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8233 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 8234 | } |
65a21cd6 | 8235 | |
4398ad45 VS |
8236 | if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) |
8237 | cntl |= CURSOR_ROTATE_180; | |
8238 | ||
4b0e333e CW |
8239 | if (intel_crtc->cursor_cntl != cntl) { |
8240 | I915_WRITE(CURCNTR(pipe), cntl); | |
8241 | POSTING_READ(CURCNTR(pipe)); | |
8242 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8243 | } |
4b0e333e | 8244 | |
65a21cd6 | 8245 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8246 | I915_WRITE(CURBASE(pipe), base); |
8247 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
8248 | |
8249 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
8250 | } |
8251 | ||
cda4b7d3 | 8252 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8253 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8254 | bool on) | |
cda4b7d3 CW |
8255 | { |
8256 | struct drm_device *dev = crtc->dev; | |
8257 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8258 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8259 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8260 | int x = crtc->cursor_x; |
8261 | int y = crtc->cursor_y; | |
d6e4db15 | 8262 | u32 base = 0, pos = 0; |
cda4b7d3 | 8263 | |
d6e4db15 | 8264 | if (on) |
cda4b7d3 | 8265 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8266 | |
d6e4db15 VS |
8267 | if (x >= intel_crtc->config.pipe_src_w) |
8268 | base = 0; | |
8269 | ||
8270 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8271 | base = 0; |
8272 | ||
8273 | if (x < 0) { | |
efc9064e | 8274 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8275 | base = 0; |
8276 | ||
8277 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8278 | x = -x; | |
8279 | } | |
8280 | pos |= x << CURSOR_X_SHIFT; | |
8281 | ||
8282 | if (y < 0) { | |
efc9064e | 8283 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8284 | base = 0; |
8285 | ||
8286 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8287 | y = -y; | |
8288 | } | |
8289 | pos |= y << CURSOR_Y_SHIFT; | |
8290 | ||
4b0e333e | 8291 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8292 | return; |
8293 | ||
5efb3e28 VS |
8294 | I915_WRITE(CURPOS(pipe), pos); |
8295 | ||
4398ad45 VS |
8296 | /* ILK+ do this automagically */ |
8297 | if (HAS_GMCH_DISPLAY(dev) && | |
8298 | to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) { | |
8299 | base += (intel_crtc->cursor_height * | |
8300 | intel_crtc->cursor_width - 1) * 4; | |
8301 | } | |
8302 | ||
8ac54669 | 8303 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8304 | i845_update_cursor(crtc, base); |
8305 | else | |
8306 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8307 | } |
8308 | ||
dc41c154 VS |
8309 | static bool cursor_size_ok(struct drm_device *dev, |
8310 | uint32_t width, uint32_t height) | |
8311 | { | |
8312 | if (width == 0 || height == 0) | |
8313 | return false; | |
8314 | ||
8315 | /* | |
8316 | * 845g/865g are special in that they are only limited by | |
8317 | * the width of their cursors, the height is arbitrary up to | |
8318 | * the precision of the register. Everything else requires | |
8319 | * square cursors, limited to a few power-of-two sizes. | |
8320 | */ | |
8321 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8322 | if ((width & 63) != 0) | |
8323 | return false; | |
8324 | ||
8325 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8326 | return false; | |
8327 | ||
8328 | if (height > 1023) | |
8329 | return false; | |
8330 | } else { | |
8331 | switch (width | height) { | |
8332 | case 256: | |
8333 | case 128: | |
8334 | if (IS_GEN2(dev)) | |
8335 | return false; | |
8336 | case 64: | |
8337 | break; | |
8338 | default: | |
8339 | return false; | |
8340 | } | |
8341 | } | |
8342 | ||
8343 | return true; | |
8344 | } | |
8345 | ||
79e53945 | 8346 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8347 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8348 | { |
7203425a | 8349 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8351 | |
7203425a | 8352 | for (i = start; i < end; i++) { |
79e53945 JB |
8353 | intel_crtc->lut_r[i] = red[i] >> 8; |
8354 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8355 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8356 | } | |
8357 | ||
8358 | intel_crtc_load_lut(crtc); | |
8359 | } | |
8360 | ||
79e53945 JB |
8361 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8362 | static struct drm_display_mode load_detect_mode = { | |
8363 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8364 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8365 | }; | |
8366 | ||
a8bb6818 DV |
8367 | struct drm_framebuffer * |
8368 | __intel_framebuffer_create(struct drm_device *dev, | |
8369 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8370 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8371 | { |
8372 | struct intel_framebuffer *intel_fb; | |
8373 | int ret; | |
8374 | ||
8375 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8376 | if (!intel_fb) { | |
6ccb81f2 | 8377 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
8378 | return ERR_PTR(-ENOMEM); |
8379 | } | |
8380 | ||
8381 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8382 | if (ret) |
8383 | goto err; | |
d2dff872 CW |
8384 | |
8385 | return &intel_fb->base; | |
dd4916c5 | 8386 | err: |
6ccb81f2 | 8387 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
8388 | kfree(intel_fb); |
8389 | ||
8390 | return ERR_PTR(ret); | |
d2dff872 CW |
8391 | } |
8392 | ||
b5ea642a | 8393 | static struct drm_framebuffer * |
a8bb6818 DV |
8394 | intel_framebuffer_create(struct drm_device *dev, |
8395 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8396 | struct drm_i915_gem_object *obj) | |
8397 | { | |
8398 | struct drm_framebuffer *fb; | |
8399 | int ret; | |
8400 | ||
8401 | ret = i915_mutex_lock_interruptible(dev); | |
8402 | if (ret) | |
8403 | return ERR_PTR(ret); | |
8404 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8405 | mutex_unlock(&dev->struct_mutex); | |
8406 | ||
8407 | return fb; | |
8408 | } | |
8409 | ||
d2dff872 CW |
8410 | static u32 |
8411 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8412 | { | |
8413 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8414 | return ALIGN(pitch, 64); | |
8415 | } | |
8416 | ||
8417 | static u32 | |
8418 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8419 | { | |
8420 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8421 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8422 | } |
8423 | ||
8424 | static struct drm_framebuffer * | |
8425 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8426 | struct drm_display_mode *mode, | |
8427 | int depth, int bpp) | |
8428 | { | |
8429 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8430 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8431 | |
8432 | obj = i915_gem_alloc_object(dev, | |
8433 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8434 | if (obj == NULL) | |
8435 | return ERR_PTR(-ENOMEM); | |
8436 | ||
8437 | mode_cmd.width = mode->hdisplay; | |
8438 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8439 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8440 | bpp); | |
5ca0c34a | 8441 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8442 | |
8443 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8444 | } | |
8445 | ||
8446 | static struct drm_framebuffer * | |
8447 | mode_fits_in_fbdev(struct drm_device *dev, | |
8448 | struct drm_display_mode *mode) | |
8449 | { | |
4520f53a | 8450 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8451 | struct drm_i915_private *dev_priv = dev->dev_private; |
8452 | struct drm_i915_gem_object *obj; | |
8453 | struct drm_framebuffer *fb; | |
8454 | ||
4c0e5528 | 8455 | if (!dev_priv->fbdev) |
d2dff872 CW |
8456 | return NULL; |
8457 | ||
4c0e5528 | 8458 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8459 | return NULL; |
8460 | ||
4c0e5528 DV |
8461 | obj = dev_priv->fbdev->fb->obj; |
8462 | BUG_ON(!obj); | |
8463 | ||
8bcd4553 | 8464 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8465 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8466 | fb->bits_per_pixel)) | |
d2dff872 CW |
8467 | return NULL; |
8468 | ||
01f2c773 | 8469 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8470 | return NULL; |
8471 | ||
8472 | return fb; | |
4520f53a DV |
8473 | #else |
8474 | return NULL; | |
8475 | #endif | |
d2dff872 CW |
8476 | } |
8477 | ||
d2434ab7 | 8478 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8479 | struct drm_display_mode *mode, |
51fd371b RC |
8480 | struct intel_load_detect_pipe *old, |
8481 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8482 | { |
8483 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8484 | struct intel_encoder *intel_encoder = |
8485 | intel_attached_encoder(connector); | |
79e53945 | 8486 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8487 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8488 | struct drm_crtc *crtc = NULL; |
8489 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8490 | struct drm_framebuffer *fb; |
51fd371b RC |
8491 | struct drm_mode_config *config = &dev->mode_config; |
8492 | int ret, i = -1; | |
79e53945 | 8493 | |
d2dff872 | 8494 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8495 | connector->base.id, connector->name, |
8e329a03 | 8496 | encoder->base.id, encoder->name); |
d2dff872 | 8497 | |
51fd371b RC |
8498 | retry: |
8499 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8500 | if (ret) | |
8501 | goto fail_unlock; | |
6e9f798d | 8502 | |
79e53945 JB |
8503 | /* |
8504 | * Algorithm gets a little messy: | |
7a5e4805 | 8505 | * |
79e53945 JB |
8506 | * - if the connector already has an assigned crtc, use it (but make |
8507 | * sure it's on first) | |
7a5e4805 | 8508 | * |
79e53945 JB |
8509 | * - try to find the first unused crtc that can drive this connector, |
8510 | * and use that if we find one | |
79e53945 JB |
8511 | */ |
8512 | ||
8513 | /* See if we already have a CRTC for this connector */ | |
8514 | if (encoder->crtc) { | |
8515 | crtc = encoder->crtc; | |
8261b191 | 8516 | |
51fd371b | 8517 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
8518 | if (ret) |
8519 | goto fail_unlock; | |
8520 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
8521 | if (ret) |
8522 | goto fail_unlock; | |
7b24056b | 8523 | |
24218aac | 8524 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8525 | old->load_detect_temp = false; |
8526 | ||
8527 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8528 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8529 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8530 | |
7173188d | 8531 | return true; |
79e53945 JB |
8532 | } |
8533 | ||
8534 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8535 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8536 | i++; |
8537 | if (!(encoder->possible_crtcs & (1 << i))) | |
8538 | continue; | |
a459249c VS |
8539 | if (possible_crtc->enabled) |
8540 | continue; | |
8541 | /* This can occur when applying the pipe A quirk on resume. */ | |
8542 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
8543 | continue; | |
8544 | ||
8545 | crtc = possible_crtc; | |
8546 | break; | |
79e53945 JB |
8547 | } |
8548 | ||
8549 | /* | |
8550 | * If we didn't find an unused CRTC, don't use any. | |
8551 | */ | |
8552 | if (!crtc) { | |
7173188d | 8553 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8554 | goto fail_unlock; |
79e53945 JB |
8555 | } |
8556 | ||
51fd371b RC |
8557 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8558 | if (ret) | |
4d02e2de DV |
8559 | goto fail_unlock; |
8560 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
8561 | if (ret) | |
51fd371b | 8562 | goto fail_unlock; |
fc303101 DV |
8563 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8564 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8565 | |
8566 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8567 | intel_crtc->new_enabled = true; |
8568 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8569 | old->dpms_mode = connector->dpms; |
8261b191 | 8570 | old->load_detect_temp = true; |
d2dff872 | 8571 | old->release_fb = NULL; |
79e53945 | 8572 | |
6492711d CW |
8573 | if (!mode) |
8574 | mode = &load_detect_mode; | |
79e53945 | 8575 | |
d2dff872 CW |
8576 | /* We need a framebuffer large enough to accommodate all accesses |
8577 | * that the plane may generate whilst we perform load detection. | |
8578 | * We can not rely on the fbcon either being present (we get called | |
8579 | * during its initialisation to detect all boot displays, or it may | |
8580 | * not even exist) or that it is large enough to satisfy the | |
8581 | * requested mode. | |
8582 | */ | |
94352cf9 DV |
8583 | fb = mode_fits_in_fbdev(dev, mode); |
8584 | if (fb == NULL) { | |
d2dff872 | 8585 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8586 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8587 | old->release_fb = fb; | |
d2dff872 CW |
8588 | } else |
8589 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8590 | if (IS_ERR(fb)) { |
d2dff872 | 8591 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8592 | goto fail; |
79e53945 | 8593 | } |
79e53945 | 8594 | |
c0c36b94 | 8595 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8596 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8597 | if (old->release_fb) |
8598 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8599 | goto fail; |
79e53945 | 8600 | } |
7173188d | 8601 | |
79e53945 | 8602 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8603 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8604 | return true; |
412b61d8 VS |
8605 | |
8606 | fail: | |
8607 | intel_crtc->new_enabled = crtc->enabled; | |
8608 | if (intel_crtc->new_enabled) | |
8609 | intel_crtc->new_config = &intel_crtc->config; | |
8610 | else | |
8611 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8612 | fail_unlock: |
8613 | if (ret == -EDEADLK) { | |
8614 | drm_modeset_backoff(ctx); | |
8615 | goto retry; | |
8616 | } | |
8617 | ||
412b61d8 | 8618 | return false; |
79e53945 JB |
8619 | } |
8620 | ||
d2434ab7 | 8621 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
208bf9fd | 8622 | struct intel_load_detect_pipe *old) |
79e53945 | 8623 | { |
d2434ab7 DV |
8624 | struct intel_encoder *intel_encoder = |
8625 | intel_attached_encoder(connector); | |
4ef69c7a | 8626 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8627 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8628 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8629 | |
d2dff872 | 8630 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8631 | connector->base.id, connector->name, |
8e329a03 | 8632 | encoder->base.id, encoder->name); |
d2dff872 | 8633 | |
8261b191 | 8634 | if (old->load_detect_temp) { |
fc303101 DV |
8635 | to_intel_connector(connector)->new_encoder = NULL; |
8636 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8637 | intel_crtc->new_enabled = false; |
8638 | intel_crtc->new_config = NULL; | |
fc303101 | 8639 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8640 | |
36206361 DV |
8641 | if (old->release_fb) { |
8642 | drm_framebuffer_unregister_private(old->release_fb); | |
8643 | drm_framebuffer_unreference(old->release_fb); | |
8644 | } | |
d2dff872 | 8645 | |
0622a53c | 8646 | return; |
79e53945 JB |
8647 | } |
8648 | ||
c751ce4f | 8649 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8650 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8651 | connector->funcs->dpms(connector, old->dpms_mode); | |
79e53945 JB |
8652 | } |
8653 | ||
da4a1efa VS |
8654 | static int i9xx_pll_refclk(struct drm_device *dev, |
8655 | const struct intel_crtc_config *pipe_config) | |
8656 | { | |
8657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8658 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8659 | ||
8660 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8661 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8662 | else if (HAS_PCH_SPLIT(dev)) |
8663 | return 120000; | |
8664 | else if (!IS_GEN2(dev)) | |
8665 | return 96000; | |
8666 | else | |
8667 | return 48000; | |
8668 | } | |
8669 | ||
79e53945 | 8670 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8671 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8672 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8673 | { |
f1f644dc | 8674 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8675 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8676 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8677 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8678 | u32 fp; |
8679 | intel_clock_t clock; | |
da4a1efa | 8680 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8681 | |
8682 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8683 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8684 | else |
293623f7 | 8685 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8686 | |
8687 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8688 | if (IS_PINEVIEW(dev)) { |
8689 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8690 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8691 | } else { |
8692 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8693 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8694 | } | |
8695 | ||
a6c45cf0 | 8696 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8697 | if (IS_PINEVIEW(dev)) |
8698 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8699 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8700 | else |
8701 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8702 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8703 | ||
8704 | switch (dpll & DPLL_MODE_MASK) { | |
8705 | case DPLLB_MODE_DAC_SERIAL: | |
8706 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8707 | 5 : 10; | |
8708 | break; | |
8709 | case DPLLB_MODE_LVDS: | |
8710 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8711 | 7 : 14; | |
8712 | break; | |
8713 | default: | |
28c97730 | 8714 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8715 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8716 | return; |
79e53945 JB |
8717 | } |
8718 | ||
ac58c3f0 | 8719 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8720 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8721 | else |
da4a1efa | 8722 | i9xx_clock(refclk, &clock); |
79e53945 | 8723 | } else { |
0fb58223 | 8724 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8725 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8726 | |
8727 | if (is_lvds) { | |
8728 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8729 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8730 | |
8731 | if (lvds & LVDS_CLKB_POWER_UP) | |
8732 | clock.p2 = 7; | |
8733 | else | |
8734 | clock.p2 = 14; | |
79e53945 JB |
8735 | } else { |
8736 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8737 | clock.p1 = 2; | |
8738 | else { | |
8739 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8740 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8741 | } | |
8742 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8743 | clock.p2 = 4; | |
8744 | else | |
8745 | clock.p2 = 2; | |
79e53945 | 8746 | } |
da4a1efa VS |
8747 | |
8748 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8749 | } |
8750 | ||
18442d08 VS |
8751 | /* |
8752 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8753 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8754 | * encoder's get_config() function. |
8755 | */ | |
8756 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8757 | } |
8758 | ||
6878da05 VS |
8759 | int intel_dotclock_calculate(int link_freq, |
8760 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8761 | { |
f1f644dc JB |
8762 | /* |
8763 | * The calculation for the data clock is: | |
1041a02f | 8764 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8765 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8766 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8767 | * |
8768 | * and the link clock is simpler: | |
1041a02f | 8769 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8770 | */ |
8771 | ||
6878da05 VS |
8772 | if (!m_n->link_n) |
8773 | return 0; | |
f1f644dc | 8774 | |
6878da05 VS |
8775 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8776 | } | |
f1f644dc | 8777 | |
18442d08 VS |
8778 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8779 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8780 | { |
8781 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8782 | |
18442d08 VS |
8783 | /* read out port_clock from the DPLL */ |
8784 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8785 | |
f1f644dc | 8786 | /* |
18442d08 | 8787 | * This value does not include pixel_multiplier. |
241bfc38 | 8788 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8789 | * agree once we know their relationship in the encoder's |
8790 | * get_config() function. | |
79e53945 | 8791 | */ |
241bfc38 | 8792 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8793 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8794 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8795 | } |
8796 | ||
8797 | /** Returns the currently programmed mode of the given pipe. */ | |
8798 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8799 | struct drm_crtc *crtc) | |
8800 | { | |
548f245b | 8801 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8803 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8804 | struct drm_display_mode *mode; |
f1f644dc | 8805 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8806 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8807 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8808 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8809 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8810 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8811 | |
8812 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8813 | if (!mode) | |
8814 | return NULL; | |
8815 | ||
f1f644dc JB |
8816 | /* |
8817 | * Construct a pipe_config sufficient for getting the clock info | |
8818 | * back out of crtc_clock_get. | |
8819 | * | |
8820 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8821 | * to use a real value here instead. | |
8822 | */ | |
293623f7 | 8823 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8824 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8825 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8826 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8827 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8828 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8829 | ||
773ae034 | 8830 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8831 | mode->hdisplay = (htot & 0xffff) + 1; |
8832 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8833 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8834 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8835 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8836 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8837 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8838 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8839 | ||
8840 | drm_mode_set_name(mode); | |
79e53945 JB |
8841 | |
8842 | return mode; | |
8843 | } | |
8844 | ||
652c393a JB |
8845 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
8846 | { | |
8847 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8848 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8849 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8850 | |
baff296c | 8851 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
8852 | return; |
8853 | ||
8854 | if (!dev_priv->lvds_downclock_avail) | |
8855 | return; | |
8856 | ||
8857 | /* | |
8858 | * Since this is called by a timer, we should never get here in | |
8859 | * the manual case. | |
8860 | */ | |
8861 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8862 | int pipe = intel_crtc->pipe; |
8863 | int dpll_reg = DPLL(pipe); | |
8864 | int dpll; | |
f6e5b160 | 8865 | |
44d98a61 | 8866 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8867 | |
8ac5a6d5 | 8868 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8869 | |
dc257cf1 | 8870 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8871 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8872 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8873 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8874 | dpll = I915_READ(dpll_reg); |
8875 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8876 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8877 | } |
8878 | ||
8879 | } | |
8880 | ||
f047e395 CW |
8881 | void intel_mark_busy(struct drm_device *dev) |
8882 | { | |
c67a470b PZ |
8883 | struct drm_i915_private *dev_priv = dev->dev_private; |
8884 | ||
f62a0076 CW |
8885 | if (dev_priv->mm.busy) |
8886 | return; | |
8887 | ||
43694d69 | 8888 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8889 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8890 | dev_priv->mm.busy = true; |
f047e395 CW |
8891 | } |
8892 | ||
8893 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8894 | { |
c67a470b | 8895 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8896 | struct drm_crtc *crtc; |
652c393a | 8897 | |
f62a0076 CW |
8898 | if (!dev_priv->mm.busy) |
8899 | return; | |
8900 | ||
8901 | dev_priv->mm.busy = false; | |
8902 | ||
d330a953 | 8903 | if (!i915.powersave) |
bb4cdd53 | 8904 | goto out; |
652c393a | 8905 | |
70e1e0ec | 8906 | for_each_crtc(dev, crtc) { |
f4510a27 | 8907 | if (!crtc->primary->fb) |
652c393a JB |
8908 | continue; |
8909 | ||
725a5b54 | 8910 | intel_decrease_pllclock(crtc); |
652c393a | 8911 | } |
b29c19b6 | 8912 | |
3d13ef2e | 8913 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8914 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8915 | |
8916 | out: | |
43694d69 | 8917 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
8918 | } |
8919 | ||
79e53945 JB |
8920 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8921 | { | |
8922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8923 | struct drm_device *dev = crtc->dev; |
8924 | struct intel_unpin_work *work; | |
67e77c5a | 8925 | |
5e2d7afc | 8926 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
8927 | work = intel_crtc->unpin_work; |
8928 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 8929 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
8930 | |
8931 | if (work) { | |
8932 | cancel_work_sync(&work->work); | |
8933 | kfree(work); | |
8934 | } | |
79e53945 JB |
8935 | |
8936 | drm_crtc_cleanup(crtc); | |
67e77c5a | 8937 | |
79e53945 JB |
8938 | kfree(intel_crtc); |
8939 | } | |
8940 | ||
6b95a207 KH |
8941 | static void intel_unpin_work_fn(struct work_struct *__work) |
8942 | { | |
8943 | struct intel_unpin_work *work = | |
8944 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8945 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 8946 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 8947 | |
b4a98e57 | 8948 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8949 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8950 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8951 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8952 | |
7ff0ebcc | 8953 | intel_fbc_update(dev); |
f06cc1b9 JH |
8954 | |
8955 | if (work->flip_queued_req) | |
146d84f0 | 8956 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
8957 | mutex_unlock(&dev->struct_mutex); |
8958 | ||
f99d7069 DV |
8959 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
8960 | ||
b4a98e57 CW |
8961 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
8962 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8963 | ||
6b95a207 KH |
8964 | kfree(work); |
8965 | } | |
8966 | ||
1afe3e9d | 8967 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8968 | struct drm_crtc *crtc) |
6b95a207 | 8969 | { |
6b95a207 KH |
8970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8971 | struct intel_unpin_work *work; | |
6b95a207 KH |
8972 | unsigned long flags; |
8973 | ||
8974 | /* Ignore early vblank irqs */ | |
8975 | if (intel_crtc == NULL) | |
8976 | return; | |
8977 | ||
f326038a DV |
8978 | /* |
8979 | * This is called both by irq handlers and the reset code (to complete | |
8980 | * lost pageflips) so needs the full irqsave spinlocks. | |
8981 | */ | |
6b95a207 KH |
8982 | spin_lock_irqsave(&dev->event_lock, flags); |
8983 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8984 | |
8985 | /* Ensure we don't miss a work->pending update ... */ | |
8986 | smp_rmb(); | |
8987 | ||
8988 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8989 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8990 | return; | |
8991 | } | |
8992 | ||
d6bbafa1 | 8993 | page_flip_completed(intel_crtc); |
0af7e4df | 8994 | |
6b95a207 | 8995 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
8996 | } |
8997 | ||
1afe3e9d JB |
8998 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8999 | { | |
fbee40df | 9000 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9001 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9002 | ||
49b14a5c | 9003 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9004 | } |
9005 | ||
9006 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9007 | { | |
fbee40df | 9008 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9009 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9010 | ||
49b14a5c | 9011 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9012 | } |
9013 | ||
75f7f3ec VS |
9014 | /* Is 'a' after or equal to 'b'? */ |
9015 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9016 | { | |
9017 | return !((a - b) & 0x80000000); | |
9018 | } | |
9019 | ||
9020 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9021 | { | |
9022 | struct drm_device *dev = crtc->base.dev; | |
9023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9024 | ||
bdfa7542 VS |
9025 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
9026 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
9027 | return true; | |
9028 | ||
75f7f3ec VS |
9029 | /* |
9030 | * The relevant registers doen't exist on pre-ctg. | |
9031 | * As the flip done interrupt doesn't trigger for mmio | |
9032 | * flips on gmch platforms, a flip count check isn't | |
9033 | * really needed there. But since ctg has the registers, | |
9034 | * include it in the check anyway. | |
9035 | */ | |
9036 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9037 | return true; | |
9038 | ||
9039 | /* | |
9040 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9041 | * used the same base address. In that case the mmio flip might | |
9042 | * have completed, but the CS hasn't even executed the flip yet. | |
9043 | * | |
9044 | * A flip count check isn't enough as the CS might have updated | |
9045 | * the base address just after start of vblank, but before we | |
9046 | * managed to process the interrupt. This means we'd complete the | |
9047 | * CS flip too soon. | |
9048 | * | |
9049 | * Combining both checks should get us a good enough result. It may | |
9050 | * still happen that the CS flip has been executed, but has not | |
9051 | * yet actually completed. But in case the base address is the same | |
9052 | * anyway, we don't really care. | |
9053 | */ | |
9054 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9055 | crtc->unpin_work->gtt_offset && | |
9056 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9057 | crtc->unpin_work->flip_count); | |
9058 | } | |
9059 | ||
6b95a207 KH |
9060 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9061 | { | |
fbee40df | 9062 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9063 | struct intel_crtc *intel_crtc = |
9064 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9065 | unsigned long flags; | |
9066 | ||
f326038a DV |
9067 | |
9068 | /* | |
9069 | * This is called both by irq handlers and the reset code (to complete | |
9070 | * lost pageflips) so needs the full irqsave spinlocks. | |
9071 | * | |
9072 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
9073 | * generate a page-flip completion irq, i.e. every modeset |
9074 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9075 | */ | |
6b95a207 | 9076 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9077 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9078 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9079 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9080 | } | |
9081 | ||
eba905b2 | 9082 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9083 | { |
9084 | /* Ensure that the work item is consistent when activating it ... */ | |
9085 | smp_wmb(); | |
9086 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9087 | /* and that it is marked active as soon as the irq could fire. */ | |
9088 | smp_wmb(); | |
9089 | } | |
9090 | ||
8c9f3aaf JB |
9091 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9092 | struct drm_crtc *crtc, | |
9093 | struct drm_framebuffer *fb, | |
ed8d1975 | 9094 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9095 | struct intel_engine_cs *ring, |
ed8d1975 | 9096 | uint32_t flags) |
8c9f3aaf | 9097 | { |
8c9f3aaf | 9098 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9099 | u32 flip_mask; |
9100 | int ret; | |
9101 | ||
6d90c952 | 9102 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9103 | if (ret) |
4fa62c89 | 9104 | return ret; |
8c9f3aaf JB |
9105 | |
9106 | /* Can't queue multiple flips, so wait for the previous | |
9107 | * one to finish before executing the next. | |
9108 | */ | |
9109 | if (intel_crtc->plane) | |
9110 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9111 | else | |
9112 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9113 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9114 | intel_ring_emit(ring, MI_NOOP); | |
9115 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9116 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9117 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9118 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9119 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9120 | |
9121 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9122 | __intel_ring_advance(ring); |
83d4092b | 9123 | return 0; |
8c9f3aaf JB |
9124 | } |
9125 | ||
9126 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9127 | struct drm_crtc *crtc, | |
9128 | struct drm_framebuffer *fb, | |
ed8d1975 | 9129 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9130 | struct intel_engine_cs *ring, |
ed8d1975 | 9131 | uint32_t flags) |
8c9f3aaf | 9132 | { |
8c9f3aaf | 9133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9134 | u32 flip_mask; |
9135 | int ret; | |
9136 | ||
6d90c952 | 9137 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9138 | if (ret) |
4fa62c89 | 9139 | return ret; |
8c9f3aaf JB |
9140 | |
9141 | if (intel_crtc->plane) | |
9142 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9143 | else | |
9144 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9145 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9146 | intel_ring_emit(ring, MI_NOOP); | |
9147 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9148 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9149 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9150 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9151 | intel_ring_emit(ring, MI_NOOP); |
9152 | ||
e7d841ca | 9153 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9154 | __intel_ring_advance(ring); |
83d4092b | 9155 | return 0; |
8c9f3aaf JB |
9156 | } |
9157 | ||
9158 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9159 | struct drm_crtc *crtc, | |
9160 | struct drm_framebuffer *fb, | |
ed8d1975 | 9161 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9162 | struct intel_engine_cs *ring, |
ed8d1975 | 9163 | uint32_t flags) |
8c9f3aaf JB |
9164 | { |
9165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9166 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9167 | uint32_t pf, pipesrc; | |
9168 | int ret; | |
9169 | ||
6d90c952 | 9170 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9171 | if (ret) |
4fa62c89 | 9172 | return ret; |
8c9f3aaf JB |
9173 | |
9174 | /* i965+ uses the linear or tiled offsets from the | |
9175 | * Display Registers (which do not change across a page-flip) | |
9176 | * so we need only reprogram the base address. | |
9177 | */ | |
6d90c952 DV |
9178 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9179 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9180 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9181 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9182 | obj->tiling_mode); |
8c9f3aaf JB |
9183 | |
9184 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9185 | * untested on non-native modes, so ignore it for now. | |
9186 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9187 | */ | |
9188 | pf = 0; | |
9189 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9190 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9191 | |
9192 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9193 | __intel_ring_advance(ring); |
83d4092b | 9194 | return 0; |
8c9f3aaf JB |
9195 | } |
9196 | ||
9197 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9198 | struct drm_crtc *crtc, | |
9199 | struct drm_framebuffer *fb, | |
ed8d1975 | 9200 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9201 | struct intel_engine_cs *ring, |
ed8d1975 | 9202 | uint32_t flags) |
8c9f3aaf JB |
9203 | { |
9204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9206 | uint32_t pf, pipesrc; | |
9207 | int ret; | |
9208 | ||
6d90c952 | 9209 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9210 | if (ret) |
4fa62c89 | 9211 | return ret; |
8c9f3aaf | 9212 | |
6d90c952 DV |
9213 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9214 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9215 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9216 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9217 | |
dc257cf1 DV |
9218 | /* Contrary to the suggestions in the documentation, |
9219 | * "Enable Panel Fitter" does not seem to be required when page | |
9220 | * flipping with a non-native mode, and worse causes a normal | |
9221 | * modeset to fail. | |
9222 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9223 | */ | |
9224 | pf = 0; | |
8c9f3aaf | 9225 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9226 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9227 | |
9228 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9229 | __intel_ring_advance(ring); |
83d4092b | 9230 | return 0; |
8c9f3aaf JB |
9231 | } |
9232 | ||
7c9017e5 JB |
9233 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9234 | struct drm_crtc *crtc, | |
9235 | struct drm_framebuffer *fb, | |
ed8d1975 | 9236 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9237 | struct intel_engine_cs *ring, |
ed8d1975 | 9238 | uint32_t flags) |
7c9017e5 | 9239 | { |
7c9017e5 | 9240 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9241 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9242 | int len, ret; |
9243 | ||
eba905b2 | 9244 | switch (intel_crtc->plane) { |
cb05d8de DV |
9245 | case PLANE_A: |
9246 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9247 | break; | |
9248 | case PLANE_B: | |
9249 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9250 | break; | |
9251 | case PLANE_C: | |
9252 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9253 | break; | |
9254 | default: | |
9255 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9256 | return -ENODEV; |
cb05d8de DV |
9257 | } |
9258 | ||
ffe74d75 | 9259 | len = 4; |
f476828a | 9260 | if (ring->id == RCS) { |
ffe74d75 | 9261 | len += 6; |
f476828a DL |
9262 | /* |
9263 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9264 | * 48bits addresses, and we need a NOOP for the batch size to | |
9265 | * stay even. | |
9266 | */ | |
9267 | if (IS_GEN8(dev)) | |
9268 | len += 2; | |
9269 | } | |
ffe74d75 | 9270 | |
f66fab8e VS |
9271 | /* |
9272 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9273 | * "The full packet must be contained within the same cache line." | |
9274 | * | |
9275 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9276 | * cacheline, if we ever start emitting more commands before | |
9277 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9278 | * then do the cacheline alignment, and finally emit the | |
9279 | * MI_DISPLAY_FLIP. | |
9280 | */ | |
9281 | ret = intel_ring_cacheline_align(ring); | |
9282 | if (ret) | |
4fa62c89 | 9283 | return ret; |
f66fab8e | 9284 | |
ffe74d75 | 9285 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9286 | if (ret) |
4fa62c89 | 9287 | return ret; |
7c9017e5 | 9288 | |
ffe74d75 CW |
9289 | /* Unmask the flip-done completion message. Note that the bspec says that |
9290 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9291 | * more than one flip event at any time (or ensure that one flip message | |
9292 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9293 | * Experimentation says that BCS works despite DERRMR masking all | |
9294 | * flip-done completion events and that unmasking all planes at once | |
9295 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9296 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9297 | */ | |
9298 | if (ring->id == RCS) { | |
9299 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9300 | intel_ring_emit(ring, DERRMR); | |
9301 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9302 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9303 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9304 | if (IS_GEN8(dev)) |
9305 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9306 | MI_SRM_LRM_GLOBAL_GTT); | |
9307 | else | |
9308 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9309 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9310 | intel_ring_emit(ring, DERRMR); |
9311 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9312 | if (IS_GEN8(dev)) { |
9313 | intel_ring_emit(ring, 0); | |
9314 | intel_ring_emit(ring, MI_NOOP); | |
9315 | } | |
ffe74d75 CW |
9316 | } |
9317 | ||
cb05d8de | 9318 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9319 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9320 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9321 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9322 | |
9323 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9324 | __intel_ring_advance(ring); |
83d4092b | 9325 | return 0; |
7c9017e5 JB |
9326 | } |
9327 | ||
84c33a64 SG |
9328 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9329 | struct drm_i915_gem_object *obj) | |
9330 | { | |
9331 | /* | |
9332 | * This is not being used for older platforms, because | |
9333 | * non-availability of flip done interrupt forces us to use | |
9334 | * CS flips. Older platforms derive flip done using some clever | |
9335 | * tricks involving the flip_pending status bits and vblank irqs. | |
9336 | * So using MMIO flips there would disrupt this mechanism. | |
9337 | */ | |
9338 | ||
8e09bf83 CW |
9339 | if (ring == NULL) |
9340 | return true; | |
9341 | ||
84c33a64 SG |
9342 | if (INTEL_INFO(ring->dev)->gen < 5) |
9343 | return false; | |
9344 | ||
9345 | if (i915.use_mmio_flip < 0) | |
9346 | return false; | |
9347 | else if (i915.use_mmio_flip > 0) | |
9348 | return true; | |
14bf993e OM |
9349 | else if (i915.enable_execlists) |
9350 | return true; | |
84c33a64 | 9351 | else |
41c52415 | 9352 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
9353 | } |
9354 | ||
ff944564 DL |
9355 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
9356 | { | |
9357 | struct drm_device *dev = intel_crtc->base.dev; | |
9358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9359 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
9360 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
9361 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9362 | const enum pipe pipe = intel_crtc->pipe; | |
9363 | u32 ctl, stride; | |
9364 | ||
9365 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
9366 | ctl &= ~PLANE_CTL_TILED_MASK; | |
9367 | if (obj->tiling_mode == I915_TILING_X) | |
9368 | ctl |= PLANE_CTL_TILED_X; | |
9369 | ||
9370 | /* | |
9371 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
9372 | * linear buffers or in number of tiles for tiled buffers. | |
9373 | */ | |
9374 | stride = fb->pitches[0] >> 6; | |
9375 | if (obj->tiling_mode == I915_TILING_X) | |
9376 | stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */ | |
9377 | ||
9378 | /* | |
9379 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
9380 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
9381 | */ | |
9382 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
9383 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
9384 | ||
9385 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
9386 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
9387 | } | |
9388 | ||
9389 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
9390 | { |
9391 | struct drm_device *dev = intel_crtc->base.dev; | |
9392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9393 | struct intel_framebuffer *intel_fb = | |
9394 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9395 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9396 | u32 dspcntr; | |
9397 | u32 reg; | |
9398 | ||
84c33a64 SG |
9399 | reg = DSPCNTR(intel_crtc->plane); |
9400 | dspcntr = I915_READ(reg); | |
9401 | ||
c5d97472 DL |
9402 | if (obj->tiling_mode != I915_TILING_NONE) |
9403 | dspcntr |= DISPPLANE_TILED; | |
9404 | else | |
9405 | dspcntr &= ~DISPPLANE_TILED; | |
9406 | ||
84c33a64 SG |
9407 | I915_WRITE(reg, dspcntr); |
9408 | ||
9409 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9410 | intel_crtc->unpin_work->gtt_offset); | |
9411 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 9412 | |
ff944564 DL |
9413 | } |
9414 | ||
9415 | /* | |
9416 | * XXX: This is the temporary way to update the plane registers until we get | |
9417 | * around to using the usual plane update functions for MMIO flips | |
9418 | */ | |
9419 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9420 | { | |
9421 | struct drm_device *dev = intel_crtc->base.dev; | |
9422 | bool atomic_update; | |
9423 | u32 start_vbl_count; | |
9424 | ||
9425 | intel_mark_page_flip_active(intel_crtc); | |
9426 | ||
9427 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
9428 | ||
9429 | if (INTEL_INFO(dev)->gen >= 9) | |
9430 | skl_do_mmio_flip(intel_crtc); | |
9431 | else | |
9432 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
9433 | ilk_do_mmio_flip(intel_crtc); | |
9434 | ||
9362c7c5 ACO |
9435 | if (atomic_update) |
9436 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
9437 | } |
9438 | ||
9362c7c5 | 9439 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 9440 | { |
cc8c4cc2 | 9441 | struct intel_crtc *crtc = |
9362c7c5 | 9442 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 9443 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 9444 | |
cc8c4cc2 JH |
9445 | mmio_flip = &crtc->mmio_flip; |
9446 | if (mmio_flip->req) | |
9c654818 JH |
9447 | WARN_ON(__i915_wait_request(mmio_flip->req, |
9448 | crtc->reset_counter, | |
9449 | false, NULL, NULL) != 0); | |
84c33a64 | 9450 | |
cc8c4cc2 JH |
9451 | intel_do_mmio_flip(crtc); |
9452 | if (mmio_flip->req) { | |
9453 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 9454 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
9455 | mutex_unlock(&crtc->base.dev->struct_mutex); |
9456 | } | |
84c33a64 SG |
9457 | } |
9458 | ||
9459 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9460 | struct drm_crtc *crtc, | |
9461 | struct drm_framebuffer *fb, | |
9462 | struct drm_i915_gem_object *obj, | |
9463 | struct intel_engine_cs *ring, | |
9464 | uint32_t flags) | |
9465 | { | |
84c33a64 | 9466 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 9467 | |
cc8c4cc2 JH |
9468 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
9469 | obj->last_write_req); | |
536f5b5e ACO |
9470 | |
9471 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 9472 | |
84c33a64 SG |
9473 | return 0; |
9474 | } | |
9475 | ||
830c81db DL |
9476 | static int intel_gen9_queue_flip(struct drm_device *dev, |
9477 | struct drm_crtc *crtc, | |
9478 | struct drm_framebuffer *fb, | |
9479 | struct drm_i915_gem_object *obj, | |
9480 | struct intel_engine_cs *ring, | |
9481 | uint32_t flags) | |
9482 | { | |
9483 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9484 | uint32_t plane = 0, stride; | |
9485 | int ret; | |
9486 | ||
9487 | switch(intel_crtc->pipe) { | |
9488 | case PIPE_A: | |
9489 | plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A; | |
9490 | break; | |
9491 | case PIPE_B: | |
9492 | plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B; | |
9493 | break; | |
9494 | case PIPE_C: | |
9495 | plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C; | |
9496 | break; | |
9497 | default: | |
9498 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
9499 | return -ENODEV; | |
9500 | } | |
9501 | ||
9502 | switch (obj->tiling_mode) { | |
9503 | case I915_TILING_NONE: | |
9504 | stride = fb->pitches[0] >> 6; | |
9505 | break; | |
9506 | case I915_TILING_X: | |
9507 | stride = fb->pitches[0] >> 9; | |
9508 | break; | |
9509 | default: | |
9510 | WARN_ONCE(1, "unknown tiling in flip command\n"); | |
9511 | return -ENODEV; | |
9512 | } | |
9513 | ||
9514 | ret = intel_ring_begin(ring, 10); | |
9515 | if (ret) | |
9516 | return ret; | |
9517 | ||
9518 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9519 | intel_ring_emit(ring, DERRMR); | |
9520 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9521 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9522 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
9523 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9524 | MI_SRM_LRM_GLOBAL_GTT); | |
9525 | intel_ring_emit(ring, DERRMR); | |
9526 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
9527 | intel_ring_emit(ring, 0); | |
9528 | ||
9529 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane); | |
9530 | intel_ring_emit(ring, stride << 6 | obj->tiling_mode); | |
9531 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); | |
9532 | ||
9533 | intel_mark_page_flip_active(intel_crtc); | |
9534 | __intel_ring_advance(ring); | |
9535 | ||
9536 | return 0; | |
9537 | } | |
9538 | ||
8c9f3aaf JB |
9539 | static int intel_default_queue_flip(struct drm_device *dev, |
9540 | struct drm_crtc *crtc, | |
9541 | struct drm_framebuffer *fb, | |
ed8d1975 | 9542 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9543 | struct intel_engine_cs *ring, |
ed8d1975 | 9544 | uint32_t flags) |
8c9f3aaf JB |
9545 | { |
9546 | return -ENODEV; | |
9547 | } | |
9548 | ||
d6bbafa1 CW |
9549 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
9550 | struct drm_crtc *crtc) | |
9551 | { | |
9552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9553 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9554 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
9555 | u32 addr; | |
9556 | ||
9557 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
9558 | return true; | |
9559 | ||
9560 | if (!work->enable_stall_check) | |
9561 | return false; | |
9562 | ||
9563 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
9564 | if (work->flip_queued_req && |
9565 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
9566 | return false; |
9567 | ||
9568 | work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe); | |
9569 | } | |
9570 | ||
9571 | if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3) | |
9572 | return false; | |
9573 | ||
9574 | /* Potential stall - if we see that the flip has happened, | |
9575 | * assume a missed interrupt. */ | |
9576 | if (INTEL_INFO(dev)->gen >= 4) | |
9577 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
9578 | else | |
9579 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
9580 | ||
9581 | /* There is a potential issue here with a false positive after a flip | |
9582 | * to the same address. We could address this by checking for a | |
9583 | * non-incrementing frame counter. | |
9584 | */ | |
9585 | return addr == work->gtt_offset; | |
9586 | } | |
9587 | ||
9588 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
9589 | { | |
9590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9591 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
9592 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
f326038a DV |
9593 | |
9594 | WARN_ON(!in_irq()); | |
d6bbafa1 CW |
9595 | |
9596 | if (crtc == NULL) | |
9597 | return; | |
9598 | ||
f326038a | 9599 | spin_lock(&dev->event_lock); |
d6bbafa1 CW |
9600 | if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) { |
9601 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", | |
9602 | intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe)); | |
9603 | page_flip_completed(intel_crtc); | |
9604 | } | |
f326038a | 9605 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
9606 | } |
9607 | ||
6b95a207 KH |
9608 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9609 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9610 | struct drm_pending_vblank_event *event, |
9611 | uint32_t page_flip_flags) | |
6b95a207 KH |
9612 | { |
9613 | struct drm_device *dev = crtc->dev; | |
9614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9615 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 9616 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 9617 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 9618 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 9619 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 9620 | struct intel_unpin_work *work; |
a4872ba6 | 9621 | struct intel_engine_cs *ring; |
52e68630 | 9622 | int ret; |
6b95a207 | 9623 | |
2ff8fde1 MR |
9624 | /* |
9625 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
9626 | * check to be safe. In the future we may enable pageflipping from | |
9627 | * a disabled primary plane. | |
9628 | */ | |
9629 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
9630 | return -EBUSY; | |
9631 | ||
e6a595d2 | 9632 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9633 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9634 | return -EINVAL; |
9635 | ||
9636 | /* | |
9637 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9638 | * Note that pitch changes could also affect these register. | |
9639 | */ | |
9640 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9641 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9642 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9643 | return -EINVAL; |
9644 | ||
f900db47 CW |
9645 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9646 | goto out_hang; | |
9647 | ||
b14c5679 | 9648 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9649 | if (work == NULL) |
9650 | return -ENOMEM; | |
9651 | ||
6b95a207 | 9652 | work->event = event; |
b4a98e57 | 9653 | work->crtc = crtc; |
2ff8fde1 | 9654 | work->old_fb_obj = intel_fb_obj(old_fb); |
6b95a207 KH |
9655 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9656 | ||
87b6b101 | 9657 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9658 | if (ret) |
9659 | goto free_work; | |
9660 | ||
6b95a207 | 9661 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 9662 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 9663 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
9664 | /* Before declaring the flip queue wedged, check if |
9665 | * the hardware completed the operation behind our backs. | |
9666 | */ | |
9667 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
9668 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
9669 | page_flip_completed(intel_crtc); | |
9670 | } else { | |
9671 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 9672 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 9673 | |
d6bbafa1 CW |
9674 | drm_crtc_vblank_put(crtc); |
9675 | kfree(work); | |
9676 | return -EBUSY; | |
9677 | } | |
6b95a207 KH |
9678 | } |
9679 | intel_crtc->unpin_work = work; | |
5e2d7afc | 9680 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 9681 | |
b4a98e57 CW |
9682 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9683 | flush_workqueue(dev_priv->wq); | |
9684 | ||
79158103 CW |
9685 | ret = i915_mutex_lock_interruptible(dev); |
9686 | if (ret) | |
9687 | goto cleanup; | |
6b95a207 | 9688 | |
75dfca80 | 9689 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9690 | drm_gem_object_reference(&work->old_fb_obj->base); |
9691 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9692 | |
f4510a27 | 9693 | crtc->primary->fb = fb; |
96b099fd | 9694 | |
e1f99ce6 | 9695 | work->pending_flip_obj = obj; |
e1f99ce6 | 9696 | |
b4a98e57 | 9697 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9698 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9699 | |
75f7f3ec | 9700 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 9701 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 9702 | |
4fa62c89 VS |
9703 | if (IS_VALLEYVIEW(dev)) { |
9704 | ring = &dev_priv->ring[BCS]; | |
8e09bf83 CW |
9705 | if (obj->tiling_mode != work->old_fb_obj->tiling_mode) |
9706 | /* vlv: DISPLAY_FLIP fails to change tiling */ | |
9707 | ring = NULL; | |
48bf5b2d | 9708 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 9709 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 9710 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 9711 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
9712 | if (ring == NULL || ring->id != RCS) |
9713 | ring = &dev_priv->ring[BCS]; | |
9714 | } else { | |
9715 | ring = &dev_priv->ring[RCS]; | |
9716 | } | |
9717 | ||
850c4cdc | 9718 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring); |
8c9f3aaf JB |
9719 | if (ret) |
9720 | goto cleanup_pending; | |
6b95a207 | 9721 | |
4fa62c89 VS |
9722 | work->gtt_offset = |
9723 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9724 | ||
d6bbafa1 | 9725 | if (use_mmio_flip(ring, obj)) { |
84c33a64 SG |
9726 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
9727 | page_flip_flags); | |
d6bbafa1 CW |
9728 | if (ret) |
9729 | goto cleanup_unpin; | |
9730 | ||
f06cc1b9 JH |
9731 | i915_gem_request_assign(&work->flip_queued_req, |
9732 | obj->last_write_req); | |
d6bbafa1 | 9733 | } else { |
84c33a64 | 9734 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
9735 | page_flip_flags); |
9736 | if (ret) | |
9737 | goto cleanup_unpin; | |
9738 | ||
f06cc1b9 JH |
9739 | i915_gem_request_assign(&work->flip_queued_req, |
9740 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
9741 | } |
9742 | ||
9743 | work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe); | |
9744 | work->enable_stall_check = true; | |
4fa62c89 | 9745 | |
a071fa00 DV |
9746 | i915_gem_track_fb(work->old_fb_obj, obj, |
9747 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
9748 | ||
7ff0ebcc | 9749 | intel_fbc_disable(dev); |
f99d7069 | 9750 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
9751 | mutex_unlock(&dev->struct_mutex); |
9752 | ||
e5510fac JB |
9753 | trace_i915_flip_request(intel_crtc->plane, obj); |
9754 | ||
6b95a207 | 9755 | return 0; |
96b099fd | 9756 | |
4fa62c89 VS |
9757 | cleanup_unpin: |
9758 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9759 | cleanup_pending: |
b4a98e57 | 9760 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9761 | crtc->primary->fb = old_fb; |
05394f39 CW |
9762 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9763 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9764 | mutex_unlock(&dev->struct_mutex); |
9765 | ||
79158103 | 9766 | cleanup: |
5e2d7afc | 9767 | spin_lock_irq(&dev->event_lock); |
96b099fd | 9768 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 9769 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 9770 | |
87b6b101 | 9771 | drm_crtc_vblank_put(crtc); |
7317c75e | 9772 | free_work: |
96b099fd CW |
9773 | kfree(work); |
9774 | ||
f900db47 CW |
9775 | if (ret == -EIO) { |
9776 | out_hang: | |
53a366b9 | 9777 | ret = intel_plane_restore(primary); |
f0d3dad3 | 9778 | if (ret == 0 && event) { |
5e2d7afc | 9779 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 9780 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 9781 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 9782 | } |
f900db47 | 9783 | } |
96b099fd | 9784 | return ret; |
6b95a207 KH |
9785 | } |
9786 | ||
f6e5b160 | 9787 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9788 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9789 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
9790 | .atomic_begin = intel_begin_crtc_commit, |
9791 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
9792 | }; |
9793 | ||
9a935856 DV |
9794 | /** |
9795 | * intel_modeset_update_staged_output_state | |
9796 | * | |
9797 | * Updates the staged output configuration state, e.g. after we've read out the | |
9798 | * current hw state. | |
9799 | */ | |
9800 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9801 | { |
7668851f | 9802 | struct intel_crtc *crtc; |
9a935856 DV |
9803 | struct intel_encoder *encoder; |
9804 | struct intel_connector *connector; | |
f6e5b160 | 9805 | |
9a935856 DV |
9806 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9807 | base.head) { | |
9808 | connector->new_encoder = | |
9809 | to_intel_encoder(connector->base.encoder); | |
9810 | } | |
f6e5b160 | 9811 | |
b2784e15 | 9812 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
9813 | encoder->new_crtc = |
9814 | to_intel_crtc(encoder->base.crtc); | |
9815 | } | |
7668851f | 9816 | |
d3fcc808 | 9817 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9818 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9819 | |
9820 | if (crtc->new_enabled) | |
9821 | crtc->new_config = &crtc->config; | |
9822 | else | |
9823 | crtc->new_config = NULL; | |
7668851f | 9824 | } |
f6e5b160 CW |
9825 | } |
9826 | ||
9a935856 DV |
9827 | /** |
9828 | * intel_modeset_commit_output_state | |
9829 | * | |
9830 | * This function copies the stage display pipe configuration to the real one. | |
9831 | */ | |
9832 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9833 | { | |
7668851f | 9834 | struct intel_crtc *crtc; |
9a935856 DV |
9835 | struct intel_encoder *encoder; |
9836 | struct intel_connector *connector; | |
f6e5b160 | 9837 | |
9a935856 DV |
9838 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9839 | base.head) { | |
9840 | connector->base.encoder = &connector->new_encoder->base; | |
9841 | } | |
f6e5b160 | 9842 | |
b2784e15 | 9843 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
9844 | encoder->base.crtc = &encoder->new_crtc->base; |
9845 | } | |
7668851f | 9846 | |
d3fcc808 | 9847 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9848 | crtc->base.enabled = crtc->new_enabled; |
9849 | } | |
9a935856 DV |
9850 | } |
9851 | ||
050f7aeb | 9852 | static void |
eba905b2 | 9853 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9854 | struct intel_crtc_config *pipe_config) |
9855 | { | |
9856 | int bpp = pipe_config->pipe_bpp; | |
9857 | ||
9858 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9859 | connector->base.base.id, | |
c23cc417 | 9860 | connector->base.name); |
050f7aeb DV |
9861 | |
9862 | /* Don't use an invalid EDID bpc value */ | |
9863 | if (connector->base.display_info.bpc && | |
9864 | connector->base.display_info.bpc * 3 < bpp) { | |
9865 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9866 | bpp, connector->base.display_info.bpc*3); | |
9867 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9868 | } | |
9869 | ||
9870 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9871 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9872 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9873 | bpp); | |
9874 | pipe_config->pipe_bpp = 24; | |
9875 | } | |
9876 | } | |
9877 | ||
4e53c2e0 | 9878 | static int |
050f7aeb DV |
9879 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9880 | struct drm_framebuffer *fb, | |
9881 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9882 | { |
050f7aeb DV |
9883 | struct drm_device *dev = crtc->base.dev; |
9884 | struct intel_connector *connector; | |
4e53c2e0 DV |
9885 | int bpp; |
9886 | ||
d42264b1 DV |
9887 | switch (fb->pixel_format) { |
9888 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9889 | bpp = 8*3; /* since we go through a colormap */ |
9890 | break; | |
d42264b1 DV |
9891 | case DRM_FORMAT_XRGB1555: |
9892 | case DRM_FORMAT_ARGB1555: | |
9893 | /* checked in intel_framebuffer_init already */ | |
9894 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9895 | return -EINVAL; | |
9896 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9897 | bpp = 6*3; /* min is 18bpp */ |
9898 | break; | |
d42264b1 DV |
9899 | case DRM_FORMAT_XBGR8888: |
9900 | case DRM_FORMAT_ABGR8888: | |
9901 | /* checked in intel_framebuffer_init already */ | |
9902 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9903 | return -EINVAL; | |
9904 | case DRM_FORMAT_XRGB8888: | |
9905 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9906 | bpp = 8*3; |
9907 | break; | |
d42264b1 DV |
9908 | case DRM_FORMAT_XRGB2101010: |
9909 | case DRM_FORMAT_ARGB2101010: | |
9910 | case DRM_FORMAT_XBGR2101010: | |
9911 | case DRM_FORMAT_ABGR2101010: | |
9912 | /* checked in intel_framebuffer_init already */ | |
9913 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 9914 | return -EINVAL; |
4e53c2e0 DV |
9915 | bpp = 10*3; |
9916 | break; | |
baba133a | 9917 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
9918 | default: |
9919 | DRM_DEBUG_KMS("unsupported depth\n"); | |
9920 | return -EINVAL; | |
9921 | } | |
9922 | ||
4e53c2e0 DV |
9923 | pipe_config->pipe_bpp = bpp; |
9924 | ||
9925 | /* Clamp display bpp to EDID value */ | |
9926 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 9927 | base.head) { |
1b829e05 DV |
9928 | if (!connector->new_encoder || |
9929 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
9930 | continue; |
9931 | ||
050f7aeb | 9932 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
9933 | } |
9934 | ||
9935 | return bpp; | |
9936 | } | |
9937 | ||
644db711 DV |
9938 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9939 | { | |
9940 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
9941 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 9942 | mode->crtc_clock, |
644db711 DV |
9943 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9944 | mode->crtc_hsync_end, mode->crtc_htotal, | |
9945 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
9946 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
9947 | } | |
9948 | ||
c0b03411 DV |
9949 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9950 | struct intel_crtc_config *pipe_config, | |
9951 | const char *context) | |
9952 | { | |
9953 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
9954 | context, pipe_name(crtc->pipe)); | |
9955 | ||
9956 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
9957 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
9958 | pipe_config->pipe_bpp, pipe_config->dither); | |
9959 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
9960 | pipe_config->has_pch_encoder, | |
9961 | pipe_config->fdi_lanes, | |
9962 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
9963 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
9964 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
9965 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9966 | pipe_config->has_dp_encoder, | |
9967 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
9968 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
9969 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
9970 | |
9971 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
9972 | pipe_config->has_dp_encoder, | |
9973 | pipe_config->dp_m2_n2.gmch_m, | |
9974 | pipe_config->dp_m2_n2.gmch_n, | |
9975 | pipe_config->dp_m2_n2.link_m, | |
9976 | pipe_config->dp_m2_n2.link_n, | |
9977 | pipe_config->dp_m2_n2.tu); | |
9978 | ||
55072d19 DV |
9979 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
9980 | pipe_config->has_audio, | |
9981 | pipe_config->has_infoframe); | |
9982 | ||
c0b03411 DV |
9983 | DRM_DEBUG_KMS("requested mode:\n"); |
9984 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
9985 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
9986 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 9987 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 9988 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
9989 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
9990 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
9991 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
9992 | pipe_config->gmch_pfit.control, | |
9993 | pipe_config->gmch_pfit.pgm_ratios, | |
9994 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 9995 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 9996 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
9997 | pipe_config->pch_pfit.size, |
9998 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 9999 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10000 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10001 | } |
10002 | ||
bc079e8b VS |
10003 | static bool encoders_cloneable(const struct intel_encoder *a, |
10004 | const struct intel_encoder *b) | |
accfc0c5 | 10005 | { |
bc079e8b VS |
10006 | /* masks could be asymmetric, so check both ways */ |
10007 | return a == b || (a->cloneable & (1 << b->type) && | |
10008 | b->cloneable & (1 << a->type)); | |
10009 | } | |
10010 | ||
10011 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
10012 | struct intel_encoder *encoder) | |
10013 | { | |
10014 | struct drm_device *dev = crtc->base.dev; | |
10015 | struct intel_encoder *source_encoder; | |
10016 | ||
b2784e15 | 10017 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b VS |
10018 | if (source_encoder->new_crtc != crtc) |
10019 | continue; | |
10020 | ||
10021 | if (!encoders_cloneable(encoder, source_encoder)) | |
10022 | return false; | |
10023 | } | |
10024 | ||
10025 | return true; | |
10026 | } | |
10027 | ||
10028 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
10029 | { | |
10030 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
10031 | struct intel_encoder *encoder; |
10032 | ||
b2784e15 | 10033 | for_each_intel_encoder(dev, encoder) { |
bc079e8b | 10034 | if (encoder->new_crtc != crtc) |
accfc0c5 DV |
10035 | continue; |
10036 | ||
bc079e8b VS |
10037 | if (!check_single_encoder_cloning(crtc, encoder)) |
10038 | return false; | |
accfc0c5 DV |
10039 | } |
10040 | ||
bc079e8b | 10041 | return true; |
accfc0c5 DV |
10042 | } |
10043 | ||
00f0b378 VS |
10044 | static bool check_digital_port_conflicts(struct drm_device *dev) |
10045 | { | |
10046 | struct intel_connector *connector; | |
10047 | unsigned int used_ports = 0; | |
10048 | ||
10049 | /* | |
10050 | * Walk the connector list instead of the encoder | |
10051 | * list to detect the problem on ddi platforms | |
10052 | * where there's just one encoder per digital port. | |
10053 | */ | |
10054 | list_for_each_entry(connector, | |
10055 | &dev->mode_config.connector_list, base.head) { | |
10056 | struct intel_encoder *encoder = connector->new_encoder; | |
10057 | ||
10058 | if (!encoder) | |
10059 | continue; | |
10060 | ||
10061 | WARN_ON(!encoder->new_crtc); | |
10062 | ||
10063 | switch (encoder->type) { | |
10064 | unsigned int port_mask; | |
10065 | case INTEL_OUTPUT_UNKNOWN: | |
10066 | if (WARN_ON(!HAS_DDI(dev))) | |
10067 | break; | |
10068 | case INTEL_OUTPUT_DISPLAYPORT: | |
10069 | case INTEL_OUTPUT_HDMI: | |
10070 | case INTEL_OUTPUT_EDP: | |
10071 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10072 | ||
10073 | /* the same port mustn't appear more than once */ | |
10074 | if (used_ports & port_mask) | |
10075 | return false; | |
10076 | ||
10077 | used_ports |= port_mask; | |
10078 | default: | |
10079 | break; | |
10080 | } | |
10081 | } | |
10082 | ||
10083 | return true; | |
10084 | } | |
10085 | ||
b8cecdf5 DV |
10086 | static struct intel_crtc_config * |
10087 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 10088 | struct drm_framebuffer *fb, |
b8cecdf5 | 10089 | struct drm_display_mode *mode) |
ee7b9f93 | 10090 | { |
7758a113 | 10091 | struct drm_device *dev = crtc->dev; |
7758a113 | 10092 | struct intel_encoder *encoder; |
b8cecdf5 | 10093 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
10094 | int plane_bpp, ret = -EINVAL; |
10095 | bool retry = true; | |
ee7b9f93 | 10096 | |
bc079e8b | 10097 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
10098 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10099 | return ERR_PTR(-EINVAL); | |
10100 | } | |
10101 | ||
00f0b378 VS |
10102 | if (!check_digital_port_conflicts(dev)) { |
10103 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
10104 | return ERR_PTR(-EINVAL); | |
10105 | } | |
10106 | ||
b8cecdf5 DV |
10107 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10108 | if (!pipe_config) | |
7758a113 DV |
10109 | return ERR_PTR(-ENOMEM); |
10110 | ||
b8cecdf5 DV |
10111 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
10112 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 10113 | |
e143a21c DV |
10114 | pipe_config->cpu_transcoder = |
10115 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10116 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10117 | |
2960bc9c ID |
10118 | /* |
10119 | * Sanitize sync polarity flags based on requested ones. If neither | |
10120 | * positive or negative polarity is requested, treat this as meaning | |
10121 | * negative polarity. | |
10122 | */ | |
10123 | if (!(pipe_config->adjusted_mode.flags & | |
10124 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
10125 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
10126 | ||
10127 | if (!(pipe_config->adjusted_mode.flags & | |
10128 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
10129 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
10130 | ||
050f7aeb DV |
10131 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10132 | * plane pixel format and any sink constraints into account. Returns the | |
10133 | * source plane bpp so that dithering can be selected on mismatches | |
10134 | * after encoders and crtc also have had their say. */ | |
10135 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10136 | fb, pipe_config); | |
4e53c2e0 DV |
10137 | if (plane_bpp < 0) |
10138 | goto fail; | |
10139 | ||
e41a56be VS |
10140 | /* |
10141 | * Determine the real pipe dimensions. Note that stereo modes can | |
10142 | * increase the actual pipe size due to the frame doubling and | |
10143 | * insertion of additional space for blanks between the frame. This | |
10144 | * is stored in the crtc timings. We use the requested mode to do this | |
10145 | * computation to clearly distinguish it from the adjusted mode, which | |
10146 | * can be changed by the connectors in the below retry loop. | |
10147 | */ | |
ecb7e16b GP |
10148 | drm_crtc_get_hv_timing(&pipe_config->requested_mode, |
10149 | &pipe_config->pipe_src_w, | |
10150 | &pipe_config->pipe_src_h); | |
e41a56be | 10151 | |
e29c22c0 | 10152 | encoder_retry: |
ef1b460d | 10153 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10154 | pipe_config->port_clock = 0; |
ef1b460d | 10155 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10156 | |
135c81b8 | 10157 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 10158 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 10159 | |
7758a113 DV |
10160 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10161 | * adjust it according to limitations or connector properties, and also | |
10162 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10163 | */ |
b2784e15 | 10164 | for_each_intel_encoder(dev, encoder) { |
47f1c6c9 | 10165 | |
7758a113 DV |
10166 | if (&encoder->new_crtc->base != crtc) |
10167 | continue; | |
7ae89233 | 10168 | |
efea6e8e DV |
10169 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10170 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10171 | goto fail; |
10172 | } | |
ee7b9f93 | 10173 | } |
47f1c6c9 | 10174 | |
ff9a6750 DV |
10175 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10176 | * done afterwards in case the encoder adjusts the mode. */ | |
10177 | if (!pipe_config->port_clock) | |
241bfc38 DL |
10178 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
10179 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 10180 | |
a43f6e0f | 10181 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10182 | if (ret < 0) { |
7758a113 DV |
10183 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10184 | goto fail; | |
ee7b9f93 | 10185 | } |
e29c22c0 DV |
10186 | |
10187 | if (ret == RETRY) { | |
10188 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10189 | ret = -EINVAL; | |
10190 | goto fail; | |
10191 | } | |
10192 | ||
10193 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10194 | retry = false; | |
10195 | goto encoder_retry; | |
10196 | } | |
10197 | ||
4e53c2e0 DV |
10198 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10199 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10200 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10201 | ||
b8cecdf5 | 10202 | return pipe_config; |
7758a113 | 10203 | fail: |
b8cecdf5 | 10204 | kfree(pipe_config); |
e29c22c0 | 10205 | return ERR_PTR(ret); |
ee7b9f93 | 10206 | } |
47f1c6c9 | 10207 | |
e2e1ed41 DV |
10208 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10209 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10210 | static void | |
10211 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10212 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10213 | { |
10214 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10215 | struct drm_device *dev = crtc->dev; |
10216 | struct intel_encoder *encoder; | |
10217 | struct intel_connector *connector; | |
10218 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10219 | |
e2e1ed41 | 10220 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10221 | |
e2e1ed41 DV |
10222 | /* Check which crtcs have changed outputs connected to them, these need |
10223 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10224 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10225 | * bit set at most. */ | |
10226 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10227 | base.head) { | |
10228 | if (connector->base.encoder == &connector->new_encoder->base) | |
10229 | continue; | |
79e53945 | 10230 | |
e2e1ed41 DV |
10231 | if (connector->base.encoder) { |
10232 | tmp_crtc = connector->base.encoder->crtc; | |
10233 | ||
10234 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10235 | } | |
10236 | ||
10237 | if (connector->new_encoder) | |
10238 | *prepare_pipes |= | |
10239 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10240 | } |
10241 | ||
b2784e15 | 10242 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
10243 | if (encoder->base.crtc == &encoder->new_crtc->base) |
10244 | continue; | |
10245 | ||
10246 | if (encoder->base.crtc) { | |
10247 | tmp_crtc = encoder->base.crtc; | |
10248 | ||
10249 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10250 | } | |
10251 | ||
10252 | if (encoder->new_crtc) | |
10253 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10254 | } |
10255 | ||
7668851f | 10256 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10257 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10258 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 10259 | continue; |
7e7d76c3 | 10260 | |
7668851f | 10261 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10262 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10263 | else |
10264 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10265 | } |
10266 | ||
e2e1ed41 DV |
10267 | |
10268 | /* set_mode is also used to update properties on life display pipes. */ | |
10269 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10270 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10271 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10272 | ||
b6c5164d DV |
10273 | /* |
10274 | * For simplicity do a full modeset on any pipe where the output routing | |
10275 | * changed. We could be more clever, but that would require us to be | |
10276 | * more careful with calling the relevant encoder->mode_set functions. | |
10277 | */ | |
e2e1ed41 DV |
10278 | if (*prepare_pipes) |
10279 | *modeset_pipes = *prepare_pipes; | |
10280 | ||
10281 | /* ... and mask these out. */ | |
10282 | *modeset_pipes &= ~(*disable_pipes); | |
10283 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10284 | |
10285 | /* | |
10286 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10287 | * obies this rule, but the modeset restore mode of | |
10288 | * intel_modeset_setup_hw_state does not. | |
10289 | */ | |
10290 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10291 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10292 | |
10293 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10294 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10295 | } |
79e53945 | 10296 | |
ea9d758d | 10297 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10298 | { |
ea9d758d | 10299 | struct drm_encoder *encoder; |
f6e5b160 | 10300 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10301 | |
ea9d758d DV |
10302 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10303 | if (encoder->crtc == crtc) | |
10304 | return true; | |
10305 | ||
10306 | return false; | |
10307 | } | |
10308 | ||
10309 | static void | |
10310 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10311 | { | |
ba41c0de | 10312 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
10313 | struct intel_encoder *intel_encoder; |
10314 | struct intel_crtc *intel_crtc; | |
10315 | struct drm_connector *connector; | |
10316 | ||
ba41c0de DV |
10317 | intel_shared_dpll_commit(dev_priv); |
10318 | ||
b2784e15 | 10319 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
10320 | if (!intel_encoder->base.crtc) |
10321 | continue; | |
10322 | ||
10323 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10324 | ||
10325 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10326 | intel_encoder->connectors_active = false; | |
10327 | } | |
10328 | ||
10329 | intel_modeset_commit_output_state(dev); | |
10330 | ||
7668851f | 10331 | /* Double check state. */ |
d3fcc808 | 10332 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10333 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
10334 | WARN_ON(intel_crtc->new_config && |
10335 | intel_crtc->new_config != &intel_crtc->config); | |
10336 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
10337 | } |
10338 | ||
10339 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10340 | if (!connector->encoder || !connector->encoder->crtc) | |
10341 | continue; | |
10342 | ||
10343 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10344 | ||
10345 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10346 | struct drm_property *dpms_property = |
10347 | dev->mode_config.dpms_property; | |
10348 | ||
ea9d758d | 10349 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10350 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10351 | dpms_property, |
10352 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10353 | |
10354 | intel_encoder = to_intel_encoder(connector->encoder); | |
10355 | intel_encoder->connectors_active = true; | |
10356 | } | |
10357 | } | |
10358 | ||
10359 | } | |
10360 | ||
3bd26263 | 10361 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10362 | { |
3bd26263 | 10363 | int diff; |
f1f644dc JB |
10364 | |
10365 | if (clock1 == clock2) | |
10366 | return true; | |
10367 | ||
10368 | if (!clock1 || !clock2) | |
10369 | return false; | |
10370 | ||
10371 | diff = abs(clock1 - clock2); | |
10372 | ||
10373 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10374 | return true; | |
10375 | ||
10376 | return false; | |
10377 | } | |
10378 | ||
25c5b266 DV |
10379 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10380 | list_for_each_entry((intel_crtc), \ | |
10381 | &(dev)->mode_config.crtc_list, \ | |
10382 | base.head) \ | |
0973f18f | 10383 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10384 | |
0e8ffe1b | 10385 | static bool |
2fa2fe9a DV |
10386 | intel_pipe_config_compare(struct drm_device *dev, |
10387 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
10388 | struct intel_crtc_config *pipe_config) |
10389 | { | |
66e985c0 DV |
10390 | #define PIPE_CONF_CHECK_X(name) \ |
10391 | if (current_config->name != pipe_config->name) { \ | |
10392 | DRM_ERROR("mismatch in " #name " " \ | |
10393 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10394 | current_config->name, \ | |
10395 | pipe_config->name); \ | |
10396 | return false; \ | |
10397 | } | |
10398 | ||
08a24034 DV |
10399 | #define PIPE_CONF_CHECK_I(name) \ |
10400 | if (current_config->name != pipe_config->name) { \ | |
10401 | DRM_ERROR("mismatch in " #name " " \ | |
10402 | "(expected %i, found %i)\n", \ | |
10403 | current_config->name, \ | |
10404 | pipe_config->name); \ | |
10405 | return false; \ | |
88adfff1 DV |
10406 | } |
10407 | ||
b95af8be VK |
10408 | /* This is required for BDW+ where there is only one set of registers for |
10409 | * switching between high and low RR. | |
10410 | * This macro can be used whenever a comparison has to be made between one | |
10411 | * hw state and multiple sw state variables. | |
10412 | */ | |
10413 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
10414 | if ((current_config->name != pipe_config->name) && \ | |
10415 | (current_config->alt_name != pipe_config->name)) { \ | |
10416 | DRM_ERROR("mismatch in " #name " " \ | |
10417 | "(expected %i or %i, found %i)\n", \ | |
10418 | current_config->name, \ | |
10419 | current_config->alt_name, \ | |
10420 | pipe_config->name); \ | |
10421 | return false; \ | |
10422 | } | |
10423 | ||
1bd1bd80 DV |
10424 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10425 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10426 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10427 | "(expected %i, found %i)\n", \ |
10428 | current_config->name & (mask), \ | |
10429 | pipe_config->name & (mask)); \ | |
10430 | return false; \ | |
10431 | } | |
10432 | ||
5e550656 VS |
10433 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10434 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10435 | DRM_ERROR("mismatch in " #name " " \ | |
10436 | "(expected %i, found %i)\n", \ | |
10437 | current_config->name, \ | |
10438 | pipe_config->name); \ | |
10439 | return false; \ | |
10440 | } | |
10441 | ||
bb760063 DV |
10442 | #define PIPE_CONF_QUIRK(quirk) \ |
10443 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10444 | ||
eccb140b DV |
10445 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10446 | ||
08a24034 DV |
10447 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10448 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10449 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10450 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10451 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10452 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10453 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10454 | |
eb14cb74 | 10455 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
10456 | |
10457 | if (INTEL_INFO(dev)->gen < 8) { | |
10458 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10459 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10460 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10461 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10462 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10463 | ||
10464 | if (current_config->has_drrs) { | |
10465 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
10466 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
10467 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
10468 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
10469 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
10470 | } | |
10471 | } else { | |
10472 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
10473 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
10474 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
10475 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
10476 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
10477 | } | |
eb14cb74 | 10478 | |
1bd1bd80 DV |
10479 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
10480 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
10481 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
10482 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
10483 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
10484 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
10485 | ||
10486 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
10487 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
10488 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
10489 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
10490 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
10491 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
10492 | ||
c93f54cf | 10493 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10494 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10495 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10496 | IS_VALLEYVIEW(dev)) | |
10497 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 10498 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 10499 | |
9ed109a7 DV |
10500 | PIPE_CONF_CHECK_I(has_audio); |
10501 | ||
1bd1bd80 DV |
10502 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10503 | DRM_MODE_FLAG_INTERLACE); | |
10504 | ||
bb760063 DV |
10505 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10506 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10507 | DRM_MODE_FLAG_PHSYNC); | |
10508 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10509 | DRM_MODE_FLAG_NHSYNC); | |
10510 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10511 | DRM_MODE_FLAG_PVSYNC); | |
10512 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10513 | DRM_MODE_FLAG_NVSYNC); | |
10514 | } | |
045ac3b5 | 10515 | |
37327abd VS |
10516 | PIPE_CONF_CHECK_I(pipe_src_w); |
10517 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10518 | |
9953599b DV |
10519 | /* |
10520 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10521 | * screen. Since we don't yet re-compute the pipe config when moving | |
10522 | * just the lvds port away to another pipe the sw tracking won't match. | |
10523 | * | |
10524 | * Proper atomic modesets with recomputed global state will fix this. | |
10525 | * Until then just don't check gmch state for inherited modes. | |
10526 | */ | |
10527 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10528 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10529 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10530 | if (INTEL_INFO(dev)->gen < 4) | |
10531 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10532 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10533 | } | |
10534 | ||
fd4daa9c CW |
10535 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10536 | if (current_config->pch_pfit.enabled) { | |
10537 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10538 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10539 | } | |
2fa2fe9a | 10540 | |
e59150dc JB |
10541 | /* BDW+ don't expose a synchronous way to read the state */ |
10542 | if (IS_HASWELL(dev)) | |
10543 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10544 | |
282740f7 VS |
10545 | PIPE_CONF_CHECK_I(double_wide); |
10546 | ||
26804afd DV |
10547 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
10548 | ||
c0d43d62 | 10549 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10550 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10551 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10552 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10553 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 10554 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
10555 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
10556 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
10557 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 10558 | |
42571aef VS |
10559 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10560 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10561 | ||
a9a7e98a JB |
10562 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10563 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10564 | |
66e985c0 | 10565 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10566 | #undef PIPE_CONF_CHECK_I |
b95af8be | 10567 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 10568 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10569 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10570 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10571 | |
0e8ffe1b DV |
10572 | return true; |
10573 | } | |
10574 | ||
08db6652 DL |
10575 | static void check_wm_state(struct drm_device *dev) |
10576 | { | |
10577 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10578 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
10579 | struct intel_crtc *intel_crtc; | |
10580 | int plane; | |
10581 | ||
10582 | if (INTEL_INFO(dev)->gen < 9) | |
10583 | return; | |
10584 | ||
10585 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
10586 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
10587 | ||
10588 | for_each_intel_crtc(dev, intel_crtc) { | |
10589 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
10590 | const enum pipe pipe = intel_crtc->pipe; | |
10591 | ||
10592 | if (!intel_crtc->active) | |
10593 | continue; | |
10594 | ||
10595 | /* planes */ | |
10596 | for_each_plane(pipe, plane) { | |
10597 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
10598 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
10599 | ||
10600 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
10601 | continue; | |
10602 | ||
10603 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
10604 | "(expected (%u,%u), found (%u,%u))\n", | |
10605 | pipe_name(pipe), plane + 1, | |
10606 | sw_entry->start, sw_entry->end, | |
10607 | hw_entry->start, hw_entry->end); | |
10608 | } | |
10609 | ||
10610 | /* cursor */ | |
10611 | hw_entry = &hw_ddb.cursor[pipe]; | |
10612 | sw_entry = &sw_ddb->cursor[pipe]; | |
10613 | ||
10614 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
10615 | continue; | |
10616 | ||
10617 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
10618 | "(expected (%u,%u), found (%u,%u))\n", | |
10619 | pipe_name(pipe), | |
10620 | sw_entry->start, sw_entry->end, | |
10621 | hw_entry->start, hw_entry->end); | |
10622 | } | |
10623 | } | |
10624 | ||
91d1b4bd DV |
10625 | static void |
10626 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10627 | { |
8af6cf88 DV |
10628 | struct intel_connector *connector; |
10629 | ||
10630 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10631 | base.head) { | |
10632 | /* This also checks the encoder/connector hw state with the | |
10633 | * ->get_hw_state callbacks. */ | |
10634 | intel_connector_check_state(connector); | |
10635 | ||
e2c719b7 | 10636 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
10637 | "connector's staged encoder doesn't match current encoder\n"); |
10638 | } | |
91d1b4bd DV |
10639 | } |
10640 | ||
10641 | static void | |
10642 | check_encoder_state(struct drm_device *dev) | |
10643 | { | |
10644 | struct intel_encoder *encoder; | |
10645 | struct intel_connector *connector; | |
8af6cf88 | 10646 | |
b2784e15 | 10647 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10648 | bool enabled = false; |
10649 | bool active = false; | |
10650 | enum pipe pipe, tracked_pipe; | |
10651 | ||
10652 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10653 | encoder->base.base.id, | |
8e329a03 | 10654 | encoder->base.name); |
8af6cf88 | 10655 | |
e2c719b7 | 10656 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 10657 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 10658 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
10659 | "encoder's active_connectors set, but no crtc\n"); |
10660 | ||
10661 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10662 | base.head) { | |
10663 | if (connector->base.encoder != &encoder->base) | |
10664 | continue; | |
10665 | enabled = true; | |
10666 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10667 | active = true; | |
10668 | } | |
0e32b39c DA |
10669 | /* |
10670 | * for MST connectors if we unplug the connector is gone | |
10671 | * away but the encoder is still connected to a crtc | |
10672 | * until a modeset happens in response to the hotplug. | |
10673 | */ | |
10674 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
10675 | continue; | |
10676 | ||
e2c719b7 | 10677 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
10678 | "encoder's enabled state mismatch " |
10679 | "(expected %i, found %i)\n", | |
10680 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 10681 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
10682 | "active encoder with no crtc\n"); |
10683 | ||
e2c719b7 | 10684 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
10685 | "encoder's computed active state doesn't match tracked active state " |
10686 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10687 | ||
10688 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 10689 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
10690 | "encoder's hw state doesn't match sw tracking " |
10691 | "(expected %i, found %i)\n", | |
10692 | encoder->connectors_active, active); | |
10693 | ||
10694 | if (!encoder->base.crtc) | |
10695 | continue; | |
10696 | ||
10697 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 10698 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
10699 | "active encoder's pipe doesn't match" |
10700 | "(expected %i, found %i)\n", | |
10701 | tracked_pipe, pipe); | |
10702 | ||
10703 | } | |
91d1b4bd DV |
10704 | } |
10705 | ||
10706 | static void | |
10707 | check_crtc_state(struct drm_device *dev) | |
10708 | { | |
fbee40df | 10709 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10710 | struct intel_crtc *crtc; |
10711 | struct intel_encoder *encoder; | |
10712 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10713 | |
d3fcc808 | 10714 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10715 | bool enabled = false; |
10716 | bool active = false; | |
10717 | ||
045ac3b5 JB |
10718 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10719 | ||
8af6cf88 DV |
10720 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10721 | crtc->base.base.id); | |
10722 | ||
e2c719b7 | 10723 | I915_STATE_WARN(crtc->active && !crtc->base.enabled, |
8af6cf88 DV |
10724 | "active crtc, but not enabled in sw tracking\n"); |
10725 | ||
b2784e15 | 10726 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10727 | if (encoder->base.crtc != &crtc->base) |
10728 | continue; | |
10729 | enabled = true; | |
10730 | if (encoder->connectors_active) | |
10731 | active = true; | |
10732 | } | |
6c49f241 | 10733 | |
e2c719b7 | 10734 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
10735 | "crtc's computed active state doesn't match tracked active state " |
10736 | "(expected %i, found %i)\n", active, crtc->active); | |
e2c719b7 | 10737 | I915_STATE_WARN(enabled != crtc->base.enabled, |
8af6cf88 DV |
10738 | "crtc's computed enabled state doesn't match tracked enabled state " |
10739 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10740 | ||
0e8ffe1b DV |
10741 | active = dev_priv->display.get_pipe_config(crtc, |
10742 | &pipe_config); | |
d62cf62a | 10743 | |
b6b5d049 VS |
10744 | /* hw state is inconsistent with the pipe quirk */ |
10745 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
10746 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
10747 | active = crtc->active; |
10748 | ||
b2784e15 | 10749 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 10750 | enum pipe pipe; |
6c49f241 DV |
10751 | if (encoder->base.crtc != &crtc->base) |
10752 | continue; | |
1d37b689 | 10753 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10754 | encoder->get_config(encoder, &pipe_config); |
10755 | } | |
10756 | ||
e2c719b7 | 10757 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
10758 | "crtc active state doesn't match with hw state " |
10759 | "(expected %i, found %i)\n", crtc->active, active); | |
10760 | ||
c0b03411 DV |
10761 | if (active && |
10762 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
e2c719b7 | 10763 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
10764 | intel_dump_pipe_config(crtc, &pipe_config, |
10765 | "[hw state]"); | |
10766 | intel_dump_pipe_config(crtc, &crtc->config, | |
10767 | "[sw state]"); | |
10768 | } | |
8af6cf88 DV |
10769 | } |
10770 | } | |
10771 | ||
91d1b4bd DV |
10772 | static void |
10773 | check_shared_dpll_state(struct drm_device *dev) | |
10774 | { | |
fbee40df | 10775 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10776 | struct intel_crtc *crtc; |
10777 | struct intel_dpll_hw_state dpll_hw_state; | |
10778 | int i; | |
5358901f DV |
10779 | |
10780 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10781 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10782 | int enabled_crtcs = 0, active_crtcs = 0; | |
10783 | bool active; | |
10784 | ||
10785 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10786 | ||
10787 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10788 | ||
10789 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10790 | ||
e2c719b7 | 10791 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 10792 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 10793 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 10794 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 10795 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 10796 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 10797 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 10798 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
10799 | "pll on state mismatch (expected %i, found %i)\n", |
10800 | pll->on, active); | |
10801 | ||
d3fcc808 | 10802 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10803 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10804 | enabled_crtcs++; | |
10805 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10806 | active_crtcs++; | |
10807 | } | |
e2c719b7 | 10808 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
10809 | "pll active crtcs mismatch (expected %i, found %i)\n", |
10810 | pll->active, active_crtcs); | |
e2c719b7 | 10811 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 10812 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 10813 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 10814 | |
e2c719b7 | 10815 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
10816 | sizeof(dpll_hw_state)), |
10817 | "pll hw state mismatch\n"); | |
5358901f | 10818 | } |
8af6cf88 DV |
10819 | } |
10820 | ||
91d1b4bd DV |
10821 | void |
10822 | intel_modeset_check_state(struct drm_device *dev) | |
10823 | { | |
08db6652 | 10824 | check_wm_state(dev); |
91d1b4bd DV |
10825 | check_connector_state(dev); |
10826 | check_encoder_state(dev); | |
10827 | check_crtc_state(dev); | |
10828 | check_shared_dpll_state(dev); | |
10829 | } | |
10830 | ||
18442d08 VS |
10831 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10832 | int dotclock) | |
10833 | { | |
10834 | /* | |
10835 | * FDI already provided one idea for the dotclock. | |
10836 | * Yell if the encoder disagrees. | |
10837 | */ | |
241bfc38 | 10838 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10839 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10840 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10841 | } |
10842 | ||
80715b2f VS |
10843 | static void update_scanline_offset(struct intel_crtc *crtc) |
10844 | { | |
10845 | struct drm_device *dev = crtc->base.dev; | |
10846 | ||
10847 | /* | |
10848 | * The scanline counter increments at the leading edge of hsync. | |
10849 | * | |
10850 | * On most platforms it starts counting from vtotal-1 on the | |
10851 | * first active line. That means the scanline counter value is | |
10852 | * always one less than what we would expect. Ie. just after | |
10853 | * start of vblank, which also occurs at start of hsync (on the | |
10854 | * last active line), the scanline counter will read vblank_start-1. | |
10855 | * | |
10856 | * On gen2 the scanline counter starts counting from 1 instead | |
10857 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
10858 | * to keep the value positive), instead of adding one. | |
10859 | * | |
10860 | * On HSW+ the behaviour of the scanline counter depends on the output | |
10861 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
10862 | * there's an extra 1 line difference. So we need to add two instead of | |
10863 | * one to the value. | |
10864 | */ | |
10865 | if (IS_GEN2(dev)) { | |
10866 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
10867 | int vtotal; | |
10868 | ||
10869 | vtotal = mode->crtc_vtotal; | |
10870 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
10871 | vtotal /= 2; | |
10872 | ||
10873 | crtc->scanline_offset = vtotal - 1; | |
10874 | } else if (HAS_DDI(dev) && | |
409ee761 | 10875 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
10876 | crtc->scanline_offset = 2; |
10877 | } else | |
10878 | crtc->scanline_offset = 1; | |
10879 | } | |
10880 | ||
7f27126e JB |
10881 | static struct intel_crtc_config * |
10882 | intel_modeset_compute_config(struct drm_crtc *crtc, | |
10883 | struct drm_display_mode *mode, | |
10884 | struct drm_framebuffer *fb, | |
10885 | unsigned *modeset_pipes, | |
10886 | unsigned *prepare_pipes, | |
10887 | unsigned *disable_pipes) | |
10888 | { | |
10889 | struct intel_crtc_config *pipe_config = NULL; | |
10890 | ||
10891 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
10892 | prepare_pipes, disable_pipes); | |
10893 | ||
10894 | if ((*modeset_pipes) == 0) | |
10895 | goto out; | |
10896 | ||
10897 | /* | |
10898 | * Note this needs changes when we start tracking multiple modes | |
10899 | * and crtcs. At that point we'll need to compute the whole config | |
10900 | * (i.e. one pipe_config for each crtc) rather than just the one | |
10901 | * for this crtc. | |
10902 | */ | |
10903 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); | |
10904 | if (IS_ERR(pipe_config)) { | |
10905 | goto out; | |
10906 | } | |
10907 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, | |
10908 | "[modeset]"); | |
7f27126e JB |
10909 | |
10910 | out: | |
10911 | return pipe_config; | |
10912 | } | |
10913 | ||
f30da187 DV |
10914 | static int __intel_set_mode(struct drm_crtc *crtc, |
10915 | struct drm_display_mode *mode, | |
7f27126e JB |
10916 | int x, int y, struct drm_framebuffer *fb, |
10917 | struct intel_crtc_config *pipe_config, | |
10918 | unsigned modeset_pipes, | |
10919 | unsigned prepare_pipes, | |
10920 | unsigned disable_pipes) | |
a6778b3c DV |
10921 | { |
10922 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10923 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10924 | struct drm_display_mode *saved_mode; |
25c5b266 | 10925 | struct intel_crtc *intel_crtc; |
c0c36b94 | 10926 | int ret = 0; |
a6778b3c | 10927 | |
4b4b9238 | 10928 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10929 | if (!saved_mode) |
10930 | return -ENOMEM; | |
a6778b3c | 10931 | |
3ac18232 | 10932 | *saved_mode = crtc->mode; |
a6778b3c | 10933 | |
b9950a13 VS |
10934 | if (modeset_pipes) |
10935 | to_intel_crtc(crtc)->new_config = pipe_config; | |
10936 | ||
30a970c6 JB |
10937 | /* |
10938 | * See if the config requires any additional preparation, e.g. | |
10939 | * to adjust global state with pipes off. We need to do this | |
10940 | * here so we can get the modeset_pipe updated config for the new | |
10941 | * mode set on this crtc. For other crtcs we need to use the | |
10942 | * adjusted_mode bits in the crtc directly. | |
10943 | */ | |
c164f833 | 10944 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10945 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10946 | |
c164f833 VS |
10947 | /* may have added more to prepare_pipes than we should */ |
10948 | prepare_pipes &= ~disable_pipes; | |
10949 | } | |
10950 | ||
8bd31e67 ACO |
10951 | if (dev_priv->display.crtc_compute_clock) { |
10952 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
10953 | ||
10954 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
10955 | if (ret) | |
10956 | goto done; | |
10957 | ||
10958 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
10959 | ret = dev_priv->display.crtc_compute_clock(intel_crtc); | |
10960 | if (ret) { | |
10961 | intel_shared_dpll_abort_config(dev_priv); | |
10962 | goto done; | |
10963 | } | |
10964 | } | |
10965 | } | |
10966 | ||
460da916 DV |
10967 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10968 | intel_crtc_disable(&intel_crtc->base); | |
10969 | ||
ea9d758d DV |
10970 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10971 | if (intel_crtc->base.enabled) | |
10972 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10973 | } | |
a6778b3c | 10974 | |
6c4c86f5 DV |
10975 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10976 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
10977 | * |
10978 | * Note we'll need to fix this up when we start tracking multiple | |
10979 | * pipes; here we assume a single modeset_pipe and only track the | |
10980 | * single crtc and mode. | |
f6e5b160 | 10981 | */ |
b8cecdf5 | 10982 | if (modeset_pipes) { |
25c5b266 | 10983 | crtc->mode = *mode; |
b8cecdf5 DV |
10984 | /* mode_set/enable/disable functions rely on a correct pipe |
10985 | * config. */ | |
10986 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10987 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10988 | |
10989 | /* | |
10990 | * Calculate and store various constants which | |
10991 | * are later needed by vblank and swap-completion | |
10992 | * timestamping. They are derived from true hwmode. | |
10993 | */ | |
10994 | drm_calc_timestamping_constants(crtc, | |
10995 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10996 | } |
7758a113 | 10997 | |
ea9d758d DV |
10998 | /* Only after disabling all output pipelines that will be changed can we |
10999 | * update the the output configuration. */ | |
11000 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 11001 | |
50f6e502 | 11002 | modeset_update_crtc_power_domains(dev); |
47fab737 | 11003 | |
a6778b3c DV |
11004 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
11005 | * on the DPLL. | |
f6e5b160 | 11006 | */ |
25c5b266 | 11007 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
11008 | struct drm_plane *primary = intel_crtc->base.primary; |
11009 | int vdisplay, hdisplay; | |
4c10794f | 11010 | |
455a6808 GP |
11011 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
11012 | ret = primary->funcs->update_plane(primary, &intel_crtc->base, | |
11013 | fb, 0, 0, | |
11014 | hdisplay, vdisplay, | |
11015 | x << 16, y << 16, | |
11016 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
11017 | } |
11018 | ||
11019 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
11020 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11021 | update_scanline_offset(intel_crtc); | |
11022 | ||
25c5b266 | 11023 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 11024 | } |
a6778b3c | 11025 | |
a6778b3c DV |
11026 | /* FIXME: add subpixel order */ |
11027 | done: | |
4b4b9238 | 11028 | if (ret && crtc->enabled) |
3ac18232 | 11029 | crtc->mode = *saved_mode; |
a6778b3c | 11030 | |
b8cecdf5 | 11031 | kfree(pipe_config); |
3ac18232 | 11032 | kfree(saved_mode); |
a6778b3c | 11033 | return ret; |
f6e5b160 CW |
11034 | } |
11035 | ||
7f27126e JB |
11036 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
11037 | struct drm_display_mode *mode, | |
11038 | int x, int y, struct drm_framebuffer *fb, | |
11039 | struct intel_crtc_config *pipe_config, | |
11040 | unsigned modeset_pipes, | |
11041 | unsigned prepare_pipes, | |
11042 | unsigned disable_pipes) | |
f30da187 DV |
11043 | { |
11044 | int ret; | |
11045 | ||
7f27126e JB |
11046 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
11047 | prepare_pipes, disable_pipes); | |
f30da187 DV |
11048 | |
11049 | if (ret == 0) | |
11050 | intel_modeset_check_state(crtc->dev); | |
11051 | ||
11052 | return ret; | |
11053 | } | |
11054 | ||
7f27126e JB |
11055 | static int intel_set_mode(struct drm_crtc *crtc, |
11056 | struct drm_display_mode *mode, | |
11057 | int x, int y, struct drm_framebuffer *fb) | |
11058 | { | |
11059 | struct intel_crtc_config *pipe_config; | |
11060 | unsigned modeset_pipes, prepare_pipes, disable_pipes; | |
11061 | ||
11062 | pipe_config = intel_modeset_compute_config(crtc, mode, fb, | |
11063 | &modeset_pipes, | |
11064 | &prepare_pipes, | |
11065 | &disable_pipes); | |
11066 | ||
11067 | if (IS_ERR(pipe_config)) | |
11068 | return PTR_ERR(pipe_config); | |
11069 | ||
11070 | return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
11071 | modeset_pipes, prepare_pipes, | |
11072 | disable_pipes); | |
11073 | } | |
11074 | ||
c0c36b94 CW |
11075 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11076 | { | |
f4510a27 | 11077 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
11078 | } |
11079 | ||
25c5b266 DV |
11080 | #undef for_each_intel_crtc_masked |
11081 | ||
d9e55608 DV |
11082 | static void intel_set_config_free(struct intel_set_config *config) |
11083 | { | |
11084 | if (!config) | |
11085 | return; | |
11086 | ||
1aa4b628 DV |
11087 | kfree(config->save_connector_encoders); |
11088 | kfree(config->save_encoder_crtcs); | |
7668851f | 11089 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11090 | kfree(config); |
11091 | } | |
11092 | ||
85f9eb71 DV |
11093 | static int intel_set_config_save_state(struct drm_device *dev, |
11094 | struct intel_set_config *config) | |
11095 | { | |
7668851f | 11096 | struct drm_crtc *crtc; |
85f9eb71 DV |
11097 | struct drm_encoder *encoder; |
11098 | struct drm_connector *connector; | |
11099 | int count; | |
11100 | ||
7668851f VS |
11101 | config->save_crtc_enabled = |
11102 | kcalloc(dev->mode_config.num_crtc, | |
11103 | sizeof(bool), GFP_KERNEL); | |
11104 | if (!config->save_crtc_enabled) | |
11105 | return -ENOMEM; | |
11106 | ||
1aa4b628 DV |
11107 | config->save_encoder_crtcs = |
11108 | kcalloc(dev->mode_config.num_encoder, | |
11109 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11110 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11111 | return -ENOMEM; |
11112 | ||
1aa4b628 DV |
11113 | config->save_connector_encoders = |
11114 | kcalloc(dev->mode_config.num_connector, | |
11115 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11116 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11117 | return -ENOMEM; |
11118 | ||
11119 | /* Copy data. Note that driver private data is not affected. | |
11120 | * Should anything bad happen only the expected state is | |
11121 | * restored, not the drivers personal bookkeeping. | |
11122 | */ | |
7668851f | 11123 | count = 0; |
70e1e0ec | 11124 | for_each_crtc(dev, crtc) { |
7668851f VS |
11125 | config->save_crtc_enabled[count++] = crtc->enabled; |
11126 | } | |
11127 | ||
85f9eb71 DV |
11128 | count = 0; |
11129 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11130 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11131 | } |
11132 | ||
11133 | count = 0; | |
11134 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11135 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11136 | } |
11137 | ||
11138 | return 0; | |
11139 | } | |
11140 | ||
11141 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11142 | struct intel_set_config *config) | |
11143 | { | |
7668851f | 11144 | struct intel_crtc *crtc; |
9a935856 DV |
11145 | struct intel_encoder *encoder; |
11146 | struct intel_connector *connector; | |
85f9eb71 DV |
11147 | int count; |
11148 | ||
7668851f | 11149 | count = 0; |
d3fcc808 | 11150 | for_each_intel_crtc(dev, crtc) { |
7668851f | 11151 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
11152 | |
11153 | if (crtc->new_enabled) | |
11154 | crtc->new_config = &crtc->config; | |
11155 | else | |
11156 | crtc->new_config = NULL; | |
7668851f VS |
11157 | } |
11158 | ||
85f9eb71 | 11159 | count = 0; |
b2784e15 | 11160 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11161 | encoder->new_crtc = |
11162 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11163 | } |
11164 | ||
11165 | count = 0; | |
9a935856 DV |
11166 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
11167 | connector->new_encoder = | |
11168 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
11169 | } |
11170 | } | |
11171 | ||
e3de42b6 | 11172 | static bool |
2e57f47d | 11173 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
11174 | { |
11175 | int i; | |
11176 | ||
2e57f47d CW |
11177 | if (set->num_connectors == 0) |
11178 | return false; | |
11179 | ||
11180 | if (WARN_ON(set->connectors == NULL)) | |
11181 | return false; | |
11182 | ||
11183 | for (i = 0; i < set->num_connectors; i++) | |
11184 | if (set->connectors[i]->encoder && | |
11185 | set->connectors[i]->encoder->crtc == set->crtc && | |
11186 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
11187 | return true; |
11188 | ||
11189 | return false; | |
11190 | } | |
11191 | ||
5e2b584e DV |
11192 | static void |
11193 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
11194 | struct intel_set_config *config) | |
11195 | { | |
11196 | ||
11197 | /* We should be able to check here if the fb has the same properties | |
11198 | * and then just flip_or_move it */ | |
2e57f47d CW |
11199 | if (is_crtc_connector_off(set)) { |
11200 | config->mode_changed = true; | |
f4510a27 | 11201 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
11202 | /* |
11203 | * If we have no fb, we can only flip as long as the crtc is | |
11204 | * active, otherwise we need a full mode set. The crtc may | |
11205 | * be active if we've only disabled the primary plane, or | |
11206 | * in fastboot situations. | |
11207 | */ | |
f4510a27 | 11208 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
11209 | struct intel_crtc *intel_crtc = |
11210 | to_intel_crtc(set->crtc); | |
11211 | ||
3b150f08 | 11212 | if (intel_crtc->active) { |
319d9827 JB |
11213 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
11214 | config->fb_changed = true; | |
11215 | } else { | |
11216 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
11217 | config->mode_changed = true; | |
11218 | } | |
5e2b584e DV |
11219 | } else if (set->fb == NULL) { |
11220 | config->mode_changed = true; | |
72f4901e | 11221 | } else if (set->fb->pixel_format != |
f4510a27 | 11222 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 11223 | config->mode_changed = true; |
e3de42b6 | 11224 | } else { |
5e2b584e | 11225 | config->fb_changed = true; |
e3de42b6 | 11226 | } |
5e2b584e DV |
11227 | } |
11228 | ||
835c5873 | 11229 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
11230 | config->fb_changed = true; |
11231 | ||
11232 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
11233 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
11234 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
11235 | drm_mode_debug_printmodeline(set->mode); | |
11236 | config->mode_changed = true; | |
11237 | } | |
a1d95703 CW |
11238 | |
11239 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
11240 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
11241 | } |
11242 | ||
2e431051 | 11243 | static int |
9a935856 DV |
11244 | intel_modeset_stage_output_state(struct drm_device *dev, |
11245 | struct drm_mode_set *set, | |
11246 | struct intel_set_config *config) | |
50f56119 | 11247 | { |
9a935856 DV |
11248 | struct intel_connector *connector; |
11249 | struct intel_encoder *encoder; | |
7668851f | 11250 | struct intel_crtc *crtc; |
f3f08572 | 11251 | int ro; |
50f56119 | 11252 | |
9abdda74 | 11253 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11254 | * of connectors. For paranoia, double-check this. */ |
11255 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11256 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11257 | ||
9a935856 DV |
11258 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11259 | base.head) { | |
11260 | /* Otherwise traverse passed in connector list and get encoders | |
11261 | * for them. */ | |
50f56119 | 11262 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 11263 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 11264 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
11265 | break; |
11266 | } | |
11267 | } | |
11268 | ||
9a935856 DV |
11269 | /* If we disable the crtc, disable all its connectors. Also, if |
11270 | * the connector is on the changing crtc but not on the new | |
11271 | * connector list, disable it. */ | |
11272 | if ((!set->fb || ro == set->num_connectors) && | |
11273 | connector->base.encoder && | |
11274 | connector->base.encoder->crtc == set->crtc) { | |
11275 | connector->new_encoder = NULL; | |
11276 | ||
11277 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11278 | connector->base.base.id, | |
c23cc417 | 11279 | connector->base.name); |
9a935856 DV |
11280 | } |
11281 | ||
11282 | ||
11283 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 11284 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 11285 | config->mode_changed = true; |
50f56119 DV |
11286 | } |
11287 | } | |
9a935856 | 11288 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11289 | |
9a935856 | 11290 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
11291 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11292 | base.head) { | |
7668851f VS |
11293 | struct drm_crtc *new_crtc; |
11294 | ||
9a935856 | 11295 | if (!connector->new_encoder) |
50f56119 DV |
11296 | continue; |
11297 | ||
9a935856 | 11298 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11299 | |
11300 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11301 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11302 | new_crtc = set->crtc; |
11303 | } | |
11304 | ||
11305 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11306 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11307 | new_crtc)) { | |
5e2b584e | 11308 | return -EINVAL; |
50f56119 | 11309 | } |
0e32b39c | 11310 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 DV |
11311 | |
11312 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
11313 | connector->base.base.id, | |
c23cc417 | 11314 | connector->base.name, |
9a935856 DV |
11315 | new_crtc->base.id); |
11316 | } | |
11317 | ||
11318 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 11319 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 11320 | int num_connectors = 0; |
9a935856 DV |
11321 | list_for_each_entry(connector, |
11322 | &dev->mode_config.connector_list, | |
11323 | base.head) { | |
11324 | if (connector->new_encoder == encoder) { | |
11325 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11326 | num_connectors++; |
9a935856 DV |
11327 | } |
11328 | } | |
5a65f358 PZ |
11329 | |
11330 | if (num_connectors == 0) | |
11331 | encoder->new_crtc = NULL; | |
11332 | else if (num_connectors > 1) | |
11333 | return -EINVAL; | |
11334 | ||
9a935856 DV |
11335 | /* Only now check for crtc changes so we don't miss encoders |
11336 | * that will be disabled. */ | |
11337 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 11338 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 11339 | config->mode_changed = true; |
50f56119 DV |
11340 | } |
11341 | } | |
9a935856 | 11342 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
0e32b39c DA |
11343 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11344 | base.head) { | |
11345 | if (connector->new_encoder) | |
11346 | if (connector->new_encoder != connector->encoder) | |
11347 | connector->encoder = connector->new_encoder; | |
11348 | } | |
d3fcc808 | 11349 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11350 | crtc->new_enabled = false; |
11351 | ||
b2784e15 | 11352 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
11353 | if (encoder->new_crtc == crtc) { |
11354 | crtc->new_enabled = true; | |
11355 | break; | |
11356 | } | |
11357 | } | |
11358 | ||
11359 | if (crtc->new_enabled != crtc->base.enabled) { | |
11360 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
11361 | crtc->new_enabled ? "en" : "dis"); | |
11362 | config->mode_changed = true; | |
11363 | } | |
7bd0a8e7 VS |
11364 | |
11365 | if (crtc->new_enabled) | |
11366 | crtc->new_config = &crtc->config; | |
11367 | else | |
11368 | crtc->new_config = NULL; | |
7668851f VS |
11369 | } |
11370 | ||
2e431051 DV |
11371 | return 0; |
11372 | } | |
11373 | ||
7d00a1f5 VS |
11374 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11375 | { | |
11376 | struct drm_device *dev = crtc->base.dev; | |
11377 | struct intel_encoder *encoder; | |
11378 | struct intel_connector *connector; | |
11379 | ||
11380 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11381 | pipe_name(crtc->pipe)); | |
11382 | ||
11383 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
11384 | if (connector->new_encoder && | |
11385 | connector->new_encoder->new_crtc == crtc) | |
11386 | connector->new_encoder = NULL; | |
11387 | } | |
11388 | ||
b2784e15 | 11389 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
11390 | if (encoder->new_crtc == crtc) |
11391 | encoder->new_crtc = NULL; | |
11392 | } | |
11393 | ||
11394 | crtc->new_enabled = false; | |
7bd0a8e7 | 11395 | crtc->new_config = NULL; |
7d00a1f5 VS |
11396 | } |
11397 | ||
2e431051 DV |
11398 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11399 | { | |
11400 | struct drm_device *dev; | |
2e431051 DV |
11401 | struct drm_mode_set save_set; |
11402 | struct intel_set_config *config; | |
50f52756 JB |
11403 | struct intel_crtc_config *pipe_config; |
11404 | unsigned modeset_pipes, prepare_pipes, disable_pipes; | |
2e431051 | 11405 | int ret; |
2e431051 | 11406 | |
8d3e375e DV |
11407 | BUG_ON(!set); |
11408 | BUG_ON(!set->crtc); | |
11409 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11410 | |
7e53f3a4 DV |
11411 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11412 | BUG_ON(!set->mode && set->fb); | |
11413 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11414 | |
2e431051 DV |
11415 | if (set->fb) { |
11416 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11417 | set->crtc->base.id, set->fb->base.id, | |
11418 | (int)set->num_connectors, set->x, set->y); | |
11419 | } else { | |
11420 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11421 | } |
11422 | ||
11423 | dev = set->crtc->dev; | |
11424 | ||
11425 | ret = -ENOMEM; | |
11426 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
11427 | if (!config) | |
11428 | goto out_config; | |
11429 | ||
11430 | ret = intel_set_config_save_state(dev, config); | |
11431 | if (ret) | |
11432 | goto out_config; | |
11433 | ||
11434 | save_set.crtc = set->crtc; | |
11435 | save_set.mode = &set->crtc->mode; | |
11436 | save_set.x = set->crtc->x; | |
11437 | save_set.y = set->crtc->y; | |
f4510a27 | 11438 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
11439 | |
11440 | /* Compute whether we need a full modeset, only an fb base update or no | |
11441 | * change at all. In the future we might also check whether only the | |
11442 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
11443 | * such cases. */ | |
11444 | intel_set_config_compute_mode_changes(set, config); | |
11445 | ||
9a935856 | 11446 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
11447 | if (ret) |
11448 | goto fail; | |
11449 | ||
50f52756 JB |
11450 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
11451 | set->fb, | |
11452 | &modeset_pipes, | |
11453 | &prepare_pipes, | |
11454 | &disable_pipes); | |
20664591 | 11455 | if (IS_ERR(pipe_config)) { |
6ac0483b | 11456 | ret = PTR_ERR(pipe_config); |
50f52756 | 11457 | goto fail; |
20664591 | 11458 | } else if (pipe_config) { |
b9950a13 | 11459 | if (pipe_config->has_audio != |
20664591 JB |
11460 | to_intel_crtc(set->crtc)->config.has_audio) |
11461 | config->mode_changed = true; | |
11462 | ||
af15d2ce JB |
11463 | /* |
11464 | * Note we have an issue here with infoframes: current code | |
11465 | * only updates them on the full mode set path per hw | |
11466 | * requirements. So here we should be checking for any | |
11467 | * required changes and forcing a mode set. | |
11468 | */ | |
20664591 | 11469 | } |
50f52756 JB |
11470 | |
11471 | /* set_mode will free it in the mode_changed case */ | |
11472 | if (!config->mode_changed) | |
11473 | kfree(pipe_config); | |
11474 | ||
1f9954d0 JB |
11475 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
11476 | ||
5e2b584e | 11477 | if (config->mode_changed) { |
50f52756 JB |
11478 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
11479 | set->x, set->y, set->fb, pipe_config, | |
11480 | modeset_pipes, prepare_pipes, | |
11481 | disable_pipes); | |
5e2b584e | 11482 | } else if (config->fb_changed) { |
3b150f08 | 11483 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 GP |
11484 | struct drm_plane *primary = set->crtc->primary; |
11485 | int vdisplay, hdisplay; | |
3b150f08 | 11486 | |
455a6808 GP |
11487 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); |
11488 | ret = primary->funcs->update_plane(primary, set->crtc, set->fb, | |
11489 | 0, 0, hdisplay, vdisplay, | |
11490 | set->x << 16, set->y << 16, | |
11491 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
11492 | |
11493 | /* | |
11494 | * We need to make sure the primary plane is re-enabled if it | |
11495 | * has previously been turned off. | |
11496 | */ | |
11497 | if (!intel_crtc->primary_enabled && ret == 0) { | |
11498 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 11499 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
11500 | } |
11501 | ||
7ca51a3a JB |
11502 | /* |
11503 | * In the fastboot case this may be our only check of the | |
11504 | * state after boot. It would be better to only do it on | |
11505 | * the first update, but we don't have a nice way of doing that | |
11506 | * (and really, set_config isn't used much for high freq page | |
11507 | * flipping, so increasing its cost here shouldn't be a big | |
11508 | * deal). | |
11509 | */ | |
d330a953 | 11510 | if (i915.fastboot && ret == 0) |
7ca51a3a | 11511 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
11512 | } |
11513 | ||
2d05eae1 | 11514 | if (ret) { |
bf67dfeb DV |
11515 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11516 | set->crtc->base.id, ret); | |
50f56119 | 11517 | fail: |
2d05eae1 | 11518 | intel_set_config_restore_state(dev, config); |
50f56119 | 11519 | |
7d00a1f5 VS |
11520 | /* |
11521 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
11522 | * force the pipe off to avoid oopsing in the modeset code | |
11523 | * due to fb==NULL. This should only happen during boot since | |
11524 | * we don't yet reconstruct the FB from the hardware state. | |
11525 | */ | |
11526 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
11527 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
11528 | ||
2d05eae1 CW |
11529 | /* Try to restore the config */ |
11530 | if (config->mode_changed && | |
11531 | intel_set_mode(save_set.crtc, save_set.mode, | |
11532 | save_set.x, save_set.y, save_set.fb)) | |
11533 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
11534 | } | |
50f56119 | 11535 | |
d9e55608 DV |
11536 | out_config: |
11537 | intel_set_config_free(config); | |
50f56119 DV |
11538 | return ret; |
11539 | } | |
f6e5b160 CW |
11540 | |
11541 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 11542 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 11543 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
11544 | .destroy = intel_crtc_destroy, |
11545 | .page_flip = intel_crtc_page_flip, | |
11546 | }; | |
11547 | ||
5358901f DV |
11548 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11549 | struct intel_shared_dpll *pll, | |
11550 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 11551 | { |
5358901f | 11552 | uint32_t val; |
ee7b9f93 | 11553 | |
f458ebbc | 11554 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
11555 | return false; |
11556 | ||
5358901f | 11557 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
11558 | hw_state->dpll = val; |
11559 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
11560 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
11561 | |
11562 | return val & DPLL_VCO_ENABLE; | |
11563 | } | |
11564 | ||
15bdd4cf DV |
11565 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11566 | struct intel_shared_dpll *pll) | |
11567 | { | |
3e369b76 ACO |
11568 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
11569 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
11570 | } |
11571 | ||
e7b903d2 DV |
11572 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11573 | struct intel_shared_dpll *pll) | |
11574 | { | |
e7b903d2 | 11575 | /* PCH refclock must be enabled first */ |
89eff4be | 11576 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 11577 | |
3e369b76 | 11578 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
11579 | |
11580 | /* Wait for the clocks to stabilize. */ | |
11581 | POSTING_READ(PCH_DPLL(pll->id)); | |
11582 | udelay(150); | |
11583 | ||
11584 | /* The pixel multiplier can only be updated once the | |
11585 | * DPLL is enabled and the clocks are stable. | |
11586 | * | |
11587 | * So write it again. | |
11588 | */ | |
3e369b76 | 11589 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 11590 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
11591 | udelay(200); |
11592 | } | |
11593 | ||
11594 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11595 | struct intel_shared_dpll *pll) | |
11596 | { | |
11597 | struct drm_device *dev = dev_priv->dev; | |
11598 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11599 | |
11600 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11601 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11602 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11603 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11604 | } |
11605 | ||
15bdd4cf DV |
11606 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11607 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11608 | udelay(200); |
11609 | } | |
11610 | ||
46edb027 DV |
11611 | static char *ibx_pch_dpll_names[] = { |
11612 | "PCH DPLL A", | |
11613 | "PCH DPLL B", | |
11614 | }; | |
11615 | ||
7c74ade1 | 11616 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11617 | { |
e7b903d2 | 11618 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11619 | int i; |
11620 | ||
7c74ade1 | 11621 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11622 | |
e72f9fbf | 11623 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11624 | dev_priv->shared_dplls[i].id = i; |
11625 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11626 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11627 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11628 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11629 | dev_priv->shared_dplls[i].get_hw_state = |
11630 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11631 | } |
11632 | } | |
11633 | ||
7c74ade1 DV |
11634 | static void intel_shared_dpll_init(struct drm_device *dev) |
11635 | { | |
e7b903d2 | 11636 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 11637 | |
9cd86933 DV |
11638 | if (HAS_DDI(dev)) |
11639 | intel_ddi_pll_init(dev); | |
11640 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
11641 | ibx_pch_dpll_init(dev); |
11642 | else | |
11643 | dev_priv->num_shared_dpll = 0; | |
11644 | ||
11645 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11646 | } |
11647 | ||
6beb8c23 MR |
11648 | /** |
11649 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
11650 | * @plane: drm plane to prepare for | |
11651 | * @fb: framebuffer to prepare for presentation | |
11652 | * | |
11653 | * Prepares a framebuffer for usage on a display plane. Generally this | |
11654 | * involves pinning the underlying object and updating the frontbuffer tracking | |
11655 | * bits. Some older platforms need special physical address handling for | |
11656 | * cursor planes. | |
11657 | * | |
11658 | * Returns 0 on success, negative error code on failure. | |
11659 | */ | |
11660 | int | |
11661 | intel_prepare_plane_fb(struct drm_plane *plane, | |
11662 | struct drm_framebuffer *fb) | |
465c120c MR |
11663 | { |
11664 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
11665 | struct intel_plane *intel_plane = to_intel_plane(plane); |
11666 | enum pipe pipe = intel_plane->pipe; | |
11667 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11668 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
11669 | unsigned frontbuffer_bits = 0; | |
11670 | int ret = 0; | |
465c120c | 11671 | |
ea2c67bb | 11672 | if (!obj) |
465c120c MR |
11673 | return 0; |
11674 | ||
6beb8c23 MR |
11675 | switch (plane->type) { |
11676 | case DRM_PLANE_TYPE_PRIMARY: | |
11677 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
11678 | break; | |
11679 | case DRM_PLANE_TYPE_CURSOR: | |
11680 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
11681 | break; | |
11682 | case DRM_PLANE_TYPE_OVERLAY: | |
11683 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
11684 | break; | |
11685 | } | |
465c120c | 11686 | |
6beb8c23 | 11687 | mutex_lock(&dev->struct_mutex); |
465c120c | 11688 | |
6beb8c23 MR |
11689 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
11690 | INTEL_INFO(dev)->cursor_needs_physical) { | |
11691 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
11692 | ret = i915_gem_object_attach_phys(obj, align); | |
11693 | if (ret) | |
11694 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
11695 | } else { | |
11696 | ret = intel_pin_and_fence_fb_obj(plane, fb, NULL); | |
11697 | } | |
465c120c | 11698 | |
6beb8c23 MR |
11699 | if (ret == 0) |
11700 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 11701 | |
4c34574f | 11702 | mutex_unlock(&dev->struct_mutex); |
465c120c | 11703 | |
6beb8c23 MR |
11704 | return ret; |
11705 | } | |
11706 | ||
38f3ce3a MR |
11707 | /** |
11708 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
11709 | * @plane: drm plane to clean up for | |
11710 | * @fb: old framebuffer that was on plane | |
11711 | * | |
11712 | * Cleans up a framebuffer that has just been removed from a plane. | |
11713 | */ | |
11714 | void | |
11715 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
11716 | struct drm_framebuffer *fb) | |
11717 | { | |
11718 | struct drm_device *dev = plane->dev; | |
11719 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11720 | ||
11721 | if (WARN_ON(!obj)) | |
11722 | return; | |
11723 | ||
11724 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
11725 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
11726 | mutex_lock(&dev->struct_mutex); | |
11727 | intel_unpin_fb_obj(obj); | |
11728 | mutex_unlock(&dev->struct_mutex); | |
11729 | } | |
465c120c MR |
11730 | } |
11731 | ||
11732 | static int | |
3c692a41 GP |
11733 | intel_check_primary_plane(struct drm_plane *plane, |
11734 | struct intel_plane_state *state) | |
11735 | { | |
32b7eeec MR |
11736 | struct drm_device *dev = plane->dev; |
11737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 11738 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 11739 | struct intel_crtc *intel_crtc; |
32b7eeec | 11740 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2b875c22 | 11741 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
11742 | struct drm_rect *dest = &state->dst; |
11743 | struct drm_rect *src = &state->src; | |
11744 | const struct drm_rect *clip = &state->clip; | |
465c120c MR |
11745 | int ret; |
11746 | ||
ea2c67bb MR |
11747 | crtc = crtc ? crtc : plane->crtc; |
11748 | intel_crtc = to_intel_crtc(crtc); | |
11749 | ||
c59cb179 MR |
11750 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
11751 | src, dest, clip, | |
11752 | DRM_PLANE_HELPER_NO_SCALING, | |
11753 | DRM_PLANE_HELPER_NO_SCALING, | |
11754 | false, true, &state->visible); | |
11755 | if (ret) | |
11756 | return ret; | |
465c120c | 11757 | |
32b7eeec MR |
11758 | if (intel_crtc->active) { |
11759 | intel_crtc->atomic.wait_for_flips = true; | |
11760 | ||
11761 | /* | |
11762 | * FBC does not work on some platforms for rotated | |
11763 | * planes, so disable it when rotation is not 0 and | |
11764 | * update it when rotation is set back to 0. | |
11765 | * | |
11766 | * FIXME: This is redundant with the fbc update done in | |
11767 | * the primary plane enable function except that that | |
11768 | * one is done too late. We eventually need to unify | |
11769 | * this. | |
11770 | */ | |
11771 | if (intel_crtc->primary_enabled && | |
11772 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11773 | dev_priv->fbc.plane == intel_crtc->plane && | |
11774 | intel_plane->rotation != BIT(DRM_ROTATE_0)) { | |
11775 | intel_crtc->atomic.disable_fbc = true; | |
11776 | } | |
11777 | ||
11778 | if (state->visible) { | |
11779 | /* | |
11780 | * BDW signals flip done immediately if the plane | |
11781 | * is disabled, even if the plane enable is already | |
11782 | * armed to occur at the next vblank :( | |
11783 | */ | |
11784 | if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled) | |
11785 | intel_crtc->atomic.wait_vblank = true; | |
11786 | } | |
11787 | ||
11788 | intel_crtc->atomic.fb_bits |= | |
11789 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
11790 | ||
11791 | intel_crtc->atomic.update_fbc = true; | |
ccc759dc GP |
11792 | } |
11793 | ||
14af293f GP |
11794 | return 0; |
11795 | } | |
11796 | ||
11797 | static void | |
11798 | intel_commit_primary_plane(struct drm_plane *plane, | |
11799 | struct intel_plane_state *state) | |
11800 | { | |
2b875c22 MR |
11801 | struct drm_crtc *crtc = state->base.crtc; |
11802 | struct drm_framebuffer *fb = state->base.fb; | |
11803 | struct drm_device *dev = plane->dev; | |
14af293f | 11804 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 11805 | struct intel_crtc *intel_crtc; |
14af293f | 11806 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
14af293f GP |
11807 | struct intel_plane *intel_plane = to_intel_plane(plane); |
11808 | struct drm_rect *src = &state->src; | |
11809 | ||
ea2c67bb MR |
11810 | crtc = crtc ? crtc : plane->crtc; |
11811 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
11812 | |
11813 | plane->fb = fb; | |
9dc806fc MR |
11814 | crtc->x = src->x1 >> 16; |
11815 | crtc->y = src->y1 >> 16; | |
ccc759dc | 11816 | |
ccc759dc | 11817 | intel_plane->obj = obj; |
4c34574f | 11818 | |
ccc759dc | 11819 | if (intel_crtc->active) { |
ccc759dc | 11820 | if (state->visible) { |
ccc759dc GP |
11821 | /* FIXME: kill this fastboot hack */ |
11822 | intel_update_pipe_size(intel_crtc); | |
465c120c | 11823 | |
ccc759dc | 11824 | intel_crtc->primary_enabled = true; |
465c120c | 11825 | |
ccc759dc GP |
11826 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
11827 | crtc->x, crtc->y); | |
ccc759dc GP |
11828 | } else { |
11829 | /* | |
11830 | * If clipping results in a non-visible primary plane, | |
11831 | * we'll disable the primary plane. Note that this is | |
11832 | * a bit different than what happens if userspace | |
11833 | * explicitly disables the plane by passing fb=0 | |
11834 | * because plane->fb still gets set and pinned. | |
11835 | */ | |
11836 | intel_disable_primary_hw_plane(plane, crtc); | |
48404c1e | 11837 | } |
ccc759dc | 11838 | } |
465c120c MR |
11839 | } |
11840 | ||
32b7eeec | 11841 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 11842 | { |
32b7eeec | 11843 | struct drm_device *dev = crtc->dev; |
140fd38d | 11844 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 11845 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
11846 | struct intel_plane *intel_plane; |
11847 | struct drm_plane *p; | |
11848 | unsigned fb_bits = 0; | |
11849 | ||
11850 | /* Track fb's for any planes being disabled */ | |
11851 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
11852 | intel_plane = to_intel_plane(p); | |
11853 | ||
11854 | if (intel_crtc->atomic.disabled_planes & | |
11855 | (1 << drm_plane_index(p))) { | |
11856 | switch (p->type) { | |
11857 | case DRM_PLANE_TYPE_PRIMARY: | |
11858 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
11859 | break; | |
11860 | case DRM_PLANE_TYPE_CURSOR: | |
11861 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
11862 | break; | |
11863 | case DRM_PLANE_TYPE_OVERLAY: | |
11864 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
11865 | break; | |
11866 | } | |
3c692a41 | 11867 | |
ea2c67bb MR |
11868 | mutex_lock(&dev->struct_mutex); |
11869 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
11870 | mutex_unlock(&dev->struct_mutex); | |
11871 | } | |
11872 | } | |
3c692a41 | 11873 | |
32b7eeec MR |
11874 | if (intel_crtc->atomic.wait_for_flips) |
11875 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 11876 | |
32b7eeec MR |
11877 | if (intel_crtc->atomic.disable_fbc) |
11878 | intel_fbc_disable(dev); | |
3c692a41 | 11879 | |
32b7eeec MR |
11880 | if (intel_crtc->atomic.pre_disable_primary) |
11881 | intel_pre_disable_primary(crtc); | |
3c692a41 | 11882 | |
32b7eeec MR |
11883 | if (intel_crtc->atomic.update_wm) |
11884 | intel_update_watermarks(crtc); | |
3c692a41 | 11885 | |
32b7eeec | 11886 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 11887 | |
c34c9ee4 MR |
11888 | /* Perform vblank evasion around commit operation */ |
11889 | if (intel_crtc->active) | |
11890 | intel_crtc->atomic.evade = | |
11891 | intel_pipe_update_start(intel_crtc, | |
11892 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
11893 | } |
11894 | ||
11895 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
11896 | { | |
11897 | struct drm_device *dev = crtc->dev; | |
11898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11899 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11900 | struct drm_plane *p; | |
11901 | ||
c34c9ee4 MR |
11902 | if (intel_crtc->atomic.evade) |
11903 | intel_pipe_update_end(intel_crtc, | |
11904 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 11905 | |
140fd38d | 11906 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 11907 | |
32b7eeec MR |
11908 | if (intel_crtc->atomic.wait_vblank) |
11909 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
11910 | ||
11911 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
11912 | ||
11913 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 11914 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 11915 | intel_fbc_update(dev); |
ccc759dc | 11916 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 11917 | } |
3c692a41 | 11918 | |
32b7eeec MR |
11919 | if (intel_crtc->atomic.post_enable_primary) |
11920 | intel_post_enable_primary(crtc); | |
3c692a41 | 11921 | |
32b7eeec MR |
11922 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
11923 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
11924 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
11925 | false, false); | |
11926 | ||
11927 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
11928 | } |
11929 | ||
cf4c7c12 | 11930 | /** |
4a3b8769 MR |
11931 | * intel_plane_destroy - destroy a plane |
11932 | * @plane: plane to destroy | |
cf4c7c12 | 11933 | * |
4a3b8769 MR |
11934 | * Common destruction function for all types of planes (primary, cursor, |
11935 | * sprite). | |
cf4c7c12 | 11936 | */ |
4a3b8769 | 11937 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
11938 | { |
11939 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11940 | drm_plane_cleanup(plane); | |
11941 | kfree(intel_plane); | |
11942 | } | |
11943 | ||
11944 | static const struct drm_plane_funcs intel_primary_plane_funcs = { | |
ea2c67bb MR |
11945 | .update_plane = drm_plane_helper_update, |
11946 | .disable_plane = drm_plane_helper_disable, | |
3d7d6510 | 11947 | .destroy = intel_plane_destroy, |
ea2c67bb MR |
11948 | .set_property = intel_plane_set_property, |
11949 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
11950 | .atomic_destroy_state = intel_plane_destroy_state, | |
11951 | ||
465c120c MR |
11952 | }; |
11953 | ||
11954 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
11955 | int pipe) | |
11956 | { | |
11957 | struct intel_plane *primary; | |
11958 | const uint32_t *intel_primary_formats; | |
11959 | int num_formats; | |
11960 | ||
11961 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
11962 | if (primary == NULL) | |
11963 | return NULL; | |
11964 | ||
ea2c67bb MR |
11965 | primary->base.state = intel_plane_duplicate_state(&primary->base); |
11966 | if (primary->base.state == NULL) { | |
11967 | kfree(primary); | |
11968 | return NULL; | |
11969 | } | |
11970 | ||
465c120c MR |
11971 | primary->can_scale = false; |
11972 | primary->max_downscale = 1; | |
11973 | primary->pipe = pipe; | |
11974 | primary->plane = pipe; | |
48404c1e | 11975 | primary->rotation = BIT(DRM_ROTATE_0); |
c59cb179 MR |
11976 | primary->check_plane = intel_check_primary_plane; |
11977 | primary->commit_plane = intel_commit_primary_plane; | |
465c120c MR |
11978 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
11979 | primary->plane = !pipe; | |
11980 | ||
11981 | if (INTEL_INFO(dev)->gen <= 3) { | |
11982 | intel_primary_formats = intel_primary_formats_gen2; | |
11983 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
11984 | } else { | |
11985 | intel_primary_formats = intel_primary_formats_gen4; | |
11986 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
11987 | } | |
11988 | ||
11989 | drm_universal_plane_init(dev, &primary->base, 0, | |
11990 | &intel_primary_plane_funcs, | |
11991 | intel_primary_formats, num_formats, | |
11992 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e SJ |
11993 | |
11994 | if (INTEL_INFO(dev)->gen >= 4) { | |
11995 | if (!dev->mode_config.rotation_property) | |
11996 | dev->mode_config.rotation_property = | |
11997 | drm_mode_create_rotation_property(dev, | |
11998 | BIT(DRM_ROTATE_0) | | |
11999 | BIT(DRM_ROTATE_180)); | |
12000 | if (dev->mode_config.rotation_property) | |
12001 | drm_object_attach_property(&primary->base.base, | |
12002 | dev->mode_config.rotation_property, | |
12003 | primary->rotation); | |
12004 | } | |
12005 | ||
ea2c67bb MR |
12006 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
12007 | ||
465c120c MR |
12008 | return &primary->base; |
12009 | } | |
12010 | ||
3d7d6510 | 12011 | static int |
852e787c GP |
12012 | intel_check_cursor_plane(struct drm_plane *plane, |
12013 | struct intel_plane_state *state) | |
3d7d6510 | 12014 | { |
2b875c22 | 12015 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12016 | struct drm_device *dev = plane->dev; |
2b875c22 | 12017 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
12018 | struct drm_rect *dest = &state->dst; |
12019 | struct drm_rect *src = &state->src; | |
12020 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 12021 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 12022 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
12023 | unsigned stride; |
12024 | int ret; | |
3d7d6510 | 12025 | |
ea2c67bb MR |
12026 | crtc = crtc ? crtc : plane->crtc; |
12027 | intel_crtc = to_intel_crtc(crtc); | |
12028 | ||
757f9a3e | 12029 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 12030 | src, dest, clip, |
3d7d6510 MR |
12031 | DRM_PLANE_HELPER_NO_SCALING, |
12032 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 12033 | true, true, &state->visible); |
757f9a3e GP |
12034 | if (ret) |
12035 | return ret; | |
12036 | ||
12037 | ||
12038 | /* if we want to turn off the cursor ignore width and height */ | |
12039 | if (!obj) | |
32b7eeec | 12040 | goto finish; |
757f9a3e | 12041 | |
757f9a3e | 12042 | /* Check for which cursor types we support */ |
ea2c67bb MR |
12043 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
12044 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
12045 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
12046 | return -EINVAL; |
12047 | } | |
12048 | ||
ea2c67bb MR |
12049 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
12050 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
12051 | DRM_DEBUG_KMS("buffer is too small\n"); |
12052 | return -ENOMEM; | |
12053 | } | |
12054 | ||
e391ea88 GP |
12055 | if (fb == crtc->cursor->fb) |
12056 | return 0; | |
12057 | ||
757f9a3e GP |
12058 | /* we only need to pin inside GTT if cursor is non-phy */ |
12059 | mutex_lock(&dev->struct_mutex); | |
12060 | if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) { | |
12061 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); | |
12062 | ret = -EINVAL; | |
12063 | } | |
12064 | mutex_unlock(&dev->struct_mutex); | |
12065 | ||
32b7eeec MR |
12066 | finish: |
12067 | if (intel_crtc->active) { | |
ea2c67bb | 12068 | if (intel_crtc->cursor_width != state->base.crtc_w) |
32b7eeec MR |
12069 | intel_crtc->atomic.update_wm = true; |
12070 | ||
12071 | intel_crtc->atomic.fb_bits |= | |
12072 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
12073 | } | |
12074 | ||
757f9a3e | 12075 | return ret; |
852e787c | 12076 | } |
3d7d6510 | 12077 | |
f4a2cf29 | 12078 | static void |
852e787c GP |
12079 | intel_commit_cursor_plane(struct drm_plane *plane, |
12080 | struct intel_plane_state *state) | |
12081 | { | |
2b875c22 | 12082 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
12083 | struct drm_device *dev = plane->dev; |
12084 | struct intel_crtc *intel_crtc; | |
a919db90 | 12085 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2b875c22 | 12086 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 12087 | uint32_t addr; |
852e787c | 12088 | |
ea2c67bb MR |
12089 | crtc = crtc ? crtc : plane->crtc; |
12090 | intel_crtc = to_intel_crtc(crtc); | |
12091 | ||
2b875c22 | 12092 | plane->fb = state->base.fb; |
ea2c67bb MR |
12093 | crtc->cursor_x = state->base.crtc_x; |
12094 | crtc->cursor_y = state->base.crtc_y; | |
12095 | ||
a919db90 SJ |
12096 | intel_plane->obj = obj; |
12097 | ||
a912f12f GP |
12098 | if (intel_crtc->cursor_bo == obj) |
12099 | goto update; | |
4ed91096 | 12100 | |
f4a2cf29 | 12101 | if (!obj) |
a912f12f | 12102 | addr = 0; |
f4a2cf29 | 12103 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 12104 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 12105 | else |
a912f12f | 12106 | addr = obj->phys_handle->busaddr; |
852e787c | 12107 | |
a912f12f GP |
12108 | intel_crtc->cursor_addr = addr; |
12109 | intel_crtc->cursor_bo = obj; | |
12110 | update: | |
ea2c67bb MR |
12111 | intel_crtc->cursor_width = state->base.crtc_w; |
12112 | intel_crtc->cursor_height = state->base.crtc_h; | |
852e787c | 12113 | |
32b7eeec | 12114 | if (intel_crtc->active) |
a912f12f | 12115 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
12116 | } |
12117 | ||
3d7d6510 | 12118 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { |
ea2c67bb MR |
12119 | .update_plane = drm_plane_helper_update, |
12120 | .disable_plane = drm_plane_helper_disable, | |
3d7d6510 | 12121 | .destroy = intel_plane_destroy, |
4398ad45 | 12122 | .set_property = intel_plane_set_property, |
ea2c67bb MR |
12123 | .atomic_duplicate_state = intel_plane_duplicate_state, |
12124 | .atomic_destroy_state = intel_plane_destroy_state, | |
3d7d6510 MR |
12125 | }; |
12126 | ||
12127 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, | |
12128 | int pipe) | |
12129 | { | |
12130 | struct intel_plane *cursor; | |
12131 | ||
12132 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
12133 | if (cursor == NULL) | |
12134 | return NULL; | |
12135 | ||
ea2c67bb MR |
12136 | cursor->base.state = intel_plane_duplicate_state(&cursor->base); |
12137 | if (cursor->base.state == NULL) { | |
12138 | kfree(cursor); | |
12139 | return NULL; | |
12140 | } | |
12141 | ||
3d7d6510 MR |
12142 | cursor->can_scale = false; |
12143 | cursor->max_downscale = 1; | |
12144 | cursor->pipe = pipe; | |
12145 | cursor->plane = pipe; | |
4398ad45 | 12146 | cursor->rotation = BIT(DRM_ROTATE_0); |
c59cb179 MR |
12147 | cursor->check_plane = intel_check_cursor_plane; |
12148 | cursor->commit_plane = intel_commit_cursor_plane; | |
3d7d6510 MR |
12149 | |
12150 | drm_universal_plane_init(dev, &cursor->base, 0, | |
12151 | &intel_cursor_plane_funcs, | |
12152 | intel_cursor_formats, | |
12153 | ARRAY_SIZE(intel_cursor_formats), | |
12154 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
12155 | |
12156 | if (INTEL_INFO(dev)->gen >= 4) { | |
12157 | if (!dev->mode_config.rotation_property) | |
12158 | dev->mode_config.rotation_property = | |
12159 | drm_mode_create_rotation_property(dev, | |
12160 | BIT(DRM_ROTATE_0) | | |
12161 | BIT(DRM_ROTATE_180)); | |
12162 | if (dev->mode_config.rotation_property) | |
12163 | drm_object_attach_property(&cursor->base.base, | |
12164 | dev->mode_config.rotation_property, | |
12165 | cursor->rotation); | |
12166 | } | |
12167 | ||
ea2c67bb MR |
12168 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
12169 | ||
3d7d6510 MR |
12170 | return &cursor->base; |
12171 | } | |
12172 | ||
b358d0a6 | 12173 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 12174 | { |
fbee40df | 12175 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 12176 | struct intel_crtc *intel_crtc; |
3d7d6510 MR |
12177 | struct drm_plane *primary = NULL; |
12178 | struct drm_plane *cursor = NULL; | |
465c120c | 12179 | int i, ret; |
79e53945 | 12180 | |
955382f3 | 12181 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
12182 | if (intel_crtc == NULL) |
12183 | return; | |
12184 | ||
465c120c | 12185 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
12186 | if (!primary) |
12187 | goto fail; | |
12188 | ||
12189 | cursor = intel_cursor_plane_create(dev, pipe); | |
12190 | if (!cursor) | |
12191 | goto fail; | |
12192 | ||
465c120c | 12193 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
12194 | cursor, &intel_crtc_funcs); |
12195 | if (ret) | |
12196 | goto fail; | |
79e53945 JB |
12197 | |
12198 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
12199 | for (i = 0; i < 256; i++) { |
12200 | intel_crtc->lut_r[i] = i; | |
12201 | intel_crtc->lut_g[i] = i; | |
12202 | intel_crtc->lut_b[i] = i; | |
12203 | } | |
12204 | ||
1f1c2e24 VS |
12205 | /* |
12206 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 12207 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 12208 | */ |
80824003 JB |
12209 | intel_crtc->pipe = pipe; |
12210 | intel_crtc->plane = pipe; | |
3a77c4c4 | 12211 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 12212 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 12213 | intel_crtc->plane = !pipe; |
80824003 JB |
12214 | } |
12215 | ||
4b0e333e CW |
12216 | intel_crtc->cursor_base = ~0; |
12217 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 12218 | intel_crtc->cursor_size = ~0; |
8d7849db | 12219 | |
22fd0fab JB |
12220 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
12221 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
12222 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
12223 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
12224 | ||
9362c7c5 ACO |
12225 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
12226 | ||
79e53945 | 12227 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
12228 | |
12229 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
12230 | return; |
12231 | ||
12232 | fail: | |
12233 | if (primary) | |
12234 | drm_plane_cleanup(primary); | |
12235 | if (cursor) | |
12236 | drm_plane_cleanup(cursor); | |
12237 | kfree(intel_crtc); | |
79e53945 JB |
12238 | } |
12239 | ||
752aa88a JB |
12240 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
12241 | { | |
12242 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 12243 | struct drm_device *dev = connector->base.dev; |
752aa88a | 12244 | |
51fd371b | 12245 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 12246 | |
d3babd3f | 12247 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
12248 | return INVALID_PIPE; |
12249 | ||
12250 | return to_intel_crtc(encoder->crtc)->pipe; | |
12251 | } | |
12252 | ||
08d7b3d1 | 12253 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 12254 | struct drm_file *file) |
08d7b3d1 | 12255 | { |
08d7b3d1 | 12256 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 12257 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 12258 | struct intel_crtc *crtc; |
08d7b3d1 | 12259 | |
1cff8f6b DV |
12260 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
12261 | return -ENODEV; | |
08d7b3d1 | 12262 | |
7707e653 | 12263 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 12264 | |
7707e653 | 12265 | if (!drmmode_crtc) { |
08d7b3d1 | 12266 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 12267 | return -ENOENT; |
08d7b3d1 CW |
12268 | } |
12269 | ||
7707e653 | 12270 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 12271 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 12272 | |
c05422d5 | 12273 | return 0; |
08d7b3d1 CW |
12274 | } |
12275 | ||
66a9278e | 12276 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 12277 | { |
66a9278e DV |
12278 | struct drm_device *dev = encoder->base.dev; |
12279 | struct intel_encoder *source_encoder; | |
79e53945 | 12280 | int index_mask = 0; |
79e53945 JB |
12281 | int entry = 0; |
12282 | ||
b2784e15 | 12283 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 12284 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
12285 | index_mask |= (1 << entry); |
12286 | ||
79e53945 JB |
12287 | entry++; |
12288 | } | |
4ef69c7a | 12289 | |
79e53945 JB |
12290 | return index_mask; |
12291 | } | |
12292 | ||
4d302442 CW |
12293 | static bool has_edp_a(struct drm_device *dev) |
12294 | { | |
12295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12296 | ||
12297 | if (!IS_MOBILE(dev)) | |
12298 | return false; | |
12299 | ||
12300 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
12301 | return false; | |
12302 | ||
e3589908 | 12303 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
12304 | return false; |
12305 | ||
12306 | return true; | |
12307 | } | |
12308 | ||
84b4e042 JB |
12309 | static bool intel_crt_present(struct drm_device *dev) |
12310 | { | |
12311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12312 | ||
884497ed DL |
12313 | if (INTEL_INFO(dev)->gen >= 9) |
12314 | return false; | |
12315 | ||
cf404ce4 | 12316 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
12317 | return false; |
12318 | ||
12319 | if (IS_CHERRYVIEW(dev)) | |
12320 | return false; | |
12321 | ||
12322 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
12323 | return false; | |
12324 | ||
12325 | return true; | |
12326 | } | |
12327 | ||
79e53945 JB |
12328 | static void intel_setup_outputs(struct drm_device *dev) |
12329 | { | |
725e30ad | 12330 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 12331 | struct intel_encoder *encoder; |
cb0953d7 | 12332 | bool dpd_is_edp = false; |
79e53945 | 12333 | |
c9093354 | 12334 | intel_lvds_init(dev); |
79e53945 | 12335 | |
84b4e042 | 12336 | if (intel_crt_present(dev)) |
79935fca | 12337 | intel_crt_init(dev); |
cb0953d7 | 12338 | |
affa9354 | 12339 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
12340 | int found; |
12341 | ||
12342 | /* Haswell uses DDI functions to detect digital outputs */ | |
12343 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
12344 | /* DDI A only supports eDP */ | |
12345 | if (found) | |
12346 | intel_ddi_init(dev, PORT_A); | |
12347 | ||
12348 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
12349 | * register */ | |
12350 | found = I915_READ(SFUSE_STRAP); | |
12351 | ||
12352 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
12353 | intel_ddi_init(dev, PORT_B); | |
12354 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
12355 | intel_ddi_init(dev, PORT_C); | |
12356 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
12357 | intel_ddi_init(dev, PORT_D); | |
12358 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 12359 | int found; |
5d8a7752 | 12360 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
12361 | |
12362 | if (has_edp_a(dev)) | |
12363 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 12364 | |
dc0fa718 | 12365 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 12366 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 12367 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 12368 | if (!found) |
e2debe91 | 12369 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 12370 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 12371 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
12372 | } |
12373 | ||
dc0fa718 | 12374 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 12375 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 12376 | |
dc0fa718 | 12377 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 12378 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 12379 | |
5eb08b69 | 12380 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 12381 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 12382 | |
270b3042 | 12383 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 12384 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 12385 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
12386 | /* |
12387 | * The DP_DETECTED bit is the latched state of the DDC | |
12388 | * SDA pin at boot. However since eDP doesn't require DDC | |
12389 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
12390 | * eDP ports may have been muxed to an alternate function. | |
12391 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
12392 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
12393 | * detect eDP ports. | |
12394 | */ | |
d2182a66 VS |
12395 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
12396 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
12397 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
12398 | PORT_B); | |
e17ac6db VS |
12399 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
12400 | intel_dp_is_edp(dev, PORT_B)) | |
12401 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 12402 | |
d2182a66 VS |
12403 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
12404 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
12405 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
12406 | PORT_C); | |
e17ac6db VS |
12407 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
12408 | intel_dp_is_edp(dev, PORT_C)) | |
12409 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 12410 | |
9418c1f1 | 12411 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 12412 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
12413 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
12414 | PORT_D); | |
e17ac6db VS |
12415 | /* eDP not supported on port D, so don't check VBT */ |
12416 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
12417 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
12418 | } |
12419 | ||
3cfca973 | 12420 | intel_dsi_init(dev); |
103a196f | 12421 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 12422 | bool found = false; |
7d57382e | 12423 | |
e2debe91 | 12424 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12425 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 12426 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
12427 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
12428 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 12429 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 12430 | } |
27185ae1 | 12431 | |
e7281eab | 12432 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12433 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 12434 | } |
13520b05 KH |
12435 | |
12436 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 12437 | |
e2debe91 | 12438 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12439 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 12440 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 12441 | } |
27185ae1 | 12442 | |
e2debe91 | 12443 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 12444 | |
b01f2c3a JB |
12445 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
12446 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 12447 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 12448 | } |
e7281eab | 12449 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12450 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 12451 | } |
27185ae1 | 12452 | |
b01f2c3a | 12453 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 12454 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 12455 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 12456 | } else if (IS_GEN2(dev)) |
79e53945 JB |
12457 | intel_dvo_init(dev); |
12458 | ||
103a196f | 12459 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
12460 | intel_tv_init(dev); |
12461 | ||
0bc12bcb | 12462 | intel_psr_init(dev); |
7c8f8a70 | 12463 | |
b2784e15 | 12464 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
12465 | encoder->base.possible_crtcs = encoder->crtc_mask; |
12466 | encoder->base.possible_clones = | |
66a9278e | 12467 | intel_encoder_clones(encoder); |
79e53945 | 12468 | } |
47356eb6 | 12469 | |
dde86e2d | 12470 | intel_init_pch_refclk(dev); |
270b3042 DV |
12471 | |
12472 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
12473 | } |
12474 | ||
12475 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
12476 | { | |
60a5ca01 | 12477 | struct drm_device *dev = fb->dev; |
79e53945 | 12478 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 12479 | |
ef2d633e | 12480 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 12481 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 12482 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
12483 | drm_gem_object_unreference(&intel_fb->obj->base); |
12484 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12485 | kfree(intel_fb); |
12486 | } | |
12487 | ||
12488 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 12489 | struct drm_file *file, |
79e53945 JB |
12490 | unsigned int *handle) |
12491 | { | |
12492 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 12493 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 12494 | |
05394f39 | 12495 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
12496 | } |
12497 | ||
12498 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
12499 | .destroy = intel_user_framebuffer_destroy, | |
12500 | .create_handle = intel_user_framebuffer_create_handle, | |
12501 | }; | |
12502 | ||
b5ea642a DV |
12503 | static int intel_framebuffer_init(struct drm_device *dev, |
12504 | struct intel_framebuffer *intel_fb, | |
12505 | struct drm_mode_fb_cmd2 *mode_cmd, | |
12506 | struct drm_i915_gem_object *obj) | |
79e53945 | 12507 | { |
a57ce0b2 | 12508 | int aligned_height; |
a35cdaa0 | 12509 | int pitch_limit; |
79e53945 JB |
12510 | int ret; |
12511 | ||
dd4916c5 DV |
12512 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
12513 | ||
c16ed4be CW |
12514 | if (obj->tiling_mode == I915_TILING_Y) { |
12515 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 12516 | return -EINVAL; |
c16ed4be | 12517 | } |
57cd6508 | 12518 | |
c16ed4be CW |
12519 | if (mode_cmd->pitches[0] & 63) { |
12520 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
12521 | mode_cmd->pitches[0]); | |
57cd6508 | 12522 | return -EINVAL; |
c16ed4be | 12523 | } |
57cd6508 | 12524 | |
a35cdaa0 CW |
12525 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
12526 | pitch_limit = 32*1024; | |
12527 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
12528 | if (obj->tiling_mode) | |
12529 | pitch_limit = 16*1024; | |
12530 | else | |
12531 | pitch_limit = 32*1024; | |
12532 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
12533 | if (obj->tiling_mode) | |
12534 | pitch_limit = 8*1024; | |
12535 | else | |
12536 | pitch_limit = 16*1024; | |
12537 | } else | |
12538 | /* XXX DSPC is limited to 4k tiled */ | |
12539 | pitch_limit = 8*1024; | |
12540 | ||
12541 | if (mode_cmd->pitches[0] > pitch_limit) { | |
12542 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
12543 | obj->tiling_mode ? "tiled" : "linear", | |
12544 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 12545 | return -EINVAL; |
c16ed4be | 12546 | } |
5d7bd705 VS |
12547 | |
12548 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
12549 | mode_cmd->pitches[0] != obj->stride) { |
12550 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
12551 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 12552 | return -EINVAL; |
c16ed4be | 12553 | } |
5d7bd705 | 12554 | |
57779d06 | 12555 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 12556 | switch (mode_cmd->pixel_format) { |
57779d06 | 12557 | case DRM_FORMAT_C8: |
04b3924d VS |
12558 | case DRM_FORMAT_RGB565: |
12559 | case DRM_FORMAT_XRGB8888: | |
12560 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
12561 | break; |
12562 | case DRM_FORMAT_XRGB1555: | |
12563 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 12564 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
12565 | DRM_DEBUG("unsupported pixel format: %s\n", |
12566 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12567 | return -EINVAL; |
c16ed4be | 12568 | } |
57779d06 VS |
12569 | break; |
12570 | case DRM_FORMAT_XBGR8888: | |
12571 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
12572 | case DRM_FORMAT_XRGB2101010: |
12573 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
12574 | case DRM_FORMAT_XBGR2101010: |
12575 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 12576 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
12577 | DRM_DEBUG("unsupported pixel format: %s\n", |
12578 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12579 | return -EINVAL; |
c16ed4be | 12580 | } |
b5626747 | 12581 | break; |
04b3924d VS |
12582 | case DRM_FORMAT_YUYV: |
12583 | case DRM_FORMAT_UYVY: | |
12584 | case DRM_FORMAT_YVYU: | |
12585 | case DRM_FORMAT_VYUY: | |
c16ed4be | 12586 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
12587 | DRM_DEBUG("unsupported pixel format: %s\n", |
12588 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12589 | return -EINVAL; |
c16ed4be | 12590 | } |
57cd6508 CW |
12591 | break; |
12592 | default: | |
4ee62c76 VS |
12593 | DRM_DEBUG("unsupported pixel format: %s\n", |
12594 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
12595 | return -EINVAL; |
12596 | } | |
12597 | ||
90f9a336 VS |
12598 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
12599 | if (mode_cmd->offsets[0] != 0) | |
12600 | return -EINVAL; | |
12601 | ||
a57ce0b2 JB |
12602 | aligned_height = intel_align_height(dev, mode_cmd->height, |
12603 | obj->tiling_mode); | |
53155c0a DV |
12604 | /* FIXME drm helper for size checks (especially planar formats)? */ |
12605 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
12606 | return -EINVAL; | |
12607 | ||
c7d73f6a DV |
12608 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
12609 | intel_fb->obj = obj; | |
80075d49 | 12610 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 12611 | |
79e53945 JB |
12612 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
12613 | if (ret) { | |
12614 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
12615 | return ret; | |
12616 | } | |
12617 | ||
79e53945 JB |
12618 | return 0; |
12619 | } | |
12620 | ||
79e53945 JB |
12621 | static struct drm_framebuffer * |
12622 | intel_user_framebuffer_create(struct drm_device *dev, | |
12623 | struct drm_file *filp, | |
308e5bcb | 12624 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 12625 | { |
05394f39 | 12626 | struct drm_i915_gem_object *obj; |
79e53945 | 12627 | |
308e5bcb JB |
12628 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
12629 | mode_cmd->handles[0])); | |
c8725226 | 12630 | if (&obj->base == NULL) |
cce13ff7 | 12631 | return ERR_PTR(-ENOENT); |
79e53945 | 12632 | |
d2dff872 | 12633 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
12634 | } |
12635 | ||
4520f53a | 12636 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 12637 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
12638 | { |
12639 | } | |
12640 | #endif | |
12641 | ||
79e53945 | 12642 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 12643 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 12644 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
12645 | }; |
12646 | ||
e70236a8 JB |
12647 | /* Set up chip specific display functions */ |
12648 | static void intel_init_display(struct drm_device *dev) | |
12649 | { | |
12650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12651 | ||
ee9300bb DV |
12652 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
12653 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
12654 | else if (IS_CHERRYVIEW(dev)) |
12655 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
12656 | else if (IS_VALLEYVIEW(dev)) |
12657 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
12658 | else if (IS_PINEVIEW(dev)) | |
12659 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
12660 | else | |
12661 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
12662 | ||
affa9354 | 12663 | if (HAS_DDI(dev)) { |
0e8ffe1b | 12664 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 12665 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
797d0259 ACO |
12666 | dev_priv->display.crtc_compute_clock = |
12667 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
12668 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
12669 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 12670 | dev_priv->display.off = ironlake_crtc_off; |
70d21f0e DL |
12671 | if (INTEL_INFO(dev)->gen >= 9) |
12672 | dev_priv->display.update_primary_plane = | |
12673 | skylake_update_primary_plane; | |
12674 | else | |
12675 | dev_priv->display.update_primary_plane = | |
12676 | ironlake_update_primary_plane; | |
09b4ddf9 | 12677 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 12678 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 12679 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
3fb37703 ACO |
12680 | dev_priv->display.crtc_compute_clock = |
12681 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
12682 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
12683 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 12684 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12685 | dev_priv->display.update_primary_plane = |
12686 | ironlake_update_primary_plane; | |
89b667f8 JB |
12687 | } else if (IS_VALLEYVIEW(dev)) { |
12688 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 12689 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
d6dfee7a | 12690 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
12691 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
12692 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
12693 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
12694 | dev_priv->display.update_primary_plane = |
12695 | i9xx_update_primary_plane; | |
f564048e | 12696 | } else { |
0e8ffe1b | 12697 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 12698 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
d6dfee7a | 12699 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
12700 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12701 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 12702 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
12703 | dev_priv->display.update_primary_plane = |
12704 | i9xx_update_primary_plane; | |
f564048e | 12705 | } |
e70236a8 | 12706 | |
e70236a8 | 12707 | /* Returns the core display clock speed */ |
25eb05fc JB |
12708 | if (IS_VALLEYVIEW(dev)) |
12709 | dev_priv->display.get_display_clock_speed = | |
12710 | valleyview_get_display_clock_speed; | |
12711 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
12712 | dev_priv->display.get_display_clock_speed = |
12713 | i945_get_display_clock_speed; | |
12714 | else if (IS_I915G(dev)) | |
12715 | dev_priv->display.get_display_clock_speed = | |
12716 | i915_get_display_clock_speed; | |
257a7ffc | 12717 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
12718 | dev_priv->display.get_display_clock_speed = |
12719 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
12720 | else if (IS_PINEVIEW(dev)) |
12721 | dev_priv->display.get_display_clock_speed = | |
12722 | pnv_get_display_clock_speed; | |
e70236a8 JB |
12723 | else if (IS_I915GM(dev)) |
12724 | dev_priv->display.get_display_clock_speed = | |
12725 | i915gm_get_display_clock_speed; | |
12726 | else if (IS_I865G(dev)) | |
12727 | dev_priv->display.get_display_clock_speed = | |
12728 | i865_get_display_clock_speed; | |
f0f8a9ce | 12729 | else if (IS_I85X(dev)) |
e70236a8 JB |
12730 | dev_priv->display.get_display_clock_speed = |
12731 | i855_get_display_clock_speed; | |
12732 | else /* 852, 830 */ | |
12733 | dev_priv->display.get_display_clock_speed = | |
12734 | i830_get_display_clock_speed; | |
12735 | ||
7c10a2b5 | 12736 | if (IS_GEN5(dev)) { |
3bb11b53 | 12737 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
12738 | } else if (IS_GEN6(dev)) { |
12739 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
12740 | } else if (IS_IVYBRIDGE(dev)) { |
12741 | /* FIXME: detect B0+ stepping and use auto training */ | |
12742 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
3bb11b53 SJ |
12743 | dev_priv->display.modeset_global_resources = |
12744 | ivb_modeset_global_resources; | |
059b2fe9 | 12745 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 12746 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
12747 | } else if (IS_VALLEYVIEW(dev)) { |
12748 | dev_priv->display.modeset_global_resources = | |
12749 | valleyview_modeset_global_resources; | |
e70236a8 | 12750 | } |
8c9f3aaf JB |
12751 | |
12752 | /* Default just returns -ENODEV to indicate unsupported */ | |
12753 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
12754 | ||
12755 | switch (INTEL_INFO(dev)->gen) { | |
12756 | case 2: | |
12757 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
12758 | break; | |
12759 | ||
12760 | case 3: | |
12761 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
12762 | break; | |
12763 | ||
12764 | case 4: | |
12765 | case 5: | |
12766 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
12767 | break; | |
12768 | ||
12769 | case 6: | |
12770 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
12771 | break; | |
7c9017e5 | 12772 | case 7: |
4e0bbc31 | 12773 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
12774 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
12775 | break; | |
830c81db DL |
12776 | case 9: |
12777 | dev_priv->display.queue_flip = intel_gen9_queue_flip; | |
12778 | break; | |
8c9f3aaf | 12779 | } |
7bd688cd JN |
12780 | |
12781 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
12782 | |
12783 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
12784 | } |
12785 | ||
b690e96c JB |
12786 | /* |
12787 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
12788 | * resume, or other times. This quirk makes sure that's the case for | |
12789 | * affected systems. | |
12790 | */ | |
0206e353 | 12791 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
12792 | { |
12793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12794 | ||
12795 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 12796 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
12797 | } |
12798 | ||
b6b5d049 VS |
12799 | static void quirk_pipeb_force(struct drm_device *dev) |
12800 | { | |
12801 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12802 | ||
12803 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
12804 | DRM_INFO("applying pipe b force quirk\n"); | |
12805 | } | |
12806 | ||
435793df KP |
12807 | /* |
12808 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
12809 | */ | |
12810 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
12811 | { | |
12812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12813 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 12814 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
12815 | } |
12816 | ||
4dca20ef | 12817 | /* |
5a15ab5b CE |
12818 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
12819 | * brightness value | |
4dca20ef CE |
12820 | */ |
12821 | static void quirk_invert_brightness(struct drm_device *dev) | |
12822 | { | |
12823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12824 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 12825 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
12826 | } |
12827 | ||
9c72cc6f SD |
12828 | /* Some VBT's incorrectly indicate no backlight is present */ |
12829 | static void quirk_backlight_present(struct drm_device *dev) | |
12830 | { | |
12831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12832 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
12833 | DRM_INFO("applying backlight present quirk\n"); | |
12834 | } | |
12835 | ||
b690e96c JB |
12836 | struct intel_quirk { |
12837 | int device; | |
12838 | int subsystem_vendor; | |
12839 | int subsystem_device; | |
12840 | void (*hook)(struct drm_device *dev); | |
12841 | }; | |
12842 | ||
5f85f176 EE |
12843 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
12844 | struct intel_dmi_quirk { | |
12845 | void (*hook)(struct drm_device *dev); | |
12846 | const struct dmi_system_id (*dmi_id_list)[]; | |
12847 | }; | |
12848 | ||
12849 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
12850 | { | |
12851 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
12852 | return 1; | |
12853 | } | |
12854 | ||
12855 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
12856 | { | |
12857 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
12858 | { | |
12859 | .callback = intel_dmi_reverse_brightness, | |
12860 | .ident = "NCR Corporation", | |
12861 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
12862 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
12863 | }, | |
12864 | }, | |
12865 | { } /* terminating entry */ | |
12866 | }, | |
12867 | .hook = quirk_invert_brightness, | |
12868 | }, | |
12869 | }; | |
12870 | ||
c43b5634 | 12871 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 12872 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 12873 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 12874 | |
b690e96c JB |
12875 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
12876 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
12877 | ||
b690e96c JB |
12878 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
12879 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
12880 | ||
5f080c0f VS |
12881 | /* 830 needs to leave pipe A & dpll A up */ |
12882 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
12883 | ||
b6b5d049 VS |
12884 | /* 830 needs to leave pipe B & dpll B up */ |
12885 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
12886 | ||
435793df KP |
12887 | /* Lenovo U160 cannot use SSC on LVDS */ |
12888 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
12889 | |
12890 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
12891 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 12892 | |
be505f64 AH |
12893 | /* Acer Aspire 5734Z must invert backlight brightness */ |
12894 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
12895 | ||
12896 | /* Acer/eMachines G725 */ | |
12897 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
12898 | ||
12899 | /* Acer/eMachines e725 */ | |
12900 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
12901 | ||
12902 | /* Acer/Packard Bell NCL20 */ | |
12903 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
12904 | ||
12905 | /* Acer Aspire 4736Z */ | |
12906 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
12907 | |
12908 | /* Acer Aspire 5336 */ | |
12909 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
12910 | |
12911 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
12912 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 12913 | |
dfb3d47b SD |
12914 | /* Acer C720 Chromebook (Core i3 4005U) */ |
12915 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
12916 | ||
b2a9601c | 12917 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
12918 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
12919 | ||
d4967d8c SD |
12920 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
12921 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
12922 | |
12923 | /* HP Chromebook 14 (Celeron 2955U) */ | |
12924 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
b690e96c JB |
12925 | }; |
12926 | ||
12927 | static void intel_init_quirks(struct drm_device *dev) | |
12928 | { | |
12929 | struct pci_dev *d = dev->pdev; | |
12930 | int i; | |
12931 | ||
12932 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
12933 | struct intel_quirk *q = &intel_quirks[i]; | |
12934 | ||
12935 | if (d->device == q->device && | |
12936 | (d->subsystem_vendor == q->subsystem_vendor || | |
12937 | q->subsystem_vendor == PCI_ANY_ID) && | |
12938 | (d->subsystem_device == q->subsystem_device || | |
12939 | q->subsystem_device == PCI_ANY_ID)) | |
12940 | q->hook(dev); | |
12941 | } | |
5f85f176 EE |
12942 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
12943 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
12944 | intel_dmi_quirks[i].hook(dev); | |
12945 | } | |
b690e96c JB |
12946 | } |
12947 | ||
9cce37f4 JB |
12948 | /* Disable the VGA plane that we never use */ |
12949 | static void i915_disable_vga(struct drm_device *dev) | |
12950 | { | |
12951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12952 | u8 sr1; | |
766aa1c4 | 12953 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 12954 | |
2b37c616 | 12955 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 12956 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 12957 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
12958 | sr1 = inb(VGA_SR_DATA); |
12959 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
12960 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
12961 | udelay(300); | |
12962 | ||
01f5a626 | 12963 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
12964 | POSTING_READ(vga_reg); |
12965 | } | |
12966 | ||
f817586c DV |
12967 | void intel_modeset_init_hw(struct drm_device *dev) |
12968 | { | |
a8f78b58 ED |
12969 | intel_prepare_ddi(dev); |
12970 | ||
f8bf63fd VS |
12971 | if (IS_VALLEYVIEW(dev)) |
12972 | vlv_update_cdclk(dev); | |
12973 | ||
f817586c DV |
12974 | intel_init_clock_gating(dev); |
12975 | ||
8090c6b9 | 12976 | intel_enable_gt_powersave(dev); |
f817586c DV |
12977 | } |
12978 | ||
79e53945 JB |
12979 | void intel_modeset_init(struct drm_device *dev) |
12980 | { | |
652c393a | 12981 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 12982 | int sprite, ret; |
8cc87b75 | 12983 | enum pipe pipe; |
46f297fb | 12984 | struct intel_crtc *crtc; |
79e53945 JB |
12985 | |
12986 | drm_mode_config_init(dev); | |
12987 | ||
12988 | dev->mode_config.min_width = 0; | |
12989 | dev->mode_config.min_height = 0; | |
12990 | ||
019d96cb DA |
12991 | dev->mode_config.preferred_depth = 24; |
12992 | dev->mode_config.prefer_shadow = 1; | |
12993 | ||
e6ecefaa | 12994 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 12995 | |
b690e96c JB |
12996 | intel_init_quirks(dev); |
12997 | ||
1fa61106 ED |
12998 | intel_init_pm(dev); |
12999 | ||
e3c74757 BW |
13000 | if (INTEL_INFO(dev)->num_pipes == 0) |
13001 | return; | |
13002 | ||
e70236a8 | 13003 | intel_init_display(dev); |
7c10a2b5 | 13004 | intel_init_audio(dev); |
e70236a8 | 13005 | |
a6c45cf0 CW |
13006 | if (IS_GEN2(dev)) { |
13007 | dev->mode_config.max_width = 2048; | |
13008 | dev->mode_config.max_height = 2048; | |
13009 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
13010 | dev->mode_config.max_width = 4096; |
13011 | dev->mode_config.max_height = 4096; | |
79e53945 | 13012 | } else { |
a6c45cf0 CW |
13013 | dev->mode_config.max_width = 8192; |
13014 | dev->mode_config.max_height = 8192; | |
79e53945 | 13015 | } |
068be561 | 13016 | |
dc41c154 VS |
13017 | if (IS_845G(dev) || IS_I865G(dev)) { |
13018 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
13019 | dev->mode_config.cursor_height = 1023; | |
13020 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
13021 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
13022 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
13023 | } else { | |
13024 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
13025 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
13026 | } | |
13027 | ||
5d4545ae | 13028 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 13029 | |
28c97730 | 13030 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
13031 | INTEL_INFO(dev)->num_pipes, |
13032 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 13033 | |
055e393f | 13034 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 13035 | intel_crtc_init(dev, pipe); |
1fe47785 DL |
13036 | for_each_sprite(pipe, sprite) { |
13037 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 13038 | if (ret) |
06da8da2 | 13039 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 13040 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 13041 | } |
79e53945 JB |
13042 | } |
13043 | ||
f42bb70d JB |
13044 | intel_init_dpio(dev); |
13045 | ||
e72f9fbf | 13046 | intel_shared_dpll_init(dev); |
ee7b9f93 | 13047 | |
9cce37f4 JB |
13048 | /* Just disable it once at startup */ |
13049 | i915_disable_vga(dev); | |
79e53945 | 13050 | intel_setup_outputs(dev); |
11be49eb CW |
13051 | |
13052 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 13053 | intel_fbc_disable(dev); |
fa9fa083 | 13054 | |
6e9f798d | 13055 | drm_modeset_lock_all(dev); |
fa9fa083 | 13056 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 13057 | drm_modeset_unlock_all(dev); |
46f297fb | 13058 | |
d3fcc808 | 13059 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
13060 | if (!crtc->active) |
13061 | continue; | |
13062 | ||
46f297fb | 13063 | /* |
46f297fb JB |
13064 | * Note that reserving the BIOS fb up front prevents us |
13065 | * from stuffing other stolen allocations like the ring | |
13066 | * on top. This prevents some ugliness at boot time, and | |
13067 | * can even allow for smooth boot transitions if the BIOS | |
13068 | * fb is large enough for the active pipe configuration. | |
13069 | */ | |
13070 | if (dev_priv->display.get_plane_config) { | |
13071 | dev_priv->display.get_plane_config(crtc, | |
13072 | &crtc->plane_config); | |
13073 | /* | |
13074 | * If the fb is shared between multiple heads, we'll | |
13075 | * just get the first one. | |
13076 | */ | |
484b41dd | 13077 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 13078 | } |
46f297fb | 13079 | } |
2c7111db CW |
13080 | } |
13081 | ||
7fad798e DV |
13082 | static void intel_enable_pipe_a(struct drm_device *dev) |
13083 | { | |
13084 | struct intel_connector *connector; | |
13085 | struct drm_connector *crt = NULL; | |
13086 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 13087 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
13088 | |
13089 | /* We can't just switch on the pipe A, we need to set things up with a | |
13090 | * proper mode and output configuration. As a gross hack, enable pipe A | |
13091 | * by enabling the load detect pipe once. */ | |
13092 | list_for_each_entry(connector, | |
13093 | &dev->mode_config.connector_list, | |
13094 | base.head) { | |
13095 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
13096 | crt = &connector->base; | |
13097 | break; | |
13098 | } | |
13099 | } | |
13100 | ||
13101 | if (!crt) | |
13102 | return; | |
13103 | ||
208bf9fd VS |
13104 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
13105 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
7fad798e DV |
13106 | } |
13107 | ||
fa555837 DV |
13108 | static bool |
13109 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
13110 | { | |
7eb552ae BW |
13111 | struct drm_device *dev = crtc->base.dev; |
13112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
13113 | u32 reg, val; |
13114 | ||
7eb552ae | 13115 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
13116 | return true; |
13117 | ||
13118 | reg = DSPCNTR(!crtc->plane); | |
13119 | val = I915_READ(reg); | |
13120 | ||
13121 | if ((val & DISPLAY_PLANE_ENABLE) && | |
13122 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
13123 | return false; | |
13124 | ||
13125 | return true; | |
13126 | } | |
13127 | ||
24929352 DV |
13128 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
13129 | { | |
13130 | struct drm_device *dev = crtc->base.dev; | |
13131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 13132 | u32 reg; |
24929352 | 13133 | |
24929352 | 13134 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 13135 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
13136 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
13137 | ||
d3eaf884 | 13138 | /* restore vblank interrupts to correct state */ |
d297e103 VS |
13139 | if (crtc->active) { |
13140 | update_scanline_offset(crtc); | |
d3eaf884 | 13141 | drm_vblank_on(dev, crtc->pipe); |
d297e103 | 13142 | } else |
d3eaf884 VS |
13143 | drm_vblank_off(dev, crtc->pipe); |
13144 | ||
24929352 | 13145 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
13146 | * disable the crtc (and hence change the state) if it is wrong. Note |
13147 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
13148 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
13149 | struct intel_connector *connector; |
13150 | bool plane; | |
13151 | ||
24929352 DV |
13152 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
13153 | crtc->base.base.id); | |
13154 | ||
13155 | /* Pipe has the wrong plane attached and the plane is active. | |
13156 | * Temporarily change the plane mapping and disable everything | |
13157 | * ... */ | |
13158 | plane = crtc->plane; | |
13159 | crtc->plane = !plane; | |
9c8958bc | 13160 | crtc->primary_enabled = true; |
24929352 DV |
13161 | dev_priv->display.crtc_disable(&crtc->base); |
13162 | crtc->plane = plane; | |
13163 | ||
13164 | /* ... and break all links. */ | |
13165 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13166 | base.head) { | |
13167 | if (connector->encoder->base.crtc != &crtc->base) | |
13168 | continue; | |
13169 | ||
7f1950fb EE |
13170 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13171 | connector->base.encoder = NULL; | |
24929352 | 13172 | } |
7f1950fb EE |
13173 | /* multiple connectors may have the same encoder: |
13174 | * handle them and break crtc link separately */ | |
13175 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13176 | base.head) | |
13177 | if (connector->encoder->base.crtc == &crtc->base) { | |
13178 | connector->encoder->base.crtc = NULL; | |
13179 | connector->encoder->connectors_active = false; | |
13180 | } | |
24929352 DV |
13181 | |
13182 | WARN_ON(crtc->active); | |
13183 | crtc->base.enabled = false; | |
13184 | } | |
24929352 | 13185 | |
7fad798e DV |
13186 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
13187 | crtc->pipe == PIPE_A && !crtc->active) { | |
13188 | /* BIOS forgot to enable pipe A, this mostly happens after | |
13189 | * resume. Force-enable the pipe to fix this, the update_dpms | |
13190 | * call below we restore the pipe to the right state, but leave | |
13191 | * the required bits on. */ | |
13192 | intel_enable_pipe_a(dev); | |
13193 | } | |
13194 | ||
24929352 DV |
13195 | /* Adjust the state of the output pipe according to whether we |
13196 | * have active connectors/encoders. */ | |
13197 | intel_crtc_update_dpms(&crtc->base); | |
13198 | ||
13199 | if (crtc->active != crtc->base.enabled) { | |
13200 | struct intel_encoder *encoder; | |
13201 | ||
13202 | /* This can happen either due to bugs in the get_hw_state | |
13203 | * functions or because the pipe is force-enabled due to the | |
13204 | * pipe A quirk. */ | |
13205 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
13206 | crtc->base.base.id, | |
13207 | crtc->base.enabled ? "enabled" : "disabled", | |
13208 | crtc->active ? "enabled" : "disabled"); | |
13209 | ||
13210 | crtc->base.enabled = crtc->active; | |
13211 | ||
13212 | /* Because we only establish the connector -> encoder -> | |
13213 | * crtc links if something is active, this means the | |
13214 | * crtc is now deactivated. Break the links. connector | |
13215 | * -> encoder links are only establish when things are | |
13216 | * actually up, hence no need to break them. */ | |
13217 | WARN_ON(crtc->active); | |
13218 | ||
13219 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
13220 | WARN_ON(encoder->connectors_active); | |
13221 | encoder->base.crtc = NULL; | |
13222 | } | |
13223 | } | |
c5ab3bc0 | 13224 | |
a3ed6aad | 13225 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
13226 | /* |
13227 | * We start out with underrun reporting disabled to avoid races. | |
13228 | * For correct bookkeeping mark this on active crtcs. | |
13229 | * | |
c5ab3bc0 DV |
13230 | * Also on gmch platforms we dont have any hardware bits to |
13231 | * disable the underrun reporting. Which means we need to start | |
13232 | * out with underrun reporting disabled also on inactive pipes, | |
13233 | * since otherwise we'll complain about the garbage we read when | |
13234 | * e.g. coming up after runtime pm. | |
13235 | * | |
4cc31489 DV |
13236 | * No protection against concurrent access is required - at |
13237 | * worst a fifo underrun happens which also sets this to false. | |
13238 | */ | |
13239 | crtc->cpu_fifo_underrun_disabled = true; | |
13240 | crtc->pch_fifo_underrun_disabled = true; | |
13241 | } | |
24929352 DV |
13242 | } |
13243 | ||
13244 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
13245 | { | |
13246 | struct intel_connector *connector; | |
13247 | struct drm_device *dev = encoder->base.dev; | |
13248 | ||
13249 | /* We need to check both for a crtc link (meaning that the | |
13250 | * encoder is active and trying to read from a pipe) and the | |
13251 | * pipe itself being active. */ | |
13252 | bool has_active_crtc = encoder->base.crtc && | |
13253 | to_intel_crtc(encoder->base.crtc)->active; | |
13254 | ||
13255 | if (encoder->connectors_active && !has_active_crtc) { | |
13256 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
13257 | encoder->base.base.id, | |
8e329a03 | 13258 | encoder->base.name); |
24929352 DV |
13259 | |
13260 | /* Connector is active, but has no active pipe. This is | |
13261 | * fallout from our resume register restoring. Disable | |
13262 | * the encoder manually again. */ | |
13263 | if (encoder->base.crtc) { | |
13264 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
13265 | encoder->base.base.id, | |
8e329a03 | 13266 | encoder->base.name); |
24929352 | 13267 | encoder->disable(encoder); |
a62d1497 VS |
13268 | if (encoder->post_disable) |
13269 | encoder->post_disable(encoder); | |
24929352 | 13270 | } |
7f1950fb EE |
13271 | encoder->base.crtc = NULL; |
13272 | encoder->connectors_active = false; | |
24929352 DV |
13273 | |
13274 | /* Inconsistent output/port/pipe state happens presumably due to | |
13275 | * a bug in one of the get_hw_state functions. Or someplace else | |
13276 | * in our code, like the register restore mess on resume. Clamp | |
13277 | * things to off as a safer default. */ | |
13278 | list_for_each_entry(connector, | |
13279 | &dev->mode_config.connector_list, | |
13280 | base.head) { | |
13281 | if (connector->encoder != encoder) | |
13282 | continue; | |
7f1950fb EE |
13283 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13284 | connector->base.encoder = NULL; | |
24929352 DV |
13285 | } |
13286 | } | |
13287 | /* Enabled encoders without active connectors will be fixed in | |
13288 | * the crtc fixup. */ | |
13289 | } | |
13290 | ||
04098753 | 13291 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
13292 | { |
13293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 13294 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 13295 | |
04098753 ID |
13296 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
13297 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
13298 | i915_disable_vga(dev); | |
13299 | } | |
13300 | } | |
13301 | ||
13302 | void i915_redisable_vga(struct drm_device *dev) | |
13303 | { | |
13304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13305 | ||
8dc8a27c PZ |
13306 | /* This function can be called both from intel_modeset_setup_hw_state or |
13307 | * at a very early point in our resume sequence, where the power well | |
13308 | * structures are not yet restored. Since this function is at a very | |
13309 | * paranoid "someone might have enabled VGA while we were not looking" | |
13310 | * level, just check if the power well is enabled instead of trying to | |
13311 | * follow the "don't touch the power well if we don't need it" policy | |
13312 | * the rest of the driver uses. */ | |
f458ebbc | 13313 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
13314 | return; |
13315 | ||
04098753 | 13316 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
13317 | } |
13318 | ||
98ec7739 VS |
13319 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
13320 | { | |
13321 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
13322 | ||
13323 | if (!crtc->active) | |
13324 | return false; | |
13325 | ||
13326 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
13327 | } | |
13328 | ||
30e984df | 13329 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
13330 | { |
13331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13332 | enum pipe pipe; | |
24929352 DV |
13333 | struct intel_crtc *crtc; |
13334 | struct intel_encoder *encoder; | |
13335 | struct intel_connector *connector; | |
5358901f | 13336 | int i; |
24929352 | 13337 | |
d3fcc808 | 13338 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 13339 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 13340 | |
9953599b DV |
13341 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
13342 | ||
0e8ffe1b DV |
13343 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
13344 | &crtc->config); | |
24929352 DV |
13345 | |
13346 | crtc->base.enabled = crtc->active; | |
98ec7739 | 13347 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
13348 | |
13349 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
13350 | crtc->base.base.id, | |
13351 | crtc->active ? "enabled" : "disabled"); | |
13352 | } | |
13353 | ||
5358901f DV |
13354 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13355 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13356 | ||
3e369b76 ACO |
13357 | pll->on = pll->get_hw_state(dev_priv, pll, |
13358 | &pll->config.hw_state); | |
5358901f | 13359 | pll->active = 0; |
3e369b76 | 13360 | pll->config.crtc_mask = 0; |
d3fcc808 | 13361 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 13362 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 13363 | pll->active++; |
3e369b76 | 13364 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 13365 | } |
5358901f | 13366 | } |
5358901f | 13367 | |
1e6f2ddc | 13368 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 13369 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 13370 | |
3e369b76 | 13371 | if (pll->config.crtc_mask) |
bd2bb1b9 | 13372 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
13373 | } |
13374 | ||
b2784e15 | 13375 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13376 | pipe = 0; |
13377 | ||
13378 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
13379 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13380 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 13381 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
13382 | } else { |
13383 | encoder->base.crtc = NULL; | |
13384 | } | |
13385 | ||
13386 | encoder->connectors_active = false; | |
6f2bcceb | 13387 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 13388 | encoder->base.base.id, |
8e329a03 | 13389 | encoder->base.name, |
24929352 | 13390 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 13391 | pipe_name(pipe)); |
24929352 DV |
13392 | } |
13393 | ||
13394 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13395 | base.head) { | |
13396 | if (connector->get_hw_state(connector)) { | |
13397 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
13398 | connector->encoder->connectors_active = true; | |
13399 | connector->base.encoder = &connector->encoder->base; | |
13400 | } else { | |
13401 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
13402 | connector->base.encoder = NULL; | |
13403 | } | |
13404 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
13405 | connector->base.base.id, | |
c23cc417 | 13406 | connector->base.name, |
24929352 DV |
13407 | connector->base.encoder ? "enabled" : "disabled"); |
13408 | } | |
30e984df DV |
13409 | } |
13410 | ||
13411 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
13412 | * and i915 state tracking structures. */ | |
13413 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
13414 | bool force_restore) | |
13415 | { | |
13416 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13417 | enum pipe pipe; | |
30e984df DV |
13418 | struct intel_crtc *crtc; |
13419 | struct intel_encoder *encoder; | |
35c95375 | 13420 | int i; |
30e984df DV |
13421 | |
13422 | intel_modeset_readout_hw_state(dev); | |
24929352 | 13423 | |
babea61d JB |
13424 | /* |
13425 | * Now that we have the config, copy it to each CRTC struct | |
13426 | * Note that this could go away if we move to using crtc_config | |
13427 | * checking everywhere. | |
13428 | */ | |
d3fcc808 | 13429 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 13430 | if (crtc->active && i915.fastboot) { |
f6a83288 | 13431 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
13432 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
13433 | crtc->base.base.id); | |
13434 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
13435 | } | |
13436 | } | |
13437 | ||
24929352 | 13438 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 13439 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13440 | intel_sanitize_encoder(encoder); |
13441 | } | |
13442 | ||
055e393f | 13443 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
13444 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13445 | intel_sanitize_crtc(crtc); | |
c0b03411 | 13446 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 13447 | } |
9a935856 | 13448 | |
35c95375 DV |
13449 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13450 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13451 | ||
13452 | if (!pll->on || pll->active) | |
13453 | continue; | |
13454 | ||
13455 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
13456 | ||
13457 | pll->disable(dev_priv, pll); | |
13458 | pll->on = false; | |
13459 | } | |
13460 | ||
3078999f PB |
13461 | if (IS_GEN9(dev)) |
13462 | skl_wm_get_hw_state(dev); | |
13463 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
13464 | ilk_wm_get_hw_state(dev); |
13465 | ||
45e2b5f6 | 13466 | if (force_restore) { |
7d0bc1ea VS |
13467 | i915_redisable_vga(dev); |
13468 | ||
f30da187 DV |
13469 | /* |
13470 | * We need to use raw interfaces for restoring state to avoid | |
13471 | * checking (bogus) intermediate states. | |
13472 | */ | |
055e393f | 13473 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
13474 | struct drm_crtc *crtc = |
13475 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 13476 | |
7f27126e JB |
13477 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
13478 | crtc->primary->fb); | |
45e2b5f6 DV |
13479 | } |
13480 | } else { | |
13481 | intel_modeset_update_staged_output_state(dev); | |
13482 | } | |
8af6cf88 DV |
13483 | |
13484 | intel_modeset_check_state(dev); | |
2c7111db CW |
13485 | } |
13486 | ||
13487 | void intel_modeset_gem_init(struct drm_device *dev) | |
13488 | { | |
92122789 | 13489 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 13490 | struct drm_crtc *c; |
2ff8fde1 | 13491 | struct drm_i915_gem_object *obj; |
484b41dd | 13492 | |
ae48434c ID |
13493 | mutex_lock(&dev->struct_mutex); |
13494 | intel_init_gt_powersave(dev); | |
13495 | mutex_unlock(&dev->struct_mutex); | |
13496 | ||
92122789 JB |
13497 | /* |
13498 | * There may be no VBT; and if the BIOS enabled SSC we can | |
13499 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
13500 | * BIOS isn't using it, don't assume it will work even if the VBT | |
13501 | * indicates as much. | |
13502 | */ | |
13503 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
13504 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
13505 | DREF_SSC1_ENABLE); | |
13506 | ||
1833b134 | 13507 | intel_modeset_init_hw(dev); |
02e792fb DV |
13508 | |
13509 | intel_setup_overlay(dev); | |
484b41dd JB |
13510 | |
13511 | /* | |
13512 | * Make sure any fbs we allocated at startup are properly | |
13513 | * pinned & fenced. When we do the allocation it's too early | |
13514 | * for this. | |
13515 | */ | |
13516 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 13517 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
13518 | obj = intel_fb_obj(c->primary->fb); |
13519 | if (obj == NULL) | |
484b41dd JB |
13520 | continue; |
13521 | ||
850c4cdc TU |
13522 | if (intel_pin_and_fence_fb_obj(c->primary, |
13523 | c->primary->fb, | |
13524 | NULL)) { | |
484b41dd JB |
13525 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
13526 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
13527 | drm_framebuffer_unreference(c->primary->fb); |
13528 | c->primary->fb = NULL; | |
484b41dd JB |
13529 | } |
13530 | } | |
13531 | mutex_unlock(&dev->struct_mutex); | |
0962c3c9 VS |
13532 | |
13533 | intel_backlight_register(dev); | |
79e53945 JB |
13534 | } |
13535 | ||
4932e2c3 ID |
13536 | void intel_connector_unregister(struct intel_connector *intel_connector) |
13537 | { | |
13538 | struct drm_connector *connector = &intel_connector->base; | |
13539 | ||
13540 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 13541 | drm_connector_unregister(connector); |
4932e2c3 ID |
13542 | } |
13543 | ||
79e53945 JB |
13544 | void intel_modeset_cleanup(struct drm_device *dev) |
13545 | { | |
652c393a | 13546 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 13547 | struct drm_connector *connector; |
652c393a | 13548 | |
2eb5252e ID |
13549 | intel_disable_gt_powersave(dev); |
13550 | ||
0962c3c9 VS |
13551 | intel_backlight_unregister(dev); |
13552 | ||
fd0c0642 DV |
13553 | /* |
13554 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 13555 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
13556 | * experience fancy races otherwise. |
13557 | */ | |
2aeb7d3a | 13558 | intel_irq_uninstall(dev_priv); |
eb21b92b | 13559 | |
fd0c0642 DV |
13560 | /* |
13561 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
13562 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
13563 | */ | |
f87ea761 | 13564 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 13565 | |
652c393a JB |
13566 | mutex_lock(&dev->struct_mutex); |
13567 | ||
723bfd70 JB |
13568 | intel_unregister_dsm_handler(); |
13569 | ||
7ff0ebcc | 13570 | intel_fbc_disable(dev); |
e70236a8 | 13571 | |
930ebb46 DV |
13572 | ironlake_teardown_rc6(dev); |
13573 | ||
69341a5e KH |
13574 | mutex_unlock(&dev->struct_mutex); |
13575 | ||
1630fe75 CW |
13576 | /* flush any delayed tasks or pending work */ |
13577 | flush_scheduled_work(); | |
13578 | ||
db31af1d JN |
13579 | /* destroy the backlight and sysfs files before encoders/connectors */ |
13580 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
13581 | struct intel_connector *intel_connector; |
13582 | ||
13583 | intel_connector = to_intel_connector(connector); | |
13584 | intel_connector->unregister(intel_connector); | |
db31af1d | 13585 | } |
d9255d57 | 13586 | |
79e53945 | 13587 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
13588 | |
13589 | intel_cleanup_overlay(dev); | |
ae48434c ID |
13590 | |
13591 | mutex_lock(&dev->struct_mutex); | |
13592 | intel_cleanup_gt_powersave(dev); | |
13593 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13594 | } |
13595 | ||
f1c79df3 ZW |
13596 | /* |
13597 | * Return which encoder is currently attached for connector. | |
13598 | */ | |
df0e9248 | 13599 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 13600 | { |
df0e9248 CW |
13601 | return &intel_attached_encoder(connector)->base; |
13602 | } | |
f1c79df3 | 13603 | |
df0e9248 CW |
13604 | void intel_connector_attach_encoder(struct intel_connector *connector, |
13605 | struct intel_encoder *encoder) | |
13606 | { | |
13607 | connector->encoder = encoder; | |
13608 | drm_mode_connector_attach_encoder(&connector->base, | |
13609 | &encoder->base); | |
79e53945 | 13610 | } |
28d52043 DA |
13611 | |
13612 | /* | |
13613 | * set vga decode state - true == enable VGA decode | |
13614 | */ | |
13615 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
13616 | { | |
13617 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 13618 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
13619 | u16 gmch_ctrl; |
13620 | ||
75fa041d CW |
13621 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
13622 | DRM_ERROR("failed to read control word\n"); | |
13623 | return -EIO; | |
13624 | } | |
13625 | ||
c0cc8a55 CW |
13626 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
13627 | return 0; | |
13628 | ||
28d52043 DA |
13629 | if (state) |
13630 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
13631 | else | |
13632 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
13633 | |
13634 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
13635 | DRM_ERROR("failed to write control word\n"); | |
13636 | return -EIO; | |
13637 | } | |
13638 | ||
28d52043 DA |
13639 | return 0; |
13640 | } | |
c4a1d9e4 | 13641 | |
c4a1d9e4 | 13642 | struct intel_display_error_state { |
ff57f1b0 PZ |
13643 | |
13644 | u32 power_well_driver; | |
13645 | ||
63b66e5b CW |
13646 | int num_transcoders; |
13647 | ||
c4a1d9e4 CW |
13648 | struct intel_cursor_error_state { |
13649 | u32 control; | |
13650 | u32 position; | |
13651 | u32 base; | |
13652 | u32 size; | |
52331309 | 13653 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13654 | |
13655 | struct intel_pipe_error_state { | |
ddf9c536 | 13656 | bool power_domain_on; |
c4a1d9e4 | 13657 | u32 source; |
f301b1e1 | 13658 | u32 stat; |
52331309 | 13659 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13660 | |
13661 | struct intel_plane_error_state { | |
13662 | u32 control; | |
13663 | u32 stride; | |
13664 | u32 size; | |
13665 | u32 pos; | |
13666 | u32 addr; | |
13667 | u32 surface; | |
13668 | u32 tile_offset; | |
52331309 | 13669 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
13670 | |
13671 | struct intel_transcoder_error_state { | |
ddf9c536 | 13672 | bool power_domain_on; |
63b66e5b CW |
13673 | enum transcoder cpu_transcoder; |
13674 | ||
13675 | u32 conf; | |
13676 | ||
13677 | u32 htotal; | |
13678 | u32 hblank; | |
13679 | u32 hsync; | |
13680 | u32 vtotal; | |
13681 | u32 vblank; | |
13682 | u32 vsync; | |
13683 | } transcoder[4]; | |
c4a1d9e4 CW |
13684 | }; |
13685 | ||
13686 | struct intel_display_error_state * | |
13687 | intel_display_capture_error_state(struct drm_device *dev) | |
13688 | { | |
fbee40df | 13689 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 13690 | struct intel_display_error_state *error; |
63b66e5b CW |
13691 | int transcoders[] = { |
13692 | TRANSCODER_A, | |
13693 | TRANSCODER_B, | |
13694 | TRANSCODER_C, | |
13695 | TRANSCODER_EDP, | |
13696 | }; | |
c4a1d9e4 CW |
13697 | int i; |
13698 | ||
63b66e5b CW |
13699 | if (INTEL_INFO(dev)->num_pipes == 0) |
13700 | return NULL; | |
13701 | ||
9d1cb914 | 13702 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
13703 | if (error == NULL) |
13704 | return NULL; | |
13705 | ||
190be112 | 13706 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
13707 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
13708 | ||
055e393f | 13709 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 13710 | error->pipe[i].power_domain_on = |
f458ebbc DV |
13711 | __intel_display_power_is_enabled(dev_priv, |
13712 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 13713 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
13714 | continue; |
13715 | ||
5efb3e28 VS |
13716 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
13717 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
13718 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
13719 | |
13720 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
13721 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 13722 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 13723 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
13724 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
13725 | } | |
ca291363 PZ |
13726 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
13727 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
13728 | if (INTEL_INFO(dev)->gen >= 4) { |
13729 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
13730 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
13731 | } | |
13732 | ||
c4a1d9e4 | 13733 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 13734 | |
3abfce77 | 13735 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 13736 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
13737 | } |
13738 | ||
13739 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
13740 | if (HAS_DDI(dev_priv->dev)) | |
13741 | error->num_transcoders++; /* Account for eDP. */ | |
13742 | ||
13743 | for (i = 0; i < error->num_transcoders; i++) { | |
13744 | enum transcoder cpu_transcoder = transcoders[i]; | |
13745 | ||
ddf9c536 | 13746 | error->transcoder[i].power_domain_on = |
f458ebbc | 13747 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 13748 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 13749 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
13750 | continue; |
13751 | ||
63b66e5b CW |
13752 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
13753 | ||
13754 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
13755 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
13756 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
13757 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
13758 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
13759 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
13760 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
13761 | } |
13762 | ||
13763 | return error; | |
13764 | } | |
13765 | ||
edc3d884 MK |
13766 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
13767 | ||
c4a1d9e4 | 13768 | void |
edc3d884 | 13769 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
13770 | struct drm_device *dev, |
13771 | struct intel_display_error_state *error) | |
13772 | { | |
055e393f | 13773 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
13774 | int i; |
13775 | ||
63b66e5b CW |
13776 | if (!error) |
13777 | return; | |
13778 | ||
edc3d884 | 13779 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 13780 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 13781 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 13782 | error->power_well_driver); |
055e393f | 13783 | for_each_pipe(dev_priv, i) { |
edc3d884 | 13784 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
13785 | err_printf(m, " Power: %s\n", |
13786 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 13787 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 13788 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
13789 | |
13790 | err_printf(m, "Plane [%d]:\n", i); | |
13791 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
13792 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 13793 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
13794 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
13795 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 13796 | } |
4b71a570 | 13797 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 13798 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 13799 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
13800 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
13801 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
13802 | } |
13803 | ||
edc3d884 MK |
13804 | err_printf(m, "Cursor [%d]:\n", i); |
13805 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
13806 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
13807 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 13808 | } |
63b66e5b CW |
13809 | |
13810 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 13811 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 13812 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
13813 | err_printf(m, " Power: %s\n", |
13814 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
13815 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
13816 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
13817 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
13818 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
13819 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
13820 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
13821 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
13822 | } | |
c4a1d9e4 | 13823 | } |
e2fcdaa9 VS |
13824 | |
13825 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
13826 | { | |
13827 | struct intel_crtc *crtc; | |
13828 | ||
13829 | for_each_intel_crtc(dev, crtc) { | |
13830 | struct intel_unpin_work *work; | |
e2fcdaa9 | 13831 | |
5e2d7afc | 13832 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
13833 | |
13834 | work = crtc->unpin_work; | |
13835 | ||
13836 | if (work && work->event && | |
13837 | work->event->base.file_priv == file) { | |
13838 | kfree(work->event); | |
13839 | work->event = NULL; | |
13840 | } | |
13841 | ||
5e2d7afc | 13842 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
13843 | } |
13844 | } |