projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
ea916ea0
KM		 75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
465c120c
MR		 79};
80
3d7d6510
MR		 81/* Cursor formats */
82static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84};
85
6b383a7f 86static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 87
f1f644dc 88static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 89 struct intel_crtc_state *pipe_config);
18442d08 90static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 91 struct intel_crtc_state *pipe_config);
f1f644dc 92
eb1bfe80
JB		 93static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
5b18e57c
DV		 97static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 99static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
29407aab 102static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 103static void haswell_set_pipeconf(struct drm_crtc *crtc);
104static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 105static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
d288f65f 107static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 108 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 109static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 111static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
bfd16b2a
ML		 115static void skylake_pfit_enable(struct intel_crtc *crtc);
116static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117static void ironlake_pfit_enable(struct intel_crtc *crtc);
043e9bda 118static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 119
79e53945 120typedef struct {
0206e353 121 int min, max;
79e53945
JB		 122} intel_range_t;
123
124typedef struct {
0206e353
AJ		 125 int dot_limit;
126 int p2_slow, p2_fast;
79e53945
JB		 127} intel_p2_t;
128
d4906093
ML		 129typedef struct intel_limit intel_limit_t;
130struct intel_limit {
0206e353
AJ		 131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
d4906093 133};
79e53945 134
bfa7df01
VS		 135/* returns HPLL frequency in kHz */
136static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137{
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147}
148
149static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151{
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169}
170
d2acd215
DV		 171int
172intel_pch_rawclk(struct drm_device *dev)
173{
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179}
180
79e50a4f
JN		 181/* hrawclock is 1/4 the FSB frequency */
182int intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
bfa7df01
VS		 214static void intel_update_czclk(struct drm_i915_private *dev_priv)
215{
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223}
224
021357ac
CW		 225static inline u32 /* units of 100MHz */
226intel_fdi_link_freq(struct drm_device *dev)
227{
8b99e68c
CW		 228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
021357ac
CW		 233}
234
5d536e28 235static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 236 .dot = { .min = 25000, .max = 350000 },
9c333719 237 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 238 .n = { .min = 2, .max = 16 },
0206e353
AJ		 239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 246};
247
5d536e28
DV		 248static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
9c333719 250 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 251 .n = { .min = 2, .max = 16 },
5d536e28
DV		 252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259};
260
e4b36699 261static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 262 .dot = { .min = 25000, .max = 350000 },
9c333719 263 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 264 .n = { .min = 2, .max = 16 },
0206e353
AJ		 265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
e4b36699 272};
273e27ca 273
e4b36699 274static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 285};
286
287static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 298};
299
273e27ca 300
e4b36699 301static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
044c7c41 313 },
e4b36699
KP		 314};
315
316static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 327};
328
329static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
044c7c41 340 },
e4b36699
KP		 341};
342
343static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
044c7c41 354 },
e4b36699
KP		 355};
356
f2b115e6 357static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 360 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
273e27ca 363 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 370};
371
f2b115e6 372static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 383};
384
273e27ca
EA		 385/* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
b91ad0ec 390static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 401};
402
b91ad0ec 403static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 414};
415
416static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 427};
428
273e27ca 429/* LVDS 100mhz refclk limits. */
b91ad0ec 430static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
0206e353 438 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 441};
442
443static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
0206e353 451 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 454};
455
dc730512 456static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 464 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 465 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
b99ab663 468 .p1 = { .min = 2, .max = 3 },
5fdc9c49 469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 470};
471
ef9348c8
CML		 472static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 480 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486};
487
5ab7b0b7
ID		 488static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
e6292556 491 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498};
499
cdba954e
ACO		 500static bool
501needs_modeset(struct drm_crtc_state *state)
502{
fc596660 503 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 504}
505
e0638cdf
PZ		 506/**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
4093561b 509bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 510{
409ee761 511 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 512 struct intel_encoder *encoder;
513
409ee761 514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 515 if (encoder->type == type)
516 return true;
517
518 return false;
519}
520
d0737e1d
ACO		 521/**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
a93e255f
ACO		 527static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
d0737e1d 529{
a93e255f 530 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 531 struct drm_connector *connector;
a93e255f 532 struct drm_connector_state *connector_state;
d0737e1d 533 struct intel_encoder *encoder;
a93e255f
ACO		 534 int i, num_connectors = 0;
535
da3ced29 536 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
d0737e1d 541
a93e255f
ACO		 542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
d0737e1d 544 return true;
a93e255f
ACO		 545 }
546
547 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 548
549 return false;
550}
551
a93e255f
ACO		 552static const intel_limit_t *
553intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 554{
a93e255f 555 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 556 const intel_limit_t *limit;
b91ad0ec 557
a93e255f 558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 559 if (intel_is_dual_link_lvds(dev)) {
1b894b59 560 if (refclk == 100000)
b91ad0ec
ZW		 561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
1b894b59 565 if (refclk == 100000)
b91ad0ec
ZW		 566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
c6bb3538 570 } else
b91ad0ec 571 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 572
573 return limit;
574}
575
a93e255f
ACO		 576static const intel_limit_t *
577intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 578{
a93e255f 579 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 580 const intel_limit_t *limit;
581
a93e255f 582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 583 if (intel_is_dual_link_lvds(dev))
e4b36699 584 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 585 else
e4b36699 586 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 589 limit = &intel_limits_g4x_hdmi;
a93e255f 590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 591 limit = &intel_limits_g4x_sdvo;
044c7c41 592 } else /* The option is for other outputs */
e4b36699 593 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 594
595 return limit;
596}
597
a93e255f
ACO		 598static const intel_limit_t *
599intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 600{
a93e255f 601 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 602 const intel_limit_t *limit;
603
5ab7b0b7
ID		 604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
a93e255f 607 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 608 else if (IS_G4X(dev)) {
a93e255f 609 limit = intel_g4x_limit(crtc_state);
f2b115e6 610 } else if (IS_PINEVIEW(dev)) {
a93e255f 611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 612 limit = &intel_limits_pineview_lvds;
2177832f 613 else
f2b115e6 614 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
a0c4da24 617 } else if (IS_VALLEYVIEW(dev)) {
dc730512 618 limit = &intel_limits_vlv;
a6c45cf0 619 } else if (!IS_GEN2(dev)) {
a93e255f 620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
79e53945 624 } else {
a93e255f 625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 626 limit = &intel_limits_i8xx_lvds;
a93e255f 627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 628 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 629 else
630 limit = &intel_limits_i8xx_dac;
79e53945
JB		 631 }
632 return limit;
633}
634
dccbea3b
ID		 635/*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
f2b115e6 643/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 644static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 645{
2177832f
SL		 646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
ed5ca77e 648 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 649 return 0;
fb03ac01
VS		 650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 652
653 return clock->dot;
2177832f
SL		 654}
655
7429e9d4
DV		 656static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657{
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659}
660
dccbea3b 661static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 662{
7429e9d4 663 clock->m = i9xx_dpll_compute_m(clock);
79e53945 664 clock->p = clock->p1 * clock->p2;
ed5ca77e 665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 666 return 0;
fb03ac01
VS		 667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 669
670 return clock->dot;
79e53945
JB		 671}
672
dccbea3b 673static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 674{
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 678 return 0;
589eca67
ID		 679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 681
682 return clock->dot / 5;
589eca67
ID		 683}
684
dccbea3b 685int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 686{
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 690 return 0;
ef9348c8
CML		 691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 694
695 return clock->dot / 5;
ef9348c8
CML		 696}
697
7c04d1d9 698#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 699/**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
1b894b59
CW		 704static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
79e53945 707{
f01b7962
VS		 708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
79e53945 710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 711 INTELPllInvalid("p1 out of range\n");
79e53945 712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 713 INTELPllInvalid("m2 out of range\n");
79e53945 714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 715 INTELPllInvalid("m1 out of range\n");
f01b7962 716
5ab7b0b7 717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
5ab7b0b7 721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
79e53945 728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 729 INTELPllInvalid("vco out of range\n");
79e53945
JB		 730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 734 INTELPllInvalid("dot out of range\n");
79e53945
JB		 735
736 return true;
737}
738
3b1429d9
VS		 739static int
740i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
79e53945 743{
3b1429d9 744 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 745
a93e255f 746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 747 /*
a210b028
DV		 748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
79e53945 751 */
1974cad0 752 if (intel_is_dual_link_lvds(dev))
3b1429d9 753 return limit->p2.p2_fast;
79e53945 754 else
3b1429d9 755 return limit->p2.p2_slow;
79e53945
JB		 756 } else {
757 if (target < limit->p2.dot_limit)
3b1429d9 758 return limit->p2.p2_slow;
79e53945 759 else
3b1429d9 760 return limit->p2.p2_fast;
79e53945 761 }
3b1429d9
VS		 762}
763
764static bool
765i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769{
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
79e53945 773
0206e353 774 memset(best_clock, 0, sizeof(*best_clock));
79e53945 775
3b1429d9
VS		 776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
42158660
ZY		 778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 782 if (clock.m2 >= clock.m1)
42158660
ZY		 783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 788 int this_err;
789
dccbea3b 790 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809}
810
811static bool
a93e255f
ACO		 812pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
79e53945 816{
3b1429d9 817 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 818 intel_clock_t clock;
79e53945
JB		 819 int err = target;
820
0206e353 821 memset(best_clock, 0, sizeof(*best_clock));
79e53945 822
3b1429d9
VS		 823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
42158660
ZY		 825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 833 int this_err;
834
dccbea3b 835 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
79e53945 838 continue;
cec2f356
SP		 839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
79e53945
JB		 842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854}
855
d4906093 856static bool
a93e255f
ACO		 857g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
d4906093 861{
3b1429d9 862 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 863 intel_clock_t clock;
864 int max_n;
3b1429d9 865 bool found = false;
6ba770dc
AJ		 866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 868
869 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
d4906093 873 max_n = limit->n.max;
f77f13e2 874 /* based on hardware requirement, prefer smaller n to precision */
d4906093 875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 876 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
dccbea3b 885 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
d4906093 888 continue;
1b894b59
CW		 889
890 this_err = abs(clock.dot - target);
d4906093
ML		 891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
2c07245f
ZW		 901 return found;
902}
903
d5dd62bd
ID		 904/*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913{
9ca3ba01
ID		 914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
24be4e46
ID		 924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
d5dd62bd
ID		 927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942}
943
a0c4da24 944static bool
a93e255f
ACO		 945vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
a0c4da24 949{
a93e255f 950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 951 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 952 intel_clock_t clock;
69e4f900 953 unsigned int bestppm = 1000000;
27e639bf
VS		 954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 956 bool found = false;
a0c4da24 957
6b4bf1c4
VS		 958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 961
962 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 967 clock.p = clock.p1 * clock.p2;
a0c4da24 968 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 970 unsigned int ppm;
69e4f900 971
6b4bf1c4
VS		 972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
dccbea3b 975 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 976
f01b7962
VS		 977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
43b0ac53
VS		 979 continue;
980
d5dd62bd
ID		 981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
6b4bf1c4 986
d5dd62bd
ID		 987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
a0c4da24
JB		 990 }
991 }
992 }
993 }
a0c4da24 994
49e497ef 995 return found;
a0c4da24 996}
a4fc5ed6 997
ef9348c8 998static bool
a93e255f
ACO		 999chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003{
a93e255f 1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 1005 struct drm_device *dev = crtc->base.dev;
9ca3ba01 1006 unsigned int best_error_ppm;
ef9348c8
CML		 1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 1012 best_error_ppm = 1000000;
ef9348c8
CML		 1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 1026 unsigned int error_ppm;
ef9348c8
CML		 1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
dccbea3b 1038 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
9ca3ba01
ID		 1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
ef9348c8
CML		 1050 }
1051 }
1052
1053 return found;
1054}
1055
5ab7b0b7
ID		 1056bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058{
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063}
1064
20ddf665
VS		 1065bool intel_crtc_active(struct drm_crtc *crtc)
1066{
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
241bfc38 1072 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 1073 * as Haswell has gained clock readout/fastboot support.
1074 *
66e514c1 1075 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1076 * properly reconstruct framebuffers.
c3d1f436
MR		 1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
20ddf665 1081 */
c3d1f436 1082 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1084}
1085
a5c961d1
PZ		 1086enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088{
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
6e3c9717 1092 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1093}
1094
fbf49ea2
VS		 1095static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096{
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1108 msleep(5);
fbf49ea2
VS		 1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112}
1113
ab7ad7f6
KP		 1114/*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1116 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
ab7ad7f6
KP		 1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
58e10eb9 1128 *
9d0498a2 1129 */
575f7ab7 1130static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1131{
575f7ab7 1132 struct drm_device *dev = crtc->base.dev;
9d0498a2 1133 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1135 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1138 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1139
1140 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
284637d9 1143 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1144 } else {
ab7ad7f6 1145 /* Wait for the display line to settle */
fbf49ea2 1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1147 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1148 }
79e53945
JB		 1149}
1150
b24e7179
JB		 1151static const char *state_string(bool enabled)
1152{
1153 return enabled ? "on" : "off";
1154}
1155
1156/* Only for pre-ILK configs */
55607e8a
DV		 1157void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
b24e7179 1159{
b24e7179
JB		 1160 u32 val;
1161 bool cur_state;
1162
649636ef 1163 val = I915_READ(DPLL(pipe));
b24e7179 1164 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1165 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1168}
b24e7179 1169
23538ef1
JN		 1170/* XXX: the dsi pll is shared between MIPI DSI ports */
1171static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172{
1173 u32 val;
1174 bool cur_state;
1175
a580516d 1176 mutex_lock(&dev_priv->sb_lock);
23538ef1 1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1178 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1179
1180 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1181 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184}
1185#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
55607e8a 1188struct intel_shared_dpll *
e2b78267
DV		 1189intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190{
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
6e3c9717 1193 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1194 return NULL;
1195
6e3c9717 1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1197}
1198
040484af 1199/* For ILK+ */
55607e8a
DV		 1200void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1202 bool state)
040484af 1203{
040484af 1204 bool cur_state;
5358901f 1205 struct intel_dpll_hw_state hw_state;
040484af 1206
92b27b08 1207 if (WARN (!pll,
46edb027 1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1209 return;
ee7b9f93 1210
5358901f 1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1212 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
040484af 1215}
040484af
JB		 1216
1217static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219{
040484af 1220 bool cur_state;
ad80a810
PZ		 1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222 pipe);
040484af 1223
affa9354
PZ		 1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
649636ef 1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
ad80a810 1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7 1228 } else {
649636ef 1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
bf507ef7
ED		 1230 cur_state = !!(val & FDI_TX_ENABLE);
1231 }
e2c719b7 1232 I915_STATE_WARN(cur_state != state,
040484af
JB		 1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1235}
1236#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241{
040484af
JB		 1242 u32 val;
1243 bool cur_state;
1244
649636ef 1245 val = I915_READ(FDI_RX_CTL(pipe));
d63fa0dc 1246 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1247 I915_STATE_WARN(cur_state != state,
040484af
JB		 1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1250}
1251#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256{
040484af
JB		 1257 u32 val;
1258
1259 /* ILK FDI PLL is always enabled */
3d13ef2e 1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1261 return;
1262
bf507ef7 1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1264 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1265 return;
1266
649636ef 1267 val = I915_READ(FDI_TX_CTL(pipe));
e2c719b7 1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1269}
1270
55607e8a
DV		 1271void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
040484af 1273{
040484af 1274 u32 val;
55607e8a 1275 bool cur_state;
040484af 1276
649636ef 1277 val = I915_READ(FDI_RX_CTL(pipe));
55607e8a 1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1279 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
040484af
JB		 1282}
1283
b680c37a
DV		 1284void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
ea0760cf 1286{
bedd4dba
JN		 1287 struct drm_device *dev = dev_priv->dev;
1288 int pp_reg;
ea0760cf
JB		 1289 u32 val;
1290 enum pipe panel_pipe = PIPE_A;
0de3b485 1291 bool locked = true;
ea0760cf 1292
bedd4dba
JN		 1293 if (WARN_ON(HAS_DDI(dev)))
1294 return;
1295
1296 if (HAS_PCH_SPLIT(dev)) {
1297 u32 port_sel;
1298
ea0760cf 1299 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309 panel_pipe = pipe;
ea0760cf
JB		 1310 } else {
1311 pp_reg = PP_CONTROL;
bedd4dba
JN		 1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
ea0760cf
JB		 1314 }
1315
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1319 locked = false;
1320
e2c719b7 1321 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1322 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1323 pipe_name(pipe));
ea0760cf
JB		 1324}
1325
93ce0ba6
JN		 1326static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328{
1329 struct drm_device *dev = dev_priv->dev;
1330 bool cur_state;
1331
d9d82081 1332 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
d9d82081 1334 else
5efb3e28 1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1336
e2c719b7 1337 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340}
1341#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
b840d907
JB		 1344void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
b24e7179 1346{
63d7bbe9 1347 bool cur_state;
702e7a56
PZ		 1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349 pipe);
b24e7179 1350
b6b5d049
VS		 1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1354 state = true;
1355
f458ebbc 1356 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1358 cur_state = false;
1359 } else {
649636ef 1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
69310161
PZ		 1361 cur_state = !!(val & PIPECONF_ENABLE);
1362 }
1363
e2c719b7 1364 I915_STATE_WARN(cur_state != state,
63d7bbe9 1365 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1366 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1367}
1368
931872fc
CW		 1369static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
b24e7179 1371{
b24e7179 1372 u32 val;
931872fc 1373 bool cur_state;
b24e7179 1374
649636ef 1375 val = I915_READ(DSPCNTR(plane));
931872fc 1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1377 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1380}
1381
931872fc
CW		 1382#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
b24e7179
JB		 1385static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387{
653e1026 1388 struct drm_device *dev = dev_priv->dev;
649636ef 1389 int i;
b24e7179 1390
653e1026
VS		 1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
649636ef 1393 u32 val = I915_READ(DSPCNTR(pipe));
e2c719b7 1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1395 "plane %c assertion failure, should be disabled but not\n",
1396 plane_name(pipe));
19ec1358 1397 return;
28c05794 1398 }
19ec1358 1399
b24e7179 1400 /* Need to check both planes against the pipe */
055e393f 1401 for_each_pipe(dev_priv, i) {
649636ef
VS		 1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
b24e7179 1404 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1408 }
1409}
1410
19332d7a
JB		 1411static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413{
20674eef 1414 struct drm_device *dev = dev_priv->dev;
649636ef 1415 int sprite;
19332d7a 1416
7feb8b88 1417 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1418 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1423 }
1424 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1425 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
e2c719b7 1427 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1429 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1430 }
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
649636ef 1432 u32 val = I915_READ(SPRCTL(pipe));
e2c719b7 1433 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
649636ef 1437 u32 val = I915_READ(DVSCNTR(pipe));
e2c719b7 1438 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1440 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1441 }
1442}
1443
08c71e5e
VS		 1444static void assert_vblank_disabled(struct drm_crtc *crtc)
1445{
e2c719b7 1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1447 drm_crtc_vblank_put(crtc);
1448}
1449
89eff4be 1450static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1451{
1452 u32 val;
1453 bool enabled;
1454
e2c719b7 1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1456
92f2584a
JB		 1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1461}
1462
ab9412ba
DV		 1463static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
92f2584a 1465{
92f2584a
JB		 1466 u32 val;
1467 bool enabled;
1468
649636ef 1469 val = I915_READ(PCH_TRANSCONF(pipe));
92f2584a 1470 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1471 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 pipe_name(pipe));
92f2584a
JB		 1474}
1475
4e634389
KP		 1476static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1478{
1479 if ((val & DP_PORT_EN) == 0)
1480 return false;
1481
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486 return false;
44f37d1f
CML		 1487 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489 return false;
f0575e92
KP		 1490 } else {
1491 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492 return false;
1493 }
1494 return true;
1495}
1496
1519b995
KP		 1497static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499{
dc0fa718 1500 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1501 return false;
1502
1503 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1504 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1505 return false;
44f37d1f
CML		 1506 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508 return false;
1519b995 1509 } else {
dc0fa718 1510 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1511 return false;
1512 }
1513 return true;
1514}
1515
1516static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517 enum pipe pipe, u32 val)
1518{
1519 if ((val & LVDS_PORT_EN) == 0)
1520 return false;
1521
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527 return false;
1528 }
1529 return true;
1530}
1531
1532static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, u32 val)
1534{
1535 if ((val & ADPA_DAC_ENABLE) == 0)
1536 return false;
1537 if (HAS_PCH_CPT(dev_priv->dev)) {
1538 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539 return false;
1540 } else {
1541 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542 return false;
1543 }
1544 return true;
1545}
1546
291906f1 1547static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1548 enum pipe pipe, int reg, u32 port_sel)
291906f1 1549{
47a05eca 1550 u32 val = I915_READ(reg);
e2c719b7 1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1553 reg, pipe_name(pipe));
de9a35ab 1554
e2c719b7 1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1556 && (val & DP_PIPEB_SELECT),
de9a35ab 1557 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1558}
1559
1560static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, int reg)
1562{
47a05eca 1563 u32 val = I915_READ(reg);
e2c719b7 1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1566 reg, pipe_name(pipe));
de9a35ab 1567
e2c719b7 1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1569 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1570 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1571}
1572
1573static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575{
291906f1 1576 u32 val;
291906f1 1577
f0575e92
KP		 1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1 1581
649636ef 1582 val = I915_READ(PCH_ADPA);
e2c719b7 1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
649636ef 1587 val = I915_READ(PCH_LVDS);
e2c719b7 1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1590 pipe_name(pipe));
291906f1 1591
e2debe91
PZ		 1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1595}
1596
d288f65f 1597static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1598 const struct intel_crtc_state *pipe_config)
87442f73 1599{
426115cf
DV		 1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
d288f65f 1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1604
426115cf 1605 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1611 if (IS_MOBILE(dev_priv->dev))
426115cf 1612 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1613
426115cf
DV		 1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
d288f65f 1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1622 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1623
1624 /* We do this three times for luck */
426115cf 1625 I915_WRITE(reg, dpll);
87442f73
DV		 1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
426115cf 1628 I915_WRITE(reg, dpll);
87442f73
DV		 1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
426115cf 1631 I915_WRITE(reg, dpll);
87442f73
DV		 1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634}
1635
d288f65f 1636static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1637 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1638{
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
a580516d 1649 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
54433e91
VS		 1656 mutex_unlock(&dev_priv->sb_lock);
1657
9d556c99
CML		 1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
d288f65f 1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1665
1666 /* Check PLL is locked */
a11b0703 1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
a11b0703 1670 /* not sure when this should be written */
d288f65f 1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1672 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1673}
1674
1c4e0274
VS		 1675static int intel_num_dvo_pipes(struct drm_device *dev)
1676{
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
3538b9df 1681 count += crtc->base.state->active &&
409ee761 1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1683
1684 return count;
1685}
1686
66e3d5c0 1687static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1688{
66e3d5c0
DV		 1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
6e3c9717 1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1693
66e3d5c0 1694 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1695
63d7bbe9 1696 /* No really, not for ILK+ */
3d13ef2e 1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1698
1699 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1702
1c4e0274
VS		 1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
66e3d5c0
DV		 1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1722 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
63d7bbe9
JB		 1731
1732 /* We do this three times for luck */
66e3d5c0 1733 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
66e3d5c0 1736 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
66e3d5c0 1739 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742}
1743
1744/**
50b44a44 1745 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1c4e0274 1753static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1754{
1c4e0274
VS		 1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
409ee761 1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1762 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
b6b5d049
VS		 1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
b8afb911 1777 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1778 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1779}
1780
f6071166
JB		 1781static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782{
b8afb911 1783 u32 val;
f6071166
JB		 1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
e5cbfbfb
ID		 1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
b8afb911 1792 val = DPLL_VGA_MODE_DIS;
f6071166 1793 if (pipe == PIPE_B)
60bfe44f 1794 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1795 I915_WRITE(DPLL(pipe), val);
1796 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1797
1798}
1799
1800static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801{
d752048d 1802 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1803 u32 val;
1804
a11b0703
VS		 1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1807
a11b0703 1808 /* Set PLL en = 0 */
60bfe44f
VS		 1809 val = DPLL_SSC_REF_CLK_CHV |
1810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1811 if (pipe != PIPE_A)
1812 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813 I915_WRITE(DPLL(pipe), val);
1814 POSTING_READ(DPLL(pipe));
d752048d 1815
a580516d 1816 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1817
1818 /* Disable 10bit clock to display controller */
1819 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820 val &= ~DPIO_DCLKP_EN;
1821 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
a580516d 1823 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1824}
1825
e4607fcf 1826void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1827 struct intel_digital_port *dport,
1828 unsigned int expected_mask)
89b667f8
JB		 1829{
1830 u32 port_mask;
00fc31b7 1831 int dpll_reg;
89b667f8 1832
e4607fcf
CML		 1833 switch (dport->port) {
1834 case PORT_B:
89b667f8 1835 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1836 dpll_reg = DPLL(0);
e4607fcf
CML		 1837 break;
1838 case PORT_C:
89b667f8 1839 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1840 dpll_reg = DPLL(0);
9b6de0a1 1841 expected_mask <<= 4;
00fc31b7
CML		 1842 break;
1843 case PORT_D:
1844 port_mask = DPLL_PORTD_READY_MASK;
1845 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1846 break;
1847 default:
1848 BUG();
1849 }
89b667f8 1850
9b6de0a1
VS		 1851 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1854}
1855
b14b1055
DV		 1856static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857{
1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
be19f0ff
CW		 1862 if (WARN_ON(pll == NULL))
1863 return;
1864
3e369b76 1865 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1866 if (pll->active == 0) {
1867 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868 WARN_ON(pll->on);
1869 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871 pll->mode_set(dev_priv, pll);
1872 }
1873}
1874
92f2584a 1875/**
85b3894f 1876 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1877 * @dev_priv: i915 private structure
1878 * @pipe: pipe PLL to enable
1879 *
1880 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881 * drives the transcoder clock.
1882 */
85b3894f 1883static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1884{
3d13ef2e
DL		 1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1888
87a875bb 1889 if (WARN_ON(pll == NULL))
48da64a8
CW		 1890 return;
1891
3e369b76 1892 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1893 return;
ee7b9f93 1894
74dd6928 1895 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1896 pll->name, pll->active, pll->on,
e2b78267 1897 crtc->base.base.id);
92f2584a 1898
cdbd2316
DV		 1899 if (pll->active++) {
1900 WARN_ON(!pll->on);
e9d6944e 1901 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1902 return;
1903 }
f4a091c7 1904 WARN_ON(pll->on);
ee7b9f93 1905
bd2bb1b9
PZ		 1906 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
46edb027 1908 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1909 pll->enable(dev_priv, pll);
ee7b9f93 1910 pll->on = true;
92f2584a
JB		 1911}
1912
f6daaec2 1913static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1914{
3d13ef2e
DL		 1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1918
92f2584a 1919 /* PCH only available on ILK+ */
80aa9312
JB		 1920 if (INTEL_INFO(dev)->gen < 5)
1921 return;
1922
eddfcbcd
ML		 1923 if (pll == NULL)
1924 return;
92f2584a 1925
eddfcbcd 1926 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1927 return;
7a419866 1928
46edb027
DV		 1929 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930 pll->name, pll->active, pll->on,
e2b78267 1931 crtc->base.base.id);
7a419866 1932
48da64a8 1933 if (WARN_ON(pll->active == 0)) {
e9d6944e 1934 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1935 return;
1936 }
1937
e9d6944e 1938 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1939 WARN_ON(!pll->on);
cdbd2316 1940 if (--pll->active)
7a419866 1941 return;
ee7b9f93 1942
46edb027 1943 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1944 pll->disable(dev_priv, pll);
ee7b9f93 1945 pll->on = false;
bd2bb1b9
PZ		 1946
1947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1948}
1949
b8a4f404
PZ		 1950static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951 enum pipe pipe)
040484af 1952{
23670b32 1953 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1956 uint32_t reg, val, pipeconf_val;
040484af
JB		 1957
1958 /* PCH only available on ILK+ */
55522f37 1959 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1960
1961 /* Make sure PCH DPLL is enabled */
e72f9fbf 1962 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1963 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1964
1965 /* FDI must be feeding us bits for PCH ports */
1966 assert_fdi_tx_enabled(dev_priv, pipe);
1967 assert_fdi_rx_enabled(dev_priv, pipe);
1968
23670b32
DV		 1969 if (HAS_PCH_CPT(dev)) {
1970 /* Workaround: Set the timing override bit before enabling the
1971 * pch transcoder. */
1972 reg = TRANS_CHICKEN2(pipe);
1973 val = I915_READ(reg);
1974 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1975 I915_WRITE(reg, val);
59c859d6 1976 }
23670b32 1977
ab9412ba 1978 reg = PCH_TRANSCONF(pipe);
040484af 1979 val = I915_READ(reg);
5f7f726d 1980 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1981
1982 if (HAS_PCH_IBX(dev_priv->dev)) {
1983 /*
c5de7c6f
VS		 1984 * Make the BPC in transcoder be consistent with
1985 * that in pipeconf reg. For HDMI we must use 8bpc
1986 * here for both 8bpc and 12bpc.
e9bcff5c 1987 */
dfd07d72 1988 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1989 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1990 val |= PIPECONF_8BPC;
1991 else
1992 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1993 }
5f7f726d
PZ		 1994
1995 val &= ~TRANS_INTERLACE_MASK;
1996 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1997 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1998 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1999 val |= TRANS_LEGACY_INTERLACED_ILK;
2000 else
2001 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2002 else
2003 val |= TRANS_PROGRESSIVE;
2004
040484af
JB		 2005 I915_WRITE(reg, val | TRANS_ENABLE);
2006 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2007 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2008}
2009
8fb033d7 2010static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2011 enum transcoder cpu_transcoder)
040484af 2012{
8fb033d7 2013 u32 val, pipeconf_val;
8fb033d7
PZ		 2014
2015 /* PCH only available on ILK+ */
55522f37 2016 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2017
8fb033d7 2018 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2019 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2020 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2021
223a6fdf 2022 /* Workaround: set timing override bit. */
36c0d0cf 2023 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2024 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2025 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
223a6fdf 2026
25f3ef11 2027 val = TRANS_ENABLE;
937bb610 2028 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2029
9a76b1c6
PZ		 2030 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2031 PIPECONF_INTERLACED_ILK)
a35f2679 2032 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2033 else
2034 val |= TRANS_PROGRESSIVE;
2035
ab9412ba
DV		 2036 I915_WRITE(LPT_TRANSCONF, val);
2037 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2038 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2039}
2040
b8a4f404
PZ		 2041static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2042 enum pipe pipe)
040484af 2043{
23670b32
DV		 2044 struct drm_device *dev = dev_priv->dev;
2045 uint32_t reg, val;
040484af
JB		 2046
2047 /* FDI relies on the transcoder */
2048 assert_fdi_tx_disabled(dev_priv, pipe);
2049 assert_fdi_rx_disabled(dev_priv, pipe);
2050
291906f1
JB		 2051 /* Ports must be off as well */
2052 assert_pch_ports_disabled(dev_priv, pipe);
2053
ab9412ba 2054 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2055 val = I915_READ(reg);
2056 val &= ~TRANS_ENABLE;
2057 I915_WRITE(reg, val);
2058 /* wait for PCH transcoder off, transcoder state */
2059 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2060 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2061
2062 if (!HAS_PCH_IBX(dev)) {
2063 /* Workaround: Clear the timing override chicken bit again. */
2064 reg = TRANS_CHICKEN2(pipe);
2065 val = I915_READ(reg);
2066 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2067 I915_WRITE(reg, val);
2068 }
040484af
JB		 2069}
2070
ab4d966c 2071static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2072{
8fb033d7
PZ		 2073 u32 val;
2074
ab9412ba 2075 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2076 val &= ~TRANS_ENABLE;
ab9412ba 2077 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2078 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2079 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2080 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2081
2082 /* Workaround: clear timing override bit. */
36c0d0cf 2083 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2085 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
040484af
JB		 2086}
2087
b24e7179 2088/**
309cfea8 2089 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2090 * @crtc: crtc responsible for the pipe
b24e7179 2091 *
0372264a 2092 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2093 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2094 */
e1fdc473 2095static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2096{
0372264a
PZ		 2097 struct drm_device *dev = crtc->base.dev;
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 enum pipe pipe = crtc->pipe;
1a70a728 2100 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1a240d4d 2101 enum pipe pch_transcoder;
b24e7179
JB		 2102 int reg;
2103 u32 val;
2104
9e2ee2dd
VS		 2105 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2106
58c6eaa2 2107 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2108 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2109 assert_sprites_disabled(dev_priv, pipe);
2110
681e5811 2111 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2112 pch_transcoder = TRANSCODER_A;
2113 else
2114 pch_transcoder = pipe;
2115
b24e7179
JB		 2116 /*
2117 * A pipe without a PLL won't actually be able to drive bits from
2118 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2119 * need the check.
2120 */
50360403 2121 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2122 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2123 assert_dsi_pll_enabled(dev_priv);
2124 else
2125 assert_pll_enabled(dev_priv, pipe);
040484af 2126 else {
6e3c9717 2127 if (crtc->config->has_pch_encoder) {
040484af 2128 /* if driving the PCH, we need FDI enabled */
cc391bbb 2129 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2130 assert_fdi_tx_pll_enabled(dev_priv,
2131 (enum pipe) cpu_transcoder);
040484af
JB		 2132 }
2133 /* FIXME: assert CPU port conditions for SNB+ */
2134 }
b24e7179 2135
702e7a56 2136 reg = PIPECONF(cpu_transcoder);
b24e7179 2137 val = I915_READ(reg);
7ad25d48 2138 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2139 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2140 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2141 return;
7ad25d48 2142 }
00d70b15
CW		 2143
2144 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2145 POSTING_READ(reg);
b24e7179
JB		 2146}
2147
2148/**
309cfea8 2149 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2150 * @crtc: crtc whose pipes is to be disabled
b24e7179 2151 *
575f7ab7
VS		 2152 * Disable the pipe of @crtc, making sure that various hardware
2153 * specific requirements are met, if applicable, e.g. plane
2154 * disabled, panel fitter off, etc.
b24e7179
JB		 2155 *
2156 * Will wait until the pipe has shut down before returning.
2157 */
575f7ab7 2158static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2159{
575f7ab7 2160 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2161 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2162 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2163 int reg;
2164 u32 val;
2165
9e2ee2dd
VS		 2166 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2167
b24e7179
JB		 2168 /*
2169 * Make sure planes won't keep trying to pump pixels to us,
2170 * or we might hang the display.
2171 */
2172 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2173 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2174 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2175
702e7a56 2176 reg = PIPECONF(cpu_transcoder);
b24e7179 2177 val = I915_READ(reg);
00d70b15
CW		 2178 if ((val & PIPECONF_ENABLE) == 0)
2179 return;
2180
67adc644
VS		 2181 /*
2182 * Double wide has implications for planes
2183 * so best keep it disabled when not needed.
2184 */
6e3c9717 2185 if (crtc->config->double_wide)
67adc644
VS		 2186 val &= ~PIPECONF_DOUBLE_WIDE;
2187
2188 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2189 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2190 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2191 val &= ~PIPECONF_ENABLE;
2192
2193 I915_WRITE(reg, val);
2194 if ((val & PIPECONF_ENABLE) == 0)
2195 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2196}
2197
693db184
CW		 2198static bool need_vtd_wa(struct drm_device *dev)
2199{
2200#ifdef CONFIG_INTEL_IOMMU
2201 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2202 return true;
2203#endif
2204 return false;
2205}
2206
50470bb0 2207unsigned int
6761dd31 2208intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
fe47ea0c 2209 uint64_t fb_format_modifier, unsigned int plane)
a57ce0b2 2210{
6761dd31
TU		 2211 unsigned int tile_height;
2212 uint32_t pixel_bytes;
a57ce0b2 2213
b5d0e9bf
DL		 2214 switch (fb_format_modifier) {
2215 case DRM_FORMAT_MOD_NONE:
2216 tile_height = 1;
2217 break;
2218 case I915_FORMAT_MOD_X_TILED:
2219 tile_height = IS_GEN2(dev) ? 16 : 8;
2220 break;
2221 case I915_FORMAT_MOD_Y_TILED:
2222 tile_height = 32;
2223 break;
2224 case I915_FORMAT_MOD_Yf_TILED:
fe47ea0c 2225 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
6761dd31 2226 switch (pixel_bytes) {
b5d0e9bf 2227 default:
6761dd31 2228 case 1:
b5d0e9bf
DL		 2229 tile_height = 64;
2230 break;
6761dd31
TU		 2231 case 2:
2232 case 4:
b5d0e9bf
DL		 2233 tile_height = 32;
2234 break;
6761dd31 2235 case 8:
b5d0e9bf
DL		 2236 tile_height = 16;
2237 break;
6761dd31 2238 case 16:
b5d0e9bf
DL		 2239 WARN_ONCE(1,
2240 "128-bit pixels are not supported for display!");
2241 tile_height = 16;
2242 break;
2243 }
2244 break;
2245 default:
2246 MISSING_CASE(fb_format_modifier);
2247 tile_height = 1;
2248 break;
2249 }
091df6cb 2250
6761dd31
TU		 2251 return tile_height;
2252}
2253
2254unsigned int
2255intel_fb_align_height(struct drm_device *dev, unsigned int height,
2256 uint32_t pixel_format, uint64_t fb_format_modifier)
2257{
2258 return ALIGN(height, intel_tile_height(dev, pixel_format,
fe47ea0c 2259 fb_format_modifier, 0));
a57ce0b2
JB		 2260}
2261
f64b98cd
TU		 2262static int
2263intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2264 const struct drm_plane_state *plane_state)
2265{
50470bb0 2266 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2267 unsigned int tile_height, tile_pitch;
50470bb0 2268
f64b98cd
TU		 2269 *view = i915_ggtt_view_normal;
2270
50470bb0
TU		 2271 if (!plane_state)
2272 return 0;
2273
121920fa 2274 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2275 return 0;
2276
9abc4648 2277 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2278
2279 info->height = fb->height;
2280 info->pixel_format = fb->pixel_format;
2281 info->pitch = fb->pitches[0];
89e3e142 2282 info->uv_offset = fb->offsets[1];
50470bb0
TU		 2283 info->fb_modifier = fb->modifier[0];
2284
84fe03f7 2285 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
fe47ea0c 2286 fb->modifier[0], 0);
84fe03f7
TU		 2287 tile_pitch = PAGE_SIZE / tile_height;
2288 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2289 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2290 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2291
89e3e142
TU		 2292 if (info->pixel_format == DRM_FORMAT_NV12) {
2293 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2294 fb->modifier[0], 1);
2295 tile_pitch = PAGE_SIZE / tile_height;
2296 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2297 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2298 tile_height);
2299 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2300 PAGE_SIZE;
2301 }
2302
f64b98cd
TU		 2303 return 0;
2304}
2305
4e9a86b6
VS		 2306static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2307{
2308 if (INTEL_INFO(dev_priv)->gen >= 9)
2309 return 256 * 1024;
985b8bb4
VS		 2310 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2311 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2312 return 128 * 1024;
2313 else if (INTEL_INFO(dev_priv)->gen >= 4)
2314 return 4 * 1024;
2315 else
44c5905e 2316 return 0;
4e9a86b6
VS		 2317}
2318
127bd2ac 2319int
850c4cdc
TU		 2320intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2321 struct drm_framebuffer *fb,
7580d774 2322 const struct drm_plane_state *plane_state)
6b95a207 2323{
850c4cdc 2324 struct drm_device *dev = fb->dev;
ce453d81 2325 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2326 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2327 struct i915_ggtt_view view;
6b95a207
KH		 2328 u32 alignment;
2329 int ret;
2330
ebcdd39e
MR		 2331 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2332
7b911adc
TU		 2333 switch (fb->modifier[0]) {
2334 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2335 alignment = intel_linear_alignment(dev_priv);
6b95a207 2336 break;
7b911adc 2337 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2338 if (INTEL_INFO(dev)->gen >= 9)
2339 alignment = 256 * 1024;
2340 else {
2341 /* pin() will align the object as required by fence */
2342 alignment = 0;
2343 }
6b95a207 2344 break;
7b911adc 2345 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2346 case I915_FORMAT_MOD_Yf_TILED:
2347 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2348 "Y tiling bo slipped through, driver bug!\n"))
2349 return -EINVAL;
2350 alignment = 1 * 1024 * 1024;
2351 break;
6b95a207 2352 default:
7b911adc
TU		 2353 MISSING_CASE(fb->modifier[0]);
2354 return -EINVAL;
6b95a207
KH		 2355 }
2356
f64b98cd
TU		 2357 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2358 if (ret)
2359 return ret;
2360
693db184
CW		 2361 /* Note that the w/a also requires 64 PTE of padding following the
2362 * bo. We currently fill all unused PTE with the shadow page and so
2363 * we should always have valid PTE following the scanout preventing
2364 * the VT-d warning.
2365 */
2366 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2367 alignment = 256 * 1024;
2368
d6dd6843
PZ		 2369 /*
2370 * Global gtt pte registers are special registers which actually forward
2371 * writes to a chunk of system memory. Which means that there is no risk
2372 * that the register values disappear as soon as we call
2373 * intel_runtime_pm_put(), so it is correct to wrap only the
2374 * pin/unpin/fence and not more.
2375 */
2376 intel_runtime_pm_get(dev_priv);
2377
7580d774
ML		 2378 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2379 &view);
48b956c5 2380 if (ret)
b26a6b35 2381 goto err_pm;
6b95a207
KH		 2382
2383 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2384 * fence, whereas 965+ only requires a fence if using
2385 * framebuffer compression. For simplicity, we always install
2386 * a fence as the cost is not that onerous.
2387 */
06d98131 2388 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2389 if (ret == -EDEADLK) {
2390 /*
2391 * -EDEADLK means there are no free fences
2392 * no pending flips.
2393 *
2394 * This is propagated to atomic, but it uses
2395 * -EDEADLK to force a locking recovery, so
2396 * change the returned error to -EBUSY.
2397 */
2398 ret = -EBUSY;
2399 goto err_unpin;
2400 } else if (ret)
9a5a53b3 2401 goto err_unpin;
1690e1eb 2402
9a5a53b3 2403 i915_gem_object_pin_fence(obj);
6b95a207 2404
d6dd6843 2405 intel_runtime_pm_put(dev_priv);
6b95a207 2406 return 0;
48b956c5
CW		 2407
2408err_unpin:
f64b98cd 2409 i915_gem_object_unpin_from_display_plane(obj, &view);
b26a6b35 2410err_pm:
d6dd6843 2411 intel_runtime_pm_put(dev_priv);
48b956c5 2412 return ret;
6b95a207
KH		 2413}
2414
82bc3b2d
TU		 2415static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2416 const struct drm_plane_state *plane_state)
1690e1eb 2417{
82bc3b2d 2418 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2419 struct i915_ggtt_view view;
2420 int ret;
82bc3b2d 2421
ebcdd39e
MR		 2422 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2423
f64b98cd
TU		 2424 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2425 WARN_ONCE(ret, "Couldn't get view from plane state!");
2426
1690e1eb 2427 i915_gem_object_unpin_fence(obj);
f64b98cd 2428 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2429}
2430
c2c75131
DV		 2431/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2432 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2433unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2434 int *x, int *y,
bc752862
CW		 2435 unsigned int tiling_mode,
2436 unsigned int cpp,
2437 unsigned int pitch)
c2c75131 2438{
bc752862
CW		 2439 if (tiling_mode != I915_TILING_NONE) {
2440 unsigned int tile_rows, tiles;
c2c75131 2441
bc752862
CW		 2442 tile_rows = *y / 8;
2443 *y %= 8;
c2c75131 2444
bc752862
CW		 2445 tiles = *x / (512/cpp);
2446 *x %= 512/cpp;
2447
2448 return tile_rows * pitch * 8 + tiles * 4096;
2449 } else {
4e9a86b6 2450 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2451 unsigned int offset;
2452
2453 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2454 *y = (offset & alignment) / pitch;
2455 *x = ((offset & alignment) - *y * pitch) / cpp;
2456 return offset & ~alignment;
bc752862 2457 }
c2c75131
DV		 2458}
2459
b35d63fa 2460static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2461{
2462 switch (format) {
2463 case DISPPLANE_8BPP:
2464 return DRM_FORMAT_C8;
2465 case DISPPLANE_BGRX555:
2466 return DRM_FORMAT_XRGB1555;
2467 case DISPPLANE_BGRX565:
2468 return DRM_FORMAT_RGB565;
2469 default:
2470 case DISPPLANE_BGRX888:
2471 return DRM_FORMAT_XRGB8888;
2472 case DISPPLANE_RGBX888:
2473 return DRM_FORMAT_XBGR8888;
2474 case DISPPLANE_BGRX101010:
2475 return DRM_FORMAT_XRGB2101010;
2476 case DISPPLANE_RGBX101010:
2477 return DRM_FORMAT_XBGR2101010;
2478 }
2479}
2480
bc8d7dff
DL		 2481static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2482{
2483 switch (format) {
2484 case PLANE_CTL_FORMAT_RGB_565:
2485 return DRM_FORMAT_RGB565;
2486 default:
2487 case PLANE_CTL_FORMAT_XRGB_8888:
2488 if (rgb_order) {
2489 if (alpha)
2490 return DRM_FORMAT_ABGR8888;
2491 else
2492 return DRM_FORMAT_XBGR8888;
2493 } else {
2494 if (alpha)
2495 return DRM_FORMAT_ARGB8888;
2496 else
2497 return DRM_FORMAT_XRGB8888;
2498 }
2499 case PLANE_CTL_FORMAT_XRGB_2101010:
2500 if (rgb_order)
2501 return DRM_FORMAT_XBGR2101010;
2502 else
2503 return DRM_FORMAT_XRGB2101010;
2504 }
2505}
2506
5724dbd1 2507static bool
f6936e29
DV		 2508intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2509 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2510{
2511 struct drm_device *dev = crtc->base.dev;
3badb49f 2512 struct drm_i915_private *dev_priv = to_i915(dev);
46f297fb
JB		 2513 struct drm_i915_gem_object *obj = NULL;
2514 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2515 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2516 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2517 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2518 PAGE_SIZE);
2519
2520 size_aligned -= base_aligned;
46f297fb 2521
ff2652ea
CW		 2522 if (plane_config->size == 0)
2523 return false;
2524
3badb49f
PZ		 2525 /* If the FB is too big, just don't use it since fbdev is not very
2526 * important and we should probably use that space with FBC or other
2527 * features. */
2528 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2529 return false;
2530
f37b5c2b
DV		 2531 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2532 base_aligned,
2533 base_aligned,
2534 size_aligned);
46f297fb 2535 if (!obj)
484b41dd 2536 return false;
46f297fb 2537
49af449b
DL		 2538 obj->tiling_mode = plane_config->tiling;
2539 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2540 obj->stride = fb->pitches[0];
46f297fb 2541
6bf129df
DL		 2542 mode_cmd.pixel_format = fb->pixel_format;
2543 mode_cmd.width = fb->width;
2544 mode_cmd.height = fb->height;
2545 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2546 mode_cmd.modifier[0] = fb->modifier[0];
2547 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2548
2549 mutex_lock(&dev->struct_mutex);
6bf129df 2550 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2551 &mode_cmd, obj)) {
46f297fb
JB		 2552 DRM_DEBUG_KMS("intel fb init failed\n");
2553 goto out_unref_obj;
2554 }
46f297fb 2555 mutex_unlock(&dev->struct_mutex);
484b41dd 2556
f6936e29 2557 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2558 return true;
46f297fb
JB		 2559
2560out_unref_obj:
2561 drm_gem_object_unreference(&obj->base);
2562 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2563 return false;
2564}
2565
afd65eb4
MR		 2566/* Update plane->state->fb to match plane->fb after driver-internal updates */
2567static void
2568update_state_fb(struct drm_plane *plane)
2569{
2570 if (plane->fb == plane->state->fb)
2571 return;
2572
2573 if (plane->state->fb)
2574 drm_framebuffer_unreference(plane->state->fb);
2575 plane->state->fb = plane->fb;
2576 if (plane->state->fb)
2577 drm_framebuffer_reference(plane->state->fb);
2578}
2579
5724dbd1 2580static void
f6936e29
DV		 2581intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2582 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2583{
2584 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2585 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2586 struct drm_crtc *c;
2587 struct intel_crtc *i;
2ff8fde1 2588 struct drm_i915_gem_object *obj;
88595ac9 2589 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2590 struct drm_plane_state *plane_state = primary->state;
88595ac9 2591 struct drm_framebuffer *fb;
484b41dd 2592
2d14030b 2593 if (!plane_config->fb)
484b41dd
JB		 2594 return;
2595
f6936e29 2596 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2597 fb = &plane_config->fb->base;
2598 goto valid_fb;
f55548b5 2599 }
484b41dd 2600
2d14030b 2601 kfree(plane_config->fb);
484b41dd
JB		 2602
2603 /*
2604 * Failed to alloc the obj, check to see if we should share
2605 * an fb with another CRTC instead
2606 */
70e1e0ec 2607 for_each_crtc(dev, c) {
484b41dd
JB		 2608 i = to_intel_crtc(c);
2609
2610 if (c == &intel_crtc->base)
2611 continue;
2612
2ff8fde1
MR		 2613 if (!i->active)
2614 continue;
2615
88595ac9
DV		 2616 fb = c->primary->fb;
2617 if (!fb)
484b41dd
JB		 2618 continue;
2619
88595ac9 2620 obj = intel_fb_obj(fb);
2ff8fde1 2621 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2622 drm_framebuffer_reference(fb);
2623 goto valid_fb;
484b41dd
JB		 2624 }
2625 }
88595ac9
DV		 2626
2627 return;
2628
2629valid_fb:
be5651f2
ML		 2630 plane_state->src_x = plane_state->src_y = 0;
2631 plane_state->src_w = fb->width << 16;
2632 plane_state->src_h = fb->height << 16;
2633
2634 plane_state->crtc_x = plane_state->src_y = 0;
2635 plane_state->crtc_w = fb->width;
2636 plane_state->crtc_h = fb->height;
2637
88595ac9
DV		 2638 obj = intel_fb_obj(fb);
2639 if (obj->tiling_mode != I915_TILING_NONE)
2640 dev_priv->preserve_bios_swizzle = true;
2641
be5651f2
ML		 2642 drm_framebuffer_reference(fb);
2643 primary->fb = primary->state->fb = fb;
36750f28 2644 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2645 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2646 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2647}
2648
29b9bde6
DV		 2649static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2650 struct drm_framebuffer *fb,
2651 int x, int y)
81255565
JB		 2652{
2653 struct drm_device *dev = crtc->dev;
2654 struct drm_i915_private *dev_priv = dev->dev_private;
2655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2656 struct drm_plane *primary = crtc->primary;
2657 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2658 struct drm_i915_gem_object *obj;
81255565 2659 int plane = intel_crtc->plane;
e506a0c6 2660 unsigned long linear_offset;
81255565 2661 u32 dspcntr;
f45651ba 2662 u32 reg = DSPCNTR(plane);
48404c1e 2663 int pixel_size;
f45651ba 2664
b70709a6 2665 if (!visible || !fb) {
fdd508a6
VS		 2666 I915_WRITE(reg, 0);
2667 if (INTEL_INFO(dev)->gen >= 4)
2668 I915_WRITE(DSPSURF(plane), 0);
2669 else
2670 I915_WRITE(DSPADDR(plane), 0);
2671 POSTING_READ(reg);
2672 return;
2673 }
2674
c9ba6fad
VS		 2675 obj = intel_fb_obj(fb);
2676 if (WARN_ON(obj == NULL))
2677 return;
2678
2679 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2680
f45651ba
VS		 2681 dspcntr = DISPPLANE_GAMMA_ENABLE;
2682
fdd508a6 2683 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2684
2685 if (INTEL_INFO(dev)->gen < 4) {
2686 if (intel_crtc->pipe == PIPE_B)
2687 dspcntr |= DISPPLANE_SEL_PIPE_B;
2688
2689 /* pipesrc and dspsize control the size that is scaled from,
2690 * which should always be the user's requested size.
2691 */
2692 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2695 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2696 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2697 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2698 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2699 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2700 I915_WRITE(PRIMPOS(plane), 0);
2701 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2702 }
81255565 2703
57779d06
VS		 2704 switch (fb->pixel_format) {
2705 case DRM_FORMAT_C8:
81255565
JB		 2706 dspcntr |= DISPPLANE_8BPP;
2707 break;
57779d06 2708 case DRM_FORMAT_XRGB1555:
57779d06 2709 dspcntr |= DISPPLANE_BGRX555;
81255565 2710 break;
57779d06
VS		 2711 case DRM_FORMAT_RGB565:
2712 dspcntr |= DISPPLANE_BGRX565;
2713 break;
2714 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2715 dspcntr |= DISPPLANE_BGRX888;
2716 break;
2717 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2718 dspcntr |= DISPPLANE_RGBX888;
2719 break;
2720 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
57779d06 2724 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2725 break;
2726 default:
baba133a 2727 BUG();
81255565 2728 }
57779d06 2729
f45651ba
VS		 2730 if (INTEL_INFO(dev)->gen >= 4 &&
2731 obj->tiling_mode != I915_TILING_NONE)
2732 dspcntr |= DISPPLANE_TILED;
81255565 2733
de1aa629
VS		 2734 if (IS_G4X(dev))
2735 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2736
b9897127 2737 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2738
c2c75131
DV		 2739 if (INTEL_INFO(dev)->gen >= 4) {
2740 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2741 intel_gen4_compute_page_offset(dev_priv,
2742 &x, &y, obj->tiling_mode,
b9897127 2743 pixel_size,
bc752862 2744 fb->pitches[0]);
c2c75131
DV		 2745 linear_offset -= intel_crtc->dspaddr_offset;
2746 } else {
e506a0c6 2747 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2748 }
e506a0c6 2749
8e7d688b 2750 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2751 dspcntr |= DISPPLANE_ROTATE_180;
2752
6e3c9717
ACO		 2753 x += (intel_crtc->config->pipe_src_w - 1);
2754 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2755
2756 /* Finding the last pixel of the last line of the display
2757 data and adding to linear_offset*/
2758 linear_offset +=
6e3c9717
ACO		 2759 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2760 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2761 }
2762
2db3366b
PZ		 2763 intel_crtc->adjusted_x = x;
2764 intel_crtc->adjusted_y = y;
2765
48404c1e
SJ		 2766 I915_WRITE(reg, dspcntr);
2767
01f2c773 2768 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2769 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2770 I915_WRITE(DSPSURF(plane),
2771 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2772 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2773 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2774 } else
f343c5f6 2775 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2776 POSTING_READ(reg);
17638cd6
JB		 2777}
2778
29b9bde6
DV		 2779static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2780 struct drm_framebuffer *fb,
2781 int x, int y)
17638cd6
JB		 2782{
2783 struct drm_device *dev = crtc->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2786 struct drm_plane *primary = crtc->primary;
2787 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2788 struct drm_i915_gem_object *obj;
17638cd6 2789 int plane = intel_crtc->plane;
e506a0c6 2790 unsigned long linear_offset;
17638cd6 2791 u32 dspcntr;
f45651ba 2792 u32 reg = DSPCNTR(plane);
48404c1e 2793 int pixel_size;
f45651ba 2794
b70709a6 2795 if (!visible || !fb) {
fdd508a6
VS		 2796 I915_WRITE(reg, 0);
2797 I915_WRITE(DSPSURF(plane), 0);
2798 POSTING_READ(reg);
2799 return;
2800 }
2801
c9ba6fad
VS		 2802 obj = intel_fb_obj(fb);
2803 if (WARN_ON(obj == NULL))
2804 return;
2805
2806 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2807
f45651ba
VS		 2808 dspcntr = DISPPLANE_GAMMA_ENABLE;
2809
fdd508a6 2810 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2811
2812 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2813 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2814
57779d06
VS		 2815 switch (fb->pixel_format) {
2816 case DRM_FORMAT_C8:
17638cd6
JB		 2817 dspcntr |= DISPPLANE_8BPP;
2818 break;
57779d06
VS		 2819 case DRM_FORMAT_RGB565:
2820 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2821 break;
57779d06 2822 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2823 dspcntr |= DISPPLANE_BGRX888;
2824 break;
2825 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2826 dspcntr |= DISPPLANE_RGBX888;
2827 break;
2828 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
57779d06 2832 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2833 break;
2834 default:
baba133a 2835 BUG();
17638cd6
JB		 2836 }
2837
2838 if (obj->tiling_mode != I915_TILING_NONE)
2839 dspcntr |= DISPPLANE_TILED;
17638cd6 2840
f45651ba 2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2842 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2843
b9897127 2844 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2845 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2846 intel_gen4_compute_page_offset(dev_priv,
2847 &x, &y, obj->tiling_mode,
b9897127 2848 pixel_size,
bc752862 2849 fb->pitches[0]);
c2c75131 2850 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
6e3c9717
ACO		 2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2863 }
2864 }
2865
2db3366b
PZ		 2866 intel_crtc->adjusted_x = x;
2867 intel_crtc->adjusted_y = y;
2868
48404c1e 2869 I915_WRITE(reg, dspcntr);
17638cd6 2870
01f2c773 2871 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2872 I915_WRITE(DSPSURF(plane),
2873 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2874 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2875 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2876 } else {
2877 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2878 I915_WRITE(DSPLINOFF(plane), linear_offset);
2879 }
17638cd6 2880 POSTING_READ(reg);
17638cd6
JB		 2881}
2882
b321803d
DL		 2883u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2884 uint32_t pixel_format)
2885{
2886 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2887
2888 /*
2889 * The stride is either expressed as a multiple of 64 bytes
2890 * chunks for linear buffers or in number of tiles for tiled
2891 * buffers.
2892 */
2893 switch (fb_modifier) {
2894 case DRM_FORMAT_MOD_NONE:
2895 return 64;
2896 case I915_FORMAT_MOD_X_TILED:
2897 if (INTEL_INFO(dev)->gen == 2)
2898 return 128;
2899 return 512;
2900 case I915_FORMAT_MOD_Y_TILED:
2901 /* No need to check for old gens and Y tiling since this is
2902 * about the display engine and those will be blocked before
2903 * we get here.
2904 */
2905 return 128;
2906 case I915_FORMAT_MOD_Yf_TILED:
2907 if (bits_per_pixel == 8)
2908 return 64;
2909 else
2910 return 128;
2911 default:
2912 MISSING_CASE(fb_modifier);
2913 return 64;
2914 }
2915}
2916
44eb0cb9
MK		 2917u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2918 struct drm_i915_gem_object *obj,
2919 unsigned int plane)
121920fa 2920{
9abc4648 2921 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
dedf278c 2922 struct i915_vma *vma;
44eb0cb9 2923 u64 offset;
121920fa
TU		 2924
2925 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2926 view = &i915_ggtt_view_rotated;
121920fa 2927
dedf278c
TU		 2928 vma = i915_gem_obj_to_ggtt_view(obj, view);
2929 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2930 view->type))
2931 return -1;
2932
44eb0cb9 2933 offset = vma->node.start;
dedf278c
TU		 2934
2935 if (plane == 1) {
2936 offset += vma->ggtt_view.rotation_info.uv_start_page *
2937 PAGE_SIZE;
2938 }
2939
44eb0cb9
MK		 2940 WARN_ON(upper_32_bits(offset));
2941
2942 return lower_32_bits(offset);
121920fa
TU		 2943}
2944
e435d6e5
ML		 2945static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2946{
2947 struct drm_device *dev = intel_crtc->base.dev;
2948 struct drm_i915_private *dev_priv = dev->dev_private;
2949
2950 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2951 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2952 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2953}
2954
a1b2278e
CK		 2955/*
2956 * This function detaches (aka. unbinds) unused scalers in hardware
2957 */
0583236e 2958static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2959{
a1b2278e
CK		 2960 struct intel_crtc_scaler_state *scaler_state;
2961 int i;
2962
a1b2278e
CK		 2963 scaler_state = &intel_crtc->config->scaler_state;
2964
2965 /* loop through and disable scalers that aren't in use */
2966 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2967 if (!scaler_state->scalers[i].in_use)
2968 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2969 }
2970}
2971
6156a456 2972u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2973{
6156a456 2974 switch (pixel_format) {
d161cf7a 2975 case DRM_FORMAT_C8:
c34ce3d1 2976 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2977 case DRM_FORMAT_RGB565:
c34ce3d1 2978 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2979 case DRM_FORMAT_XBGR8888:
c34ce3d1 2980 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2981 case DRM_FORMAT_XRGB8888:
c34ce3d1 2982 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2983 /*
2984 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2985 * to be already pre-multiplied. We need to add a knob (or a different
2986 * DRM_FORMAT) for user-space to configure that.
2987 */
f75fb42a 2988 case DRM_FORMAT_ABGR8888:
c34ce3d1 2989 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2990 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2991 case DRM_FORMAT_ARGB8888:
c34ce3d1 2992 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2993 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2994 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2995 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2996 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2997 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2998 case DRM_FORMAT_YUYV:
c34ce3d1 2999 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 3000 case DRM_FORMAT_YVYU:
c34ce3d1 3001 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 3002 case DRM_FORMAT_UYVY:
c34ce3d1 3003 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 3004 case DRM_FORMAT_VYUY:
c34ce3d1 3005 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 3006 default:
4249eeef 3007 MISSING_CASE(pixel_format);
70d21f0e 3008 }
8cfcba41 3009
c34ce3d1 3010 return 0;
6156a456 3011}
70d21f0e 3012
6156a456
CK		 3013u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3014{
6156a456 3015 switch (fb_modifier) {
30af77c4 3016 case DRM_FORMAT_MOD_NONE:
70d21f0e 3017 break;
30af77c4 3018 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3019 return PLANE_CTL_TILED_X;
b321803d 3020 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3021 return PLANE_CTL_TILED_Y;
b321803d 3022 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3023 return PLANE_CTL_TILED_YF;
70d21f0e 3024 default:
6156a456 3025 MISSING_CASE(fb_modifier);
70d21f0e 3026 }
8cfcba41 3027
c34ce3d1 3028 return 0;
6156a456 3029}
70d21f0e 3030
6156a456
CK		 3031u32 skl_plane_ctl_rotation(unsigned int rotation)
3032{
3b7a5119 3033 switch (rotation) {
6156a456
CK		 3034 case BIT(DRM_ROTATE_0):
3035 break;
1e8df167
SJ		 3036 /*
3037 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3038 * while i915 HW rotation is clockwise, thats why this swapping.
3039 */
3b7a5119 3040 case BIT(DRM_ROTATE_90):
1e8df167 3041 return PLANE_CTL_ROTATE_270;
3b7a5119 3042 case BIT(DRM_ROTATE_180):
c34ce3d1 3043 return PLANE_CTL_ROTATE_180;
3b7a5119 3044 case BIT(DRM_ROTATE_270):
1e8df167 3045 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3046 default:
3047 MISSING_CASE(rotation);
3048 }
3049
c34ce3d1 3050 return 0;
6156a456
CK		 3051}
3052
3053static void skylake_update_primary_plane(struct drm_crtc *crtc,
3054 struct drm_framebuffer *fb,
3055 int x, int y)
3056{
3057 struct drm_device *dev = crtc->dev;
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3060 struct drm_plane *plane = crtc->primary;
3061 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3062 struct drm_i915_gem_object *obj;
3063 int pipe = intel_crtc->pipe;
3064 u32 plane_ctl, stride_div, stride;
3065 u32 tile_height, plane_offset, plane_size;
3066 unsigned int rotation;
3067 int x_offset, y_offset;
44eb0cb9 3068 u32 surf_addr;
6156a456
CK		 3069 struct intel_crtc_state *crtc_state = intel_crtc->config;
3070 struct intel_plane_state *plane_state;
3071 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3072 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3073 int scaler_id = -1;
3074
6156a456
CK		 3075 plane_state = to_intel_plane_state(plane->state);
3076
b70709a6 3077 if (!visible || !fb) {
6156a456
CK		 3078 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3079 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3080 POSTING_READ(PLANE_CTL(pipe, 0));
3081 return;
3b7a5119 3082 }
70d21f0e 3083
6156a456
CK		 3084 plane_ctl = PLANE_CTL_ENABLE |
3085 PLANE_CTL_PIPE_GAMMA_ENABLE |
3086 PLANE_CTL_PIPE_CSC_ENABLE;
3087
3088 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3089 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3090 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3091
3092 rotation = plane->state->rotation;
3093 plane_ctl |= skl_plane_ctl_rotation(rotation);
3094
b321803d
DL		 3095 obj = intel_fb_obj(fb);
3096 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3097 fb->pixel_format);
dedf278c 3098 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3b7a5119 3099
a42e5a23
PZ		 3100 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3101
3102 scaler_id = plane_state->scaler_id;
3103 src_x = plane_state->src.x1 >> 16;
3104 src_y = plane_state->src.y1 >> 16;
3105 src_w = drm_rect_width(&plane_state->src) >> 16;
3106 src_h = drm_rect_height(&plane_state->src) >> 16;
3107 dst_x = plane_state->dst.x1;
3108 dst_y = plane_state->dst.y1;
3109 dst_w = drm_rect_width(&plane_state->dst);
3110 dst_h = drm_rect_height(&plane_state->dst);
3111
3112 WARN_ON(x != src_x || y != src_y);
6156a456 3113
3b7a5119
SJ		 3114 if (intel_rotation_90_or_270(rotation)) {
3115 /* stride = Surface height in tiles */
2614f17d 3116 tile_height = intel_tile_height(dev, fb->pixel_format,
fe47ea0c 3117 fb->modifier[0], 0);
3b7a5119 3118 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3119 x_offset = stride * tile_height - y - src_h;
3b7a5119 3120 y_offset = x;
6156a456 3121 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3122 } else {
3123 stride = fb->pitches[0] / stride_div;
3124 x_offset = x;
3125 y_offset = y;
6156a456 3126 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3127 }
3128 plane_offset = y_offset << 16 | x_offset;
b321803d 3129
2db3366b
PZ		 3130 intel_crtc->adjusted_x = x_offset;
3131 intel_crtc->adjusted_y = y_offset;
3132
70d21f0e 3133 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3134 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3135 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3136 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3137
3138 if (scaler_id >= 0) {
3139 uint32_t ps_ctrl = 0;
3140
3141 WARN_ON(!dst_w || !dst_h);
3142 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3143 crtc_state->scaler_state.scalers[scaler_id].mode;
3144 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3145 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3146 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3147 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3148 I915_WRITE(PLANE_POS(pipe, 0), 0);
3149 } else {
3150 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3151 }
3152
121920fa 3153 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3154
3155 POSTING_READ(PLANE_SURF(pipe, 0));
3156}
3157
17638cd6
JB		 3158/* Assume fb object is pinned & idle & fenced and just update base pointers */
3159static int
3160intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3161 int x, int y, enum mode_set_atomic state)
3162{
3163 struct drm_device *dev = crtc->dev;
3164 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3165
ff2a3117 3166 if (dev_priv->fbc.disable_fbc)
7733b49b 3167 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3168
29b9bde6
DV		 3169 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3170
3171 return 0;
81255565
JB		 3172}
3173
7514747d 3174static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3175{
96a02917
VS		 3176 struct drm_crtc *crtc;
3177
70e1e0ec 3178 for_each_crtc(dev, crtc) {
96a02917
VS		 3179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3180 enum plane plane = intel_crtc->plane;
3181
3182 intel_prepare_page_flip(dev, plane);
3183 intel_finish_page_flip_plane(dev, plane);
3184 }
7514747d
VS		 3185}
3186
3187static void intel_update_primary_planes(struct drm_device *dev)
3188{
7514747d 3189 struct drm_crtc *crtc;
96a02917 3190
70e1e0ec 3191 for_each_crtc(dev, crtc) {
11c22da6
ML		 3192 struct intel_plane *plane = to_intel_plane(crtc->primary);
3193 struct intel_plane_state *plane_state;
96a02917 3194
11c22da6 3195 drm_modeset_lock_crtc(crtc, &plane->base);
11c22da6
ML		 3196 plane_state = to_intel_plane_state(plane->base.state);
3197
f029ee82 3198 if (crtc->state->active && plane_state->base.fb)
11c22da6
ML		 3199 plane->commit_plane(&plane->base, plane_state);
3200
3201 drm_modeset_unlock_crtc(crtc);
96a02917
VS		 3202 }
3203}
3204
7514747d
VS		 3205void intel_prepare_reset(struct drm_device *dev)
3206{
3207 /* no reset support for gen2 */
3208 if (IS_GEN2(dev))
3209 return;
3210
3211 /* reset doesn't touch the display */
3212 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3213 return;
3214
3215 drm_modeset_lock_all(dev);
f98ce92f
VS		 3216 /*
3217 * Disabling the crtcs gracefully seems nicer. Also the
3218 * g33 docs say we should at least disable all the planes.
3219 */
6b72d486 3220 intel_display_suspend(dev);
7514747d
VS		 3221}
3222
3223void intel_finish_reset(struct drm_device *dev)
3224{
3225 struct drm_i915_private *dev_priv = to_i915(dev);
3226
3227 /*
3228 * Flips in the rings will be nuked by the reset,
3229 * so complete all pending flips so that user space
3230 * will get its events and not get stuck.
3231 */
3232 intel_complete_page_flips(dev);
3233
3234 /* no reset support for gen2 */
3235 if (IS_GEN2(dev))
3236 return;
3237
3238 /* reset doesn't touch the display */
3239 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3240 /*
3241 * Flips in the rings have been nuked by the reset,
3242 * so update the base address of all primary
3243 * planes to the the last fb to make sure we're
3244 * showing the correct fb after a reset.
11c22da6
ML		 3245 *
3246 * FIXME: Atomic will make this obsolete since we won't schedule
3247 * CS-based flips (which might get lost in gpu resets) any more.
7514747d
VS		 3248 */
3249 intel_update_primary_planes(dev);
3250 return;
3251 }
3252
3253 /*
3254 * The display has been reset as well,
3255 * so need a full re-initialization.
3256 */
3257 intel_runtime_pm_disable_interrupts(dev_priv);
3258 intel_runtime_pm_enable_interrupts(dev_priv);
3259
3260 intel_modeset_init_hw(dev);
3261
3262 spin_lock_irq(&dev_priv->irq_lock);
3263 if (dev_priv->display.hpd_irq_setup)
3264 dev_priv->display.hpd_irq_setup(dev);
3265 spin_unlock_irq(&dev_priv->irq_lock);
3266
043e9bda 3267 intel_display_resume(dev);
7514747d
VS		 3268
3269 intel_hpd_init(dev_priv);
3270
3271 drm_modeset_unlock_all(dev);
3272}
3273
7d5e3799
CW		 3274static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3275{
3276 struct drm_device *dev = crtc->dev;
3277 struct drm_i915_private *dev_priv = dev->dev_private;
3278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3279 bool pending;
3280
3281 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3282 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3283 return false;
3284
5e2d7afc 3285 spin_lock_irq(&dev->event_lock);
7d5e3799 3286 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3287 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3288
3289 return pending;
3290}
3291
bfd16b2a
ML		 3292static void intel_update_pipe_config(struct intel_crtc *crtc,
3293 struct intel_crtc_state *old_crtc_state)
e30e8f75
GP		 3294{
3295 struct drm_device *dev = crtc->base.dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
bfd16b2a
ML		 3297 struct intel_crtc_state *pipe_config =
3298 to_intel_crtc_state(crtc->base.state);
e30e8f75 3299
bfd16b2a
ML		 3300 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3301 crtc->base.mode = crtc->base.state->mode;
3302
3303 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3304 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3305 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
e30e8f75 3306
44522d85
ML		 3307 if (HAS_DDI(dev))
3308 intel_set_pipe_csc(&crtc->base);
3309
e30e8f75
GP		 3310 /*
3311 * Update pipe size and adjust fitter if needed: the reason for this is
3312 * that in compute_mode_changes we check the native mode (not the pfit
3313 * mode) to see if we can flip rather than do a full mode set. In the
3314 * fastboot case, we'll flip, but if we don't update the pipesrc and
3315 * pfit state, we'll end up with a big fb scanned out into the wrong
3316 * sized surface.
e30e8f75
GP		 3317 */
3318
e30e8f75 3319 I915_WRITE(PIPESRC(crtc->pipe),
bfd16b2a
ML		 3320 ((pipe_config->pipe_src_w - 1) << 16) |
3321 (pipe_config->pipe_src_h - 1));
3322
3323 /* on skylake this is done by detaching scalers */
3324 if (INTEL_INFO(dev)->gen >= 9) {
3325 skl_detach_scalers(crtc);
3326
3327 if (pipe_config->pch_pfit.enabled)
3328 skylake_pfit_enable(crtc);
3329 } else if (HAS_PCH_SPLIT(dev)) {
3330 if (pipe_config->pch_pfit.enabled)
3331 ironlake_pfit_enable(crtc);
3332 else if (old_crtc_state->pch_pfit.enabled)
3333 ironlake_pfit_disable(crtc, true);
e30e8f75 3334 }
e30e8f75
GP		 3335}
3336
5e84e1a4
ZW		 3337static void intel_fdi_normal_train(struct drm_crtc *crtc)
3338{
3339 struct drm_device *dev = crtc->dev;
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3342 int pipe = intel_crtc->pipe;
3343 u32 reg, temp;
3344
3345 /* enable normal train */
3346 reg = FDI_TX_CTL(pipe);
3347 temp = I915_READ(reg);
61e499bf 3348 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3349 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3350 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3351 } else {
3352 temp &= ~FDI_LINK_TRAIN_NONE;
3353 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3354 }
5e84e1a4
ZW		 3355 I915_WRITE(reg, temp);
3356
3357 reg = FDI_RX_CTL(pipe);
3358 temp = I915_READ(reg);
3359 if (HAS_PCH_CPT(dev)) {
3360 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3361 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3362 } else {
3363 temp &= ~FDI_LINK_TRAIN_NONE;
3364 temp |= FDI_LINK_TRAIN_NONE;
3365 }
3366 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3367
3368 /* wait one idle pattern time */
3369 POSTING_READ(reg);
3370 udelay(1000);
357555c0
JB		 3371
3372 /* IVB wants error correction enabled */
3373 if (IS_IVYBRIDGE(dev))
3374 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3375 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3376}
3377
8db9d77b
ZW		 3378/* The FDI link training functions for ILK/Ibexpeak. */
3379static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3384 int pipe = intel_crtc->pipe;
5eddb70b 3385 u32 reg, temp, tries;
8db9d77b 3386
1c8562f6 3387 /* FDI needs bits from pipe first */
0fc932b8 3388 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3389
e1a44743
AJ		 3390 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3391 for train result */
5eddb70b
CW		 3392 reg = FDI_RX_IMR(pipe);
3393 temp = I915_READ(reg);
e1a44743
AJ		 3394 temp &= ~FDI_RX_SYMBOL_LOCK;
3395 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3396 I915_WRITE(reg, temp);
3397 I915_READ(reg);
e1a44743
AJ		 3398 udelay(150);
3399
8db9d77b 3400 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3401 reg = FDI_TX_CTL(pipe);
3402 temp = I915_READ(reg);
627eb5a3 3403 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3404 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3405 temp &= ~FDI_LINK_TRAIN_NONE;
3406 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3407 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3408
5eddb70b
CW		 3409 reg = FDI_RX_CTL(pipe);
3410 temp = I915_READ(reg);
8db9d77b
ZW		 3411 temp &= ~FDI_LINK_TRAIN_NONE;
3412 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3413 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3414
3415 POSTING_READ(reg);
8db9d77b
ZW		 3416 udelay(150);
3417
5b2adf89 3418 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3419 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3420 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3421 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3422
5eddb70b 3423 reg = FDI_RX_IIR(pipe);
e1a44743 3424 for (tries = 0; tries < 5; tries++) {
5eddb70b 3425 temp = I915_READ(reg);
8db9d77b
ZW		 3426 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3427
3428 if ((temp & FDI_RX_BIT_LOCK)) {
3429 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3430 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3431 break;
3432 }
8db9d77b 3433 }
e1a44743 3434 if (tries == 5)
5eddb70b 3435 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3436
3437 /* Train 2 */
5eddb70b
CW		 3438 reg = FDI_TX_CTL(pipe);
3439 temp = I915_READ(reg);
8db9d77b
ZW		 3440 temp &= ~FDI_LINK_TRAIN_NONE;
3441 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3442 I915_WRITE(reg, temp);
8db9d77b 3443
5eddb70b
CW		 3444 reg = FDI_RX_CTL(pipe);
3445 temp = I915_READ(reg);
8db9d77b
ZW		 3446 temp &= ~FDI_LINK_TRAIN_NONE;
3447 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3448 I915_WRITE(reg, temp);
8db9d77b 3449
5eddb70b
CW		 3450 POSTING_READ(reg);
3451 udelay(150);
8db9d77b 3452
5eddb70b 3453 reg = FDI_RX_IIR(pipe);
e1a44743 3454 for (tries = 0; tries < 5; tries++) {
5eddb70b 3455 temp = I915_READ(reg);
8db9d77b
ZW		 3456 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3457
3458 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3459 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3460 DRM_DEBUG_KMS("FDI train 2 done.\n");
3461 break;
3462 }
8db9d77b 3463 }
e1a44743 3464 if (tries == 5)
5eddb70b 3465 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3466
3467 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3468
8db9d77b
ZW		 3469}
3470
0206e353 3471static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3472 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3473 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3474 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3475 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3476};
3477
3478/* The FDI link training functions for SNB/Cougarpoint. */
3479static void gen6_fdi_link_train(struct drm_crtc *crtc)
3480{
3481 struct drm_device *dev = crtc->dev;
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3484 int pipe = intel_crtc->pipe;
fa37d39e 3485 u32 reg, temp, i, retry;
8db9d77b 3486
e1a44743
AJ		 3487 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3488 for train result */
5eddb70b
CW		 3489 reg = FDI_RX_IMR(pipe);
3490 temp = I915_READ(reg);
e1a44743
AJ		 3491 temp &= ~FDI_RX_SYMBOL_LOCK;
3492 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3493 I915_WRITE(reg, temp);
3494
3495 POSTING_READ(reg);
e1a44743
AJ		 3496 udelay(150);
3497
8db9d77b 3498 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3499 reg = FDI_TX_CTL(pipe);
3500 temp = I915_READ(reg);
627eb5a3 3501 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3502 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3503 temp &= ~FDI_LINK_TRAIN_NONE;
3504 temp |= FDI_LINK_TRAIN_PATTERN_1;
3505 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3506 /* SNB-B */
3507 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3508 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3509
d74cf324
DV		 3510 I915_WRITE(FDI_RX_MISC(pipe),
3511 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3512
5eddb70b
CW		 3513 reg = FDI_RX_CTL(pipe);
3514 temp = I915_READ(reg);
8db9d77b
ZW		 3515 if (HAS_PCH_CPT(dev)) {
3516 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3518 } else {
3519 temp &= ~FDI_LINK_TRAIN_NONE;
3520 temp |= FDI_LINK_TRAIN_PATTERN_1;
3521 }
5eddb70b
CW		 3522 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3523
3524 POSTING_READ(reg);
8db9d77b
ZW		 3525 udelay(150);
3526
0206e353 3527 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3528 reg = FDI_TX_CTL(pipe);
3529 temp = I915_READ(reg);
8db9d77b
ZW		 3530 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3531 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3532 I915_WRITE(reg, temp);
3533
3534 POSTING_READ(reg);
8db9d77b
ZW		 3535 udelay(500);
3536
fa37d39e
SP		 3537 for (retry = 0; retry < 5; retry++) {
3538 reg = FDI_RX_IIR(pipe);
3539 temp = I915_READ(reg);
3540 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3541 if (temp & FDI_RX_BIT_LOCK) {
3542 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3543 DRM_DEBUG_KMS("FDI train 1 done.\n");
3544 break;
3545 }
3546 udelay(50);
8db9d77b 3547 }
fa37d39e
SP		 3548 if (retry < 5)
3549 break;
8db9d77b
ZW		 3550 }
3551 if (i == 4)
5eddb70b 3552 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3553
3554 /* Train 2 */
5eddb70b
CW		 3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
8db9d77b
ZW		 3557 temp &= ~FDI_LINK_TRAIN_NONE;
3558 temp |= FDI_LINK_TRAIN_PATTERN_2;
3559 if (IS_GEN6(dev)) {
3560 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3561 /* SNB-B */
3562 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3563 }
5eddb70b 3564 I915_WRITE(reg, temp);
8db9d77b 3565
5eddb70b
CW		 3566 reg = FDI_RX_CTL(pipe);
3567 temp = I915_READ(reg);
8db9d77b
ZW		 3568 if (HAS_PCH_CPT(dev)) {
3569 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3570 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3571 } else {
3572 temp &= ~FDI_LINK_TRAIN_NONE;
3573 temp |= FDI_LINK_TRAIN_PATTERN_2;
3574 }
5eddb70b
CW		 3575 I915_WRITE(reg, temp);
3576
3577 POSTING_READ(reg);
8db9d77b
ZW		 3578 udelay(150);
3579
0206e353 3580 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3581 reg = FDI_TX_CTL(pipe);
3582 temp = I915_READ(reg);
8db9d77b
ZW		 3583 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3584 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3585 I915_WRITE(reg, temp);
3586
3587 POSTING_READ(reg);
8db9d77b
ZW		 3588 udelay(500);
3589
fa37d39e
SP		 3590 for (retry = 0; retry < 5; retry++) {
3591 reg = FDI_RX_IIR(pipe);
3592 temp = I915_READ(reg);
3593 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3594 if (temp & FDI_RX_SYMBOL_LOCK) {
3595 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3596 DRM_DEBUG_KMS("FDI train 2 done.\n");
3597 break;
3598 }
3599 udelay(50);
8db9d77b 3600 }
fa37d39e
SP		 3601 if (retry < 5)
3602 break;
8db9d77b
ZW		 3603 }
3604 if (i == 4)
5eddb70b 3605 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3606
3607 DRM_DEBUG_KMS("FDI train done.\n");
3608}
3609
357555c0
JB		 3610/* Manual link training for Ivy Bridge A0 parts */
3611static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3612{
3613 struct drm_device *dev = crtc->dev;
3614 struct drm_i915_private *dev_priv = dev->dev_private;
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3616 int pipe = intel_crtc->pipe;
139ccd3f 3617 u32 reg, temp, i, j;
357555c0
JB		 3618
3619 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3620 for train result */
3621 reg = FDI_RX_IMR(pipe);
3622 temp = I915_READ(reg);
3623 temp &= ~FDI_RX_SYMBOL_LOCK;
3624 temp &= ~FDI_RX_BIT_LOCK;
3625 I915_WRITE(reg, temp);
3626
3627 POSTING_READ(reg);
3628 udelay(150);
3629
01a415fd
DV		 3630 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3631 I915_READ(FDI_RX_IIR(pipe)));
3632
139ccd3f
JB		 3633 /* Try each vswing and preemphasis setting twice before moving on */
3634 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3635 /* disable first in case we need to retry */
3636 reg = FDI_TX_CTL(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3639 temp &= ~FDI_TX_ENABLE;
3640 I915_WRITE(reg, temp);
357555c0 3641
139ccd3f
JB		 3642 reg = FDI_RX_CTL(pipe);
3643 temp = I915_READ(reg);
3644 temp &= ~FDI_LINK_TRAIN_AUTO;
3645 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3646 temp &= ~FDI_RX_ENABLE;
3647 I915_WRITE(reg, temp);
357555c0 3648
139ccd3f 3649 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3650 reg = FDI_TX_CTL(pipe);
3651 temp = I915_READ(reg);
139ccd3f 3652 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3653 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3654 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3656 temp |= snb_b_fdi_train_param[j/2];
3657 temp |= FDI_COMPOSITE_SYNC;
3658 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3659
139ccd3f
JB		 3660 I915_WRITE(FDI_RX_MISC(pipe),
3661 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3662
139ccd3f 3663 reg = FDI_RX_CTL(pipe);
357555c0 3664 temp = I915_READ(reg);
139ccd3f
JB		 3665 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3666 temp |= FDI_COMPOSITE_SYNC;
3667 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3668
139ccd3f
JB		 3669 POSTING_READ(reg);
3670 udelay(1); /* should be 0.5us */
357555c0 3671
139ccd3f
JB		 3672 for (i = 0; i < 4; i++) {
3673 reg = FDI_RX_IIR(pipe);
3674 temp = I915_READ(reg);
3675 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3676
139ccd3f
JB		 3677 if (temp & FDI_RX_BIT_LOCK ||
3678 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3679 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3680 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3681 i);
3682 break;
3683 }
3684 udelay(1); /* should be 0.5us */
3685 }
3686 if (i == 4) {
3687 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3688 continue;
3689 }
357555c0 3690
139ccd3f 3691 /* Train 2 */
357555c0
JB		 3692 reg = FDI_TX_CTL(pipe);
3693 temp = I915_READ(reg);
139ccd3f
JB		 3694 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3695 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3696 I915_WRITE(reg, temp);
3697
3698 reg = FDI_RX_CTL(pipe);
3699 temp = I915_READ(reg);
3700 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3701 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3702 I915_WRITE(reg, temp);
3703
3704 POSTING_READ(reg);
139ccd3f 3705 udelay(2); /* should be 1.5us */
357555c0 3706
139ccd3f
JB		 3707 for (i = 0; i < 4; i++) {
3708 reg = FDI_RX_IIR(pipe);
3709 temp = I915_READ(reg);
3710 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3711
139ccd3f
JB		 3712 if (temp & FDI_RX_SYMBOL_LOCK ||
3713 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3714 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3715 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3716 i);
3717 goto train_done;
3718 }
3719 udelay(2); /* should be 1.5us */
357555c0 3720 }
139ccd3f
JB		 3721 if (i == 4)
3722 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3723 }
357555c0 3724
139ccd3f 3725train_done:
357555c0
JB		 3726 DRM_DEBUG_KMS("FDI train done.\n");
3727}
3728
88cefb6c 3729static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3730{
88cefb6c 3731 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3732 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3733 int pipe = intel_crtc->pipe;
5eddb70b 3734 u32 reg, temp;
79e53945 3735
c64e311e 3736
c98e9dcf 3737 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3738 reg = FDI_RX_CTL(pipe);
3739 temp = I915_READ(reg);
627eb5a3 3740 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3741 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3742 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3743 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3744
3745 POSTING_READ(reg);
c98e9dcf
JB		 3746 udelay(200);
3747
3748 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3749 temp = I915_READ(reg);
3750 I915_WRITE(reg, temp | FDI_PCDCLK);
3751
3752 POSTING_READ(reg);
c98e9dcf
JB		 3753 udelay(200);
3754
20749730
PZ		 3755 /* Enable CPU FDI TX PLL, always on for Ironlake */
3756 reg = FDI_TX_CTL(pipe);
3757 temp = I915_READ(reg);
3758 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3759 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3760
20749730
PZ		 3761 POSTING_READ(reg);
3762 udelay(100);
6be4a607 3763 }
0e23b99d
JB		 3764}
3765
88cefb6c
DV		 3766static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3767{
3768 struct drm_device *dev = intel_crtc->base.dev;
3769 struct drm_i915_private *dev_priv = dev->dev_private;
3770 int pipe = intel_crtc->pipe;
3771 u32 reg, temp;
3772
3773 /* Switch from PCDclk to Rawclk */
3774 reg = FDI_RX_CTL(pipe);
3775 temp = I915_READ(reg);
3776 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3777
3778 /* Disable CPU FDI TX PLL */
3779 reg = FDI_TX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3782
3783 POSTING_READ(reg);
3784 udelay(100);
3785
3786 reg = FDI_RX_CTL(pipe);
3787 temp = I915_READ(reg);
3788 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3789
3790 /* Wait for the clocks to turn off. */
3791 POSTING_READ(reg);
3792 udelay(100);
3793}
3794
0fc932b8
JB		 3795static void ironlake_fdi_disable(struct drm_crtc *crtc)
3796{
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3800 int pipe = intel_crtc->pipe;
3801 u32 reg, temp;
3802
3803 /* disable CPU FDI tx and PCH FDI rx */
3804 reg = FDI_TX_CTL(pipe);
3805 temp = I915_READ(reg);
3806 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3807 POSTING_READ(reg);
3808
3809 reg = FDI_RX_CTL(pipe);
3810 temp = I915_READ(reg);
3811 temp &= ~(0x7 << 16);
dfd07d72 3812 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3813 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3814
3815 POSTING_READ(reg);
3816 udelay(100);
3817
3818 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3819 if (HAS_PCH_IBX(dev))
6f06ce18 3820 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3821
3822 /* still set train pattern 1 */
3823 reg = FDI_TX_CTL(pipe);
3824 temp = I915_READ(reg);
3825 temp &= ~FDI_LINK_TRAIN_NONE;
3826 temp |= FDI_LINK_TRAIN_PATTERN_1;
3827 I915_WRITE(reg, temp);
3828
3829 reg = FDI_RX_CTL(pipe);
3830 temp = I915_READ(reg);
3831 if (HAS_PCH_CPT(dev)) {
3832 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3833 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3834 } else {
3835 temp &= ~FDI_LINK_TRAIN_NONE;
3836 temp |= FDI_LINK_TRAIN_PATTERN_1;
3837 }
3838 /* BPC in FDI rx is consistent with that in PIPECONF */
3839 temp &= ~(0x07 << 16);
dfd07d72 3840 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3841 I915_WRITE(reg, temp);
3842
3843 POSTING_READ(reg);
3844 udelay(100);
3845}
3846
5dce5b93
CW		 3847bool intel_has_pending_fb_unpin(struct drm_device *dev)
3848{
3849 struct intel_crtc *crtc;
3850
3851 /* Note that we don't need to be called with mode_config.lock here
3852 * as our list of CRTC objects is static for the lifetime of the
3853 * device and so cannot disappear as we iterate. Similarly, we can
3854 * happily treat the predicates as racy, atomic checks as userspace
3855 * cannot claim and pin a new fb without at least acquring the
3856 * struct_mutex and so serialising with us.
3857 */
d3fcc808 3858 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3859 if (atomic_read(&crtc->unpin_work_count) == 0)
3860 continue;
3861
3862 if (crtc->unpin_work)
3863 intel_wait_for_vblank(dev, crtc->pipe);
3864
3865 return true;
3866 }
3867
3868 return false;
3869}
3870
d6bbafa1
CW		 3871static void page_flip_completed(struct intel_crtc *intel_crtc)
3872{
3873 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3874 struct intel_unpin_work *work = intel_crtc->unpin_work;
3875
3876 /* ensure that the unpin work is consistent wrt ->pending. */
3877 smp_rmb();
3878 intel_crtc->unpin_work = NULL;
3879
3880 if (work->event)
3881 drm_send_vblank_event(intel_crtc->base.dev,
3882 intel_crtc->pipe,
3883 work->event);
3884
3885 drm_crtc_vblank_put(&intel_crtc->base);
3886
3887 wake_up_all(&dev_priv->pending_flip_queue);
3888 queue_work(dev_priv->wq, &work->work);
3889
3890 trace_i915_flip_complete(intel_crtc->plane,
3891 work->pending_flip_obj);
3892}
3893
5008e874 3894static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3895{
0f91128d 3896 struct drm_device *dev = crtc->dev;
5bb61643 3897 struct drm_i915_private *dev_priv = dev->dev_private;
5008e874 3898 long ret;
e6c3a2a6 3899
2c10d571 3900 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
5008e874
ML		 3901
3902 ret = wait_event_interruptible_timeout(
3903 dev_priv->pending_flip_queue,
3904 !intel_crtc_has_pending_flip(crtc),
3905 60*HZ);
3906
3907 if (ret < 0)
3908 return ret;
3909
3910 if (ret == 0) {
9c787942 3911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3912
5e2d7afc 3913 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3914 if (intel_crtc->unpin_work) {
3915 WARN_ONCE(1, "Removing stuck page flip\n");
3916 page_flip_completed(intel_crtc);
3917 }
5e2d7afc 3918 spin_unlock_irq(&dev->event_lock);
9c787942 3919 }
5bb61643 3920
5008e874 3921 return 0;
e6c3a2a6
CW		 3922}
3923
e615efe4
ED		 3924/* Program iCLKIP clock to the desired frequency */
3925static void lpt_program_iclkip(struct drm_crtc *crtc)
3926{
3927 struct drm_device *dev = crtc->dev;
3928 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3929 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3930 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3931 u32 temp;
3932
a580516d 3933 mutex_lock(&dev_priv->sb_lock);
09153000 3934
e615efe4
ED		 3935 /* It is necessary to ungate the pixclk gate prior to programming
3936 * the divisors, and gate it back when it is done.
3937 */
3938 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3939
3940 /* Disable SSCCTL */
3941 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3942 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3943 SBI_SSCCTL_DISABLE,
3944 SBI_ICLK);
e615efe4
ED		 3945
3946 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3947 if (clock == 20000) {
e615efe4
ED		 3948 auxdiv = 1;
3949 divsel = 0x41;
3950 phaseinc = 0x20;
3951 } else {
3952 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3953 * but the adjusted_mode->crtc_clock in in KHz. To get the
3954 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3955 * convert the virtual clock precision to KHz here for higher
3956 * precision.
3957 */
3958 u32 iclk_virtual_root_freq = 172800 * 1000;
3959 u32 iclk_pi_range = 64;
3960 u32 desired_divisor, msb_divisor_value, pi_value;
3961
12d7ceed 3962 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3963 msb_divisor_value = desired_divisor / iclk_pi_range;
3964 pi_value = desired_divisor % iclk_pi_range;
3965
3966 auxdiv = 0;
3967 divsel = msb_divisor_value - 2;
3968 phaseinc = pi_value;
3969 }
3970
3971 /* This should not happen with any sane values */
3972 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3973 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3974 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3975 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3976
3977 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3978 clock,
e615efe4
ED		 3979 auxdiv,
3980 divsel,
3981 phasedir,
3982 phaseinc);
3983
3984 /* Program SSCDIVINTPHASE6 */
988d6ee8 3985 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3986 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3987 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3988 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3989 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3990 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3991 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3992 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3993
3994 /* Program SSCAUXDIV */
988d6ee8 3995 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3996 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3997 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3998 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3999
4000 /* Enable modulator and associated divider */
988d6ee8 4001 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4002 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4003 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4004
4005 /* Wait for initialization time */
4006 udelay(24);
4007
4008 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4009
a580516d 4010 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4011}
4012
275f01b2
DV		 4013static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4014 enum pipe pch_transcoder)
4015{
4016 struct drm_device *dev = crtc->base.dev;
4017 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4018 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4019
4020 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4021 I915_READ(HTOTAL(cpu_transcoder)));
4022 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4023 I915_READ(HBLANK(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4025 I915_READ(HSYNC(cpu_transcoder)));
4026
4027 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4028 I915_READ(VTOTAL(cpu_transcoder)));
4029 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4030 I915_READ(VBLANK(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4032 I915_READ(VSYNC(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4034 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4035}
4036
003632d9 4037static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4038{
4039 struct drm_i915_private *dev_priv = dev->dev_private;
4040 uint32_t temp;
4041
4042 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4043 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4044 return;
4045
4046 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4047 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4048
003632d9
ACO		 4049 temp &= ~FDI_BC_BIFURCATION_SELECT;
4050 if (enable)
4051 temp |= FDI_BC_BIFURCATION_SELECT;
4052
4053 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4054 I915_WRITE(SOUTH_CHICKEN1, temp);
4055 POSTING_READ(SOUTH_CHICKEN1);
4056}
4057
4058static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4059{
4060 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4061
4062 switch (intel_crtc->pipe) {
4063 case PIPE_A:
4064 break;
4065 case PIPE_B:
6e3c9717 4066 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4067 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4068 else
003632d9 4069 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4070
4071 break;
4072 case PIPE_C:
003632d9 4073 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4074
4075 break;
4076 default:
4077 BUG();
4078 }
4079}
4080
f67a559d
JB		 4081/*
4082 * Enable PCH resources required for PCH ports:
4083 * - PCH PLLs
4084 * - FDI training & RX/TX
4085 * - update transcoder timings
4086 * - DP transcoding bits
4087 * - transcoder
4088 */
4089static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4090{
4091 struct drm_device *dev = crtc->dev;
4092 struct drm_i915_private *dev_priv = dev->dev_private;
4093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4094 int pipe = intel_crtc->pipe;
ee7b9f93 4095 u32 reg, temp;
2c07245f 4096
ab9412ba 4097 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4098
1fbc0d78
DV		 4099 if (IS_IVYBRIDGE(dev))
4100 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4101
cd986abb
DV		 4102 /* Write the TU size bits before fdi link training, so that error
4103 * detection works. */
4104 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4105 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4106
c98e9dcf 4107 /* For PCH output, training FDI link */
674cf967 4108 dev_priv->display.fdi_link_train(crtc);
2c07245f 4109
3ad8a208
DV		 4110 /* We need to program the right clock selection before writing the pixel
4111 * mutliplier into the DPLL. */
303b81e0 4112 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4113 u32 sel;
4b645f14 4114
c98e9dcf 4115 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4116 temp |= TRANS_DPLL_ENABLE(pipe);
4117 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4118 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4119 temp |= sel;
4120 else
4121 temp &= ~sel;
c98e9dcf 4122 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4123 }
5eddb70b 4124
3ad8a208
DV		 4125 /* XXX: pch pll's can be enabled any time before we enable the PCH
4126 * transcoder, and we actually should do this to not upset any PCH
4127 * transcoder that already use the clock when we share it.
4128 *
4129 * Note that enable_shared_dpll tries to do the right thing, but
4130 * get_shared_dpll unconditionally resets the pll - we need that to have
4131 * the right LVDS enable sequence. */
85b3894f 4132 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4133
d9b6cb56
JB		 4134 /* set transcoder timing, panel must allow it */
4135 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4136 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4137
303b81e0 4138 intel_fdi_normal_train(crtc);
5e84e1a4 4139
c98e9dcf 4140 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4141 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
9c4edaee
VS		 4142 const struct drm_display_mode *adjusted_mode =
4143 &intel_crtc->config->base.adjusted_mode;
dfd07d72 4144 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4145 reg = TRANS_DP_CTL(pipe);
4146 temp = I915_READ(reg);
4147 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4148 TRANS_DP_SYNC_MASK |
4149 TRANS_DP_BPC_MASK);
e3ef4479 4150 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4151 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf 4152
9c4edaee 4153 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4154 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
9c4edaee 4155 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4156 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4157
4158 switch (intel_trans_dp_port_sel(crtc)) {
4159 case PCH_DP_B:
5eddb70b 4160 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4161 break;
4162 case PCH_DP_C:
5eddb70b 4163 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4164 break;
4165 case PCH_DP_D:
5eddb70b 4166 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4167 break;
4168 default:
e95d41e1 4169 BUG();
32f9d658 4170 }
2c07245f 4171
5eddb70b 4172 I915_WRITE(reg, temp);
6be4a607 4173 }
b52eb4dc 4174
b8a4f404 4175 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4176}
4177
1507e5bd
PZ		 4178static void lpt_pch_enable(struct drm_crtc *crtc)
4179{
4180 struct drm_device *dev = crtc->dev;
4181 struct drm_i915_private *dev_priv = dev->dev_private;
4182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4183 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4184
ab9412ba 4185 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4186
8c52b5e8 4187 lpt_program_iclkip(crtc);
1507e5bd 4188
0540e488 4189 /* Set transcoder timing. */
275f01b2 4190 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4191
937bb610 4192 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4193}
4194
190f68c5
ACO		 4195struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4196 struct intel_crtc_state *crtc_state)
ee7b9f93 4197{
e2b78267 4198 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4199 struct intel_shared_dpll *pll;
de419ab6 4200 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4201 enum intel_dpll_id i;
ee7b9f93 4202
de419ab6
ML		 4203 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4204
98b6bd99
DV		 4205 if (HAS_PCH_IBX(dev_priv->dev)) {
4206 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4207 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4208 pll = &dev_priv->shared_dplls[i];
98b6bd99 4209
46edb027
DV		 4210 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4211 crtc->base.base.id, pll->name);
98b6bd99 4212
de419ab6 4213 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4214
98b6bd99
DV		 4215 goto found;
4216 }
4217
bcddf610
S		 4218 if (IS_BROXTON(dev_priv->dev)) {
4219 /* PLL is attached to port in bxt */
4220 struct intel_encoder *encoder;
4221 struct intel_digital_port *intel_dig_port;
4222
4223 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4224 if (WARN_ON(!encoder))
4225 return NULL;
4226
4227 intel_dig_port = enc_to_dig_port(&encoder->base);
4228 /* 1:1 mapping between ports and PLLs */
4229 i = (enum intel_dpll_id)intel_dig_port->port;
4230 pll = &dev_priv->shared_dplls[i];
4231 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4232 crtc->base.base.id, pll->name);
de419ab6 4233 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4234
4235 goto found;
4236 }
4237
e72f9fbf
DV		 4238 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4239 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4240
4241 /* Only want to check enabled timings first */
de419ab6 4242 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4243 continue;
4244
190f68c5 4245 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4246 &shared_dpll[i].hw_state,
4247 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4248 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4249 crtc->base.base.id, pll->name,
de419ab6 4250 shared_dpll[i].crtc_mask,
8bd31e67 4251 pll->active);
ee7b9f93
JB		 4252 goto found;
4253 }
4254 }
4255
4256 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4257 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4258 pll = &dev_priv->shared_dplls[i];
de419ab6 4259 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4260 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4261 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4262 goto found;
4263 }
4264 }
4265
4266 return NULL;
4267
4268found:
de419ab6
ML		 4269 if (shared_dpll[i].crtc_mask == 0)
4270 shared_dpll[i].hw_state =
4271 crtc_state->dpll_hw_state;
f2a69f44 4272
190f68c5 4273 crtc_state->shared_dpll = i;
46edb027
DV		 4274 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4275 pipe_name(crtc->pipe));
ee7b9f93 4276
de419ab6 4277 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4278
ee7b9f93
JB		 4279 return pll;
4280}
4281
de419ab6 4282static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4283{
de419ab6
ML		 4284 struct drm_i915_private *dev_priv = to_i915(state->dev);
4285 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4286 struct intel_shared_dpll *pll;
4287 enum intel_dpll_id i;
4288
de419ab6
ML		 4289 if (!to_intel_atomic_state(state)->dpll_set)
4290 return;
8bd31e67 4291
de419ab6 4292 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4293 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4294 pll = &dev_priv->shared_dplls[i];
de419ab6 4295 pll->config = shared_dpll[i];
8bd31e67
ACO		 4296 }
4297}
4298
a1520318 4299static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4300{
4301 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4302 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4303 u32 temp;
4304
4305 temp = I915_READ(dslreg);
4306 udelay(500);
4307 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4308 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4309 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4310 }
4311}
4312
86adf9d7
ML		 4313static int
4314skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4315 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4316 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4317{
86adf9d7
ML		 4318 struct intel_crtc_scaler_state *scaler_state =
4319 &crtc_state->scaler_state;
4320 struct intel_crtc *intel_crtc =
4321 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4322 int need_scaling;
6156a456
CK		 4323
4324 need_scaling = intel_rotation_90_or_270(rotation) ?
4325 (src_h != dst_w || src_w != dst_h):
4326 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4327
4328 /*
4329 * if plane is being disabled or scaler is no more required or force detach
4330 * - free scaler binded to this plane/crtc
4331 * - in order to do this, update crtc->scaler_usage
4332 *
4333 * Here scaler state in crtc_state is set free so that
4334 * scaler can be assigned to other user. Actual register
4335 * update to free the scaler is done in plane/panel-fit programming.
4336 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4337 */
86adf9d7 4338 if (force_detach || !need_scaling) {
a1b2278e 4339 if (*scaler_id >= 0) {
86adf9d7 4340 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4341 scaler_state->scalers[*scaler_id].in_use = 0;
4342
86adf9d7
ML		 4343 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4344 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4345 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4346 scaler_state->scaler_users);
4347 *scaler_id = -1;
4348 }
4349 return 0;
4350 }
4351
4352 /* range checks */
4353 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4354 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4355
4356 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4357 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4358 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4359 "size is out of scaler range\n",
86adf9d7 4360 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4361 return -EINVAL;
4362 }
4363
86adf9d7
ML		 4364 /* mark this plane as a scaler user in crtc_state */
4365 scaler_state->scaler_users |= (1 << scaler_user);
4366 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4367 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4368 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4369 scaler_state->scaler_users);
4370
4371 return 0;
4372}
4373
4374/**
4375 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4376 *
4377 * @state: crtc's scaler state
86adf9d7
ML		 4378 *
4379 * Return
4380 * 0 - scaler_usage updated successfully
4381 * error - requested scaling cannot be supported or other error condition
4382 */
e435d6e5 4383int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4384{
4385 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
7c5f93b0 4386 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
86adf9d7
ML		 4387
4388 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4389 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4390
e435d6e5 4391 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4392 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4393 state->pipe_src_w, state->pipe_src_h,
aad941d5 4394 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
86adf9d7
ML		 4395}
4396
4397/**
4398 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4399 *
4400 * @state: crtc's scaler state
86adf9d7
ML		 4401 * @plane_state: atomic plane state to update
4402 *
4403 * Return
4404 * 0 - scaler_usage updated successfully
4405 * error - requested scaling cannot be supported or other error condition
4406 */
da20eabd
ML		 4407static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4408 struct intel_plane_state *plane_state)
86adf9d7
ML		 4409{
4410
4411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4412 struct intel_plane *intel_plane =
4413 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4414 struct drm_framebuffer *fb = plane_state->base.fb;
4415 int ret;
4416
4417 bool force_detach = !fb || !plane_state->visible;
4418
4419 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4420 intel_plane->base.base.id, intel_crtc->pipe,
4421 drm_plane_index(&intel_plane->base));
4422
4423 ret = skl_update_scaler(crtc_state, force_detach,
4424 drm_plane_index(&intel_plane->base),
4425 &plane_state->scaler_id,
4426 plane_state->base.rotation,
4427 drm_rect_width(&plane_state->src) >> 16,
4428 drm_rect_height(&plane_state->src) >> 16,
4429 drm_rect_width(&plane_state->dst),
4430 drm_rect_height(&plane_state->dst));
4431
4432 if (ret || plane_state->scaler_id < 0)
4433 return ret;
4434
a1b2278e 4435 /* check colorkey */
818ed961 4436 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4437 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4438 intel_plane->base.base.id);
a1b2278e
CK		 4439 return -EINVAL;
4440 }
4441
4442 /* Check src format */
86adf9d7
ML		 4443 switch (fb->pixel_format) {
4444 case DRM_FORMAT_RGB565:
4445 case DRM_FORMAT_XBGR8888:
4446 case DRM_FORMAT_XRGB8888:
4447 case DRM_FORMAT_ABGR8888:
4448 case DRM_FORMAT_ARGB8888:
4449 case DRM_FORMAT_XRGB2101010:
4450 case DRM_FORMAT_XBGR2101010:
4451 case DRM_FORMAT_YUYV:
4452 case DRM_FORMAT_YVYU:
4453 case DRM_FORMAT_UYVY:
4454 case DRM_FORMAT_VYUY:
4455 break;
4456 default:
4457 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4458 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4459 return -EINVAL;
a1b2278e
CK		 4460 }
4461
a1b2278e
CK		 4462 return 0;
4463}
4464
e435d6e5
ML		 4465static void skylake_scaler_disable(struct intel_crtc *crtc)
4466{
4467 int i;
4468
4469 for (i = 0; i < crtc->num_scalers; i++)
4470 skl_detach_scaler(crtc, i);
4471}
4472
4473static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4474{
4475 struct drm_device *dev = crtc->base.dev;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477 int pipe = crtc->pipe;
a1b2278e
CK		 4478 struct intel_crtc_scaler_state *scaler_state =
4479 &crtc->config->scaler_state;
4480
4481 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4482
6e3c9717 4483 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4484 int id;
4485
4486 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4487 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4488 return;
4489 }
4490
4491 id = scaler_state->scaler_id;
4492 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4493 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4494 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4495 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4496
4497 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4498 }
4499}
4500
b074cec8
JB		 4501static void ironlake_pfit_enable(struct intel_crtc *crtc)
4502{
4503 struct drm_device *dev = crtc->base.dev;
4504 struct drm_i915_private *dev_priv = dev->dev_private;
4505 int pipe = crtc->pipe;
4506
6e3c9717 4507 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4508 /* Force use of hard-coded filter coefficients
4509 * as some pre-programmed values are broken,
4510 * e.g. x201.
4511 */
4512 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4513 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4514 PF_PIPE_SEL_IVB(pipe));
4515 else
4516 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4517 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4518 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4519 }
4520}
4521
20bc8673 4522void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4523{
cea165c3
VS		 4524 struct drm_device *dev = crtc->base.dev;
4525 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4526
6e3c9717 4527 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4528 return;
4529
cea165c3
VS		 4530 /* We can only enable IPS after we enable a plane and wait for a vblank */
4531 intel_wait_for_vblank(dev, crtc->pipe);
4532
d77e4531 4533 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4534 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4535 mutex_lock(&dev_priv->rps.hw_lock);
4536 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4537 mutex_unlock(&dev_priv->rps.hw_lock);
4538 /* Quoting Art Runyan: "its not safe to expect any particular
4539 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4540 * mailbox." Moreover, the mailbox may return a bogus state,
4541 * so we need to just enable it and continue on.
2a114cc1
BW		 4542 */
4543 } else {
4544 I915_WRITE(IPS_CTL, IPS_ENABLE);
4545 /* The bit only becomes 1 in the next vblank, so this wait here
4546 * is essentially intel_wait_for_vblank. If we don't have this
4547 * and don't wait for vblanks until the end of crtc_enable, then
4548 * the HW state readout code will complain that the expected
4549 * IPS_CTL value is not the one we read. */
4550 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4551 DRM_ERROR("Timed out waiting for IPS enable\n");
4552 }
d77e4531
PZ		 4553}
4554
20bc8673 4555void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4556{
4557 struct drm_device *dev = crtc->base.dev;
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559
6e3c9717 4560 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4561 return;
4562
4563 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4564 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4565 mutex_lock(&dev_priv->rps.hw_lock);
4566 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4567 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4568 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4569 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4570 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4571 } else {
2a114cc1 4572 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4573 POSTING_READ(IPS_CTL);
4574 }
d77e4531
PZ		 4575
4576 /* We need to wait for a vblank before we can disable the plane. */
4577 intel_wait_for_vblank(dev, crtc->pipe);
4578}
4579
4580/** Loads the palette/gamma unit for the CRTC with the prepared values */
4581static void intel_crtc_load_lut(struct drm_crtc *crtc)
4582{
4583 struct drm_device *dev = crtc->dev;
4584 struct drm_i915_private *dev_priv = dev->dev_private;
4585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4586 enum pipe pipe = intel_crtc->pipe;
d77e4531
PZ		 4587 int i;
4588 bool reenable_ips = false;
4589
4590 /* The clocks have to be on to load the palette. */
53d9f4e9 4591 if (!crtc->state->active)
d77e4531
PZ		 4592 return;
4593
50360403 4594 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4595 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4596 assert_dsi_pll_enabled(dev_priv);
4597 else
4598 assert_pll_enabled(dev_priv, pipe);
4599 }
4600
d77e4531
PZ		 4601 /* Workaround : Do not read or write the pipe palette/gamma data while
4602 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4603 */
6e3c9717 4604 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4605 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4606 GAMMA_MODE_MODE_SPLIT)) {
4607 hsw_disable_ips(intel_crtc);
4608 reenable_ips = true;
4609 }
4610
4611 for (i = 0; i < 256; i++) {
f65a9c5b
VS		 4612 u32 palreg;
4613
4614 if (HAS_GMCH_DISPLAY(dev))
4615 palreg = PALETTE(pipe, i);
4616 else
4617 palreg = LGC_PALETTE(pipe, i);
4618
4619 I915_WRITE(palreg,
d77e4531
PZ		 4620 (intel_crtc->lut_r[i] << 16) |
4621 (intel_crtc->lut_g[i] << 8) |
4622 intel_crtc->lut_b[i]);
4623 }
4624
4625 if (reenable_ips)
4626 hsw_enable_ips(intel_crtc);
4627}
4628
7cac945f 4629static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4630{
7cac945f 4631 if (intel_crtc->overlay) {
d3eedb1a
VS		 4632 struct drm_device *dev = intel_crtc->base.dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634
4635 mutex_lock(&dev->struct_mutex);
4636 dev_priv->mm.interruptible = false;
4637 (void) intel_overlay_switch_off(intel_crtc->overlay);
4638 dev_priv->mm.interruptible = true;
4639 mutex_unlock(&dev->struct_mutex);
4640 }
4641
4642 /* Let userspace switch the overlay on again. In most cases userspace
4643 * has to recompute where to put it anyway.
4644 */
4645}
4646
87d4300a
ML		 4647/**
4648 * intel_post_enable_primary - Perform operations after enabling primary plane
4649 * @crtc: the CRTC whose primary plane was just enabled
4650 *
4651 * Performs potentially sleeping operations that must be done after the primary
4652 * plane is enabled, such as updating FBC and IPS. Note that this may be
4653 * called due to an explicit primary plane update, or due to an implicit
4654 * re-enable that is caused when a sprite plane is updated to no longer
4655 * completely hide the primary plane.
4656 */
4657static void
4658intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4659{
4660 struct drm_device *dev = crtc->dev;
87d4300a 4661 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4663 int pipe = intel_crtc->pipe;
a5c4d7bc 4664
87d4300a
ML		 4665 /*
4666 * BDW signals flip done immediately if the plane
4667 * is disabled, even if the plane enable is already
4668 * armed to occur at the next vblank :(
4669 */
4670 if (IS_BROADWELL(dev))
4671 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4672
87d4300a
ML		 4673 /*
4674 * FIXME IPS should be fine as long as one plane is
4675 * enabled, but in practice it seems to have problems
4676 * when going from primary only to sprite only and vice
4677 * versa.
4678 */
a5c4d7bc
VS		 4679 hsw_enable_ips(intel_crtc);
4680
f99d7069 4681 /*
87d4300a
ML		 4682 * Gen2 reports pipe underruns whenever all planes are disabled.
4683 * So don't enable underrun reporting before at least some planes
4684 * are enabled.
4685 * FIXME: Need to fix the logic to work when we turn off all planes
4686 * but leave the pipe running.
f99d7069 4687 */
87d4300a
ML		 4688 if (IS_GEN2(dev))
4689 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4690
4691 /* Underruns don't raise interrupts, so check manually. */
4692 if (HAS_GMCH_DISPLAY(dev))
4693 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4694}
4695
87d4300a
ML		 4696/**
4697 * intel_pre_disable_primary - Perform operations before disabling primary plane
4698 * @crtc: the CRTC whose primary plane is to be disabled
4699 *
4700 * Performs potentially sleeping operations that must be done before the
4701 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4702 * be called due to an explicit primary plane update, or due to an implicit
4703 * disable that is caused when a sprite plane completely hides the primary
4704 * plane.
4705 */
4706static void
4707intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4708{
4709 struct drm_device *dev = crtc->dev;
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712 int pipe = intel_crtc->pipe;
a5c4d7bc 4713
87d4300a
ML		 4714 /*
4715 * Gen2 reports pipe underruns whenever all planes are disabled.
4716 * So diasble underrun reporting before all the planes get disabled.
4717 * FIXME: Need to fix the logic to work when we turn off all planes
4718 * but leave the pipe running.
4719 */
4720 if (IS_GEN2(dev))
4721 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4722
87d4300a
ML		 4723 /*
4724 * Vblank time updates from the shadow to live plane control register
4725 * are blocked if the memory self-refresh mode is active at that
4726 * moment. So to make sure the plane gets truly disabled, disable
4727 * first the self-refresh mode. The self-refresh enable bit in turn
4728 * will be checked/applied by the HW only at the next frame start
4729 * event which is after the vblank start event, so we need to have a
4730 * wait-for-vblank between disabling the plane and the pipe.
4731 */
262cd2e1 4732 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4733 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4734 dev_priv->wm.vlv.cxsr = false;
4735 intel_wait_for_vblank(dev, pipe);
4736 }
87d4300a 4737
87d4300a
ML		 4738 /*
4739 * FIXME IPS should be fine as long as one plane is
4740 * enabled, but in practice it seems to have problems
4741 * when going from primary only to sprite only and vice
4742 * versa.
4743 */
a5c4d7bc 4744 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4745}
4746
ac21b225
ML		 4747static void intel_post_plane_update(struct intel_crtc *crtc)
4748{
4749 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4750 struct drm_device *dev = crtc->base.dev;
7733b49b 4751 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4752
4753 if (atomic->wait_vblank)
4754 intel_wait_for_vblank(dev, crtc->pipe);
4755
4756 intel_frontbuffer_flip(dev, atomic->fb_bits);
4757
852eb00d
VS		 4758 if (atomic->disable_cxsr)
4759 crtc->wm.cxsr_allowed = true;
4760
f015c551
VS		 4761 if (crtc->atomic.update_wm_post)
4762 intel_update_watermarks(&crtc->base);
4763
c80ac854 4764 if (atomic->update_fbc)
7733b49b 4765 intel_fbc_update(dev_priv);
ac21b225
ML		 4766
4767 if (atomic->post_enable_primary)
4768 intel_post_enable_primary(&crtc->base);
4769
ac21b225
ML		 4770 memset(atomic, 0, sizeof(*atomic));
4771}
4772
4773static void intel_pre_plane_update(struct intel_crtc *crtc)
4774{
4775 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4776 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225 4777 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
ac21b225 4778
c80ac854 4779 if (atomic->disable_fbc)
25ad93fd 4780 intel_fbc_disable_crtc(crtc);
ac21b225 4781
066cf55b
RV		 4782 if (crtc->atomic.disable_ips)
4783 hsw_disable_ips(crtc);
4784
ac21b225
ML		 4785 if (atomic->pre_disable_primary)
4786 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4787
4788 if (atomic->disable_cxsr) {
4789 crtc->wm.cxsr_allowed = false;
4790 intel_set_memory_cxsr(dev_priv, false);
4791 }
ac21b225
ML		 4792}
4793
d032ffa0 4794static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4795{
4796 struct drm_device *dev = crtc->dev;
4797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4798 struct drm_plane *p;
87d4300a
ML		 4799 int pipe = intel_crtc->pipe;
4800
7cac945f 4801 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4802
d032ffa0
ML		 4803 drm_for_each_plane_mask(p, dev, plane_mask)
4804 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4805
f99d7069
DV		 4806 /*
4807 * FIXME: Once we grow proper nuclear flip support out of this we need
4808 * to compute the mask of flip planes precisely. For the time being
4809 * consider this a flip to a NULL plane.
4810 */
4811 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4812}
4813
f67a559d
JB		 4814static void ironlake_crtc_enable(struct drm_crtc *crtc)
4815{
4816 struct drm_device *dev = crtc->dev;
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4819 struct intel_encoder *encoder;
f67a559d 4820 int pipe = intel_crtc->pipe;
f67a559d 4821
53d9f4e9 4822 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4823 return;
4824
6e3c9717 4825 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4826 intel_prepare_shared_dpll(intel_crtc);
4827
6e3c9717 4828 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4829 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4830
4831 intel_set_pipe_timings(intel_crtc);
4832
6e3c9717 4833 if (intel_crtc->config->has_pch_encoder) {
29407aab 4834 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4835 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4836 }
4837
4838 ironlake_set_pipeconf(crtc);
4839
f67a559d 4840 intel_crtc->active = true;
8664281b 4841
a72e4c9f
DV		 4842 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4843 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4844
f6736a1a 4845 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4846 if (encoder->pre_enable)
4847 encoder->pre_enable(encoder);
f67a559d 4848
6e3c9717 4849 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4850 /* Note: FDI PLL enabling _must_ be done before we enable the
4851 * cpu pipes, hence this is separate from all the other fdi/pch
4852 * enabling. */
88cefb6c 4853 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4854 } else {
4855 assert_fdi_tx_disabled(dev_priv, pipe);
4856 assert_fdi_rx_disabled(dev_priv, pipe);
4857 }
f67a559d 4858
b074cec8 4859 ironlake_pfit_enable(intel_crtc);
f67a559d 4860
9c54c0dd
JB		 4861 /*
4862 * On ILK+ LUT must be loaded before the pipe is running but with
4863 * clocks enabled
4864 */
4865 intel_crtc_load_lut(crtc);
4866
f37fcc2a 4867 intel_update_watermarks(crtc);
e1fdc473 4868 intel_enable_pipe(intel_crtc);
f67a559d 4869
6e3c9717 4870 if (intel_crtc->config->has_pch_encoder)
f67a559d 4871 ironlake_pch_enable(crtc);
c98e9dcf 4872
f9b61ff6
DV		 4873 assert_vblank_disabled(crtc);
4874 drm_crtc_vblank_on(crtc);
4875
fa5c73b1
DV		 4876 for_each_encoder_on_crtc(dev, crtc, encoder)
4877 encoder->enable(encoder);
61b77ddd
DV		 4878
4879 if (HAS_PCH_CPT(dev))
a1520318 4880 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4881}
4882
42db64ef
PZ		 4883/* IPS only exists on ULT machines and is tied to pipe A. */
4884static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4885{
f5adf94e 4886 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4887}
4888
4f771f10
PZ		 4889static void haswell_crtc_enable(struct drm_crtc *crtc)
4890{
4891 struct drm_device *dev = crtc->dev;
4892 struct drm_i915_private *dev_priv = dev->dev_private;
4893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4894 struct intel_encoder *encoder;
99d736a2
ML		 4895 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4896 struct intel_crtc_state *pipe_config =
4897 to_intel_crtc_state(crtc->state);
7d4aefd0 4898 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4f771f10 4899
53d9f4e9 4900 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4901 return;
4902
df8ad70c
DV		 4903 if (intel_crtc_to_shared_dpll(intel_crtc))
4904 intel_enable_shared_dpll(intel_crtc);
4905
6e3c9717 4906 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4907 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4908
4909 intel_set_pipe_timings(intel_crtc);
4910
6e3c9717
ACO		 4911 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4912 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4913 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4914 }
4915
6e3c9717 4916 if (intel_crtc->config->has_pch_encoder) {
229fca97 4917 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4918 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4919 }
4920
4921 haswell_set_pipeconf(crtc);
4922
4923 intel_set_pipe_csc(crtc);
4924
4f771f10 4925 intel_crtc->active = true;
8664281b 4926
a72e4c9f 4927 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7d4aefd0
SS		 4928 for_each_encoder_on_crtc(dev, crtc, encoder) {
4929 if (encoder->pre_pll_enable)
4930 encoder->pre_pll_enable(encoder);
4f771f10
PZ		 4931 if (encoder->pre_enable)
4932 encoder->pre_enable(encoder);
7d4aefd0 4933 }
4f771f10 4934
6e3c9717 4935 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4936 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4937 true);
4fe9467d
ID		 4938 dev_priv->display.fdi_link_train(crtc);
4939 }
4940
7d4aefd0
SS		 4941 if (!is_dsi)
4942 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4943
1c132b44 4944 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 4945 skylake_pfit_enable(intel_crtc);
ff6d9f55 4946 else
1c132b44 4947 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4948
4949 /*
4950 * On ILK+ LUT must be loaded before the pipe is running but with
4951 * clocks enabled
4952 */
4953 intel_crtc_load_lut(crtc);
4954
1f544388 4955 intel_ddi_set_pipe_settings(crtc);
7d4aefd0
SS		 4956 if (!is_dsi)
4957 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4958
f37fcc2a 4959 intel_update_watermarks(crtc);
e1fdc473 4960 intel_enable_pipe(intel_crtc);
42db64ef 4961
6e3c9717 4962 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4963 lpt_pch_enable(crtc);
4f771f10 4964
7d4aefd0 4965 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
0e32b39c
DA		 4966 intel_ddi_set_vc_payload_alloc(crtc, true);
4967
f9b61ff6
DV		 4968 assert_vblank_disabled(crtc);
4969 drm_crtc_vblank_on(crtc);
4970
8807e55b 4971 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4972 encoder->enable(encoder);
8807e55b
JN		 4973 intel_opregion_notify_encoder(encoder, true);
4974 }
4f771f10 4975
e4916946
PZ		 4976 /* If we change the relative order between pipe/planes enabling, we need
4977 * to change the workaround. */
99d736a2
ML		 4978 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4979 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4980 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4981 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4982 }
4f771f10
PZ		 4983}
4984
bfd16b2a 4985static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
3f8dce3a
DV		 4986{
4987 struct drm_device *dev = crtc->base.dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 int pipe = crtc->pipe;
4990
4991 /* To avoid upsetting the power well on haswell only disable the pfit if
4992 * it's in use. The hw state code will make sure we get this right. */
bfd16b2a 4993 if (force || crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4994 I915_WRITE(PF_CTL(pipe), 0);
4995 I915_WRITE(PF_WIN_POS(pipe), 0);
4996 I915_WRITE(PF_WIN_SZ(pipe), 0);
4997 }
4998}
4999
6be4a607
JB		 5000static void ironlake_crtc_disable(struct drm_crtc *crtc)
5001{
5002 struct drm_device *dev = crtc->dev;
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5005 struct intel_encoder *encoder;
6be4a607 5006 int pipe = intel_crtc->pipe;
5eddb70b 5007 u32 reg, temp;
b52eb4dc 5008
ea9d758d
DV		 5009 for_each_encoder_on_crtc(dev, crtc, encoder)
5010 encoder->disable(encoder);
5011
f9b61ff6
DV		 5012 drm_crtc_vblank_off(crtc);
5013 assert_vblank_disabled(crtc);
5014
6e3c9717 5015 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5016 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5017
575f7ab7 5018 intel_disable_pipe(intel_crtc);
32f9d658 5019
bfd16b2a 5020 ironlake_pfit_disable(intel_crtc, false);
2c07245f 5021
5a74f70a
VS		 5022 if (intel_crtc->config->has_pch_encoder)
5023 ironlake_fdi_disable(crtc);
5024
bf49ec8c
DV		 5025 for_each_encoder_on_crtc(dev, crtc, encoder)
5026 if (encoder->post_disable)
5027 encoder->post_disable(encoder);
2c07245f 5028
6e3c9717 5029 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5030 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5031
d925c59a
DV		 5032 if (HAS_PCH_CPT(dev)) {
5033 /* disable TRANS_DP_CTL */
5034 reg = TRANS_DP_CTL(pipe);
5035 temp = I915_READ(reg);
5036 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5037 TRANS_DP_PORT_SEL_MASK);
5038 temp |= TRANS_DP_PORT_SEL_NONE;
5039 I915_WRITE(reg, temp);
5040
5041 /* disable DPLL_SEL */
5042 temp = I915_READ(PCH_DPLL_SEL);
11887397 5043 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5044 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5045 }
e3421a18 5046
d925c59a
DV		 5047 ironlake_fdi_pll_disable(intel_crtc);
5048 }
6be4a607 5049}
1b3c7a47 5050
4f771f10 5051static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5052{
4f771f10
PZ		 5053 struct drm_device *dev = crtc->dev;
5054 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5056 struct intel_encoder *encoder;
6e3c9717 5057 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7d4aefd0 5058 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
ee7b9f93 5059
8807e55b
JN		 5060 for_each_encoder_on_crtc(dev, crtc, encoder) {
5061 intel_opregion_notify_encoder(encoder, false);
4f771f10 5062 encoder->disable(encoder);
8807e55b 5063 }
4f771f10 5064
f9b61ff6
DV		 5065 drm_crtc_vblank_off(crtc);
5066 assert_vblank_disabled(crtc);
5067
6e3c9717 5068 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5069 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5070 false);
575f7ab7 5071 intel_disable_pipe(intel_crtc);
4f771f10 5072
6e3c9717 5073 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5074 intel_ddi_set_vc_payload_alloc(crtc, false);
5075
7d4aefd0
SS		 5076 if (!is_dsi)
5077 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5078
1c132b44 5079 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5080 skylake_scaler_disable(intel_crtc);
ff6d9f55 5081 else
bfd16b2a 5082 ironlake_pfit_disable(intel_crtc, false);
4f771f10 5083
7d4aefd0
SS		 5084 if (!is_dsi)
5085 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5086
6e3c9717 5087 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5088 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5089 intel_ddi_fdi_disable(crtc);
83616634 5090 }
4f771f10 5091
97b040aa
ID		 5092 for_each_encoder_on_crtc(dev, crtc, encoder)
5093 if (encoder->post_disable)
5094 encoder->post_disable(encoder);
4f771f10
PZ		 5095}
5096
2dd24552
JB		 5097static void i9xx_pfit_enable(struct intel_crtc *crtc)
5098{
5099 struct drm_device *dev = crtc->base.dev;
5100 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5101 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5102
681a8504 5103 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5104 return;
5105
2dd24552 5106 /*
c0b03411
DV		 5107 * The panel fitter should only be adjusted whilst the pipe is disabled,
5108 * according to register description and PRM.
2dd24552 5109 */
c0b03411
DV		 5110 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5111 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5112
b074cec8
JB		 5113 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5114 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5115
5116 /* Border color in case we don't scale up to the full screen. Black by
5117 * default, change to something else for debugging. */
5118 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5119}
5120
d05410f9
DA		 5121static enum intel_display_power_domain port_to_power_domain(enum port port)
5122{
5123 switch (port) {
5124 case PORT_A:
5125 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5126 case PORT_B:
5127 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5128 case PORT_C:
5129 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5130 case PORT_D:
5131 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ		 5132 case PORT_E:
5133 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA		 5134 default:
5135 WARN_ON_ONCE(1);
5136 return POWER_DOMAIN_PORT_OTHER;
5137 }
5138}
5139
77d22dca
ID		 5140#define for_each_power_domain(domain, mask) \
5141 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5142 if ((1 << (domain)) & (mask))
5143
319be8ae
ID		 5144enum intel_display_power_domain
5145intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5146{
5147 struct drm_device *dev = intel_encoder->base.dev;
5148 struct intel_digital_port *intel_dig_port;
5149
5150 switch (intel_encoder->type) {
5151 case INTEL_OUTPUT_UNKNOWN:
5152 /* Only DDI platforms should ever use this output type */
5153 WARN_ON_ONCE(!HAS_DDI(dev));
5154 case INTEL_OUTPUT_DISPLAYPORT:
5155 case INTEL_OUTPUT_HDMI:
5156 case INTEL_OUTPUT_EDP:
5157 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5158 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5159 case INTEL_OUTPUT_DP_MST:
5160 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5161 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5162 case INTEL_OUTPUT_ANALOG:
5163 return POWER_DOMAIN_PORT_CRT;
5164 case INTEL_OUTPUT_DSI:
5165 return POWER_DOMAIN_PORT_DSI;
5166 default:
5167 return POWER_DOMAIN_PORT_OTHER;
5168 }
5169}
5170
5171static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5172{
319be8ae
ID		 5173 struct drm_device *dev = crtc->dev;
5174 struct intel_encoder *intel_encoder;
5175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5176 enum pipe pipe = intel_crtc->pipe;
77d22dca 5177 unsigned long mask;
1a70a728 5178 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
77d22dca 5179
292b990e
ML		 5180 if (!crtc->state->active)
5181 return 0;
5182
77d22dca
ID		 5183 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5184 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5185 if (intel_crtc->config->pch_pfit.enabled ||
5186 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5187 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5188
319be8ae
ID		 5189 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5190 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5191
77d22dca
ID		 5192 return mask;
5193}
5194
292b990e 5195static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5196{
292b990e
ML		 5197 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5199 enum intel_display_power_domain domain;
5200 unsigned long domains, new_domains, old_domains;
77d22dca 5201
292b990e
ML		 5202 old_domains = intel_crtc->enabled_power_domains;
5203 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5204
292b990e
ML		 5205 domains = new_domains & ~old_domains;
5206
5207 for_each_power_domain(domain, domains)
5208 intel_display_power_get(dev_priv, domain);
5209
5210 return old_domains & ~new_domains;
5211}
5212
5213static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5214 unsigned long domains)
5215{
5216 enum intel_display_power_domain domain;
5217
5218 for_each_power_domain(domain, domains)
5219 intel_display_power_put(dev_priv, domain);
5220}
77d22dca 5221
292b990e
ML		 5222static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5223{
5224 struct drm_device *dev = state->dev;
5225 struct drm_i915_private *dev_priv = dev->dev_private;
5226 unsigned long put_domains[I915_MAX_PIPES] = {};
5227 struct drm_crtc_state *crtc_state;
5228 struct drm_crtc *crtc;
5229 int i;
77d22dca 5230
292b990e
ML		 5231 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5232 if (needs_modeset(crtc->state))
5233 put_domains[to_intel_crtc(crtc)->pipe] =
5234 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5235 }
5236
27c329ed
ML		 5237 if (dev_priv->display.modeset_commit_cdclk) {
5238 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5239
5240 if (cdclk != dev_priv->cdclk_freq &&
5241 !WARN_ON(!state->allow_modeset))
5242 dev_priv->display.modeset_commit_cdclk(state);
5243 }
50f6e502 5244
292b990e
ML		 5245 for (i = 0; i < I915_MAX_PIPES; i++)
5246 if (put_domains[i])
5247 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5248}
5249
adafdc6f
MK		 5250static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5251{
5252 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5253
5254 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5255 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5256 return max_cdclk_freq;
5257 else if (IS_CHERRYVIEW(dev_priv))
5258 return max_cdclk_freq*95/100;
5259 else if (INTEL_INFO(dev_priv)->gen < 4)
5260 return 2*max_cdclk_freq*90/100;
5261 else
5262 return max_cdclk_freq*90/100;
5263}
5264
560a7ae4
DL		 5265static void intel_update_max_cdclk(struct drm_device *dev)
5266{
5267 struct drm_i915_private *dev_priv = dev->dev_private;
5268
ef11bdb3 5269 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
560a7ae4
DL		 5270 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5271
5272 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5273 dev_priv->max_cdclk_freq = 675000;
5274 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5275 dev_priv->max_cdclk_freq = 540000;
5276 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5277 dev_priv->max_cdclk_freq = 450000;
5278 else
5279 dev_priv->max_cdclk_freq = 337500;
5280 } else if (IS_BROADWELL(dev)) {
5281 /*
5282 * FIXME with extra cooling we can allow
5283 * 540 MHz for ULX and 675 Mhz for ULT.
5284 * How can we know if extra cooling is
5285 * available? PCI ID, VTB, something else?
5286 */
5287 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5288 dev_priv->max_cdclk_freq = 450000;
5289 else if (IS_BDW_ULX(dev))
5290 dev_priv->max_cdclk_freq = 450000;
5291 else if (IS_BDW_ULT(dev))
5292 dev_priv->max_cdclk_freq = 540000;
5293 else
5294 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5295 } else if (IS_CHERRYVIEW(dev)) {
5296 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5297 } else if (IS_VALLEYVIEW(dev)) {
5298 dev_priv->max_cdclk_freq = 400000;
5299 } else {
5300 /* otherwise assume cdclk is fixed */
5301 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5302 }
5303
adafdc6f
MK		 5304 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5305
560a7ae4
DL		 5306 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5307 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5308
5309 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5310 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5311}
5312
5313static void intel_update_cdclk(struct drm_device *dev)
5314{
5315 struct drm_i915_private *dev_priv = dev->dev_private;
5316
5317 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5318 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5319 dev_priv->cdclk_freq);
5320
5321 /*
5322 * Program the gmbus_freq based on the cdclk frequency.
5323 * BSpec erroneously claims we should aim for 4MHz, but
5324 * in fact 1MHz is the correct frequency.
5325 */
5326 if (IS_VALLEYVIEW(dev)) {
5327 /*
5328 * Program the gmbus_freq based on the cdclk frequency.
5329 * BSpec erroneously claims we should aim for 4MHz, but
5330 * in fact 1MHz is the correct frequency.
5331 */
5332 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5333 }
5334
5335 if (dev_priv->max_cdclk_freq == 0)
5336 intel_update_max_cdclk(dev);
5337}
5338
70d0c574 5339static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5340{
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5342 uint32_t divider;
5343 uint32_t ratio;
5344 uint32_t current_freq;
5345 int ret;
5346
5347 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5348 switch (frequency) {
5349 case 144000:
5350 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5351 ratio = BXT_DE_PLL_RATIO(60);
5352 break;
5353 case 288000:
5354 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5355 ratio = BXT_DE_PLL_RATIO(60);
5356 break;
5357 case 384000:
5358 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5359 ratio = BXT_DE_PLL_RATIO(60);
5360 break;
5361 case 576000:
5362 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5363 ratio = BXT_DE_PLL_RATIO(60);
5364 break;
5365 case 624000:
5366 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5367 ratio = BXT_DE_PLL_RATIO(65);
5368 break;
5369 case 19200:
5370 /*
5371 * Bypass frequency with DE PLL disabled. Init ratio, divider
5372 * to suppress GCC warning.
5373 */
5374 ratio = 0;
5375 divider = 0;
5376 break;
5377 default:
5378 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5379
5380 return;
5381 }
5382
5383 mutex_lock(&dev_priv->rps.hw_lock);
5384 /* Inform power controller of upcoming frequency change */
5385 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5386 0x80000000);
5387 mutex_unlock(&dev_priv->rps.hw_lock);
5388
5389 if (ret) {
5390 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5391 ret, frequency);
5392 return;
5393 }
5394
5395 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5396 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5397 current_freq = current_freq * 500 + 1000;
5398
5399 /*
5400 * DE PLL has to be disabled when
5401 * - setting to 19.2MHz (bypass, PLL isn't used)
5402 * - before setting to 624MHz (PLL needs toggling)
5403 * - before setting to any frequency from 624MHz (PLL needs toggling)
5404 */
5405 if (frequency == 19200 || frequency == 624000 ||
5406 current_freq == 624000) {
5407 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5408 /* Timeout 200us */
5409 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5410 1))
5411 DRM_ERROR("timout waiting for DE PLL unlock\n");
5412 }
5413
5414 if (frequency != 19200) {
5415 uint32_t val;
5416
5417 val = I915_READ(BXT_DE_PLL_CTL);
5418 val &= ~BXT_DE_PLL_RATIO_MASK;
5419 val |= ratio;
5420 I915_WRITE(BXT_DE_PLL_CTL, val);
5421
5422 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5423 /* Timeout 200us */
5424 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5425 DRM_ERROR("timeout waiting for DE PLL lock\n");
5426
5427 val = I915_READ(CDCLK_CTL);
5428 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5429 val |= divider;
5430 /*
5431 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5432 * enable otherwise.
5433 */
5434 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5435 if (frequency >= 500000)
5436 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5437
5438 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5439 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5440 val |= (frequency - 1000) / 500;
5441 I915_WRITE(CDCLK_CTL, val);
5442 }
5443
5444 mutex_lock(&dev_priv->rps.hw_lock);
5445 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5446 DIV_ROUND_UP(frequency, 25000));
5447 mutex_unlock(&dev_priv->rps.hw_lock);
5448
5449 if (ret) {
5450 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5451 ret, frequency);
5452 return;
5453 }
5454
a47871bd 5455 intel_update_cdclk(dev);
f8437dd1
VK		 5456}
5457
5458void broxton_init_cdclk(struct drm_device *dev)
5459{
5460 struct drm_i915_private *dev_priv = dev->dev_private;
5461 uint32_t val;
5462
5463 /*
5464 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5465 * or else the reset will hang because there is no PCH to respond.
5466 * Move the handshake programming to initialization sequence.
5467 * Previously was left up to BIOS.
5468 */
5469 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5470 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5471 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5472
5473 /* Enable PG1 for cdclk */
5474 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5475
5476 /* check if cd clock is enabled */
5477 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5478 DRM_DEBUG_KMS("Display already initialized\n");
5479 return;
5480 }
5481
5482 /*
5483 * FIXME:
5484 * - The initial CDCLK needs to be read from VBT.
5485 * Need to make this change after VBT has changes for BXT.
5486 * - check if setting the max (or any) cdclk freq is really necessary
5487 * here, it belongs to modeset time
5488 */
5489 broxton_set_cdclk(dev, 624000);
5490
5491 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5492 POSTING_READ(DBUF_CTL);
5493
f8437dd1
VK		 5494 udelay(10);
5495
5496 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5497 DRM_ERROR("DBuf power enable timeout!\n");
5498}
5499
5500void broxton_uninit_cdclk(struct drm_device *dev)
5501{
5502 struct drm_i915_private *dev_priv = dev->dev_private;
5503
5504 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5505 POSTING_READ(DBUF_CTL);
5506
f8437dd1
VK		 5507 udelay(10);
5508
5509 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5510 DRM_ERROR("DBuf power disable timeout!\n");
5511
5512 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5513 broxton_set_cdclk(dev, 19200);
5514
5515 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5516}
5517
5d96d8af
DL		 5518static const struct skl_cdclk_entry {
5519 unsigned int freq;
5520 unsigned int vco;
5521} skl_cdclk_frequencies[] = {
5522 { .freq = 308570, .vco = 8640 },
5523 { .freq = 337500, .vco = 8100 },
5524 { .freq = 432000, .vco = 8640 },
5525 { .freq = 450000, .vco = 8100 },
5526 { .freq = 540000, .vco = 8100 },
5527 { .freq = 617140, .vco = 8640 },
5528 { .freq = 675000, .vco = 8100 },
5529};
5530
5531static unsigned int skl_cdclk_decimal(unsigned int freq)
5532{
5533 return (freq - 1000) / 500;
5534}
5535
5536static unsigned int skl_cdclk_get_vco(unsigned int freq)
5537{
5538 unsigned int i;
5539
5540 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5541 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5542
5543 if (e->freq == freq)
5544 return e->vco;
5545 }
5546
5547 return 8100;
5548}
5549
5550static void
5551skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5552{
5553 unsigned int min_freq;
5554 u32 val;
5555
5556 /* select the minimum CDCLK before enabling DPLL 0 */
5557 val = I915_READ(CDCLK_CTL);
5558 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5559 val |= CDCLK_FREQ_337_308;
5560
5561 if (required_vco == 8640)
5562 min_freq = 308570;
5563 else
5564 min_freq = 337500;
5565
5566 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5567
5568 I915_WRITE(CDCLK_CTL, val);
5569 POSTING_READ(CDCLK_CTL);
5570
5571 /*
5572 * We always enable DPLL0 with the lowest link rate possible, but still
5573 * taking into account the VCO required to operate the eDP panel at the
5574 * desired frequency. The usual DP link rates operate with a VCO of
5575 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5576 * The modeset code is responsible for the selection of the exact link
5577 * rate later on, with the constraint of choosing a frequency that
5578 * works with required_vco.
5579 */
5580 val = I915_READ(DPLL_CTRL1);
5581
5582 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5583 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5584 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5585 if (required_vco == 8640)
5586 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5587 SKL_DPLL0);
5588 else
5589 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5590 SKL_DPLL0);
5591
5592 I915_WRITE(DPLL_CTRL1, val);
5593 POSTING_READ(DPLL_CTRL1);
5594
5595 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5596
5597 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5598 DRM_ERROR("DPLL0 not locked\n");
5599}
5600
5601static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5602{
5603 int ret;
5604 u32 val;
5605
5606 /* inform PCU we want to change CDCLK */
5607 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5608 mutex_lock(&dev_priv->rps.hw_lock);
5609 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5610 mutex_unlock(&dev_priv->rps.hw_lock);
5611
5612 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5613}
5614
5615static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5616{
5617 unsigned int i;
5618
5619 for (i = 0; i < 15; i++) {
5620 if (skl_cdclk_pcu_ready(dev_priv))
5621 return true;
5622 udelay(10);
5623 }
5624
5625 return false;
5626}
5627
5628static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5629{
560a7ae4 5630 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5631 u32 freq_select, pcu_ack;
5632
5633 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5634
5635 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5636 DRM_ERROR("failed to inform PCU about cdclk change\n");
5637 return;
5638 }
5639
5640 /* set CDCLK_CTL */
5641 switch(freq) {
5642 case 450000:
5643 case 432000:
5644 freq_select = CDCLK_FREQ_450_432;
5645 pcu_ack = 1;
5646 break;
5647 case 540000:
5648 freq_select = CDCLK_FREQ_540;
5649 pcu_ack = 2;
5650 break;
5651 case 308570:
5652 case 337500:
5653 default:
5654 freq_select = CDCLK_FREQ_337_308;
5655 pcu_ack = 0;
5656 break;
5657 case 617140:
5658 case 675000:
5659 freq_select = CDCLK_FREQ_675_617;
5660 pcu_ack = 3;
5661 break;
5662 }
5663
5664 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5665 POSTING_READ(CDCLK_CTL);
5666
5667 /* inform PCU of the change */
5668 mutex_lock(&dev_priv->rps.hw_lock);
5669 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5670 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5671
5672 intel_update_cdclk(dev);
5d96d8af
DL		 5673}
5674
5675void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5676{
5677 /* disable DBUF power */
5678 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5679 POSTING_READ(DBUF_CTL);
5680
5681 udelay(10);
5682
5683 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5684 DRM_ERROR("DBuf power disable timeout\n");
5685
4e961e42
AM		 5686 /*
5687 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5688 */
5689 if (dev_priv->csr.dmc_payload) {
5690 /* disable DPLL0 */
5691 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5692 ~LCPLL_PLL_ENABLE);
5693 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5694 DRM_ERROR("Couldn't disable DPLL0\n");
5695 }
5d96d8af
DL		 5696
5697 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5698}
5699
5700void skl_init_cdclk(struct drm_i915_private *dev_priv)
5701{
5702 u32 val;
5703 unsigned int required_vco;
5704
5705 /* enable PCH reset handshake */
5706 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5707 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5708
5709 /* enable PG1 and Misc I/O */
5710 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5711
39d9b85a
GW		 5712 /* DPLL0 not enabled (happens on early BIOS versions) */
5713 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5714 /* enable DPLL0 */
5715 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5716 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5717 }
5718
5d96d8af
DL		 5719 /* set CDCLK to the frequency the BIOS chose */
5720 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5721
5722 /* enable DBUF power */
5723 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5724 POSTING_READ(DBUF_CTL);
5725
5726 udelay(10);
5727
5728 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5729 DRM_ERROR("DBuf power enable timeout\n");
5730}
5731
c73666f3
SK		 5732int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5733{
5734 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5735 uint32_t cdctl = I915_READ(CDCLK_CTL);
5736 int freq = dev_priv->skl_boot_cdclk;
5737
f1b391a5
SK		 5738 /*
5739 * check if the pre-os intialized the display
5740 * There is SWF18 scratchpad register defined which is set by the
5741 * pre-os which can be used by the OS drivers to check the status
5742 */
5743 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5744 goto sanitize;
5745
c73666f3
SK		 5746 /* Is PLL enabled and locked ? */
5747 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5748 goto sanitize;
5749
5750 /* DPLL okay; verify the cdclock
5751 *
5752 * Noticed in some instances that the freq selection is correct but
5753 * decimal part is programmed wrong from BIOS where pre-os does not
5754 * enable display. Verify the same as well.
5755 */
5756 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5757 /* All well; nothing to sanitize */
5758 return false;
5759sanitize:
5760 /*
5761 * As of now initialize with max cdclk till
5762 * we get dynamic cdclk support
5763 * */
5764 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5765 skl_init_cdclk(dev_priv);
5766
5767 /* we did have to sanitize */
5768 return true;
5769}
5770
30a970c6
JB		 5771/* Adjust CDclk dividers to allow high res or save power if possible */
5772static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5773{
5774 struct drm_i915_private *dev_priv = dev->dev_private;
5775 u32 val, cmd;
5776
164dfd28
VK		 5777 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5778 != dev_priv->cdclk_freq);
d60c4473 5779
dfcab17e 5780 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5781 cmd = 2;
dfcab17e 5782 else if (cdclk == 266667)
30a970c6
JB		 5783 cmd = 1;
5784 else
5785 cmd = 0;
5786
5787 mutex_lock(&dev_priv->rps.hw_lock);
5788 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5789 val &= ~DSPFREQGUAR_MASK;
5790 val |= (cmd << DSPFREQGUAR_SHIFT);
5791 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5792 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5793 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5794 50)) {
5795 DRM_ERROR("timed out waiting for CDclk change\n");
5796 }
5797 mutex_unlock(&dev_priv->rps.hw_lock);
5798
54433e91
VS		 5799 mutex_lock(&dev_priv->sb_lock);
5800
dfcab17e 5801 if (cdclk == 400000) {
6bcda4f0 5802 u32 divider;
30a970c6 5803
6bcda4f0 5804 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5805
30a970c6
JB		 5806 /* adjust cdclk divider */
5807 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
87d5d259 5808 val &= ~CCK_FREQUENCY_VALUES;
30a970c6
JB		 5809 val |= divider;
5810 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5811
5812 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
87d5d259 5813 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
a877e801
VS		 5814 50))
5815 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5816 }
5817
30a970c6
JB		 5818 /* adjust self-refresh exit latency value */
5819 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5820 val &= ~0x7f;
5821
5822 /*
5823 * For high bandwidth configs, we set a higher latency in the bunit
5824 * so that the core display fetch happens in time to avoid underruns.
5825 */
dfcab17e 5826 if (cdclk == 400000)
30a970c6
JB		 5827 val |= 4500 / 250; /* 4.5 usec */
5828 else
5829 val |= 3000 / 250; /* 3.0 usec */
5830 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5831
a580516d 5832 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5833
b6283055 5834 intel_update_cdclk(dev);
30a970c6
JB		 5835}
5836
383c5a6a
VS		 5837static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5838{
5839 struct drm_i915_private *dev_priv = dev->dev_private;
5840 u32 val, cmd;
5841
164dfd28
VK		 5842 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5843 != dev_priv->cdclk_freq);
383c5a6a
VS		 5844
5845 switch (cdclk) {
383c5a6a
VS		 5846 case 333333:
5847 case 320000:
383c5a6a 5848 case 266667:
383c5a6a 5849 case 200000:
383c5a6a
VS		 5850 break;
5851 default:
5f77eeb0 5852 MISSING_CASE(cdclk);
383c5a6a
VS		 5853 return;
5854 }
5855
9d0d3fda
VS		 5856 /*
5857 * Specs are full of misinformation, but testing on actual
5858 * hardware has shown that we just need to write the desired
5859 * CCK divider into the Punit register.
5860 */
5861 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5862
383c5a6a
VS		 5863 mutex_lock(&dev_priv->rps.hw_lock);
5864 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5865 val &= ~DSPFREQGUAR_MASK_CHV;
5866 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5867 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5868 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5869 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5870 50)) {
5871 DRM_ERROR("timed out waiting for CDclk change\n");
5872 }
5873 mutex_unlock(&dev_priv->rps.hw_lock);
5874
b6283055 5875 intel_update_cdclk(dev);
383c5a6a
VS		 5876}
5877
30a970c6
JB		 5878static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5879 int max_pixclk)
5880{
6bcda4f0 5881 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5882 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5883
30a970c6
JB		 5884 /*
5885 * Really only a few cases to deal with, as only 4 CDclks are supported:
5886 * 200MHz
5887 * 267MHz
29dc7ef3 5888 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5889 * 400MHz (VLV only)
5890 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5891 * of the lower bin and adjust if needed.
e37c67a1
VS		 5892 *
5893 * We seem to get an unstable or solid color picture at 200MHz.
5894 * Not sure what's wrong. For now use 200MHz only when all pipes
5895 * are off.
30a970c6 5896 */
6cca3195
VS		 5897 if (!IS_CHERRYVIEW(dev_priv) &&
5898 max_pixclk > freq_320*limit/100)
dfcab17e 5899 return 400000;
6cca3195 5900 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5901 return freq_320;
e37c67a1 5902 else if (max_pixclk > 0)
dfcab17e 5903 return 266667;
e37c67a1
VS		 5904 else
5905 return 200000;
30a970c6
JB		 5906}
5907
f8437dd1
VK		 5908static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5909 int max_pixclk)
5910{
5911 /*
5912 * FIXME:
5913 * - remove the guardband, it's not needed on BXT
5914 * - set 19.2MHz bypass frequency if there are no active pipes
5915 */
5916 if (max_pixclk > 576000*9/10)
5917 return 624000;
5918 else if (max_pixclk > 384000*9/10)
5919 return 576000;
5920 else if (max_pixclk > 288000*9/10)
5921 return 384000;
5922 else if (max_pixclk > 144000*9/10)
5923 return 288000;
5924 else
5925 return 144000;
5926}
5927
a821fc46
ACO		 5928/* Compute the max pixel clock for new configuration. Uses atomic state if
5929 * that's non-NULL, look at current state otherwise. */
5930static int intel_mode_max_pixclk(struct drm_device *dev,
5931 struct drm_atomic_state *state)
30a970c6 5932{
30a970c6 5933 struct intel_crtc *intel_crtc;
304603f4 5934 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5935 int max_pixclk = 0;
5936
d3fcc808 5937 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5938 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5939 if (IS_ERR(crtc_state))
5940 return PTR_ERR(crtc_state);
5941
5942 if (!crtc_state->base.enable)
5943 continue;
5944
5945 max_pixclk = max(max_pixclk,
5946 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5947 }
5948
5949 return max_pixclk;
5950}
5951
27c329ed 5952static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5953{
27c329ed
ML		 5954 struct drm_device *dev = state->dev;
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5957
304603f4
ACO		 5958 if (max_pixclk < 0)
5959 return max_pixclk;
30a970c6 5960
27c329ed
ML		 5961 to_intel_atomic_state(state)->cdclk =
5962 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5963
27c329ed
ML		 5964 return 0;
5965}
304603f4 5966
27c329ed
ML		 5967static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5968{
5969 struct drm_device *dev = state->dev;
5970 struct drm_i915_private *dev_priv = dev->dev_private;
5971 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5972
27c329ed
ML		 5973 if (max_pixclk < 0)
5974 return max_pixclk;
85a96e7a 5975
27c329ed
ML		 5976 to_intel_atomic_state(state)->cdclk =
5977 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5978
27c329ed 5979 return 0;
30a970c6
JB		 5980}
5981
1e69cd74
VS		 5982static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5983{
5984 unsigned int credits, default_credits;
5985
5986 if (IS_CHERRYVIEW(dev_priv))
5987 default_credits = PFI_CREDIT(12);
5988 else
5989 default_credits = PFI_CREDIT(8);
5990
bfa7df01 5991 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
1e69cd74
VS		 5992 /* CHV suggested value is 31 or 63 */
5993 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5994 credits = PFI_CREDIT_63;
1e69cd74
VS		 5995 else
5996 credits = PFI_CREDIT(15);
5997 } else {
5998 credits = default_credits;
5999 }
6000
6001 /*
6002 * WA - write default credits before re-programming
6003 * FIXME: should we also set the resend bit here?
6004 */
6005 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6006 default_credits);
6007
6008 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6009 credits | PFI_CREDIT_RESEND);
6010
6011 /*
6012 * FIXME is this guaranteed to clear
6013 * immediately or should we poll for it?
6014 */
6015 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6016}
6017
27c329ed 6018static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 6019{
a821fc46 6020 struct drm_device *dev = old_state->dev;
27c329ed 6021 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 6022 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 6023
27c329ed
ML		 6024 /*
6025 * FIXME: We can end up here with all power domains off, yet
6026 * with a CDCLK frequency other than the minimum. To account
6027 * for this take the PIPE-A power domain, which covers the HW
6028 * blocks needed for the following programming. This can be
6029 * removed once it's guaranteed that we get here either with
6030 * the minimum CDCLK set, or the required power domains
6031 * enabled.
6032 */
6033 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6034
27c329ed
ML		 6035 if (IS_CHERRYVIEW(dev))
6036 cherryview_set_cdclk(dev, req_cdclk);
6037 else
6038 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6039
27c329ed 6040 vlv_program_pfi_credits(dev_priv);
1e69cd74 6041
27c329ed 6042 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6043}
6044
89b667f8
JB		 6045static void valleyview_crtc_enable(struct drm_crtc *crtc)
6046{
6047 struct drm_device *dev = crtc->dev;
a72e4c9f 6048 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6050 struct intel_encoder *encoder;
6051 int pipe = intel_crtc->pipe;
23538ef1 6052 bool is_dsi;
89b667f8 6053
53d9f4e9 6054 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6055 return;
6056
409ee761 6057 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6058
6e3c9717 6059 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6060 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6061
6062 intel_set_pipe_timings(intel_crtc);
6063
c14b0485
VS		 6064 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6065 struct drm_i915_private *dev_priv = dev->dev_private;
6066
6067 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6068 I915_WRITE(CHV_CANVAS(pipe), 0);
6069 }
6070
5b18e57c
DV		 6071 i9xx_set_pipeconf(intel_crtc);
6072
89b667f8 6073 intel_crtc->active = true;
89b667f8 6074
a72e4c9f 6075 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6076
89b667f8
JB		 6077 for_each_encoder_on_crtc(dev, crtc, encoder)
6078 if (encoder->pre_pll_enable)
6079 encoder->pre_pll_enable(encoder);
6080
9d556c99 6081 if (!is_dsi) {
c0b4c660
VS		 6082 if (IS_CHERRYVIEW(dev)) {
6083 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6084 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6085 } else {
6086 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6087 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6088 }
9d556c99 6089 }
89b667f8
JB		 6090
6091 for_each_encoder_on_crtc(dev, crtc, encoder)
6092 if (encoder->pre_enable)
6093 encoder->pre_enable(encoder);
6094
2dd24552
JB		 6095 i9xx_pfit_enable(intel_crtc);
6096
63cbb074
VS		 6097 intel_crtc_load_lut(crtc);
6098
e1fdc473 6099 intel_enable_pipe(intel_crtc);
be6a6f8e 6100
4b3a9526
VS		 6101 assert_vblank_disabled(crtc);
6102 drm_crtc_vblank_on(crtc);
6103
f9b61ff6
DV		 6104 for_each_encoder_on_crtc(dev, crtc, encoder)
6105 encoder->enable(encoder);
89b667f8
JB		 6106}
6107
f13c2ef3
DV		 6108static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6109{
6110 struct drm_device *dev = crtc->base.dev;
6111 struct drm_i915_private *dev_priv = dev->dev_private;
6112
6e3c9717
ACO		 6113 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6114 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6115}
6116
0b8765c6 6117static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6118{
6119 struct drm_device *dev = crtc->dev;
a72e4c9f 6120 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6122 struct intel_encoder *encoder;
79e53945 6123 int pipe = intel_crtc->pipe;
79e53945 6124
53d9f4e9 6125 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6126 return;
6127
f13c2ef3
DV		 6128 i9xx_set_pll_dividers(intel_crtc);
6129
6e3c9717 6130 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6131 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6132
6133 intel_set_pipe_timings(intel_crtc);
6134
5b18e57c
DV		 6135 i9xx_set_pipeconf(intel_crtc);
6136
f7abfe8b 6137 intel_crtc->active = true;
6b383a7f 6138
4a3436e8 6139 if (!IS_GEN2(dev))
a72e4c9f 6140 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6141
9d6d9f19
MK		 6142 for_each_encoder_on_crtc(dev, crtc, encoder)
6143 if (encoder->pre_enable)
6144 encoder->pre_enable(encoder);
6145
f6736a1a
DV		 6146 i9xx_enable_pll(intel_crtc);
6147
2dd24552
JB		 6148 i9xx_pfit_enable(intel_crtc);
6149
63cbb074
VS		 6150 intel_crtc_load_lut(crtc);
6151
f37fcc2a 6152 intel_update_watermarks(crtc);
e1fdc473 6153 intel_enable_pipe(intel_crtc);
be6a6f8e 6154
4b3a9526
VS		 6155 assert_vblank_disabled(crtc);
6156 drm_crtc_vblank_on(crtc);
6157
f9b61ff6
DV		 6158 for_each_encoder_on_crtc(dev, crtc, encoder)
6159 encoder->enable(encoder);
0b8765c6 6160}
79e53945 6161
87476d63
DV		 6162static void i9xx_pfit_disable(struct intel_crtc *crtc)
6163{
6164 struct drm_device *dev = crtc->base.dev;
6165 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6166
6e3c9717 6167 if (!crtc->config->gmch_pfit.control)
328d8e82 6168 return;
87476d63 6169
328d8e82 6170 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6171
328d8e82
DV		 6172 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6173 I915_READ(PFIT_CONTROL));
6174 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6175}
6176
0b8765c6
JB		 6177static void i9xx_crtc_disable(struct drm_crtc *crtc)
6178{
6179 struct drm_device *dev = crtc->dev;
6180 struct drm_i915_private *dev_priv = dev->dev_private;
6181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6182 struct intel_encoder *encoder;
0b8765c6 6183 int pipe = intel_crtc->pipe;
ef9c3aee 6184
6304cd91
VS		 6185 /*
6186 * On gen2 planes are double buffered but the pipe isn't, so we must
6187 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6188 * We also need to wait on all gmch platforms because of the
6189 * self-refresh mode constraint explained above.
6304cd91 6190 */
564ed191 6191 intel_wait_for_vblank(dev, pipe);
6304cd91 6192
4b3a9526
VS		 6193 for_each_encoder_on_crtc(dev, crtc, encoder)
6194 encoder->disable(encoder);
6195
f9b61ff6
DV		 6196 drm_crtc_vblank_off(crtc);
6197 assert_vblank_disabled(crtc);
6198
575f7ab7 6199 intel_disable_pipe(intel_crtc);
24a1f16d 6200
87476d63 6201 i9xx_pfit_disable(intel_crtc);
24a1f16d 6202
89b667f8
JB		 6203 for_each_encoder_on_crtc(dev, crtc, encoder)
6204 if (encoder->post_disable)
6205 encoder->post_disable(encoder);
6206
409ee761 6207 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6208 if (IS_CHERRYVIEW(dev))
6209 chv_disable_pll(dev_priv, pipe);
6210 else if (IS_VALLEYVIEW(dev))
6211 vlv_disable_pll(dev_priv, pipe);
6212 else
1c4e0274 6213 i9xx_disable_pll(intel_crtc);
076ed3b2 6214 }
0b8765c6 6215
d6db995f
VS		 6216 for_each_encoder_on_crtc(dev, crtc, encoder)
6217 if (encoder->post_pll_disable)
6218 encoder->post_pll_disable(encoder);
6219
4a3436e8 6220 if (!IS_GEN2(dev))
a72e4c9f 6221 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6222}
6223
b17d48e2
ML		 6224static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6225{
6226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6227 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6228 enum intel_display_power_domain domain;
6229 unsigned long domains;
6230
6231 if (!intel_crtc->active)
6232 return;
6233
a539205a 6234 if (to_intel_plane_state(crtc->primary->state)->visible) {
fc32b1fd
ML		 6235 WARN_ON(intel_crtc->unpin_work);
6236
a539205a
ML		 6237 intel_pre_disable_primary(crtc);
6238 }
6239
d032ffa0 6240 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6241 dev_priv->display.crtc_disable(crtc);
37d9078b
MR		 6242 intel_crtc->active = false;
6243 intel_update_watermarks(crtc);
1f7457b1 6244 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6245
6246 domains = intel_crtc->enabled_power_domains;
6247 for_each_power_domain(domain, domains)
6248 intel_display_power_put(dev_priv, domain);
6249 intel_crtc->enabled_power_domains = 0;
6250}
6251
6b72d486
ML		 6252/*
6253 * turn all crtc's off, but do not adjust state
6254 * This has to be paired with a call to intel_modeset_setup_hw_state.
6255 */
70e0bd74 6256int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6257{
70e0bd74
ML		 6258 struct drm_mode_config *config = &dev->mode_config;
6259 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6260 struct drm_atomic_state *state;
6b72d486 6261 struct drm_crtc *crtc;
70e0bd74
ML		 6262 unsigned crtc_mask = 0;
6263 int ret = 0;
6264
6265 if (WARN_ON(!ctx))
6266 return 0;
6267
6268 lockdep_assert_held(&ctx->ww_ctx);
6269 state = drm_atomic_state_alloc(dev);
6270 if (WARN_ON(!state))
6271 return -ENOMEM;
6272
6273 state->acquire_ctx = ctx;
6274 state->allow_modeset = true;
6275
6276 for_each_crtc(dev, crtc) {
6277 struct drm_crtc_state *crtc_state =
6278 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6279
70e0bd74
ML		 6280 ret = PTR_ERR_OR_ZERO(crtc_state);
6281 if (ret)
6282 goto free;
6283
6284 if (!crtc_state->active)
6285 continue;
6286
6287 crtc_state->active = false;
6288 crtc_mask |= 1 << drm_crtc_index(crtc);
6289 }
6290
6291 if (crtc_mask) {
74c090b1 6292 ret = drm_atomic_commit(state);
70e0bd74
ML		 6293
6294 if (!ret) {
6295 for_each_crtc(dev, crtc)
6296 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6297 crtc->state->active = true;
6298
6299 return ret;
6300 }
6301 }
6302
6303free:
6304 if (ret)
6305 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6306 drm_atomic_state_free(state);
6307 return ret;
ee7b9f93
JB		 6308}
6309
ea5b213a 6310void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6311{
4ef69c7a 6312 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6313
ea5b213a
CW		 6314 drm_encoder_cleanup(encoder);
6315 kfree(intel_encoder);
7e7d76c3
JB		 6316}
6317
0a91ca29
DV		 6318/* Cross check the actual hw state with our own modeset state tracking (and it's
6319 * internal consistency). */
b980514c 6320static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6321{
35dd3c64
ML		 6322 struct drm_crtc *crtc = connector->base.state->crtc;
6323
6324 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6325 connector->base.base.id,
6326 connector->base.name);
6327
0a91ca29 6328 if (connector->get_hw_state(connector)) {
e85376cb 6329 struct intel_encoder *encoder = connector->encoder;
35dd3c64 6330 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6331
35dd3c64
ML		 6332 I915_STATE_WARN(!crtc,
6333 "connector enabled without attached crtc\n");
0a91ca29 6334
35dd3c64
ML		 6335 if (!crtc)
6336 return;
6337
6338 I915_STATE_WARN(!crtc->state->active,
6339 "connector is active, but attached crtc isn't\n");
6340
e85376cb 6341 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
35dd3c64
ML		 6342 return;
6343
e85376cb 6344 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
35dd3c64
ML		 6345 "atomic encoder doesn't match attached encoder\n");
6346
e85376cb 6347 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
35dd3c64
ML		 6348 "attached encoder crtc differs from connector crtc\n");
6349 } else {
4d688a2a
ML		 6350 I915_STATE_WARN(crtc && crtc->state->active,
6351 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6352 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6353 "best encoder set without crtc!\n");
0a91ca29 6354 }
79e53945
JB		 6355}
6356
08d9bc92
ACO		 6357int intel_connector_init(struct intel_connector *connector)
6358{
6359 struct drm_connector_state *connector_state;
6360
6361 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6362 if (!connector_state)
6363 return -ENOMEM;
6364
6365 connector->base.state = connector_state;
6366 return 0;
6367}
6368
6369struct intel_connector *intel_connector_alloc(void)
6370{
6371 struct intel_connector *connector;
6372
6373 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6374 if (!connector)
6375 return NULL;
6376
6377 if (intel_connector_init(connector) < 0) {
6378 kfree(connector);
6379 return NULL;
6380 }
6381
6382 return connector;
6383}
6384
f0947c37
DV		 6385/* Simple connector->get_hw_state implementation for encoders that support only
6386 * one connector and no cloning and hence the encoder state determines the state
6387 * of the connector. */
6388bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6389{
24929352 6390 enum pipe pipe = 0;
f0947c37 6391 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6392
f0947c37 6393 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6394}
6395
6d293983 6396static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6397{
6d293983
ACO		 6398 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6399 return crtc_state->fdi_lanes;
d272ddfa
VS		 6400
6401 return 0;
6402}
6403
6d293983 6404static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6405 struct intel_crtc_state *pipe_config)
1857e1da 6406{
6d293983
ACO		 6407 struct drm_atomic_state *state = pipe_config->base.state;
6408 struct intel_crtc *other_crtc;
6409 struct intel_crtc_state *other_crtc_state;
6410
1857e1da
DV		 6411 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6412 pipe_name(pipe), pipe_config->fdi_lanes);
6413 if (pipe_config->fdi_lanes > 4) {
6414 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6415 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6416 return -EINVAL;
1857e1da
DV		 6417 }
6418
bafb6553 6419 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6420 if (pipe_config->fdi_lanes > 2) {
6421 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6422 pipe_config->fdi_lanes);
6d293983 6423 return -EINVAL;
1857e1da 6424 } else {
6d293983 6425 return 0;
1857e1da
DV		 6426 }
6427 }
6428
6429 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6430 return 0;
1857e1da
DV		 6431
6432 /* Ivybridge 3 pipe is really complicated */
6433 switch (pipe) {
6434 case PIPE_A:
6d293983 6435 return 0;
1857e1da 6436 case PIPE_B:
6d293983
ACO		 6437 if (pipe_config->fdi_lanes <= 2)
6438 return 0;
6439
6440 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6441 other_crtc_state =
6442 intel_atomic_get_crtc_state(state, other_crtc);
6443 if (IS_ERR(other_crtc_state))
6444 return PTR_ERR(other_crtc_state);
6445
6446 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6447 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6448 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6449 return -EINVAL;
1857e1da 6450 }
6d293983 6451 return 0;
1857e1da 6452 case PIPE_C:
251cc67c
VS		 6453 if (pipe_config->fdi_lanes > 2) {
6454 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6455 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6456 return -EINVAL;
251cc67c 6457 }
6d293983
ACO		 6458
6459 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6460 other_crtc_state =
6461 intel_atomic_get_crtc_state(state, other_crtc);
6462 if (IS_ERR(other_crtc_state))
6463 return PTR_ERR(other_crtc_state);
6464
6465 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6466 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6467 return -EINVAL;
1857e1da 6468 }
6d293983 6469 return 0;
1857e1da
DV		 6470 default:
6471 BUG();
6472 }
6473}
6474
e29c22c0
DV		 6475#define RETRY 1
6476static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6477 struct intel_crtc_state *pipe_config)
877d48d5 6478{
1857e1da 6479 struct drm_device *dev = intel_crtc->base.dev;
7c5f93b0 6480 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6481 int lane, link_bw, fdi_dotclock, ret;
6482 bool needs_recompute = false;
877d48d5 6483
e29c22c0 6484retry:
877d48d5
DV		 6485 /* FDI is a binary signal running at ~2.7GHz, encoding
6486 * each output octet as 10 bits. The actual frequency
6487 * is stored as a divider into a 100MHz clock, and the
6488 * mode pixel clock is stored in units of 1KHz.
6489 * Hence the bw of each lane in terms of the mode signal
6490 * is:
6491 */
6492 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6493
241bfc38 6494 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6495
2bd89a07 6496 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6497 pipe_config->pipe_bpp);
6498
6499 pipe_config->fdi_lanes = lane;
6500
2bd89a07 6501 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6502 link_bw, &pipe_config->fdi_m_n);
1857e1da 6503
6d293983
ACO		 6504 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6505 intel_crtc->pipe, pipe_config);
6506 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6507 pipe_config->pipe_bpp -= 2*3;
6508 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6509 pipe_config->pipe_bpp);
6510 needs_recompute = true;
6511 pipe_config->bw_constrained = true;
6512
6513 goto retry;
6514 }
6515
6516 if (needs_recompute)
6517 return RETRY;
6518
6d293983 6519 return ret;
877d48d5
DV		 6520}
6521
8cfb3407
VS		 6522static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6523 struct intel_crtc_state *pipe_config)
6524{
6525 if (pipe_config->pipe_bpp > 24)
6526 return false;
6527
6528 /* HSW can handle pixel rate up to cdclk? */
6529 if (IS_HASWELL(dev_priv->dev))
6530 return true;
6531
6532 /*
b432e5cf
VS		 6533 * We compare against max which means we must take
6534 * the increased cdclk requirement into account when
6535 * calculating the new cdclk.
6536 *
6537 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6538 */
6539 return ilk_pipe_pixel_rate(pipe_config) <=
6540 dev_priv->max_cdclk_freq * 95 / 100;
6541}
6542
42db64ef 6543static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6544 struct intel_crtc_state *pipe_config)
42db64ef 6545{
8cfb3407
VS		 6546 struct drm_device *dev = crtc->base.dev;
6547 struct drm_i915_private *dev_priv = dev->dev_private;
6548
d330a953 6549 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6550 hsw_crtc_supports_ips(crtc) &&
6551 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6552}
6553
39acb4aa
VS		 6554static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6555{
6556 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6557
6558 /* GDG double wide on either pipe, otherwise pipe A only */
6559 return INTEL_INFO(dev_priv)->gen < 4 &&
6560 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6561}
6562
a43f6e0f 6563static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6564 struct intel_crtc_state *pipe_config)
79e53945 6565{
a43f6e0f 6566 struct drm_device *dev = crtc->base.dev;
8bd31e67 6567 struct drm_i915_private *dev_priv = dev->dev_private;
7c5f93b0 6568 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6569
ad3a4479 6570 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6571 if (INTEL_INFO(dev)->gen < 4) {
39acb4aa 6572 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
cf532bb2
VS		 6573
6574 /*
39acb4aa 6575 * Enable double wide mode when the dot clock
cf532bb2 6576 * is > 90% of the (display) core speed.
cf532bb2 6577 */
39acb4aa
VS		 6578 if (intel_crtc_supports_double_wide(crtc) &&
6579 adjusted_mode->crtc_clock > clock_limit) {
ad3a4479 6580 clock_limit *= 2;
cf532bb2 6581 pipe_config->double_wide = true;
ad3a4479
VS		 6582 }
6583
39acb4aa
VS		 6584 if (adjusted_mode->crtc_clock > clock_limit) {
6585 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6586 adjusted_mode->crtc_clock, clock_limit,
6587 yesno(pipe_config->double_wide));
e29c22c0 6588 return -EINVAL;
39acb4aa 6589 }
2c07245f 6590 }
89749350 6591
1d1d0e27
VS		 6592 /*
6593 * Pipe horizontal size must be even in:
6594 * - DVO ganged mode
6595 * - LVDS dual channel mode
6596 * - Double wide pipe
6597 */
a93e255f 6598 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6599 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6600 pipe_config->pipe_src_w &= ~1;
6601
8693a824
DL		 6602 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6603 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6604 */
6605 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
aad941d5 6606 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
e29c22c0 6607 return -EINVAL;
44f46b42 6608
f5adf94e 6609 if (HAS_IPS(dev))
a43f6e0f
DV		 6610 hsw_compute_ips_config(crtc, pipe_config);
6611
877d48d5 6612 if (pipe_config->has_pch_encoder)
a43f6e0f 6613 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6614
cf5a15be 6615 return 0;
79e53945
JB		 6616}
6617
1652d19e
VS		 6618static int skylake_get_display_clock_speed(struct drm_device *dev)
6619{
6620 struct drm_i915_private *dev_priv = to_i915(dev);
6621 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6622 uint32_t cdctl = I915_READ(CDCLK_CTL);
6623 uint32_t linkrate;
6624
414355a7 6625 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6626 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6627
6628 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6629 return 540000;
6630
6631 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6632 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6633
71cd8423
DL		 6634 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6635 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6636 /* vco 8640 */
6637 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6638 case CDCLK_FREQ_450_432:
6639 return 432000;
6640 case CDCLK_FREQ_337_308:
6641 return 308570;
6642 case CDCLK_FREQ_675_617:
6643 return 617140;
6644 default:
6645 WARN(1, "Unknown cd freq selection\n");
6646 }
6647 } else {
6648 /* vco 8100 */
6649 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6650 case CDCLK_FREQ_450_432:
6651 return 450000;
6652 case CDCLK_FREQ_337_308:
6653 return 337500;
6654 case CDCLK_FREQ_675_617:
6655 return 675000;
6656 default:
6657 WARN(1, "Unknown cd freq selection\n");
6658 }
6659 }
6660
6661 /* error case, do as if DPLL0 isn't enabled */
6662 return 24000;
6663}
6664
acd3f3d3
BP		 6665static int broxton_get_display_clock_speed(struct drm_device *dev)
6666{
6667 struct drm_i915_private *dev_priv = to_i915(dev);
6668 uint32_t cdctl = I915_READ(CDCLK_CTL);
6669 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6670 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6671 int cdclk;
6672
6673 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6674 return 19200;
6675
6676 cdclk = 19200 * pll_ratio / 2;
6677
6678 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6679 case BXT_CDCLK_CD2X_DIV_SEL_1:
6680 return cdclk; /* 576MHz or 624MHz */
6681 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6682 return cdclk * 2 / 3; /* 384MHz */
6683 case BXT_CDCLK_CD2X_DIV_SEL_2:
6684 return cdclk / 2; /* 288MHz */
6685 case BXT_CDCLK_CD2X_DIV_SEL_4:
6686 return cdclk / 4; /* 144MHz */
6687 }
6688
6689 /* error case, do as if DE PLL isn't enabled */
6690 return 19200;
6691}
6692
1652d19e
VS		 6693static int broadwell_get_display_clock_speed(struct drm_device *dev)
6694{
6695 struct drm_i915_private *dev_priv = dev->dev_private;
6696 uint32_t lcpll = I915_READ(LCPLL_CTL);
6697 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6698
6699 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6700 return 800000;
6701 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6702 return 450000;
6703 else if (freq == LCPLL_CLK_FREQ_450)
6704 return 450000;
6705 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6706 return 540000;
6707 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6708 return 337500;
6709 else
6710 return 675000;
6711}
6712
6713static int haswell_get_display_clock_speed(struct drm_device *dev)
6714{
6715 struct drm_i915_private *dev_priv = dev->dev_private;
6716 uint32_t lcpll = I915_READ(LCPLL_CTL);
6717 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6718
6719 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6720 return 800000;
6721 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6722 return 450000;
6723 else if (freq == LCPLL_CLK_FREQ_450)
6724 return 450000;
6725 else if (IS_HSW_ULT(dev))
6726 return 337500;
6727 else
6728 return 540000;
79e53945
JB		 6729}
6730
25eb05fc
JB		 6731static int valleyview_get_display_clock_speed(struct drm_device *dev)
6732{
bfa7df01
VS		 6733 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6734 CCK_DISPLAY_CLOCK_CONTROL);
25eb05fc
JB		 6735}
6736
b37a6434
VS		 6737static int ilk_get_display_clock_speed(struct drm_device *dev)
6738{
6739 return 450000;
6740}
6741
e70236a8
JB		 6742static int i945_get_display_clock_speed(struct drm_device *dev)
6743{
6744 return 400000;
6745}
79e53945 6746
e70236a8 6747static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6748{
e907f170 6749 return 333333;
e70236a8 6750}
79e53945 6751
e70236a8
JB		 6752static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6753{
6754 return 200000;
6755}
79e53945 6756
257a7ffc
DV		 6757static int pnv_get_display_clock_speed(struct drm_device *dev)
6758{
6759 u16 gcfgc = 0;
6760
6761 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6762
6763 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6764 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6765 return 266667;
257a7ffc 6766 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6767 return 333333;
257a7ffc 6768 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6769 return 444444;
257a7ffc
DV		 6770 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6771 return 200000;
6772 default:
6773 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6774 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6775 return 133333;
257a7ffc 6776 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6777 return 166667;
257a7ffc
DV		 6778 }
6779}
6780
e70236a8
JB		 6781static int i915gm_get_display_clock_speed(struct drm_device *dev)
6782{
6783 u16 gcfgc = 0;
79e53945 6784
e70236a8
JB		 6785 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6786
6787 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6788 return 133333;
e70236a8
JB		 6789 else {
6790 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6791 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6792 return 333333;
e70236a8
JB		 6793 default:
6794 case GC_DISPLAY_CLOCK_190_200_MHZ:
6795 return 190000;
79e53945 6796 }
e70236a8
JB		 6797 }
6798}
6799
6800static int i865_get_display_clock_speed(struct drm_device *dev)
6801{
e907f170 6802 return 266667;
e70236a8
JB		 6803}
6804
1b1d2716 6805static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6806{
6807 u16 hpllcc = 0;
1b1d2716 6808
65cd2b3f
VS		 6809 /*
6810 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6811 * encoding is different :(
6812 * FIXME is this the right way to detect 852GM/852GMV?
6813 */
6814 if (dev->pdev->revision == 0x1)
6815 return 133333;
6816
1b1d2716
VS		 6817 pci_bus_read_config_word(dev->pdev->bus,
6818 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6819
e70236a8
JB		 6820 /* Assume that the hardware is in the high speed state. This
6821 * should be the default.
6822 */
6823 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6824 case GC_CLOCK_133_200:
1b1d2716 6825 case GC_CLOCK_133_200_2:
e70236a8
JB		 6826 case GC_CLOCK_100_200:
6827 return 200000;
6828 case GC_CLOCK_166_250:
6829 return 250000;
6830 case GC_CLOCK_100_133:
e907f170 6831 return 133333;
1b1d2716
VS		 6832 case GC_CLOCK_133_266:
6833 case GC_CLOCK_133_266_2:
6834 case GC_CLOCK_166_266:
6835 return 266667;
e70236a8 6836 }
79e53945 6837
e70236a8
JB		 6838 /* Shouldn't happen */
6839 return 0;
6840}
79e53945 6841
e70236a8
JB		 6842static int i830_get_display_clock_speed(struct drm_device *dev)
6843{
e907f170 6844 return 133333;
79e53945
JB		 6845}
6846
34edce2f
VS		 6847static unsigned int intel_hpll_vco(struct drm_device *dev)
6848{
6849 struct drm_i915_private *dev_priv = dev->dev_private;
6850 static const unsigned int blb_vco[8] = {
6851 [0] = 3200000,
6852 [1] = 4000000,
6853 [2] = 5333333,
6854 [3] = 4800000,
6855 [4] = 6400000,
6856 };
6857 static const unsigned int pnv_vco[8] = {
6858 [0] = 3200000,
6859 [1] = 4000000,
6860 [2] = 5333333,
6861 [3] = 4800000,
6862 [4] = 2666667,
6863 };
6864 static const unsigned int cl_vco[8] = {
6865 [0] = 3200000,
6866 [1] = 4000000,
6867 [2] = 5333333,
6868 [3] = 6400000,
6869 [4] = 3333333,
6870 [5] = 3566667,
6871 [6] = 4266667,
6872 };
6873 static const unsigned int elk_vco[8] = {
6874 [0] = 3200000,
6875 [1] = 4000000,
6876 [2] = 5333333,
6877 [3] = 4800000,
6878 };
6879 static const unsigned int ctg_vco[8] = {
6880 [0] = 3200000,
6881 [1] = 4000000,
6882 [2] = 5333333,
6883 [3] = 6400000,
6884 [4] = 2666667,
6885 [5] = 4266667,
6886 };
6887 const unsigned int *vco_table;
6888 unsigned int vco;
6889 uint8_t tmp = 0;
6890
6891 /* FIXME other chipsets? */
6892 if (IS_GM45(dev))
6893 vco_table = ctg_vco;
6894 else if (IS_G4X(dev))
6895 vco_table = elk_vco;
6896 else if (IS_CRESTLINE(dev))
6897 vco_table = cl_vco;
6898 else if (IS_PINEVIEW(dev))
6899 vco_table = pnv_vco;
6900 else if (IS_G33(dev))
6901 vco_table = blb_vco;
6902 else
6903 return 0;
6904
6905 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6906
6907 vco = vco_table[tmp & 0x7];
6908 if (vco == 0)
6909 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6910 else
6911 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6912
6913 return vco;
6914}
6915
6916static int gm45_get_display_clock_speed(struct drm_device *dev)
6917{
6918 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6919 uint16_t tmp = 0;
6920
6921 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6922
6923 cdclk_sel = (tmp >> 12) & 0x1;
6924
6925 switch (vco) {
6926 case 2666667:
6927 case 4000000:
6928 case 5333333:
6929 return cdclk_sel ? 333333 : 222222;
6930 case 3200000:
6931 return cdclk_sel ? 320000 : 228571;
6932 default:
6933 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6934 return 222222;
6935 }
6936}
6937
6938static int i965gm_get_display_clock_speed(struct drm_device *dev)
6939{
6940 static const uint8_t div_3200[] = { 16, 10, 8 };
6941 static const uint8_t div_4000[] = { 20, 12, 10 };
6942 static const uint8_t div_5333[] = { 24, 16, 14 };
6943 const uint8_t *div_table;
6944 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6945 uint16_t tmp = 0;
6946
6947 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6948
6949 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6950
6951 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6952 goto fail;
6953
6954 switch (vco) {
6955 case 3200000:
6956 div_table = div_3200;
6957 break;
6958 case 4000000:
6959 div_table = div_4000;
6960 break;
6961 case 5333333:
6962 div_table = div_5333;
6963 break;
6964 default:
6965 goto fail;
6966 }
6967
6968 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6969
caf4e252 6970fail:
34edce2f
VS		 6971 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6972 return 200000;
6973}
6974
6975static int g33_get_display_clock_speed(struct drm_device *dev)
6976{
6977 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6978 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6979 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6980 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6981 const uint8_t *div_table;
6982 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6983 uint16_t tmp = 0;
6984
6985 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6986
6987 cdclk_sel = (tmp >> 4) & 0x7;
6988
6989 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6990 goto fail;
6991
6992 switch (vco) {
6993 case 3200000:
6994 div_table = div_3200;
6995 break;
6996 case 4000000:
6997 div_table = div_4000;
6998 break;
6999 case 4800000:
7000 div_table = div_4800;
7001 break;
7002 case 5333333:
7003 div_table = div_5333;
7004 break;
7005 default:
7006 goto fail;
7007 }
7008
7009 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7010
caf4e252 7011fail:
34edce2f
VS		 7012 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7013 return 190476;
7014}
7015
2c07245f 7016static void
a65851af 7017intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7018{
a65851af
VS		 7019 while (*num > DATA_LINK_M_N_MASK ||
7020 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7021 *num >>= 1;
7022 *den >>= 1;
7023 }
7024}
7025
a65851af
VS		 7026static void compute_m_n(unsigned int m, unsigned int n,
7027 uint32_t *ret_m, uint32_t *ret_n)
7028{
7029 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7030 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7031 intel_reduce_m_n_ratio(ret_m, ret_n);
7032}
7033
e69d0bc1
DV		 7034void
7035intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7036 int pixel_clock, int link_clock,
7037 struct intel_link_m_n *m_n)
2c07245f 7038{
e69d0bc1 7039 m_n->tu = 64;
a65851af
VS		 7040
7041 compute_m_n(bits_per_pixel * pixel_clock,
7042 link_clock * nlanes * 8,
7043 &m_n->gmch_m, &m_n->gmch_n);
7044
7045 compute_m_n(pixel_clock, link_clock,
7046 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7047}
7048
a7615030
CW		 7049static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7050{
d330a953
JN		 7051 if (i915.panel_use_ssc >= 0)
7052 return i915.panel_use_ssc != 0;
41aa3448 7053 return dev_priv->vbt.lvds_use_ssc
435793df 7054 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7055}
7056
a93e255f
ACO		 7057static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7058 int num_connectors)
c65d77d8 7059{
a93e255f 7060 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7061 struct drm_i915_private *dev_priv = dev->dev_private;
7062 int refclk;
7063
a93e255f
ACO		 7064 WARN_ON(!crtc_state->base.state);
7065
5ab7b0b7 7066 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7067 refclk = 100000;
a93e255f 7068 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7069 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7070 refclk = dev_priv->vbt.lvds_ssc_freq;
7071 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7072 } else if (!IS_GEN2(dev)) {
7073 refclk = 96000;
7074 } else {
7075 refclk = 48000;
7076 }
7077
7078 return refclk;
7079}
7080
7429e9d4 7081static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7082{
7df00d7a 7083 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7084}
f47709a9 7085
7429e9d4
DV		 7086static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7087{
7088 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7089}
7090
f47709a9 7091static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7092 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7093 intel_clock_t *reduced_clock)
7094{
f47709a9 7095 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7096 u32 fp, fp2 = 0;
7097
7098 if (IS_PINEVIEW(dev)) {
190f68c5 7099 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7100 if (reduced_clock)
7429e9d4 7101 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7102 } else {
190f68c5 7103 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7104 if (reduced_clock)
7429e9d4 7105 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7106 }
7107
190f68c5 7108 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7109
f47709a9 7110 crtc->lowfreq_avail = false;
a93e255f 7111 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7112 reduced_clock) {
190f68c5 7113 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7114 crtc->lowfreq_avail = true;
a7516a05 7115 } else {
190f68c5 7116 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7117 }
7118}
7119
5e69f97f
CML		 7120static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7121 pipe)
89b667f8
JB		 7122{
7123 u32 reg_val;
7124
7125 /*
7126 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7127 * and set it to a reasonable value instead.
7128 */
ab3c759a 7129 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7130 reg_val &= 0xffffff00;
7131 reg_val |= 0x00000030;
ab3c759a 7132 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7133
ab3c759a 7134 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7135 reg_val &= 0x8cffffff;
7136 reg_val = 0x8c000000;
ab3c759a 7137 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7138
ab3c759a 7139 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7140 reg_val &= 0xffffff00;
ab3c759a 7141 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7142
ab3c759a 7143 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7144 reg_val &= 0x00ffffff;
7145 reg_val |= 0xb0000000;
ab3c759a 7146 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7147}
7148
b551842d
DV		 7149static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7150 struct intel_link_m_n *m_n)
7151{
7152 struct drm_device *dev = crtc->base.dev;
7153 struct drm_i915_private *dev_priv = dev->dev_private;
7154 int pipe = crtc->pipe;
7155
e3b95f1e
DV		 7156 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7157 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7158 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7159 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7160}
7161
7162static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7163 struct intel_link_m_n *m_n,
7164 struct intel_link_m_n *m2_n2)
b551842d
DV		 7165{
7166 struct drm_device *dev = crtc->base.dev;
7167 struct drm_i915_private *dev_priv = dev->dev_private;
7168 int pipe = crtc->pipe;
6e3c9717 7169 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7170
7171 if (INTEL_INFO(dev)->gen >= 5) {
7172 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7173 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7174 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7175 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7176 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7177 * for gen < 8) and if DRRS is supported (to make sure the
7178 * registers are not unnecessarily accessed).
7179 */
44395bfe 7180 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7181 crtc->config->has_drrs) {
f769cd24
VK		 7182 I915_WRITE(PIPE_DATA_M2(transcoder),
7183 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7184 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7185 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7186 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7187 }
b551842d 7188 } else {
e3b95f1e
DV		 7189 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7190 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7191 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7192 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7193 }
7194}
7195
fe3cd48d 7196void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7197{
fe3cd48d
R		 7198 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7199
7200 if (m_n == M1_N1) {
7201 dp_m_n = &crtc->config->dp_m_n;
7202 dp_m2_n2 = &crtc->config->dp_m2_n2;
7203 } else if (m_n == M2_N2) {
7204
7205 /*
7206 * M2_N2 registers are not supported. Hence m2_n2 divider value
7207 * needs to be programmed into M1_N1.
7208 */
7209 dp_m_n = &crtc->config->dp_m2_n2;
7210 } else {
7211 DRM_ERROR("Unsupported divider value\n");
7212 return;
7213 }
7214
6e3c9717
ACO		 7215 if (crtc->config->has_pch_encoder)
7216 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7217 else
fe3cd48d 7218 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7219}
7220
251ac862
DV		 7221static void vlv_compute_dpll(struct intel_crtc *crtc,
7222 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7223{
7224 u32 dpll, dpll_md;
7225
7226 /*
7227 * Enable DPIO clock input. We should never disable the reference
7228 * clock for pipe B, since VGA hotplug / manual detection depends
7229 * on it.
7230 */
60bfe44f
VS		 7231 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7232 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7233 /* We should never disable this, set it here for state tracking */
7234 if (crtc->pipe == PIPE_B)
7235 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7236 dpll |= DPLL_VCO_ENABLE;
d288f65f 7237 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7238
d288f65f 7239 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7240 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7241 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7242}
7243
d288f65f 7244static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7245 const struct intel_crtc_state *pipe_config)
a0c4da24 7246{
f47709a9 7247 struct drm_device *dev = crtc->base.dev;
a0c4da24 7248 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7249 int pipe = crtc->pipe;
bdd4b6a6 7250 u32 mdiv;
a0c4da24 7251 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7252 u32 coreclk, reg_val;
a0c4da24 7253
a580516d 7254 mutex_lock(&dev_priv->sb_lock);
09153000 7255
d288f65f
VS		 7256 bestn = pipe_config->dpll.n;
7257 bestm1 = pipe_config->dpll.m1;
7258 bestm2 = pipe_config->dpll.m2;
7259 bestp1 = pipe_config->dpll.p1;
7260 bestp2 = pipe_config->dpll.p2;
a0c4da24 7261
89b667f8
JB		 7262 /* See eDP HDMI DPIO driver vbios notes doc */
7263
7264 /* PLL B needs special handling */
bdd4b6a6 7265 if (pipe == PIPE_B)
5e69f97f 7266 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7267
7268 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7269 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7270
7271 /* Disable target IRef on PLL */
ab3c759a 7272 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7273 reg_val &= 0x00ffffff;
ab3c759a 7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7275
7276 /* Disable fast lock */
ab3c759a 7277 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7278
7279 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7280 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7281 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7282 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7283 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7284
7285 /*
7286 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7287 * but we don't support that).
7288 * Note: don't use the DAC post divider as it seems unstable.
7289 */
7290 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7291 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7292
a0c4da24 7293 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7295
89b667f8 7296 /* Set HBR and RBR LPF coefficients */
d288f65f 7297 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7298 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7299 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7300 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7301 0x009f0003);
89b667f8 7302 else
ab3c759a 7303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7304 0x00d0000f);
7305
681a8504 7306 if (pipe_config->has_dp_encoder) {
89b667f8 7307 /* Use SSC source */
bdd4b6a6 7308 if (pipe == PIPE_A)
ab3c759a 7309 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7310 0x0df40000);
7311 else
ab3c759a 7312 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7313 0x0df70000);
7314 } else { /* HDMI or VGA */
7315 /* Use bend source */
bdd4b6a6 7316 if (pipe == PIPE_A)
ab3c759a 7317 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7318 0x0df70000);
7319 else
ab3c759a 7320 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7321 0x0df40000);
7322 }
a0c4da24 7323
ab3c759a 7324 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7325 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7326 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7327 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7328 coreclk |= 0x01000000;
ab3c759a 7329 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7330
ab3c759a 7331 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7332 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7333}
7334
251ac862
DV		 7335static void chv_compute_dpll(struct intel_crtc *crtc,
7336 struct intel_crtc_state *pipe_config)
1ae0d137 7337{
60bfe44f
VS		 7338 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7339 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7340 DPLL_VCO_ENABLE;
7341 if (crtc->pipe != PIPE_A)
d288f65f 7342 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7343
d288f65f
VS		 7344 pipe_config->dpll_hw_state.dpll_md =
7345 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7346}
7347
d288f65f 7348static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7349 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7350{
7351 struct drm_device *dev = crtc->base.dev;
7352 struct drm_i915_private *dev_priv = dev->dev_private;
7353 int pipe = crtc->pipe;
7354 int dpll_reg = DPLL(crtc->pipe);
7355 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7356 u32 loopfilter, tribuf_calcntr;
9d556c99 7357 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7358 u32 dpio_val;
9cbe40c1 7359 int vco;
9d556c99 7360
d288f65f
VS		 7361 bestn = pipe_config->dpll.n;
7362 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7363 bestm1 = pipe_config->dpll.m1;
7364 bestm2 = pipe_config->dpll.m2 >> 22;
7365 bestp1 = pipe_config->dpll.p1;
7366 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7367 vco = pipe_config->dpll.vco;
a945ce7e 7368 dpio_val = 0;
9cbe40c1 7369 loopfilter = 0;
9d556c99
CML		 7370
7371 /*
7372 * Enable Refclk and SSC
7373 */
a11b0703 7374 I915_WRITE(dpll_reg,
d288f65f 7375 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7376
a580516d 7377 mutex_lock(&dev_priv->sb_lock);
9d556c99 7378
9d556c99
CML		 7379 /* p1 and p2 divider */
7380 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7381 5 << DPIO_CHV_S1_DIV_SHIFT |
7382 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7383 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7384 1 << DPIO_CHV_K_DIV_SHIFT);
7385
7386 /* Feedback post-divider - m2 */
7387 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7388
7389 /* Feedback refclk divider - n and m1 */
7390 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7391 DPIO_CHV_M1_DIV_BY_2 |
7392 1 << DPIO_CHV_N_DIV_SHIFT);
7393
7394 /* M2 fraction division */
25a25dfc 7395 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7396
7397 /* M2 fraction division enable */
a945ce7e
VP		 7398 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7399 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7400 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7401 if (bestm2_frac)
7402 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7403 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7404
de3a0fde
VP		 7405 /* Program digital lock detect threshold */
7406 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7407 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7408 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7409 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7410 if (!bestm2_frac)
7411 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7412 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7413
9d556c99 7414 /* Loop filter */
9cbe40c1
VP		 7415 if (vco == 5400000) {
7416 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7417 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7418 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7419 tribuf_calcntr = 0x9;
7420 } else if (vco <= 6200000) {
7421 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7422 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7423 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7424 tribuf_calcntr = 0x9;
7425 } else if (vco <= 6480000) {
7426 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7427 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7428 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7429 tribuf_calcntr = 0x8;
7430 } else {
7431 /* Not supported. Apply the same limits as in the max case */
7432 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7433 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7434 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7435 tribuf_calcntr = 0;
7436 }
9d556c99
CML		 7437 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7438
968040b2 7439 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7440 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7441 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7442 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7443
9d556c99
CML		 7444 /* AFC Recal */
7445 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7446 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7447 DPIO_AFC_RECAL);
7448
a580516d 7449 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7450}
7451
d288f65f
VS		 7452/**
7453 * vlv_force_pll_on - forcibly enable just the PLL
7454 * @dev_priv: i915 private structure
7455 * @pipe: pipe PLL to enable
7456 * @dpll: PLL configuration
7457 *
7458 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7459 * in cases where we need the PLL enabled even when @pipe is not going to
7460 * be enabled.
7461 */
7462void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7463 const struct dpll *dpll)
7464{
7465 struct intel_crtc *crtc =
7466 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7467 struct intel_crtc_state pipe_config = {
a93e255f 7468 .base.crtc = &crtc->base,
d288f65f
VS		 7469 .pixel_multiplier = 1,
7470 .dpll = *dpll,
7471 };
7472
7473 if (IS_CHERRYVIEW(dev)) {
251ac862 7474 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7475 chv_prepare_pll(crtc, &pipe_config);
7476 chv_enable_pll(crtc, &pipe_config);
7477 } else {
251ac862 7478 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7479 vlv_prepare_pll(crtc, &pipe_config);
7480 vlv_enable_pll(crtc, &pipe_config);
7481 }
7482}
7483
7484/**
7485 * vlv_force_pll_off - forcibly disable just the PLL
7486 * @dev_priv: i915 private structure
7487 * @pipe: pipe PLL to disable
7488 *
7489 * Disable the PLL for @pipe. To be used in cases where we need
7490 * the PLL enabled even when @pipe is not going to be enabled.
7491 */
7492void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7493{
7494 if (IS_CHERRYVIEW(dev))
7495 chv_disable_pll(to_i915(dev), pipe);
7496 else
7497 vlv_disable_pll(to_i915(dev), pipe);
7498}
7499
251ac862
DV		 7500static void i9xx_compute_dpll(struct intel_crtc *crtc,
7501 struct intel_crtc_state *crtc_state,
7502 intel_clock_t *reduced_clock,
7503 int num_connectors)
eb1cbe48 7504{
f47709a9 7505 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7506 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7507 u32 dpll;
7508 bool is_sdvo;
190f68c5 7509 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7510
190f68c5 7511 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7512
a93e255f
ACO		 7513 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7514 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7515
7516 dpll = DPLL_VGA_MODE_DIS;
7517
a93e255f 7518 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7519 dpll |= DPLLB_MODE_LVDS;
7520 else
7521 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7522
ef1b460d 7523 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7524 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7525 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7526 }
198a037f
DV		 7527
7528 if (is_sdvo)
4a33e48d 7529 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7530
190f68c5 7531 if (crtc_state->has_dp_encoder)
4a33e48d 7532 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7533
7534 /* compute bitmask from p1 value */
7535 if (IS_PINEVIEW(dev))
7536 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7537 else {
7538 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7539 if (IS_G4X(dev) && reduced_clock)
7540 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7541 }
7542 switch (clock->p2) {
7543 case 5:
7544 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7545 break;
7546 case 7:
7547 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7548 break;
7549 case 10:
7550 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7551 break;
7552 case 14:
7553 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7554 break;
7555 }
7556 if (INTEL_INFO(dev)->gen >= 4)
7557 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7558
190f68c5 7559 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7560 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7561 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7562 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7563 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7564 else
7565 dpll |= PLL_REF_INPUT_DREFCLK;
7566
7567 dpll |= DPLL_VCO_ENABLE;
190f68c5 7568 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7569
eb1cbe48 7570 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7571 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7572 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7573 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7574 }
7575}
7576
251ac862
DV		 7577static void i8xx_compute_dpll(struct intel_crtc *crtc,
7578 struct intel_crtc_state *crtc_state,
7579 intel_clock_t *reduced_clock,
7580 int num_connectors)
eb1cbe48 7581{
f47709a9 7582 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7583 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7584 u32 dpll;
190f68c5 7585 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7586
190f68c5 7587 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7588
eb1cbe48
DV		 7589 dpll = DPLL_VGA_MODE_DIS;
7590
a93e255f 7591 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7592 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7593 } else {
7594 if (clock->p1 == 2)
7595 dpll |= PLL_P1_DIVIDE_BY_TWO;
7596 else
7597 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7598 if (clock->p2 == 4)
7599 dpll |= PLL_P2_DIVIDE_BY_4;
7600 }
7601
a93e255f 7602 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7603 dpll |= DPLL_DVO_2X_MODE;
7604
a93e255f 7605 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7606 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7607 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7608 else
7609 dpll |= PLL_REF_INPUT_DREFCLK;
7610
7611 dpll |= DPLL_VCO_ENABLE;
190f68c5 7612 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7613}
7614
8a654f3b 7615static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7616{
7617 struct drm_device *dev = intel_crtc->base.dev;
7618 struct drm_i915_private *dev_priv = dev->dev_private;
7619 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7620 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7c5f93b0 7621 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7622 uint32_t crtc_vtotal, crtc_vblank_end;
7623 int vsyncshift = 0;
4d8a62ea
DV		 7624
7625 /* We need to be careful not to changed the adjusted mode, for otherwise
7626 * the hw state checker will get angry at the mismatch. */
7627 crtc_vtotal = adjusted_mode->crtc_vtotal;
7628 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7629
609aeaca 7630 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7631 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7632 crtc_vtotal -= 1;
7633 crtc_vblank_end -= 1;
609aeaca 7634
409ee761 7635 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7636 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7637 else
7638 vsyncshift = adjusted_mode->crtc_hsync_start -
7639 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7640 if (vsyncshift < 0)
7641 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7642 }
7643
7644 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7645 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7646
fe2b8f9d 7647 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7648 (adjusted_mode->crtc_hdisplay - 1) |
7649 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7650 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7651 (adjusted_mode->crtc_hblank_start - 1) |
7652 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7653 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7654 (adjusted_mode->crtc_hsync_start - 1) |
7655 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7656
fe2b8f9d 7657 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7658 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7659 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7660 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7661 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7662 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7663 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7664 (adjusted_mode->crtc_vsync_start - 1) |
7665 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7666
b5e508d4
PZ		 7667 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7668 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7669 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7670 * bits. */
7671 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7672 (pipe == PIPE_B || pipe == PIPE_C))
7673 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7674
b0e77b9c
PZ		 7675 /* pipesrc controls the size that is scaled from, which should
7676 * always be the user's requested size.
7677 */
7678 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7679 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7680 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7681}
7682
1bd1bd80 7683static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7684 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7685{
7686 struct drm_device *dev = crtc->base.dev;
7687 struct drm_i915_private *dev_priv = dev->dev_private;
7688 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7689 uint32_t tmp;
7690
7691 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7692 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7693 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7694 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7695 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7696 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7697 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7698 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7699 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7700
7701 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7702 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7703 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7704 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7705 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7706 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7707 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7708 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7709 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7710
7711 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7712 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7713 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7714 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7715 }
7716
7717 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7718 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7719 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7720
2d112de7
ACO		 7721 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7722 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7723}
7724
f6a83288 7725void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7726 struct intel_crtc_state *pipe_config)
babea61d 7727{
2d112de7
ACO		 7728 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7729 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7730 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7731 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7732
2d112de7
ACO		 7733 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7734 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7735 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7736 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7737
2d112de7 7738 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7739 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7740
2d112de7
ACO		 7741 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7742 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7743
7744 mode->hsync = drm_mode_hsync(mode);
7745 mode->vrefresh = drm_mode_vrefresh(mode);
7746 drm_mode_set_name(mode);
babea61d
JB		 7747}
7748
84b046f3
DV		 7749static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7750{
7751 struct drm_device *dev = intel_crtc->base.dev;
7752 struct drm_i915_private *dev_priv = dev->dev_private;
7753 uint32_t pipeconf;
7754
9f11a9e4 7755 pipeconf = 0;
84b046f3 7756
b6b5d049
VS		 7757 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7758 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7759 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7760
6e3c9717 7761 if (intel_crtc->config->double_wide)
cf532bb2 7762 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7763
ff9ce46e
DV		 7764 /* only g4x and later have fancy bpc/dither controls */
7765 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7766 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7767 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7768 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7769 PIPECONF_DITHER_TYPE_SP;
84b046f3 7770
6e3c9717 7771 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7772 case 18:
7773 pipeconf |= PIPECONF_6BPC;
7774 break;
7775 case 24:
7776 pipeconf |= PIPECONF_8BPC;
7777 break;
7778 case 30:
7779 pipeconf |= PIPECONF_10BPC;
7780 break;
7781 default:
7782 /* Case prevented by intel_choose_pipe_bpp_dither. */
7783 BUG();
84b046f3
DV		 7784 }
7785 }
7786
7787 if (HAS_PIPE_CXSR(dev)) {
7788 if (intel_crtc->lowfreq_avail) {
7789 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7790 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7791 } else {
7792 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7793 }
7794 }
7795
6e3c9717 7796 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7797 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7798 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7799 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7800 else
7801 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7802 } else
84b046f3
DV		 7803 pipeconf |= PIPECONF_PROGRESSIVE;
7804
6e3c9717 7805 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7806 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7807
84b046f3
DV		 7808 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7809 POSTING_READ(PIPECONF(intel_crtc->pipe));
7810}
7811
190f68c5
ACO		 7812static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7813 struct intel_crtc_state *crtc_state)
79e53945 7814{
c7653199 7815 struct drm_device *dev = crtc->base.dev;
79e53945 7816 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7817 int refclk, num_connectors = 0;
c329a4ec
DV		 7818 intel_clock_t clock;
7819 bool ok;
7820 bool is_dsi = false;
5eddb70b 7821 struct intel_encoder *encoder;
d4906093 7822 const intel_limit_t *limit;
55bb9992 7823 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7824 struct drm_connector *connector;
55bb9992
ACO		 7825 struct drm_connector_state *connector_state;
7826 int i;
79e53945 7827
dd3cd74a
ACO		 7828 memset(&crtc_state->dpll_hw_state, 0,
7829 sizeof(crtc_state->dpll_hw_state));
7830
da3ced29 7831 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7832 if (connector_state->crtc != &crtc->base)
7833 continue;
7834
7835 encoder = to_intel_encoder(connector_state->best_encoder);
7836
5eddb70b 7837 switch (encoder->type) {
e9fd1c02
JN		 7838 case INTEL_OUTPUT_DSI:
7839 is_dsi = true;
7840 break;
6847d71b
PZ		 7841 default:
7842 break;
79e53945 7843 }
43565a06 7844
c751ce4f 7845 num_connectors++;
79e53945
JB		 7846 }
7847
f2335330 7848 if (is_dsi)
5b18e57c 7849 return 0;
f2335330 7850
190f68c5 7851 if (!crtc_state->clock_set) {
a93e255f 7852 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7853
e9fd1c02
JN		 7854 /*
7855 * Returns a set of divisors for the desired target clock with
7856 * the given refclk, or FALSE. The returned values represent
7857 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7858 * 2) / p1 / p2.
7859 */
a93e255f
ACO		 7860 limit = intel_limit(crtc_state, refclk);
7861 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7862 crtc_state->port_clock,
e9fd1c02 7863 refclk, NULL, &clock);
f2335330 7864 if (!ok) {
e9fd1c02
JN		 7865 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7866 return -EINVAL;
7867 }
79e53945 7868
f2335330 7869 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7870 crtc_state->dpll.n = clock.n;
7871 crtc_state->dpll.m1 = clock.m1;
7872 crtc_state->dpll.m2 = clock.m2;
7873 crtc_state->dpll.p1 = clock.p1;
7874 crtc_state->dpll.p2 = clock.p2;
f47709a9 7875 }
7026d4ac 7876
e9fd1c02 7877 if (IS_GEN2(dev)) {
c329a4ec 7878 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7879 num_connectors);
9d556c99 7880 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7881 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7882 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7883 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7884 } else {
c329a4ec 7885 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7886 num_connectors);
e9fd1c02 7887 }
79e53945 7888
c8f7a0db 7889 return 0;
f564048e
EA		 7890}
7891
2fa2fe9a 7892static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7893 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7894{
7895 struct drm_device *dev = crtc->base.dev;
7896 struct drm_i915_private *dev_priv = dev->dev_private;
7897 uint32_t tmp;
7898
dc9e7dec
VS		 7899 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7900 return;
7901
2fa2fe9a 7902 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7903 if (!(tmp & PFIT_ENABLE))
7904 return;
2fa2fe9a 7905
06922821 7906 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7907 if (INTEL_INFO(dev)->gen < 4) {
7908 if (crtc->pipe != PIPE_B)
7909 return;
2fa2fe9a
DV		 7910 } else {
7911 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7912 return;
7913 }
7914
06922821 7915 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7916 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7917 if (INTEL_INFO(dev)->gen < 5)
7918 pipe_config->gmch_pfit.lvds_border_bits =
7919 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7920}
7921
acbec814 7922static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7923 struct intel_crtc_state *pipe_config)
acbec814
JB		 7924{
7925 struct drm_device *dev = crtc->base.dev;
7926 struct drm_i915_private *dev_priv = dev->dev_private;
7927 int pipe = pipe_config->cpu_transcoder;
7928 intel_clock_t clock;
7929 u32 mdiv;
662c6ecb 7930 int refclk = 100000;
acbec814 7931
f573de5a
SK		 7932 /* In case of MIPI DPLL will not even be used */
7933 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7934 return;
7935
a580516d 7936 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7937 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7938 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7939
7940 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7941 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7942 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7943 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7944 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7945
dccbea3b 7946 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7947}
7948
5724dbd1
DL		 7949static void
7950i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7951 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7952{
7953 struct drm_device *dev = crtc->base.dev;
7954 struct drm_i915_private *dev_priv = dev->dev_private;
7955 u32 val, base, offset;
7956 int pipe = crtc->pipe, plane = crtc->plane;
7957 int fourcc, pixel_format;
6761dd31 7958 unsigned int aligned_height;
b113d5ee 7959 struct drm_framebuffer *fb;
1b842c89 7960 struct intel_framebuffer *intel_fb;
1ad292b5 7961
42a7b088
DL		 7962 val = I915_READ(DSPCNTR(plane));
7963 if (!(val & DISPLAY_PLANE_ENABLE))
7964 return;
7965
d9806c9f 7966 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7967 if (!intel_fb) {
1ad292b5
JB		 7968 DRM_DEBUG_KMS("failed to alloc fb\n");
7969 return;
7970 }
7971
1b842c89
DL		 7972 fb = &intel_fb->base;
7973
18c5247e
DV		 7974 if (INTEL_INFO(dev)->gen >= 4) {
7975 if (val & DISPPLANE_TILED) {
49af449b 7976 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7977 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7978 }
7979 }
1ad292b5
JB		 7980
7981 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7982 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7983 fb->pixel_format = fourcc;
7984 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7985
7986 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7987 if (plane_config->tiling)
1ad292b5
JB		 7988 offset = I915_READ(DSPTILEOFF(plane));
7989 else
7990 offset = I915_READ(DSPLINOFF(plane));
7991 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7992 } else {
7993 base = I915_READ(DSPADDR(plane));
7994 }
7995 plane_config->base = base;
7996
7997 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7998 fb->width = ((val >> 16) & 0xfff) + 1;
7999 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8000
8001 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8002 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8003
b113d5ee 8004 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8005 fb->pixel_format,
8006 fb->modifier[0]);
1ad292b5 8007
f37b5c2b 8008 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8009
2844a921
DL		 8010 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8011 pipe_name(pipe), plane, fb->width, fb->height,
8012 fb->bits_per_pixel, base, fb->pitches[0],
8013 plane_config->size);
1ad292b5 8014
2d14030b 8015 plane_config->fb = intel_fb;
1ad292b5
JB		 8016}
8017
70b23a98 8018static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8019 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8020{
8021 struct drm_device *dev = crtc->base.dev;
8022 struct drm_i915_private *dev_priv = dev->dev_private;
8023 int pipe = pipe_config->cpu_transcoder;
8024 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8025 intel_clock_t clock;
0d7b6b11 8026 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 8027 int refclk = 100000;
8028
a580516d 8029 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8030 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8031 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8032 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8033 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8034 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8035 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8036
8037 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8038 clock.m2 = (pll_dw0 & 0xff) << 22;
8039 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8040 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8041 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8042 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8043 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8044
dccbea3b 8045 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8046}
8047
0e8ffe1b 8048static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8049 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8050{
8051 struct drm_device *dev = crtc->base.dev;
8052 struct drm_i915_private *dev_priv = dev->dev_private;
8053 uint32_t tmp;
8054
f458ebbc
DV		 8055 if (!intel_display_power_is_enabled(dev_priv,
8056 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8057 return false;
8058
e143a21c 8059 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8060 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8061
0e8ffe1b
DV		 8062 tmp = I915_READ(PIPECONF(crtc->pipe));
8063 if (!(tmp & PIPECONF_ENABLE))
8064 return false;
8065
42571aef
VS		 8066 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8067 switch (tmp & PIPECONF_BPC_MASK) {
8068 case PIPECONF_6BPC:
8069 pipe_config->pipe_bpp = 18;
8070 break;
8071 case PIPECONF_8BPC:
8072 pipe_config->pipe_bpp = 24;
8073 break;
8074 case PIPECONF_10BPC:
8075 pipe_config->pipe_bpp = 30;
8076 break;
8077 default:
8078 break;
8079 }
8080 }
8081
b5a9fa09
DV		 8082 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8083 pipe_config->limited_color_range = true;
8084
282740f7
VS		 8085 if (INTEL_INFO(dev)->gen < 4)
8086 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8087
1bd1bd80
DV		 8088 intel_get_pipe_timings(crtc, pipe_config);
8089
2fa2fe9a
DV		 8090 i9xx_get_pfit_config(crtc, pipe_config);
8091
6c49f241
DV		 8092 if (INTEL_INFO(dev)->gen >= 4) {
8093 tmp = I915_READ(DPLL_MD(crtc->pipe));
8094 pipe_config->pixel_multiplier =
8095 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8096 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8097 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8098 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8099 tmp = I915_READ(DPLL(crtc->pipe));
8100 pipe_config->pixel_multiplier =
8101 ((tmp & SDVO_MULTIPLIER_MASK)
8102 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8103 } else {
8104 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8105 * port and will be fixed up in the encoder->get_config
8106 * function. */
8107 pipe_config->pixel_multiplier = 1;
8108 }
8bcc2795
DV		 8109 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8110 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8111 /*
8112 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8113 * on 830. Filter it out here so that we don't
8114 * report errors due to that.
8115 */
8116 if (IS_I830(dev))
8117 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8118
8bcc2795
DV		 8119 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8120 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8121 } else {
8122 /* Mask out read-only status bits. */
8123 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8124 DPLL_PORTC_READY_MASK |
8125 DPLL_PORTB_READY_MASK);
8bcc2795 8126 }
6c49f241 8127
70b23a98
VS		 8128 if (IS_CHERRYVIEW(dev))
8129 chv_crtc_clock_get(crtc, pipe_config);
8130 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8131 vlv_crtc_clock_get(crtc, pipe_config);
8132 else
8133 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8134
0f64614d
VS		 8135 /*
8136 * Normally the dotclock is filled in by the encoder .get_config()
8137 * but in case the pipe is enabled w/o any ports we need a sane
8138 * default.
8139 */
8140 pipe_config->base.adjusted_mode.crtc_clock =
8141 pipe_config->port_clock / pipe_config->pixel_multiplier;
8142
0e8ffe1b
DV		 8143 return true;
8144}
8145
dde86e2d 8146static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8147{
8148 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8149 struct intel_encoder *encoder;
74cfd7ac 8150 u32 val, final;
13d83a67 8151 bool has_lvds = false;
199e5d79 8152 bool has_cpu_edp = false;
199e5d79 8153 bool has_panel = false;
99eb6a01
KP		 8154 bool has_ck505 = false;
8155 bool can_ssc = false;
13d83a67
JB		 8156
8157 /* We need to take the global config into account */
b2784e15 8158 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8159 switch (encoder->type) {
8160 case INTEL_OUTPUT_LVDS:
8161 has_panel = true;
8162 has_lvds = true;
8163 break;
8164 case INTEL_OUTPUT_EDP:
8165 has_panel = true;
2de6905f 8166 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8167 has_cpu_edp = true;
8168 break;
6847d71b
PZ		 8169 default:
8170 break;
13d83a67
JB		 8171 }
8172 }
8173
99eb6a01 8174 if (HAS_PCH_IBX(dev)) {
41aa3448 8175 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8176 can_ssc = has_ck505;
8177 } else {
8178 has_ck505 = false;
8179 can_ssc = true;
8180 }
8181
2de6905f
ID		 8182 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8183 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8184
8185 /* Ironlake: try to setup display ref clock before DPLL
8186 * enabling. This is only under driver's control after
8187 * PCH B stepping, previous chipset stepping should be
8188 * ignoring this setting.
8189 */
74cfd7ac
CW		 8190 val = I915_READ(PCH_DREF_CONTROL);
8191
8192 /* As we must carefully and slowly disable/enable each source in turn,
8193 * compute the final state we want first and check if we need to
8194 * make any changes at all.
8195 */
8196 final = val;
8197 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8198 if (has_ck505)
8199 final |= DREF_NONSPREAD_CK505_ENABLE;
8200 else
8201 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8202
8203 final &= ~DREF_SSC_SOURCE_MASK;
8204 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8205 final &= ~DREF_SSC1_ENABLE;
8206
8207 if (has_panel) {
8208 final |= DREF_SSC_SOURCE_ENABLE;
8209
8210 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8211 final |= DREF_SSC1_ENABLE;
8212
8213 if (has_cpu_edp) {
8214 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8215 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8216 else
8217 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8218 } else
8219 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8220 } else {
8221 final |= DREF_SSC_SOURCE_DISABLE;
8222 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8223 }
8224
8225 if (final == val)
8226 return;
8227
13d83a67 8228 /* Always enable nonspread source */
74cfd7ac 8229 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8230
99eb6a01 8231 if (has_ck505)
74cfd7ac 8232 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8233 else
74cfd7ac 8234 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8235
199e5d79 8236 if (has_panel) {
74cfd7ac
CW		 8237 val &= ~DREF_SSC_SOURCE_MASK;
8238 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8239
199e5d79 8240 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8241 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8242 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8243 val |= DREF_SSC1_ENABLE;
e77166b5 8244 } else
74cfd7ac 8245 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8246
8247 /* Get SSC going before enabling the outputs */
74cfd7ac 8248 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8249 POSTING_READ(PCH_DREF_CONTROL);
8250 udelay(200);
8251
74cfd7ac 8252 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8253
8254 /* Enable CPU source on CPU attached eDP */
199e5d79 8255 if (has_cpu_edp) {
99eb6a01 8256 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8257 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8258 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8259 } else
74cfd7ac 8260 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8261 } else
74cfd7ac 8262 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8263
74cfd7ac 8264 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8265 POSTING_READ(PCH_DREF_CONTROL);
8266 udelay(200);
8267 } else {
8268 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8269
74cfd7ac 8270 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8271
8272 /* Turn off CPU output */
74cfd7ac 8273 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8274
74cfd7ac 8275 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8276 POSTING_READ(PCH_DREF_CONTROL);
8277 udelay(200);
8278
8279 /* Turn off the SSC source */
74cfd7ac
CW		 8280 val &= ~DREF_SSC_SOURCE_MASK;
8281 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8282
8283 /* Turn off SSC1 */
74cfd7ac 8284 val &= ~DREF_SSC1_ENABLE;
199e5d79 8285
74cfd7ac 8286 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8287 POSTING_READ(PCH_DREF_CONTROL);
8288 udelay(200);
8289 }
74cfd7ac
CW		 8290
8291 BUG_ON(val != final);
13d83a67
JB		 8292}
8293
f31f2d55 8294static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8295{
f31f2d55 8296 uint32_t tmp;
dde86e2d 8297
0ff066a9
PZ		 8298 tmp = I915_READ(SOUTH_CHICKEN2);
8299 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8300 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8301
0ff066a9
PZ		 8302 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8303 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8304 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8305
0ff066a9
PZ		 8306 tmp = I915_READ(SOUTH_CHICKEN2);
8307 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8308 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8309
0ff066a9
PZ		 8310 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8311 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8312 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8313}
8314
8315/* WaMPhyProgramming:hsw */
8316static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8317{
8318 uint32_t tmp;
dde86e2d
PZ		 8319
8320 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8321 tmp &= ~(0xFF << 24);
8322 tmp |= (0x12 << 24);
8323 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8324
dde86e2d
PZ		 8325 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8326 tmp |= (1 << 11);
8327 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8328
8329 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8330 tmp |= (1 << 11);
8331 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8332
dde86e2d
PZ		 8333 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8334 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8335 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8336
8337 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8338 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8339 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8340
0ff066a9
PZ		 8341 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8342 tmp &= ~(7 << 13);
8343 tmp |= (5 << 13);
8344 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8345
0ff066a9
PZ		 8346 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8347 tmp &= ~(7 << 13);
8348 tmp |= (5 << 13);
8349 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8350
8351 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8352 tmp &= ~0xFF;
8353 tmp |= 0x1C;
8354 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8355
8356 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8357 tmp &= ~0xFF;
8358 tmp |= 0x1C;
8359 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8360
8361 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8362 tmp &= ~(0xFF << 16);
8363 tmp |= (0x1C << 16);
8364 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8365
8366 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8367 tmp &= ~(0xFF << 16);
8368 tmp |= (0x1C << 16);
8369 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8370
0ff066a9
PZ		 8371 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8372 tmp |= (1 << 27);
8373 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8374
0ff066a9
PZ		 8375 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8376 tmp |= (1 << 27);
8377 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8378
0ff066a9
PZ		 8379 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8380 tmp &= ~(0xF << 28);
8381 tmp |= (4 << 28);
8382 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8383
0ff066a9
PZ		 8384 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8385 tmp &= ~(0xF << 28);
8386 tmp |= (4 << 28);
8387 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8388}
8389
2fa86a1f
PZ		 8390/* Implements 3 different sequences from BSpec chapter "Display iCLK
8391 * Programming" based on the parameters passed:
8392 * - Sequence to enable CLKOUT_DP
8393 * - Sequence to enable CLKOUT_DP without spread
8394 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8395 */
8396static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8397 bool with_fdi)
f31f2d55
PZ		 8398{
8399 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8400 uint32_t reg, tmp;
8401
8402 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8403 with_spread = true;
c2699524 8404 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8405 with_fdi = false;
f31f2d55 8406
a580516d 8407 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8408
8409 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8410 tmp &= ~SBI_SSCCTL_DISABLE;
8411 tmp |= SBI_SSCCTL_PATHALT;
8412 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8413
8414 udelay(24);
8415
2fa86a1f
PZ		 8416 if (with_spread) {
8417 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8418 tmp &= ~SBI_SSCCTL_PATHALT;
8419 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8420
2fa86a1f
PZ		 8421 if (with_fdi) {
8422 lpt_reset_fdi_mphy(dev_priv);
8423 lpt_program_fdi_mphy(dev_priv);
8424 }
8425 }
dde86e2d 8426
c2699524 8427 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ		 8428 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8429 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8430 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8431
a580516d 8432 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8433}
8434
47701c3b
PZ		 8435/* Sequence to disable CLKOUT_DP */
8436static void lpt_disable_clkout_dp(struct drm_device *dev)
8437{
8438 struct drm_i915_private *dev_priv = dev->dev_private;
8439 uint32_t reg, tmp;
8440
a580516d 8441 mutex_lock(&dev_priv->sb_lock);
47701c3b 8442
c2699524 8443 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ		 8444 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8445 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8446 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8447
8448 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8449 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8450 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8451 tmp |= SBI_SSCCTL_PATHALT;
8452 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8453 udelay(32);
8454 }
8455 tmp |= SBI_SSCCTL_DISABLE;
8456 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8457 }
8458
a580516d 8459 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8460}
8461
bf8fa3d3
PZ		 8462static void lpt_init_pch_refclk(struct drm_device *dev)
8463{
bf8fa3d3
PZ		 8464 struct intel_encoder *encoder;
8465 bool has_vga = false;
8466
b2784e15 8467 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8468 switch (encoder->type) {
8469 case INTEL_OUTPUT_ANALOG:
8470 has_vga = true;
8471 break;
6847d71b
PZ		 8472 default:
8473 break;
bf8fa3d3
PZ		 8474 }
8475 }
8476
47701c3b
PZ		 8477 if (has_vga)
8478 lpt_enable_clkout_dp(dev, true, true);
8479 else
8480 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8481}
8482
dde86e2d
PZ		 8483/*
8484 * Initialize reference clocks when the driver loads
8485 */
8486void intel_init_pch_refclk(struct drm_device *dev)
8487{
8488 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8489 ironlake_init_pch_refclk(dev);
8490 else if (HAS_PCH_LPT(dev))
8491 lpt_init_pch_refclk(dev);
8492}
8493
55bb9992 8494static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8495{
55bb9992 8496 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8497 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8498 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8499 struct drm_connector *connector;
55bb9992 8500 struct drm_connector_state *connector_state;
d9d444cb 8501 struct intel_encoder *encoder;
55bb9992 8502 int num_connectors = 0, i;
d9d444cb
JB		 8503 bool is_lvds = false;
8504
da3ced29 8505 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8506 if (connector_state->crtc != crtc_state->base.crtc)
8507 continue;
8508
8509 encoder = to_intel_encoder(connector_state->best_encoder);
8510
d9d444cb
JB		 8511 switch (encoder->type) {
8512 case INTEL_OUTPUT_LVDS:
8513 is_lvds = true;
8514 break;
6847d71b
PZ		 8515 default:
8516 break;
d9d444cb
JB		 8517 }
8518 num_connectors++;
8519 }
8520
8521 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8522 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8523 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8524 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8525 }
8526
8527 return 120000;
8528}
8529
6ff93609 8530static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8531{
c8203565 8532 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8534 int pipe = intel_crtc->pipe;
c8203565
PZ		 8535 uint32_t val;
8536
78114071 8537 val = 0;
c8203565 8538
6e3c9717 8539 switch (intel_crtc->config->pipe_bpp) {
c8203565 8540 case 18:
dfd07d72 8541 val |= PIPECONF_6BPC;
c8203565
PZ		 8542 break;
8543 case 24:
dfd07d72 8544 val |= PIPECONF_8BPC;
c8203565
PZ		 8545 break;
8546 case 30:
dfd07d72 8547 val |= PIPECONF_10BPC;
c8203565
PZ		 8548 break;
8549 case 36:
dfd07d72 8550 val |= PIPECONF_12BPC;
c8203565
PZ		 8551 break;
8552 default:
cc769b62
PZ		 8553 /* Case prevented by intel_choose_pipe_bpp_dither. */
8554 BUG();
c8203565
PZ		 8555 }
8556
6e3c9717 8557 if (intel_crtc->config->dither)
c8203565
PZ		 8558 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8559
6e3c9717 8560 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8561 val |= PIPECONF_INTERLACED_ILK;
8562 else
8563 val |= PIPECONF_PROGRESSIVE;
8564
6e3c9717 8565 if (intel_crtc->config->limited_color_range)
3685a8f3 8566 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8567
c8203565
PZ		 8568 I915_WRITE(PIPECONF(pipe), val);
8569 POSTING_READ(PIPECONF(pipe));
8570}
8571
86d3efce
VS		 8572/*
8573 * Set up the pipe CSC unit.
8574 *
8575 * Currently only full range RGB to limited range RGB conversion
8576 * is supported, but eventually this should handle various
8577 * RGB<->YCbCr scenarios as well.
8578 */
50f3b016 8579static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8580{
8581 struct drm_device *dev = crtc->dev;
8582 struct drm_i915_private *dev_priv = dev->dev_private;
8583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8584 int pipe = intel_crtc->pipe;
8585 uint16_t coeff = 0x7800; /* 1.0 */
8586
8587 /*
8588 * TODO: Check what kind of values actually come out of the pipe
8589 * with these coeff/postoff values and adjust to get the best
8590 * accuracy. Perhaps we even need to take the bpc value into
8591 * consideration.
8592 */
8593
6e3c9717 8594 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8595 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8596
8597 /*
8598 * GY/GU and RY/RU should be the other way around according
8599 * to BSpec, but reality doesn't agree. Just set them up in
8600 * a way that results in the correct picture.
8601 */
8602 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8603 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8604
8605 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8606 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8607
8608 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8609 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8610
8611 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8612 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8613 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8614
8615 if (INTEL_INFO(dev)->gen > 6) {
8616 uint16_t postoff = 0;
8617
6e3c9717 8618 if (intel_crtc->config->limited_color_range)
32cf0cb0 8619 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8620
8621 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8622 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8623 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8624
8625 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8626 } else {
8627 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8628
6e3c9717 8629 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8630 mode |= CSC_BLACK_SCREEN_OFFSET;
8631
8632 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8633 }
8634}
8635
6ff93609 8636static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8637{
756f85cf
PZ		 8638 struct drm_device *dev = crtc->dev;
8639 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8641 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8642 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8643 uint32_t val;
8644
3eff4faa 8645 val = 0;
ee2b0b38 8646
6e3c9717 8647 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8648 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8649
6e3c9717 8650 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8651 val |= PIPECONF_INTERLACED_ILK;
8652 else
8653 val |= PIPECONF_PROGRESSIVE;
8654
702e7a56
PZ		 8655 I915_WRITE(PIPECONF(cpu_transcoder), val);
8656 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8657
8658 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8659 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8660
3cdf122c 8661 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8662 val = 0;
8663
6e3c9717 8664 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8665 case 18:
8666 val |= PIPEMISC_DITHER_6_BPC;
8667 break;
8668 case 24:
8669 val |= PIPEMISC_DITHER_8_BPC;
8670 break;
8671 case 30:
8672 val |= PIPEMISC_DITHER_10_BPC;
8673 break;
8674 case 36:
8675 val |= PIPEMISC_DITHER_12_BPC;
8676 break;
8677 default:
8678 /* Case prevented by pipe_config_set_bpp. */
8679 BUG();
8680 }
8681
6e3c9717 8682 if (intel_crtc->config->dither)
756f85cf
PZ		 8683 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8684
8685 I915_WRITE(PIPEMISC(pipe), val);
8686 }
ee2b0b38
PZ		 8687}
8688
6591c6e4 8689static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8690 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8691 intel_clock_t *clock,
8692 bool *has_reduced_clock,
8693 intel_clock_t *reduced_clock)
8694{
8695 struct drm_device *dev = crtc->dev;
8696 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8697 int refclk;
d4906093 8698 const intel_limit_t *limit;
c329a4ec 8699 bool ret;
79e53945 8700
55bb9992 8701 refclk = ironlake_get_refclk(crtc_state);
79e53945 8702
d4906093
ML		 8703 /*
8704 * Returns a set of divisors for the desired target clock with the given
8705 * refclk, or FALSE. The returned values represent the clock equation:
8706 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8707 */
a93e255f
ACO		 8708 limit = intel_limit(crtc_state, refclk);
8709 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8710 crtc_state->port_clock,
ee9300bb 8711 refclk, NULL, clock);
6591c6e4
PZ		 8712 if (!ret)
8713 return false;
cda4b7d3 8714
6591c6e4
PZ		 8715 return true;
8716}
8717
d4b1931c
PZ		 8718int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8719{
8720 /*
8721 * Account for spread spectrum to avoid
8722 * oversubscribing the link. Max center spread
8723 * is 2.5%; use 5% for safety's sake.
8724 */
8725 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8726 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8727}
8728
7429e9d4 8729static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8730{
7429e9d4 8731 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8732}
8733
de13a2e3 8734static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8735 struct intel_crtc_state *crtc_state,
7429e9d4 8736 u32 *fp,
9a7c7890 8737 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8738{
de13a2e3 8739 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8740 struct drm_device *dev = crtc->dev;
8741 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8742 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8743 struct drm_connector *connector;
55bb9992
ACO		 8744 struct drm_connector_state *connector_state;
8745 struct intel_encoder *encoder;
de13a2e3 8746 uint32_t dpll;
55bb9992 8747 int factor, num_connectors = 0, i;
09ede541 8748 bool is_lvds = false, is_sdvo = false;
79e53945 8749
da3ced29 8750 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8751 if (connector_state->crtc != crtc_state->base.crtc)
8752 continue;
8753
8754 encoder = to_intel_encoder(connector_state->best_encoder);
8755
8756 switch (encoder->type) {
79e53945
JB		 8757 case INTEL_OUTPUT_LVDS:
8758 is_lvds = true;
8759 break;
8760 case INTEL_OUTPUT_SDVO:
7d57382e 8761 case INTEL_OUTPUT_HDMI:
79e53945 8762 is_sdvo = true;
79e53945 8763 break;
6847d71b
PZ		 8764 default:
8765 break;
79e53945 8766 }
43565a06 8767
c751ce4f 8768 num_connectors++;
79e53945 8769 }
79e53945 8770
c1858123 8771 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8772 factor = 21;
8773 if (is_lvds) {
8774 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8775 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8776 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8777 factor = 25;
190f68c5 8778 } else if (crtc_state->sdvo_tv_clock)
8febb297 8779 factor = 20;
c1858123 8780
190f68c5 8781 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8782 *fp |= FP_CB_TUNE;
2c07245f 8783
9a7c7890
DV		 8784 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8785 *fp2 |= FP_CB_TUNE;
8786
5eddb70b 8787 dpll = 0;
2c07245f 8788
a07d6787
EA		 8789 if (is_lvds)
8790 dpll |= DPLLB_MODE_LVDS;
8791 else
8792 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8793
190f68c5 8794 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8795 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8796
8797 if (is_sdvo)
4a33e48d 8798 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8799 if (crtc_state->has_dp_encoder)
4a33e48d 8800 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8801
a07d6787 8802 /* compute bitmask from p1 value */
190f68c5 8803 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8804 /* also FPA1 */
190f68c5 8805 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8806
190f68c5 8807 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8808 case 5:
8809 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8810 break;
8811 case 7:
8812 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8813 break;
8814 case 10:
8815 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8816 break;
8817 case 14:
8818 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8819 break;
79e53945
JB		 8820 }
8821
b4c09f3b 8822 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8823 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8824 else
8825 dpll |= PLL_REF_INPUT_DREFCLK;
8826
959e16d6 8827 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8828}
8829
190f68c5
ACO		 8830static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8831 struct intel_crtc_state *crtc_state)
de13a2e3 8832{
c7653199 8833 struct drm_device *dev = crtc->base.dev;
de13a2e3 8834 intel_clock_t clock, reduced_clock;
cbbab5bd 8835 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8836 bool ok, has_reduced_clock = false;
8b47047b 8837 bool is_lvds = false;
e2b78267 8838 struct intel_shared_dpll *pll;
de13a2e3 8839
dd3cd74a
ACO		 8840 memset(&crtc_state->dpll_hw_state, 0,
8841 sizeof(crtc_state->dpll_hw_state));
8842
409ee761 8843 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8844
5dc5298b
PZ		 8845 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8846 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8847
190f68c5 8848 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8849 &has_reduced_clock, &reduced_clock);
190f68c5 8850 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8851 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8852 return -EINVAL;
79e53945 8853 }
f47709a9 8854 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8855 if (!crtc_state->clock_set) {
8856 crtc_state->dpll.n = clock.n;
8857 crtc_state->dpll.m1 = clock.m1;
8858 crtc_state->dpll.m2 = clock.m2;
8859 crtc_state->dpll.p1 = clock.p1;
8860 crtc_state->dpll.p2 = clock.p2;
f47709a9 8861 }
79e53945 8862
5dc5298b 8863 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8864 if (crtc_state->has_pch_encoder) {
8865 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8866 if (has_reduced_clock)
7429e9d4 8867 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8868
190f68c5 8869 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8870 &fp, &reduced_clock,
8871 has_reduced_clock ? &fp2 : NULL);
8872
190f68c5
ACO		 8873 crtc_state->dpll_hw_state.dpll = dpll;
8874 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8875 if (has_reduced_clock)
190f68c5 8876 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8877 else
190f68c5 8878 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8879
190f68c5 8880 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8881 if (pll == NULL) {
84f44ce7 8882 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8883 pipe_name(crtc->pipe));
4b645f14
JB		 8884 return -EINVAL;
8885 }
3fb37703 8886 }
79e53945 8887
ab585dea 8888 if (is_lvds && has_reduced_clock)
c7653199 8889 crtc->lowfreq_avail = true;
bcd644e0 8890 else
c7653199 8891 crtc->lowfreq_avail = false;
e2b78267 8892
c8f7a0db 8893 return 0;
79e53945
JB		 8894}
8895
eb14cb74
VS		 8896static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8897 struct intel_link_m_n *m_n)
8898{
8899 struct drm_device *dev = crtc->base.dev;
8900 struct drm_i915_private *dev_priv = dev->dev_private;
8901 enum pipe pipe = crtc->pipe;
8902
8903 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8904 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8905 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8906 & ~TU_SIZE_MASK;
8907 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8908 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8909 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8910}
8911
8912static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8913 enum transcoder transcoder,
b95af8be
VK		 8914 struct intel_link_m_n *m_n,
8915 struct intel_link_m_n *m2_n2)
72419203
DV		 8916{
8917 struct drm_device *dev = crtc->base.dev;
8918 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8919 enum pipe pipe = crtc->pipe;
72419203 8920
eb14cb74
VS		 8921 if (INTEL_INFO(dev)->gen >= 5) {
8922 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8923 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8924 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8925 & ~TU_SIZE_MASK;
8926 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8927 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8928 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8929 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8930 * gen < 8) and if DRRS is supported (to make sure the
8931 * registers are not unnecessarily read).
8932 */
8933 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8934 crtc->config->has_drrs) {
b95af8be
VK		 8935 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8936 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8937 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8938 & ~TU_SIZE_MASK;
8939 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8940 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8941 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8942 }
eb14cb74
VS		 8943 } else {
8944 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8945 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8946 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8947 & ~TU_SIZE_MASK;
8948 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8949 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8950 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8951 }
8952}
8953
8954void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8955 struct intel_crtc_state *pipe_config)
eb14cb74 8956{
681a8504 8957 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8958 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8959 else
8960 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8961 &pipe_config->dp_m_n,
8962 &pipe_config->dp_m2_n2);
eb14cb74 8963}
72419203 8964
eb14cb74 8965static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8966 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8967{
8968 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8969 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8970}
8971
bd2e244f 8972static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8973 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8974{
8975 struct drm_device *dev = crtc->base.dev;
8976 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8977 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8978 uint32_t ps_ctrl = 0;
8979 int id = -1;
8980 int i;
bd2e244f 8981
a1b2278e
CK		 8982 /* find scaler attached to this pipe */
8983 for (i = 0; i < crtc->num_scalers; i++) {
8984 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8985 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8986 id = i;
8987 pipe_config->pch_pfit.enabled = true;
8988 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8989 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8990 break;
8991 }
8992 }
bd2e244f 8993
a1b2278e
CK		 8994 scaler_state->scaler_id = id;
8995 if (id >= 0) {
8996 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8997 } else {
8998 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8999 }
9000}
9001
5724dbd1
DL		 9002static void
9003skylake_get_initial_plane_config(struct intel_crtc *crtc,
9004 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9005{
9006 struct drm_device *dev = crtc->base.dev;
9007 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9008 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9009 int pipe = crtc->pipe;
9010 int fourcc, pixel_format;
6761dd31 9011 unsigned int aligned_height;
bc8d7dff 9012 struct drm_framebuffer *fb;
1b842c89 9013 struct intel_framebuffer *intel_fb;
bc8d7dff 9014
d9806c9f 9015 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9016 if (!intel_fb) {
bc8d7dff
DL		 9017 DRM_DEBUG_KMS("failed to alloc fb\n");
9018 return;
9019 }
9020
1b842c89
DL		 9021 fb = &intel_fb->base;
9022
bc8d7dff 9023 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9024 if (!(val & PLANE_CTL_ENABLE))
9025 goto error;
9026
bc8d7dff
DL		 9027 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9028 fourcc = skl_format_to_fourcc(pixel_format,
9029 val & PLANE_CTL_ORDER_RGBX,
9030 val & PLANE_CTL_ALPHA_MASK);
9031 fb->pixel_format = fourcc;
9032 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9033
40f46283
DL		 9034 tiling = val & PLANE_CTL_TILED_MASK;
9035 switch (tiling) {
9036 case PLANE_CTL_TILED_LINEAR:
9037 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9038 break;
9039 case PLANE_CTL_TILED_X:
9040 plane_config->tiling = I915_TILING_X;
9041 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9042 break;
9043 case PLANE_CTL_TILED_Y:
9044 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9045 break;
9046 case PLANE_CTL_TILED_YF:
9047 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9048 break;
9049 default:
9050 MISSING_CASE(tiling);
9051 goto error;
9052 }
9053
bc8d7dff
DL		 9054 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9055 plane_config->base = base;
9056
9057 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9058
9059 val = I915_READ(PLANE_SIZE(pipe, 0));
9060 fb->height = ((val >> 16) & 0xfff) + 1;
9061 fb->width = ((val >> 0) & 0x1fff) + 1;
9062
9063 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9064 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9065 fb->pixel_format);
bc8d7dff
DL		 9066 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9067
9068 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9069 fb->pixel_format,
9070 fb->modifier[0]);
bc8d7dff 9071
f37b5c2b 9072 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9073
9074 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9075 pipe_name(pipe), fb->width, fb->height,
9076 fb->bits_per_pixel, base, fb->pitches[0],
9077 plane_config->size);
9078
2d14030b 9079 plane_config->fb = intel_fb;
bc8d7dff
DL		 9080 return;
9081
9082error:
9083 kfree(fb);
9084}
9085
2fa2fe9a 9086static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9087 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9088{
9089 struct drm_device *dev = crtc->base.dev;
9090 struct drm_i915_private *dev_priv = dev->dev_private;
9091 uint32_t tmp;
9092
9093 tmp = I915_READ(PF_CTL(crtc->pipe));
9094
9095 if (tmp & PF_ENABLE) {
fd4daa9c 9096 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9097 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9098 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9099
9100 /* We currently do not free assignements of panel fitters on
9101 * ivb/hsw (since we don't use the higher upscaling modes which
9102 * differentiates them) so just WARN about this case for now. */
9103 if (IS_GEN7(dev)) {
9104 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9105 PF_PIPE_SEL_IVB(crtc->pipe));
9106 }
2fa2fe9a 9107 }
79e53945
JB		 9108}
9109
5724dbd1
DL		 9110static void
9111ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9112 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9113{
9114 struct drm_device *dev = crtc->base.dev;
9115 struct drm_i915_private *dev_priv = dev->dev_private;
9116 u32 val, base, offset;
aeee5a49 9117 int pipe = crtc->pipe;
4c6baa59 9118 int fourcc, pixel_format;
6761dd31 9119 unsigned int aligned_height;
b113d5ee 9120 struct drm_framebuffer *fb;
1b842c89 9121 struct intel_framebuffer *intel_fb;
4c6baa59 9122
42a7b088
DL		 9123 val = I915_READ(DSPCNTR(pipe));
9124 if (!(val & DISPLAY_PLANE_ENABLE))
9125 return;
9126
d9806c9f 9127 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9128 if (!intel_fb) {
4c6baa59
JB		 9129 DRM_DEBUG_KMS("failed to alloc fb\n");
9130 return;
9131 }
9132
1b842c89
DL		 9133 fb = &intel_fb->base;
9134
18c5247e
DV		 9135 if (INTEL_INFO(dev)->gen >= 4) {
9136 if (val & DISPPLANE_TILED) {
49af449b 9137 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9138 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9139 }
9140 }
4c6baa59
JB		 9141
9142 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9143 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9144 fb->pixel_format = fourcc;
9145 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9146
aeee5a49 9147 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9148 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9149 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9150 } else {
49af449b 9151 if (plane_config->tiling)
aeee5a49 9152 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9153 else
aeee5a49 9154 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9155 }
9156 plane_config->base = base;
9157
9158 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9159 fb->width = ((val >> 16) & 0xfff) + 1;
9160 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9161
9162 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9163 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9164
b113d5ee 9165 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9166 fb->pixel_format,
9167 fb->modifier[0]);
4c6baa59 9168
f37b5c2b 9169 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9170
2844a921
DL		 9171 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9172 pipe_name(pipe), fb->width, fb->height,
9173 fb->bits_per_pixel, base, fb->pitches[0],
9174 plane_config->size);
b113d5ee 9175
2d14030b 9176 plane_config->fb = intel_fb;
4c6baa59
JB		 9177}
9178
0e8ffe1b 9179static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9180 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9181{
9182 struct drm_device *dev = crtc->base.dev;
9183 struct drm_i915_private *dev_priv = dev->dev_private;
9184 uint32_t tmp;
9185
f458ebbc
DV		 9186 if (!intel_display_power_is_enabled(dev_priv,
9187 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9188 return false;
9189
e143a21c 9190 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9191 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9192
0e8ffe1b
DV		 9193 tmp = I915_READ(PIPECONF(crtc->pipe));
9194 if (!(tmp & PIPECONF_ENABLE))
9195 return false;
9196
42571aef
VS		 9197 switch (tmp & PIPECONF_BPC_MASK) {
9198 case PIPECONF_6BPC:
9199 pipe_config->pipe_bpp = 18;
9200 break;
9201 case PIPECONF_8BPC:
9202 pipe_config->pipe_bpp = 24;
9203 break;
9204 case PIPECONF_10BPC:
9205 pipe_config->pipe_bpp = 30;
9206 break;
9207 case PIPECONF_12BPC:
9208 pipe_config->pipe_bpp = 36;
9209 break;
9210 default:
9211 break;
9212 }
9213
b5a9fa09
DV		 9214 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9215 pipe_config->limited_color_range = true;
9216
ab9412ba 9217 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9218 struct intel_shared_dpll *pll;
9219
88adfff1
DV		 9220 pipe_config->has_pch_encoder = true;
9221
627eb5a3
DV		 9222 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9223 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9224 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9225
9226 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9227
c0d43d62 9228 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9229 pipe_config->shared_dpll =
9230 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9231 } else {
9232 tmp = I915_READ(PCH_DPLL_SEL);
9233 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9234 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9235 else
9236 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9237 }
66e985c0
DV		 9238
9239 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9240
9241 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9242 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9243
9244 tmp = pipe_config->dpll_hw_state.dpll;
9245 pipe_config->pixel_multiplier =
9246 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9247 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9248
9249 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9250 } else {
9251 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9252 }
9253
1bd1bd80
DV		 9254 intel_get_pipe_timings(crtc, pipe_config);
9255
2fa2fe9a
DV		 9256 ironlake_get_pfit_config(crtc, pipe_config);
9257
0e8ffe1b
DV		 9258 return true;
9259}
9260
be256dc7
PZ		 9261static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9262{
9263 struct drm_device *dev = dev_priv->dev;
be256dc7 9264 struct intel_crtc *crtc;
be256dc7 9265
d3fcc808 9266 for_each_intel_crtc(dev, crtc)
e2c719b7 9267 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9268 pipe_name(crtc->pipe));
9269
e2c719b7
RC		 9270 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9271 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
01403de3
VS		 9272 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9273 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
e2c719b7
RC		 9274 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9275 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9276 "CPU PWM1 enabled\n");
c5107b87 9277 if (IS_HASWELL(dev))
e2c719b7 9278 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9279 "CPU PWM2 enabled\n");
e2c719b7 9280 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9281 "PCH PWM1 enabled\n");
e2c719b7 9282 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9283 "Utility pin enabled\n");
e2c719b7 9284 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9285
9926ada1
PZ		 9286 /*
9287 * In theory we can still leave IRQs enabled, as long as only the HPD
9288 * interrupts remain enabled. We used to check for that, but since it's
9289 * gen-specific and since we only disable LCPLL after we fully disable
9290 * the interrupts, the check below should be enough.
9291 */
e2c719b7 9292 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9293}
9294
9ccd5aeb
PZ		 9295static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9296{
9297 struct drm_device *dev = dev_priv->dev;
9298
9299 if (IS_HASWELL(dev))
9300 return I915_READ(D_COMP_HSW);
9301 else
9302 return I915_READ(D_COMP_BDW);
9303}
9304
3c4c9b81
PZ		 9305static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9306{
9307 struct drm_device *dev = dev_priv->dev;
9308
9309 if (IS_HASWELL(dev)) {
9310 mutex_lock(&dev_priv->rps.hw_lock);
9311 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9312 val))
f475dadf 9313 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9314 mutex_unlock(&dev_priv->rps.hw_lock);
9315 } else {
9ccd5aeb
PZ		 9316 I915_WRITE(D_COMP_BDW, val);
9317 POSTING_READ(D_COMP_BDW);
3c4c9b81 9318 }
be256dc7
PZ		 9319}
9320
9321/*
9322 * This function implements pieces of two sequences from BSpec:
9323 * - Sequence for display software to disable LCPLL
9324 * - Sequence for display software to allow package C8+
9325 * The steps implemented here are just the steps that actually touch the LCPLL
9326 * register. Callers should take care of disabling all the display engine
9327 * functions, doing the mode unset, fixing interrupts, etc.
9328 */
6ff58d53
PZ		 9329static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9330 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9331{
9332 uint32_t val;
9333
9334 assert_can_disable_lcpll(dev_priv);
9335
9336 val = I915_READ(LCPLL_CTL);
9337
9338 if (switch_to_fclk) {
9339 val |= LCPLL_CD_SOURCE_FCLK;
9340 I915_WRITE(LCPLL_CTL, val);
9341
9342 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9343 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9344 DRM_ERROR("Switching to FCLK failed\n");
9345
9346 val = I915_READ(LCPLL_CTL);
9347 }
9348
9349 val |= LCPLL_PLL_DISABLE;
9350 I915_WRITE(LCPLL_CTL, val);
9351 POSTING_READ(LCPLL_CTL);
9352
9353 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9354 DRM_ERROR("LCPLL still locked\n");
9355
9ccd5aeb 9356 val = hsw_read_dcomp(dev_priv);
be256dc7 9357 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9358 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9359 ndelay(100);
9360
9ccd5aeb
PZ		 9361 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9362 1))
be256dc7
PZ		 9363 DRM_ERROR("D_COMP RCOMP still in progress\n");
9364
9365 if (allow_power_down) {
9366 val = I915_READ(LCPLL_CTL);
9367 val |= LCPLL_POWER_DOWN_ALLOW;
9368 I915_WRITE(LCPLL_CTL, val);
9369 POSTING_READ(LCPLL_CTL);
9370 }
9371}
9372
9373/*
9374 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9375 * source.
9376 */
6ff58d53 9377static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9378{
9379 uint32_t val;
9380
9381 val = I915_READ(LCPLL_CTL);
9382
9383 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9384 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9385 return;
9386
a8a8bd54
PZ		 9387 /*
9388 * Make sure we're not on PC8 state before disabling PC8, otherwise
9389 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9390 */
59bad947 9391 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9392
be256dc7
PZ		 9393 if (val & LCPLL_POWER_DOWN_ALLOW) {
9394 val &= ~LCPLL_POWER_DOWN_ALLOW;
9395 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9396 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9397 }
9398
9ccd5aeb 9399 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9400 val |= D_COMP_COMP_FORCE;
9401 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9402 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9403
9404 val = I915_READ(LCPLL_CTL);
9405 val &= ~LCPLL_PLL_DISABLE;
9406 I915_WRITE(LCPLL_CTL, val);
9407
9408 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9409 DRM_ERROR("LCPLL not locked yet\n");
9410
9411 if (val & LCPLL_CD_SOURCE_FCLK) {
9412 val = I915_READ(LCPLL_CTL);
9413 val &= ~LCPLL_CD_SOURCE_FCLK;
9414 I915_WRITE(LCPLL_CTL, val);
9415
9416 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9417 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9418 DRM_ERROR("Switching back to LCPLL failed\n");
9419 }
215733fa 9420
59bad947 9421 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9422 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9423}
9424
765dab67
PZ		 9425/*
9426 * Package states C8 and deeper are really deep PC states that can only be
9427 * reached when all the devices on the system allow it, so even if the graphics
9428 * device allows PC8+, it doesn't mean the system will actually get to these
9429 * states. Our driver only allows PC8+ when going into runtime PM.
9430 *
9431 * The requirements for PC8+ are that all the outputs are disabled, the power
9432 * well is disabled and most interrupts are disabled, and these are also
9433 * requirements for runtime PM. When these conditions are met, we manually do
9434 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9435 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9436 * hang the machine.
9437 *
9438 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9439 * the state of some registers, so when we come back from PC8+ we need to
9440 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9441 * need to take care of the registers kept by RC6. Notice that this happens even
9442 * if we don't put the device in PCI D3 state (which is what currently happens
9443 * because of the runtime PM support).
9444 *
9445 * For more, read "Display Sequences for Package C8" on the hardware
9446 * documentation.
9447 */
a14cb6fc 9448void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9449{
c67a470b
PZ		 9450 struct drm_device *dev = dev_priv->dev;
9451 uint32_t val;
9452
c67a470b
PZ		 9453 DRM_DEBUG_KMS("Enabling package C8+\n");
9454
c2699524 9455 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9456 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9457 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9458 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9459 }
9460
9461 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9462 hsw_disable_lcpll(dev_priv, true, true);
9463}
9464
a14cb6fc 9465void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9466{
9467 struct drm_device *dev = dev_priv->dev;
9468 uint32_t val;
9469
c67a470b
PZ		 9470 DRM_DEBUG_KMS("Disabling package C8+\n");
9471
9472 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9473 lpt_init_pch_refclk(dev);
9474
c2699524 9475 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9476 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9477 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9478 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9479 }
9480
9481 intel_prepare_ddi(dev);
c67a470b
PZ		 9482}
9483
27c329ed 9484static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9485{
a821fc46 9486 struct drm_device *dev = old_state->dev;
27c329ed 9487 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9488
27c329ed 9489 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9490}
9491
b432e5cf 9492/* compute the max rate for new configuration */
27c329ed 9493static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9494{
b432e5cf 9495 struct intel_crtc *intel_crtc;
27c329ed 9496 struct intel_crtc_state *crtc_state;
b432e5cf 9497 int max_pixel_rate = 0;
b432e5cf 9498
27c329ed
ML		 9499 for_each_intel_crtc(state->dev, intel_crtc) {
9500 int pixel_rate;
9501
9502 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9503 if (IS_ERR(crtc_state))
9504 return PTR_ERR(crtc_state);
9505
9506 if (!crtc_state->base.enable)
b432e5cf
VS		 9507 continue;
9508
27c329ed 9509 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9510
9511 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9512 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9513 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9514
9515 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9516 }
9517
9518 return max_pixel_rate;
9519}
9520
9521static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9522{
9523 struct drm_i915_private *dev_priv = dev->dev_private;
9524 uint32_t val, data;
9525 int ret;
9526
9527 if (WARN((I915_READ(LCPLL_CTL) &
9528 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9529 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9530 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9531 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9532 "trying to change cdclk frequency with cdclk not enabled\n"))
9533 return;
9534
9535 mutex_lock(&dev_priv->rps.hw_lock);
9536 ret = sandybridge_pcode_write(dev_priv,
9537 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9538 mutex_unlock(&dev_priv->rps.hw_lock);
9539 if (ret) {
9540 DRM_ERROR("failed to inform pcode about cdclk change\n");
9541 return;
9542 }
9543
9544 val = I915_READ(LCPLL_CTL);
9545 val |= LCPLL_CD_SOURCE_FCLK;
9546 I915_WRITE(LCPLL_CTL, val);
9547
9548 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9549 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9550 DRM_ERROR("Switching to FCLK failed\n");
9551
9552 val = I915_READ(LCPLL_CTL);
9553 val &= ~LCPLL_CLK_FREQ_MASK;
9554
9555 switch (cdclk) {
9556 case 450000:
9557 val |= LCPLL_CLK_FREQ_450;
9558 data = 0;
9559 break;
9560 case 540000:
9561 val |= LCPLL_CLK_FREQ_54O_BDW;
9562 data = 1;
9563 break;
9564 case 337500:
9565 val |= LCPLL_CLK_FREQ_337_5_BDW;
9566 data = 2;
9567 break;
9568 case 675000:
9569 val |= LCPLL_CLK_FREQ_675_BDW;
9570 data = 3;
9571 break;
9572 default:
9573 WARN(1, "invalid cdclk frequency\n");
9574 return;
9575 }
9576
9577 I915_WRITE(LCPLL_CTL, val);
9578
9579 val = I915_READ(LCPLL_CTL);
9580 val &= ~LCPLL_CD_SOURCE_FCLK;
9581 I915_WRITE(LCPLL_CTL, val);
9582
9583 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9584 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9585 DRM_ERROR("Switching back to LCPLL failed\n");
9586
9587 mutex_lock(&dev_priv->rps.hw_lock);
9588 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9589 mutex_unlock(&dev_priv->rps.hw_lock);
9590
9591 intel_update_cdclk(dev);
9592
9593 WARN(cdclk != dev_priv->cdclk_freq,
9594 "cdclk requested %d kHz but got %d kHz\n",
9595 cdclk, dev_priv->cdclk_freq);
9596}
9597
27c329ed 9598static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9599{
27c329ed
ML		 9600 struct drm_i915_private *dev_priv = to_i915(state->dev);
9601 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9602 int cdclk;
9603
9604 /*
9605 * FIXME should also account for plane ratio
9606 * once 64bpp pixel formats are supported.
9607 */
27c329ed 9608 if (max_pixclk > 540000)
b432e5cf 9609 cdclk = 675000;
27c329ed 9610 else if (max_pixclk > 450000)
b432e5cf 9611 cdclk = 540000;
27c329ed 9612 else if (max_pixclk > 337500)
b432e5cf
VS		 9613 cdclk = 450000;
9614 else
9615 cdclk = 337500;
9616
9617 /*
9618 * FIXME move the cdclk caclulation to
9619 * compute_config() so we can fail gracegully.
9620 */
9621 if (cdclk > dev_priv->max_cdclk_freq) {
9622 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9623 cdclk, dev_priv->max_cdclk_freq);
9624 cdclk = dev_priv->max_cdclk_freq;
9625 }
9626
27c329ed 9627 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9628
9629 return 0;
9630}
9631
27c329ed 9632static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9633{
27c329ed
ML		 9634 struct drm_device *dev = old_state->dev;
9635 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9636
27c329ed 9637 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9638}
9639
190f68c5
ACO		 9640static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9641 struct intel_crtc_state *crtc_state)
09b4ddf9 9642{
190f68c5 9643 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9644 return -EINVAL;
716c2e55 9645
c7653199 9646 crtc->lowfreq_avail = false;
644cef34 9647
c8f7a0db 9648 return 0;
79e53945
JB		 9649}
9650
3760b59c
S		 9651static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9652 enum port port,
9653 struct intel_crtc_state *pipe_config)
9654{
9655 switch (port) {
9656 case PORT_A:
9657 pipe_config->ddi_pll_sel = SKL_DPLL0;
9658 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9659 break;
9660 case PORT_B:
9661 pipe_config->ddi_pll_sel = SKL_DPLL1;
9662 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9663 break;
9664 case PORT_C:
9665 pipe_config->ddi_pll_sel = SKL_DPLL2;
9666 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9667 break;
9668 default:
9669 DRM_ERROR("Incorrect port type\n");
9670 }
9671}
9672
96b7dfb7
S		 9673static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9674 enum port port,
5cec258b 9675 struct intel_crtc_state *pipe_config)
96b7dfb7 9676{
3148ade7 9677 u32 temp, dpll_ctl1;
96b7dfb7
S		 9678
9679 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9680 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9681
9682 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9683 case SKL_DPLL0:
9684 /*
9685 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9686 * of the shared DPLL framework and thus needs to be read out
9687 * separately
9688 */
9689 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9690 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9691 break;
96b7dfb7
S		 9692 case SKL_DPLL1:
9693 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9694 break;
9695 case SKL_DPLL2:
9696 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9697 break;
9698 case SKL_DPLL3:
9699 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9700 break;
96b7dfb7
S		 9701 }
9702}
9703
7d2c8175
DL		 9704static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9705 enum port port,
5cec258b 9706 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9707{
9708 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9709
9710 switch (pipe_config->ddi_pll_sel) {
9711 case PORT_CLK_SEL_WRPLL1:
9712 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9713 break;
9714 case PORT_CLK_SEL_WRPLL2:
9715 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9716 break;
9717 }
9718}
9719
26804afd 9720static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9721 struct intel_crtc_state *pipe_config)
26804afd
DV		 9722{
9723 struct drm_device *dev = crtc->base.dev;
9724 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9725 struct intel_shared_dpll *pll;
26804afd
DV		 9726 enum port port;
9727 uint32_t tmp;
9728
9729 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9730
9731 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9732
ef11bdb3 9733 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
96b7dfb7 9734 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9735 else if (IS_BROXTON(dev))
9736 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9737 else
9738 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9739
d452c5b6
DV		 9740 if (pipe_config->shared_dpll >= 0) {
9741 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9742
9743 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9744 &pipe_config->dpll_hw_state));
9745 }
9746
26804afd
DV		 9747 /*
9748 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9749 * DDI E. So just check whether this pipe is wired to DDI E and whether
9750 * the PCH transcoder is on.
9751 */
ca370455
DL		 9752 if (INTEL_INFO(dev)->gen < 9 &&
9753 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9754 pipe_config->has_pch_encoder = true;
9755
9756 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9757 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9758 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9759
9760 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9761 }
9762}
9763
0e8ffe1b 9764static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9765 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9766{
9767 struct drm_device *dev = crtc->base.dev;
9768 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9769 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9770 uint32_t tmp;
9771
f458ebbc 9772 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9773 POWER_DOMAIN_PIPE(crtc->pipe)))
9774 return false;
9775
e143a21c 9776 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9777 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9778
eccb140b
DV		 9779 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9780 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9781 enum pipe trans_edp_pipe;
9782 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9783 default:
9784 WARN(1, "unknown pipe linked to edp transcoder\n");
9785 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9786 case TRANS_DDI_EDP_INPUT_A_ON:
9787 trans_edp_pipe = PIPE_A;
9788 break;
9789 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9790 trans_edp_pipe = PIPE_B;
9791 break;
9792 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9793 trans_edp_pipe = PIPE_C;
9794 break;
9795 }
9796
9797 if (trans_edp_pipe == crtc->pipe)
9798 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9799 }
9800
f458ebbc 9801 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9802 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9803 return false;
9804
eccb140b 9805 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9806 if (!(tmp & PIPECONF_ENABLE))
9807 return false;
9808
26804afd 9809 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9810
1bd1bd80
DV		 9811 intel_get_pipe_timings(crtc, pipe_config);
9812
a1b2278e
CK		 9813 if (INTEL_INFO(dev)->gen >= 9) {
9814 skl_init_scalers(dev, crtc, pipe_config);
9815 }
9816
2fa2fe9a 9817 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9818
9819 if (INTEL_INFO(dev)->gen >= 9) {
9820 pipe_config->scaler_state.scaler_id = -1;
9821 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9822 }
9823
bd2e244f 9824 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
1c132b44 9825 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 9826 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9827 else
1c132b44 9828 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 9829 }
88adfff1 9830
e59150dc
JB		 9831 if (IS_HASWELL(dev))
9832 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9833 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9834
ebb69c95
CT		 9835 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9836 pipe_config->pixel_multiplier =
9837 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9838 } else {
9839 pipe_config->pixel_multiplier = 1;
9840 }
6c49f241 9841
0e8ffe1b
DV		 9842 return true;
9843}
9844
560b85bb
CW		 9845static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9846{
9847 struct drm_device *dev = crtc->dev;
9848 struct drm_i915_private *dev_priv = dev->dev_private;
9849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9850 uint32_t cntl = 0, size = 0;
560b85bb 9851
dc41c154 9852 if (base) {
3dd512fb
MR		 9853 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9854 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9855 unsigned int stride = roundup_pow_of_two(width) * 4;
9856
9857 switch (stride) {
9858 default:
9859 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9860 width, stride);
9861 stride = 256;
9862 /* fallthrough */
9863 case 256:
9864 case 512:
9865 case 1024:
9866 case 2048:
9867 break;
4b0e333e
CW		 9868 }
9869
dc41c154
VS		 9870 cntl |= CURSOR_ENABLE |
9871 CURSOR_GAMMA_ENABLE |
9872 CURSOR_FORMAT_ARGB |
9873 CURSOR_STRIDE(stride);
9874
9875 size = (height << 12) | width;
4b0e333e 9876 }
560b85bb 9877
dc41c154
VS		 9878 if (intel_crtc->cursor_cntl != 0 &&
9879 (intel_crtc->cursor_base != base ||
9880 intel_crtc->cursor_size != size ||
9881 intel_crtc->cursor_cntl != cntl)) {
9882 /* On these chipsets we can only modify the base/size/stride
9883 * whilst the cursor is disabled.
9884 */
0b87c24e
VS		 9885 I915_WRITE(CURCNTR(PIPE_A), 0);
9886 POSTING_READ(CURCNTR(PIPE_A));
dc41c154 9887 intel_crtc->cursor_cntl = 0;
4b0e333e 9888 }
560b85bb 9889
99d1f387 9890 if (intel_crtc->cursor_base != base) {
0b87c24e 9891 I915_WRITE(CURBASE(PIPE_A), base);
99d1f387
VS		 9892 intel_crtc->cursor_base = base;
9893 }
4726e0b0 9894
dc41c154
VS		 9895 if (intel_crtc->cursor_size != size) {
9896 I915_WRITE(CURSIZE, size);
9897 intel_crtc->cursor_size = size;
4b0e333e 9898 }
560b85bb 9899
4b0e333e 9900 if (intel_crtc->cursor_cntl != cntl) {
0b87c24e
VS		 9901 I915_WRITE(CURCNTR(PIPE_A), cntl);
9902 POSTING_READ(CURCNTR(PIPE_A));
4b0e333e 9903 intel_crtc->cursor_cntl = cntl;
560b85bb 9904 }
560b85bb
CW		 9905}
9906
560b85bb 9907static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9908{
9909 struct drm_device *dev = crtc->dev;
9910 struct drm_i915_private *dev_priv = dev->dev_private;
9911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9912 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9913 uint32_t cntl;
9914
9915 cntl = 0;
9916 if (base) {
9917 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9918 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9919 case 64:
9920 cntl |= CURSOR_MODE_64_ARGB_AX;
9921 break;
9922 case 128:
9923 cntl |= CURSOR_MODE_128_ARGB_AX;
9924 break;
9925 case 256:
9926 cntl |= CURSOR_MODE_256_ARGB_AX;
9927 break;
9928 default:
3dd512fb 9929 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9930 return;
65a21cd6 9931 }
4b0e333e 9932 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7 9933
fc6f93bc 9934 if (HAS_DDI(dev))
47bf17a7 9935 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9936 }
65a21cd6 9937
8e7d688b 9938 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9939 cntl |= CURSOR_ROTATE_180;
9940
4b0e333e
CW		 9941 if (intel_crtc->cursor_cntl != cntl) {
9942 I915_WRITE(CURCNTR(pipe), cntl);
9943 POSTING_READ(CURCNTR(pipe));
9944 intel_crtc->cursor_cntl = cntl;
65a21cd6 9945 }
4b0e333e 9946
65a21cd6 9947 /* and commit changes on next vblank */
5efb3e28
VS		 9948 I915_WRITE(CURBASE(pipe), base);
9949 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9950
9951 intel_crtc->cursor_base = base;
65a21cd6
JB		 9952}
9953
cda4b7d3 9954/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9955static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9956 bool on)
cda4b7d3
CW		 9957{
9958 struct drm_device *dev = crtc->dev;
9959 struct drm_i915_private *dev_priv = dev->dev_private;
9960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9961 int pipe = intel_crtc->pipe;
9b4101be
ML		 9962 struct drm_plane_state *cursor_state = crtc->cursor->state;
9963 int x = cursor_state->crtc_x;
9964 int y = cursor_state->crtc_y;
d6e4db15 9965 u32 base = 0, pos = 0;
cda4b7d3 9966
d6e4db15 9967 if (on)
cda4b7d3 9968 base = intel_crtc->cursor_addr;
cda4b7d3 9969
6e3c9717 9970 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9971 base = 0;
9972
6e3c9717 9973 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9974 base = 0;
9975
9976 if (x < 0) {
9b4101be 9977 if (x + cursor_state->crtc_w <= 0)
cda4b7d3
CW		 9978 base = 0;
9979
9980 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9981 x = -x;
9982 }
9983 pos |= x << CURSOR_X_SHIFT;
9984
9985 if (y < 0) {
9b4101be 9986 if (y + cursor_state->crtc_h <= 0)
cda4b7d3
CW		 9987 base = 0;
9988
9989 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9990 y = -y;
9991 }
9992 pos |= y << CURSOR_Y_SHIFT;
9993
4b0e333e 9994 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9995 return;
9996
5efb3e28
VS		 9997 I915_WRITE(CURPOS(pipe), pos);
9998
4398ad45
VS		 9999 /* ILK+ do this automagically */
10000 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10001 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9b4101be
ML		 10002 base += (cursor_state->crtc_h *
10003 cursor_state->crtc_w - 1) * 4;
4398ad45
VS		 10004 }
10005
8ac54669 10006 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10007 i845_update_cursor(crtc, base);
10008 else
10009 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10010}
10011
dc41c154
VS		 10012static bool cursor_size_ok(struct drm_device *dev,
10013 uint32_t width, uint32_t height)
10014{
10015 if (width == 0 || height == 0)
10016 return false;
10017
10018 /*
10019 * 845g/865g are special in that they are only limited by
10020 * the width of their cursors, the height is arbitrary up to
10021 * the precision of the register. Everything else requires
10022 * square cursors, limited to a few power-of-two sizes.
10023 */
10024 if (IS_845G(dev) || IS_I865G(dev)) {
10025 if ((width & 63) != 0)
10026 return false;
10027
10028 if (width > (IS_845G(dev) ? 64 : 512))
10029 return false;
10030
10031 if (height > 1023)
10032 return false;
10033 } else {
10034 switch (width | height) {
10035 case 256:
10036 case 128:
10037 if (IS_GEN2(dev))
10038 return false;
10039 case 64:
10040 break;
10041 default:
10042 return false;
10043 }
10044 }
10045
10046 return true;
10047}
10048
79e53945 10049static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10050 u16 *blue, uint32_t start, uint32_t size)
79e53945 10051{
7203425a 10052 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10054
7203425a 10055 for (i = start; i < end; i++) {
79e53945
JB		 10056 intel_crtc->lut_r[i] = red[i] >> 8;
10057 intel_crtc->lut_g[i] = green[i] >> 8;
10058 intel_crtc->lut_b[i] = blue[i] >> 8;
10059 }
10060
10061 intel_crtc_load_lut(crtc);
10062}
10063
79e53945
JB		 10064/* VESA 640x480x72Hz mode to set on the pipe */
10065static struct drm_display_mode load_detect_mode = {
10066 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10067 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10068};
10069
a8bb6818
DV		 10070struct drm_framebuffer *
10071__intel_framebuffer_create(struct drm_device *dev,
10072 struct drm_mode_fb_cmd2 *mode_cmd,
10073 struct drm_i915_gem_object *obj)
d2dff872
CW		 10074{
10075 struct intel_framebuffer *intel_fb;
10076 int ret;
10077
10078 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
dcb1394e 10079 if (!intel_fb)
d2dff872 10080 return ERR_PTR(-ENOMEM);
d2dff872
CW		 10081
10082 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10083 if (ret)
10084 goto err;
d2dff872
CW		 10085
10086 return &intel_fb->base;
dcb1394e 10087
dd4916c5 10088err:
dd4916c5 10089 kfree(intel_fb);
dd4916c5 10090 return ERR_PTR(ret);
d2dff872
CW		 10091}
10092
b5ea642a 10093static struct drm_framebuffer *
a8bb6818
DV		 10094intel_framebuffer_create(struct drm_device *dev,
10095 struct drm_mode_fb_cmd2 *mode_cmd,
10096 struct drm_i915_gem_object *obj)
10097{
10098 struct drm_framebuffer *fb;
10099 int ret;
10100
10101 ret = i915_mutex_lock_interruptible(dev);
10102 if (ret)
10103 return ERR_PTR(ret);
10104 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10105 mutex_unlock(&dev->struct_mutex);
10106
10107 return fb;
10108}
10109
d2dff872
CW		 10110static u32
10111intel_framebuffer_pitch_for_width(int width, int bpp)
10112{
10113 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10114 return ALIGN(pitch, 64);
10115}
10116
10117static u32
10118intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10119{
10120 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10121 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10122}
10123
10124static struct drm_framebuffer *
10125intel_framebuffer_create_for_mode(struct drm_device *dev,
10126 struct drm_display_mode *mode,
10127 int depth, int bpp)
10128{
dcb1394e 10129 struct drm_framebuffer *fb;
d2dff872 10130 struct drm_i915_gem_object *obj;
0fed39bd 10131 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10132
10133 obj = i915_gem_alloc_object(dev,
10134 intel_framebuffer_size_for_mode(mode, bpp));
10135 if (obj == NULL)
10136 return ERR_PTR(-ENOMEM);
10137
10138 mode_cmd.width = mode->hdisplay;
10139 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10140 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10141 bpp);
5ca0c34a 10142 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872 10143
dcb1394e
LW		 10144 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10145 if (IS_ERR(fb))
10146 drm_gem_object_unreference_unlocked(&obj->base);
10147
10148 return fb;
d2dff872
CW		 10149}
10150
10151static struct drm_framebuffer *
10152mode_fits_in_fbdev(struct drm_device *dev,
10153 struct drm_display_mode *mode)
10154{
0695726e 10155#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10156 struct drm_i915_private *dev_priv = dev->dev_private;
10157 struct drm_i915_gem_object *obj;
10158 struct drm_framebuffer *fb;
10159
4c0e5528 10160 if (!dev_priv->fbdev)
d2dff872
CW		 10161 return NULL;
10162
4c0e5528 10163 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10164 return NULL;
10165
4c0e5528
DV		 10166 obj = dev_priv->fbdev->fb->obj;
10167 BUG_ON(!obj);
10168
8bcd4553 10169 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10170 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10171 fb->bits_per_pixel))
d2dff872
CW		 10172 return NULL;
10173
01f2c773 10174 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10175 return NULL;
10176
10177 return fb;
4520f53a
DV		 10178#else
10179 return NULL;
10180#endif
d2dff872
CW		 10181}
10182
d3a40d1b
ACO		 10183static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10184 struct drm_crtc *crtc,
10185 struct drm_display_mode *mode,
10186 struct drm_framebuffer *fb,
10187 int x, int y)
10188{
10189 struct drm_plane_state *plane_state;
10190 int hdisplay, vdisplay;
10191 int ret;
10192
10193 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10194 if (IS_ERR(plane_state))
10195 return PTR_ERR(plane_state);
10196
10197 if (mode)
10198 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10199 else
10200 hdisplay = vdisplay = 0;
10201
10202 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10203 if (ret)
10204 return ret;
10205 drm_atomic_set_fb_for_plane(plane_state, fb);
10206 plane_state->crtc_x = 0;
10207 plane_state->crtc_y = 0;
10208 plane_state->crtc_w = hdisplay;
10209 plane_state->crtc_h = vdisplay;
10210 plane_state->src_x = x << 16;
10211 plane_state->src_y = y << 16;
10212 plane_state->src_w = hdisplay << 16;
10213 plane_state->src_h = vdisplay << 16;
10214
10215 return 0;
10216}
10217
d2434ab7 10218bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10219 struct drm_display_mode *mode,
51fd371b
RC		 10220 struct intel_load_detect_pipe *old,
10221 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10222{
10223 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10224 struct intel_encoder *intel_encoder =
10225 intel_attached_encoder(connector);
79e53945 10226 struct drm_crtc *possible_crtc;
4ef69c7a 10227 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10228 struct drm_crtc *crtc = NULL;
10229 struct drm_device *dev = encoder->dev;
94352cf9 10230 struct drm_framebuffer *fb;
51fd371b 10231 struct drm_mode_config *config = &dev->mode_config;
83a57153 10232 struct drm_atomic_state *state = NULL;
944b0c76 10233 struct drm_connector_state *connector_state;
4be07317 10234 struct intel_crtc_state *crtc_state;
51fd371b 10235 int ret, i = -1;
79e53945 10236
d2dff872 10237 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10238 connector->base.id, connector->name,
8e329a03 10239 encoder->base.id, encoder->name);
d2dff872 10240
51fd371b
RC		 10241retry:
10242 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10243 if (ret)
ad3c558f 10244 goto fail;
6e9f798d 10245
79e53945
JB		 10246 /*
10247 * Algorithm gets a little messy:
7a5e4805 10248 *
79e53945
JB		 10249 * - if the connector already has an assigned crtc, use it (but make
10250 * sure it's on first)
7a5e4805 10251 *
79e53945
JB		 10252 * - try to find the first unused crtc that can drive this connector,
10253 * and use that if we find one
79e53945
JB		 10254 */
10255
10256 /* See if we already have a CRTC for this connector */
10257 if (encoder->crtc) {
10258 crtc = encoder->crtc;
8261b191 10259
51fd371b 10260 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10261 if (ret)
ad3c558f 10262 goto fail;
4d02e2de 10263 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10264 if (ret)
ad3c558f 10265 goto fail;
7b24056b 10266
24218aac 10267 old->dpms_mode = connector->dpms;
8261b191
CW		 10268 old->load_detect_temp = false;
10269
10270 /* Make sure the crtc and connector are running */
24218aac
DV		 10271 if (connector->dpms != DRM_MODE_DPMS_ON)
10272 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10273
7173188d 10274 return true;
79e53945
JB		 10275 }
10276
10277 /* Find an unused one (if possible) */
70e1e0ec 10278 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10279 i++;
10280 if (!(encoder->possible_crtcs & (1 << i)))
10281 continue;
83d65738 10282 if (possible_crtc->state->enable)
a459249c 10283 continue;
a459249c
VS		 10284
10285 crtc = possible_crtc;
10286 break;
79e53945
JB		 10287 }
10288
10289 /*
10290 * If we didn't find an unused CRTC, don't use any.
10291 */
10292 if (!crtc) {
7173188d 10293 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10294 goto fail;
79e53945
JB		 10295 }
10296
51fd371b
RC		 10297 ret = drm_modeset_lock(&crtc->mutex, ctx);
10298 if (ret)
ad3c558f 10299 goto fail;
4d02e2de
DV		 10300 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10301 if (ret)
ad3c558f 10302 goto fail;
79e53945
JB		 10303
10304 intel_crtc = to_intel_crtc(crtc);
24218aac 10305 old->dpms_mode = connector->dpms;
8261b191 10306 old->load_detect_temp = true;
d2dff872 10307 old->release_fb = NULL;
79e53945 10308
83a57153
ACO		 10309 state = drm_atomic_state_alloc(dev);
10310 if (!state)
10311 return false;
10312
10313 state->acquire_ctx = ctx;
10314
944b0c76
ACO		 10315 connector_state = drm_atomic_get_connector_state(state, connector);
10316 if (IS_ERR(connector_state)) {
10317 ret = PTR_ERR(connector_state);
10318 goto fail;
10319 }
10320
10321 connector_state->crtc = crtc;
10322 connector_state->best_encoder = &intel_encoder->base;
10323
4be07317
ACO		 10324 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10325 if (IS_ERR(crtc_state)) {
10326 ret = PTR_ERR(crtc_state);
10327 goto fail;
10328 }
10329
49d6fa21 10330 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10331
6492711d
CW		 10332 if (!mode)
10333 mode = &load_detect_mode;
79e53945 10334
d2dff872
CW		 10335 /* We need a framebuffer large enough to accommodate all accesses
10336 * that the plane may generate whilst we perform load detection.
10337 * We can not rely on the fbcon either being present (we get called
10338 * during its initialisation to detect all boot displays, or it may
10339 * not even exist) or that it is large enough to satisfy the
10340 * requested mode.
10341 */
94352cf9
DV		 10342 fb = mode_fits_in_fbdev(dev, mode);
10343 if (fb == NULL) {
d2dff872 10344 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10345 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10346 old->release_fb = fb;
d2dff872
CW		 10347 } else
10348 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10349 if (IS_ERR(fb)) {
d2dff872 10350 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10351 goto fail;
79e53945 10352 }
79e53945 10353
d3a40d1b
ACO		 10354 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10355 if (ret)
10356 goto fail;
10357
8c7b5ccb
ACO		 10358 drm_mode_copy(&crtc_state->base.mode, mode);
10359
74c090b1 10360 if (drm_atomic_commit(state)) {
6492711d 10361 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10362 if (old->release_fb)
10363 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10364 goto fail;
79e53945 10365 }
9128b040 10366 crtc->primary->crtc = crtc;
7173188d 10367
79e53945 10368 /* let the connector get through one full cycle before testing */
9d0498a2 10369 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10370 return true;
412b61d8 10371
ad3c558f 10372fail:
e5d958ef
ACO		 10373 drm_atomic_state_free(state);
10374 state = NULL;
83a57153 10375
51fd371b
RC		 10376 if (ret == -EDEADLK) {
10377 drm_modeset_backoff(ctx);
10378 goto retry;
10379 }
10380
412b61d8 10381 return false;
79e53945
JB		 10382}
10383
d2434ab7 10384void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10385 struct intel_load_detect_pipe *old,
10386 struct drm_modeset_acquire_ctx *ctx)
79e53945 10387{
83a57153 10388 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10389 struct intel_encoder *intel_encoder =
10390 intel_attached_encoder(connector);
4ef69c7a 10391 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10392 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10394 struct drm_atomic_state *state;
944b0c76 10395 struct drm_connector_state *connector_state;
4be07317 10396 struct intel_crtc_state *crtc_state;
d3a40d1b 10397 int ret;
79e53945 10398
d2dff872 10399 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10400 connector->base.id, connector->name,
8e329a03 10401 encoder->base.id, encoder->name);
d2dff872 10402
8261b191 10403 if (old->load_detect_temp) {
83a57153 10404 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10405 if (!state)
10406 goto fail;
83a57153
ACO		 10407
10408 state->acquire_ctx = ctx;
10409
944b0c76
ACO		 10410 connector_state = drm_atomic_get_connector_state(state, connector);
10411 if (IS_ERR(connector_state))
10412 goto fail;
10413
4be07317
ACO		 10414 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10415 if (IS_ERR(crtc_state))
10416 goto fail;
10417
944b0c76
ACO		 10418 connector_state->best_encoder = NULL;
10419 connector_state->crtc = NULL;
10420
49d6fa21 10421 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10422
d3a40d1b
ACO		 10423 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10424 0, 0);
10425 if (ret)
10426 goto fail;
10427
74c090b1 10428 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10429 if (ret)
10430 goto fail;
d2dff872 10431
36206361
DV		 10432 if (old->release_fb) {
10433 drm_framebuffer_unregister_private(old->release_fb);
10434 drm_framebuffer_unreference(old->release_fb);
10435 }
d2dff872 10436
0622a53c 10437 return;
79e53945
JB		 10438 }
10439
c751ce4f 10440 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10441 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10442 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10443
10444 return;
10445fail:
10446 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10447 drm_atomic_state_free(state);
79e53945
JB		 10448}
10449
da4a1efa 10450static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10451 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10452{
10453 struct drm_i915_private *dev_priv = dev->dev_private;
10454 u32 dpll = pipe_config->dpll_hw_state.dpll;
10455
10456 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10457 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10458 else if (HAS_PCH_SPLIT(dev))
10459 return 120000;
10460 else if (!IS_GEN2(dev))
10461 return 96000;
10462 else
10463 return 48000;
10464}
10465
79e53945 10466/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10467static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10468 struct intel_crtc_state *pipe_config)
79e53945 10469{
f1f644dc 10470 struct drm_device *dev = crtc->base.dev;
79e53945 10471 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10472 int pipe = pipe_config->cpu_transcoder;
293623f7 10473 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10474 u32 fp;
10475 intel_clock_t clock;
dccbea3b 10476 int port_clock;
da4a1efa 10477 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10478
10479 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10480 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10481 else
293623f7 10482 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10483
10484 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10485 if (IS_PINEVIEW(dev)) {
10486 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10487 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10488 } else {
10489 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10490 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10491 }
10492
a6c45cf0 10493 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10494 if (IS_PINEVIEW(dev))
10495 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10496 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10497 else
10498 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10499 DPLL_FPA01_P1_POST_DIV_SHIFT);
10500
10501 switch (dpll & DPLL_MODE_MASK) {
10502 case DPLLB_MODE_DAC_SERIAL:
10503 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10504 5 : 10;
10505 break;
10506 case DPLLB_MODE_LVDS:
10507 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10508 7 : 14;
10509 break;
10510 default:
28c97730 10511 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10512 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10513 return;
79e53945
JB		 10514 }
10515
ac58c3f0 10516 if (IS_PINEVIEW(dev))
dccbea3b 10517 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10518 else
dccbea3b 10519 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10520 } else {
0fb58223 10521 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10522 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10523
10524 if (is_lvds) {
10525 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10526 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10527
10528 if (lvds & LVDS_CLKB_POWER_UP)
10529 clock.p2 = 7;
10530 else
10531 clock.p2 = 14;
79e53945
JB		 10532 } else {
10533 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10534 clock.p1 = 2;
10535 else {
10536 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10537 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10538 }
10539 if (dpll & PLL_P2_DIVIDE_BY_4)
10540 clock.p2 = 4;
10541 else
10542 clock.p2 = 2;
79e53945 10543 }
da4a1efa 10544
dccbea3b 10545 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10546 }
10547
18442d08
VS		 10548 /*
10549 * This value includes pixel_multiplier. We will use
241bfc38 10550 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10551 * encoder's get_config() function.
10552 */
dccbea3b 10553 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10554}
10555
6878da05
VS		 10556int intel_dotclock_calculate(int link_freq,
10557 const struct intel_link_m_n *m_n)
f1f644dc 10558{
f1f644dc
JB		 10559 /*
10560 * The calculation for the data clock is:
1041a02f 10561 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10562 * But we want to avoid losing precison if possible, so:
1041a02f 10563 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10564 *
10565 * and the link clock is simpler:
1041a02f 10566 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10567 */
10568
6878da05
VS		 10569 if (!m_n->link_n)
10570 return 0;
f1f644dc 10571
6878da05
VS		 10572 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10573}
f1f644dc 10574
18442d08 10575static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10576 struct intel_crtc_state *pipe_config)
6878da05
VS		 10577{
10578 struct drm_device *dev = crtc->base.dev;
79e53945 10579
18442d08
VS		 10580 /* read out port_clock from the DPLL */
10581 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10582
f1f644dc 10583 /*
18442d08 10584 * This value does not include pixel_multiplier.
241bfc38 10585 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10586 * agree once we know their relationship in the encoder's
10587 * get_config() function.
79e53945 10588 */
2d112de7 10589 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10590 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10591 &pipe_config->fdi_m_n);
79e53945
JB		 10592}
10593
10594/** Returns the currently programmed mode of the given pipe. */
10595struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10596 struct drm_crtc *crtc)
10597{
548f245b 10598 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10600 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10601 struct drm_display_mode *mode;
5cec258b 10602 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10603 int htot = I915_READ(HTOTAL(cpu_transcoder));
10604 int hsync = I915_READ(HSYNC(cpu_transcoder));
10605 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10606 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10607 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10608
10609 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10610 if (!mode)
10611 return NULL;
10612
f1f644dc
JB		 10613 /*
10614 * Construct a pipe_config sufficient for getting the clock info
10615 * back out of crtc_clock_get.
10616 *
10617 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10618 * to use a real value here instead.
10619 */
293623f7 10620 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10621 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10622 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10623 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10624 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10625 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10626
773ae034 10627 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10628 mode->hdisplay = (htot & 0xffff) + 1;
10629 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10630 mode->hsync_start = (hsync & 0xffff) + 1;
10631 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10632 mode->vdisplay = (vtot & 0xffff) + 1;
10633 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10634 mode->vsync_start = (vsync & 0xffff) + 1;
10635 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10636
10637 drm_mode_set_name(mode);
79e53945
JB		 10638
10639 return mode;
10640}
10641
f047e395
CW		 10642void intel_mark_busy(struct drm_device *dev)
10643{
c67a470b
PZ		 10644 struct drm_i915_private *dev_priv = dev->dev_private;
10645
f62a0076
CW		 10646 if (dev_priv->mm.busy)
10647 return;
10648
43694d69 10649 intel_runtime_pm_get(dev_priv);
c67a470b 10650 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10651 if (INTEL_INFO(dev)->gen >= 6)
10652 gen6_rps_busy(dev_priv);
f62a0076 10653 dev_priv->mm.busy = true;
f047e395
CW		 10654}
10655
10656void intel_mark_idle(struct drm_device *dev)
652c393a 10657{
c67a470b 10658 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10659
f62a0076
CW		 10660 if (!dev_priv->mm.busy)
10661 return;
10662
10663 dev_priv->mm.busy = false;
10664
3d13ef2e 10665 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10666 gen6_rps_idle(dev->dev_private);
bb4cdd53 10667
43694d69 10668 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10669}
10670
79e53945
JB		 10671static void intel_crtc_destroy(struct drm_crtc *crtc)
10672{
10673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10674 struct drm_device *dev = crtc->dev;
10675 struct intel_unpin_work *work;
67e77c5a 10676
5e2d7afc 10677 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10678 work = intel_crtc->unpin_work;
10679 intel_crtc->unpin_work = NULL;
5e2d7afc 10680 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10681
10682 if (work) {
10683 cancel_work_sync(&work->work);
10684 kfree(work);
10685 }
79e53945
JB		 10686
10687 drm_crtc_cleanup(crtc);
67e77c5a 10688
79e53945
JB		 10689 kfree(intel_crtc);
10690}
10691
6b95a207
KH		 10692static void intel_unpin_work_fn(struct work_struct *__work)
10693{
10694 struct intel_unpin_work *work =
10695 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10696 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10697 struct drm_device *dev = crtc->base.dev;
10698 struct drm_plane *primary = crtc->base.primary;
6b95a207 10699
b4a98e57 10700 mutex_lock(&dev->struct_mutex);
a9ff8714 10701 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10702 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10703
f06cc1b9 10704 if (work->flip_queued_req)
146d84f0 10705 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10706 mutex_unlock(&dev->struct_mutex);
10707
a9ff8714 10708 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10709 drm_framebuffer_unreference(work->old_fb);
f99d7069 10710
a9ff8714
VS		 10711 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10712 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10713
6b95a207
KH		 10714 kfree(work);
10715}
10716
1afe3e9d 10717static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10718 struct drm_crtc *crtc)
6b95a207 10719{
6b95a207
KH		 10720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10721 struct intel_unpin_work *work;
6b95a207
KH		 10722 unsigned long flags;
10723
10724 /* Ignore early vblank irqs */
10725 if (intel_crtc == NULL)
10726 return;
10727
f326038a
DV		 10728 /*
10729 * This is called both by irq handlers and the reset code (to complete
10730 * lost pageflips) so needs the full irqsave spinlocks.
10731 */
6b95a207
KH		 10732 spin_lock_irqsave(&dev->event_lock, flags);
10733 work = intel_crtc->unpin_work;
e7d841ca
CW		 10734
10735 /* Ensure we don't miss a work->pending update ... */
10736 smp_rmb();
10737
10738 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10739 spin_unlock_irqrestore(&dev->event_lock, flags);
10740 return;
10741 }
10742
d6bbafa1 10743 page_flip_completed(intel_crtc);
0af7e4df 10744
6b95a207 10745 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10746}
10747
1afe3e9d
JB		 10748void intel_finish_page_flip(struct drm_device *dev, int pipe)
10749{
fbee40df 10750 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10751 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10752
49b14a5c 10753 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10754}
10755
10756void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10757{
fbee40df 10758 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10759 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10760
49b14a5c 10761 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10762}
10763
75f7f3ec
VS		 10764/* Is 'a' after or equal to 'b'? */
10765static bool g4x_flip_count_after_eq(u32 a, u32 b)
10766{
10767 return !((a - b) & 0x80000000);
10768}
10769
10770static bool page_flip_finished(struct intel_crtc *crtc)
10771{
10772 struct drm_device *dev = crtc->base.dev;
10773 struct drm_i915_private *dev_priv = dev->dev_private;
10774
bdfa7542
VS		 10775 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10776 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10777 return true;
10778
75f7f3ec
VS		 10779 /*
10780 * The relevant registers doen't exist on pre-ctg.
10781 * As the flip done interrupt doesn't trigger for mmio
10782 * flips on gmch platforms, a flip count check isn't
10783 * really needed there. But since ctg has the registers,
10784 * include it in the check anyway.
10785 */
10786 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10787 return true;
10788
10789 /*
10790 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10791 * used the same base address. In that case the mmio flip might
10792 * have completed, but the CS hasn't even executed the flip yet.
10793 *
10794 * A flip count check isn't enough as the CS might have updated
10795 * the base address just after start of vblank, but before we
10796 * managed to process the interrupt. This means we'd complete the
10797 * CS flip too soon.
10798 *
10799 * Combining both checks should get us a good enough result. It may
10800 * still happen that the CS flip has been executed, but has not
10801 * yet actually completed. But in case the base address is the same
10802 * anyway, we don't really care.
10803 */
10804 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10805 crtc->unpin_work->gtt_offset &&
fd8f507c 10806 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
75f7f3ec
VS		 10807 crtc->unpin_work->flip_count);
10808}
10809
6b95a207
KH		 10810void intel_prepare_page_flip(struct drm_device *dev, int plane)
10811{
fbee40df 10812 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10813 struct intel_crtc *intel_crtc =
10814 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10815 unsigned long flags;
10816
f326038a
DV		 10817
10818 /*
10819 * This is called both by irq handlers and the reset code (to complete
10820 * lost pageflips) so needs the full irqsave spinlocks.
10821 *
10822 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10823 * generate a page-flip completion irq, i.e. every modeset
10824 * is also accompanied by a spurious intel_prepare_page_flip().
10825 */
6b95a207 10826 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10827 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10828 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10829 spin_unlock_irqrestore(&dev->event_lock, flags);
10830}
10831
6042639c 10832static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
e7d841ca
CW		 10833{
10834 /* Ensure that the work item is consistent when activating it ... */
10835 smp_wmb();
6042639c 10836 atomic_set(&work->pending, INTEL_FLIP_PENDING);
e7d841ca
CW		 10837 /* and that it is marked active as soon as the irq could fire. */
10838 smp_wmb();
10839}
10840
8c9f3aaf
JB		 10841static int intel_gen2_queue_flip(struct drm_device *dev,
10842 struct drm_crtc *crtc,
10843 struct drm_framebuffer *fb,
ed8d1975 10844 struct drm_i915_gem_object *obj,
6258fbe2 10845 struct drm_i915_gem_request *req,
ed8d1975 10846 uint32_t flags)
8c9f3aaf 10847{
6258fbe2 10848 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10850 u32 flip_mask;
10851 int ret;
10852
5fb9de1a 10853 ret = intel_ring_begin(req, 6);
8c9f3aaf 10854 if (ret)
4fa62c89 10855 return ret;
8c9f3aaf
JB		 10856
10857 /* Can't queue multiple flips, so wait for the previous
10858 * one to finish before executing the next.
10859 */
10860 if (intel_crtc->plane)
10861 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10862 else
10863 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10864 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10865 intel_ring_emit(ring, MI_NOOP);
10866 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10867 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10868 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10869 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10870 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca 10871
6042639c 10872 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10873 return 0;
8c9f3aaf
JB		 10874}
10875
10876static int intel_gen3_queue_flip(struct drm_device *dev,
10877 struct drm_crtc *crtc,
10878 struct drm_framebuffer *fb,
ed8d1975 10879 struct drm_i915_gem_object *obj,
6258fbe2 10880 struct drm_i915_gem_request *req,
ed8d1975 10881 uint32_t flags)
8c9f3aaf 10882{
6258fbe2 10883 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10885 u32 flip_mask;
10886 int ret;
10887
5fb9de1a 10888 ret = intel_ring_begin(req, 6);
8c9f3aaf 10889 if (ret)
4fa62c89 10890 return ret;
8c9f3aaf
JB		 10891
10892 if (intel_crtc->plane)
10893 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10894 else
10895 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10896 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10897 intel_ring_emit(ring, MI_NOOP);
10898 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10899 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10900 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10901 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10902 intel_ring_emit(ring, MI_NOOP);
10903
6042639c 10904 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10905 return 0;
8c9f3aaf
JB		 10906}
10907
10908static int intel_gen4_queue_flip(struct drm_device *dev,
10909 struct drm_crtc *crtc,
10910 struct drm_framebuffer *fb,
ed8d1975 10911 struct drm_i915_gem_object *obj,
6258fbe2 10912 struct drm_i915_gem_request *req,
ed8d1975 10913 uint32_t flags)
8c9f3aaf 10914{
6258fbe2 10915 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10916 struct drm_i915_private *dev_priv = dev->dev_private;
10917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10918 uint32_t pf, pipesrc;
10919 int ret;
10920
5fb9de1a 10921 ret = intel_ring_begin(req, 4);
8c9f3aaf 10922 if (ret)
4fa62c89 10923 return ret;
8c9f3aaf
JB		 10924
10925 /* i965+ uses the linear or tiled offsets from the
10926 * Display Registers (which do not change across a page-flip)
10927 * so we need only reprogram the base address.
10928 */
6d90c952
DV		 10929 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10930 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10931 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10932 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10933 obj->tiling_mode);
8c9f3aaf
JB		 10934
10935 /* XXX Enabling the panel-fitter across page-flip is so far
10936 * untested on non-native modes, so ignore it for now.
10937 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10938 */
10939 pf = 0;
10940 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10941 intel_ring_emit(ring, pf | pipesrc);
e7d841ca 10942
6042639c 10943 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10944 return 0;
8c9f3aaf
JB		 10945}
10946
10947static int intel_gen6_queue_flip(struct drm_device *dev,
10948 struct drm_crtc *crtc,
10949 struct drm_framebuffer *fb,
ed8d1975 10950 struct drm_i915_gem_object *obj,
6258fbe2 10951 struct drm_i915_gem_request *req,
ed8d1975 10952 uint32_t flags)
8c9f3aaf 10953{
6258fbe2 10954 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10955 struct drm_i915_private *dev_priv = dev->dev_private;
10956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10957 uint32_t pf, pipesrc;
10958 int ret;
10959
5fb9de1a 10960 ret = intel_ring_begin(req, 4);
8c9f3aaf 10961 if (ret)
4fa62c89 10962 return ret;
8c9f3aaf 10963
6d90c952
DV		 10964 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10965 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10966 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10967 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10968
dc257cf1
DV		 10969 /* Contrary to the suggestions in the documentation,
10970 * "Enable Panel Fitter" does not seem to be required when page
10971 * flipping with a non-native mode, and worse causes a normal
10972 * modeset to fail.
10973 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10974 */
10975 pf = 0;
8c9f3aaf 10976 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10977 intel_ring_emit(ring, pf | pipesrc);
e7d841ca 10978
6042639c 10979 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10980 return 0;
8c9f3aaf
JB		 10981}
10982
7c9017e5
JB		 10983static int intel_gen7_queue_flip(struct drm_device *dev,
10984 struct drm_crtc *crtc,
10985 struct drm_framebuffer *fb,
ed8d1975 10986 struct drm_i915_gem_object *obj,
6258fbe2 10987 struct drm_i915_gem_request *req,
ed8d1975 10988 uint32_t flags)
7c9017e5 10989{
6258fbe2 10990 struct intel_engine_cs *ring = req->ring;
7c9017e5 10991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10992 uint32_t plane_bit = 0;
ffe74d75
CW		 10993 int len, ret;
10994
eba905b2 10995 switch (intel_crtc->plane) {
cb05d8de
DV		 10996 case PLANE_A:
10997 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10998 break;
10999 case PLANE_B:
11000 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11001 break;
11002 case PLANE_C:
11003 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11004 break;
11005 default:
11006 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11007 return -ENODEV;
cb05d8de
DV		 11008 }
11009
ffe74d75 11010 len = 4;
f476828a 11011 if (ring->id == RCS) {
ffe74d75 11012 len += 6;
f476828a
DL		 11013 /*
11014 * On Gen 8, SRM is now taking an extra dword to accommodate
11015 * 48bits addresses, and we need a NOOP for the batch size to
11016 * stay even.
11017 */
11018 if (IS_GEN8(dev))
11019 len += 2;
11020 }
ffe74d75 11021
f66fab8e
VS		 11022 /*
11023 * BSpec MI_DISPLAY_FLIP for IVB:
11024 * "The full packet must be contained within the same cache line."
11025 *
11026 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11027 * cacheline, if we ever start emitting more commands before
11028 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11029 * then do the cacheline alignment, and finally emit the
11030 * MI_DISPLAY_FLIP.
11031 */
bba09b12 11032 ret = intel_ring_cacheline_align(req);
f66fab8e 11033 if (ret)
4fa62c89 11034 return ret;
f66fab8e 11035
5fb9de1a 11036 ret = intel_ring_begin(req, len);
7c9017e5 11037 if (ret)
4fa62c89 11038 return ret;
7c9017e5 11039
ffe74d75
CW		 11040 /* Unmask the flip-done completion message. Note that the bspec says that
11041 * we should do this for both the BCS and RCS, and that we must not unmask
11042 * more than one flip event at any time (or ensure that one flip message
11043 * can be sent by waiting for flip-done prior to queueing new flips).
11044 * Experimentation says that BCS works despite DERRMR masking all
11045 * flip-done completion events and that unmasking all planes at once
11046 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11047 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11048 */
11049 if (ring->id == RCS) {
11050 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11051 intel_ring_emit(ring, DERRMR);
11052 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11053 DERRMR_PIPEB_PRI_FLIP_DONE |
11054 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11055 if (IS_GEN8(dev))
f1afe24f 11056 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11057 MI_SRM_LRM_GLOBAL_GTT);
11058 else
f1afe24f 11059 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11060 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11061 intel_ring_emit(ring, DERRMR);
11062 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11063 if (IS_GEN8(dev)) {
11064 intel_ring_emit(ring, 0);
11065 intel_ring_emit(ring, MI_NOOP);
11066 }
ffe74d75
CW		 11067 }
11068
cb05d8de 11069 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11070 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11071 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11072 intel_ring_emit(ring, (MI_NOOP));
e7d841ca 11073
6042639c 11074 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 11075 return 0;
7c9017e5
JB		 11076}
11077
84c33a64
SG		 11078static bool use_mmio_flip(struct intel_engine_cs *ring,
11079 struct drm_i915_gem_object *obj)
11080{
11081 /*
11082 * This is not being used for older platforms, because
11083 * non-availability of flip done interrupt forces us to use
11084 * CS flips. Older platforms derive flip done using some clever
11085 * tricks involving the flip_pending status bits and vblank irqs.
11086 * So using MMIO flips there would disrupt this mechanism.
11087 */
11088
8e09bf83
CW		 11089 if (ring == NULL)
11090 return true;
11091
84c33a64
SG		 11092 if (INTEL_INFO(ring->dev)->gen < 5)
11093 return false;
11094
11095 if (i915.use_mmio_flip < 0)
11096 return false;
11097 else if (i915.use_mmio_flip > 0)
11098 return true;
14bf993e
OM		 11099 else if (i915.enable_execlists)
11100 return true;
84c33a64 11101 else
b4716185 11102 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11103}
11104
6042639c 11105static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
86efe24a 11106 unsigned int rotation,
6042639c 11107 struct intel_unpin_work *work)
ff944564
DL		 11108{
11109 struct drm_device *dev = intel_crtc->base.dev;
11110 struct drm_i915_private *dev_priv = dev->dev_private;
11111 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564 11112 const enum pipe pipe = intel_crtc->pipe;
86efe24a 11113 u32 ctl, stride, tile_height;
ff944564
DL		 11114
11115 ctl = I915_READ(PLANE_CTL(pipe, 0));
11116 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11117 switch (fb->modifier[0]) {
11118 case DRM_FORMAT_MOD_NONE:
11119 break;
11120 case I915_FORMAT_MOD_X_TILED:
ff944564 11121 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11122 break;
11123 case I915_FORMAT_MOD_Y_TILED:
11124 ctl |= PLANE_CTL_TILED_Y;
11125 break;
11126 case I915_FORMAT_MOD_Yf_TILED:
11127 ctl |= PLANE_CTL_TILED_YF;
11128 break;
11129 default:
11130 MISSING_CASE(fb->modifier[0]);
11131 }
ff944564
DL		 11132
11133 /*
11134 * The stride is either expressed as a multiple of 64 bytes chunks for
11135 * linear buffers or in number of tiles for tiled buffers.
11136 */
86efe24a
TU		 11137 if (intel_rotation_90_or_270(rotation)) {
11138 /* stride = Surface height in tiles */
11139 tile_height = intel_tile_height(dev, fb->pixel_format,
11140 fb->modifier[0], 0);
11141 stride = DIV_ROUND_UP(fb->height, tile_height);
11142 } else {
11143 stride = fb->pitches[0] /
11144 intel_fb_stride_alignment(dev, fb->modifier[0],
11145 fb->pixel_format);
11146 }
ff944564
DL		 11147
11148 /*
11149 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11150 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11151 */
11152 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11153 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11154
6042639c 11155 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
ff944564
DL		 11156 POSTING_READ(PLANE_SURF(pipe, 0));
11157}
11158
6042639c
CW		 11159static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11160 struct intel_unpin_work *work)
84c33a64
SG		 11161{
11162 struct drm_device *dev = intel_crtc->base.dev;
11163 struct drm_i915_private *dev_priv = dev->dev_private;
11164 struct intel_framebuffer *intel_fb =
11165 to_intel_framebuffer(intel_crtc->base.primary->fb);
11166 struct drm_i915_gem_object *obj = intel_fb->obj;
11167 u32 dspcntr;
11168 u32 reg;
11169
84c33a64
SG		 11170 reg = DSPCNTR(intel_crtc->plane);
11171 dspcntr = I915_READ(reg);
11172
c5d97472
DL		 11173 if (obj->tiling_mode != I915_TILING_NONE)
11174 dspcntr |= DISPPLANE_TILED;
11175 else
11176 dspcntr &= ~DISPPLANE_TILED;
11177
84c33a64
SG		 11178 I915_WRITE(reg, dspcntr);
11179
6042639c 11180 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
84c33a64 11181 POSTING_READ(DSPSURF(intel_crtc->plane));
ff944564
DL		 11182}
11183
11184/*
11185 * XXX: This is the temporary way to update the plane registers until we get
11186 * around to using the usual plane update functions for MMIO flips
11187 */
6042639c 11188static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
ff944564 11189{
6042639c
CW		 11190 struct intel_crtc *crtc = mmio_flip->crtc;
11191 struct intel_unpin_work *work;
11192
11193 spin_lock_irq(&crtc->base.dev->event_lock);
11194 work = crtc->unpin_work;
11195 spin_unlock_irq(&crtc->base.dev->event_lock);
11196 if (work == NULL)
11197 return;
ff944564 11198
6042639c 11199 intel_mark_page_flip_active(work);
ff944564 11200
6042639c 11201 intel_pipe_update_start(crtc);
ff944564 11202
6042639c 11203 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
86efe24a 11204 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
ff944564
DL		 11205 else
11206 /* use_mmio_flip() retricts MMIO flips to ilk+ */
6042639c 11207 ilk_do_mmio_flip(crtc, work);
ff944564 11208
6042639c 11209 intel_pipe_update_end(crtc);
84c33a64
SG		 11210}
11211
9362c7c5 11212static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11213{
b2cfe0ab
CW		 11214 struct intel_mmio_flip *mmio_flip =
11215 container_of(work, struct intel_mmio_flip, work);
84c33a64 11216
6042639c 11217 if (mmio_flip->req) {
eed29a5b 11218 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11219 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11220 false, NULL,
11221 &mmio_flip->i915->rps.mmioflips));
6042639c
CW		 11222 i915_gem_request_unreference__unlocked(mmio_flip->req);
11223 }
84c33a64 11224
6042639c 11225 intel_do_mmio_flip(mmio_flip);
b2cfe0ab 11226 kfree(mmio_flip);
84c33a64
SG		 11227}
11228
11229static int intel_queue_mmio_flip(struct drm_device *dev,
11230 struct drm_crtc *crtc,
86efe24a 11231 struct drm_i915_gem_object *obj)
84c33a64 11232{
b2cfe0ab
CW		 11233 struct intel_mmio_flip *mmio_flip;
11234
11235 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11236 if (mmio_flip == NULL)
11237 return -ENOMEM;
84c33a64 11238
bcafc4e3 11239 mmio_flip->i915 = to_i915(dev);
eed29a5b 11240 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11241 mmio_flip->crtc = to_intel_crtc(crtc);
86efe24a 11242 mmio_flip->rotation = crtc->primary->state->rotation;
536f5b5e 11243
b2cfe0ab
CW		 11244 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11245 schedule_work(&mmio_flip->work);
84c33a64 11246
84c33a64
SG		 11247 return 0;
11248}
11249
8c9f3aaf
JB		 11250static int intel_default_queue_flip(struct drm_device *dev,
11251 struct drm_crtc *crtc,
11252 struct drm_framebuffer *fb,
ed8d1975 11253 struct drm_i915_gem_object *obj,
6258fbe2 11254 struct drm_i915_gem_request *req,
ed8d1975 11255 uint32_t flags)
8c9f3aaf
JB		 11256{
11257 return -ENODEV;
11258}
11259
d6bbafa1
CW		 11260static bool __intel_pageflip_stall_check(struct drm_device *dev,
11261 struct drm_crtc *crtc)
11262{
11263 struct drm_i915_private *dev_priv = dev->dev_private;
11264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11265 struct intel_unpin_work *work = intel_crtc->unpin_work;
11266 u32 addr;
11267
11268 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11269 return true;
11270
908565c2
CW		 11271 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11272 return false;
11273
d6bbafa1
CW		 11274 if (!work->enable_stall_check)
11275 return false;
11276
11277 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11278 if (work->flip_queued_req &&
11279 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11280 return false;
11281
1e3feefd 11282 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11283 }
11284
1e3feefd 11285 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11286 return false;
11287
11288 /* Potential stall - if we see that the flip has happened,
11289 * assume a missed interrupt. */
11290 if (INTEL_INFO(dev)->gen >= 4)
11291 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11292 else
11293 addr = I915_READ(DSPADDR(intel_crtc->plane));
11294
11295 /* There is a potential issue here with a false positive after a flip
11296 * to the same address. We could address this by checking for a
11297 * non-incrementing frame counter.
11298 */
11299 return addr == work->gtt_offset;
11300}
11301
11302void intel_check_page_flip(struct drm_device *dev, int pipe)
11303{
11304 struct drm_i915_private *dev_priv = dev->dev_private;
11305 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11307 struct intel_unpin_work *work;
f326038a 11308
6c51d46f 11309 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11310
11311 if (crtc == NULL)
11312 return;
11313
f326038a 11314 spin_lock(&dev->event_lock);
6ad790c0
CW		 11315 work = intel_crtc->unpin_work;
11316 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11317 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11318 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11319 page_flip_completed(intel_crtc);
6ad790c0 11320 work = NULL;
d6bbafa1 11321 }
6ad790c0
CW		 11322 if (work != NULL &&
11323 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11324 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11325 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11326}
11327
6b95a207
KH		 11328static int intel_crtc_page_flip(struct drm_crtc *crtc,
11329 struct drm_framebuffer *fb,
ed8d1975
KP		 11330 struct drm_pending_vblank_event *event,
11331 uint32_t page_flip_flags)
6b95a207
KH		 11332{
11333 struct drm_device *dev = crtc->dev;
11334 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11335 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11336 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11338 struct drm_plane *primary = crtc->primary;
a071fa00 11339 enum pipe pipe = intel_crtc->pipe;
6b95a207 11340 struct intel_unpin_work *work;
a4872ba6 11341 struct intel_engine_cs *ring;
cf5d8a46 11342 bool mmio_flip;
91af127f 11343 struct drm_i915_gem_request *request = NULL;
52e68630 11344 int ret;
6b95a207 11345
2ff8fde1
MR		 11346 /*
11347 * drm_mode_page_flip_ioctl() should already catch this, but double
11348 * check to be safe. In the future we may enable pageflipping from
11349 * a disabled primary plane.
11350 */
11351 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11352 return -EBUSY;
11353
e6a595d2 11354 /* Can't change pixel format via MI display flips. */
f4510a27 11355 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11356 return -EINVAL;
11357
11358 /*
11359 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11360 * Note that pitch changes could also affect these register.
11361 */
11362 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11363 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11364 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11365 return -EINVAL;
11366
f900db47
CW		 11367 if (i915_terminally_wedged(&dev_priv->gpu_error))
11368 goto out_hang;
11369
b14c5679 11370 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11371 if (work == NULL)
11372 return -ENOMEM;
11373
6b95a207 11374 work->event = event;
b4a98e57 11375 work->crtc = crtc;
ab8d6675 11376 work->old_fb = old_fb;
6b95a207
KH		 11377 INIT_WORK(&work->work, intel_unpin_work_fn);
11378
87b6b101 11379 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11380 if (ret)
11381 goto free_work;
11382
6b95a207 11383 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11384 spin_lock_irq(&dev->event_lock);
6b95a207 11385 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11386 /* Before declaring the flip queue wedged, check if
11387 * the hardware completed the operation behind our backs.
11388 */
11389 if (__intel_pageflip_stall_check(dev, crtc)) {
11390 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11391 page_flip_completed(intel_crtc);
11392 } else {
11393 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11394 spin_unlock_irq(&dev->event_lock);
468f0b44 11395
d6bbafa1
CW		 11396 drm_crtc_vblank_put(crtc);
11397 kfree(work);
11398 return -EBUSY;
11399 }
6b95a207
KH		 11400 }
11401 intel_crtc->unpin_work = work;
5e2d7afc 11402 spin_unlock_irq(&dev->event_lock);
6b95a207 11403
b4a98e57
CW		 11404 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11405 flush_workqueue(dev_priv->wq);
11406
75dfca80 11407 /* Reference the objects for the scheduled work. */
ab8d6675 11408 drm_framebuffer_reference(work->old_fb);
05394f39 11409 drm_gem_object_reference(&obj->base);
6b95a207 11410
f4510a27 11411 crtc->primary->fb = fb;
afd65eb4 11412 update_state_fb(crtc->primary);
1ed1f968 11413
e1f99ce6 11414 work->pending_flip_obj = obj;
e1f99ce6 11415
89ed88ba
CW		 11416 ret = i915_mutex_lock_interruptible(dev);
11417 if (ret)
11418 goto cleanup;
11419
b4a98e57 11420 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11421 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11422
75f7f3ec 11423 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
fd8f507c 11424 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
75f7f3ec 11425
4fa62c89
VS		 11426 if (IS_VALLEYVIEW(dev)) {
11427 ring = &dev_priv->ring[BCS];
ab8d6675 11428 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11429 /* vlv: DISPLAY_FLIP fails to change tiling */
11430 ring = NULL;
48bf5b2d 11431 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11432 ring = &dev_priv->ring[BCS];
4fa62c89 11433 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11434 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11435 if (ring == NULL || ring->id != RCS)
11436 ring = &dev_priv->ring[BCS];
11437 } else {
11438 ring = &dev_priv->ring[RCS];
11439 }
11440
cf5d8a46
CW		 11441 mmio_flip = use_mmio_flip(ring, obj);
11442
11443 /* When using CS flips, we want to emit semaphores between rings.
11444 * However, when using mmio flips we will create a task to do the
11445 * synchronisation, so all we want here is to pin the framebuffer
11446 * into the display plane and skip any waits.
11447 */
7580d774
ML		 11448 if (!mmio_flip) {
11449 ret = i915_gem_object_sync(obj, ring, &request);
11450 if (ret)
11451 goto cleanup_pending;
11452 }
11453
82bc3b2d 11454 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
7580d774 11455 crtc->primary->state);
8c9f3aaf
JB		 11456 if (ret)
11457 goto cleanup_pending;
6b95a207 11458
dedf278c
TU		 11459 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11460 obj, 0);
11461 work->gtt_offset += intel_crtc->dspaddr_offset;
4fa62c89 11462
cf5d8a46 11463 if (mmio_flip) {
86efe24a 11464 ret = intel_queue_mmio_flip(dev, crtc, obj);
d6bbafa1
CW		 11465 if (ret)
11466 goto cleanup_unpin;
11467
f06cc1b9
JH		 11468 i915_gem_request_assign(&work->flip_queued_req,
11469 obj->last_write_req);
d6bbafa1 11470 } else {
6258fbe2
JH		 11471 if (!request) {
11472 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11473 if (ret)
11474 goto cleanup_unpin;
11475 }
11476
11477 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11478 page_flip_flags);
11479 if (ret)
11480 goto cleanup_unpin;
11481
6258fbe2 11482 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11483 }
11484
91af127f 11485 if (request)
75289874 11486 i915_add_request_no_flush(request);
91af127f 11487
1e3feefd 11488 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11489 work->enable_stall_check = true;
4fa62c89 11490
ab8d6675 11491 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11492 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11493 mutex_unlock(&dev->struct_mutex);
a071fa00 11494
4e1e26f1 11495 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11496 intel_frontbuffer_flip_prepare(dev,
11497 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11498
e5510fac
JB		 11499 trace_i915_flip_request(intel_crtc->plane, obj);
11500
6b95a207 11501 return 0;
96b099fd 11502
4fa62c89 11503cleanup_unpin:
82bc3b2d 11504 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11505cleanup_pending:
91af127f
JH		 11506 if (request)
11507 i915_gem_request_cancel(request);
b4a98e57 11508 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11509 mutex_unlock(&dev->struct_mutex);
11510cleanup:
f4510a27 11511 crtc->primary->fb = old_fb;
afd65eb4 11512 update_state_fb(crtc->primary);
89ed88ba
CW		 11513
11514 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11515 drm_framebuffer_unreference(work->old_fb);
96b099fd 11516
5e2d7afc 11517 spin_lock_irq(&dev->event_lock);
96b099fd 11518 intel_crtc->unpin_work = NULL;
5e2d7afc 11519 spin_unlock_irq(&dev->event_lock);
96b099fd 11520
87b6b101 11521 drm_crtc_vblank_put(crtc);
7317c75e 11522free_work:
96b099fd
CW		 11523 kfree(work);
11524
f900db47 11525 if (ret == -EIO) {
02e0efb5
ML		 11526 struct drm_atomic_state *state;
11527 struct drm_plane_state *plane_state;
11528
f900db47 11529out_hang:
02e0efb5
ML		 11530 state = drm_atomic_state_alloc(dev);
11531 if (!state)
11532 return -ENOMEM;
11533 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11534
11535retry:
11536 plane_state = drm_atomic_get_plane_state(state, primary);
11537 ret = PTR_ERR_OR_ZERO(plane_state);
11538 if (!ret) {
11539 drm_atomic_set_fb_for_plane(plane_state, fb);
11540
11541 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11542 if (!ret)
11543 ret = drm_atomic_commit(state);
11544 }
11545
11546 if (ret == -EDEADLK) {
11547 drm_modeset_backoff(state->acquire_ctx);
11548 drm_atomic_state_clear(state);
11549 goto retry;
11550 }
11551
11552 if (ret)
11553 drm_atomic_state_free(state);
11554
f0d3dad3 11555 if (ret == 0 && event) {
5e2d7afc 11556 spin_lock_irq(&dev->event_lock);
a071fa00 11557 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11558 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11559 }
f900db47 11560 }
96b099fd 11561 return ret;
6b95a207
KH		 11562}
11563
da20eabd
ML		 11564
11565/**
11566 * intel_wm_need_update - Check whether watermarks need updating
11567 * @plane: drm plane
11568 * @state: new plane state
11569 *
11570 * Check current plane state versus the new one to determine whether
11571 * watermarks need to be recalculated.
11572 *
11573 * Returns true or false.
11574 */
11575static bool intel_wm_need_update(struct drm_plane *plane,
11576 struct drm_plane_state *state)
11577{
d21fbe87
MR		 11578 struct intel_plane_state *new = to_intel_plane_state(state);
11579 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11580
11581 /* Update watermarks on tiling or size changes. */
da20eabd
ML		 11582 if (!plane->state->fb || !state->fb ||
11583 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
d21fbe87
MR		 11584 plane->state->rotation != state->rotation ||
11585 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11586 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11587 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11588 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
2791a16c 11589 return true;
7809e5ae 11590
2791a16c 11591 return false;
7809e5ae
MR		 11592}
11593
d21fbe87
MR		 11594static bool needs_scaling(struct intel_plane_state *state)
11595{
11596 int src_w = drm_rect_width(&state->src) >> 16;
11597 int src_h = drm_rect_height(&state->src) >> 16;
11598 int dst_w = drm_rect_width(&state->dst);
11599 int dst_h = drm_rect_height(&state->dst);
11600
11601 return (src_w != dst_w || src_h != dst_h);
11602}
11603
da20eabd
ML		 11604int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11605 struct drm_plane_state *plane_state)
11606{
11607 struct drm_crtc *crtc = crtc_state->crtc;
11608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11609 struct drm_plane *plane = plane_state->plane;
11610 struct drm_device *dev = crtc->dev;
11611 struct drm_i915_private *dev_priv = dev->dev_private;
11612 struct intel_plane_state *old_plane_state =
11613 to_intel_plane_state(plane->state);
11614 int idx = intel_crtc->base.base.id, ret;
11615 int i = drm_plane_index(plane);
11616 bool mode_changed = needs_modeset(crtc_state);
11617 bool was_crtc_enabled = crtc->state->active;
11618 bool is_crtc_enabled = crtc_state->active;
da20eabd
ML		 11619 bool turn_off, turn_on, visible, was_visible;
11620 struct drm_framebuffer *fb = plane_state->fb;
11621
11622 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11623 plane->type != DRM_PLANE_TYPE_CURSOR) {
11624 ret = skl_update_scaler_plane(
11625 to_intel_crtc_state(crtc_state),
11626 to_intel_plane_state(plane_state));
11627 if (ret)
11628 return ret;
11629 }
11630
da20eabd
ML		 11631 was_visible = old_plane_state->visible;
11632 visible = to_intel_plane_state(plane_state)->visible;
11633
11634 if (!was_crtc_enabled && WARN_ON(was_visible))
11635 was_visible = false;
11636
11637 if (!is_crtc_enabled && WARN_ON(visible))
11638 visible = false;
11639
11640 if (!was_visible && !visible)
11641 return 0;
11642
11643 turn_off = was_visible && (!visible || mode_changed);
11644 turn_on = visible && (!was_visible || mode_changed);
11645
11646 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11647 plane->base.id, fb ? fb->base.id : -1);
11648
11649 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11650 plane->base.id, was_visible, visible,
11651 turn_off, turn_on, mode_changed);
11652
852eb00d 11653 if (turn_on) {
f015c551 11654 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11655 /* must disable cxsr around plane enable/disable */
11656 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11657 intel_crtc->atomic.disable_cxsr = true;
11658 /* to potentially re-enable cxsr */
11659 intel_crtc->atomic.wait_vblank = true;
11660 intel_crtc->atomic.update_wm_post = true;
11661 }
11662 } else if (turn_off) {
f015c551 11663 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11664 /* must disable cxsr around plane enable/disable */
11665 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11666 if (is_crtc_enabled)
11667 intel_crtc->atomic.wait_vblank = true;
11668 intel_crtc->atomic.disable_cxsr = true;
11669 }
11670 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11671 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11672 }
da20eabd 11673
8be6ca85 11674 if (visible || was_visible)
a9ff8714
VS		 11675 intel_crtc->atomic.fb_bits |=
11676 to_intel_plane(plane)->frontbuffer_bit;
11677
da20eabd
ML		 11678 switch (plane->type) {
11679 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11680 intel_crtc->atomic.pre_disable_primary = turn_off;
11681 intel_crtc->atomic.post_enable_primary = turn_on;
11682
066cf55b
RV		 11683 if (turn_off) {
11684 /*
11685 * FIXME: Actually if we will still have any other
11686 * plane enabled on the pipe we could let IPS enabled
11687 * still, but for now lets consider that when we make
11688 * primary invisible by setting DSPCNTR to 0 on
11689 * update_primary_plane function IPS needs to be
11690 * disable.
11691 */
11692 intel_crtc->atomic.disable_ips = true;
11693
da20eabd 11694 intel_crtc->atomic.disable_fbc = true;
066cf55b 11695 }
da20eabd
ML		 11696
11697 /*
11698 * FBC does not work on some platforms for rotated
11699 * planes, so disable it when rotation is not 0 and
11700 * update it when rotation is set back to 0.
11701 *
11702 * FIXME: This is redundant with the fbc update done in
11703 * the primary plane enable function except that that
11704 * one is done too late. We eventually need to unify
11705 * this.
11706 */
11707
11708 if (visible &&
11709 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11710 dev_priv->fbc.crtc == intel_crtc &&
11711 plane_state->rotation != BIT(DRM_ROTATE_0))
11712 intel_crtc->atomic.disable_fbc = true;
11713
11714 /*
11715 * BDW signals flip done immediately if the plane
11716 * is disabled, even if the plane enable is already
11717 * armed to occur at the next vblank :(
11718 */
11719 if (turn_on && IS_BROADWELL(dev))
11720 intel_crtc->atomic.wait_vblank = true;
11721
11722 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11723 break;
11724 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11725 break;
11726 case DRM_PLANE_TYPE_OVERLAY:
d21fbe87
MR		 11727 /*
11728 * WaCxSRDisabledForSpriteScaling:ivb
11729 *
11730 * cstate->update_wm was already set above, so this flag will
11731 * take effect when we commit and program watermarks.
11732 */
11733 if (IS_IVYBRIDGE(dev) &&
11734 needs_scaling(to_intel_plane_state(plane_state)) &&
11735 !needs_scaling(old_plane_state)) {
11736 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11737 } else if (turn_off && !mode_changed) {
da20eabd
ML		 11738 intel_crtc->atomic.wait_vblank = true;
11739 intel_crtc->atomic.update_sprite_watermarks |=
11740 1 << i;
11741 }
d21fbe87
MR		 11742
11743 break;
da20eabd
ML		 11744 }
11745 return 0;
11746}
11747
6d3a1ce7
ML		 11748static bool encoders_cloneable(const struct intel_encoder *a,
11749 const struct intel_encoder *b)
11750{
11751 /* masks could be asymmetric, so check both ways */
11752 return a == b || (a->cloneable & (1 << b->type) &&
11753 b->cloneable & (1 << a->type));
11754}
11755
11756static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11757 struct intel_crtc *crtc,
11758 struct intel_encoder *encoder)
11759{
11760 struct intel_encoder *source_encoder;
11761 struct drm_connector *connector;
11762 struct drm_connector_state *connector_state;
11763 int i;
11764
11765 for_each_connector_in_state(state, connector, connector_state, i) {
11766 if (connector_state->crtc != &crtc->base)
11767 continue;
11768
11769 source_encoder =
11770 to_intel_encoder(connector_state->best_encoder);
11771 if (!encoders_cloneable(encoder, source_encoder))
11772 return false;
11773 }
11774
11775 return true;
11776}
11777
11778static bool check_encoder_cloning(struct drm_atomic_state *state,
11779 struct intel_crtc *crtc)
11780{
11781 struct intel_encoder *encoder;
11782 struct drm_connector *connector;
11783 struct drm_connector_state *connector_state;
11784 int i;
11785
11786 for_each_connector_in_state(state, connector, connector_state, i) {
11787 if (connector_state->crtc != &crtc->base)
11788 continue;
11789
11790 encoder = to_intel_encoder(connector_state->best_encoder);
11791 if (!check_single_encoder_cloning(state, crtc, encoder))
11792 return false;
11793 }
11794
11795 return true;
11796}
11797
11798static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11799 struct drm_crtc_state *crtc_state)
11800{
cf5a15be 11801 struct drm_device *dev = crtc->dev;
ad421372 11802 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11804 struct intel_crtc_state *pipe_config =
11805 to_intel_crtc_state(crtc_state);
6d3a1ce7 11806 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11807 int ret;
6d3a1ce7
ML		 11808 bool mode_changed = needs_modeset(crtc_state);
11809
11810 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11811 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11812 return -EINVAL;
11813 }
11814
852eb00d
VS		 11815 if (mode_changed && !crtc_state->active)
11816 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11817
ad421372
ML		 11818 if (mode_changed && crtc_state->enable &&
11819 dev_priv->display.crtc_compute_clock &&
11820 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11821 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11822 pipe_config);
11823 if (ret)
11824 return ret;
11825 }
11826
e435d6e5 11827 ret = 0;
86c8bbbe
MR		 11828 if (dev_priv->display.compute_pipe_wm) {
11829 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11830 if (ret)
11831 return ret;
11832 }
11833
e435d6e5
ML		 11834 if (INTEL_INFO(dev)->gen >= 9) {
11835 if (mode_changed)
11836 ret = skl_update_scaler_crtc(pipe_config);
11837
11838 if (!ret)
11839 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11840 pipe_config);
11841 }
11842
11843 return ret;
6d3a1ce7
ML		 11844}
11845
65b38e0d 11846static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11847 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11848 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11849 .atomic_begin = intel_begin_crtc_commit,
11850 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11851 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11852};
11853
d29b2f9d
ACO		 11854static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11855{
11856 struct intel_connector *connector;
11857
11858 for_each_intel_connector(dev, connector) {
11859 if (connector->base.encoder) {
11860 connector->base.state->best_encoder =
11861 connector->base.encoder;
11862 connector->base.state->crtc =
11863 connector->base.encoder->crtc;
11864 } else {
11865 connector->base.state->best_encoder = NULL;
11866 connector->base.state->crtc = NULL;
11867 }
11868 }
11869}
11870
050f7aeb 11871static void
eba905b2 11872connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11873 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11874{
11875 int bpp = pipe_config->pipe_bpp;
11876
11877 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11878 connector->base.base.id,
c23cc417 11879 connector->base.name);
050f7aeb
DV		 11880
11881 /* Don't use an invalid EDID bpc value */
11882 if (connector->base.display_info.bpc &&
11883 connector->base.display_info.bpc * 3 < bpp) {
11884 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11885 bpp, connector->base.display_info.bpc*3);
11886 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11887 }
11888
11889 /* Clamp bpp to 8 on screens without EDID 1.4 */
11890 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11891 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11892 bpp);
11893 pipe_config->pipe_bpp = 24;
11894 }
11895}
11896
4e53c2e0 11897static int
050f7aeb 11898compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11899 struct intel_crtc_state *pipe_config)
4e53c2e0 11900{
050f7aeb 11901 struct drm_device *dev = crtc->base.dev;
1486017f 11902 struct drm_atomic_state *state;
da3ced29
ACO		 11903 struct drm_connector *connector;
11904 struct drm_connector_state *connector_state;
1486017f 11905 int bpp, i;
4e53c2e0 11906
d328c9d7 11907 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11908 bpp = 10*3;
d328c9d7
DV		 11909 else if (INTEL_INFO(dev)->gen >= 5)
11910 bpp = 12*3;
11911 else
11912 bpp = 8*3;
11913
4e53c2e0 11914
4e53c2e0
DV		 11915 pipe_config->pipe_bpp = bpp;
11916
1486017f
ACO		 11917 state = pipe_config->base.state;
11918
4e53c2e0 11919 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11920 for_each_connector_in_state(state, connector, connector_state, i) {
11921 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11922 continue;
11923
da3ced29
ACO		 11924 connected_sink_compute_bpp(to_intel_connector(connector),
11925 pipe_config);
4e53c2e0
DV		 11926 }
11927
11928 return bpp;
11929}
11930
644db711
DV		 11931static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11932{
11933 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11934 "type: 0x%x flags: 0x%x\n",
1342830c 11935 mode->crtc_clock,
644db711
DV		 11936 mode->crtc_hdisplay, mode->crtc_hsync_start,
11937 mode->crtc_hsync_end, mode->crtc_htotal,
11938 mode->crtc_vdisplay, mode->crtc_vsync_start,
11939 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11940}
11941
c0b03411 11942static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11943 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11944 const char *context)
11945{
6a60cd87
CK		 11946 struct drm_device *dev = crtc->base.dev;
11947 struct drm_plane *plane;
11948 struct intel_plane *intel_plane;
11949 struct intel_plane_state *state;
11950 struct drm_framebuffer *fb;
11951
11952 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11953 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11954
11955 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11956 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11957 pipe_config->pipe_bpp, pipe_config->dither);
11958 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11959 pipe_config->has_pch_encoder,
11960 pipe_config->fdi_lanes,
11961 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11962 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11963 pipe_config->fdi_m_n.tu);
90a6b7b0 11964 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11965 pipe_config->has_dp_encoder,
90a6b7b0 11966 pipe_config->lane_count,
eb14cb74
VS		 11967 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11968 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11969 pipe_config->dp_m_n.tu);
b95af8be 11970
90a6b7b0 11971 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11972 pipe_config->has_dp_encoder,
90a6b7b0 11973 pipe_config->lane_count,
b95af8be
VK		 11974 pipe_config->dp_m2_n2.gmch_m,
11975 pipe_config->dp_m2_n2.gmch_n,
11976 pipe_config->dp_m2_n2.link_m,
11977 pipe_config->dp_m2_n2.link_n,
11978 pipe_config->dp_m2_n2.tu);
11979
55072d19
DV		 11980 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11981 pipe_config->has_audio,
11982 pipe_config->has_infoframe);
11983
c0b03411 11984 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11985 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11986 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11987 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11988 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11989 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11990 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11991 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11992 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11993 crtc->num_scalers,
11994 pipe_config->scaler_state.scaler_users,
11995 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11996 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11997 pipe_config->gmch_pfit.control,
11998 pipe_config->gmch_pfit.pgm_ratios,
11999 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12000 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12001 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 12002 pipe_config->pch_pfit.size,
12003 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12004 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12005 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12006
415ff0f6 12007 if (IS_BROXTON(dev)) {
05712c15 12008 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 12009 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 12010 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 12011 pipe_config->ddi_pll_sel,
12012 pipe_config->dpll_hw_state.ebb0,
05712c15 12013 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 12014 pipe_config->dpll_hw_state.pll0,
12015 pipe_config->dpll_hw_state.pll1,
12016 pipe_config->dpll_hw_state.pll2,
12017 pipe_config->dpll_hw_state.pll3,
12018 pipe_config->dpll_hw_state.pll6,
12019 pipe_config->dpll_hw_state.pll8,
05712c15 12020 pipe_config->dpll_hw_state.pll9,
c8453338 12021 pipe_config->dpll_hw_state.pll10,
415ff0f6 12022 pipe_config->dpll_hw_state.pcsdw12);
ef11bdb3 12023 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
415ff0f6
TU		 12024 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12025 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12026 pipe_config->ddi_pll_sel,
12027 pipe_config->dpll_hw_state.ctrl1,
12028 pipe_config->dpll_hw_state.cfgcr1,
12029 pipe_config->dpll_hw_state.cfgcr2);
12030 } else if (HAS_DDI(dev)) {
12031 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12032 pipe_config->ddi_pll_sel,
12033 pipe_config->dpll_hw_state.wrpll);
12034 } else {
12035 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12036 "fp0: 0x%x, fp1: 0x%x\n",
12037 pipe_config->dpll_hw_state.dpll,
12038 pipe_config->dpll_hw_state.dpll_md,
12039 pipe_config->dpll_hw_state.fp0,
12040 pipe_config->dpll_hw_state.fp1);
12041 }
12042
6a60cd87
CK		 12043 DRM_DEBUG_KMS("planes on this crtc\n");
12044 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12045 intel_plane = to_intel_plane(plane);
12046 if (intel_plane->pipe != crtc->pipe)
12047 continue;
12048
12049 state = to_intel_plane_state(plane->state);
12050 fb = state->base.fb;
12051 if (!fb) {
12052 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12053 "disabled, scaler_id = %d\n",
12054 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12055 plane->base.id, intel_plane->pipe,
12056 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12057 drm_plane_index(plane), state->scaler_id);
12058 continue;
12059 }
12060
12061 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12062 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12063 plane->base.id, intel_plane->pipe,
12064 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12065 drm_plane_index(plane));
12066 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12067 fb->base.id, fb->width, fb->height, fb->pixel_format);
12068 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12069 state->scaler_id,
12070 state->src.x1 >> 16, state->src.y1 >> 16,
12071 drm_rect_width(&state->src) >> 16,
12072 drm_rect_height(&state->src) >> 16,
12073 state->dst.x1, state->dst.y1,
12074 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12075 }
c0b03411
DV		 12076}
12077
5448a00d 12078static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12079{
5448a00d
ACO		 12080 struct drm_device *dev = state->dev;
12081 struct intel_encoder *encoder;
da3ced29 12082 struct drm_connector *connector;
5448a00d 12083 struct drm_connector_state *connector_state;
00f0b378 12084 unsigned int used_ports = 0;
5448a00d 12085 int i;
00f0b378
VS		 12086
12087 /*
12088 * Walk the connector list instead of the encoder
12089 * list to detect the problem on ddi platforms
12090 * where there's just one encoder per digital port.
12091 */
da3ced29 12092 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12093 if (!connector_state->best_encoder)
00f0b378
VS		 12094 continue;
12095
5448a00d
ACO		 12096 encoder = to_intel_encoder(connector_state->best_encoder);
12097
12098 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12099
12100 switch (encoder->type) {
12101 unsigned int port_mask;
12102 case INTEL_OUTPUT_UNKNOWN:
12103 if (WARN_ON(!HAS_DDI(dev)))
12104 break;
12105 case INTEL_OUTPUT_DISPLAYPORT:
12106 case INTEL_OUTPUT_HDMI:
12107 case INTEL_OUTPUT_EDP:
12108 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12109
12110 /* the same port mustn't appear more than once */
12111 if (used_ports & port_mask)
12112 return false;
12113
12114 used_ports |= port_mask;
12115 default:
12116 break;
12117 }
12118 }
12119
12120 return true;
12121}
12122
83a57153
ACO		 12123static void
12124clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12125{
12126 struct drm_crtc_state tmp_state;
663a3640 12127 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12128 struct intel_dpll_hw_state dpll_hw_state;
12129 enum intel_dpll_id shared_dpll;
8504c74c 12130 uint32_t ddi_pll_sel;
c4e2d043 12131 bool force_thru;
83a57153 12132
7546a384
ACO		 12133 /* FIXME: before the switch to atomic started, a new pipe_config was
12134 * kzalloc'd. Code that depends on any field being zero should be
12135 * fixed, so that the crtc_state can be safely duplicated. For now,
12136 * only fields that are know to not cause problems are preserved. */
12137
83a57153 12138 tmp_state = crtc_state->base;
663a3640 12139 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12140 shared_dpll = crtc_state->shared_dpll;
12141 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12142 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12143 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12144
83a57153 12145 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12146
83a57153 12147 crtc_state->base = tmp_state;
663a3640 12148 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12149 crtc_state->shared_dpll = shared_dpll;
12150 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12151 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12152 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12153}
12154
548ee15b 12155static int
b8cecdf5 12156intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12157 struct intel_crtc_state *pipe_config)
ee7b9f93 12158{
b359283a 12159 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12160 struct intel_encoder *encoder;
da3ced29 12161 struct drm_connector *connector;
0b901879 12162 struct drm_connector_state *connector_state;
d328c9d7 12163 int base_bpp, ret = -EINVAL;
0b901879 12164 int i;
e29c22c0 12165 bool retry = true;
ee7b9f93 12166
83a57153 12167 clear_intel_crtc_state(pipe_config);
7758a113 12168
e143a21c
DV		 12169 pipe_config->cpu_transcoder =
12170 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12171
2960bc9c
ID		 12172 /*
12173 * Sanitize sync polarity flags based on requested ones. If neither
12174 * positive or negative polarity is requested, treat this as meaning
12175 * negative polarity.
12176 */
2d112de7 12177 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12178 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12179 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12180
2d112de7 12181 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12182 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12183 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12184
d328c9d7
DV		 12185 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12186 pipe_config);
12187 if (base_bpp < 0)
4e53c2e0
DV		 12188 goto fail;
12189
e41a56be
VS		 12190 /*
12191 * Determine the real pipe dimensions. Note that stereo modes can
12192 * increase the actual pipe size due to the frame doubling and
12193 * insertion of additional space for blanks between the frame. This
12194 * is stored in the crtc timings. We use the requested mode to do this
12195 * computation to clearly distinguish it from the adjusted mode, which
12196 * can be changed by the connectors in the below retry loop.
12197 */
2d112de7 12198 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12199 &pipe_config->pipe_src_w,
12200 &pipe_config->pipe_src_h);
e41a56be 12201
e29c22c0 12202encoder_retry:
ef1b460d 12203 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12204 pipe_config->port_clock = 0;
ef1b460d 12205 pipe_config->pixel_multiplier = 1;
ff9a6750 12206
135c81b8 12207 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12208 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12209 CRTC_STEREO_DOUBLE);
135c81b8 12210
7758a113
DV		 12211 /* Pass our mode to the connectors and the CRTC to give them a chance to
12212 * adjust it according to limitations or connector properties, and also
12213 * a chance to reject the mode entirely.
47f1c6c9 12214 */
da3ced29 12215 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12216 if (connector_state->crtc != crtc)
7758a113 12217 continue;
7ae89233 12218
0b901879
ACO		 12219 encoder = to_intel_encoder(connector_state->best_encoder);
12220
efea6e8e
DV		 12221 if (!(encoder->compute_config(encoder, pipe_config))) {
12222 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12223 goto fail;
12224 }
ee7b9f93 12225 }
47f1c6c9 12226
ff9a6750
DV		 12227 /* Set default port clock if not overwritten by the encoder. Needs to be
12228 * done afterwards in case the encoder adjusts the mode. */
12229 if (!pipe_config->port_clock)
2d112de7 12230 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12231 * pipe_config->pixel_multiplier;
ff9a6750 12232
a43f6e0f 12233 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12234 if (ret < 0) {
7758a113
DV		 12235 DRM_DEBUG_KMS("CRTC fixup failed\n");
12236 goto fail;
ee7b9f93 12237 }
e29c22c0
DV		 12238
12239 if (ret == RETRY) {
12240 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12241 ret = -EINVAL;
12242 goto fail;
12243 }
12244
12245 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12246 retry = false;
12247 goto encoder_retry;
12248 }
12249
e8fa4270
DV		 12250 /* Dithering seems to not pass-through bits correctly when it should, so
12251 * only enable it on 6bpc panels. */
12252 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12253 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12254 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12255
7758a113 12256fail:
548ee15b 12257 return ret;
ee7b9f93 12258}
47f1c6c9 12259
ea9d758d 12260static void
4740b0f2 12261intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12262{
0a9ab303
ACO		 12263 struct drm_crtc *crtc;
12264 struct drm_crtc_state *crtc_state;
8a75d157 12265 int i;
ea9d758d 12266
7668851f 12267 /* Double check state. */
8a75d157 12268 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12269 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12270
12271 /* Update hwmode for vblank functions */
12272 if (crtc->state->active)
12273 crtc->hwmode = crtc->state->adjusted_mode;
12274 else
12275 crtc->hwmode.crtc_clock = 0;
61067a5e
ML		 12276
12277 /*
12278 * Update legacy state to satisfy fbc code. This can
12279 * be removed when fbc uses the atomic state.
12280 */
12281 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12282 struct drm_plane_state *plane_state = crtc->primary->state;
12283
12284 crtc->primary->fb = plane_state->fb;
12285 crtc->x = plane_state->src_x >> 16;
12286 crtc->y = plane_state->src_y >> 16;
12287 }
ea9d758d 12288 }
ea9d758d
DV		 12289}
12290
3bd26263 12291static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12292{
3bd26263 12293 int diff;
f1f644dc
JB		 12294
12295 if (clock1 == clock2)
12296 return true;
12297
12298 if (!clock1 || !clock2)
12299 return false;
12300
12301 diff = abs(clock1 - clock2);
12302
12303 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12304 return true;
12305
12306 return false;
12307}
12308
25c5b266
DV		 12309#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12310 list_for_each_entry((intel_crtc), \
12311 &(dev)->mode_config.crtc_list, \
12312 base.head) \
0973f18f 12313 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12314
cfb23ed6
ML		 12315static bool
12316intel_compare_m_n(unsigned int m, unsigned int n,
12317 unsigned int m2, unsigned int n2,
12318 bool exact)
12319{
12320 if (m == m2 && n == n2)
12321 return true;
12322
12323 if (exact || !m || !n || !m2 || !n2)
12324 return false;
12325
12326 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12327
12328 if (m > m2) {
12329 while (m > m2) {
12330 m2 <<= 1;
12331 n2 <<= 1;
12332 }
12333 } else if (m < m2) {
12334 while (m < m2) {
12335 m <<= 1;
12336 n <<= 1;
12337 }
12338 }
12339
12340 return m == m2 && n == n2;
12341}
12342
12343static bool
12344intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12345 struct intel_link_m_n *m2_n2,
12346 bool adjust)
12347{
12348 if (m_n->tu == m2_n2->tu &&
12349 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12350 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12351 intel_compare_m_n(m_n->link_m, m_n->link_n,
12352 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12353 if (adjust)
12354 *m2_n2 = *m_n;
12355
12356 return true;
12357 }
12358
12359 return false;
12360}
12361
0e8ffe1b 12362static bool
2fa2fe9a 12363intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12364 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12365 struct intel_crtc_state *pipe_config,
12366 bool adjust)
0e8ffe1b 12367{
cfb23ed6
ML		 12368 bool ret = true;
12369
12370#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12371 do { \
12372 if (!adjust) \
12373 DRM_ERROR(fmt, ##__VA_ARGS__); \
12374 else \
12375 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12376 } while (0)
12377
66e985c0
DV		 12378#define PIPE_CONF_CHECK_X(name) \
12379 if (current_config->name != pipe_config->name) { \
cfb23ed6 12380 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12381 "(expected 0x%08x, found 0x%08x)\n", \
12382 current_config->name, \
12383 pipe_config->name); \
cfb23ed6 12384 ret = false; \
66e985c0
DV		 12385 }
12386
08a24034
DV		 12387#define PIPE_CONF_CHECK_I(name) \
12388 if (current_config->name != pipe_config->name) { \
cfb23ed6 12389 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12390 "(expected %i, found %i)\n", \
12391 current_config->name, \
12392 pipe_config->name); \
cfb23ed6
ML		 12393 ret = false; \
12394 }
12395
12396#define PIPE_CONF_CHECK_M_N(name) \
12397 if (!intel_compare_link_m_n(&current_config->name, \
12398 &pipe_config->name,\
12399 adjust)) { \
12400 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12401 "(expected tu %i gmch %i/%i link %i/%i, " \
12402 "found tu %i, gmch %i/%i link %i/%i)\n", \
12403 current_config->name.tu, \
12404 current_config->name.gmch_m, \
12405 current_config->name.gmch_n, \
12406 current_config->name.link_m, \
12407 current_config->name.link_n, \
12408 pipe_config->name.tu, \
12409 pipe_config->name.gmch_m, \
12410 pipe_config->name.gmch_n, \
12411 pipe_config->name.link_m, \
12412 pipe_config->name.link_n); \
12413 ret = false; \
12414 }
12415
12416#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12417 if (!intel_compare_link_m_n(&current_config->name, \
12418 &pipe_config->name, adjust) && \
12419 !intel_compare_link_m_n(&current_config->alt_name, \
12420 &pipe_config->name, adjust)) { \
12421 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12422 "(expected tu %i gmch %i/%i link %i/%i, " \
12423 "or tu %i gmch %i/%i link %i/%i, " \
12424 "found tu %i, gmch %i/%i link %i/%i)\n", \
12425 current_config->name.tu, \
12426 current_config->name.gmch_m, \
12427 current_config->name.gmch_n, \
12428 current_config->name.link_m, \
12429 current_config->name.link_n, \
12430 current_config->alt_name.tu, \
12431 current_config->alt_name.gmch_m, \
12432 current_config->alt_name.gmch_n, \
12433 current_config->alt_name.link_m, \
12434 current_config->alt_name.link_n, \
12435 pipe_config->name.tu, \
12436 pipe_config->name.gmch_m, \
12437 pipe_config->name.gmch_n, \
12438 pipe_config->name.link_m, \
12439 pipe_config->name.link_n); \
12440 ret = false; \
88adfff1
DV		 12441 }
12442
b95af8be
VK		 12443/* This is required for BDW+ where there is only one set of registers for
12444 * switching between high and low RR.
12445 * This macro can be used whenever a comparison has to be made between one
12446 * hw state and multiple sw state variables.
12447 */
12448#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12449 if ((current_config->name != pipe_config->name) && \
12450 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12451 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12452 "(expected %i or %i, found %i)\n", \
12453 current_config->name, \
12454 current_config->alt_name, \
12455 pipe_config->name); \
cfb23ed6 12456 ret = false; \
b95af8be
VK		 12457 }
12458
1bd1bd80
DV		 12459#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12460 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12461 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12462 "(expected %i, found %i)\n", \
12463 current_config->name & (mask), \
12464 pipe_config->name & (mask)); \
cfb23ed6 12465 ret = false; \
1bd1bd80
DV		 12466 }
12467
5e550656
VS		 12468#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12469 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12470 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12471 "(expected %i, found %i)\n", \
12472 current_config->name, \
12473 pipe_config->name); \
cfb23ed6 12474 ret = false; \
5e550656
VS		 12475 }
12476
bb760063
DV		 12477#define PIPE_CONF_QUIRK(quirk) \
12478 ((current_config->quirks | pipe_config->quirks) & (quirk))
12479
eccb140b
DV		 12480 PIPE_CONF_CHECK_I(cpu_transcoder);
12481
08a24034
DV		 12482 PIPE_CONF_CHECK_I(has_pch_encoder);
12483 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12484 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12485
eb14cb74 12486 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12487 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12488
12489 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12490 PIPE_CONF_CHECK_M_N(dp_m_n);
12491
12492 PIPE_CONF_CHECK_I(has_drrs);
12493 if (current_config->has_drrs)
12494 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12495 } else
12496 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12497
2d112de7
ACO		 12498 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12499 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12500 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12501 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12502 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12503 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12504
2d112de7
ACO		 12505 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12506 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12507 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12508 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12509 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12510 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12511
c93f54cf 12512 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12513 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12514 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12515 IS_VALLEYVIEW(dev))
12516 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12517 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12518
9ed109a7
DV		 12519 PIPE_CONF_CHECK_I(has_audio);
12520
2d112de7 12521 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12522 DRM_MODE_FLAG_INTERLACE);
12523
bb760063 12524 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12525 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12526 DRM_MODE_FLAG_PHSYNC);
2d112de7 12527 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12528 DRM_MODE_FLAG_NHSYNC);
2d112de7 12529 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12530 DRM_MODE_FLAG_PVSYNC);
2d112de7 12531 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12532 DRM_MODE_FLAG_NVSYNC);
12533 }
045ac3b5 12534
333b8ca8 12535 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV		 12536 /* pfit ratios are autocomputed by the hw on gen4+ */
12537 if (INTEL_INFO(dev)->gen < 4)
12538 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
333b8ca8 12539 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12540
bfd16b2a
ML		 12541 if (!adjust) {
12542 PIPE_CONF_CHECK_I(pipe_src_w);
12543 PIPE_CONF_CHECK_I(pipe_src_h);
12544
12545 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12546 if (current_config->pch_pfit.enabled) {
12547 PIPE_CONF_CHECK_X(pch_pfit.pos);
12548 PIPE_CONF_CHECK_X(pch_pfit.size);
12549 }
2fa2fe9a 12550
7aefe2b5
ML		 12551 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12552 }
a1b2278e 12553
e59150dc
JB		 12554 /* BDW+ don't expose a synchronous way to read the state */
12555 if (IS_HASWELL(dev))
12556 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12557
282740f7
VS		 12558 PIPE_CONF_CHECK_I(double_wide);
12559
26804afd
DV		 12560 PIPE_CONF_CHECK_X(ddi_pll_sel);
12561
c0d43d62 12562 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12563 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12564 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12565 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12566 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12567 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12568 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12569 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12570 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12571
42571aef
VS		 12572 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12573 PIPE_CONF_CHECK_I(pipe_bpp);
12574
2d112de7 12575 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12576 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12577
66e985c0 12578#undef PIPE_CONF_CHECK_X
08a24034 12579#undef PIPE_CONF_CHECK_I
b95af8be 12580#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12581#undef PIPE_CONF_CHECK_FLAGS
5e550656 12582#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12583#undef PIPE_CONF_QUIRK
cfb23ed6 12584#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12585
cfb23ed6 12586 return ret;
0e8ffe1b
DV		 12587}
12588
08db6652
DL		 12589static void check_wm_state(struct drm_device *dev)
12590{
12591 struct drm_i915_private *dev_priv = dev->dev_private;
12592 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12593 struct intel_crtc *intel_crtc;
12594 int plane;
12595
12596 if (INTEL_INFO(dev)->gen < 9)
12597 return;
12598
12599 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12600 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12601
12602 for_each_intel_crtc(dev, intel_crtc) {
12603 struct skl_ddb_entry *hw_entry, *sw_entry;
12604 const enum pipe pipe = intel_crtc->pipe;
12605
12606 if (!intel_crtc->active)
12607 continue;
12608
12609 /* planes */
dd740780 12610 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12611 hw_entry = &hw_ddb.plane[pipe][plane];
12612 sw_entry = &sw_ddb->plane[pipe][plane];
12613
12614 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12615 continue;
12616
12617 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12618 "(expected (%u,%u), found (%u,%u))\n",
12619 pipe_name(pipe), plane + 1,
12620 sw_entry->start, sw_entry->end,
12621 hw_entry->start, hw_entry->end);
12622 }
12623
12624 /* cursor */
4969d33e
MR		 12625 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12626 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
08db6652
DL		 12627
12628 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12629 continue;
12630
12631 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12632 "(expected (%u,%u), found (%u,%u))\n",
12633 pipe_name(pipe),
12634 sw_entry->start, sw_entry->end,
12635 hw_entry->start, hw_entry->end);
12636 }
12637}
12638
91d1b4bd 12639static void
35dd3c64
ML		 12640check_connector_state(struct drm_device *dev,
12641 struct drm_atomic_state *old_state)
8af6cf88 12642{
35dd3c64
ML		 12643 struct drm_connector_state *old_conn_state;
12644 struct drm_connector *connector;
12645 int i;
8af6cf88 12646
35dd3c64
ML		 12647 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12648 struct drm_encoder *encoder = connector->encoder;
12649 struct drm_connector_state *state = connector->state;
ad3c558f 12650
8af6cf88
DV		 12651 /* This also checks the encoder/connector hw state with the
12652 * ->get_hw_state callbacks. */
35dd3c64 12653 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12654
ad3c558f 12655 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12656 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12657 }
91d1b4bd
DV		 12658}
12659
12660static void
12661check_encoder_state(struct drm_device *dev)
12662{
12663 struct intel_encoder *encoder;
12664 struct intel_connector *connector;
8af6cf88 12665
b2784e15 12666 for_each_intel_encoder(dev, encoder) {
8af6cf88 12667 bool enabled = false;
4d20cd86 12668 enum pipe pipe;
8af6cf88
DV		 12669
12670 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12671 encoder->base.base.id,
8e329a03 12672 encoder->base.name);
8af6cf88 12673
3a3371ff 12674 for_each_intel_connector(dev, connector) {
4d20cd86 12675 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12676 continue;
12677 enabled = true;
ad3c558f
ML		 12678
12679 I915_STATE_WARN(connector->base.state->crtc !=
12680 encoder->base.crtc,
12681 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12682 }
0e32b39c 12683
e2c719b7 12684 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12685 "encoder's enabled state mismatch "
12686 "(expected %i, found %i)\n",
12687 !!encoder->base.crtc, enabled);
7c60d198
ML		 12688
12689 if (!encoder->base.crtc) {
4d20cd86 12690 bool active;
7c60d198 12691
4d20cd86
ML		 12692 active = encoder->get_hw_state(encoder, &pipe);
12693 I915_STATE_WARN(active,
12694 "encoder detached but still enabled on pipe %c.\n",
12695 pipe_name(pipe));
7c60d198 12696 }
8af6cf88 12697 }
91d1b4bd
DV		 12698}
12699
12700static void
4d20cd86 12701check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12702{
fbee40df 12703 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12704 struct intel_encoder *encoder;
4d20cd86
ML		 12705 struct drm_crtc_state *old_crtc_state;
12706 struct drm_crtc *crtc;
12707 int i;
8af6cf88 12708
4d20cd86
ML		 12709 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12711 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12712 bool active;
8af6cf88 12713
bfd16b2a
ML		 12714 if (!needs_modeset(crtc->state) &&
12715 !to_intel_crtc_state(crtc->state)->update_pipe)
4d20cd86 12716 continue;
045ac3b5 12717
4d20cd86
ML		 12718 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12719 pipe_config = to_intel_crtc_state(old_crtc_state);
12720 memset(pipe_config, 0, sizeof(*pipe_config));
12721 pipe_config->base.crtc = crtc;
12722 pipe_config->base.state = old_state;
8af6cf88 12723
4d20cd86
ML		 12724 DRM_DEBUG_KMS("[CRTC:%d]\n",
12725 crtc->base.id);
8af6cf88 12726
4d20cd86
ML		 12727 active = dev_priv->display.get_pipe_config(intel_crtc,
12728 pipe_config);
d62cf62a 12729
b6b5d049 12730 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12731 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12732 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12733 active = crtc->state->active;
6c49f241 12734
4d20cd86 12735 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12736 "crtc active state doesn't match with hw state "
4d20cd86 12737 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12738
4d20cd86 12739 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12740 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12741 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12742
12743 for_each_encoder_on_crtc(dev, crtc, encoder) {
12744 enum pipe pipe;
12745
12746 active = encoder->get_hw_state(encoder, &pipe);
12747 I915_STATE_WARN(active != crtc->state->active,
12748 "[ENCODER:%i] active %i with crtc active %i\n",
12749 encoder->base.base.id, active, crtc->state->active);
12750
12751 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12752 "Encoder connected to wrong pipe %c\n",
12753 pipe_name(pipe));
12754
12755 if (active)
12756 encoder->get_config(encoder, pipe_config);
12757 }
53d9f4e9 12758
4d20cd86 12759 if (!crtc->state->active)
cfb23ed6
ML		 12760 continue;
12761
4d20cd86
ML		 12762 sw_config = to_intel_crtc_state(crtc->state);
12763 if (!intel_pipe_config_compare(dev, sw_config,
12764 pipe_config, false)) {
e2c719b7 12765 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12766 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12767 "[hw state]");
4d20cd86 12768 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12769 "[sw state]");
12770 }
8af6cf88
DV		 12771 }
12772}
12773
91d1b4bd
DV		 12774static void
12775check_shared_dpll_state(struct drm_device *dev)
12776{
fbee40df 12777 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12778 struct intel_crtc *crtc;
12779 struct intel_dpll_hw_state dpll_hw_state;
12780 int i;
5358901f
DV		 12781
12782 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12783 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12784 int enabled_crtcs = 0, active_crtcs = 0;
12785 bool active;
12786
12787 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12788
12789 DRM_DEBUG_KMS("%s\n", pll->name);
12790
12791 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12792
e2c719b7 12793 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12794 "more active pll users than references: %i vs %i\n",
3e369b76 12795 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12796 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12797 "pll in active use but not on in sw tracking\n");
e2c719b7 12798 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12799 "pll in on but not on in use in sw tracking\n");
e2c719b7 12800 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12801 "pll on state mismatch (expected %i, found %i)\n",
12802 pll->on, active);
12803
d3fcc808 12804 for_each_intel_crtc(dev, crtc) {
83d65738 12805 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12806 enabled_crtcs++;
12807 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12808 active_crtcs++;
12809 }
e2c719b7 12810 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12811 "pll active crtcs mismatch (expected %i, found %i)\n",
12812 pll->active, active_crtcs);
e2c719b7 12813 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12814 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12815 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12816
e2c719b7 12817 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12818 sizeof(dpll_hw_state)),
12819 "pll hw state mismatch\n");
5358901f 12820 }
8af6cf88
DV		 12821}
12822
ee165b1a
ML		 12823static void
12824intel_modeset_check_state(struct drm_device *dev,
12825 struct drm_atomic_state *old_state)
91d1b4bd 12826{
08db6652 12827 check_wm_state(dev);
35dd3c64 12828 check_connector_state(dev, old_state);
91d1b4bd 12829 check_encoder_state(dev);
4d20cd86 12830 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12831 check_shared_dpll_state(dev);
12832}
12833
5cec258b 12834void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12835 int dotclock)
12836{
12837 /*
12838 * FDI already provided one idea for the dotclock.
12839 * Yell if the encoder disagrees.
12840 */
2d112de7 12841 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12842 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12843 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12844}
12845
80715b2f
VS		 12846static void update_scanline_offset(struct intel_crtc *crtc)
12847{
12848 struct drm_device *dev = crtc->base.dev;
12849
12850 /*
12851 * The scanline counter increments at the leading edge of hsync.
12852 *
12853 * On most platforms it starts counting from vtotal-1 on the
12854 * first active line. That means the scanline counter value is
12855 * always one less than what we would expect. Ie. just after
12856 * start of vblank, which also occurs at start of hsync (on the
12857 * last active line), the scanline counter will read vblank_start-1.
12858 *
12859 * On gen2 the scanline counter starts counting from 1 instead
12860 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12861 * to keep the value positive), instead of adding one.
12862 *
12863 * On HSW+ the behaviour of the scanline counter depends on the output
12864 * type. For DP ports it behaves like most other platforms, but on HDMI
12865 * there's an extra 1 line difference. So we need to add two instead of
12866 * one to the value.
12867 */
12868 if (IS_GEN2(dev)) {
124abe07 12869 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12870 int vtotal;
12871
124abe07
VS		 12872 vtotal = adjusted_mode->crtc_vtotal;
12873 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
80715b2f
VS		 12874 vtotal /= 2;
12875
12876 crtc->scanline_offset = vtotal - 1;
12877 } else if (HAS_DDI(dev) &&
409ee761 12878 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12879 crtc->scanline_offset = 2;
12880 } else
12881 crtc->scanline_offset = 1;
12882}
12883
ad421372 12884static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12885{
225da59b 12886 struct drm_device *dev = state->dev;
ed6739ef 12887 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12888 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12889 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12890 struct intel_crtc_state *intel_crtc_state;
12891 struct drm_crtc *crtc;
12892 struct drm_crtc_state *crtc_state;
0a9ab303 12893 int i;
ed6739ef
ACO		 12894
12895 if (!dev_priv->display.crtc_compute_clock)
ad421372 12896 return;
ed6739ef 12897
0a9ab303 12898 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12899 int dpll;
12900
0a9ab303 12901 intel_crtc = to_intel_crtc(crtc);
4978cc93 12902 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12903 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12904
ad421372 12905 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12906 continue;
12907
ad421372 12908 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12909
ad421372
ML		 12910 if (!shared_dpll)
12911 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12912
ad421372
ML		 12913 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12914 }
ed6739ef
ACO		 12915}
12916
99d736a2
ML		 12917/*
12918 * This implements the workaround described in the "notes" section of the mode
12919 * set sequence documentation. When going from no pipes or single pipe to
12920 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12921 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12922 */
12923static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12924{
12925 struct drm_crtc_state *crtc_state;
12926 struct intel_crtc *intel_crtc;
12927 struct drm_crtc *crtc;
12928 struct intel_crtc_state *first_crtc_state = NULL;
12929 struct intel_crtc_state *other_crtc_state = NULL;
12930 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12931 int i;
12932
12933 /* look at all crtc's that are going to be enabled in during modeset */
12934 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12935 intel_crtc = to_intel_crtc(crtc);
12936
12937 if (!crtc_state->active || !needs_modeset(crtc_state))
12938 continue;
12939
12940 if (first_crtc_state) {
12941 other_crtc_state = to_intel_crtc_state(crtc_state);
12942 break;
12943 } else {
12944 first_crtc_state = to_intel_crtc_state(crtc_state);
12945 first_pipe = intel_crtc->pipe;
12946 }
12947 }
12948
12949 /* No workaround needed? */
12950 if (!first_crtc_state)
12951 return 0;
12952
12953 /* w/a possibly needed, check how many crtc's are already enabled. */
12954 for_each_intel_crtc(state->dev, intel_crtc) {
12955 struct intel_crtc_state *pipe_config;
12956
12957 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12958 if (IS_ERR(pipe_config))
12959 return PTR_ERR(pipe_config);
12960
12961 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12962
12963 if (!pipe_config->base.active ||
12964 needs_modeset(&pipe_config->base))
12965 continue;
12966
12967 /* 2 or more enabled crtcs means no need for w/a */
12968 if (enabled_pipe != INVALID_PIPE)
12969 return 0;
12970
12971 enabled_pipe = intel_crtc->pipe;
12972 }
12973
12974 if (enabled_pipe != INVALID_PIPE)
12975 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12976 else if (other_crtc_state)
12977 other_crtc_state->hsw_workaround_pipe = first_pipe;
12978
12979 return 0;
12980}
12981
27c329ed
ML		 12982static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12983{
12984 struct drm_crtc *crtc;
12985 struct drm_crtc_state *crtc_state;
12986 int ret = 0;
12987
12988 /* add all active pipes to the state */
12989 for_each_crtc(state->dev, crtc) {
12990 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12991 if (IS_ERR(crtc_state))
12992 return PTR_ERR(crtc_state);
12993
12994 if (!crtc_state->active || needs_modeset(crtc_state))
12995 continue;
12996
12997 crtc_state->mode_changed = true;
12998
12999 ret = drm_atomic_add_affected_connectors(state, crtc);
13000 if (ret)
13001 break;
13002
13003 ret = drm_atomic_add_affected_planes(state, crtc);
13004 if (ret)
13005 break;
13006 }
13007
13008 return ret;
13009}
13010
c347a676 13011static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 13012{
13013 struct drm_device *dev = state->dev;
27c329ed 13014 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 13015 int ret;
13016
b359283a
ML		 13017 if (!check_digital_port_conflicts(state)) {
13018 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13019 return -EINVAL;
13020 }
13021
054518dd
ACO		 13022 /*
13023 * See if the config requires any additional preparation, e.g.
13024 * to adjust global state with pipes off. We need to do this
13025 * here so we can get the modeset_pipe updated config for the new
13026 * mode set on this crtc. For other crtcs we need to use the
13027 * adjusted_mode bits in the crtc directly.
13028 */
27c329ed
ML		 13029 if (dev_priv->display.modeset_calc_cdclk) {
13030 unsigned int cdclk;
b432e5cf 13031
27c329ed
ML		 13032 ret = dev_priv->display.modeset_calc_cdclk(state);
13033
13034 cdclk = to_intel_atomic_state(state)->cdclk;
13035 if (!ret && cdclk != dev_priv->cdclk_freq)
13036 ret = intel_modeset_all_pipes(state);
13037
13038 if (ret < 0)
054518dd 13039 return ret;
27c329ed
ML		 13040 } else
13041 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13042
ad421372 13043 intel_modeset_clear_plls(state);
054518dd 13044
99d736a2 13045 if (IS_HASWELL(dev))
ad421372 13046 return haswell_mode_set_planes_workaround(state);
99d736a2 13047
ad421372 13048 return 0;
c347a676
ACO		 13049}
13050
aa363136
MR		 13051/*
13052 * Handle calculation of various watermark data at the end of the atomic check
13053 * phase. The code here should be run after the per-crtc and per-plane 'check'
13054 * handlers to ensure that all derived state has been updated.
13055 */
13056static void calc_watermark_data(struct drm_atomic_state *state)
13057{
13058 struct drm_device *dev = state->dev;
13059 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13060 struct drm_crtc *crtc;
13061 struct drm_crtc_state *cstate;
13062 struct drm_plane *plane;
13063 struct drm_plane_state *pstate;
13064
13065 /*
13066 * Calculate watermark configuration details now that derived
13067 * plane/crtc state is all properly updated.
13068 */
13069 drm_for_each_crtc(crtc, dev) {
13070 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13071 crtc->state;
13072
13073 if (cstate->active)
13074 intel_state->wm_config.num_pipes_active++;
13075 }
13076 drm_for_each_legacy_plane(plane, dev) {
13077 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13078 plane->state;
13079
13080 if (!to_intel_plane_state(pstate)->visible)
13081 continue;
13082
13083 intel_state->wm_config.sprites_enabled = true;
13084 if (pstate->crtc_w != pstate->src_w >> 16 ||
13085 pstate->crtc_h != pstate->src_h >> 16)
13086 intel_state->wm_config.sprites_scaled = true;
13087 }
13088}
13089
74c090b1
ML		 13090/**
13091 * intel_atomic_check - validate state object
13092 * @dev: drm device
13093 * @state: state to validate
13094 */
13095static int intel_atomic_check(struct drm_device *dev,
13096 struct drm_atomic_state *state)
c347a676 13097{
aa363136 13098 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
c347a676
ACO		 13099 struct drm_crtc *crtc;
13100 struct drm_crtc_state *crtc_state;
13101 int ret, i;
61333b60 13102 bool any_ms = false;
c347a676 13103
74c090b1 13104 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 13105 if (ret)
13106 return ret;
13107
c347a676 13108 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 13109 struct intel_crtc_state *pipe_config =
13110 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 13111
13112 /* Catch I915_MODE_FLAG_INHERITED */
13113 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13114 crtc_state->mode_changed = true;
cfb23ed6 13115
61333b60
ML		 13116 if (!crtc_state->enable) {
13117 if (needs_modeset(crtc_state))
13118 any_ms = true;
c347a676 13119 continue;
61333b60 13120 }
c347a676 13121
26495481 13122 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 13123 continue;
13124
26495481
DV		 13125 /* FIXME: For only active_changed we shouldn't need to do any
13126 * state recomputation at all. */
13127
1ed51de9
DV		 13128 ret = drm_atomic_add_affected_connectors(state, crtc);
13129 if (ret)
13130 return ret;
b359283a 13131
cfb23ed6 13132 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13133 if (ret)
13134 return ret;
13135
6764e9f8 13136 if (intel_pipe_config_compare(state->dev,
cfb23ed6 13137 to_intel_crtc_state(crtc->state),
1ed51de9 13138 pipe_config, true)) {
26495481 13139 crtc_state->mode_changed = false;
bfd16b2a 13140 to_intel_crtc_state(crtc_state)->update_pipe = true;
26495481
DV		 13141 }
13142
13143 if (needs_modeset(crtc_state)) {
13144 any_ms = true;
cfb23ed6
ML		 13145
13146 ret = drm_atomic_add_affected_planes(state, crtc);
13147 if (ret)
13148 return ret;
13149 }
61333b60 13150
26495481
DV		 13151 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13152 needs_modeset(crtc_state) ?
13153 "[modeset]" : "[fastset]");
c347a676
ACO		 13154 }
13155
61333b60
ML		 13156 if (any_ms) {
13157 ret = intel_modeset_checks(state);
13158
13159 if (ret)
13160 return ret;
27c329ed 13161 } else
aa363136 13162 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
76305b1a 13163
aa363136
MR		 13164 ret = drm_atomic_helper_check_planes(state->dev, state);
13165 if (ret)
13166 return ret;
13167
13168 calc_watermark_data(state);
13169
13170 return 0;
054518dd
ACO		 13171}
13172
5008e874
ML		 13173static int intel_atomic_prepare_commit(struct drm_device *dev,
13174 struct drm_atomic_state *state,
13175 bool async)
13176{
7580d774
ML		 13177 struct drm_i915_private *dev_priv = dev->dev_private;
13178 struct drm_plane_state *plane_state;
5008e874 13179 struct drm_crtc_state *crtc_state;
7580d774 13180 struct drm_plane *plane;
5008e874
ML		 13181 struct drm_crtc *crtc;
13182 int i, ret;
13183
13184 if (async) {
13185 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13186 return -EINVAL;
13187 }
13188
13189 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13190 ret = intel_crtc_wait_for_pending_flips(crtc);
13191 if (ret)
13192 return ret;
7580d774
ML		 13193
13194 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13195 flush_workqueue(dev_priv->wq);
5008e874
ML		 13196 }
13197
f935675f
ML		 13198 ret = mutex_lock_interruptible(&dev->struct_mutex);
13199 if (ret)
13200 return ret;
13201
5008e874 13202 ret = drm_atomic_helper_prepare_planes(dev, state);
7580d774
ML		 13203 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13204 u32 reset_counter;
13205
13206 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13207 mutex_unlock(&dev->struct_mutex);
13208
13209 for_each_plane_in_state(state, plane, plane_state, i) {
13210 struct intel_plane_state *intel_plane_state =
13211 to_intel_plane_state(plane_state);
13212
13213 if (!intel_plane_state->wait_req)
13214 continue;
13215
13216 ret = __i915_wait_request(intel_plane_state->wait_req,
13217 reset_counter, true,
13218 NULL, NULL);
13219
13220 /* Swallow -EIO errors to allow updates during hw lockup. */
13221 if (ret == -EIO)
13222 ret = 0;
13223
13224 if (ret)
13225 break;
13226 }
13227
13228 if (!ret)
13229 return 0;
13230
13231 mutex_lock(&dev->struct_mutex);
13232 drm_atomic_helper_cleanup_planes(dev, state);
13233 }
5008e874 13234
f935675f 13235 mutex_unlock(&dev->struct_mutex);
5008e874
ML		 13236 return ret;
13237}
13238
74c090b1
ML		 13239/**
13240 * intel_atomic_commit - commit validated state object
13241 * @dev: DRM device
13242 * @state: the top-level driver state object
13243 * @async: asynchronous commit
13244 *
13245 * This function commits a top-level state object that has been validated
13246 * with drm_atomic_helper_check().
13247 *
13248 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13249 * we can only handle plane-related operations and do not yet support
13250 * asynchronous commit.
13251 *
13252 * RETURNS
13253 * Zero for success or -errno.
13254 */
13255static int intel_atomic_commit(struct drm_device *dev,
13256 struct drm_atomic_state *state,
13257 bool async)
a6778b3c 13258{
fbee40df 13259 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303 13260 struct drm_crtc_state *crtc_state;
7580d774 13261 struct drm_crtc *crtc;
c0c36b94 13262 int ret = 0;
0a9ab303 13263 int i;
61333b60 13264 bool any_ms = false;
a6778b3c 13265
5008e874 13266 ret = intel_atomic_prepare_commit(dev, state, async);
7580d774
ML		 13267 if (ret) {
13268 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
d4afb8cc 13269 return ret;
7580d774 13270 }
d4afb8cc 13271
1c5e19f8 13272 drm_atomic_helper_swap_state(dev, state);
aa363136 13273 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
1c5e19f8 13274
0a9ab303 13275 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13277
61333b60
ML		 13278 if (!needs_modeset(crtc->state))
13279 continue;
13280
13281 any_ms = true;
a539205a 13282 intel_pre_plane_update(intel_crtc);
460da916 13283
a539205a
ML		 13284 if (crtc_state->active) {
13285 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13286 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13287 intel_crtc->active = false;
13288 intel_disable_shared_dpll(intel_crtc);
a539205a 13289 }
b8cecdf5 13290 }
7758a113 13291
ea9d758d
DV		 13292 /* Only after disabling all output pipelines that will be changed can we
13293 * update the the output configuration. */
4740b0f2 13294 intel_modeset_update_crtc_state(state);
f6e5b160 13295
4740b0f2
ML		 13296 if (any_ms) {
13297 intel_shared_dpll_commit(state);
13298
13299 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13300 modeset_update_crtc_power_domains(state);
4740b0f2 13301 }
47fab737 13302
a6778b3c 13303 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13304 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13306 bool modeset = needs_modeset(crtc->state);
bfd16b2a
ML		 13307 bool update_pipe = !modeset &&
13308 to_intel_crtc_state(crtc->state)->update_pipe;
13309 unsigned long put_domains = 0;
f6ac4b2a
ML		 13310
13311 if (modeset && crtc->state->active) {
a539205a
ML		 13312 update_scanline_offset(to_intel_crtc(crtc));
13313 dev_priv->display.crtc_enable(crtc);
13314 }
80715b2f 13315
bfd16b2a
ML		 13316 if (update_pipe) {
13317 put_domains = modeset_get_crtc_power_domains(crtc);
13318
13319 /* make sure intel_modeset_check_state runs */
13320 any_ms = true;
13321 }
13322
f6ac4b2a
ML		 13323 if (!modeset)
13324 intel_pre_plane_update(intel_crtc);
13325
6173ee28
ML		 13326 if (crtc->state->active &&
13327 (crtc->state->planes_changed || update_pipe))
62852622 13328 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
bfd16b2a
ML		 13329
13330 if (put_domains)
13331 modeset_put_power_domains(dev_priv, put_domains);
13332
f6ac4b2a 13333 intel_post_plane_update(intel_crtc);
80715b2f 13334 }
a6778b3c 13335
a6778b3c 13336 /* FIXME: add subpixel order */
83a57153 13337
74c090b1 13338 drm_atomic_helper_wait_for_vblanks(dev, state);
f935675f
ML		 13339
13340 mutex_lock(&dev->struct_mutex);
d4afb8cc 13341 drm_atomic_helper_cleanup_planes(dev, state);
f935675f 13342 mutex_unlock(&dev->struct_mutex);
2bfb4627 13343
74c090b1 13344 if (any_ms)
ee165b1a
ML		 13345 intel_modeset_check_state(dev, state);
13346
13347 drm_atomic_state_free(state);
f30da187 13348
74c090b1 13349 return 0;
7f27126e
JB		 13350}
13351
c0c36b94
CW		 13352void intel_crtc_restore_mode(struct drm_crtc *crtc)
13353{
83a57153
ACO		 13354 struct drm_device *dev = crtc->dev;
13355 struct drm_atomic_state *state;
e694eb02 13356 struct drm_crtc_state *crtc_state;
2bfb4627 13357 int ret;
83a57153
ACO		 13358
13359 state = drm_atomic_state_alloc(dev);
13360 if (!state) {
e694eb02 13361 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13362 crtc->base.id);
13363 return;
13364 }
13365
e694eb02 13366 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13367
e694eb02
ML		 13368retry:
13369 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13370 ret = PTR_ERR_OR_ZERO(crtc_state);
13371 if (!ret) {
13372 if (!crtc_state->active)
13373 goto out;
83a57153 13374
e694eb02 13375 crtc_state->mode_changed = true;
74c090b1 13376 ret = drm_atomic_commit(state);
83a57153
ACO		 13377 }
13378
e694eb02
ML		 13379 if (ret == -EDEADLK) {
13380 drm_atomic_state_clear(state);
13381 drm_modeset_backoff(state->acquire_ctx);
13382 goto retry;
4ed9fb37 13383 }
4be07317 13384
2bfb4627 13385 if (ret)
e694eb02 13386out:
2bfb4627 13387 drm_atomic_state_free(state);
c0c36b94
CW		 13388}
13389
25c5b266
DV		 13390#undef for_each_intel_crtc_masked
13391
f6e5b160 13392static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13393 .gamma_set = intel_crtc_gamma_set,
74c090b1 13394 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13395 .destroy = intel_crtc_destroy,
13396 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13397 .atomic_duplicate_state = intel_crtc_duplicate_state,
13398 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13399};
13400
5358901f
DV		 13401static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13402 struct intel_shared_dpll *pll,
13403 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13404{
5358901f 13405 uint32_t val;
ee7b9f93 13406
f458ebbc 13407 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13408 return false;
13409
5358901f 13410 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13411 hw_state->dpll = val;
13412 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13413 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13414
13415 return val & DPLL_VCO_ENABLE;
13416}
13417
15bdd4cf
DV		 13418static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13419 struct intel_shared_dpll *pll)
13420{
3e369b76
ACO		 13421 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13422 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13423}
13424
e7b903d2
DV		 13425static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13426 struct intel_shared_dpll *pll)
13427{
e7b903d2 13428 /* PCH refclock must be enabled first */
89eff4be 13429 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13430
3e369b76 13431 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13432
13433 /* Wait for the clocks to stabilize. */
13434 POSTING_READ(PCH_DPLL(pll->id));
13435 udelay(150);
13436
13437 /* The pixel multiplier can only be updated once the
13438 * DPLL is enabled and the clocks are stable.
13439 *
13440 * So write it again.
13441 */
3e369b76 13442 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13443 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13444 udelay(200);
13445}
13446
13447static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13448 struct intel_shared_dpll *pll)
13449{
13450 struct drm_device *dev = dev_priv->dev;
13451 struct intel_crtc *crtc;
e7b903d2
DV		 13452
13453 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13454 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13455 if (intel_crtc_to_shared_dpll(crtc) == pll)
13456 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13457 }
13458
15bdd4cf
DV		 13459 I915_WRITE(PCH_DPLL(pll->id), 0);
13460 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13461 udelay(200);
13462}
13463
46edb027
DV		 13464static char *ibx_pch_dpll_names[] = {
13465 "PCH DPLL A",
13466 "PCH DPLL B",
13467};
13468
7c74ade1 13469static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13470{
e7b903d2 13471 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13472 int i;
13473
7c74ade1 13474 dev_priv->num_shared_dpll = 2;
ee7b9f93 13475
e72f9fbf 13476 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13477 dev_priv->shared_dplls[i].id = i;
13478 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13479 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13480 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13481 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13482 dev_priv->shared_dplls[i].get_hw_state =
13483 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13484 }
13485}
13486
7c74ade1
DV		 13487static void intel_shared_dpll_init(struct drm_device *dev)
13488{
e7b903d2 13489 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13490
9cd86933
DV		 13491 if (HAS_DDI(dev))
13492 intel_ddi_pll_init(dev);
13493 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13494 ibx_pch_dpll_init(dev);
13495 else
13496 dev_priv->num_shared_dpll = 0;
13497
13498 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13499}
13500
6beb8c23
MR		 13501/**
13502 * intel_prepare_plane_fb - Prepare fb for usage on plane
13503 * @plane: drm plane to prepare for
13504 * @fb: framebuffer to prepare for presentation
13505 *
13506 * Prepares a framebuffer for usage on a display plane. Generally this
13507 * involves pinning the underlying object and updating the frontbuffer tracking
13508 * bits. Some older platforms need special physical address handling for
13509 * cursor planes.
13510 *
f935675f
ML		 13511 * Must be called with struct_mutex held.
13512 *
6beb8c23
MR		 13513 * Returns 0 on success, negative error code on failure.
13514 */
13515int
13516intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee 13517 const struct drm_plane_state *new_state)
465c120c
MR		 13518{
13519 struct drm_device *dev = plane->dev;
844f9111 13520 struct drm_framebuffer *fb = new_state->fb;
6beb8c23 13521 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23 13522 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1ee49399 13523 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
6beb8c23 13524 int ret = 0;
465c120c 13525
1ee49399 13526 if (!obj && !old_obj)
465c120c
MR		 13527 return 0;
13528
5008e874
ML		 13529 if (old_obj) {
13530 struct drm_crtc_state *crtc_state =
13531 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13532
13533 /* Big Hammer, we also need to ensure that any pending
13534 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13535 * current scanout is retired before unpinning the old
13536 * framebuffer. Note that we rely on userspace rendering
13537 * into the buffer attached to the pipe they are waiting
13538 * on. If not, userspace generates a GPU hang with IPEHR
13539 * point to the MI_WAIT_FOR_EVENT.
13540 *
13541 * This should only fail upon a hung GPU, in which case we
13542 * can safely continue.
13543 */
13544 if (needs_modeset(crtc_state))
13545 ret = i915_gem_object_wait_rendering(old_obj, true);
13546
13547 /* Swallow -EIO errors to allow updates during hw lockup. */
13548 if (ret && ret != -EIO)
f935675f 13549 return ret;
5008e874
ML		 13550 }
13551
1ee49399
ML		 13552 if (!obj) {
13553 ret = 0;
13554 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
6beb8c23
MR		 13555 INTEL_INFO(dev)->cursor_needs_physical) {
13556 int align = IS_I830(dev) ? 16 * 1024 : 256;
13557 ret = i915_gem_object_attach_phys(obj, align);
13558 if (ret)
13559 DRM_DEBUG_KMS("failed to attach phys object\n");
13560 } else {
7580d774 13561 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
6beb8c23 13562 }
465c120c 13563
7580d774
ML		 13564 if (ret == 0) {
13565 if (obj) {
13566 struct intel_plane_state *plane_state =
13567 to_intel_plane_state(new_state);
13568
13569 i915_gem_request_assign(&plane_state->wait_req,
13570 obj->last_write_req);
13571 }
13572
a9ff8714 13573 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
7580d774 13574 }
fdd508a6 13575
6beb8c23
MR		 13576 return ret;
13577}
13578
38f3ce3a
MR		 13579/**
13580 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13581 * @plane: drm plane to clean up for
13582 * @fb: old framebuffer that was on plane
13583 *
13584 * Cleans up a framebuffer that has just been removed from a plane.
f935675f
ML		 13585 *
13586 * Must be called with struct_mutex held.
38f3ce3a
MR		 13587 */
13588void
13589intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee 13590 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13591{
13592 struct drm_device *dev = plane->dev;
1ee49399 13593 struct intel_plane *intel_plane = to_intel_plane(plane);
7580d774 13594 struct intel_plane_state *old_intel_state;
1ee49399
ML		 13595 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13596 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
38f3ce3a 13597
7580d774
ML		 13598 old_intel_state = to_intel_plane_state(old_state);
13599
1ee49399 13600 if (!obj && !old_obj)
38f3ce3a
MR		 13601 return;
13602
1ee49399
ML		 13603 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13604 !INTEL_INFO(dev)->cursor_needs_physical))
844f9111 13605 intel_unpin_fb_obj(old_state->fb, old_state);
1ee49399
ML		 13606
13607 /* prepare_fb aborted? */
13608 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13609 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13610 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
7580d774
ML		 13611
13612 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13613
465c120c
MR		 13614}
13615
6156a456
CK		 13616int
13617skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13618{
13619 int max_scale;
13620 struct drm_device *dev;
13621 struct drm_i915_private *dev_priv;
13622 int crtc_clock, cdclk;
13623
13624 if (!intel_crtc || !crtc_state)
13625 return DRM_PLANE_HELPER_NO_SCALING;
13626
13627 dev = intel_crtc->base.dev;
13628 dev_priv = dev->dev_private;
13629 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13630 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456 13631
54bf1ce6 13632 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
6156a456
CK		 13633 return DRM_PLANE_HELPER_NO_SCALING;
13634
13635 /*
13636 * skl max scale is lower of:
13637 * close to 3 but not 3, -1 is for that purpose
13638 * or
13639 * cdclk/crtc_clock
13640 */
13641 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13642
13643 return max_scale;
13644}
13645
465c120c 13646static int
3c692a41 13647intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13648 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13649 struct intel_plane_state *state)
13650{
2b875c22
MR		 13651 struct drm_crtc *crtc = state->base.crtc;
13652 struct drm_framebuffer *fb = state->base.fb;
6156a456 13653 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13654 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13655 bool can_position = false;
465c120c 13656
061e4b8d
ML		 13657 /* use scaler when colorkey is not required */
13658 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13659 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13660 min_scale = 1;
13661 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13662 can_position = true;
6156a456 13663 }
d8106366 13664
061e4b8d
ML		 13665 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13666 &state->dst, &state->clip,
da20eabd
ML		 13667 min_scale, max_scale,
13668 can_position, true,
13669 &state->visible);
14af293f
GP		 13670}
13671
13672static void
13673intel_commit_primary_plane(struct drm_plane *plane,
13674 struct intel_plane_state *state)
13675{
2b875c22
MR		 13676 struct drm_crtc *crtc = state->base.crtc;
13677 struct drm_framebuffer *fb = state->base.fb;
13678 struct drm_device *dev = plane->dev;
14af293f 13679 struct drm_i915_private *dev_priv = dev->dev_private;
14af293f 13680
ea2c67bb 13681 crtc = crtc ? crtc : plane->crtc;
ccc759dc 13682
d4b08630
ML		 13683 dev_priv->display.update_primary_plane(crtc, fb,
13684 state->src.x1 >> 16,
13685 state->src.y1 >> 16);
465c120c
MR		 13686}
13687
a8ad0d8e
ML		 13688static void
13689intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13690 struct drm_crtc *crtc)
a8ad0d8e
ML		 13691{
13692 struct drm_device *dev = plane->dev;
13693 struct drm_i915_private *dev_priv = dev->dev_private;
13694
a8ad0d8e
ML		 13695 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13696}
13697
613d2b27
ML		 13698static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13699 struct drm_crtc_state *old_crtc_state)
3c692a41 13700{
32b7eeec 13701 struct drm_device *dev = crtc->dev;
3c692a41 13702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
bfd16b2a
ML		 13703 struct intel_crtc_state *old_intel_state =
13704 to_intel_crtc_state(old_crtc_state);
13705 bool modeset = needs_modeset(crtc->state);
3c692a41 13706
f015c551 13707 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13708 intel_update_watermarks(crtc);
3c692a41 13709
c34c9ee4 13710 /* Perform vblank evasion around commit operation */
62852622 13711 intel_pipe_update_start(intel_crtc);
0583236e 13712
bfd16b2a
ML		 13713 if (modeset)
13714 return;
13715
13716 if (to_intel_crtc_state(crtc->state)->update_pipe)
13717 intel_update_pipe_config(intel_crtc, old_intel_state);
13718 else if (INTEL_INFO(dev)->gen >= 9)
0583236e 13719 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13720}
13721
613d2b27
ML		 13722static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13723 struct drm_crtc_state *old_crtc_state)
32b7eeec 13724{
32b7eeec 13725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13726
62852622 13727 intel_pipe_update_end(intel_crtc);
3c692a41
GP		 13728}
13729
cf4c7c12 13730/**
4a3b8769
MR		 13731 * intel_plane_destroy - destroy a plane
13732 * @plane: plane to destroy
cf4c7c12 13733 *
4a3b8769
MR		 13734 * Common destruction function for all types of planes (primary, cursor,
13735 * sprite).
cf4c7c12 13736 */
4a3b8769 13737void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13738{
13739 struct intel_plane *intel_plane = to_intel_plane(plane);
13740 drm_plane_cleanup(plane);
13741 kfree(intel_plane);
13742}
13743
65a3fea0 13744const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13745 .update_plane = drm_atomic_helper_update_plane,
13746 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13747 .destroy = intel_plane_destroy,
c196e1d6 13748 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13749 .atomic_get_property = intel_plane_atomic_get_property,
13750 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13751 .atomic_duplicate_state = intel_plane_duplicate_state,
13752 .atomic_destroy_state = intel_plane_destroy_state,
13753
465c120c
MR		 13754};
13755
13756static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13757 int pipe)
13758{
13759 struct intel_plane *primary;
8e7d688b 13760 struct intel_plane_state *state;
465c120c 13761 const uint32_t *intel_primary_formats;
45e3743a 13762 unsigned int num_formats;
465c120c
MR		 13763
13764 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13765 if (primary == NULL)
13766 return NULL;
13767
8e7d688b
MR		 13768 state = intel_create_plane_state(&primary->base);
13769 if (!state) {
ea2c67bb
MR		 13770 kfree(primary);
13771 return NULL;
13772 }
8e7d688b 13773 primary->base.state = &state->base;
ea2c67bb 13774
465c120c
MR		 13775 primary->can_scale = false;
13776 primary->max_downscale = 1;
6156a456
CK		 13777 if (INTEL_INFO(dev)->gen >= 9) {
13778 primary->can_scale = true;
af99ceda 13779 state->scaler_id = -1;
6156a456 13780 }
465c120c
MR		 13781 primary->pipe = pipe;
13782 primary->plane = pipe;
a9ff8714 13783 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13784 primary->check_plane = intel_check_primary_plane;
13785 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13786 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13787 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13788 primary->plane = !pipe;
13789
6c0fd451
DL		 13790 if (INTEL_INFO(dev)->gen >= 9) {
13791 intel_primary_formats = skl_primary_formats;
13792 num_formats = ARRAY_SIZE(skl_primary_formats);
13793 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13794 intel_primary_formats = i965_primary_formats;
13795 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13796 } else {
13797 intel_primary_formats = i8xx_primary_formats;
13798 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13799 }
13800
13801 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13802 &intel_plane_funcs,
465c120c
MR		 13803 intel_primary_formats, num_formats,
13804 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13805
3b7a5119
SJ		 13806 if (INTEL_INFO(dev)->gen >= 4)
13807 intel_create_rotation_property(dev, primary);
48404c1e 13808
ea2c67bb
MR		 13809 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13810
465c120c
MR		 13811 return &primary->base;
13812}
13813
3b7a5119
SJ		 13814void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13815{
13816 if (!dev->mode_config.rotation_property) {
13817 unsigned long flags = BIT(DRM_ROTATE_0) |
13818 BIT(DRM_ROTATE_180);
13819
13820 if (INTEL_INFO(dev)->gen >= 9)
13821 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13822
13823 dev->mode_config.rotation_property =
13824 drm_mode_create_rotation_property(dev, flags);
13825 }
13826 if (dev->mode_config.rotation_property)
13827 drm_object_attach_property(&plane->base.base,
13828 dev->mode_config.rotation_property,
13829 plane->base.state->rotation);
13830}
13831
3d7d6510 13832static int
852e787c 13833intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13834 struct intel_crtc_state *crtc_state,
852e787c 13835 struct intel_plane_state *state)
3d7d6510 13836{
061e4b8d 13837 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13838 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13839 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13840 unsigned stride;
13841 int ret;
3d7d6510 13842
061e4b8d
ML		 13843 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13844 &state->dst, &state->clip,
3d7d6510
MR		 13845 DRM_PLANE_HELPER_NO_SCALING,
13846 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13847 true, true, &state->visible);
757f9a3e
GP		 13848 if (ret)
13849 return ret;
13850
757f9a3e
GP		 13851 /* if we want to turn off the cursor ignore width and height */
13852 if (!obj)
da20eabd 13853 return 0;
757f9a3e 13854
757f9a3e 13855 /* Check for which cursor types we support */
061e4b8d 13856 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13857 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13858 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13859 return -EINVAL;
13860 }
13861
ea2c67bb
MR		 13862 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13863 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13864 DRM_DEBUG_KMS("buffer is too small\n");
13865 return -ENOMEM;
13866 }
13867
3a656b54 13868 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13869 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13870 return -EINVAL;
32b7eeec
MR		 13871 }
13872
da20eabd 13873 return 0;
852e787c 13874}
3d7d6510 13875
a8ad0d8e
ML		 13876static void
13877intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13878 struct drm_crtc *crtc)
a8ad0d8e 13879{
a8ad0d8e
ML		 13880 intel_crtc_update_cursor(crtc, false);
13881}
13882
f4a2cf29 13883static void
852e787c
GP		 13884intel_commit_cursor_plane(struct drm_plane *plane,
13885 struct intel_plane_state *state)
13886{
2b875c22 13887 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13888 struct drm_device *dev = plane->dev;
13889 struct intel_crtc *intel_crtc;
2b875c22 13890 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13891 uint32_t addr;
852e787c 13892
ea2c67bb
MR		 13893 crtc = crtc ? crtc : plane->crtc;
13894 intel_crtc = to_intel_crtc(crtc);
13895
a912f12f
GP		 13896 if (intel_crtc->cursor_bo == obj)
13897 goto update;
4ed91096 13898
f4a2cf29 13899 if (!obj)
a912f12f 13900 addr = 0;
f4a2cf29 13901 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13902 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13903 else
a912f12f 13904 addr = obj->phys_handle->busaddr;
852e787c 13905
a912f12f
GP		 13906 intel_crtc->cursor_addr = addr;
13907 intel_crtc->cursor_bo = obj;
852e787c 13908
302d19ac 13909update:
62852622 13910 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13911}
13912
3d7d6510
MR		 13913static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13914 int pipe)
13915{
13916 struct intel_plane *cursor;
8e7d688b 13917 struct intel_plane_state *state;
3d7d6510
MR		 13918
13919 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13920 if (cursor == NULL)
13921 return NULL;
13922
8e7d688b
MR		 13923 state = intel_create_plane_state(&cursor->base);
13924 if (!state) {
ea2c67bb
MR		 13925 kfree(cursor);
13926 return NULL;
13927 }
8e7d688b 13928 cursor->base.state = &state->base;
ea2c67bb 13929
3d7d6510
MR		 13930 cursor->can_scale = false;
13931 cursor->max_downscale = 1;
13932 cursor->pipe = pipe;
13933 cursor->plane = pipe;
a9ff8714 13934 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13935 cursor->check_plane = intel_check_cursor_plane;
13936 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13937 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13938
13939 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13940 &intel_plane_funcs,
3d7d6510
MR		 13941 intel_cursor_formats,
13942 ARRAY_SIZE(intel_cursor_formats),
13943 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13944
13945 if (INTEL_INFO(dev)->gen >= 4) {
13946 if (!dev->mode_config.rotation_property)
13947 dev->mode_config.rotation_property =
13948 drm_mode_create_rotation_property(dev,
13949 BIT(DRM_ROTATE_0) |
13950 BIT(DRM_ROTATE_180));
13951 if (dev->mode_config.rotation_property)
13952 drm_object_attach_property(&cursor->base.base,
13953 dev->mode_config.rotation_property,
8e7d688b 13954 state->base.rotation);
4398ad45
VS		 13955 }
13956
af99ceda
CK		 13957 if (INTEL_INFO(dev)->gen >=9)
13958 state->scaler_id = -1;
13959
ea2c67bb
MR		 13960 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13961
3d7d6510
MR		 13962 return &cursor->base;
13963}
13964
549e2bfb
CK		 13965static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13966 struct intel_crtc_state *crtc_state)
13967{
13968 int i;
13969 struct intel_scaler *intel_scaler;
13970 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13971
13972 for (i = 0; i < intel_crtc->num_scalers; i++) {
13973 intel_scaler = &scaler_state->scalers[i];
13974 intel_scaler->in_use = 0;
549e2bfb
CK		 13975 intel_scaler->mode = PS_SCALER_MODE_DYN;
13976 }
13977
13978 scaler_state->scaler_id = -1;
13979}
13980
b358d0a6 13981static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13982{
fbee40df 13983 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13984 struct intel_crtc *intel_crtc;
f5de6e07 13985 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13986 struct drm_plane *primary = NULL;
13987 struct drm_plane *cursor = NULL;
465c120c 13988 int i, ret;
79e53945 13989
955382f3 13990 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13991 if (intel_crtc == NULL)
13992 return;
13993
f5de6e07
ACO		 13994 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13995 if (!crtc_state)
13996 goto fail;
550acefd
ACO		 13997 intel_crtc->config = crtc_state;
13998 intel_crtc->base.state = &crtc_state->base;
07878248 13999 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14000
549e2bfb
CK		 14001 /* initialize shared scalers */
14002 if (INTEL_INFO(dev)->gen >= 9) {
14003 if (pipe == PIPE_C)
14004 intel_crtc->num_scalers = 1;
14005 else
14006 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14007
14008 skl_init_scalers(dev, intel_crtc, crtc_state);
14009 }
14010
465c120c 14011 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14012 if (!primary)
14013 goto fail;
14014
14015 cursor = intel_cursor_plane_create(dev, pipe);
14016 if (!cursor)
14017 goto fail;
14018
465c120c 14019 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14020 cursor, &intel_crtc_funcs);
14021 if (ret)
14022 goto fail;
79e53945
JB		 14023
14024 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14025 for (i = 0; i < 256; i++) {
14026 intel_crtc->lut_r[i] = i;
14027 intel_crtc->lut_g[i] = i;
14028 intel_crtc->lut_b[i] = i;
14029 }
14030
1f1c2e24
VS		 14031 /*
14032 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14033 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14034 */
80824003
JB		 14035 intel_crtc->pipe = pipe;
14036 intel_crtc->plane = pipe;
3a77c4c4 14037 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14038 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14039 intel_crtc->plane = !pipe;
80824003
JB		 14040 }
14041
4b0e333e
CW		 14042 intel_crtc->cursor_base = ~0;
14043 intel_crtc->cursor_cntl = ~0;
dc41c154 14044 intel_crtc->cursor_size = ~0;
8d7849db 14045
852eb00d
VS		 14046 intel_crtc->wm.cxsr_allowed = true;
14047
22fd0fab
JB		 14048 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14049 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14050 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14051 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14052
79e53945 14053 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14054
14055 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14056 return;
14057
14058fail:
14059 if (primary)
14060 drm_plane_cleanup(primary);
14061 if (cursor)
14062 drm_plane_cleanup(cursor);
f5de6e07 14063 kfree(crtc_state);
3d7d6510 14064 kfree(intel_crtc);
79e53945
JB		 14065}
14066
752aa88a
JB		 14067enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14068{
14069 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14070 struct drm_device *dev = connector->base.dev;
752aa88a 14071
51fd371b 14072 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14073
d3babd3f 14074 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14075 return INVALID_PIPE;
14076
14077 return to_intel_crtc(encoder->crtc)->pipe;
14078}
14079
08d7b3d1 14080int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14081 struct drm_file *file)
08d7b3d1 14082{
08d7b3d1 14083 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14084 struct drm_crtc *drmmode_crtc;
c05422d5 14085 struct intel_crtc *crtc;
08d7b3d1 14086
7707e653 14087 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14088
7707e653 14089 if (!drmmode_crtc) {
08d7b3d1 14090 DRM_ERROR("no such CRTC id\n");
3f2c2057 14091 return -ENOENT;
08d7b3d1
CW		 14092 }
14093
7707e653 14094 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14095 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14096
c05422d5 14097 return 0;
08d7b3d1
CW		 14098}
14099
66a9278e 14100static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14101{
66a9278e
DV		 14102 struct drm_device *dev = encoder->base.dev;
14103 struct intel_encoder *source_encoder;
79e53945 14104 int index_mask = 0;
79e53945
JB		 14105 int entry = 0;
14106
b2784e15 14107 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14108 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14109 index_mask |= (1 << entry);
14110
79e53945
JB		 14111 entry++;
14112 }
4ef69c7a 14113
79e53945
JB		 14114 return index_mask;
14115}
14116
4d302442
CW		 14117static bool has_edp_a(struct drm_device *dev)
14118{
14119 struct drm_i915_private *dev_priv = dev->dev_private;
14120
14121 if (!IS_MOBILE(dev))
14122 return false;
14123
14124 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14125 return false;
14126
e3589908 14127 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14128 return false;
14129
14130 return true;
14131}
14132
84b4e042
JB		 14133static bool intel_crt_present(struct drm_device *dev)
14134{
14135 struct drm_i915_private *dev_priv = dev->dev_private;
14136
884497ed
DL		 14137 if (INTEL_INFO(dev)->gen >= 9)
14138 return false;
14139
cf404ce4 14140 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14141 return false;
14142
14143 if (IS_CHERRYVIEW(dev))
14144 return false;
14145
14146 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14147 return false;
14148
14149 return true;
14150}
14151
79e53945
JB		 14152static void intel_setup_outputs(struct drm_device *dev)
14153{
725e30ad 14154 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14155 struct intel_encoder *encoder;
cb0953d7 14156 bool dpd_is_edp = false;
79e53945 14157
c9093354 14158 intel_lvds_init(dev);
79e53945 14159
84b4e042 14160 if (intel_crt_present(dev))
79935fca 14161 intel_crt_init(dev);
cb0953d7 14162
c776eb2e
VK		 14163 if (IS_BROXTON(dev)) {
14164 /*
14165 * FIXME: Broxton doesn't support port detection via the
14166 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14167 * detect the ports.
14168 */
14169 intel_ddi_init(dev, PORT_A);
14170 intel_ddi_init(dev, PORT_B);
14171 intel_ddi_init(dev, PORT_C);
14172 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14173 int found;
14174
de31facd
JB		 14175 /*
14176 * Haswell uses DDI functions to detect digital outputs.
14177 * On SKL pre-D0 the strap isn't connected, so we assume
14178 * it's there.
14179 */
77179400 14180 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
de31facd 14181 /* WaIgnoreDDIAStrap: skl */
ef11bdb3 14182 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
0e72a5b5
ED		 14183 intel_ddi_init(dev, PORT_A);
14184
14185 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14186 * register */
14187 found = I915_READ(SFUSE_STRAP);
14188
14189 if (found & SFUSE_STRAP_DDIB_DETECTED)
14190 intel_ddi_init(dev, PORT_B);
14191 if (found & SFUSE_STRAP_DDIC_DETECTED)
14192 intel_ddi_init(dev, PORT_C);
14193 if (found & SFUSE_STRAP_DDID_DETECTED)
14194 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 14195 /*
14196 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14197 */
ef11bdb3 14198 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
2800e4c2
RV		 14199 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14200 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14201 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14202 intel_ddi_init(dev, PORT_E);
14203
0e72a5b5 14204 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14205 int found;
5d8a7752 14206 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14207
14208 if (has_edp_a(dev))
14209 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14210
dc0fa718 14211 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14212 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14213 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14214 if (!found)
e2debe91 14215 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14216 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14217 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14218 }
14219
dc0fa718 14220 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14221 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14222
dc0fa718 14223 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14224 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14225
5eb08b69 14226 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14227 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14228
270b3042 14229 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14230 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14231 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14232 /*
14233 * The DP_DETECTED bit is the latched state of the DDC
14234 * SDA pin at boot. However since eDP doesn't require DDC
14235 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14236 * eDP ports may have been muxed to an alternate function.
14237 * Thus we can't rely on the DP_DETECTED bit alone to detect
14238 * eDP ports. Consult the VBT as well as DP_DETECTED to
14239 * detect eDP ports.
14240 */
e66eb81d 14241 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
d2182a66 14242 !intel_dp_is_edp(dev, PORT_B))
e66eb81d
VS		 14243 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14244 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
e17ac6db 14245 intel_dp_is_edp(dev, PORT_B))
e66eb81d 14246 intel_dp_init(dev, VLV_DP_B, PORT_B);
585a94b8 14247
e66eb81d 14248 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
d2182a66 14249 !intel_dp_is_edp(dev, PORT_C))
e66eb81d
VS		 14250 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14251 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
e17ac6db 14252 intel_dp_is_edp(dev, PORT_C))
e66eb81d 14253 intel_dp_init(dev, VLV_DP_C, PORT_C);
19c03924 14254
9418c1f1 14255 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14256 /* eDP not supported on port D, so don't check VBT */
e66eb81d
VS		 14257 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14258 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14259 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14260 intel_dp_init(dev, CHV_DP_D, PORT_D);
9418c1f1
VS		 14261 }
14262
3cfca973 14263 intel_dsi_init(dev);
09da55dc 14264 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14265 bool found = false;
7d57382e 14266
e2debe91 14267 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14268 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14269 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14270 if (!found && IS_G4X(dev)) {
b01f2c3a 14271 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14272 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14273 }
27185ae1 14274
3fec3d2f 14275 if (!found && IS_G4X(dev))
ab9d7c30 14276 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14277 }
13520b05
KH		 14278
14279 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14280
e2debe91 14281 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14282 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14283 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14284 }
27185ae1 14285
e2debe91 14286 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14287
3fec3d2f 14288 if (IS_G4X(dev)) {
b01f2c3a 14289 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14290 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14291 }
3fec3d2f 14292 if (IS_G4X(dev))
ab9d7c30 14293 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14294 }
27185ae1 14295
3fec3d2f 14296 if (IS_G4X(dev) &&
e7281eab 14297 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14298 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14299 } else if (IS_GEN2(dev))
79e53945
JB		 14300 intel_dvo_init(dev);
14301
103a196f 14302 if (SUPPORTS_TV(dev))
79e53945
JB		 14303 intel_tv_init(dev);
14304
0bc12bcb 14305 intel_psr_init(dev);
7c8f8a70 14306
b2784e15 14307 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14308 encoder->base.possible_crtcs = encoder->crtc_mask;
14309 encoder->base.possible_clones =
66a9278e 14310 intel_encoder_clones(encoder);
79e53945 14311 }
47356eb6 14312
dde86e2d 14313 intel_init_pch_refclk(dev);
270b3042
DV		 14314
14315 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14316}
14317
14318static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14319{
60a5ca01 14320 struct drm_device *dev = fb->dev;
79e53945 14321 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14322
ef2d633e 14323 drm_framebuffer_cleanup(fb);
60a5ca01 14324 mutex_lock(&dev->struct_mutex);
ef2d633e 14325 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14326 drm_gem_object_unreference(&intel_fb->obj->base);
14327 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14328 kfree(intel_fb);
14329}
14330
14331static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14332 struct drm_file *file,
79e53945
JB		 14333 unsigned int *handle)
14334{
14335 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14336 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14337
05394f39 14338 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14339}
14340
86c98588
RV		 14341static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14342 struct drm_file *file,
14343 unsigned flags, unsigned color,
14344 struct drm_clip_rect *clips,
14345 unsigned num_clips)
14346{
14347 struct drm_device *dev = fb->dev;
14348 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14349 struct drm_i915_gem_object *obj = intel_fb->obj;
14350
14351 mutex_lock(&dev->struct_mutex);
74b4ea1e 14352 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14353 mutex_unlock(&dev->struct_mutex);
14354
14355 return 0;
14356}
14357
79e53945
JB		 14358static const struct drm_framebuffer_funcs intel_fb_funcs = {
14359 .destroy = intel_user_framebuffer_destroy,
14360 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14361 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14362};
14363
b321803d
DL		 14364static
14365u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14366 uint32_t pixel_format)
14367{
14368 u32 gen = INTEL_INFO(dev)->gen;
14369
14370 if (gen >= 9) {
14371 /* "The stride in bytes must not exceed the of the size of 8K
14372 * pixels and 32K bytes."
14373 */
14374 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14375 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14376 return 32*1024;
14377 } else if (gen >= 4) {
14378 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14379 return 16*1024;
14380 else
14381 return 32*1024;
14382 } else if (gen >= 3) {
14383 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14384 return 8*1024;
14385 else
14386 return 16*1024;
14387 } else {
14388 /* XXX DSPC is limited to 4k tiled */
14389 return 8*1024;
14390 }
14391}
14392
b5ea642a
DV		 14393static int intel_framebuffer_init(struct drm_device *dev,
14394 struct intel_framebuffer *intel_fb,
14395 struct drm_mode_fb_cmd2 *mode_cmd,
14396 struct drm_i915_gem_object *obj)
79e53945 14397{
6761dd31 14398 unsigned int aligned_height;
79e53945 14399 int ret;
b321803d 14400 u32 pitch_limit, stride_alignment;
79e53945 14401
dd4916c5
DV		 14402 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14403
2a80eada
DV		 14404 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14405 /* Enforce that fb modifier and tiling mode match, but only for
14406 * X-tiled. This is needed for FBC. */
14407 if (!!(obj->tiling_mode == I915_TILING_X) !=
14408 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14409 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14410 return -EINVAL;
14411 }
14412 } else {
14413 if (obj->tiling_mode == I915_TILING_X)
14414 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14415 else if (obj->tiling_mode == I915_TILING_Y) {
14416 DRM_DEBUG("No Y tiling for legacy addfb\n");
14417 return -EINVAL;
14418 }
14419 }
14420
9a8f0a12
TU		 14421 /* Passed in modifier sanity checking. */
14422 switch (mode_cmd->modifier[0]) {
14423 case I915_FORMAT_MOD_Y_TILED:
14424 case I915_FORMAT_MOD_Yf_TILED:
14425 if (INTEL_INFO(dev)->gen < 9) {
14426 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14427 mode_cmd->modifier[0]);
14428 return -EINVAL;
14429 }
14430 case DRM_FORMAT_MOD_NONE:
14431 case I915_FORMAT_MOD_X_TILED:
14432 break;
14433 default:
c0f40428
JB		 14434 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14435 mode_cmd->modifier[0]);
57cd6508 14436 return -EINVAL;
c16ed4be 14437 }
57cd6508 14438
b321803d
DL		 14439 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14440 mode_cmd->pixel_format);
14441 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14442 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14443 mode_cmd->pitches[0], stride_alignment);
57cd6508 14444 return -EINVAL;
c16ed4be 14445 }
57cd6508 14446
b321803d
DL		 14447 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14448 mode_cmd->pixel_format);
a35cdaa0 14449 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14450 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14451 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14452 "tiled" : "linear",
a35cdaa0 14453 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14454 return -EINVAL;
c16ed4be 14455 }
5d7bd705 14456
2a80eada 14457 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14458 mode_cmd->pitches[0] != obj->stride) {
14459 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14460 mode_cmd->pitches[0], obj->stride);
5d7bd705 14461 return -EINVAL;
c16ed4be 14462 }
5d7bd705 14463
57779d06 14464 /* Reject formats not supported by any plane early. */
308e5bcb 14465 switch (mode_cmd->pixel_format) {
57779d06 14466 case DRM_FORMAT_C8:
04b3924d
VS		 14467 case DRM_FORMAT_RGB565:
14468 case DRM_FORMAT_XRGB8888:
14469 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14470 break;
14471 case DRM_FORMAT_XRGB1555:
c16ed4be 14472 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14473 DRM_DEBUG("unsupported pixel format: %s\n",
14474 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14475 return -EINVAL;
c16ed4be 14476 }
57779d06 14477 break;
57779d06 14478 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14479 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14480 DRM_DEBUG("unsupported pixel format: %s\n",
14481 drm_get_format_name(mode_cmd->pixel_format));
14482 return -EINVAL;
14483 }
14484 break;
14485 case DRM_FORMAT_XBGR8888:
04b3924d 14486 case DRM_FORMAT_XRGB2101010:
57779d06 14487 case DRM_FORMAT_XBGR2101010:
c16ed4be 14488 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14489 DRM_DEBUG("unsupported pixel format: %s\n",
14490 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14491 return -EINVAL;
c16ed4be 14492 }
b5626747 14493 break;
7531208b
DL		 14494 case DRM_FORMAT_ABGR2101010:
14495 if (!IS_VALLEYVIEW(dev)) {
14496 DRM_DEBUG("unsupported pixel format: %s\n",
14497 drm_get_format_name(mode_cmd->pixel_format));
14498 return -EINVAL;
14499 }
14500 break;
04b3924d
VS		 14501 case DRM_FORMAT_YUYV:
14502 case DRM_FORMAT_UYVY:
14503 case DRM_FORMAT_YVYU:
14504 case DRM_FORMAT_VYUY:
c16ed4be 14505 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14506 DRM_DEBUG("unsupported pixel format: %s\n",
14507 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14508 return -EINVAL;
c16ed4be 14509 }
57cd6508
CW		 14510 break;
14511 default:
4ee62c76
VS		 14512 DRM_DEBUG("unsupported pixel format: %s\n",
14513 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14514 return -EINVAL;
14515 }
14516
90f9a336
VS		 14517 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14518 if (mode_cmd->offsets[0] != 0)
14519 return -EINVAL;
14520
ec2c981e 14521 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14522 mode_cmd->pixel_format,
14523 mode_cmd->modifier[0]);
53155c0a
DV		 14524 /* FIXME drm helper for size checks (especially planar formats)? */
14525 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14526 return -EINVAL;
14527
c7d73f6a
DV		 14528 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14529 intel_fb->obj = obj;
80075d49 14530 intel_fb->obj->framebuffer_references++;
c7d73f6a 14531
79e53945
JB		 14532 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14533 if (ret) {
14534 DRM_ERROR("framebuffer init failed %d\n", ret);
14535 return ret;
14536 }
14537
79e53945
JB		 14538 return 0;
14539}
14540
79e53945
JB		 14541static struct drm_framebuffer *
14542intel_user_framebuffer_create(struct drm_device *dev,
14543 struct drm_file *filp,
308e5bcb 14544 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14545{
dcb1394e 14546 struct drm_framebuffer *fb;
05394f39 14547 struct drm_i915_gem_object *obj;
79e53945 14548
308e5bcb
JB		 14549 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14550 mode_cmd->handles[0]));
c8725226 14551 if (&obj->base == NULL)
cce13ff7 14552 return ERR_PTR(-ENOENT);
79e53945 14553
dcb1394e
LW		 14554 fb = intel_framebuffer_create(dev, mode_cmd, obj);
14555 if (IS_ERR(fb))
14556 drm_gem_object_unreference_unlocked(&obj->base);
14557
14558 return fb;
79e53945
JB		 14559}
14560
0695726e 14561#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14562static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14563{
14564}
14565#endif
14566
79e53945 14567static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14568 .fb_create = intel_user_framebuffer_create,
0632fef6 14569 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14570 .atomic_check = intel_atomic_check,
14571 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14572 .atomic_state_alloc = intel_atomic_state_alloc,
14573 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14574};
14575
e70236a8
JB		 14576/* Set up chip specific display functions */
14577static void intel_init_display(struct drm_device *dev)
14578{
14579 struct drm_i915_private *dev_priv = dev->dev_private;
14580
ee9300bb
DV		 14581 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14582 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14583 else if (IS_CHERRYVIEW(dev))
14584 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14585 else if (IS_VALLEYVIEW(dev))
14586 dev_priv->display.find_dpll = vlv_find_best_dpll;
14587 else if (IS_PINEVIEW(dev))
14588 dev_priv->display.find_dpll = pnv_find_best_dpll;
14589 else
14590 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14591
bc8d7dff
DL		 14592 if (INTEL_INFO(dev)->gen >= 9) {
14593 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14594 dev_priv->display.get_initial_plane_config =
14595 skylake_get_initial_plane_config;
bc8d7dff
DL		 14596 dev_priv->display.crtc_compute_clock =
14597 haswell_crtc_compute_clock;
14598 dev_priv->display.crtc_enable = haswell_crtc_enable;
14599 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14600 dev_priv->display.update_primary_plane =
14601 skylake_update_primary_plane;
14602 } else if (HAS_DDI(dev)) {
0e8ffe1b 14603 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14604 dev_priv->display.get_initial_plane_config =
14605 ironlake_get_initial_plane_config;
797d0259
ACO		 14606 dev_priv->display.crtc_compute_clock =
14607 haswell_crtc_compute_clock;
4f771f10
PZ		 14608 dev_priv->display.crtc_enable = haswell_crtc_enable;
14609 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14610 dev_priv->display.update_primary_plane =
14611 ironlake_update_primary_plane;
09b4ddf9 14612 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14613 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14614 dev_priv->display.get_initial_plane_config =
14615 ironlake_get_initial_plane_config;
3fb37703
ACO		 14616 dev_priv->display.crtc_compute_clock =
14617 ironlake_crtc_compute_clock;
76e5a89c
DV		 14618 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14619 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14620 dev_priv->display.update_primary_plane =
14621 ironlake_update_primary_plane;
89b667f8
JB		 14622 } else if (IS_VALLEYVIEW(dev)) {
14623 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14624 dev_priv->display.get_initial_plane_config =
14625 i9xx_get_initial_plane_config;
d6dfee7a 14626 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14627 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14628 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14629 dev_priv->display.update_primary_plane =
14630 i9xx_update_primary_plane;
f564048e 14631 } else {
0e8ffe1b 14632 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14633 dev_priv->display.get_initial_plane_config =
14634 i9xx_get_initial_plane_config;
d6dfee7a 14635 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14636 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14637 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14638 dev_priv->display.update_primary_plane =
14639 i9xx_update_primary_plane;
f564048e 14640 }
e70236a8 14641
e70236a8 14642 /* Returns the core display clock speed */
ef11bdb3 14643 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1652d19e
VS		 14644 dev_priv->display.get_display_clock_speed =
14645 skylake_get_display_clock_speed;
acd3f3d3
BP		 14646 else if (IS_BROXTON(dev))
14647 dev_priv->display.get_display_clock_speed =
14648 broxton_get_display_clock_speed;
1652d19e
VS		 14649 else if (IS_BROADWELL(dev))
14650 dev_priv->display.get_display_clock_speed =
14651 broadwell_get_display_clock_speed;
14652 else if (IS_HASWELL(dev))
14653 dev_priv->display.get_display_clock_speed =
14654 haswell_get_display_clock_speed;
14655 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14656 dev_priv->display.get_display_clock_speed =
14657 valleyview_get_display_clock_speed;
b37a6434
VS		 14658 else if (IS_GEN5(dev))
14659 dev_priv->display.get_display_clock_speed =
14660 ilk_get_display_clock_speed;
a7c66cd8 14661 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14662 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14663 dev_priv->display.get_display_clock_speed =
14664 i945_get_display_clock_speed;
34edce2f
VS		 14665 else if (IS_GM45(dev))
14666 dev_priv->display.get_display_clock_speed =
14667 gm45_get_display_clock_speed;
14668 else if (IS_CRESTLINE(dev))
14669 dev_priv->display.get_display_clock_speed =
14670 i965gm_get_display_clock_speed;
14671 else if (IS_PINEVIEW(dev))
14672 dev_priv->display.get_display_clock_speed =
14673 pnv_get_display_clock_speed;
14674 else if (IS_G33(dev) || IS_G4X(dev))
14675 dev_priv->display.get_display_clock_speed =
14676 g33_get_display_clock_speed;
e70236a8
JB		 14677 else if (IS_I915G(dev))
14678 dev_priv->display.get_display_clock_speed =
14679 i915_get_display_clock_speed;
257a7ffc 14680 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14681 dev_priv->display.get_display_clock_speed =
14682 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14683 else if (IS_PINEVIEW(dev))
14684 dev_priv->display.get_display_clock_speed =
14685 pnv_get_display_clock_speed;
e70236a8
JB		 14686 else if (IS_I915GM(dev))
14687 dev_priv->display.get_display_clock_speed =
14688 i915gm_get_display_clock_speed;
14689 else if (IS_I865G(dev))
14690 dev_priv->display.get_display_clock_speed =
14691 i865_get_display_clock_speed;
f0f8a9ce 14692 else if (IS_I85X(dev))
e70236a8 14693 dev_priv->display.get_display_clock_speed =
1b1d2716 14694 i85x_get_display_clock_speed;
623e01e5
VS		 14695 else { /* 830 */
14696 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14697 dev_priv->display.get_display_clock_speed =
14698 i830_get_display_clock_speed;
623e01e5 14699 }
e70236a8 14700
7c10a2b5 14701 if (IS_GEN5(dev)) {
3bb11b53 14702 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14703 } else if (IS_GEN6(dev)) {
14704 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14705 } else if (IS_IVYBRIDGE(dev)) {
14706 /* FIXME: detect B0+ stepping and use auto training */
14707 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14708 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14709 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14710 if (IS_BROADWELL(dev)) {
14711 dev_priv->display.modeset_commit_cdclk =
14712 broadwell_modeset_commit_cdclk;
14713 dev_priv->display.modeset_calc_cdclk =
14714 broadwell_modeset_calc_cdclk;
14715 }
30a970c6 14716 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14717 dev_priv->display.modeset_commit_cdclk =
14718 valleyview_modeset_commit_cdclk;
14719 dev_priv->display.modeset_calc_cdclk =
14720 valleyview_modeset_calc_cdclk;
f8437dd1 14721 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14722 dev_priv->display.modeset_commit_cdclk =
14723 broxton_modeset_commit_cdclk;
14724 dev_priv->display.modeset_calc_cdclk =
14725 broxton_modeset_calc_cdclk;
e70236a8 14726 }
8c9f3aaf 14727
8c9f3aaf
JB		 14728 switch (INTEL_INFO(dev)->gen) {
14729 case 2:
14730 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14731 break;
14732
14733 case 3:
14734 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14735 break;
14736
14737 case 4:
14738 case 5:
14739 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14740 break;
14741
14742 case 6:
14743 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14744 break;
7c9017e5 14745 case 7:
4e0bbc31 14746 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14747 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14748 break;
830c81db 14749 case 9:
ba343e02
TU		 14750 /* Drop through - unsupported since execlist only. */
14751 default:
14752 /* Default just returns -ENODEV to indicate unsupported */
14753 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14754 }
7bd688cd 14755
e39b999a 14756 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14757}
14758
b690e96c
JB		 14759/*
14760 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14761 * resume, or other times. This quirk makes sure that's the case for
14762 * affected systems.
14763 */
0206e353 14764static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14765{
14766 struct drm_i915_private *dev_priv = dev->dev_private;
14767
14768 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14769 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14770}
14771
b6b5d049
VS		 14772static void quirk_pipeb_force(struct drm_device *dev)
14773{
14774 struct drm_i915_private *dev_priv = dev->dev_private;
14775
14776 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14777 DRM_INFO("applying pipe b force quirk\n");
14778}
14779
435793df
KP		 14780/*
14781 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14782 */
14783static void quirk_ssc_force_disable(struct drm_device *dev)
14784{
14785 struct drm_i915_private *dev_priv = dev->dev_private;
14786 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14787 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14788}
14789
4dca20ef 14790/*
5a15ab5b
CE		 14791 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14792 * brightness value
4dca20ef
CE		 14793 */
14794static void quirk_invert_brightness(struct drm_device *dev)
14795{
14796 struct drm_i915_private *dev_priv = dev->dev_private;
14797 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14798 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14799}
14800
9c72cc6f
SD		 14801/* Some VBT's incorrectly indicate no backlight is present */
14802static void quirk_backlight_present(struct drm_device *dev)
14803{
14804 struct drm_i915_private *dev_priv = dev->dev_private;
14805 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14806 DRM_INFO("applying backlight present quirk\n");
14807}
14808
b690e96c
JB		 14809struct intel_quirk {
14810 int device;
14811 int subsystem_vendor;
14812 int subsystem_device;
14813 void (*hook)(struct drm_device *dev);
14814};
14815
5f85f176
EE		 14816/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14817struct intel_dmi_quirk {
14818 void (*hook)(struct drm_device *dev);
14819 const struct dmi_system_id (*dmi_id_list)[];
14820};
14821
14822static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14823{
14824 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14825 return 1;
14826}
14827
14828static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14829 {
14830 .dmi_id_list = &(const struct dmi_system_id[]) {
14831 {
14832 .callback = intel_dmi_reverse_brightness,
14833 .ident = "NCR Corporation",
14834 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14835 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14836 },
14837 },
14838 { } /* terminating entry */
14839 },
14840 .hook = quirk_invert_brightness,
14841 },
14842};
14843
c43b5634 14844static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14845 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14846 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14847
b690e96c
JB		 14848 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14849 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14850
5f080c0f
VS		 14851 /* 830 needs to leave pipe A & dpll A up */
14852 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14853
b6b5d049
VS		 14854 /* 830 needs to leave pipe B & dpll B up */
14855 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14856
435793df
KP		 14857 /* Lenovo U160 cannot use SSC on LVDS */
14858 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14859
14860 /* Sony Vaio Y cannot use SSC on LVDS */
14861 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14862
be505f64
AH		 14863 /* Acer Aspire 5734Z must invert backlight brightness */
14864 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14865
14866 /* Acer/eMachines G725 */
14867 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14868
14869 /* Acer/eMachines e725 */
14870 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14871
14872 /* Acer/Packard Bell NCL20 */
14873 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14874
14875 /* Acer Aspire 4736Z */
14876 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14877
14878 /* Acer Aspire 5336 */
14879 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14880
14881 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14882 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14883
dfb3d47b
SD		 14884 /* Acer C720 Chromebook (Core i3 4005U) */
14885 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14886
b2a9601c 14887 /* Apple Macbook 2,1 (Core 2 T7400) */
14888 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14889
d4967d8c
SD		 14890 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14891 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14892
14893 /* HP Chromebook 14 (Celeron 2955U) */
14894 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14895
14896 /* Dell Chromebook 11 */
14897 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14898};
14899
14900static void intel_init_quirks(struct drm_device *dev)
14901{
14902 struct pci_dev *d = dev->pdev;
14903 int i;
14904
14905 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14906 struct intel_quirk *q = &intel_quirks[i];
14907
14908 if (d->device == q->device &&
14909 (d->subsystem_vendor == q->subsystem_vendor ||
14910 q->subsystem_vendor == PCI_ANY_ID) &&
14911 (d->subsystem_device == q->subsystem_device ||
14912 q->subsystem_device == PCI_ANY_ID))
14913 q->hook(dev);
14914 }
5f85f176
EE		 14915 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14916 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14917 intel_dmi_quirks[i].hook(dev);
14918 }
b690e96c
JB		 14919}
14920
9cce37f4
JB		 14921/* Disable the VGA plane that we never use */
14922static void i915_disable_vga(struct drm_device *dev)
14923{
14924 struct drm_i915_private *dev_priv = dev->dev_private;
14925 u8 sr1;
766aa1c4 14926 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14927
2b37c616 14928 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14929 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14930 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14931 sr1 = inb(VGA_SR_DATA);
14932 outb(sr1 | 1<<5, VGA_SR_DATA);
14933 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14934 udelay(300);
14935
01f5a626 14936 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14937 POSTING_READ(vga_reg);
14938}
14939
f817586c
DV		 14940void intel_modeset_init_hw(struct drm_device *dev)
14941{
b6283055 14942 intel_update_cdclk(dev);
a8f78b58 14943 intel_prepare_ddi(dev);
f817586c 14944 intel_init_clock_gating(dev);
8090c6b9 14945 intel_enable_gt_powersave(dev);
f817586c
DV		 14946}
14947
79e53945
JB		 14948void intel_modeset_init(struct drm_device *dev)
14949{
652c393a 14950 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14951 int sprite, ret;
8cc87b75 14952 enum pipe pipe;
46f297fb 14953 struct intel_crtc *crtc;
79e53945
JB		 14954
14955 drm_mode_config_init(dev);
14956
14957 dev->mode_config.min_width = 0;
14958 dev->mode_config.min_height = 0;
14959
019d96cb
DA		 14960 dev->mode_config.preferred_depth = 24;
14961 dev->mode_config.prefer_shadow = 1;
14962
25bab385
TU		 14963 dev->mode_config.allow_fb_modifiers = true;
14964
e6ecefaa 14965 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14966
b690e96c
JB		 14967 intel_init_quirks(dev);
14968
1fa61106
ED		 14969 intel_init_pm(dev);
14970
e3c74757
BW		 14971 if (INTEL_INFO(dev)->num_pipes == 0)
14972 return;
14973
69f92f67
LW		 14974 /*
14975 * There may be no VBT; and if the BIOS enabled SSC we can
14976 * just keep using it to avoid unnecessary flicker. Whereas if the
14977 * BIOS isn't using it, don't assume it will work even if the VBT
14978 * indicates as much.
14979 */
14980 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14981 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14982 DREF_SSC1_ENABLE);
14983
14984 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14985 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14986 bios_lvds_use_ssc ? "en" : "dis",
14987 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14988 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14989 }
14990 }
14991
e70236a8 14992 intel_init_display(dev);
7c10a2b5 14993 intel_init_audio(dev);
e70236a8 14994
a6c45cf0
CW		 14995 if (IS_GEN2(dev)) {
14996 dev->mode_config.max_width = 2048;
14997 dev->mode_config.max_height = 2048;
14998 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14999 dev->mode_config.max_width = 4096;
15000 dev->mode_config.max_height = 4096;
79e53945 15001 } else {
a6c45cf0
CW		 15002 dev->mode_config.max_width = 8192;
15003 dev->mode_config.max_height = 8192;
79e53945 15004 }
068be561 15005
dc41c154
VS		 15006 if (IS_845G(dev) || IS_I865G(dev)) {
15007 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15008 dev->mode_config.cursor_height = 1023;
15009 } else if (IS_GEN2(dev)) {
068be561
DL		 15010 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15011 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15012 } else {
15013 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15014 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15015 }
15016
5d4545ae 15017 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15018
28c97730 15019 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15020 INTEL_INFO(dev)->num_pipes,
15021 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15022
055e393f 15023 for_each_pipe(dev_priv, pipe) {
8cc87b75 15024 intel_crtc_init(dev, pipe);
3bdcfc0c 15025 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15026 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15027 if (ret)
06da8da2 15028 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15029 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15030 }
79e53945
JB		 15031 }
15032
bfa7df01
VS		 15033 intel_update_czclk(dev_priv);
15034 intel_update_cdclk(dev);
15035
e72f9fbf 15036 intel_shared_dpll_init(dev);
ee7b9f93 15037
9cce37f4
JB		 15038 /* Just disable it once at startup */
15039 i915_disable_vga(dev);
79e53945 15040 intel_setup_outputs(dev);
11be49eb 15041
6e9f798d 15042 drm_modeset_lock_all(dev);
043e9bda 15043 intel_modeset_setup_hw_state(dev);
6e9f798d 15044 drm_modeset_unlock_all(dev);
46f297fb 15045
d3fcc808 15046 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 15047 struct intel_initial_plane_config plane_config = {};
15048
46f297fb
JB		 15049 if (!crtc->active)
15050 continue;
15051
46f297fb 15052 /*
46f297fb
JB		 15053 * Note that reserving the BIOS fb up front prevents us
15054 * from stuffing other stolen allocations like the ring
15055 * on top. This prevents some ugliness at boot time, and
15056 * can even allow for smooth boot transitions if the BIOS
15057 * fb is large enough for the active pipe configuration.
15058 */
eeebeac5
ML		 15059 dev_priv->display.get_initial_plane_config(crtc,
15060 &plane_config);
15061
15062 /*
15063 * If the fb is shared between multiple heads, we'll
15064 * just get the first one.
15065 */
15066 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 15067 }
2c7111db
CW		 15068}
15069
7fad798e
DV		 15070static void intel_enable_pipe_a(struct drm_device *dev)
15071{
15072 struct intel_connector *connector;
15073 struct drm_connector *crt = NULL;
15074 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15075 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15076
15077 /* We can't just switch on the pipe A, we need to set things up with a
15078 * proper mode and output configuration. As a gross hack, enable pipe A
15079 * by enabling the load detect pipe once. */
3a3371ff 15080 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15081 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15082 crt = &connector->base;
15083 break;
15084 }
15085 }
15086
15087 if (!crt)
15088 return;
15089
208bf9fd 15090 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15091 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15092}
15093
fa555837
DV		 15094static bool
15095intel_check_plane_mapping(struct intel_crtc *crtc)
15096{
7eb552ae
BW		 15097 struct drm_device *dev = crtc->base.dev;
15098 struct drm_i915_private *dev_priv = dev->dev_private;
649636ef 15099 u32 val;
fa555837 15100
7eb552ae 15101 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15102 return true;
15103
649636ef 15104 val = I915_READ(DSPCNTR(!crtc->plane));
fa555837
DV		 15105
15106 if ((val & DISPLAY_PLANE_ENABLE) &&
15107 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15108 return false;
15109
15110 return true;
15111}
15112
02e93c35
VS		 15113static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15114{
15115 struct drm_device *dev = crtc->base.dev;
15116 struct intel_encoder *encoder;
15117
15118 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15119 return true;
15120
15121 return false;
15122}
15123
24929352
DV		 15124static void intel_sanitize_crtc(struct intel_crtc *crtc)
15125{
15126 struct drm_device *dev = crtc->base.dev;
15127 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15128 u32 reg;
24929352 15129
24929352 15130 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15131 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15132 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15133
d3eaf884 15134 /* restore vblank interrupts to correct state */
9625604c 15135 drm_crtc_vblank_reset(&crtc->base);
d297e103 15136 if (crtc->active) {
f9cd7b88
VS		 15137 struct intel_plane *plane;
15138
9625604c 15139 drm_crtc_vblank_on(&crtc->base);
f9cd7b88
VS		 15140
15141 /* Disable everything but the primary plane */
15142 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15143 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15144 continue;
15145
15146 plane->disable_plane(&plane->base, &crtc->base);
15147 }
9625604c 15148 }
d3eaf884 15149
24929352 15150 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15151 * disable the crtc (and hence change the state) if it is wrong. Note
15152 * that gen4+ has a fixed plane -> pipe mapping. */
15153 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15154 bool plane;
15155
24929352
DV		 15156 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15157 crtc->base.base.id);
15158
15159 /* Pipe has the wrong plane attached and the plane is active.
15160 * Temporarily change the plane mapping and disable everything
15161 * ... */
15162 plane = crtc->plane;
b70709a6 15163 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15164 crtc->plane = !plane;
b17d48e2 15165 intel_crtc_disable_noatomic(&crtc->base);
24929352 15166 crtc->plane = plane;
24929352 15167 }
24929352 15168
7fad798e
DV		 15169 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15170 crtc->pipe == PIPE_A && !crtc->active) {
15171 /* BIOS forgot to enable pipe A, this mostly happens after
15172 * resume. Force-enable the pipe to fix this, the update_dpms
15173 * call below we restore the pipe to the right state, but leave
15174 * the required bits on. */
15175 intel_enable_pipe_a(dev);
15176 }
15177
24929352
DV		 15178 /* Adjust the state of the output pipe according to whether we
15179 * have active connectors/encoders. */
02e93c35 15180 if (!intel_crtc_has_encoders(crtc))
b17d48e2 15181 intel_crtc_disable_noatomic(&crtc->base);
24929352 15182
53d9f4e9 15183 if (crtc->active != crtc->base.state->active) {
02e93c35 15184 struct intel_encoder *encoder;
24929352
DV		 15185
15186 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15187 * functions or because of calls to intel_crtc_disable_noatomic,
15188 * or because the pipe is force-enabled due to the
24929352
DV		 15189 * pipe A quirk. */
15190 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15191 crtc->base.base.id,
83d65738 15192 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15193 crtc->active ? "enabled" : "disabled");
15194
4be40c98 15195 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 15196 crtc->base.state->active = crtc->active;
24929352
DV		 15197 crtc->base.enabled = crtc->active;
15198
15199 /* Because we only establish the connector -> encoder ->
15200 * crtc links if something is active, this means the
15201 * crtc is now deactivated. Break the links. connector
15202 * -> encoder links are only establish when things are
15203 * actually up, hence no need to break them. */
15204 WARN_ON(crtc->active);
15205
2d406bb0 15206 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 15207 encoder->base.crtc = NULL;
24929352 15208 }
c5ab3bc0 15209
a3ed6aad 15210 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15211 /*
15212 * We start out with underrun reporting disabled to avoid races.
15213 * For correct bookkeeping mark this on active crtcs.
15214 *
c5ab3bc0
DV		 15215 * Also on gmch platforms we dont have any hardware bits to
15216 * disable the underrun reporting. Which means we need to start
15217 * out with underrun reporting disabled also on inactive pipes,
15218 * since otherwise we'll complain about the garbage we read when
15219 * e.g. coming up after runtime pm.
15220 *
4cc31489
DV		 15221 * No protection against concurrent access is required - at
15222 * worst a fifo underrun happens which also sets this to false.
15223 */
15224 crtc->cpu_fifo_underrun_disabled = true;
15225 crtc->pch_fifo_underrun_disabled = true;
15226 }
24929352
DV		 15227}
15228
15229static void intel_sanitize_encoder(struct intel_encoder *encoder)
15230{
15231 struct intel_connector *connector;
15232 struct drm_device *dev = encoder->base.dev;
873ffe69 15233 bool active = false;
24929352
DV		 15234
15235 /* We need to check both for a crtc link (meaning that the
15236 * encoder is active and trying to read from a pipe) and the
15237 * pipe itself being active. */
15238 bool has_active_crtc = encoder->base.crtc &&
15239 to_intel_crtc(encoder->base.crtc)->active;
15240
873ffe69
ML		 15241 for_each_intel_connector(dev, connector) {
15242 if (connector->base.encoder != &encoder->base)
15243 continue;
15244
15245 active = true;
15246 break;
15247 }
15248
15249 if (active && !has_active_crtc) {
24929352
DV		 15250 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15251 encoder->base.base.id,
8e329a03 15252 encoder->base.name);
24929352
DV		 15253
15254 /* Connector is active, but has no active pipe. This is
15255 * fallout from our resume register restoring. Disable
15256 * the encoder manually again. */
15257 if (encoder->base.crtc) {
15258 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15259 encoder->base.base.id,
8e329a03 15260 encoder->base.name);
24929352 15261 encoder->disable(encoder);
a62d1497
VS		 15262 if (encoder->post_disable)
15263 encoder->post_disable(encoder);
24929352 15264 }
7f1950fb 15265 encoder->base.crtc = NULL;
24929352
DV		 15266
15267 /* Inconsistent output/port/pipe state happens presumably due to
15268 * a bug in one of the get_hw_state functions. Or someplace else
15269 * in our code, like the register restore mess on resume. Clamp
15270 * things to off as a safer default. */
3a3371ff 15271 for_each_intel_connector(dev, connector) {
24929352
DV		 15272 if (connector->encoder != encoder)
15273 continue;
7f1950fb
EE		 15274 connector->base.dpms = DRM_MODE_DPMS_OFF;
15275 connector->base.encoder = NULL;
24929352
DV		 15276 }
15277 }
15278 /* Enabled encoders without active connectors will be fixed in
15279 * the crtc fixup. */
15280}
15281
04098753 15282void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15283{
15284 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15285 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15286
04098753
ID		 15287 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15288 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15289 i915_disable_vga(dev);
15290 }
15291}
15292
15293void i915_redisable_vga(struct drm_device *dev)
15294{
15295 struct drm_i915_private *dev_priv = dev->dev_private;
15296
8dc8a27c
PZ		 15297 /* This function can be called both from intel_modeset_setup_hw_state or
15298 * at a very early point in our resume sequence, where the power well
15299 * structures are not yet restored. Since this function is at a very
15300 * paranoid "someone might have enabled VGA while we were not looking"
15301 * level, just check if the power well is enabled instead of trying to
15302 * follow the "don't touch the power well if we don't need it" policy
15303 * the rest of the driver uses. */
f458ebbc 15304 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15305 return;
15306
04098753 15307 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15308}
15309
f9cd7b88 15310static bool primary_get_hw_state(struct intel_plane *plane)
98ec7739 15311{
f9cd7b88 15312 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
98ec7739 15313
f9cd7b88 15314 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
d032ffa0
ML		 15315}
15316
f9cd7b88
VS		 15317/* FIXME read out full plane state for all planes */
15318static void readout_plane_state(struct intel_crtc *crtc)
d032ffa0 15319{
b26d3ea3 15320 struct drm_plane *primary = crtc->base.primary;
f9cd7b88 15321 struct intel_plane_state *plane_state =
b26d3ea3 15322 to_intel_plane_state(primary->state);
d032ffa0 15323
19b8d387 15324 plane_state->visible = crtc->active &&
b26d3ea3
ML		 15325 primary_get_hw_state(to_intel_plane(primary));
15326
15327 if (plane_state->visible)
15328 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
98ec7739
VS		 15329}
15330
30e984df 15331static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15332{
15333 struct drm_i915_private *dev_priv = dev->dev_private;
15334 enum pipe pipe;
24929352
DV		 15335 struct intel_crtc *crtc;
15336 struct intel_encoder *encoder;
15337 struct intel_connector *connector;
5358901f 15338 int i;
24929352 15339
d3fcc808 15340 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15341 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15342 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15343 crtc->config->base.crtc = &crtc->base;
3b117c8f 15344
0e8ffe1b 15345 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15346 crtc->config);
24929352 15347
49d6fa21 15348 crtc->base.state->active = crtc->active;
24929352 15349 crtc->base.enabled = crtc->active;
b70709a6 15350
f9cd7b88 15351 readout_plane_state(crtc);
24929352
DV		 15352
15353 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15354 crtc->base.base.id,
15355 crtc->active ? "enabled" : "disabled");
15356 }
15357
5358901f
DV		 15358 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15359 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15360
3e369b76
ACO		 15361 pll->on = pll->get_hw_state(dev_priv, pll,
15362 &pll->config.hw_state);
5358901f 15363 pll->active = 0;
3e369b76 15364 pll->config.crtc_mask = 0;
d3fcc808 15365 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15366 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15367 pll->active++;
3e369b76 15368 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15369 }
5358901f 15370 }
5358901f 15371
1e6f2ddc 15372 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15373 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15374
3e369b76 15375 if (pll->config.crtc_mask)
bd2bb1b9 15376 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15377 }
15378
b2784e15 15379 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15380 pipe = 0;
15381
15382 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15383 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15384 encoder->base.crtc = &crtc->base;
6e3c9717 15385 encoder->get_config(encoder, crtc->config);
24929352
DV		 15386 } else {
15387 encoder->base.crtc = NULL;
15388 }
15389
6f2bcceb 15390 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15391 encoder->base.base.id,
8e329a03 15392 encoder->base.name,
24929352 15393 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15394 pipe_name(pipe));
24929352
DV		 15395 }
15396
3a3371ff 15397 for_each_intel_connector(dev, connector) {
24929352
DV		 15398 if (connector->get_hw_state(connector)) {
15399 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15400 connector->base.encoder = &connector->encoder->base;
15401 } else {
15402 connector->base.dpms = DRM_MODE_DPMS_OFF;
15403 connector->base.encoder = NULL;
15404 }
15405 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15406 connector->base.base.id,
c23cc417 15407 connector->base.name,
24929352
DV		 15408 connector->base.encoder ? "enabled" : "disabled");
15409 }
7f4c6284
VS		 15410
15411 for_each_intel_crtc(dev, crtc) {
15412 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15413
15414 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15415 if (crtc->base.state->active) {
15416 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15417 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15418 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15419
15420 /*
15421 * The initial mode needs to be set in order to keep
15422 * the atomic core happy. It wants a valid mode if the
15423 * crtc's enabled, so we do the above call.
15424 *
15425 * At this point some state updated by the connectors
15426 * in their ->detect() callback has not run yet, so
15427 * no recalculation can be done yet.
15428 *
15429 * Even if we could do a recalculation and modeset
15430 * right now it would cause a double modeset if
15431 * fbdev or userspace chooses a different initial mode.
15432 *
15433 * If that happens, someone indicated they wanted a
15434 * mode change, which means it's safe to do a full
15435 * recalculation.
15436 */
15437 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
9eca6832
VS		 15438
15439 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15440 update_scanline_offset(crtc);
7f4c6284
VS		 15441 }
15442 }
30e984df
DV		 15443}
15444
043e9bda
ML		 15445/* Scan out the current hw modeset state,
15446 * and sanitizes it to the current state
15447 */
15448static void
15449intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15450{
15451 struct drm_i915_private *dev_priv = dev->dev_private;
15452 enum pipe pipe;
30e984df
DV		 15453 struct intel_crtc *crtc;
15454 struct intel_encoder *encoder;
35c95375 15455 int i;
30e984df
DV		 15456
15457 intel_modeset_readout_hw_state(dev);
24929352
DV		 15458
15459 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15460 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15461 intel_sanitize_encoder(encoder);
15462 }
15463
055e393f 15464 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15465 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15466 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15467 intel_dump_pipe_config(crtc, crtc->config,
15468 "[setup_hw_state]");
24929352 15469 }
9a935856 15470
d29b2f9d
ACO		 15471 intel_modeset_update_connector_atomic_state(dev);
15472
35c95375
DV		 15473 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15474 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15475
15476 if (!pll->on || pll->active)
15477 continue;
15478
15479 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15480
15481 pll->disable(dev_priv, pll);
15482 pll->on = false;
15483 }
15484
26e1fe4f 15485 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15486 vlv_wm_get_hw_state(dev);
15487 else if (IS_GEN9(dev))
3078999f
PB		 15488 skl_wm_get_hw_state(dev);
15489 else if (HAS_PCH_SPLIT(dev))
243e6a44 15490 ilk_wm_get_hw_state(dev);
292b990e
ML		 15491
15492 for_each_intel_crtc(dev, crtc) {
15493 unsigned long put_domains;
15494
15495 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15496 if (WARN_ON(put_domains))
15497 modeset_put_power_domains(dev_priv, put_domains);
15498 }
15499 intel_display_set_init_power(dev_priv, false);
043e9bda 15500}
7d0bc1ea 15501
043e9bda
ML		 15502void intel_display_resume(struct drm_device *dev)
15503{
15504 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15505 struct intel_connector *conn;
15506 struct intel_plane *plane;
15507 struct drm_crtc *crtc;
15508 int ret;
f30da187 15509
043e9bda
ML		 15510 if (!state)
15511 return;
15512
15513 state->acquire_ctx = dev->mode_config.acquire_ctx;
15514
15515 /* preserve complete old state, including dpll */
15516 intel_atomic_get_shared_dpll_state(state);
15517
15518 for_each_crtc(dev, crtc) {
15519 struct drm_crtc_state *crtc_state =
15520 drm_atomic_get_crtc_state(state, crtc);
15521
15522 ret = PTR_ERR_OR_ZERO(crtc_state);
15523 if (ret)
15524 goto err;
15525
15526 /* force a restore */
15527 crtc_state->mode_changed = true;
45e2b5f6 15528 }
8af6cf88 15529
043e9bda
ML		 15530 for_each_intel_plane(dev, plane) {
15531 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15532 if (ret)
15533 goto err;
15534 }
15535
15536 for_each_intel_connector(dev, conn) {
15537 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15538 if (ret)
15539 goto err;
15540 }
15541
15542 intel_modeset_setup_hw_state(dev);
15543
15544 i915_redisable_vga(dev);
74c090b1 15545 ret = drm_atomic_commit(state);
043e9bda
ML		 15546 if (!ret)
15547 return;
15548
15549err:
15550 DRM_ERROR("Restoring old state failed with %i\n", ret);
15551 drm_atomic_state_free(state);
2c7111db
CW		 15552}
15553
15554void intel_modeset_gem_init(struct drm_device *dev)
15555{
484b41dd 15556 struct drm_crtc *c;
2ff8fde1 15557 struct drm_i915_gem_object *obj;
e0d6149b 15558 int ret;
484b41dd 15559
ae48434c
ID		 15560 mutex_lock(&dev->struct_mutex);
15561 intel_init_gt_powersave(dev);
15562 mutex_unlock(&dev->struct_mutex);
15563
1833b134 15564 intel_modeset_init_hw(dev);
02e792fb
DV		 15565
15566 intel_setup_overlay(dev);
484b41dd
JB		 15567
15568 /*
15569 * Make sure any fbs we allocated at startup are properly
15570 * pinned & fenced. When we do the allocation it's too early
15571 * for this.
15572 */
70e1e0ec 15573 for_each_crtc(dev, c) {
2ff8fde1
MR		 15574 obj = intel_fb_obj(c->primary->fb);
15575 if (obj == NULL)
484b41dd
JB		 15576 continue;
15577
e0d6149b
TU		 15578 mutex_lock(&dev->struct_mutex);
15579 ret = intel_pin_and_fence_fb_obj(c->primary,
15580 c->primary->fb,
7580d774 15581 c->primary->state);
e0d6149b
TU		 15582 mutex_unlock(&dev->struct_mutex);
15583 if (ret) {
484b41dd
JB		 15584 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15585 to_intel_crtc(c)->pipe);
66e514c1
DA		 15586 drm_framebuffer_unreference(c->primary->fb);
15587 c->primary->fb = NULL;
36750f28 15588 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15589 update_state_fb(c->primary);
36750f28 15590 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15591 }
15592 }
0962c3c9
VS		 15593
15594 intel_backlight_register(dev);
79e53945
JB		 15595}
15596
4932e2c3
ID		 15597void intel_connector_unregister(struct intel_connector *intel_connector)
15598{
15599 struct drm_connector *connector = &intel_connector->base;
15600
15601 intel_panel_destroy_backlight(connector);
34ea3d38 15602 drm_connector_unregister(connector);
4932e2c3
ID		 15603}
15604
79e53945
JB		 15605void intel_modeset_cleanup(struct drm_device *dev)
15606{
652c393a 15607 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15608 struct drm_connector *connector;
652c393a 15609
2eb5252e
ID		 15610 intel_disable_gt_powersave(dev);
15611
0962c3c9
VS		 15612 intel_backlight_unregister(dev);
15613
fd0c0642
DV		 15614 /*
15615 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15616 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15617 * experience fancy races otherwise.
15618 */
2aeb7d3a 15619 intel_irq_uninstall(dev_priv);
eb21b92b 15620
fd0c0642
DV		 15621 /*
15622 * Due to the hpd irq storm handling the hotplug work can re-arm the
15623 * poll handlers. Hence disable polling after hpd handling is shut down.
15624 */
f87ea761 15625 drm_kms_helper_poll_fini(dev);
fd0c0642 15626
723bfd70
JB		 15627 intel_unregister_dsm_handler();
15628
7733b49b 15629 intel_fbc_disable(dev_priv);
69341a5e 15630
1630fe75
CW		 15631 /* flush any delayed tasks or pending work */
15632 flush_scheduled_work();
15633
db31af1d
JN		 15634 /* destroy the backlight and sysfs files before encoders/connectors */
15635 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15636 struct intel_connector *intel_connector;
15637
15638 intel_connector = to_intel_connector(connector);
15639 intel_connector->unregister(intel_connector);
db31af1d 15640 }
d9255d57 15641
79e53945 15642 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15643
15644 intel_cleanup_overlay(dev);
ae48434c
ID		 15645
15646 mutex_lock(&dev->struct_mutex);
15647 intel_cleanup_gt_powersave(dev);
15648 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15649}
15650
f1c79df3
ZW		 15651/*
15652 * Return which encoder is currently attached for connector.
15653 */
df0e9248 15654struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15655{
df0e9248
CW		 15656 return &intel_attached_encoder(connector)->base;
15657}
f1c79df3 15658
df0e9248
CW		 15659void intel_connector_attach_encoder(struct intel_connector *connector,
15660 struct intel_encoder *encoder)
15661{
15662 connector->encoder = encoder;
15663 drm_mode_connector_attach_encoder(&connector->base,
15664 &encoder->base);
79e53945 15665}
28d52043
DA		 15666
15667/*
15668 * set vga decode state - true == enable VGA decode
15669 */
15670int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15671{
15672 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15673 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15674 u16 gmch_ctrl;
15675
75fa041d
CW		 15676 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15677 DRM_ERROR("failed to read control word\n");
15678 return -EIO;
15679 }
15680
c0cc8a55
CW		 15681 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15682 return 0;
15683
28d52043
DA		 15684 if (state)
15685 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15686 else
15687 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15688
15689 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15690 DRM_ERROR("failed to write control word\n");
15691 return -EIO;
15692 }
15693
28d52043
DA		 15694 return 0;
15695}
c4a1d9e4 15696
c4a1d9e4 15697struct intel_display_error_state {
ff57f1b0
PZ		 15698
15699 u32 power_well_driver;
15700
63b66e5b
CW		 15701 int num_transcoders;
15702
c4a1d9e4
CW		 15703 struct intel_cursor_error_state {
15704 u32 control;
15705 u32 position;
15706 u32 base;
15707 u32 size;
52331309 15708 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15709
15710 struct intel_pipe_error_state {
ddf9c536 15711 bool power_domain_on;
c4a1d9e4 15712 u32 source;
f301b1e1 15713 u32 stat;
52331309 15714 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15715
15716 struct intel_plane_error_state {
15717 u32 control;
15718 u32 stride;
15719 u32 size;
15720 u32 pos;
15721 u32 addr;
15722 u32 surface;
15723 u32 tile_offset;
52331309 15724 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15725
15726 struct intel_transcoder_error_state {
ddf9c536 15727 bool power_domain_on;
63b66e5b
CW		 15728 enum transcoder cpu_transcoder;
15729
15730 u32 conf;
15731
15732 u32 htotal;
15733 u32 hblank;
15734 u32 hsync;
15735 u32 vtotal;
15736 u32 vblank;
15737 u32 vsync;
15738 } transcoder[4];
c4a1d9e4
CW		 15739};
15740
15741struct intel_display_error_state *
15742intel_display_capture_error_state(struct drm_device *dev)
15743{
fbee40df 15744 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15745 struct intel_display_error_state *error;
63b66e5b
CW		 15746 int transcoders[] = {
15747 TRANSCODER_A,
15748 TRANSCODER_B,
15749 TRANSCODER_C,
15750 TRANSCODER_EDP,
15751 };
c4a1d9e4
CW		 15752 int i;
15753
63b66e5b
CW		 15754 if (INTEL_INFO(dev)->num_pipes == 0)
15755 return NULL;
15756
9d1cb914 15757 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15758 if (error == NULL)
15759 return NULL;
15760
190be112 15761 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15762 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15763
055e393f 15764 for_each_pipe(dev_priv, i) {
ddf9c536 15765 error->pipe[i].power_domain_on =
f458ebbc
DV		 15766 __intel_display_power_is_enabled(dev_priv,
15767 POWER_DOMAIN_PIPE(i));
ddf9c536 15768 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15769 continue;
15770
5efb3e28
VS		 15771 error->cursor[i].control = I915_READ(CURCNTR(i));
15772 error->cursor[i].position = I915_READ(CURPOS(i));
15773 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15774
15775 error->plane[i].control = I915_READ(DSPCNTR(i));
15776 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15777 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15778 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15779 error->plane[i].pos = I915_READ(DSPPOS(i));
15780 }
ca291363
PZ		 15781 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15782 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15783 if (INTEL_INFO(dev)->gen >= 4) {
15784 error->plane[i].surface = I915_READ(DSPSURF(i));
15785 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15786 }
15787
c4a1d9e4 15788 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15789
3abfce77 15790 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15791 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15792 }
15793
15794 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15795 if (HAS_DDI(dev_priv->dev))
15796 error->num_transcoders++; /* Account for eDP. */
15797
15798 for (i = 0; i < error->num_transcoders; i++) {
15799 enum transcoder cpu_transcoder = transcoders[i];
15800
ddf9c536 15801 error->transcoder[i].power_domain_on =
f458ebbc 15802 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15803 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15804 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15805 continue;
15806
63b66e5b
CW		 15807 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15808
15809 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15810 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15811 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15812 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15813 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15814 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15815 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15816 }
15817
15818 return error;
15819}
15820
edc3d884
MK		 15821#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15822
c4a1d9e4 15823void
edc3d884 15824intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15825 struct drm_device *dev,
15826 struct intel_display_error_state *error)
15827{
055e393f 15828 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15829 int i;
15830
63b66e5b
CW		 15831 if (!error)
15832 return;
15833
edc3d884 15834 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15835 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15836 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15837 error->power_well_driver);
055e393f 15838 for_each_pipe(dev_priv, i) {
edc3d884 15839 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15840 err_printf(m, " Power: %s\n",
15841 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15842 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15843 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15844
15845 err_printf(m, "Plane [%d]:\n", i);
15846 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15847 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15848 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15849 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15850 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15851 }
4b71a570 15852 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15853 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15854 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15855 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15856 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15857 }
15858
edc3d884
MK		 15859 err_printf(m, "Cursor [%d]:\n", i);
15860 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15861 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15862 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15863 }
63b66e5b
CW		 15864
15865 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15866 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15867 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15868 err_printf(m, " Power: %s\n",
15869 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15870 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15871 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15872 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15873 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15874 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15875 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15876 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15877 }
c4a1d9e4 15878}
e2fcdaa9
VS		 15879
15880void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15881{
15882 struct intel_crtc *crtc;
15883
15884 for_each_intel_crtc(dev, crtc) {
15885 struct intel_unpin_work *work;
e2fcdaa9 15886
5e2d7afc 15887 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15888
15889 work = crtc->unpin_work;
15890
15891 if (work && work->event &&
15892 work->event->base.file_priv == file) {
15893 kfree(work->event);
15894 work->event = NULL;
15895 }
15896
5e2d7afc 15897 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15898 }
15899}
Linux kernel - Deliverables
This page took 4.096947 seconds and 5 git commands to generate.