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drm/i915: no longer call drm_helper_resume_force_mode
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
af447bd3 872 flag = 0;
a0c4da24
JB		 873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
284637d9 1009 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
284637d9 1027 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab
DV		 1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1381}
1382
1383static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385{
47a05eca 1386 u32 val = I915_READ(reg);
e9a851ed 1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1389 reg, pipe_name(pipe));
de9a35ab
DV		 1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1393}
1394
1395static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
291906f1 1400
f0575e92
KP		 1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
e9a851ed 1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1409 pipe_name(pipe));
291906f1
JB		 1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
e9a851ed 1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 pipe_name(pipe));
291906f1
JB		 1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420}
1421
63d7bbe9
JB		 1422/**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
7434a255
TR		 1432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1434 */
a37b9b34 1435static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1436{
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
a0c4da24 1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461}
1462
1463/**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489}
1490
a416edef
ED		 1491/* SBI access */
1492static void
1493intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494{
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
39fb50f6 1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520}
1521
1522static u32
1523intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524{
1525 unsigned long flags;
39fb50f6 1526 u32 value = 0;
a416edef
ED		 1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
39fb50f6 1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552}
1553
92f2584a
JB		 1554/**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
ee7b9f93 1562static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1563{
ee7b9f93 1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1565 struct intel_pch_pll *pll;
92f2584a
JB		 1566 int reg;
1567 u32 val;
1568
48da64a8 1569 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1570 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
ee7b9f93
JB		 1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
92f2584a
JB		 1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
ee7b9f93 1585 if (pll->active++ && pll->on) {
92b27b08 1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
92f2584a
JB		 1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
ee7b9f93
JB		 1598
1599 pll->on = true;
92f2584a
JB		 1600}
1601
ee7b9f93 1602static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1603{
ee7b9f93
JB		 1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1606 int reg;
ee7b9f93 1607 u32 val;
4c609cb8 1608
92f2584a
JB		 1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1611 if (pll == NULL)
1612 return;
92f2584a 1613
48da64a8
CW		 1614 if (WARN_ON(pll->refcount == 0))
1615 return;
7a419866 1616
ee7b9f93
JB		 1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
7a419866 1620
48da64a8 1621 if (WARN_ON(pll->active == 0)) {
92b27b08 1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1623 return;
1624 }
1625
ee7b9f93 1626 if (--pll->active) {
92b27b08 1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1628 return;
ee7b9f93
JB		 1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1635
ee7b9f93 1636 reg = pll->pll_reg;
92f2584a
JB		 1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
ee7b9f93
JB		 1642
1643 pll->on = false;
92f2584a
JB		 1644}
1645
040484af
JB		 1646static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648{
1649 int reg;
5f7f726d 1650 u32 val, pipeconf_val;
7c26e5c6 1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
040484af
JB		 1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
59c859d6
ED		 1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
040484af
JB		 1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
5f7f726d 1671 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
5f7f726d 1679 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1680 }
5f7f726d
PZ		 1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
040484af
JB		 1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695}
1696
1697static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699{
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
291906f1
JB		 1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
040484af
JB		 1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1717}
1718
b24e7179 1719/**
309cfea8 1720 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
040484af 1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
040484af
JB		 1733static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
b24e7179
JB		 1735{
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
b24e7179
JB		 1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
00d70b15
CW		 1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762}
1763
1764/**
309cfea8 1765 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778{
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
00d70b15
CW		 1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799}
1800
d74362c9
KP		 1801/*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
6f1d69b0 1805void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1806 enum plane plane)
1807{
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810}
1811
b24e7179
JB		 1812/**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822{
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
00d70b15
CW		 1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1835 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837}
1838
b24e7179
JB		 1839/**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849{
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
00d70b15
CW		 1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861}
1862
47a05eca 1863static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1864 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1865{
1866 u32 val = I915_READ(reg);
4e634389 1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1869 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1870 }
47a05eca
JB		 1871}
1872
1873static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875{
1876 u32 val = I915_READ(reg);
e9a851ed 1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
f0575e92
KP		 1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
47a05eca 1880 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1881 }
47a05eca
JB		 1882}
1883
1884/* Disable any ports connected to this transcoder */
1885static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887{
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
f0575e92
KP		 1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
e9a851ed 1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
47a05eca
JB		 1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
e9a851ed 1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1519b995 1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914}
1915
127bd2ac 1916int
48b956c5 1917intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1918 struct drm_i915_gem_object *obj,
919926ae 1919 struct intel_ring_buffer *pipelined)
6b95a207 1920{
ce453d81 1921 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1922 u32 alignment;
1923 int ret;
1924
05394f39 1925 switch (obj->tiling_mode) {
6b95a207 1926 case I915_TILING_NONE:
534843da
CW		 1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
a6c45cf0 1929 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
6b95a207
KH		 1933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
ce453d81 1946 dev_priv->mm.interruptible = false;
2da3b9b9 1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1948 if (ret)
ce453d81 1949 goto err_interruptible;
6b95a207
KH		 1950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
06d98131 1956 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1957 if (ret)
1958 goto err_unpin;
1690e1eb 1959
9a5a53b3 1960 i915_gem_object_pin_fence(obj);
6b95a207 1961
ce453d81 1962 dev_priv->mm.interruptible = true;
6b95a207 1963 return 0;
48b956c5
CW		 1964
1965err_unpin:
1966 i915_gem_object_unpin(obj);
ce453d81
CW		 1967err_interruptible:
1968 dev_priv->mm.interruptible = true;
48b956c5 1969 return ret;
6b95a207
KH		 1970}
1971
1690e1eb
CW		 1972void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973{
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976}
1977
c2c75131
DV		 1978/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983{
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992}
1993
17638cd6
JB		 1994static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
81255565
JB		 1996{
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
05394f39 2001 struct drm_i915_gem_object *obj;
81255565 2002 int plane = intel_crtc->plane;
e506a0c6 2003 unsigned long linear_offset;
81255565 2004 u32 dspcntr;
5eddb70b 2005 u32 reg;
81255565
JB		 2006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
81255565 2018
5eddb70b
CW		 2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
81255565
JB		 2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
17638cd6 2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2039 return -EINVAL;
2040 }
a6c45cf0 2041 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2042 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
5eddb70b 2048 I915_WRITE(reg, dspcntr);
81255565 2049
e506a0c6 2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2051
c2c75131
DV		 2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
e506a0c6 2059 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2060 }
e506a0c6
DV		 2061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2065 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2070 } else
e506a0c6 2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2072 POSTING_READ(reg);
81255565 2073
17638cd6
JB		 2074 return 0;
2075}
2076
2077static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079{
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
e506a0c6 2086 unsigned long linear_offset;
17638cd6
JB		 2087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
27f8227b 2093 case 2:
17638cd6
JB		 2094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
e506a0c6 2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2147
e506a0c6
DV		 2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2155 POSTING_READ(reg);
2156
2157 return 0;
2158}
2159
2160/* Assume fb object is pinned & idle & fenced and just update base pointers */
2161static int
2162intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164{
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2167
6b8e6ed0
CW		 2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
3dec0095 2170 intel_increase_pllclock(crtc);
81255565 2171
6b8e6ed0 2172 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2173}
2174
14667a4b
CW		 2175static int
2176intel_finish_fb(struct drm_framebuffer *old_fb)
2177{
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200}
2201
5c3b82e2 2202static int
3c4fdcfb 2203intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2204 struct drm_framebuffer *fb)
79e53945
JB		 2205{
2206 struct drm_device *dev = crtc->dev;
6b8e6ed0 2207 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2210 struct drm_framebuffer *old_fb;
5c3b82e2 2211 int ret;
79e53945
JB		 2212
2213 /* no fb bound */
94352cf9 2214 if (!fb) {
a5071c2f 2215 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2216 return 0;
2217 }
2218
5826eca5
ED		 2219 if(intel_crtc->plane > dev_priv->num_pipe) {
2220 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2221 intel_crtc->plane,
2222 dev_priv->num_pipe);
5c3b82e2 2223 return -EINVAL;
79e53945
JB		 2224 }
2225
5c3b82e2 2226 mutex_lock(&dev->struct_mutex);
265db958 2227 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2228 to_intel_framebuffer(fb)->obj,
919926ae 2229 NULL);
5c3b82e2
CW		 2230 if (ret != 0) {
2231 mutex_unlock(&dev->struct_mutex);
a5071c2f 2232 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2233 return ret;
2234 }
79e53945 2235
94352cf9
DV		 2236 if (crtc->fb)
2237 intel_finish_fb(crtc->fb);
265db958 2238
94352cf9 2239 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2240 if (ret) {
94352cf9 2241 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2242 mutex_unlock(&dev->struct_mutex);
a5071c2f 2243 DRM_ERROR("failed to update base address\n");
4e6cfefc 2244 return ret;
79e53945 2245 }
3c4fdcfb 2246
94352cf9
DV		 2247 old_fb = crtc->fb;
2248 crtc->fb = fb;
2249
b7f1de28
CW		 2250 if (old_fb) {
2251 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2252 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2253 }
652c393a 2254
6b8e6ed0 2255 intel_update_fbc(dev);
5c3b82e2 2256 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2257
2258 if (!dev->primary->master)
5c3b82e2 2259 return 0;
79e53945
JB		 2260
2261 master_priv = dev->primary->master->driver_priv;
2262 if (!master_priv->sarea_priv)
5c3b82e2 2263 return 0;
79e53945 2264
265db958 2265 if (intel_crtc->pipe) {
79e53945
JB		 2266 master_priv->sarea_priv->pipeB_x = x;
2267 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2268 } else {
2269 master_priv->sarea_priv->pipeA_x = x;
2270 master_priv->sarea_priv->pipeA_y = y;
79e53945 2271 }
5c3b82e2
CW		 2272
2273 return 0;
79e53945
JB		 2274}
2275
5eddb70b 2276static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2277{
2278 struct drm_device *dev = crtc->dev;
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280 u32 dpa_ctl;
2281
28c97730 2282 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2283 dpa_ctl = I915_READ(DP_A);
2284 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2285
2286 if (clock < 200000) {
2287 u32 temp;
2288 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2289 /* workaround for 160Mhz:
2290 1) program 0x4600c bits 15:0 = 0x8124
2291 2) program 0x46010 bit 0 = 1
2292 3) program 0x46034 bit 24 = 1
2293 4) program 0x64000 bit 14 = 1
2294 */
2295 temp = I915_READ(0x4600c);
2296 temp &= 0xffff0000;
2297 I915_WRITE(0x4600c, temp | 0x8124);
2298
2299 temp = I915_READ(0x46010);
2300 I915_WRITE(0x46010, temp | 1);
2301
2302 temp = I915_READ(0x46034);
2303 I915_WRITE(0x46034, temp | (1 << 24));
2304 } else {
2305 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2306 }
2307 I915_WRITE(DP_A, dpa_ctl);
2308
5eddb70b 2309 POSTING_READ(DP_A);
32f9d658
ZW		 2310 udelay(500);
2311}
2312
5e84e1a4
ZW		 2313static void intel_fdi_normal_train(struct drm_crtc *crtc)
2314{
2315 struct drm_device *dev = crtc->dev;
2316 struct drm_i915_private *dev_priv = dev->dev_private;
2317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318 int pipe = intel_crtc->pipe;
2319 u32 reg, temp;
2320
2321 /* enable normal train */
2322 reg = FDI_TX_CTL(pipe);
2323 temp = I915_READ(reg);
61e499bf 2324 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2325 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2326 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2327 } else {
2328 temp &= ~FDI_LINK_TRAIN_NONE;
2329 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2330 }
5e84e1a4
ZW		 2331 I915_WRITE(reg, temp);
2332
2333 reg = FDI_RX_CTL(pipe);
2334 temp = I915_READ(reg);
2335 if (HAS_PCH_CPT(dev)) {
2336 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2337 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2338 } else {
2339 temp &= ~FDI_LINK_TRAIN_NONE;
2340 temp |= FDI_LINK_TRAIN_NONE;
2341 }
2342 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2343
2344 /* wait one idle pattern time */
2345 POSTING_READ(reg);
2346 udelay(1000);
357555c0
JB		 2347
2348 /* IVB wants error correction enabled */
2349 if (IS_IVYBRIDGE(dev))
2350 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2351 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2352}
2353
291427f5
JB		 2354static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2355{
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357 u32 flags = I915_READ(SOUTH_CHICKEN1);
2358
2359 flags |= FDI_PHASE_SYNC_OVR(pipe);
2360 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2361 flags |= FDI_PHASE_SYNC_EN(pipe);
2362 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2363 POSTING_READ(SOUTH_CHICKEN1);
2364}
2365
8db9d77b
ZW		 2366/* The FDI link training functions for ILK/Ibexpeak. */
2367static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2368{
2369 struct drm_device *dev = crtc->dev;
2370 struct drm_i915_private *dev_priv = dev->dev_private;
2371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2372 int pipe = intel_crtc->pipe;
0fc932b8 2373 int plane = intel_crtc->plane;
5eddb70b 2374 u32 reg, temp, tries;
8db9d77b 2375
0fc932b8
JB		 2376 /* FDI needs bits from pipe & plane first */
2377 assert_pipe_enabled(dev_priv, pipe);
2378 assert_plane_enabled(dev_priv, plane);
2379
e1a44743
AJ		 2380 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2381 for train result */
5eddb70b
CW		 2382 reg = FDI_RX_IMR(pipe);
2383 temp = I915_READ(reg);
e1a44743
AJ		 2384 temp &= ~FDI_RX_SYMBOL_LOCK;
2385 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2386 I915_WRITE(reg, temp);
2387 I915_READ(reg);
e1a44743
AJ		 2388 udelay(150);
2389
8db9d77b 2390 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2391 reg = FDI_TX_CTL(pipe);
2392 temp = I915_READ(reg);
77ffb597
AJ		 2393 temp &= ~(7 << 19);
2394 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2397 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2398
5eddb70b
CW		 2399 reg = FDI_RX_CTL(pipe);
2400 temp = I915_READ(reg);
8db9d77b
ZW		 2401 temp &= ~FDI_LINK_TRAIN_NONE;
2402 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2403 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2404
2405 POSTING_READ(reg);
8db9d77b
ZW		 2406 udelay(150);
2407
5b2adf89 2408 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2409 if (HAS_PCH_IBX(dev)) {
2410 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2411 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2412 FDI_RX_PHASE_SYNC_POINTER_EN);
2413 }
5b2adf89 2414
5eddb70b 2415 reg = FDI_RX_IIR(pipe);
e1a44743 2416 for (tries = 0; tries < 5; tries++) {
5eddb70b 2417 temp = I915_READ(reg);
8db9d77b
ZW		 2418 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2419
2420 if ((temp & FDI_RX_BIT_LOCK)) {
2421 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2422 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2423 break;
2424 }
8db9d77b 2425 }
e1a44743 2426 if (tries == 5)
5eddb70b 2427 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2428
2429 /* Train 2 */
5eddb70b
CW		 2430 reg = FDI_TX_CTL(pipe);
2431 temp = I915_READ(reg);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2434 I915_WRITE(reg, temp);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2440 I915_WRITE(reg, temp);
8db9d77b 2441
5eddb70b
CW		 2442 POSTING_READ(reg);
2443 udelay(150);
8db9d77b 2444
5eddb70b 2445 reg = FDI_RX_IIR(pipe);
e1a44743 2446 for (tries = 0; tries < 5; tries++) {
5eddb70b 2447 temp = I915_READ(reg);
8db9d77b
ZW		 2448 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2449
2450 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2451 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2452 DRM_DEBUG_KMS("FDI train 2 done.\n");
2453 break;
2454 }
8db9d77b 2455 }
e1a44743 2456 if (tries == 5)
5eddb70b 2457 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2458
2459 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2460
8db9d77b
ZW		 2461}
2462
0206e353 2463static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2464 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2465 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2466 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2467 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2468};
2469
2470/* The FDI link training functions for SNB/Cougarpoint. */
2471static void gen6_fdi_link_train(struct drm_crtc *crtc)
2472{
2473 struct drm_device *dev = crtc->dev;
2474 struct drm_i915_private *dev_priv = dev->dev_private;
2475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2476 int pipe = intel_crtc->pipe;
fa37d39e 2477 u32 reg, temp, i, retry;
8db9d77b 2478
e1a44743
AJ		 2479 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2480 for train result */
5eddb70b
CW		 2481 reg = FDI_RX_IMR(pipe);
2482 temp = I915_READ(reg);
e1a44743
AJ		 2483 temp &= ~FDI_RX_SYMBOL_LOCK;
2484 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2485 I915_WRITE(reg, temp);
2486
2487 POSTING_READ(reg);
e1a44743
AJ		 2488 udelay(150);
2489
8db9d77b 2490 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2491 reg = FDI_TX_CTL(pipe);
2492 temp = I915_READ(reg);
77ffb597
AJ		 2493 temp &= ~(7 << 19);
2494 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2495 temp &= ~FDI_LINK_TRAIN_NONE;
2496 temp |= FDI_LINK_TRAIN_PATTERN_1;
2497 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2498 /* SNB-B */
2499 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2500 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2501
5eddb70b
CW		 2502 reg = FDI_RX_CTL(pipe);
2503 temp = I915_READ(reg);
8db9d77b
ZW		 2504 if (HAS_PCH_CPT(dev)) {
2505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2506 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2507 } else {
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 }
5eddb70b
CW		 2511 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2512
2513 POSTING_READ(reg);
8db9d77b
ZW		 2514 udelay(150);
2515
291427f5
JB		 2516 if (HAS_PCH_CPT(dev))
2517 cpt_phase_pointer_enable(dev, pipe);
2518
0206e353 2519 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2523 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2524 I915_WRITE(reg, temp);
2525
2526 POSTING_READ(reg);
8db9d77b
ZW		 2527 udelay(500);
2528
fa37d39e
SP		 2529 for (retry = 0; retry < 5; retry++) {
2530 reg = FDI_RX_IIR(pipe);
2531 temp = I915_READ(reg);
2532 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533 if (temp & FDI_RX_BIT_LOCK) {
2534 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2535 DRM_DEBUG_KMS("FDI train 1 done.\n");
2536 break;
2537 }
2538 udelay(50);
8db9d77b 2539 }
fa37d39e
SP		 2540 if (retry < 5)
2541 break;
8db9d77b
ZW		 2542 }
2543 if (i == 4)
5eddb70b 2544 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2545
2546 /* Train 2 */
5eddb70b
CW		 2547 reg = FDI_TX_CTL(pipe);
2548 temp = I915_READ(reg);
8db9d77b
ZW		 2549 temp &= ~FDI_LINK_TRAIN_NONE;
2550 temp |= FDI_LINK_TRAIN_PATTERN_2;
2551 if (IS_GEN6(dev)) {
2552 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2553 /* SNB-B */
2554 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2555 }
5eddb70b 2556 I915_WRITE(reg, temp);
8db9d77b 2557
5eddb70b
CW		 2558 reg = FDI_RX_CTL(pipe);
2559 temp = I915_READ(reg);
8db9d77b
ZW		 2560 if (HAS_PCH_CPT(dev)) {
2561 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2562 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2563 } else {
2564 temp &= ~FDI_LINK_TRAIN_NONE;
2565 temp |= FDI_LINK_TRAIN_PATTERN_2;
2566 }
5eddb70b
CW		 2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
8db9d77b
ZW		 2570 udelay(150);
2571
0206e353 2572 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2573 reg = FDI_TX_CTL(pipe);
2574 temp = I915_READ(reg);
8db9d77b
ZW		 2575 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2576 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2577 I915_WRITE(reg, temp);
2578
2579 POSTING_READ(reg);
8db9d77b
ZW		 2580 udelay(500);
2581
fa37d39e
SP		 2582 for (retry = 0; retry < 5; retry++) {
2583 reg = FDI_RX_IIR(pipe);
2584 temp = I915_READ(reg);
2585 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586 if (temp & FDI_RX_SYMBOL_LOCK) {
2587 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2588 DRM_DEBUG_KMS("FDI train 2 done.\n");
2589 break;
2590 }
2591 udelay(50);
8db9d77b 2592 }
fa37d39e
SP		 2593 if (retry < 5)
2594 break;
8db9d77b
ZW		 2595 }
2596 if (i == 4)
5eddb70b 2597 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2598
2599 DRM_DEBUG_KMS("FDI train done.\n");
2600}
2601
357555c0
JB		 2602/* Manual link training for Ivy Bridge A0 parts */
2603static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2604{
2605 struct drm_device *dev = crtc->dev;
2606 struct drm_i915_private *dev_priv = dev->dev_private;
2607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2608 int pipe = intel_crtc->pipe;
2609 u32 reg, temp, i;
2610
2611 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2612 for train result */
2613 reg = FDI_RX_IMR(pipe);
2614 temp = I915_READ(reg);
2615 temp &= ~FDI_RX_SYMBOL_LOCK;
2616 temp &= ~FDI_RX_BIT_LOCK;
2617 I915_WRITE(reg, temp);
2618
2619 POSTING_READ(reg);
2620 udelay(150);
2621
2622 /* enable CPU FDI TX and PCH FDI RX */
2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
2625 temp &= ~(7 << 19);
2626 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2627 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2628 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2629 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2631 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2632 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2633
2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~FDI_LINK_TRAIN_AUTO;
2637 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2638 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2639 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2640 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2641
2642 POSTING_READ(reg);
2643 udelay(150);
2644
291427f5
JB		 2645 if (HAS_PCH_CPT(dev))
2646 cpt_phase_pointer_enable(dev, pipe);
2647
0206e353 2648 for (i = 0; i < 4; i++) {
357555c0
JB		 2649 reg = FDI_TX_CTL(pipe);
2650 temp = I915_READ(reg);
2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652 temp |= snb_b_fdi_train_param[i];
2653 I915_WRITE(reg, temp);
2654
2655 POSTING_READ(reg);
2656 udelay(500);
2657
2658 reg = FDI_RX_IIR(pipe);
2659 temp = I915_READ(reg);
2660 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2661
2662 if (temp & FDI_RX_BIT_LOCK ||
2663 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2664 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2665 DRM_DEBUG_KMS("FDI train 1 done.\n");
2666 break;
2667 }
2668 }
2669 if (i == 4)
2670 DRM_ERROR("FDI train 1 fail!\n");
2671
2672 /* Train 2 */
2673 reg = FDI_TX_CTL(pipe);
2674 temp = I915_READ(reg);
2675 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2676 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2677 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2679 I915_WRITE(reg, temp);
2680
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2685 I915_WRITE(reg, temp);
2686
2687 POSTING_READ(reg);
2688 udelay(150);
2689
0206e353 2690 for (i = 0; i < 4; i++) {
357555c0
JB		 2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2694 temp |= snb_b_fdi_train_param[i];
2695 I915_WRITE(reg, temp);
2696
2697 POSTING_READ(reg);
2698 udelay(500);
2699
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704 if (temp & FDI_RX_SYMBOL_LOCK) {
2705 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2706 DRM_DEBUG_KMS("FDI train 2 done.\n");
2707 break;
2708 }
2709 }
2710 if (i == 4)
2711 DRM_ERROR("FDI train 2 fail!\n");
2712
2713 DRM_DEBUG_KMS("FDI train done.\n");
2714}
2715
88cefb6c 2716static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2717{
88cefb6c 2718 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2719 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2720 int pipe = intel_crtc->pipe;
5eddb70b 2721 u32 reg, temp;
79e53945 2722
c64e311e 2723 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2724 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2725 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2726
c98e9dcf 2727 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2728 reg = FDI_RX_CTL(pipe);
2729 temp = I915_READ(reg);
2730 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2731 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2732 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2733 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2734
2735 POSTING_READ(reg);
c98e9dcf
JB		 2736 udelay(200);
2737
2738 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2739 temp = I915_READ(reg);
2740 I915_WRITE(reg, temp | FDI_PCDCLK);
2741
2742 POSTING_READ(reg);
c98e9dcf
JB		 2743 udelay(200);
2744
bf507ef7
ED		 2745 /* On Haswell, the PLL configuration for ports and pipes is handled
2746 * separately, as part of DDI setup */
2747 if (!IS_HASWELL(dev)) {
2748 /* Enable CPU FDI TX PLL, always on for Ironlake */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2752 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2753
bf507ef7
ED		 2754 POSTING_READ(reg);
2755 udelay(100);
2756 }
6be4a607 2757 }
0e23b99d
JB		 2758}
2759
88cefb6c
DV		 2760static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2761{
2762 struct drm_device *dev = intel_crtc->base.dev;
2763 struct drm_i915_private *dev_priv = dev->dev_private;
2764 int pipe = intel_crtc->pipe;
2765 u32 reg, temp;
2766
2767 /* Switch from PCDclk to Rawclk */
2768 reg = FDI_RX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2771
2772 /* Disable CPU FDI TX PLL */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2776
2777 POSTING_READ(reg);
2778 udelay(100);
2779
2780 reg = FDI_RX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2783
2784 /* Wait for the clocks to turn off. */
2785 POSTING_READ(reg);
2786 udelay(100);
2787}
2788
291427f5
JB		 2789static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2790{
2791 struct drm_i915_private *dev_priv = dev->dev_private;
2792 u32 flags = I915_READ(SOUTH_CHICKEN1);
2793
2794 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2795 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2796 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2797 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2798 POSTING_READ(SOUTH_CHICKEN1);
2799}
0fc932b8
JB		 2800static void ironlake_fdi_disable(struct drm_crtc *crtc)
2801{
2802 struct drm_device *dev = crtc->dev;
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805 int pipe = intel_crtc->pipe;
2806 u32 reg, temp;
2807
2808 /* disable CPU FDI tx and PCH FDI rx */
2809 reg = FDI_TX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2812 POSTING_READ(reg);
2813
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~(0x7 << 16);
2817 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2818 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2819
2820 POSTING_READ(reg);
2821 udelay(100);
2822
2823 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2824 if (HAS_PCH_IBX(dev)) {
2825 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2826 I915_WRITE(FDI_RX_CHICKEN(pipe),
2827 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2828 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2829 } else if (HAS_PCH_CPT(dev)) {
2830 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2831 }
0fc932b8
JB		 2832
2833 /* still set train pattern 1 */
2834 reg = FDI_TX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~FDI_LINK_TRAIN_NONE;
2837 temp |= FDI_LINK_TRAIN_PATTERN_1;
2838 I915_WRITE(reg, temp);
2839
2840 reg = FDI_RX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 if (HAS_PCH_CPT(dev)) {
2843 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2845 } else {
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848 }
2849 /* BPC in FDI rx is consistent with that in PIPECONF */
2850 temp &= ~(0x07 << 16);
2851 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2852 I915_WRITE(reg, temp);
2853
2854 POSTING_READ(reg);
2855 udelay(100);
2856}
2857
e6c3a2a6
CW		 2858static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2859{
0f91128d 2860 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2861
2862 if (crtc->fb == NULL)
2863 return;
2864
0f91128d
CW		 2865 mutex_lock(&dev->struct_mutex);
2866 intel_finish_fb(crtc->fb);
2867 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2868}
2869
040484af
JB		 2870static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2871{
2872 struct drm_device *dev = crtc->dev;
228d3e36 2873 struct intel_encoder *intel_encoder;
040484af
JB		 2874
2875 /*
2876 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2877 * must be driven by its own crtc; no sharing is possible.
2878 */
228d3e36 2879 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
040484af 2880
6ee8bab0
ED		 2881 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2882 * CPU handles all others */
2883 if (IS_HASWELL(dev)) {
2884 /* It is still unclear how this will work on PPT, so throw up a warning */
2885 WARN_ON(!HAS_PCH_LPT(dev));
2886
228d3e36 2887 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
6ee8bab0
ED		 2888 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2889 return true;
2890 } else {
2891 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
228d3e36 2892 intel_encoder->type);
6ee8bab0
ED		 2893 return false;
2894 }
2895 }
2896
228d3e36 2897 switch (intel_encoder->type) {
040484af 2898 case INTEL_OUTPUT_EDP:
228d3e36 2899 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2900 return false;
2901 continue;
2902 }
2903 }
2904
2905 return true;
2906}
2907
e615efe4
ED		 2908/* Program iCLKIP clock to the desired frequency */
2909static void lpt_program_iclkip(struct drm_crtc *crtc)
2910{
2911 struct drm_device *dev = crtc->dev;
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2913 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2914 u32 temp;
2915
2916 /* It is necessary to ungate the pixclk gate prior to programming
2917 * the divisors, and gate it back when it is done.
2918 */
2919 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2920
2921 /* Disable SSCCTL */
2922 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2923 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2924 SBI_SSCCTL_DISABLE);
2925
2926 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2927 if (crtc->mode.clock == 20000) {
2928 auxdiv = 1;
2929 divsel = 0x41;
2930 phaseinc = 0x20;
2931 } else {
2932 /* The iCLK virtual clock root frequency is in MHz,
2933 * but the crtc->mode.clock in in KHz. To get the divisors,
2934 * it is necessary to divide one by another, so we
2935 * convert the virtual clock precision to KHz here for higher
2936 * precision.
2937 */
2938 u32 iclk_virtual_root_freq = 172800 * 1000;
2939 u32 iclk_pi_range = 64;
2940 u32 desired_divisor, msb_divisor_value, pi_value;
2941
2942 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2943 msb_divisor_value = desired_divisor / iclk_pi_range;
2944 pi_value = desired_divisor % iclk_pi_range;
2945
2946 auxdiv = 0;
2947 divsel = msb_divisor_value - 2;
2948 phaseinc = pi_value;
2949 }
2950
2951 /* This should not happen with any sane values */
2952 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2953 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2954 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2955 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2956
2957 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2958 crtc->mode.clock,
2959 auxdiv,
2960 divsel,
2961 phasedir,
2962 phaseinc);
2963
2964 /* Program SSCDIVINTPHASE6 */
2965 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2966 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2967 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2968 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2969 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2970 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2971 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2972
2973 intel_sbi_write(dev_priv,
2974 SBI_SSCDIVINTPHASE6,
2975 temp);
2976
2977 /* Program SSCAUXDIV */
2978 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2979 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2980 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2981 intel_sbi_write(dev_priv,
2982 SBI_SSCAUXDIV6,
2983 temp);
2984
2985
2986 /* Enable modulator and associated divider */
2987 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2988 temp &= ~SBI_SSCCTL_DISABLE;
2989 intel_sbi_write(dev_priv,
2990 SBI_SSCCTL6,
2991 temp);
2992
2993 /* Wait for initialization time */
2994 udelay(24);
2995
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2997}
2998
f67a559d
JB		 2999/*
3000 * Enable PCH resources required for PCH ports:
3001 * - PCH PLLs
3002 * - FDI training & RX/TX
3003 * - update transcoder timings
3004 * - DP transcoding bits
3005 * - transcoder
3006 */
3007static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3008{
3009 struct drm_device *dev = crtc->dev;
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3012 int pipe = intel_crtc->pipe;
ee7b9f93 3013 u32 reg, temp;
2c07245f 3014
e7e164db
CW		 3015 assert_transcoder_disabled(dev_priv, pipe);
3016
c98e9dcf 3017 /* For PCH output, training FDI link */
674cf967 3018 dev_priv->display.fdi_link_train(crtc);
2c07245f 3019
6f13b7b5
CW		 3020 intel_enable_pch_pll(intel_crtc);
3021
e615efe4
ED		 3022 if (HAS_PCH_LPT(dev)) {
3023 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3024 lpt_program_iclkip(crtc);
3025 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 3026 u32 sel;
4b645f14 3027
c98e9dcf 3028 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3029 switch (pipe) {
3030 default:
3031 case 0:
3032 temp |= TRANSA_DPLL_ENABLE;
3033 sel = TRANSA_DPLLB_SEL;
3034 break;
3035 case 1:
3036 temp |= TRANSB_DPLL_ENABLE;
3037 sel = TRANSB_DPLLB_SEL;
3038 break;
3039 case 2:
3040 temp |= TRANSC_DPLL_ENABLE;
3041 sel = TRANSC_DPLLB_SEL;
3042 break;
d64311ab 3043 }
ee7b9f93
JB		 3044 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3045 temp |= sel;
3046 else
3047 temp &= ~sel;
c98e9dcf 3048 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3049 }
5eddb70b 3050
d9b6cb56
JB		 3051 /* set transcoder timing, panel must allow it */
3052 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3053 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3054 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3055 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3056
5eddb70b
CW		 3057 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3058 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3059 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3060 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3061
f57e1e3a
ED		 3062 if (!IS_HASWELL(dev))
3063 intel_fdi_normal_train(crtc);
5e84e1a4 3064
c98e9dcf
JB		 3065 /* For PCH DP, enable TRANS_DP_CTL */
3066 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3067 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3068 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3069 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3070 reg = TRANS_DP_CTL(pipe);
3071 temp = I915_READ(reg);
3072 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3073 TRANS_DP_SYNC_MASK |
3074 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3075 temp |= (TRANS_DP_OUTPUT_ENABLE |
3076 TRANS_DP_ENH_FRAMING);
9325c9f0 3077 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3078
3079 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3080 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3081 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3082 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3083
3084 switch (intel_trans_dp_port_sel(crtc)) {
3085 case PCH_DP_B:
5eddb70b 3086 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3087 break;
3088 case PCH_DP_C:
5eddb70b 3089 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3090 break;
3091 case PCH_DP_D:
5eddb70b 3092 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3093 break;
3094 default:
3095 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3096 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3097 break;
32f9d658 3098 }
2c07245f 3099
5eddb70b 3100 I915_WRITE(reg, temp);
6be4a607 3101 }
b52eb4dc 3102
040484af 3103 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3104}
3105
ee7b9f93
JB		 3106static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3107{
3108 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3109
3110 if (pll == NULL)
3111 return;
3112
3113 if (pll->refcount == 0) {
3114 WARN(1, "bad PCH PLL refcount\n");
3115 return;
3116 }
3117
3118 --pll->refcount;
3119 intel_crtc->pch_pll = NULL;
3120}
3121
3122static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3123{
3124 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3125 struct intel_pch_pll *pll;
3126 int i;
3127
3128 pll = intel_crtc->pch_pll;
3129 if (pll) {
3130 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3131 intel_crtc->base.base.id, pll->pll_reg);
3132 goto prepare;
3133 }
3134
98b6bd99
DV		 3135 if (HAS_PCH_IBX(dev_priv->dev)) {
3136 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3137 i = intel_crtc->pipe;
3138 pll = &dev_priv->pch_plls[i];
3139
3140 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3141 intel_crtc->base.base.id, pll->pll_reg);
3142
3143 goto found;
3144 }
3145
ee7b9f93
JB		 3146 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3147 pll = &dev_priv->pch_plls[i];
3148
3149 /* Only want to check enabled timings first */
3150 if (pll->refcount == 0)
3151 continue;
3152
3153 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3154 fp == I915_READ(pll->fp0_reg)) {
3155 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3156 intel_crtc->base.base.id,
3157 pll->pll_reg, pll->refcount, pll->active);
3158
3159 goto found;
3160 }
3161 }
3162
3163 /* Ok no matching timings, maybe there's a free one? */
3164 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3165 pll = &dev_priv->pch_plls[i];
3166 if (pll->refcount == 0) {
3167 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3168 intel_crtc->base.base.id, pll->pll_reg);
3169 goto found;
3170 }
3171 }
3172
3173 return NULL;
3174
3175found:
3176 intel_crtc->pch_pll = pll;
3177 pll->refcount++;
3178 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3179prepare: /* separate function? */
3180 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3181
e04c7350
CW		 3182 /* Wait for the clocks to stabilize before rewriting the regs */
3183 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3184 POSTING_READ(pll->pll_reg);
3185 udelay(150);
e04c7350
CW		 3186
3187 I915_WRITE(pll->fp0_reg, fp);
3188 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3189 pll->on = false;
3190 return pll;
3191}
3192
d4270e57
JB		 3193void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3194{
3195 struct drm_i915_private *dev_priv = dev->dev_private;
3196 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3197 u32 temp;
3198
3199 temp = I915_READ(dslreg);
3200 udelay(500);
3201 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3202 /* Without this, mode sets may fail silently on FDI */
3203 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3204 udelay(250);
3205 I915_WRITE(tc2reg, 0);
3206 if (wait_for(I915_READ(dslreg) != temp, 5))
3207 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3208 }
3209}
3210
f67a559d
JB		 3211static void ironlake_crtc_enable(struct drm_crtc *crtc)
3212{
3213 struct drm_device *dev = crtc->dev;
3214 struct drm_i915_private *dev_priv = dev->dev_private;
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3216 struct intel_encoder *encoder;
f67a559d
JB		 3217 int pipe = intel_crtc->pipe;
3218 int plane = intel_crtc->plane;
3219 u32 temp;
3220 bool is_pch_port;
3221
08a48469
DV		 3222 WARN_ON(!crtc->enabled);
3223
f67a559d 3224 if (intel_crtc->active)
ea9d758d 3225 return;
f67a559d
JB		 3226
3227 intel_crtc->active = true;
3228 intel_update_watermarks(dev);
3229
3230 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3231 temp = I915_READ(PCH_LVDS);
3232 if ((temp & LVDS_PORT_EN) == 0)
3233 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3234 }
3235
3236 is_pch_port = intel_crtc_driving_pch(crtc);
3237
3238 if (is_pch_port)
88cefb6c 3239 ironlake_fdi_pll_enable(intel_crtc);
f67a559d
JB		 3240 else
3241 ironlake_fdi_disable(crtc);
3242
3243 /* Enable panel fitting for LVDS */
3244 if (dev_priv->pch_pf_size &&
3245 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3246 /* Force use of hard-coded filter coefficients
3247 * as some pre-programmed values are broken,
3248 * e.g. x201.
3249 */
9db4a9c7
JB		 3250 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3251 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3252 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3253 }
3254
9c54c0dd
JB		 3255 /*
3256 * On ILK+ LUT must be loaded before the pipe is running but with
3257 * clocks enabled
3258 */
3259 intel_crtc_load_lut(crtc);
3260
f67a559d
JB		 3261 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3262 intel_enable_plane(dev_priv, plane, pipe);
3263
3264 if (is_pch_port)
3265 ironlake_pch_enable(crtc);
c98e9dcf 3266
d1ebd816 3267 mutex_lock(&dev->struct_mutex);
bed4a673 3268 intel_update_fbc(dev);
d1ebd816
BW		 3269 mutex_unlock(&dev->struct_mutex);
3270
6b383a7f 3271 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3272
fa5c73b1
DV		 3273 for_each_encoder_on_crtc(dev, crtc, encoder)
3274 encoder->enable(encoder);
61b77ddd
DV		 3275
3276 if (HAS_PCH_CPT(dev))
3277 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 3278}
3279
3280static void ironlake_crtc_disable(struct drm_crtc *crtc)
3281{
3282 struct drm_device *dev = crtc->dev;
3283 struct drm_i915_private *dev_priv = dev->dev_private;
3284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3285 struct intel_encoder *encoder;
6be4a607
JB		 3286 int pipe = intel_crtc->pipe;
3287 int plane = intel_crtc->plane;
5eddb70b 3288 u32 reg, temp;
b52eb4dc 3289
ef9c3aee 3290
f7abfe8b
CW		 3291 if (!intel_crtc->active)
3292 return;
3293
ea9d758d
DV		 3294 for_each_encoder_on_crtc(dev, crtc, encoder)
3295 encoder->disable(encoder);
3296
e6c3a2a6 3297 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3298 drm_vblank_off(dev, pipe);
6b383a7f 3299 intel_crtc_update_cursor(crtc, false);
5eddb70b 3300
b24e7179 3301 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3302
973d04f9
CW		 3303 if (dev_priv->cfb_plane == plane)
3304 intel_disable_fbc(dev);
2c07245f 3305
b24e7179 3306 intel_disable_pipe(dev_priv, pipe);
32f9d658 3307
6be4a607 3308 /* Disable PF */
9db4a9c7
JB		 3309 I915_WRITE(PF_CTL(pipe), 0);
3310 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3311
0fc932b8 3312 ironlake_fdi_disable(crtc);
2c07245f 3313
47a05eca
JB		 3314 /* This is a horrible layering violation; we should be doing this in
3315 * the connector/encoder ->prepare instead, but we don't always have
3316 * enough information there about the config to know whether it will
3317 * actually be necessary or just cause undesired flicker.
3318 */
3319 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3320
040484af 3321 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3322
6be4a607
JB		 3323 if (HAS_PCH_CPT(dev)) {
3324 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3325 reg = TRANS_DP_CTL(pipe);
3326 temp = I915_READ(reg);
3327 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3328 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3329 I915_WRITE(reg, temp);
6be4a607
JB		 3330
3331 /* disable DPLL_SEL */
3332 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3333 switch (pipe) {
3334 case 0:
d64311ab 3335 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3336 break;
3337 case 1:
6be4a607 3338 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3339 break;
3340 case 2:
4b645f14 3341 /* C shares PLL A or B */
d64311ab 3342 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3343 break;
3344 default:
3345 BUG(); /* wtf */
3346 }
6be4a607 3347 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3348 }
e3421a18 3349
6be4a607 3350 /* disable PCH DPLL */
ee7b9f93 3351 intel_disable_pch_pll(intel_crtc);
8db9d77b 3352
88cefb6c 3353 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3354
f7abfe8b 3355 intel_crtc->active = false;
6b383a7f 3356 intel_update_watermarks(dev);
d1ebd816
BW		 3357
3358 mutex_lock(&dev->struct_mutex);
6b383a7f 3359 intel_update_fbc(dev);
d1ebd816 3360 mutex_unlock(&dev->struct_mutex);
6be4a607 3361}
1b3c7a47 3362
ee7b9f93
JB		 3363static void ironlake_crtc_off(struct drm_crtc *crtc)
3364{
3365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366 intel_put_pch_pll(intel_crtc);
3367}
3368
02e792fb
DV		 3369static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3370{
02e792fb 3371 if (!enable && intel_crtc->overlay) {
23f09ce3 3372 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3373 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3374
23f09ce3 3375 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3376 dev_priv->mm.interruptible = false;
3377 (void) intel_overlay_switch_off(intel_crtc->overlay);
3378 dev_priv->mm.interruptible = true;
23f09ce3 3379 mutex_unlock(&dev->struct_mutex);
02e792fb 3380 }
02e792fb 3381
5dcdbcb0
CW		 3382 /* Let userspace switch the overlay on again. In most cases userspace
3383 * has to recompute where to put it anyway.
3384 */
02e792fb
DV		 3385}
3386
0b8765c6 3387static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3388{
3389 struct drm_device *dev = crtc->dev;
79e53945
JB		 3390 struct drm_i915_private *dev_priv = dev->dev_private;
3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3392 struct intel_encoder *encoder;
79e53945 3393 int pipe = intel_crtc->pipe;
80824003 3394 int plane = intel_crtc->plane;
79e53945 3395
08a48469
DV		 3396 WARN_ON(!crtc->enabled);
3397
f7abfe8b 3398 if (intel_crtc->active)
ea9d758d 3399 return;
f7abfe8b
CW		 3400
3401 intel_crtc->active = true;
6b383a7f
CW		 3402 intel_update_watermarks(dev);
3403
63d7bbe9 3404 intel_enable_pll(dev_priv, pipe);
040484af 3405 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3406 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3407
0b8765c6 3408 intel_crtc_load_lut(crtc);
bed4a673 3409 intel_update_fbc(dev);
79e53945 3410
0b8765c6
JB		 3411 /* Give the overlay scaler a chance to enable if it's on this pipe */
3412 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3413 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3414
fa5c73b1
DV		 3415 for_each_encoder_on_crtc(dev, crtc, encoder)
3416 encoder->enable(encoder);
0b8765c6 3417}
79e53945 3418
0b8765c6
JB		 3419static void i9xx_crtc_disable(struct drm_crtc *crtc)
3420{
3421 struct drm_device *dev = crtc->dev;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3424 struct intel_encoder *encoder;
0b8765c6
JB		 3425 int pipe = intel_crtc->pipe;
3426 int plane = intel_crtc->plane;
b690e96c 3427
ef9c3aee 3428
f7abfe8b
CW		 3429 if (!intel_crtc->active)
3430 return;
3431
ea9d758d
DV		 3432 for_each_encoder_on_crtc(dev, crtc, encoder)
3433 encoder->disable(encoder);
3434
0b8765c6 3435 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3436 intel_crtc_wait_for_pending_flips(crtc);
3437 drm_vblank_off(dev, pipe);
0b8765c6 3438 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3439 intel_crtc_update_cursor(crtc, false);
0b8765c6 3440
973d04f9
CW		 3441 if (dev_priv->cfb_plane == plane)
3442 intel_disable_fbc(dev);
79e53945 3443
b24e7179 3444 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3445 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3446 intel_disable_pll(dev_priv, pipe);
0b8765c6 3447
f7abfe8b 3448 intel_crtc->active = false;
6b383a7f
CW		 3449 intel_update_fbc(dev);
3450 intel_update_watermarks(dev);
0b8765c6
JB		 3451}
3452
ee7b9f93
JB		 3453static void i9xx_crtc_off(struct drm_crtc *crtc)
3454{
3455}
3456
976f8a20
DV		 3457static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3458 bool enabled)
2c07245f
ZW		 3459{
3460 struct drm_device *dev = crtc->dev;
3461 struct drm_i915_master_private *master_priv;
3462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3463 int pipe = intel_crtc->pipe;
79e53945
JB		 3464
3465 if (!dev->primary->master)
3466 return;
3467
3468 master_priv = dev->primary->master->driver_priv;
3469 if (!master_priv->sarea_priv)
3470 return;
3471
79e53945
JB		 3472 switch (pipe) {
3473 case 0:
3474 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3475 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3476 break;
3477 case 1:
3478 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3479 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3480 break;
3481 default:
9db4a9c7 3482 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3483 break;
3484 }
79e53945
JB		 3485}
3486
976f8a20
DV		 3487/**
3488 * Sets the power management mode of the pipe and plane.
3489 */
3490void intel_crtc_update_dpms(struct drm_crtc *crtc)
3491{
3492 struct drm_device *dev = crtc->dev;
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 struct intel_encoder *intel_encoder;
3495 bool enable = false;
3496
3497 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3498 enable |= intel_encoder->connectors_active;
3499
3500 if (enable)
3501 dev_priv->display.crtc_enable(crtc);
3502 else
3503 dev_priv->display.crtc_disable(crtc);
3504
3505 intel_crtc_update_sarea(crtc, enable);
3506}
3507
3508static void intel_crtc_noop(struct drm_crtc *crtc)
3509{
3510}
3511
cdd59983
CW		 3512static void intel_crtc_disable(struct drm_crtc *crtc)
3513{
cdd59983 3514 struct drm_device *dev = crtc->dev;
976f8a20 3515 struct drm_connector *connector;
ee7b9f93 3516 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3517
976f8a20
DV		 3518 /* crtc should still be enabled when we disable it. */
3519 WARN_ON(!crtc->enabled);
3520
3521 dev_priv->display.crtc_disable(crtc);
3522 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3523 dev_priv->display.off(crtc);
3524
931872fc
CW		 3525 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3526 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3527
3528 if (crtc->fb) {
3529 mutex_lock(&dev->struct_mutex);
1690e1eb 3530 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3531 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3532 crtc->fb = NULL;
3533 }
3534
3535 /* Update computed state. */
3536 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3537 if (!connector->encoder || !connector->encoder->crtc)
3538 continue;
3539
3540 if (connector->encoder->crtc != crtc)
3541 continue;
3542
3543 connector->dpms = DRM_MODE_DPMS_OFF;
3544 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3545 }
3546}
3547
a261b246
DV		 3548void intel_modeset_disable(struct drm_device *dev)
3549{
3550 struct drm_crtc *crtc;
3551
3552 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3553 if (crtc->enabled)
3554 intel_crtc_disable(crtc);
3555 }
3556}
3557
1f703855 3558void intel_encoder_noop(struct drm_encoder *encoder)
5ab432ef 3559{
5ab432ef
DV		 3560}
3561
ea5b213a
CW		 3562void intel_encoder_destroy(struct drm_encoder *encoder)
3563{
4ef69c7a 3564 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3565
ea5b213a
CW		 3566 drm_encoder_cleanup(encoder);
3567 kfree(intel_encoder);
3568}
3569
5ab432ef
DV		 3570/* Simple dpms helper for encodres with just one connector, no cloning and only
3571 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3572 * state of the entire output pipe. */
3573void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3574{
3575 if (mode == DRM_MODE_DPMS_ON) {
3576 encoder->connectors_active = true;
3577
b2cabb0e 3578 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3579 } else {
3580 encoder->connectors_active = false;
3581
b2cabb0e 3582 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3583 }
3584}
3585
0a91ca29
DV		 3586/* Cross check the actual hw state with our own modeset state tracking (and it's
3587 * internal consistency). */
3588void intel_connector_check_state(struct intel_connector *connector)
3589{
3590 if (connector->get_hw_state(connector)) {
3591 struct intel_encoder *encoder = connector->encoder;
3592 struct drm_crtc *crtc;
3593 bool encoder_enabled;
3594 enum pipe pipe;
3595
3596 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3597 connector->base.base.id,
3598 drm_get_connector_name(&connector->base));
3599
3600 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3601 "wrong connector dpms state\n");
3602 WARN(connector->base.encoder != &encoder->base,
3603 "active connector not linked to encoder\n");
3604 WARN(!encoder->connectors_active,
3605 "encoder->connectors_active not set\n");
3606
3607 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3608 WARN(!encoder_enabled, "encoder not enabled\n");
3609 if (WARN_ON(!encoder->base.crtc))
3610 return;
3611
3612 crtc = encoder->base.crtc;
3613
3614 WARN(!crtc->enabled, "crtc not enabled\n");
3615 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3616 WARN(pipe != to_intel_crtc(crtc)->pipe,
3617 "encoder active on the wrong pipe\n");
3618 }
3619}
3620
5ab432ef
DV		 3621/* Even simpler default implementation, if there's really no special case to
3622 * consider. */
3623void intel_connector_dpms(struct drm_connector *connector, int mode)
3624{
3625 struct intel_encoder *encoder = intel_attached_encoder(connector);
3626
3627 /* All the simple cases only support two dpms states. */
3628 if (mode != DRM_MODE_DPMS_ON)
3629 mode = DRM_MODE_DPMS_OFF;
3630
3631 if (mode == connector->dpms)
3632 return;
3633
3634 connector->dpms = mode;
3635
3636 /* Only need to change hw state when actually enabled */
3637 if (encoder->base.crtc)
3638 intel_encoder_dpms(encoder, mode);
3639 else
3640 encoder->connectors_active = false;
0a91ca29
DV		 3641
3642 intel_connector_check_state(to_intel_connector(connector));
5ab432ef
DV		 3643}
3644
f0947c37
DV		 3645/* Simple connector->get_hw_state implementation for encoders that support only
3646 * one connector and no cloning and hence the encoder state determines the state
3647 * of the connector. */
3648bool intel_connector_get_hw_state(struct intel_connector *connector)
3649{
24929352 3650 enum pipe pipe = 0;
f0947c37
DV		 3651 struct intel_encoder *encoder = connector->encoder;
3652
3653 return encoder->get_hw_state(encoder, &pipe);
3654}
3655
79e53945 3656static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3657 const struct drm_display_mode *mode,
79e53945
JB		 3658 struct drm_display_mode *adjusted_mode)
3659{
2c07245f 3660 struct drm_device *dev = crtc->dev;
89749350 3661
bad720ff 3662 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3663 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3664 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3665 return false;
2c07245f 3666 }
89749350 3667
f9bef081
DV		 3668 /* All interlaced capable intel hw wants timings in frames. Note though
3669 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3670 * timings, so we need to be careful not to clobber these.*/
3671 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3672 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3673
79e53945
JB		 3674 return true;
3675}
3676
25eb05fc
JB		 3677static int valleyview_get_display_clock_speed(struct drm_device *dev)
3678{
3679 return 400000; /* FIXME */
3680}
3681
e70236a8
JB		 3682static int i945_get_display_clock_speed(struct drm_device *dev)
3683{
3684 return 400000;
3685}
79e53945 3686
e70236a8 3687static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3688{
e70236a8
JB		 3689 return 333000;
3690}
79e53945 3691
e70236a8
JB		 3692static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3693{
3694 return 200000;
3695}
79e53945 3696
e70236a8
JB		 3697static int i915gm_get_display_clock_speed(struct drm_device *dev)
3698{
3699 u16 gcfgc = 0;
79e53945 3700
e70236a8
JB		 3701 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3702
3703 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3704 return 133000;
3705 else {
3706 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3707 case GC_DISPLAY_CLOCK_333_MHZ:
3708 return 333000;
3709 default:
3710 case GC_DISPLAY_CLOCK_190_200_MHZ:
3711 return 190000;
79e53945 3712 }
e70236a8
JB		 3713 }
3714}
3715
3716static int i865_get_display_clock_speed(struct drm_device *dev)
3717{
3718 return 266000;
3719}
3720
3721static int i855_get_display_clock_speed(struct drm_device *dev)
3722{
3723 u16 hpllcc = 0;
3724 /* Assume that the hardware is in the high speed state. This
3725 * should be the default.
3726 */
3727 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3728 case GC_CLOCK_133_200:
3729 case GC_CLOCK_100_200:
3730 return 200000;
3731 case GC_CLOCK_166_250:
3732 return 250000;
3733 case GC_CLOCK_100_133:
79e53945 3734 return 133000;
e70236a8 3735 }
79e53945 3736
e70236a8
JB		 3737 /* Shouldn't happen */
3738 return 0;
3739}
79e53945 3740
e70236a8
JB		 3741static int i830_get_display_clock_speed(struct drm_device *dev)
3742{
3743 return 133000;
79e53945
JB		 3744}
3745
2c07245f
ZW		 3746struct fdi_m_n {
3747 u32 tu;
3748 u32 gmch_m;
3749 u32 gmch_n;
3750 u32 link_m;
3751 u32 link_n;
3752};
3753
3754static void
3755fdi_reduce_ratio(u32 *num, u32 *den)
3756{
3757 while (*num > 0xffffff || *den > 0xffffff) {
3758 *num >>= 1;
3759 *den >>= 1;
3760 }
3761}
3762
2c07245f 3763static void
f2b115e6
AJ		 3764ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3765 int link_clock, struct fdi_m_n *m_n)
2c07245f 3766{
2c07245f
ZW		 3767 m_n->tu = 64; /* default size */
3768
22ed1113
CW		 3769 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3770 m_n->gmch_m = bits_per_pixel * pixel_clock;
3771 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3772 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3773
22ed1113
CW		 3774 m_n->link_m = pixel_clock;
3775 m_n->link_n = link_clock;
2c07245f
ZW		 3776 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3777}
3778
a7615030
CW		 3779static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3780{
72bbe58c
KP		 3781 if (i915_panel_use_ssc >= 0)
3782 return i915_panel_use_ssc != 0;
3783 return dev_priv->lvds_use_ssc
435793df 3784 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3785}
3786
5a354204
JB		 3787/**
3788 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3789 * @crtc: CRTC structure
3b5c78a3 3790 * @mode: requested mode
5a354204
JB		 3791 *
3792 * A pipe may be connected to one or more outputs. Based on the depth of the
3793 * attached framebuffer, choose a good color depth to use on the pipe.
3794 *
3795 * If possible, match the pipe depth to the fb depth. In some cases, this
3796 * isn't ideal, because the connected output supports a lesser or restricted
3797 * set of depths. Resolve that here:
3798 * LVDS typically supports only 6bpc, so clamp down in that case
3799 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3800 * Displays may support a restricted set as well, check EDID and clamp as
3801 * appropriate.
3b5c78a3 3802 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3803 *
3804 * RETURNS:
3805 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3806 * true if they don't match).
3807 */
3808static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 3809 struct drm_framebuffer *fb,
3b5c78a3
AJ		 3810 unsigned int *pipe_bpp,
3811 struct drm_display_mode *mode)
5a354204
JB		 3812{
3813 struct drm_device *dev = crtc->dev;
3814 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3815 struct drm_connector *connector;
6c2b7c12 3816 struct intel_encoder *intel_encoder;
5a354204
JB		 3817 unsigned int display_bpc = UINT_MAX, bpc;
3818
3819 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3820 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3821
3822 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3823 unsigned int lvds_bpc;
3824
3825 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3826 LVDS_A3_POWER_UP)
3827 lvds_bpc = 8;
3828 else
3829 lvds_bpc = 6;
3830
3831 if (lvds_bpc < display_bpc) {
82820490 3832 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3833 display_bpc = lvds_bpc;
3834 }
3835 continue;
3836 }
3837
5a354204
JB		 3838 /* Not one of the known troublemakers, check the EDID */
3839 list_for_each_entry(connector, &dev->mode_config.connector_list,
3840 head) {
6c2b7c12 3841 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3842 continue;
3843
62ac41a6
JB		 3844 /* Don't use an invalid EDID bpc value */
3845 if (connector->display_info.bpc &&
3846 connector->display_info.bpc < display_bpc) {
82820490 3847 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3848 display_bpc = connector->display_info.bpc;
3849 }
3850 }
3851
3852 /*
3853 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3854 * through, clamp it down. (Note: >12bpc will be caught below.)
3855 */
3856 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3857 if (display_bpc > 8 && display_bpc < 12) {
82820490 3858 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3859 display_bpc = 12;
3860 } else {
82820490 3861 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3862 display_bpc = 8;
3863 }
3864 }
3865 }
3866
3b5c78a3
AJ		 3867 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3868 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3869 display_bpc = 6;
3870 }
3871
5a354204
JB		 3872 /*
3873 * We could just drive the pipe at the highest bpc all the time and
3874 * enable dithering as needed, but that costs bandwidth. So choose
3875 * the minimum value that expresses the full color range of the fb but
3876 * also stays within the max display bpc discovered above.
3877 */
3878
94352cf9 3879 switch (fb->depth) {
5a354204
JB		 3880 case 8:
3881 bpc = 8; /* since we go through a colormap */
3882 break;
3883 case 15:
3884 case 16:
3885 bpc = 6; /* min is 18bpp */
3886 break;
3887 case 24:
578393cd 3888 bpc = 8;
5a354204
JB		 3889 break;
3890 case 30:
578393cd 3891 bpc = 10;
5a354204
JB		 3892 break;
3893 case 48:
578393cd 3894 bpc = 12;
5a354204
JB		 3895 break;
3896 default:
3897 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3898 bpc = min((unsigned int)8, display_bpc);
3899 break;
3900 }
3901
578393cd
KP		 3902 display_bpc = min(display_bpc, bpc);
3903
82820490
AJ		 3904 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3905 bpc, display_bpc);
5a354204 3906
578393cd 3907 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3908
3909 return display_bpc != bpc;
3910}
3911
a0c4da24
JB		 3912static int vlv_get_refclk(struct drm_crtc *crtc)
3913{
3914 struct drm_device *dev = crtc->dev;
3915 struct drm_i915_private *dev_priv = dev->dev_private;
3916 int refclk = 27000; /* for DP & HDMI */
3917
3918 return 100000; /* only one validated so far */
3919
3920 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3921 refclk = 96000;
3922 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3923 if (intel_panel_use_ssc(dev_priv))
3924 refclk = 100000;
3925 else
3926 refclk = 96000;
3927 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3928 refclk = 100000;
3929 }
3930
3931 return refclk;
3932}
3933
c65d77d8
JB		 3934static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3935{
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
3938 int refclk;
3939
a0c4da24
JB		 3940 if (IS_VALLEYVIEW(dev)) {
3941 refclk = vlv_get_refclk(crtc);
3942 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3943 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3944 refclk = dev_priv->lvds_ssc_freq * 1000;
3945 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3946 refclk / 1000);
3947 } else if (!IS_GEN2(dev)) {
3948 refclk = 96000;
3949 } else {
3950 refclk = 48000;
3951 }
3952
3953 return refclk;
3954}
3955
3956static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3957 intel_clock_t *clock)
3958{
3959 /* SDVO TV has fixed PLL values depend on its clock range,
3960 this mirrors vbios setting. */
3961 if (adjusted_mode->clock >= 100000
3962 && adjusted_mode->clock < 140500) {
3963 clock->p1 = 2;
3964 clock->p2 = 10;
3965 clock->n = 3;
3966 clock->m1 = 16;
3967 clock->m2 = 8;
3968 } else if (adjusted_mode->clock >= 140500
3969 && adjusted_mode->clock <= 200000) {
3970 clock->p1 = 1;
3971 clock->p2 = 10;
3972 clock->n = 6;
3973 clock->m1 = 12;
3974 clock->m2 = 8;
3975 }
3976}
3977
a7516a05
JB		 3978static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3979 intel_clock_t *clock,
3980 intel_clock_t *reduced_clock)
3981{
3982 struct drm_device *dev = crtc->dev;
3983 struct drm_i915_private *dev_priv = dev->dev_private;
3984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3985 int pipe = intel_crtc->pipe;
3986 u32 fp, fp2 = 0;
3987
3988 if (IS_PINEVIEW(dev)) {
3989 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3990 if (reduced_clock)
3991 fp2 = (1 << reduced_clock->n) << 16 |
3992 reduced_clock->m1 << 8 | reduced_clock->m2;
3993 } else {
3994 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3995 if (reduced_clock)
3996 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3997 reduced_clock->m2;
3998 }
3999
4000 I915_WRITE(FP0(pipe), fp);
4001
4002 intel_crtc->lowfreq_avail = false;
4003 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4004 reduced_clock && i915_powersave) {
4005 I915_WRITE(FP1(pipe), fp2);
4006 intel_crtc->lowfreq_avail = true;
4007 } else {
4008 I915_WRITE(FP1(pipe), fp);
4009 }
4010}
4011
93e537a1
DV		 4012static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4013 struct drm_display_mode *adjusted_mode)
4014{
4015 struct drm_device *dev = crtc->dev;
4016 struct drm_i915_private *dev_priv = dev->dev_private;
4017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4018 int pipe = intel_crtc->pipe;
284d5df5 4019 u32 temp;
93e537a1
DV		 4020
4021 temp = I915_READ(LVDS);
4022 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4023 if (pipe == 1) {
4024 temp |= LVDS_PIPEB_SELECT;
4025 } else {
4026 temp &= ~LVDS_PIPEB_SELECT;
4027 }
4028 /* set the corresponsding LVDS_BORDER bit */
4029 temp |= dev_priv->lvds_border_bits;
4030 /* Set the B0-B3 data pairs corresponding to whether we're going to
4031 * set the DPLLs for dual-channel mode or not.
4032 */
4033 if (clock->p2 == 7)
4034 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4035 else
4036 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4037
4038 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4039 * appropriately here, but we need to look more thoroughly into how
4040 * panels behave in the two modes.
4041 */
4042 /* set the dithering flag on LVDS as needed */
4043 if (INTEL_INFO(dev)->gen >= 4) {
4044 if (dev_priv->lvds_dither)
4045 temp |= LVDS_ENABLE_DITHER;
4046 else
4047 temp &= ~LVDS_ENABLE_DITHER;
4048 }
284d5df5 4049 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4050 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4051 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4052 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4053 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4054 I915_WRITE(LVDS, temp);
4055}
4056
a0c4da24
JB		 4057static void vlv_update_pll(struct drm_crtc *crtc,
4058 struct drm_display_mode *mode,
4059 struct drm_display_mode *adjusted_mode,
4060 intel_clock_t *clock, intel_clock_t *reduced_clock,
4061 int refclk, int num_connectors)
4062{
4063 struct drm_device *dev = crtc->dev;
4064 struct drm_i915_private *dev_priv = dev->dev_private;
4065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4066 int pipe = intel_crtc->pipe;
4067 u32 dpll, mdiv, pdiv;
4068 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4069 bool is_hdmi;
4070
4071 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4072
4073 bestn = clock->n;
4074 bestm1 = clock->m1;
4075 bestm2 = clock->m2;
4076 bestp1 = clock->p1;
4077 bestp2 = clock->p2;
4078
4079 /* Enable DPIO clock input */
4080 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4081 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4082 I915_WRITE(DPLL(pipe), dpll);
4083 POSTING_READ(DPLL(pipe));
4084
4085 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4086 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4087 mdiv |= ((bestn << DPIO_N_SHIFT));
4088 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4089 mdiv |= (1 << DPIO_K_SHIFT);
4090 mdiv |= DPIO_ENABLE_CALIBRATION;
4091 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4092
4093 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4094
4095 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4096 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4097 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4098 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4099
4100 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4101
4102 dpll |= DPLL_VCO_ENABLE;
4103 I915_WRITE(DPLL(pipe), dpll);
4104 POSTING_READ(DPLL(pipe));
4105 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4106 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4107
4108 if (is_hdmi) {
4109 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4110
4111 if (temp > 1)
4112 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4113 else
4114 temp = 0;
4115
4116 I915_WRITE(DPLL_MD(pipe), temp);
4117 POSTING_READ(DPLL_MD(pipe));
4118 }
4119
4120 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4121}
4122
eb1cbe48
DV		 4123static void i9xx_update_pll(struct drm_crtc *crtc,
4124 struct drm_display_mode *mode,
4125 struct drm_display_mode *adjusted_mode,
4126 intel_clock_t *clock, intel_clock_t *reduced_clock,
4127 int num_connectors)
4128{
4129 struct drm_device *dev = crtc->dev;
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4132 int pipe = intel_crtc->pipe;
4133 u32 dpll;
4134 bool is_sdvo;
4135
4136 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4137 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4138
4139 dpll = DPLL_VGA_MODE_DIS;
4140
4141 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4142 dpll |= DPLLB_MODE_LVDS;
4143 else
4144 dpll |= DPLLB_MODE_DAC_SERIAL;
4145 if (is_sdvo) {
4146 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4147 if (pixel_multiplier > 1) {
4148 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4149 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4150 }
4151 dpll |= DPLL_DVO_HIGH_SPEED;
4152 }
4153 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4154 dpll |= DPLL_DVO_HIGH_SPEED;
4155
4156 /* compute bitmask from p1 value */
4157 if (IS_PINEVIEW(dev))
4158 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4159 else {
4160 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4161 if (IS_G4X(dev) && reduced_clock)
4162 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4163 }
4164 switch (clock->p2) {
4165 case 5:
4166 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4167 break;
4168 case 7:
4169 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4170 break;
4171 case 10:
4172 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4173 break;
4174 case 14:
4175 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4176 break;
4177 }
4178 if (INTEL_INFO(dev)->gen >= 4)
4179 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4180
4181 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4182 dpll |= PLL_REF_INPUT_TVCLKINBC;
4183 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4184 /* XXX: just matching BIOS for now */
4185 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4186 dpll |= 3;
4187 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4188 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4189 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4190 else
4191 dpll |= PLL_REF_INPUT_DREFCLK;
4192
4193 dpll |= DPLL_VCO_ENABLE;
4194 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4195 POSTING_READ(DPLL(pipe));
4196 udelay(150);
4197
4198 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4199 * This is an exception to the general rule that mode_set doesn't turn
4200 * things on.
4201 */
4202 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4203 intel_update_lvds(crtc, clock, adjusted_mode);
4204
4205 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4206 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4207
4208 I915_WRITE(DPLL(pipe), dpll);
4209
4210 /* Wait for the clocks to stabilize. */
4211 POSTING_READ(DPLL(pipe));
4212 udelay(150);
4213
4214 if (INTEL_INFO(dev)->gen >= 4) {
4215 u32 temp = 0;
4216 if (is_sdvo) {
4217 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4218 if (temp > 1)
4219 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4220 else
4221 temp = 0;
4222 }
4223 I915_WRITE(DPLL_MD(pipe), temp);
4224 } else {
4225 /* The pixel multiplier can only be updated once the
4226 * DPLL is enabled and the clocks are stable.
4227 *
4228 * So write it again.
4229 */
4230 I915_WRITE(DPLL(pipe), dpll);
4231 }
4232}
4233
4234static void i8xx_update_pll(struct drm_crtc *crtc,
4235 struct drm_display_mode *adjusted_mode,
4236 intel_clock_t *clock,
4237 int num_connectors)
4238{
4239 struct drm_device *dev = crtc->dev;
4240 struct drm_i915_private *dev_priv = dev->dev_private;
4241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4242 int pipe = intel_crtc->pipe;
4243 u32 dpll;
4244
4245 dpll = DPLL_VGA_MODE_DIS;
4246
4247 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4248 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4249 } else {
4250 if (clock->p1 == 2)
4251 dpll |= PLL_P1_DIVIDE_BY_TWO;
4252 else
4253 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4254 if (clock->p2 == 4)
4255 dpll |= PLL_P2_DIVIDE_BY_4;
4256 }
4257
4258 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4259 /* XXX: just matching BIOS for now */
4260 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4261 dpll |= 3;
4262 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4263 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4264 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4265 else
4266 dpll |= PLL_REF_INPUT_DREFCLK;
4267
4268 dpll |= DPLL_VCO_ENABLE;
4269 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4270 POSTING_READ(DPLL(pipe));
4271 udelay(150);
4272
4273 I915_WRITE(DPLL(pipe), dpll);
4274
4275 /* Wait for the clocks to stabilize. */
4276 POSTING_READ(DPLL(pipe));
4277 udelay(150);
4278
4279 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4280 * This is an exception to the general rule that mode_set doesn't turn
4281 * things on.
4282 */
4283 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4284 intel_update_lvds(crtc, clock, adjusted_mode);
4285
4286 /* The pixel multiplier can only be updated once the
4287 * DPLL is enabled and the clocks are stable.
4288 *
4289 * So write it again.
4290 */
4291 I915_WRITE(DPLL(pipe), dpll);
4292}
4293
f564048e
EA		 4294static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4295 struct drm_display_mode *mode,
4296 struct drm_display_mode *adjusted_mode,
4297 int x, int y,
94352cf9 4298 struct drm_framebuffer *fb)
79e53945
JB		 4299{
4300 struct drm_device *dev = crtc->dev;
4301 struct drm_i915_private *dev_priv = dev->dev_private;
4302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4303 int pipe = intel_crtc->pipe;
80824003 4304 int plane = intel_crtc->plane;
c751ce4f 4305 int refclk, num_connectors = 0;
652c393a 4306 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 4307 u32 dspcntr, pipeconf, vsyncshift;
4308 bool ok, has_reduced_clock = false, is_sdvo = false;
4309 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4310 struct intel_encoder *encoder;
d4906093 4311 const intel_limit_t *limit;
5c3b82e2 4312 int ret;
79e53945 4313
6c2b7c12 4314 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4315 switch (encoder->type) {
79e53945
JB		 4316 case INTEL_OUTPUT_LVDS:
4317 is_lvds = true;
4318 break;
4319 case INTEL_OUTPUT_SDVO:
7d57382e 4320 case INTEL_OUTPUT_HDMI:
79e53945 4321 is_sdvo = true;
5eddb70b 4322 if (encoder->needs_tv_clock)
e2f0ba97 4323 is_tv = true;
79e53945 4324 break;
79e53945
JB		 4325 case INTEL_OUTPUT_TVOUT:
4326 is_tv = true;
4327 break;
a4fc5ed6
KP		 4328 case INTEL_OUTPUT_DISPLAYPORT:
4329 is_dp = true;
4330 break;
79e53945 4331 }
43565a06 4332
c751ce4f 4333 num_connectors++;
79e53945
JB		 4334 }
4335
c65d77d8 4336 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4337
d4906093
ML		 4338 /*
4339 * Returns a set of divisors for the desired target clock with the given
4340 * refclk, or FALSE. The returned values represent the clock equation:
4341 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4342 */
1b894b59 4343 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4344 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4345 &clock);
79e53945
JB		 4346 if (!ok) {
4347 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4348 return -EINVAL;
79e53945
JB		 4349 }
4350
cda4b7d3 4351 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4352 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4353
ddc9003c 4354 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4355 /*
4356 * Ensure we match the reduced clock's P to the target clock.
4357 * If the clocks don't match, we can't switch the display clock
4358 * by using the FP0/FP1. In such case we will disable the LVDS
4359 * downclock feature.
4360 */
ddc9003c 4361 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4362 dev_priv->lvds_downclock,
4363 refclk,
cec2f356 4364 &clock,
5eddb70b 4365 &reduced_clock);
7026d4ac
ZW		 4366 }
4367
c65d77d8
JB		 4368 if (is_sdvo && is_tv)
4369 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4370
a7516a05
JB		 4371 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4372 &reduced_clock : NULL);
79e53945 4373
eb1cbe48
DV		 4374 if (IS_GEN2(dev))
4375 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
a0c4da24
JB		 4376 else if (IS_VALLEYVIEW(dev))
4377 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4378 refclk, num_connectors);
79e53945 4379 else
eb1cbe48
DV		 4380 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4381 has_reduced_clock ? &reduced_clock : NULL,
4382 num_connectors);
79e53945
JB		 4383
4384 /* setup pipeconf */
5eddb70b 4385 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4386
4387 /* Set up the display plane register */
4388 dspcntr = DISPPLANE_GAMMA_ENABLE;
4389
929c77fb
EA		 4390 if (pipe == 0)
4391 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4392 else
4393 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4394
a6c45cf0 4395 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4396 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4397 * core speed.
4398 *
4399 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4400 * pipe == 0 check?
4401 */
e70236a8
JB		 4402 if (mode->clock >
4403 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4404 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4405 else
5eddb70b 4406 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4407 }
4408
3b5c78a3
AJ		 4409 /* default to 8bpc */
4410 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4411 if (is_dp) {
4412 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4413 pipeconf |= PIPECONF_BPP_6 |
4414 PIPECONF_DITHER_EN |
4415 PIPECONF_DITHER_TYPE_SP;
4416 }
4417 }
4418
28c97730 4419 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4420 drm_mode_debug_printmodeline(mode);
4421
a7516a05
JB		 4422 if (HAS_PIPE_CXSR(dev)) {
4423 if (intel_crtc->lowfreq_avail) {
28c97730 4424 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4425 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4426 } else {
28c97730 4427 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4428 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4429 }
4430 }
4431
617cf884 4432 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4433 if (!IS_GEN2(dev) &&
4434 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4435 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4436 /* the chip adds 2 halflines automatically */
734b4157 4437 adjusted_mode->crtc_vtotal -= 1;
734b4157 4438 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4439 vsyncshift = adjusted_mode->crtc_hsync_start
4440 - adjusted_mode->crtc_htotal/2;
4441 } else {
617cf884 4442 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4443 vsyncshift = 0;
4444 }
4445
4446 if (!IS_GEN3(dev))
4447 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4448
5eddb70b
CW		 4449 I915_WRITE(HTOTAL(pipe),
4450 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4451 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4452 I915_WRITE(HBLANK(pipe),
4453 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4454 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4455 I915_WRITE(HSYNC(pipe),
4456 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4457 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4458
4459 I915_WRITE(VTOTAL(pipe),
4460 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4461 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4462 I915_WRITE(VBLANK(pipe),
4463 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4464 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4465 I915_WRITE(VSYNC(pipe),
4466 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4467 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4468
4469 /* pipesrc and dspsize control the size that is scaled from,
4470 * which should always be the user's requested size.
79e53945 4471 */
929c77fb
EA		 4472 I915_WRITE(DSPSIZE(plane),
4473 ((mode->vdisplay - 1) << 16) |
4474 (mode->hdisplay - 1));
4475 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4476 I915_WRITE(PIPESRC(pipe),
4477 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4478
f564048e
EA		 4479 I915_WRITE(PIPECONF(pipe), pipeconf);
4480 POSTING_READ(PIPECONF(pipe));
929c77fb 4481 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4482
4483 intel_wait_for_vblank(dev, pipe);
4484
f564048e
EA		 4485 I915_WRITE(DSPCNTR(plane), dspcntr);
4486 POSTING_READ(DSPCNTR(plane));
4487
94352cf9 4488 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4489
4490 intel_update_watermarks(dev);
4491
f564048e
EA		 4492 return ret;
4493}
4494
9fb526db
KP		 4495/*
4496 * Initialize reference clocks when the driver loads
4497 */
4498void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4499{
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4502 struct intel_encoder *encoder;
13d83a67
JB		 4503 u32 temp;
4504 bool has_lvds = false;
199e5d79
KP		 4505 bool has_cpu_edp = false;
4506 bool has_pch_edp = false;
4507 bool has_panel = false;
99eb6a01
KP		 4508 bool has_ck505 = false;
4509 bool can_ssc = false;
13d83a67
JB		 4510
4511 /* We need to take the global config into account */
199e5d79
KP		 4512 list_for_each_entry(encoder, &mode_config->encoder_list,
4513 base.head) {
4514 switch (encoder->type) {
4515 case INTEL_OUTPUT_LVDS:
4516 has_panel = true;
4517 has_lvds = true;
4518 break;
4519 case INTEL_OUTPUT_EDP:
4520 has_panel = true;
4521 if (intel_encoder_is_pch_edp(&encoder->base))
4522 has_pch_edp = true;
4523 else
4524 has_cpu_edp = true;
4525 break;
13d83a67
JB		 4526 }
4527 }
4528
99eb6a01
KP		 4529 if (HAS_PCH_IBX(dev)) {
4530 has_ck505 = dev_priv->display_clock_mode;
4531 can_ssc = has_ck505;
4532 } else {
4533 has_ck505 = false;
4534 can_ssc = true;
4535 }
4536
4537 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4538 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4539 has_ck505);
13d83a67
JB		 4540
4541 /* Ironlake: try to setup display ref clock before DPLL
4542 * enabling. This is only under driver's control after
4543 * PCH B stepping, previous chipset stepping should be
4544 * ignoring this setting.
4545 */
4546 temp = I915_READ(PCH_DREF_CONTROL);
4547 /* Always enable nonspread source */
4548 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4549
99eb6a01
KP		 4550 if (has_ck505)
4551 temp |= DREF_NONSPREAD_CK505_ENABLE;
4552 else
4553 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4554
199e5d79
KP		 4555 if (has_panel) {
4556 temp &= ~DREF_SSC_SOURCE_MASK;
4557 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4558
199e5d79 4559 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4560 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4561 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4562 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4563 } else
4564 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4565
4566 /* Get SSC going before enabling the outputs */
4567 I915_WRITE(PCH_DREF_CONTROL, temp);
4568 POSTING_READ(PCH_DREF_CONTROL);
4569 udelay(200);
4570
13d83a67
JB		 4571 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4572
4573 /* Enable CPU source on CPU attached eDP */
199e5d79 4574 if (has_cpu_edp) {
99eb6a01 4575 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4576 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4577 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4578 }
13d83a67
JB		 4579 else
4580 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4581 } else
4582 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4583
4584 I915_WRITE(PCH_DREF_CONTROL, temp);
4585 POSTING_READ(PCH_DREF_CONTROL);
4586 udelay(200);
4587 } else {
4588 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4589
4590 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4591
4592 /* Turn off CPU output */
4593 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4594
4595 I915_WRITE(PCH_DREF_CONTROL, temp);
4596 POSTING_READ(PCH_DREF_CONTROL);
4597 udelay(200);
4598
4599 /* Turn off the SSC source */
4600 temp &= ~DREF_SSC_SOURCE_MASK;
4601 temp |= DREF_SSC_SOURCE_DISABLE;
4602
4603 /* Turn off SSC1 */
4604 temp &= ~ DREF_SSC1_ENABLE;
4605
13d83a67
JB		 4606 I915_WRITE(PCH_DREF_CONTROL, temp);
4607 POSTING_READ(PCH_DREF_CONTROL);
4608 udelay(200);
4609 }
4610}
4611
d9d444cb
JB		 4612static int ironlake_get_refclk(struct drm_crtc *crtc)
4613{
4614 struct drm_device *dev = crtc->dev;
4615 struct drm_i915_private *dev_priv = dev->dev_private;
4616 struct intel_encoder *encoder;
d9d444cb
JB		 4617 struct intel_encoder *edp_encoder = NULL;
4618 int num_connectors = 0;
4619 bool is_lvds = false;
4620
6c2b7c12 4621 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4622 switch (encoder->type) {
4623 case INTEL_OUTPUT_LVDS:
4624 is_lvds = true;
4625 break;
4626 case INTEL_OUTPUT_EDP:
4627 edp_encoder = encoder;
4628 break;
4629 }
4630 num_connectors++;
4631 }
4632
4633 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4634 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4635 dev_priv->lvds_ssc_freq);
4636 return dev_priv->lvds_ssc_freq * 1000;
4637 }
4638
4639 return 120000;
4640}
4641
f564048e
EA		 4642static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4643 struct drm_display_mode *mode,
4644 struct drm_display_mode *adjusted_mode,
4645 int x, int y,
94352cf9 4646 struct drm_framebuffer *fb)
79e53945
JB		 4647{
4648 struct drm_device *dev = crtc->dev;
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4651 int pipe = intel_crtc->pipe;
80824003 4652 int plane = intel_crtc->plane;
c751ce4f 4653 int refclk, num_connectors = 0;
652c393a 4654 intel_clock_t clock, reduced_clock;
5eddb70b 4655 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4656 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4657 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
e3aef172 4658 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4659 const intel_limit_t *limit;
5c3b82e2 4660 int ret;
2c07245f 4661 struct fdi_m_n m_n = {0};
fae14981 4662 u32 temp;
5a354204
JB		 4663 int target_clock, pixel_multiplier, lane, link_bw, factor;
4664 unsigned int pipe_bpp;
4665 bool dither;
e3aef172 4666 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4667
6c2b7c12 4668 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4669 switch (encoder->type) {
79e53945
JB		 4670 case INTEL_OUTPUT_LVDS:
4671 is_lvds = true;
4672 break;
4673 case INTEL_OUTPUT_SDVO:
7d57382e 4674 case INTEL_OUTPUT_HDMI:
79e53945 4675 is_sdvo = true;
5eddb70b 4676 if (encoder->needs_tv_clock)
e2f0ba97 4677 is_tv = true;
79e53945 4678 break;
79e53945
JB		 4679 case INTEL_OUTPUT_TVOUT:
4680 is_tv = true;
4681 break;
4682 case INTEL_OUTPUT_ANALOG:
4683 is_crt = true;
4684 break;
a4fc5ed6
KP		 4685 case INTEL_OUTPUT_DISPLAYPORT:
4686 is_dp = true;
4687 break;
32f9d658 4688 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4689 is_dp = true;
4690 if (intel_encoder_is_pch_edp(&encoder->base))
4691 is_pch_edp = true;
4692 else
4693 is_cpu_edp = true;
4694 edp_encoder = encoder;
32f9d658 4695 break;
79e53945 4696 }
43565a06 4697
c751ce4f 4698 num_connectors++;
79e53945
JB		 4699 }
4700
d9d444cb 4701 refclk = ironlake_get_refclk(crtc);
79e53945 4702
d4906093
ML		 4703 /*
4704 * Returns a set of divisors for the desired target clock with the given
4705 * refclk, or FALSE. The returned values represent the clock equation:
4706 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4707 */
1b894b59 4708 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4709 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4710 &clock);
79e53945
JB		 4711 if (!ok) {
4712 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4713 return -EINVAL;
79e53945
JB		 4714 }
4715
cda4b7d3 4716 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4717 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4718
ddc9003c 4719 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4720 /*
4721 * Ensure we match the reduced clock's P to the target clock.
4722 * If the clocks don't match, we can't switch the display clock
4723 * by using the FP0/FP1. In such case we will disable the LVDS
4724 * downclock feature.
4725 */
ddc9003c 4726 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4727 dev_priv->lvds_downclock,
4728 refclk,
cec2f356 4729 &clock,
5eddb70b 4730 &reduced_clock);
652c393a 4731 }
61e9653f
DV		 4732
4733 if (is_sdvo && is_tv)
4734 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4735
7026d4ac 4736
2c07245f 4737 /* FDI link */
8febb297
EA		 4738 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4739 lane = 0;
4740 /* CPU eDP doesn't require FDI link, so just set DP M/N
4741 according to current link config */
e3aef172 4742 if (is_cpu_edp) {
e3aef172 4743 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 4744 } else {
8febb297
EA		 4745 /* FDI is a binary signal running at ~2.7GHz, encoding
4746 * each output octet as 10 bits. The actual frequency
4747 * is stored as a divider into a 100MHz clock, and the
4748 * mode pixel clock is stored in units of 1KHz.
4749 * Hence the bw of each lane in terms of the mode signal
4750 * is:
4751 */
4752 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4753 }
58a27471 4754
94bf2ced
DV		 4755 /* [e]DP over FDI requires target mode clock instead of link clock. */
4756 if (edp_encoder)
4757 target_clock = intel_edp_target_clock(edp_encoder, mode);
4758 else if (is_dp)
4759 target_clock = mode->clock;
4760 else
4761 target_clock = adjusted_mode->clock;
4762
8febb297
EA		 4763 /* determine panel color depth */
4764 temp = I915_READ(PIPECONF(pipe));
4765 temp &= ~PIPE_BPC_MASK;
94352cf9 4766 dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
5a354204
JB		 4767 switch (pipe_bpp) {
4768 case 18:
4769 temp |= PIPE_6BPC;
8febb297 4770 break;
5a354204
JB		 4771 case 24:
4772 temp |= PIPE_8BPC;
8febb297 4773 break;
5a354204
JB		 4774 case 30:
4775 temp |= PIPE_10BPC;
8febb297 4776 break;
5a354204
JB		 4777 case 36:
4778 temp |= PIPE_12BPC;
8febb297
EA		 4779 break;
4780 default:
62ac41a6
JB		 4781 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4782 pipe_bpp);
5a354204
JB		 4783 temp |= PIPE_8BPC;
4784 pipe_bpp = 24;
4785 break;
8febb297 4786 }
77ffb597 4787
5a354204
JB		 4788 intel_crtc->bpp = pipe_bpp;
4789 I915_WRITE(PIPECONF(pipe), temp);
4790
8febb297
EA		 4791 if (!lane) {
4792 /*
4793 * Account for spread spectrum to avoid
4794 * oversubscribing the link. Max center spread
4795 * is 2.5%; use 5% for safety's sake.
4796 */
5a354204 4797 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4798 lane = bps / (link_bw * 8) + 1;
5eb08b69 4799 }
2c07245f 4800
8febb297
EA		 4801 intel_crtc->fdi_lanes = lane;
4802
4803 if (pixel_multiplier > 1)
4804 link_bw *= pixel_multiplier;
5a354204
JB		 4805 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4806 &m_n);
8febb297 4807
a07d6787
EA		 4808 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4809 if (has_reduced_clock)
4810 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4811 reduced_clock.m2;
79e53945 4812
c1858123 4813 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4814 factor = 21;
4815 if (is_lvds) {
4816 if ((intel_panel_use_ssc(dev_priv) &&
4817 dev_priv->lvds_ssc_freq == 100) ||
4818 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4819 factor = 25;
4820 } else if (is_sdvo && is_tv)
4821 factor = 20;
c1858123 4822
cb0e0931 4823 if (clock.m < factor * clock.n)
8febb297 4824 fp |= FP_CB_TUNE;
2c07245f 4825
5eddb70b 4826 dpll = 0;
2c07245f 4827
a07d6787
EA		 4828 if (is_lvds)
4829 dpll |= DPLLB_MODE_LVDS;
4830 else
4831 dpll |= DPLLB_MODE_DAC_SERIAL;
4832 if (is_sdvo) {
4833 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4834 if (pixel_multiplier > 1) {
4835 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4836 }
a07d6787
EA		 4837 dpll |= DPLL_DVO_HIGH_SPEED;
4838 }
e3aef172 4839 if (is_dp && !is_cpu_edp)
a07d6787 4840 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4841
a07d6787
EA		 4842 /* compute bitmask from p1 value */
4843 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4844 /* also FPA1 */
4845 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4846
4847 switch (clock.p2) {
4848 case 5:
4849 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4850 break;
4851 case 7:
4852 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4853 break;
4854 case 10:
4855 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4856 break;
4857 case 14:
4858 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4859 break;
79e53945
JB		 4860 }
4861
43565a06
KH		 4862 if (is_sdvo && is_tv)
4863 dpll |= PLL_REF_INPUT_TVCLKINBC;
4864 else if (is_tv)
79e53945 4865 /* XXX: just matching BIOS for now */
43565a06 4866 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4867 dpll |= 3;
a7615030 4868 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4869 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4870 else
4871 dpll |= PLL_REF_INPUT_DREFCLK;
4872
4873 /* setup pipeconf */
5eddb70b 4874 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4875
4876 /* Set up the display plane register */
4877 dspcntr = DISPPLANE_GAMMA_ENABLE;
4878
f7cb34d4 4879 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4880 drm_mode_debug_printmodeline(mode);
4881
9d82aa17
ED		 4882 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4883 * pre-Haswell/LPT generation */
4884 if (HAS_PCH_LPT(dev)) {
4885 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4886 pipe);
4887 } else if (!is_cpu_edp) {
ee7b9f93 4888 struct intel_pch_pll *pll;
4b645f14 4889
ee7b9f93
JB		 4890 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4891 if (pll == NULL) {
4892 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4893 pipe);
4b645f14
JB		 4894 return -EINVAL;
4895 }
ee7b9f93
JB		 4896 } else
4897 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4898
4899 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4900 * This is an exception to the general rule that mode_set doesn't turn
4901 * things on.
4902 */
4903 if (is_lvds) {
fae14981 4904 temp = I915_READ(PCH_LVDS);
5eddb70b 4905 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4906 if (HAS_PCH_CPT(dev)) {
4907 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4908 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4909 } else {
4910 if (pipe == 1)
4911 temp |= LVDS_PIPEB_SELECT;
4912 else
4913 temp &= ~LVDS_PIPEB_SELECT;
4914 }
4b645f14 4915
a3e17eb8 4916 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4917 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4918 /* Set the B0-B3 data pairs corresponding to whether we're going to
4919 * set the DPLLs for dual-channel mode or not.
4920 */
4921 if (clock.p2 == 7)
5eddb70b 4922 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4923 else
5eddb70b 4924 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4925
4926 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4927 * appropriately here, but we need to look more thoroughly into how
4928 * panels behave in the two modes.
4929 */
284d5df5 4930 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4931 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4932 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4933 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4934 temp |= LVDS_VSYNC_POLARITY;
fae14981 4935 I915_WRITE(PCH_LVDS, temp);
79e53945 4936 }
434ed097 4937
8febb297
EA		 4938 pipeconf &= ~PIPECONF_DITHER_EN;
4939 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4940 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4941 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4942 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4943 }
e3aef172 4944 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4945 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4946 } else {
8db9d77b 4947 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4948 I915_WRITE(TRANSDATA_M1(pipe), 0);
4949 I915_WRITE(TRANSDATA_N1(pipe), 0);
4950 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4951 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4952 }
79e53945 4953
ee7b9f93
JB		 4954 if (intel_crtc->pch_pll) {
4955 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4956
32f9d658 4957 /* Wait for the clocks to stabilize. */
ee7b9f93 4958 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4959 udelay(150);
4960
8febb297
EA		 4961 /* The pixel multiplier can only be updated once the
4962 * DPLL is enabled and the clocks are stable.
4963 *
4964 * So write it again.
4965 */
ee7b9f93 4966 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4967 }
79e53945 4968
5eddb70b 4969 intel_crtc->lowfreq_avail = false;
ee7b9f93 4970 if (intel_crtc->pch_pll) {
4b645f14 4971 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4972 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 4973 intel_crtc->lowfreq_avail = true;
4b645f14 4974 } else {
ee7b9f93 4975 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 4976 }
4977 }
4978
617cf884 4979 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4980 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4981 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4982 /* the chip adds 2 halflines automatically */
734b4157 4983 adjusted_mode->crtc_vtotal -= 1;
734b4157 4984 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4985 I915_WRITE(VSYNCSHIFT(pipe),
4986 adjusted_mode->crtc_hsync_start
4987 - adjusted_mode->crtc_htotal/2);
4988 } else {
617cf884 4989 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4990 I915_WRITE(VSYNCSHIFT(pipe), 0);
4991 }
734b4157 4992
5eddb70b
CW		 4993 I915_WRITE(HTOTAL(pipe),
4994 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4995 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4996 I915_WRITE(HBLANK(pipe),
4997 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4998 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4999 I915_WRITE(HSYNC(pipe),
5000 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5001 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5002
5003 I915_WRITE(VTOTAL(pipe),
5004 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5005 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5006 I915_WRITE(VBLANK(pipe),
5007 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5008 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5009 I915_WRITE(VSYNC(pipe),
5010 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5011 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5012
8febb297
EA		 5013 /* pipesrc controls the size that is scaled from, which should
5014 * always be the user's requested size.
79e53945 5015 */
5eddb70b
CW		 5016 I915_WRITE(PIPESRC(pipe),
5017 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5018
8febb297
EA		 5019 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5020 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5021 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5022 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5023
e3aef172 5024 if (is_cpu_edp)
8febb297 5025 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5026
5eddb70b
CW		 5027 I915_WRITE(PIPECONF(pipe), pipeconf);
5028 POSTING_READ(PIPECONF(pipe));
79e53945 5029
9d0498a2 5030 intel_wait_for_vblank(dev, pipe);
79e53945 5031
5eddb70b 5032 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5033 POSTING_READ(DSPCNTR(plane));
79e53945 5034
94352cf9 5035 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5036
5037 intel_update_watermarks(dev);
5038
1f8eeabf
ED		 5039 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5040
1f803ee5 5041 return ret;
79e53945
JB		 5042}
5043
f564048e
EA		 5044static int intel_crtc_mode_set(struct drm_crtc *crtc,
5045 struct drm_display_mode *mode,
5046 struct drm_display_mode *adjusted_mode,
5047 int x, int y,
94352cf9 5048 struct drm_framebuffer *fb)
f564048e
EA		 5049{
5050 struct drm_device *dev = crtc->dev;
5051 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5053 int pipe = intel_crtc->pipe;
f564048e
EA		 5054 int ret;
5055
0b701d27 5056 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5057
f564048e 5058 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5059 x, y, fb);
79e53945 5060 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5061
1f803ee5 5062 return ret;
79e53945
JB		 5063}
5064
3a9627f4
WF		 5065static bool intel_eld_uptodate(struct drm_connector *connector,
5066 int reg_eldv, uint32_t bits_eldv,
5067 int reg_elda, uint32_t bits_elda,
5068 int reg_edid)
5069{
5070 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5071 uint8_t *eld = connector->eld;
5072 uint32_t i;
5073
5074 i = I915_READ(reg_eldv);
5075 i &= bits_eldv;
5076
5077 if (!eld[0])
5078 return !i;
5079
5080 if (!i)
5081 return false;
5082
5083 i = I915_READ(reg_elda);
5084 i &= ~bits_elda;
5085 I915_WRITE(reg_elda, i);
5086
5087 for (i = 0; i < eld[2]; i++)
5088 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5089 return false;
5090
5091 return true;
5092}
5093
e0dac65e
WF		 5094static void g4x_write_eld(struct drm_connector *connector,
5095 struct drm_crtc *crtc)
5096{
5097 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5098 uint8_t *eld = connector->eld;
5099 uint32_t eldv;
5100 uint32_t len;
5101 uint32_t i;
5102
5103 i = I915_READ(G4X_AUD_VID_DID);
5104
5105 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5106 eldv = G4X_ELDV_DEVCL_DEVBLC;
5107 else
5108 eldv = G4X_ELDV_DEVCTG;
5109
3a9627f4
WF		 5110 if (intel_eld_uptodate(connector,
5111 G4X_AUD_CNTL_ST, eldv,
5112 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5113 G4X_HDMIW_HDMIEDID))
5114 return;
5115
e0dac65e
WF		 5116 i = I915_READ(G4X_AUD_CNTL_ST);
5117 i &= ~(eldv | G4X_ELD_ADDR);
5118 len = (i >> 9) & 0x1f; /* ELD buffer size */
5119 I915_WRITE(G4X_AUD_CNTL_ST, i);
5120
5121 if (!eld[0])
5122 return;
5123
5124 len = min_t(uint8_t, eld[2], len);
5125 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5126 for (i = 0; i < len; i++)
5127 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5128
5129 i = I915_READ(G4X_AUD_CNTL_ST);
5130 i |= eldv;
5131 I915_WRITE(G4X_AUD_CNTL_ST, i);
5132}
5133
83358c85
WX		 5134static void haswell_write_eld(struct drm_connector *connector,
5135 struct drm_crtc *crtc)
5136{
5137 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5138 uint8_t *eld = connector->eld;
5139 struct drm_device *dev = crtc->dev;
5140 uint32_t eldv;
5141 uint32_t i;
5142 int len;
5143 int pipe = to_intel_crtc(crtc)->pipe;
5144 int tmp;
5145
5146 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5147 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5148 int aud_config = HSW_AUD_CFG(pipe);
5149 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5150
5151
5152 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5153
5154 /* Audio output enable */
5155 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5156 tmp = I915_READ(aud_cntrl_st2);
5157 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5158 I915_WRITE(aud_cntrl_st2, tmp);
5159
5160 /* Wait for 1 vertical blank */
5161 intel_wait_for_vblank(dev, pipe);
5162
5163 /* Set ELD valid state */
5164 tmp = I915_READ(aud_cntrl_st2);
5165 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5166 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5167 I915_WRITE(aud_cntrl_st2, tmp);
5168 tmp = I915_READ(aud_cntrl_st2);
5169 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5170
5171 /* Enable HDMI mode */
5172 tmp = I915_READ(aud_config);
5173 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5174 /* clear N_programing_enable and N_value_index */
5175 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5176 I915_WRITE(aud_config, tmp);
5177
5178 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5179
5180 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5181
5182 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5183 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5184 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5185 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5186 } else
5187 I915_WRITE(aud_config, 0);
5188
5189 if (intel_eld_uptodate(connector,
5190 aud_cntrl_st2, eldv,
5191 aud_cntl_st, IBX_ELD_ADDRESS,
5192 hdmiw_hdmiedid))
5193 return;
5194
5195 i = I915_READ(aud_cntrl_st2);
5196 i &= ~eldv;
5197 I915_WRITE(aud_cntrl_st2, i);
5198
5199 if (!eld[0])
5200 return;
5201
5202 i = I915_READ(aud_cntl_st);
5203 i &= ~IBX_ELD_ADDRESS;
5204 I915_WRITE(aud_cntl_st, i);
5205 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5206 DRM_DEBUG_DRIVER("port num:%d\n", i);
5207
5208 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5209 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5210 for (i = 0; i < len; i++)
5211 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5212
5213 i = I915_READ(aud_cntrl_st2);
5214 i |= eldv;
5215 I915_WRITE(aud_cntrl_st2, i);
5216
5217}
5218
e0dac65e
WF		 5219static void ironlake_write_eld(struct drm_connector *connector,
5220 struct drm_crtc *crtc)
5221{
5222 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5223 uint8_t *eld = connector->eld;
5224 uint32_t eldv;
5225 uint32_t i;
5226 int len;
5227 int hdmiw_hdmiedid;
b6daa025 5228 int aud_config;
e0dac65e
WF		 5229 int aud_cntl_st;
5230 int aud_cntrl_st2;
9b138a83 5231 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5232
b3f33cbf 5233 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5234 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5235 aud_config = IBX_AUD_CFG(pipe);
5236 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5237 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5238 } else {
9b138a83
WX		 5239 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5240 aud_config = CPT_AUD_CFG(pipe);
5241 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5242 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5243 }
5244
9b138a83 5245 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5246
5247 i = I915_READ(aud_cntl_st);
9b138a83 5248 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5249 if (!i) {
5250 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5251 /* operate blindly on all ports */
1202b4c6
WF		 5252 eldv = IBX_ELD_VALIDB;
5253 eldv |= IBX_ELD_VALIDB << 4;
5254 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5255 } else {
5256 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5257 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5258 }
5259
3a9627f4
WF		 5260 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5261 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5262 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5263 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5264 } else
5265 I915_WRITE(aud_config, 0);
e0dac65e 5266
3a9627f4
WF		 5267 if (intel_eld_uptodate(connector,
5268 aud_cntrl_st2, eldv,
5269 aud_cntl_st, IBX_ELD_ADDRESS,
5270 hdmiw_hdmiedid))
5271 return;
5272
e0dac65e
WF		 5273 i = I915_READ(aud_cntrl_st2);
5274 i &= ~eldv;
5275 I915_WRITE(aud_cntrl_st2, i);
5276
5277 if (!eld[0])
5278 return;
5279
e0dac65e 5280 i = I915_READ(aud_cntl_st);
1202b4c6 5281 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5282 I915_WRITE(aud_cntl_st, i);
5283
5284 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5285 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5286 for (i = 0; i < len; i++)
5287 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5288
5289 i = I915_READ(aud_cntrl_st2);
5290 i |= eldv;
5291 I915_WRITE(aud_cntrl_st2, i);
5292}
5293
5294void intel_write_eld(struct drm_encoder *encoder,
5295 struct drm_display_mode *mode)
5296{
5297 struct drm_crtc *crtc = encoder->crtc;
5298 struct drm_connector *connector;
5299 struct drm_device *dev = encoder->dev;
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301
5302 connector = drm_select_eld(encoder, mode);
5303 if (!connector)
5304 return;
5305
5306 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5307 connector->base.id,
5308 drm_get_connector_name(connector),
5309 connector->encoder->base.id,
5310 drm_get_encoder_name(connector->encoder));
5311
5312 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5313
5314 if (dev_priv->display.write_eld)
5315 dev_priv->display.write_eld(connector, crtc);
5316}
5317
79e53945
JB		 5318/** Loads the palette/gamma unit for the CRTC with the prepared values */
5319void intel_crtc_load_lut(struct drm_crtc *crtc)
5320{
5321 struct drm_device *dev = crtc->dev;
5322 struct drm_i915_private *dev_priv = dev->dev_private;
5323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5324 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5325 int i;
5326
5327 /* The clocks have to be on to load the palette. */
aed3f09d 5328 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5329 return;
5330
f2b115e6 5331 /* use legacy palette for Ironlake */
bad720ff 5332 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5333 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5334
79e53945
JB		 5335 for (i = 0; i < 256; i++) {
5336 I915_WRITE(palreg + 4 * i,
5337 (intel_crtc->lut_r[i] << 16) |
5338 (intel_crtc->lut_g[i] << 8) |
5339 intel_crtc->lut_b[i]);
5340 }
5341}
5342
560b85bb
CW		 5343static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5344{
5345 struct drm_device *dev = crtc->dev;
5346 struct drm_i915_private *dev_priv = dev->dev_private;
5347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5348 bool visible = base != 0;
5349 u32 cntl;
5350
5351 if (intel_crtc->cursor_visible == visible)
5352 return;
5353
9db4a9c7 5354 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5355 if (visible) {
5356 /* On these chipsets we can only modify the base whilst
5357 * the cursor is disabled.
5358 */
9db4a9c7 5359 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5360
5361 cntl &= ~(CURSOR_FORMAT_MASK);
5362 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5363 cntl |= CURSOR_ENABLE |
5364 CURSOR_GAMMA_ENABLE |
5365 CURSOR_FORMAT_ARGB;
5366 } else
5367 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5368 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5369
5370 intel_crtc->cursor_visible = visible;
5371}
5372
5373static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5374{
5375 struct drm_device *dev = crtc->dev;
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5378 int pipe = intel_crtc->pipe;
5379 bool visible = base != 0;
5380
5381 if (intel_crtc->cursor_visible != visible) {
548f245b 5382 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5383 if (base) {
5384 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5385 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5386 cntl |= pipe << 28; /* Connect to correct pipe */
5387 } else {
5388 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5389 cntl |= CURSOR_MODE_DISABLE;
5390 }
9db4a9c7 5391 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5392
5393 intel_crtc->cursor_visible = visible;
5394 }
5395 /* and commit changes on next vblank */
9db4a9c7 5396 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5397}
5398
65a21cd6
JB		 5399static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5400{
5401 struct drm_device *dev = crtc->dev;
5402 struct drm_i915_private *dev_priv = dev->dev_private;
5403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5404 int pipe = intel_crtc->pipe;
5405 bool visible = base != 0;
5406
5407 if (intel_crtc->cursor_visible != visible) {
5408 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5409 if (base) {
5410 cntl &= ~CURSOR_MODE;
5411 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5412 } else {
5413 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5414 cntl |= CURSOR_MODE_DISABLE;
5415 }
5416 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5417
5418 intel_crtc->cursor_visible = visible;
5419 }
5420 /* and commit changes on next vblank */
5421 I915_WRITE(CURBASE_IVB(pipe), base);
5422}
5423
cda4b7d3 5424/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5425static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5426 bool on)
cda4b7d3
CW		 5427{
5428 struct drm_device *dev = crtc->dev;
5429 struct drm_i915_private *dev_priv = dev->dev_private;
5430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5431 int pipe = intel_crtc->pipe;
5432 int x = intel_crtc->cursor_x;
5433 int y = intel_crtc->cursor_y;
560b85bb 5434 u32 base, pos;
cda4b7d3
CW		 5435 bool visible;
5436
5437 pos = 0;
5438
6b383a7f 5439 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5440 base = intel_crtc->cursor_addr;
5441 if (x > (int) crtc->fb->width)
5442 base = 0;
5443
5444 if (y > (int) crtc->fb->height)
5445 base = 0;
5446 } else
5447 base = 0;
5448
5449 if (x < 0) {
5450 if (x + intel_crtc->cursor_width < 0)
5451 base = 0;
5452
5453 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5454 x = -x;
5455 }
5456 pos |= x << CURSOR_X_SHIFT;
5457
5458 if (y < 0) {
5459 if (y + intel_crtc->cursor_height < 0)
5460 base = 0;
5461
5462 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5463 y = -y;
5464 }
5465 pos |= y << CURSOR_Y_SHIFT;
5466
5467 visible = base != 0;
560b85bb 5468 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5469 return;
5470
0cd83aa9 5471 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5472 I915_WRITE(CURPOS_IVB(pipe), pos);
5473 ivb_update_cursor(crtc, base);
5474 } else {
5475 I915_WRITE(CURPOS(pipe), pos);
5476 if (IS_845G(dev) || IS_I865G(dev))
5477 i845_update_cursor(crtc, base);
5478 else
5479 i9xx_update_cursor(crtc, base);
5480 }
cda4b7d3
CW		 5481}
5482
79e53945 5483static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5484 struct drm_file *file,
79e53945
JB		 5485 uint32_t handle,
5486 uint32_t width, uint32_t height)
5487{
5488 struct drm_device *dev = crtc->dev;
5489 struct drm_i915_private *dev_priv = dev->dev_private;
5490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5491 struct drm_i915_gem_object *obj;
cda4b7d3 5492 uint32_t addr;
3f8bc370 5493 int ret;
79e53945 5494
79e53945
JB		 5495 /* if we want to turn off the cursor ignore width and height */
5496 if (!handle) {
28c97730 5497 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5498 addr = 0;
05394f39 5499 obj = NULL;
5004417d 5500 mutex_lock(&dev->struct_mutex);
3f8bc370 5501 goto finish;
79e53945
JB		 5502 }
5503
5504 /* Currently we only support 64x64 cursors */
5505 if (width != 64 || height != 64) {
5506 DRM_ERROR("we currently only support 64x64 cursors\n");
5507 return -EINVAL;
5508 }
5509
05394f39 5510 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5511 if (&obj->base == NULL)
79e53945
JB		 5512 return -ENOENT;
5513
05394f39 5514 if (obj->base.size < width * height * 4) {
79e53945 5515 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5516 ret = -ENOMEM;
5517 goto fail;
79e53945
JB		 5518 }
5519
71acb5eb 5520 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5521 mutex_lock(&dev->struct_mutex);
b295d1b6 5522 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5523 if (obj->tiling_mode) {
5524 DRM_ERROR("cursor cannot be tiled\n");
5525 ret = -EINVAL;
5526 goto fail_locked;
5527 }
5528
2da3b9b9 5529 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5530 if (ret) {
5531 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5532 goto fail_locked;
e7b526bb
CW		 5533 }
5534
d9e86c0e
CW		 5535 ret = i915_gem_object_put_fence(obj);
5536 if (ret) {
2da3b9b9 5537 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5538 goto fail_unpin;
5539 }
5540
05394f39 5541 addr = obj->gtt_offset;
71acb5eb 5542 } else {
6eeefaf3 5543 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5544 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5545 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5546 align);
71acb5eb
DA		 5547 if (ret) {
5548 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5549 goto fail_locked;
71acb5eb 5550 }
05394f39 5551 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5552 }
5553
a6c45cf0 5554 if (IS_GEN2(dev))
14b60391
JB		 5555 I915_WRITE(CURSIZE, (height << 12) | width);
5556
3f8bc370 5557 finish:
3f8bc370 5558 if (intel_crtc->cursor_bo) {
b295d1b6 5559 if (dev_priv->info->cursor_needs_physical) {
05394f39 5560 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5561 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5562 } else
5563 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5564 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5565 }
80824003 5566
7f9872e0 5567 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5568
5569 intel_crtc->cursor_addr = addr;
05394f39 5570 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5571 intel_crtc->cursor_width = width;
5572 intel_crtc->cursor_height = height;
5573
6b383a7f 5574 intel_crtc_update_cursor(crtc, true);
3f8bc370 5575
79e53945 5576 return 0;
e7b526bb 5577fail_unpin:
05394f39 5578 i915_gem_object_unpin(obj);
7f9872e0 5579fail_locked:
34b8686e 5580 mutex_unlock(&dev->struct_mutex);
bc9025bd 5581fail:
05394f39 5582 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5583 return ret;
79e53945
JB		 5584}
5585
5586static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5587{
79e53945 5588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5589
cda4b7d3
CW		 5590 intel_crtc->cursor_x = x;
5591 intel_crtc->cursor_y = y;
652c393a 5592
6b383a7f 5593 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5594
5595 return 0;
5596}
5597
5598/** Sets the color ramps on behalf of RandR */
5599void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5600 u16 blue, int regno)
5601{
5602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5603
5604 intel_crtc->lut_r[regno] = red >> 8;
5605 intel_crtc->lut_g[regno] = green >> 8;
5606 intel_crtc->lut_b[regno] = blue >> 8;
5607}
5608
b8c00ac5
DA		 5609void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5610 u16 *blue, int regno)
5611{
5612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5613
5614 *red = intel_crtc->lut_r[regno] << 8;
5615 *green = intel_crtc->lut_g[regno] << 8;
5616 *blue = intel_crtc->lut_b[regno] << 8;
5617}
5618
79e53945 5619static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5620 u16 *blue, uint32_t start, uint32_t size)
79e53945 5621{
7203425a 5622 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5624
7203425a 5625 for (i = start; i < end; i++) {
79e53945
JB		 5626 intel_crtc->lut_r[i] = red[i] >> 8;
5627 intel_crtc->lut_g[i] = green[i] >> 8;
5628 intel_crtc->lut_b[i] = blue[i] >> 8;
5629 }
5630
5631 intel_crtc_load_lut(crtc);
5632}
5633
5634/**
5635 * Get a pipe with a simple mode set on it for doing load-based monitor
5636 * detection.
5637 *
5638 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5639 * its requirements. The pipe will be connected to no other encoders.
79e53945 5640 *
c751ce4f 5641 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5642 * configured for it. In the future, it could choose to temporarily disable
5643 * some outputs to free up a pipe for its use.
5644 *
5645 * \return crtc, or NULL if no pipes are available.
5646 */
5647
5648/* VESA 640x480x72Hz mode to set on the pipe */
5649static struct drm_display_mode load_detect_mode = {
5650 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5651 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5652};
5653
d2dff872
CW		 5654static struct drm_framebuffer *
5655intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5656 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5657 struct drm_i915_gem_object *obj)
5658{
5659 struct intel_framebuffer *intel_fb;
5660 int ret;
5661
5662 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5663 if (!intel_fb) {
5664 drm_gem_object_unreference_unlocked(&obj->base);
5665 return ERR_PTR(-ENOMEM);
5666 }
5667
5668 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5669 if (ret) {
5670 drm_gem_object_unreference_unlocked(&obj->base);
5671 kfree(intel_fb);
5672 return ERR_PTR(ret);
5673 }
5674
5675 return &intel_fb->base;
5676}
5677
5678static u32
5679intel_framebuffer_pitch_for_width(int width, int bpp)
5680{
5681 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5682 return ALIGN(pitch, 64);
5683}
5684
5685static u32
5686intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5687{
5688 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5689 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5690}
5691
5692static struct drm_framebuffer *
5693intel_framebuffer_create_for_mode(struct drm_device *dev,
5694 struct drm_display_mode *mode,
5695 int depth, int bpp)
5696{
5697 struct drm_i915_gem_object *obj;
308e5bcb 5698 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5699
5700 obj = i915_gem_alloc_object(dev,
5701 intel_framebuffer_size_for_mode(mode, bpp));
5702 if (obj == NULL)
5703 return ERR_PTR(-ENOMEM);
5704
5705 mode_cmd.width = mode->hdisplay;
5706 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5707 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5708 bpp);
5ca0c34a 5709 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5710
5711 return intel_framebuffer_create(dev, &mode_cmd, obj);
5712}
5713
5714static struct drm_framebuffer *
5715mode_fits_in_fbdev(struct drm_device *dev,
5716 struct drm_display_mode *mode)
5717{
5718 struct drm_i915_private *dev_priv = dev->dev_private;
5719 struct drm_i915_gem_object *obj;
5720 struct drm_framebuffer *fb;
5721
5722 if (dev_priv->fbdev == NULL)
5723 return NULL;
5724
5725 obj = dev_priv->fbdev->ifb.obj;
5726 if (obj == NULL)
5727 return NULL;
5728
5729 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5730 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5731 fb->bits_per_pixel))
d2dff872
CW		 5732 return NULL;
5733
01f2c773 5734 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5735 return NULL;
5736
5737 return fb;
5738}
5739
d2434ab7 5740bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 5741 struct drm_display_mode *mode,
8261b191 5742 struct intel_load_detect_pipe *old)
79e53945
JB		 5743{
5744 struct intel_crtc *intel_crtc;
d2434ab7
DV		 5745 struct intel_encoder *intel_encoder =
5746 intel_attached_encoder(connector);
79e53945 5747 struct drm_crtc *possible_crtc;
4ef69c7a 5748 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5749 struct drm_crtc *crtc = NULL;
5750 struct drm_device *dev = encoder->dev;
94352cf9 5751 struct drm_framebuffer *fb;
79e53945
JB		 5752 int i = -1;
5753
d2dff872
CW		 5754 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5755 connector->base.id, drm_get_connector_name(connector),
5756 encoder->base.id, drm_get_encoder_name(encoder));
5757
79e53945
JB		 5758 /*
5759 * Algorithm gets a little messy:
7a5e4805 5760 *
79e53945
JB		 5761 * - if the connector already has an assigned crtc, use it (but make
5762 * sure it's on first)
7a5e4805 5763 *
79e53945
JB		 5764 * - try to find the first unused crtc that can drive this connector,
5765 * and use that if we find one
79e53945
JB		 5766 */
5767
5768 /* See if we already have a CRTC for this connector */
5769 if (encoder->crtc) {
5770 crtc = encoder->crtc;
8261b191 5771
24218aac 5772 old->dpms_mode = connector->dpms;
8261b191
CW		 5773 old->load_detect_temp = false;
5774
5775 /* Make sure the crtc and connector are running */
24218aac
DV		 5776 if (connector->dpms != DRM_MODE_DPMS_ON)
5777 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 5778
7173188d 5779 return true;
79e53945
JB		 5780 }
5781
5782 /* Find an unused one (if possible) */
5783 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5784 i++;
5785 if (!(encoder->possible_crtcs & (1 << i)))
5786 continue;
5787 if (!possible_crtc->enabled) {
5788 crtc = possible_crtc;
5789 break;
5790 }
79e53945
JB		 5791 }
5792
5793 /*
5794 * If we didn't find an unused CRTC, don't use any.
5795 */
5796 if (!crtc) {
7173188d
CW		 5797 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5798 return false;
79e53945
JB		 5799 }
5800
fc303101
DV		 5801 intel_encoder->new_crtc = to_intel_crtc(crtc);
5802 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 5803
5804 intel_crtc = to_intel_crtc(crtc);
24218aac 5805 old->dpms_mode = connector->dpms;
8261b191 5806 old->load_detect_temp = true;
d2dff872 5807 old->release_fb = NULL;
79e53945 5808
6492711d
CW		 5809 if (!mode)
5810 mode = &load_detect_mode;
79e53945 5811
d2dff872
CW		 5812 /* We need a framebuffer large enough to accommodate all accesses
5813 * that the plane may generate whilst we perform load detection.
5814 * We can not rely on the fbcon either being present (we get called
5815 * during its initialisation to detect all boot displays, or it may
5816 * not even exist) or that it is large enough to satisfy the
5817 * requested mode.
5818 */
94352cf9
DV		 5819 fb = mode_fits_in_fbdev(dev, mode);
5820 if (fb == NULL) {
d2dff872 5821 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 5822 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5823 old->release_fb = fb;
d2dff872
CW		 5824 } else
5825 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 5826 if (IS_ERR(fb)) {
d2dff872 5827 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 5828 goto fail;
79e53945 5829 }
79e53945 5830
94352cf9 5831 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 5832 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5833 if (old->release_fb)
5834 old->release_fb->funcs->destroy(old->release_fb);
24218aac 5835 goto fail;
79e53945 5836 }
7173188d 5837
79e53945 5838 /* let the connector get through one full cycle before testing */
9d0498a2 5839 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5840
7173188d 5841 return true;
24218aac
DV		 5842fail:
5843 connector->encoder = NULL;
5844 encoder->crtc = NULL;
24218aac 5845 return false;
79e53945
JB		 5846}
5847
d2434ab7 5848void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 5849 struct intel_load_detect_pipe *old)
79e53945 5850{
d2434ab7
DV		 5851 struct intel_encoder *intel_encoder =
5852 intel_attached_encoder(connector);
4ef69c7a 5853 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 5854
d2dff872
CW		 5855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5856 connector->base.id, drm_get_connector_name(connector),
5857 encoder->base.id, drm_get_encoder_name(encoder));
5858
8261b191 5859 if (old->load_detect_temp) {
fc303101
DV		 5860 struct drm_crtc *crtc = encoder->crtc;
5861
5862 to_intel_connector(connector)->new_encoder = NULL;
5863 intel_encoder->new_crtc = NULL;
5864 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 5865
5866 if (old->release_fb)
5867 old->release_fb->funcs->destroy(old->release_fb);
5868
0622a53c 5869 return;
79e53945
JB		 5870 }
5871
c751ce4f 5872 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 5873 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5874 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 5875}
5876
5877/* Returns the clock of the currently programmed mode of the given pipe. */
5878static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5879{
5880 struct drm_i915_private *dev_priv = dev->dev_private;
5881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5882 int pipe = intel_crtc->pipe;
548f245b 5883 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5884 u32 fp;
5885 intel_clock_t clock;
5886
5887 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5888 fp = I915_READ(FP0(pipe));
79e53945 5889 else
39adb7a5 5890 fp = I915_READ(FP1(pipe));
79e53945
JB		 5891
5892 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5893 if (IS_PINEVIEW(dev)) {
5894 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5895 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5896 } else {
5897 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5898 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5899 }
5900
a6c45cf0 5901 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5902 if (IS_PINEVIEW(dev))
5903 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5904 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5905 else
5906 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5907 DPLL_FPA01_P1_POST_DIV_SHIFT);
5908
5909 switch (dpll & DPLL_MODE_MASK) {
5910 case DPLLB_MODE_DAC_SERIAL:
5911 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5912 5 : 10;
5913 break;
5914 case DPLLB_MODE_LVDS:
5915 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5916 7 : 14;
5917 break;
5918 default:
28c97730 5919 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5920 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5921 return 0;
5922 }
5923
5924 /* XXX: Handle the 100Mhz refclk */
2177832f 5925 intel_clock(dev, 96000, &clock);
79e53945
JB		 5926 } else {
5927 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5928
5929 if (is_lvds) {
5930 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5931 DPLL_FPA01_P1_POST_DIV_SHIFT);
5932 clock.p2 = 14;
5933
5934 if ((dpll & PLL_REF_INPUT_MASK) ==
5935 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5936 /* XXX: might not be 66MHz */
2177832f 5937 intel_clock(dev, 66000, &clock);
79e53945 5938 } else
2177832f 5939 intel_clock(dev, 48000, &clock);
79e53945
JB		 5940 } else {
5941 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5942 clock.p1 = 2;
5943 else {
5944 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5945 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5946 }
5947 if (dpll & PLL_P2_DIVIDE_BY_4)
5948 clock.p2 = 4;
5949 else
5950 clock.p2 = 2;
5951
2177832f 5952 intel_clock(dev, 48000, &clock);
79e53945
JB		 5953 }
5954 }
5955
5956 /* XXX: It would be nice to validate the clocks, but we can't reuse
5957 * i830PllIsValid() because it relies on the xf86_config connector
5958 * configuration being accurate, which it isn't necessarily.
5959 */
5960
5961 return clock.dot;
5962}
5963
5964/** Returns the currently programmed mode of the given pipe. */
5965struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5966 struct drm_crtc *crtc)
5967{
548f245b 5968 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5970 int pipe = intel_crtc->pipe;
5971 struct drm_display_mode *mode;
548f245b
JB		 5972 int htot = I915_READ(HTOTAL(pipe));
5973 int hsync = I915_READ(HSYNC(pipe));
5974 int vtot = I915_READ(VTOTAL(pipe));
5975 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5976
5977 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5978 if (!mode)
5979 return NULL;
5980
5981 mode->clock = intel_crtc_clock_get(dev, crtc);
5982 mode->hdisplay = (htot & 0xffff) + 1;
5983 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5984 mode->hsync_start = (hsync & 0xffff) + 1;
5985 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5986 mode->vdisplay = (vtot & 0xffff) + 1;
5987 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5988 mode->vsync_start = (vsync & 0xffff) + 1;
5989 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5990
5991 drm_mode_set_name(mode);
79e53945
JB		 5992
5993 return mode;
5994}
5995
3dec0095 5996static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5997{
5998 struct drm_device *dev = crtc->dev;
5999 drm_i915_private_t *dev_priv = dev->dev_private;
6000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6001 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6002 int dpll_reg = DPLL(pipe);
6003 int dpll;
652c393a 6004
bad720ff 6005 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6006 return;
6007
6008 if (!dev_priv->lvds_downclock_avail)
6009 return;
6010
dbdc6479 6011 dpll = I915_READ(dpll_reg);
652c393a 6012 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6013 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6014
8ac5a6d5 6015 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6016
6017 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6018 I915_WRITE(dpll_reg, dpll);
9d0498a2 6019 intel_wait_for_vblank(dev, pipe);
dbdc6479 6020
652c393a
JB		 6021 dpll = I915_READ(dpll_reg);
6022 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6023 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6024 }
652c393a
JB		 6025}
6026
6027static void intel_decrease_pllclock(struct drm_crtc *crtc)
6028{
6029 struct drm_device *dev = crtc->dev;
6030 drm_i915_private_t *dev_priv = dev->dev_private;
6031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6032
bad720ff 6033 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6034 return;
6035
6036 if (!dev_priv->lvds_downclock_avail)
6037 return;
6038
6039 /*
6040 * Since this is called by a timer, we should never get here in
6041 * the manual case.
6042 */
6043 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6044 int pipe = intel_crtc->pipe;
6045 int dpll_reg = DPLL(pipe);
6046 int dpll;
f6e5b160 6047
44d98a61 6048 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6049
8ac5a6d5 6050 assert_panel_unlocked(dev_priv, pipe);
652c393a 6051
dc257cf1 6052 dpll = I915_READ(dpll_reg);
652c393a
JB		 6053 dpll |= DISPLAY_RATE_SELECT_FPA1;
6054 I915_WRITE(dpll_reg, dpll);
9d0498a2 6055 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6056 dpll = I915_READ(dpll_reg);
6057 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6058 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6059 }
6060
6061}
6062
f047e395
CW		 6063void intel_mark_busy(struct drm_device *dev)
6064{
f047e395
CW		 6065 i915_update_gfx_val(dev->dev_private);
6066}
6067
6068void intel_mark_idle(struct drm_device *dev)
652c393a 6069{
f047e395
CW		 6070}
6071
6072void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6073{
6074 struct drm_device *dev = obj->base.dev;
652c393a 6075 struct drm_crtc *crtc;
652c393a
JB		 6076
6077 if (!i915_powersave)
6078 return;
6079
652c393a 6080 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6081 if (!crtc->fb)
6082 continue;
6083
f047e395
CW		 6084 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6085 intel_increase_pllclock(crtc);
652c393a 6086 }
652c393a
JB		 6087}
6088
f047e395 6089void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6090{
f047e395
CW		 6091 struct drm_device *dev = obj->base.dev;
6092 struct drm_crtc *crtc;
652c393a 6093
f047e395 6094 if (!i915_powersave)
acb87dfb
CW		 6095 return;
6096
652c393a
JB		 6097 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6098 if (!crtc->fb)
6099 continue;
6100
f047e395
CW		 6101 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6102 intel_decrease_pllclock(crtc);
652c393a
JB		 6103 }
6104}
6105
79e53945
JB		 6106static void intel_crtc_destroy(struct drm_crtc *crtc)
6107{
6108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6109 struct drm_device *dev = crtc->dev;
6110 struct intel_unpin_work *work;
6111 unsigned long flags;
6112
6113 spin_lock_irqsave(&dev->event_lock, flags);
6114 work = intel_crtc->unpin_work;
6115 intel_crtc->unpin_work = NULL;
6116 spin_unlock_irqrestore(&dev->event_lock, flags);
6117
6118 if (work) {
6119 cancel_work_sync(&work->work);
6120 kfree(work);
6121 }
79e53945
JB		 6122
6123 drm_crtc_cleanup(crtc);
67e77c5a 6124
79e53945
JB		 6125 kfree(intel_crtc);
6126}
6127
6b95a207
KH		 6128static void intel_unpin_work_fn(struct work_struct *__work)
6129{
6130 struct intel_unpin_work *work =
6131 container_of(__work, struct intel_unpin_work, work);
6132
6133 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6134 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6135 drm_gem_object_unreference(&work->pending_flip_obj->base);
6136 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6137
7782de3b 6138 intel_update_fbc(work->dev);
6b95a207
KH		 6139 mutex_unlock(&work->dev->struct_mutex);
6140 kfree(work);
6141}
6142
1afe3e9d 6143static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6144 struct drm_crtc *crtc)
6b95a207
KH		 6145{
6146 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6148 struct intel_unpin_work *work;
05394f39 6149 struct drm_i915_gem_object *obj;
6b95a207 6150 struct drm_pending_vblank_event *e;
49b14a5c 6151 struct timeval tnow, tvbl;
6b95a207
KH		 6152 unsigned long flags;
6153
6154 /* Ignore early vblank irqs */
6155 if (intel_crtc == NULL)
6156 return;
6157
49b14a5c
MK		 6158 do_gettimeofday(&tnow);
6159
6b95a207
KH		 6160 spin_lock_irqsave(&dev->event_lock, flags);
6161 work = intel_crtc->unpin_work;
6162 if (work == NULL || !work->pending) {
6163 spin_unlock_irqrestore(&dev->event_lock, flags);
6164 return;
6165 }
6166
6167 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6168
6169 if (work->event) {
6170 e = work->event;
49b14a5c 6171 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6172
6173 /* Called before vblank count and timestamps have
6174 * been updated for the vblank interval of flip
6175 * completion? Need to increment vblank count and
6176 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6177 * to account for this. We assume this happened if we
6178 * get called over 0.9 frame durations after the last
6179 * timestamped vblank.
6180 *
6181 * This calculation can not be used with vrefresh rates
6182 * below 5Hz (10Hz to be on the safe side) without
6183 * promoting to 64 integers.
0af7e4df 6184 */
49b14a5c
MK		 6185 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6186 9 * crtc->framedur_ns) {
0af7e4df 6187 e->event.sequence++;
49b14a5c
MK		 6188 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6189 crtc->framedur_ns);
0af7e4df
MK		 6190 }
6191
49b14a5c
MK		 6192 e->event.tv_sec = tvbl.tv_sec;
6193 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6194
6b95a207
KH		 6195 list_add_tail(&e->base.link,
6196 &e->base.file_priv->event_list);
6197 wake_up_interruptible(&e->base.file_priv->event_wait);
6198 }
6199
0af7e4df
MK		 6200 drm_vblank_put(dev, intel_crtc->pipe);
6201
6b95a207
KH		 6202 spin_unlock_irqrestore(&dev->event_lock, flags);
6203
05394f39 6204 obj = work->old_fb_obj;
d9e86c0e 6205
e59f2bac 6206 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6207 &obj->pending_flip.counter);
6208 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6209 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6210
6b95a207 6211 schedule_work(&work->work);
e5510fac
JB		 6212
6213 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6214}
6215
1afe3e9d
JB		 6216void intel_finish_page_flip(struct drm_device *dev, int pipe)
6217{
6218 drm_i915_private_t *dev_priv = dev->dev_private;
6219 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6220
49b14a5c 6221 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6222}
6223
6224void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6225{
6226 drm_i915_private_t *dev_priv = dev->dev_private;
6227 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6228
49b14a5c 6229 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6230}
6231
6b95a207
KH		 6232void intel_prepare_page_flip(struct drm_device *dev, int plane)
6233{
6234 drm_i915_private_t *dev_priv = dev->dev_private;
6235 struct intel_crtc *intel_crtc =
6236 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6237 unsigned long flags;
6238
6239 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6240 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6241 if ((++intel_crtc->unpin_work->pending) > 1)
6242 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6243 } else {
6244 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6245 }
6b95a207
KH		 6246 spin_unlock_irqrestore(&dev->event_lock, flags);
6247}
6248
8c9f3aaf
JB		 6249static int intel_gen2_queue_flip(struct drm_device *dev,
6250 struct drm_crtc *crtc,
6251 struct drm_framebuffer *fb,
6252 struct drm_i915_gem_object *obj)
6253{
6254 struct drm_i915_private *dev_priv = dev->dev_private;
6255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6256 u32 flip_mask;
6d90c952 6257 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6258 int ret;
6259
6d90c952 6260 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6261 if (ret)
83d4092b 6262 goto err;
8c9f3aaf 6263
6d90c952 6264 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6265 if (ret)
83d4092b 6266 goto err_unpin;
8c9f3aaf
JB		 6267
6268 /* Can't queue multiple flips, so wait for the previous
6269 * one to finish before executing the next.
6270 */
6271 if (intel_crtc->plane)
6272 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6273 else
6274 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6275 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6276 intel_ring_emit(ring, MI_NOOP);
6277 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6278 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6279 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6280 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6281 intel_ring_emit(ring, 0); /* aux display base address, unused */
6282 intel_ring_advance(ring);
83d4092b
CW		 6283 return 0;
6284
6285err_unpin:
6286 intel_unpin_fb_obj(obj);
6287err:
8c9f3aaf
JB		 6288 return ret;
6289}
6290
6291static int intel_gen3_queue_flip(struct drm_device *dev,
6292 struct drm_crtc *crtc,
6293 struct drm_framebuffer *fb,
6294 struct drm_i915_gem_object *obj)
6295{
6296 struct drm_i915_private *dev_priv = dev->dev_private;
6297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6298 u32 flip_mask;
6d90c952 6299 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6300 int ret;
6301
6d90c952 6302 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6303 if (ret)
83d4092b 6304 goto err;
8c9f3aaf 6305
6d90c952 6306 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6307 if (ret)
83d4092b 6308 goto err_unpin;
8c9f3aaf
JB		 6309
6310 if (intel_crtc->plane)
6311 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6312 else
6313 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6314 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6315 intel_ring_emit(ring, MI_NOOP);
6316 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6317 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6318 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6319 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6320 intel_ring_emit(ring, MI_NOOP);
6321
6322 intel_ring_advance(ring);
83d4092b
CW		 6323 return 0;
6324
6325err_unpin:
6326 intel_unpin_fb_obj(obj);
6327err:
8c9f3aaf
JB		 6328 return ret;
6329}
6330
6331static int intel_gen4_queue_flip(struct drm_device *dev,
6332 struct drm_crtc *crtc,
6333 struct drm_framebuffer *fb,
6334 struct drm_i915_gem_object *obj)
6335{
6336 struct drm_i915_private *dev_priv = dev->dev_private;
6337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6338 uint32_t pf, pipesrc;
6d90c952 6339 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6340 int ret;
6341
6d90c952 6342 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6343 if (ret)
83d4092b 6344 goto err;
8c9f3aaf 6345
6d90c952 6346 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6347 if (ret)
83d4092b 6348 goto err_unpin;
8c9f3aaf
JB		 6349
6350 /* i965+ uses the linear or tiled offsets from the
6351 * Display Registers (which do not change across a page-flip)
6352 * so we need only reprogram the base address.
6353 */
6d90c952
DV		 6354 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6355 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6356 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6357 intel_ring_emit(ring,
6358 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6359 obj->tiling_mode);
8c9f3aaf
JB		 6360
6361 /* XXX Enabling the panel-fitter across page-flip is so far
6362 * untested on non-native modes, so ignore it for now.
6363 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6364 */
6365 pf = 0;
6366 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6367 intel_ring_emit(ring, pf | pipesrc);
6368 intel_ring_advance(ring);
83d4092b
CW		 6369 return 0;
6370
6371err_unpin:
6372 intel_unpin_fb_obj(obj);
6373err:
8c9f3aaf
JB		 6374 return ret;
6375}
6376
6377static int intel_gen6_queue_flip(struct drm_device *dev,
6378 struct drm_crtc *crtc,
6379 struct drm_framebuffer *fb,
6380 struct drm_i915_gem_object *obj)
6381{
6382 struct drm_i915_private *dev_priv = dev->dev_private;
6383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6384 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6385 uint32_t pf, pipesrc;
6386 int ret;
6387
6d90c952 6388 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6389 if (ret)
83d4092b 6390 goto err;
8c9f3aaf 6391
6d90c952 6392 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6393 if (ret)
83d4092b 6394 goto err_unpin;
8c9f3aaf 6395
6d90c952
DV		 6396 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6397 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6398 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6399 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6400
dc257cf1
DV		 6401 /* Contrary to the suggestions in the documentation,
6402 * "Enable Panel Fitter" does not seem to be required when page
6403 * flipping with a non-native mode, and worse causes a normal
6404 * modeset to fail.
6405 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6406 */
6407 pf = 0;
8c9f3aaf 6408 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6409 intel_ring_emit(ring, pf | pipesrc);
6410 intel_ring_advance(ring);
83d4092b
CW		 6411 return 0;
6412
6413err_unpin:
6414 intel_unpin_fb_obj(obj);
6415err:
8c9f3aaf
JB		 6416 return ret;
6417}
6418
7c9017e5
JB		 6419/*
6420 * On gen7 we currently use the blit ring because (in early silicon at least)
6421 * the render ring doesn't give us interrpts for page flip completion, which
6422 * means clients will hang after the first flip is queued. Fortunately the
6423 * blit ring generates interrupts properly, so use it instead.
6424 */
6425static int intel_gen7_queue_flip(struct drm_device *dev,
6426 struct drm_crtc *crtc,
6427 struct drm_framebuffer *fb,
6428 struct drm_i915_gem_object *obj)
6429{
6430 struct drm_i915_private *dev_priv = dev->dev_private;
6431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6432 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6433 uint32_t plane_bit = 0;
7c9017e5
JB		 6434 int ret;
6435
6436 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6437 if (ret)
83d4092b 6438 goto err;
7c9017e5 6439
cb05d8de
DV		 6440 switch(intel_crtc->plane) {
6441 case PLANE_A:
6442 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6443 break;
6444 case PLANE_B:
6445 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6446 break;
6447 case PLANE_C:
6448 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6449 break;
6450 default:
6451 WARN_ONCE(1, "unknown plane in flip command\n");
6452 ret = -ENODEV;
ab3951eb 6453 goto err_unpin;
cb05d8de
DV		 6454 }
6455
7c9017e5
JB		 6456 ret = intel_ring_begin(ring, 4);
6457 if (ret)
83d4092b 6458 goto err_unpin;
7c9017e5 6459
cb05d8de 6460 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6461 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6462 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6463 intel_ring_emit(ring, (MI_NOOP));
6464 intel_ring_advance(ring);
83d4092b
CW		 6465 return 0;
6466
6467err_unpin:
6468 intel_unpin_fb_obj(obj);
6469err:
7c9017e5
JB		 6470 return ret;
6471}
6472
8c9f3aaf
JB		 6473static int intel_default_queue_flip(struct drm_device *dev,
6474 struct drm_crtc *crtc,
6475 struct drm_framebuffer *fb,
6476 struct drm_i915_gem_object *obj)
6477{
6478 return -ENODEV;
6479}
6480
6b95a207
KH		 6481static int intel_crtc_page_flip(struct drm_crtc *crtc,
6482 struct drm_framebuffer *fb,
6483 struct drm_pending_vblank_event *event)
6484{
6485 struct drm_device *dev = crtc->dev;
6486 struct drm_i915_private *dev_priv = dev->dev_private;
6487 struct intel_framebuffer *intel_fb;
05394f39 6488 struct drm_i915_gem_object *obj;
6b95a207
KH		 6489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6490 struct intel_unpin_work *work;
8c9f3aaf 6491 unsigned long flags;
52e68630 6492 int ret;
6b95a207 6493
e6a595d2
VS		 6494 /* Can't change pixel format via MI display flips. */
6495 if (fb->pixel_format != crtc->fb->pixel_format)
6496 return -EINVAL;
6497
6498 /*
6499 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6500 * Note that pitch changes could also affect these register.
6501 */
6502 if (INTEL_INFO(dev)->gen > 3 &&
6503 (fb->offsets[0] != crtc->fb->offsets[0] ||
6504 fb->pitches[0] != crtc->fb->pitches[0]))
6505 return -EINVAL;
6506
6b95a207
KH		 6507 work = kzalloc(sizeof *work, GFP_KERNEL);
6508 if (work == NULL)
6509 return -ENOMEM;
6510
6b95a207
KH		 6511 work->event = event;
6512 work->dev = crtc->dev;
6513 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6514 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6515 INIT_WORK(&work->work, intel_unpin_work_fn);
6516
7317c75e
JB		 6517 ret = drm_vblank_get(dev, intel_crtc->pipe);
6518 if (ret)
6519 goto free_work;
6520
6b95a207
KH		 6521 /* We borrow the event spin lock for protecting unpin_work */
6522 spin_lock_irqsave(&dev->event_lock, flags);
6523 if (intel_crtc->unpin_work) {
6524 spin_unlock_irqrestore(&dev->event_lock, flags);
6525 kfree(work);
7317c75e 6526 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6527
6528 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6529 return -EBUSY;
6530 }
6531 intel_crtc->unpin_work = work;
6532 spin_unlock_irqrestore(&dev->event_lock, flags);
6533
6534 intel_fb = to_intel_framebuffer(fb);
6535 obj = intel_fb->obj;
6536
79158103
CW		 6537 ret = i915_mutex_lock_interruptible(dev);
6538 if (ret)
6539 goto cleanup;
6b95a207 6540
75dfca80 6541 /* Reference the objects for the scheduled work. */
05394f39
CW		 6542 drm_gem_object_reference(&work->old_fb_obj->base);
6543 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6544
6545 crtc->fb = fb;
96b099fd 6546
e1f99ce6 6547 work->pending_flip_obj = obj;
e1f99ce6 6548
4e5359cd
SF		 6549 work->enable_stall_check = true;
6550
e1f99ce6
CW		 6551 /* Block clients from rendering to the new back buffer until
6552 * the flip occurs and the object is no longer visible.
6553 */
05394f39 6554 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6555
8c9f3aaf
JB		 6556 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6557 if (ret)
6558 goto cleanup_pending;
6b95a207 6559
7782de3b 6560 intel_disable_fbc(dev);
f047e395 6561 intel_mark_fb_busy(obj);
6b95a207
KH		 6562 mutex_unlock(&dev->struct_mutex);
6563
e5510fac
JB		 6564 trace_i915_flip_request(intel_crtc->plane, obj);
6565
6b95a207 6566 return 0;
96b099fd 6567
8c9f3aaf
JB		 6568cleanup_pending:
6569 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6570 drm_gem_object_unreference(&work->old_fb_obj->base);
6571 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6572 mutex_unlock(&dev->struct_mutex);
6573
79158103 6574cleanup:
96b099fd
CW		 6575 spin_lock_irqsave(&dev->event_lock, flags);
6576 intel_crtc->unpin_work = NULL;
6577 spin_unlock_irqrestore(&dev->event_lock, flags);
6578
7317c75e
JB		 6579 drm_vblank_put(dev, intel_crtc->pipe);
6580free_work:
96b099fd
CW		 6581 kfree(work);
6582
6583 return ret;
6b95a207
KH		 6584}
6585
f6e5b160 6586static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 6587 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6588 .load_lut = intel_crtc_load_lut,
976f8a20 6589 .disable = intel_crtc_noop,
f6e5b160
CW		 6590};
6591
6ed0f796
DV		 6592bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6593{
6594 struct intel_encoder *other_encoder;
6595 struct drm_crtc *crtc = &encoder->new_crtc->base;
6596
6597 if (WARN_ON(!crtc))
6598 return false;
6599
6600 list_for_each_entry(other_encoder,
6601 &crtc->dev->mode_config.encoder_list,
6602 base.head) {
6603
6604 if (&other_encoder->new_crtc->base != crtc ||
6605 encoder == other_encoder)
6606 continue;
6607 else
6608 return true;
6609 }
6610
6611 return false;
6612}
6613
50f56119
DV		 6614static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6615 struct drm_crtc *crtc)
6616{
6617 struct drm_device *dev;
6618 struct drm_crtc *tmp;
6619 int crtc_mask = 1;
6620
6621 WARN(!crtc, "checking null crtc?\n");
6622
6623 dev = crtc->dev;
6624
6625 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6626 if (tmp == crtc)
6627 break;
6628 crtc_mask <<= 1;
6629 }
6630
6631 if (encoder->possible_crtcs & crtc_mask)
6632 return true;
6633 return false;
6634}
6635
9a935856
DV		 6636/**
6637 * intel_modeset_update_staged_output_state
6638 *
6639 * Updates the staged output configuration state, e.g. after we've read out the
6640 * current hw state.
6641 */
6642static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6643{
6644 struct intel_encoder *encoder;
6645 struct intel_connector *connector;
6646
6647 list_for_each_entry(connector, &dev->mode_config.connector_list,
6648 base.head) {
6649 connector->new_encoder =
6650 to_intel_encoder(connector->base.encoder);
6651 }
6652
6653 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6654 base.head) {
6655 encoder->new_crtc =
6656 to_intel_crtc(encoder->base.crtc);
6657 }
6658}
6659
6660/**
6661 * intel_modeset_commit_output_state
6662 *
6663 * This function copies the stage display pipe configuration to the real one.
6664 */
6665static void intel_modeset_commit_output_state(struct drm_device *dev)
6666{
6667 struct intel_encoder *encoder;
6668 struct intel_connector *connector;
6669
6670 list_for_each_entry(connector, &dev->mode_config.connector_list,
6671 base.head) {
6672 connector->base.encoder = &connector->new_encoder->base;
6673 }
6674
6675 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6676 base.head) {
6677 encoder->base.crtc = &encoder->new_crtc->base;
6678 }
6679}
6680
7758a113
DV		 6681static struct drm_display_mode *
6682intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6683 struct drm_display_mode *mode)
6684{
6685 struct drm_device *dev = crtc->dev;
6686 struct drm_display_mode *adjusted_mode;
6687 struct drm_encoder_helper_funcs *encoder_funcs;
6688 struct intel_encoder *encoder;
6689
6690 adjusted_mode = drm_mode_duplicate(dev, mode);
6691 if (!adjusted_mode)
6692 return ERR_PTR(-ENOMEM);
6693
6694 /* Pass our mode to the connectors and the CRTC to give them a chance to
6695 * adjust it according to limitations or connector properties, and also
6696 * a chance to reject the mode entirely.
6697 */
6698 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6699 base.head) {
6700
6701 if (&encoder->new_crtc->base != crtc)
6702 continue;
6703 encoder_funcs = encoder->base.helper_private;
6704 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6705 adjusted_mode))) {
6706 DRM_DEBUG_KMS("Encoder fixup failed\n");
6707 goto fail;
6708 }
6709 }
6710
6711 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6712 DRM_DEBUG_KMS("CRTC fixup failed\n");
6713 goto fail;
6714 }
6715 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6716
6717 return adjusted_mode;
6718fail:
6719 drm_mode_destroy(dev, adjusted_mode);
6720 return ERR_PTR(-EINVAL);
6721}
6722
e2e1ed41
DV		 6723/* Computes which crtcs are affected and sets the relevant bits in the mask. For
6724 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6725static void
6726intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6727 unsigned *prepare_pipes, unsigned *disable_pipes)
6728{
6729 struct intel_crtc *intel_crtc;
6730 struct drm_device *dev = crtc->dev;
6731 struct intel_encoder *encoder;
6732 struct intel_connector *connector;
6733 struct drm_crtc *tmp_crtc;
6734
6735 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
6736
6737 /* Check which crtcs have changed outputs connected to them, these need
6738 * to be part of the prepare_pipes mask. We don't (yet) support global
6739 * modeset across multiple crtcs, so modeset_pipes will only have one
6740 * bit set at most. */
6741 list_for_each_entry(connector, &dev->mode_config.connector_list,
6742 base.head) {
6743 if (connector->base.encoder == &connector->new_encoder->base)
6744 continue;
6745
6746 if (connector->base.encoder) {
6747 tmp_crtc = connector->base.encoder->crtc;
6748
6749 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6750 }
6751
6752 if (connector->new_encoder)
6753 *prepare_pipes |=
6754 1 << connector->new_encoder->new_crtc->pipe;
6755 }
6756
6757 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6758 base.head) {
6759 if (encoder->base.crtc == &encoder->new_crtc->base)
6760 continue;
6761
6762 if (encoder->base.crtc) {
6763 tmp_crtc = encoder->base.crtc;
6764
6765 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6766 }
6767
6768 if (encoder->new_crtc)
6769 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
6770 }
6771
6772 /* Check for any pipes that will be fully disabled ... */
6773 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6774 base.head) {
6775 bool used = false;
6776
6777 /* Don't try to disable disabled crtcs. */
6778 if (!intel_crtc->base.enabled)
6779 continue;
6780
6781 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6782 base.head) {
6783 if (encoder->new_crtc == intel_crtc)
6784 used = true;
6785 }
6786
6787 if (!used)
6788 *disable_pipes |= 1 << intel_crtc->pipe;
6789 }
6790
6791
6792 /* set_mode is also used to update properties on life display pipes. */
6793 intel_crtc = to_intel_crtc(crtc);
6794 if (crtc->enabled)
6795 *prepare_pipes |= 1 << intel_crtc->pipe;
6796
6797 /* We only support modeset on one single crtc, hence we need to do that
6798 * only for the passed in crtc iff we change anything else than just
6799 * disable crtcs.
6800 *
6801 * This is actually not true, to be fully compatible with the old crtc
6802 * helper we automatically disable _any_ output (i.e. doesn't need to be
6803 * connected to the crtc we're modesetting on) if it's disconnected.
6804 * Which is a rather nutty api (since changed the output configuration
6805 * without userspace's explicit request can lead to confusion), but
6806 * alas. Hence we currently need to modeset on all pipes we prepare. */
6807 if (*prepare_pipes)
6808 *modeset_pipes = *prepare_pipes;
6809
6810 /* ... and mask these out. */
6811 *modeset_pipes &= ~(*disable_pipes);
6812 *prepare_pipes &= ~(*disable_pipes);
6813}
6814
ea9d758d
DV		 6815static bool intel_crtc_in_use(struct drm_crtc *crtc)
6816{
6817 struct drm_encoder *encoder;
6818 struct drm_device *dev = crtc->dev;
6819
6820 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
6821 if (encoder->crtc == crtc)
6822 return true;
6823
6824 return false;
6825}
6826
6827static void
6828intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
6829{
6830 struct intel_encoder *intel_encoder;
6831 struct intel_crtc *intel_crtc;
6832 struct drm_connector *connector;
6833
6834 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
6835 base.head) {
6836 if (!intel_encoder->base.crtc)
6837 continue;
6838
6839 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
6840
6841 if (prepare_pipes & (1 << intel_crtc->pipe))
6842 intel_encoder->connectors_active = false;
6843 }
6844
6845 intel_modeset_commit_output_state(dev);
6846
6847 /* Update computed state. */
6848 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6849 base.head) {
6850 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
6851 }
6852
6853 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6854 if (!connector->encoder || !connector->encoder->crtc)
6855 continue;
6856
6857 intel_crtc = to_intel_crtc(connector->encoder->crtc);
6858
6859 if (prepare_pipes & (1 << intel_crtc->pipe)) {
6860 connector->dpms = DRM_MODE_DPMS_ON;
6861
6862 intel_encoder = to_intel_encoder(connector->encoder);
6863 intel_encoder->connectors_active = true;
6864 }
6865 }
6866
6867}
6868
25c5b266
DV		 6869#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6870 list_for_each_entry((intel_crtc), \
6871 &(dev)->mode_config.crtc_list, \
6872 base.head) \
6873 if (mask & (1 <<(intel_crtc)->pipe)) \
6874
a6778b3c
DV		 6875bool intel_set_mode(struct drm_crtc *crtc,
6876 struct drm_display_mode *mode,
94352cf9 6877 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 6878{
6879 struct drm_device *dev = crtc->dev;
dbf2b54e 6880 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 6881 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c 6882 struct drm_encoder_helper_funcs *encoder_funcs;
a6778b3c 6883 struct drm_encoder *encoder;
25c5b266
DV		 6884 struct intel_crtc *intel_crtc;
6885 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 6886 bool ret = true;
6887
e2e1ed41 6888 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 6889 &prepare_pipes, &disable_pipes);
6890
6891 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
6892 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 6893
976f8a20
DV		 6894 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
6895 intel_crtc_disable(&intel_crtc->base);
87f1faa6 6896
a6778b3c
DV		 6897 saved_hwmode = crtc->hwmode;
6898 saved_mode = crtc->mode;
a6778b3c 6899
25c5b266
DV		 6900 /* Hack: Because we don't (yet) support global modeset on multiple
6901 * crtcs, we don't keep track of the new mode for more than one crtc.
6902 * Hence simply check whether any bit is set in modeset_pipes in all the
6903 * pieces of code that are not yet converted to deal with mutliple crtcs
6904 * changing their mode at the same time. */
6905 adjusted_mode = NULL;
6906 if (modeset_pipes) {
6907 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
6908 if (IS_ERR(adjusted_mode)) {
6909 return false;
6910 }
25c5b266 6911 }
a6778b3c 6912
ea9d758d
DV		 6913 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
6914 if (intel_crtc->base.enabled)
6915 dev_priv->display.crtc_disable(&intel_crtc->base);
6916 }
a6778b3c 6917
25c5b266
DV		 6918 if (modeset_pipes) {
6919 crtc->mode = *mode;
6920 crtc->x = x;
6921 crtc->y = y;
6922 }
7758a113 6923
ea9d758d
DV		 6924 /* Only after disabling all output pipelines that will be changed can we
6925 * update the the output configuration. */
6926 intel_modeset_update_state(dev, prepare_pipes);
6927
a6778b3c
DV		 6928 /* Set up the DPLL and any encoders state that needs to adjust or depend
6929 * on the DPLL.
6930 */
25c5b266
DV		 6931 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
6932 ret = !intel_crtc_mode_set(&intel_crtc->base,
6933 mode, adjusted_mode,
6934 x, y, fb);
6935 if (!ret)
6936 goto done;
a6778b3c 6937
25c5b266 6938 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
a6778b3c 6939
25c5b266
DV		 6940 if (encoder->crtc != &intel_crtc->base)
6941 continue;
a6778b3c 6942
25c5b266
DV		 6943 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6944 encoder->base.id, drm_get_encoder_name(encoder),
6945 mode->base.id, mode->name);
6946 encoder_funcs = encoder->helper_private;
6947 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
6948 }
a6778b3c
DV		 6949 }
6950
6951 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 6952 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
6953 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 6954
25c5b266
DV		 6955 if (modeset_pipes) {
6956 /* Store real post-adjustment hardware mode. */
6957 crtc->hwmode = *adjusted_mode;
a6778b3c 6958
25c5b266
DV		 6959 /* Calculate and store various constants which
6960 * are later needed by vblank and swap-completion
6961 * timestamping. They are derived from true hwmode.
6962 */
6963 drm_calc_timestamping_constants(crtc);
6964 }
a6778b3c
DV		 6965
6966 /* FIXME: add subpixel order */
6967done:
6968 drm_mode_destroy(dev, adjusted_mode);
25c5b266 6969 if (!ret && crtc->enabled) {
a6778b3c
DV		 6970 crtc->hwmode = saved_hwmode;
6971 crtc->mode = saved_mode;
a6778b3c
DV		 6972 }
6973
6974 return ret;
6975}
6976
25c5b266
DV		 6977#undef for_each_intel_crtc_masked
6978
d9e55608
DV		 6979static void intel_set_config_free(struct intel_set_config *config)
6980{
6981 if (!config)
6982 return;
6983
1aa4b628
DV		 6984 kfree(config->save_connector_encoders);
6985 kfree(config->save_encoder_crtcs);
d9e55608
DV		 6986 kfree(config);
6987}
6988
85f9eb71
DV		 6989static int intel_set_config_save_state(struct drm_device *dev,
6990 struct intel_set_config *config)
6991{
85f9eb71
DV		 6992 struct drm_encoder *encoder;
6993 struct drm_connector *connector;
6994 int count;
6995
1aa4b628
DV		 6996 config->save_encoder_crtcs =
6997 kcalloc(dev->mode_config.num_encoder,
6998 sizeof(struct drm_crtc *), GFP_KERNEL);
6999 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7000 return -ENOMEM;
7001
1aa4b628
DV		 7002 config->save_connector_encoders =
7003 kcalloc(dev->mode_config.num_connector,
7004 sizeof(struct drm_encoder *), GFP_KERNEL);
7005 if (!config->save_connector_encoders)
85f9eb71
DV		 7006 return -ENOMEM;
7007
7008 /* Copy data. Note that driver private data is not affected.
7009 * Should anything bad happen only the expected state is
7010 * restored, not the drivers personal bookkeeping.
7011 */
85f9eb71
DV		 7012 count = 0;
7013 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7014 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7015 }
7016
7017 count = 0;
7018 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7019 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7020 }
7021
7022 return 0;
7023}
7024
7025static void intel_set_config_restore_state(struct drm_device *dev,
7026 struct intel_set_config *config)
7027{
9a935856
DV		 7028 struct intel_encoder *encoder;
7029 struct intel_connector *connector;
85f9eb71
DV		 7030 int count;
7031
85f9eb71 7032 count = 0;
9a935856
DV		 7033 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7034 encoder->new_crtc =
7035 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7036 }
7037
7038 count = 0;
9a935856
DV		 7039 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7040 connector->new_encoder =
7041 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7042 }
7043}
7044
5e2b584e
DV		 7045static void
7046intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7047 struct intel_set_config *config)
7048{
7049
7050 /* We should be able to check here if the fb has the same properties
7051 * and then just flip_or_move it */
7052 if (set->crtc->fb != set->fb) {
7053 /* If we have no fb then treat it as a full mode set */
7054 if (set->crtc->fb == NULL) {
7055 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7056 config->mode_changed = true;
7057 } else if (set->fb == NULL) {
7058 config->mode_changed = true;
7059 } else if (set->fb->depth != set->crtc->fb->depth) {
7060 config->mode_changed = true;
7061 } else if (set->fb->bits_per_pixel !=
7062 set->crtc->fb->bits_per_pixel) {
7063 config->mode_changed = true;
7064 } else
7065 config->fb_changed = true;
7066 }
7067
835c5873 7068 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7069 config->fb_changed = true;
7070
7071 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7072 DRM_DEBUG_KMS("modes are different, full mode set\n");
7073 drm_mode_debug_printmodeline(&set->crtc->mode);
7074 drm_mode_debug_printmodeline(set->mode);
7075 config->mode_changed = true;
7076 }
7077}
7078
2e431051 7079static int
9a935856
DV		 7080intel_modeset_stage_output_state(struct drm_device *dev,
7081 struct drm_mode_set *set,
7082 struct intel_set_config *config)
50f56119 7083{
85f9eb71 7084 struct drm_crtc *new_crtc;
9a935856
DV		 7085 struct intel_connector *connector;
7086 struct intel_encoder *encoder;
2e431051 7087 int count, ro;
50f56119 7088
9a935856
DV		 7089 /* The upper layers ensure that we either disabl a crtc or have a list
7090 * of connectors. For paranoia, double-check this. */
7091 WARN_ON(!set->fb && (set->num_connectors != 0));
7092 WARN_ON(set->fb && (set->num_connectors == 0));
7093
50f56119 7094 count = 0;
9a935856
DV		 7095 list_for_each_entry(connector, &dev->mode_config.connector_list,
7096 base.head) {
7097 /* Otherwise traverse passed in connector list and get encoders
7098 * for them. */
50f56119 7099 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7100 if (set->connectors[ro] == &connector->base) {
7101 connector->new_encoder = connector->encoder;
50f56119
DV		 7102 break;
7103 }
7104 }
7105
9a935856
DV		 7106 /* If we disable the crtc, disable all its connectors. Also, if
7107 * the connector is on the changing crtc but not on the new
7108 * connector list, disable it. */
7109 if ((!set->fb || ro == set->num_connectors) &&
7110 connector->base.encoder &&
7111 connector->base.encoder->crtc == set->crtc) {
7112 connector->new_encoder = NULL;
7113
7114 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7115 connector->base.base.id,
7116 drm_get_connector_name(&connector->base));
7117 }
7118
7119
7120 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7121 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7122 config->mode_changed = true;
50f56119 7123 }
9a935856
DV		 7124
7125 /* Disable all disconnected encoders. */
7126 if (connector->base.status == connector_status_disconnected)
7127 connector->new_encoder = NULL;
50f56119 7128 }
9a935856 7129 /* connector->new_encoder is now updated for all connectors. */
50f56119 7130
9a935856 7131 /* Update crtc of enabled connectors. */
50f56119 7132 count = 0;
9a935856
DV		 7133 list_for_each_entry(connector, &dev->mode_config.connector_list,
7134 base.head) {
7135 if (!connector->new_encoder)
50f56119
DV		 7136 continue;
7137
9a935856 7138 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7139
7140 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7141 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7142 new_crtc = set->crtc;
7143 }
7144
7145 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7146 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7147 new_crtc)) {
5e2b584e 7148 return -EINVAL;
50f56119 7149 }
9a935856
DV		 7150 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7151
7152 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7153 connector->base.base.id,
7154 drm_get_connector_name(&connector->base),
7155 new_crtc->base.id);
7156 }
7157
7158 /* Check for any encoders that needs to be disabled. */
7159 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7160 base.head) {
7161 list_for_each_entry(connector,
7162 &dev->mode_config.connector_list,
7163 base.head) {
7164 if (connector->new_encoder == encoder) {
7165 WARN_ON(!connector->new_encoder->new_crtc);
7166
7167 goto next_encoder;
7168 }
7169 }
7170 encoder->new_crtc = NULL;
7171next_encoder:
7172 /* Only now check for crtc changes so we don't miss encoders
7173 * that will be disabled. */
7174 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7175 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7176 config->mode_changed = true;
50f56119
DV		 7177 }
7178 }
9a935856 7179 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7180
2e431051
DV		 7181 return 0;
7182}
7183
7184static int intel_crtc_set_config(struct drm_mode_set *set)
7185{
7186 struct drm_device *dev;
2e431051
DV		 7187 struct drm_mode_set save_set;
7188 struct intel_set_config *config;
7189 int ret;
7190 int i;
7191
8d3e375e
DV		 7192 BUG_ON(!set);
7193 BUG_ON(!set->crtc);
7194 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7195
7196 if (!set->mode)
7197 set->fb = NULL;
7198
431e50f7
DV		 7199 /* The fb helper likes to play gross jokes with ->mode_set_config.
7200 * Unfortunately the crtc helper doesn't do much at all for this case,
7201 * so we have to cope with this madness until the fb helper is fixed up. */
7202 if (set->fb && set->num_connectors == 0)
7203 return 0;
7204
2e431051
DV		 7205 if (set->fb) {
7206 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7207 set->crtc->base.id, set->fb->base.id,
7208 (int)set->num_connectors, set->x, set->y);
7209 } else {
7210 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7211 }
7212
7213 dev = set->crtc->dev;
7214
7215 ret = -ENOMEM;
7216 config = kzalloc(sizeof(*config), GFP_KERNEL);
7217 if (!config)
7218 goto out_config;
7219
7220 ret = intel_set_config_save_state(dev, config);
7221 if (ret)
7222 goto out_config;
7223
7224 save_set.crtc = set->crtc;
7225 save_set.mode = &set->crtc->mode;
7226 save_set.x = set->crtc->x;
7227 save_set.y = set->crtc->y;
7228 save_set.fb = set->crtc->fb;
7229
7230 /* Compute whether we need a full modeset, only an fb base update or no
7231 * change at all. In the future we might also check whether only the
7232 * mode changed, e.g. for LVDS where we only change the panel fitter in
7233 * such cases. */
7234 intel_set_config_compute_mode_changes(set, config);
7235
9a935856 7236 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7237 if (ret)
7238 goto fail;
7239
5e2b584e 7240 if (config->mode_changed) {
87f1faa6 7241 if (set->mode) {
50f56119
DV		 7242 DRM_DEBUG_KMS("attempting to set mode from"
7243 " userspace\n");
7244 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7245 }
7246
7247 if (!intel_set_mode(set->crtc, set->mode,
7248 set->x, set->y, set->fb)) {
7249 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7250 set->crtc->base.id);
7251 ret = -EINVAL;
7252 goto fail;
7253 }
7254
7255 if (set->crtc->enabled) {
50f56119
DV		 7256 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
7257 for (i = 0; i < set->num_connectors; i++) {
7258 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
7259 drm_get_connector_name(set->connectors[i]));
7260 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
7261 }
7262 }
5e2b584e 7263 } else if (config->fb_changed) {
4f660f49 7264 ret = intel_pipe_set_base(set->crtc,
94352cf9 7265 set->x, set->y, set->fb);
50f56119
DV		 7266 }
7267
d9e55608
DV		 7268 intel_set_config_free(config);
7269
50f56119
DV		 7270 return 0;
7271
7272fail:
85f9eb71 7273 intel_set_config_restore_state(dev, config);
50f56119
DV		 7274
7275 /* Try to restore the config */
5e2b584e 7276 if (config->mode_changed &&
a6778b3c
DV		 7277 !intel_set_mode(save_set.crtc, save_set.mode,
7278 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 7279 DRM_ERROR("failed to restore config after modeset failure\n");
7280
d9e55608
DV		 7281out_config:
7282 intel_set_config_free(config);
50f56119
DV		 7283 return ret;
7284}
7285
f6e5b160 7286static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7287 .cursor_set = intel_crtc_cursor_set,
7288 .cursor_move = intel_crtc_cursor_move,
7289 .gamma_set = intel_crtc_gamma_set,
50f56119 7290 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7291 .destroy = intel_crtc_destroy,
7292 .page_flip = intel_crtc_page_flip,
7293};
7294
ee7b9f93
JB		 7295static void intel_pch_pll_init(struct drm_device *dev)
7296{
7297 drm_i915_private_t *dev_priv = dev->dev_private;
7298 int i;
7299
7300 if (dev_priv->num_pch_pll == 0) {
7301 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7302 return;
7303 }
7304
7305 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7306 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7307 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7308 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7309 }
7310}
7311
b358d0a6 7312static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7313{
22fd0fab 7314 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7315 struct intel_crtc *intel_crtc;
7316 int i;
7317
7318 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7319 if (intel_crtc == NULL)
7320 return;
7321
7322 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7323
7324 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7325 for (i = 0; i < 256; i++) {
7326 intel_crtc->lut_r[i] = i;
7327 intel_crtc->lut_g[i] = i;
7328 intel_crtc->lut_b[i] = i;
7329 }
7330
80824003
JB		 7331 /* Swap pipes & planes for FBC on pre-965 */
7332 intel_crtc->pipe = pipe;
7333 intel_crtc->plane = pipe;
e2e767ab 7334 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7335 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7336 intel_crtc->plane = !pipe;
80824003
JB		 7337 }
7338
22fd0fab
JB		 7339 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7340 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7341 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7342 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7343
5a354204 7344 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7345
79e53945 7346 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7347}
7348
08d7b3d1 7349int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7350 struct drm_file *file)
08d7b3d1 7351{
08d7b3d1 7352 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7353 struct drm_mode_object *drmmode_obj;
7354 struct intel_crtc *crtc;
08d7b3d1 7355
1cff8f6b
DV		 7356 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7357 return -ENODEV;
08d7b3d1 7358
c05422d5
DV		 7359 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7360 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7361
c05422d5 7362 if (!drmmode_obj) {
08d7b3d1
CW		 7363 DRM_ERROR("no such CRTC id\n");
7364 return -EINVAL;
7365 }
7366
c05422d5
DV		 7367 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7368 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7369
c05422d5 7370 return 0;
08d7b3d1
CW		 7371}
7372
66a9278e 7373static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7374{
66a9278e
DV		 7375 struct drm_device *dev = encoder->base.dev;
7376 struct intel_encoder *source_encoder;
79e53945 7377 int index_mask = 0;
79e53945
JB		 7378 int entry = 0;
7379
66a9278e
DV		 7380 list_for_each_entry(source_encoder,
7381 &dev->mode_config.encoder_list, base.head) {
7382
7383 if (encoder == source_encoder)
79e53945 7384 index_mask |= (1 << entry);
66a9278e
DV		 7385
7386 /* Intel hw has only one MUX where enocoders could be cloned. */
7387 if (encoder->cloneable && source_encoder->cloneable)
7388 index_mask |= (1 << entry);
7389
79e53945
JB		 7390 entry++;
7391 }
4ef69c7a 7392
79e53945
JB		 7393 return index_mask;
7394}
7395
4d302442
CW		 7396static bool has_edp_a(struct drm_device *dev)
7397{
7398 struct drm_i915_private *dev_priv = dev->dev_private;
7399
7400 if (!IS_MOBILE(dev))
7401 return false;
7402
7403 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7404 return false;
7405
7406 if (IS_GEN5(dev) &&
7407 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7408 return false;
7409
7410 return true;
7411}
7412
79e53945
JB		 7413static void intel_setup_outputs(struct drm_device *dev)
7414{
725e30ad 7415 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7416 struct intel_encoder *encoder;
cb0953d7 7417 bool dpd_is_edp = false;
f3cfcba6 7418 bool has_lvds;
79e53945 7419
f3cfcba6 7420 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7421 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7422 /* disable the panel fitter on everything but LVDS */
7423 I915_WRITE(PFIT_CONTROL, 0);
7424 }
79e53945 7425
bad720ff 7426 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7427 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7428
4d302442 7429 if (has_edp_a(dev))
ab9d7c30 7430 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 7431
cb0953d7 7432 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7433 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 7434 }
7435
7436 intel_crt_init(dev);
7437
0e72a5b5
ED		 7438 if (IS_HASWELL(dev)) {
7439 int found;
7440
7441 /* Haswell uses DDI functions to detect digital outputs */
7442 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7443 /* DDI A only supports eDP */
7444 if (found)
7445 intel_ddi_init(dev, PORT_A);
7446
7447 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7448 * register */
7449 found = I915_READ(SFUSE_STRAP);
7450
7451 if (found & SFUSE_STRAP_DDIB_DETECTED)
7452 intel_ddi_init(dev, PORT_B);
7453 if (found & SFUSE_STRAP_DDIC_DETECTED)
7454 intel_ddi_init(dev, PORT_C);
7455 if (found & SFUSE_STRAP_DDID_DETECTED)
7456 intel_ddi_init(dev, PORT_D);
7457 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 7458 int found;
7459
30ad48b7 7460 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 7461 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 7462 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 7463 if (!found)
08d644ad 7464 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 7465 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 7466 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 7467 }
7468
7469 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 7470 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 7471
b708a1d5 7472 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 7473 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 7474
5eb08b69 7475 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 7476 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 7477
cb0953d7 7478 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7479 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 7480 } else if (IS_VALLEYVIEW(dev)) {
7481 int found;
7482
7483 if (I915_READ(SDVOB) & PORT_DETECTED) {
7484 /* SDVOB multiplex with HDMIB */
7485 found = intel_sdvo_init(dev, SDVOB, true);
7486 if (!found)
08d644ad 7487 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 7488 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 7489 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 7490 }
7491
7492 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 7493 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 7494
4a87d65d
JB		 7495 /* Shares lanes with HDMI on SDVOC */
7496 if (I915_READ(DP_C) & DP_DETECTED)
ab9d7c30 7497 intel_dp_init(dev, DP_C, PORT_C);
103a196f 7498 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7499 bool found = false;
7d57382e 7500
725e30ad 7501 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7502 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 7503 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 7504 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7505 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 7506 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 7507 }
27185ae1 7508
b01f2c3a
JB		 7509 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7510 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 7511 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 7512 }
725e30ad 7513 }
13520b05
KH		 7514
7515 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7516
b01f2c3a
JB		 7517 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7518 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 7519 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 7520 }
27185ae1
ML		 7521
7522 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7523
b01f2c3a
JB		 7524 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7525 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 7526 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 7527 }
7528 if (SUPPORTS_INTEGRATED_DP(dev)) {
7529 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 7530 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 7531 }
725e30ad 7532 }
27185ae1 7533
b01f2c3a
JB		 7534 if (SUPPORTS_INTEGRATED_DP(dev) &&
7535 (I915_READ(DP_D) & DP_DETECTED)) {
7536 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 7537 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 7538 }
bad720ff 7539 } else if (IS_GEN2(dev))
79e53945
JB		 7540 intel_dvo_init(dev);
7541
103a196f 7542 if (SUPPORTS_TV(dev))
79e53945
JB		 7543 intel_tv_init(dev);
7544
4ef69c7a
CW		 7545 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7546 encoder->base.possible_crtcs = encoder->crtc_mask;
7547 encoder->base.possible_clones =
66a9278e 7548 intel_encoder_clones(encoder);
79e53945 7549 }
47356eb6 7550
40579abe 7551 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 7552 ironlake_init_pch_refclk(dev);
79e53945
JB		 7553}
7554
7555static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7556{
7557 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7558
7559 drm_framebuffer_cleanup(fb);
05394f39 7560 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7561
7562 kfree(intel_fb);
7563}
7564
7565static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7566 struct drm_file *file,
79e53945
JB		 7567 unsigned int *handle)
7568{
7569 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7570 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7571
05394f39 7572 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7573}
7574
7575static const struct drm_framebuffer_funcs intel_fb_funcs = {
7576 .destroy = intel_user_framebuffer_destroy,
7577 .create_handle = intel_user_framebuffer_create_handle,
7578};
7579
38651674
DA		 7580int intel_framebuffer_init(struct drm_device *dev,
7581 struct intel_framebuffer *intel_fb,
308e5bcb 7582 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7583 struct drm_i915_gem_object *obj)
79e53945 7584{
79e53945
JB		 7585 int ret;
7586
05394f39 7587 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7588 return -EINVAL;
7589
308e5bcb 7590 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7591 return -EINVAL;
7592
308e5bcb 7593 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7594 case DRM_FORMAT_RGB332:
7595 case DRM_FORMAT_RGB565:
7596 case DRM_FORMAT_XRGB8888:
b250da79 7597 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 7598 case DRM_FORMAT_ARGB8888:
7599 case DRM_FORMAT_XRGB2101010:
7600 case DRM_FORMAT_ARGB2101010:
308e5bcb 7601 /* RGB formats are common across chipsets */
b5626747 7602 break;
04b3924d
VS		 7603 case DRM_FORMAT_YUYV:
7604 case DRM_FORMAT_UYVY:
7605 case DRM_FORMAT_YVYU:
7606 case DRM_FORMAT_VYUY:
57cd6508
CW		 7607 break;
7608 default:
aca25848
ED		 7609 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7610 mode_cmd->pixel_format);
57cd6508
CW		 7611 return -EINVAL;
7612 }
7613
79e53945
JB		 7614 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7615 if (ret) {
7616 DRM_ERROR("framebuffer init failed %d\n", ret);
7617 return ret;
7618 }
7619
7620 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7621 intel_fb->obj = obj;
79e53945
JB		 7622 return 0;
7623}
7624
79e53945
JB		 7625static struct drm_framebuffer *
7626intel_user_framebuffer_create(struct drm_device *dev,
7627 struct drm_file *filp,
308e5bcb 7628 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7629{
05394f39 7630 struct drm_i915_gem_object *obj;
79e53945 7631
308e5bcb
JB		 7632 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7633 mode_cmd->handles[0]));
c8725226 7634 if (&obj->base == NULL)
cce13ff7 7635 return ERR_PTR(-ENOENT);
79e53945 7636
d2dff872 7637 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7638}
7639
79e53945 7640static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7641 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7642 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7643};
7644
e70236a8
JB		 7645/* Set up chip specific display functions */
7646static void intel_init_display(struct drm_device *dev)
7647{
7648 struct drm_i915_private *dev_priv = dev->dev_private;
7649
7650 /* We always want a DPMS function */
f564048e 7651 if (HAS_PCH_SPLIT(dev)) {
f564048e 7652 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 7653 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7654 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 7655 dev_priv->display.off = ironlake_crtc_off;
17638cd6 7656 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7657 } else {
f564048e 7658 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 7659 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7660 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 7661 dev_priv->display.off = i9xx_crtc_off;
17638cd6 7662 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7663 }
e70236a8 7664
e70236a8 7665 /* Returns the core display clock speed */
25eb05fc
JB		 7666 if (IS_VALLEYVIEW(dev))
7667 dev_priv->display.get_display_clock_speed =
7668 valleyview_get_display_clock_speed;
7669 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 7670 dev_priv->display.get_display_clock_speed =
7671 i945_get_display_clock_speed;
7672 else if (IS_I915G(dev))
7673 dev_priv->display.get_display_clock_speed =
7674 i915_get_display_clock_speed;
f2b115e6 7675 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7676 dev_priv->display.get_display_clock_speed =
7677 i9xx_misc_get_display_clock_speed;
7678 else if (IS_I915GM(dev))
7679 dev_priv->display.get_display_clock_speed =
7680 i915gm_get_display_clock_speed;
7681 else if (IS_I865G(dev))
7682 dev_priv->display.get_display_clock_speed =
7683 i865_get_display_clock_speed;
f0f8a9ce 7684 else if (IS_I85X(dev))
e70236a8
JB		 7685 dev_priv->display.get_display_clock_speed =
7686 i855_get_display_clock_speed;
7687 else /* 852, 830 */
7688 dev_priv->display.get_display_clock_speed =
7689 i830_get_display_clock_speed;
7690
7f8a8569 7691 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7692 if (IS_GEN5(dev)) {
674cf967 7693 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7694 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7695 } else if (IS_GEN6(dev)) {
674cf967 7696 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7697 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7698 } else if (IS_IVYBRIDGE(dev)) {
7699 /* FIXME: detect B0+ stepping and use auto training */
7700 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7701 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7702 } else if (IS_HASWELL(dev)) {
7703 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 7704 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 7705 } else
7706 dev_priv->display.update_wm = NULL;
6067aaea 7707 } else if (IS_G4X(dev)) {
e0dac65e 7708 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7709 }
8c9f3aaf
JB		 7710
7711 /* Default just returns -ENODEV to indicate unsupported */
7712 dev_priv->display.queue_flip = intel_default_queue_flip;
7713
7714 switch (INTEL_INFO(dev)->gen) {
7715 case 2:
7716 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7717 break;
7718
7719 case 3:
7720 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7721 break;
7722
7723 case 4:
7724 case 5:
7725 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7726 break;
7727
7728 case 6:
7729 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7730 break;
7c9017e5
JB		 7731 case 7:
7732 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7733 break;
8c9f3aaf 7734 }
e70236a8
JB		 7735}
7736
b690e96c
JB		 7737/*
7738 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7739 * resume, or other times. This quirk makes sure that's the case for
7740 * affected systems.
7741 */
0206e353 7742static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7743{
7744 struct drm_i915_private *dev_priv = dev->dev_private;
7745
7746 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7747 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7748}
7749
435793df
KP		 7750/*
7751 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7752 */
7753static void quirk_ssc_force_disable(struct drm_device *dev)
7754{
7755 struct drm_i915_private *dev_priv = dev->dev_private;
7756 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7757 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7758}
7759
4dca20ef 7760/*
5a15ab5b
CE		 7761 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7762 * brightness value
4dca20ef
CE		 7763 */
7764static void quirk_invert_brightness(struct drm_device *dev)
7765{
7766 struct drm_i915_private *dev_priv = dev->dev_private;
7767 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7768 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7769}
7770
b690e96c
JB		 7771struct intel_quirk {
7772 int device;
7773 int subsystem_vendor;
7774 int subsystem_device;
7775 void (*hook)(struct drm_device *dev);
7776};
7777
c43b5634 7778static struct intel_quirk intel_quirks[] = {
b690e96c 7779 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7780 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 7781
b690e96c
JB		 7782 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7783 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7784
b690e96c
JB		 7785 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7786 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7787
7788 /* 855 & before need to leave pipe A & dpll A up */
7789 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7790 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 7791 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7792
7793 /* Lenovo U160 cannot use SSC on LVDS */
7794 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7795
7796 /* Sony Vaio Y cannot use SSC on LVDS */
7797 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7798
7799 /* Acer Aspire 5734Z must invert backlight brightness */
7800 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7801};
7802
7803static void intel_init_quirks(struct drm_device *dev)
7804{
7805 struct pci_dev *d = dev->pdev;
7806 int i;
7807
7808 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7809 struct intel_quirk *q = &intel_quirks[i];
7810
7811 if (d->device == q->device &&
7812 (d->subsystem_vendor == q->subsystem_vendor ||
7813 q->subsystem_vendor == PCI_ANY_ID) &&
7814 (d->subsystem_device == q->subsystem_device ||
7815 q->subsystem_device == PCI_ANY_ID))
7816 q->hook(dev);
7817 }
7818}
7819
9cce37f4
JB		 7820/* Disable the VGA plane that we never use */
7821static void i915_disable_vga(struct drm_device *dev)
7822{
7823 struct drm_i915_private *dev_priv = dev->dev_private;
7824 u8 sr1;
7825 u32 vga_reg;
7826
7827 if (HAS_PCH_SPLIT(dev))
7828 vga_reg = CPU_VGACNTRL;
7829 else
7830 vga_reg = VGACNTRL;
7831
7832 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 7833 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 7834 sr1 = inb(VGA_SR_DATA);
7835 outb(sr1 | 1<<5, VGA_SR_DATA);
7836 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7837 udelay(300);
7838
7839 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7840 POSTING_READ(vga_reg);
7841}
7842
f817586c
DV		 7843void intel_modeset_init_hw(struct drm_device *dev)
7844{
0232e927
ED		 7845 /* We attempt to init the necessary power wells early in the initialization
7846 * time, so the subsystems that expect power to be enabled can work.
7847 */
7848 intel_init_power_wells(dev);
7849
a8f78b58
ED		 7850 intel_prepare_ddi(dev);
7851
f817586c
DV		 7852 intel_init_clock_gating(dev);
7853
79f5b2c7 7854 mutex_lock(&dev->struct_mutex);
8090c6b9 7855 intel_enable_gt_powersave(dev);
79f5b2c7 7856 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 7857}
7858
79e53945
JB		 7859void intel_modeset_init(struct drm_device *dev)
7860{
652c393a 7861 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 7862 int i, ret;
79e53945
JB		 7863
7864 drm_mode_config_init(dev);
7865
7866 dev->mode_config.min_width = 0;
7867 dev->mode_config.min_height = 0;
7868
019d96cb
DA		 7869 dev->mode_config.preferred_depth = 24;
7870 dev->mode_config.prefer_shadow = 1;
7871
e6ecefaa 7872 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 7873
b690e96c
JB		 7874 intel_init_quirks(dev);
7875
1fa61106
ED		 7876 intel_init_pm(dev);
7877
e70236a8
JB		 7878 intel_init_display(dev);
7879
a6c45cf0
CW		 7880 if (IS_GEN2(dev)) {
7881 dev->mode_config.max_width = 2048;
7882 dev->mode_config.max_height = 2048;
7883 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7884 dev->mode_config.max_width = 4096;
7885 dev->mode_config.max_height = 4096;
79e53945 7886 } else {
a6c45cf0
CW		 7887 dev->mode_config.max_width = 8192;
7888 dev->mode_config.max_height = 8192;
79e53945 7889 }
dd2757f8 7890 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 7891
28c97730 7892 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7893 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7894
a3524f1b 7895 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 7896 intel_crtc_init(dev, i);
00c2064b
JB		 7897 ret = intel_plane_init(dev, i);
7898 if (ret)
7899 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 7900 }
7901
ee7b9f93
JB		 7902 intel_pch_pll_init(dev);
7903
9cce37f4
JB		 7904 /* Just disable it once at startup */
7905 i915_disable_vga(dev);
79e53945 7906 intel_setup_outputs(dev);
2c7111db
CW		 7907}
7908
24929352
DV		 7909static void
7910intel_connector_break_all_links(struct intel_connector *connector)
7911{
7912 connector->base.dpms = DRM_MODE_DPMS_OFF;
7913 connector->base.encoder = NULL;
7914 connector->encoder->connectors_active = false;
7915 connector->encoder->base.crtc = NULL;
7916}
7917
7fad798e
DV		 7918static void intel_enable_pipe_a(struct drm_device *dev)
7919{
7920 struct intel_connector *connector;
7921 struct drm_connector *crt = NULL;
7922 struct intel_load_detect_pipe load_detect_temp;
7923
7924 /* We can't just switch on the pipe A, we need to set things up with a
7925 * proper mode and output configuration. As a gross hack, enable pipe A
7926 * by enabling the load detect pipe once. */
7927 list_for_each_entry(connector,
7928 &dev->mode_config.connector_list,
7929 base.head) {
7930 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
7931 crt = &connector->base;
7932 break;
7933 }
7934 }
7935
7936 if (!crt)
7937 return;
7938
7939 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
7940 intel_release_load_detect_pipe(crt, &load_detect_temp);
7941
7942
7943}
7944
24929352
DV		 7945static void intel_sanitize_crtc(struct intel_crtc *crtc)
7946{
7947 struct drm_device *dev = crtc->base.dev;
7948 struct drm_i915_private *dev_priv = dev->dev_private;
7949 u32 reg, val;
7950
24929352
DV		 7951 /* Clear any frame start delays used for debugging left by the BIOS */
7952 reg = PIPECONF(crtc->pipe);
7953 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7954
7955 /* We need to sanitize the plane -> pipe mapping first because this will
7956 * disable the crtc (and hence change the state) if it is wrong. */
7957 if (!HAS_PCH_SPLIT(dev)) {
7958 struct intel_connector *connector;
7959 bool plane;
7960
7961 reg = DSPCNTR(crtc->plane);
7962 val = I915_READ(reg);
7963
7964 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
7965 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
7966 goto ok;
7967
7968 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
7969 crtc->base.base.id);
7970
7971 /* Pipe has the wrong plane attached and the plane is active.
7972 * Temporarily change the plane mapping and disable everything
7973 * ... */
7974 plane = crtc->plane;
7975 crtc->plane = !plane;
7976 dev_priv->display.crtc_disable(&crtc->base);
7977 crtc->plane = plane;
7978
7979 /* ... and break all links. */
7980 list_for_each_entry(connector, &dev->mode_config.connector_list,
7981 base.head) {
7982 if (connector->encoder->base.crtc != &crtc->base)
7983 continue;
7984
7985 intel_connector_break_all_links(connector);
7986 }
7987
7988 WARN_ON(crtc->active);
7989 crtc->base.enabled = false;
7990 }
7991ok:
7992
7fad798e
DV		 7993 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
7994 crtc->pipe == PIPE_A && !crtc->active) {
7995 /* BIOS forgot to enable pipe A, this mostly happens after
7996 * resume. Force-enable the pipe to fix this, the update_dpms
7997 * call below we restore the pipe to the right state, but leave
7998 * the required bits on. */
7999 intel_enable_pipe_a(dev);
8000 }
8001
24929352
DV		 8002 /* Adjust the state of the output pipe according to whether we
8003 * have active connectors/encoders. */
8004 intel_crtc_update_dpms(&crtc->base);
8005
8006 if (crtc->active != crtc->base.enabled) {
8007 struct intel_encoder *encoder;
8008
8009 /* This can happen either due to bugs in the get_hw_state
8010 * functions or because the pipe is force-enabled due to the
8011 * pipe A quirk. */
8012 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8013 crtc->base.base.id,
8014 crtc->base.enabled ? "enabled" : "disabled",
8015 crtc->active ? "enabled" : "disabled");
8016
8017 crtc->base.enabled = crtc->active;
8018
8019 /* Because we only establish the connector -> encoder ->
8020 * crtc links if something is active, this means the
8021 * crtc is now deactivated. Break the links. connector
8022 * -> encoder links are only establish when things are
8023 * actually up, hence no need to break them. */
8024 WARN_ON(crtc->active);
8025
8026 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8027 WARN_ON(encoder->connectors_active);
8028 encoder->base.crtc = NULL;
8029 }
8030 }
8031}
8032
8033static void intel_sanitize_encoder(struct intel_encoder *encoder)
8034{
8035 struct intel_connector *connector;
8036 struct drm_device *dev = encoder->base.dev;
8037
8038 /* We need to check both for a crtc link (meaning that the
8039 * encoder is active and trying to read from a pipe) and the
8040 * pipe itself being active. */
8041 bool has_active_crtc = encoder->base.crtc &&
8042 to_intel_crtc(encoder->base.crtc)->active;
8043
8044 if (encoder->connectors_active && !has_active_crtc) {
8045 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8046 encoder->base.base.id,
8047 drm_get_encoder_name(&encoder->base));
8048
8049 /* Connector is active, but has no active pipe. This is
8050 * fallout from our resume register restoring. Disable
8051 * the encoder manually again. */
8052 if (encoder->base.crtc) {
8053 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8054 encoder->base.base.id,
8055 drm_get_encoder_name(&encoder->base));
8056 encoder->disable(encoder);
8057 }
8058
8059 /* Inconsistent output/port/pipe state happens presumably due to
8060 * a bug in one of the get_hw_state functions. Or someplace else
8061 * in our code, like the register restore mess on resume. Clamp
8062 * things to off as a safer default. */
8063 list_for_each_entry(connector,
8064 &dev->mode_config.connector_list,
8065 base.head) {
8066 if (connector->encoder != encoder)
8067 continue;
8068
8069 intel_connector_break_all_links(connector);
8070 }
8071 }
8072 /* Enabled encoders without active connectors will be fixed in
8073 * the crtc fixup. */
8074}
8075
8076/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8077 * and i915 state tracking structures. */
8078void intel_modeset_setup_hw_state(struct drm_device *dev)
8079{
8080 struct drm_i915_private *dev_priv = dev->dev_private;
8081 enum pipe pipe;
8082 u32 tmp;
8083 struct intel_crtc *crtc;
8084 struct intel_encoder *encoder;
8085 struct intel_connector *connector;
8086
8087 for_each_pipe(pipe) {
8088 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8089
8090 tmp = I915_READ(PIPECONF(pipe));
8091 if (tmp & PIPECONF_ENABLE)
8092 crtc->active = true;
8093 else
8094 crtc->active = false;
8095
8096 crtc->base.enabled = crtc->active;
8097
8098 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8099 crtc->base.base.id,
8100 crtc->active ? "enabled" : "disabled");
8101 }
8102
8103 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8104 base.head) {
8105 pipe = 0;
8106
8107 if (encoder->get_hw_state(encoder, &pipe)) {
8108 encoder->base.crtc =
8109 dev_priv->pipe_to_crtc_mapping[pipe];
8110 } else {
8111 encoder->base.crtc = NULL;
8112 }
8113
8114 encoder->connectors_active = false;
8115 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8116 encoder->base.base.id,
8117 drm_get_encoder_name(&encoder->base),
8118 encoder->base.crtc ? "enabled" : "disabled",
8119 pipe);
8120 }
8121
8122 list_for_each_entry(connector, &dev->mode_config.connector_list,
8123 base.head) {
8124 if (connector->get_hw_state(connector)) {
8125 connector->base.dpms = DRM_MODE_DPMS_ON;
8126 connector->encoder->connectors_active = true;
8127 connector->base.encoder = &connector->encoder->base;
8128 } else {
8129 connector->base.dpms = DRM_MODE_DPMS_OFF;
8130 connector->base.encoder = NULL;
8131 }
8132 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8133 connector->base.base.id,
8134 drm_get_connector_name(&connector->base),
8135 connector->base.encoder ? "enabled" : "disabled");
8136 }
8137
8138 /* HW state is read out, now we need to sanitize this mess. */
8139 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8140 base.head) {
8141 intel_sanitize_encoder(encoder);
8142 }
8143
8144 for_each_pipe(pipe) {
8145 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8146 intel_sanitize_crtc(crtc);
8147 }
9a935856
DV		 8148
8149 intel_modeset_update_staged_output_state(dev);
24929352
DV		 8150}
8151
2c7111db
CW		 8152void intel_modeset_gem_init(struct drm_device *dev)
8153{
1833b134 8154 intel_modeset_init_hw(dev);
02e792fb
DV		 8155
8156 intel_setup_overlay(dev);
24929352
DV		 8157
8158 intel_modeset_setup_hw_state(dev);
79e53945
JB		 8159}
8160
8161void intel_modeset_cleanup(struct drm_device *dev)
8162{
652c393a
JB		 8163 struct drm_i915_private *dev_priv = dev->dev_private;
8164 struct drm_crtc *crtc;
8165 struct intel_crtc *intel_crtc;
8166
f87ea761 8167 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8168 mutex_lock(&dev->struct_mutex);
8169
723bfd70
JB		 8170 intel_unregister_dsm_handler();
8171
8172
652c393a
JB		 8173 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8174 /* Skip inactive CRTCs */
8175 if (!crtc->fb)
8176 continue;
8177
8178 intel_crtc = to_intel_crtc(crtc);
3dec0095 8179 intel_increase_pllclock(crtc);
652c393a
JB		 8180 }
8181
973d04f9 8182 intel_disable_fbc(dev);
e70236a8 8183
8090c6b9 8184 intel_disable_gt_powersave(dev);
0cdab21f 8185
930ebb46
DV		 8186 ironlake_teardown_rc6(dev);
8187
57f350b6
JB		 8188 if (IS_VALLEYVIEW(dev))
8189 vlv_init_dpio(dev);
8190
69341a5e
KH		 8191 mutex_unlock(&dev->struct_mutex);
8192
6c0d9350
DV		 8193 /* Disable the irq before mode object teardown, for the irq might
8194 * enqueue unpin/hotplug work. */
8195 drm_irq_uninstall(dev);
8196 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8197 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8198
1630fe75
CW		 8199 /* flush any delayed tasks or pending work */
8200 flush_scheduled_work();
8201
79e53945
JB		 8202 drm_mode_config_cleanup(dev);
8203}
8204
f1c79df3
ZW		 8205/*
8206 * Return which encoder is currently attached for connector.
8207 */
df0e9248 8208struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8209{
df0e9248
CW		 8210 return &intel_attached_encoder(connector)->base;
8211}
f1c79df3 8212
df0e9248
CW		 8213void intel_connector_attach_encoder(struct intel_connector *connector,
8214 struct intel_encoder *encoder)
8215{
8216 connector->encoder = encoder;
8217 drm_mode_connector_attach_encoder(&connector->base,
8218 &encoder->base);
79e53945 8219}
28d52043
DA		 8220
8221/*
8222 * set vga decode state - true == enable VGA decode
8223 */
8224int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8225{
8226 struct drm_i915_private *dev_priv = dev->dev_private;
8227 u16 gmch_ctrl;
8228
8229 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8230 if (state)
8231 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8232 else
8233 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8234 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8235 return 0;
8236}
c4a1d9e4
CW		 8237
8238#ifdef CONFIG_DEBUG_FS
8239#include <linux/seq_file.h>
8240
8241struct intel_display_error_state {
8242 struct intel_cursor_error_state {
8243 u32 control;
8244 u32 position;
8245 u32 base;
8246 u32 size;
52331309 8247 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 8248
8249 struct intel_pipe_error_state {
8250 u32 conf;
8251 u32 source;
8252
8253 u32 htotal;
8254 u32 hblank;
8255 u32 hsync;
8256 u32 vtotal;
8257 u32 vblank;
8258 u32 vsync;
52331309 8259 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 8260
8261 struct intel_plane_error_state {
8262 u32 control;
8263 u32 stride;
8264 u32 size;
8265 u32 pos;
8266 u32 addr;
8267 u32 surface;
8268 u32 tile_offset;
52331309 8269 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 8270};
8271
8272struct intel_display_error_state *
8273intel_display_capture_error_state(struct drm_device *dev)
8274{
0206e353 8275 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8276 struct intel_display_error_state *error;
8277 int i;
8278
8279 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8280 if (error == NULL)
8281 return NULL;
8282
52331309 8283 for_each_pipe(i) {
c4a1d9e4
CW		 8284 error->cursor[i].control = I915_READ(CURCNTR(i));
8285 error->cursor[i].position = I915_READ(CURPOS(i));
8286 error->cursor[i].base = I915_READ(CURBASE(i));
8287
8288 error->plane[i].control = I915_READ(DSPCNTR(i));
8289 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8290 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8291 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8292 error->plane[i].addr = I915_READ(DSPADDR(i));
8293 if (INTEL_INFO(dev)->gen >= 4) {
8294 error->plane[i].surface = I915_READ(DSPSURF(i));
8295 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8296 }
8297
8298 error->pipe[i].conf = I915_READ(PIPECONF(i));
8299 error->pipe[i].source = I915_READ(PIPESRC(i));
8300 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8301 error->pipe[i].hblank = I915_READ(HBLANK(i));
8302 error->pipe[i].hsync = I915_READ(HSYNC(i));
8303 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8304 error->pipe[i].vblank = I915_READ(VBLANK(i));
8305 error->pipe[i].vsync = I915_READ(VSYNC(i));
8306 }
8307
8308 return error;
8309}
8310
8311void
8312intel_display_print_error_state(struct seq_file *m,
8313 struct drm_device *dev,
8314 struct intel_display_error_state *error)
8315{
52331309 8316 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8317 int i;
8318
52331309
DL		 8319 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8320 for_each_pipe(i) {
c4a1d9e4
CW		 8321 seq_printf(m, "Pipe [%d]:\n", i);
8322 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8323 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8324 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8325 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8326 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8327 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8328 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8329 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8330
8331 seq_printf(m, "Plane [%d]:\n", i);
8332 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8333 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8334 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8335 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8336 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8337 if (INTEL_INFO(dev)->gen >= 4) {
8338 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8339 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8340 }
8341
8342 seq_printf(m, "Cursor [%d]:\n", i);
8343 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8344 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8345 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8346 }
8347}
8348#endif
Linux kernel - Deliverables
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