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drm: Check the fb size against the adjusted v/hdisplay for stereo modes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
a0c4da24
JB		 312static const intel_limit_t intel_limits_vlv_dac = {
313 .dot = { .min = 25000, .max = 270000 },
314 .vco = { .min = 4000000, .max = 6000000 },
315 .n = { .min = 1, .max = 7 },
316 .m = { .min = 22, .max = 450 }, /* guess */
317 .m1 = { .min = 2, .max = 3 },
318 .m2 = { .min = 11, .max = 156 },
319 .p = { .min = 10, .max = 30 },
75e53986 320 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 321 .p2 = { .dot_limit = 270000,
322 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 323};
324
325static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 326 .dot = { .min = 25000, .max = 270000 },
327 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 328 .n = { .min = 1, .max = 7 },
329 .m = { .min = 60, .max = 300 }, /* guess */
330 .m1 = { .min = 2, .max = 3 },
331 .m2 = { .min = 11, .max = 156 },
332 .p = { .min = 10, .max = 30 },
333 .p1 = { .min = 2, .max = 3 },
334 .p2 = { .dot_limit = 270000,
335 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 336};
337
e0638cdf
PZ		 338/**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342{
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351}
352
1b894b59
CW		 353static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
2c07245f 355{
b91ad0ec 356 struct drm_device *dev = crtc->dev;
2c07245f 357 const intel_limit_t *limit;
b91ad0ec
ZW		 358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 360 if (intel_is_dual_link_lvds(dev)) {
1b894b59 361 if (refclk == 100000)
b91ad0ec
ZW		 362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
1b894b59 366 if (refclk == 100000)
b91ad0ec
ZW		 367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
c6bb3538 371 } else
b91ad0ec 372 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 373
374 return limit;
375}
376
044c7c41
ML		 377static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378{
379 struct drm_device *dev = crtc->dev;
044c7c41
ML		 380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 383 if (intel_is_dual_link_lvds(dev))
e4b36699 384 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 385 else
e4b36699 386 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 389 limit = &intel_limits_g4x_hdmi;
044c7c41 390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 391 limit = &intel_limits_g4x_sdvo;
044c7c41 392 } else /* The option is for other outputs */
e4b36699 393 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 394
395 return limit;
396}
397
1b894b59 398static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 399{
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
bad720ff 403 if (HAS_PCH_SPLIT(dev))
1b894b59 404 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 405 else if (IS_G4X(dev)) {
044c7c41 406 limit = intel_g4x_limit(crtc);
f2b115e6 407 } else if (IS_PINEVIEW(dev)) {
2177832f 408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 409 limit = &intel_limits_pineview_lvds;
2177832f 410 else
f2b115e6 411 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 412 } else if (IS_VALLEYVIEW(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
414 limit = &intel_limits_vlv_dac;
a0c4da24 415 else
65ce4bf5 416 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
420 else
421 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 422 } else {
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 424 limit = &intel_limits_i8xx_lvds;
5d536e28 425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 426 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 427 else
428 limit = &intel_limits_i8xx_dac;
79e53945
JB		 429 }
430 return limit;
431}
432
f2b115e6
AJ		 433/* m1 is reserved as 0 in Pineview, n is a ring counter */
434static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 435{
2177832f
SL		 436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 clock->vco = refclk * clock->m / clock->n;
439 clock->dot = clock->vco / clock->p;
440}
441
7429e9d4
DV		 442static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
443{
444 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
445}
446
ac58c3f0 447static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 448{
7429e9d4 449 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 450 clock->p = clock->p1 * clock->p2;
451 clock->vco = refclk * clock->m / (clock->n + 2);
452 clock->dot = clock->vco / clock->p;
453}
454
7c04d1d9 455#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 456/**
457 * Returns whether the given set of divisors are valid for a given refclk with
458 * the given connectors.
459 */
460
1b894b59
CW		 461static bool intel_PLL_is_valid(struct drm_device *dev,
462 const intel_limit_t *limit,
463 const intel_clock_t *clock)
79e53945 464{
79e53945 465 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 466 INTELPllInvalid("p1 out of range\n");
79e53945 467 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 468 INTELPllInvalid("p out of range\n");
79e53945 469 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 470 INTELPllInvalid("m2 out of range\n");
79e53945 471 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 472 INTELPllInvalid("m1 out of range\n");
f2b115e6 473 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 474 INTELPllInvalid("m1 <= m2\n");
79e53945 475 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 476 INTELPllInvalid("m out of range\n");
79e53945 477 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 478 INTELPllInvalid("n out of range\n");
79e53945 479 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 480 INTELPllInvalid("vco out of range\n");
79e53945
JB		 481 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
482 * connector, etc., rather than just a single range.
483 */
484 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 485 INTELPllInvalid("dot out of range\n");
79e53945
JB		 486
487 return true;
488}
489
d4906093 490static bool
ee9300bb 491i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 492 int target, int refclk, intel_clock_t *match_clock,
493 intel_clock_t *best_clock)
79e53945
JB		 494{
495 struct drm_device *dev = crtc->dev;
79e53945 496 intel_clock_t clock;
79e53945
JB		 497 int err = target;
498
a210b028 499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 500 /*
a210b028
DV		 501 * For LVDS just rely on its current settings for dual-channel.
502 * We haven't figured out how to reliably set up different
503 * single/dual channel state, if we even can.
79e53945 504 */
1974cad0 505 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 506 clock.p2 = limit->p2.p2_fast;
507 else
508 clock.p2 = limit->p2.p2_slow;
509 } else {
510 if (target < limit->p2.dot_limit)
511 clock.p2 = limit->p2.p2_slow;
512 else
513 clock.p2 = limit->p2.p2_fast;
514 }
515
0206e353 516 memset(best_clock, 0, sizeof(*best_clock));
79e53945 517
42158660
ZY		 518 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
519 clock.m1++) {
520 for (clock.m2 = limit->m2.min;
521 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 522 if (clock.m2 >= clock.m1)
42158660
ZY		 523 break;
524 for (clock.n = limit->n.min;
525 clock.n <= limit->n.max; clock.n++) {
526 for (clock.p1 = limit->p1.min;
527 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 528 int this_err;
529
ac58c3f0
DV		 530 i9xx_clock(refclk, &clock);
531 if (!intel_PLL_is_valid(dev, limit,
532 &clock))
533 continue;
534 if (match_clock &&
535 clock.p != match_clock->p)
536 continue;
537
538 this_err = abs(clock.dot - target);
539 if (this_err < err) {
540 *best_clock = clock;
541 err = this_err;
542 }
543 }
544 }
545 }
546 }
547
548 return (err != target);
549}
550
551static bool
ee9300bb
DV		 552pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
553 int target, int refclk, intel_clock_t *match_clock,
554 intel_clock_t *best_clock)
79e53945
JB		 555{
556 struct drm_device *dev = crtc->dev;
79e53945 557 intel_clock_t clock;
79e53945
JB		 558 int err = target;
559
a210b028 560 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 561 /*
a210b028
DV		 562 * For LVDS just rely on its current settings for dual-channel.
563 * We haven't figured out how to reliably set up different
564 * single/dual channel state, if we even can.
79e53945 565 */
1974cad0 566 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 567 clock.p2 = limit->p2.p2_fast;
568 else
569 clock.p2 = limit->p2.p2_slow;
570 } else {
571 if (target < limit->p2.dot_limit)
572 clock.p2 = limit->p2.p2_slow;
573 else
574 clock.p2 = limit->p2.p2_fast;
575 }
576
0206e353 577 memset(best_clock, 0, sizeof(*best_clock));
79e53945 578
42158660
ZY		 579 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
580 clock.m1++) {
581 for (clock.m2 = limit->m2.min;
582 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 583 for (clock.n = limit->n.min;
584 clock.n <= limit->n.max; clock.n++) {
585 for (clock.p1 = limit->p1.min;
586 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 587 int this_err;
588
ac58c3f0 589 pineview_clock(refclk, &clock);
1b894b59
CW		 590 if (!intel_PLL_is_valid(dev, limit,
591 &clock))
79e53945 592 continue;
cec2f356
SP		 593 if (match_clock &&
594 clock.p != match_clock->p)
595 continue;
79e53945
JB		 596
597 this_err = abs(clock.dot - target);
598 if (this_err < err) {
599 *best_clock = clock;
600 err = this_err;
601 }
602 }
603 }
604 }
605 }
606
607 return (err != target);
608}
609
d4906093 610static bool
ee9300bb
DV		 611g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
612 int target, int refclk, intel_clock_t *match_clock,
613 intel_clock_t *best_clock)
d4906093
ML		 614{
615 struct drm_device *dev = crtc->dev;
d4906093
ML		 616 intel_clock_t clock;
617 int max_n;
618 bool found;
6ba770dc
AJ		 619 /* approximately equals target * 0.00585 */
620 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 621 found = false;
622
623 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 624 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 625 clock.p2 = limit->p2.p2_fast;
626 else
627 clock.p2 = limit->p2.p2_slow;
628 } else {
629 if (target < limit->p2.dot_limit)
630 clock.p2 = limit->p2.p2_slow;
631 else
632 clock.p2 = limit->p2.p2_fast;
633 }
634
635 memset(best_clock, 0, sizeof(*best_clock));
636 max_n = limit->n.max;
f77f13e2 637 /* based on hardware requirement, prefer smaller n to precision */
d4906093 638 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 639 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 640 for (clock.m1 = limit->m1.max;
641 clock.m1 >= limit->m1.min; clock.m1--) {
642 for (clock.m2 = limit->m2.max;
643 clock.m2 >= limit->m2.min; clock.m2--) {
644 for (clock.p1 = limit->p1.max;
645 clock.p1 >= limit->p1.min; clock.p1--) {
646 int this_err;
647
ac58c3f0 648 i9xx_clock(refclk, &clock);
1b894b59
CW		 649 if (!intel_PLL_is_valid(dev, limit,
650 &clock))
d4906093 651 continue;
1b894b59
CW		 652
653 this_err = abs(clock.dot - target);
d4906093
ML		 654 if (this_err < err_most) {
655 *best_clock = clock;
656 err_most = this_err;
657 max_n = clock.n;
658 found = true;
659 }
660 }
661 }
662 }
663 }
2c07245f
ZW		 664 return found;
665}
666
a0c4da24 667static bool
ee9300bb
DV		 668vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *match_clock,
670 intel_clock_t *best_clock)
a0c4da24
JB		 671{
672 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
673 u32 m, n, fastclk;
f3f08572 674 u32 updrate, minupdate, p;
a0c4da24
JB		 675 unsigned long bestppm, ppm, absppm;
676 int dotclk, flag;
677
af447bd3 678 flag = 0;
a0c4da24
JB		 679 dotclk = target * 1000;
680 bestppm = 1000000;
681 ppm = absppm = 0;
682 fastclk = dotclk / (2*100);
683 updrate = 0;
684 minupdate = 19200;
a0c4da24
JB		 685 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
686 bestm1 = bestm2 = bestp1 = bestp2 = 0;
687
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
690 updrate = refclk / n;
691 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
692 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
693 if (p2 > 10)
694 p2 = p2 - 1;
695 p = p1 * p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
698 m2 = (((2*(fastclk * p * n / m1 )) +
699 refclk) / (2*refclk));
700 m = m1 * m2;
701 vco = updrate * m;
702 if (vco >= limit->vco.min && vco < limit->vco.max) {
703 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
704 absppm = (ppm > 0) ? ppm : (-ppm);
705 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
706 bestppm = 0;
707 flag = 1;
708 }
709 if (absppm < bestppm - 10) {
710 bestppm = absppm;
711 flag = 1;
712 }
713 if (flag) {
714 bestn = n;
715 bestm1 = m1;
716 bestm2 = m2;
717 bestp1 = p1;
718 bestp2 = p2;
719 flag = 0;
720 }
721 }
722 }
723 }
724 }
725 }
726 best_clock->n = bestn;
727 best_clock->m1 = bestm1;
728 best_clock->m2 = bestm2;
729 best_clock->p1 = bestp1;
730 best_clock->p2 = bestp2;
731
732 return true;
733}
a4fc5ed6 734
20ddf665
VS		 735bool intel_crtc_active(struct drm_crtc *crtc)
736{
737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
738
739 /* Be paranoid as we can arrive here with only partial
740 * state retrieved from the hardware during setup.
741 *
742 * We can ditch the adjusted_mode.clock check as soon
743 * as Haswell has gained clock readout/fastboot support.
744 *
745 * We can ditch the crtc->fb check as soon as we can
746 * properly reconstruct framebuffers.
747 */
748 return intel_crtc->active && crtc->fb &&
749 intel_crtc->config.adjusted_mode.clock;
750}
751
a5c961d1
PZ		 752enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
753 enum pipe pipe)
754{
755 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
757
3b117c8f 758 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 759}
760
a928d536
PZ		 761static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
762{
763 struct drm_i915_private *dev_priv = dev->dev_private;
764 u32 frame, frame_reg = PIPEFRAME(pipe);
765
766 frame = I915_READ(frame_reg);
767
768 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
769 DRM_DEBUG_KMS("vblank wait timed out\n");
770}
771
9d0498a2
JB		 772/**
773 * intel_wait_for_vblank - wait for vblank on a given pipe
774 * @dev: drm device
775 * @pipe: pipe to wait for
776 *
777 * Wait for vblank to occur on a given pipe. Needed for various bits of
778 * mode setting code.
779 */
780void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 781{
9d0498a2 782 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 783 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 784
a928d536
PZ		 785 if (INTEL_INFO(dev)->gen >= 5) {
786 ironlake_wait_for_vblank(dev, pipe);
787 return;
788 }
789
300387c0
CW		 790 /* Clear existing vblank status. Note this will clear any other
791 * sticky status fields as well.
792 *
793 * This races with i915_driver_irq_handler() with the result
794 * that either function could miss a vblank event. Here it is not
795 * fatal, as we will either wait upon the next vblank interrupt or
796 * timeout. Generally speaking intel_wait_for_vblank() is only
797 * called during modeset at which time the GPU should be idle and
798 * should *not* be performing page flips and thus not waiting on
799 * vblanks...
800 * Currently, the result of us stealing a vblank from the irq
801 * handler is that a single frame will be skipped during swapbuffers.
802 */
803 I915_WRITE(pipestat_reg,
804 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
805
9d0498a2 806 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 807 if (wait_for(I915_READ(pipestat_reg) &
808 PIPE_VBLANK_INTERRUPT_STATUS,
809 50))
9d0498a2
JB		 810 DRM_DEBUG_KMS("vblank wait timed out\n");
811}
812
ab7ad7f6
KP		 813/*
814 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 815 * @dev: drm device
816 * @pipe: pipe to wait for
817 *
818 * After disabling a pipe, we can't wait for vblank in the usual way,
819 * spinning on the vblank interrupt status bit, since we won't actually
820 * see an interrupt when the pipe is disabled.
821 *
ab7ad7f6
KP		 822 * On Gen4 and above:
823 * wait for the pipe register state bit to turn off
824 *
825 * Otherwise:
826 * wait for the display line value to settle (it usually
827 * ends up stopping at the start of the next frame).
58e10eb9 828 *
9d0498a2 829 */
58e10eb9 830void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 831{
832 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 833 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
834 pipe);
ab7ad7f6
KP		 835
836 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 837 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 838
839 /* Wait for the Pipe State to go off */
58e10eb9
CW		 840 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
841 100))
284637d9 842 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 843 } else {
837ba00f 844 u32 last_line, line_mask;
58e10eb9 845 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 846 unsigned long timeout = jiffies + msecs_to_jiffies(100);
847
837ba00f
PZ		 848 if (IS_GEN2(dev))
849 line_mask = DSL_LINEMASK_GEN2;
850 else
851 line_mask = DSL_LINEMASK_GEN3;
852
ab7ad7f6
KP		 853 /* Wait for the display line to settle */
854 do {
837ba00f 855 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 856 mdelay(5);
837ba00f 857 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 858 time_after(timeout, jiffies));
859 if (time_after(jiffies, timeout))
284637d9 860 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 861 }
79e53945
JB		 862}
863
b0ea7d37
DL		 864/*
865 * ibx_digital_port_connected - is the specified port connected?
866 * @dev_priv: i915 private structure
867 * @port: the port to test
868 *
869 * Returns true if @port is connected, false otherwise.
870 */
871bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
872 struct intel_digital_port *port)
873{
874 u32 bit;
875
c36346e3
DL		 876 if (HAS_PCH_IBX(dev_priv->dev)) {
877 switch(port->port) {
878 case PORT_B:
879 bit = SDE_PORTB_HOTPLUG;
880 break;
881 case PORT_C:
882 bit = SDE_PORTC_HOTPLUG;
883 break;
884 case PORT_D:
885 bit = SDE_PORTD_HOTPLUG;
886 break;
887 default:
888 return true;
889 }
890 } else {
891 switch(port->port) {
892 case PORT_B:
893 bit = SDE_PORTB_HOTPLUG_CPT;
894 break;
895 case PORT_C:
896 bit = SDE_PORTC_HOTPLUG_CPT;
897 break;
898 case PORT_D:
899 bit = SDE_PORTD_HOTPLUG_CPT;
900 break;
901 default:
902 return true;
903 }
b0ea7d37
DL		 904 }
905
906 return I915_READ(SDEISR) & bit;
907}
908
b24e7179
JB		 909static const char *state_string(bool enabled)
910{
911 return enabled ? "on" : "off";
912}
913
914/* Only for pre-ILK configs */
55607e8a
DV		 915void assert_pll(struct drm_i915_private *dev_priv,
916 enum pipe pipe, bool state)
b24e7179
JB		 917{
918 int reg;
919 u32 val;
920 bool cur_state;
921
922 reg = DPLL(pipe);
923 val = I915_READ(reg);
924 cur_state = !!(val & DPLL_VCO_ENABLE);
925 WARN(cur_state != state,
926 "PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state), state_string(cur_state));
928}
b24e7179 929
23538ef1
JN		 930/* XXX: the dsi pll is shared between MIPI DSI ports */
931static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
932{
933 u32 val;
934 bool cur_state;
935
936 mutex_lock(&dev_priv->dpio_lock);
937 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
938 mutex_unlock(&dev_priv->dpio_lock);
939
940 cur_state = val & DSI_PLL_VCO_EN;
941 WARN(cur_state != state,
942 "DSI PLL state assertion failure (expected %s, current %s)\n",
943 state_string(state), state_string(cur_state));
944}
945#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
946#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
947
55607e8a 948struct intel_shared_dpll *
e2b78267
DV		 949intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
950{
951 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
952
a43f6e0f 953 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 954 return NULL;
955
a43f6e0f 956 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 957}
958
040484af 959/* For ILK+ */
55607e8a
DV		 960void assert_shared_dpll(struct drm_i915_private *dev_priv,
961 struct intel_shared_dpll *pll,
962 bool state)
040484af 963{
040484af 964 bool cur_state;
5358901f 965 struct intel_dpll_hw_state hw_state;
040484af 966
9d82aa17
ED		 967 if (HAS_PCH_LPT(dev_priv->dev)) {
968 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
969 return;
970 }
971
92b27b08 972 if (WARN (!pll,
46edb027 973 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 974 return;
ee7b9f93 975
5358901f 976 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 977 WARN(cur_state != state,
5358901f
DV		 978 "%s assertion failure (expected %s, current %s)\n",
979 pll->name, state_string(state), state_string(cur_state));
040484af 980}
040484af
JB		 981
982static void assert_fdi_tx(struct drm_i915_private *dev_priv,
983 enum pipe pipe, bool state)
984{
985 int reg;
986 u32 val;
987 bool cur_state;
ad80a810
PZ		 988 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
989 pipe);
040484af 990
affa9354
PZ		 991 if (HAS_DDI(dev_priv->dev)) {
992 /* DDI does not have a specific FDI_TX register */
ad80a810 993 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 994 val = I915_READ(reg);
ad80a810 995 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 996 } else {
997 reg = FDI_TX_CTL(pipe);
998 val = I915_READ(reg);
999 cur_state = !!(val & FDI_TX_ENABLE);
1000 }
040484af
JB		 1001 WARN(cur_state != state,
1002 "FDI TX state assertion failure (expected %s, current %s)\n",
1003 state_string(state), state_string(cur_state));
1004}
1005#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1006#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1007
1008static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1009 enum pipe pipe, bool state)
1010{
1011 int reg;
1012 u32 val;
1013 bool cur_state;
1014
d63fa0dc
PZ		 1015 reg = FDI_RX_CTL(pipe);
1016 val = I915_READ(reg);
1017 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1018 WARN(cur_state != state,
1019 "FDI RX state assertion failure (expected %s, current %s)\n",
1020 state_string(state), state_string(cur_state));
1021}
1022#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1023#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1024
1025static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1026 enum pipe pipe)
1027{
1028 int reg;
1029 u32 val;
1030
1031 /* ILK FDI PLL is always enabled */
1032 if (dev_priv->info->gen == 5)
1033 return;
1034
bf507ef7 1035 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1036 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1037 return;
1038
040484af
JB		 1039 reg = FDI_TX_CTL(pipe);
1040 val = I915_READ(reg);
1041 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1042}
1043
55607e8a
DV		 1044void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1045 enum pipe pipe, bool state)
040484af
JB		 1046{
1047 int reg;
1048 u32 val;
55607e8a 1049 bool cur_state;
040484af
JB		 1050
1051 reg = FDI_RX_CTL(pipe);
1052 val = I915_READ(reg);
55607e8a
DV		 1053 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1054 WARN(cur_state != state,
1055 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1056 state_string(state), state_string(cur_state));
040484af
JB		 1057}
1058
ea0760cf
JB		 1059static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1060 enum pipe pipe)
1061{
1062 int pp_reg, lvds_reg;
1063 u32 val;
1064 enum pipe panel_pipe = PIPE_A;
0de3b485 1065 bool locked = true;
ea0760cf
JB		 1066
1067 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1068 pp_reg = PCH_PP_CONTROL;
1069 lvds_reg = PCH_LVDS;
1070 } else {
1071 pp_reg = PP_CONTROL;
1072 lvds_reg = LVDS;
1073 }
1074
1075 val = I915_READ(pp_reg);
1076 if (!(val & PANEL_POWER_ON) ||
1077 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1078 locked = false;
1079
1080 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1081 panel_pipe = PIPE_B;
1082
1083 WARN(panel_pipe == pipe && locked,
1084 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1085 pipe_name(pipe));
ea0760cf
JB		 1086}
1087
93ce0ba6
JN		 1088static void assert_cursor(struct drm_i915_private *dev_priv,
1089 enum pipe pipe, bool state)
1090{
1091 struct drm_device *dev = dev_priv->dev;
1092 bool cur_state;
1093
1094 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1095 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1096 else if (IS_845G(dev) || IS_I865G(dev))
1097 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1098 else
1099 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1100
1101 WARN(cur_state != state,
1102 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1103 pipe_name(pipe), state_string(state), state_string(cur_state));
1104}
1105#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1106#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1107
b840d907
JB		 1108void assert_pipe(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
b24e7179
JB		 1110{
1111 int reg;
1112 u32 val;
63d7bbe9 1113 bool cur_state;
702e7a56
PZ		 1114 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1115 pipe);
b24e7179 1116
8e636784
DV		 1117 /* if we need the pipe A quirk it must be always on */
1118 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1119 state = true;
1120
b97186f0
PZ		 1121 if (!intel_display_power_enabled(dev_priv->dev,
1122 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1123 cur_state = false;
1124 } else {
1125 reg = PIPECONF(cpu_transcoder);
1126 val = I915_READ(reg);
1127 cur_state = !!(val & PIPECONF_ENABLE);
1128 }
1129
63d7bbe9
JB		 1130 WARN(cur_state != state,
1131 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1132 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1133}
1134
931872fc
CW		 1135static void assert_plane(struct drm_i915_private *dev_priv,
1136 enum plane plane, bool state)
b24e7179
JB		 1137{
1138 int reg;
1139 u32 val;
931872fc 1140 bool cur_state;
b24e7179
JB		 1141
1142 reg = DSPCNTR(plane);
1143 val = I915_READ(reg);
931872fc
CW		 1144 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1145 WARN(cur_state != state,
1146 "plane %c assertion failure (expected %s, current %s)\n",
1147 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1148}
1149
931872fc
CW		 1150#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1151#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1152
b24e7179
JB		 1153static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1154 enum pipe pipe)
1155{
653e1026 1156 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1157 int reg, i;
1158 u32 val;
1159 int cur_pipe;
1160
653e1026
VS		 1161 /* Primary planes are fixed to pipes on gen4+ */
1162 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1163 reg = DSPCNTR(pipe);
1164 val = I915_READ(reg);
1165 WARN((val & DISPLAY_PLANE_ENABLE),
1166 "plane %c assertion failure, should be disabled but not\n",
1167 plane_name(pipe));
19ec1358 1168 return;
28c05794 1169 }
19ec1358 1170
b24e7179 1171 /* Need to check both planes against the pipe */
08e2a7de 1172 for_each_pipe(i) {
b24e7179
JB		 1173 reg = DSPCNTR(i);
1174 val = I915_READ(reg);
1175 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1176 DISPPLANE_SEL_PIPE_SHIFT;
1177 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1178 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1179 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1180 }
1181}
1182
19332d7a
JB		 1183static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1184 enum pipe pipe)
1185{
20674eef 1186 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1187 int reg, i;
1188 u32 val;
1189
20674eef
VS		 1190 if (IS_VALLEYVIEW(dev)) {
1191 for (i = 0; i < dev_priv->num_plane; i++) {
1192 reg = SPCNTR(pipe, i);
1193 val = I915_READ(reg);
1194 WARN((val & SP_ENABLE),
1195 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1196 sprite_name(pipe, i), pipe_name(pipe));
1197 }
1198 } else if (INTEL_INFO(dev)->gen >= 7) {
1199 reg = SPRCTL(pipe);
19332d7a 1200 val = I915_READ(reg);
20674eef 1201 WARN((val & SPRITE_ENABLE),
06da8da2 1202 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1203 plane_name(pipe), pipe_name(pipe));
1204 } else if (INTEL_INFO(dev)->gen >= 5) {
1205 reg = DVSCNTR(pipe);
19332d7a 1206 val = I915_READ(reg);
20674eef 1207 WARN((val & DVS_ENABLE),
06da8da2 1208 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1209 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1210 }
1211}
1212
92f2584a
JB		 1213static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1214{
1215 u32 val;
1216 bool enabled;
1217
9d82aa17
ED		 1218 if (HAS_PCH_LPT(dev_priv->dev)) {
1219 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1220 return;
1221 }
1222
92f2584a
JB		 1223 val = I915_READ(PCH_DREF_CONTROL);
1224 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1225 DREF_SUPERSPREAD_SOURCE_MASK));
1226 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1227}
1228
ab9412ba
DV		 1229static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1230 enum pipe pipe)
92f2584a
JB		 1231{
1232 int reg;
1233 u32 val;
1234 bool enabled;
1235
ab9412ba 1236 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1237 val = I915_READ(reg);
1238 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1239 WARN(enabled,
1240 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1241 pipe_name(pipe));
92f2584a
JB		 1242}
1243
4e634389
KP		 1244static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1245 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1246{
1247 if ((val & DP_PORT_EN) == 0)
1248 return false;
1249
1250 if (HAS_PCH_CPT(dev_priv->dev)) {
1251 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1252 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1253 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1254 return false;
1255 } else {
1256 if ((val & DP_PIPE_MASK) != (pipe << 30))
1257 return false;
1258 }
1259 return true;
1260}
1261
1519b995
KP		 1262static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe, u32 val)
1264{
dc0fa718 1265 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1266 return false;
1267
1268 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1269 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1270 return false;
1271 } else {
dc0fa718 1272 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1273 return false;
1274 }
1275 return true;
1276}
1277
1278static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe, u32 val)
1280{
1281 if ((val & LVDS_PORT_EN) == 0)
1282 return false;
1283
1284 if (HAS_PCH_CPT(dev_priv->dev)) {
1285 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1286 return false;
1287 } else {
1288 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1289 return false;
1290 }
1291 return true;
1292}
1293
1294static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe, u32 val)
1296{
1297 if ((val & ADPA_DAC_ENABLE) == 0)
1298 return false;
1299 if (HAS_PCH_CPT(dev_priv->dev)) {
1300 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1301 return false;
1302 } else {
1303 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1304 return false;
1305 }
1306 return true;
1307}
1308
291906f1 1309static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1310 enum pipe pipe, int reg, u32 port_sel)
291906f1 1311{
47a05eca 1312 u32 val = I915_READ(reg);
4e634389 1313 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1314 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1315 reg, pipe_name(pipe));
de9a35ab 1316
75c5da27
DV		 1317 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1318 && (val & DP_PIPEB_SELECT),
de9a35ab 1319 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1320}
1321
1322static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, int reg)
1324{
47a05eca 1325 u32 val = I915_READ(reg);
b70ad586 1326 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1327 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1328 reg, pipe_name(pipe));
de9a35ab 1329
dc0fa718 1330 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1331 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1332 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1333}
1334
1335static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1336 enum pipe pipe)
1337{
1338 int reg;
1339 u32 val;
291906f1 1340
f0575e92
KP		 1341 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1344
1345 reg = PCH_ADPA;
1346 val = I915_READ(reg);
b70ad586 1347 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1348 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1349 pipe_name(pipe));
291906f1
JB		 1350
1351 reg = PCH_LVDS;
1352 val = I915_READ(reg);
b70ad586 1353 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1354 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1355 pipe_name(pipe));
291906f1 1356
e2debe91
PZ		 1357 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1360}
1361
426115cf 1362static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1363{
426115cf
DV		 1364 struct drm_device *dev = crtc->base.dev;
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366 int reg = DPLL(crtc->pipe);
1367 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1368
426115cf 1369 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1370
1371 /* No really, not for ILK+ */
1372 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1373
1374 /* PLL is protected by panel, make sure we can write it */
1375 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1376 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1377
426115cf
DV		 1378 I915_WRITE(reg, dpll);
1379 POSTING_READ(reg);
1380 udelay(150);
1381
1382 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1383 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1384
1385 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1386 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1387
1388 /* We do this three times for luck */
426115cf 1389 I915_WRITE(reg, dpll);
87442f73
DV		 1390 POSTING_READ(reg);
1391 udelay(150); /* wait for warmup */
426115cf 1392 I915_WRITE(reg, dpll);
87442f73
DV		 1393 POSTING_READ(reg);
1394 udelay(150); /* wait for warmup */
426115cf 1395 I915_WRITE(reg, dpll);
87442f73
DV		 1396 POSTING_READ(reg);
1397 udelay(150); /* wait for warmup */
1398}
1399
66e3d5c0 1400static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1401{
66e3d5c0
DV		 1402 struct drm_device *dev = crtc->base.dev;
1403 struct drm_i915_private *dev_priv = dev->dev_private;
1404 int reg = DPLL(crtc->pipe);
1405 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1406
66e3d5c0 1407 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1408
63d7bbe9 1409 /* No really, not for ILK+ */
87442f73 1410 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1411
1412 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1413 if (IS_MOBILE(dev) && !IS_I830(dev))
1414 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1415
66e3d5c0
DV		 1416 I915_WRITE(reg, dpll);
1417
1418 /* Wait for the clocks to stabilize. */
1419 POSTING_READ(reg);
1420 udelay(150);
1421
1422 if (INTEL_INFO(dev)->gen >= 4) {
1423 I915_WRITE(DPLL_MD(crtc->pipe),
1424 crtc->config.dpll_hw_state.dpll_md);
1425 } else {
1426 /* The pixel multiplier can only be updated once the
1427 * DPLL is enabled and the clocks are stable.
1428 *
1429 * So write it again.
1430 */
1431 I915_WRITE(reg, dpll);
1432 }
63d7bbe9
JB		 1433
1434 /* We do this three times for luck */
66e3d5c0 1435 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1436 POSTING_READ(reg);
1437 udelay(150); /* wait for warmup */
66e3d5c0 1438 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1439 POSTING_READ(reg);
1440 udelay(150); /* wait for warmup */
66e3d5c0 1441 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1442 POSTING_READ(reg);
1443 udelay(150); /* wait for warmup */
1444}
1445
1446/**
50b44a44 1447 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1448 * @dev_priv: i915 private structure
1449 * @pipe: pipe PLL to disable
1450 *
1451 * Disable the PLL for @pipe, making sure the pipe is off first.
1452 *
1453 * Note! This is for pre-ILK only.
1454 */
50b44a44 1455static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1456{
63d7bbe9
JB		 1457 /* Don't disable pipe A or pipe A PLLs if needed */
1458 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1459 return;
1460
1461 /* Make sure the pipe isn't still relying on us */
1462 assert_pipe_disabled(dev_priv, pipe);
1463
50b44a44
DV		 1464 I915_WRITE(DPLL(pipe), 0);
1465 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1466}
1467
89b667f8
JB		 1468void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1469{
1470 u32 port_mask;
1471
1472 if (!port)
1473 port_mask = DPLL_PORTB_READY_MASK;
1474 else
1475 port_mask = DPLL_PORTC_READY_MASK;
1476
1477 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1478 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1479 'B' + port, I915_READ(DPLL(0)));
1480}
1481
92f2584a 1482/**
e72f9fbf 1483 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1484 * @dev_priv: i915 private structure
1485 * @pipe: pipe PLL to enable
1486 *
1487 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1488 * drives the transcoder clock.
1489 */
e2b78267 1490static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1491{
e2b78267
DV		 1492 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1493 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1494
48da64a8 1495 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1496 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1497 if (WARN_ON(pll == NULL))
48da64a8
CW		 1498 return;
1499
1500 if (WARN_ON(pll->refcount == 0))
1501 return;
ee7b9f93 1502
46edb027
DV		 1503 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1504 pll->name, pll->active, pll->on,
e2b78267 1505 crtc->base.base.id);
92f2584a 1506
cdbd2316
DV		 1507 if (pll->active++) {
1508 WARN_ON(!pll->on);
e9d6944e 1509 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1510 return;
1511 }
f4a091c7 1512 WARN_ON(pll->on);
ee7b9f93 1513
46edb027 1514 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1515 pll->enable(dev_priv, pll);
ee7b9f93 1516 pll->on = true;
92f2584a
JB		 1517}
1518
e2b78267 1519static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1520{
e2b78267
DV		 1521 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1523
92f2584a
JB		 1524 /* PCH only available on ILK+ */
1525 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1526 if (WARN_ON(pll == NULL))
ee7b9f93 1527 return;
92f2584a 1528
48da64a8
CW		 1529 if (WARN_ON(pll->refcount == 0))
1530 return;
7a419866 1531
46edb027
DV		 1532 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1533 pll->name, pll->active, pll->on,
e2b78267 1534 crtc->base.base.id);
7a419866 1535
48da64a8 1536 if (WARN_ON(pll->active == 0)) {
e9d6944e 1537 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1538 return;
1539 }
1540
e9d6944e 1541 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1542 WARN_ON(!pll->on);
cdbd2316 1543 if (--pll->active)
7a419866 1544 return;
ee7b9f93 1545
46edb027 1546 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1547 pll->disable(dev_priv, pll);
ee7b9f93 1548 pll->on = false;
92f2584a
JB		 1549}
1550
b8a4f404
PZ		 1551static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1552 enum pipe pipe)
040484af 1553{
23670b32 1554 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1555 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1557 uint32_t reg, val, pipeconf_val;
040484af
JB		 1558
1559 /* PCH only available on ILK+ */
1560 BUG_ON(dev_priv->info->gen < 5);
1561
1562 /* Make sure PCH DPLL is enabled */
e72f9fbf 1563 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1564 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1565
1566 /* FDI must be feeding us bits for PCH ports */
1567 assert_fdi_tx_enabled(dev_priv, pipe);
1568 assert_fdi_rx_enabled(dev_priv, pipe);
1569
23670b32
DV		 1570 if (HAS_PCH_CPT(dev)) {
1571 /* Workaround: Set the timing override bit before enabling the
1572 * pch transcoder. */
1573 reg = TRANS_CHICKEN2(pipe);
1574 val = I915_READ(reg);
1575 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1576 I915_WRITE(reg, val);
59c859d6 1577 }
23670b32 1578
ab9412ba 1579 reg = PCH_TRANSCONF(pipe);
040484af 1580 val = I915_READ(reg);
5f7f726d 1581 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1582
1583 if (HAS_PCH_IBX(dev_priv->dev)) {
1584 /*
1585 * make the BPC in transcoder be consistent with
1586 * that in pipeconf reg.
1587 */
dfd07d72
DV		 1588 val &= ~PIPECONF_BPC_MASK;
1589 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1590 }
5f7f726d
PZ		 1591
1592 val &= ~TRANS_INTERLACE_MASK;
1593 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1594 if (HAS_PCH_IBX(dev_priv->dev) &&
1595 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1596 val |= TRANS_LEGACY_INTERLACED_ILK;
1597 else
1598 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1599 else
1600 val |= TRANS_PROGRESSIVE;
1601
040484af
JB		 1602 I915_WRITE(reg, val | TRANS_ENABLE);
1603 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1604 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1605}
1606
8fb033d7 1607static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1608 enum transcoder cpu_transcoder)
040484af 1609{
8fb033d7 1610 u32 val, pipeconf_val;
8fb033d7
PZ		 1611
1612 /* PCH only available on ILK+ */
1613 BUG_ON(dev_priv->info->gen < 5);
1614
8fb033d7 1615 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1616 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1617 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1618
223a6fdf
PZ		 1619 /* Workaround: set timing override bit. */
1620 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1621 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1622 I915_WRITE(_TRANSA_CHICKEN2, val);
1623
25f3ef11 1624 val = TRANS_ENABLE;
937bb610 1625 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1626
9a76b1c6
PZ		 1627 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1628 PIPECONF_INTERLACED_ILK)
a35f2679 1629 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1630 else
1631 val |= TRANS_PROGRESSIVE;
1632
ab9412ba
DV		 1633 I915_WRITE(LPT_TRANSCONF, val);
1634 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1635 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1636}
1637
b8a4f404
PZ		 1638static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1639 enum pipe pipe)
040484af 1640{
23670b32
DV		 1641 struct drm_device *dev = dev_priv->dev;
1642 uint32_t reg, val;
040484af
JB		 1643
1644 /* FDI relies on the transcoder */
1645 assert_fdi_tx_disabled(dev_priv, pipe);
1646 assert_fdi_rx_disabled(dev_priv, pipe);
1647
291906f1
JB		 1648 /* Ports must be off as well */
1649 assert_pch_ports_disabled(dev_priv, pipe);
1650
ab9412ba 1651 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1652 val = I915_READ(reg);
1653 val &= ~TRANS_ENABLE;
1654 I915_WRITE(reg, val);
1655 /* wait for PCH transcoder off, transcoder state */
1656 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1657 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1658
1659 if (!HAS_PCH_IBX(dev)) {
1660 /* Workaround: Clear the timing override chicken bit again. */
1661 reg = TRANS_CHICKEN2(pipe);
1662 val = I915_READ(reg);
1663 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1664 I915_WRITE(reg, val);
1665 }
040484af
JB		 1666}
1667
ab4d966c 1668static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1669{
8fb033d7
PZ		 1670 u32 val;
1671
ab9412ba 1672 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1673 val &= ~TRANS_ENABLE;
ab9412ba 1674 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1675 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1676 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1677 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1678
1679 /* Workaround: clear timing override bit. */
1680 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1681 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1682 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1683}
1684
b24e7179 1685/**
309cfea8 1686 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1687 * @dev_priv: i915 private structure
1688 * @pipe: pipe to enable
040484af 1689 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1690 *
1691 * Enable @pipe, making sure that various hardware specific requirements
1692 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1693 *
1694 * @pipe should be %PIPE_A or %PIPE_B.
1695 *
1696 * Will wait until the pipe is actually running (i.e. first vblank) before
1697 * returning.
1698 */
040484af 1699static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1700 bool pch_port, bool dsi)
b24e7179 1701{
702e7a56
PZ		 1702 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1703 pipe);
1a240d4d 1704 enum pipe pch_transcoder;
b24e7179
JB		 1705 int reg;
1706 u32 val;
1707
58c6eaa2 1708 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1709 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1710 assert_sprites_disabled(dev_priv, pipe);
1711
681e5811 1712 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1713 pch_transcoder = TRANSCODER_A;
1714 else
1715 pch_transcoder = pipe;
1716
b24e7179
JB		 1717 /*
1718 * A pipe without a PLL won't actually be able to drive bits from
1719 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1720 * need the check.
1721 */
1722 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1723 if (dsi)
1724 assert_dsi_pll_enabled(dev_priv);
1725 else
1726 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1727 else {
1728 if (pch_port) {
1729 /* if driving the PCH, we need FDI enabled */
cc391bbb 1730 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1731 assert_fdi_tx_pll_enabled(dev_priv,
1732 (enum pipe) cpu_transcoder);
040484af
JB		 1733 }
1734 /* FIXME: assert CPU port conditions for SNB+ */
1735 }
b24e7179 1736
702e7a56 1737 reg = PIPECONF(cpu_transcoder);
b24e7179 1738 val = I915_READ(reg);
00d70b15
CW		 1739 if (val & PIPECONF_ENABLE)
1740 return;
1741
1742 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1743 intel_wait_for_vblank(dev_priv->dev, pipe);
1744}
1745
1746/**
309cfea8 1747 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to disable
1750 *
1751 * Disable @pipe, making sure that various hardware specific requirements
1752 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1753 *
1754 * @pipe should be %PIPE_A or %PIPE_B.
1755 *
1756 * Will wait until the pipe has shut down before returning.
1757 */
1758static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1759 enum pipe pipe)
1760{
702e7a56
PZ		 1761 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1762 pipe);
b24e7179
JB		 1763 int reg;
1764 u32 val;
1765
1766 /*
1767 * Make sure planes won't keep trying to pump pixels to us,
1768 * or we might hang the display.
1769 */
1770 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1771 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1772 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1773
1774 /* Don't disable pipe A or pipe A PLLs if needed */
1775 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1776 return;
1777
702e7a56 1778 reg = PIPECONF(cpu_transcoder);
b24e7179 1779 val = I915_READ(reg);
00d70b15
CW		 1780 if ((val & PIPECONF_ENABLE) == 0)
1781 return;
1782
1783 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1784 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1785}
1786
d74362c9
KP		 1787/*
1788 * Plane regs are double buffered, going from enabled->disabled needs a
1789 * trigger in order to latch. The display address reg provides this.
1790 */
6f1d69b0 1791void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1792 enum plane plane)
1793{
14f86147
DL		 1794 if (dev_priv->info->gen >= 4)
1795 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1796 else
1797 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1798}
1799
b24e7179
JB		 1800/**
1801 * intel_enable_plane - enable a display plane on a given pipe
1802 * @dev_priv: i915 private structure
1803 * @plane: plane to enable
1804 * @pipe: pipe being fed
1805 *
1806 * Enable @plane on @pipe, making sure that @pipe is running first.
1807 */
1808static void intel_enable_plane(struct drm_i915_private *dev_priv,
1809 enum plane plane, enum pipe pipe)
1810{
1811 int reg;
1812 u32 val;
1813
1814 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1815 assert_pipe_enabled(dev_priv, pipe);
1816
1817 reg = DSPCNTR(plane);
1818 val = I915_READ(reg);
00d70b15
CW		 1819 if (val & DISPLAY_PLANE_ENABLE)
1820 return;
1821
1822 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1823 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1824 intel_wait_for_vblank(dev_priv->dev, pipe);
1825}
1826
b24e7179
JB		 1827/**
1828 * intel_disable_plane - disable a display plane
1829 * @dev_priv: i915 private structure
1830 * @plane: plane to disable
1831 * @pipe: pipe consuming the data
1832 *
1833 * Disable @plane; should be an independent operation.
1834 */
1835static void intel_disable_plane(struct drm_i915_private *dev_priv,
1836 enum plane plane, enum pipe pipe)
1837{
1838 int reg;
1839 u32 val;
1840
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
00d70b15
CW		 1843 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1844 return;
1845
1846 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1847 intel_flush_display_plane(dev_priv, plane);
1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1849}
1850
693db184
CW		 1851static bool need_vtd_wa(struct drm_device *dev)
1852{
1853#ifdef CONFIG_INTEL_IOMMU
1854 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1855 return true;
1856#endif
1857 return false;
1858}
1859
127bd2ac 1860int
48b956c5 1861intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1862 struct drm_i915_gem_object *obj,
919926ae 1863 struct intel_ring_buffer *pipelined)
6b95a207 1864{
ce453d81 1865 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1866 u32 alignment;
1867 int ret;
1868
05394f39 1869 switch (obj->tiling_mode) {
6b95a207 1870 case I915_TILING_NONE:
534843da
CW		 1871 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1872 alignment = 128 * 1024;
a6c45cf0 1873 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1874 alignment = 4 * 1024;
1875 else
1876 alignment = 64 * 1024;
6b95a207
KH		 1877 break;
1878 case I915_TILING_X:
1879 /* pin() will align the object as required by fence */
1880 alignment = 0;
1881 break;
1882 case I915_TILING_Y:
8bb6e959
DV		 1883 /* Despite that we check this in framebuffer_init userspace can
1884 * screw us over and change the tiling after the fact. Only
1885 * pinned buffers can't change their tiling. */
1886 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1887 return -EINVAL;
1888 default:
1889 BUG();
1890 }
1891
693db184
CW		 1892 /* Note that the w/a also requires 64 PTE of padding following the
1893 * bo. We currently fill all unused PTE with the shadow page and so
1894 * we should always have valid PTE following the scanout preventing
1895 * the VT-d warning.
1896 */
1897 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1898 alignment = 256 * 1024;
1899
ce453d81 1900 dev_priv->mm.interruptible = false;
2da3b9b9 1901 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1902 if (ret)
ce453d81 1903 goto err_interruptible;
6b95a207
KH		 1904
1905 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1906 * fence, whereas 965+ only requires a fence if using
1907 * framebuffer compression. For simplicity, we always install
1908 * a fence as the cost is not that onerous.
1909 */
06d98131 1910 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1911 if (ret)
1912 goto err_unpin;
1690e1eb 1913
9a5a53b3 1914 i915_gem_object_pin_fence(obj);
6b95a207 1915
ce453d81 1916 dev_priv->mm.interruptible = true;
6b95a207 1917 return 0;
48b956c5
CW		 1918
1919err_unpin:
cc98b413 1920 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1921err_interruptible:
1922 dev_priv->mm.interruptible = true;
48b956c5 1923 return ret;
6b95a207
KH		 1924}
1925
1690e1eb
CW		 1926void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1927{
1928 i915_gem_object_unpin_fence(obj);
cc98b413 1929 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1930}
1931
c2c75131
DV		 1932/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1933 * is assumed to be a power-of-two. */
bc752862
CW		 1934unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1935 unsigned int tiling_mode,
1936 unsigned int cpp,
1937 unsigned int pitch)
c2c75131 1938{
bc752862
CW		 1939 if (tiling_mode != I915_TILING_NONE) {
1940 unsigned int tile_rows, tiles;
c2c75131 1941
bc752862
CW		 1942 tile_rows = *y / 8;
1943 *y %= 8;
c2c75131 1944
bc752862
CW		 1945 tiles = *x / (512/cpp);
1946 *x %= 512/cpp;
1947
1948 return tile_rows * pitch * 8 + tiles * 4096;
1949 } else {
1950 unsigned int offset;
1951
1952 offset = *y * pitch + *x * cpp;
1953 *y = 0;
1954 *x = (offset & 4095) / cpp;
1955 return offset & -4096;
1956 }
c2c75131
DV		 1957}
1958
17638cd6
JB		 1959static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1960 int x, int y)
81255565
JB		 1961{
1962 struct drm_device *dev = crtc->dev;
1963 struct drm_i915_private *dev_priv = dev->dev_private;
1964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965 struct intel_framebuffer *intel_fb;
05394f39 1966 struct drm_i915_gem_object *obj;
81255565 1967 int plane = intel_crtc->plane;
e506a0c6 1968 unsigned long linear_offset;
81255565 1969 u32 dspcntr;
5eddb70b 1970 u32 reg;
81255565
JB		 1971
1972 switch (plane) {
1973 case 0:
1974 case 1:
1975 break;
1976 default:
84f44ce7 1977 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1978 return -EINVAL;
1979 }
1980
1981 intel_fb = to_intel_framebuffer(fb);
1982 obj = intel_fb->obj;
81255565 1983
5eddb70b
CW		 1984 reg = DSPCNTR(plane);
1985 dspcntr = I915_READ(reg);
81255565
JB		 1986 /* Mask out pixel format bits in case we change it */
1987 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1988 switch (fb->pixel_format) {
1989 case DRM_FORMAT_C8:
81255565
JB		 1990 dspcntr |= DISPPLANE_8BPP;
1991 break;
57779d06
VS		 1992 case DRM_FORMAT_XRGB1555:
1993 case DRM_FORMAT_ARGB1555:
1994 dspcntr |= DISPPLANE_BGRX555;
81255565 1995 break;
57779d06
VS		 1996 case DRM_FORMAT_RGB565:
1997 dspcntr |= DISPPLANE_BGRX565;
1998 break;
1999 case DRM_FORMAT_XRGB8888:
2000 case DRM_FORMAT_ARGB8888:
2001 dspcntr |= DISPPLANE_BGRX888;
2002 break;
2003 case DRM_FORMAT_XBGR8888:
2004 case DRM_FORMAT_ABGR8888:
2005 dspcntr |= DISPPLANE_RGBX888;
2006 break;
2007 case DRM_FORMAT_XRGB2101010:
2008 case DRM_FORMAT_ARGB2101010:
2009 dspcntr |= DISPPLANE_BGRX101010;
2010 break;
2011 case DRM_FORMAT_XBGR2101010:
2012 case DRM_FORMAT_ABGR2101010:
2013 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2014 break;
2015 default:
baba133a 2016 BUG();
81255565 2017 }
57779d06 2018
a6c45cf0 2019 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2020 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2021 dspcntr |= DISPPLANE_TILED;
2022 else
2023 dspcntr &= ~DISPPLANE_TILED;
2024 }
2025
de1aa629
VS		 2026 if (IS_G4X(dev))
2027 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2028
5eddb70b 2029 I915_WRITE(reg, dspcntr);
81255565 2030
e506a0c6 2031 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2032
c2c75131
DV		 2033 if (INTEL_INFO(dev)->gen >= 4) {
2034 intel_crtc->dspaddr_offset =
bc752862
CW		 2035 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2036 fb->bits_per_pixel / 8,
2037 fb->pitches[0]);
c2c75131
DV		 2038 linear_offset -= intel_crtc->dspaddr_offset;
2039 } else {
e506a0c6 2040 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2041 }
e506a0c6 2042
f343c5f6
BW		 2043 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2044 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2045 fb->pitches[0]);
01f2c773 2046 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2047 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2048 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2049 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2050 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2051 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2052 } else
f343c5f6 2053 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2054 POSTING_READ(reg);
81255565 2055
17638cd6
JB		 2056 return 0;
2057}
2058
2059static int ironlake_update_plane(struct drm_crtc *crtc,
2060 struct drm_framebuffer *fb, int x, int y)
2061{
2062 struct drm_device *dev = crtc->dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2065 struct intel_framebuffer *intel_fb;
2066 struct drm_i915_gem_object *obj;
2067 int plane = intel_crtc->plane;
e506a0c6 2068 unsigned long linear_offset;
17638cd6
JB		 2069 u32 dspcntr;
2070 u32 reg;
2071
2072 switch (plane) {
2073 case 0:
2074 case 1:
27f8227b 2075 case 2:
17638cd6
JB		 2076 break;
2077 default:
84f44ce7 2078 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2079 return -EINVAL;
2080 }
2081
2082 intel_fb = to_intel_framebuffer(fb);
2083 obj = intel_fb->obj;
2084
2085 reg = DSPCNTR(plane);
2086 dspcntr = I915_READ(reg);
2087 /* Mask out pixel format bits in case we change it */
2088 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2089 switch (fb->pixel_format) {
2090 case DRM_FORMAT_C8:
17638cd6
JB		 2091 dspcntr |= DISPPLANE_8BPP;
2092 break;
57779d06
VS		 2093 case DRM_FORMAT_RGB565:
2094 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2095 break;
57779d06
VS		 2096 case DRM_FORMAT_XRGB8888:
2097 case DRM_FORMAT_ARGB8888:
2098 dspcntr |= DISPPLANE_BGRX888;
2099 break;
2100 case DRM_FORMAT_XBGR8888:
2101 case DRM_FORMAT_ABGR8888:
2102 dspcntr |= DISPPLANE_RGBX888;
2103 break;
2104 case DRM_FORMAT_XRGB2101010:
2105 case DRM_FORMAT_ARGB2101010:
2106 dspcntr |= DISPPLANE_BGRX101010;
2107 break;
2108 case DRM_FORMAT_XBGR2101010:
2109 case DRM_FORMAT_ABGR2101010:
2110 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2111 break;
2112 default:
baba133a 2113 BUG();
17638cd6
JB		 2114 }
2115
2116 if (obj->tiling_mode != I915_TILING_NONE)
2117 dspcntr |= DISPPLANE_TILED;
2118 else
2119 dspcntr &= ~DISPPLANE_TILED;
2120
1f5d76db
PZ		 2121 if (IS_HASWELL(dev))
2122 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2123 else
2124 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2125
2126 I915_WRITE(reg, dspcntr);
2127
e506a0c6 2128 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2129 intel_crtc->dspaddr_offset =
bc752862
CW		 2130 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2131 fb->bits_per_pixel / 8,
2132 fb->pitches[0]);
c2c75131 2133 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2134
f343c5f6
BW		 2135 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2136 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2137 fb->pitches[0]);
01f2c773 2138 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2139 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2140 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2141 if (IS_HASWELL(dev)) {
2142 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2143 } else {
2144 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2145 I915_WRITE(DSPLINOFF(plane), linear_offset);
2146 }
17638cd6
JB		 2147 POSTING_READ(reg);
2148
2149 return 0;
2150}
2151
2152/* Assume fb object is pinned & idle & fenced and just update base pointers */
2153static int
2154intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2155 int x, int y, enum mode_set_atomic state)
2156{
2157 struct drm_device *dev = crtc->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2159
6b8e6ed0
CW		 2160 if (dev_priv->display.disable_fbc)
2161 dev_priv->display.disable_fbc(dev);
3dec0095 2162 intel_increase_pllclock(crtc);
81255565 2163
6b8e6ed0 2164 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2165}
2166
96a02917
VS		 2167void intel_display_handle_reset(struct drm_device *dev)
2168{
2169 struct drm_i915_private *dev_priv = dev->dev_private;
2170 struct drm_crtc *crtc;
2171
2172 /*
2173 * Flips in the rings have been nuked by the reset,
2174 * so complete all pending flips so that user space
2175 * will get its events and not get stuck.
2176 *
2177 * Also update the base address of all primary
2178 * planes to the the last fb to make sure we're
2179 * showing the correct fb after a reset.
2180 *
2181 * Need to make two loops over the crtcs so that we
2182 * don't try to grab a crtc mutex before the
2183 * pending_flip_queue really got woken up.
2184 */
2185
2186 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188 enum plane plane = intel_crtc->plane;
2189
2190 intel_prepare_page_flip(dev, plane);
2191 intel_finish_page_flip_plane(dev, plane);
2192 }
2193
2194 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2196
2197 mutex_lock(&crtc->mutex);
2198 if (intel_crtc->active)
2199 dev_priv->display.update_plane(crtc, crtc->fb,
2200 crtc->x, crtc->y);
2201 mutex_unlock(&crtc->mutex);
2202 }
2203}
2204
14667a4b
CW		 2205static int
2206intel_finish_fb(struct drm_framebuffer *old_fb)
2207{
2208 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2209 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2210 bool was_interruptible = dev_priv->mm.interruptible;
2211 int ret;
2212
14667a4b
CW		 2213 /* Big Hammer, we also need to ensure that any pending
2214 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2215 * current scanout is retired before unpinning the old
2216 * framebuffer.
2217 *
2218 * This should only fail upon a hung GPU, in which case we
2219 * can safely continue.
2220 */
2221 dev_priv->mm.interruptible = false;
2222 ret = i915_gem_object_finish_gpu(obj);
2223 dev_priv->mm.interruptible = was_interruptible;
2224
2225 return ret;
2226}
2227
198598d0
VS		 2228static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2229{
2230 struct drm_device *dev = crtc->dev;
2231 struct drm_i915_master_private *master_priv;
2232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2233
2234 if (!dev->primary->master)
2235 return;
2236
2237 master_priv = dev->primary->master->driver_priv;
2238 if (!master_priv->sarea_priv)
2239 return;
2240
2241 switch (intel_crtc->pipe) {
2242 case 0:
2243 master_priv->sarea_priv->pipeA_x = x;
2244 master_priv->sarea_priv->pipeA_y = y;
2245 break;
2246 case 1:
2247 master_priv->sarea_priv->pipeB_x = x;
2248 master_priv->sarea_priv->pipeB_y = y;
2249 break;
2250 default:
2251 break;
2252 }
2253}
2254
5c3b82e2 2255static int
3c4fdcfb 2256intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2257 struct drm_framebuffer *fb)
79e53945
JB		 2258{
2259 struct drm_device *dev = crtc->dev;
6b8e6ed0 2260 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2262 struct drm_framebuffer *old_fb;
5c3b82e2 2263 int ret;
79e53945
JB		 2264
2265 /* no fb bound */
94352cf9 2266 if (!fb) {
a5071c2f 2267 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2268 return 0;
2269 }
2270
7eb552ae 2271 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2272 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2273 plane_name(intel_crtc->plane),
2274 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2275 return -EINVAL;
79e53945
JB		 2276 }
2277
5c3b82e2 2278 mutex_lock(&dev->struct_mutex);
265db958 2279 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2280 to_intel_framebuffer(fb)->obj,
919926ae 2281 NULL);
5c3b82e2
CW		 2282 if (ret != 0) {
2283 mutex_unlock(&dev->struct_mutex);
a5071c2f 2284 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2285 return ret;
2286 }
79e53945 2287
4d6a3e63
JB		 2288 /* Update pipe size and adjust fitter if needed */
2289 if (i915_fastboot) {
2290 I915_WRITE(PIPESRC(intel_crtc->pipe),
2291 ((crtc->mode.hdisplay - 1) << 16) |
2292 (crtc->mode.vdisplay - 1));
fd4daa9c 2293 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2294 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2295 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2296 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2297 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2298 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2299 }
2300 }
2301
94352cf9 2302 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2303 if (ret) {
94352cf9 2304 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2305 mutex_unlock(&dev->struct_mutex);
a5071c2f 2306 DRM_ERROR("failed to update base address\n");
4e6cfefc 2307 return ret;
79e53945 2308 }
3c4fdcfb 2309
94352cf9
DV		 2310 old_fb = crtc->fb;
2311 crtc->fb = fb;
6c4c86f5
DV		 2312 crtc->x = x;
2313 crtc->y = y;
94352cf9 2314
b7f1de28 2315 if (old_fb) {
d7697eea
DV		 2316 if (intel_crtc->active && old_fb != fb)
2317 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2318 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2319 }
652c393a 2320
6b8e6ed0 2321 intel_update_fbc(dev);
4906557e 2322 intel_edp_psr_update(dev);
5c3b82e2 2323 mutex_unlock(&dev->struct_mutex);
79e53945 2324
198598d0 2325 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2326
2327 return 0;
79e53945
JB		 2328}
2329
5e84e1a4
ZW		 2330static void intel_fdi_normal_train(struct drm_crtc *crtc)
2331{
2332 struct drm_device *dev = crtc->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2335 int pipe = intel_crtc->pipe;
2336 u32 reg, temp;
2337
2338 /* enable normal train */
2339 reg = FDI_TX_CTL(pipe);
2340 temp = I915_READ(reg);
61e499bf 2341 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2342 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2343 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2344 } else {
2345 temp &= ~FDI_LINK_TRAIN_NONE;
2346 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2347 }
5e84e1a4
ZW		 2348 I915_WRITE(reg, temp);
2349
2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
2352 if (HAS_PCH_CPT(dev)) {
2353 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2354 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2355 } else {
2356 temp &= ~FDI_LINK_TRAIN_NONE;
2357 temp |= FDI_LINK_TRAIN_NONE;
2358 }
2359 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2360
2361 /* wait one idle pattern time */
2362 POSTING_READ(reg);
2363 udelay(1000);
357555c0
JB		 2364
2365 /* IVB wants error correction enabled */
2366 if (IS_IVYBRIDGE(dev))
2367 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2368 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2369}
2370
1e833f40
DV		 2371static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2372{
2373 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2374}
2375
01a415fd
DV		 2376static void ivb_modeset_global_resources(struct drm_device *dev)
2377{
2378 struct drm_i915_private *dev_priv = dev->dev_private;
2379 struct intel_crtc *pipe_B_crtc =
2380 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2381 struct intel_crtc *pipe_C_crtc =
2382 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2383 uint32_t temp;
2384
1e833f40
DV		 2385 /*
2386 * When everything is off disable fdi C so that we could enable fdi B
2387 * with all lanes. Note that we don't care about enabled pipes without
2388 * an enabled pch encoder.
2389 */
2390 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2391 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2392 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2394
2395 temp = I915_READ(SOUTH_CHICKEN1);
2396 temp &= ~FDI_BC_BIFURCATION_SELECT;
2397 DRM_DEBUG_KMS("disabling fdi C rx\n");
2398 I915_WRITE(SOUTH_CHICKEN1, temp);
2399 }
2400}
2401
8db9d77b
ZW		 2402/* The FDI link training functions for ILK/Ibexpeak. */
2403static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2404{
2405 struct drm_device *dev = crtc->dev;
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2408 int pipe = intel_crtc->pipe;
0fc932b8 2409 int plane = intel_crtc->plane;
5eddb70b 2410 u32 reg, temp, tries;
8db9d77b 2411
0fc932b8
JB		 2412 /* FDI needs bits from pipe & plane first */
2413 assert_pipe_enabled(dev_priv, pipe);
2414 assert_plane_enabled(dev_priv, plane);
2415
e1a44743
AJ		 2416 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2417 for train result */
5eddb70b
CW		 2418 reg = FDI_RX_IMR(pipe);
2419 temp = I915_READ(reg);
e1a44743
AJ		 2420 temp &= ~FDI_RX_SYMBOL_LOCK;
2421 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2422 I915_WRITE(reg, temp);
2423 I915_READ(reg);
e1a44743
AJ		 2424 udelay(150);
2425
8db9d77b 2426 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2427 reg = FDI_TX_CTL(pipe);
2428 temp = I915_READ(reg);
627eb5a3
DV		 2429 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2430 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2431 temp &= ~FDI_LINK_TRAIN_NONE;
2432 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2433 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2434
5eddb70b
CW		 2435 reg = FDI_RX_CTL(pipe);
2436 temp = I915_READ(reg);
8db9d77b
ZW		 2437 temp &= ~FDI_LINK_TRAIN_NONE;
2438 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2439 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2440
2441 POSTING_READ(reg);
8db9d77b
ZW		 2442 udelay(150);
2443
5b2adf89 2444 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2445 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2447 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2448
5eddb70b 2449 reg = FDI_RX_IIR(pipe);
e1a44743 2450 for (tries = 0; tries < 5; tries++) {
5eddb70b 2451 temp = I915_READ(reg);
8db9d77b
ZW		 2452 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2453
2454 if ((temp & FDI_RX_BIT_LOCK)) {
2455 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2456 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2457 break;
2458 }
8db9d77b 2459 }
e1a44743 2460 if (tries == 5)
5eddb70b 2461 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2462
2463 /* Train 2 */
5eddb70b
CW		 2464 reg = FDI_TX_CTL(pipe);
2465 temp = I915_READ(reg);
8db9d77b
ZW		 2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2468 I915_WRITE(reg, temp);
8db9d77b 2469
5eddb70b
CW		 2470 reg = FDI_RX_CTL(pipe);
2471 temp = I915_READ(reg);
8db9d77b
ZW		 2472 temp &= ~FDI_LINK_TRAIN_NONE;
2473 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2474 I915_WRITE(reg, temp);
8db9d77b 2475
5eddb70b
CW		 2476 POSTING_READ(reg);
2477 udelay(150);
8db9d77b 2478
5eddb70b 2479 reg = FDI_RX_IIR(pipe);
e1a44743 2480 for (tries = 0; tries < 5; tries++) {
5eddb70b 2481 temp = I915_READ(reg);
8db9d77b
ZW		 2482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2483
2484 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2485 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2486 DRM_DEBUG_KMS("FDI train 2 done.\n");
2487 break;
2488 }
8db9d77b 2489 }
e1a44743 2490 if (tries == 5)
5eddb70b 2491 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2492
2493 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2494
8db9d77b
ZW		 2495}
2496
0206e353 2497static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2498 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2499 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2500 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2501 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2502};
2503
2504/* The FDI link training functions for SNB/Cougarpoint. */
2505static void gen6_fdi_link_train(struct drm_crtc *crtc)
2506{
2507 struct drm_device *dev = crtc->dev;
2508 struct drm_i915_private *dev_priv = dev->dev_private;
2509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2510 int pipe = intel_crtc->pipe;
fa37d39e 2511 u32 reg, temp, i, retry;
8db9d77b 2512
e1a44743
AJ		 2513 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2514 for train result */
5eddb70b
CW		 2515 reg = FDI_RX_IMR(pipe);
2516 temp = I915_READ(reg);
e1a44743
AJ		 2517 temp &= ~FDI_RX_SYMBOL_LOCK;
2518 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2519 I915_WRITE(reg, temp);
2520
2521 POSTING_READ(reg);
e1a44743
AJ		 2522 udelay(150);
2523
8db9d77b 2524 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2525 reg = FDI_TX_CTL(pipe);
2526 temp = I915_READ(reg);
627eb5a3
DV		 2527 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2528 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_1;
2531 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2532 /* SNB-B */
2533 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2534 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2535
d74cf324
DV		 2536 I915_WRITE(FDI_RX_MISC(pipe),
2537 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2538
5eddb70b
CW		 2539 reg = FDI_RX_CTL(pipe);
2540 temp = I915_READ(reg);
8db9d77b
ZW		 2541 if (HAS_PCH_CPT(dev)) {
2542 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2543 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2544 } else {
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_1;
2547 }
5eddb70b
CW		 2548 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2549
2550 POSTING_READ(reg);
8db9d77b
ZW		 2551 udelay(150);
2552
0206e353 2553 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2554 reg = FDI_TX_CTL(pipe);
2555 temp = I915_READ(reg);
8db9d77b
ZW		 2556 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2557 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2558 I915_WRITE(reg, temp);
2559
2560 POSTING_READ(reg);
8db9d77b
ZW		 2561 udelay(500);
2562
fa37d39e
SP		 2563 for (retry = 0; retry < 5; retry++) {
2564 reg = FDI_RX_IIR(pipe);
2565 temp = I915_READ(reg);
2566 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2567 if (temp & FDI_RX_BIT_LOCK) {
2568 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2569 DRM_DEBUG_KMS("FDI train 1 done.\n");
2570 break;
2571 }
2572 udelay(50);
8db9d77b 2573 }
fa37d39e
SP		 2574 if (retry < 5)
2575 break;
8db9d77b
ZW		 2576 }
2577 if (i == 4)
5eddb70b 2578 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2579
2580 /* Train 2 */
5eddb70b
CW		 2581 reg = FDI_TX_CTL(pipe);
2582 temp = I915_READ(reg);
8db9d77b
ZW		 2583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_2;
2585 if (IS_GEN6(dev)) {
2586 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587 /* SNB-B */
2588 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2589 }
5eddb70b 2590 I915_WRITE(reg, temp);
8db9d77b 2591
5eddb70b
CW		 2592 reg = FDI_RX_CTL(pipe);
2593 temp = I915_READ(reg);
8db9d77b
ZW		 2594 if (HAS_PCH_CPT(dev)) {
2595 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2597 } else {
2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_2;
2600 }
5eddb70b
CW		 2601 I915_WRITE(reg, temp);
2602
2603 POSTING_READ(reg);
8db9d77b
ZW		 2604 udelay(150);
2605
0206e353 2606 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2607 reg = FDI_TX_CTL(pipe);
2608 temp = I915_READ(reg);
8db9d77b
ZW		 2609 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2611 I915_WRITE(reg, temp);
2612
2613 POSTING_READ(reg);
8db9d77b
ZW		 2614 udelay(500);
2615
fa37d39e
SP		 2616 for (retry = 0; retry < 5; retry++) {
2617 reg = FDI_RX_IIR(pipe);
2618 temp = I915_READ(reg);
2619 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2620 if (temp & FDI_RX_SYMBOL_LOCK) {
2621 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2622 DRM_DEBUG_KMS("FDI train 2 done.\n");
2623 break;
2624 }
2625 udelay(50);
8db9d77b 2626 }
fa37d39e
SP		 2627 if (retry < 5)
2628 break;
8db9d77b
ZW		 2629 }
2630 if (i == 4)
5eddb70b 2631 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2632
2633 DRM_DEBUG_KMS("FDI train done.\n");
2634}
2635
357555c0
JB		 2636/* Manual link training for Ivy Bridge A0 parts */
2637static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2638{
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2642 int pipe = intel_crtc->pipe;
139ccd3f 2643 u32 reg, temp, i, j;
357555c0
JB		 2644
2645 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2646 for train result */
2647 reg = FDI_RX_IMR(pipe);
2648 temp = I915_READ(reg);
2649 temp &= ~FDI_RX_SYMBOL_LOCK;
2650 temp &= ~FDI_RX_BIT_LOCK;
2651 I915_WRITE(reg, temp);
2652
2653 POSTING_READ(reg);
2654 udelay(150);
2655
01a415fd
DV		 2656 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2657 I915_READ(FDI_RX_IIR(pipe)));
2658
139ccd3f
JB		 2659 /* Try each vswing and preemphasis setting twice before moving on */
2660 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2661 /* disable first in case we need to retry */
2662 reg = FDI_TX_CTL(pipe);
2663 temp = I915_READ(reg);
2664 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2665 temp &= ~FDI_TX_ENABLE;
2666 I915_WRITE(reg, temp);
357555c0 2667
139ccd3f
JB		 2668 reg = FDI_RX_CTL(pipe);
2669 temp = I915_READ(reg);
2670 temp &= ~FDI_LINK_TRAIN_AUTO;
2671 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2672 temp &= ~FDI_RX_ENABLE;
2673 I915_WRITE(reg, temp);
357555c0 2674
139ccd3f 2675 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2676 reg = FDI_TX_CTL(pipe);
2677 temp = I915_READ(reg);
139ccd3f
JB		 2678 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2679 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2680 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2681 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2682 temp |= snb_b_fdi_train_param[j/2];
2683 temp |= FDI_COMPOSITE_SYNC;
2684 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2685
139ccd3f
JB		 2686 I915_WRITE(FDI_RX_MISC(pipe),
2687 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2688
139ccd3f 2689 reg = FDI_RX_CTL(pipe);
357555c0 2690 temp = I915_READ(reg);
139ccd3f
JB		 2691 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2692 temp |= FDI_COMPOSITE_SYNC;
2693 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2694
139ccd3f
JB		 2695 POSTING_READ(reg);
2696 udelay(1); /* should be 0.5us */
357555c0 2697
139ccd3f
JB		 2698 for (i = 0; i < 4; i++) {
2699 reg = FDI_RX_IIR(pipe);
2700 temp = I915_READ(reg);
2701 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2702
139ccd3f
JB		 2703 if (temp & FDI_RX_BIT_LOCK ||
2704 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2705 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2706 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2707 i);
2708 break;
2709 }
2710 udelay(1); /* should be 0.5us */
2711 }
2712 if (i == 4) {
2713 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2714 continue;
2715 }
357555c0 2716
139ccd3f 2717 /* Train 2 */
357555c0
JB		 2718 reg = FDI_TX_CTL(pipe);
2719 temp = I915_READ(reg);
139ccd3f
JB		 2720 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2721 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2722 I915_WRITE(reg, temp);
2723
2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2727 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2728 I915_WRITE(reg, temp);
2729
2730 POSTING_READ(reg);
139ccd3f 2731 udelay(2); /* should be 1.5us */
357555c0 2732
139ccd3f
JB		 2733 for (i = 0; i < 4; i++) {
2734 reg = FDI_RX_IIR(pipe);
2735 temp = I915_READ(reg);
2736 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2737
139ccd3f
JB		 2738 if (temp & FDI_RX_SYMBOL_LOCK ||
2739 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2740 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2741 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2742 i);
2743 goto train_done;
2744 }
2745 udelay(2); /* should be 1.5us */
357555c0 2746 }
139ccd3f
JB		 2747 if (i == 4)
2748 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2749 }
357555c0 2750
139ccd3f 2751train_done:
357555c0
JB		 2752 DRM_DEBUG_KMS("FDI train done.\n");
2753}
2754
88cefb6c 2755static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2756{
88cefb6c 2757 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2758 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2759 int pipe = intel_crtc->pipe;
5eddb70b 2760 u32 reg, temp;
79e53945 2761
c64e311e 2762
c98e9dcf 2763 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2764 reg = FDI_RX_CTL(pipe);
2765 temp = I915_READ(reg);
627eb5a3
DV		 2766 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2767 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2768 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2769 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2770
2771 POSTING_READ(reg);
c98e9dcf
JB		 2772 udelay(200);
2773
2774 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2775 temp = I915_READ(reg);
2776 I915_WRITE(reg, temp | FDI_PCDCLK);
2777
2778 POSTING_READ(reg);
c98e9dcf
JB		 2779 udelay(200);
2780
20749730
PZ		 2781 /* Enable CPU FDI TX PLL, always on for Ironlake */
2782 reg = FDI_TX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2785 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2786
20749730
PZ		 2787 POSTING_READ(reg);
2788 udelay(100);
6be4a607 2789 }
0e23b99d
JB		 2790}
2791
88cefb6c
DV		 2792static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2793{
2794 struct drm_device *dev = intel_crtc->base.dev;
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796 int pipe = intel_crtc->pipe;
2797 u32 reg, temp;
2798
2799 /* Switch from PCDclk to Rawclk */
2800 reg = FDI_RX_CTL(pipe);
2801 temp = I915_READ(reg);
2802 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2803
2804 /* Disable CPU FDI TX PLL */
2805 reg = FDI_TX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2808
2809 POSTING_READ(reg);
2810 udelay(100);
2811
2812 reg = FDI_RX_CTL(pipe);
2813 temp = I915_READ(reg);
2814 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2815
2816 /* Wait for the clocks to turn off. */
2817 POSTING_READ(reg);
2818 udelay(100);
2819}
2820
0fc932b8
JB		 2821static void ironlake_fdi_disable(struct drm_crtc *crtc)
2822{
2823 struct drm_device *dev = crtc->dev;
2824 struct drm_i915_private *dev_priv = dev->dev_private;
2825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2826 int pipe = intel_crtc->pipe;
2827 u32 reg, temp;
2828
2829 /* disable CPU FDI tx and PCH FDI rx */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2833 POSTING_READ(reg);
2834
2835 reg = FDI_RX_CTL(pipe);
2836 temp = I915_READ(reg);
2837 temp &= ~(0x7 << 16);
dfd07d72 2838 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2839 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2840
2841 POSTING_READ(reg);
2842 udelay(100);
2843
2844 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2845 if (HAS_PCH_IBX(dev)) {
2846 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2847 }
0fc932b8
JB		 2848
2849 /* still set train pattern 1 */
2850 reg = FDI_TX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 temp &= ~FDI_LINK_TRAIN_NONE;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1;
2854 I915_WRITE(reg, temp);
2855
2856 reg = FDI_RX_CTL(pipe);
2857 temp = I915_READ(reg);
2858 if (HAS_PCH_CPT(dev)) {
2859 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2860 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2861 } else {
2862 temp &= ~FDI_LINK_TRAIN_NONE;
2863 temp |= FDI_LINK_TRAIN_PATTERN_1;
2864 }
2865 /* BPC in FDI rx is consistent with that in PIPECONF */
2866 temp &= ~(0x07 << 16);
dfd07d72 2867 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2868 I915_WRITE(reg, temp);
2869
2870 POSTING_READ(reg);
2871 udelay(100);
2872}
2873
5bb61643
CW		 2874static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2875{
2876 struct drm_device *dev = crtc->dev;
2877 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2879 unsigned long flags;
2880 bool pending;
2881
10d83730
VS		 2882 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2883 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2884 return false;
2885
2886 spin_lock_irqsave(&dev->event_lock, flags);
2887 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2888 spin_unlock_irqrestore(&dev->event_lock, flags);
2889
2890 return pending;
2891}
2892
e6c3a2a6
CW		 2893static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2894{
0f91128d 2895 struct drm_device *dev = crtc->dev;
5bb61643 2896 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2897
2898 if (crtc->fb == NULL)
2899 return;
2900
2c10d571
DV		 2901 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2902
5bb61643
CW		 2903 wait_event(dev_priv->pending_flip_queue,
2904 !intel_crtc_has_pending_flip(crtc));
2905
0f91128d
CW		 2906 mutex_lock(&dev->struct_mutex);
2907 intel_finish_fb(crtc->fb);
2908 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2909}
2910
e615efe4
ED		 2911/* Program iCLKIP clock to the desired frequency */
2912static void lpt_program_iclkip(struct drm_crtc *crtc)
2913{
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
12d7ceed 2916 int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
e615efe4
ED		 2917 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2918 u32 temp;
2919
09153000
DV		 2920 mutex_lock(&dev_priv->dpio_lock);
2921
e615efe4
ED		 2922 /* It is necessary to ungate the pixclk gate prior to programming
2923 * the divisors, and gate it back when it is done.
2924 */
2925 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2926
2927 /* Disable SSCCTL */
2928 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2929 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2930 SBI_SSCCTL_DISABLE,
2931 SBI_ICLK);
e615efe4
ED		 2932
2933 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2934 if (clock == 20000) {
e615efe4
ED		 2935 auxdiv = 1;
2936 divsel = 0x41;
2937 phaseinc = 0x20;
2938 } else {
2939 /* The iCLK virtual clock root frequency is in MHz,
12d7ceed 2940 * but the adjusted_mode->clock in in KHz. To get the divisors,
e615efe4
ED		 2941 * it is necessary to divide one by another, so we
2942 * convert the virtual clock precision to KHz here for higher
2943 * precision.
2944 */
2945 u32 iclk_virtual_root_freq = 172800 * 1000;
2946 u32 iclk_pi_range = 64;
2947 u32 desired_divisor, msb_divisor_value, pi_value;
2948
12d7ceed 2949 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2950 msb_divisor_value = desired_divisor / iclk_pi_range;
2951 pi_value = desired_divisor % iclk_pi_range;
2952
2953 auxdiv = 0;
2954 divsel = msb_divisor_value - 2;
2955 phaseinc = pi_value;
2956 }
2957
2958 /* This should not happen with any sane values */
2959 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2960 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2961 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2962 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2963
2964 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2965 clock,
e615efe4
ED		 2966 auxdiv,
2967 divsel,
2968 phasedir,
2969 phaseinc);
2970
2971 /* Program SSCDIVINTPHASE6 */
988d6ee8 2972 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2973 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2974 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2975 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2976 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2977 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2978 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2979 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2980
2981 /* Program SSCAUXDIV */
988d6ee8 2982 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2983 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2984 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2985 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2986
2987 /* Enable modulator and associated divider */
988d6ee8 2988 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2989 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2990 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2991
2992 /* Wait for initialization time */
2993 udelay(24);
2994
2995 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2996
2997 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2998}
2999
275f01b2
DV		 3000static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3001 enum pipe pch_transcoder)
3002{
3003 struct drm_device *dev = crtc->base.dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3006
3007 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3008 I915_READ(HTOTAL(cpu_transcoder)));
3009 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3010 I915_READ(HBLANK(cpu_transcoder)));
3011 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3012 I915_READ(HSYNC(cpu_transcoder)));
3013
3014 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3015 I915_READ(VTOTAL(cpu_transcoder)));
3016 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3017 I915_READ(VBLANK(cpu_transcoder)));
3018 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3019 I915_READ(VSYNC(cpu_transcoder)));
3020 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3021 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3022}
3023
f67a559d
JB		 3024/*
3025 * Enable PCH resources required for PCH ports:
3026 * - PCH PLLs
3027 * - FDI training & RX/TX
3028 * - update transcoder timings
3029 * - DP transcoding bits
3030 * - transcoder
3031 */
3032static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3033{
3034 struct drm_device *dev = crtc->dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037 int pipe = intel_crtc->pipe;
ee7b9f93 3038 u32 reg, temp;
2c07245f 3039
ab9412ba 3040 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3041
cd986abb
DV		 3042 /* Write the TU size bits before fdi link training, so that error
3043 * detection works. */
3044 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3045 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3046
c98e9dcf 3047 /* For PCH output, training FDI link */
674cf967 3048 dev_priv->display.fdi_link_train(crtc);
2c07245f 3049
3ad8a208
DV		 3050 /* We need to program the right clock selection before writing the pixel
3051 * mutliplier into the DPLL. */
303b81e0 3052 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3053 u32 sel;
4b645f14 3054
c98e9dcf 3055 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3056 temp |= TRANS_DPLL_ENABLE(pipe);
3057 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3058 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3059 temp |= sel;
3060 else
3061 temp &= ~sel;
c98e9dcf 3062 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3063 }
5eddb70b 3064
3ad8a208
DV		 3065 /* XXX: pch pll's can be enabled any time before we enable the PCH
3066 * transcoder, and we actually should do this to not upset any PCH
3067 * transcoder that already use the clock when we share it.
3068 *
3069 * Note that enable_shared_dpll tries to do the right thing, but
3070 * get_shared_dpll unconditionally resets the pll - we need that to have
3071 * the right LVDS enable sequence. */
3072 ironlake_enable_shared_dpll(intel_crtc);
3073
d9b6cb56
JB		 3074 /* set transcoder timing, panel must allow it */
3075 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3076 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3077
303b81e0 3078 intel_fdi_normal_train(crtc);
5e84e1a4 3079
c98e9dcf
JB		 3080 /* For PCH DP, enable TRANS_DP_CTL */
3081 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3082 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3083 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3084 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3085 reg = TRANS_DP_CTL(pipe);
3086 temp = I915_READ(reg);
3087 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3088 TRANS_DP_SYNC_MASK |
3089 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3090 temp |= (TRANS_DP_OUTPUT_ENABLE |
3091 TRANS_DP_ENH_FRAMING);
9325c9f0 3092 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3093
3094 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3095 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3096 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3097 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3098
3099 switch (intel_trans_dp_port_sel(crtc)) {
3100 case PCH_DP_B:
5eddb70b 3101 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3102 break;
3103 case PCH_DP_C:
5eddb70b 3104 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3105 break;
3106 case PCH_DP_D:
5eddb70b 3107 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3108 break;
3109 default:
e95d41e1 3110 BUG();
32f9d658 3111 }
2c07245f 3112
5eddb70b 3113 I915_WRITE(reg, temp);
6be4a607 3114 }
b52eb4dc 3115
b8a4f404 3116 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3117}
3118
1507e5bd
PZ		 3119static void lpt_pch_enable(struct drm_crtc *crtc)
3120{
3121 struct drm_device *dev = crtc->dev;
3122 struct drm_i915_private *dev_priv = dev->dev_private;
3123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3124 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3125
ab9412ba 3126 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3127
8c52b5e8 3128 lpt_program_iclkip(crtc);
1507e5bd 3129
0540e488 3130 /* Set transcoder timing. */
275f01b2 3131 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3132
937bb610 3133 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3134}
3135
e2b78267 3136static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3137{
e2b78267 3138 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3139
3140 if (pll == NULL)
3141 return;
3142
3143 if (pll->refcount == 0) {
46edb027 3144 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3145 return;
3146 }
3147
f4a091c7
DV		 3148 if (--pll->refcount == 0) {
3149 WARN_ON(pll->on);
3150 WARN_ON(pll->active);
3151 }
3152
a43f6e0f 3153 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3154}
3155
b89a1d39 3156static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3157{
e2b78267
DV		 3158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3159 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3160 enum intel_dpll_id i;
ee7b9f93 3161
ee7b9f93 3162 if (pll) {
46edb027
DV		 3163 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3164 crtc->base.base.id, pll->name);
e2b78267 3165 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3166 }
3167
98b6bd99
DV		 3168 if (HAS_PCH_IBX(dev_priv->dev)) {
3169 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3170 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3171 pll = &dev_priv->shared_dplls[i];
98b6bd99 3172
46edb027
DV		 3173 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3174 crtc->base.base.id, pll->name);
98b6bd99
DV		 3175
3176 goto found;
3177 }
3178
e72f9fbf
DV		 3179 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3180 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3181
3182 /* Only want to check enabled timings first */
3183 if (pll->refcount == 0)
3184 continue;
3185
b89a1d39
DV		 3186 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3187 sizeof(pll->hw_state)) == 0) {
46edb027 3188 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3189 crtc->base.base.id,
46edb027 3190 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3191
3192 goto found;
3193 }
3194 }
3195
3196 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3197 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3198 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3199 if (pll->refcount == 0) {
46edb027
DV		 3200 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3201 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3202 goto found;
3203 }
3204 }
3205
3206 return NULL;
3207
3208found:
a43f6e0f 3209 crtc->config.shared_dpll = i;
46edb027
DV		 3210 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3211 pipe_name(crtc->pipe));
ee7b9f93 3212
cdbd2316 3213 if (pll->active == 0) {
66e985c0
DV		 3214 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3215 sizeof(pll->hw_state));
3216
46edb027 3217 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3218 WARN_ON(pll->on);
e9d6944e 3219 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3220
15bdd4cf 3221 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3222 }
3223 pll->refcount++;
e04c7350 3224
ee7b9f93
JB		 3225 return pll;
3226}
3227
a1520318 3228static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3229{
3230 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3231 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3232 u32 temp;
3233
3234 temp = I915_READ(dslreg);
3235 udelay(500);
3236 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3237 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3238 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3239 }
3240}
3241
b074cec8
JB		 3242static void ironlake_pfit_enable(struct intel_crtc *crtc)
3243{
3244 struct drm_device *dev = crtc->base.dev;
3245 struct drm_i915_private *dev_priv = dev->dev_private;
3246 int pipe = crtc->pipe;
3247
fd4daa9c 3248 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3249 /* Force use of hard-coded filter coefficients
3250 * as some pre-programmed values are broken,
3251 * e.g. x201.
3252 */
3253 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3254 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3255 PF_PIPE_SEL_IVB(pipe));
3256 else
3257 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3258 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3259 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3260 }
3261}
3262
bb53d4ae
VS		 3263static void intel_enable_planes(struct drm_crtc *crtc)
3264{
3265 struct drm_device *dev = crtc->dev;
3266 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3267 struct intel_plane *intel_plane;
3268
3269 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3270 if (intel_plane->pipe == pipe)
3271 intel_plane_restore(&intel_plane->base);
3272}
3273
3274static void intel_disable_planes(struct drm_crtc *crtc)
3275{
3276 struct drm_device *dev = crtc->dev;
3277 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3278 struct intel_plane *intel_plane;
3279
3280 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3281 if (intel_plane->pipe == pipe)
3282 intel_plane_disable(&intel_plane->base);
3283}
3284
d77e4531
PZ		 3285static void hsw_enable_ips(struct intel_crtc *crtc)
3286{
3287 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3288
3289 if (!crtc->config.ips_enabled)
3290 return;
3291
3292 /* We can only enable IPS after we enable a plane and wait for a vblank.
3293 * We guarantee that the plane is enabled by calling intel_enable_ips
3294 * only after intel_enable_plane. And intel_enable_plane already waits
3295 * for a vblank, so all we need to do here is to enable the IPS bit. */
3296 assert_plane_enabled(dev_priv, crtc->plane);
3297 I915_WRITE(IPS_CTL, IPS_ENABLE);
3298}
3299
3300static void hsw_disable_ips(struct intel_crtc *crtc)
3301{
3302 struct drm_device *dev = crtc->base.dev;
3303 struct drm_i915_private *dev_priv = dev->dev_private;
3304
3305 if (!crtc->config.ips_enabled)
3306 return;
3307
3308 assert_plane_enabled(dev_priv, crtc->plane);
3309 I915_WRITE(IPS_CTL, 0);
3310 POSTING_READ(IPS_CTL);
3311
3312 /* We need to wait for a vblank before we can disable the plane. */
3313 intel_wait_for_vblank(dev, crtc->pipe);
3314}
3315
3316/** Loads the palette/gamma unit for the CRTC with the prepared values */
3317static void intel_crtc_load_lut(struct drm_crtc *crtc)
3318{
3319 struct drm_device *dev = crtc->dev;
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3322 enum pipe pipe = intel_crtc->pipe;
3323 int palreg = PALETTE(pipe);
3324 int i;
3325 bool reenable_ips = false;
3326
3327 /* The clocks have to be on to load the palette. */
3328 if (!crtc->enabled || !intel_crtc->active)
3329 return;
3330
3331 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3332 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3333 assert_dsi_pll_enabled(dev_priv);
3334 else
3335 assert_pll_enabled(dev_priv, pipe);
3336 }
3337
3338 /* use legacy palette for Ironlake */
3339 if (HAS_PCH_SPLIT(dev))
3340 palreg = LGC_PALETTE(pipe);
3341
3342 /* Workaround : Do not read or write the pipe palette/gamma data while
3343 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3344 */
3345 if (intel_crtc->config.ips_enabled &&
3346 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3347 GAMMA_MODE_MODE_SPLIT)) {
3348 hsw_disable_ips(intel_crtc);
3349 reenable_ips = true;
3350 }
3351
3352 for (i = 0; i < 256; i++) {
3353 I915_WRITE(palreg + 4 * i,
3354 (intel_crtc->lut_r[i] << 16) |
3355 (intel_crtc->lut_g[i] << 8) |
3356 intel_crtc->lut_b[i]);
3357 }
3358
3359 if (reenable_ips)
3360 hsw_enable_ips(intel_crtc);
3361}
3362
f67a559d
JB		 3363static void ironlake_crtc_enable(struct drm_crtc *crtc)
3364{
3365 struct drm_device *dev = crtc->dev;
3366 struct drm_i915_private *dev_priv = dev->dev_private;
3367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3368 struct intel_encoder *encoder;
f67a559d
JB		 3369 int pipe = intel_crtc->pipe;
3370 int plane = intel_crtc->plane;
f67a559d 3371
08a48469
DV		 3372 WARN_ON(!crtc->enabled);
3373
f67a559d
JB		 3374 if (intel_crtc->active)
3375 return;
3376
3377 intel_crtc->active = true;
8664281b
PZ		 3378
3379 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3380 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3381
f6736a1a 3382 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3383 if (encoder->pre_enable)
3384 encoder->pre_enable(encoder);
f67a559d 3385
5bfe2ac0 3386 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3387 /* Note: FDI PLL enabling _must_ be done before we enable the
3388 * cpu pipes, hence this is separate from all the other fdi/pch
3389 * enabling. */
88cefb6c 3390 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3391 } else {
3392 assert_fdi_tx_disabled(dev_priv, pipe);
3393 assert_fdi_rx_disabled(dev_priv, pipe);
3394 }
f67a559d 3395
b074cec8 3396 ironlake_pfit_enable(intel_crtc);
f67a559d 3397
9c54c0dd
JB		 3398 /*
3399 * On ILK+ LUT must be loaded before the pipe is running but with
3400 * clocks enabled
3401 */
3402 intel_crtc_load_lut(crtc);
3403
f37fcc2a 3404 intel_update_watermarks(crtc);
5bfe2ac0 3405 intel_enable_pipe(dev_priv, pipe,
23538ef1 3406 intel_crtc->config.has_pch_encoder, false);
f67a559d 3407 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3408 intel_enable_planes(crtc);
5c38d48c 3409 intel_crtc_update_cursor(crtc, true);
f67a559d 3410
5bfe2ac0 3411 if (intel_crtc->config.has_pch_encoder)
f67a559d 3412 ironlake_pch_enable(crtc);
c98e9dcf 3413
d1ebd816 3414 mutex_lock(&dev->struct_mutex);
bed4a673 3415 intel_update_fbc(dev);
d1ebd816
BW		 3416 mutex_unlock(&dev->struct_mutex);
3417
fa5c73b1
DV		 3418 for_each_encoder_on_crtc(dev, crtc, encoder)
3419 encoder->enable(encoder);
61b77ddd
DV		 3420
3421 if (HAS_PCH_CPT(dev))
a1520318 3422 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3423
3424 /*
3425 * There seems to be a race in PCH platform hw (at least on some
3426 * outputs) where an enabled pipe still completes any pageflip right
3427 * away (as if the pipe is off) instead of waiting for vblank. As soon
3428 * as the first vblank happend, everything works as expected. Hence just
3429 * wait for one vblank before returning to avoid strange things
3430 * happening.
3431 */
3432 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3433}
3434
42db64ef
PZ		 3435/* IPS only exists on ULT machines and is tied to pipe A. */
3436static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3437{
f5adf94e 3438 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3439}
3440
4f771f10
PZ		 3441static void haswell_crtc_enable(struct drm_crtc *crtc)
3442{
3443 struct drm_device *dev = crtc->dev;
3444 struct drm_i915_private *dev_priv = dev->dev_private;
3445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3446 struct intel_encoder *encoder;
3447 int pipe = intel_crtc->pipe;
3448 int plane = intel_crtc->plane;
4f771f10
PZ		 3449
3450 WARN_ON(!crtc->enabled);
3451
3452 if (intel_crtc->active)
3453 return;
3454
3455 intel_crtc->active = true;
8664281b
PZ		 3456
3457 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3458 if (intel_crtc->config.has_pch_encoder)
3459 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3460
5bfe2ac0 3461 if (intel_crtc->config.has_pch_encoder)
04945641 3462 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3463
3464 for_each_encoder_on_crtc(dev, crtc, encoder)
3465 if (encoder->pre_enable)
3466 encoder->pre_enable(encoder);
3467
1f544388 3468 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3469
b074cec8 3470 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3471
3472 /*
3473 * On ILK+ LUT must be loaded before the pipe is running but with
3474 * clocks enabled
3475 */
3476 intel_crtc_load_lut(crtc);
3477
1f544388 3478 intel_ddi_set_pipe_settings(crtc);
8228c251 3479 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3480
f37fcc2a 3481 intel_update_watermarks(crtc);
5bfe2ac0 3482 intel_enable_pipe(dev_priv, pipe,
23538ef1 3483 intel_crtc->config.has_pch_encoder, false);
4f771f10 3484 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3485 intel_enable_planes(crtc);
5c38d48c 3486 intel_crtc_update_cursor(crtc, true);
4f771f10 3487
42db64ef
PZ		 3488 hsw_enable_ips(intel_crtc);
3489
5bfe2ac0 3490 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3491 lpt_pch_enable(crtc);
4f771f10
PZ		 3492
3493 mutex_lock(&dev->struct_mutex);
3494 intel_update_fbc(dev);
3495 mutex_unlock(&dev->struct_mutex);
3496
8807e55b 3497 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3498 encoder->enable(encoder);
8807e55b
JN		 3499 intel_opregion_notify_encoder(encoder, true);
3500 }
4f771f10 3501
4f771f10
PZ		 3502 /*
3503 * There seems to be a race in PCH platform hw (at least on some
3504 * outputs) where an enabled pipe still completes any pageflip right
3505 * away (as if the pipe is off) instead of waiting for vblank. As soon
3506 * as the first vblank happend, everything works as expected. Hence just
3507 * wait for one vblank before returning to avoid strange things
3508 * happening.
3509 */
3510 intel_wait_for_vblank(dev, intel_crtc->pipe);
3511}
3512
3f8dce3a
DV		 3513static void ironlake_pfit_disable(struct intel_crtc *crtc)
3514{
3515 struct drm_device *dev = crtc->base.dev;
3516 struct drm_i915_private *dev_priv = dev->dev_private;
3517 int pipe = crtc->pipe;
3518
3519 /* To avoid upsetting the power well on haswell only disable the pfit if
3520 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3521 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3522 I915_WRITE(PF_CTL(pipe), 0);
3523 I915_WRITE(PF_WIN_POS(pipe), 0);
3524 I915_WRITE(PF_WIN_SZ(pipe), 0);
3525 }
3526}
3527
6be4a607
JB		 3528static void ironlake_crtc_disable(struct drm_crtc *crtc)
3529{
3530 struct drm_device *dev = crtc->dev;
3531 struct drm_i915_private *dev_priv = dev->dev_private;
3532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3533 struct intel_encoder *encoder;
6be4a607
JB		 3534 int pipe = intel_crtc->pipe;
3535 int plane = intel_crtc->plane;
5eddb70b 3536 u32 reg, temp;
b52eb4dc 3537
ef9c3aee 3538
f7abfe8b
CW		 3539 if (!intel_crtc->active)
3540 return;
3541
ea9d758d
DV		 3542 for_each_encoder_on_crtc(dev, crtc, encoder)
3543 encoder->disable(encoder);
3544
e6c3a2a6 3545 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3546 drm_vblank_off(dev, pipe);
913d8d11 3547
5c3fe8b0 3548 if (dev_priv->fbc.plane == plane)
973d04f9 3549 intel_disable_fbc(dev);
2c07245f 3550
0d5b8c61 3551 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3552 intel_disable_planes(crtc);
0d5b8c61
VS		 3553 intel_disable_plane(dev_priv, plane, pipe);
3554
d925c59a
DV		 3555 if (intel_crtc->config.has_pch_encoder)
3556 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3557
b24e7179 3558 intel_disable_pipe(dev_priv, pipe);
32f9d658 3559
3f8dce3a 3560 ironlake_pfit_disable(intel_crtc);
2c07245f 3561
bf49ec8c
DV		 3562 for_each_encoder_on_crtc(dev, crtc, encoder)
3563 if (encoder->post_disable)
3564 encoder->post_disable(encoder);
2c07245f 3565
d925c59a
DV		 3566 if (intel_crtc->config.has_pch_encoder) {
3567 ironlake_fdi_disable(crtc);
913d8d11 3568
d925c59a
DV		 3569 ironlake_disable_pch_transcoder(dev_priv, pipe);
3570 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3571
d925c59a
DV		 3572 if (HAS_PCH_CPT(dev)) {
3573 /* disable TRANS_DP_CTL */
3574 reg = TRANS_DP_CTL(pipe);
3575 temp = I915_READ(reg);
3576 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3577 TRANS_DP_PORT_SEL_MASK);
3578 temp |= TRANS_DP_PORT_SEL_NONE;
3579 I915_WRITE(reg, temp);
3580
3581 /* disable DPLL_SEL */
3582 temp = I915_READ(PCH_DPLL_SEL);
11887397 3583 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3584 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3585 }
e3421a18 3586
d925c59a 3587 /* disable PCH DPLL */
e72f9fbf 3588 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3589
d925c59a
DV		 3590 ironlake_fdi_pll_disable(intel_crtc);
3591 }
6b383a7f 3592
f7abfe8b 3593 intel_crtc->active = false;
46ba614c 3594 intel_update_watermarks(crtc);
d1ebd816
BW		 3595
3596 mutex_lock(&dev->struct_mutex);
6b383a7f 3597 intel_update_fbc(dev);
d1ebd816 3598 mutex_unlock(&dev->struct_mutex);
6be4a607 3599}
1b3c7a47 3600
4f771f10 3601static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3602{
4f771f10
PZ		 3603 struct drm_device *dev = crtc->dev;
3604 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3606 struct intel_encoder *encoder;
3607 int pipe = intel_crtc->pipe;
3608 int plane = intel_crtc->plane;
3b117c8f 3609 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3610
4f771f10
PZ		 3611 if (!intel_crtc->active)
3612 return;
3613
8807e55b
JN		 3614 for_each_encoder_on_crtc(dev, crtc, encoder) {
3615 intel_opregion_notify_encoder(encoder, false);
4f771f10 3616 encoder->disable(encoder);
8807e55b 3617 }
4f771f10
PZ		 3618
3619 intel_crtc_wait_for_pending_flips(crtc);
3620 drm_vblank_off(dev, pipe);
4f771f10 3621
891348b2 3622 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3623 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3624 intel_disable_fbc(dev);
3625
42db64ef
PZ		 3626 hsw_disable_ips(intel_crtc);
3627
0d5b8c61 3628 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3629 intel_disable_planes(crtc);
891348b2
RV		 3630 intel_disable_plane(dev_priv, plane, pipe);
3631
8664281b
PZ		 3632 if (intel_crtc->config.has_pch_encoder)
3633 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3634 intel_disable_pipe(dev_priv, pipe);
3635
ad80a810 3636 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3637
3f8dce3a 3638 ironlake_pfit_disable(intel_crtc);
4f771f10 3639
1f544388 3640 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3641
3642 for_each_encoder_on_crtc(dev, crtc, encoder)
3643 if (encoder->post_disable)
3644 encoder->post_disable(encoder);
3645
88adfff1 3646 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3647 lpt_disable_pch_transcoder(dev_priv);
8664281b 3648 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3649 intel_ddi_fdi_disable(crtc);
83616634 3650 }
4f771f10
PZ		 3651
3652 intel_crtc->active = false;
46ba614c 3653 intel_update_watermarks(crtc);
4f771f10
PZ		 3654
3655 mutex_lock(&dev->struct_mutex);
3656 intel_update_fbc(dev);
3657 mutex_unlock(&dev->struct_mutex);
3658}
3659
ee7b9f93
JB		 3660static void ironlake_crtc_off(struct drm_crtc *crtc)
3661{
3662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3663 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3664}
3665
6441ab5f
PZ		 3666static void haswell_crtc_off(struct drm_crtc *crtc)
3667{
3668 intel_ddi_put_crtc_pll(crtc);
3669}
3670
02e792fb
DV		 3671static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3672{
02e792fb 3673 if (!enable && intel_crtc->overlay) {
23f09ce3 3674 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3675 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3676
23f09ce3 3677 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3678 dev_priv->mm.interruptible = false;
3679 (void) intel_overlay_switch_off(intel_crtc->overlay);
3680 dev_priv->mm.interruptible = true;
23f09ce3 3681 mutex_unlock(&dev->struct_mutex);
02e792fb 3682 }
02e792fb 3683
5dcdbcb0
CW		 3684 /* Let userspace switch the overlay on again. In most cases userspace
3685 * has to recompute where to put it anyway.
3686 */
02e792fb
DV		 3687}
3688
61bc95c1
EE		 3689/**
3690 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3691 * cursor plane briefly if not already running after enabling the display
3692 * plane.
3693 * This workaround avoids occasional blank screens when self refresh is
3694 * enabled.
3695 */
3696static void
3697g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3698{
3699 u32 cntl = I915_READ(CURCNTR(pipe));
3700
3701 if ((cntl & CURSOR_MODE) == 0) {
3702 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3703
3704 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3705 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3706 intel_wait_for_vblank(dev_priv->dev, pipe);
3707 I915_WRITE(CURCNTR(pipe), cntl);
3708 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3709 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3710 }
3711}
3712
2dd24552
JB		 3713static void i9xx_pfit_enable(struct intel_crtc *crtc)
3714{
3715 struct drm_device *dev = crtc->base.dev;
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 struct intel_crtc_config *pipe_config = &crtc->config;
3718
328d8e82 3719 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3720 return;
3721
2dd24552 3722 /*
c0b03411
DV		 3723 * The panel fitter should only be adjusted whilst the pipe is disabled,
3724 * according to register description and PRM.
2dd24552 3725 */
c0b03411
DV		 3726 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3727 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3728
b074cec8
JB		 3729 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3730 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3731
3732 /* Border color in case we don't scale up to the full screen. Black by
3733 * default, change to something else for debugging. */
3734 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3735}
3736
89b667f8
JB		 3737static void valleyview_crtc_enable(struct drm_crtc *crtc)
3738{
3739 struct drm_device *dev = crtc->dev;
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742 struct intel_encoder *encoder;
3743 int pipe = intel_crtc->pipe;
3744 int plane = intel_crtc->plane;
23538ef1 3745 bool is_dsi;
89b667f8
JB		 3746
3747 WARN_ON(!crtc->enabled);
3748
3749 if (intel_crtc->active)
3750 return;
3751
3752 intel_crtc->active = true;
89b667f8 3753
89b667f8
JB		 3754 for_each_encoder_on_crtc(dev, crtc, encoder)
3755 if (encoder->pre_pll_enable)
3756 encoder->pre_pll_enable(encoder);
3757
23538ef1
JN		 3758 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3759
e9fd1c02
JN		 3760 if (!is_dsi)
3761 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3762
3763 for_each_encoder_on_crtc(dev, crtc, encoder)
3764 if (encoder->pre_enable)
3765 encoder->pre_enable(encoder);
3766
2dd24552
JB		 3767 i9xx_pfit_enable(intel_crtc);
3768
63cbb074
VS		 3769 intel_crtc_load_lut(crtc);
3770
f37fcc2a 3771 intel_update_watermarks(crtc);
23538ef1 3772 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3773 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3774 intel_enable_planes(crtc);
5c38d48c 3775 intel_crtc_update_cursor(crtc, true);
89b667f8 3776
89b667f8 3777 intel_update_fbc(dev);
5004945f
JN		 3778
3779 for_each_encoder_on_crtc(dev, crtc, encoder)
3780 encoder->enable(encoder);
89b667f8
JB		 3781}
3782
0b8765c6 3783static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3784{
3785 struct drm_device *dev = crtc->dev;
79e53945
JB		 3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3788 struct intel_encoder *encoder;
79e53945 3789 int pipe = intel_crtc->pipe;
80824003 3790 int plane = intel_crtc->plane;
79e53945 3791
08a48469
DV		 3792 WARN_ON(!crtc->enabled);
3793
f7abfe8b
CW		 3794 if (intel_crtc->active)
3795 return;
3796
3797 intel_crtc->active = true;
6b383a7f 3798
9d6d9f19
MK		 3799 for_each_encoder_on_crtc(dev, crtc, encoder)
3800 if (encoder->pre_enable)
3801 encoder->pre_enable(encoder);
3802
f6736a1a
DV		 3803 i9xx_enable_pll(intel_crtc);
3804
2dd24552
JB		 3805 i9xx_pfit_enable(intel_crtc);
3806
63cbb074
VS		 3807 intel_crtc_load_lut(crtc);
3808
f37fcc2a 3809 intel_update_watermarks(crtc);
23538ef1 3810 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3811 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3812 intel_enable_planes(crtc);
22e407d7 3813 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3814 if (IS_G4X(dev))
3815 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3816 intel_crtc_update_cursor(crtc, true);
79e53945 3817
0b8765c6
JB		 3818 /* Give the overlay scaler a chance to enable if it's on this pipe */
3819 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3820
f440eb13 3821 intel_update_fbc(dev);
ef9c3aee 3822
fa5c73b1
DV		 3823 for_each_encoder_on_crtc(dev, crtc, encoder)
3824 encoder->enable(encoder);
0b8765c6 3825}
79e53945 3826
87476d63
DV		 3827static void i9xx_pfit_disable(struct intel_crtc *crtc)
3828{
3829 struct drm_device *dev = crtc->base.dev;
3830 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3831
328d8e82
DV		 3832 if (!crtc->config.gmch_pfit.control)
3833 return;
87476d63 3834
328d8e82 3835 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3836
328d8e82
DV		 3837 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3838 I915_READ(PFIT_CONTROL));
3839 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3840}
3841
0b8765c6
JB		 3842static void i9xx_crtc_disable(struct drm_crtc *crtc)
3843{
3844 struct drm_device *dev = crtc->dev;
3845 struct drm_i915_private *dev_priv = dev->dev_private;
3846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3847 struct intel_encoder *encoder;
0b8765c6
JB		 3848 int pipe = intel_crtc->pipe;
3849 int plane = intel_crtc->plane;
ef9c3aee 3850
f7abfe8b
CW		 3851 if (!intel_crtc->active)
3852 return;
3853
ea9d758d
DV		 3854 for_each_encoder_on_crtc(dev, crtc, encoder)
3855 encoder->disable(encoder);
3856
0b8765c6 3857 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3858 intel_crtc_wait_for_pending_flips(crtc);
3859 drm_vblank_off(dev, pipe);
0b8765c6 3860
5c3fe8b0 3861 if (dev_priv->fbc.plane == plane)
973d04f9 3862 intel_disable_fbc(dev);
79e53945 3863
0d5b8c61
VS		 3864 intel_crtc_dpms_overlay(intel_crtc, false);
3865 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3866 intel_disable_planes(crtc);
b24e7179 3867 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3868
b24e7179 3869 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3870
87476d63 3871 i9xx_pfit_disable(intel_crtc);
24a1f16d 3872
89b667f8
JB		 3873 for_each_encoder_on_crtc(dev, crtc, encoder)
3874 if (encoder->post_disable)
3875 encoder->post_disable(encoder);
3876
e9fd1c02
JN		 3877 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3878 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3879
f7abfe8b 3880 intel_crtc->active = false;
46ba614c 3881 intel_update_watermarks(crtc);
f37fcc2a 3882
6b383a7f 3883 intel_update_fbc(dev);
0b8765c6
JB		 3884}
3885
ee7b9f93
JB		 3886static void i9xx_crtc_off(struct drm_crtc *crtc)
3887{
3888}
3889
976f8a20
DV		 3890static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3891 bool enabled)
2c07245f
ZW		 3892{
3893 struct drm_device *dev = crtc->dev;
3894 struct drm_i915_master_private *master_priv;
3895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3896 int pipe = intel_crtc->pipe;
79e53945
JB		 3897
3898 if (!dev->primary->master)
3899 return;
3900
3901 master_priv = dev->primary->master->driver_priv;
3902 if (!master_priv->sarea_priv)
3903 return;
3904
79e53945
JB		 3905 switch (pipe) {
3906 case 0:
3907 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3908 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3909 break;
3910 case 1:
3911 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3912 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3913 break;
3914 default:
9db4a9c7 3915 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3916 break;
3917 }
79e53945
JB		 3918}
3919
976f8a20
DV		 3920/**
3921 * Sets the power management mode of the pipe and plane.
3922 */
3923void intel_crtc_update_dpms(struct drm_crtc *crtc)
3924{
3925 struct drm_device *dev = crtc->dev;
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927 struct intel_encoder *intel_encoder;
3928 bool enable = false;
3929
3930 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3931 enable |= intel_encoder->connectors_active;
3932
3933 if (enable)
3934 dev_priv->display.crtc_enable(crtc);
3935 else
3936 dev_priv->display.crtc_disable(crtc);
3937
3938 intel_crtc_update_sarea(crtc, enable);
3939}
3940
cdd59983
CW		 3941static void intel_crtc_disable(struct drm_crtc *crtc)
3942{
cdd59983 3943 struct drm_device *dev = crtc->dev;
976f8a20 3944 struct drm_connector *connector;
ee7b9f93 3945 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3947
976f8a20
DV		 3948 /* crtc should still be enabled when we disable it. */
3949 WARN_ON(!crtc->enabled);
3950
3951 dev_priv->display.crtc_disable(crtc);
c77bf565 3952 intel_crtc->eld_vld = false;
976f8a20 3953 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3954 dev_priv->display.off(crtc);
3955
931872fc 3956 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3957 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3958 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3959
3960 if (crtc->fb) {
3961 mutex_lock(&dev->struct_mutex);
1690e1eb 3962 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3963 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3964 crtc->fb = NULL;
3965 }
3966
3967 /* Update computed state. */
3968 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3969 if (!connector->encoder || !connector->encoder->crtc)
3970 continue;
3971
3972 if (connector->encoder->crtc != crtc)
3973 continue;
3974
3975 connector->dpms = DRM_MODE_DPMS_OFF;
3976 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3977 }
3978}
3979
ea5b213a 3980void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3981{
4ef69c7a 3982 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3983
ea5b213a
CW		 3984 drm_encoder_cleanup(encoder);
3985 kfree(intel_encoder);
7e7d76c3
JB		 3986}
3987
9237329d 3988/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3989 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3990 * state of the entire output pipe. */
9237329d 3991static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3992{
5ab432ef
DV		 3993 if (mode == DRM_MODE_DPMS_ON) {
3994 encoder->connectors_active = true;
3995
b2cabb0e 3996 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3997 } else {
3998 encoder->connectors_active = false;
3999
b2cabb0e 4000 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4001 }
79e53945
JB		 4002}
4003
0a91ca29
DV		 4004/* Cross check the actual hw state with our own modeset state tracking (and it's
4005 * internal consistency). */
b980514c 4006static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4007{
0a91ca29
DV		 4008 if (connector->get_hw_state(connector)) {
4009 struct intel_encoder *encoder = connector->encoder;
4010 struct drm_crtc *crtc;
4011 bool encoder_enabled;
4012 enum pipe pipe;
4013
4014 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4015 connector->base.base.id,
4016 drm_get_connector_name(&connector->base));
4017
4018 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4019 "wrong connector dpms state\n");
4020 WARN(connector->base.encoder != &encoder->base,
4021 "active connector not linked to encoder\n");
4022 WARN(!encoder->connectors_active,
4023 "encoder->connectors_active not set\n");
4024
4025 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4026 WARN(!encoder_enabled, "encoder not enabled\n");
4027 if (WARN_ON(!encoder->base.crtc))
4028 return;
4029
4030 crtc = encoder->base.crtc;
4031
4032 WARN(!crtc->enabled, "crtc not enabled\n");
4033 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4034 WARN(pipe != to_intel_crtc(crtc)->pipe,
4035 "encoder active on the wrong pipe\n");
4036 }
79e53945
JB		 4037}
4038
5ab432ef
DV		 4039/* Even simpler default implementation, if there's really no special case to
4040 * consider. */
4041void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4042{
5ab432ef 4043 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4044
5ab432ef
DV		 4045 /* All the simple cases only support two dpms states. */
4046 if (mode != DRM_MODE_DPMS_ON)
4047 mode = DRM_MODE_DPMS_OFF;
d4270e57 4048
5ab432ef
DV		 4049 if (mode == connector->dpms)
4050 return;
4051
4052 connector->dpms = mode;
4053
4054 /* Only need to change hw state when actually enabled */
4055 if (encoder->base.crtc)
4056 intel_encoder_dpms(encoder, mode);
4057 else
8af6cf88 4058 WARN_ON(encoder->connectors_active != false);
0a91ca29 4059
b980514c 4060 intel_modeset_check_state(connector->dev);
79e53945
JB		 4061}
4062
f0947c37
DV		 4063/* Simple connector->get_hw_state implementation for encoders that support only
4064 * one connector and no cloning and hence the encoder state determines the state
4065 * of the connector. */
4066bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4067{
24929352 4068 enum pipe pipe = 0;
f0947c37 4069 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4070
f0947c37 4071 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4072}
4073
1857e1da
DV		 4074static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4075 struct intel_crtc_config *pipe_config)
4076{
4077 struct drm_i915_private *dev_priv = dev->dev_private;
4078 struct intel_crtc *pipe_B_crtc =
4079 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4080
4081 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4082 pipe_name(pipe), pipe_config->fdi_lanes);
4083 if (pipe_config->fdi_lanes > 4) {
4084 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4085 pipe_name(pipe), pipe_config->fdi_lanes);
4086 return false;
4087 }
4088
4089 if (IS_HASWELL(dev)) {
4090 if (pipe_config->fdi_lanes > 2) {
4091 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4092 pipe_config->fdi_lanes);
4093 return false;
4094 } else {
4095 return true;
4096 }
4097 }
4098
4099 if (INTEL_INFO(dev)->num_pipes == 2)
4100 return true;
4101
4102 /* Ivybridge 3 pipe is really complicated */
4103 switch (pipe) {
4104 case PIPE_A:
4105 return true;
4106 case PIPE_B:
4107 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4108 pipe_config->fdi_lanes > 2) {
4109 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4110 pipe_name(pipe), pipe_config->fdi_lanes);
4111 return false;
4112 }
4113 return true;
4114 case PIPE_C:
1e833f40 4115 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4116 pipe_B_crtc->config.fdi_lanes <= 2) {
4117 if (pipe_config->fdi_lanes > 2) {
4118 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4119 pipe_name(pipe), pipe_config->fdi_lanes);
4120 return false;
4121 }
4122 } else {
4123 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4124 return false;
4125 }
4126 return true;
4127 default:
4128 BUG();
4129 }
4130}
4131
e29c22c0
DV		 4132#define RETRY 1
4133static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4134 struct intel_crtc_config *pipe_config)
877d48d5 4135{
1857e1da 4136 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4137 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4138 int lane, link_bw, fdi_dotclock;
e29c22c0 4139 bool setup_ok, needs_recompute = false;
877d48d5 4140
e29c22c0 4141retry:
877d48d5
DV		 4142 /* FDI is a binary signal running at ~2.7GHz, encoding
4143 * each output octet as 10 bits. The actual frequency
4144 * is stored as a divider into a 100MHz clock, and the
4145 * mode pixel clock is stored in units of 1KHz.
4146 * Hence the bw of each lane in terms of the mode signal
4147 * is:
4148 */
4149 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4150
ff9a6750 4151 fdi_dotclock = adjusted_mode->clock;
877d48d5 4152
2bd89a07 4153 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4154 pipe_config->pipe_bpp);
4155
4156 pipe_config->fdi_lanes = lane;
4157
2bd89a07 4158 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4159 link_bw, &pipe_config->fdi_m_n);
1857e1da 4160
e29c22c0
DV		 4161 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4162 intel_crtc->pipe, pipe_config);
4163 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4164 pipe_config->pipe_bpp -= 2*3;
4165 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4166 pipe_config->pipe_bpp);
4167 needs_recompute = true;
4168 pipe_config->bw_constrained = true;
4169
4170 goto retry;
4171 }
4172
4173 if (needs_recompute)
4174 return RETRY;
4175
4176 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4177}
4178
42db64ef
PZ		 4179static void hsw_compute_ips_config(struct intel_crtc *crtc,
4180 struct intel_crtc_config *pipe_config)
4181{
3c4ca58c
PZ		 4182 pipe_config->ips_enabled = i915_enable_ips &&
4183 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4184 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4185}
4186
a43f6e0f 4187static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4188 struct intel_crtc_config *pipe_config)
79e53945 4189{
a43f6e0f 4190 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4191 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4192
ad3a4479 4193 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4194 if (INTEL_INFO(dev)->gen < 4) {
4195 struct drm_i915_private *dev_priv = dev->dev_private;
4196 int clock_limit =
4197 dev_priv->display.get_display_clock_speed(dev);
4198
4199 /*
4200 * Enable pixel doubling when the dot clock
4201 * is > 90% of the (display) core speed.
4202 *
b397c96b
VS		 4203 * GDG double wide on either pipe,
4204 * otherwise pipe A only.
cf532bb2 4205 */
b397c96b 4206 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
ad3a4479
VS		 4207 adjusted_mode->clock > clock_limit * 9 / 10) {
4208 clock_limit *= 2;
cf532bb2 4209 pipe_config->double_wide = true;
ad3a4479
VS		 4210 }
4211
4212 if (adjusted_mode->clock > clock_limit * 9 / 10)
e29c22c0 4213 return -EINVAL;
2c07245f 4214 }
89749350 4215
1d1d0e27
VS		 4216 /*
4217 * Pipe horizontal size must be even in:
4218 * - DVO ganged mode
4219 * - LVDS dual channel mode
4220 * - Double wide pipe
4221 */
4222 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4223 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4224 pipe_config->pipe_src_w &= ~1;
4225
8693a824
DL		 4226 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4227 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4228 */
4229 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4230 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4231 return -EINVAL;
44f46b42 4232
bd080ee5 4233 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4234 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4235 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4236 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4237 * for lvds. */
4238 pipe_config->pipe_bpp = 8*3;
4239 }
4240
f5adf94e 4241 if (HAS_IPS(dev))
a43f6e0f
DV		 4242 hsw_compute_ips_config(crtc, pipe_config);
4243
4244 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4245 * clock survives for now. */
4246 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4247 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4248
877d48d5 4249 if (pipe_config->has_pch_encoder)
a43f6e0f 4250 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4251
e29c22c0 4252 return 0;
79e53945
JB		 4253}
4254
25eb05fc
JB		 4255static int valleyview_get_display_clock_speed(struct drm_device *dev)
4256{
4257 return 400000; /* FIXME */
4258}
4259
e70236a8
JB		 4260static int i945_get_display_clock_speed(struct drm_device *dev)
4261{
4262 return 400000;
4263}
79e53945 4264
e70236a8 4265static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4266{
e70236a8
JB		 4267 return 333000;
4268}
79e53945 4269
e70236a8
JB		 4270static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4271{
4272 return 200000;
4273}
79e53945 4274
257a7ffc
DV		 4275static int pnv_get_display_clock_speed(struct drm_device *dev)
4276{
4277 u16 gcfgc = 0;
4278
4279 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4280
4281 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4282 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4283 return 267000;
4284 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4285 return 333000;
4286 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4287 return 444000;
4288 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4289 return 200000;
4290 default:
4291 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4292 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4293 return 133000;
4294 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4295 return 167000;
4296 }
4297}
4298
e70236a8
JB		 4299static int i915gm_get_display_clock_speed(struct drm_device *dev)
4300{
4301 u16 gcfgc = 0;
79e53945 4302
e70236a8
JB		 4303 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4304
4305 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4306 return 133000;
4307 else {
4308 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4309 case GC_DISPLAY_CLOCK_333_MHZ:
4310 return 333000;
4311 default:
4312 case GC_DISPLAY_CLOCK_190_200_MHZ:
4313 return 190000;
79e53945 4314 }
e70236a8
JB		 4315 }
4316}
4317
4318static int i865_get_display_clock_speed(struct drm_device *dev)
4319{
4320 return 266000;
4321}
4322
4323static int i855_get_display_clock_speed(struct drm_device *dev)
4324{
4325 u16 hpllcc = 0;
4326 /* Assume that the hardware is in the high speed state. This
4327 * should be the default.
4328 */
4329 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4330 case GC_CLOCK_133_200:
4331 case GC_CLOCK_100_200:
4332 return 200000;
4333 case GC_CLOCK_166_250:
4334 return 250000;
4335 case GC_CLOCK_100_133:
79e53945 4336 return 133000;
e70236a8 4337 }
79e53945 4338
e70236a8
JB		 4339 /* Shouldn't happen */
4340 return 0;
4341}
79e53945 4342
e70236a8
JB		 4343static int i830_get_display_clock_speed(struct drm_device *dev)
4344{
4345 return 133000;
79e53945
JB		 4346}
4347
2c07245f 4348static void
a65851af 4349intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4350{
a65851af
VS		 4351 while (*num > DATA_LINK_M_N_MASK ||
4352 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4353 *num >>= 1;
4354 *den >>= 1;
4355 }
4356}
4357
a65851af
VS		 4358static void compute_m_n(unsigned int m, unsigned int n,
4359 uint32_t *ret_m, uint32_t *ret_n)
4360{
4361 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4362 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4363 intel_reduce_m_n_ratio(ret_m, ret_n);
4364}
4365
e69d0bc1
DV		 4366void
4367intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4368 int pixel_clock, int link_clock,
4369 struct intel_link_m_n *m_n)
2c07245f 4370{
e69d0bc1 4371 m_n->tu = 64;
a65851af
VS		 4372
4373 compute_m_n(bits_per_pixel * pixel_clock,
4374 link_clock * nlanes * 8,
4375 &m_n->gmch_m, &m_n->gmch_n);
4376
4377 compute_m_n(pixel_clock, link_clock,
4378 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4379}
4380
a7615030
CW		 4381static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4382{
72bbe58c
KP		 4383 if (i915_panel_use_ssc >= 0)
4384 return i915_panel_use_ssc != 0;
41aa3448 4385 return dev_priv->vbt.lvds_use_ssc
435793df 4386 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4387}
4388
c65d77d8
JB		 4389static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4390{
4391 struct drm_device *dev = crtc->dev;
4392 struct drm_i915_private *dev_priv = dev->dev_private;
4393 int refclk;
4394
a0c4da24 4395 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4396 refclk = 100000;
a0c4da24 4397 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4398 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4399 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4400 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4401 refclk / 1000);
4402 } else if (!IS_GEN2(dev)) {
4403 refclk = 96000;
4404 } else {
4405 refclk = 48000;
4406 }
4407
4408 return refclk;
4409}
4410
7429e9d4 4411static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4412{
7df00d7a 4413 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4414}
f47709a9 4415
7429e9d4
DV		 4416static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4417{
4418 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4419}
4420
f47709a9 4421static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4422 intel_clock_t *reduced_clock)
4423{
f47709a9 4424 struct drm_device *dev = crtc->base.dev;
a7516a05 4425 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4426 int pipe = crtc->pipe;
a7516a05
JB		 4427 u32 fp, fp2 = 0;
4428
4429 if (IS_PINEVIEW(dev)) {
7429e9d4 4430 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4431 if (reduced_clock)
7429e9d4 4432 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4433 } else {
7429e9d4 4434 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4435 if (reduced_clock)
7429e9d4 4436 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4437 }
4438
4439 I915_WRITE(FP0(pipe), fp);
8bcc2795 4440 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4441
f47709a9
DV		 4442 crtc->lowfreq_avail = false;
4443 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4444 reduced_clock && i915_powersave) {
4445 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4446 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4447 crtc->lowfreq_avail = true;
a7516a05
JB		 4448 } else {
4449 I915_WRITE(FP1(pipe), fp);
8bcc2795 4450 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4451 }
4452}
4453
5e69f97f
CML		 4454static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4455 pipe)
89b667f8
JB		 4456{
4457 u32 reg_val;
4458
4459 /*
4460 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4461 * and set it to a reasonable value instead.
4462 */
5e69f97f 4463 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4464 reg_val &= 0xffffff00;
4465 reg_val |= 0x00000030;
5e69f97f 4466 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4467
5e69f97f 4468 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4469 reg_val &= 0x8cffffff;
4470 reg_val = 0x8c000000;
5e69f97f 4471 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4472
5e69f97f 4473 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4474 reg_val &= 0xffffff00;
5e69f97f 4475 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4476
5e69f97f 4477 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4478 reg_val &= 0x00ffffff;
4479 reg_val |= 0xb0000000;
5e69f97f 4480 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4481}
4482
b551842d
DV		 4483static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4484 struct intel_link_m_n *m_n)
4485{
4486 struct drm_device *dev = crtc->base.dev;
4487 struct drm_i915_private *dev_priv = dev->dev_private;
4488 int pipe = crtc->pipe;
4489
e3b95f1e
DV		 4490 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4491 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4492 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4493 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4494}
4495
4496static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4497 struct intel_link_m_n *m_n)
4498{
4499 struct drm_device *dev = crtc->base.dev;
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 int pipe = crtc->pipe;
4502 enum transcoder transcoder = crtc->config.cpu_transcoder;
4503
4504 if (INTEL_INFO(dev)->gen >= 5) {
4505 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4506 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4507 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4508 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4509 } else {
e3b95f1e
DV		 4510 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4511 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4512 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4513 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4514 }
4515}
4516
03afc4a2
DV		 4517static void intel_dp_set_m_n(struct intel_crtc *crtc)
4518{
4519 if (crtc->config.has_pch_encoder)
4520 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4521 else
4522 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4523}
4524
f47709a9 4525static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4526{
f47709a9 4527 struct drm_device *dev = crtc->base.dev;
a0c4da24 4528 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4529 int pipe = crtc->pipe;
89b667f8 4530 u32 dpll, mdiv;
a0c4da24 4531 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4532 u32 coreclk, reg_val, dpll_md;
a0c4da24 4533
09153000
DV		 4534 mutex_lock(&dev_priv->dpio_lock);
4535
f47709a9
DV		 4536 bestn = crtc->config.dpll.n;
4537 bestm1 = crtc->config.dpll.m1;
4538 bestm2 = crtc->config.dpll.m2;
4539 bestp1 = crtc->config.dpll.p1;
4540 bestp2 = crtc->config.dpll.p2;
a0c4da24 4541
89b667f8
JB		 4542 /* See eDP HDMI DPIO driver vbios notes doc */
4543
4544 /* PLL B needs special handling */
4545 if (pipe)
5e69f97f 4546 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4547
4548 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4549 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4550
4551 /* Disable target IRef on PLL */
5e69f97f 4552 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4553 reg_val &= 0x00ffffff;
5e69f97f 4554 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4555
4556 /* Disable fast lock */
5e69f97f 4557 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4558
4559 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4560 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4561 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4562 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4563 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4564
4565 /*
4566 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4567 * but we don't support that).
4568 * Note: don't use the DAC post divider as it seems unstable.
4569 */
4570 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4571 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4572
a0c4da24 4573 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4574 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4575
89b667f8 4576 /* Set HBR and RBR LPF coefficients */
ff9a6750 4577 if (crtc->config.port_clock == 162000 ||
99750bd4 4578 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4579 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4580 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4581 0x009f0003);
89b667f8 4582 else
5e69f97f 4583 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4584 0x00d0000f);
4585
4586 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4587 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4588 /* Use SSC source */
4589 if (!pipe)
5e69f97f 4590 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4591 0x0df40000);
4592 else
5e69f97f 4593 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4594 0x0df70000);
4595 } else { /* HDMI or VGA */
4596 /* Use bend source */
4597 if (!pipe)
5e69f97f 4598 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4599 0x0df70000);
4600 else
5e69f97f 4601 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4602 0x0df40000);
4603 }
a0c4da24 4604
5e69f97f 4605 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4606 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4607 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4608 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4609 coreclk |= 0x01000000;
5e69f97f 4610 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4611
5e69f97f 4612 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4613
89b667f8
JB		 4614 /* Enable DPIO clock input */
4615 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4616 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4617 if (pipe)
4618 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4619
4620 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4621 crtc->config.dpll_hw_state.dpll = dpll;
4622
ef1b460d
DV		 4623 dpll_md = (crtc->config.pixel_multiplier - 1)
4624 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4625 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4626
89b667f8
JB		 4627 if (crtc->config.has_dp_encoder)
4628 intel_dp_set_m_n(crtc);
09153000
DV		 4629
4630 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4631}
4632
f47709a9
DV		 4633static void i9xx_update_pll(struct intel_crtc *crtc,
4634 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4635 int num_connectors)
4636{
f47709a9 4637 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4638 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4639 u32 dpll;
4640 bool is_sdvo;
f47709a9 4641 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4642
f47709a9 4643 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4644
f47709a9
DV		 4645 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4646 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4647
4648 dpll = DPLL_VGA_MODE_DIS;
4649
f47709a9 4650 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4651 dpll |= DPLLB_MODE_LVDS;
4652 else
4653 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4654
ef1b460d 4655 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4656 dpll |= (crtc->config.pixel_multiplier - 1)
4657 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4658 }
198a037f
DV		 4659
4660 if (is_sdvo)
4a33e48d 4661 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4662
f47709a9 4663 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4664 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4665
4666 /* compute bitmask from p1 value */
4667 if (IS_PINEVIEW(dev))
4668 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4669 else {
4670 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4671 if (IS_G4X(dev) && reduced_clock)
4672 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4673 }
4674 switch (clock->p2) {
4675 case 5:
4676 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4677 break;
4678 case 7:
4679 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4680 break;
4681 case 10:
4682 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4683 break;
4684 case 14:
4685 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4686 break;
4687 }
4688 if (INTEL_INFO(dev)->gen >= 4)
4689 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4690
09ede541 4691 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4692 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4693 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4694 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4695 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4696 else
4697 dpll |= PLL_REF_INPUT_DREFCLK;
4698
4699 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4700 crtc->config.dpll_hw_state.dpll = dpll;
4701
eb1cbe48 4702 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4703 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4704 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4705 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4706 }
66e3d5c0
DV		 4707
4708 if (crtc->config.has_dp_encoder)
4709 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4710}
4711
f47709a9 4712static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4713 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4714 int num_connectors)
4715{
f47709a9 4716 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4717 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4718 u32 dpll;
f47709a9 4719 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4720
f47709a9 4721 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4722
eb1cbe48
DV		 4723 dpll = DPLL_VGA_MODE_DIS;
4724
f47709a9 4725 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4726 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4727 } else {
4728 if (clock->p1 == 2)
4729 dpll |= PLL_P1_DIVIDE_BY_TWO;
4730 else
4731 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4732 if (clock->p2 == 4)
4733 dpll |= PLL_P2_DIVIDE_BY_4;
4734 }
4735
4a33e48d
DV		 4736 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4737 dpll |= DPLL_DVO_2X_MODE;
4738
f47709a9 4739 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4740 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4741 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4742 else
4743 dpll |= PLL_REF_INPUT_DREFCLK;
4744
4745 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4746 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4747}
4748
8a654f3b 4749static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4750{
4751 struct drm_device *dev = intel_crtc->base.dev;
4752 struct drm_i915_private *dev_priv = dev->dev_private;
4753 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4754 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4755 struct drm_display_mode *adjusted_mode =
4756 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4757 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4758
4759 /* We need to be careful not to changed the adjusted mode, for otherwise
4760 * the hw state checker will get angry at the mismatch. */
4761 crtc_vtotal = adjusted_mode->crtc_vtotal;
4762 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4763
4764 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4765 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4766 crtc_vtotal -= 1;
4767 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4768 vsyncshift = adjusted_mode->crtc_hsync_start
4769 - adjusted_mode->crtc_htotal / 2;
4770 } else {
4771 vsyncshift = 0;
4772 }
4773
4774 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4775 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4776
fe2b8f9d 4777 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4778 (adjusted_mode->crtc_hdisplay - 1) |
4779 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4780 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4781 (adjusted_mode->crtc_hblank_start - 1) |
4782 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4783 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4784 (adjusted_mode->crtc_hsync_start - 1) |
4785 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4786
fe2b8f9d 4787 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4788 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4789 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4790 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4791 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4792 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4793 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4794 (adjusted_mode->crtc_vsync_start - 1) |
4795 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4796
b5e508d4
PZ		 4797 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4798 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4799 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4800 * bits. */
4801 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4802 (pipe == PIPE_B || pipe == PIPE_C))
4803 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4804
b0e77b9c
PZ		 4805 /* pipesrc controls the size that is scaled from, which should
4806 * always be the user's requested size.
4807 */
4808 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4809 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4810 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4811}
4812
1bd1bd80
DV		 4813static void intel_get_pipe_timings(struct intel_crtc *crtc,
4814 struct intel_crtc_config *pipe_config)
4815{
4816 struct drm_device *dev = crtc->base.dev;
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4819 uint32_t tmp;
4820
4821 tmp = I915_READ(HTOTAL(cpu_transcoder));
4822 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4823 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4824 tmp = I915_READ(HBLANK(cpu_transcoder));
4825 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4826 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4827 tmp = I915_READ(HSYNC(cpu_transcoder));
4828 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4829 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4830
4831 tmp = I915_READ(VTOTAL(cpu_transcoder));
4832 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4833 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4834 tmp = I915_READ(VBLANK(cpu_transcoder));
4835 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4836 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4837 tmp = I915_READ(VSYNC(cpu_transcoder));
4838 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4839 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4840
4841 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4842 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4843 pipe_config->adjusted_mode.crtc_vtotal += 1;
4844 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4845 }
4846
4847 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4848 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4849 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4850
4851 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4852 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4853}
4854
babea61d
JB		 4855static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4856 struct intel_crtc_config *pipe_config)
4857{
4858 struct drm_crtc *crtc = &intel_crtc->base;
4859
4860 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4861 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4862 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4863 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4864
4865 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4866 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4867 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4868 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4869
4870 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4871
4872 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4873 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4874}
4875
84b046f3
DV		 4876static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4877{
4878 struct drm_device *dev = intel_crtc->base.dev;
4879 struct drm_i915_private *dev_priv = dev->dev_private;
4880 uint32_t pipeconf;
4881
9f11a9e4 4882 pipeconf = 0;
84b046f3 4883
67c72a12
DV		 4884 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4885 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4886 pipeconf |= PIPECONF_ENABLE;
4887
cf532bb2
VS		 4888 if (intel_crtc->config.double_wide)
4889 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4890
ff9ce46e
DV		 4891 /* only g4x and later have fancy bpc/dither controls */
4892 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4893 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4894 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4895 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4896 PIPECONF_DITHER_TYPE_SP;
84b046f3 4897
ff9ce46e
DV		 4898 switch (intel_crtc->config.pipe_bpp) {
4899 case 18:
4900 pipeconf |= PIPECONF_6BPC;
4901 break;
4902 case 24:
4903 pipeconf |= PIPECONF_8BPC;
4904 break;
4905 case 30:
4906 pipeconf |= PIPECONF_10BPC;
4907 break;
4908 default:
4909 /* Case prevented by intel_choose_pipe_bpp_dither. */
4910 BUG();
84b046f3
DV		 4911 }
4912 }
4913
4914 if (HAS_PIPE_CXSR(dev)) {
4915 if (intel_crtc->lowfreq_avail) {
4916 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4917 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4918 } else {
4919 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4920 }
4921 }
4922
84b046f3
DV		 4923 if (!IS_GEN2(dev) &&
4924 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4925 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4926 else
4927 pipeconf |= PIPECONF_PROGRESSIVE;
4928
9f11a9e4
DV		 4929 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4930 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4931
84b046f3
DV		 4932 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4933 POSTING_READ(PIPECONF(intel_crtc->pipe));
4934}
4935
f564048e 4936static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4937 int x, int y,
94352cf9 4938 struct drm_framebuffer *fb)
79e53945
JB		 4939{
4940 struct drm_device *dev = crtc->dev;
4941 struct drm_i915_private *dev_priv = dev->dev_private;
4942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4943 int pipe = intel_crtc->pipe;
80824003 4944 int plane = intel_crtc->plane;
c751ce4f 4945 int refclk, num_connectors = 0;
652c393a 4946 intel_clock_t clock, reduced_clock;
84b046f3 4947 u32 dspcntr;
a16af721 4948 bool ok, has_reduced_clock = false;
e9fd1c02 4949 bool is_lvds = false, is_dsi = false;
5eddb70b 4950 struct intel_encoder *encoder;
d4906093 4951 const intel_limit_t *limit;
5c3b82e2 4952 int ret;
79e53945 4953
6c2b7c12 4954 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4955 switch (encoder->type) {
79e53945
JB		 4956 case INTEL_OUTPUT_LVDS:
4957 is_lvds = true;
4958 break;
e9fd1c02
JN		 4959 case INTEL_OUTPUT_DSI:
4960 is_dsi = true;
4961 break;
79e53945 4962 }
43565a06 4963
c751ce4f 4964 num_connectors++;
79e53945
JB		 4965 }
4966
f2335330
JN		 4967 if (is_dsi)
4968 goto skip_dpll;
4969
4970 if (!intel_crtc->config.clock_set) {
4971 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4972
e9fd1c02
JN		 4973 /*
4974 * Returns a set of divisors for the desired target clock with
4975 * the given refclk, or FALSE. The returned values represent
4976 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4977 * 2) / p1 / p2.
4978 */
4979 limit = intel_limit(crtc, refclk);
4980 ok = dev_priv->display.find_dpll(limit, crtc,
4981 intel_crtc->config.port_clock,
4982 refclk, NULL, &clock);
f2335330 4983 if (!ok) {
e9fd1c02
JN		 4984 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4985 return -EINVAL;
4986 }
79e53945 4987
f2335330
JN		 4988 if (is_lvds && dev_priv->lvds_downclock_avail) {
4989 /*
4990 * Ensure we match the reduced clock's P to the target
4991 * clock. If the clocks don't match, we can't switch
4992 * the display clock by using the FP0/FP1. In such case
4993 * we will disable the LVDS downclock feature.
4994 */
4995 has_reduced_clock =
4996 dev_priv->display.find_dpll(limit, crtc,
4997 dev_priv->lvds_downclock,
4998 refclk, &clock,
4999 &reduced_clock);
5000 }
5001 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5002 intel_crtc->config.dpll.n = clock.n;
5003 intel_crtc->config.dpll.m1 = clock.m1;
5004 intel_crtc->config.dpll.m2 = clock.m2;
5005 intel_crtc->config.dpll.p1 = clock.p1;
5006 intel_crtc->config.dpll.p2 = clock.p2;
5007 }
7026d4ac 5008
e9fd1c02 5009 if (IS_GEN2(dev)) {
8a654f3b 5010 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5011 has_reduced_clock ? &reduced_clock : NULL,
5012 num_connectors);
e9fd1c02 5013 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5014 vlv_update_pll(intel_crtc);
e9fd1c02 5015 } else {
f47709a9 5016 i9xx_update_pll(intel_crtc,
eb1cbe48 5017 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5018 num_connectors);
e9fd1c02 5019 }
79e53945 5020
f2335330 5021skip_dpll:
79e53945
JB		 5022 /* Set up the display plane register */
5023 dspcntr = DISPPLANE_GAMMA_ENABLE;
5024
da6ecc5d
JB		 5025 if (!IS_VALLEYVIEW(dev)) {
5026 if (pipe == 0)
5027 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5028 else
5029 dspcntr |= DISPPLANE_SEL_PIPE_B;
5030 }
79e53945 5031
8a654f3b 5032 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5033
5034 /* pipesrc and dspsize control the size that is scaled from,
5035 * which should always be the user's requested size.
79e53945 5036 */
929c77fb 5037 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5038 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5039 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5040 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5041
84b046f3
DV		 5042 i9xx_set_pipeconf(intel_crtc);
5043
f564048e
EA		 5044 I915_WRITE(DSPCNTR(plane), dspcntr);
5045 POSTING_READ(DSPCNTR(plane));
5046
94352cf9 5047 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5048
f564048e
EA		 5049 return ret;
5050}
5051
2fa2fe9a
DV		 5052static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5053 struct intel_crtc_config *pipe_config)
5054{
5055 struct drm_device *dev = crtc->base.dev;
5056 struct drm_i915_private *dev_priv = dev->dev_private;
5057 uint32_t tmp;
5058
5059 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5060 if (!(tmp & PFIT_ENABLE))
5061 return;
2fa2fe9a 5062
06922821 5063 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5064 if (INTEL_INFO(dev)->gen < 4) {
5065 if (crtc->pipe != PIPE_B)
5066 return;
2fa2fe9a
DV		 5067 } else {
5068 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5069 return;
5070 }
5071
06922821 5072 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5073 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5074 if (INTEL_INFO(dev)->gen < 5)
5075 pipe_config->gmch_pfit.lvds_border_bits =
5076 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5077}
5078
acbec814
JB		 5079static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5080 struct intel_crtc_config *pipe_config)
5081{
5082 struct drm_device *dev = crtc->base.dev;
5083 struct drm_i915_private *dev_priv = dev->dev_private;
5084 int pipe = pipe_config->cpu_transcoder;
5085 intel_clock_t clock;
5086 u32 mdiv;
662c6ecb 5087 int refclk = 100000;
acbec814
JB		 5088
5089 mutex_lock(&dev_priv->dpio_lock);
5090 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5091 mutex_unlock(&dev_priv->dpio_lock);
5092
5093 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5094 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5095 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5096 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5097 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5098
662c6ecb
CW		 5099 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5100 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5101
5102 pipe_config->port_clock = clock.dot / 10;
5103}
5104
0e8ffe1b
DV		 5105static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5106 struct intel_crtc_config *pipe_config)
5107{
5108 struct drm_device *dev = crtc->base.dev;
5109 struct drm_i915_private *dev_priv = dev->dev_private;
5110 uint32_t tmp;
5111
e143a21c 5112 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5113 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5114
0e8ffe1b
DV		 5115 tmp = I915_READ(PIPECONF(crtc->pipe));
5116 if (!(tmp & PIPECONF_ENABLE))
5117 return false;
5118
42571aef
VS		 5119 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5120 switch (tmp & PIPECONF_BPC_MASK) {
5121 case PIPECONF_6BPC:
5122 pipe_config->pipe_bpp = 18;
5123 break;
5124 case PIPECONF_8BPC:
5125 pipe_config->pipe_bpp = 24;
5126 break;
5127 case PIPECONF_10BPC:
5128 pipe_config->pipe_bpp = 30;
5129 break;
5130 default:
5131 break;
5132 }
5133 }
5134
282740f7
VS		 5135 if (INTEL_INFO(dev)->gen < 4)
5136 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5137
1bd1bd80
DV		 5138 intel_get_pipe_timings(crtc, pipe_config);
5139
2fa2fe9a
DV		 5140 i9xx_get_pfit_config(crtc, pipe_config);
5141
6c49f241
DV		 5142 if (INTEL_INFO(dev)->gen >= 4) {
5143 tmp = I915_READ(DPLL_MD(crtc->pipe));
5144 pipe_config->pixel_multiplier =
5145 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5146 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5147 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5148 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5149 tmp = I915_READ(DPLL(crtc->pipe));
5150 pipe_config->pixel_multiplier =
5151 ((tmp & SDVO_MULTIPLIER_MASK)
5152 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5153 } else {
5154 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5155 * port and will be fixed up in the encoder->get_config
5156 * function. */
5157 pipe_config->pixel_multiplier = 1;
5158 }
8bcc2795
DV		 5159 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5160 if (!IS_VALLEYVIEW(dev)) {
5161 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5162 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5163 } else {
5164 /* Mask out read-only status bits. */
5165 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5166 DPLL_PORTC_READY_MASK |
5167 DPLL_PORTB_READY_MASK);
8bcc2795 5168 }
6c49f241 5169
acbec814
JB		 5170 if (IS_VALLEYVIEW(dev))
5171 vlv_crtc_clock_get(crtc, pipe_config);
5172 else
5173 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5174
0e8ffe1b
DV		 5175 return true;
5176}
5177
dde86e2d 5178static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5179{
5180 struct drm_i915_private *dev_priv = dev->dev_private;
5181 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5182 struct intel_encoder *encoder;
74cfd7ac 5183 u32 val, final;
13d83a67 5184 bool has_lvds = false;
199e5d79 5185 bool has_cpu_edp = false;
199e5d79 5186 bool has_panel = false;
99eb6a01
KP		 5187 bool has_ck505 = false;
5188 bool can_ssc = false;
13d83a67
JB		 5189
5190 /* We need to take the global config into account */
199e5d79
KP		 5191 list_for_each_entry(encoder, &mode_config->encoder_list,
5192 base.head) {
5193 switch (encoder->type) {
5194 case INTEL_OUTPUT_LVDS:
5195 has_panel = true;
5196 has_lvds = true;
5197 break;
5198 case INTEL_OUTPUT_EDP:
5199 has_panel = true;
2de6905f 5200 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5201 has_cpu_edp = true;
5202 break;
13d83a67
JB		 5203 }
5204 }
5205
99eb6a01 5206 if (HAS_PCH_IBX(dev)) {
41aa3448 5207 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5208 can_ssc = has_ck505;
5209 } else {
5210 has_ck505 = false;
5211 can_ssc = true;
5212 }
5213
2de6905f
ID		 5214 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5215 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5216
5217 /* Ironlake: try to setup display ref clock before DPLL
5218 * enabling. This is only under driver's control after
5219 * PCH B stepping, previous chipset stepping should be
5220 * ignoring this setting.
5221 */
74cfd7ac
CW		 5222 val = I915_READ(PCH_DREF_CONTROL);
5223
5224 /* As we must carefully and slowly disable/enable each source in turn,
5225 * compute the final state we want first and check if we need to
5226 * make any changes at all.
5227 */
5228 final = val;
5229 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5230 if (has_ck505)
5231 final |= DREF_NONSPREAD_CK505_ENABLE;
5232 else
5233 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5234
5235 final &= ~DREF_SSC_SOURCE_MASK;
5236 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5237 final &= ~DREF_SSC1_ENABLE;
5238
5239 if (has_panel) {
5240 final |= DREF_SSC_SOURCE_ENABLE;
5241
5242 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5243 final |= DREF_SSC1_ENABLE;
5244
5245 if (has_cpu_edp) {
5246 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5247 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5248 else
5249 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5250 } else
5251 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5252 } else {
5253 final |= DREF_SSC_SOURCE_DISABLE;
5254 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5255 }
5256
5257 if (final == val)
5258 return;
5259
13d83a67 5260 /* Always enable nonspread source */
74cfd7ac 5261 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5262
99eb6a01 5263 if (has_ck505)
74cfd7ac 5264 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5265 else
74cfd7ac 5266 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5267
199e5d79 5268 if (has_panel) {
74cfd7ac
CW		 5269 val &= ~DREF_SSC_SOURCE_MASK;
5270 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5271
199e5d79 5272 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5273 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5274 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5275 val |= DREF_SSC1_ENABLE;
e77166b5 5276 } else
74cfd7ac 5277 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5278
5279 /* Get SSC going before enabling the outputs */
74cfd7ac 5280 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5281 POSTING_READ(PCH_DREF_CONTROL);
5282 udelay(200);
5283
74cfd7ac 5284 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5285
5286 /* Enable CPU source on CPU attached eDP */
199e5d79 5287 if (has_cpu_edp) {
99eb6a01 5288 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5289 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5290 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5291 }
13d83a67 5292 else
74cfd7ac 5293 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5294 } else
74cfd7ac 5295 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5296
74cfd7ac 5297 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5298 POSTING_READ(PCH_DREF_CONTROL);
5299 udelay(200);
5300 } else {
5301 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5302
74cfd7ac 5303 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5304
5305 /* Turn off CPU output */
74cfd7ac 5306 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5307
74cfd7ac 5308 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5309 POSTING_READ(PCH_DREF_CONTROL);
5310 udelay(200);
5311
5312 /* Turn off the SSC source */
74cfd7ac
CW		 5313 val &= ~DREF_SSC_SOURCE_MASK;
5314 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5315
5316 /* Turn off SSC1 */
74cfd7ac 5317 val &= ~DREF_SSC1_ENABLE;
199e5d79 5318
74cfd7ac 5319 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5320 POSTING_READ(PCH_DREF_CONTROL);
5321 udelay(200);
5322 }
74cfd7ac
CW		 5323
5324 BUG_ON(val != final);
13d83a67
JB		 5325}
5326
f31f2d55 5327static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5328{
f31f2d55 5329 uint32_t tmp;
dde86e2d 5330
0ff066a9
PZ		 5331 tmp = I915_READ(SOUTH_CHICKEN2);
5332 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5333 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5334
0ff066a9
PZ		 5335 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5336 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5337 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5338
0ff066a9
PZ		 5339 tmp = I915_READ(SOUTH_CHICKEN2);
5340 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5341 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5342
0ff066a9
PZ		 5343 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5344 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5345 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5346}
5347
5348/* WaMPhyProgramming:hsw */
5349static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5350{
5351 uint32_t tmp;
dde86e2d
PZ		 5352
5353 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5354 tmp &= ~(0xFF << 24);
5355 tmp |= (0x12 << 24);
5356 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5357
dde86e2d
PZ		 5358 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5359 tmp |= (1 << 11);
5360 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5361
5362 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5363 tmp |= (1 << 11);
5364 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5365
dde86e2d
PZ		 5366 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5367 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5368 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5369
5370 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5371 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5372 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5373
0ff066a9
PZ		 5374 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5375 tmp &= ~(7 << 13);
5376 tmp |= (5 << 13);
5377 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5378
0ff066a9
PZ		 5379 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5380 tmp &= ~(7 << 13);
5381 tmp |= (5 << 13);
5382 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5383
5384 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5385 tmp &= ~0xFF;
5386 tmp |= 0x1C;
5387 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5388
5389 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5390 tmp &= ~0xFF;
5391 tmp |= 0x1C;
5392 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5393
5394 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5395 tmp &= ~(0xFF << 16);
5396 tmp |= (0x1C << 16);
5397 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5398
5399 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5400 tmp &= ~(0xFF << 16);
5401 tmp |= (0x1C << 16);
5402 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5403
0ff066a9
PZ		 5404 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5405 tmp |= (1 << 27);
5406 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5407
0ff066a9
PZ		 5408 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5409 tmp |= (1 << 27);
5410 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5411
0ff066a9
PZ		 5412 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5413 tmp &= ~(0xF << 28);
5414 tmp |= (4 << 28);
5415 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5416
0ff066a9
PZ		 5417 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5418 tmp &= ~(0xF << 28);
5419 tmp |= (4 << 28);
5420 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5421}
5422
2fa86a1f
PZ		 5423/* Implements 3 different sequences from BSpec chapter "Display iCLK
5424 * Programming" based on the parameters passed:
5425 * - Sequence to enable CLKOUT_DP
5426 * - Sequence to enable CLKOUT_DP without spread
5427 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5428 */
5429static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5430 bool with_fdi)
f31f2d55
PZ		 5431{
5432 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5433 uint32_t reg, tmp;
5434
5435 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5436 with_spread = true;
5437 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5438 with_fdi, "LP PCH doesn't have FDI\n"))
5439 with_fdi = false;
f31f2d55
PZ		 5440
5441 mutex_lock(&dev_priv->dpio_lock);
5442
5443 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5444 tmp &= ~SBI_SSCCTL_DISABLE;
5445 tmp |= SBI_SSCCTL_PATHALT;
5446 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5447
5448 udelay(24);
5449
2fa86a1f
PZ		 5450 if (with_spread) {
5451 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5452 tmp &= ~SBI_SSCCTL_PATHALT;
5453 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5454
2fa86a1f
PZ		 5455 if (with_fdi) {
5456 lpt_reset_fdi_mphy(dev_priv);
5457 lpt_program_fdi_mphy(dev_priv);
5458 }
5459 }
dde86e2d 5460
2fa86a1f
PZ		 5461 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5462 SBI_GEN0 : SBI_DBUFF0;
5463 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5464 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5465 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5466
5467 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5468}
5469
47701c3b
PZ		 5470/* Sequence to disable CLKOUT_DP */
5471static void lpt_disable_clkout_dp(struct drm_device *dev)
5472{
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474 uint32_t reg, tmp;
5475
5476 mutex_lock(&dev_priv->dpio_lock);
5477
5478 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5479 SBI_GEN0 : SBI_DBUFF0;
5480 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5481 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5482 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5483
5484 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5485 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5486 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5487 tmp |= SBI_SSCCTL_PATHALT;
5488 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5489 udelay(32);
5490 }
5491 tmp |= SBI_SSCCTL_DISABLE;
5492 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5493 }
5494
5495 mutex_unlock(&dev_priv->dpio_lock);
5496}
5497
bf8fa3d3
PZ		 5498static void lpt_init_pch_refclk(struct drm_device *dev)
5499{
5500 struct drm_mode_config *mode_config = &dev->mode_config;
5501 struct intel_encoder *encoder;
5502 bool has_vga = false;
5503
5504 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5505 switch (encoder->type) {
5506 case INTEL_OUTPUT_ANALOG:
5507 has_vga = true;
5508 break;
5509 }
5510 }
5511
47701c3b
PZ		 5512 if (has_vga)
5513 lpt_enable_clkout_dp(dev, true, true);
5514 else
5515 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5516}
5517
dde86e2d
PZ		 5518/*
5519 * Initialize reference clocks when the driver loads
5520 */
5521void intel_init_pch_refclk(struct drm_device *dev)
5522{
5523 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5524 ironlake_init_pch_refclk(dev);
5525 else if (HAS_PCH_LPT(dev))
5526 lpt_init_pch_refclk(dev);
5527}
5528
d9d444cb
JB		 5529static int ironlake_get_refclk(struct drm_crtc *crtc)
5530{
5531 struct drm_device *dev = crtc->dev;
5532 struct drm_i915_private *dev_priv = dev->dev_private;
5533 struct intel_encoder *encoder;
d9d444cb
JB		 5534 int num_connectors = 0;
5535 bool is_lvds = false;
5536
6c2b7c12 5537 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5538 switch (encoder->type) {
5539 case INTEL_OUTPUT_LVDS:
5540 is_lvds = true;
5541 break;
d9d444cb
JB		 5542 }
5543 num_connectors++;
5544 }
5545
5546 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5547 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5548 dev_priv->vbt.lvds_ssc_freq);
5549 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5550 }
5551
5552 return 120000;
5553}
5554
6ff93609 5555static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5556{
c8203565 5557 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5559 int pipe = intel_crtc->pipe;
c8203565
PZ		 5560 uint32_t val;
5561
78114071 5562 val = 0;
c8203565 5563
965e0c48 5564 switch (intel_crtc->config.pipe_bpp) {
c8203565 5565 case 18:
dfd07d72 5566 val |= PIPECONF_6BPC;
c8203565
PZ		 5567 break;
5568 case 24:
dfd07d72 5569 val |= PIPECONF_8BPC;
c8203565
PZ		 5570 break;
5571 case 30:
dfd07d72 5572 val |= PIPECONF_10BPC;
c8203565
PZ		 5573 break;
5574 case 36:
dfd07d72 5575 val |= PIPECONF_12BPC;
c8203565
PZ		 5576 break;
5577 default:
cc769b62
PZ		 5578 /* Case prevented by intel_choose_pipe_bpp_dither. */
5579 BUG();
c8203565
PZ		 5580 }
5581
d8b32247 5582 if (intel_crtc->config.dither)
c8203565
PZ		 5583 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5584
6ff93609 5585 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5586 val |= PIPECONF_INTERLACED_ILK;
5587 else
5588 val |= PIPECONF_PROGRESSIVE;
5589
50f3b016 5590 if (intel_crtc->config.limited_color_range)
3685a8f3 5591 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5592
c8203565
PZ		 5593 I915_WRITE(PIPECONF(pipe), val);
5594 POSTING_READ(PIPECONF(pipe));
5595}
5596
86d3efce
VS		 5597/*
5598 * Set up the pipe CSC unit.
5599 *
5600 * Currently only full range RGB to limited range RGB conversion
5601 * is supported, but eventually this should handle various
5602 * RGB<->YCbCr scenarios as well.
5603 */
50f3b016 5604static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5605{
5606 struct drm_device *dev = crtc->dev;
5607 struct drm_i915_private *dev_priv = dev->dev_private;
5608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5609 int pipe = intel_crtc->pipe;
5610 uint16_t coeff = 0x7800; /* 1.0 */
5611
5612 /*
5613 * TODO: Check what kind of values actually come out of the pipe
5614 * with these coeff/postoff values and adjust to get the best
5615 * accuracy. Perhaps we even need to take the bpc value into
5616 * consideration.
5617 */
5618
50f3b016 5619 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5620 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5621
5622 /*
5623 * GY/GU and RY/RU should be the other way around according
5624 * to BSpec, but reality doesn't agree. Just set them up in
5625 * a way that results in the correct picture.
5626 */
5627 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5628 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5629
5630 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5631 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5632
5633 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5634 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5635
5636 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5637 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5638 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5639
5640 if (INTEL_INFO(dev)->gen > 6) {
5641 uint16_t postoff = 0;
5642
50f3b016 5643 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5644 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5645
5646 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5647 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5648 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5649
5650 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5651 } else {
5652 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5653
50f3b016 5654 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5655 mode |= CSC_BLACK_SCREEN_OFFSET;
5656
5657 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5658 }
5659}
5660
6ff93609 5661static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5662{
5663 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5665 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5666 uint32_t val;
5667
3eff4faa 5668 val = 0;
ee2b0b38 5669
d8b32247 5670 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5671 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5672
6ff93609 5673 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5674 val |= PIPECONF_INTERLACED_ILK;
5675 else
5676 val |= PIPECONF_PROGRESSIVE;
5677
702e7a56
PZ		 5678 I915_WRITE(PIPECONF(cpu_transcoder), val);
5679 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5680
5681 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5682 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5683}
5684
6591c6e4 5685static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5686 intel_clock_t *clock,
5687 bool *has_reduced_clock,
5688 intel_clock_t *reduced_clock)
5689{
5690 struct drm_device *dev = crtc->dev;
5691 struct drm_i915_private *dev_priv = dev->dev_private;
5692 struct intel_encoder *intel_encoder;
5693 int refclk;
d4906093 5694 const intel_limit_t *limit;
a16af721 5695 bool ret, is_lvds = false;
79e53945 5696
6591c6e4
PZ		 5697 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5698 switch (intel_encoder->type) {
79e53945
JB		 5699 case INTEL_OUTPUT_LVDS:
5700 is_lvds = true;
5701 break;
79e53945
JB		 5702 }
5703 }
5704
d9d444cb 5705 refclk = ironlake_get_refclk(crtc);
79e53945 5706
d4906093
ML		 5707 /*
5708 * Returns a set of divisors for the desired target clock with the given
5709 * refclk, or FALSE. The returned values represent the clock equation:
5710 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5711 */
1b894b59 5712 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5713 ret = dev_priv->display.find_dpll(limit, crtc,
5714 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5715 refclk, NULL, clock);
6591c6e4
PZ		 5716 if (!ret)
5717 return false;
cda4b7d3 5718
ddc9003c 5719 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5720 /*
5721 * Ensure we match the reduced clock's P to the target clock.
5722 * If the clocks don't match, we can't switch the display clock
5723 * by using the FP0/FP1. In such case we will disable the LVDS
5724 * downclock feature.
5725 */
ee9300bb
DV		 5726 *has_reduced_clock =
5727 dev_priv->display.find_dpll(limit, crtc,
5728 dev_priv->lvds_downclock,
5729 refclk, clock,
5730 reduced_clock);
652c393a 5731 }
61e9653f 5732
6591c6e4
PZ		 5733 return true;
5734}
5735
01a415fd
DV		 5736static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5737{
5738 struct drm_i915_private *dev_priv = dev->dev_private;
5739 uint32_t temp;
5740
5741 temp = I915_READ(SOUTH_CHICKEN1);
5742 if (temp & FDI_BC_BIFURCATION_SELECT)
5743 return;
5744
5745 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5746 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5747
5748 temp |= FDI_BC_BIFURCATION_SELECT;
5749 DRM_DEBUG_KMS("enabling fdi C rx\n");
5750 I915_WRITE(SOUTH_CHICKEN1, temp);
5751 POSTING_READ(SOUTH_CHICKEN1);
5752}
5753
ebfd86fd 5754static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5755{
5756 struct drm_device *dev = intel_crtc->base.dev;
5757 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5758
5759 switch (intel_crtc->pipe) {
5760 case PIPE_A:
ebfd86fd 5761 break;
01a415fd 5762 case PIPE_B:
ebfd86fd 5763 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5764 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5765 else
5766 cpt_enable_fdi_bc_bifurcation(dev);
5767
ebfd86fd 5768 break;
01a415fd 5769 case PIPE_C:
01a415fd
DV		 5770 cpt_enable_fdi_bc_bifurcation(dev);
5771
ebfd86fd 5772 break;
01a415fd
DV		 5773 default:
5774 BUG();
5775 }
5776}
5777
d4b1931c
PZ		 5778int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5779{
5780 /*
5781 * Account for spread spectrum to avoid
5782 * oversubscribing the link. Max center spread
5783 * is 2.5%; use 5% for safety's sake.
5784 */
5785 u32 bps = target_clock * bpp * 21 / 20;
5786 return bps / (link_bw * 8) + 1;
5787}
5788
7429e9d4 5789static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5790{
7429e9d4 5791 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5792}
5793
de13a2e3 5794static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5795 u32 *fp,
9a7c7890 5796 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5797{
de13a2e3 5798 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5799 struct drm_device *dev = crtc->dev;
5800 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5801 struct intel_encoder *intel_encoder;
5802 uint32_t dpll;
6cc5f341 5803 int factor, num_connectors = 0;
09ede541 5804 bool is_lvds = false, is_sdvo = false;
79e53945 5805
de13a2e3
PZ		 5806 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5807 switch (intel_encoder->type) {
79e53945
JB		 5808 case INTEL_OUTPUT_LVDS:
5809 is_lvds = true;
5810 break;
5811 case INTEL_OUTPUT_SDVO:
7d57382e 5812 case INTEL_OUTPUT_HDMI:
79e53945 5813 is_sdvo = true;
79e53945 5814 break;
79e53945 5815 }
43565a06 5816
c751ce4f 5817 num_connectors++;
79e53945 5818 }
79e53945 5819
c1858123 5820 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5821 factor = 21;
5822 if (is_lvds) {
5823 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5824 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5825 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5826 factor = 25;
09ede541 5827 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5828 factor = 20;
c1858123 5829
7429e9d4 5830 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5831 *fp |= FP_CB_TUNE;
2c07245f 5832
9a7c7890
DV		 5833 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5834 *fp2 |= FP_CB_TUNE;
5835
5eddb70b 5836 dpll = 0;
2c07245f 5837
a07d6787
EA		 5838 if (is_lvds)
5839 dpll |= DPLLB_MODE_LVDS;
5840 else
5841 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5842
ef1b460d
DV		 5843 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5844 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5845
5846 if (is_sdvo)
4a33e48d 5847 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5848 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5849 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5850
a07d6787 5851 /* compute bitmask from p1 value */
7429e9d4 5852 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5853 /* also FPA1 */
7429e9d4 5854 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5855
7429e9d4 5856 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5857 case 5:
5858 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5859 break;
5860 case 7:
5861 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5862 break;
5863 case 10:
5864 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5865 break;
5866 case 14:
5867 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5868 break;
79e53945
JB		 5869 }
5870
b4c09f3b 5871 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5872 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5873 else
5874 dpll |= PLL_REF_INPUT_DREFCLK;
5875
959e16d6 5876 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5877}
5878
5879static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5880 int x, int y,
5881 struct drm_framebuffer *fb)
5882{
5883 struct drm_device *dev = crtc->dev;
5884 struct drm_i915_private *dev_priv = dev->dev_private;
5885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5886 int pipe = intel_crtc->pipe;
5887 int plane = intel_crtc->plane;
5888 int num_connectors = 0;
5889 intel_clock_t clock, reduced_clock;
cbbab5bd 5890 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5891 bool ok, has_reduced_clock = false;
8b47047b 5892 bool is_lvds = false;
de13a2e3 5893 struct intel_encoder *encoder;
e2b78267 5894 struct intel_shared_dpll *pll;
de13a2e3 5895 int ret;
de13a2e3
PZ		 5896
5897 for_each_encoder_on_crtc(dev, crtc, encoder) {
5898 switch (encoder->type) {
5899 case INTEL_OUTPUT_LVDS:
5900 is_lvds = true;
5901 break;
de13a2e3
PZ		 5902 }
5903
5904 num_connectors++;
a07d6787 5905 }
79e53945 5906
5dc5298b
PZ		 5907 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5908 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5909
ff9a6750 5910 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5911 &has_reduced_clock, &reduced_clock);
ee9300bb 5912 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5913 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5914 return -EINVAL;
79e53945 5915 }
f47709a9
DV		 5916 /* Compat-code for transition, will disappear. */
5917 if (!intel_crtc->config.clock_set) {
5918 intel_crtc->config.dpll.n = clock.n;
5919 intel_crtc->config.dpll.m1 = clock.m1;
5920 intel_crtc->config.dpll.m2 = clock.m2;
5921 intel_crtc->config.dpll.p1 = clock.p1;
5922 intel_crtc->config.dpll.p2 = clock.p2;
5923 }
79e53945 5924
5dc5298b 5925 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5926 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5927 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5928 if (has_reduced_clock)
7429e9d4 5929 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5930
7429e9d4 5931 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5932 &fp, &reduced_clock,
5933 has_reduced_clock ? &fp2 : NULL);
5934
959e16d6 5935 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5936 intel_crtc->config.dpll_hw_state.fp0 = fp;
5937 if (has_reduced_clock)
5938 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5939 else
5940 intel_crtc->config.dpll_hw_state.fp1 = fp;
5941
b89a1d39 5942 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5943 if (pll == NULL) {
84f44ce7
VS		 5944 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5945 pipe_name(pipe));
4b645f14
JB		 5946 return -EINVAL;
5947 }
ee7b9f93 5948 } else
e72f9fbf 5949 intel_put_shared_dpll(intel_crtc);
79e53945 5950
03afc4a2
DV		 5951 if (intel_crtc->config.has_dp_encoder)
5952 intel_dp_set_m_n(intel_crtc);
79e53945 5953
bcd644e0
DV		 5954 if (is_lvds && has_reduced_clock && i915_powersave)
5955 intel_crtc->lowfreq_avail = true;
5956 else
5957 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5958
5959 if (intel_crtc->config.has_pch_encoder) {
5960 pll = intel_crtc_to_shared_dpll(intel_crtc);
5961
652c393a
JB		 5962 }
5963
8a654f3b 5964 intel_set_pipe_timings(intel_crtc);
5eddb70b 5965
ca3a0ff8 5966 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5967 intel_cpu_transcoder_set_m_n(intel_crtc,
5968 &intel_crtc->config.fdi_m_n);
5969 }
2c07245f 5970
ebfd86fd
DV		 5971 if (IS_IVYBRIDGE(dev))
5972 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5973
6ff93609 5974 ironlake_set_pipeconf(crtc);
79e53945 5975
a1f9e77e
PZ		 5976 /* Set up the display plane register */
5977 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5978 POSTING_READ(DSPCNTR(plane));
79e53945 5979
94352cf9 5980 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5981
1857e1da 5982 return ret;
79e53945
JB		 5983}
5984
eb14cb74
VS		 5985static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5986 struct intel_link_m_n *m_n)
5987{
5988 struct drm_device *dev = crtc->base.dev;
5989 struct drm_i915_private *dev_priv = dev->dev_private;
5990 enum pipe pipe = crtc->pipe;
5991
5992 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5993 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5994 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5995 & ~TU_SIZE_MASK;
5996 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5997 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5998 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5999}
6000
6001static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6002 enum transcoder transcoder,
6003 struct intel_link_m_n *m_n)
72419203
DV		 6004{
6005 struct drm_device *dev = crtc->base.dev;
6006 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6007 enum pipe pipe = crtc->pipe;
72419203 6008
eb14cb74
VS		 6009 if (INTEL_INFO(dev)->gen >= 5) {
6010 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6011 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6012 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6013 & ~TU_SIZE_MASK;
6014 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6015 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6016 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6017 } else {
6018 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6019 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6020 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6021 & ~TU_SIZE_MASK;
6022 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6023 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6024 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6025 }
6026}
6027
6028void intel_dp_get_m_n(struct intel_crtc *crtc,
6029 struct intel_crtc_config *pipe_config)
6030{
6031 if (crtc->config.has_pch_encoder)
6032 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6033 else
6034 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6035 &pipe_config->dp_m_n);
6036}
72419203 6037
eb14cb74
VS		 6038static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6039 struct intel_crtc_config *pipe_config)
6040{
6041 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6042 &pipe_config->fdi_m_n);
72419203
DV		 6043}
6044
2fa2fe9a
DV		 6045static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6046 struct intel_crtc_config *pipe_config)
6047{
6048 struct drm_device *dev = crtc->base.dev;
6049 struct drm_i915_private *dev_priv = dev->dev_private;
6050 uint32_t tmp;
6051
6052 tmp = I915_READ(PF_CTL(crtc->pipe));
6053
6054 if (tmp & PF_ENABLE) {
fd4daa9c 6055 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6056 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6057 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6058
6059 /* We currently do not free assignements of panel fitters on
6060 * ivb/hsw (since we don't use the higher upscaling modes which
6061 * differentiates them) so just WARN about this case for now. */
6062 if (IS_GEN7(dev)) {
6063 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6064 PF_PIPE_SEL_IVB(crtc->pipe));
6065 }
2fa2fe9a 6066 }
79e53945
JB		 6067}
6068
0e8ffe1b
DV		 6069static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6070 struct intel_crtc_config *pipe_config)
6071{
6072 struct drm_device *dev = crtc->base.dev;
6073 struct drm_i915_private *dev_priv = dev->dev_private;
6074 uint32_t tmp;
6075
e143a21c 6076 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6077 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6078
0e8ffe1b
DV		 6079 tmp = I915_READ(PIPECONF(crtc->pipe));
6080 if (!(tmp & PIPECONF_ENABLE))
6081 return false;
6082
42571aef
VS		 6083 switch (tmp & PIPECONF_BPC_MASK) {
6084 case PIPECONF_6BPC:
6085 pipe_config->pipe_bpp = 18;
6086 break;
6087 case PIPECONF_8BPC:
6088 pipe_config->pipe_bpp = 24;
6089 break;
6090 case PIPECONF_10BPC:
6091 pipe_config->pipe_bpp = 30;
6092 break;
6093 case PIPECONF_12BPC:
6094 pipe_config->pipe_bpp = 36;
6095 break;
6096 default:
6097 break;
6098 }
6099
ab9412ba 6100 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6101 struct intel_shared_dpll *pll;
6102
88adfff1
DV		 6103 pipe_config->has_pch_encoder = true;
6104
627eb5a3
DV		 6105 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6106 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6107 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6108
6109 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6110
c0d43d62 6111 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6112 pipe_config->shared_dpll =
6113 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6114 } else {
6115 tmp = I915_READ(PCH_DPLL_SEL);
6116 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6117 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6118 else
6119 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6120 }
66e985c0
DV		 6121
6122 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6123
6124 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6125 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6126
6127 tmp = pipe_config->dpll_hw_state.dpll;
6128 pipe_config->pixel_multiplier =
6129 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6130 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6131
6132 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6133 } else {
6134 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6135 }
6136
1bd1bd80
DV		 6137 intel_get_pipe_timings(crtc, pipe_config);
6138
2fa2fe9a
DV		 6139 ironlake_get_pfit_config(crtc, pipe_config);
6140
0e8ffe1b
DV		 6141 return true;
6142}
6143
be256dc7
PZ		 6144static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6145{
6146 struct drm_device *dev = dev_priv->dev;
6147 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6148 struct intel_crtc *crtc;
6149 unsigned long irqflags;
bd633a7c 6150 uint32_t val;
be256dc7
PZ		 6151
6152 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6153 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6154 pipe_name(crtc->pipe));
6155
6156 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6157 WARN(plls->spll_refcount, "SPLL enabled\n");
6158 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6159 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6160 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6161 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6162 "CPU PWM1 enabled\n");
6163 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6164 "CPU PWM2 enabled\n");
6165 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6166 "PCH PWM1 enabled\n");
6167 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6168 "Utility pin enabled\n");
6169 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6170
6171 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6172 val = I915_READ(DEIMR);
6173 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6174 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6175 val = I915_READ(SDEIMR);
bd633a7c 6176 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6177 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6178 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6179}
6180
6181/*
6182 * This function implements pieces of two sequences from BSpec:
6183 * - Sequence for display software to disable LCPLL
6184 * - Sequence for display software to allow package C8+
6185 * The steps implemented here are just the steps that actually touch the LCPLL
6186 * register. Callers should take care of disabling all the display engine
6187 * functions, doing the mode unset, fixing interrupts, etc.
6188 */
6ff58d53
PZ		 6189static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6190 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6191{
6192 uint32_t val;
6193
6194 assert_can_disable_lcpll(dev_priv);
6195
6196 val = I915_READ(LCPLL_CTL);
6197
6198 if (switch_to_fclk) {
6199 val |= LCPLL_CD_SOURCE_FCLK;
6200 I915_WRITE(LCPLL_CTL, val);
6201
6202 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6203 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6204 DRM_ERROR("Switching to FCLK failed\n");
6205
6206 val = I915_READ(LCPLL_CTL);
6207 }
6208
6209 val |= LCPLL_PLL_DISABLE;
6210 I915_WRITE(LCPLL_CTL, val);
6211 POSTING_READ(LCPLL_CTL);
6212
6213 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6214 DRM_ERROR("LCPLL still locked\n");
6215
6216 val = I915_READ(D_COMP);
6217 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6218 mutex_lock(&dev_priv->rps.hw_lock);
6219 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6220 DRM_ERROR("Failed to disable D_COMP\n");
6221 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6222 POSTING_READ(D_COMP);
6223 ndelay(100);
6224
6225 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6226 DRM_ERROR("D_COMP RCOMP still in progress\n");
6227
6228 if (allow_power_down) {
6229 val = I915_READ(LCPLL_CTL);
6230 val |= LCPLL_POWER_DOWN_ALLOW;
6231 I915_WRITE(LCPLL_CTL, val);
6232 POSTING_READ(LCPLL_CTL);
6233 }
6234}
6235
6236/*
6237 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6238 * source.
6239 */
6ff58d53 6240static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6241{
6242 uint32_t val;
6243
6244 val = I915_READ(LCPLL_CTL);
6245
6246 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6247 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6248 return;
6249
215733fa
PZ		 6250 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6251 * we'll hang the machine! */
6252 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6253
be256dc7
PZ		 6254 if (val & LCPLL_POWER_DOWN_ALLOW) {
6255 val &= ~LCPLL_POWER_DOWN_ALLOW;
6256 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6257 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6258 }
6259
6260 val = I915_READ(D_COMP);
6261 val |= D_COMP_COMP_FORCE;
6262 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6263 mutex_lock(&dev_priv->rps.hw_lock);
6264 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6265 DRM_ERROR("Failed to enable D_COMP\n");
6266 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6267 POSTING_READ(D_COMP);
be256dc7
PZ		 6268
6269 val = I915_READ(LCPLL_CTL);
6270 val &= ~LCPLL_PLL_DISABLE;
6271 I915_WRITE(LCPLL_CTL, val);
6272
6273 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6274 DRM_ERROR("LCPLL not locked yet\n");
6275
6276 if (val & LCPLL_CD_SOURCE_FCLK) {
6277 val = I915_READ(LCPLL_CTL);
6278 val &= ~LCPLL_CD_SOURCE_FCLK;
6279 I915_WRITE(LCPLL_CTL, val);
6280
6281 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6282 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6283 DRM_ERROR("Switching back to LCPLL failed\n");
6284 }
215733fa
PZ		 6285
6286 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6287}
6288
c67a470b
PZ		 6289void hsw_enable_pc8_work(struct work_struct *__work)
6290{
6291 struct drm_i915_private *dev_priv =
6292 container_of(to_delayed_work(__work), struct drm_i915_private,
6293 pc8.enable_work);
6294 struct drm_device *dev = dev_priv->dev;
6295 uint32_t val;
6296
6297 if (dev_priv->pc8.enabled)
6298 return;
6299
6300 DRM_DEBUG_KMS("Enabling package C8+\n");
6301
6302 dev_priv->pc8.enabled = true;
6303
6304 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6305 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6306 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6307 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6308 }
6309
6310 lpt_disable_clkout_dp(dev);
6311 hsw_pc8_disable_interrupts(dev);
6312 hsw_disable_lcpll(dev_priv, true, true);
6313}
6314
6315static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6316{
6317 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6318 WARN(dev_priv->pc8.disable_count < 1,
6319 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6320
6321 dev_priv->pc8.disable_count--;
6322 if (dev_priv->pc8.disable_count != 0)
6323 return;
6324
6325 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6326 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6327}
6328
6329static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6330{
6331 struct drm_device *dev = dev_priv->dev;
6332 uint32_t val;
6333
6334 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6335 WARN(dev_priv->pc8.disable_count < 0,
6336 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6337
6338 dev_priv->pc8.disable_count++;
6339 if (dev_priv->pc8.disable_count != 1)
6340 return;
6341
6342 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6343 if (!dev_priv->pc8.enabled)
6344 return;
6345
6346 DRM_DEBUG_KMS("Disabling package C8+\n");
6347
6348 hsw_restore_lcpll(dev_priv);
6349 hsw_pc8_restore_interrupts(dev);
6350 lpt_init_pch_refclk(dev);
6351
6352 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6353 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6354 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6355 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6356 }
6357
6358 intel_prepare_ddi(dev);
6359 i915_gem_init_swizzling(dev);
6360 mutex_lock(&dev_priv->rps.hw_lock);
6361 gen6_update_ring_freq(dev);
6362 mutex_unlock(&dev_priv->rps.hw_lock);
6363 dev_priv->pc8.enabled = false;
6364}
6365
6366void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6367{
6368 mutex_lock(&dev_priv->pc8.lock);
6369 __hsw_enable_package_c8(dev_priv);
6370 mutex_unlock(&dev_priv->pc8.lock);
6371}
6372
6373void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6374{
6375 mutex_lock(&dev_priv->pc8.lock);
6376 __hsw_disable_package_c8(dev_priv);
6377 mutex_unlock(&dev_priv->pc8.lock);
6378}
6379
6380static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6381{
6382 struct drm_device *dev = dev_priv->dev;
6383 struct intel_crtc *crtc;
6384 uint32_t val;
6385
6386 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6387 if (crtc->base.enabled)
6388 return false;
6389
6390 /* This case is still possible since we have the i915.disable_power_well
6391 * parameter and also the KVMr or something else might be requesting the
6392 * power well. */
6393 val = I915_READ(HSW_PWR_WELL_DRIVER);
6394 if (val != 0) {
6395 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6396 return false;
6397 }
6398
6399 return true;
6400}
6401
6402/* Since we're called from modeset_global_resources there's no way to
6403 * symmetrically increase and decrease the refcount, so we use
6404 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6405 * or not.
6406 */
6407static void hsw_update_package_c8(struct drm_device *dev)
6408{
6409 struct drm_i915_private *dev_priv = dev->dev_private;
6410 bool allow;
6411
6412 if (!i915_enable_pc8)
6413 return;
6414
6415 mutex_lock(&dev_priv->pc8.lock);
6416
6417 allow = hsw_can_enable_package_c8(dev_priv);
6418
6419 if (allow == dev_priv->pc8.requirements_met)
6420 goto done;
6421
6422 dev_priv->pc8.requirements_met = allow;
6423
6424 if (allow)
6425 __hsw_enable_package_c8(dev_priv);
6426 else
6427 __hsw_disable_package_c8(dev_priv);
6428
6429done:
6430 mutex_unlock(&dev_priv->pc8.lock);
6431}
6432
6433static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6434{
6435 if (!dev_priv->pc8.gpu_idle) {
6436 dev_priv->pc8.gpu_idle = true;
6437 hsw_enable_package_c8(dev_priv);
6438 }
6439}
6440
6441static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6442{
6443 if (dev_priv->pc8.gpu_idle) {
6444 dev_priv->pc8.gpu_idle = false;
6445 hsw_disable_package_c8(dev_priv);
6446 }
be256dc7
PZ		 6447}
6448
d6dd9eb1
DV		 6449static void haswell_modeset_global_resources(struct drm_device *dev)
6450{
d6dd9eb1
DV		 6451 bool enable = false;
6452 struct intel_crtc *crtc;
d6dd9eb1
DV		 6453
6454 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6455 if (!crtc->base.enabled)
6456 continue;
d6dd9eb1 6457
fd4daa9c 6458 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6459 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6460 enable = true;
6461 }
6462
d6dd9eb1 6463 intel_set_power_well(dev, enable);
c67a470b
PZ		 6464
6465 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6466}
6467
09b4ddf9 6468static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6469 int x, int y,
6470 struct drm_framebuffer *fb)
6471{
6472 struct drm_device *dev = crtc->dev;
6473 struct drm_i915_private *dev_priv = dev->dev_private;
6474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6475 int plane = intel_crtc->plane;
09b4ddf9 6476 int ret;
09b4ddf9 6477
ff9a6750 6478 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6479 return -EINVAL;
6480
03afc4a2
DV		 6481 if (intel_crtc->config.has_dp_encoder)
6482 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6483
6484 intel_crtc->lowfreq_avail = false;
09b4ddf9 6485
8a654f3b 6486 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6487
ca3a0ff8 6488 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6489 intel_cpu_transcoder_set_m_n(intel_crtc,
6490 &intel_crtc->config.fdi_m_n);
6491 }
09b4ddf9 6492
6ff93609 6493 haswell_set_pipeconf(crtc);
09b4ddf9 6494
50f3b016 6495 intel_set_pipe_csc(crtc);
86d3efce 6496
09b4ddf9 6497 /* Set up the display plane register */
86d3efce 6498 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6499 POSTING_READ(DSPCNTR(plane));
6500
6501 ret = intel_pipe_set_base(crtc, x, y, fb);
6502
1f803ee5 6503 return ret;
79e53945
JB		 6504}
6505
0e8ffe1b
DV		 6506static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6507 struct intel_crtc_config *pipe_config)
6508{
6509 struct drm_device *dev = crtc->base.dev;
6510 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6511 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6512 uint32_t tmp;
6513
e143a21c 6514 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6515 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6516
eccb140b
DV		 6517 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6518 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6519 enum pipe trans_edp_pipe;
6520 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6521 default:
6522 WARN(1, "unknown pipe linked to edp transcoder\n");
6523 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6524 case TRANS_DDI_EDP_INPUT_A_ON:
6525 trans_edp_pipe = PIPE_A;
6526 break;
6527 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6528 trans_edp_pipe = PIPE_B;
6529 break;
6530 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6531 trans_edp_pipe = PIPE_C;
6532 break;
6533 }
6534
6535 if (trans_edp_pipe == crtc->pipe)
6536 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6537 }
6538
b97186f0 6539 if (!intel_display_power_enabled(dev,
eccb140b 6540 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6541 return false;
6542
eccb140b 6543 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6544 if (!(tmp & PIPECONF_ENABLE))
6545 return false;
6546
88adfff1 6547 /*
f196e6be 6548 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6549 * DDI E. So just check whether this pipe is wired to DDI E and whether
6550 * the PCH transcoder is on.
6551 */
eccb140b 6552 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6553 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6554 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6555 pipe_config->has_pch_encoder = true;
6556
627eb5a3
DV		 6557 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6558 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6559 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6560
6561 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6562 }
6563
1bd1bd80
DV		 6564 intel_get_pipe_timings(crtc, pipe_config);
6565
2fa2fe9a
DV		 6566 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6567 if (intel_display_power_enabled(dev, pfit_domain))
6568 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6569
42db64ef
PZ		 6570 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6571 (I915_READ(IPS_CTL) & IPS_ENABLE);
6572
6c49f241
DV		 6573 pipe_config->pixel_multiplier = 1;
6574
0e8ffe1b
DV		 6575 return true;
6576}
6577
f564048e 6578static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6579 int x, int y,
94352cf9 6580 struct drm_framebuffer *fb)
f564048e
EA		 6581{
6582 struct drm_device *dev = crtc->dev;
6583 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6584 struct intel_encoder *encoder;
0b701d27 6585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6586 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6587 int pipe = intel_crtc->pipe;
f564048e
EA		 6588 int ret;
6589
0b701d27 6590 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6591
b8cecdf5
DV		 6592 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6593
79e53945 6594 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6595
9256aa19
DV		 6596 if (ret != 0)
6597 return ret;
6598
6599 for_each_encoder_on_crtc(dev, crtc, encoder) {
6600 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6601 encoder->base.base.id,
6602 drm_get_encoder_name(&encoder->base),
6603 mode->base.id, mode->name);
36f2d1f1 6604 encoder->mode_set(encoder);
9256aa19
DV		 6605 }
6606
6607 return 0;
79e53945
JB		 6608}
6609
3a9627f4
WF		 6610static bool intel_eld_uptodate(struct drm_connector *connector,
6611 int reg_eldv, uint32_t bits_eldv,
6612 int reg_elda, uint32_t bits_elda,
6613 int reg_edid)
6614{
6615 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6616 uint8_t *eld = connector->eld;
6617 uint32_t i;
6618
6619 i = I915_READ(reg_eldv);
6620 i &= bits_eldv;
6621
6622 if (!eld[0])
6623 return !i;
6624
6625 if (!i)
6626 return false;
6627
6628 i = I915_READ(reg_elda);
6629 i &= ~bits_elda;
6630 I915_WRITE(reg_elda, i);
6631
6632 for (i = 0; i < eld[2]; i++)
6633 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6634 return false;
6635
6636 return true;
6637}
6638
e0dac65e
WF		 6639static void g4x_write_eld(struct drm_connector *connector,
6640 struct drm_crtc *crtc)
6641{
6642 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6643 uint8_t *eld = connector->eld;
6644 uint32_t eldv;
6645 uint32_t len;
6646 uint32_t i;
6647
6648 i = I915_READ(G4X_AUD_VID_DID);
6649
6650 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6651 eldv = G4X_ELDV_DEVCL_DEVBLC;
6652 else
6653 eldv = G4X_ELDV_DEVCTG;
6654
3a9627f4
WF		 6655 if (intel_eld_uptodate(connector,
6656 G4X_AUD_CNTL_ST, eldv,
6657 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6658 G4X_HDMIW_HDMIEDID))
6659 return;
6660
e0dac65e
WF		 6661 i = I915_READ(G4X_AUD_CNTL_ST);
6662 i &= ~(eldv | G4X_ELD_ADDR);
6663 len = (i >> 9) & 0x1f; /* ELD buffer size */
6664 I915_WRITE(G4X_AUD_CNTL_ST, i);
6665
6666 if (!eld[0])
6667 return;
6668
6669 len = min_t(uint8_t, eld[2], len);
6670 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6671 for (i = 0; i < len; i++)
6672 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6673
6674 i = I915_READ(G4X_AUD_CNTL_ST);
6675 i |= eldv;
6676 I915_WRITE(G4X_AUD_CNTL_ST, i);
6677}
6678
83358c85
WX		 6679static void haswell_write_eld(struct drm_connector *connector,
6680 struct drm_crtc *crtc)
6681{
6682 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6683 uint8_t *eld = connector->eld;
6684 struct drm_device *dev = crtc->dev;
7b9f35a6 6685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6686 uint32_t eldv;
6687 uint32_t i;
6688 int len;
6689 int pipe = to_intel_crtc(crtc)->pipe;
6690 int tmp;
6691
6692 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6693 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6694 int aud_config = HSW_AUD_CFG(pipe);
6695 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6696
6697
6698 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6699
6700 /* Audio output enable */
6701 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6702 tmp = I915_READ(aud_cntrl_st2);
6703 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6704 I915_WRITE(aud_cntrl_st2, tmp);
6705
6706 /* Wait for 1 vertical blank */
6707 intel_wait_for_vblank(dev, pipe);
6708
6709 /* Set ELD valid state */
6710 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6711 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6712 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6713 I915_WRITE(aud_cntrl_st2, tmp);
6714 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6715 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6716
6717 /* Enable HDMI mode */
6718 tmp = I915_READ(aud_config);
7e7cb34f 6719 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6720 /* clear N_programing_enable and N_value_index */
6721 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6722 I915_WRITE(aud_config, tmp);
6723
6724 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6725
6726 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6727 intel_crtc->eld_vld = true;
83358c85
WX		 6728
6729 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6730 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6731 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6732 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6733 } else
6734 I915_WRITE(aud_config, 0);
6735
6736 if (intel_eld_uptodate(connector,
6737 aud_cntrl_st2, eldv,
6738 aud_cntl_st, IBX_ELD_ADDRESS,
6739 hdmiw_hdmiedid))
6740 return;
6741
6742 i = I915_READ(aud_cntrl_st2);
6743 i &= ~eldv;
6744 I915_WRITE(aud_cntrl_st2, i);
6745
6746 if (!eld[0])
6747 return;
6748
6749 i = I915_READ(aud_cntl_st);
6750 i &= ~IBX_ELD_ADDRESS;
6751 I915_WRITE(aud_cntl_st, i);
6752 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6753 DRM_DEBUG_DRIVER("port num:%d\n", i);
6754
6755 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6756 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6757 for (i = 0; i < len; i++)
6758 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6759
6760 i = I915_READ(aud_cntrl_st2);
6761 i |= eldv;
6762 I915_WRITE(aud_cntrl_st2, i);
6763
6764}
6765
e0dac65e
WF		 6766static void ironlake_write_eld(struct drm_connector *connector,
6767 struct drm_crtc *crtc)
6768{
6769 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6770 uint8_t *eld = connector->eld;
6771 uint32_t eldv;
6772 uint32_t i;
6773 int len;
6774 int hdmiw_hdmiedid;
b6daa025 6775 int aud_config;
e0dac65e
WF		 6776 int aud_cntl_st;
6777 int aud_cntrl_st2;
9b138a83 6778 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6779
b3f33cbf 6780 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6781 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6782 aud_config = IBX_AUD_CFG(pipe);
6783 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6784 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6785 } else {
9b138a83
WX		 6786 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6787 aud_config = CPT_AUD_CFG(pipe);
6788 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6789 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6790 }
6791
9b138a83 6792 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6793
6794 i = I915_READ(aud_cntl_st);
9b138a83 6795 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6796 if (!i) {
6797 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6798 /* operate blindly on all ports */
1202b4c6
WF		 6799 eldv = IBX_ELD_VALIDB;
6800 eldv |= IBX_ELD_VALIDB << 4;
6801 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6802 } else {
2582a850 6803 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6804 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6805 }
6806
3a9627f4
WF		 6807 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6808 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6809 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6810 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6811 } else
6812 I915_WRITE(aud_config, 0);
e0dac65e 6813
3a9627f4
WF		 6814 if (intel_eld_uptodate(connector,
6815 aud_cntrl_st2, eldv,
6816 aud_cntl_st, IBX_ELD_ADDRESS,
6817 hdmiw_hdmiedid))
6818 return;
6819
e0dac65e
WF		 6820 i = I915_READ(aud_cntrl_st2);
6821 i &= ~eldv;
6822 I915_WRITE(aud_cntrl_st2, i);
6823
6824 if (!eld[0])
6825 return;
6826
e0dac65e 6827 i = I915_READ(aud_cntl_st);
1202b4c6 6828 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6829 I915_WRITE(aud_cntl_st, i);
6830
6831 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6832 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6833 for (i = 0; i < len; i++)
6834 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6835
6836 i = I915_READ(aud_cntrl_st2);
6837 i |= eldv;
6838 I915_WRITE(aud_cntrl_st2, i);
6839}
6840
6841void intel_write_eld(struct drm_encoder *encoder,
6842 struct drm_display_mode *mode)
6843{
6844 struct drm_crtc *crtc = encoder->crtc;
6845 struct drm_connector *connector;
6846 struct drm_device *dev = encoder->dev;
6847 struct drm_i915_private *dev_priv = dev->dev_private;
6848
6849 connector = drm_select_eld(encoder, mode);
6850 if (!connector)
6851 return;
6852
6853 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6854 connector->base.id,
6855 drm_get_connector_name(connector),
6856 connector->encoder->base.id,
6857 drm_get_encoder_name(connector->encoder));
6858
6859 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6860
6861 if (dev_priv->display.write_eld)
6862 dev_priv->display.write_eld(connector, crtc);
6863}
6864
560b85bb
CW		 6865static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6866{
6867 struct drm_device *dev = crtc->dev;
6868 struct drm_i915_private *dev_priv = dev->dev_private;
6869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6870 bool visible = base != 0;
6871 u32 cntl;
6872
6873 if (intel_crtc->cursor_visible == visible)
6874 return;
6875
9db4a9c7 6876 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6877 if (visible) {
6878 /* On these chipsets we can only modify the base whilst
6879 * the cursor is disabled.
6880 */
9db4a9c7 6881 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6882
6883 cntl &= ~(CURSOR_FORMAT_MASK);
6884 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6885 cntl |= CURSOR_ENABLE |
6886 CURSOR_GAMMA_ENABLE |
6887 CURSOR_FORMAT_ARGB;
6888 } else
6889 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6890 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6891
6892 intel_crtc->cursor_visible = visible;
6893}
6894
6895static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6896{
6897 struct drm_device *dev = crtc->dev;
6898 struct drm_i915_private *dev_priv = dev->dev_private;
6899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6900 int pipe = intel_crtc->pipe;
6901 bool visible = base != 0;
6902
6903 if (intel_crtc->cursor_visible != visible) {
548f245b 6904 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6905 if (base) {
6906 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6907 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6908 cntl |= pipe << 28; /* Connect to correct pipe */
6909 } else {
6910 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6911 cntl |= CURSOR_MODE_DISABLE;
6912 }
9db4a9c7 6913 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6914
6915 intel_crtc->cursor_visible = visible;
6916 }
6917 /* and commit changes on next vblank */
9db4a9c7 6918 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6919}
6920
65a21cd6
JB		 6921static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6922{
6923 struct drm_device *dev = crtc->dev;
6924 struct drm_i915_private *dev_priv = dev->dev_private;
6925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6926 int pipe = intel_crtc->pipe;
6927 bool visible = base != 0;
6928
6929 if (intel_crtc->cursor_visible != visible) {
6930 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6931 if (base) {
6932 cntl &= ~CURSOR_MODE;
6933 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6934 } else {
6935 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6936 cntl |= CURSOR_MODE_DISABLE;
6937 }
1f5d76db 6938 if (IS_HASWELL(dev)) {
86d3efce 6939 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6940 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6941 }
65a21cd6
JB		 6942 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6943
6944 intel_crtc->cursor_visible = visible;
6945 }
6946 /* and commit changes on next vblank */
6947 I915_WRITE(CURBASE_IVB(pipe), base);
6948}
6949
cda4b7d3 6950/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6951static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6952 bool on)
cda4b7d3
CW		 6953{
6954 struct drm_device *dev = crtc->dev;
6955 struct drm_i915_private *dev_priv = dev->dev_private;
6956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6957 int pipe = intel_crtc->pipe;
6958 int x = intel_crtc->cursor_x;
6959 int y = intel_crtc->cursor_y;
d6e4db15 6960 u32 base = 0, pos = 0;
cda4b7d3
CW		 6961 bool visible;
6962
d6e4db15 6963 if (on)
cda4b7d3 6964 base = intel_crtc->cursor_addr;
cda4b7d3 6965
d6e4db15
VS		 6966 if (x >= intel_crtc->config.pipe_src_w)
6967 base = 0;
6968
6969 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 6970 base = 0;
6971
6972 if (x < 0) {
efc9064e 6973 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 6974 base = 0;
6975
6976 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6977 x = -x;
6978 }
6979 pos |= x << CURSOR_X_SHIFT;
6980
6981 if (y < 0) {
efc9064e 6982 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 6983 base = 0;
6984
6985 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6986 y = -y;
6987 }
6988 pos |= y << CURSOR_Y_SHIFT;
6989
6990 visible = base != 0;
560b85bb 6991 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6992 return;
6993
0cd83aa9 6994 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6995 I915_WRITE(CURPOS_IVB(pipe), pos);
6996 ivb_update_cursor(crtc, base);
6997 } else {
6998 I915_WRITE(CURPOS(pipe), pos);
6999 if (IS_845G(dev) || IS_I865G(dev))
7000 i845_update_cursor(crtc, base);
7001 else
7002 i9xx_update_cursor(crtc, base);
7003 }
cda4b7d3
CW		 7004}
7005
79e53945 7006static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7007 struct drm_file *file,
79e53945
JB		 7008 uint32_t handle,
7009 uint32_t width, uint32_t height)
7010{
7011 struct drm_device *dev = crtc->dev;
7012 struct drm_i915_private *dev_priv = dev->dev_private;
7013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7014 struct drm_i915_gem_object *obj;
cda4b7d3 7015 uint32_t addr;
3f8bc370 7016 int ret;
79e53945 7017
79e53945
JB		 7018 /* if we want to turn off the cursor ignore width and height */
7019 if (!handle) {
28c97730 7020 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7021 addr = 0;
05394f39 7022 obj = NULL;
5004417d 7023 mutex_lock(&dev->struct_mutex);
3f8bc370 7024 goto finish;
79e53945
JB		 7025 }
7026
7027 /* Currently we only support 64x64 cursors */
7028 if (width != 64 || height != 64) {
7029 DRM_ERROR("we currently only support 64x64 cursors\n");
7030 return -EINVAL;
7031 }
7032
05394f39 7033 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7034 if (&obj->base == NULL)
79e53945
JB		 7035 return -ENOENT;
7036
05394f39 7037 if (obj->base.size < width * height * 4) {
79e53945 7038 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7039 ret = -ENOMEM;
7040 goto fail;
79e53945
JB		 7041 }
7042
71acb5eb 7043 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7044 mutex_lock(&dev->struct_mutex);
b295d1b6 7045 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7046 unsigned alignment;
7047
d9e86c0e
CW		 7048 if (obj->tiling_mode) {
7049 DRM_ERROR("cursor cannot be tiled\n");
7050 ret = -EINVAL;
7051 goto fail_locked;
7052 }
7053
693db184
CW		 7054 /* Note that the w/a also requires 2 PTE of padding following
7055 * the bo. We currently fill all unused PTE with the shadow
7056 * page and so we should always have valid PTE following the
7057 * cursor preventing the VT-d warning.
7058 */
7059 alignment = 0;
7060 if (need_vtd_wa(dev))
7061 alignment = 64*1024;
7062
7063 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7064 if (ret) {
7065 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7066 goto fail_locked;
e7b526bb
CW		 7067 }
7068
d9e86c0e
CW		 7069 ret = i915_gem_object_put_fence(obj);
7070 if (ret) {
2da3b9b9 7071 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7072 goto fail_unpin;
7073 }
7074
f343c5f6 7075 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7076 } else {
6eeefaf3 7077 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7078 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7079 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7080 align);
71acb5eb
DA		 7081 if (ret) {
7082 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7083 goto fail_locked;
71acb5eb 7084 }
05394f39 7085 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7086 }
7087
a6c45cf0 7088 if (IS_GEN2(dev))
14b60391
JB		 7089 I915_WRITE(CURSIZE, (height << 12) | width);
7090
3f8bc370 7091 finish:
3f8bc370 7092 if (intel_crtc->cursor_bo) {
b295d1b6 7093 if (dev_priv->info->cursor_needs_physical) {
05394f39 7094 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7095 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7096 } else
cc98b413 7097 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7098 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7099 }
80824003 7100
7f9872e0 7101 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7102
7103 intel_crtc->cursor_addr = addr;
05394f39 7104 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7105 intel_crtc->cursor_width = width;
7106 intel_crtc->cursor_height = height;
7107
f2f5f771
VS		 7108 if (intel_crtc->active)
7109 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7110
79e53945 7111 return 0;
e7b526bb 7112fail_unpin:
cc98b413 7113 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7114fail_locked:
34b8686e 7115 mutex_unlock(&dev->struct_mutex);
bc9025bd 7116fail:
05394f39 7117 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7118 return ret;
79e53945
JB		 7119}
7120
7121static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7122{
79e53945 7123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7124
cda4b7d3
CW		 7125 intel_crtc->cursor_x = x;
7126 intel_crtc->cursor_y = y;
652c393a 7127
f2f5f771
VS		 7128 if (intel_crtc->active)
7129 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7130
7131 return 0;
b8c00ac5
DA		 7132}
7133
79e53945 7134static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7135 u16 *blue, uint32_t start, uint32_t size)
79e53945 7136{
7203425a 7137 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7139
7203425a 7140 for (i = start; i < end; i++) {
79e53945
JB		 7141 intel_crtc->lut_r[i] = red[i] >> 8;
7142 intel_crtc->lut_g[i] = green[i] >> 8;
7143 intel_crtc->lut_b[i] = blue[i] >> 8;
7144 }
7145
7146 intel_crtc_load_lut(crtc);
7147}
7148
79e53945
JB		 7149/* VESA 640x480x72Hz mode to set on the pipe */
7150static struct drm_display_mode load_detect_mode = {
7151 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7152 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7153};
7154
d2dff872
CW		 7155static struct drm_framebuffer *
7156intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7157 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7158 struct drm_i915_gem_object *obj)
7159{
7160 struct intel_framebuffer *intel_fb;
7161 int ret;
7162
7163 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7164 if (!intel_fb) {
7165 drm_gem_object_unreference_unlocked(&obj->base);
7166 return ERR_PTR(-ENOMEM);
7167 }
7168
7169 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7170 if (ret) {
7171 drm_gem_object_unreference_unlocked(&obj->base);
7172 kfree(intel_fb);
7173 return ERR_PTR(ret);
7174 }
7175
7176 return &intel_fb->base;
7177}
7178
7179static u32
7180intel_framebuffer_pitch_for_width(int width, int bpp)
7181{
7182 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7183 return ALIGN(pitch, 64);
7184}
7185
7186static u32
7187intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7188{
7189 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7190 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7191}
7192
7193static struct drm_framebuffer *
7194intel_framebuffer_create_for_mode(struct drm_device *dev,
7195 struct drm_display_mode *mode,
7196 int depth, int bpp)
7197{
7198 struct drm_i915_gem_object *obj;
0fed39bd 7199 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7200
7201 obj = i915_gem_alloc_object(dev,
7202 intel_framebuffer_size_for_mode(mode, bpp));
7203 if (obj == NULL)
7204 return ERR_PTR(-ENOMEM);
7205
7206 mode_cmd.width = mode->hdisplay;
7207 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7208 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7209 bpp);
5ca0c34a 7210 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7211
7212 return intel_framebuffer_create(dev, &mode_cmd, obj);
7213}
7214
7215static struct drm_framebuffer *
7216mode_fits_in_fbdev(struct drm_device *dev,
7217 struct drm_display_mode *mode)
7218{
7219 struct drm_i915_private *dev_priv = dev->dev_private;
7220 struct drm_i915_gem_object *obj;
7221 struct drm_framebuffer *fb;
7222
7223 if (dev_priv->fbdev == NULL)
7224 return NULL;
7225
7226 obj = dev_priv->fbdev->ifb.obj;
7227 if (obj == NULL)
7228 return NULL;
7229
7230 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7231 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7232 fb->bits_per_pixel))
d2dff872
CW		 7233 return NULL;
7234
01f2c773 7235 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7236 return NULL;
7237
7238 return fb;
7239}
7240
d2434ab7 7241bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7242 struct drm_display_mode *mode,
8261b191 7243 struct intel_load_detect_pipe *old)
79e53945
JB		 7244{
7245 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7246 struct intel_encoder *intel_encoder =
7247 intel_attached_encoder(connector);
79e53945 7248 struct drm_crtc *possible_crtc;
4ef69c7a 7249 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7250 struct drm_crtc *crtc = NULL;
7251 struct drm_device *dev = encoder->dev;
94352cf9 7252 struct drm_framebuffer *fb;
79e53945
JB		 7253 int i = -1;
7254
d2dff872
CW		 7255 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7256 connector->base.id, drm_get_connector_name(connector),
7257 encoder->base.id, drm_get_encoder_name(encoder));
7258
79e53945
JB		 7259 /*
7260 * Algorithm gets a little messy:
7a5e4805 7261 *
79e53945
JB		 7262 * - if the connector already has an assigned crtc, use it (but make
7263 * sure it's on first)
7a5e4805 7264 *
79e53945
JB		 7265 * - try to find the first unused crtc that can drive this connector,
7266 * and use that if we find one
79e53945
JB		 7267 */
7268
7269 /* See if we already have a CRTC for this connector */
7270 if (encoder->crtc) {
7271 crtc = encoder->crtc;
8261b191 7272
7b24056b
DV		 7273 mutex_lock(&crtc->mutex);
7274
24218aac 7275 old->dpms_mode = connector->dpms;
8261b191
CW		 7276 old->load_detect_temp = false;
7277
7278 /* Make sure the crtc and connector are running */
24218aac
DV		 7279 if (connector->dpms != DRM_MODE_DPMS_ON)
7280 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7281
7173188d 7282 return true;
79e53945
JB		 7283 }
7284
7285 /* Find an unused one (if possible) */
7286 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7287 i++;
7288 if (!(encoder->possible_crtcs & (1 << i)))
7289 continue;
7290 if (!possible_crtc->enabled) {
7291 crtc = possible_crtc;
7292 break;
7293 }
79e53945
JB		 7294 }
7295
7296 /*
7297 * If we didn't find an unused CRTC, don't use any.
7298 */
7299 if (!crtc) {
7173188d
CW		 7300 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7301 return false;
79e53945
JB		 7302 }
7303
7b24056b 7304 mutex_lock(&crtc->mutex);
fc303101
DV		 7305 intel_encoder->new_crtc = to_intel_crtc(crtc);
7306 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7307
7308 intel_crtc = to_intel_crtc(crtc);
24218aac 7309 old->dpms_mode = connector->dpms;
8261b191 7310 old->load_detect_temp = true;
d2dff872 7311 old->release_fb = NULL;
79e53945 7312
6492711d
CW		 7313 if (!mode)
7314 mode = &load_detect_mode;
79e53945 7315
d2dff872
CW		 7316 /* We need a framebuffer large enough to accommodate all accesses
7317 * that the plane may generate whilst we perform load detection.
7318 * We can not rely on the fbcon either being present (we get called
7319 * during its initialisation to detect all boot displays, or it may
7320 * not even exist) or that it is large enough to satisfy the
7321 * requested mode.
7322 */
94352cf9
DV		 7323 fb = mode_fits_in_fbdev(dev, mode);
7324 if (fb == NULL) {
d2dff872 7325 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7326 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7327 old->release_fb = fb;
d2dff872
CW		 7328 } else
7329 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7330 if (IS_ERR(fb)) {
d2dff872 7331 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7332 mutex_unlock(&crtc->mutex);
0e8b3d3e 7333 return false;
79e53945 7334 }
79e53945 7335
c0c36b94 7336 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7337 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7338 if (old->release_fb)
7339 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7340 mutex_unlock(&crtc->mutex);
0e8b3d3e 7341 return false;
79e53945 7342 }
7173188d 7343
79e53945 7344 /* let the connector get through one full cycle before testing */
9d0498a2 7345 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7346 return true;
79e53945
JB		 7347}
7348
d2434ab7 7349void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7350 struct intel_load_detect_pipe *old)
79e53945 7351{
d2434ab7
DV		 7352 struct intel_encoder *intel_encoder =
7353 intel_attached_encoder(connector);
4ef69c7a 7354 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7355 struct drm_crtc *crtc = encoder->crtc;
79e53945 7356
d2dff872
CW		 7357 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7358 connector->base.id, drm_get_connector_name(connector),
7359 encoder->base.id, drm_get_encoder_name(encoder));
7360
8261b191 7361 if (old->load_detect_temp) {
fc303101
DV		 7362 to_intel_connector(connector)->new_encoder = NULL;
7363 intel_encoder->new_crtc = NULL;
7364 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7365
36206361
DV		 7366 if (old->release_fb) {
7367 drm_framebuffer_unregister_private(old->release_fb);
7368 drm_framebuffer_unreference(old->release_fb);
7369 }
d2dff872 7370
67c96400 7371 mutex_unlock(&crtc->mutex);
0622a53c 7372 return;
79e53945
JB		 7373 }
7374
c751ce4f 7375 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7376 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7377 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7378
7379 mutex_unlock(&crtc->mutex);
79e53945
JB		 7380}
7381
da4a1efa
VS		 7382static int i9xx_pll_refclk(struct drm_device *dev,
7383 const struct intel_crtc_config *pipe_config)
7384{
7385 struct drm_i915_private *dev_priv = dev->dev_private;
7386 u32 dpll = pipe_config->dpll_hw_state.dpll;
7387
7388 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7389 return dev_priv->vbt.lvds_ssc_freq * 1000;
7390 else if (HAS_PCH_SPLIT(dev))
7391 return 120000;
7392 else if (!IS_GEN2(dev))
7393 return 96000;
7394 else
7395 return 48000;
7396}
7397
79e53945 7398/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7399static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7400 struct intel_crtc_config *pipe_config)
79e53945 7401{
f1f644dc 7402 struct drm_device *dev = crtc->base.dev;
79e53945 7403 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7404 int pipe = pipe_config->cpu_transcoder;
293623f7 7405 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7406 u32 fp;
7407 intel_clock_t clock;
da4a1efa 7408 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7409
7410 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7411 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7412 else
293623f7 7413 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7414
7415 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7416 if (IS_PINEVIEW(dev)) {
7417 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7418 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7419 } else {
7420 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7421 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7422 }
7423
a6c45cf0 7424 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7425 if (IS_PINEVIEW(dev))
7426 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7427 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7428 else
7429 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7430 DPLL_FPA01_P1_POST_DIV_SHIFT);
7431
7432 switch (dpll & DPLL_MODE_MASK) {
7433 case DPLLB_MODE_DAC_SERIAL:
7434 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7435 5 : 10;
7436 break;
7437 case DPLLB_MODE_LVDS:
7438 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7439 7 : 14;
7440 break;
7441 default:
28c97730 7442 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7443 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7444 return;
79e53945
JB		 7445 }
7446
ac58c3f0 7447 if (IS_PINEVIEW(dev))
da4a1efa 7448 pineview_clock(refclk, &clock);
ac58c3f0 7449 else
da4a1efa 7450 i9xx_clock(refclk, &clock);
79e53945
JB		 7451 } else {
7452 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7453
7454 if (is_lvds) {
7455 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7456 DPLL_FPA01_P1_POST_DIV_SHIFT);
7457 clock.p2 = 14;
79e53945
JB		 7458 } else {
7459 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7460 clock.p1 = 2;
7461 else {
7462 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7463 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7464 }
7465 if (dpll & PLL_P2_DIVIDE_BY_4)
7466 clock.p2 = 4;
7467 else
7468 clock.p2 = 2;
79e53945 7469 }
da4a1efa
VS		 7470
7471 i9xx_clock(refclk, &clock);
79e53945
JB		 7472 }
7473
18442d08
VS		 7474 /*
7475 * This value includes pixel_multiplier. We will use
7476 * port_clock to compute adjusted_mode.clock in the
7477 * encoder's get_config() function.
7478 */
7479 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7480}
7481
6878da05
VS		 7482int intel_dotclock_calculate(int link_freq,
7483 const struct intel_link_m_n *m_n)
f1f644dc 7484{
f1f644dc
JB		 7485 /*
7486 * The calculation for the data clock is:
1041a02f 7487 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7488 * But we want to avoid losing precison if possible, so:
1041a02f 7489 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7490 *
7491 * and the link clock is simpler:
1041a02f 7492 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7493 */
7494
6878da05
VS		 7495 if (!m_n->link_n)
7496 return 0;
f1f644dc 7497
6878da05
VS		 7498 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7499}
f1f644dc 7500
18442d08
VS		 7501static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7502 struct intel_crtc_config *pipe_config)
6878da05
VS		 7503{
7504 struct drm_device *dev = crtc->base.dev;
79e53945 7505
18442d08
VS		 7506 /* read out port_clock from the DPLL */
7507 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7508
f1f644dc 7509 /*
18442d08
VS		 7510 * This value does not include pixel_multiplier.
7511 * We will check that port_clock and adjusted_mode.clock
7512 * agree once we know their relationship in the encoder's
7513 * get_config() function.
79e53945 7514 */
18442d08
VS		 7515 pipe_config->adjusted_mode.clock =
7516 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7517 &pipe_config->fdi_m_n);
79e53945
JB		 7518}
7519
7520/** Returns the currently programmed mode of the given pipe. */
7521struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7522 struct drm_crtc *crtc)
7523{
548f245b 7524 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7526 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7527 struct drm_display_mode *mode;
f1f644dc 7528 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7529 int htot = I915_READ(HTOTAL(cpu_transcoder));
7530 int hsync = I915_READ(HSYNC(cpu_transcoder));
7531 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7532 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7533 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7534
7535 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7536 if (!mode)
7537 return NULL;
7538
f1f644dc
JB		 7539 /*
7540 * Construct a pipe_config sufficient for getting the clock info
7541 * back out of crtc_clock_get.
7542 *
7543 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7544 * to use a real value here instead.
7545 */
293623f7 7546 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7547 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7548 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7549 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7550 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7551 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7552
773ae034 7553 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7554 mode->hdisplay = (htot & 0xffff) + 1;
7555 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7556 mode->hsync_start = (hsync & 0xffff) + 1;
7557 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7558 mode->vdisplay = (vtot & 0xffff) + 1;
7559 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7560 mode->vsync_start = (vsync & 0xffff) + 1;
7561 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7562
7563 drm_mode_set_name(mode);
79e53945
JB		 7564
7565 return mode;
7566}
7567
3dec0095 7568static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7569{
7570 struct drm_device *dev = crtc->dev;
7571 drm_i915_private_t *dev_priv = dev->dev_private;
7572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7573 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7574 int dpll_reg = DPLL(pipe);
7575 int dpll;
652c393a 7576
bad720ff 7577 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7578 return;
7579
7580 if (!dev_priv->lvds_downclock_avail)
7581 return;
7582
dbdc6479 7583 dpll = I915_READ(dpll_reg);
652c393a 7584 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7585 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7586
8ac5a6d5 7587 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7588
7589 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7590 I915_WRITE(dpll_reg, dpll);
9d0498a2 7591 intel_wait_for_vblank(dev, pipe);
dbdc6479 7592
652c393a
JB		 7593 dpll = I915_READ(dpll_reg);
7594 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7595 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7596 }
652c393a
JB		 7597}
7598
7599static void intel_decrease_pllclock(struct drm_crtc *crtc)
7600{
7601 struct drm_device *dev = crtc->dev;
7602 drm_i915_private_t *dev_priv = dev->dev_private;
7603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7604
bad720ff 7605 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7606 return;
7607
7608 if (!dev_priv->lvds_downclock_avail)
7609 return;
7610
7611 /*
7612 * Since this is called by a timer, we should never get here in
7613 * the manual case.
7614 */
7615 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7616 int pipe = intel_crtc->pipe;
7617 int dpll_reg = DPLL(pipe);
7618 int dpll;
f6e5b160 7619
44d98a61 7620 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7621
8ac5a6d5 7622 assert_panel_unlocked(dev_priv, pipe);
652c393a 7623
dc257cf1 7624 dpll = I915_READ(dpll_reg);
652c393a
JB		 7625 dpll |= DISPLAY_RATE_SELECT_FPA1;
7626 I915_WRITE(dpll_reg, dpll);
9d0498a2 7627 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7628 dpll = I915_READ(dpll_reg);
7629 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7630 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7631 }
7632
7633}
7634
f047e395
CW		 7635void intel_mark_busy(struct drm_device *dev)
7636{
c67a470b
PZ		 7637 struct drm_i915_private *dev_priv = dev->dev_private;
7638
7639 hsw_package_c8_gpu_busy(dev_priv);
7640 i915_update_gfx_val(dev_priv);
f047e395
CW		 7641}
7642
7643void intel_mark_idle(struct drm_device *dev)
652c393a 7644{
c67a470b 7645 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7646 struct drm_crtc *crtc;
652c393a 7647
c67a470b
PZ		 7648 hsw_package_c8_gpu_idle(dev_priv);
7649
652c393a
JB		 7650 if (!i915_powersave)
7651 return;
7652
652c393a 7653 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7654 if (!crtc->fb)
7655 continue;
7656
725a5b54 7657 intel_decrease_pllclock(crtc);
652c393a 7658 }
652c393a
JB		 7659}
7660
c65355bb
CW		 7661void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7662 struct intel_ring_buffer *ring)
652c393a 7663{
f047e395
CW		 7664 struct drm_device *dev = obj->base.dev;
7665 struct drm_crtc *crtc;
652c393a 7666
f047e395 7667 if (!i915_powersave)
acb87dfb
CW		 7668 return;
7669
652c393a
JB		 7670 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7671 if (!crtc->fb)
7672 continue;
7673
c65355bb
CW		 7674 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7675 continue;
7676
7677 intel_increase_pllclock(crtc);
7678 if (ring && intel_fbc_enabled(dev))
7679 ring->fbc_dirty = true;
652c393a
JB		 7680 }
7681}
7682
79e53945
JB		 7683static void intel_crtc_destroy(struct drm_crtc *crtc)
7684{
7685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7686 struct drm_device *dev = crtc->dev;
7687 struct intel_unpin_work *work;
7688 unsigned long flags;
7689
7690 spin_lock_irqsave(&dev->event_lock, flags);
7691 work = intel_crtc->unpin_work;
7692 intel_crtc->unpin_work = NULL;
7693 spin_unlock_irqrestore(&dev->event_lock, flags);
7694
7695 if (work) {
7696 cancel_work_sync(&work->work);
7697 kfree(work);
7698 }
79e53945 7699
40ccc72b
MK		 7700 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7701
79e53945 7702 drm_crtc_cleanup(crtc);
67e77c5a 7703
79e53945
JB		 7704 kfree(intel_crtc);
7705}
7706
6b95a207
KH		 7707static void intel_unpin_work_fn(struct work_struct *__work)
7708{
7709 struct intel_unpin_work *work =
7710 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7711 struct drm_device *dev = work->crtc->dev;
6b95a207 7712
b4a98e57 7713 mutex_lock(&dev->struct_mutex);
1690e1eb 7714 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7715 drm_gem_object_unreference(&work->pending_flip_obj->base);
7716 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7717
b4a98e57
CW		 7718 intel_update_fbc(dev);
7719 mutex_unlock(&dev->struct_mutex);
7720
7721 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7722 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7723
6b95a207
KH		 7724 kfree(work);
7725}
7726
1afe3e9d 7727static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7728 struct drm_crtc *crtc)
6b95a207
KH		 7729{
7730 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7732 struct intel_unpin_work *work;
6b95a207
KH		 7733 unsigned long flags;
7734
7735 /* Ignore early vblank irqs */
7736 if (intel_crtc == NULL)
7737 return;
7738
7739 spin_lock_irqsave(&dev->event_lock, flags);
7740 work = intel_crtc->unpin_work;
e7d841ca
CW		 7741
7742 /* Ensure we don't miss a work->pending update ... */
7743 smp_rmb();
7744
7745 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7746 spin_unlock_irqrestore(&dev->event_lock, flags);
7747 return;
7748 }
7749
e7d841ca
CW		 7750 /* and that the unpin work is consistent wrt ->pending. */
7751 smp_rmb();
7752
6b95a207 7753 intel_crtc->unpin_work = NULL;
6b95a207 7754
45a066eb
RC		 7755 if (work->event)
7756 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7757
0af7e4df
MK		 7758 drm_vblank_put(dev, intel_crtc->pipe);
7759
6b95a207
KH		 7760 spin_unlock_irqrestore(&dev->event_lock, flags);
7761
2c10d571 7762 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7763
7764 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7765
7766 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7767}
7768
1afe3e9d
JB		 7769void intel_finish_page_flip(struct drm_device *dev, int pipe)
7770{
7771 drm_i915_private_t *dev_priv = dev->dev_private;
7772 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7773
49b14a5c 7774 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7775}
7776
7777void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7778{
7779 drm_i915_private_t *dev_priv = dev->dev_private;
7780 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7781
49b14a5c 7782 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7783}
7784
6b95a207
KH		 7785void intel_prepare_page_flip(struct drm_device *dev, int plane)
7786{
7787 drm_i915_private_t *dev_priv = dev->dev_private;
7788 struct intel_crtc *intel_crtc =
7789 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7790 unsigned long flags;
7791
e7d841ca
CW		 7792 /* NB: An MMIO update of the plane base pointer will also
7793 * generate a page-flip completion irq, i.e. every modeset
7794 * is also accompanied by a spurious intel_prepare_page_flip().
7795 */
6b95a207 7796 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7797 if (intel_crtc->unpin_work)
7798 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7799 spin_unlock_irqrestore(&dev->event_lock, flags);
7800}
7801
e7d841ca
CW		 7802inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7803{
7804 /* Ensure that the work item is consistent when activating it ... */
7805 smp_wmb();
7806 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7807 /* and that it is marked active as soon as the irq could fire. */
7808 smp_wmb();
7809}
7810
8c9f3aaf
JB		 7811static int intel_gen2_queue_flip(struct drm_device *dev,
7812 struct drm_crtc *crtc,
7813 struct drm_framebuffer *fb,
ed8d1975
KP		 7814 struct drm_i915_gem_object *obj,
7815 uint32_t flags)
8c9f3aaf
JB		 7816{
7817 struct drm_i915_private *dev_priv = dev->dev_private;
7818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7819 u32 flip_mask;
6d90c952 7820 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7821 int ret;
7822
6d90c952 7823 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7824 if (ret)
83d4092b 7825 goto err;
8c9f3aaf 7826
6d90c952 7827 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7828 if (ret)
83d4092b 7829 goto err_unpin;
8c9f3aaf
JB		 7830
7831 /* Can't queue multiple flips, so wait for the previous
7832 * one to finish before executing the next.
7833 */
7834 if (intel_crtc->plane)
7835 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7836 else
7837 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7838 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7839 intel_ring_emit(ring, MI_NOOP);
7840 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7841 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7842 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7843 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7844 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7845
7846 intel_mark_page_flip_active(intel_crtc);
09246732 7847 __intel_ring_advance(ring);
83d4092b
CW		 7848 return 0;
7849
7850err_unpin:
7851 intel_unpin_fb_obj(obj);
7852err:
8c9f3aaf
JB		 7853 return ret;
7854}
7855
7856static int intel_gen3_queue_flip(struct drm_device *dev,
7857 struct drm_crtc *crtc,
7858 struct drm_framebuffer *fb,
ed8d1975
KP		 7859 struct drm_i915_gem_object *obj,
7860 uint32_t flags)
8c9f3aaf
JB		 7861{
7862 struct drm_i915_private *dev_priv = dev->dev_private;
7863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7864 u32 flip_mask;
6d90c952 7865 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7866 int ret;
7867
6d90c952 7868 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7869 if (ret)
83d4092b 7870 goto err;
8c9f3aaf 7871
6d90c952 7872 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7873 if (ret)
83d4092b 7874 goto err_unpin;
8c9f3aaf
JB		 7875
7876 if (intel_crtc->plane)
7877 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7878 else
7879 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7880 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7881 intel_ring_emit(ring, MI_NOOP);
7882 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7883 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7884 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7885 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7886 intel_ring_emit(ring, MI_NOOP);
7887
e7d841ca 7888 intel_mark_page_flip_active(intel_crtc);
09246732 7889 __intel_ring_advance(ring);
83d4092b
CW		 7890 return 0;
7891
7892err_unpin:
7893 intel_unpin_fb_obj(obj);
7894err:
8c9f3aaf
JB		 7895 return ret;
7896}
7897
7898static int intel_gen4_queue_flip(struct drm_device *dev,
7899 struct drm_crtc *crtc,
7900 struct drm_framebuffer *fb,
ed8d1975
KP		 7901 struct drm_i915_gem_object *obj,
7902 uint32_t flags)
8c9f3aaf
JB		 7903{
7904 struct drm_i915_private *dev_priv = dev->dev_private;
7905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7906 uint32_t pf, pipesrc;
6d90c952 7907 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7908 int ret;
7909
6d90c952 7910 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7911 if (ret)
83d4092b 7912 goto err;
8c9f3aaf 7913
6d90c952 7914 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7915 if (ret)
83d4092b 7916 goto err_unpin;
8c9f3aaf
JB		 7917
7918 /* i965+ uses the linear or tiled offsets from the
7919 * Display Registers (which do not change across a page-flip)
7920 * so we need only reprogram the base address.
7921 */
6d90c952
DV		 7922 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7923 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7924 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7925 intel_ring_emit(ring,
f343c5f6 7926 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7927 obj->tiling_mode);
8c9f3aaf
JB		 7928
7929 /* XXX Enabling the panel-fitter across page-flip is so far
7930 * untested on non-native modes, so ignore it for now.
7931 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7932 */
7933 pf = 0;
7934 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7935 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7936
7937 intel_mark_page_flip_active(intel_crtc);
09246732 7938 __intel_ring_advance(ring);
83d4092b
CW		 7939 return 0;
7940
7941err_unpin:
7942 intel_unpin_fb_obj(obj);
7943err:
8c9f3aaf
JB		 7944 return ret;
7945}
7946
7947static int intel_gen6_queue_flip(struct drm_device *dev,
7948 struct drm_crtc *crtc,
7949 struct drm_framebuffer *fb,
ed8d1975
KP		 7950 struct drm_i915_gem_object *obj,
7951 uint32_t flags)
8c9f3aaf
JB		 7952{
7953 struct drm_i915_private *dev_priv = dev->dev_private;
7954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7955 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7956 uint32_t pf, pipesrc;
7957 int ret;
7958
6d90c952 7959 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7960 if (ret)
83d4092b 7961 goto err;
8c9f3aaf 7962
6d90c952 7963 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7964 if (ret)
83d4092b 7965 goto err_unpin;
8c9f3aaf 7966
6d90c952
DV		 7967 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7968 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7969 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7970 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7971
dc257cf1
DV		 7972 /* Contrary to the suggestions in the documentation,
7973 * "Enable Panel Fitter" does not seem to be required when page
7974 * flipping with a non-native mode, and worse causes a normal
7975 * modeset to fail.
7976 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7977 */
7978 pf = 0;
8c9f3aaf 7979 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7980 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7981
7982 intel_mark_page_flip_active(intel_crtc);
09246732 7983 __intel_ring_advance(ring);
83d4092b
CW		 7984 return 0;
7985
7986err_unpin:
7987 intel_unpin_fb_obj(obj);
7988err:
8c9f3aaf
JB		 7989 return ret;
7990}
7991
7c9017e5
JB		 7992static int intel_gen7_queue_flip(struct drm_device *dev,
7993 struct drm_crtc *crtc,
7994 struct drm_framebuffer *fb,
ed8d1975
KP		 7995 struct drm_i915_gem_object *obj,
7996 uint32_t flags)
7c9017e5
JB		 7997{
7998 struct drm_i915_private *dev_priv = dev->dev_private;
7999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8000 struct intel_ring_buffer *ring;
cb05d8de 8001 uint32_t plane_bit = 0;
ffe74d75
CW		 8002 int len, ret;
8003
8004 ring = obj->ring;
1c5fd085 8005 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8006 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8007
8008 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8009 if (ret)
83d4092b 8010 goto err;
7c9017e5 8011
cb05d8de
DV		 8012 switch(intel_crtc->plane) {
8013 case PLANE_A:
8014 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8015 break;
8016 case PLANE_B:
8017 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8018 break;
8019 case PLANE_C:
8020 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8021 break;
8022 default:
8023 WARN_ONCE(1, "unknown plane in flip command\n");
8024 ret = -ENODEV;
ab3951eb 8025 goto err_unpin;
cb05d8de
DV		 8026 }
8027
ffe74d75
CW		 8028 len = 4;
8029 if (ring->id == RCS)
8030 len += 6;
8031
8032 ret = intel_ring_begin(ring, len);
7c9017e5 8033 if (ret)
83d4092b 8034 goto err_unpin;
7c9017e5 8035
ffe74d75
CW		 8036 /* Unmask the flip-done completion message. Note that the bspec says that
8037 * we should do this for both the BCS and RCS, and that we must not unmask
8038 * more than one flip event at any time (or ensure that one flip message
8039 * can be sent by waiting for flip-done prior to queueing new flips).
8040 * Experimentation says that BCS works despite DERRMR masking all
8041 * flip-done completion events and that unmasking all planes at once
8042 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8043 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8044 */
8045 if (ring->id == RCS) {
8046 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8047 intel_ring_emit(ring, DERRMR);
8048 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8049 DERRMR_PIPEB_PRI_FLIP_DONE |
8050 DERRMR_PIPEC_PRI_FLIP_DONE));
8051 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8052 intel_ring_emit(ring, DERRMR);
8053 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8054 }
8055
cb05d8de 8056 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8057 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8058 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8059 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8060
8061 intel_mark_page_flip_active(intel_crtc);
09246732 8062 __intel_ring_advance(ring);
83d4092b
CW		 8063 return 0;
8064
8065err_unpin:
8066 intel_unpin_fb_obj(obj);
8067err:
7c9017e5
JB		 8068 return ret;
8069}
8070
8c9f3aaf
JB		 8071static int intel_default_queue_flip(struct drm_device *dev,
8072 struct drm_crtc *crtc,
8073 struct drm_framebuffer *fb,
ed8d1975
KP		 8074 struct drm_i915_gem_object *obj,
8075 uint32_t flags)
8c9f3aaf
JB		 8076{
8077 return -ENODEV;
8078}
8079
6b95a207
KH		 8080static int intel_crtc_page_flip(struct drm_crtc *crtc,
8081 struct drm_framebuffer *fb,
ed8d1975
KP		 8082 struct drm_pending_vblank_event *event,
8083 uint32_t page_flip_flags)
6b95a207
KH		 8084{
8085 struct drm_device *dev = crtc->dev;
8086 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8087 struct drm_framebuffer *old_fb = crtc->fb;
8088 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8090 struct intel_unpin_work *work;
8c9f3aaf 8091 unsigned long flags;
52e68630 8092 int ret;
6b95a207 8093
e6a595d2
VS		 8094 /* Can't change pixel format via MI display flips. */
8095 if (fb->pixel_format != crtc->fb->pixel_format)
8096 return -EINVAL;
8097
8098 /*
8099 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8100 * Note that pitch changes could also affect these register.
8101 */
8102 if (INTEL_INFO(dev)->gen > 3 &&
8103 (fb->offsets[0] != crtc->fb->offsets[0] ||
8104 fb->pitches[0] != crtc->fb->pitches[0]))
8105 return -EINVAL;
8106
b14c5679 8107 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8108 if (work == NULL)
8109 return -ENOMEM;
8110
6b95a207 8111 work->event = event;
b4a98e57 8112 work->crtc = crtc;
4a35f83b 8113 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8114 INIT_WORK(&work->work, intel_unpin_work_fn);
8115
7317c75e
JB		 8116 ret = drm_vblank_get(dev, intel_crtc->pipe);
8117 if (ret)
8118 goto free_work;
8119
6b95a207
KH		 8120 /* We borrow the event spin lock for protecting unpin_work */
8121 spin_lock_irqsave(&dev->event_lock, flags);
8122 if (intel_crtc->unpin_work) {
8123 spin_unlock_irqrestore(&dev->event_lock, flags);
8124 kfree(work);
7317c75e 8125 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8126
8127 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8128 return -EBUSY;
8129 }
8130 intel_crtc->unpin_work = work;
8131 spin_unlock_irqrestore(&dev->event_lock, flags);
8132
b4a98e57
CW		 8133 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8134 flush_workqueue(dev_priv->wq);
8135
79158103
CW		 8136 ret = i915_mutex_lock_interruptible(dev);
8137 if (ret)
8138 goto cleanup;
6b95a207 8139
75dfca80 8140 /* Reference the objects for the scheduled work. */
05394f39
CW		 8141 drm_gem_object_reference(&work->old_fb_obj->base);
8142 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8143
8144 crtc->fb = fb;
96b099fd 8145
e1f99ce6 8146 work->pending_flip_obj = obj;
e1f99ce6 8147
4e5359cd
SF		 8148 work->enable_stall_check = true;
8149
b4a98e57 8150 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8151 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8152
ed8d1975 8153 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8154 if (ret)
8155 goto cleanup_pending;
6b95a207 8156
7782de3b 8157 intel_disable_fbc(dev);
c65355bb 8158 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8159 mutex_unlock(&dev->struct_mutex);
8160
e5510fac
JB		 8161 trace_i915_flip_request(intel_crtc->plane, obj);
8162
6b95a207 8163 return 0;
96b099fd 8164
8c9f3aaf 8165cleanup_pending:
b4a98e57 8166 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8167 crtc->fb = old_fb;
05394f39
CW		 8168 drm_gem_object_unreference(&work->old_fb_obj->base);
8169 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8170 mutex_unlock(&dev->struct_mutex);
8171
79158103 8172cleanup:
96b099fd
CW		 8173 spin_lock_irqsave(&dev->event_lock, flags);
8174 intel_crtc->unpin_work = NULL;
8175 spin_unlock_irqrestore(&dev->event_lock, flags);
8176
7317c75e
JB		 8177 drm_vblank_put(dev, intel_crtc->pipe);
8178free_work:
96b099fd
CW		 8179 kfree(work);
8180
8181 return ret;
6b95a207
KH		 8182}
8183
f6e5b160 8184static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8185 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8186 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8187};
8188
50f56119
DV		 8189static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8190 struct drm_crtc *crtc)
8191{
8192 struct drm_device *dev;
8193 struct drm_crtc *tmp;
8194 int crtc_mask = 1;
47f1c6c9 8195
50f56119 8196 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8197
50f56119 8198 dev = crtc->dev;
47f1c6c9 8199
50f56119
DV		 8200 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8201 if (tmp == crtc)
8202 break;
8203 crtc_mask <<= 1;
8204 }
47f1c6c9 8205
50f56119
DV		 8206 if (encoder->possible_crtcs & crtc_mask)
8207 return true;
8208 return false;
47f1c6c9 8209}
79e53945 8210
9a935856
DV		 8211/**
8212 * intel_modeset_update_staged_output_state
8213 *
8214 * Updates the staged output configuration state, e.g. after we've read out the
8215 * current hw state.
8216 */
8217static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8218{
9a935856
DV		 8219 struct intel_encoder *encoder;
8220 struct intel_connector *connector;
f6e5b160 8221
9a935856
DV		 8222 list_for_each_entry(connector, &dev->mode_config.connector_list,
8223 base.head) {
8224 connector->new_encoder =
8225 to_intel_encoder(connector->base.encoder);
8226 }
f6e5b160 8227
9a935856
DV		 8228 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8229 base.head) {
8230 encoder->new_crtc =
8231 to_intel_crtc(encoder->base.crtc);
8232 }
f6e5b160
CW		 8233}
8234
9a935856
DV		 8235/**
8236 * intel_modeset_commit_output_state
8237 *
8238 * This function copies the stage display pipe configuration to the real one.
8239 */
8240static void intel_modeset_commit_output_state(struct drm_device *dev)
8241{
8242 struct intel_encoder *encoder;
8243 struct intel_connector *connector;
f6e5b160 8244
9a935856
DV		 8245 list_for_each_entry(connector, &dev->mode_config.connector_list,
8246 base.head) {
8247 connector->base.encoder = &connector->new_encoder->base;
8248 }
f6e5b160 8249
9a935856
DV		 8250 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8251 base.head) {
8252 encoder->base.crtc = &encoder->new_crtc->base;
8253 }
8254}
8255
050f7aeb
DV		 8256static void
8257connected_sink_compute_bpp(struct intel_connector * connector,
8258 struct intel_crtc_config *pipe_config)
8259{
8260 int bpp = pipe_config->pipe_bpp;
8261
8262 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8263 connector->base.base.id,
8264 drm_get_connector_name(&connector->base));
8265
8266 /* Don't use an invalid EDID bpc value */
8267 if (connector->base.display_info.bpc &&
8268 connector->base.display_info.bpc * 3 < bpp) {
8269 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8270 bpp, connector->base.display_info.bpc*3);
8271 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8272 }
8273
8274 /* Clamp bpp to 8 on screens without EDID 1.4 */
8275 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8276 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8277 bpp);
8278 pipe_config->pipe_bpp = 24;
8279 }
8280}
8281
4e53c2e0 8282static int
050f7aeb
DV		 8283compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8284 struct drm_framebuffer *fb,
8285 struct intel_crtc_config *pipe_config)
4e53c2e0 8286{
050f7aeb
DV		 8287 struct drm_device *dev = crtc->base.dev;
8288 struct intel_connector *connector;
4e53c2e0
DV		 8289 int bpp;
8290
d42264b1
DV		 8291 switch (fb->pixel_format) {
8292 case DRM_FORMAT_C8:
4e53c2e0
DV		 8293 bpp = 8*3; /* since we go through a colormap */
8294 break;
d42264b1
DV		 8295 case DRM_FORMAT_XRGB1555:
8296 case DRM_FORMAT_ARGB1555:
8297 /* checked in intel_framebuffer_init already */
8298 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8299 return -EINVAL;
8300 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8301 bpp = 6*3; /* min is 18bpp */
8302 break;
d42264b1
DV		 8303 case DRM_FORMAT_XBGR8888:
8304 case DRM_FORMAT_ABGR8888:
8305 /* checked in intel_framebuffer_init already */
8306 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8307 return -EINVAL;
8308 case DRM_FORMAT_XRGB8888:
8309 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8310 bpp = 8*3;
8311 break;
d42264b1
DV		 8312 case DRM_FORMAT_XRGB2101010:
8313 case DRM_FORMAT_ARGB2101010:
8314 case DRM_FORMAT_XBGR2101010:
8315 case DRM_FORMAT_ABGR2101010:
8316 /* checked in intel_framebuffer_init already */
8317 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8318 return -EINVAL;
4e53c2e0
DV		 8319 bpp = 10*3;
8320 break;
baba133a 8321 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8322 default:
8323 DRM_DEBUG_KMS("unsupported depth\n");
8324 return -EINVAL;
8325 }
8326
4e53c2e0
DV		 8327 pipe_config->pipe_bpp = bpp;
8328
8329 /* Clamp display bpp to EDID value */
8330 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8331 base.head) {
1b829e05
DV		 8332 if (!connector->new_encoder ||
8333 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8334 continue;
8335
050f7aeb 8336 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8337 }
8338
8339 return bpp;
8340}
8341
644db711
DV		 8342static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8343{
8344 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8345 "type: 0x%x flags: 0x%x\n",
8346 mode->clock,
8347 mode->crtc_hdisplay, mode->crtc_hsync_start,
8348 mode->crtc_hsync_end, mode->crtc_htotal,
8349 mode->crtc_vdisplay, mode->crtc_vsync_start,
8350 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8351}
8352
c0b03411
DV		 8353static void intel_dump_pipe_config(struct intel_crtc *crtc,
8354 struct intel_crtc_config *pipe_config,
8355 const char *context)
8356{
8357 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8358 context, pipe_name(crtc->pipe));
8359
8360 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8361 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8362 pipe_config->pipe_bpp, pipe_config->dither);
8363 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8364 pipe_config->has_pch_encoder,
8365 pipe_config->fdi_lanes,
8366 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8367 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8368 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8369 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8370 pipe_config->has_dp_encoder,
8371 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8372 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8373 pipe_config->dp_m_n.tu);
c0b03411
DV		 8374 DRM_DEBUG_KMS("requested mode:\n");
8375 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8376 DRM_DEBUG_KMS("adjusted mode:\n");
8377 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8378 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8379 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8380 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8381 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8382 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8383 pipe_config->gmch_pfit.control,
8384 pipe_config->gmch_pfit.pgm_ratios,
8385 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8386 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8387 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8388 pipe_config->pch_pfit.size,
8389 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8390 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8391 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8392}
8393
accfc0c5
DV		 8394static bool check_encoder_cloning(struct drm_crtc *crtc)
8395{
8396 int num_encoders = 0;
8397 bool uncloneable_encoders = false;
8398 struct intel_encoder *encoder;
8399
8400 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8401 base.head) {
8402 if (&encoder->new_crtc->base != crtc)
8403 continue;
8404
8405 num_encoders++;
8406 if (!encoder->cloneable)
8407 uncloneable_encoders = true;
8408 }
8409
8410 return !(num_encoders > 1 && uncloneable_encoders);
8411}
8412
b8cecdf5
DV		 8413static struct intel_crtc_config *
8414intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8415 struct drm_framebuffer *fb,
b8cecdf5 8416 struct drm_display_mode *mode)
ee7b9f93 8417{
7758a113 8418 struct drm_device *dev = crtc->dev;
7758a113 8419 struct intel_encoder *encoder;
b8cecdf5 8420 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8421 int plane_bpp, ret = -EINVAL;
8422 bool retry = true;
ee7b9f93 8423
accfc0c5
DV		 8424 if (!check_encoder_cloning(crtc)) {
8425 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8426 return ERR_PTR(-EINVAL);
8427 }
8428
b8cecdf5
DV		 8429 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8430 if (!pipe_config)
7758a113
DV		 8431 return ERR_PTR(-ENOMEM);
8432
b8cecdf5
DV		 8433 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8434 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd
VS		 8435
8436 pipe_config->pipe_src_w = mode->hdisplay;
8437 pipe_config->pipe_src_h = mode->vdisplay;
8438
e143a21c
DV		 8439 pipe_config->cpu_transcoder =
8440 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8441 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8442
2960bc9c
ID		 8443 /*
8444 * Sanitize sync polarity flags based on requested ones. If neither
8445 * positive or negative polarity is requested, treat this as meaning
8446 * negative polarity.
8447 */
8448 if (!(pipe_config->adjusted_mode.flags &
8449 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8450 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8451
8452 if (!(pipe_config->adjusted_mode.flags &
8453 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8454 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8455
050f7aeb
DV		 8456 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8457 * plane pixel format and any sink constraints into account. Returns the
8458 * source plane bpp so that dithering can be selected on mismatches
8459 * after encoders and crtc also have had their say. */
8460 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8461 fb, pipe_config);
4e53c2e0
DV		 8462 if (plane_bpp < 0)
8463 goto fail;
8464
e29c22c0 8465encoder_retry:
ef1b460d 8466 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8467 pipe_config->port_clock = 0;
ef1b460d 8468 pipe_config->pixel_multiplier = 1;
ff9a6750 8469
135c81b8
DV		 8470 /* Fill in default crtc timings, allow encoders to overwrite them. */
8471 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8472
7758a113
DV		 8473 /* Pass our mode to the connectors and the CRTC to give them a chance to
8474 * adjust it according to limitations or connector properties, and also
8475 * a chance to reject the mode entirely.
47f1c6c9 8476 */
7758a113
DV		 8477 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8478 base.head) {
47f1c6c9 8479
7758a113
DV		 8480 if (&encoder->new_crtc->base != crtc)
8481 continue;
7ae89233 8482
efea6e8e
DV		 8483 if (!(encoder->compute_config(encoder, pipe_config))) {
8484 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8485 goto fail;
8486 }
ee7b9f93 8487 }
47f1c6c9 8488
ff9a6750
DV		 8489 /* Set default port clock if not overwritten by the encoder. Needs to be
8490 * done afterwards in case the encoder adjusts the mode. */
8491 if (!pipe_config->port_clock)
3c52f4eb
VS		 8492 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8493 pipe_config->pixel_multiplier;
ff9a6750 8494
a43f6e0f 8495 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8496 if (ret < 0) {
7758a113
DV		 8497 DRM_DEBUG_KMS("CRTC fixup failed\n");
8498 goto fail;
ee7b9f93 8499 }
e29c22c0
DV		 8500
8501 if (ret == RETRY) {
8502 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8503 ret = -EINVAL;
8504 goto fail;
8505 }
8506
8507 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8508 retry = false;
8509 goto encoder_retry;
8510 }
8511
4e53c2e0
DV		 8512 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8513 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8514 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8515
b8cecdf5 8516 return pipe_config;
7758a113 8517fail:
b8cecdf5 8518 kfree(pipe_config);
e29c22c0 8519 return ERR_PTR(ret);
ee7b9f93 8520}
47f1c6c9 8521
e2e1ed41
DV		 8522/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8523 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8524static void
8525intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8526 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8527{
8528 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8529 struct drm_device *dev = crtc->dev;
8530 struct intel_encoder *encoder;
8531 struct intel_connector *connector;
8532 struct drm_crtc *tmp_crtc;
79e53945 8533
e2e1ed41 8534 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8535
e2e1ed41
DV		 8536 /* Check which crtcs have changed outputs connected to them, these need
8537 * to be part of the prepare_pipes mask. We don't (yet) support global
8538 * modeset across multiple crtcs, so modeset_pipes will only have one
8539 * bit set at most. */
8540 list_for_each_entry(connector, &dev->mode_config.connector_list,
8541 base.head) {
8542 if (connector->base.encoder == &connector->new_encoder->base)
8543 continue;
79e53945 8544
e2e1ed41
DV		 8545 if (connector->base.encoder) {
8546 tmp_crtc = connector->base.encoder->crtc;
8547
8548 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8549 }
8550
8551 if (connector->new_encoder)
8552 *prepare_pipes |=
8553 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8554 }
8555
e2e1ed41
DV		 8556 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8557 base.head) {
8558 if (encoder->base.crtc == &encoder->new_crtc->base)
8559 continue;
8560
8561 if (encoder->base.crtc) {
8562 tmp_crtc = encoder->base.crtc;
8563
8564 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8565 }
8566
8567 if (encoder->new_crtc)
8568 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8569 }
8570
e2e1ed41
DV		 8571 /* Check for any pipes that will be fully disabled ... */
8572 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8573 base.head) {
8574 bool used = false;
22fd0fab 8575
e2e1ed41
DV		 8576 /* Don't try to disable disabled crtcs. */
8577 if (!intel_crtc->base.enabled)
8578 continue;
7e7d76c3 8579
e2e1ed41
DV		 8580 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8581 base.head) {
8582 if (encoder->new_crtc == intel_crtc)
8583 used = true;
8584 }
8585
8586 if (!used)
8587 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8588 }
8589
e2e1ed41
DV		 8590
8591 /* set_mode is also used to update properties on life display pipes. */
8592 intel_crtc = to_intel_crtc(crtc);
8593 if (crtc->enabled)
8594 *prepare_pipes |= 1 << intel_crtc->pipe;
8595
b6c5164d
DV		 8596 /*
8597 * For simplicity do a full modeset on any pipe where the output routing
8598 * changed. We could be more clever, but that would require us to be
8599 * more careful with calling the relevant encoder->mode_set functions.
8600 */
e2e1ed41
DV		 8601 if (*prepare_pipes)
8602 *modeset_pipes = *prepare_pipes;
8603
8604 /* ... and mask these out. */
8605 *modeset_pipes &= ~(*disable_pipes);
8606 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8607
8608 /*
8609 * HACK: We don't (yet) fully support global modesets. intel_set_config
8610 * obies this rule, but the modeset restore mode of
8611 * intel_modeset_setup_hw_state does not.
8612 */
8613 *modeset_pipes &= 1 << intel_crtc->pipe;
8614 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8615
8616 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8617 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8618}
79e53945 8619
ea9d758d 8620static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8621{
ea9d758d 8622 struct drm_encoder *encoder;
f6e5b160 8623 struct drm_device *dev = crtc->dev;
f6e5b160 8624
ea9d758d
DV		 8625 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8626 if (encoder->crtc == crtc)
8627 return true;
8628
8629 return false;
8630}
8631
8632static void
8633intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8634{
8635 struct intel_encoder *intel_encoder;
8636 struct intel_crtc *intel_crtc;
8637 struct drm_connector *connector;
8638
8639 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8640 base.head) {
8641 if (!intel_encoder->base.crtc)
8642 continue;
8643
8644 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8645
8646 if (prepare_pipes & (1 << intel_crtc->pipe))
8647 intel_encoder->connectors_active = false;
8648 }
8649
8650 intel_modeset_commit_output_state(dev);
8651
8652 /* Update computed state. */
8653 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8654 base.head) {
8655 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8656 }
8657
8658 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8659 if (!connector->encoder || !connector->encoder->crtc)
8660 continue;
8661
8662 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8663
8664 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8665 struct drm_property *dpms_property =
8666 dev->mode_config.dpms_property;
8667
ea9d758d 8668 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8669 drm_object_property_set_value(&connector->base,
68d34720
DV		 8670 dpms_property,
8671 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8672
8673 intel_encoder = to_intel_encoder(connector->encoder);
8674 intel_encoder->connectors_active = true;
8675 }
8676 }
8677
8678}
8679
3bd26263 8680static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8681{
3bd26263 8682 int diff;
f1f644dc
JB		 8683
8684 if (clock1 == clock2)
8685 return true;
8686
8687 if (!clock1 || !clock2)
8688 return false;
8689
8690 diff = abs(clock1 - clock2);
8691
8692 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8693 return true;
8694
8695 return false;
8696}
8697
25c5b266
DV		 8698#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8699 list_for_each_entry((intel_crtc), \
8700 &(dev)->mode_config.crtc_list, \
8701 base.head) \
0973f18f 8702 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8703
0e8ffe1b 8704static bool
2fa2fe9a
DV		 8705intel_pipe_config_compare(struct drm_device *dev,
8706 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8707 struct intel_crtc_config *pipe_config)
8708{
66e985c0
DV		 8709#define PIPE_CONF_CHECK_X(name) \
8710 if (current_config->name != pipe_config->name) { \
8711 DRM_ERROR("mismatch in " #name " " \
8712 "(expected 0x%08x, found 0x%08x)\n", \
8713 current_config->name, \
8714 pipe_config->name); \
8715 return false; \
8716 }
8717
08a24034
DV		 8718#define PIPE_CONF_CHECK_I(name) \
8719 if (current_config->name != pipe_config->name) { \
8720 DRM_ERROR("mismatch in " #name " " \
8721 "(expected %i, found %i)\n", \
8722 current_config->name, \
8723 pipe_config->name); \
8724 return false; \
88adfff1
DV		 8725 }
8726
1bd1bd80
DV		 8727#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8728 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8729 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8730 "(expected %i, found %i)\n", \
8731 current_config->name & (mask), \
8732 pipe_config->name & (mask)); \
8733 return false; \
8734 }
8735
5e550656
VS		 8736#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8737 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8738 DRM_ERROR("mismatch in " #name " " \
8739 "(expected %i, found %i)\n", \
8740 current_config->name, \
8741 pipe_config->name); \
8742 return false; \
8743 }
8744
bb760063
DV		 8745#define PIPE_CONF_QUIRK(quirk) \
8746 ((current_config->quirks | pipe_config->quirks) & (quirk))
8747
eccb140b
DV		 8748 PIPE_CONF_CHECK_I(cpu_transcoder);
8749
08a24034
DV		 8750 PIPE_CONF_CHECK_I(has_pch_encoder);
8751 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8752 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8753 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8754 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8755 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8756 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8757
eb14cb74
VS		 8758 PIPE_CONF_CHECK_I(has_dp_encoder);
8759 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8760 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8761 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8762 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8763 PIPE_CONF_CHECK_I(dp_m_n.tu);
8764
1bd1bd80
DV		 8765 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8766 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8767 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8768 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8769 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8770 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8771
8772 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8773 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8774 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8775 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8776 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8777 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8778
c93f54cf 8779 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8780
1bd1bd80
DV		 8781 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8782 DRM_MODE_FLAG_INTERLACE);
8783
bb760063
DV		 8784 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8785 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8786 DRM_MODE_FLAG_PHSYNC);
8787 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8788 DRM_MODE_FLAG_NHSYNC);
8789 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8790 DRM_MODE_FLAG_PVSYNC);
8791 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8792 DRM_MODE_FLAG_NVSYNC);
8793 }
045ac3b5 8794
37327abd
VS		 8795 PIPE_CONF_CHECK_I(pipe_src_w);
8796 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8797
2fa2fe9a
DV		 8798 PIPE_CONF_CHECK_I(gmch_pfit.control);
8799 /* pfit ratios are autocomputed by the hw on gen4+ */
8800 if (INTEL_INFO(dev)->gen < 4)
8801 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8802 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8803 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8804 if (current_config->pch_pfit.enabled) {
8805 PIPE_CONF_CHECK_I(pch_pfit.pos);
8806 PIPE_CONF_CHECK_I(pch_pfit.size);
8807 }
2fa2fe9a 8808
42db64ef
PZ		 8809 PIPE_CONF_CHECK_I(ips_enabled);
8810
282740f7
VS		 8811 PIPE_CONF_CHECK_I(double_wide);
8812
c0d43d62 8813 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8814 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8815 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8816 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8817 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8818
42571aef
VS		 8819 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8820 PIPE_CONF_CHECK_I(pipe_bpp);
8821
d71b8d4a 8822 if (!IS_HASWELL(dev)) {
5e550656 8823 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
d71b8d4a
VS		 8824 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8825 }
5e550656 8826
66e985c0 8827#undef PIPE_CONF_CHECK_X
08a24034 8828#undef PIPE_CONF_CHECK_I
1bd1bd80 8829#undef PIPE_CONF_CHECK_FLAGS
5e550656 8830#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8831#undef PIPE_CONF_QUIRK
88adfff1 8832
0e8ffe1b
DV		 8833 return true;
8834}
8835
91d1b4bd
DV		 8836static void
8837check_connector_state(struct drm_device *dev)
8af6cf88 8838{
8af6cf88
DV		 8839 struct intel_connector *connector;
8840
8841 list_for_each_entry(connector, &dev->mode_config.connector_list,
8842 base.head) {
8843 /* This also checks the encoder/connector hw state with the
8844 * ->get_hw_state callbacks. */
8845 intel_connector_check_state(connector);
8846
8847 WARN(&connector->new_encoder->base != connector->base.encoder,
8848 "connector's staged encoder doesn't match current encoder\n");
8849 }
91d1b4bd
DV		 8850}
8851
8852static void
8853check_encoder_state(struct drm_device *dev)
8854{
8855 struct intel_encoder *encoder;
8856 struct intel_connector *connector;
8af6cf88
DV		 8857
8858 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8859 base.head) {
8860 bool enabled = false;
8861 bool active = false;
8862 enum pipe pipe, tracked_pipe;
8863
8864 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8865 encoder->base.base.id,
8866 drm_get_encoder_name(&encoder->base));
8867
8868 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8869 "encoder's stage crtc doesn't match current crtc\n");
8870 WARN(encoder->connectors_active && !encoder->base.crtc,
8871 "encoder's active_connectors set, but no crtc\n");
8872
8873 list_for_each_entry(connector, &dev->mode_config.connector_list,
8874 base.head) {
8875 if (connector->base.encoder != &encoder->base)
8876 continue;
8877 enabled = true;
8878 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8879 active = true;
8880 }
8881 WARN(!!encoder->base.crtc != enabled,
8882 "encoder's enabled state mismatch "
8883 "(expected %i, found %i)\n",
8884 !!encoder->base.crtc, enabled);
8885 WARN(active && !encoder->base.crtc,
8886 "active encoder with no crtc\n");
8887
8888 WARN(encoder->connectors_active != active,
8889 "encoder's computed active state doesn't match tracked active state "
8890 "(expected %i, found %i)\n", active, encoder->connectors_active);
8891
8892 active = encoder->get_hw_state(encoder, &pipe);
8893 WARN(active != encoder->connectors_active,
8894 "encoder's hw state doesn't match sw tracking "
8895 "(expected %i, found %i)\n",
8896 encoder->connectors_active, active);
8897
8898 if (!encoder->base.crtc)
8899 continue;
8900
8901 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8902 WARN(active && pipe != tracked_pipe,
8903 "active encoder's pipe doesn't match"
8904 "(expected %i, found %i)\n",
8905 tracked_pipe, pipe);
8906
8907 }
91d1b4bd
DV		 8908}
8909
8910static void
8911check_crtc_state(struct drm_device *dev)
8912{
8913 drm_i915_private_t *dev_priv = dev->dev_private;
8914 struct intel_crtc *crtc;
8915 struct intel_encoder *encoder;
8916 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8917
8918 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8919 base.head) {
8920 bool enabled = false;
8921 bool active = false;
8922
045ac3b5
JB		 8923 memset(&pipe_config, 0, sizeof(pipe_config));
8924
8af6cf88
DV		 8925 DRM_DEBUG_KMS("[CRTC:%d]\n",
8926 crtc->base.base.id);
8927
8928 WARN(crtc->active && !crtc->base.enabled,
8929 "active crtc, but not enabled in sw tracking\n");
8930
8931 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8932 base.head) {
8933 if (encoder->base.crtc != &crtc->base)
8934 continue;
8935 enabled = true;
8936 if (encoder->connectors_active)
8937 active = true;
8938 }
6c49f241 8939
8af6cf88
DV		 8940 WARN(active != crtc->active,
8941 "crtc's computed active state doesn't match tracked active state "
8942 "(expected %i, found %i)\n", active, crtc->active);
8943 WARN(enabled != crtc->base.enabled,
8944 "crtc's computed enabled state doesn't match tracked enabled state "
8945 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8946
0e8ffe1b
DV		 8947 active = dev_priv->display.get_pipe_config(crtc,
8948 &pipe_config);
d62cf62a
DV		 8949
8950 /* hw state is inconsistent with the pipe A quirk */
8951 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8952 active = crtc->active;
8953
6c49f241
DV		 8954 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8955 base.head) {
3eaba51c 8956 enum pipe pipe;
6c49f241
DV		 8957 if (encoder->base.crtc != &crtc->base)
8958 continue;
3eaba51c
VS		 8959 if (encoder->get_config &&
8960 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8961 encoder->get_config(encoder, &pipe_config);
8962 }
8963
0e8ffe1b
DV		 8964 WARN(crtc->active != active,
8965 "crtc active state doesn't match with hw state "
8966 "(expected %i, found %i)\n", crtc->active, active);
8967
c0b03411
DV		 8968 if (active &&
8969 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8970 WARN(1, "pipe state doesn't match!\n");
8971 intel_dump_pipe_config(crtc, &pipe_config,
8972 "[hw state]");
8973 intel_dump_pipe_config(crtc, &crtc->config,
8974 "[sw state]");
8975 }
8af6cf88
DV		 8976 }
8977}
8978
91d1b4bd
DV		 8979static void
8980check_shared_dpll_state(struct drm_device *dev)
8981{
8982 drm_i915_private_t *dev_priv = dev->dev_private;
8983 struct intel_crtc *crtc;
8984 struct intel_dpll_hw_state dpll_hw_state;
8985 int i;
5358901f
DV		 8986
8987 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8988 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8989 int enabled_crtcs = 0, active_crtcs = 0;
8990 bool active;
8991
8992 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8993
8994 DRM_DEBUG_KMS("%s\n", pll->name);
8995
8996 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8997
8998 WARN(pll->active > pll->refcount,
8999 "more active pll users than references: %i vs %i\n",
9000 pll->active, pll->refcount);
9001 WARN(pll->active && !pll->on,
9002 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9003 WARN(pll->on && !pll->active,
9004 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9005 WARN(pll->on != active,
9006 "pll on state mismatch (expected %i, found %i)\n",
9007 pll->on, active);
9008
9009 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9010 base.head) {
9011 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9012 enabled_crtcs++;
9013 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9014 active_crtcs++;
9015 }
9016 WARN(pll->active != active_crtcs,
9017 "pll active crtcs mismatch (expected %i, found %i)\n",
9018 pll->active, active_crtcs);
9019 WARN(pll->refcount != enabled_crtcs,
9020 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9021 pll->refcount, enabled_crtcs);
66e985c0
DV		 9022
9023 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9024 sizeof(dpll_hw_state)),
9025 "pll hw state mismatch\n");
5358901f 9026 }
8af6cf88
DV		 9027}
9028
91d1b4bd
DV		 9029void
9030intel_modeset_check_state(struct drm_device *dev)
9031{
9032 check_connector_state(dev);
9033 check_encoder_state(dev);
9034 check_crtc_state(dev);
9035 check_shared_dpll_state(dev);
9036}
9037
18442d08
VS		 9038void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9039 int dotclock)
9040{
9041 /*
9042 * FDI already provided one idea for the dotclock.
9043 * Yell if the encoder disagrees.
9044 */
9045 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
9046 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9047 pipe_config->adjusted_mode.clock, dotclock);
9048}
9049
f30da187
DV		 9050static int __intel_set_mode(struct drm_crtc *crtc,
9051 struct drm_display_mode *mode,
9052 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9053{
9054 struct drm_device *dev = crtc->dev;
dbf2b54e 9055 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9056 struct drm_display_mode *saved_mode, *saved_hwmode;
9057 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9058 struct intel_crtc *intel_crtc;
9059 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9060 int ret = 0;
a6778b3c 9061
a1e22653 9062 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9063 if (!saved_mode)
9064 return -ENOMEM;
3ac18232 9065 saved_hwmode = saved_mode + 1;
a6778b3c 9066
e2e1ed41 9067 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9068 &prepare_pipes, &disable_pipes);
9069
3ac18232
TG		 9070 *saved_hwmode = crtc->hwmode;
9071 *saved_mode = crtc->mode;
a6778b3c 9072
25c5b266
DV		 9073 /* Hack: Because we don't (yet) support global modeset on multiple
9074 * crtcs, we don't keep track of the new mode for more than one crtc.
9075 * Hence simply check whether any bit is set in modeset_pipes in all the
9076 * pieces of code that are not yet converted to deal with mutliple crtcs
9077 * changing their mode at the same time. */
25c5b266 9078 if (modeset_pipes) {
4e53c2e0 9079 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9080 if (IS_ERR(pipe_config)) {
9081 ret = PTR_ERR(pipe_config);
9082 pipe_config = NULL;
9083
3ac18232 9084 goto out;
25c5b266 9085 }
c0b03411
DV		 9086 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9087 "[modeset]");
25c5b266 9088 }
a6778b3c 9089
460da916
DV		 9090 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9091 intel_crtc_disable(&intel_crtc->base);
9092
ea9d758d
DV		 9093 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9094 if (intel_crtc->base.enabled)
9095 dev_priv->display.crtc_disable(&intel_crtc->base);
9096 }
a6778b3c 9097
6c4c86f5
DV		 9098 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9099 * to set it here already despite that we pass it down the callchain.
f6e5b160 9100 */
b8cecdf5 9101 if (modeset_pipes) {
25c5b266 9102 crtc->mode = *mode;
b8cecdf5
DV		 9103 /* mode_set/enable/disable functions rely on a correct pipe
9104 * config. */
9105 to_intel_crtc(crtc)->config = *pipe_config;
9106 }
7758a113 9107
ea9d758d
DV		 9108 /* Only after disabling all output pipelines that will be changed can we
9109 * update the the output configuration. */
9110 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9111
47fab737
DV		 9112 if (dev_priv->display.modeset_global_resources)
9113 dev_priv->display.modeset_global_resources(dev);
9114
a6778b3c
DV		 9115 /* Set up the DPLL and any encoders state that needs to adjust or depend
9116 * on the DPLL.
f6e5b160 9117 */
25c5b266 9118 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9119 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9120 x, y, fb);
9121 if (ret)
9122 goto done;
a6778b3c
DV		 9123 }
9124
9125 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9126 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9127 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9128
25c5b266
DV		 9129 if (modeset_pipes) {
9130 /* Store real post-adjustment hardware mode. */
b8cecdf5 9131 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9132
25c5b266
DV		 9133 /* Calculate and store various constants which
9134 * are later needed by vblank and swap-completion
9135 * timestamping. They are derived from true hwmode.
9136 */
9137 drm_calc_timestamping_constants(crtc);
9138 }
a6778b3c
DV		 9139
9140 /* FIXME: add subpixel order */
9141done:
c0c36b94 9142 if (ret && crtc->enabled) {
3ac18232
TG		 9143 crtc->hwmode = *saved_hwmode;
9144 crtc->mode = *saved_mode;
a6778b3c
DV		 9145 }
9146
3ac18232 9147out:
b8cecdf5 9148 kfree(pipe_config);
3ac18232 9149 kfree(saved_mode);
a6778b3c 9150 return ret;
f6e5b160
CW		 9151}
9152
e7457a9a
DL		 9153static int intel_set_mode(struct drm_crtc *crtc,
9154 struct drm_display_mode *mode,
9155 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9156{
9157 int ret;
9158
9159 ret = __intel_set_mode(crtc, mode, x, y, fb);
9160
9161 if (ret == 0)
9162 intel_modeset_check_state(crtc->dev);
9163
9164 return ret;
9165}
9166
c0c36b94
CW		 9167void intel_crtc_restore_mode(struct drm_crtc *crtc)
9168{
9169 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9170}
9171
25c5b266
DV		 9172#undef for_each_intel_crtc_masked
9173
d9e55608
DV		 9174static void intel_set_config_free(struct intel_set_config *config)
9175{
9176 if (!config)
9177 return;
9178
1aa4b628
DV		 9179 kfree(config->save_connector_encoders);
9180 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9181 kfree(config);
9182}
9183
85f9eb71
DV		 9184static int intel_set_config_save_state(struct drm_device *dev,
9185 struct intel_set_config *config)
9186{
85f9eb71
DV		 9187 struct drm_encoder *encoder;
9188 struct drm_connector *connector;
9189 int count;
9190
1aa4b628
DV		 9191 config->save_encoder_crtcs =
9192 kcalloc(dev->mode_config.num_encoder,
9193 sizeof(struct drm_crtc *), GFP_KERNEL);
9194 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9195 return -ENOMEM;
9196
1aa4b628
DV		 9197 config->save_connector_encoders =
9198 kcalloc(dev->mode_config.num_connector,
9199 sizeof(struct drm_encoder *), GFP_KERNEL);
9200 if (!config->save_connector_encoders)
85f9eb71
DV		 9201 return -ENOMEM;
9202
9203 /* Copy data. Note that driver private data is not affected.
9204 * Should anything bad happen only the expected state is
9205 * restored, not the drivers personal bookkeeping.
9206 */
85f9eb71
DV		 9207 count = 0;
9208 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9209 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9210 }
9211
9212 count = 0;
9213 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9214 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9215 }
9216
9217 return 0;
9218}
9219
9220static void intel_set_config_restore_state(struct drm_device *dev,
9221 struct intel_set_config *config)
9222{
9a935856
DV		 9223 struct intel_encoder *encoder;
9224 struct intel_connector *connector;
85f9eb71
DV		 9225 int count;
9226
85f9eb71 9227 count = 0;
9a935856
DV		 9228 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9229 encoder->new_crtc =
9230 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9231 }
9232
9233 count = 0;
9a935856
DV		 9234 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9235 connector->new_encoder =
9236 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9237 }
9238}
9239
e3de42b6 9240static bool
2e57f47d 9241is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9242{
9243 int i;
9244
2e57f47d
CW		 9245 if (set->num_connectors == 0)
9246 return false;
9247
9248 if (WARN_ON(set->connectors == NULL))
9249 return false;
9250
9251 for (i = 0; i < set->num_connectors; i++)
9252 if (set->connectors[i]->encoder &&
9253 set->connectors[i]->encoder->crtc == set->crtc &&
9254 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9255 return true;
9256
9257 return false;
9258}
9259
5e2b584e
DV		 9260static void
9261intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9262 struct intel_set_config *config)
9263{
9264
9265 /* We should be able to check here if the fb has the same properties
9266 * and then just flip_or_move it */
2e57f47d
CW		 9267 if (is_crtc_connector_off(set)) {
9268 config->mode_changed = true;
e3de42b6 9269 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9270 /* If we have no fb then treat it as a full mode set */
9271 if (set->crtc->fb == NULL) {
319d9827
JB		 9272 struct intel_crtc *intel_crtc =
9273 to_intel_crtc(set->crtc);
9274
9275 if (intel_crtc->active && i915_fastboot) {
9276 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9277 config->fb_changed = true;
9278 } else {
9279 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9280 config->mode_changed = true;
9281 }
5e2b584e
DV		 9282 } else if (set->fb == NULL) {
9283 config->mode_changed = true;
72f4901e
DV		 9284 } else if (set->fb->pixel_format !=
9285 set->crtc->fb->pixel_format) {
5e2b584e 9286 config->mode_changed = true;
e3de42b6 9287 } else {
5e2b584e 9288 config->fb_changed = true;
e3de42b6 9289 }
5e2b584e
DV		 9290 }
9291
835c5873 9292 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9293 config->fb_changed = true;
9294
9295 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9296 DRM_DEBUG_KMS("modes are different, full mode set\n");
9297 drm_mode_debug_printmodeline(&set->crtc->mode);
9298 drm_mode_debug_printmodeline(set->mode);
9299 config->mode_changed = true;
9300 }
a1d95703
CW		 9301
9302 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9303 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9304}
9305
2e431051 9306static int
9a935856
DV		 9307intel_modeset_stage_output_state(struct drm_device *dev,
9308 struct drm_mode_set *set,
9309 struct intel_set_config *config)
50f56119 9310{
85f9eb71 9311 struct drm_crtc *new_crtc;
9a935856
DV		 9312 struct intel_connector *connector;
9313 struct intel_encoder *encoder;
f3f08572 9314 int ro;
50f56119 9315
9abdda74 9316 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9317 * of connectors. For paranoia, double-check this. */
9318 WARN_ON(!set->fb && (set->num_connectors != 0));
9319 WARN_ON(set->fb && (set->num_connectors == 0));
9320
9a935856
DV		 9321 list_for_each_entry(connector, &dev->mode_config.connector_list,
9322 base.head) {
9323 /* Otherwise traverse passed in connector list and get encoders
9324 * for them. */
50f56119 9325 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9326 if (set->connectors[ro] == &connector->base) {
9327 connector->new_encoder = connector->encoder;
50f56119
DV		 9328 break;
9329 }
9330 }
9331
9a935856
DV		 9332 /* If we disable the crtc, disable all its connectors. Also, if
9333 * the connector is on the changing crtc but not on the new
9334 * connector list, disable it. */
9335 if ((!set->fb || ro == set->num_connectors) &&
9336 connector->base.encoder &&
9337 connector->base.encoder->crtc == set->crtc) {
9338 connector->new_encoder = NULL;
9339
9340 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9341 connector->base.base.id,
9342 drm_get_connector_name(&connector->base));
9343 }
9344
9345
9346 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9347 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9348 config->mode_changed = true;
50f56119
DV		 9349 }
9350 }
9a935856 9351 /* connector->new_encoder is now updated for all connectors. */
50f56119 9352
9a935856 9353 /* Update crtc of enabled connectors. */
9a935856
DV		 9354 list_for_each_entry(connector, &dev->mode_config.connector_list,
9355 base.head) {
9356 if (!connector->new_encoder)
50f56119
DV		 9357 continue;
9358
9a935856 9359 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9360
9361 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9362 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9363 new_crtc = set->crtc;
9364 }
9365
9366 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9367 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9368 new_crtc)) {
5e2b584e 9369 return -EINVAL;
50f56119 9370 }
9a935856
DV		 9371 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9372
9373 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9374 connector->base.base.id,
9375 drm_get_connector_name(&connector->base),
9376 new_crtc->base.id);
9377 }
9378
9379 /* Check for any encoders that needs to be disabled. */
9380 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9381 base.head) {
9382 list_for_each_entry(connector,
9383 &dev->mode_config.connector_list,
9384 base.head) {
9385 if (connector->new_encoder == encoder) {
9386 WARN_ON(!connector->new_encoder->new_crtc);
9387
9388 goto next_encoder;
9389 }
9390 }
9391 encoder->new_crtc = NULL;
9392next_encoder:
9393 /* Only now check for crtc changes so we don't miss encoders
9394 * that will be disabled. */
9395 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9396 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9397 config->mode_changed = true;
50f56119
DV		 9398 }
9399 }
9a935856 9400 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9401
2e431051
DV		 9402 return 0;
9403}
9404
9405static int intel_crtc_set_config(struct drm_mode_set *set)
9406{
9407 struct drm_device *dev;
2e431051
DV		 9408 struct drm_mode_set save_set;
9409 struct intel_set_config *config;
9410 int ret;
2e431051 9411
8d3e375e
DV		 9412 BUG_ON(!set);
9413 BUG_ON(!set->crtc);
9414 BUG_ON(!set->crtc->helper_private);
2e431051 9415
7e53f3a4
DV		 9416 /* Enforce sane interface api - has been abused by the fb helper. */
9417 BUG_ON(!set->mode && set->fb);
9418 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9419
2e431051
DV		 9420 if (set->fb) {
9421 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9422 set->crtc->base.id, set->fb->base.id,
9423 (int)set->num_connectors, set->x, set->y);
9424 } else {
9425 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9426 }
9427
9428 dev = set->crtc->dev;
9429
9430 ret = -ENOMEM;
9431 config = kzalloc(sizeof(*config), GFP_KERNEL);
9432 if (!config)
9433 goto out_config;
9434
9435 ret = intel_set_config_save_state(dev, config);
9436 if (ret)
9437 goto out_config;
9438
9439 save_set.crtc = set->crtc;
9440 save_set.mode = &set->crtc->mode;
9441 save_set.x = set->crtc->x;
9442 save_set.y = set->crtc->y;
9443 save_set.fb = set->crtc->fb;
9444
9445 /* Compute whether we need a full modeset, only an fb base update or no
9446 * change at all. In the future we might also check whether only the
9447 * mode changed, e.g. for LVDS where we only change the panel fitter in
9448 * such cases. */
9449 intel_set_config_compute_mode_changes(set, config);
9450
9a935856 9451 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9452 if (ret)
9453 goto fail;
9454
5e2b584e 9455 if (config->mode_changed) {
c0c36b94
CW		 9456 ret = intel_set_mode(set->crtc, set->mode,
9457 set->x, set->y, set->fb);
5e2b584e 9458 } else if (config->fb_changed) {
4878cae2
VS		 9459 intel_crtc_wait_for_pending_flips(set->crtc);
9460
4f660f49 9461 ret = intel_pipe_set_base(set->crtc,
94352cf9 9462 set->x, set->y, set->fb);
50f56119
DV		 9463 }
9464
2d05eae1 9465 if (ret) {
bf67dfeb
DV		 9466 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9467 set->crtc->base.id, ret);
50f56119 9468fail:
2d05eae1 9469 intel_set_config_restore_state(dev, config);
50f56119 9470
2d05eae1
CW		 9471 /* Try to restore the config */
9472 if (config->mode_changed &&
9473 intel_set_mode(save_set.crtc, save_set.mode,
9474 save_set.x, save_set.y, save_set.fb))
9475 DRM_ERROR("failed to restore config after modeset failure\n");
9476 }
50f56119 9477
d9e55608
DV		 9478out_config:
9479 intel_set_config_free(config);
50f56119
DV		 9480 return ret;
9481}
f6e5b160
CW		 9482
9483static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9484 .cursor_set = intel_crtc_cursor_set,
9485 .cursor_move = intel_crtc_cursor_move,
9486 .gamma_set = intel_crtc_gamma_set,
50f56119 9487 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9488 .destroy = intel_crtc_destroy,
9489 .page_flip = intel_crtc_page_flip,
9490};
9491
79f689aa
PZ		 9492static void intel_cpu_pll_init(struct drm_device *dev)
9493{
affa9354 9494 if (HAS_DDI(dev))
79f689aa
PZ		 9495 intel_ddi_pll_init(dev);
9496}
9497
5358901f
DV		 9498static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9499 struct intel_shared_dpll *pll,
9500 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9501{
5358901f 9502 uint32_t val;
ee7b9f93 9503
5358901f 9504 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9505 hw_state->dpll = val;
9506 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9507 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9508
9509 return val & DPLL_VCO_ENABLE;
9510}
9511
15bdd4cf
DV		 9512static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9513 struct intel_shared_dpll *pll)
9514{
9515 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9516 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9517}
9518
e7b903d2
DV		 9519static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9520 struct intel_shared_dpll *pll)
9521{
e7b903d2
DV		 9522 /* PCH refclock must be enabled first */
9523 assert_pch_refclk_enabled(dev_priv);
9524
15bdd4cf
DV		 9525 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9526
9527 /* Wait for the clocks to stabilize. */
9528 POSTING_READ(PCH_DPLL(pll->id));
9529 udelay(150);
9530
9531 /* The pixel multiplier can only be updated once the
9532 * DPLL is enabled and the clocks are stable.
9533 *
9534 * So write it again.
9535 */
9536 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9537 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9538 udelay(200);
9539}
9540
9541static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9542 struct intel_shared_dpll *pll)
9543{
9544 struct drm_device *dev = dev_priv->dev;
9545 struct intel_crtc *crtc;
e7b903d2
DV		 9546
9547 /* Make sure no transcoder isn't still depending on us. */
9548 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9549 if (intel_crtc_to_shared_dpll(crtc) == pll)
9550 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9551 }
9552
15bdd4cf
DV		 9553 I915_WRITE(PCH_DPLL(pll->id), 0);
9554 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9555 udelay(200);
9556}
9557
46edb027
DV		 9558static char *ibx_pch_dpll_names[] = {
9559 "PCH DPLL A",
9560 "PCH DPLL B",
9561};
9562
7c74ade1 9563static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9564{
e7b903d2 9565 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9566 int i;
9567
7c74ade1 9568 dev_priv->num_shared_dpll = 2;
ee7b9f93 9569
e72f9fbf 9570 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9571 dev_priv->shared_dplls[i].id = i;
9572 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9573 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9574 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9575 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9576 dev_priv->shared_dplls[i].get_hw_state =
9577 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9578 }
9579}
9580
7c74ade1
DV		 9581static void intel_shared_dpll_init(struct drm_device *dev)
9582{
e7b903d2 9583 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9584
9585 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9586 ibx_pch_dpll_init(dev);
9587 else
9588 dev_priv->num_shared_dpll = 0;
9589
9590 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9591 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9592 dev_priv->num_shared_dpll);
9593}
9594
b358d0a6 9595static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9596{
22fd0fab 9597 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9598 struct intel_crtc *intel_crtc;
9599 int i;
9600
955382f3 9601 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9602 if (intel_crtc == NULL)
9603 return;
9604
9605 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9606
9607 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9608 for (i = 0; i < 256; i++) {
9609 intel_crtc->lut_r[i] = i;
9610 intel_crtc->lut_g[i] = i;
9611 intel_crtc->lut_b[i] = i;
9612 }
9613
80824003
JB		 9614 /* Swap pipes & planes for FBC on pre-965 */
9615 intel_crtc->pipe = pipe;
9616 intel_crtc->plane = pipe;
e2e767ab 9617 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9618 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9619 intel_crtc->plane = !pipe;
80824003
JB		 9620 }
9621
22fd0fab
JB		 9622 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9623 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9624 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9625 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9626
79e53945 9627 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9628}
9629
08d7b3d1 9630int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9631 struct drm_file *file)
08d7b3d1 9632{
08d7b3d1 9633 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9634 struct drm_mode_object *drmmode_obj;
9635 struct intel_crtc *crtc;
08d7b3d1 9636
1cff8f6b
DV		 9637 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9638 return -ENODEV;
08d7b3d1 9639
c05422d5
DV		 9640 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9641 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9642
c05422d5 9643 if (!drmmode_obj) {
08d7b3d1
CW		 9644 DRM_ERROR("no such CRTC id\n");
9645 return -EINVAL;
9646 }
9647
c05422d5
DV		 9648 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9649 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9650
c05422d5 9651 return 0;
08d7b3d1
CW		 9652}
9653
66a9278e 9654static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9655{
66a9278e
DV		 9656 struct drm_device *dev = encoder->base.dev;
9657 struct intel_encoder *source_encoder;
79e53945 9658 int index_mask = 0;
79e53945
JB		 9659 int entry = 0;
9660
66a9278e
DV		 9661 list_for_each_entry(source_encoder,
9662 &dev->mode_config.encoder_list, base.head) {
9663
9664 if (encoder == source_encoder)
79e53945 9665 index_mask |= (1 << entry);
66a9278e
DV		 9666
9667 /* Intel hw has only one MUX where enocoders could be cloned. */
9668 if (encoder->cloneable && source_encoder->cloneable)
9669 index_mask |= (1 << entry);
9670
79e53945
JB		 9671 entry++;
9672 }
4ef69c7a 9673
79e53945
JB		 9674 return index_mask;
9675}
9676
4d302442
CW		 9677static bool has_edp_a(struct drm_device *dev)
9678{
9679 struct drm_i915_private *dev_priv = dev->dev_private;
9680
9681 if (!IS_MOBILE(dev))
9682 return false;
9683
9684 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9685 return false;
9686
9687 if (IS_GEN5(dev) &&
9688 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9689 return false;
9690
9691 return true;
9692}
9693
79e53945
JB		 9694static void intel_setup_outputs(struct drm_device *dev)
9695{
725e30ad 9696 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9697 struct intel_encoder *encoder;
cb0953d7 9698 bool dpd_is_edp = false;
79e53945 9699
c9093354 9700 intel_lvds_init(dev);
79e53945 9701
c40c0f5b 9702 if (!IS_ULT(dev))
79935fca 9703 intel_crt_init(dev);
cb0953d7 9704
affa9354 9705 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9706 int found;
9707
9708 /* Haswell uses DDI functions to detect digital outputs */
9709 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9710 /* DDI A only supports eDP */
9711 if (found)
9712 intel_ddi_init(dev, PORT_A);
9713
9714 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9715 * register */
9716 found = I915_READ(SFUSE_STRAP);
9717
9718 if (found & SFUSE_STRAP_DDIB_DETECTED)
9719 intel_ddi_init(dev, PORT_B);
9720 if (found & SFUSE_STRAP_DDIC_DETECTED)
9721 intel_ddi_init(dev, PORT_C);
9722 if (found & SFUSE_STRAP_DDID_DETECTED)
9723 intel_ddi_init(dev, PORT_D);
9724 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9725 int found;
270b3042
DV		 9726 dpd_is_edp = intel_dpd_is_edp(dev);
9727
9728 if (has_edp_a(dev))
9729 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9730
dc0fa718 9731 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9732 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9733 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9734 if (!found)
e2debe91 9735 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9736 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9737 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9738 }
9739
dc0fa718 9740 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9741 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9742
dc0fa718 9743 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9744 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9745
5eb08b69 9746 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9747 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9748
270b3042 9749 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9750 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9751 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9752 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9753 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9754 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9755 PORT_C);
9756 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9757 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9758 PORT_C);
9759 }
19c03924 9760
dc0fa718 9761 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9762 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9763 PORT_B);
67cfc203
VS		 9764 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9765 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9766 }
3cfca973
JN		 9767
9768 intel_dsi_init(dev);
103a196f 9769 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9770 bool found = false;
7d57382e 9771
e2debe91 9772 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9773 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9774 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9775 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9776 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9777 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9778 }
27185ae1 9779
e7281eab 9780 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9781 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9782 }
13520b05
KH		 9783
9784 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9785
e2debe91 9786 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9787 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9788 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9789 }
27185ae1 9790
e2debe91 9791 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9792
b01f2c3a
JB		 9793 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9794 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9795 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9796 }
e7281eab 9797 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9798 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9799 }
27185ae1 9800
b01f2c3a 9801 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9802 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9803 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9804 } else if (IS_GEN2(dev))
79e53945
JB		 9805 intel_dvo_init(dev);
9806
103a196f 9807 if (SUPPORTS_TV(dev))
79e53945
JB		 9808 intel_tv_init(dev);
9809
4ef69c7a
CW		 9810 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9811 encoder->base.possible_crtcs = encoder->crtc_mask;
9812 encoder->base.possible_clones =
66a9278e 9813 intel_encoder_clones(encoder);
79e53945 9814 }
47356eb6 9815
dde86e2d 9816 intel_init_pch_refclk(dev);
270b3042
DV		 9817
9818 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9819}
9820
ddfe1567
CW		 9821void intel_framebuffer_fini(struct intel_framebuffer *fb)
9822{
9823 drm_framebuffer_cleanup(&fb->base);
9824 drm_gem_object_unreference_unlocked(&fb->obj->base);
9825}
9826
79e53945
JB		 9827static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9828{
9829 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9830
ddfe1567 9831 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9832 kfree(intel_fb);
9833}
9834
9835static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9836 struct drm_file *file,
79e53945
JB		 9837 unsigned int *handle)
9838{
9839 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9840 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9841
05394f39 9842 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9843}
9844
9845static const struct drm_framebuffer_funcs intel_fb_funcs = {
9846 .destroy = intel_user_framebuffer_destroy,
9847 .create_handle = intel_user_framebuffer_create_handle,
9848};
9849
38651674
DA		 9850int intel_framebuffer_init(struct drm_device *dev,
9851 struct intel_framebuffer *intel_fb,
308e5bcb 9852 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9853 struct drm_i915_gem_object *obj)
79e53945 9854{
a35cdaa0 9855 int pitch_limit;
79e53945
JB		 9856 int ret;
9857
c16ed4be
CW		 9858 if (obj->tiling_mode == I915_TILING_Y) {
9859 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9860 return -EINVAL;
c16ed4be 9861 }
57cd6508 9862
c16ed4be
CW		 9863 if (mode_cmd->pitches[0] & 63) {
9864 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9865 mode_cmd->pitches[0]);
57cd6508 9866 return -EINVAL;
c16ed4be 9867 }
57cd6508 9868
a35cdaa0
CW		 9869 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9870 pitch_limit = 32*1024;
9871 } else if (INTEL_INFO(dev)->gen >= 4) {
9872 if (obj->tiling_mode)
9873 pitch_limit = 16*1024;
9874 else
9875 pitch_limit = 32*1024;
9876 } else if (INTEL_INFO(dev)->gen >= 3) {
9877 if (obj->tiling_mode)
9878 pitch_limit = 8*1024;
9879 else
9880 pitch_limit = 16*1024;
9881 } else
9882 /* XXX DSPC is limited to 4k tiled */
9883 pitch_limit = 8*1024;
9884
9885 if (mode_cmd->pitches[0] > pitch_limit) {
9886 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9887 obj->tiling_mode ? "tiled" : "linear",
9888 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9889 return -EINVAL;
c16ed4be 9890 }
5d7bd705
VS		 9891
9892 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9893 mode_cmd->pitches[0] != obj->stride) {
9894 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9895 mode_cmd->pitches[0], obj->stride);
5d7bd705 9896 return -EINVAL;
c16ed4be 9897 }
5d7bd705 9898
57779d06 9899 /* Reject formats not supported by any plane early. */
308e5bcb 9900 switch (mode_cmd->pixel_format) {
57779d06 9901 case DRM_FORMAT_C8:
04b3924d
VS		 9902 case DRM_FORMAT_RGB565:
9903 case DRM_FORMAT_XRGB8888:
9904 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9905 break;
9906 case DRM_FORMAT_XRGB1555:
9907 case DRM_FORMAT_ARGB1555:
c16ed4be 9908 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9909 DRM_DEBUG("unsupported pixel format: %s\n",
9910 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9911 return -EINVAL;
c16ed4be 9912 }
57779d06
VS		 9913 break;
9914 case DRM_FORMAT_XBGR8888:
9915 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9916 case DRM_FORMAT_XRGB2101010:
9917 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9918 case DRM_FORMAT_XBGR2101010:
9919 case DRM_FORMAT_ABGR2101010:
c16ed4be 9920 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9921 DRM_DEBUG("unsupported pixel format: %s\n",
9922 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9923 return -EINVAL;
c16ed4be 9924 }
b5626747 9925 break;
04b3924d
VS		 9926 case DRM_FORMAT_YUYV:
9927 case DRM_FORMAT_UYVY:
9928 case DRM_FORMAT_YVYU:
9929 case DRM_FORMAT_VYUY:
c16ed4be 9930 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9931 DRM_DEBUG("unsupported pixel format: %s\n",
9932 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9933 return -EINVAL;
c16ed4be 9934 }
57cd6508
CW		 9935 break;
9936 default:
4ee62c76
VS		 9937 DRM_DEBUG("unsupported pixel format: %s\n",
9938 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9939 return -EINVAL;
9940 }
9941
90f9a336
VS		 9942 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9943 if (mode_cmd->offsets[0] != 0)
9944 return -EINVAL;
9945
c7d73f6a
DV		 9946 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9947 intel_fb->obj = obj;
9948
79e53945
JB		 9949 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9950 if (ret) {
9951 DRM_ERROR("framebuffer init failed %d\n", ret);
9952 return ret;
9953 }
9954
79e53945
JB		 9955 return 0;
9956}
9957
79e53945
JB		 9958static struct drm_framebuffer *
9959intel_user_framebuffer_create(struct drm_device *dev,
9960 struct drm_file *filp,
308e5bcb 9961 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9962{
05394f39 9963 struct drm_i915_gem_object *obj;
79e53945 9964
308e5bcb
JB		 9965 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9966 mode_cmd->handles[0]));
c8725226 9967 if (&obj->base == NULL)
cce13ff7 9968 return ERR_PTR(-ENOENT);
79e53945 9969
d2dff872 9970 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9971}
9972
79e53945 9973static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9974 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9975 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9976};
9977
e70236a8
JB		 9978/* Set up chip specific display functions */
9979static void intel_init_display(struct drm_device *dev)
9980{
9981 struct drm_i915_private *dev_priv = dev->dev_private;
9982
ee9300bb
DV		 9983 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9984 dev_priv->display.find_dpll = g4x_find_best_dpll;
9985 else if (IS_VALLEYVIEW(dev))
9986 dev_priv->display.find_dpll = vlv_find_best_dpll;
9987 else if (IS_PINEVIEW(dev))
9988 dev_priv->display.find_dpll = pnv_find_best_dpll;
9989 else
9990 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9991
affa9354 9992 if (HAS_DDI(dev)) {
0e8ffe1b 9993 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9994 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9995 dev_priv->display.crtc_enable = haswell_crtc_enable;
9996 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9997 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9998 dev_priv->display.update_plane = ironlake_update_plane;
9999 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10000 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10001 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10002 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10003 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10004 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10005 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10006 } else if (IS_VALLEYVIEW(dev)) {
10007 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10008 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10009 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10010 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10011 dev_priv->display.off = i9xx_crtc_off;
10012 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10013 } else {
0e8ffe1b 10014 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10015 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10016 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10017 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10018 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10019 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10020 }
e70236a8 10021
e70236a8 10022 /* Returns the core display clock speed */
25eb05fc
JB		 10023 if (IS_VALLEYVIEW(dev))
10024 dev_priv->display.get_display_clock_speed =
10025 valleyview_get_display_clock_speed;
10026 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10027 dev_priv->display.get_display_clock_speed =
10028 i945_get_display_clock_speed;
10029 else if (IS_I915G(dev))
10030 dev_priv->display.get_display_clock_speed =
10031 i915_get_display_clock_speed;
257a7ffc 10032 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10033 dev_priv->display.get_display_clock_speed =
10034 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10035 else if (IS_PINEVIEW(dev))
10036 dev_priv->display.get_display_clock_speed =
10037 pnv_get_display_clock_speed;
e70236a8
JB		 10038 else if (IS_I915GM(dev))
10039 dev_priv->display.get_display_clock_speed =
10040 i915gm_get_display_clock_speed;
10041 else if (IS_I865G(dev))
10042 dev_priv->display.get_display_clock_speed =
10043 i865_get_display_clock_speed;
f0f8a9ce 10044 else if (IS_I85X(dev))
e70236a8
JB		 10045 dev_priv->display.get_display_clock_speed =
10046 i855_get_display_clock_speed;
10047 else /* 852, 830 */
10048 dev_priv->display.get_display_clock_speed =
10049 i830_get_display_clock_speed;
10050
7f8a8569 10051 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10052 if (IS_GEN5(dev)) {
674cf967 10053 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10054 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10055 } else if (IS_GEN6(dev)) {
674cf967 10056 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10057 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10058 } else if (IS_IVYBRIDGE(dev)) {
10059 /* FIXME: detect B0+ stepping and use auto training */
10060 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10061 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10062 dev_priv->display.modeset_global_resources =
10063 ivb_modeset_global_resources;
c82e4d26
ED		 10064 } else if (IS_HASWELL(dev)) {
10065 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10066 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10067 dev_priv->display.modeset_global_resources =
10068 haswell_modeset_global_resources;
a0e63c22 10069 }
6067aaea 10070 } else if (IS_G4X(dev)) {
e0dac65e 10071 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10072 }
8c9f3aaf
JB		 10073
10074 /* Default just returns -ENODEV to indicate unsupported */
10075 dev_priv->display.queue_flip = intel_default_queue_flip;
10076
10077 switch (INTEL_INFO(dev)->gen) {
10078 case 2:
10079 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10080 break;
10081
10082 case 3:
10083 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10084 break;
10085
10086 case 4:
10087 case 5:
10088 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10089 break;
10090
10091 case 6:
10092 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10093 break;
7c9017e5
JB		 10094 case 7:
10095 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10096 break;
8c9f3aaf 10097 }
e70236a8
JB		 10098}
10099
b690e96c
JB		 10100/*
10101 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10102 * resume, or other times. This quirk makes sure that's the case for
10103 * affected systems.
10104 */
0206e353 10105static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10106{
10107 struct drm_i915_private *dev_priv = dev->dev_private;
10108
10109 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10110 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10111}
10112
435793df
KP		 10113/*
10114 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10115 */
10116static void quirk_ssc_force_disable(struct drm_device *dev)
10117{
10118 struct drm_i915_private *dev_priv = dev->dev_private;
10119 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10120 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10121}
10122
4dca20ef 10123/*
5a15ab5b
CE		 10124 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10125 * brightness value
4dca20ef
CE		 10126 */
10127static void quirk_invert_brightness(struct drm_device *dev)
10128{
10129 struct drm_i915_private *dev_priv = dev->dev_private;
10130 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10131 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10132}
10133
e85843be
KM		 10134/*
10135 * Some machines (Dell XPS13) suffer broken backlight controls if
10136 * BLM_PCH_PWM_ENABLE is set.
10137 */
10138static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10139{
10140 struct drm_i915_private *dev_priv = dev->dev_private;
10141 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10142 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10143}
10144
b690e96c
JB		 10145struct intel_quirk {
10146 int device;
10147 int subsystem_vendor;
10148 int subsystem_device;
10149 void (*hook)(struct drm_device *dev);
10150};
10151
5f85f176
EE		 10152/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10153struct intel_dmi_quirk {
10154 void (*hook)(struct drm_device *dev);
10155 const struct dmi_system_id (*dmi_id_list)[];
10156};
10157
10158static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10159{
10160 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10161 return 1;
10162}
10163
10164static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10165 {
10166 .dmi_id_list = &(const struct dmi_system_id[]) {
10167 {
10168 .callback = intel_dmi_reverse_brightness,
10169 .ident = "NCR Corporation",
10170 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10171 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10172 },
10173 },
10174 { } /* terminating entry */
10175 },
10176 .hook = quirk_invert_brightness,
10177 },
10178};
10179
c43b5634 10180static struct intel_quirk intel_quirks[] = {
b690e96c 10181 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10182 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10183
b690e96c
JB		 10184 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10185 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10186
b690e96c
JB		 10187 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10188 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10189
ccd0d36e 10190 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10191 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10192 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10193
10194 /* Lenovo U160 cannot use SSC on LVDS */
10195 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10196
10197 /* Sony Vaio Y cannot use SSC on LVDS */
10198 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10199
ee1452d7
JN		 10200 /*
10201 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10202 * seem to use inverted backlight PWM.
10203 */
10204 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10205
10206 /* Dell XPS13 HD Sandy Bridge */
10207 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10208 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10209 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10210};
10211
10212static void intel_init_quirks(struct drm_device *dev)
10213{
10214 struct pci_dev *d = dev->pdev;
10215 int i;
10216
10217 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10218 struct intel_quirk *q = &intel_quirks[i];
10219
10220 if (d->device == q->device &&
10221 (d->subsystem_vendor == q->subsystem_vendor ||
10222 q->subsystem_vendor == PCI_ANY_ID) &&
10223 (d->subsystem_device == q->subsystem_device ||
10224 q->subsystem_device == PCI_ANY_ID))
10225 q->hook(dev);
10226 }
5f85f176
EE		 10227 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10228 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10229 intel_dmi_quirks[i].hook(dev);
10230 }
b690e96c
JB		 10231}
10232
9cce37f4
JB		 10233/* Disable the VGA plane that we never use */
10234static void i915_disable_vga(struct drm_device *dev)
10235{
10236 struct drm_i915_private *dev_priv = dev->dev_private;
10237 u8 sr1;
766aa1c4 10238 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10239
10240 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10241 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10242 sr1 = inb(VGA_SR_DATA);
10243 outb(sr1 | 1<<5, VGA_SR_DATA);
10244 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10245 udelay(300);
10246
10247 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10248 POSTING_READ(vga_reg);
10249}
10250
6e1b4fda 10251static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10252{
10253 /* Enable VGA memory on Intel HD */
10254 if (HAS_PCH_SPLIT(dev)) {
10255 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10256 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10257 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10258 VGA_RSRC_LEGACY_MEM |
10259 VGA_RSRC_NORMAL_IO |
10260 VGA_RSRC_NORMAL_MEM);
10261 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10262 }
10263}
10264
6e1b4fda
VS		 10265void i915_disable_vga_mem(struct drm_device *dev)
10266{
10267 /* Disable VGA memory on Intel HD */
10268 if (HAS_PCH_SPLIT(dev)) {
10269 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10270 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10271 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10272 VGA_RSRC_NORMAL_IO |
10273 VGA_RSRC_NORMAL_MEM);
10274 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10275 }
10276}
10277
f817586c
DV		 10278void intel_modeset_init_hw(struct drm_device *dev)
10279{
a8f78b58
ED		 10280 intel_prepare_ddi(dev);
10281
f817586c
DV		 10282 intel_init_clock_gating(dev);
10283
79f5b2c7 10284 mutex_lock(&dev->struct_mutex);
8090c6b9 10285 intel_enable_gt_powersave(dev);
79f5b2c7 10286 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10287}
10288
7d708ee4
ID		 10289void intel_modeset_suspend_hw(struct drm_device *dev)
10290{
10291 intel_suspend_hw(dev);
10292}
10293
79e53945
JB		 10294void intel_modeset_init(struct drm_device *dev)
10295{
652c393a 10296 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10297 int i, j, ret;
79e53945
JB		 10298
10299 drm_mode_config_init(dev);
10300
10301 dev->mode_config.min_width = 0;
10302 dev->mode_config.min_height = 0;
10303
019d96cb
DA		 10304 dev->mode_config.preferred_depth = 24;
10305 dev->mode_config.prefer_shadow = 1;
10306
e6ecefaa 10307 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10308
b690e96c
JB		 10309 intel_init_quirks(dev);
10310
1fa61106
ED		 10311 intel_init_pm(dev);
10312
e3c74757
BW		 10313 if (INTEL_INFO(dev)->num_pipes == 0)
10314 return;
10315
e70236a8
JB		 10316 intel_init_display(dev);
10317
a6c45cf0
CW		 10318 if (IS_GEN2(dev)) {
10319 dev->mode_config.max_width = 2048;
10320 dev->mode_config.max_height = 2048;
10321 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10322 dev->mode_config.max_width = 4096;
10323 dev->mode_config.max_height = 4096;
79e53945 10324 } else {
a6c45cf0
CW		 10325 dev->mode_config.max_width = 8192;
10326 dev->mode_config.max_height = 8192;
79e53945 10327 }
5d4545ae 10328 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10329
28c97730 10330 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10331 INTEL_INFO(dev)->num_pipes,
10332 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10333
08e2a7de 10334 for_each_pipe(i) {
79e53945 10335 intel_crtc_init(dev, i);
7f1f3851
JB		 10336 for (j = 0; j < dev_priv->num_plane; j++) {
10337 ret = intel_plane_init(dev, i, j);
10338 if (ret)
06da8da2
VS		 10339 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10340 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10341 }
79e53945
JB		 10342 }
10343
79f689aa 10344 intel_cpu_pll_init(dev);
e72f9fbf 10345 intel_shared_dpll_init(dev);
ee7b9f93 10346
9cce37f4
JB		 10347 /* Just disable it once at startup */
10348 i915_disable_vga(dev);
79e53945 10349 intel_setup_outputs(dev);
11be49eb
CW		 10350
10351 /* Just in case the BIOS is doing something questionable. */
10352 intel_disable_fbc(dev);
2c7111db
CW		 10353}
10354
24929352
DV		 10355static void
10356intel_connector_break_all_links(struct intel_connector *connector)
10357{
10358 connector->base.dpms = DRM_MODE_DPMS_OFF;
10359 connector->base.encoder = NULL;
10360 connector->encoder->connectors_active = false;
10361 connector->encoder->base.crtc = NULL;
10362}
10363
7fad798e
DV		 10364static void intel_enable_pipe_a(struct drm_device *dev)
10365{
10366 struct intel_connector *connector;
10367 struct drm_connector *crt = NULL;
10368 struct intel_load_detect_pipe load_detect_temp;
10369
10370 /* We can't just switch on the pipe A, we need to set things up with a
10371 * proper mode and output configuration. As a gross hack, enable pipe A
10372 * by enabling the load detect pipe once. */
10373 list_for_each_entry(connector,
10374 &dev->mode_config.connector_list,
10375 base.head) {
10376 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10377 crt = &connector->base;
10378 break;
10379 }
10380 }
10381
10382 if (!crt)
10383 return;
10384
10385 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10386 intel_release_load_detect_pipe(crt, &load_detect_temp);
10387
652c393a 10388
7fad798e
DV		 10389}
10390
fa555837
DV		 10391static bool
10392intel_check_plane_mapping(struct intel_crtc *crtc)
10393{
7eb552ae
BW		 10394 struct drm_device *dev = crtc->base.dev;
10395 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10396 u32 reg, val;
10397
7eb552ae 10398 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10399 return true;
10400
10401 reg = DSPCNTR(!crtc->plane);
10402 val = I915_READ(reg);
10403
10404 if ((val & DISPLAY_PLANE_ENABLE) &&
10405 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10406 return false;
10407
10408 return true;
10409}
10410
24929352
DV		 10411static void intel_sanitize_crtc(struct intel_crtc *crtc)
10412{
10413 struct drm_device *dev = crtc->base.dev;
10414 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10415 u32 reg;
24929352 10416
24929352 10417 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10418 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10419 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10420
10421 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10422 * disable the crtc (and hence change the state) if it is wrong. Note
10423 * that gen4+ has a fixed plane -> pipe mapping. */
10424 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10425 struct intel_connector *connector;
10426 bool plane;
10427
24929352
DV		 10428 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10429 crtc->base.base.id);
10430
10431 /* Pipe has the wrong plane attached and the plane is active.
10432 * Temporarily change the plane mapping and disable everything
10433 * ... */
10434 plane = crtc->plane;
10435 crtc->plane = !plane;
10436 dev_priv->display.crtc_disable(&crtc->base);
10437 crtc->plane = plane;
10438
10439 /* ... and break all links. */
10440 list_for_each_entry(connector, &dev->mode_config.connector_list,
10441 base.head) {
10442 if (connector->encoder->base.crtc != &crtc->base)
10443 continue;
10444
10445 intel_connector_break_all_links(connector);
10446 }
10447
10448 WARN_ON(crtc->active);
10449 crtc->base.enabled = false;
10450 }
24929352 10451
7fad798e
DV		 10452 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10453 crtc->pipe == PIPE_A && !crtc->active) {
10454 /* BIOS forgot to enable pipe A, this mostly happens after
10455 * resume. Force-enable the pipe to fix this, the update_dpms
10456 * call below we restore the pipe to the right state, but leave
10457 * the required bits on. */
10458 intel_enable_pipe_a(dev);
10459 }
10460
24929352
DV		 10461 /* Adjust the state of the output pipe according to whether we
10462 * have active connectors/encoders. */
10463 intel_crtc_update_dpms(&crtc->base);
10464
10465 if (crtc->active != crtc->base.enabled) {
10466 struct intel_encoder *encoder;
10467
10468 /* This can happen either due to bugs in the get_hw_state
10469 * functions or because the pipe is force-enabled due to the
10470 * pipe A quirk. */
10471 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10472 crtc->base.base.id,
10473 crtc->base.enabled ? "enabled" : "disabled",
10474 crtc->active ? "enabled" : "disabled");
10475
10476 crtc->base.enabled = crtc->active;
10477
10478 /* Because we only establish the connector -> encoder ->
10479 * crtc links if something is active, this means the
10480 * crtc is now deactivated. Break the links. connector
10481 * -> encoder links are only establish when things are
10482 * actually up, hence no need to break them. */
10483 WARN_ON(crtc->active);
10484
10485 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10486 WARN_ON(encoder->connectors_active);
10487 encoder->base.crtc = NULL;
10488 }
10489 }
10490}
10491
10492static void intel_sanitize_encoder(struct intel_encoder *encoder)
10493{
10494 struct intel_connector *connector;
10495 struct drm_device *dev = encoder->base.dev;
10496
10497 /* We need to check both for a crtc link (meaning that the
10498 * encoder is active and trying to read from a pipe) and the
10499 * pipe itself being active. */
10500 bool has_active_crtc = encoder->base.crtc &&
10501 to_intel_crtc(encoder->base.crtc)->active;
10502
10503 if (encoder->connectors_active && !has_active_crtc) {
10504 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10505 encoder->base.base.id,
10506 drm_get_encoder_name(&encoder->base));
10507
10508 /* Connector is active, but has no active pipe. This is
10509 * fallout from our resume register restoring. Disable
10510 * the encoder manually again. */
10511 if (encoder->base.crtc) {
10512 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10513 encoder->base.base.id,
10514 drm_get_encoder_name(&encoder->base));
10515 encoder->disable(encoder);
10516 }
10517
10518 /* Inconsistent output/port/pipe state happens presumably due to
10519 * a bug in one of the get_hw_state functions. Or someplace else
10520 * in our code, like the register restore mess on resume. Clamp
10521 * things to off as a safer default. */
10522 list_for_each_entry(connector,
10523 &dev->mode_config.connector_list,
10524 base.head) {
10525 if (connector->encoder != encoder)
10526 continue;
10527
10528 intel_connector_break_all_links(connector);
10529 }
10530 }
10531 /* Enabled encoders without active connectors will be fixed in
10532 * the crtc fixup. */
10533}
10534
44cec740 10535void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10536{
10537 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10538 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10539
8dc8a27c
PZ		 10540 /* This function can be called both from intel_modeset_setup_hw_state or
10541 * at a very early point in our resume sequence, where the power well
10542 * structures are not yet restored. Since this function is at a very
10543 * paranoid "someone might have enabled VGA while we were not looking"
10544 * level, just check if the power well is enabled instead of trying to
10545 * follow the "don't touch the power well if we don't need it" policy
10546 * the rest of the driver uses. */
10547 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10548 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10549 return;
10550
0fde901f
KM		 10551 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10552 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10553 i915_disable_vga(dev);
6e1b4fda 10554 i915_disable_vga_mem(dev);
0fde901f
KM		 10555 }
10556}
10557
30e984df 10558static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10559{
10560 struct drm_i915_private *dev_priv = dev->dev_private;
10561 enum pipe pipe;
24929352
DV		 10562 struct intel_crtc *crtc;
10563 struct intel_encoder *encoder;
10564 struct intel_connector *connector;
5358901f 10565 int i;
24929352 10566
0e8ffe1b
DV		 10567 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10568 base.head) {
88adfff1 10569 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10570
0e8ffe1b
DV		 10571 crtc->active = dev_priv->display.get_pipe_config(crtc,
10572 &crtc->config);
24929352
DV		 10573
10574 crtc->base.enabled = crtc->active;
10575
10576 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10577 crtc->base.base.id,
10578 crtc->active ? "enabled" : "disabled");
10579 }
10580
5358901f 10581 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10582 if (HAS_DDI(dev))
6441ab5f
PZ		 10583 intel_ddi_setup_hw_pll_state(dev);
10584
5358901f
DV		 10585 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10586 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10587
10588 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10589 pll->active = 0;
10590 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10591 base.head) {
10592 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10593 pll->active++;
10594 }
10595 pll->refcount = pll->active;
10596
35c95375
DV		 10597 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10598 pll->name, pll->refcount, pll->on);
5358901f
DV		 10599 }
10600
24929352
DV		 10601 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10602 base.head) {
10603 pipe = 0;
10604
10605 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10606 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10607 encoder->base.crtc = &crtc->base;
510d5f2f 10608 if (encoder->get_config)
045ac3b5 10609 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10610 } else {
10611 encoder->base.crtc = NULL;
10612 }
10613
10614 encoder->connectors_active = false;
10615 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10616 encoder->base.base.id,
10617 drm_get_encoder_name(&encoder->base),
10618 encoder->base.crtc ? "enabled" : "disabled",
10619 pipe);
10620 }
10621
10622 list_for_each_entry(connector, &dev->mode_config.connector_list,
10623 base.head) {
10624 if (connector->get_hw_state(connector)) {
10625 connector->base.dpms = DRM_MODE_DPMS_ON;
10626 connector->encoder->connectors_active = true;
10627 connector->base.encoder = &connector->encoder->base;
10628 } else {
10629 connector->base.dpms = DRM_MODE_DPMS_OFF;
10630 connector->base.encoder = NULL;
10631 }
10632 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10633 connector->base.base.id,
10634 drm_get_connector_name(&connector->base),
10635 connector->base.encoder ? "enabled" : "disabled");
10636 }
30e984df
DV		 10637}
10638
10639/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10640 * and i915 state tracking structures. */
10641void intel_modeset_setup_hw_state(struct drm_device *dev,
10642 bool force_restore)
10643{
10644 struct drm_i915_private *dev_priv = dev->dev_private;
10645 enum pipe pipe;
30e984df
DV		 10646 struct intel_crtc *crtc;
10647 struct intel_encoder *encoder;
35c95375 10648 int i;
30e984df
DV		 10649
10650 intel_modeset_readout_hw_state(dev);
24929352 10651
babea61d
JB		 10652 /*
10653 * Now that we have the config, copy it to each CRTC struct
10654 * Note that this could go away if we move to using crtc_config
10655 * checking everywhere.
10656 */
10657 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10658 base.head) {
10659 if (crtc->active && i915_fastboot) {
10660 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10661
10662 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10663 crtc->base.base.id);
10664 drm_mode_debug_printmodeline(&crtc->base.mode);
10665 }
10666 }
10667
24929352
DV		 10668 /* HW state is read out, now we need to sanitize this mess. */
10669 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10670 base.head) {
10671 intel_sanitize_encoder(encoder);
10672 }
10673
10674 for_each_pipe(pipe) {
10675 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10676 intel_sanitize_crtc(crtc);
c0b03411 10677 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10678 }
9a935856 10679
35c95375
DV		 10680 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10681 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10682
10683 if (!pll->on || pll->active)
10684 continue;
10685
10686 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10687
10688 pll->disable(dev_priv, pll);
10689 pll->on = false;
10690 }
10691
45e2b5f6 10692 if (force_restore) {
7d0bc1ea
VS		 10693 i915_redisable_vga(dev);
10694
f30da187
DV		 10695 /*
10696 * We need to use raw interfaces for restoring state to avoid
10697 * checking (bogus) intermediate states.
10698 */
45e2b5f6 10699 for_each_pipe(pipe) {
b5644d05
JB		 10700 struct drm_crtc *crtc =
10701 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10702
10703 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10704 crtc->fb);
45e2b5f6
DV		 10705 }
10706 } else {
10707 intel_modeset_update_staged_output_state(dev);
10708 }
8af6cf88
DV		 10709
10710 intel_modeset_check_state(dev);
2e938892
DV		 10711
10712 drm_mode_config_reset(dev);
2c7111db
CW		 10713}
10714
10715void intel_modeset_gem_init(struct drm_device *dev)
10716{
1833b134 10717 intel_modeset_init_hw(dev);
02e792fb
DV		 10718
10719 intel_setup_overlay(dev);
24929352 10720
45e2b5f6 10721 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10722}
10723
10724void intel_modeset_cleanup(struct drm_device *dev)
10725{
652c393a
JB		 10726 struct drm_i915_private *dev_priv = dev->dev_private;
10727 struct drm_crtc *crtc;
652c393a 10728
fd0c0642
DV		 10729 /*
10730 * Interrupts and polling as the first thing to avoid creating havoc.
10731 * Too much stuff here (turning of rps, connectors, ...) would
10732 * experience fancy races otherwise.
10733 */
10734 drm_irq_uninstall(dev);
10735 cancel_work_sync(&dev_priv->hotplug_work);
10736 /*
10737 * Due to the hpd irq storm handling the hotplug work can re-arm the
10738 * poll handlers. Hence disable polling after hpd handling is shut down.
10739 */
f87ea761 10740 drm_kms_helper_poll_fini(dev);
fd0c0642 10741
652c393a
JB		 10742 mutex_lock(&dev->struct_mutex);
10743
723bfd70
JB		 10744 intel_unregister_dsm_handler();
10745
652c393a
JB		 10746 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10747 /* Skip inactive CRTCs */
10748 if (!crtc->fb)
10749 continue;
10750
3dec0095 10751 intel_increase_pllclock(crtc);
652c393a
JB		 10752 }
10753
973d04f9 10754 intel_disable_fbc(dev);
e70236a8 10755
6e1b4fda 10756 i915_enable_vga_mem(dev);
81b5c7bc 10757
8090c6b9 10758 intel_disable_gt_powersave(dev);
0cdab21f 10759
930ebb46
DV		 10760 ironlake_teardown_rc6(dev);
10761
69341a5e
KH		 10762 mutex_unlock(&dev->struct_mutex);
10763
1630fe75
CW		 10764 /* flush any delayed tasks or pending work */
10765 flush_scheduled_work();
10766
dc652f90
JN		 10767 /* destroy backlight, if any, before the connectors */
10768 intel_panel_destroy_backlight(dev);
10769
79e53945 10770 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10771
10772 intel_cleanup_overlay(dev);
79e53945
JB		 10773}
10774
f1c79df3
ZW		 10775/*
10776 * Return which encoder is currently attached for connector.
10777 */
df0e9248 10778struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10779{
df0e9248
CW		 10780 return &intel_attached_encoder(connector)->base;
10781}
f1c79df3 10782
df0e9248
CW		 10783void intel_connector_attach_encoder(struct intel_connector *connector,
10784 struct intel_encoder *encoder)
10785{
10786 connector->encoder = encoder;
10787 drm_mode_connector_attach_encoder(&connector->base,
10788 &encoder->base);
79e53945 10789}
28d52043
DA		 10790
10791/*
10792 * set vga decode state - true == enable VGA decode
10793 */
10794int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10795{
10796 struct drm_i915_private *dev_priv = dev->dev_private;
10797 u16 gmch_ctrl;
10798
10799 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10800 if (state)
10801 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10802 else
10803 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10804 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10805 return 0;
10806}
c4a1d9e4 10807
c4a1d9e4 10808struct intel_display_error_state {
ff57f1b0
PZ		 10809
10810 u32 power_well_driver;
10811
63b66e5b
CW		 10812 int num_transcoders;
10813
c4a1d9e4
CW		 10814 struct intel_cursor_error_state {
10815 u32 control;
10816 u32 position;
10817 u32 base;
10818 u32 size;
52331309 10819 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10820
10821 struct intel_pipe_error_state {
c4a1d9e4 10822 u32 source;
52331309 10823 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10824
10825 struct intel_plane_error_state {
10826 u32 control;
10827 u32 stride;
10828 u32 size;
10829 u32 pos;
10830 u32 addr;
10831 u32 surface;
10832 u32 tile_offset;
52331309 10833 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10834
10835 struct intel_transcoder_error_state {
10836 enum transcoder cpu_transcoder;
10837
10838 u32 conf;
10839
10840 u32 htotal;
10841 u32 hblank;
10842 u32 hsync;
10843 u32 vtotal;
10844 u32 vblank;
10845 u32 vsync;
10846 } transcoder[4];
c4a1d9e4
CW		 10847};
10848
10849struct intel_display_error_state *
10850intel_display_capture_error_state(struct drm_device *dev)
10851{
0206e353 10852 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10853 struct intel_display_error_state *error;
63b66e5b
CW		 10854 int transcoders[] = {
10855 TRANSCODER_A,
10856 TRANSCODER_B,
10857 TRANSCODER_C,
10858 TRANSCODER_EDP,
10859 };
c4a1d9e4
CW		 10860 int i;
10861
63b66e5b
CW		 10862 if (INTEL_INFO(dev)->num_pipes == 0)
10863 return NULL;
10864
c4a1d9e4
CW		 10865 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10866 if (error == NULL)
10867 return NULL;
10868
ff57f1b0
PZ		 10869 if (HAS_POWER_WELL(dev))
10870 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10871
52331309 10872 for_each_pipe(i) {
a18c4c3d
PZ		 10873 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10874 error->cursor[i].control = I915_READ(CURCNTR(i));
10875 error->cursor[i].position = I915_READ(CURPOS(i));
10876 error->cursor[i].base = I915_READ(CURBASE(i));
10877 } else {
10878 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10879 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10880 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10881 }
c4a1d9e4
CW		 10882
10883 error->plane[i].control = I915_READ(DSPCNTR(i));
10884 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10885 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10886 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10887 error->plane[i].pos = I915_READ(DSPPOS(i));
10888 }
ca291363
PZ		 10889 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10890 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10891 if (INTEL_INFO(dev)->gen >= 4) {
10892 error->plane[i].surface = I915_READ(DSPSURF(i));
10893 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10894 }
10895
c4a1d9e4 10896 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10897 }
10898
10899 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10900 if (HAS_DDI(dev_priv->dev))
10901 error->num_transcoders++; /* Account for eDP. */
10902
10903 for (i = 0; i < error->num_transcoders; i++) {
10904 enum transcoder cpu_transcoder = transcoders[i];
10905
10906 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10907
10908 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10909 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10910 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10911 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10912 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10913 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10914 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10915 }
10916
12d217c7
PZ		 10917 /* In the code above we read the registers without checking if the power
10918 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10919 * prevent the next I915_WRITE from detecting it and printing an error
10920 * message. */
907b28c5 10921 intel_uncore_clear_errors(dev);
12d217c7 10922
c4a1d9e4
CW		 10923 return error;
10924}
10925
edc3d884
MK		 10926#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10927
c4a1d9e4 10928void
edc3d884 10929intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10930 struct drm_device *dev,
10931 struct intel_display_error_state *error)
10932{
10933 int i;
10934
63b66e5b
CW		 10935 if (!error)
10936 return;
10937
edc3d884 10938 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10939 if (HAS_POWER_WELL(dev))
edc3d884 10940 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10941 error->power_well_driver);
52331309 10942 for_each_pipe(i) {
edc3d884 10943 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10944 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10945
10946 err_printf(m, "Plane [%d]:\n", i);
10947 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10948 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10949 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10950 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10951 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10952 }
4b71a570 10953 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10954 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10955 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10956 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10957 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10958 }
10959
edc3d884
MK		 10960 err_printf(m, "Cursor [%d]:\n", i);
10961 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10962 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10963 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10964 }
63b66e5b
CW		 10965
10966 for (i = 0; i < error->num_transcoders; i++) {
10967 err_printf(m, " CPU transcoder: %c\n",
10968 transcoder_name(error->transcoder[i].cpu_transcoder));
10969 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10970 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10971 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10972 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10973 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10974 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10975 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10976 }
c4a1d9e4 10977}
Linux kernel - Deliverables
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