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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c MR |
48 | /* Primary plane formats supported by all gen */ |
49 | #define COMMON_PRIMARY_FORMATS \ | |
50 | DRM_FORMAT_C8, \ | |
51 | DRM_FORMAT_RGB565, \ | |
52 | DRM_FORMAT_XRGB8888, \ | |
53 | DRM_FORMAT_ARGB8888 | |
54 | ||
55 | /* Primary plane formats for gen <= 3 */ | |
56 | static const uint32_t intel_primary_formats_gen2[] = { | |
57 | COMMON_PRIMARY_FORMATS, | |
58 | DRM_FORMAT_XRGB1555, | |
59 | DRM_FORMAT_ARGB1555, | |
60 | }; | |
61 | ||
62 | /* Primary plane formats for gen >= 4 */ | |
63 | static const uint32_t intel_primary_formats_gen4[] = { | |
64 | COMMON_PRIMARY_FORMATS, \ | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_ABGR8888, | |
67 | DRM_FORMAT_XRGB2101010, | |
68 | DRM_FORMAT_ARGB2101010, | |
69 | DRM_FORMAT_XBGR2101010, | |
70 | DRM_FORMAT_ABGR2101010, | |
71 | }; | |
72 | ||
3d7d6510 MR |
73 | /* Cursor formats */ |
74 | static const uint32_t intel_cursor_formats[] = { | |
75 | DRM_FORMAT_ARGB8888, | |
76 | }; | |
77 | ||
6b383a7f | 78 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 79 | |
f1f644dc | 80 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 81 | struct intel_crtc_state *pipe_config); |
18442d08 | 82 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 83 | struct intel_crtc_state *pipe_config); |
f1f644dc | 84 | |
8c7b5ccb | 85 | static int intel_set_mode(struct drm_crtc *crtc, |
83a57153 | 86 | struct drm_atomic_state *state); |
eb1bfe80 JB |
87 | static int intel_framebuffer_init(struct drm_device *dev, |
88 | struct intel_framebuffer *ifb, | |
89 | struct drm_mode_fb_cmd2 *mode_cmd, | |
90 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
91 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
92 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 93 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
94 | struct intel_link_m_n *m_n, |
95 | struct intel_link_m_n *m2_n2); | |
29407aab | 96 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
97 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
98 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 99 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 100 | const struct intel_crtc_state *pipe_config); |
d288f65f | 101 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 102 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
103 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
104 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
549e2bfb CK |
105 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
106 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
107 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
108 | int num_connectors); | |
ce22dba9 ML |
109 | static void intel_crtc_enable_planes(struct drm_crtc *crtc); |
110 | static void intel_crtc_disable_planes(struct drm_crtc *crtc); | |
e7457a9a | 111 | |
0e32b39c DA |
112 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
113 | { | |
114 | if (!connector->mst_port) | |
115 | return connector->encoder; | |
116 | else | |
117 | return &connector->mst_port->mst_encoders[pipe]->base; | |
118 | } | |
119 | ||
79e53945 | 120 | typedef struct { |
0206e353 | 121 | int min, max; |
79e53945 JB |
122 | } intel_range_t; |
123 | ||
124 | typedef struct { | |
0206e353 AJ |
125 | int dot_limit; |
126 | int p2_slow, p2_fast; | |
79e53945 JB |
127 | } intel_p2_t; |
128 | ||
d4906093 ML |
129 | typedef struct intel_limit intel_limit_t; |
130 | struct intel_limit { | |
0206e353 AJ |
131 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
132 | intel_p2_t p2; | |
d4906093 | 133 | }; |
79e53945 | 134 | |
d2acd215 DV |
135 | int |
136 | intel_pch_rawclk(struct drm_device *dev) | |
137 | { | |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
139 | ||
140 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
141 | ||
142 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
143 | } | |
144 | ||
021357ac CW |
145 | static inline u32 /* units of 100MHz */ |
146 | intel_fdi_link_freq(struct drm_device *dev) | |
147 | { | |
8b99e68c CW |
148 | if (IS_GEN5(dev)) { |
149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
150 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
151 | } else | |
152 | return 27; | |
021357ac CW |
153 | } |
154 | ||
5d536e28 | 155 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 156 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 157 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 158 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
159 | .m = { .min = 96, .max = 140 }, |
160 | .m1 = { .min = 18, .max = 26 }, | |
161 | .m2 = { .min = 6, .max = 16 }, | |
162 | .p = { .min = 4, .max = 128 }, | |
163 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
164 | .p2 = { .dot_limit = 165000, |
165 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
166 | }; |
167 | ||
5d536e28 DV |
168 | static const intel_limit_t intel_limits_i8xx_dvo = { |
169 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 170 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 171 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
172 | .m = { .min = 96, .max = 140 }, |
173 | .m1 = { .min = 18, .max = 26 }, | |
174 | .m2 = { .min = 6, .max = 16 }, | |
175 | .p = { .min = 4, .max = 128 }, | |
176 | .p1 = { .min = 2, .max = 33 }, | |
177 | .p2 = { .dot_limit = 165000, | |
178 | .p2_slow = 4, .p2_fast = 4 }, | |
179 | }; | |
180 | ||
e4b36699 | 181 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 182 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 183 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 184 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
185 | .m = { .min = 96, .max = 140 }, |
186 | .m1 = { .min = 18, .max = 26 }, | |
187 | .m2 = { .min = 6, .max = 16 }, | |
188 | .p = { .min = 4, .max = 128 }, | |
189 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
190 | .p2 = { .dot_limit = 165000, |
191 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 192 | }; |
273e27ca | 193 | |
e4b36699 | 194 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
195 | .dot = { .min = 20000, .max = 400000 }, |
196 | .vco = { .min = 1400000, .max = 2800000 }, | |
197 | .n = { .min = 1, .max = 6 }, | |
198 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
199 | .m1 = { .min = 8, .max = 18 }, |
200 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
201 | .p = { .min = 5, .max = 80 }, |
202 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
203 | .p2 = { .dot_limit = 200000, |
204 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
205 | }; |
206 | ||
207 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
208 | .dot = { .min = 20000, .max = 400000 }, |
209 | .vco = { .min = 1400000, .max = 2800000 }, | |
210 | .n = { .min = 1, .max = 6 }, | |
211 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
212 | .m1 = { .min = 8, .max = 18 }, |
213 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
214 | .p = { .min = 7, .max = 98 }, |
215 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
216 | .p2 = { .dot_limit = 112000, |
217 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
218 | }; |
219 | ||
273e27ca | 220 | |
e4b36699 | 221 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
222 | .dot = { .min = 25000, .max = 270000 }, |
223 | .vco = { .min = 1750000, .max = 3500000}, | |
224 | .n = { .min = 1, .max = 4 }, | |
225 | .m = { .min = 104, .max = 138 }, | |
226 | .m1 = { .min = 17, .max = 23 }, | |
227 | .m2 = { .min = 5, .max = 11 }, | |
228 | .p = { .min = 10, .max = 30 }, | |
229 | .p1 = { .min = 1, .max = 3}, | |
230 | .p2 = { .dot_limit = 270000, | |
231 | .p2_slow = 10, | |
232 | .p2_fast = 10 | |
044c7c41 | 233 | }, |
e4b36699 KP |
234 | }; |
235 | ||
236 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
237 | .dot = { .min = 22000, .max = 400000 }, |
238 | .vco = { .min = 1750000, .max = 3500000}, | |
239 | .n = { .min = 1, .max = 4 }, | |
240 | .m = { .min = 104, .max = 138 }, | |
241 | .m1 = { .min = 16, .max = 23 }, | |
242 | .m2 = { .min = 5, .max = 11 }, | |
243 | .p = { .min = 5, .max = 80 }, | |
244 | .p1 = { .min = 1, .max = 8}, | |
245 | .p2 = { .dot_limit = 165000, | |
246 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
247 | }; |
248 | ||
249 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
250 | .dot = { .min = 20000, .max = 115000 }, |
251 | .vco = { .min = 1750000, .max = 3500000 }, | |
252 | .n = { .min = 1, .max = 3 }, | |
253 | .m = { .min = 104, .max = 138 }, | |
254 | .m1 = { .min = 17, .max = 23 }, | |
255 | .m2 = { .min = 5, .max = 11 }, | |
256 | .p = { .min = 28, .max = 112 }, | |
257 | .p1 = { .min = 2, .max = 8 }, | |
258 | .p2 = { .dot_limit = 0, | |
259 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 260 | }, |
e4b36699 KP |
261 | }; |
262 | ||
263 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
264 | .dot = { .min = 80000, .max = 224000 }, |
265 | .vco = { .min = 1750000, .max = 3500000 }, | |
266 | .n = { .min = 1, .max = 3 }, | |
267 | .m = { .min = 104, .max = 138 }, | |
268 | .m1 = { .min = 17, .max = 23 }, | |
269 | .m2 = { .min = 5, .max = 11 }, | |
270 | .p = { .min = 14, .max = 42 }, | |
271 | .p1 = { .min = 2, .max = 6 }, | |
272 | .p2 = { .dot_limit = 0, | |
273 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 274 | }, |
e4b36699 KP |
275 | }; |
276 | ||
f2b115e6 | 277 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
278 | .dot = { .min = 20000, .max = 400000}, |
279 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 280 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
281 | .n = { .min = 3, .max = 6 }, |
282 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 283 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
284 | .m1 = { .min = 0, .max = 0 }, |
285 | .m2 = { .min = 0, .max = 254 }, | |
286 | .p = { .min = 5, .max = 80 }, | |
287 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
288 | .p2 = { .dot_limit = 200000, |
289 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
290 | }; |
291 | ||
f2b115e6 | 292 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
293 | .dot = { .min = 20000, .max = 400000 }, |
294 | .vco = { .min = 1700000, .max = 3500000 }, | |
295 | .n = { .min = 3, .max = 6 }, | |
296 | .m = { .min = 2, .max = 256 }, | |
297 | .m1 = { .min = 0, .max = 0 }, | |
298 | .m2 = { .min = 0, .max = 254 }, | |
299 | .p = { .min = 7, .max = 112 }, | |
300 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
301 | .p2 = { .dot_limit = 112000, |
302 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
303 | }; |
304 | ||
273e27ca EA |
305 | /* Ironlake / Sandybridge |
306 | * | |
307 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
308 | * the range value for them is (actual_value - 2). | |
309 | */ | |
b91ad0ec | 310 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
311 | .dot = { .min = 25000, .max = 350000 }, |
312 | .vco = { .min = 1760000, .max = 3510000 }, | |
313 | .n = { .min = 1, .max = 5 }, | |
314 | .m = { .min = 79, .max = 127 }, | |
315 | .m1 = { .min = 12, .max = 22 }, | |
316 | .m2 = { .min = 5, .max = 9 }, | |
317 | .p = { .min = 5, .max = 80 }, | |
318 | .p1 = { .min = 1, .max = 8 }, | |
319 | .p2 = { .dot_limit = 225000, | |
320 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
321 | }; |
322 | ||
b91ad0ec | 323 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
324 | .dot = { .min = 25000, .max = 350000 }, |
325 | .vco = { .min = 1760000, .max = 3510000 }, | |
326 | .n = { .min = 1, .max = 3 }, | |
327 | .m = { .min = 79, .max = 118 }, | |
328 | .m1 = { .min = 12, .max = 22 }, | |
329 | .m2 = { .min = 5, .max = 9 }, | |
330 | .p = { .min = 28, .max = 112 }, | |
331 | .p1 = { .min = 2, .max = 8 }, | |
332 | .p2 = { .dot_limit = 225000, | |
333 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
334 | }; |
335 | ||
336 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
337 | .dot = { .min = 25000, .max = 350000 }, |
338 | .vco = { .min = 1760000, .max = 3510000 }, | |
339 | .n = { .min = 1, .max = 3 }, | |
340 | .m = { .min = 79, .max = 127 }, | |
341 | .m1 = { .min = 12, .max = 22 }, | |
342 | .m2 = { .min = 5, .max = 9 }, | |
343 | .p = { .min = 14, .max = 56 }, | |
344 | .p1 = { .min = 2, .max = 8 }, | |
345 | .p2 = { .dot_limit = 225000, | |
346 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
347 | }; |
348 | ||
273e27ca | 349 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 350 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
351 | .dot = { .min = 25000, .max = 350000 }, |
352 | .vco = { .min = 1760000, .max = 3510000 }, | |
353 | .n = { .min = 1, .max = 2 }, | |
354 | .m = { .min = 79, .max = 126 }, | |
355 | .m1 = { .min = 12, .max = 22 }, | |
356 | .m2 = { .min = 5, .max = 9 }, | |
357 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 358 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
359 | .p2 = { .dot_limit = 225000, |
360 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
361 | }; |
362 | ||
363 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
364 | .dot = { .min = 25000, .max = 350000 }, |
365 | .vco = { .min = 1760000, .max = 3510000 }, | |
366 | .n = { .min = 1, .max = 3 }, | |
367 | .m = { .min = 79, .max = 126 }, | |
368 | .m1 = { .min = 12, .max = 22 }, | |
369 | .m2 = { .min = 5, .max = 9 }, | |
370 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 371 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
372 | .p2 = { .dot_limit = 225000, |
373 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
374 | }; |
375 | ||
dc730512 | 376 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
377 | /* |
378 | * These are the data rate limits (measured in fast clocks) | |
379 | * since those are the strictest limits we have. The fast | |
380 | * clock and actual rate limits are more relaxed, so checking | |
381 | * them would make no difference. | |
382 | */ | |
383 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 384 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 385 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
386 | .m1 = { .min = 2, .max = 3 }, |
387 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 388 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 389 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
390 | }; |
391 | ||
ef9348c8 CML |
392 | static const intel_limit_t intel_limits_chv = { |
393 | /* | |
394 | * These are the data rate limits (measured in fast clocks) | |
395 | * since those are the strictest limits we have. The fast | |
396 | * clock and actual rate limits are more relaxed, so checking | |
397 | * them would make no difference. | |
398 | */ | |
399 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 400 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
401 | .n = { .min = 1, .max = 1 }, |
402 | .m1 = { .min = 2, .max = 2 }, | |
403 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
404 | .p1 = { .min = 2, .max = 4 }, | |
405 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
406 | }; | |
407 | ||
5ab7b0b7 ID |
408 | static const intel_limit_t intel_limits_bxt = { |
409 | /* FIXME: find real dot limits */ | |
410 | .dot = { .min = 0, .max = INT_MAX }, | |
411 | .vco = { .min = 4800000, .max = 6480000 }, | |
412 | .n = { .min = 1, .max = 1 }, | |
413 | .m1 = { .min = 2, .max = 2 }, | |
414 | /* FIXME: find real m2 limits */ | |
415 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
416 | .p1 = { .min = 2, .max = 4 }, | |
417 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
418 | }; | |
419 | ||
6b4bf1c4 VS |
420 | static void vlv_clock(int refclk, intel_clock_t *clock) |
421 | { | |
422 | clock->m = clock->m1 * clock->m2; | |
423 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
424 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
425 | return; | |
fb03ac01 VS |
426 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
427 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
428 | } |
429 | ||
e0638cdf PZ |
430 | /** |
431 | * Returns whether any output on the specified pipe is of the specified type | |
432 | */ | |
4093561b | 433 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 434 | { |
409ee761 | 435 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
436 | struct intel_encoder *encoder; |
437 | ||
409ee761 | 438 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
439 | if (encoder->type == type) |
440 | return true; | |
441 | ||
442 | return false; | |
443 | } | |
444 | ||
d0737e1d ACO |
445 | /** |
446 | * Returns whether any output on the specified pipe will have the specified | |
447 | * type after a staged modeset is complete, i.e., the same as | |
448 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
449 | * encoder->crtc. | |
450 | */ | |
a93e255f ACO |
451 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
452 | int type) | |
d0737e1d | 453 | { |
a93e255f | 454 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 455 | struct drm_connector *connector; |
a93e255f | 456 | struct drm_connector_state *connector_state; |
d0737e1d | 457 | struct intel_encoder *encoder; |
a93e255f ACO |
458 | int i, num_connectors = 0; |
459 | ||
da3ced29 | 460 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
461 | if (connector_state->crtc != crtc_state->base.crtc) |
462 | continue; | |
463 | ||
464 | num_connectors++; | |
d0737e1d | 465 | |
a93e255f ACO |
466 | encoder = to_intel_encoder(connector_state->best_encoder); |
467 | if (encoder->type == type) | |
d0737e1d | 468 | return true; |
a93e255f ACO |
469 | } |
470 | ||
471 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
472 | |
473 | return false; | |
474 | } | |
475 | ||
a93e255f ACO |
476 | static const intel_limit_t * |
477 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 478 | { |
a93e255f | 479 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 480 | const intel_limit_t *limit; |
b91ad0ec | 481 | |
a93e255f | 482 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 483 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 484 | if (refclk == 100000) |
b91ad0ec ZW |
485 | limit = &intel_limits_ironlake_dual_lvds_100m; |
486 | else | |
487 | limit = &intel_limits_ironlake_dual_lvds; | |
488 | } else { | |
1b894b59 | 489 | if (refclk == 100000) |
b91ad0ec ZW |
490 | limit = &intel_limits_ironlake_single_lvds_100m; |
491 | else | |
492 | limit = &intel_limits_ironlake_single_lvds; | |
493 | } | |
c6bb3538 | 494 | } else |
b91ad0ec | 495 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
496 | |
497 | return limit; | |
498 | } | |
499 | ||
a93e255f ACO |
500 | static const intel_limit_t * |
501 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 502 | { |
a93e255f | 503 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
504 | const intel_limit_t *limit; |
505 | ||
a93e255f | 506 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 507 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 508 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 509 | else |
e4b36699 | 510 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
511 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
512 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 513 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 514 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 515 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 516 | } else /* The option is for other outputs */ |
e4b36699 | 517 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
518 | |
519 | return limit; | |
520 | } | |
521 | ||
a93e255f ACO |
522 | static const intel_limit_t * |
523 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 524 | { |
a93e255f | 525 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
526 | const intel_limit_t *limit; |
527 | ||
5ab7b0b7 ID |
528 | if (IS_BROXTON(dev)) |
529 | limit = &intel_limits_bxt; | |
530 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 531 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 532 | else if (IS_G4X(dev)) { |
a93e255f | 533 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 534 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 535 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 536 | limit = &intel_limits_pineview_lvds; |
2177832f | 537 | else |
f2b115e6 | 538 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
539 | } else if (IS_CHERRYVIEW(dev)) { |
540 | limit = &intel_limits_chv; | |
a0c4da24 | 541 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 542 | limit = &intel_limits_vlv; |
a6c45cf0 | 543 | } else if (!IS_GEN2(dev)) { |
a93e255f | 544 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
545 | limit = &intel_limits_i9xx_lvds; |
546 | else | |
547 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 548 | } else { |
a93e255f | 549 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 550 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 551 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 552 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
553 | else |
554 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
555 | } |
556 | return limit; | |
557 | } | |
558 | ||
f2b115e6 AJ |
559 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
560 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 561 | { |
2177832f SL |
562 | clock->m = clock->m2 + 2; |
563 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
564 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
565 | return; | |
fb03ac01 VS |
566 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
567 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
568 | } |
569 | ||
7429e9d4 DV |
570 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
571 | { | |
572 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
573 | } | |
574 | ||
ac58c3f0 | 575 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 576 | { |
7429e9d4 | 577 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 578 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
579 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
580 | return; | |
fb03ac01 VS |
581 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
582 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
583 | } |
584 | ||
ef9348c8 CML |
585 | static void chv_clock(int refclk, intel_clock_t *clock) |
586 | { | |
587 | clock->m = clock->m1 * clock->m2; | |
588 | clock->p = clock->p1 * clock->p2; | |
589 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
590 | return; | |
591 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
592 | clock->n << 22); | |
593 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
594 | } | |
595 | ||
7c04d1d9 | 596 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
597 | /** |
598 | * Returns whether the given set of divisors are valid for a given refclk with | |
599 | * the given connectors. | |
600 | */ | |
601 | ||
1b894b59 CW |
602 | static bool intel_PLL_is_valid(struct drm_device *dev, |
603 | const intel_limit_t *limit, | |
604 | const intel_clock_t *clock) | |
79e53945 | 605 | { |
f01b7962 VS |
606 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
607 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 608 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 609 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 610 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 611 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 612 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 613 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 614 | |
5ab7b0b7 | 615 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
616 | if (clock->m1 <= clock->m2) |
617 | INTELPllInvalid("m1 <= m2\n"); | |
618 | ||
5ab7b0b7 | 619 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
620 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
621 | INTELPllInvalid("p out of range\n"); | |
622 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
623 | INTELPllInvalid("m out of range\n"); | |
624 | } | |
625 | ||
79e53945 | 626 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 627 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
628 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
629 | * connector, etc., rather than just a single range. | |
630 | */ | |
631 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 632 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
633 | |
634 | return true; | |
635 | } | |
636 | ||
d4906093 | 637 | static bool |
a93e255f ACO |
638 | i9xx_find_best_dpll(const intel_limit_t *limit, |
639 | struct intel_crtc_state *crtc_state, | |
cec2f356 SP |
640 | int target, int refclk, intel_clock_t *match_clock, |
641 | intel_clock_t *best_clock) | |
79e53945 | 642 | { |
a93e255f | 643 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 644 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 645 | intel_clock_t clock; |
79e53945 JB |
646 | int err = target; |
647 | ||
a93e255f | 648 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 649 | /* |
a210b028 DV |
650 | * For LVDS just rely on its current settings for dual-channel. |
651 | * We haven't figured out how to reliably set up different | |
652 | * single/dual channel state, if we even can. | |
79e53945 | 653 | */ |
1974cad0 | 654 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
655 | clock.p2 = limit->p2.p2_fast; |
656 | else | |
657 | clock.p2 = limit->p2.p2_slow; | |
658 | } else { | |
659 | if (target < limit->p2.dot_limit) | |
660 | clock.p2 = limit->p2.p2_slow; | |
661 | else | |
662 | clock.p2 = limit->p2.p2_fast; | |
663 | } | |
664 | ||
0206e353 | 665 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 666 | |
42158660 ZY |
667 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
668 | clock.m1++) { | |
669 | for (clock.m2 = limit->m2.min; | |
670 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 671 | if (clock.m2 >= clock.m1) |
42158660 ZY |
672 | break; |
673 | for (clock.n = limit->n.min; | |
674 | clock.n <= limit->n.max; clock.n++) { | |
675 | for (clock.p1 = limit->p1.min; | |
676 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
677 | int this_err; |
678 | ||
ac58c3f0 DV |
679 | i9xx_clock(refclk, &clock); |
680 | if (!intel_PLL_is_valid(dev, limit, | |
681 | &clock)) | |
682 | continue; | |
683 | if (match_clock && | |
684 | clock.p != match_clock->p) | |
685 | continue; | |
686 | ||
687 | this_err = abs(clock.dot - target); | |
688 | if (this_err < err) { | |
689 | *best_clock = clock; | |
690 | err = this_err; | |
691 | } | |
692 | } | |
693 | } | |
694 | } | |
695 | } | |
696 | ||
697 | return (err != target); | |
698 | } | |
699 | ||
700 | static bool | |
a93e255f ACO |
701 | pnv_find_best_dpll(const intel_limit_t *limit, |
702 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
703 | int target, int refclk, intel_clock_t *match_clock, |
704 | intel_clock_t *best_clock) | |
79e53945 | 705 | { |
a93e255f | 706 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 707 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 708 | intel_clock_t clock; |
79e53945 JB |
709 | int err = target; |
710 | ||
a93e255f | 711 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 712 | /* |
a210b028 DV |
713 | * For LVDS just rely on its current settings for dual-channel. |
714 | * We haven't figured out how to reliably set up different | |
715 | * single/dual channel state, if we even can. | |
79e53945 | 716 | */ |
1974cad0 | 717 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
718 | clock.p2 = limit->p2.p2_fast; |
719 | else | |
720 | clock.p2 = limit->p2.p2_slow; | |
721 | } else { | |
722 | if (target < limit->p2.dot_limit) | |
723 | clock.p2 = limit->p2.p2_slow; | |
724 | else | |
725 | clock.p2 = limit->p2.p2_fast; | |
726 | } | |
727 | ||
0206e353 | 728 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 729 | |
42158660 ZY |
730 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
731 | clock.m1++) { | |
732 | for (clock.m2 = limit->m2.min; | |
733 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
734 | for (clock.n = limit->n.min; |
735 | clock.n <= limit->n.max; clock.n++) { | |
736 | for (clock.p1 = limit->p1.min; | |
737 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
738 | int this_err; |
739 | ||
ac58c3f0 | 740 | pineview_clock(refclk, &clock); |
1b894b59 CW |
741 | if (!intel_PLL_is_valid(dev, limit, |
742 | &clock)) | |
79e53945 | 743 | continue; |
cec2f356 SP |
744 | if (match_clock && |
745 | clock.p != match_clock->p) | |
746 | continue; | |
79e53945 JB |
747 | |
748 | this_err = abs(clock.dot - target); | |
749 | if (this_err < err) { | |
750 | *best_clock = clock; | |
751 | err = this_err; | |
752 | } | |
753 | } | |
754 | } | |
755 | } | |
756 | } | |
757 | ||
758 | return (err != target); | |
759 | } | |
760 | ||
d4906093 | 761 | static bool |
a93e255f ACO |
762 | g4x_find_best_dpll(const intel_limit_t *limit, |
763 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
764 | int target, int refclk, intel_clock_t *match_clock, |
765 | intel_clock_t *best_clock) | |
d4906093 | 766 | { |
a93e255f | 767 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 768 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
769 | intel_clock_t clock; |
770 | int max_n; | |
771 | bool found; | |
6ba770dc AJ |
772 | /* approximately equals target * 0.00585 */ |
773 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
774 | found = false; |
775 | ||
a93e255f | 776 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 777 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
778 | clock.p2 = limit->p2.p2_fast; |
779 | else | |
780 | clock.p2 = limit->p2.p2_slow; | |
781 | } else { | |
782 | if (target < limit->p2.dot_limit) | |
783 | clock.p2 = limit->p2.p2_slow; | |
784 | else | |
785 | clock.p2 = limit->p2.p2_fast; | |
786 | } | |
787 | ||
788 | memset(best_clock, 0, sizeof(*best_clock)); | |
789 | max_n = limit->n.max; | |
f77f13e2 | 790 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 791 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 792 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
793 | for (clock.m1 = limit->m1.max; |
794 | clock.m1 >= limit->m1.min; clock.m1--) { | |
795 | for (clock.m2 = limit->m2.max; | |
796 | clock.m2 >= limit->m2.min; clock.m2--) { | |
797 | for (clock.p1 = limit->p1.max; | |
798 | clock.p1 >= limit->p1.min; clock.p1--) { | |
799 | int this_err; | |
800 | ||
ac58c3f0 | 801 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
802 | if (!intel_PLL_is_valid(dev, limit, |
803 | &clock)) | |
d4906093 | 804 | continue; |
1b894b59 CW |
805 | |
806 | this_err = abs(clock.dot - target); | |
d4906093 ML |
807 | if (this_err < err_most) { |
808 | *best_clock = clock; | |
809 | err_most = this_err; | |
810 | max_n = clock.n; | |
811 | found = true; | |
812 | } | |
813 | } | |
814 | } | |
815 | } | |
816 | } | |
2c07245f ZW |
817 | return found; |
818 | } | |
819 | ||
d5dd62bd ID |
820 | /* |
821 | * Check if the calculated PLL configuration is more optimal compared to the | |
822 | * best configuration and error found so far. Return the calculated error. | |
823 | */ | |
824 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
825 | const intel_clock_t *calculated_clock, | |
826 | const intel_clock_t *best_clock, | |
827 | unsigned int best_error_ppm, | |
828 | unsigned int *error_ppm) | |
829 | { | |
9ca3ba01 ID |
830 | /* |
831 | * For CHV ignore the error and consider only the P value. | |
832 | * Prefer a bigger P value based on HW requirements. | |
833 | */ | |
834 | if (IS_CHERRYVIEW(dev)) { | |
835 | *error_ppm = 0; | |
836 | ||
837 | return calculated_clock->p > best_clock->p; | |
838 | } | |
839 | ||
24be4e46 ID |
840 | if (WARN_ON_ONCE(!target_freq)) |
841 | return false; | |
842 | ||
d5dd62bd ID |
843 | *error_ppm = div_u64(1000000ULL * |
844 | abs(target_freq - calculated_clock->dot), | |
845 | target_freq); | |
846 | /* | |
847 | * Prefer a better P value over a better (smaller) error if the error | |
848 | * is small. Ensure this preference for future configurations too by | |
849 | * setting the error to 0. | |
850 | */ | |
851 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
852 | *error_ppm = 0; | |
853 | ||
854 | return true; | |
855 | } | |
856 | ||
857 | return *error_ppm + 10 < best_error_ppm; | |
858 | } | |
859 | ||
a0c4da24 | 860 | static bool |
a93e255f ACO |
861 | vlv_find_best_dpll(const intel_limit_t *limit, |
862 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
863 | int target, int refclk, intel_clock_t *match_clock, |
864 | intel_clock_t *best_clock) | |
a0c4da24 | 865 | { |
a93e255f | 866 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 867 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 868 | intel_clock_t clock; |
69e4f900 | 869 | unsigned int bestppm = 1000000; |
27e639bf VS |
870 | /* min update 19.2 MHz */ |
871 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 872 | bool found = false; |
a0c4da24 | 873 | |
6b4bf1c4 VS |
874 | target *= 5; /* fast clock */ |
875 | ||
876 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
877 | |
878 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 879 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 880 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 881 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 882 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 883 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 884 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 885 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 886 | unsigned int ppm; |
69e4f900 | 887 | |
6b4bf1c4 VS |
888 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
889 | refclk * clock.m1); | |
890 | ||
891 | vlv_clock(refclk, &clock); | |
43b0ac53 | 892 | |
f01b7962 VS |
893 | if (!intel_PLL_is_valid(dev, limit, |
894 | &clock)) | |
43b0ac53 VS |
895 | continue; |
896 | ||
d5dd62bd ID |
897 | if (!vlv_PLL_is_optimal(dev, target, |
898 | &clock, | |
899 | best_clock, | |
900 | bestppm, &ppm)) | |
901 | continue; | |
6b4bf1c4 | 902 | |
d5dd62bd ID |
903 | *best_clock = clock; |
904 | bestppm = ppm; | |
905 | found = true; | |
a0c4da24 JB |
906 | } |
907 | } | |
908 | } | |
909 | } | |
a0c4da24 | 910 | |
49e497ef | 911 | return found; |
a0c4da24 | 912 | } |
a4fc5ed6 | 913 | |
ef9348c8 | 914 | static bool |
a93e255f ACO |
915 | chv_find_best_dpll(const intel_limit_t *limit, |
916 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
917 | int target, int refclk, intel_clock_t *match_clock, |
918 | intel_clock_t *best_clock) | |
919 | { | |
a93e255f | 920 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 921 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 922 | unsigned int best_error_ppm; |
ef9348c8 CML |
923 | intel_clock_t clock; |
924 | uint64_t m2; | |
925 | int found = false; | |
926 | ||
927 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 928 | best_error_ppm = 1000000; |
ef9348c8 CML |
929 | |
930 | /* | |
931 | * Based on hardware doc, the n always set to 1, and m1 always | |
932 | * set to 2. If requires to support 200Mhz refclk, we need to | |
933 | * revisit this because n may not 1 anymore. | |
934 | */ | |
935 | clock.n = 1, clock.m1 = 2; | |
936 | target *= 5; /* fast clock */ | |
937 | ||
938 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
939 | for (clock.p2 = limit->p2.p2_fast; | |
940 | clock.p2 >= limit->p2.p2_slow; | |
941 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 942 | unsigned int error_ppm; |
ef9348c8 CML |
943 | |
944 | clock.p = clock.p1 * clock.p2; | |
945 | ||
946 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
947 | clock.n) << 22, refclk * clock.m1); | |
948 | ||
949 | if (m2 > INT_MAX/clock.m1) | |
950 | continue; | |
951 | ||
952 | clock.m2 = m2; | |
953 | ||
954 | chv_clock(refclk, &clock); | |
955 | ||
956 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
957 | continue; | |
958 | ||
9ca3ba01 ID |
959 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
960 | best_error_ppm, &error_ppm)) | |
961 | continue; | |
962 | ||
963 | *best_clock = clock; | |
964 | best_error_ppm = error_ppm; | |
965 | found = true; | |
ef9348c8 CML |
966 | } |
967 | } | |
968 | ||
969 | return found; | |
970 | } | |
971 | ||
5ab7b0b7 ID |
972 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
973 | intel_clock_t *best_clock) | |
974 | { | |
975 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
976 | ||
977 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
978 | target_clock, refclk, NULL, best_clock); | |
979 | } | |
980 | ||
20ddf665 VS |
981 | bool intel_crtc_active(struct drm_crtc *crtc) |
982 | { | |
983 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
984 | ||
985 | /* Be paranoid as we can arrive here with only partial | |
986 | * state retrieved from the hardware during setup. | |
987 | * | |
241bfc38 | 988 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
989 | * as Haswell has gained clock readout/fastboot support. |
990 | * | |
66e514c1 | 991 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 992 | * properly reconstruct framebuffers. |
c3d1f436 MR |
993 | * |
994 | * FIXME: The intel_crtc->active here should be switched to | |
995 | * crtc->state->active once we have proper CRTC states wired up | |
996 | * for atomic. | |
20ddf665 | 997 | */ |
c3d1f436 | 998 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 999 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1000 | } |
1001 | ||
a5c961d1 PZ |
1002 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1003 | enum pipe pipe) | |
1004 | { | |
1005 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1006 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1007 | ||
6e3c9717 | 1008 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1009 | } |
1010 | ||
fbf49ea2 VS |
1011 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1012 | { | |
1013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1014 | u32 reg = PIPEDSL(pipe); | |
1015 | u32 line1, line2; | |
1016 | u32 line_mask; | |
1017 | ||
1018 | if (IS_GEN2(dev)) | |
1019 | line_mask = DSL_LINEMASK_GEN2; | |
1020 | else | |
1021 | line_mask = DSL_LINEMASK_GEN3; | |
1022 | ||
1023 | line1 = I915_READ(reg) & line_mask; | |
1024 | mdelay(5); | |
1025 | line2 = I915_READ(reg) & line_mask; | |
1026 | ||
1027 | return line1 == line2; | |
1028 | } | |
1029 | ||
ab7ad7f6 KP |
1030 | /* |
1031 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1032 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1033 | * |
1034 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1035 | * spinning on the vblank interrupt status bit, since we won't actually | |
1036 | * see an interrupt when the pipe is disabled. | |
1037 | * | |
ab7ad7f6 KP |
1038 | * On Gen4 and above: |
1039 | * wait for the pipe register state bit to turn off | |
1040 | * | |
1041 | * Otherwise: | |
1042 | * wait for the display line value to settle (it usually | |
1043 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1044 | * |
9d0498a2 | 1045 | */ |
575f7ab7 | 1046 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1047 | { |
575f7ab7 | 1048 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1049 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1050 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1051 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1052 | |
1053 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1054 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1055 | |
1056 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1057 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1058 | 100)) | |
284637d9 | 1059 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1060 | } else { |
ab7ad7f6 | 1061 | /* Wait for the display line to settle */ |
fbf49ea2 | 1062 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1063 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1064 | } |
79e53945 JB |
1065 | } |
1066 | ||
b0ea7d37 DL |
1067 | /* |
1068 | * ibx_digital_port_connected - is the specified port connected? | |
1069 | * @dev_priv: i915 private structure | |
1070 | * @port: the port to test | |
1071 | * | |
1072 | * Returns true if @port is connected, false otherwise. | |
1073 | */ | |
1074 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1075 | struct intel_digital_port *port) | |
1076 | { | |
1077 | u32 bit; | |
1078 | ||
c36346e3 | 1079 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1080 | switch (port->port) { |
c36346e3 DL |
1081 | case PORT_B: |
1082 | bit = SDE_PORTB_HOTPLUG; | |
1083 | break; | |
1084 | case PORT_C: | |
1085 | bit = SDE_PORTC_HOTPLUG; | |
1086 | break; | |
1087 | case PORT_D: | |
1088 | bit = SDE_PORTD_HOTPLUG; | |
1089 | break; | |
1090 | default: | |
1091 | return true; | |
1092 | } | |
1093 | } else { | |
eba905b2 | 1094 | switch (port->port) { |
c36346e3 DL |
1095 | case PORT_B: |
1096 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1097 | break; | |
1098 | case PORT_C: | |
1099 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1100 | break; | |
1101 | case PORT_D: | |
1102 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1103 | break; | |
1104 | default: | |
1105 | return true; | |
1106 | } | |
b0ea7d37 DL |
1107 | } |
1108 | ||
1109 | return I915_READ(SDEISR) & bit; | |
1110 | } | |
1111 | ||
b24e7179 JB |
1112 | static const char *state_string(bool enabled) |
1113 | { | |
1114 | return enabled ? "on" : "off"; | |
1115 | } | |
1116 | ||
1117 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1118 | void assert_pll(struct drm_i915_private *dev_priv, |
1119 | enum pipe pipe, bool state) | |
b24e7179 JB |
1120 | { |
1121 | int reg; | |
1122 | u32 val; | |
1123 | bool cur_state; | |
1124 | ||
1125 | reg = DPLL(pipe); | |
1126 | val = I915_READ(reg); | |
1127 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1128 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1129 | "PLL state assertion failure (expected %s, current %s)\n", |
1130 | state_string(state), state_string(cur_state)); | |
1131 | } | |
b24e7179 | 1132 | |
23538ef1 JN |
1133 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1134 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1135 | { | |
1136 | u32 val; | |
1137 | bool cur_state; | |
1138 | ||
1139 | mutex_lock(&dev_priv->dpio_lock); | |
1140 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1141 | mutex_unlock(&dev_priv->dpio_lock); | |
1142 | ||
1143 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1144 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1145 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1146 | state_string(state), state_string(cur_state)); | |
1147 | } | |
1148 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1149 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1150 | ||
55607e8a | 1151 | struct intel_shared_dpll * |
e2b78267 DV |
1152 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1153 | { | |
1154 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1155 | ||
6e3c9717 | 1156 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1157 | return NULL; |
1158 | ||
6e3c9717 | 1159 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1160 | } |
1161 | ||
040484af | 1162 | /* For ILK+ */ |
55607e8a DV |
1163 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1164 | struct intel_shared_dpll *pll, | |
1165 | bool state) | |
040484af | 1166 | { |
040484af | 1167 | bool cur_state; |
5358901f | 1168 | struct intel_dpll_hw_state hw_state; |
040484af | 1169 | |
92b27b08 | 1170 | if (WARN (!pll, |
46edb027 | 1171 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1172 | return; |
ee7b9f93 | 1173 | |
5358901f | 1174 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1175 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1176 | "%s assertion failure (expected %s, current %s)\n", |
1177 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1178 | } |
040484af JB |
1179 | |
1180 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1181 | enum pipe pipe, bool state) | |
1182 | { | |
1183 | int reg; | |
1184 | u32 val; | |
1185 | bool cur_state; | |
ad80a810 PZ |
1186 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1187 | pipe); | |
040484af | 1188 | |
affa9354 PZ |
1189 | if (HAS_DDI(dev_priv->dev)) { |
1190 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1191 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1192 | val = I915_READ(reg); |
ad80a810 | 1193 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1194 | } else { |
1195 | reg = FDI_TX_CTL(pipe); | |
1196 | val = I915_READ(reg); | |
1197 | cur_state = !!(val & FDI_TX_ENABLE); | |
1198 | } | |
e2c719b7 | 1199 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1200 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1201 | state_string(state), state_string(cur_state)); | |
1202 | } | |
1203 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1204 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1205 | ||
1206 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1207 | enum pipe pipe, bool state) | |
1208 | { | |
1209 | int reg; | |
1210 | u32 val; | |
1211 | bool cur_state; | |
1212 | ||
d63fa0dc PZ |
1213 | reg = FDI_RX_CTL(pipe); |
1214 | val = I915_READ(reg); | |
1215 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1216 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1217 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1218 | state_string(state), state_string(cur_state)); | |
1219 | } | |
1220 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1221 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1222 | ||
1223 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1224 | enum pipe pipe) | |
1225 | { | |
1226 | int reg; | |
1227 | u32 val; | |
1228 | ||
1229 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1230 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1231 | return; |
1232 | ||
bf507ef7 | 1233 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1234 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1235 | return; |
1236 | ||
040484af JB |
1237 | reg = FDI_TX_CTL(pipe); |
1238 | val = I915_READ(reg); | |
e2c719b7 | 1239 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1240 | } |
1241 | ||
55607e8a DV |
1242 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1243 | enum pipe pipe, bool state) | |
040484af JB |
1244 | { |
1245 | int reg; | |
1246 | u32 val; | |
55607e8a | 1247 | bool cur_state; |
040484af JB |
1248 | |
1249 | reg = FDI_RX_CTL(pipe); | |
1250 | val = I915_READ(reg); | |
55607e8a | 1251 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1252 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1253 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1254 | state_string(state), state_string(cur_state)); | |
040484af JB |
1255 | } |
1256 | ||
b680c37a DV |
1257 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1258 | enum pipe pipe) | |
ea0760cf | 1259 | { |
bedd4dba JN |
1260 | struct drm_device *dev = dev_priv->dev; |
1261 | int pp_reg; | |
ea0760cf JB |
1262 | u32 val; |
1263 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1264 | bool locked = true; |
ea0760cf | 1265 | |
bedd4dba JN |
1266 | if (WARN_ON(HAS_DDI(dev))) |
1267 | return; | |
1268 | ||
1269 | if (HAS_PCH_SPLIT(dev)) { | |
1270 | u32 port_sel; | |
1271 | ||
ea0760cf | 1272 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1273 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1274 | ||
1275 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1276 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1277 | panel_pipe = PIPE_B; | |
1278 | /* XXX: else fix for eDP */ | |
1279 | } else if (IS_VALLEYVIEW(dev)) { | |
1280 | /* presumably write lock depends on pipe, not port select */ | |
1281 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1282 | panel_pipe = pipe; | |
ea0760cf JB |
1283 | } else { |
1284 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1285 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1286 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1287 | } |
1288 | ||
1289 | val = I915_READ(pp_reg); | |
1290 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1291 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1292 | locked = false; |
1293 | ||
e2c719b7 | 1294 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1295 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1296 | pipe_name(pipe)); |
ea0760cf JB |
1297 | } |
1298 | ||
93ce0ba6 JN |
1299 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1300 | enum pipe pipe, bool state) | |
1301 | { | |
1302 | struct drm_device *dev = dev_priv->dev; | |
1303 | bool cur_state; | |
1304 | ||
d9d82081 | 1305 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1306 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1307 | else |
5efb3e28 | 1308 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1309 | |
e2c719b7 | 1310 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1311 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1312 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1313 | } | |
1314 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1315 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1316 | ||
b840d907 JB |
1317 | void assert_pipe(struct drm_i915_private *dev_priv, |
1318 | enum pipe pipe, bool state) | |
b24e7179 JB |
1319 | { |
1320 | int reg; | |
1321 | u32 val; | |
63d7bbe9 | 1322 | bool cur_state; |
702e7a56 PZ |
1323 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1324 | pipe); | |
b24e7179 | 1325 | |
b6b5d049 VS |
1326 | /* if we need the pipe quirk it must be always on */ |
1327 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1328 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1329 | state = true; |
1330 | ||
f458ebbc | 1331 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1332 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1333 | cur_state = false; |
1334 | } else { | |
1335 | reg = PIPECONF(cpu_transcoder); | |
1336 | val = I915_READ(reg); | |
1337 | cur_state = !!(val & PIPECONF_ENABLE); | |
1338 | } | |
1339 | ||
e2c719b7 | 1340 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1341 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1342 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1343 | } |
1344 | ||
931872fc CW |
1345 | static void assert_plane(struct drm_i915_private *dev_priv, |
1346 | enum plane plane, bool state) | |
b24e7179 JB |
1347 | { |
1348 | int reg; | |
1349 | u32 val; | |
931872fc | 1350 | bool cur_state; |
b24e7179 JB |
1351 | |
1352 | reg = DSPCNTR(plane); | |
1353 | val = I915_READ(reg); | |
931872fc | 1354 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1355 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1356 | "plane %c assertion failure (expected %s, current %s)\n", |
1357 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1358 | } |
1359 | ||
931872fc CW |
1360 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1361 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1362 | ||
b24e7179 JB |
1363 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1364 | enum pipe pipe) | |
1365 | { | |
653e1026 | 1366 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1367 | int reg, i; |
1368 | u32 val; | |
1369 | int cur_pipe; | |
1370 | ||
653e1026 VS |
1371 | /* Primary planes are fixed to pipes on gen4+ */ |
1372 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1373 | reg = DSPCNTR(pipe); |
1374 | val = I915_READ(reg); | |
e2c719b7 | 1375 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1376 | "plane %c assertion failure, should be disabled but not\n", |
1377 | plane_name(pipe)); | |
19ec1358 | 1378 | return; |
28c05794 | 1379 | } |
19ec1358 | 1380 | |
b24e7179 | 1381 | /* Need to check both planes against the pipe */ |
055e393f | 1382 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1383 | reg = DSPCNTR(i); |
1384 | val = I915_READ(reg); | |
1385 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1386 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1387 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1388 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1389 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1390 | } |
1391 | } | |
1392 | ||
19332d7a JB |
1393 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1394 | enum pipe pipe) | |
1395 | { | |
20674eef | 1396 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1397 | int reg, sprite; |
19332d7a JB |
1398 | u32 val; |
1399 | ||
7feb8b88 | 1400 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1401 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1402 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1403 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1404 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1405 | sprite, pipe_name(pipe)); | |
1406 | } | |
1407 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1408 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1409 | reg = SPCNTR(pipe, sprite); |
20674eef | 1410 | val = I915_READ(reg); |
e2c719b7 | 1411 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1412 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1413 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1414 | } |
1415 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1416 | reg = SPRCTL(pipe); | |
19332d7a | 1417 | val = I915_READ(reg); |
e2c719b7 | 1418 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1419 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1420 | plane_name(pipe), pipe_name(pipe)); |
1421 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1422 | reg = DVSCNTR(pipe); | |
19332d7a | 1423 | val = I915_READ(reg); |
e2c719b7 | 1424 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1425 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1426 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1427 | } |
1428 | } | |
1429 | ||
08c71e5e VS |
1430 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1431 | { | |
e2c719b7 | 1432 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1433 | drm_crtc_vblank_put(crtc); |
1434 | } | |
1435 | ||
89eff4be | 1436 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1437 | { |
1438 | u32 val; | |
1439 | bool enabled; | |
1440 | ||
e2c719b7 | 1441 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1442 | |
92f2584a JB |
1443 | val = I915_READ(PCH_DREF_CONTROL); |
1444 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1445 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1446 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1447 | } |
1448 | ||
ab9412ba DV |
1449 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1450 | enum pipe pipe) | |
92f2584a JB |
1451 | { |
1452 | int reg; | |
1453 | u32 val; | |
1454 | bool enabled; | |
1455 | ||
ab9412ba | 1456 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1457 | val = I915_READ(reg); |
1458 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1459 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1460 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1461 | pipe_name(pipe)); | |
92f2584a JB |
1462 | } |
1463 | ||
4e634389 KP |
1464 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1465 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1466 | { |
1467 | if ((val & DP_PORT_EN) == 0) | |
1468 | return false; | |
1469 | ||
1470 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1471 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1472 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1473 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1474 | return false; | |
44f37d1f CML |
1475 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1476 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1477 | return false; | |
f0575e92 KP |
1478 | } else { |
1479 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1480 | return false; | |
1481 | } | |
1482 | return true; | |
1483 | } | |
1484 | ||
1519b995 KP |
1485 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1486 | enum pipe pipe, u32 val) | |
1487 | { | |
dc0fa718 | 1488 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1489 | return false; |
1490 | ||
1491 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1492 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1493 | return false; |
44f37d1f CML |
1494 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1495 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1496 | return false; | |
1519b995 | 1497 | } else { |
dc0fa718 | 1498 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1499 | return false; |
1500 | } | |
1501 | return true; | |
1502 | } | |
1503 | ||
1504 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1505 | enum pipe pipe, u32 val) | |
1506 | { | |
1507 | if ((val & LVDS_PORT_EN) == 0) | |
1508 | return false; | |
1509 | ||
1510 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1511 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1512 | return false; | |
1513 | } else { | |
1514 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1515 | return false; | |
1516 | } | |
1517 | return true; | |
1518 | } | |
1519 | ||
1520 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1521 | enum pipe pipe, u32 val) | |
1522 | { | |
1523 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1524 | return false; | |
1525 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1526 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1527 | return false; | |
1528 | } else { | |
1529 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1530 | return false; | |
1531 | } | |
1532 | return true; | |
1533 | } | |
1534 | ||
291906f1 | 1535 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1536 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1537 | { |
47a05eca | 1538 | u32 val = I915_READ(reg); |
e2c719b7 | 1539 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1540 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1541 | reg, pipe_name(pipe)); |
de9a35ab | 1542 | |
e2c719b7 | 1543 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1544 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1545 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1546 | } |
1547 | ||
1548 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1549 | enum pipe pipe, int reg) | |
1550 | { | |
47a05eca | 1551 | u32 val = I915_READ(reg); |
e2c719b7 | 1552 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1553 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1554 | reg, pipe_name(pipe)); |
de9a35ab | 1555 | |
e2c719b7 | 1556 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1557 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1558 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1559 | } |
1560 | ||
1561 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1562 | enum pipe pipe) | |
1563 | { | |
1564 | int reg; | |
1565 | u32 val; | |
291906f1 | 1566 | |
f0575e92 KP |
1567 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1568 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1569 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1570 | |
1571 | reg = PCH_ADPA; | |
1572 | val = I915_READ(reg); | |
e2c719b7 | 1573 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1574 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1575 | pipe_name(pipe)); |
291906f1 JB |
1576 | |
1577 | reg = PCH_LVDS; | |
1578 | val = I915_READ(reg); | |
e2c719b7 | 1579 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1580 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1581 | pipe_name(pipe)); |
291906f1 | 1582 | |
e2debe91 PZ |
1583 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1584 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1585 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1586 | } |
1587 | ||
40e9cf64 JB |
1588 | static void intel_init_dpio(struct drm_device *dev) |
1589 | { | |
1590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1591 | ||
1592 | if (!IS_VALLEYVIEW(dev)) | |
1593 | return; | |
1594 | ||
a09caddd CML |
1595 | /* |
1596 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1597 | * CHV x1 PHY (DP/HDMI D) | |
1598 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1599 | */ | |
1600 | if (IS_CHERRYVIEW(dev)) { | |
1601 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1602 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1603 | } else { | |
1604 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1605 | } | |
5382f5f3 JB |
1606 | } |
1607 | ||
d288f65f | 1608 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1609 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1610 | { |
426115cf DV |
1611 | struct drm_device *dev = crtc->base.dev; |
1612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1613 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1614 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1615 | |
426115cf | 1616 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1617 | |
1618 | /* No really, not for ILK+ */ | |
1619 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1620 | ||
1621 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1622 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1623 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1624 | |
426115cf DV |
1625 | I915_WRITE(reg, dpll); |
1626 | POSTING_READ(reg); | |
1627 | udelay(150); | |
1628 | ||
1629 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1630 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1631 | ||
d288f65f | 1632 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1633 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1634 | |
1635 | /* We do this three times for luck */ | |
426115cf | 1636 | I915_WRITE(reg, dpll); |
87442f73 DV |
1637 | POSTING_READ(reg); |
1638 | udelay(150); /* wait for warmup */ | |
426115cf | 1639 | I915_WRITE(reg, dpll); |
87442f73 DV |
1640 | POSTING_READ(reg); |
1641 | udelay(150); /* wait for warmup */ | |
426115cf | 1642 | I915_WRITE(reg, dpll); |
87442f73 DV |
1643 | POSTING_READ(reg); |
1644 | udelay(150); /* wait for warmup */ | |
1645 | } | |
1646 | ||
d288f65f | 1647 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1648 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1649 | { |
1650 | struct drm_device *dev = crtc->base.dev; | |
1651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1652 | int pipe = crtc->pipe; | |
1653 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1654 | u32 tmp; |
1655 | ||
1656 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1657 | ||
1658 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1659 | ||
1660 | mutex_lock(&dev_priv->dpio_lock); | |
1661 | ||
1662 | /* Enable back the 10bit clock to display controller */ | |
1663 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1664 | tmp |= DPIO_DCLKP_EN; | |
1665 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1666 | ||
1667 | /* | |
1668 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1669 | */ | |
1670 | udelay(1); | |
1671 | ||
1672 | /* Enable PLL */ | |
d288f65f | 1673 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1674 | |
1675 | /* Check PLL is locked */ | |
a11b0703 | 1676 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1677 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1678 | ||
a11b0703 | 1679 | /* not sure when this should be written */ |
d288f65f | 1680 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1681 | POSTING_READ(DPLL_MD(pipe)); |
1682 | ||
9d556c99 CML |
1683 | mutex_unlock(&dev_priv->dpio_lock); |
1684 | } | |
1685 | ||
1c4e0274 VS |
1686 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1687 | { | |
1688 | struct intel_crtc *crtc; | |
1689 | int count = 0; | |
1690 | ||
1691 | for_each_intel_crtc(dev, crtc) | |
1692 | count += crtc->active && | |
409ee761 | 1693 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1694 | |
1695 | return count; | |
1696 | } | |
1697 | ||
66e3d5c0 | 1698 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1699 | { |
66e3d5c0 DV |
1700 | struct drm_device *dev = crtc->base.dev; |
1701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1702 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1703 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1704 | |
66e3d5c0 | 1705 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1706 | |
63d7bbe9 | 1707 | /* No really, not for ILK+ */ |
3d13ef2e | 1708 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1709 | |
1710 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1711 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1712 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1713 | |
1c4e0274 VS |
1714 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1715 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1716 | /* | |
1717 | * It appears to be important that we don't enable this | |
1718 | * for the current pipe before otherwise configuring the | |
1719 | * PLL. No idea how this should be handled if multiple | |
1720 | * DVO outputs are enabled simultaneosly. | |
1721 | */ | |
1722 | dpll |= DPLL_DVO_2X_MODE; | |
1723 | I915_WRITE(DPLL(!crtc->pipe), | |
1724 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1725 | } | |
66e3d5c0 DV |
1726 | |
1727 | /* Wait for the clocks to stabilize. */ | |
1728 | POSTING_READ(reg); | |
1729 | udelay(150); | |
1730 | ||
1731 | if (INTEL_INFO(dev)->gen >= 4) { | |
1732 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1733 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1734 | } else { |
1735 | /* The pixel multiplier can only be updated once the | |
1736 | * DPLL is enabled and the clocks are stable. | |
1737 | * | |
1738 | * So write it again. | |
1739 | */ | |
1740 | I915_WRITE(reg, dpll); | |
1741 | } | |
63d7bbe9 JB |
1742 | |
1743 | /* We do this three times for luck */ | |
66e3d5c0 | 1744 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1745 | POSTING_READ(reg); |
1746 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1747 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1748 | POSTING_READ(reg); |
1749 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1750 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1751 | POSTING_READ(reg); |
1752 | udelay(150); /* wait for warmup */ | |
1753 | } | |
1754 | ||
1755 | /** | |
50b44a44 | 1756 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1757 | * @dev_priv: i915 private structure |
1758 | * @pipe: pipe PLL to disable | |
1759 | * | |
1760 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1761 | * | |
1762 | * Note! This is for pre-ILK only. | |
1763 | */ | |
1c4e0274 | 1764 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1765 | { |
1c4e0274 VS |
1766 | struct drm_device *dev = crtc->base.dev; |
1767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1768 | enum pipe pipe = crtc->pipe; | |
1769 | ||
1770 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1771 | if (IS_I830(dev) && | |
409ee761 | 1772 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1773 | intel_num_dvo_pipes(dev) == 1) { |
1774 | I915_WRITE(DPLL(PIPE_B), | |
1775 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1776 | I915_WRITE(DPLL(PIPE_A), | |
1777 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1778 | } | |
1779 | ||
b6b5d049 VS |
1780 | /* Don't disable pipe or pipe PLLs if needed */ |
1781 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1782 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1783 | return; |
1784 | ||
1785 | /* Make sure the pipe isn't still relying on us */ | |
1786 | assert_pipe_disabled(dev_priv, pipe); | |
1787 | ||
50b44a44 DV |
1788 | I915_WRITE(DPLL(pipe), 0); |
1789 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1790 | } |
1791 | ||
f6071166 JB |
1792 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1793 | { | |
1794 | u32 val = 0; | |
1795 | ||
1796 | /* Make sure the pipe isn't still relying on us */ | |
1797 | assert_pipe_disabled(dev_priv, pipe); | |
1798 | ||
e5cbfbfb ID |
1799 | /* |
1800 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1801 | * The latter is needed for VGA hotplug / manual detection. | |
1802 | */ | |
f6071166 | 1803 | if (pipe == PIPE_B) |
e5cbfbfb | 1804 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1805 | I915_WRITE(DPLL(pipe), val); |
1806 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1807 | |
1808 | } | |
1809 | ||
1810 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1811 | { | |
d752048d | 1812 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1813 | u32 val; |
1814 | ||
a11b0703 VS |
1815 | /* Make sure the pipe isn't still relying on us */ |
1816 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1817 | |
a11b0703 | 1818 | /* Set PLL en = 0 */ |
d17ec4ce | 1819 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1820 | if (pipe != PIPE_A) |
1821 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1822 | I915_WRITE(DPLL(pipe), val); | |
1823 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1824 | |
1825 | mutex_lock(&dev_priv->dpio_lock); | |
1826 | ||
1827 | /* Disable 10bit clock to display controller */ | |
1828 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1829 | val &= ~DPIO_DCLKP_EN; | |
1830 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1831 | ||
61407f6d VS |
1832 | /* disable left/right clock distribution */ |
1833 | if (pipe != PIPE_B) { | |
1834 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1835 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1836 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1837 | } else { | |
1838 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1839 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1840 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1841 | } | |
1842 | ||
d752048d | 1843 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1844 | } |
1845 | ||
e4607fcf CML |
1846 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1847 | struct intel_digital_port *dport) | |
89b667f8 JB |
1848 | { |
1849 | u32 port_mask; | |
00fc31b7 | 1850 | int dpll_reg; |
89b667f8 | 1851 | |
e4607fcf CML |
1852 | switch (dport->port) { |
1853 | case PORT_B: | |
89b667f8 | 1854 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1855 | dpll_reg = DPLL(0); |
e4607fcf CML |
1856 | break; |
1857 | case PORT_C: | |
89b667f8 | 1858 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1859 | dpll_reg = DPLL(0); |
1860 | break; | |
1861 | case PORT_D: | |
1862 | port_mask = DPLL_PORTD_READY_MASK; | |
1863 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1864 | break; |
1865 | default: | |
1866 | BUG(); | |
1867 | } | |
89b667f8 | 1868 | |
00fc31b7 | 1869 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1870 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1871 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1872 | } |
1873 | ||
b14b1055 DV |
1874 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1875 | { | |
1876 | struct drm_device *dev = crtc->base.dev; | |
1877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1878 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1879 | ||
be19f0ff CW |
1880 | if (WARN_ON(pll == NULL)) |
1881 | return; | |
1882 | ||
3e369b76 | 1883 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1884 | if (pll->active == 0) { |
1885 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1886 | WARN_ON(pll->on); | |
1887 | assert_shared_dpll_disabled(dev_priv, pll); | |
1888 | ||
1889 | pll->mode_set(dev_priv, pll); | |
1890 | } | |
1891 | } | |
1892 | ||
92f2584a | 1893 | /** |
85b3894f | 1894 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1895 | * @dev_priv: i915 private structure |
1896 | * @pipe: pipe PLL to enable | |
1897 | * | |
1898 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1899 | * drives the transcoder clock. | |
1900 | */ | |
85b3894f | 1901 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1902 | { |
3d13ef2e DL |
1903 | struct drm_device *dev = crtc->base.dev; |
1904 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1905 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1906 | |
87a875bb | 1907 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1908 | return; |
1909 | ||
3e369b76 | 1910 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1911 | return; |
ee7b9f93 | 1912 | |
74dd6928 | 1913 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1914 | pll->name, pll->active, pll->on, |
e2b78267 | 1915 | crtc->base.base.id); |
92f2584a | 1916 | |
cdbd2316 DV |
1917 | if (pll->active++) { |
1918 | WARN_ON(!pll->on); | |
e9d6944e | 1919 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1920 | return; |
1921 | } | |
f4a091c7 | 1922 | WARN_ON(pll->on); |
ee7b9f93 | 1923 | |
bd2bb1b9 PZ |
1924 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1925 | ||
46edb027 | 1926 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1927 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1928 | pll->on = true; |
92f2584a JB |
1929 | } |
1930 | ||
f6daaec2 | 1931 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1932 | { |
3d13ef2e DL |
1933 | struct drm_device *dev = crtc->base.dev; |
1934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1935 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1936 | |
92f2584a | 1937 | /* PCH only available on ILK+ */ |
3d13ef2e | 1938 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1939 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1940 | return; |
92f2584a | 1941 | |
3e369b76 | 1942 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1943 | return; |
7a419866 | 1944 | |
46edb027 DV |
1945 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1946 | pll->name, pll->active, pll->on, | |
e2b78267 | 1947 | crtc->base.base.id); |
7a419866 | 1948 | |
48da64a8 | 1949 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1950 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1951 | return; |
1952 | } | |
1953 | ||
e9d6944e | 1954 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1955 | WARN_ON(!pll->on); |
cdbd2316 | 1956 | if (--pll->active) |
7a419866 | 1957 | return; |
ee7b9f93 | 1958 | |
46edb027 | 1959 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1960 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1961 | pll->on = false; |
bd2bb1b9 PZ |
1962 | |
1963 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1964 | } |
1965 | ||
b8a4f404 PZ |
1966 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1967 | enum pipe pipe) | |
040484af | 1968 | { |
23670b32 | 1969 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1970 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1971 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1972 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1973 | |
1974 | /* PCH only available on ILK+ */ | |
55522f37 | 1975 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1976 | |
1977 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1978 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1979 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1980 | |
1981 | /* FDI must be feeding us bits for PCH ports */ | |
1982 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1983 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1984 | ||
23670b32 DV |
1985 | if (HAS_PCH_CPT(dev)) { |
1986 | /* Workaround: Set the timing override bit before enabling the | |
1987 | * pch transcoder. */ | |
1988 | reg = TRANS_CHICKEN2(pipe); | |
1989 | val = I915_READ(reg); | |
1990 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1991 | I915_WRITE(reg, val); | |
59c859d6 | 1992 | } |
23670b32 | 1993 | |
ab9412ba | 1994 | reg = PCH_TRANSCONF(pipe); |
040484af | 1995 | val = I915_READ(reg); |
5f7f726d | 1996 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1997 | |
1998 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1999 | /* | |
2000 | * make the BPC in transcoder be consistent with | |
2001 | * that in pipeconf reg. | |
2002 | */ | |
dfd07d72 DV |
2003 | val &= ~PIPECONF_BPC_MASK; |
2004 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2005 | } |
5f7f726d PZ |
2006 | |
2007 | val &= ~TRANS_INTERLACE_MASK; | |
2008 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2009 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2010 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2011 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2012 | else | |
2013 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2014 | else |
2015 | val |= TRANS_PROGRESSIVE; | |
2016 | ||
040484af JB |
2017 | I915_WRITE(reg, val | TRANS_ENABLE); |
2018 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2019 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2020 | } |
2021 | ||
8fb033d7 | 2022 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2023 | enum transcoder cpu_transcoder) |
040484af | 2024 | { |
8fb033d7 | 2025 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2026 | |
2027 | /* PCH only available on ILK+ */ | |
55522f37 | 2028 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2029 | |
8fb033d7 | 2030 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2031 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2032 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2033 | |
223a6fdf PZ |
2034 | /* Workaround: set timing override bit. */ |
2035 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2036 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2037 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2038 | ||
25f3ef11 | 2039 | val = TRANS_ENABLE; |
937bb610 | 2040 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2041 | |
9a76b1c6 PZ |
2042 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2043 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2044 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2045 | else |
2046 | val |= TRANS_PROGRESSIVE; | |
2047 | ||
ab9412ba DV |
2048 | I915_WRITE(LPT_TRANSCONF, val); |
2049 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2050 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2051 | } |
2052 | ||
b8a4f404 PZ |
2053 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2054 | enum pipe pipe) | |
040484af | 2055 | { |
23670b32 DV |
2056 | struct drm_device *dev = dev_priv->dev; |
2057 | uint32_t reg, val; | |
040484af JB |
2058 | |
2059 | /* FDI relies on the transcoder */ | |
2060 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2061 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2062 | ||
291906f1 JB |
2063 | /* Ports must be off as well */ |
2064 | assert_pch_ports_disabled(dev_priv, pipe); | |
2065 | ||
ab9412ba | 2066 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2067 | val = I915_READ(reg); |
2068 | val &= ~TRANS_ENABLE; | |
2069 | I915_WRITE(reg, val); | |
2070 | /* wait for PCH transcoder off, transcoder state */ | |
2071 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2072 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2073 | |
2074 | if (!HAS_PCH_IBX(dev)) { | |
2075 | /* Workaround: Clear the timing override chicken bit again. */ | |
2076 | reg = TRANS_CHICKEN2(pipe); | |
2077 | val = I915_READ(reg); | |
2078 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2079 | I915_WRITE(reg, val); | |
2080 | } | |
040484af JB |
2081 | } |
2082 | ||
ab4d966c | 2083 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2084 | { |
8fb033d7 PZ |
2085 | u32 val; |
2086 | ||
ab9412ba | 2087 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2088 | val &= ~TRANS_ENABLE; |
ab9412ba | 2089 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2090 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2091 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2092 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2093 | |
2094 | /* Workaround: clear timing override bit. */ | |
2095 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2096 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2097 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2098 | } |
2099 | ||
b24e7179 | 2100 | /** |
309cfea8 | 2101 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2102 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2103 | * |
0372264a | 2104 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2105 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2106 | */ |
e1fdc473 | 2107 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2108 | { |
0372264a PZ |
2109 | struct drm_device *dev = crtc->base.dev; |
2110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2111 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2112 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2113 | pipe); | |
1a240d4d | 2114 | enum pipe pch_transcoder; |
b24e7179 JB |
2115 | int reg; |
2116 | u32 val; | |
2117 | ||
58c6eaa2 | 2118 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2119 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2120 | assert_sprites_disabled(dev_priv, pipe); |
2121 | ||
681e5811 | 2122 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2123 | pch_transcoder = TRANSCODER_A; |
2124 | else | |
2125 | pch_transcoder = pipe; | |
2126 | ||
b24e7179 JB |
2127 | /* |
2128 | * A pipe without a PLL won't actually be able to drive bits from | |
2129 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2130 | * need the check. | |
2131 | */ | |
50360403 | 2132 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
409ee761 | 2133 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2134 | assert_dsi_pll_enabled(dev_priv); |
2135 | else | |
2136 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2137 | else { |
6e3c9717 | 2138 | if (crtc->config->has_pch_encoder) { |
040484af | 2139 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2140 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2141 | assert_fdi_tx_pll_enabled(dev_priv, |
2142 | (enum pipe) cpu_transcoder); | |
040484af JB |
2143 | } |
2144 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2145 | } | |
b24e7179 | 2146 | |
702e7a56 | 2147 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2148 | val = I915_READ(reg); |
7ad25d48 | 2149 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2150 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2151 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2152 | return; |
7ad25d48 | 2153 | } |
00d70b15 CW |
2154 | |
2155 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2156 | POSTING_READ(reg); |
b24e7179 JB |
2157 | } |
2158 | ||
2159 | /** | |
309cfea8 | 2160 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2161 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2162 | * |
575f7ab7 VS |
2163 | * Disable the pipe of @crtc, making sure that various hardware |
2164 | * specific requirements are met, if applicable, e.g. plane | |
2165 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2166 | * |
2167 | * Will wait until the pipe has shut down before returning. | |
2168 | */ | |
575f7ab7 | 2169 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2170 | { |
575f7ab7 | 2171 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2172 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2173 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2174 | int reg; |
2175 | u32 val; | |
2176 | ||
2177 | /* | |
2178 | * Make sure planes won't keep trying to pump pixels to us, | |
2179 | * or we might hang the display. | |
2180 | */ | |
2181 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2182 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2183 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2184 | |
702e7a56 | 2185 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2186 | val = I915_READ(reg); |
00d70b15 CW |
2187 | if ((val & PIPECONF_ENABLE) == 0) |
2188 | return; | |
2189 | ||
67adc644 VS |
2190 | /* |
2191 | * Double wide has implications for planes | |
2192 | * so best keep it disabled when not needed. | |
2193 | */ | |
6e3c9717 | 2194 | if (crtc->config->double_wide) |
67adc644 VS |
2195 | val &= ~PIPECONF_DOUBLE_WIDE; |
2196 | ||
2197 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2198 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2199 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2200 | val &= ~PIPECONF_ENABLE; |
2201 | ||
2202 | I915_WRITE(reg, val); | |
2203 | if ((val & PIPECONF_ENABLE) == 0) | |
2204 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2205 | } |
2206 | ||
d74362c9 KP |
2207 | /* |
2208 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2209 | * trigger in order to latch. The display address reg provides this. | |
2210 | */ | |
1dba99f4 VS |
2211 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2212 | enum plane plane) | |
d74362c9 | 2213 | { |
3d13ef2e DL |
2214 | struct drm_device *dev = dev_priv->dev; |
2215 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2216 | |
2217 | I915_WRITE(reg, I915_READ(reg)); | |
2218 | POSTING_READ(reg); | |
d74362c9 KP |
2219 | } |
2220 | ||
b24e7179 | 2221 | /** |
262ca2b0 | 2222 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2223 | * @plane: plane to be enabled |
2224 | * @crtc: crtc for the plane | |
b24e7179 | 2225 | * |
fdd508a6 | 2226 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2227 | */ |
fdd508a6 VS |
2228 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2229 | struct drm_crtc *crtc) | |
b24e7179 | 2230 | { |
fdd508a6 VS |
2231 | struct drm_device *dev = plane->dev; |
2232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2234 | |
2235 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2236 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b70709a6 | 2237 | to_intel_plane_state(plane->state)->visible = true; |
939c2fe8 | 2238 | |
fdd508a6 VS |
2239 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2240 | crtc->x, crtc->y); | |
b24e7179 JB |
2241 | } |
2242 | ||
693db184 CW |
2243 | static bool need_vtd_wa(struct drm_device *dev) |
2244 | { | |
2245 | #ifdef CONFIG_INTEL_IOMMU | |
2246 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2247 | return true; | |
2248 | #endif | |
2249 | return false; | |
2250 | } | |
2251 | ||
50470bb0 | 2252 | unsigned int |
6761dd31 TU |
2253 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2254 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2255 | { |
6761dd31 TU |
2256 | unsigned int tile_height; |
2257 | uint32_t pixel_bytes; | |
a57ce0b2 | 2258 | |
b5d0e9bf DL |
2259 | switch (fb_format_modifier) { |
2260 | case DRM_FORMAT_MOD_NONE: | |
2261 | tile_height = 1; | |
2262 | break; | |
2263 | case I915_FORMAT_MOD_X_TILED: | |
2264 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2265 | break; | |
2266 | case I915_FORMAT_MOD_Y_TILED: | |
2267 | tile_height = 32; | |
2268 | break; | |
2269 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2270 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2271 | switch (pixel_bytes) { | |
b5d0e9bf | 2272 | default: |
6761dd31 | 2273 | case 1: |
b5d0e9bf DL |
2274 | tile_height = 64; |
2275 | break; | |
6761dd31 TU |
2276 | case 2: |
2277 | case 4: | |
b5d0e9bf DL |
2278 | tile_height = 32; |
2279 | break; | |
6761dd31 | 2280 | case 8: |
b5d0e9bf DL |
2281 | tile_height = 16; |
2282 | break; | |
6761dd31 | 2283 | case 16: |
b5d0e9bf DL |
2284 | WARN_ONCE(1, |
2285 | "128-bit pixels are not supported for display!"); | |
2286 | tile_height = 16; | |
2287 | break; | |
2288 | } | |
2289 | break; | |
2290 | default: | |
2291 | MISSING_CASE(fb_format_modifier); | |
2292 | tile_height = 1; | |
2293 | break; | |
2294 | } | |
091df6cb | 2295 | |
6761dd31 TU |
2296 | return tile_height; |
2297 | } | |
2298 | ||
2299 | unsigned int | |
2300 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2301 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2302 | { | |
2303 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2304 | fb_format_modifier)); | |
a57ce0b2 JB |
2305 | } |
2306 | ||
f64b98cd TU |
2307 | static int |
2308 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2309 | const struct drm_plane_state *plane_state) | |
2310 | { | |
50470bb0 | 2311 | struct intel_rotation_info *info = &view->rotation_info; |
50470bb0 | 2312 | |
f64b98cd TU |
2313 | *view = i915_ggtt_view_normal; |
2314 | ||
50470bb0 TU |
2315 | if (!plane_state) |
2316 | return 0; | |
2317 | ||
121920fa | 2318 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2319 | return 0; |
2320 | ||
9abc4648 | 2321 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2322 | |
2323 | info->height = fb->height; | |
2324 | info->pixel_format = fb->pixel_format; | |
2325 | info->pitch = fb->pitches[0]; | |
2326 | info->fb_modifier = fb->modifier[0]; | |
2327 | ||
f64b98cd TU |
2328 | return 0; |
2329 | } | |
2330 | ||
127bd2ac | 2331 | int |
850c4cdc TU |
2332 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2333 | struct drm_framebuffer *fb, | |
82bc3b2d | 2334 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2335 | struct intel_engine_cs *pipelined) |
6b95a207 | 2336 | { |
850c4cdc | 2337 | struct drm_device *dev = fb->dev; |
ce453d81 | 2338 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2339 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2340 | struct i915_ggtt_view view; |
6b95a207 KH |
2341 | u32 alignment; |
2342 | int ret; | |
2343 | ||
ebcdd39e MR |
2344 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2345 | ||
7b911adc TU |
2346 | switch (fb->modifier[0]) { |
2347 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2348 | if (INTEL_INFO(dev)->gen >= 9) |
2349 | alignment = 256 * 1024; | |
2350 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2351 | alignment = 128 * 1024; |
a6c45cf0 | 2352 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2353 | alignment = 4 * 1024; |
2354 | else | |
2355 | alignment = 64 * 1024; | |
6b95a207 | 2356 | break; |
7b911adc | 2357 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2358 | if (INTEL_INFO(dev)->gen >= 9) |
2359 | alignment = 256 * 1024; | |
2360 | else { | |
2361 | /* pin() will align the object as required by fence */ | |
2362 | alignment = 0; | |
2363 | } | |
6b95a207 | 2364 | break; |
7b911adc | 2365 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2366 | case I915_FORMAT_MOD_Yf_TILED: |
2367 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2368 | "Y tiling bo slipped through, driver bug!\n")) | |
2369 | return -EINVAL; | |
2370 | alignment = 1 * 1024 * 1024; | |
2371 | break; | |
6b95a207 | 2372 | default: |
7b911adc TU |
2373 | MISSING_CASE(fb->modifier[0]); |
2374 | return -EINVAL; | |
6b95a207 KH |
2375 | } |
2376 | ||
f64b98cd TU |
2377 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2378 | if (ret) | |
2379 | return ret; | |
2380 | ||
693db184 CW |
2381 | /* Note that the w/a also requires 64 PTE of padding following the |
2382 | * bo. We currently fill all unused PTE with the shadow page and so | |
2383 | * we should always have valid PTE following the scanout preventing | |
2384 | * the VT-d warning. | |
2385 | */ | |
2386 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2387 | alignment = 256 * 1024; | |
2388 | ||
d6dd6843 PZ |
2389 | /* |
2390 | * Global gtt pte registers are special registers which actually forward | |
2391 | * writes to a chunk of system memory. Which means that there is no risk | |
2392 | * that the register values disappear as soon as we call | |
2393 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2394 | * pin/unpin/fence and not more. | |
2395 | */ | |
2396 | intel_runtime_pm_get(dev_priv); | |
2397 | ||
ce453d81 | 2398 | dev_priv->mm.interruptible = false; |
e6617330 | 2399 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2400 | &view); |
48b956c5 | 2401 | if (ret) |
ce453d81 | 2402 | goto err_interruptible; |
6b95a207 KH |
2403 | |
2404 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2405 | * fence, whereas 965+ only requires a fence if using | |
2406 | * framebuffer compression. For simplicity, we always install | |
2407 | * a fence as the cost is not that onerous. | |
2408 | */ | |
06d98131 | 2409 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2410 | if (ret) |
2411 | goto err_unpin; | |
1690e1eb | 2412 | |
9a5a53b3 | 2413 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2414 | |
ce453d81 | 2415 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2416 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2417 | return 0; |
48b956c5 CW |
2418 | |
2419 | err_unpin: | |
f64b98cd | 2420 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2421 | err_interruptible: |
2422 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2423 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2424 | return ret; |
6b95a207 KH |
2425 | } |
2426 | ||
82bc3b2d TU |
2427 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2428 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2429 | { |
82bc3b2d | 2430 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2431 | struct i915_ggtt_view view; |
2432 | int ret; | |
82bc3b2d | 2433 | |
ebcdd39e MR |
2434 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2435 | ||
f64b98cd TU |
2436 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2437 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2438 | ||
1690e1eb | 2439 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2440 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2441 | } |
2442 | ||
c2c75131 DV |
2443 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2444 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2445 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2446 | unsigned int tiling_mode, | |
2447 | unsigned int cpp, | |
2448 | unsigned int pitch) | |
c2c75131 | 2449 | { |
bc752862 CW |
2450 | if (tiling_mode != I915_TILING_NONE) { |
2451 | unsigned int tile_rows, tiles; | |
c2c75131 | 2452 | |
bc752862 CW |
2453 | tile_rows = *y / 8; |
2454 | *y %= 8; | |
c2c75131 | 2455 | |
bc752862 CW |
2456 | tiles = *x / (512/cpp); |
2457 | *x %= 512/cpp; | |
2458 | ||
2459 | return tile_rows * pitch * 8 + tiles * 4096; | |
2460 | } else { | |
2461 | unsigned int offset; | |
2462 | ||
2463 | offset = *y * pitch + *x * cpp; | |
2464 | *y = 0; | |
2465 | *x = (offset & 4095) / cpp; | |
2466 | return offset & -4096; | |
2467 | } | |
c2c75131 DV |
2468 | } |
2469 | ||
b35d63fa | 2470 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2471 | { |
2472 | switch (format) { | |
2473 | case DISPPLANE_8BPP: | |
2474 | return DRM_FORMAT_C8; | |
2475 | case DISPPLANE_BGRX555: | |
2476 | return DRM_FORMAT_XRGB1555; | |
2477 | case DISPPLANE_BGRX565: | |
2478 | return DRM_FORMAT_RGB565; | |
2479 | default: | |
2480 | case DISPPLANE_BGRX888: | |
2481 | return DRM_FORMAT_XRGB8888; | |
2482 | case DISPPLANE_RGBX888: | |
2483 | return DRM_FORMAT_XBGR8888; | |
2484 | case DISPPLANE_BGRX101010: | |
2485 | return DRM_FORMAT_XRGB2101010; | |
2486 | case DISPPLANE_RGBX101010: | |
2487 | return DRM_FORMAT_XBGR2101010; | |
2488 | } | |
2489 | } | |
2490 | ||
bc8d7dff DL |
2491 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2492 | { | |
2493 | switch (format) { | |
2494 | case PLANE_CTL_FORMAT_RGB_565: | |
2495 | return DRM_FORMAT_RGB565; | |
2496 | default: | |
2497 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2498 | if (rgb_order) { | |
2499 | if (alpha) | |
2500 | return DRM_FORMAT_ABGR8888; | |
2501 | else | |
2502 | return DRM_FORMAT_XBGR8888; | |
2503 | } else { | |
2504 | if (alpha) | |
2505 | return DRM_FORMAT_ARGB8888; | |
2506 | else | |
2507 | return DRM_FORMAT_XRGB8888; | |
2508 | } | |
2509 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2510 | if (rgb_order) | |
2511 | return DRM_FORMAT_XBGR2101010; | |
2512 | else | |
2513 | return DRM_FORMAT_XRGB2101010; | |
2514 | } | |
2515 | } | |
2516 | ||
5724dbd1 | 2517 | static bool |
f6936e29 DV |
2518 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2519 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2520 | { |
2521 | struct drm_device *dev = crtc->base.dev; | |
2522 | struct drm_i915_gem_object *obj = NULL; | |
2523 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2524 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2525 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2526 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2527 | PAGE_SIZE); | |
2528 | ||
2529 | size_aligned -= base_aligned; | |
46f297fb | 2530 | |
ff2652ea CW |
2531 | if (plane_config->size == 0) |
2532 | return false; | |
2533 | ||
f37b5c2b DV |
2534 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2535 | base_aligned, | |
2536 | base_aligned, | |
2537 | size_aligned); | |
46f297fb | 2538 | if (!obj) |
484b41dd | 2539 | return false; |
46f297fb | 2540 | |
49af449b DL |
2541 | obj->tiling_mode = plane_config->tiling; |
2542 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2543 | obj->stride = fb->pitches[0]; |
46f297fb | 2544 | |
6bf129df DL |
2545 | mode_cmd.pixel_format = fb->pixel_format; |
2546 | mode_cmd.width = fb->width; | |
2547 | mode_cmd.height = fb->height; | |
2548 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2549 | mode_cmd.modifier[0] = fb->modifier[0]; |
2550 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2551 | |
2552 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2553 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2554 | &mode_cmd, obj)) { |
46f297fb JB |
2555 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2556 | goto out_unref_obj; | |
2557 | } | |
46f297fb | 2558 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2559 | |
f6936e29 | 2560 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2561 | return true; |
46f297fb JB |
2562 | |
2563 | out_unref_obj: | |
2564 | drm_gem_object_unreference(&obj->base); | |
2565 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2566 | return false; |
2567 | } | |
2568 | ||
afd65eb4 MR |
2569 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2570 | static void | |
2571 | update_state_fb(struct drm_plane *plane) | |
2572 | { | |
2573 | if (plane->fb == plane->state->fb) | |
2574 | return; | |
2575 | ||
2576 | if (plane->state->fb) | |
2577 | drm_framebuffer_unreference(plane->state->fb); | |
2578 | plane->state->fb = plane->fb; | |
2579 | if (plane->state->fb) | |
2580 | drm_framebuffer_reference(plane->state->fb); | |
2581 | } | |
2582 | ||
5724dbd1 | 2583 | static void |
f6936e29 DV |
2584 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2585 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2586 | { |
2587 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2588 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2589 | struct drm_crtc *c; |
2590 | struct intel_crtc *i; | |
2ff8fde1 | 2591 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2592 | struct drm_plane *primary = intel_crtc->base.primary; |
2593 | struct drm_framebuffer *fb; | |
484b41dd | 2594 | |
2d14030b | 2595 | if (!plane_config->fb) |
484b41dd JB |
2596 | return; |
2597 | ||
f6936e29 | 2598 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2599 | fb = &plane_config->fb->base; |
2600 | goto valid_fb; | |
f55548b5 | 2601 | } |
484b41dd | 2602 | |
2d14030b | 2603 | kfree(plane_config->fb); |
484b41dd JB |
2604 | |
2605 | /* | |
2606 | * Failed to alloc the obj, check to see if we should share | |
2607 | * an fb with another CRTC instead | |
2608 | */ | |
70e1e0ec | 2609 | for_each_crtc(dev, c) { |
484b41dd JB |
2610 | i = to_intel_crtc(c); |
2611 | ||
2612 | if (c == &intel_crtc->base) | |
2613 | continue; | |
2614 | ||
2ff8fde1 MR |
2615 | if (!i->active) |
2616 | continue; | |
2617 | ||
88595ac9 DV |
2618 | fb = c->primary->fb; |
2619 | if (!fb) | |
484b41dd JB |
2620 | continue; |
2621 | ||
88595ac9 | 2622 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2623 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2624 | drm_framebuffer_reference(fb); |
2625 | goto valid_fb; | |
484b41dd JB |
2626 | } |
2627 | } | |
88595ac9 DV |
2628 | |
2629 | return; | |
2630 | ||
2631 | valid_fb: | |
2632 | obj = intel_fb_obj(fb); | |
2633 | if (obj->tiling_mode != I915_TILING_NONE) | |
2634 | dev_priv->preserve_bios_swizzle = true; | |
2635 | ||
2636 | primary->fb = fb; | |
2637 | primary->state->crtc = &intel_crtc->base; | |
2638 | primary->crtc = &intel_crtc->base; | |
2639 | update_state_fb(primary); | |
2640 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2641 | } |
2642 | ||
29b9bde6 DV |
2643 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2644 | struct drm_framebuffer *fb, | |
2645 | int x, int y) | |
81255565 JB |
2646 | { |
2647 | struct drm_device *dev = crtc->dev; | |
2648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2649 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2650 | struct drm_plane *primary = crtc->primary; |
2651 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2652 | struct drm_i915_gem_object *obj; |
81255565 | 2653 | int plane = intel_crtc->plane; |
e506a0c6 | 2654 | unsigned long linear_offset; |
81255565 | 2655 | u32 dspcntr; |
f45651ba | 2656 | u32 reg = DSPCNTR(plane); |
48404c1e | 2657 | int pixel_size; |
f45651ba | 2658 | |
b70709a6 | 2659 | if (!visible || !fb) { |
fdd508a6 VS |
2660 | I915_WRITE(reg, 0); |
2661 | if (INTEL_INFO(dev)->gen >= 4) | |
2662 | I915_WRITE(DSPSURF(plane), 0); | |
2663 | else | |
2664 | I915_WRITE(DSPADDR(plane), 0); | |
2665 | POSTING_READ(reg); | |
2666 | return; | |
2667 | } | |
2668 | ||
c9ba6fad VS |
2669 | obj = intel_fb_obj(fb); |
2670 | if (WARN_ON(obj == NULL)) | |
2671 | return; | |
2672 | ||
2673 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2674 | ||
f45651ba VS |
2675 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2676 | ||
fdd508a6 | 2677 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2678 | |
2679 | if (INTEL_INFO(dev)->gen < 4) { | |
2680 | if (intel_crtc->pipe == PIPE_B) | |
2681 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2682 | ||
2683 | /* pipesrc and dspsize control the size that is scaled from, | |
2684 | * which should always be the user's requested size. | |
2685 | */ | |
2686 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2687 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2688 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2689 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2690 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2691 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2692 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2693 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2694 | I915_WRITE(PRIMPOS(plane), 0); |
2695 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2696 | } |
81255565 | 2697 | |
57779d06 VS |
2698 | switch (fb->pixel_format) { |
2699 | case DRM_FORMAT_C8: | |
81255565 JB |
2700 | dspcntr |= DISPPLANE_8BPP; |
2701 | break; | |
57779d06 VS |
2702 | case DRM_FORMAT_XRGB1555: |
2703 | case DRM_FORMAT_ARGB1555: | |
2704 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2705 | break; |
57779d06 VS |
2706 | case DRM_FORMAT_RGB565: |
2707 | dspcntr |= DISPPLANE_BGRX565; | |
2708 | break; | |
2709 | case DRM_FORMAT_XRGB8888: | |
2710 | case DRM_FORMAT_ARGB8888: | |
2711 | dspcntr |= DISPPLANE_BGRX888; | |
2712 | break; | |
2713 | case DRM_FORMAT_XBGR8888: | |
2714 | case DRM_FORMAT_ABGR8888: | |
2715 | dspcntr |= DISPPLANE_RGBX888; | |
2716 | break; | |
2717 | case DRM_FORMAT_XRGB2101010: | |
2718 | case DRM_FORMAT_ARGB2101010: | |
2719 | dspcntr |= DISPPLANE_BGRX101010; | |
2720 | break; | |
2721 | case DRM_FORMAT_XBGR2101010: | |
2722 | case DRM_FORMAT_ABGR2101010: | |
2723 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2724 | break; |
2725 | default: | |
baba133a | 2726 | BUG(); |
81255565 | 2727 | } |
57779d06 | 2728 | |
f45651ba VS |
2729 | if (INTEL_INFO(dev)->gen >= 4 && |
2730 | obj->tiling_mode != I915_TILING_NONE) | |
2731 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2732 | |
de1aa629 VS |
2733 | if (IS_G4X(dev)) |
2734 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2735 | ||
b9897127 | 2736 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2737 | |
c2c75131 DV |
2738 | if (INTEL_INFO(dev)->gen >= 4) { |
2739 | intel_crtc->dspaddr_offset = | |
bc752862 | 2740 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2741 | pixel_size, |
bc752862 | 2742 | fb->pitches[0]); |
c2c75131 DV |
2743 | linear_offset -= intel_crtc->dspaddr_offset; |
2744 | } else { | |
e506a0c6 | 2745 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2746 | } |
e506a0c6 | 2747 | |
8e7d688b | 2748 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2749 | dspcntr |= DISPPLANE_ROTATE_180; |
2750 | ||
6e3c9717 ACO |
2751 | x += (intel_crtc->config->pipe_src_w - 1); |
2752 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2753 | |
2754 | /* Finding the last pixel of the last line of the display | |
2755 | data and adding to linear_offset*/ | |
2756 | linear_offset += | |
6e3c9717 ACO |
2757 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2758 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2759 | } |
2760 | ||
2761 | I915_WRITE(reg, dspcntr); | |
2762 | ||
01f2c773 | 2763 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2764 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2765 | I915_WRITE(DSPSURF(plane), |
2766 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2767 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2768 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2769 | } else |
f343c5f6 | 2770 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2771 | POSTING_READ(reg); |
17638cd6 JB |
2772 | } |
2773 | ||
29b9bde6 DV |
2774 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2775 | struct drm_framebuffer *fb, | |
2776 | int x, int y) | |
17638cd6 JB |
2777 | { |
2778 | struct drm_device *dev = crtc->dev; | |
2779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2780 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2781 | struct drm_plane *primary = crtc->primary; |
2782 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2783 | struct drm_i915_gem_object *obj; |
17638cd6 | 2784 | int plane = intel_crtc->plane; |
e506a0c6 | 2785 | unsigned long linear_offset; |
17638cd6 | 2786 | u32 dspcntr; |
f45651ba | 2787 | u32 reg = DSPCNTR(plane); |
48404c1e | 2788 | int pixel_size; |
f45651ba | 2789 | |
b70709a6 | 2790 | if (!visible || !fb) { |
fdd508a6 VS |
2791 | I915_WRITE(reg, 0); |
2792 | I915_WRITE(DSPSURF(plane), 0); | |
2793 | POSTING_READ(reg); | |
2794 | return; | |
2795 | } | |
2796 | ||
c9ba6fad VS |
2797 | obj = intel_fb_obj(fb); |
2798 | if (WARN_ON(obj == NULL)) | |
2799 | return; | |
2800 | ||
2801 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2802 | ||
f45651ba VS |
2803 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2804 | ||
fdd508a6 | 2805 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2806 | |
2807 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2808 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2809 | |
57779d06 VS |
2810 | switch (fb->pixel_format) { |
2811 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2812 | dspcntr |= DISPPLANE_8BPP; |
2813 | break; | |
57779d06 VS |
2814 | case DRM_FORMAT_RGB565: |
2815 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2816 | break; |
57779d06 VS |
2817 | case DRM_FORMAT_XRGB8888: |
2818 | case DRM_FORMAT_ARGB8888: | |
2819 | dspcntr |= DISPPLANE_BGRX888; | |
2820 | break; | |
2821 | case DRM_FORMAT_XBGR8888: | |
2822 | case DRM_FORMAT_ABGR8888: | |
2823 | dspcntr |= DISPPLANE_RGBX888; | |
2824 | break; | |
2825 | case DRM_FORMAT_XRGB2101010: | |
2826 | case DRM_FORMAT_ARGB2101010: | |
2827 | dspcntr |= DISPPLANE_BGRX101010; | |
2828 | break; | |
2829 | case DRM_FORMAT_XBGR2101010: | |
2830 | case DRM_FORMAT_ABGR2101010: | |
2831 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2832 | break; |
2833 | default: | |
baba133a | 2834 | BUG(); |
17638cd6 JB |
2835 | } |
2836 | ||
2837 | if (obj->tiling_mode != I915_TILING_NONE) | |
2838 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2839 | |
f45651ba | 2840 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2841 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2842 | |
b9897127 | 2843 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2844 | intel_crtc->dspaddr_offset = |
bc752862 | 2845 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2846 | pixel_size, |
bc752862 | 2847 | fb->pitches[0]); |
c2c75131 | 2848 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2849 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2850 | dspcntr |= DISPPLANE_ROTATE_180; |
2851 | ||
2852 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2853 | x += (intel_crtc->config->pipe_src_w - 1); |
2854 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2855 | |
2856 | /* Finding the last pixel of the last line of the display | |
2857 | data and adding to linear_offset*/ | |
2858 | linear_offset += | |
6e3c9717 ACO |
2859 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2860 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2861 | } |
2862 | } | |
2863 | ||
2864 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2865 | |
01f2c773 | 2866 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2867 | I915_WRITE(DSPSURF(plane), |
2868 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2869 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2870 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2871 | } else { | |
2872 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2873 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2874 | } | |
17638cd6 | 2875 | POSTING_READ(reg); |
17638cd6 JB |
2876 | } |
2877 | ||
b321803d DL |
2878 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2879 | uint32_t pixel_format) | |
2880 | { | |
2881 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2882 | ||
2883 | /* | |
2884 | * The stride is either expressed as a multiple of 64 bytes | |
2885 | * chunks for linear buffers or in number of tiles for tiled | |
2886 | * buffers. | |
2887 | */ | |
2888 | switch (fb_modifier) { | |
2889 | case DRM_FORMAT_MOD_NONE: | |
2890 | return 64; | |
2891 | case I915_FORMAT_MOD_X_TILED: | |
2892 | if (INTEL_INFO(dev)->gen == 2) | |
2893 | return 128; | |
2894 | return 512; | |
2895 | case I915_FORMAT_MOD_Y_TILED: | |
2896 | /* No need to check for old gens and Y tiling since this is | |
2897 | * about the display engine and those will be blocked before | |
2898 | * we get here. | |
2899 | */ | |
2900 | return 128; | |
2901 | case I915_FORMAT_MOD_Yf_TILED: | |
2902 | if (bits_per_pixel == 8) | |
2903 | return 64; | |
2904 | else | |
2905 | return 128; | |
2906 | default: | |
2907 | MISSING_CASE(fb_modifier); | |
2908 | return 64; | |
2909 | } | |
2910 | } | |
2911 | ||
121920fa TU |
2912 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2913 | struct drm_i915_gem_object *obj) | |
2914 | { | |
9abc4648 | 2915 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2916 | |
2917 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2918 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2919 | |
2920 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2921 | } | |
2922 | ||
a1b2278e CK |
2923 | /* |
2924 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2925 | */ | |
2926 | void skl_detach_scalers(struct intel_crtc *intel_crtc) | |
2927 | { | |
2928 | struct drm_device *dev; | |
2929 | struct drm_i915_private *dev_priv; | |
2930 | struct intel_crtc_scaler_state *scaler_state; | |
2931 | int i; | |
2932 | ||
2933 | if (!intel_crtc || !intel_crtc->config) | |
2934 | return; | |
2935 | ||
2936 | dev = intel_crtc->base.dev; | |
2937 | dev_priv = dev->dev_private; | |
2938 | scaler_state = &intel_crtc->config->scaler_state; | |
2939 | ||
2940 | /* loop through and disable scalers that aren't in use */ | |
2941 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
2942 | if (!scaler_state->scalers[i].in_use) { | |
2943 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0); | |
2944 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0); | |
2945 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0); | |
2946 | DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n", | |
2947 | intel_crtc->base.base.id, intel_crtc->pipe, i); | |
2948 | } | |
2949 | } | |
2950 | } | |
2951 | ||
6156a456 | 2952 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2953 | { |
6156a456 CK |
2954 | u32 plane_ctl_format = 0; |
2955 | switch (pixel_format) { | |
70d21f0e | 2956 | case DRM_FORMAT_RGB565: |
6156a456 | 2957 | plane_ctl_format = PLANE_CTL_FORMAT_RGB_565; |
f75fb42a | 2958 | break; |
70d21f0e | 2959 | case DRM_FORMAT_XBGR8888: |
6156a456 CK |
2960 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
2961 | break; | |
2962 | case DRM_FORMAT_XRGB8888: | |
2963 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888; | |
70d21f0e | 2964 | break; |
6156a456 CK |
2965 | /* |
2966 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2967 | * to be already pre-multiplied. We need to add a knob (or a different | |
2968 | * DRM_FORMAT) for user-space to configure that. | |
2969 | */ | |
f75fb42a | 2970 | case DRM_FORMAT_ABGR8888: |
6156a456 CK |
2971 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
2972 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2973 | break; | |
2974 | case DRM_FORMAT_ARGB8888: | |
2975 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | | |
2976 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
f75fb42a | 2977 | break; |
70d21f0e | 2978 | case DRM_FORMAT_XRGB2101010: |
6156a456 | 2979 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e DL |
2980 | break; |
2981 | case DRM_FORMAT_XBGR2101010: | |
6156a456 CK |
2982 | plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
2983 | break; | |
2984 | case DRM_FORMAT_YUYV: | |
2985 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; | |
2986 | break; | |
2987 | case DRM_FORMAT_YVYU: | |
2988 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; | |
2989 | break; | |
2990 | case DRM_FORMAT_UYVY: | |
2991 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; | |
2992 | break; | |
2993 | case DRM_FORMAT_VYUY: | |
2994 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; | |
70d21f0e DL |
2995 | break; |
2996 | default: | |
2997 | BUG(); | |
2998 | } | |
6156a456 CK |
2999 | return plane_ctl_format; |
3000 | } | |
70d21f0e | 3001 | |
6156a456 CK |
3002 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3003 | { | |
3004 | u32 plane_ctl_tiling = 0; | |
3005 | switch (fb_modifier) { | |
30af77c4 | 3006 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3007 | break; |
30af77c4 | 3008 | case I915_FORMAT_MOD_X_TILED: |
6156a456 | 3009 | plane_ctl_tiling = PLANE_CTL_TILED_X; |
b321803d DL |
3010 | break; |
3011 | case I915_FORMAT_MOD_Y_TILED: | |
6156a456 | 3012 | plane_ctl_tiling = PLANE_CTL_TILED_Y; |
b321803d DL |
3013 | break; |
3014 | case I915_FORMAT_MOD_Yf_TILED: | |
6156a456 | 3015 | plane_ctl_tiling = PLANE_CTL_TILED_YF; |
70d21f0e DL |
3016 | break; |
3017 | default: | |
6156a456 | 3018 | MISSING_CASE(fb_modifier); |
70d21f0e | 3019 | } |
6156a456 CK |
3020 | return plane_ctl_tiling; |
3021 | } | |
70d21f0e | 3022 | |
6156a456 CK |
3023 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3024 | { | |
3025 | u32 plane_ctl_rotation = 0; | |
3b7a5119 | 3026 | switch (rotation) { |
6156a456 CK |
3027 | case BIT(DRM_ROTATE_0): |
3028 | break; | |
3b7a5119 | 3029 | case BIT(DRM_ROTATE_90): |
6156a456 | 3030 | plane_ctl_rotation = PLANE_CTL_ROTATE_90; |
3b7a5119 | 3031 | break; |
3b7a5119 | 3032 | case BIT(DRM_ROTATE_180): |
6156a456 | 3033 | plane_ctl_rotation = PLANE_CTL_ROTATE_180; |
3b7a5119 | 3034 | break; |
3b7a5119 | 3035 | case BIT(DRM_ROTATE_270): |
6156a456 | 3036 | plane_ctl_rotation = PLANE_CTL_ROTATE_270; |
3b7a5119 | 3037 | break; |
6156a456 CK |
3038 | default: |
3039 | MISSING_CASE(rotation); | |
3040 | } | |
3041 | ||
3042 | return plane_ctl_rotation; | |
3043 | } | |
3044 | ||
3045 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3046 | struct drm_framebuffer *fb, | |
3047 | int x, int y) | |
3048 | { | |
3049 | struct drm_device *dev = crtc->dev; | |
3050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3051 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3052 | struct drm_plane *plane = crtc->primary; |
3053 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3054 | struct drm_i915_gem_object *obj; |
3055 | int pipe = intel_crtc->pipe; | |
3056 | u32 plane_ctl, stride_div, stride; | |
3057 | u32 tile_height, plane_offset, plane_size; | |
3058 | unsigned int rotation; | |
3059 | int x_offset, y_offset; | |
3060 | unsigned long surf_addr; | |
6156a456 CK |
3061 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3062 | struct intel_plane_state *plane_state; | |
3063 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3064 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3065 | int scaler_id = -1; | |
3066 | ||
6156a456 CK |
3067 | plane_state = to_intel_plane_state(plane->state); |
3068 | ||
b70709a6 | 3069 | if (!visible || !fb) { |
6156a456 CK |
3070 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3071 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3072 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3073 | return; | |
3b7a5119 | 3074 | } |
70d21f0e | 3075 | |
6156a456 CK |
3076 | plane_ctl = PLANE_CTL_ENABLE | |
3077 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3078 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3079 | ||
3080 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3081 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3082 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3083 | ||
3084 | rotation = plane->state->rotation; | |
3085 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3086 | ||
b321803d DL |
3087 | obj = intel_fb_obj(fb); |
3088 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3089 | fb->pixel_format); | |
3b7a5119 SJ |
3090 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3091 | ||
6156a456 CK |
3092 | /* |
3093 | * FIXME: intel_plane_state->src, dst aren't set when transitional | |
3094 | * update_plane helpers are called from legacy paths. | |
3095 | * Once full atomic crtc is available, below check can be avoided. | |
3096 | */ | |
3097 | if (drm_rect_width(&plane_state->src)) { | |
3098 | scaler_id = plane_state->scaler_id; | |
3099 | src_x = plane_state->src.x1 >> 16; | |
3100 | src_y = plane_state->src.y1 >> 16; | |
3101 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3102 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3103 | dst_x = plane_state->dst.x1; | |
3104 | dst_y = plane_state->dst.y1; | |
3105 | dst_w = drm_rect_width(&plane_state->dst); | |
3106 | dst_h = drm_rect_height(&plane_state->dst); | |
3107 | ||
3108 | WARN_ON(x != src_x || y != src_y); | |
3109 | } else { | |
3110 | src_w = intel_crtc->config->pipe_src_w; | |
3111 | src_h = intel_crtc->config->pipe_src_h; | |
3112 | } | |
3113 | ||
3b7a5119 SJ |
3114 | if (intel_rotation_90_or_270(rotation)) { |
3115 | /* stride = Surface height in tiles */ | |
3116 | tile_height = intel_tile_height(dev, fb->bits_per_pixel, | |
3117 | fb->modifier[0]); | |
3118 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
6156a456 | 3119 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3120 | y_offset = x; |
6156a456 | 3121 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3122 | } else { |
3123 | stride = fb->pitches[0] / stride_div; | |
3124 | x_offset = x; | |
3125 | y_offset = y; | |
6156a456 | 3126 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3127 | } |
3128 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3129 | |
70d21f0e | 3130 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3131 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3132 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3133 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3134 | |
3135 | if (scaler_id >= 0) { | |
3136 | uint32_t ps_ctrl = 0; | |
3137 | ||
3138 | WARN_ON(!dst_w || !dst_h); | |
3139 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3140 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3141 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3142 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3143 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3144 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3145 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3146 | } else { | |
3147 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3148 | } | |
3149 | ||
121920fa | 3150 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3151 | |
3152 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3153 | } | |
3154 | ||
17638cd6 JB |
3155 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3156 | static int | |
3157 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3158 | int x, int y, enum mode_set_atomic state) | |
3159 | { | |
3160 | struct drm_device *dev = crtc->dev; | |
3161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3162 | |
6b8e6ed0 CW |
3163 | if (dev_priv->display.disable_fbc) |
3164 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3165 | |
29b9bde6 DV |
3166 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3167 | ||
3168 | return 0; | |
81255565 JB |
3169 | } |
3170 | ||
7514747d | 3171 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3172 | { |
96a02917 VS |
3173 | struct drm_crtc *crtc; |
3174 | ||
70e1e0ec | 3175 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3176 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3177 | enum plane plane = intel_crtc->plane; | |
3178 | ||
3179 | intel_prepare_page_flip(dev, plane); | |
3180 | intel_finish_page_flip_plane(dev, plane); | |
3181 | } | |
7514747d VS |
3182 | } |
3183 | ||
3184 | static void intel_update_primary_planes(struct drm_device *dev) | |
3185 | { | |
3186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3187 | struct drm_crtc *crtc; | |
96a02917 | 3188 | |
70e1e0ec | 3189 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3190 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3191 | ||
51fd371b | 3192 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3193 | /* |
3194 | * FIXME: Once we have proper support for primary planes (and | |
3195 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3196 | * a NULL crtc->primary->fb. |
947fdaad | 3197 | */ |
f4510a27 | 3198 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3199 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3200 | crtc->primary->fb, |
262ca2b0 MR |
3201 | crtc->x, |
3202 | crtc->y); | |
51fd371b | 3203 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3204 | } |
3205 | } | |
3206 | ||
ce22dba9 ML |
3207 | void intel_crtc_reset(struct intel_crtc *crtc) |
3208 | { | |
3209 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
3210 | ||
3211 | if (!crtc->active) | |
3212 | return; | |
3213 | ||
3214 | intel_crtc_disable_planes(&crtc->base); | |
3215 | dev_priv->display.crtc_disable(&crtc->base); | |
3216 | dev_priv->display.crtc_enable(&crtc->base); | |
3217 | intel_crtc_enable_planes(&crtc->base); | |
3218 | } | |
3219 | ||
7514747d VS |
3220 | void intel_prepare_reset(struct drm_device *dev) |
3221 | { | |
f98ce92f VS |
3222 | struct drm_i915_private *dev_priv = to_i915(dev); |
3223 | struct intel_crtc *crtc; | |
3224 | ||
7514747d VS |
3225 | /* no reset support for gen2 */ |
3226 | if (IS_GEN2(dev)) | |
3227 | return; | |
3228 | ||
3229 | /* reset doesn't touch the display */ | |
3230 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3231 | return; | |
3232 | ||
3233 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3234 | |
3235 | /* | |
3236 | * Disabling the crtcs gracefully seems nicer. Also the | |
3237 | * g33 docs say we should at least disable all the planes. | |
3238 | */ | |
3239 | for_each_intel_crtc(dev, crtc) { | |
ce22dba9 ML |
3240 | if (!crtc->active) |
3241 | continue; | |
3242 | ||
3243 | intel_crtc_disable_planes(&crtc->base); | |
3244 | dev_priv->display.crtc_disable(&crtc->base); | |
f98ce92f | 3245 | } |
7514747d VS |
3246 | } |
3247 | ||
3248 | void intel_finish_reset(struct drm_device *dev) | |
3249 | { | |
3250 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3251 | ||
3252 | /* | |
3253 | * Flips in the rings will be nuked by the reset, | |
3254 | * so complete all pending flips so that user space | |
3255 | * will get its events and not get stuck. | |
3256 | */ | |
3257 | intel_complete_page_flips(dev); | |
3258 | ||
3259 | /* no reset support for gen2 */ | |
3260 | if (IS_GEN2(dev)) | |
3261 | return; | |
3262 | ||
3263 | /* reset doesn't touch the display */ | |
3264 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3265 | /* | |
3266 | * Flips in the rings have been nuked by the reset, | |
3267 | * so update the base address of all primary | |
3268 | * planes to the the last fb to make sure we're | |
3269 | * showing the correct fb after a reset. | |
3270 | */ | |
3271 | intel_update_primary_planes(dev); | |
3272 | return; | |
3273 | } | |
3274 | ||
3275 | /* | |
3276 | * The display has been reset as well, | |
3277 | * so need a full re-initialization. | |
3278 | */ | |
3279 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3280 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3281 | ||
3282 | intel_modeset_init_hw(dev); | |
3283 | ||
3284 | spin_lock_irq(&dev_priv->irq_lock); | |
3285 | if (dev_priv->display.hpd_irq_setup) | |
3286 | dev_priv->display.hpd_irq_setup(dev); | |
3287 | spin_unlock_irq(&dev_priv->irq_lock); | |
3288 | ||
3289 | intel_modeset_setup_hw_state(dev, true); | |
3290 | ||
3291 | intel_hpd_init(dev_priv); | |
3292 | ||
3293 | drm_modeset_unlock_all(dev); | |
3294 | } | |
3295 | ||
14667a4b CW |
3296 | static int |
3297 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
3298 | { | |
2ff8fde1 | 3299 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
3300 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3301 | bool was_interruptible = dev_priv->mm.interruptible; | |
3302 | int ret; | |
3303 | ||
14667a4b CW |
3304 | /* Big Hammer, we also need to ensure that any pending |
3305 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3306 | * current scanout is retired before unpinning the old | |
3307 | * framebuffer. | |
3308 | * | |
3309 | * This should only fail upon a hung GPU, in which case we | |
3310 | * can safely continue. | |
3311 | */ | |
3312 | dev_priv->mm.interruptible = false; | |
3313 | ret = i915_gem_object_finish_gpu(obj); | |
3314 | dev_priv->mm.interruptible = was_interruptible; | |
3315 | ||
3316 | return ret; | |
3317 | } | |
3318 | ||
7d5e3799 CW |
3319 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3320 | { | |
3321 | struct drm_device *dev = crtc->dev; | |
3322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3323 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3324 | bool pending; |
3325 | ||
3326 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3327 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3328 | return false; | |
3329 | ||
5e2d7afc | 3330 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3331 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3332 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3333 | |
3334 | return pending; | |
3335 | } | |
3336 | ||
e30e8f75 GP |
3337 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3338 | { | |
3339 | struct drm_device *dev = crtc->base.dev; | |
3340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3341 | const struct drm_display_mode *adjusted_mode; | |
3342 | ||
3343 | if (!i915.fastboot) | |
3344 | return; | |
3345 | ||
3346 | /* | |
3347 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3348 | * that in compute_mode_changes we check the native mode (not the pfit | |
3349 | * mode) to see if we can flip rather than do a full mode set. In the | |
3350 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3351 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3352 | * sized surface. | |
3353 | * | |
3354 | * To fix this properly, we need to hoist the checks up into | |
3355 | * compute_mode_changes (or above), check the actual pfit state and | |
3356 | * whether the platform allows pfit disable with pipe active, and only | |
3357 | * then update the pipesrc and pfit state, even on the flip path. | |
3358 | */ | |
3359 | ||
6e3c9717 | 3360 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3361 | |
3362 | I915_WRITE(PIPESRC(crtc->pipe), | |
3363 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3364 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3365 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3366 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3367 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3368 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3369 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3370 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3371 | } | |
6e3c9717 ACO |
3372 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3373 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3374 | } |
3375 | ||
5e84e1a4 ZW |
3376 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3377 | { | |
3378 | struct drm_device *dev = crtc->dev; | |
3379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3381 | int pipe = intel_crtc->pipe; | |
3382 | u32 reg, temp; | |
3383 | ||
3384 | /* enable normal train */ | |
3385 | reg = FDI_TX_CTL(pipe); | |
3386 | temp = I915_READ(reg); | |
61e499bf | 3387 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3388 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3389 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3390 | } else { |
3391 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3392 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3393 | } |
5e84e1a4 ZW |
3394 | I915_WRITE(reg, temp); |
3395 | ||
3396 | reg = FDI_RX_CTL(pipe); | |
3397 | temp = I915_READ(reg); | |
3398 | if (HAS_PCH_CPT(dev)) { | |
3399 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3400 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3401 | } else { | |
3402 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3403 | temp |= FDI_LINK_TRAIN_NONE; | |
3404 | } | |
3405 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3406 | ||
3407 | /* wait one idle pattern time */ | |
3408 | POSTING_READ(reg); | |
3409 | udelay(1000); | |
357555c0 JB |
3410 | |
3411 | /* IVB wants error correction enabled */ | |
3412 | if (IS_IVYBRIDGE(dev)) | |
3413 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3414 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3415 | } |
3416 | ||
8db9d77b ZW |
3417 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3418 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3419 | { | |
3420 | struct drm_device *dev = crtc->dev; | |
3421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3422 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3423 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3424 | u32 reg, temp, tries; |
8db9d77b | 3425 | |
1c8562f6 | 3426 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3427 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3428 | |
e1a44743 AJ |
3429 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3430 | for train result */ | |
5eddb70b CW |
3431 | reg = FDI_RX_IMR(pipe); |
3432 | temp = I915_READ(reg); | |
e1a44743 AJ |
3433 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3434 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3435 | I915_WRITE(reg, temp); |
3436 | I915_READ(reg); | |
e1a44743 AJ |
3437 | udelay(150); |
3438 | ||
8db9d77b | 3439 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3440 | reg = FDI_TX_CTL(pipe); |
3441 | temp = I915_READ(reg); | |
627eb5a3 | 3442 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3443 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3444 | temp &= ~FDI_LINK_TRAIN_NONE; |
3445 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3446 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3447 | |
5eddb70b CW |
3448 | reg = FDI_RX_CTL(pipe); |
3449 | temp = I915_READ(reg); | |
8db9d77b ZW |
3450 | temp &= ~FDI_LINK_TRAIN_NONE; |
3451 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3452 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3453 | ||
3454 | POSTING_READ(reg); | |
8db9d77b ZW |
3455 | udelay(150); |
3456 | ||
5b2adf89 | 3457 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3458 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3459 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3460 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3461 | |
5eddb70b | 3462 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3463 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3464 | temp = I915_READ(reg); |
8db9d77b ZW |
3465 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3466 | ||
3467 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3468 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3469 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3470 | break; |
3471 | } | |
8db9d77b | 3472 | } |
e1a44743 | 3473 | if (tries == 5) |
5eddb70b | 3474 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3475 | |
3476 | /* Train 2 */ | |
5eddb70b CW |
3477 | reg = FDI_TX_CTL(pipe); |
3478 | temp = I915_READ(reg); | |
8db9d77b ZW |
3479 | temp &= ~FDI_LINK_TRAIN_NONE; |
3480 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3481 | I915_WRITE(reg, temp); |
8db9d77b | 3482 | |
5eddb70b CW |
3483 | reg = FDI_RX_CTL(pipe); |
3484 | temp = I915_READ(reg); | |
8db9d77b ZW |
3485 | temp &= ~FDI_LINK_TRAIN_NONE; |
3486 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3487 | I915_WRITE(reg, temp); |
8db9d77b | 3488 | |
5eddb70b CW |
3489 | POSTING_READ(reg); |
3490 | udelay(150); | |
8db9d77b | 3491 | |
5eddb70b | 3492 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3493 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3494 | temp = I915_READ(reg); |
8db9d77b ZW |
3495 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3496 | ||
3497 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3498 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3499 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3500 | break; | |
3501 | } | |
8db9d77b | 3502 | } |
e1a44743 | 3503 | if (tries == 5) |
5eddb70b | 3504 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3505 | |
3506 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3507 | |
8db9d77b ZW |
3508 | } |
3509 | ||
0206e353 | 3510 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3511 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3512 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3513 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3514 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3515 | }; | |
3516 | ||
3517 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3518 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3519 | { | |
3520 | struct drm_device *dev = crtc->dev; | |
3521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3522 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3523 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3524 | u32 reg, temp, i, retry; |
8db9d77b | 3525 | |
e1a44743 AJ |
3526 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3527 | for train result */ | |
5eddb70b CW |
3528 | reg = FDI_RX_IMR(pipe); |
3529 | temp = I915_READ(reg); | |
e1a44743 AJ |
3530 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3531 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3532 | I915_WRITE(reg, temp); |
3533 | ||
3534 | POSTING_READ(reg); | |
e1a44743 AJ |
3535 | udelay(150); |
3536 | ||
8db9d77b | 3537 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3538 | reg = FDI_TX_CTL(pipe); |
3539 | temp = I915_READ(reg); | |
627eb5a3 | 3540 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3541 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3542 | temp &= ~FDI_LINK_TRAIN_NONE; |
3543 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3544 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3545 | /* SNB-B */ | |
3546 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3547 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3548 | |
d74cf324 DV |
3549 | I915_WRITE(FDI_RX_MISC(pipe), |
3550 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3551 | ||
5eddb70b CW |
3552 | reg = FDI_RX_CTL(pipe); |
3553 | temp = I915_READ(reg); | |
8db9d77b ZW |
3554 | if (HAS_PCH_CPT(dev)) { |
3555 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3556 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3557 | } else { | |
3558 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3559 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3560 | } | |
5eddb70b CW |
3561 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3562 | ||
3563 | POSTING_READ(reg); | |
8db9d77b ZW |
3564 | udelay(150); |
3565 | ||
0206e353 | 3566 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3567 | reg = FDI_TX_CTL(pipe); |
3568 | temp = I915_READ(reg); | |
8db9d77b ZW |
3569 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3570 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3571 | I915_WRITE(reg, temp); |
3572 | ||
3573 | POSTING_READ(reg); | |
8db9d77b ZW |
3574 | udelay(500); |
3575 | ||
fa37d39e SP |
3576 | for (retry = 0; retry < 5; retry++) { |
3577 | reg = FDI_RX_IIR(pipe); | |
3578 | temp = I915_READ(reg); | |
3579 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3580 | if (temp & FDI_RX_BIT_LOCK) { | |
3581 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3582 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3583 | break; | |
3584 | } | |
3585 | udelay(50); | |
8db9d77b | 3586 | } |
fa37d39e SP |
3587 | if (retry < 5) |
3588 | break; | |
8db9d77b ZW |
3589 | } |
3590 | if (i == 4) | |
5eddb70b | 3591 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3592 | |
3593 | /* Train 2 */ | |
5eddb70b CW |
3594 | reg = FDI_TX_CTL(pipe); |
3595 | temp = I915_READ(reg); | |
8db9d77b ZW |
3596 | temp &= ~FDI_LINK_TRAIN_NONE; |
3597 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3598 | if (IS_GEN6(dev)) { | |
3599 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3600 | /* SNB-B */ | |
3601 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3602 | } | |
5eddb70b | 3603 | I915_WRITE(reg, temp); |
8db9d77b | 3604 | |
5eddb70b CW |
3605 | reg = FDI_RX_CTL(pipe); |
3606 | temp = I915_READ(reg); | |
8db9d77b ZW |
3607 | if (HAS_PCH_CPT(dev)) { |
3608 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3609 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3610 | } else { | |
3611 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3612 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3613 | } | |
5eddb70b CW |
3614 | I915_WRITE(reg, temp); |
3615 | ||
3616 | POSTING_READ(reg); | |
8db9d77b ZW |
3617 | udelay(150); |
3618 | ||
0206e353 | 3619 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3620 | reg = FDI_TX_CTL(pipe); |
3621 | temp = I915_READ(reg); | |
8db9d77b ZW |
3622 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3623 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3624 | I915_WRITE(reg, temp); |
3625 | ||
3626 | POSTING_READ(reg); | |
8db9d77b ZW |
3627 | udelay(500); |
3628 | ||
fa37d39e SP |
3629 | for (retry = 0; retry < 5; retry++) { |
3630 | reg = FDI_RX_IIR(pipe); | |
3631 | temp = I915_READ(reg); | |
3632 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3633 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3634 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3635 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3636 | break; | |
3637 | } | |
3638 | udelay(50); | |
8db9d77b | 3639 | } |
fa37d39e SP |
3640 | if (retry < 5) |
3641 | break; | |
8db9d77b ZW |
3642 | } |
3643 | if (i == 4) | |
5eddb70b | 3644 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3645 | |
3646 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3647 | } | |
3648 | ||
357555c0 JB |
3649 | /* Manual link training for Ivy Bridge A0 parts */ |
3650 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3651 | { | |
3652 | struct drm_device *dev = crtc->dev; | |
3653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3654 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3655 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3656 | u32 reg, temp, i, j; |
357555c0 JB |
3657 | |
3658 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3659 | for train result */ | |
3660 | reg = FDI_RX_IMR(pipe); | |
3661 | temp = I915_READ(reg); | |
3662 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3663 | temp &= ~FDI_RX_BIT_LOCK; | |
3664 | I915_WRITE(reg, temp); | |
3665 | ||
3666 | POSTING_READ(reg); | |
3667 | udelay(150); | |
3668 | ||
01a415fd DV |
3669 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3670 | I915_READ(FDI_RX_IIR(pipe))); | |
3671 | ||
139ccd3f JB |
3672 | /* Try each vswing and preemphasis setting twice before moving on */ |
3673 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3674 | /* disable first in case we need to retry */ | |
3675 | reg = FDI_TX_CTL(pipe); | |
3676 | temp = I915_READ(reg); | |
3677 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3678 | temp &= ~FDI_TX_ENABLE; | |
3679 | I915_WRITE(reg, temp); | |
357555c0 | 3680 | |
139ccd3f JB |
3681 | reg = FDI_RX_CTL(pipe); |
3682 | temp = I915_READ(reg); | |
3683 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3684 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3685 | temp &= ~FDI_RX_ENABLE; | |
3686 | I915_WRITE(reg, temp); | |
357555c0 | 3687 | |
139ccd3f | 3688 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3689 | reg = FDI_TX_CTL(pipe); |
3690 | temp = I915_READ(reg); | |
139ccd3f | 3691 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3692 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3693 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3694 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3695 | temp |= snb_b_fdi_train_param[j/2]; |
3696 | temp |= FDI_COMPOSITE_SYNC; | |
3697 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3698 | |
139ccd3f JB |
3699 | I915_WRITE(FDI_RX_MISC(pipe), |
3700 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3701 | |
139ccd3f | 3702 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3703 | temp = I915_READ(reg); |
139ccd3f JB |
3704 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3705 | temp |= FDI_COMPOSITE_SYNC; | |
3706 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3707 | |
139ccd3f JB |
3708 | POSTING_READ(reg); |
3709 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3710 | |
139ccd3f JB |
3711 | for (i = 0; i < 4; i++) { |
3712 | reg = FDI_RX_IIR(pipe); | |
3713 | temp = I915_READ(reg); | |
3714 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3715 | |
139ccd3f JB |
3716 | if (temp & FDI_RX_BIT_LOCK || |
3717 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3718 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3719 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3720 | i); | |
3721 | break; | |
3722 | } | |
3723 | udelay(1); /* should be 0.5us */ | |
3724 | } | |
3725 | if (i == 4) { | |
3726 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3727 | continue; | |
3728 | } | |
357555c0 | 3729 | |
139ccd3f | 3730 | /* Train 2 */ |
357555c0 JB |
3731 | reg = FDI_TX_CTL(pipe); |
3732 | temp = I915_READ(reg); | |
139ccd3f JB |
3733 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3734 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3735 | I915_WRITE(reg, temp); | |
3736 | ||
3737 | reg = FDI_RX_CTL(pipe); | |
3738 | temp = I915_READ(reg); | |
3739 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3740 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3741 | I915_WRITE(reg, temp); |
3742 | ||
3743 | POSTING_READ(reg); | |
139ccd3f | 3744 | udelay(2); /* should be 1.5us */ |
357555c0 | 3745 | |
139ccd3f JB |
3746 | for (i = 0; i < 4; i++) { |
3747 | reg = FDI_RX_IIR(pipe); | |
3748 | temp = I915_READ(reg); | |
3749 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3750 | |
139ccd3f JB |
3751 | if (temp & FDI_RX_SYMBOL_LOCK || |
3752 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3753 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3754 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3755 | i); | |
3756 | goto train_done; | |
3757 | } | |
3758 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3759 | } |
139ccd3f JB |
3760 | if (i == 4) |
3761 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3762 | } |
357555c0 | 3763 | |
139ccd3f | 3764 | train_done: |
357555c0 JB |
3765 | DRM_DEBUG_KMS("FDI train done.\n"); |
3766 | } | |
3767 | ||
88cefb6c | 3768 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3769 | { |
88cefb6c | 3770 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3771 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3772 | int pipe = intel_crtc->pipe; |
5eddb70b | 3773 | u32 reg, temp; |
79e53945 | 3774 | |
c64e311e | 3775 | |
c98e9dcf | 3776 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3777 | reg = FDI_RX_CTL(pipe); |
3778 | temp = I915_READ(reg); | |
627eb5a3 | 3779 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3780 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3781 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3782 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3783 | ||
3784 | POSTING_READ(reg); | |
c98e9dcf JB |
3785 | udelay(200); |
3786 | ||
3787 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3788 | temp = I915_READ(reg); |
3789 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3790 | ||
3791 | POSTING_READ(reg); | |
c98e9dcf JB |
3792 | udelay(200); |
3793 | ||
20749730 PZ |
3794 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3795 | reg = FDI_TX_CTL(pipe); | |
3796 | temp = I915_READ(reg); | |
3797 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3798 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3799 | |
20749730 PZ |
3800 | POSTING_READ(reg); |
3801 | udelay(100); | |
6be4a607 | 3802 | } |
0e23b99d JB |
3803 | } |
3804 | ||
88cefb6c DV |
3805 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3806 | { | |
3807 | struct drm_device *dev = intel_crtc->base.dev; | |
3808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3809 | int pipe = intel_crtc->pipe; | |
3810 | u32 reg, temp; | |
3811 | ||
3812 | /* Switch from PCDclk to Rawclk */ | |
3813 | reg = FDI_RX_CTL(pipe); | |
3814 | temp = I915_READ(reg); | |
3815 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3816 | ||
3817 | /* Disable CPU FDI TX PLL */ | |
3818 | reg = FDI_TX_CTL(pipe); | |
3819 | temp = I915_READ(reg); | |
3820 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3821 | ||
3822 | POSTING_READ(reg); | |
3823 | udelay(100); | |
3824 | ||
3825 | reg = FDI_RX_CTL(pipe); | |
3826 | temp = I915_READ(reg); | |
3827 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3828 | ||
3829 | /* Wait for the clocks to turn off. */ | |
3830 | POSTING_READ(reg); | |
3831 | udelay(100); | |
3832 | } | |
3833 | ||
0fc932b8 JB |
3834 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3835 | { | |
3836 | struct drm_device *dev = crtc->dev; | |
3837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3838 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3839 | int pipe = intel_crtc->pipe; | |
3840 | u32 reg, temp; | |
3841 | ||
3842 | /* disable CPU FDI tx and PCH FDI rx */ | |
3843 | reg = FDI_TX_CTL(pipe); | |
3844 | temp = I915_READ(reg); | |
3845 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3846 | POSTING_READ(reg); | |
3847 | ||
3848 | reg = FDI_RX_CTL(pipe); | |
3849 | temp = I915_READ(reg); | |
3850 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3851 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3852 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3853 | ||
3854 | POSTING_READ(reg); | |
3855 | udelay(100); | |
3856 | ||
3857 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3858 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3859 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3860 | |
3861 | /* still set train pattern 1 */ | |
3862 | reg = FDI_TX_CTL(pipe); | |
3863 | temp = I915_READ(reg); | |
3864 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3865 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3866 | I915_WRITE(reg, temp); | |
3867 | ||
3868 | reg = FDI_RX_CTL(pipe); | |
3869 | temp = I915_READ(reg); | |
3870 | if (HAS_PCH_CPT(dev)) { | |
3871 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3872 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3873 | } else { | |
3874 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3875 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3876 | } | |
3877 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3878 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3879 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3880 | I915_WRITE(reg, temp); |
3881 | ||
3882 | POSTING_READ(reg); | |
3883 | udelay(100); | |
3884 | } | |
3885 | ||
5dce5b93 CW |
3886 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3887 | { | |
3888 | struct intel_crtc *crtc; | |
3889 | ||
3890 | /* Note that we don't need to be called with mode_config.lock here | |
3891 | * as our list of CRTC objects is static for the lifetime of the | |
3892 | * device and so cannot disappear as we iterate. Similarly, we can | |
3893 | * happily treat the predicates as racy, atomic checks as userspace | |
3894 | * cannot claim and pin a new fb without at least acquring the | |
3895 | * struct_mutex and so serialising with us. | |
3896 | */ | |
d3fcc808 | 3897 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3898 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3899 | continue; | |
3900 | ||
3901 | if (crtc->unpin_work) | |
3902 | intel_wait_for_vblank(dev, crtc->pipe); | |
3903 | ||
3904 | return true; | |
3905 | } | |
3906 | ||
3907 | return false; | |
3908 | } | |
3909 | ||
d6bbafa1 CW |
3910 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3911 | { | |
3912 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3913 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3914 | ||
3915 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3916 | smp_rmb(); | |
3917 | intel_crtc->unpin_work = NULL; | |
3918 | ||
3919 | if (work->event) | |
3920 | drm_send_vblank_event(intel_crtc->base.dev, | |
3921 | intel_crtc->pipe, | |
3922 | work->event); | |
3923 | ||
3924 | drm_crtc_vblank_put(&intel_crtc->base); | |
3925 | ||
3926 | wake_up_all(&dev_priv->pending_flip_queue); | |
3927 | queue_work(dev_priv->wq, &work->work); | |
3928 | ||
3929 | trace_i915_flip_complete(intel_crtc->plane, | |
3930 | work->pending_flip_obj); | |
3931 | } | |
3932 | ||
46a55d30 | 3933 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3934 | { |
0f91128d | 3935 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3936 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3937 | |
2c10d571 | 3938 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3939 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3940 | !intel_crtc_has_pending_flip(crtc), | |
3941 | 60*HZ) == 0)) { | |
3942 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3943 | |
5e2d7afc | 3944 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3945 | if (intel_crtc->unpin_work) { |
3946 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3947 | page_flip_completed(intel_crtc); | |
3948 | } | |
5e2d7afc | 3949 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3950 | } |
5bb61643 | 3951 | |
975d568a CW |
3952 | if (crtc->primary->fb) { |
3953 | mutex_lock(&dev->struct_mutex); | |
3954 | intel_finish_fb(crtc->primary->fb); | |
3955 | mutex_unlock(&dev->struct_mutex); | |
3956 | } | |
e6c3a2a6 CW |
3957 | } |
3958 | ||
e615efe4 ED |
3959 | /* Program iCLKIP clock to the desired frequency */ |
3960 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3961 | { | |
3962 | struct drm_device *dev = crtc->dev; | |
3963 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3964 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3965 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3966 | u32 temp; | |
3967 | ||
09153000 DV |
3968 | mutex_lock(&dev_priv->dpio_lock); |
3969 | ||
e615efe4 ED |
3970 | /* It is necessary to ungate the pixclk gate prior to programming |
3971 | * the divisors, and gate it back when it is done. | |
3972 | */ | |
3973 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3974 | ||
3975 | /* Disable SSCCTL */ | |
3976 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3977 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3978 | SBI_SSCCTL_DISABLE, | |
3979 | SBI_ICLK); | |
e615efe4 ED |
3980 | |
3981 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3982 | if (clock == 20000) { |
e615efe4 ED |
3983 | auxdiv = 1; |
3984 | divsel = 0x41; | |
3985 | phaseinc = 0x20; | |
3986 | } else { | |
3987 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3988 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3989 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3990 | * convert the virtual clock precision to KHz here for higher |
3991 | * precision. | |
3992 | */ | |
3993 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3994 | u32 iclk_pi_range = 64; | |
3995 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3996 | ||
12d7ceed | 3997 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3998 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3999 | pi_value = desired_divisor % iclk_pi_range; | |
4000 | ||
4001 | auxdiv = 0; | |
4002 | divsel = msb_divisor_value - 2; | |
4003 | phaseinc = pi_value; | |
4004 | } | |
4005 | ||
4006 | /* This should not happen with any sane values */ | |
4007 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4008 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4009 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4010 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4011 | ||
4012 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4013 | clock, |
e615efe4 ED |
4014 | auxdiv, |
4015 | divsel, | |
4016 | phasedir, | |
4017 | phaseinc); | |
4018 | ||
4019 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 4020 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4021 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4022 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4023 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4024 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4025 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4026 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4027 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4028 | |
4029 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4030 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4031 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4032 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4033 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4034 | |
4035 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4036 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4037 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4038 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
4039 | |
4040 | /* Wait for initialization time */ | |
4041 | udelay(24); | |
4042 | ||
4043 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
4044 | |
4045 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
4046 | } |
4047 | ||
275f01b2 DV |
4048 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4049 | enum pipe pch_transcoder) | |
4050 | { | |
4051 | struct drm_device *dev = crtc->base.dev; | |
4052 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4053 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4054 | |
4055 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4056 | I915_READ(HTOTAL(cpu_transcoder))); | |
4057 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4058 | I915_READ(HBLANK(cpu_transcoder))); | |
4059 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4060 | I915_READ(HSYNC(cpu_transcoder))); | |
4061 | ||
4062 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4063 | I915_READ(VTOTAL(cpu_transcoder))); | |
4064 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4065 | I915_READ(VBLANK(cpu_transcoder))); | |
4066 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4067 | I915_READ(VSYNC(cpu_transcoder))); | |
4068 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4069 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4070 | } | |
4071 | ||
003632d9 | 4072 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4073 | { |
4074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4075 | uint32_t temp; | |
4076 | ||
4077 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4078 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4079 | return; |
4080 | ||
4081 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4082 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4083 | ||
003632d9 ACO |
4084 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4085 | if (enable) | |
4086 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4087 | ||
4088 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4089 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4090 | POSTING_READ(SOUTH_CHICKEN1); | |
4091 | } | |
4092 | ||
4093 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4094 | { | |
4095 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4096 | |
4097 | switch (intel_crtc->pipe) { | |
4098 | case PIPE_A: | |
4099 | break; | |
4100 | case PIPE_B: | |
6e3c9717 | 4101 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4102 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4103 | else |
003632d9 | 4104 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4105 | |
4106 | break; | |
4107 | case PIPE_C: | |
003632d9 | 4108 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4109 | |
4110 | break; | |
4111 | default: | |
4112 | BUG(); | |
4113 | } | |
4114 | } | |
4115 | ||
f67a559d JB |
4116 | /* |
4117 | * Enable PCH resources required for PCH ports: | |
4118 | * - PCH PLLs | |
4119 | * - FDI training & RX/TX | |
4120 | * - update transcoder timings | |
4121 | * - DP transcoding bits | |
4122 | * - transcoder | |
4123 | */ | |
4124 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4125 | { |
4126 | struct drm_device *dev = crtc->dev; | |
4127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4128 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4129 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4130 | u32 reg, temp; |
2c07245f | 4131 | |
ab9412ba | 4132 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4133 | |
1fbc0d78 DV |
4134 | if (IS_IVYBRIDGE(dev)) |
4135 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4136 | ||
cd986abb DV |
4137 | /* Write the TU size bits before fdi link training, so that error |
4138 | * detection works. */ | |
4139 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4140 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4141 | ||
c98e9dcf | 4142 | /* For PCH output, training FDI link */ |
674cf967 | 4143 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4144 | |
3ad8a208 DV |
4145 | /* We need to program the right clock selection before writing the pixel |
4146 | * mutliplier into the DPLL. */ | |
303b81e0 | 4147 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4148 | u32 sel; |
4b645f14 | 4149 | |
c98e9dcf | 4150 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4151 | temp |= TRANS_DPLL_ENABLE(pipe); |
4152 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4153 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4154 | temp |= sel; |
4155 | else | |
4156 | temp &= ~sel; | |
c98e9dcf | 4157 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4158 | } |
5eddb70b | 4159 | |
3ad8a208 DV |
4160 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4161 | * transcoder, and we actually should do this to not upset any PCH | |
4162 | * transcoder that already use the clock when we share it. | |
4163 | * | |
4164 | * Note that enable_shared_dpll tries to do the right thing, but | |
4165 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4166 | * the right LVDS enable sequence. */ | |
85b3894f | 4167 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4168 | |
d9b6cb56 JB |
4169 | /* set transcoder timing, panel must allow it */ |
4170 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4171 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4172 | |
303b81e0 | 4173 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4174 | |
c98e9dcf | 4175 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4176 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4177 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4178 | reg = TRANS_DP_CTL(pipe); |
4179 | temp = I915_READ(reg); | |
4180 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4181 | TRANS_DP_SYNC_MASK | |
4182 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
4183 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
4184 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 4185 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4186 | |
4187 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4188 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4189 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4190 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4191 | |
4192 | switch (intel_trans_dp_port_sel(crtc)) { | |
4193 | case PCH_DP_B: | |
5eddb70b | 4194 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4195 | break; |
4196 | case PCH_DP_C: | |
5eddb70b | 4197 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4198 | break; |
4199 | case PCH_DP_D: | |
5eddb70b | 4200 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4201 | break; |
4202 | default: | |
e95d41e1 | 4203 | BUG(); |
32f9d658 | 4204 | } |
2c07245f | 4205 | |
5eddb70b | 4206 | I915_WRITE(reg, temp); |
6be4a607 | 4207 | } |
b52eb4dc | 4208 | |
b8a4f404 | 4209 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4210 | } |
4211 | ||
1507e5bd PZ |
4212 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4213 | { | |
4214 | struct drm_device *dev = crtc->dev; | |
4215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4216 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4217 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4218 | |
ab9412ba | 4219 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4220 | |
8c52b5e8 | 4221 | lpt_program_iclkip(crtc); |
1507e5bd | 4222 | |
0540e488 | 4223 | /* Set transcoder timing. */ |
275f01b2 | 4224 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4225 | |
937bb610 | 4226 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4227 | } |
4228 | ||
716c2e55 | 4229 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4230 | { |
e2b78267 | 4231 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4232 | |
4233 | if (pll == NULL) | |
4234 | return; | |
4235 | ||
3e369b76 | 4236 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4237 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4238 | return; |
4239 | } | |
4240 | ||
3e369b76 ACO |
4241 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4242 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4243 | WARN_ON(pll->on); |
4244 | WARN_ON(pll->active); | |
4245 | } | |
4246 | ||
6e3c9717 | 4247 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4248 | } |
4249 | ||
190f68c5 ACO |
4250 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4251 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4252 | { |
e2b78267 | 4253 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4254 | struct intel_shared_dpll *pll; |
e2b78267 | 4255 | enum intel_dpll_id i; |
ee7b9f93 | 4256 | |
98b6bd99 DV |
4257 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4258 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4259 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4260 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4261 | |
46edb027 DV |
4262 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4263 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4264 | |
8bd31e67 | 4265 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4266 | |
98b6bd99 DV |
4267 | goto found; |
4268 | } | |
4269 | ||
bcddf610 S |
4270 | if (IS_BROXTON(dev_priv->dev)) { |
4271 | /* PLL is attached to port in bxt */ | |
4272 | struct intel_encoder *encoder; | |
4273 | struct intel_digital_port *intel_dig_port; | |
4274 | ||
4275 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4276 | if (WARN_ON(!encoder)) | |
4277 | return NULL; | |
4278 | ||
4279 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4280 | /* 1:1 mapping between ports and PLLs */ | |
4281 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4282 | pll = &dev_priv->shared_dplls[i]; | |
4283 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4284 | crtc->base.base.id, pll->name); | |
4285 | WARN_ON(pll->new_config->crtc_mask); | |
4286 | ||
4287 | goto found; | |
4288 | } | |
4289 | ||
e72f9fbf DV |
4290 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4291 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4292 | |
4293 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4294 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4295 | continue; |
4296 | ||
190f68c5 | 4297 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4298 | &pll->new_config->hw_state, |
4299 | sizeof(pll->new_config->hw_state)) == 0) { | |
4300 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4301 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4302 | pll->new_config->crtc_mask, |
4303 | pll->active); | |
ee7b9f93 JB |
4304 | goto found; |
4305 | } | |
4306 | } | |
4307 | ||
4308 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4309 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4310 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4311 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4312 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4313 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4314 | goto found; |
4315 | } | |
4316 | } | |
4317 | ||
4318 | return NULL; | |
4319 | ||
4320 | found: | |
8bd31e67 | 4321 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4322 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4323 | |
190f68c5 | 4324 | crtc_state->shared_dpll = i; |
46edb027 DV |
4325 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4326 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4327 | |
8bd31e67 | 4328 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4329 | |
ee7b9f93 JB |
4330 | return pll; |
4331 | } | |
4332 | ||
8bd31e67 ACO |
4333 | /** |
4334 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4335 | * @dev_priv: DRM device | |
4336 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4337 | * | |
4338 | * Starts a new PLL staged config, copying the current config but | |
4339 | * releasing the references of pipes specified in clear_pipes. | |
4340 | */ | |
4341 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4342 | unsigned clear_pipes) | |
4343 | { | |
4344 | struct intel_shared_dpll *pll; | |
4345 | enum intel_dpll_id i; | |
4346 | ||
4347 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4348 | pll = &dev_priv->shared_dplls[i]; | |
4349 | ||
4350 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4351 | GFP_KERNEL); | |
4352 | if (!pll->new_config) | |
4353 | goto cleanup; | |
4354 | ||
4355 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4356 | } | |
4357 | ||
4358 | return 0; | |
4359 | ||
4360 | cleanup: | |
4361 | while (--i >= 0) { | |
4362 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4363 | kfree(pll->new_config); |
8bd31e67 ACO |
4364 | pll->new_config = NULL; |
4365 | } | |
4366 | ||
4367 | return -ENOMEM; | |
4368 | } | |
4369 | ||
4370 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4371 | { | |
4372 | struct intel_shared_dpll *pll; | |
4373 | enum intel_dpll_id i; | |
4374 | ||
4375 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4376 | pll = &dev_priv->shared_dplls[i]; | |
4377 | ||
4378 | WARN_ON(pll->new_config == &pll->config); | |
4379 | ||
4380 | pll->config = *pll->new_config; | |
4381 | kfree(pll->new_config); | |
4382 | pll->new_config = NULL; | |
4383 | } | |
4384 | } | |
4385 | ||
4386 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4387 | { | |
4388 | struct intel_shared_dpll *pll; | |
4389 | enum intel_dpll_id i; | |
4390 | ||
4391 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4392 | pll = &dev_priv->shared_dplls[i]; | |
4393 | ||
4394 | WARN_ON(pll->new_config == &pll->config); | |
4395 | ||
4396 | kfree(pll->new_config); | |
4397 | pll->new_config = NULL; | |
4398 | } | |
4399 | } | |
4400 | ||
a1520318 | 4401 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4402 | { |
4403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4404 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4405 | u32 temp; |
4406 | ||
4407 | temp = I915_READ(dslreg); | |
4408 | udelay(500); | |
4409 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4410 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4411 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4412 | } |
4413 | } | |
4414 | ||
a1b2278e CK |
4415 | /** |
4416 | * skl_update_scaler_users - Stages update to crtc's scaler state | |
4417 | * @intel_crtc: crtc | |
4418 | * @crtc_state: crtc_state | |
4419 | * @plane: plane (NULL indicates crtc is requesting update) | |
4420 | * @plane_state: plane's state | |
4421 | * @force_detach: request unconditional detachment of scaler | |
4422 | * | |
4423 | * This function updates scaler state for requested plane or crtc. | |
4424 | * To request scaler usage update for a plane, caller shall pass plane pointer. | |
4425 | * To request scaler usage update for crtc, caller shall pass plane pointer | |
4426 | * as NULL. | |
4427 | * | |
4428 | * Return | |
4429 | * 0 - scaler_usage updated successfully | |
4430 | * error - requested scaling cannot be supported or other error condition | |
4431 | */ | |
4432 | int | |
4433 | skl_update_scaler_users( | |
4434 | struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, | |
4435 | struct intel_plane *intel_plane, struct intel_plane_state *plane_state, | |
4436 | int force_detach) | |
4437 | { | |
4438 | int need_scaling; | |
4439 | int idx; | |
4440 | int src_w, src_h, dst_w, dst_h; | |
4441 | int *scaler_id; | |
4442 | struct drm_framebuffer *fb; | |
4443 | struct intel_crtc_scaler_state *scaler_state; | |
6156a456 | 4444 | unsigned int rotation; |
a1b2278e CK |
4445 | |
4446 | if (!intel_crtc || !crtc_state) | |
4447 | return 0; | |
4448 | ||
4449 | scaler_state = &crtc_state->scaler_state; | |
4450 | ||
4451 | idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX; | |
4452 | fb = intel_plane ? plane_state->base.fb : NULL; | |
4453 | ||
4454 | if (intel_plane) { | |
4455 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
4456 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
4457 | dst_w = drm_rect_width(&plane_state->dst); | |
4458 | dst_h = drm_rect_height(&plane_state->dst); | |
4459 | scaler_id = &plane_state->scaler_id; | |
6156a456 | 4460 | rotation = plane_state->base.rotation; |
a1b2278e CK |
4461 | } else { |
4462 | struct drm_display_mode *adjusted_mode = | |
4463 | &crtc_state->base.adjusted_mode; | |
4464 | src_w = crtc_state->pipe_src_w; | |
4465 | src_h = crtc_state->pipe_src_h; | |
4466 | dst_w = adjusted_mode->hdisplay; | |
4467 | dst_h = adjusted_mode->vdisplay; | |
4468 | scaler_id = &scaler_state->scaler_id; | |
6156a456 | 4469 | rotation = DRM_ROTATE_0; |
a1b2278e | 4470 | } |
6156a456 CK |
4471 | |
4472 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4473 | (src_h != dst_w || src_w != dst_h): | |
4474 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4475 | |
4476 | /* | |
4477 | * if plane is being disabled or scaler is no more required or force detach | |
4478 | * - free scaler binded to this plane/crtc | |
4479 | * - in order to do this, update crtc->scaler_usage | |
4480 | * | |
4481 | * Here scaler state in crtc_state is set free so that | |
4482 | * scaler can be assigned to other user. Actual register | |
4483 | * update to free the scaler is done in plane/panel-fit programming. | |
4484 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4485 | */ | |
4486 | if (force_detach || !need_scaling || (intel_plane && | |
4487 | (!fb || !plane_state->visible))) { | |
4488 | if (*scaler_id >= 0) { | |
4489 | scaler_state->scaler_users &= ~(1 << idx); | |
4490 | scaler_state->scalers[*scaler_id].in_use = 0; | |
4491 | ||
4492 | DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d " | |
4493 | "crtc_state = %p scaler_users = 0x%x\n", | |
4494 | intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC", | |
4495 | intel_plane ? intel_plane->base.base.id : | |
4496 | intel_crtc->base.base.id, crtc_state, | |
4497 | scaler_state->scaler_users); | |
4498 | *scaler_id = -1; | |
4499 | } | |
4500 | return 0; | |
4501 | } | |
4502 | ||
4503 | /* range checks */ | |
4504 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4505 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4506 | ||
4507 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4508 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
4509 | DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u " | |
4510 | "size is out of scaler range\n", | |
4511 | intel_plane ? "PLANE" : "CRTC", | |
4512 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4513 | intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h); | |
4514 | return -EINVAL; | |
4515 | } | |
4516 | ||
4517 | /* check colorkey */ | |
4518 | if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) { | |
4519 | DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed", | |
4520 | intel_plane->base.base.id); | |
4521 | return -EINVAL; | |
4522 | } | |
4523 | ||
4524 | /* Check src format */ | |
4525 | if (intel_plane) { | |
4526 | switch (fb->pixel_format) { | |
4527 | case DRM_FORMAT_RGB565: | |
4528 | case DRM_FORMAT_XBGR8888: | |
4529 | case DRM_FORMAT_XRGB8888: | |
4530 | case DRM_FORMAT_ABGR8888: | |
4531 | case DRM_FORMAT_ARGB8888: | |
4532 | case DRM_FORMAT_XRGB2101010: | |
4533 | case DRM_FORMAT_ARGB2101010: | |
4534 | case DRM_FORMAT_XBGR2101010: | |
4535 | case DRM_FORMAT_ABGR2101010: | |
4536 | case DRM_FORMAT_YUYV: | |
4537 | case DRM_FORMAT_YVYU: | |
4538 | case DRM_FORMAT_UYVY: | |
4539 | case DRM_FORMAT_VYUY: | |
4540 | break; | |
4541 | default: | |
4542 | DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n", | |
4543 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4544 | return -EINVAL; | |
4545 | } | |
4546 | } | |
4547 | ||
4548 | /* mark this plane as a scaler user in crtc_state */ | |
4549 | scaler_state->scaler_users |= (1 << idx); | |
4550 | DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u " | |
4551 | "crtc_state = %p scaler_users = 0x%x\n", | |
4552 | intel_plane ? "PLANE" : "CRTC", | |
4553 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4554 | src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users); | |
4555 | return 0; | |
4556 | } | |
4557 | ||
4558 | static void skylake_pfit_update(struct intel_crtc *crtc, int enable) | |
bd2e244f JB |
4559 | { |
4560 | struct drm_device *dev = crtc->base.dev; | |
4561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4562 | int pipe = crtc->pipe; | |
a1b2278e CK |
4563 | struct intel_crtc_scaler_state *scaler_state = |
4564 | &crtc->config->scaler_state; | |
4565 | ||
4566 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4567 | ||
4568 | /* To update pfit, first update scaler state */ | |
4569 | skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable); | |
4570 | intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config); | |
4571 | skl_detach_scalers(crtc); | |
4572 | if (!enable) | |
4573 | return; | |
bd2e244f | 4574 | |
6e3c9717 | 4575 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4576 | int id; |
4577 | ||
4578 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4579 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4580 | return; | |
4581 | } | |
4582 | ||
4583 | id = scaler_state->scaler_id; | |
4584 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4585 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4586 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4587 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4588 | ||
4589 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4590 | } |
4591 | } | |
4592 | ||
b074cec8 JB |
4593 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4594 | { | |
4595 | struct drm_device *dev = crtc->base.dev; | |
4596 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4597 | int pipe = crtc->pipe; | |
4598 | ||
6e3c9717 | 4599 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4600 | /* Force use of hard-coded filter coefficients |
4601 | * as some pre-programmed values are broken, | |
4602 | * e.g. x201. | |
4603 | */ | |
4604 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4605 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4606 | PF_PIPE_SEL_IVB(pipe)); | |
4607 | else | |
4608 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4609 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4610 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4611 | } |
4612 | } | |
4613 | ||
4a3b8769 | 4614 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4615 | { |
4616 | struct drm_device *dev = crtc->dev; | |
4617 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4618 | struct drm_plane *plane; |
bb53d4ae VS |
4619 | struct intel_plane *intel_plane; |
4620 | ||
af2b653b MR |
4621 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4622 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4623 | if (intel_plane->pipe == pipe) |
4624 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4625 | } |
bb53d4ae VS |
4626 | } |
4627 | ||
20bc8673 | 4628 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4629 | { |
cea165c3 VS |
4630 | struct drm_device *dev = crtc->base.dev; |
4631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4632 | |
6e3c9717 | 4633 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4634 | return; |
4635 | ||
cea165c3 VS |
4636 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4637 | intel_wait_for_vblank(dev, crtc->pipe); | |
4638 | ||
d77e4531 | 4639 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4640 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4641 | mutex_lock(&dev_priv->rps.hw_lock); |
4642 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4643 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4644 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4645 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4646 | * mailbox." Moreover, the mailbox may return a bogus state, |
4647 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4648 | */ |
4649 | } else { | |
4650 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4651 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4652 | * is essentially intel_wait_for_vblank. If we don't have this | |
4653 | * and don't wait for vblanks until the end of crtc_enable, then | |
4654 | * the HW state readout code will complain that the expected | |
4655 | * IPS_CTL value is not the one we read. */ | |
4656 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4657 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4658 | } | |
d77e4531 PZ |
4659 | } |
4660 | ||
20bc8673 | 4661 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4662 | { |
4663 | struct drm_device *dev = crtc->base.dev; | |
4664 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4665 | ||
6e3c9717 | 4666 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4667 | return; |
4668 | ||
4669 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4670 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4671 | mutex_lock(&dev_priv->rps.hw_lock); |
4672 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4673 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4674 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4675 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4676 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4677 | } else { |
2a114cc1 | 4678 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4679 | POSTING_READ(IPS_CTL); |
4680 | } | |
d77e4531 PZ |
4681 | |
4682 | /* We need to wait for a vblank before we can disable the plane. */ | |
4683 | intel_wait_for_vblank(dev, crtc->pipe); | |
4684 | } | |
4685 | ||
4686 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4687 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4688 | { | |
4689 | struct drm_device *dev = crtc->dev; | |
4690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4691 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4692 | enum pipe pipe = intel_crtc->pipe; | |
4693 | int palreg = PALETTE(pipe); | |
4694 | int i; | |
4695 | bool reenable_ips = false; | |
4696 | ||
4697 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4698 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4699 | return; |
4700 | ||
50360403 | 4701 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
409ee761 | 4702 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4703 | assert_dsi_pll_enabled(dev_priv); |
4704 | else | |
4705 | assert_pll_enabled(dev_priv, pipe); | |
4706 | } | |
4707 | ||
4708 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4709 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4710 | palreg = LGC_PALETTE(pipe); |
4711 | ||
4712 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4713 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4714 | */ | |
6e3c9717 | 4715 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4716 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4717 | GAMMA_MODE_MODE_SPLIT)) { | |
4718 | hsw_disable_ips(intel_crtc); | |
4719 | reenable_ips = true; | |
4720 | } | |
4721 | ||
4722 | for (i = 0; i < 256; i++) { | |
4723 | I915_WRITE(palreg + 4 * i, | |
4724 | (intel_crtc->lut_r[i] << 16) | | |
4725 | (intel_crtc->lut_g[i] << 8) | | |
4726 | intel_crtc->lut_b[i]); | |
4727 | } | |
4728 | ||
4729 | if (reenable_ips) | |
4730 | hsw_enable_ips(intel_crtc); | |
4731 | } | |
4732 | ||
7cac945f | 4733 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4734 | { |
7cac945f | 4735 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4736 | struct drm_device *dev = intel_crtc->base.dev; |
4737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4738 | ||
4739 | mutex_lock(&dev->struct_mutex); | |
4740 | dev_priv->mm.interruptible = false; | |
4741 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4742 | dev_priv->mm.interruptible = true; | |
4743 | mutex_unlock(&dev->struct_mutex); | |
4744 | } | |
4745 | ||
4746 | /* Let userspace switch the overlay on again. In most cases userspace | |
4747 | * has to recompute where to put it anyway. | |
4748 | */ | |
4749 | } | |
4750 | ||
87d4300a ML |
4751 | /** |
4752 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4753 | * @crtc: the CRTC whose primary plane was just enabled | |
4754 | * | |
4755 | * Performs potentially sleeping operations that must be done after the primary | |
4756 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4757 | * called due to an explicit primary plane update, or due to an implicit | |
4758 | * re-enable that is caused when a sprite plane is updated to no longer | |
4759 | * completely hide the primary plane. | |
4760 | */ | |
4761 | static void | |
4762 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4763 | { |
4764 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4765 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4767 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4768 | |
87d4300a ML |
4769 | /* |
4770 | * BDW signals flip done immediately if the plane | |
4771 | * is disabled, even if the plane enable is already | |
4772 | * armed to occur at the next vblank :( | |
4773 | */ | |
4774 | if (IS_BROADWELL(dev)) | |
4775 | intel_wait_for_vblank(dev, pipe); | |
a5c4d7bc | 4776 | |
87d4300a ML |
4777 | /* |
4778 | * FIXME IPS should be fine as long as one plane is | |
4779 | * enabled, but in practice it seems to have problems | |
4780 | * when going from primary only to sprite only and vice | |
4781 | * versa. | |
4782 | */ | |
a5c4d7bc VS |
4783 | hsw_enable_ips(intel_crtc); |
4784 | ||
4785 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4786 | intel_fbc_update(dev); |
a5c4d7bc | 4787 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4788 | |
4789 | /* | |
87d4300a ML |
4790 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4791 | * So don't enable underrun reporting before at least some planes | |
4792 | * are enabled. | |
4793 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4794 | * but leave the pipe running. | |
f99d7069 | 4795 | */ |
87d4300a ML |
4796 | if (IS_GEN2(dev)) |
4797 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4798 | ||
4799 | /* Underruns don't raise interrupts, so check manually. */ | |
4800 | if (HAS_GMCH_DISPLAY(dev)) | |
4801 | i9xx_check_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4802 | } |
4803 | ||
87d4300a ML |
4804 | /** |
4805 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4806 | * @crtc: the CRTC whose primary plane is to be disabled | |
4807 | * | |
4808 | * Performs potentially sleeping operations that must be done before the | |
4809 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4810 | * be called due to an explicit primary plane update, or due to an implicit | |
4811 | * disable that is caused when a sprite plane completely hides the primary | |
4812 | * plane. | |
4813 | */ | |
4814 | static void | |
4815 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4816 | { |
4817 | struct drm_device *dev = crtc->dev; | |
4818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4819 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4820 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4821 | |
87d4300a ML |
4822 | /* |
4823 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4824 | * So diasble underrun reporting before all the planes get disabled. | |
4825 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4826 | * but leave the pipe running. | |
4827 | */ | |
4828 | if (IS_GEN2(dev)) | |
4829 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4830 | |
87d4300a ML |
4831 | /* |
4832 | * Vblank time updates from the shadow to live plane control register | |
4833 | * are blocked if the memory self-refresh mode is active at that | |
4834 | * moment. So to make sure the plane gets truly disabled, disable | |
4835 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4836 | * will be checked/applied by the HW only at the next frame start | |
4837 | * event which is after the vblank start event, so we need to have a | |
4838 | * wait-for-vblank between disabling the plane and the pipe. | |
4839 | */ | |
4840 | if (HAS_GMCH_DISPLAY(dev)) | |
4841 | intel_set_memory_cxsr(dev_priv, false); | |
4842 | ||
4843 | mutex_lock(&dev->struct_mutex); | |
e35fef21 | 4844 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4845 | intel_fbc_disable(dev); |
87d4300a | 4846 | mutex_unlock(&dev->struct_mutex); |
a5c4d7bc | 4847 | |
87d4300a ML |
4848 | /* |
4849 | * FIXME IPS should be fine as long as one plane is | |
4850 | * enabled, but in practice it seems to have problems | |
4851 | * when going from primary only to sprite only and vice | |
4852 | * versa. | |
4853 | */ | |
a5c4d7bc | 4854 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4855 | } |
4856 | ||
4857 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
4858 | { | |
87d4300a ML |
4859 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4860 | intel_enable_sprite_planes(crtc); | |
4861 | intel_crtc_update_cursor(crtc, true); | |
87d4300a ML |
4862 | |
4863 | intel_post_enable_primary(crtc); | |
4864 | } | |
4865 | ||
4866 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) | |
4867 | { | |
4868 | struct drm_device *dev = crtc->dev; | |
4869 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4870 | struct intel_plane *intel_plane; | |
4871 | int pipe = intel_crtc->pipe; | |
4872 | ||
4873 | intel_crtc_wait_for_pending_flips(crtc); | |
4874 | ||
4875 | intel_pre_disable_primary(crtc); | |
a5c4d7bc | 4876 | |
7cac945f | 4877 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 ML |
4878 | for_each_intel_plane(dev, intel_plane) { |
4879 | if (intel_plane->pipe == pipe) { | |
4880 | struct drm_crtc *from = intel_plane->base.crtc; | |
4881 | ||
4882 | intel_plane->disable_plane(&intel_plane->base, | |
4883 | from ?: crtc, true); | |
4884 | } | |
4885 | } | |
f98551ae | 4886 | |
f99d7069 DV |
4887 | /* |
4888 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4889 | * to compute the mask of flip planes precisely. For the time being | |
4890 | * consider this a flip to a NULL plane. | |
4891 | */ | |
4892 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4893 | } |
4894 | ||
f67a559d JB |
4895 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4896 | { | |
4897 | struct drm_device *dev = crtc->dev; | |
4898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4899 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4900 | struct intel_encoder *encoder; |
f67a559d | 4901 | int pipe = intel_crtc->pipe; |
f67a559d | 4902 | |
83d65738 | 4903 | WARN_ON(!crtc->state->enable); |
08a48469 | 4904 | |
f67a559d JB |
4905 | if (intel_crtc->active) |
4906 | return; | |
4907 | ||
6e3c9717 | 4908 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4909 | intel_prepare_shared_dpll(intel_crtc); |
4910 | ||
6e3c9717 | 4911 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4912 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4913 | |
4914 | intel_set_pipe_timings(intel_crtc); | |
4915 | ||
6e3c9717 | 4916 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4917 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4918 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4919 | } |
4920 | ||
4921 | ironlake_set_pipeconf(crtc); | |
4922 | ||
f67a559d | 4923 | intel_crtc->active = true; |
8664281b | 4924 | |
a72e4c9f DV |
4925 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4926 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4927 | |
f6736a1a | 4928 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4929 | if (encoder->pre_enable) |
4930 | encoder->pre_enable(encoder); | |
f67a559d | 4931 | |
6e3c9717 | 4932 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4933 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4934 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4935 | * enabling. */ | |
88cefb6c | 4936 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4937 | } else { |
4938 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4939 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4940 | } | |
f67a559d | 4941 | |
b074cec8 | 4942 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4943 | |
9c54c0dd JB |
4944 | /* |
4945 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4946 | * clocks enabled | |
4947 | */ | |
4948 | intel_crtc_load_lut(crtc); | |
4949 | ||
f37fcc2a | 4950 | intel_update_watermarks(crtc); |
e1fdc473 | 4951 | intel_enable_pipe(intel_crtc); |
f67a559d | 4952 | |
6e3c9717 | 4953 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4954 | ironlake_pch_enable(crtc); |
c98e9dcf | 4955 | |
f9b61ff6 DV |
4956 | assert_vblank_disabled(crtc); |
4957 | drm_crtc_vblank_on(crtc); | |
4958 | ||
fa5c73b1 DV |
4959 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4960 | encoder->enable(encoder); | |
61b77ddd DV |
4961 | |
4962 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4963 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6be4a607 JB |
4964 | } |
4965 | ||
42db64ef PZ |
4966 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4967 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4968 | { | |
f5adf94e | 4969 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4970 | } |
4971 | ||
e4916946 PZ |
4972 | /* |
4973 | * This implements the workaround described in the "notes" section of the mode | |
4974 | * set sequence documentation. When going from no pipes or single pipe to | |
4975 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4976 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4977 | */ | |
4978 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4979 | { | |
4980 | struct drm_device *dev = crtc->base.dev; | |
4981 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4982 | ||
4983 | /* We want to get the other_active_crtc only if there's only 1 other | |
4984 | * active crtc. */ | |
d3fcc808 | 4985 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4986 | if (!crtc_it->active || crtc_it == crtc) |
4987 | continue; | |
4988 | ||
4989 | if (other_active_crtc) | |
4990 | return; | |
4991 | ||
4992 | other_active_crtc = crtc_it; | |
4993 | } | |
4994 | if (!other_active_crtc) | |
4995 | return; | |
4996 | ||
4997 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4998 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4999 | } | |
5000 | ||
4f771f10 PZ |
5001 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
5002 | { | |
5003 | struct drm_device *dev = crtc->dev; | |
5004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5005 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5006 | struct intel_encoder *encoder; | |
5007 | int pipe = intel_crtc->pipe; | |
4f771f10 | 5008 | |
83d65738 | 5009 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
5010 | |
5011 | if (intel_crtc->active) | |
5012 | return; | |
5013 | ||
df8ad70c DV |
5014 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
5015 | intel_enable_shared_dpll(intel_crtc); | |
5016 | ||
6e3c9717 | 5017 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5018 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
5019 | |
5020 | intel_set_pipe_timings(intel_crtc); | |
5021 | ||
6e3c9717 ACO |
5022 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
5023 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
5024 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
5025 | } |
5026 | ||
6e3c9717 | 5027 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5028 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5029 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5030 | } |
5031 | ||
5032 | haswell_set_pipeconf(crtc); | |
5033 | ||
5034 | intel_set_pipe_csc(crtc); | |
5035 | ||
4f771f10 | 5036 | intel_crtc->active = true; |
8664281b | 5037 | |
a72e4c9f | 5038 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
5039 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5040 | if (encoder->pre_enable) | |
5041 | encoder->pre_enable(encoder); | |
5042 | ||
6e3c9717 | 5043 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
5044 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5045 | true); | |
4fe9467d ID |
5046 | dev_priv->display.fdi_link_train(crtc); |
5047 | } | |
5048 | ||
1f544388 | 5049 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5050 | |
ff6d9f55 | 5051 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5052 | skylake_pfit_update(intel_crtc, 1); |
ff6d9f55 | 5053 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5054 | ironlake_pfit_enable(intel_crtc); |
ff6d9f55 JB |
5055 | else |
5056 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 PZ |
5057 | |
5058 | /* | |
5059 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5060 | * clocks enabled | |
5061 | */ | |
5062 | intel_crtc_load_lut(crtc); | |
5063 | ||
1f544388 | 5064 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 5065 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5066 | |
f37fcc2a | 5067 | intel_update_watermarks(crtc); |
e1fdc473 | 5068 | intel_enable_pipe(intel_crtc); |
42db64ef | 5069 | |
6e3c9717 | 5070 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5071 | lpt_pch_enable(crtc); |
4f771f10 | 5072 | |
6e3c9717 | 5073 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5074 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5075 | ||
f9b61ff6 DV |
5076 | assert_vblank_disabled(crtc); |
5077 | drm_crtc_vblank_on(crtc); | |
5078 | ||
8807e55b | 5079 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5080 | encoder->enable(encoder); |
8807e55b JN |
5081 | intel_opregion_notify_encoder(encoder, true); |
5082 | } | |
4f771f10 | 5083 | |
e4916946 PZ |
5084 | /* If we change the relative order between pipe/planes enabling, we need |
5085 | * to change the workaround. */ | |
5086 | haswell_mode_set_planes_workaround(intel_crtc); | |
4f771f10 PZ |
5087 | } |
5088 | ||
3f8dce3a DV |
5089 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
5090 | { | |
5091 | struct drm_device *dev = crtc->base.dev; | |
5092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5093 | int pipe = crtc->pipe; | |
5094 | ||
5095 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5096 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 5097 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5098 | I915_WRITE(PF_CTL(pipe), 0); |
5099 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5100 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5101 | } | |
5102 | } | |
5103 | ||
6be4a607 JB |
5104 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5105 | { | |
5106 | struct drm_device *dev = crtc->dev; | |
5107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5108 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5109 | struct intel_encoder *encoder; |
6be4a607 | 5110 | int pipe = intel_crtc->pipe; |
5eddb70b | 5111 | u32 reg, temp; |
b52eb4dc | 5112 | |
f7abfe8b CW |
5113 | if (!intel_crtc->active) |
5114 | return; | |
5115 | ||
ea9d758d DV |
5116 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5117 | encoder->disable(encoder); | |
5118 | ||
f9b61ff6 DV |
5119 | drm_crtc_vblank_off(crtc); |
5120 | assert_vblank_disabled(crtc); | |
5121 | ||
6e3c9717 | 5122 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 5123 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 5124 | |
575f7ab7 | 5125 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5126 | |
3f8dce3a | 5127 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 5128 | |
bf49ec8c DV |
5129 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5130 | if (encoder->post_disable) | |
5131 | encoder->post_disable(encoder); | |
2c07245f | 5132 | |
6e3c9717 | 5133 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5134 | ironlake_fdi_disable(crtc); |
913d8d11 | 5135 | |
d925c59a | 5136 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5137 | |
d925c59a DV |
5138 | if (HAS_PCH_CPT(dev)) { |
5139 | /* disable TRANS_DP_CTL */ | |
5140 | reg = TRANS_DP_CTL(pipe); | |
5141 | temp = I915_READ(reg); | |
5142 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5143 | TRANS_DP_PORT_SEL_MASK); | |
5144 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5145 | I915_WRITE(reg, temp); | |
5146 | ||
5147 | /* disable DPLL_SEL */ | |
5148 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5149 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5150 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5151 | } |
e3421a18 | 5152 | |
d925c59a | 5153 | /* disable PCH DPLL */ |
e72f9fbf | 5154 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 5155 | |
d925c59a DV |
5156 | ironlake_fdi_pll_disable(intel_crtc); |
5157 | } | |
6b383a7f | 5158 | |
f7abfe8b | 5159 | intel_crtc->active = false; |
46ba614c | 5160 | intel_update_watermarks(crtc); |
d1ebd816 BW |
5161 | |
5162 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5163 | intel_fbc_update(dev); |
d1ebd816 | 5164 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 5165 | } |
1b3c7a47 | 5166 | |
4f771f10 | 5167 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5168 | { |
4f771f10 PZ |
5169 | struct drm_device *dev = crtc->dev; |
5170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5171 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5172 | struct intel_encoder *encoder; |
6e3c9717 | 5173 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5174 | |
4f771f10 PZ |
5175 | if (!intel_crtc->active) |
5176 | return; | |
5177 | ||
8807e55b JN |
5178 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5179 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5180 | encoder->disable(encoder); |
8807e55b | 5181 | } |
4f771f10 | 5182 | |
f9b61ff6 DV |
5183 | drm_crtc_vblank_off(crtc); |
5184 | assert_vblank_disabled(crtc); | |
5185 | ||
6e3c9717 | 5186 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5187 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5188 | false); | |
575f7ab7 | 5189 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5190 | |
6e3c9717 | 5191 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5192 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5193 | ||
ad80a810 | 5194 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5195 | |
ff6d9f55 | 5196 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5197 | skylake_pfit_update(intel_crtc, 0); |
ff6d9f55 | 5198 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5199 | ironlake_pfit_disable(intel_crtc); |
ff6d9f55 JB |
5200 | else |
5201 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 | 5202 | |
1f544388 | 5203 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5204 | |
6e3c9717 | 5205 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5206 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5207 | intel_ddi_fdi_disable(crtc); |
83616634 | 5208 | } |
4f771f10 | 5209 | |
97b040aa ID |
5210 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5211 | if (encoder->post_disable) | |
5212 | encoder->post_disable(encoder); | |
5213 | ||
4f771f10 | 5214 | intel_crtc->active = false; |
46ba614c | 5215 | intel_update_watermarks(crtc); |
4f771f10 PZ |
5216 | |
5217 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5218 | intel_fbc_update(dev); |
4f771f10 | 5219 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
5220 | |
5221 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
5222 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
5223 | } |
5224 | ||
ee7b9f93 JB |
5225 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
5226 | { | |
5227 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 5228 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
5229 | } |
5230 | ||
6441ab5f | 5231 | |
2dd24552 JB |
5232 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5233 | { | |
5234 | struct drm_device *dev = crtc->base.dev; | |
5235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5236 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5237 | |
681a8504 | 5238 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5239 | return; |
5240 | ||
2dd24552 | 5241 | /* |
c0b03411 DV |
5242 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5243 | * according to register description and PRM. | |
2dd24552 | 5244 | */ |
c0b03411 DV |
5245 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5246 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5247 | |
b074cec8 JB |
5248 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5249 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5250 | |
5251 | /* Border color in case we don't scale up to the full screen. Black by | |
5252 | * default, change to something else for debugging. */ | |
5253 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5254 | } |
5255 | ||
d05410f9 DA |
5256 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5257 | { | |
5258 | switch (port) { | |
5259 | case PORT_A: | |
5260 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5261 | case PORT_B: | |
5262 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5263 | case PORT_C: | |
5264 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5265 | case PORT_D: | |
5266 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
5267 | default: | |
5268 | WARN_ON_ONCE(1); | |
5269 | return POWER_DOMAIN_PORT_OTHER; | |
5270 | } | |
5271 | } | |
5272 | ||
77d22dca ID |
5273 | #define for_each_power_domain(domain, mask) \ |
5274 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5275 | if ((1 << (domain)) & (mask)) | |
5276 | ||
319be8ae ID |
5277 | enum intel_display_power_domain |
5278 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5279 | { | |
5280 | struct drm_device *dev = intel_encoder->base.dev; | |
5281 | struct intel_digital_port *intel_dig_port; | |
5282 | ||
5283 | switch (intel_encoder->type) { | |
5284 | case INTEL_OUTPUT_UNKNOWN: | |
5285 | /* Only DDI platforms should ever use this output type */ | |
5286 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5287 | case INTEL_OUTPUT_DISPLAYPORT: | |
5288 | case INTEL_OUTPUT_HDMI: | |
5289 | case INTEL_OUTPUT_EDP: | |
5290 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5291 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5292 | case INTEL_OUTPUT_DP_MST: |
5293 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5294 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5295 | case INTEL_OUTPUT_ANALOG: |
5296 | return POWER_DOMAIN_PORT_CRT; | |
5297 | case INTEL_OUTPUT_DSI: | |
5298 | return POWER_DOMAIN_PORT_DSI; | |
5299 | default: | |
5300 | return POWER_DOMAIN_PORT_OTHER; | |
5301 | } | |
5302 | } | |
5303 | ||
5304 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5305 | { |
319be8ae ID |
5306 | struct drm_device *dev = crtc->dev; |
5307 | struct intel_encoder *intel_encoder; | |
5308 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5309 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5310 | unsigned long mask; |
5311 | enum transcoder transcoder; | |
5312 | ||
5313 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
5314 | ||
5315 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5316 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5317 | if (intel_crtc->config->pch_pfit.enabled || |
5318 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5319 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5320 | ||
319be8ae ID |
5321 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5322 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5323 | ||
77d22dca ID |
5324 | return mask; |
5325 | } | |
5326 | ||
679dacd4 | 5327 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 5328 | { |
679dacd4 | 5329 | struct drm_device *dev = state->dev; |
77d22dca ID |
5330 | struct drm_i915_private *dev_priv = dev->dev_private; |
5331 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
5332 | struct intel_crtc *crtc; | |
5333 | ||
5334 | /* | |
5335 | * First get all needed power domains, then put all unneeded, to avoid | |
5336 | * any unnecessary toggling of the power wells. | |
5337 | */ | |
d3fcc808 | 5338 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5339 | enum intel_display_power_domain domain; |
5340 | ||
83d65738 | 5341 | if (!crtc->base.state->enable) |
77d22dca ID |
5342 | continue; |
5343 | ||
319be8ae | 5344 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
5345 | |
5346 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
5347 | intel_display_power_get(dev_priv, domain); | |
5348 | } | |
5349 | ||
50f6e502 | 5350 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 5351 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 5352 | |
d3fcc808 | 5353 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5354 | enum intel_display_power_domain domain; |
5355 | ||
5356 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
5357 | intel_display_power_put(dev_priv, domain); | |
5358 | ||
5359 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
5360 | } | |
5361 | ||
5362 | intel_display_set_init_power(dev_priv, false); | |
5363 | } | |
5364 | ||
f8437dd1 VK |
5365 | void broxton_set_cdclk(struct drm_device *dev, int frequency) |
5366 | { | |
5367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5368 | uint32_t divider; | |
5369 | uint32_t ratio; | |
5370 | uint32_t current_freq; | |
5371 | int ret; | |
5372 | ||
5373 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5374 | switch (frequency) { | |
5375 | case 144000: | |
5376 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5377 | ratio = BXT_DE_PLL_RATIO(60); | |
5378 | break; | |
5379 | case 288000: | |
5380 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5381 | ratio = BXT_DE_PLL_RATIO(60); | |
5382 | break; | |
5383 | case 384000: | |
5384 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5385 | ratio = BXT_DE_PLL_RATIO(60); | |
5386 | break; | |
5387 | case 576000: | |
5388 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5389 | ratio = BXT_DE_PLL_RATIO(60); | |
5390 | break; | |
5391 | case 624000: | |
5392 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5393 | ratio = BXT_DE_PLL_RATIO(65); | |
5394 | break; | |
5395 | case 19200: | |
5396 | /* | |
5397 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5398 | * to suppress GCC warning. | |
5399 | */ | |
5400 | ratio = 0; | |
5401 | divider = 0; | |
5402 | break; | |
5403 | default: | |
5404 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5405 | ||
5406 | return; | |
5407 | } | |
5408 | ||
5409 | mutex_lock(&dev_priv->rps.hw_lock); | |
5410 | /* Inform power controller of upcoming frequency change */ | |
5411 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5412 | 0x80000000); | |
5413 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5414 | ||
5415 | if (ret) { | |
5416 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5417 | ret, frequency); | |
5418 | return; | |
5419 | } | |
5420 | ||
5421 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5422 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5423 | current_freq = current_freq * 500 + 1000; | |
5424 | ||
5425 | /* | |
5426 | * DE PLL has to be disabled when | |
5427 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5428 | * - before setting to 624MHz (PLL needs toggling) | |
5429 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5430 | */ | |
5431 | if (frequency == 19200 || frequency == 624000 || | |
5432 | current_freq == 624000) { | |
5433 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5434 | /* Timeout 200us */ | |
5435 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5436 | 1)) | |
5437 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5438 | } | |
5439 | ||
5440 | if (frequency != 19200) { | |
5441 | uint32_t val; | |
5442 | ||
5443 | val = I915_READ(BXT_DE_PLL_CTL); | |
5444 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5445 | val |= ratio; | |
5446 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5447 | ||
5448 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5449 | /* Timeout 200us */ | |
5450 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5451 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5452 | ||
5453 | val = I915_READ(CDCLK_CTL); | |
5454 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5455 | val |= divider; | |
5456 | /* | |
5457 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5458 | * enable otherwise. | |
5459 | */ | |
5460 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5461 | if (frequency >= 500000) | |
5462 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5463 | ||
5464 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5465 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5466 | val |= (frequency - 1000) / 500; | |
5467 | I915_WRITE(CDCLK_CTL, val); | |
5468 | } | |
5469 | ||
5470 | mutex_lock(&dev_priv->rps.hw_lock); | |
5471 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5472 | DIV_ROUND_UP(frequency, 25000)); | |
5473 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5474 | ||
5475 | if (ret) { | |
5476 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5477 | ret, frequency); | |
5478 | return; | |
5479 | } | |
5480 | ||
5481 | dev_priv->cdclk_freq = frequency; | |
5482 | } | |
5483 | ||
5484 | void broxton_init_cdclk(struct drm_device *dev) | |
5485 | { | |
5486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5487 | uint32_t val; | |
5488 | ||
5489 | /* | |
5490 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5491 | * or else the reset will hang because there is no PCH to respond. | |
5492 | * Move the handshake programming to initialization sequence. | |
5493 | * Previously was left up to BIOS. | |
5494 | */ | |
5495 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5496 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5497 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5498 | ||
5499 | /* Enable PG1 for cdclk */ | |
5500 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5501 | ||
5502 | /* check if cd clock is enabled */ | |
5503 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5504 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5505 | return; | |
5506 | } | |
5507 | ||
5508 | /* | |
5509 | * FIXME: | |
5510 | * - The initial CDCLK needs to be read from VBT. | |
5511 | * Need to make this change after VBT has changes for BXT. | |
5512 | * - check if setting the max (or any) cdclk freq is really necessary | |
5513 | * here, it belongs to modeset time | |
5514 | */ | |
5515 | broxton_set_cdclk(dev, 624000); | |
5516 | ||
5517 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5518 | POSTING_READ(DBUF_CTL); |
5519 | ||
f8437dd1 VK |
5520 | udelay(10); |
5521 | ||
5522 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5523 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5524 | } | |
5525 | ||
5526 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5527 | { | |
5528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5529 | ||
5530 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5531 | POSTING_READ(DBUF_CTL); |
5532 | ||
f8437dd1 VK |
5533 | udelay(10); |
5534 | ||
5535 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5536 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5537 | ||
5538 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5539 | broxton_set_cdclk(dev, 19200); | |
5540 | ||
5541 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5542 | } | |
5543 | ||
dfcab17e | 5544 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5545 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5546 | { |
586f49dc | 5547 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5548 | |
586f49dc JB |
5549 | /* Obtain SKU information */ |
5550 | mutex_lock(&dev_priv->dpio_lock); | |
5551 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
5552 | CCK_FUSE_HPLL_FREQ_MASK; | |
5553 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 5554 | |
dfcab17e | 5555 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5556 | } |
5557 | ||
f8bf63fd VS |
5558 | static void vlv_update_cdclk(struct drm_device *dev) |
5559 | { | |
5560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5561 | ||
164dfd28 | 5562 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
43dc52c3 | 5563 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
164dfd28 | 5564 | dev_priv->cdclk_freq); |
f8bf63fd VS |
5565 | |
5566 | /* | |
5567 | * Program the gmbus_freq based on the cdclk frequency. | |
5568 | * BSpec erroneously claims we should aim for 4MHz, but | |
5569 | * in fact 1MHz is the correct frequency. | |
5570 | */ | |
164dfd28 | 5571 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
f8bf63fd VS |
5572 | } |
5573 | ||
30a970c6 JB |
5574 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5575 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5576 | { | |
5577 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5578 | u32 val, cmd; | |
5579 | ||
164dfd28 VK |
5580 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5581 | != dev_priv->cdclk_freq); | |
d60c4473 | 5582 | |
dfcab17e | 5583 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5584 | cmd = 2; |
dfcab17e | 5585 | else if (cdclk == 266667) |
30a970c6 JB |
5586 | cmd = 1; |
5587 | else | |
5588 | cmd = 0; | |
5589 | ||
5590 | mutex_lock(&dev_priv->rps.hw_lock); | |
5591 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5592 | val &= ~DSPFREQGUAR_MASK; | |
5593 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5594 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5595 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5596 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5597 | 50)) { | |
5598 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5599 | } | |
5600 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5601 | ||
dfcab17e | 5602 | if (cdclk == 400000) { |
6bcda4f0 | 5603 | u32 divider; |
30a970c6 | 5604 | |
6bcda4f0 | 5605 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
5606 | |
5607 | mutex_lock(&dev_priv->dpio_lock); | |
5608 | /* adjust cdclk divider */ | |
5609 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5610 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5611 | val |= divider; |
5612 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5613 | |
5614 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5615 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5616 | 50)) | |
5617 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5618 | mutex_unlock(&dev_priv->dpio_lock); |
5619 | } | |
5620 | ||
5621 | mutex_lock(&dev_priv->dpio_lock); | |
5622 | /* adjust self-refresh exit latency value */ | |
5623 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5624 | val &= ~0x7f; | |
5625 | ||
5626 | /* | |
5627 | * For high bandwidth configs, we set a higher latency in the bunit | |
5628 | * so that the core display fetch happens in time to avoid underruns. | |
5629 | */ | |
dfcab17e | 5630 | if (cdclk == 400000) |
30a970c6 JB |
5631 | val |= 4500 / 250; /* 4.5 usec */ |
5632 | else | |
5633 | val |= 3000 / 250; /* 3.0 usec */ | |
5634 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5635 | mutex_unlock(&dev_priv->dpio_lock); | |
5636 | ||
f8bf63fd | 5637 | vlv_update_cdclk(dev); |
30a970c6 JB |
5638 | } |
5639 | ||
383c5a6a VS |
5640 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5641 | { | |
5642 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5643 | u32 val, cmd; | |
5644 | ||
164dfd28 VK |
5645 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5646 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5647 | |
5648 | switch (cdclk) { | |
383c5a6a VS |
5649 | case 333333: |
5650 | case 320000: | |
383c5a6a | 5651 | case 266667: |
383c5a6a | 5652 | case 200000: |
383c5a6a VS |
5653 | break; |
5654 | default: | |
5f77eeb0 | 5655 | MISSING_CASE(cdclk); |
383c5a6a VS |
5656 | return; |
5657 | } | |
5658 | ||
9d0d3fda VS |
5659 | /* |
5660 | * Specs are full of misinformation, but testing on actual | |
5661 | * hardware has shown that we just need to write the desired | |
5662 | * CCK divider into the Punit register. | |
5663 | */ | |
5664 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5665 | ||
383c5a6a VS |
5666 | mutex_lock(&dev_priv->rps.hw_lock); |
5667 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5668 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5669 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5670 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5671 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5672 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5673 | 50)) { | |
5674 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5675 | } | |
5676 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5677 | ||
5678 | vlv_update_cdclk(dev); | |
5679 | } | |
5680 | ||
30a970c6 JB |
5681 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5682 | int max_pixclk) | |
5683 | { | |
6bcda4f0 | 5684 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5685 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5686 | |
30a970c6 JB |
5687 | /* |
5688 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5689 | * 200MHz | |
5690 | * 267MHz | |
29dc7ef3 | 5691 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5692 | * 400MHz (VLV only) |
5693 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5694 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5695 | * |
5696 | * We seem to get an unstable or solid color picture at 200MHz. | |
5697 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5698 | * are off. | |
30a970c6 | 5699 | */ |
6cca3195 VS |
5700 | if (!IS_CHERRYVIEW(dev_priv) && |
5701 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5702 | return 400000; |
6cca3195 | 5703 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5704 | return freq_320; |
e37c67a1 | 5705 | else if (max_pixclk > 0) |
dfcab17e | 5706 | return 266667; |
e37c67a1 VS |
5707 | else |
5708 | return 200000; | |
30a970c6 JB |
5709 | } |
5710 | ||
f8437dd1 VK |
5711 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5712 | int max_pixclk) | |
5713 | { | |
5714 | /* | |
5715 | * FIXME: | |
5716 | * - remove the guardband, it's not needed on BXT | |
5717 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5718 | */ | |
5719 | if (max_pixclk > 576000*9/10) | |
5720 | return 624000; | |
5721 | else if (max_pixclk > 384000*9/10) | |
5722 | return 576000; | |
5723 | else if (max_pixclk > 288000*9/10) | |
5724 | return 384000; | |
5725 | else if (max_pixclk > 144000*9/10) | |
5726 | return 288000; | |
5727 | else | |
5728 | return 144000; | |
5729 | } | |
5730 | ||
a821fc46 ACO |
5731 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
5732 | * that's non-NULL, look at current state otherwise. */ | |
5733 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
5734 | struct drm_atomic_state *state) | |
30a970c6 | 5735 | { |
30a970c6 | 5736 | struct intel_crtc *intel_crtc; |
304603f4 | 5737 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5738 | int max_pixclk = 0; |
5739 | ||
d3fcc808 | 5740 | for_each_intel_crtc(dev, intel_crtc) { |
a821fc46 ACO |
5741 | if (state) |
5742 | crtc_state = | |
5743 | intel_atomic_get_crtc_state(state, intel_crtc); | |
5744 | else | |
5745 | crtc_state = intel_crtc->config; | |
304603f4 ACO |
5746 | if (IS_ERR(crtc_state)) |
5747 | return PTR_ERR(crtc_state); | |
5748 | ||
5749 | if (!crtc_state->base.enable) | |
5750 | continue; | |
5751 | ||
5752 | max_pixclk = max(max_pixclk, | |
5753 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5754 | } |
5755 | ||
5756 | return max_pixclk; | |
5757 | } | |
5758 | ||
0a9ab303 | 5759 | static int valleyview_modeset_global_pipes(struct drm_atomic_state *state) |
30a970c6 | 5760 | { |
304603f4 | 5761 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
0a9ab303 ACO |
5762 | struct drm_crtc *crtc; |
5763 | struct drm_crtc_state *crtc_state; | |
a821fc46 | 5764 | int max_pixclk = intel_mode_max_pixclk(state->dev, state); |
0a9ab303 | 5765 | int cdclk, i; |
30a970c6 | 5766 | |
304603f4 ACO |
5767 | if (max_pixclk < 0) |
5768 | return max_pixclk; | |
30a970c6 | 5769 | |
f8437dd1 VK |
5770 | if (IS_VALLEYVIEW(dev_priv)) |
5771 | cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
5772 | else | |
5773 | cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
5774 | ||
5775 | if (cdclk == dev_priv->cdclk_freq) | |
304603f4 | 5776 | return 0; |
30a970c6 | 5777 | |
0a9ab303 ACO |
5778 | /* add all active pipes to the state */ |
5779 | for_each_crtc(state->dev, crtc) { | |
5780 | if (!crtc->state->enable) | |
5781 | continue; | |
5782 | ||
5783 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
5784 | if (IS_ERR(crtc_state)) | |
5785 | return PTR_ERR(crtc_state); | |
5786 | } | |
5787 | ||
2f2d7aa1 | 5788 | /* disable/enable all currently active pipes while we change cdclk */ |
0a9ab303 ACO |
5789 | for_each_crtc_in_state(state, crtc, crtc_state, i) |
5790 | if (crtc_state->enable) | |
5791 | crtc_state->mode_changed = true; | |
304603f4 ACO |
5792 | |
5793 | return 0; | |
30a970c6 JB |
5794 | } |
5795 | ||
1e69cd74 VS |
5796 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5797 | { | |
5798 | unsigned int credits, default_credits; | |
5799 | ||
5800 | if (IS_CHERRYVIEW(dev_priv)) | |
5801 | default_credits = PFI_CREDIT(12); | |
5802 | else | |
5803 | default_credits = PFI_CREDIT(8); | |
5804 | ||
164dfd28 | 5805 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
5806 | /* CHV suggested value is 31 or 63 */ |
5807 | if (IS_CHERRYVIEW(dev_priv)) | |
5808 | credits = PFI_CREDIT_31; | |
5809 | else | |
5810 | credits = PFI_CREDIT(15); | |
5811 | } else { | |
5812 | credits = default_credits; | |
5813 | } | |
5814 | ||
5815 | /* | |
5816 | * WA - write default credits before re-programming | |
5817 | * FIXME: should we also set the resend bit here? | |
5818 | */ | |
5819 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5820 | default_credits); | |
5821 | ||
5822 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5823 | credits | PFI_CREDIT_RESEND); | |
5824 | ||
5825 | /* | |
5826 | * FIXME is this guaranteed to clear | |
5827 | * immediately or should we poll for it? | |
5828 | */ | |
5829 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5830 | } | |
5831 | ||
a821fc46 | 5832 | static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state) |
30a970c6 | 5833 | { |
a821fc46 | 5834 | struct drm_device *dev = old_state->dev; |
30a970c6 | 5835 | struct drm_i915_private *dev_priv = dev->dev_private; |
a821fc46 | 5836 | int max_pixclk = intel_mode_max_pixclk(dev, NULL); |
304603f4 ACO |
5837 | int req_cdclk; |
5838 | ||
a821fc46 ACO |
5839 | /* The path in intel_mode_max_pixclk() with a NULL atomic state should |
5840 | * never fail. */ | |
304603f4 ACO |
5841 | if (WARN_ON(max_pixclk < 0)) |
5842 | return; | |
30a970c6 | 5843 | |
304603f4 | 5844 | req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
30a970c6 | 5845 | |
164dfd28 | 5846 | if (req_cdclk != dev_priv->cdclk_freq) { |
738c05c0 ID |
5847 | /* |
5848 | * FIXME: We can end up here with all power domains off, yet | |
5849 | * with a CDCLK frequency other than the minimum. To account | |
5850 | * for this take the PIPE-A power domain, which covers the HW | |
5851 | * blocks needed for the following programming. This can be | |
5852 | * removed once it's guaranteed that we get here either with | |
5853 | * the minimum CDCLK set, or the required power domains | |
5854 | * enabled. | |
5855 | */ | |
5856 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5857 | ||
383c5a6a VS |
5858 | if (IS_CHERRYVIEW(dev)) |
5859 | cherryview_set_cdclk(dev, req_cdclk); | |
5860 | else | |
5861 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5862 | |
1e69cd74 VS |
5863 | vlv_program_pfi_credits(dev_priv); |
5864 | ||
738c05c0 | 5865 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5866 | } |
30a970c6 JB |
5867 | } |
5868 | ||
89b667f8 JB |
5869 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5870 | { | |
5871 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5872 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5874 | struct intel_encoder *encoder; | |
5875 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5876 | bool is_dsi; |
89b667f8 | 5877 | |
83d65738 | 5878 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5879 | |
5880 | if (intel_crtc->active) | |
5881 | return; | |
5882 | ||
409ee761 | 5883 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5884 | |
1ae0d137 VS |
5885 | if (!is_dsi) { |
5886 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5887 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5888 | else |
6e3c9717 | 5889 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5890 | } |
5b18e57c | 5891 | |
6e3c9717 | 5892 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5893 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5894 | |
5895 | intel_set_pipe_timings(intel_crtc); | |
5896 | ||
c14b0485 VS |
5897 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5899 | ||
5900 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5901 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5902 | } | |
5903 | ||
5b18e57c DV |
5904 | i9xx_set_pipeconf(intel_crtc); |
5905 | ||
89b667f8 | 5906 | intel_crtc->active = true; |
89b667f8 | 5907 | |
a72e4c9f | 5908 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5909 | |
89b667f8 JB |
5910 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5911 | if (encoder->pre_pll_enable) | |
5912 | encoder->pre_pll_enable(encoder); | |
5913 | ||
9d556c99 CML |
5914 | if (!is_dsi) { |
5915 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5916 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5917 | else |
6e3c9717 | 5918 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5919 | } |
89b667f8 JB |
5920 | |
5921 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5922 | if (encoder->pre_enable) | |
5923 | encoder->pre_enable(encoder); | |
5924 | ||
2dd24552 JB |
5925 | i9xx_pfit_enable(intel_crtc); |
5926 | ||
63cbb074 VS |
5927 | intel_crtc_load_lut(crtc); |
5928 | ||
f37fcc2a | 5929 | intel_update_watermarks(crtc); |
e1fdc473 | 5930 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5931 | |
4b3a9526 VS |
5932 | assert_vblank_disabled(crtc); |
5933 | drm_crtc_vblank_on(crtc); | |
5934 | ||
f9b61ff6 DV |
5935 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5936 | encoder->enable(encoder); | |
89b667f8 JB |
5937 | } |
5938 | ||
f13c2ef3 DV |
5939 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5940 | { | |
5941 | struct drm_device *dev = crtc->base.dev; | |
5942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5943 | ||
6e3c9717 ACO |
5944 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5945 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5946 | } |
5947 | ||
0b8765c6 | 5948 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5949 | { |
5950 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5951 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5952 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5953 | struct intel_encoder *encoder; |
79e53945 | 5954 | int pipe = intel_crtc->pipe; |
79e53945 | 5955 | |
83d65738 | 5956 | WARN_ON(!crtc->state->enable); |
08a48469 | 5957 | |
f7abfe8b CW |
5958 | if (intel_crtc->active) |
5959 | return; | |
5960 | ||
f13c2ef3 DV |
5961 | i9xx_set_pll_dividers(intel_crtc); |
5962 | ||
6e3c9717 | 5963 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5964 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5965 | |
5966 | intel_set_pipe_timings(intel_crtc); | |
5967 | ||
5b18e57c DV |
5968 | i9xx_set_pipeconf(intel_crtc); |
5969 | ||
f7abfe8b | 5970 | intel_crtc->active = true; |
6b383a7f | 5971 | |
4a3436e8 | 5972 | if (!IS_GEN2(dev)) |
a72e4c9f | 5973 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5974 | |
9d6d9f19 MK |
5975 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5976 | if (encoder->pre_enable) | |
5977 | encoder->pre_enable(encoder); | |
5978 | ||
f6736a1a DV |
5979 | i9xx_enable_pll(intel_crtc); |
5980 | ||
2dd24552 JB |
5981 | i9xx_pfit_enable(intel_crtc); |
5982 | ||
63cbb074 VS |
5983 | intel_crtc_load_lut(crtc); |
5984 | ||
f37fcc2a | 5985 | intel_update_watermarks(crtc); |
e1fdc473 | 5986 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5987 | |
4b3a9526 VS |
5988 | assert_vblank_disabled(crtc); |
5989 | drm_crtc_vblank_on(crtc); | |
5990 | ||
f9b61ff6 DV |
5991 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5992 | encoder->enable(encoder); | |
0b8765c6 | 5993 | } |
79e53945 | 5994 | |
87476d63 DV |
5995 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5996 | { | |
5997 | struct drm_device *dev = crtc->base.dev; | |
5998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5999 | |
6e3c9717 | 6000 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6001 | return; |
87476d63 | 6002 | |
328d8e82 | 6003 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6004 | |
328d8e82 DV |
6005 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6006 | I915_READ(PFIT_CONTROL)); | |
6007 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6008 | } |
6009 | ||
0b8765c6 JB |
6010 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6011 | { | |
6012 | struct drm_device *dev = crtc->dev; | |
6013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6014 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6015 | struct intel_encoder *encoder; |
0b8765c6 | 6016 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6017 | |
f7abfe8b CW |
6018 | if (!intel_crtc->active) |
6019 | return; | |
6020 | ||
6304cd91 VS |
6021 | /* |
6022 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6023 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6024 | * We also need to wait on all gmch platforms because of the |
6025 | * self-refresh mode constraint explained above. | |
6304cd91 | 6026 | */ |
564ed191 | 6027 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6028 | |
4b3a9526 VS |
6029 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6030 | encoder->disable(encoder); | |
6031 | ||
f9b61ff6 DV |
6032 | drm_crtc_vblank_off(crtc); |
6033 | assert_vblank_disabled(crtc); | |
6034 | ||
575f7ab7 | 6035 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6036 | |
87476d63 | 6037 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6038 | |
89b667f8 JB |
6039 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6040 | if (encoder->post_disable) | |
6041 | encoder->post_disable(encoder); | |
6042 | ||
409ee761 | 6043 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6044 | if (IS_CHERRYVIEW(dev)) |
6045 | chv_disable_pll(dev_priv, pipe); | |
6046 | else if (IS_VALLEYVIEW(dev)) | |
6047 | vlv_disable_pll(dev_priv, pipe); | |
6048 | else | |
1c4e0274 | 6049 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6050 | } |
0b8765c6 | 6051 | |
4a3436e8 | 6052 | if (!IS_GEN2(dev)) |
a72e4c9f | 6053 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 6054 | |
f7abfe8b | 6055 | intel_crtc->active = false; |
46ba614c | 6056 | intel_update_watermarks(crtc); |
f37fcc2a | 6057 | |
efa9624e | 6058 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 6059 | intel_fbc_update(dev); |
efa9624e | 6060 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
6061 | } |
6062 | ||
ee7b9f93 JB |
6063 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
6064 | { | |
6065 | } | |
6066 | ||
b04c5bd6 BF |
6067 | /* Master function to enable/disable CRTC and corresponding power wells */ |
6068 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
6069 | { |
6070 | struct drm_device *dev = crtc->dev; | |
6071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 6072 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
6073 | enum intel_display_power_domain domain; |
6074 | unsigned long domains; | |
976f8a20 | 6075 | |
0e572fe7 DV |
6076 | if (enable) { |
6077 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
6078 | domains = get_crtc_power_domains(crtc); |
6079 | for_each_power_domain(domain, domains) | |
6080 | intel_display_power_get(dev_priv, domain); | |
6081 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
6082 | |
6083 | dev_priv->display.crtc_enable(crtc); | |
ce22dba9 | 6084 | intel_crtc_enable_planes(crtc); |
0e572fe7 DV |
6085 | } |
6086 | } else { | |
6087 | if (intel_crtc->active) { | |
ce22dba9 | 6088 | intel_crtc_disable_planes(crtc); |
0e572fe7 DV |
6089 | dev_priv->display.crtc_disable(crtc); |
6090 | ||
e1e9fb84 DV |
6091 | domains = intel_crtc->enabled_power_domains; |
6092 | for_each_power_domain(domain, domains) | |
6093 | intel_display_power_put(dev_priv, domain); | |
6094 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
6095 | } |
6096 | } | |
b04c5bd6 BF |
6097 | } |
6098 | ||
6099 | /** | |
6100 | * Sets the power management mode of the pipe and plane. | |
6101 | */ | |
6102 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
6103 | { | |
6104 | struct drm_device *dev = crtc->dev; | |
6105 | struct intel_encoder *intel_encoder; | |
6106 | bool enable = false; | |
6107 | ||
6108 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
6109 | enable |= intel_encoder->connectors_active; | |
6110 | ||
6111 | intel_crtc_control(crtc, enable); | |
0f63cca2 ACO |
6112 | |
6113 | crtc->state->active = enable; | |
976f8a20 DV |
6114 | } |
6115 | ||
cdd59983 CW |
6116 | static void intel_crtc_disable(struct drm_crtc *crtc) |
6117 | { | |
cdd59983 | 6118 | struct drm_device *dev = crtc->dev; |
976f8a20 | 6119 | struct drm_connector *connector; |
ee7b9f93 | 6120 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 6121 | |
976f8a20 | 6122 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 6123 | WARN_ON(!crtc->state->enable); |
976f8a20 | 6124 | |
ce22dba9 | 6125 | intel_crtc_disable_planes(crtc); |
976f8a20 | 6126 | dev_priv->display.crtc_disable(crtc); |
ee7b9f93 JB |
6127 | dev_priv->display.off(crtc); |
6128 | ||
70a101f8 | 6129 | drm_plane_helper_disable(crtc->primary); |
976f8a20 DV |
6130 | |
6131 | /* Update computed state. */ | |
6132 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
6133 | if (!connector->encoder || !connector->encoder->crtc) | |
6134 | continue; | |
6135 | ||
6136 | if (connector->encoder->crtc != crtc) | |
6137 | continue; | |
6138 | ||
6139 | connector->dpms = DRM_MODE_DPMS_OFF; | |
6140 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
6141 | } |
6142 | } | |
6143 | ||
ea5b213a | 6144 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6145 | { |
4ef69c7a | 6146 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6147 | |
ea5b213a CW |
6148 | drm_encoder_cleanup(encoder); |
6149 | kfree(intel_encoder); | |
7e7d76c3 JB |
6150 | } |
6151 | ||
9237329d | 6152 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
6153 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
6154 | * state of the entire output pipe. */ | |
9237329d | 6155 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 6156 | { |
5ab432ef DV |
6157 | if (mode == DRM_MODE_DPMS_ON) { |
6158 | encoder->connectors_active = true; | |
6159 | ||
b2cabb0e | 6160 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
6161 | } else { |
6162 | encoder->connectors_active = false; | |
6163 | ||
b2cabb0e | 6164 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 6165 | } |
79e53945 JB |
6166 | } |
6167 | ||
0a91ca29 DV |
6168 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6169 | * internal consistency). */ | |
b980514c | 6170 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6171 | { |
0a91ca29 DV |
6172 | if (connector->get_hw_state(connector)) { |
6173 | struct intel_encoder *encoder = connector->encoder; | |
6174 | struct drm_crtc *crtc; | |
6175 | bool encoder_enabled; | |
6176 | enum pipe pipe; | |
6177 | ||
6178 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6179 | connector->base.base.id, | |
c23cc417 | 6180 | connector->base.name); |
0a91ca29 | 6181 | |
0e32b39c DA |
6182 | /* there is no real hw state for MST connectors */ |
6183 | if (connector->mst_port) | |
6184 | return; | |
6185 | ||
e2c719b7 | 6186 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 6187 | "wrong connector dpms state\n"); |
e2c719b7 | 6188 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 6189 | "active connector not linked to encoder\n"); |
0a91ca29 | 6190 | |
36cd7444 | 6191 | if (encoder) { |
e2c719b7 | 6192 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
6193 | "encoder->connectors_active not set\n"); |
6194 | ||
6195 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
6196 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
6197 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 6198 | return; |
0a91ca29 | 6199 | |
36cd7444 | 6200 | crtc = encoder->base.crtc; |
0a91ca29 | 6201 | |
83d65738 MR |
6202 | I915_STATE_WARN(!crtc->state->enable, |
6203 | "crtc not enabled\n"); | |
e2c719b7 RC |
6204 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
6205 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
6206 | "encoder active on the wrong pipe\n"); |
6207 | } | |
0a91ca29 | 6208 | } |
79e53945 JB |
6209 | } |
6210 | ||
08d9bc92 ACO |
6211 | int intel_connector_init(struct intel_connector *connector) |
6212 | { | |
6213 | struct drm_connector_state *connector_state; | |
6214 | ||
6215 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6216 | if (!connector_state) | |
6217 | return -ENOMEM; | |
6218 | ||
6219 | connector->base.state = connector_state; | |
6220 | return 0; | |
6221 | } | |
6222 | ||
6223 | struct intel_connector *intel_connector_alloc(void) | |
6224 | { | |
6225 | struct intel_connector *connector; | |
6226 | ||
6227 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6228 | if (!connector) | |
6229 | return NULL; | |
6230 | ||
6231 | if (intel_connector_init(connector) < 0) { | |
6232 | kfree(connector); | |
6233 | return NULL; | |
6234 | } | |
6235 | ||
6236 | return connector; | |
6237 | } | |
6238 | ||
5ab432ef DV |
6239 | /* Even simpler default implementation, if there's really no special case to |
6240 | * consider. */ | |
6241 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 6242 | { |
5ab432ef DV |
6243 | /* All the simple cases only support two dpms states. */ |
6244 | if (mode != DRM_MODE_DPMS_ON) | |
6245 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 6246 | |
5ab432ef DV |
6247 | if (mode == connector->dpms) |
6248 | return; | |
6249 | ||
6250 | connector->dpms = mode; | |
6251 | ||
6252 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
6253 | if (connector->encoder) |
6254 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 6255 | |
b980514c | 6256 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
6257 | } |
6258 | ||
f0947c37 DV |
6259 | /* Simple connector->get_hw_state implementation for encoders that support only |
6260 | * one connector and no cloning and hence the encoder state determines the state | |
6261 | * of the connector. */ | |
6262 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6263 | { |
24929352 | 6264 | enum pipe pipe = 0; |
f0947c37 | 6265 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6266 | |
f0947c37 | 6267 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6268 | } |
6269 | ||
6d293983 | 6270 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6271 | { |
6d293983 ACO |
6272 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6273 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6274 | |
6275 | return 0; | |
6276 | } | |
6277 | ||
6d293983 | 6278 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6279 | struct intel_crtc_state *pipe_config) |
1857e1da | 6280 | { |
6d293983 ACO |
6281 | struct drm_atomic_state *state = pipe_config->base.state; |
6282 | struct intel_crtc *other_crtc; | |
6283 | struct intel_crtc_state *other_crtc_state; | |
6284 | ||
1857e1da DV |
6285 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6286 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6287 | if (pipe_config->fdi_lanes > 4) { | |
6288 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6289 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6290 | return -EINVAL; |
1857e1da DV |
6291 | } |
6292 | ||
bafb6553 | 6293 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6294 | if (pipe_config->fdi_lanes > 2) { |
6295 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6296 | pipe_config->fdi_lanes); | |
6d293983 | 6297 | return -EINVAL; |
1857e1da | 6298 | } else { |
6d293983 | 6299 | return 0; |
1857e1da DV |
6300 | } |
6301 | } | |
6302 | ||
6303 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6304 | return 0; |
1857e1da DV |
6305 | |
6306 | /* Ivybridge 3 pipe is really complicated */ | |
6307 | switch (pipe) { | |
6308 | case PIPE_A: | |
6d293983 | 6309 | return 0; |
1857e1da | 6310 | case PIPE_B: |
6d293983 ACO |
6311 | if (pipe_config->fdi_lanes <= 2) |
6312 | return 0; | |
6313 | ||
6314 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6315 | other_crtc_state = | |
6316 | intel_atomic_get_crtc_state(state, other_crtc); | |
6317 | if (IS_ERR(other_crtc_state)) | |
6318 | return PTR_ERR(other_crtc_state); | |
6319 | ||
6320 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6321 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6322 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6323 | return -EINVAL; |
1857e1da | 6324 | } |
6d293983 | 6325 | return 0; |
1857e1da | 6326 | case PIPE_C: |
251cc67c VS |
6327 | if (pipe_config->fdi_lanes > 2) { |
6328 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6329 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6330 | return -EINVAL; |
251cc67c | 6331 | } |
6d293983 ACO |
6332 | |
6333 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6334 | other_crtc_state = | |
6335 | intel_atomic_get_crtc_state(state, other_crtc); | |
6336 | if (IS_ERR(other_crtc_state)) | |
6337 | return PTR_ERR(other_crtc_state); | |
6338 | ||
6339 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6340 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6341 | return -EINVAL; |
1857e1da | 6342 | } |
6d293983 | 6343 | return 0; |
1857e1da DV |
6344 | default: |
6345 | BUG(); | |
6346 | } | |
6347 | } | |
6348 | ||
e29c22c0 DV |
6349 | #define RETRY 1 |
6350 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6351 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6352 | { |
1857e1da | 6353 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6354 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6355 | int lane, link_bw, fdi_dotclock, ret; |
6356 | bool needs_recompute = false; | |
877d48d5 | 6357 | |
e29c22c0 | 6358 | retry: |
877d48d5 DV |
6359 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6360 | * each output octet as 10 bits. The actual frequency | |
6361 | * is stored as a divider into a 100MHz clock, and the | |
6362 | * mode pixel clock is stored in units of 1KHz. | |
6363 | * Hence the bw of each lane in terms of the mode signal | |
6364 | * is: | |
6365 | */ | |
6366 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6367 | ||
241bfc38 | 6368 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6369 | |
2bd89a07 | 6370 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6371 | pipe_config->pipe_bpp); |
6372 | ||
6373 | pipe_config->fdi_lanes = lane; | |
6374 | ||
2bd89a07 | 6375 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6376 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6377 | |
6d293983 ACO |
6378 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6379 | intel_crtc->pipe, pipe_config); | |
6380 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6381 | pipe_config->pipe_bpp -= 2*3; |
6382 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6383 | pipe_config->pipe_bpp); | |
6384 | needs_recompute = true; | |
6385 | pipe_config->bw_constrained = true; | |
6386 | ||
6387 | goto retry; | |
6388 | } | |
6389 | ||
6390 | if (needs_recompute) | |
6391 | return RETRY; | |
6392 | ||
6d293983 | 6393 | return ret; |
877d48d5 DV |
6394 | } |
6395 | ||
42db64ef | 6396 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6397 | struct intel_crtc_state *pipe_config) |
42db64ef | 6398 | { |
d330a953 | 6399 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 6400 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 6401 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
6402 | } |
6403 | ||
a43f6e0f | 6404 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6405 | struct intel_crtc_state *pipe_config) |
79e53945 | 6406 | { |
a43f6e0f | 6407 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6408 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6409 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d03c93d4 | 6410 | int ret; |
89749350 | 6411 | |
ad3a4479 | 6412 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6413 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
6414 | int clock_limit = |
6415 | dev_priv->display.get_display_clock_speed(dev); | |
6416 | ||
6417 | /* | |
6418 | * Enable pixel doubling when the dot clock | |
6419 | * is > 90% of the (display) core speed. | |
6420 | * | |
b397c96b VS |
6421 | * GDG double wide on either pipe, |
6422 | * otherwise pipe A only. | |
cf532bb2 | 6423 | */ |
b397c96b | 6424 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6425 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6426 | clock_limit *= 2; |
cf532bb2 | 6427 | pipe_config->double_wide = true; |
ad3a4479 VS |
6428 | } |
6429 | ||
241bfc38 | 6430 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6431 | return -EINVAL; |
2c07245f | 6432 | } |
89749350 | 6433 | |
1d1d0e27 VS |
6434 | /* |
6435 | * Pipe horizontal size must be even in: | |
6436 | * - DVO ganged mode | |
6437 | * - LVDS dual channel mode | |
6438 | * - Double wide pipe | |
6439 | */ | |
a93e255f | 6440 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6441 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6442 | pipe_config->pipe_src_w &= ~1; | |
6443 | ||
8693a824 DL |
6444 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6445 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6446 | */ |
6447 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6448 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6449 | return -EINVAL; |
44f46b42 | 6450 | |
f5adf94e | 6451 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6452 | hsw_compute_ips_config(crtc, pipe_config); |
6453 | ||
877d48d5 | 6454 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6455 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6456 | |
d03c93d4 CK |
6457 | /* FIXME: remove below call once atomic mode set is place and all crtc |
6458 | * related checks called from atomic_crtc_check function */ | |
6459 | ret = 0; | |
6460 | DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n", | |
6461 | crtc, pipe_config->base.state); | |
6462 | ret = intel_atomic_setup_scalers(dev, crtc, pipe_config); | |
6463 | ||
6464 | return ret; | |
79e53945 JB |
6465 | } |
6466 | ||
1652d19e VS |
6467 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6468 | { | |
6469 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6470 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6471 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6472 | uint32_t linkrate; | |
6473 | ||
6474 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) { | |
6475 | WARN(1, "LCPLL1 not enabled\n"); | |
6476 | return 24000; /* 24MHz is the cd freq with NSSC ref */ | |
6477 | } | |
6478 | ||
6479 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6480 | return 540000; | |
6481 | ||
6482 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6483 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6484 | |
71cd8423 DL |
6485 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6486 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6487 | /* vco 8640 */ |
6488 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6489 | case CDCLK_FREQ_450_432: | |
6490 | return 432000; | |
6491 | case CDCLK_FREQ_337_308: | |
6492 | return 308570; | |
6493 | case CDCLK_FREQ_675_617: | |
6494 | return 617140; | |
6495 | default: | |
6496 | WARN(1, "Unknown cd freq selection\n"); | |
6497 | } | |
6498 | } else { | |
6499 | /* vco 8100 */ | |
6500 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6501 | case CDCLK_FREQ_450_432: | |
6502 | return 450000; | |
6503 | case CDCLK_FREQ_337_308: | |
6504 | return 337500; | |
6505 | case CDCLK_FREQ_675_617: | |
6506 | return 675000; | |
6507 | default: | |
6508 | WARN(1, "Unknown cd freq selection\n"); | |
6509 | } | |
6510 | } | |
6511 | ||
6512 | /* error case, do as if DPLL0 isn't enabled */ | |
6513 | return 24000; | |
6514 | } | |
6515 | ||
6516 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
6517 | { | |
6518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6519 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6520 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6521 | ||
6522 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6523 | return 800000; | |
6524 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6525 | return 450000; | |
6526 | else if (freq == LCPLL_CLK_FREQ_450) | |
6527 | return 450000; | |
6528 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6529 | return 540000; | |
6530 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6531 | return 337500; | |
6532 | else | |
6533 | return 675000; | |
6534 | } | |
6535 | ||
6536 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6537 | { | |
6538 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6539 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6540 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6541 | ||
6542 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6543 | return 800000; | |
6544 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6545 | return 450000; | |
6546 | else if (freq == LCPLL_CLK_FREQ_450) | |
6547 | return 450000; | |
6548 | else if (IS_HSW_ULT(dev)) | |
6549 | return 337500; | |
6550 | else | |
6551 | return 540000; | |
79e53945 JB |
6552 | } |
6553 | ||
25eb05fc JB |
6554 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6555 | { | |
d197b7d3 | 6556 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6557 | u32 val; |
6558 | int divider; | |
6559 | ||
6bcda4f0 VS |
6560 | if (dev_priv->hpll_freq == 0) |
6561 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6562 | ||
d197b7d3 VS |
6563 | mutex_lock(&dev_priv->dpio_lock); |
6564 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
6565 | mutex_unlock(&dev_priv->dpio_lock); | |
6566 | ||
6567 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6568 | ||
7d007f40 VS |
6569 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6570 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6571 | "cdclk change in progress\n"); | |
6572 | ||
6bcda4f0 | 6573 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6574 | } |
6575 | ||
b37a6434 VS |
6576 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6577 | { | |
6578 | return 450000; | |
6579 | } | |
6580 | ||
e70236a8 JB |
6581 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6582 | { | |
6583 | return 400000; | |
6584 | } | |
79e53945 | 6585 | |
e70236a8 | 6586 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6587 | { |
e907f170 | 6588 | return 333333; |
e70236a8 | 6589 | } |
79e53945 | 6590 | |
e70236a8 JB |
6591 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6592 | { | |
6593 | return 200000; | |
6594 | } | |
79e53945 | 6595 | |
257a7ffc DV |
6596 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6597 | { | |
6598 | u16 gcfgc = 0; | |
6599 | ||
6600 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6601 | ||
6602 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6603 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6604 | return 266667; |
257a7ffc | 6605 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6606 | return 333333; |
257a7ffc | 6607 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6608 | return 444444; |
257a7ffc DV |
6609 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6610 | return 200000; | |
6611 | default: | |
6612 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6613 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6614 | return 133333; |
257a7ffc | 6615 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6616 | return 166667; |
257a7ffc DV |
6617 | } |
6618 | } | |
6619 | ||
e70236a8 JB |
6620 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6621 | { | |
6622 | u16 gcfgc = 0; | |
79e53945 | 6623 | |
e70236a8 JB |
6624 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6625 | ||
6626 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6627 | return 133333; |
e70236a8 JB |
6628 | else { |
6629 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6630 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6631 | return 333333; |
e70236a8 JB |
6632 | default: |
6633 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6634 | return 190000; | |
79e53945 | 6635 | } |
e70236a8 JB |
6636 | } |
6637 | } | |
6638 | ||
6639 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6640 | { | |
e907f170 | 6641 | return 266667; |
e70236a8 JB |
6642 | } |
6643 | ||
6644 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
6645 | { | |
6646 | u16 hpllcc = 0; | |
6647 | /* Assume that the hardware is in the high speed state. This | |
6648 | * should be the default. | |
6649 | */ | |
6650 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6651 | case GC_CLOCK_133_200: | |
6652 | case GC_CLOCK_100_200: | |
6653 | return 200000; | |
6654 | case GC_CLOCK_166_250: | |
6655 | return 250000; | |
6656 | case GC_CLOCK_100_133: | |
e907f170 | 6657 | return 133333; |
e70236a8 | 6658 | } |
79e53945 | 6659 | |
e70236a8 JB |
6660 | /* Shouldn't happen */ |
6661 | return 0; | |
6662 | } | |
79e53945 | 6663 | |
e70236a8 JB |
6664 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6665 | { | |
e907f170 | 6666 | return 133333; |
79e53945 JB |
6667 | } |
6668 | ||
2c07245f | 6669 | static void |
a65851af | 6670 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6671 | { |
a65851af VS |
6672 | while (*num > DATA_LINK_M_N_MASK || |
6673 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6674 | *num >>= 1; |
6675 | *den >>= 1; | |
6676 | } | |
6677 | } | |
6678 | ||
a65851af VS |
6679 | static void compute_m_n(unsigned int m, unsigned int n, |
6680 | uint32_t *ret_m, uint32_t *ret_n) | |
6681 | { | |
6682 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6683 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6684 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6685 | } | |
6686 | ||
e69d0bc1 DV |
6687 | void |
6688 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6689 | int pixel_clock, int link_clock, | |
6690 | struct intel_link_m_n *m_n) | |
2c07245f | 6691 | { |
e69d0bc1 | 6692 | m_n->tu = 64; |
a65851af VS |
6693 | |
6694 | compute_m_n(bits_per_pixel * pixel_clock, | |
6695 | link_clock * nlanes * 8, | |
6696 | &m_n->gmch_m, &m_n->gmch_n); | |
6697 | ||
6698 | compute_m_n(pixel_clock, link_clock, | |
6699 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6700 | } |
6701 | ||
a7615030 CW |
6702 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6703 | { | |
d330a953 JN |
6704 | if (i915.panel_use_ssc >= 0) |
6705 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6706 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6707 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6708 | } |
6709 | ||
a93e255f ACO |
6710 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
6711 | int num_connectors) | |
c65d77d8 | 6712 | { |
a93e255f | 6713 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
6714 | struct drm_i915_private *dev_priv = dev->dev_private; |
6715 | int refclk; | |
6716 | ||
a93e255f ACO |
6717 | WARN_ON(!crtc_state->base.state); |
6718 | ||
5ab7b0b7 | 6719 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 6720 | refclk = 100000; |
a93e255f | 6721 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 6722 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
6723 | refclk = dev_priv->vbt.lvds_ssc_freq; |
6724 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
6725 | } else if (!IS_GEN2(dev)) { |
6726 | refclk = 96000; | |
6727 | } else { | |
6728 | refclk = 48000; | |
6729 | } | |
6730 | ||
6731 | return refclk; | |
6732 | } | |
6733 | ||
7429e9d4 | 6734 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6735 | { |
7df00d7a | 6736 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6737 | } |
f47709a9 | 6738 | |
7429e9d4 DV |
6739 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6740 | { | |
6741 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6742 | } |
6743 | ||
f47709a9 | 6744 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6745 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
6746 | intel_clock_t *reduced_clock) |
6747 | { | |
f47709a9 | 6748 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
6749 | u32 fp, fp2 = 0; |
6750 | ||
6751 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 6752 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6753 | if (reduced_clock) |
7429e9d4 | 6754 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6755 | } else { |
190f68c5 | 6756 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6757 | if (reduced_clock) |
7429e9d4 | 6758 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6759 | } |
6760 | ||
190f68c5 | 6761 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6762 | |
f47709a9 | 6763 | crtc->lowfreq_avail = false; |
a93e255f | 6764 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6765 | reduced_clock) { |
190f68c5 | 6766 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6767 | crtc->lowfreq_avail = true; |
a7516a05 | 6768 | } else { |
190f68c5 | 6769 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6770 | } |
6771 | } | |
6772 | ||
5e69f97f CML |
6773 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6774 | pipe) | |
89b667f8 JB |
6775 | { |
6776 | u32 reg_val; | |
6777 | ||
6778 | /* | |
6779 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6780 | * and set it to a reasonable value instead. | |
6781 | */ | |
ab3c759a | 6782 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6783 | reg_val &= 0xffffff00; |
6784 | reg_val |= 0x00000030; | |
ab3c759a | 6785 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6786 | |
ab3c759a | 6787 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6788 | reg_val &= 0x8cffffff; |
6789 | reg_val = 0x8c000000; | |
ab3c759a | 6790 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6791 | |
ab3c759a | 6792 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6793 | reg_val &= 0xffffff00; |
ab3c759a | 6794 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6795 | |
ab3c759a | 6796 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6797 | reg_val &= 0x00ffffff; |
6798 | reg_val |= 0xb0000000; | |
ab3c759a | 6799 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6800 | } |
6801 | ||
b551842d DV |
6802 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6803 | struct intel_link_m_n *m_n) | |
6804 | { | |
6805 | struct drm_device *dev = crtc->base.dev; | |
6806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6807 | int pipe = crtc->pipe; | |
6808 | ||
e3b95f1e DV |
6809 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6810 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6811 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6812 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6813 | } |
6814 | ||
6815 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6816 | struct intel_link_m_n *m_n, |
6817 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
6818 | { |
6819 | struct drm_device *dev = crtc->base.dev; | |
6820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6821 | int pipe = crtc->pipe; | |
6e3c9717 | 6822 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
6823 | |
6824 | if (INTEL_INFO(dev)->gen >= 5) { | |
6825 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
6826 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6827 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6828 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6829 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6830 | * for gen < 8) and if DRRS is supported (to make sure the | |
6831 | * registers are not unnecessarily accessed). | |
6832 | */ | |
44395bfe | 6833 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 6834 | crtc->config->has_drrs) { |
f769cd24 VK |
6835 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6836 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6837 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6838 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6839 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6840 | } | |
b551842d | 6841 | } else { |
e3b95f1e DV |
6842 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6843 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6844 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6845 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6846 | } |
6847 | } | |
6848 | ||
fe3cd48d | 6849 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6850 | { |
fe3cd48d R |
6851 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6852 | ||
6853 | if (m_n == M1_N1) { | |
6854 | dp_m_n = &crtc->config->dp_m_n; | |
6855 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6856 | } else if (m_n == M2_N2) { | |
6857 | ||
6858 | /* | |
6859 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6860 | * needs to be programmed into M1_N1. | |
6861 | */ | |
6862 | dp_m_n = &crtc->config->dp_m2_n2; | |
6863 | } else { | |
6864 | DRM_ERROR("Unsupported divider value\n"); | |
6865 | return; | |
6866 | } | |
6867 | ||
6e3c9717 ACO |
6868 | if (crtc->config->has_pch_encoder) |
6869 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6870 | else |
fe3cd48d | 6871 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6872 | } |
6873 | ||
d288f65f | 6874 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6875 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
6876 | { |
6877 | u32 dpll, dpll_md; | |
6878 | ||
6879 | /* | |
6880 | * Enable DPIO clock input. We should never disable the reference | |
6881 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6882 | * on it. | |
6883 | */ | |
6884 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6885 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6886 | /* We should never disable this, set it here for state tracking */ | |
6887 | if (crtc->pipe == PIPE_B) | |
6888 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6889 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6890 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6891 | |
d288f65f | 6892 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6893 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6894 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6895 | } |
6896 | ||
d288f65f | 6897 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6898 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6899 | { |
f47709a9 | 6900 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6901 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6902 | int pipe = crtc->pipe; |
bdd4b6a6 | 6903 | u32 mdiv; |
a0c4da24 | 6904 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6905 | u32 coreclk, reg_val; |
a0c4da24 | 6906 | |
09153000 DV |
6907 | mutex_lock(&dev_priv->dpio_lock); |
6908 | ||
d288f65f VS |
6909 | bestn = pipe_config->dpll.n; |
6910 | bestm1 = pipe_config->dpll.m1; | |
6911 | bestm2 = pipe_config->dpll.m2; | |
6912 | bestp1 = pipe_config->dpll.p1; | |
6913 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6914 | |
89b667f8 JB |
6915 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6916 | ||
6917 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6918 | if (pipe == PIPE_B) |
5e69f97f | 6919 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6920 | |
6921 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6922 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6923 | |
6924 | /* Disable target IRef on PLL */ | |
ab3c759a | 6925 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6926 | reg_val &= 0x00ffffff; |
ab3c759a | 6927 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6928 | |
6929 | /* Disable fast lock */ | |
ab3c759a | 6930 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6931 | |
6932 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6933 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6934 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6935 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6936 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6937 | |
6938 | /* | |
6939 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6940 | * but we don't support that). | |
6941 | * Note: don't use the DAC post divider as it seems unstable. | |
6942 | */ | |
6943 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6944 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6945 | |
a0c4da24 | 6946 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6947 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6948 | |
89b667f8 | 6949 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6950 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6951 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6952 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6953 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6954 | 0x009f0003); |
89b667f8 | 6955 | else |
ab3c759a | 6956 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6957 | 0x00d0000f); |
6958 | ||
681a8504 | 6959 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6960 | /* Use SSC source */ |
bdd4b6a6 | 6961 | if (pipe == PIPE_A) |
ab3c759a | 6962 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6963 | 0x0df40000); |
6964 | else | |
ab3c759a | 6965 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6966 | 0x0df70000); |
6967 | } else { /* HDMI or VGA */ | |
6968 | /* Use bend source */ | |
bdd4b6a6 | 6969 | if (pipe == PIPE_A) |
ab3c759a | 6970 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6971 | 0x0df70000); |
6972 | else | |
ab3c759a | 6973 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6974 | 0x0df40000); |
6975 | } | |
a0c4da24 | 6976 | |
ab3c759a | 6977 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6978 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6979 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6980 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6981 | coreclk |= 0x01000000; |
ab3c759a | 6982 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6983 | |
ab3c759a | 6984 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6985 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6986 | } |
6987 | ||
d288f65f | 6988 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6989 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6990 | { |
d288f65f | 6991 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6992 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6993 | DPLL_VCO_ENABLE; | |
6994 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6995 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6996 | |
d288f65f VS |
6997 | pipe_config->dpll_hw_state.dpll_md = |
6998 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6999 | } |
7000 | ||
d288f65f | 7001 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7002 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7003 | { |
7004 | struct drm_device *dev = crtc->base.dev; | |
7005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7006 | int pipe = crtc->pipe; | |
7007 | int dpll_reg = DPLL(crtc->pipe); | |
7008 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 7009 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7010 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7011 | u32 dpio_val; |
9cbe40c1 | 7012 | int vco; |
9d556c99 | 7013 | |
d288f65f VS |
7014 | bestn = pipe_config->dpll.n; |
7015 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7016 | bestm1 = pipe_config->dpll.m1; | |
7017 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7018 | bestp1 = pipe_config->dpll.p1; | |
7019 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7020 | vco = pipe_config->dpll.vco; |
a945ce7e | 7021 | dpio_val = 0; |
9cbe40c1 | 7022 | loopfilter = 0; |
9d556c99 CML |
7023 | |
7024 | /* | |
7025 | * Enable Refclk and SSC | |
7026 | */ | |
a11b0703 | 7027 | I915_WRITE(dpll_reg, |
d288f65f | 7028 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
7029 | |
7030 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 7031 | |
9d556c99 CML |
7032 | /* p1 and p2 divider */ |
7033 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7034 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7035 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7036 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7037 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7038 | ||
7039 | /* Feedback post-divider - m2 */ | |
7040 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7041 | ||
7042 | /* Feedback refclk divider - n and m1 */ | |
7043 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7044 | DPIO_CHV_M1_DIV_BY_2 | | |
7045 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7046 | ||
7047 | /* M2 fraction division */ | |
a945ce7e VP |
7048 | if (bestm2_frac) |
7049 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
7050 | |
7051 | /* M2 fraction division enable */ | |
a945ce7e VP |
7052 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7053 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7054 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7055 | if (bestm2_frac) | |
7056 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7057 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7058 | |
de3a0fde VP |
7059 | /* Program digital lock detect threshold */ |
7060 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7061 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7062 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7063 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7064 | if (!bestm2_frac) | |
7065 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7066 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7067 | ||
9d556c99 | 7068 | /* Loop filter */ |
9cbe40c1 VP |
7069 | if (vco == 5400000) { |
7070 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7071 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7072 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7073 | tribuf_calcntr = 0x9; | |
7074 | } else if (vco <= 6200000) { | |
7075 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7076 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7077 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7078 | tribuf_calcntr = 0x9; | |
7079 | } else if (vco <= 6480000) { | |
7080 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7081 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7082 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7083 | tribuf_calcntr = 0x8; | |
7084 | } else { | |
7085 | /* Not supported. Apply the same limits as in the max case */ | |
7086 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7087 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7088 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7089 | tribuf_calcntr = 0; | |
7090 | } | |
9d556c99 CML |
7091 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7092 | ||
968040b2 | 7093 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7094 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7095 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7096 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7097 | ||
9d556c99 CML |
7098 | /* AFC Recal */ |
7099 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7100 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7101 | DPIO_AFC_RECAL); | |
7102 | ||
7103 | mutex_unlock(&dev_priv->dpio_lock); | |
7104 | } | |
7105 | ||
d288f65f VS |
7106 | /** |
7107 | * vlv_force_pll_on - forcibly enable just the PLL | |
7108 | * @dev_priv: i915 private structure | |
7109 | * @pipe: pipe PLL to enable | |
7110 | * @dpll: PLL configuration | |
7111 | * | |
7112 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7113 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7114 | * be enabled. | |
7115 | */ | |
7116 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7117 | const struct dpll *dpll) | |
7118 | { | |
7119 | struct intel_crtc *crtc = | |
7120 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7121 | struct intel_crtc_state pipe_config = { |
a93e255f | 7122 | .base.crtc = &crtc->base, |
d288f65f VS |
7123 | .pixel_multiplier = 1, |
7124 | .dpll = *dpll, | |
7125 | }; | |
7126 | ||
7127 | if (IS_CHERRYVIEW(dev)) { | |
7128 | chv_update_pll(crtc, &pipe_config); | |
7129 | chv_prepare_pll(crtc, &pipe_config); | |
7130 | chv_enable_pll(crtc, &pipe_config); | |
7131 | } else { | |
7132 | vlv_update_pll(crtc, &pipe_config); | |
7133 | vlv_prepare_pll(crtc, &pipe_config); | |
7134 | vlv_enable_pll(crtc, &pipe_config); | |
7135 | } | |
7136 | } | |
7137 | ||
7138 | /** | |
7139 | * vlv_force_pll_off - forcibly disable just the PLL | |
7140 | * @dev_priv: i915 private structure | |
7141 | * @pipe: pipe PLL to disable | |
7142 | * | |
7143 | * Disable the PLL for @pipe. To be used in cases where we need | |
7144 | * the PLL enabled even when @pipe is not going to be enabled. | |
7145 | */ | |
7146 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7147 | { | |
7148 | if (IS_CHERRYVIEW(dev)) | |
7149 | chv_disable_pll(to_i915(dev), pipe); | |
7150 | else | |
7151 | vlv_disable_pll(to_i915(dev), pipe); | |
7152 | } | |
7153 | ||
f47709a9 | 7154 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7155 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7156 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7157 | int num_connectors) |
7158 | { | |
f47709a9 | 7159 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7160 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7161 | u32 dpll; |
7162 | bool is_sdvo; | |
190f68c5 | 7163 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7164 | |
190f68c5 | 7165 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7166 | |
a93e255f ACO |
7167 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7168 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7169 | |
7170 | dpll = DPLL_VGA_MODE_DIS; | |
7171 | ||
a93e255f | 7172 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7173 | dpll |= DPLLB_MODE_LVDS; |
7174 | else | |
7175 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7176 | |
ef1b460d | 7177 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7178 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7179 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7180 | } |
198a037f DV |
7181 | |
7182 | if (is_sdvo) | |
4a33e48d | 7183 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7184 | |
190f68c5 | 7185 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7186 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7187 | |
7188 | /* compute bitmask from p1 value */ | |
7189 | if (IS_PINEVIEW(dev)) | |
7190 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7191 | else { | |
7192 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7193 | if (IS_G4X(dev) && reduced_clock) | |
7194 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7195 | } | |
7196 | switch (clock->p2) { | |
7197 | case 5: | |
7198 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7199 | break; | |
7200 | case 7: | |
7201 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7202 | break; | |
7203 | case 10: | |
7204 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7205 | break; | |
7206 | case 14: | |
7207 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7208 | break; | |
7209 | } | |
7210 | if (INTEL_INFO(dev)->gen >= 4) | |
7211 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7212 | ||
190f68c5 | 7213 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7214 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7215 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7216 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7217 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7218 | else | |
7219 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7220 | ||
7221 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7222 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7223 | |
eb1cbe48 | 7224 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7225 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7226 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7227 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7228 | } |
7229 | } | |
7230 | ||
f47709a9 | 7231 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7232 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7233 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7234 | int num_connectors) |
7235 | { | |
f47709a9 | 7236 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7237 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7238 | u32 dpll; |
190f68c5 | 7239 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7240 | |
190f68c5 | 7241 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7242 | |
eb1cbe48 DV |
7243 | dpll = DPLL_VGA_MODE_DIS; |
7244 | ||
a93e255f | 7245 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7246 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7247 | } else { | |
7248 | if (clock->p1 == 2) | |
7249 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7250 | else | |
7251 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7252 | if (clock->p2 == 4) | |
7253 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7254 | } | |
7255 | ||
a93e255f | 7256 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7257 | dpll |= DPLL_DVO_2X_MODE; |
7258 | ||
a93e255f | 7259 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7260 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7261 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7262 | else | |
7263 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7264 | ||
7265 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7266 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7267 | } |
7268 | ||
8a654f3b | 7269 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7270 | { |
7271 | struct drm_device *dev = intel_crtc->base.dev; | |
7272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7273 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7274 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 7275 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 7276 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7277 | uint32_t crtc_vtotal, crtc_vblank_end; |
7278 | int vsyncshift = 0; | |
4d8a62ea DV |
7279 | |
7280 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7281 | * the hw state checker will get angry at the mismatch. */ | |
7282 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7283 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7284 | |
609aeaca | 7285 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7286 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7287 | crtc_vtotal -= 1; |
7288 | crtc_vblank_end -= 1; | |
609aeaca | 7289 | |
409ee761 | 7290 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7291 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7292 | else | |
7293 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7294 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7295 | if (vsyncshift < 0) |
7296 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7297 | } |
7298 | ||
7299 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7300 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7301 | |
fe2b8f9d | 7302 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7303 | (adjusted_mode->crtc_hdisplay - 1) | |
7304 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7305 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7306 | (adjusted_mode->crtc_hblank_start - 1) | |
7307 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7308 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7309 | (adjusted_mode->crtc_hsync_start - 1) | |
7310 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7311 | ||
fe2b8f9d | 7312 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7313 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7314 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7315 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7316 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7317 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7318 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7319 | (adjusted_mode->crtc_vsync_start - 1) | |
7320 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7321 | ||
b5e508d4 PZ |
7322 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7323 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7324 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7325 | * bits. */ | |
7326 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7327 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7328 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7329 | ||
b0e77b9c PZ |
7330 | /* pipesrc controls the size that is scaled from, which should |
7331 | * always be the user's requested size. | |
7332 | */ | |
7333 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7334 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7335 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7336 | } |
7337 | ||
1bd1bd80 | 7338 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7339 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7340 | { |
7341 | struct drm_device *dev = crtc->base.dev; | |
7342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7343 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7344 | uint32_t tmp; | |
7345 | ||
7346 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7347 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7348 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7349 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7350 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7351 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7352 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7353 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7354 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7355 | |
7356 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7357 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7358 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7359 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7360 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7361 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7362 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7363 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7364 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7365 | |
7366 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7367 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7368 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7369 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7370 | } |
7371 | ||
7372 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7373 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7374 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7375 | ||
2d112de7 ACO |
7376 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7377 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7378 | } |
7379 | ||
f6a83288 | 7380 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7381 | struct intel_crtc_state *pipe_config) |
babea61d | 7382 | { |
2d112de7 ACO |
7383 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7384 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7385 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7386 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7387 | |
2d112de7 ACO |
7388 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7389 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7390 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7391 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7392 | |
2d112de7 | 7393 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 7394 | |
2d112de7 ACO |
7395 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7396 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
7397 | } |
7398 | ||
84b046f3 DV |
7399 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7400 | { | |
7401 | struct drm_device *dev = intel_crtc->base.dev; | |
7402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7403 | uint32_t pipeconf; | |
7404 | ||
9f11a9e4 | 7405 | pipeconf = 0; |
84b046f3 | 7406 | |
b6b5d049 VS |
7407 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7408 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7409 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7410 | |
6e3c9717 | 7411 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7412 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7413 | |
ff9ce46e DV |
7414 | /* only g4x and later have fancy bpc/dither controls */ |
7415 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7416 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7417 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7418 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7419 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7420 | |
6e3c9717 | 7421 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7422 | case 18: |
7423 | pipeconf |= PIPECONF_6BPC; | |
7424 | break; | |
7425 | case 24: | |
7426 | pipeconf |= PIPECONF_8BPC; | |
7427 | break; | |
7428 | case 30: | |
7429 | pipeconf |= PIPECONF_10BPC; | |
7430 | break; | |
7431 | default: | |
7432 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7433 | BUG(); | |
84b046f3 DV |
7434 | } |
7435 | } | |
7436 | ||
7437 | if (HAS_PIPE_CXSR(dev)) { | |
7438 | if (intel_crtc->lowfreq_avail) { | |
7439 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7440 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7441 | } else { | |
7442 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7443 | } |
7444 | } | |
7445 | ||
6e3c9717 | 7446 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7447 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7448 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7449 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7450 | else | |
7451 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7452 | } else | |
84b046f3 DV |
7453 | pipeconf |= PIPECONF_PROGRESSIVE; |
7454 | ||
6e3c9717 | 7455 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7456 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7457 | |
84b046f3 DV |
7458 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7459 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7460 | } | |
7461 | ||
190f68c5 ACO |
7462 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7463 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7464 | { |
c7653199 | 7465 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7466 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7467 | int refclk, num_connectors = 0; |
652c393a | 7468 | intel_clock_t clock, reduced_clock; |
a16af721 | 7469 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 7470 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 7471 | struct intel_encoder *encoder; |
d4906093 | 7472 | const intel_limit_t *limit; |
55bb9992 | 7473 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7474 | struct drm_connector *connector; |
55bb9992 ACO |
7475 | struct drm_connector_state *connector_state; |
7476 | int i; | |
79e53945 | 7477 | |
da3ced29 | 7478 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
7479 | if (connector_state->crtc != &crtc->base) |
7480 | continue; | |
7481 | ||
7482 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7483 | ||
5eddb70b | 7484 | switch (encoder->type) { |
79e53945 JB |
7485 | case INTEL_OUTPUT_LVDS: |
7486 | is_lvds = true; | |
7487 | break; | |
e9fd1c02 JN |
7488 | case INTEL_OUTPUT_DSI: |
7489 | is_dsi = true; | |
7490 | break; | |
6847d71b PZ |
7491 | default: |
7492 | break; | |
79e53945 | 7493 | } |
43565a06 | 7494 | |
c751ce4f | 7495 | num_connectors++; |
79e53945 JB |
7496 | } |
7497 | ||
f2335330 | 7498 | if (is_dsi) |
5b18e57c | 7499 | return 0; |
f2335330 | 7500 | |
190f68c5 | 7501 | if (!crtc_state->clock_set) { |
a93e255f | 7502 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7503 | |
e9fd1c02 JN |
7504 | /* |
7505 | * Returns a set of divisors for the desired target clock with | |
7506 | * the given refclk, or FALSE. The returned values represent | |
7507 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7508 | * 2) / p1 / p2. | |
7509 | */ | |
a93e255f ACO |
7510 | limit = intel_limit(crtc_state, refclk); |
7511 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7512 | crtc_state->port_clock, |
e9fd1c02 | 7513 | refclk, NULL, &clock); |
f2335330 | 7514 | if (!ok) { |
e9fd1c02 JN |
7515 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7516 | return -EINVAL; | |
7517 | } | |
79e53945 | 7518 | |
f2335330 JN |
7519 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
7520 | /* | |
7521 | * Ensure we match the reduced clock's P to the target | |
7522 | * clock. If the clocks don't match, we can't switch | |
7523 | * the display clock by using the FP0/FP1. In such case | |
7524 | * we will disable the LVDS downclock feature. | |
7525 | */ | |
7526 | has_reduced_clock = | |
a93e255f | 7527 | dev_priv->display.find_dpll(limit, crtc_state, |
f2335330 JN |
7528 | dev_priv->lvds_downclock, |
7529 | refclk, &clock, | |
7530 | &reduced_clock); | |
7531 | } | |
7532 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
7533 | crtc_state->dpll.n = clock.n; |
7534 | crtc_state->dpll.m1 = clock.m1; | |
7535 | crtc_state->dpll.m2 = clock.m2; | |
7536 | crtc_state->dpll.p1 = clock.p1; | |
7537 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7538 | } |
7026d4ac | 7539 | |
e9fd1c02 | 7540 | if (IS_GEN2(dev)) { |
190f68c5 | 7541 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
7542 | has_reduced_clock ? &reduced_clock : NULL, |
7543 | num_connectors); | |
9d556c99 | 7544 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 7545 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7546 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 7547 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7548 | } else { |
190f68c5 | 7549 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 7550 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 7551 | num_connectors); |
e9fd1c02 | 7552 | } |
79e53945 | 7553 | |
c8f7a0db | 7554 | return 0; |
f564048e EA |
7555 | } |
7556 | ||
2fa2fe9a | 7557 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7558 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7559 | { |
7560 | struct drm_device *dev = crtc->base.dev; | |
7561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7562 | uint32_t tmp; | |
7563 | ||
dc9e7dec VS |
7564 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7565 | return; | |
7566 | ||
2fa2fe9a | 7567 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7568 | if (!(tmp & PFIT_ENABLE)) |
7569 | return; | |
2fa2fe9a | 7570 | |
06922821 | 7571 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7572 | if (INTEL_INFO(dev)->gen < 4) { |
7573 | if (crtc->pipe != PIPE_B) | |
7574 | return; | |
2fa2fe9a DV |
7575 | } else { |
7576 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7577 | return; | |
7578 | } | |
7579 | ||
06922821 | 7580 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7581 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7582 | if (INTEL_INFO(dev)->gen < 5) | |
7583 | pipe_config->gmch_pfit.lvds_border_bits = | |
7584 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7585 | } | |
7586 | ||
acbec814 | 7587 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7588 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7589 | { |
7590 | struct drm_device *dev = crtc->base.dev; | |
7591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7592 | int pipe = pipe_config->cpu_transcoder; | |
7593 | intel_clock_t clock; | |
7594 | u32 mdiv; | |
662c6ecb | 7595 | int refclk = 100000; |
acbec814 | 7596 | |
f573de5a SK |
7597 | /* In case of MIPI DPLL will not even be used */ |
7598 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7599 | return; | |
7600 | ||
acbec814 | 7601 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 7602 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
7603 | mutex_unlock(&dev_priv->dpio_lock); |
7604 | ||
7605 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7606 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7607 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7608 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7609 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7610 | ||
f646628b | 7611 | vlv_clock(refclk, &clock); |
acbec814 | 7612 | |
f646628b VS |
7613 | /* clock.dot is the fast clock */ |
7614 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
7615 | } |
7616 | ||
5724dbd1 DL |
7617 | static void |
7618 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7619 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7620 | { |
7621 | struct drm_device *dev = crtc->base.dev; | |
7622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7623 | u32 val, base, offset; | |
7624 | int pipe = crtc->pipe, plane = crtc->plane; | |
7625 | int fourcc, pixel_format; | |
6761dd31 | 7626 | unsigned int aligned_height; |
b113d5ee | 7627 | struct drm_framebuffer *fb; |
1b842c89 | 7628 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7629 | |
42a7b088 DL |
7630 | val = I915_READ(DSPCNTR(plane)); |
7631 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7632 | return; | |
7633 | ||
d9806c9f | 7634 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7635 | if (!intel_fb) { |
1ad292b5 JB |
7636 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7637 | return; | |
7638 | } | |
7639 | ||
1b842c89 DL |
7640 | fb = &intel_fb->base; |
7641 | ||
18c5247e DV |
7642 | if (INTEL_INFO(dev)->gen >= 4) { |
7643 | if (val & DISPPLANE_TILED) { | |
49af449b | 7644 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7645 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7646 | } | |
7647 | } | |
1ad292b5 JB |
7648 | |
7649 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7650 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7651 | fb->pixel_format = fourcc; |
7652 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7653 | |
7654 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7655 | if (plane_config->tiling) |
1ad292b5 JB |
7656 | offset = I915_READ(DSPTILEOFF(plane)); |
7657 | else | |
7658 | offset = I915_READ(DSPLINOFF(plane)); | |
7659 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7660 | } else { | |
7661 | base = I915_READ(DSPADDR(plane)); | |
7662 | } | |
7663 | plane_config->base = base; | |
7664 | ||
7665 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7666 | fb->width = ((val >> 16) & 0xfff) + 1; |
7667 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7668 | |
7669 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7670 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7671 | |
b113d5ee | 7672 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7673 | fb->pixel_format, |
7674 | fb->modifier[0]); | |
1ad292b5 | 7675 | |
f37b5c2b | 7676 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7677 | |
2844a921 DL |
7678 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7679 | pipe_name(pipe), plane, fb->width, fb->height, | |
7680 | fb->bits_per_pixel, base, fb->pitches[0], | |
7681 | plane_config->size); | |
1ad292b5 | 7682 | |
2d14030b | 7683 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7684 | } |
7685 | ||
70b23a98 | 7686 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7687 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7688 | { |
7689 | struct drm_device *dev = crtc->base.dev; | |
7690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7691 | int pipe = pipe_config->cpu_transcoder; | |
7692 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
7693 | intel_clock_t clock; | |
7694 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
7695 | int refclk = 100000; | |
7696 | ||
7697 | mutex_lock(&dev_priv->dpio_lock); | |
7698 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
7699 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7700 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7701 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
7702 | mutex_unlock(&dev_priv->dpio_lock); | |
7703 | ||
7704 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
7705 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
7706 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
7707 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7708 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7709 | ||
7710 | chv_clock(refclk, &clock); | |
7711 | ||
7712 | /* clock.dot is the fast clock */ | |
7713 | pipe_config->port_clock = clock.dot / 5; | |
7714 | } | |
7715 | ||
0e8ffe1b | 7716 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7717 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
7718 | { |
7719 | struct drm_device *dev = crtc->base.dev; | |
7720 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7721 | uint32_t tmp; | |
7722 | ||
f458ebbc DV |
7723 | if (!intel_display_power_is_enabled(dev_priv, |
7724 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
7725 | return false; |
7726 | ||
e143a21c | 7727 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7728 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7729 | |
0e8ffe1b DV |
7730 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7731 | if (!(tmp & PIPECONF_ENABLE)) | |
7732 | return false; | |
7733 | ||
42571aef VS |
7734 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
7735 | switch (tmp & PIPECONF_BPC_MASK) { | |
7736 | case PIPECONF_6BPC: | |
7737 | pipe_config->pipe_bpp = 18; | |
7738 | break; | |
7739 | case PIPECONF_8BPC: | |
7740 | pipe_config->pipe_bpp = 24; | |
7741 | break; | |
7742 | case PIPECONF_10BPC: | |
7743 | pipe_config->pipe_bpp = 30; | |
7744 | break; | |
7745 | default: | |
7746 | break; | |
7747 | } | |
7748 | } | |
7749 | ||
b5a9fa09 DV |
7750 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
7751 | pipe_config->limited_color_range = true; | |
7752 | ||
282740f7 VS |
7753 | if (INTEL_INFO(dev)->gen < 4) |
7754 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
7755 | ||
1bd1bd80 DV |
7756 | intel_get_pipe_timings(crtc, pipe_config); |
7757 | ||
2fa2fe9a DV |
7758 | i9xx_get_pfit_config(crtc, pipe_config); |
7759 | ||
6c49f241 DV |
7760 | if (INTEL_INFO(dev)->gen >= 4) { |
7761 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
7762 | pipe_config->pixel_multiplier = | |
7763 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7764 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7765 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
7766 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
7767 | tmp = I915_READ(DPLL(crtc->pipe)); | |
7768 | pipe_config->pixel_multiplier = | |
7769 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7770 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7771 | } else { | |
7772 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7773 | * port and will be fixed up in the encoder->get_config | |
7774 | * function. */ | |
7775 | pipe_config->pixel_multiplier = 1; | |
7776 | } | |
8bcc2795 DV |
7777 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
7778 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
7779 | /* |
7780 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7781 | * on 830. Filter it out here so that we don't | |
7782 | * report errors due to that. | |
7783 | */ | |
7784 | if (IS_I830(dev)) | |
7785 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
7786 | ||
8bcc2795 DV |
7787 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7788 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7789 | } else { |
7790 | /* Mask out read-only status bits. */ | |
7791 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7792 | DPLL_PORTC_READY_MASK | | |
7793 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7794 | } |
6c49f241 | 7795 | |
70b23a98 VS |
7796 | if (IS_CHERRYVIEW(dev)) |
7797 | chv_crtc_clock_get(crtc, pipe_config); | |
7798 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
7799 | vlv_crtc_clock_get(crtc, pipe_config); |
7800 | else | |
7801 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7802 | |
0e8ffe1b DV |
7803 | return true; |
7804 | } | |
7805 | ||
dde86e2d | 7806 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
7807 | { |
7808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 7809 | struct intel_encoder *encoder; |
74cfd7ac | 7810 | u32 val, final; |
13d83a67 | 7811 | bool has_lvds = false; |
199e5d79 | 7812 | bool has_cpu_edp = false; |
199e5d79 | 7813 | bool has_panel = false; |
99eb6a01 KP |
7814 | bool has_ck505 = false; |
7815 | bool can_ssc = false; | |
13d83a67 JB |
7816 | |
7817 | /* We need to take the global config into account */ | |
b2784e15 | 7818 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
7819 | switch (encoder->type) { |
7820 | case INTEL_OUTPUT_LVDS: | |
7821 | has_panel = true; | |
7822 | has_lvds = true; | |
7823 | break; | |
7824 | case INTEL_OUTPUT_EDP: | |
7825 | has_panel = true; | |
2de6905f | 7826 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7827 | has_cpu_edp = true; |
7828 | break; | |
6847d71b PZ |
7829 | default: |
7830 | break; | |
13d83a67 JB |
7831 | } |
7832 | } | |
7833 | ||
99eb6a01 | 7834 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 7835 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7836 | can_ssc = has_ck505; |
7837 | } else { | |
7838 | has_ck505 = false; | |
7839 | can_ssc = true; | |
7840 | } | |
7841 | ||
2de6905f ID |
7842 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
7843 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
7844 | |
7845 | /* Ironlake: try to setup display ref clock before DPLL | |
7846 | * enabling. This is only under driver's control after | |
7847 | * PCH B stepping, previous chipset stepping should be | |
7848 | * ignoring this setting. | |
7849 | */ | |
74cfd7ac CW |
7850 | val = I915_READ(PCH_DREF_CONTROL); |
7851 | ||
7852 | /* As we must carefully and slowly disable/enable each source in turn, | |
7853 | * compute the final state we want first and check if we need to | |
7854 | * make any changes at all. | |
7855 | */ | |
7856 | final = val; | |
7857 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7858 | if (has_ck505) | |
7859 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7860 | else | |
7861 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7862 | ||
7863 | final &= ~DREF_SSC_SOURCE_MASK; | |
7864 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
7865 | final &= ~DREF_SSC1_ENABLE; | |
7866 | ||
7867 | if (has_panel) { | |
7868 | final |= DREF_SSC_SOURCE_ENABLE; | |
7869 | ||
7870 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7871 | final |= DREF_SSC1_ENABLE; | |
7872 | ||
7873 | if (has_cpu_edp) { | |
7874 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7875 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7876 | else | |
7877 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7878 | } else | |
7879 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7880 | } else { | |
7881 | final |= DREF_SSC_SOURCE_DISABLE; | |
7882 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7883 | } | |
7884 | ||
7885 | if (final == val) | |
7886 | return; | |
7887 | ||
13d83a67 | 7888 | /* Always enable nonspread source */ |
74cfd7ac | 7889 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7890 | |
99eb6a01 | 7891 | if (has_ck505) |
74cfd7ac | 7892 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7893 | else |
74cfd7ac | 7894 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7895 | |
199e5d79 | 7896 | if (has_panel) { |
74cfd7ac CW |
7897 | val &= ~DREF_SSC_SOURCE_MASK; |
7898 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7899 | |
199e5d79 | 7900 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7901 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7902 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7903 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7904 | } else |
74cfd7ac | 7905 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7906 | |
7907 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7908 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7909 | POSTING_READ(PCH_DREF_CONTROL); |
7910 | udelay(200); | |
7911 | ||
74cfd7ac | 7912 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7913 | |
7914 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7915 | if (has_cpu_edp) { |
99eb6a01 | 7916 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7917 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7918 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7919 | } else |
74cfd7ac | 7920 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7921 | } else |
74cfd7ac | 7922 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7923 | |
74cfd7ac | 7924 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7925 | POSTING_READ(PCH_DREF_CONTROL); |
7926 | udelay(200); | |
7927 | } else { | |
7928 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7929 | ||
74cfd7ac | 7930 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7931 | |
7932 | /* Turn off CPU output */ | |
74cfd7ac | 7933 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7934 | |
74cfd7ac | 7935 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7936 | POSTING_READ(PCH_DREF_CONTROL); |
7937 | udelay(200); | |
7938 | ||
7939 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7940 | val &= ~DREF_SSC_SOURCE_MASK; |
7941 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7942 | |
7943 | /* Turn off SSC1 */ | |
74cfd7ac | 7944 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7945 | |
74cfd7ac | 7946 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7947 | POSTING_READ(PCH_DREF_CONTROL); |
7948 | udelay(200); | |
7949 | } | |
74cfd7ac CW |
7950 | |
7951 | BUG_ON(val != final); | |
13d83a67 JB |
7952 | } |
7953 | ||
f31f2d55 | 7954 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7955 | { |
f31f2d55 | 7956 | uint32_t tmp; |
dde86e2d | 7957 | |
0ff066a9 PZ |
7958 | tmp = I915_READ(SOUTH_CHICKEN2); |
7959 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7960 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7961 | |
0ff066a9 PZ |
7962 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7963 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7964 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7965 | |
0ff066a9 PZ |
7966 | tmp = I915_READ(SOUTH_CHICKEN2); |
7967 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7968 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7969 | |
0ff066a9 PZ |
7970 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7971 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7972 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7973 | } |
7974 | ||
7975 | /* WaMPhyProgramming:hsw */ | |
7976 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7977 | { | |
7978 | uint32_t tmp; | |
dde86e2d PZ |
7979 | |
7980 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7981 | tmp &= ~(0xFF << 24); | |
7982 | tmp |= (0x12 << 24); | |
7983 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7984 | ||
dde86e2d PZ |
7985 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7986 | tmp |= (1 << 11); | |
7987 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7988 | ||
7989 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7990 | tmp |= (1 << 11); | |
7991 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7992 | ||
dde86e2d PZ |
7993 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7994 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7995 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7996 | ||
7997 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7998 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7999 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8000 | ||
0ff066a9 PZ |
8001 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8002 | tmp &= ~(7 << 13); | |
8003 | tmp |= (5 << 13); | |
8004 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8005 | |
0ff066a9 PZ |
8006 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8007 | tmp &= ~(7 << 13); | |
8008 | tmp |= (5 << 13); | |
8009 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8010 | |
8011 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8012 | tmp &= ~0xFF; | |
8013 | tmp |= 0x1C; | |
8014 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8015 | ||
8016 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8017 | tmp &= ~0xFF; | |
8018 | tmp |= 0x1C; | |
8019 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8020 | ||
8021 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8022 | tmp &= ~(0xFF << 16); | |
8023 | tmp |= (0x1C << 16); | |
8024 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8025 | ||
8026 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8027 | tmp &= ~(0xFF << 16); | |
8028 | tmp |= (0x1C << 16); | |
8029 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8030 | ||
0ff066a9 PZ |
8031 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8032 | tmp |= (1 << 27); | |
8033 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8034 | |
0ff066a9 PZ |
8035 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8036 | tmp |= (1 << 27); | |
8037 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8038 | |
0ff066a9 PZ |
8039 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8040 | tmp &= ~(0xF << 28); | |
8041 | tmp |= (4 << 28); | |
8042 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8043 | |
0ff066a9 PZ |
8044 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8045 | tmp &= ~(0xF << 28); | |
8046 | tmp |= (4 << 28); | |
8047 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8048 | } |
8049 | ||
2fa86a1f PZ |
8050 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8051 | * Programming" based on the parameters passed: | |
8052 | * - Sequence to enable CLKOUT_DP | |
8053 | * - Sequence to enable CLKOUT_DP without spread | |
8054 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8055 | */ | |
8056 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8057 | bool with_fdi) | |
f31f2d55 PZ |
8058 | { |
8059 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8060 | uint32_t reg, tmp; |
8061 | ||
8062 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8063 | with_spread = true; | |
8064 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
8065 | with_fdi, "LP PCH doesn't have FDI\n")) | |
8066 | with_fdi = false; | |
f31f2d55 PZ |
8067 | |
8068 | mutex_lock(&dev_priv->dpio_lock); | |
8069 | ||
8070 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8071 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8072 | tmp |= SBI_SSCCTL_PATHALT; | |
8073 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8074 | ||
8075 | udelay(24); | |
8076 | ||
2fa86a1f PZ |
8077 | if (with_spread) { |
8078 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8079 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8080 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8081 | |
2fa86a1f PZ |
8082 | if (with_fdi) { |
8083 | lpt_reset_fdi_mphy(dev_priv); | |
8084 | lpt_program_fdi_mphy(dev_priv); | |
8085 | } | |
8086 | } | |
dde86e2d | 8087 | |
2fa86a1f PZ |
8088 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
8089 | SBI_GEN0 : SBI_DBUFF0; | |
8090 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8091 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8092 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
8093 | |
8094 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
8095 | } |
8096 | ||
47701c3b PZ |
8097 | /* Sequence to disable CLKOUT_DP */ |
8098 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8099 | { | |
8100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8101 | uint32_t reg, tmp; | |
8102 | ||
8103 | mutex_lock(&dev_priv->dpio_lock); | |
8104 | ||
8105 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
8106 | SBI_GEN0 : SBI_DBUFF0; | |
8107 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8108 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8109 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8110 | ||
8111 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8112 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8113 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8114 | tmp |= SBI_SSCCTL_PATHALT; | |
8115 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8116 | udelay(32); | |
8117 | } | |
8118 | tmp |= SBI_SSCCTL_DISABLE; | |
8119 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8120 | } | |
8121 | ||
8122 | mutex_unlock(&dev_priv->dpio_lock); | |
8123 | } | |
8124 | ||
bf8fa3d3 PZ |
8125 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8126 | { | |
bf8fa3d3 PZ |
8127 | struct intel_encoder *encoder; |
8128 | bool has_vga = false; | |
8129 | ||
b2784e15 | 8130 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8131 | switch (encoder->type) { |
8132 | case INTEL_OUTPUT_ANALOG: | |
8133 | has_vga = true; | |
8134 | break; | |
6847d71b PZ |
8135 | default: |
8136 | break; | |
bf8fa3d3 PZ |
8137 | } |
8138 | } | |
8139 | ||
47701c3b PZ |
8140 | if (has_vga) |
8141 | lpt_enable_clkout_dp(dev, true, true); | |
8142 | else | |
8143 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8144 | } |
8145 | ||
dde86e2d PZ |
8146 | /* |
8147 | * Initialize reference clocks when the driver loads | |
8148 | */ | |
8149 | void intel_init_pch_refclk(struct drm_device *dev) | |
8150 | { | |
8151 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8152 | ironlake_init_pch_refclk(dev); | |
8153 | else if (HAS_PCH_LPT(dev)) | |
8154 | lpt_init_pch_refclk(dev); | |
8155 | } | |
8156 | ||
55bb9992 | 8157 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8158 | { |
55bb9992 | 8159 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8160 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8161 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8162 | struct drm_connector *connector; |
55bb9992 | 8163 | struct drm_connector_state *connector_state; |
d9d444cb | 8164 | struct intel_encoder *encoder; |
55bb9992 | 8165 | int num_connectors = 0, i; |
d9d444cb JB |
8166 | bool is_lvds = false; |
8167 | ||
da3ced29 | 8168 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8169 | if (connector_state->crtc != crtc_state->base.crtc) |
8170 | continue; | |
8171 | ||
8172 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8173 | ||
d9d444cb JB |
8174 | switch (encoder->type) { |
8175 | case INTEL_OUTPUT_LVDS: | |
8176 | is_lvds = true; | |
8177 | break; | |
6847d71b PZ |
8178 | default: |
8179 | break; | |
d9d444cb JB |
8180 | } |
8181 | num_connectors++; | |
8182 | } | |
8183 | ||
8184 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8185 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8186 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8187 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8188 | } |
8189 | ||
8190 | return 120000; | |
8191 | } | |
8192 | ||
6ff93609 | 8193 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8194 | { |
c8203565 | 8195 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8197 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8198 | uint32_t val; |
8199 | ||
78114071 | 8200 | val = 0; |
c8203565 | 8201 | |
6e3c9717 | 8202 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8203 | case 18: |
dfd07d72 | 8204 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8205 | break; |
8206 | case 24: | |
dfd07d72 | 8207 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8208 | break; |
8209 | case 30: | |
dfd07d72 | 8210 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8211 | break; |
8212 | case 36: | |
dfd07d72 | 8213 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8214 | break; |
8215 | default: | |
cc769b62 PZ |
8216 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8217 | BUG(); | |
c8203565 PZ |
8218 | } |
8219 | ||
6e3c9717 | 8220 | if (intel_crtc->config->dither) |
c8203565 PZ |
8221 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8222 | ||
6e3c9717 | 8223 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8224 | val |= PIPECONF_INTERLACED_ILK; |
8225 | else | |
8226 | val |= PIPECONF_PROGRESSIVE; | |
8227 | ||
6e3c9717 | 8228 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8229 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8230 | |
c8203565 PZ |
8231 | I915_WRITE(PIPECONF(pipe), val); |
8232 | POSTING_READ(PIPECONF(pipe)); | |
8233 | } | |
8234 | ||
86d3efce VS |
8235 | /* |
8236 | * Set up the pipe CSC unit. | |
8237 | * | |
8238 | * Currently only full range RGB to limited range RGB conversion | |
8239 | * is supported, but eventually this should handle various | |
8240 | * RGB<->YCbCr scenarios as well. | |
8241 | */ | |
50f3b016 | 8242 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8243 | { |
8244 | struct drm_device *dev = crtc->dev; | |
8245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8246 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8247 | int pipe = intel_crtc->pipe; | |
8248 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8249 | ||
8250 | /* | |
8251 | * TODO: Check what kind of values actually come out of the pipe | |
8252 | * with these coeff/postoff values and adjust to get the best | |
8253 | * accuracy. Perhaps we even need to take the bpc value into | |
8254 | * consideration. | |
8255 | */ | |
8256 | ||
6e3c9717 | 8257 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8258 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8259 | ||
8260 | /* | |
8261 | * GY/GU and RY/RU should be the other way around according | |
8262 | * to BSpec, but reality doesn't agree. Just set them up in | |
8263 | * a way that results in the correct picture. | |
8264 | */ | |
8265 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8266 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8267 | ||
8268 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8269 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8270 | ||
8271 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8272 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8273 | ||
8274 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8275 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8276 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8277 | ||
8278 | if (INTEL_INFO(dev)->gen > 6) { | |
8279 | uint16_t postoff = 0; | |
8280 | ||
6e3c9717 | 8281 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8282 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8283 | |
8284 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8285 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8286 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8287 | ||
8288 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8289 | } else { | |
8290 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8291 | ||
6e3c9717 | 8292 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8293 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8294 | ||
8295 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8296 | } | |
8297 | } | |
8298 | ||
6ff93609 | 8299 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8300 | { |
756f85cf PZ |
8301 | struct drm_device *dev = crtc->dev; |
8302 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8303 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8304 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8305 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8306 | uint32_t val; |
8307 | ||
3eff4faa | 8308 | val = 0; |
ee2b0b38 | 8309 | |
6e3c9717 | 8310 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8311 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8312 | ||
6e3c9717 | 8313 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8314 | val |= PIPECONF_INTERLACED_ILK; |
8315 | else | |
8316 | val |= PIPECONF_PROGRESSIVE; | |
8317 | ||
702e7a56 PZ |
8318 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8319 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8320 | |
8321 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8322 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8323 | |
3cdf122c | 8324 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8325 | val = 0; |
8326 | ||
6e3c9717 | 8327 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8328 | case 18: |
8329 | val |= PIPEMISC_DITHER_6_BPC; | |
8330 | break; | |
8331 | case 24: | |
8332 | val |= PIPEMISC_DITHER_8_BPC; | |
8333 | break; | |
8334 | case 30: | |
8335 | val |= PIPEMISC_DITHER_10_BPC; | |
8336 | break; | |
8337 | case 36: | |
8338 | val |= PIPEMISC_DITHER_12_BPC; | |
8339 | break; | |
8340 | default: | |
8341 | /* Case prevented by pipe_config_set_bpp. */ | |
8342 | BUG(); | |
8343 | } | |
8344 | ||
6e3c9717 | 8345 | if (intel_crtc->config->dither) |
756f85cf PZ |
8346 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8347 | ||
8348 | I915_WRITE(PIPEMISC(pipe), val); | |
8349 | } | |
ee2b0b38 PZ |
8350 | } |
8351 | ||
6591c6e4 | 8352 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8353 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8354 | intel_clock_t *clock, |
8355 | bool *has_reduced_clock, | |
8356 | intel_clock_t *reduced_clock) | |
8357 | { | |
8358 | struct drm_device *dev = crtc->dev; | |
8359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8360 | int refclk; |
d4906093 | 8361 | const intel_limit_t *limit; |
a16af721 | 8362 | bool ret, is_lvds = false; |
79e53945 | 8363 | |
a93e255f | 8364 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 8365 | |
55bb9992 | 8366 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8367 | |
d4906093 ML |
8368 | /* |
8369 | * Returns a set of divisors for the desired target clock with the given | |
8370 | * refclk, or FALSE. The returned values represent the clock equation: | |
8371 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8372 | */ | |
a93e255f ACO |
8373 | limit = intel_limit(crtc_state, refclk); |
8374 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8375 | crtc_state->port_clock, |
ee9300bb | 8376 | refclk, NULL, clock); |
6591c6e4 PZ |
8377 | if (!ret) |
8378 | return false; | |
cda4b7d3 | 8379 | |
ddc9003c | 8380 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
8381 | /* |
8382 | * Ensure we match the reduced clock's P to the target clock. | |
8383 | * If the clocks don't match, we can't switch the display clock | |
8384 | * by using the FP0/FP1. In such case we will disable the LVDS | |
8385 | * downclock feature. | |
8386 | */ | |
ee9300bb | 8387 | *has_reduced_clock = |
a93e255f | 8388 | dev_priv->display.find_dpll(limit, crtc_state, |
ee9300bb DV |
8389 | dev_priv->lvds_downclock, |
8390 | refclk, clock, | |
8391 | reduced_clock); | |
652c393a | 8392 | } |
61e9653f | 8393 | |
6591c6e4 PZ |
8394 | return true; |
8395 | } | |
8396 | ||
d4b1931c PZ |
8397 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8398 | { | |
8399 | /* | |
8400 | * Account for spread spectrum to avoid | |
8401 | * oversubscribing the link. Max center spread | |
8402 | * is 2.5%; use 5% for safety's sake. | |
8403 | */ | |
8404 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8405 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8406 | } |
8407 | ||
7429e9d4 | 8408 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8409 | { |
7429e9d4 | 8410 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8411 | } |
8412 | ||
de13a2e3 | 8413 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8414 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8415 | u32 *fp, |
9a7c7890 | 8416 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8417 | { |
de13a2e3 | 8418 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8419 | struct drm_device *dev = crtc->dev; |
8420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8421 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8422 | struct drm_connector *connector; |
55bb9992 ACO |
8423 | struct drm_connector_state *connector_state; |
8424 | struct intel_encoder *encoder; | |
de13a2e3 | 8425 | uint32_t dpll; |
55bb9992 | 8426 | int factor, num_connectors = 0, i; |
09ede541 | 8427 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8428 | |
da3ced29 | 8429 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8430 | if (connector_state->crtc != crtc_state->base.crtc) |
8431 | continue; | |
8432 | ||
8433 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8434 | ||
8435 | switch (encoder->type) { | |
79e53945 JB |
8436 | case INTEL_OUTPUT_LVDS: |
8437 | is_lvds = true; | |
8438 | break; | |
8439 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8440 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8441 | is_sdvo = true; |
79e53945 | 8442 | break; |
6847d71b PZ |
8443 | default: |
8444 | break; | |
79e53945 | 8445 | } |
43565a06 | 8446 | |
c751ce4f | 8447 | num_connectors++; |
79e53945 | 8448 | } |
79e53945 | 8449 | |
c1858123 | 8450 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8451 | factor = 21; |
8452 | if (is_lvds) { | |
8453 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8454 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8455 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8456 | factor = 25; |
190f68c5 | 8457 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8458 | factor = 20; |
c1858123 | 8459 | |
190f68c5 | 8460 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8461 | *fp |= FP_CB_TUNE; |
2c07245f | 8462 | |
9a7c7890 DV |
8463 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8464 | *fp2 |= FP_CB_TUNE; | |
8465 | ||
5eddb70b | 8466 | dpll = 0; |
2c07245f | 8467 | |
a07d6787 EA |
8468 | if (is_lvds) |
8469 | dpll |= DPLLB_MODE_LVDS; | |
8470 | else | |
8471 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8472 | |
190f68c5 | 8473 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8474 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8475 | |
8476 | if (is_sdvo) | |
4a33e48d | 8477 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8478 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8479 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8480 | |
a07d6787 | 8481 | /* compute bitmask from p1 value */ |
190f68c5 | 8482 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8483 | /* also FPA1 */ |
190f68c5 | 8484 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8485 | |
190f68c5 | 8486 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8487 | case 5: |
8488 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8489 | break; | |
8490 | case 7: | |
8491 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8492 | break; | |
8493 | case 10: | |
8494 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8495 | break; | |
8496 | case 14: | |
8497 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8498 | break; | |
79e53945 JB |
8499 | } |
8500 | ||
b4c09f3b | 8501 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8502 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8503 | else |
8504 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8505 | ||
959e16d6 | 8506 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8507 | } |
8508 | ||
190f68c5 ACO |
8509 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8510 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8511 | { |
c7653199 | 8512 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8513 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8514 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8515 | bool ok, has_reduced_clock = false; |
8b47047b | 8516 | bool is_lvds = false; |
e2b78267 | 8517 | struct intel_shared_dpll *pll; |
de13a2e3 | 8518 | |
409ee761 | 8519 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8520 | |
5dc5298b PZ |
8521 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8522 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8523 | |
190f68c5 | 8524 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8525 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8526 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8527 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8528 | return -EINVAL; | |
79e53945 | 8529 | } |
f47709a9 | 8530 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8531 | if (!crtc_state->clock_set) { |
8532 | crtc_state->dpll.n = clock.n; | |
8533 | crtc_state->dpll.m1 = clock.m1; | |
8534 | crtc_state->dpll.m2 = clock.m2; | |
8535 | crtc_state->dpll.p1 = clock.p1; | |
8536 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8537 | } |
79e53945 | 8538 | |
5dc5298b | 8539 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8540 | if (crtc_state->has_pch_encoder) { |
8541 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8542 | if (has_reduced_clock) |
7429e9d4 | 8543 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8544 | |
190f68c5 | 8545 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8546 | &fp, &reduced_clock, |
8547 | has_reduced_clock ? &fp2 : NULL); | |
8548 | ||
190f68c5 ACO |
8549 | crtc_state->dpll_hw_state.dpll = dpll; |
8550 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8551 | if (has_reduced_clock) |
190f68c5 | 8552 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8553 | else |
190f68c5 | 8554 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8555 | |
190f68c5 | 8556 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8557 | if (pll == NULL) { |
84f44ce7 | 8558 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8559 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8560 | return -EINVAL; |
8561 | } | |
3fb37703 | 8562 | } |
79e53945 | 8563 | |
ab585dea | 8564 | if (is_lvds && has_reduced_clock) |
c7653199 | 8565 | crtc->lowfreq_avail = true; |
bcd644e0 | 8566 | else |
c7653199 | 8567 | crtc->lowfreq_avail = false; |
e2b78267 | 8568 | |
c8f7a0db | 8569 | return 0; |
79e53945 JB |
8570 | } |
8571 | ||
eb14cb74 VS |
8572 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8573 | struct intel_link_m_n *m_n) | |
8574 | { | |
8575 | struct drm_device *dev = crtc->base.dev; | |
8576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8577 | enum pipe pipe = crtc->pipe; | |
8578 | ||
8579 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8580 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8581 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8582 | & ~TU_SIZE_MASK; | |
8583 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8584 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8585 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8586 | } | |
8587 | ||
8588 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8589 | enum transcoder transcoder, | |
b95af8be VK |
8590 | struct intel_link_m_n *m_n, |
8591 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8592 | { |
8593 | struct drm_device *dev = crtc->base.dev; | |
8594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8595 | enum pipe pipe = crtc->pipe; |
72419203 | 8596 | |
eb14cb74 VS |
8597 | if (INTEL_INFO(dev)->gen >= 5) { |
8598 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8599 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8600 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8601 | & ~TU_SIZE_MASK; | |
8602 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8603 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8604 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8605 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8606 | * gen < 8) and if DRRS is supported (to make sure the | |
8607 | * registers are not unnecessarily read). | |
8608 | */ | |
8609 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8610 | crtc->config->has_drrs) { |
b95af8be VK |
8611 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8612 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8613 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8614 | & ~TU_SIZE_MASK; | |
8615 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8616 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8617 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8618 | } | |
eb14cb74 VS |
8619 | } else { |
8620 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8621 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8622 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8623 | & ~TU_SIZE_MASK; | |
8624 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8625 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8626 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8627 | } | |
8628 | } | |
8629 | ||
8630 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8631 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8632 | { |
681a8504 | 8633 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8634 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8635 | else | |
8636 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8637 | &pipe_config->dp_m_n, |
8638 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8639 | } |
72419203 | 8640 | |
eb14cb74 | 8641 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8642 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8643 | { |
8644 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8645 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8646 | } |
8647 | ||
bd2e244f | 8648 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8649 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8650 | { |
8651 | struct drm_device *dev = crtc->base.dev; | |
8652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8653 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8654 | uint32_t ps_ctrl = 0; | |
8655 | int id = -1; | |
8656 | int i; | |
bd2e244f | 8657 | |
a1b2278e CK |
8658 | /* find scaler attached to this pipe */ |
8659 | for (i = 0; i < crtc->num_scalers; i++) { | |
8660 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8661 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8662 | id = i; | |
8663 | pipe_config->pch_pfit.enabled = true; | |
8664 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8665 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8666 | break; | |
8667 | } | |
8668 | } | |
bd2e244f | 8669 | |
a1b2278e CK |
8670 | scaler_state->scaler_id = id; |
8671 | if (id >= 0) { | |
8672 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8673 | } else { | |
8674 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8675 | } |
8676 | } | |
8677 | ||
5724dbd1 DL |
8678 | static void |
8679 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8680 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8681 | { |
8682 | struct drm_device *dev = crtc->base.dev; | |
8683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8684 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8685 | int pipe = crtc->pipe; |
8686 | int fourcc, pixel_format; | |
6761dd31 | 8687 | unsigned int aligned_height; |
bc8d7dff | 8688 | struct drm_framebuffer *fb; |
1b842c89 | 8689 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8690 | |
d9806c9f | 8691 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8692 | if (!intel_fb) { |
bc8d7dff DL |
8693 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8694 | return; | |
8695 | } | |
8696 | ||
1b842c89 DL |
8697 | fb = &intel_fb->base; |
8698 | ||
bc8d7dff | 8699 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8700 | if (!(val & PLANE_CTL_ENABLE)) |
8701 | goto error; | |
8702 | ||
bc8d7dff DL |
8703 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8704 | fourcc = skl_format_to_fourcc(pixel_format, | |
8705 | val & PLANE_CTL_ORDER_RGBX, | |
8706 | val & PLANE_CTL_ALPHA_MASK); | |
8707 | fb->pixel_format = fourcc; | |
8708 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8709 | ||
40f46283 DL |
8710 | tiling = val & PLANE_CTL_TILED_MASK; |
8711 | switch (tiling) { | |
8712 | case PLANE_CTL_TILED_LINEAR: | |
8713 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
8714 | break; | |
8715 | case PLANE_CTL_TILED_X: | |
8716 | plane_config->tiling = I915_TILING_X; | |
8717 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
8718 | break; | |
8719 | case PLANE_CTL_TILED_Y: | |
8720 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
8721 | break; | |
8722 | case PLANE_CTL_TILED_YF: | |
8723 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
8724 | break; | |
8725 | default: | |
8726 | MISSING_CASE(tiling); | |
8727 | goto error; | |
8728 | } | |
8729 | ||
bc8d7dff DL |
8730 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8731 | plane_config->base = base; | |
8732 | ||
8733 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8734 | ||
8735 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8736 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8737 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8738 | ||
8739 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
8740 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
8741 | fb->pixel_format); | |
bc8d7dff DL |
8742 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8743 | ||
8744 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
8745 | fb->pixel_format, |
8746 | fb->modifier[0]); | |
bc8d7dff | 8747 | |
f37b5c2b | 8748 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8749 | |
8750 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8751 | pipe_name(pipe), fb->width, fb->height, | |
8752 | fb->bits_per_pixel, base, fb->pitches[0], | |
8753 | plane_config->size); | |
8754 | ||
2d14030b | 8755 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8756 | return; |
8757 | ||
8758 | error: | |
8759 | kfree(fb); | |
8760 | } | |
8761 | ||
2fa2fe9a | 8762 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8763 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8764 | { |
8765 | struct drm_device *dev = crtc->base.dev; | |
8766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8767 | uint32_t tmp; | |
8768 | ||
8769 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8770 | ||
8771 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8772 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8773 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8774 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8775 | |
8776 | /* We currently do not free assignements of panel fitters on | |
8777 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8778 | * differentiates them) so just WARN about this case for now. */ | |
8779 | if (IS_GEN7(dev)) { | |
8780 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
8781 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8782 | } | |
2fa2fe9a | 8783 | } |
79e53945 JB |
8784 | } |
8785 | ||
5724dbd1 DL |
8786 | static void |
8787 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8788 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8789 | { |
8790 | struct drm_device *dev = crtc->base.dev; | |
8791 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8792 | u32 val, base, offset; | |
aeee5a49 | 8793 | int pipe = crtc->pipe; |
4c6baa59 | 8794 | int fourcc, pixel_format; |
6761dd31 | 8795 | unsigned int aligned_height; |
b113d5ee | 8796 | struct drm_framebuffer *fb; |
1b842c89 | 8797 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8798 | |
42a7b088 DL |
8799 | val = I915_READ(DSPCNTR(pipe)); |
8800 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8801 | return; | |
8802 | ||
d9806c9f | 8803 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8804 | if (!intel_fb) { |
4c6baa59 JB |
8805 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8806 | return; | |
8807 | } | |
8808 | ||
1b842c89 DL |
8809 | fb = &intel_fb->base; |
8810 | ||
18c5247e DV |
8811 | if (INTEL_INFO(dev)->gen >= 4) { |
8812 | if (val & DISPPLANE_TILED) { | |
49af449b | 8813 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8814 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8815 | } | |
8816 | } | |
4c6baa59 JB |
8817 | |
8818 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8819 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8820 | fb->pixel_format = fourcc; |
8821 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 8822 | |
aeee5a49 | 8823 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 8824 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 8825 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8826 | } else { |
49af449b | 8827 | if (plane_config->tiling) |
aeee5a49 | 8828 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8829 | else |
aeee5a49 | 8830 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8831 | } |
8832 | plane_config->base = base; | |
8833 | ||
8834 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8835 | fb->width = ((val >> 16) & 0xfff) + 1; |
8836 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8837 | |
8838 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8839 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8840 | |
b113d5ee | 8841 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8842 | fb->pixel_format, |
8843 | fb->modifier[0]); | |
4c6baa59 | 8844 | |
f37b5c2b | 8845 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8846 | |
2844a921 DL |
8847 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8848 | pipe_name(pipe), fb->width, fb->height, | |
8849 | fb->bits_per_pixel, base, fb->pitches[0], | |
8850 | plane_config->size); | |
b113d5ee | 8851 | |
2d14030b | 8852 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8853 | } |
8854 | ||
0e8ffe1b | 8855 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8856 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8857 | { |
8858 | struct drm_device *dev = crtc->base.dev; | |
8859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8860 | uint32_t tmp; | |
8861 | ||
f458ebbc DV |
8862 | if (!intel_display_power_is_enabled(dev_priv, |
8863 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
8864 | return false; |
8865 | ||
e143a21c | 8866 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8867 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8868 | |
0e8ffe1b DV |
8869 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8870 | if (!(tmp & PIPECONF_ENABLE)) | |
8871 | return false; | |
8872 | ||
42571aef VS |
8873 | switch (tmp & PIPECONF_BPC_MASK) { |
8874 | case PIPECONF_6BPC: | |
8875 | pipe_config->pipe_bpp = 18; | |
8876 | break; | |
8877 | case PIPECONF_8BPC: | |
8878 | pipe_config->pipe_bpp = 24; | |
8879 | break; | |
8880 | case PIPECONF_10BPC: | |
8881 | pipe_config->pipe_bpp = 30; | |
8882 | break; | |
8883 | case PIPECONF_12BPC: | |
8884 | pipe_config->pipe_bpp = 36; | |
8885 | break; | |
8886 | default: | |
8887 | break; | |
8888 | } | |
8889 | ||
b5a9fa09 DV |
8890 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8891 | pipe_config->limited_color_range = true; | |
8892 | ||
ab9412ba | 8893 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
8894 | struct intel_shared_dpll *pll; |
8895 | ||
88adfff1 DV |
8896 | pipe_config->has_pch_encoder = true; |
8897 | ||
627eb5a3 DV |
8898 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8899 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8900 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8901 | |
8902 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8903 | |
c0d43d62 | 8904 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
8905 | pipe_config->shared_dpll = |
8906 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
8907 | } else { |
8908 | tmp = I915_READ(PCH_DPLL_SEL); | |
8909 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8910 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
8911 | else | |
8912 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
8913 | } | |
66e985c0 DV |
8914 | |
8915 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8916 | ||
8917 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8918 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8919 | |
8920 | tmp = pipe_config->dpll_hw_state.dpll; | |
8921 | pipe_config->pixel_multiplier = | |
8922 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8923 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8924 | |
8925 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8926 | } else { |
8927 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8928 | } |
8929 | ||
1bd1bd80 DV |
8930 | intel_get_pipe_timings(crtc, pipe_config); |
8931 | ||
2fa2fe9a DV |
8932 | ironlake_get_pfit_config(crtc, pipe_config); |
8933 | ||
0e8ffe1b DV |
8934 | return true; |
8935 | } | |
8936 | ||
be256dc7 PZ |
8937 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8938 | { | |
8939 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 8940 | struct intel_crtc *crtc; |
be256dc7 | 8941 | |
d3fcc808 | 8942 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8943 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8944 | pipe_name(crtc->pipe)); |
8945 | ||
e2c719b7 RC |
8946 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8947 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
8948 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
8949 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
8950 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8951 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8952 | "CPU PWM1 enabled\n"); |
c5107b87 | 8953 | if (IS_HASWELL(dev)) |
e2c719b7 | 8954 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8955 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8956 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8957 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8958 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8959 | "Utility pin enabled\n"); |
e2c719b7 | 8960 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8961 | |
9926ada1 PZ |
8962 | /* |
8963 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8964 | * interrupts remain enabled. We used to check for that, but since it's | |
8965 | * gen-specific and since we only disable LCPLL after we fully disable | |
8966 | * the interrupts, the check below should be enough. | |
8967 | */ | |
e2c719b7 | 8968 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8969 | } |
8970 | ||
9ccd5aeb PZ |
8971 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8972 | { | |
8973 | struct drm_device *dev = dev_priv->dev; | |
8974 | ||
8975 | if (IS_HASWELL(dev)) | |
8976 | return I915_READ(D_COMP_HSW); | |
8977 | else | |
8978 | return I915_READ(D_COMP_BDW); | |
8979 | } | |
8980 | ||
3c4c9b81 PZ |
8981 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8982 | { | |
8983 | struct drm_device *dev = dev_priv->dev; | |
8984 | ||
8985 | if (IS_HASWELL(dev)) { | |
8986 | mutex_lock(&dev_priv->rps.hw_lock); | |
8987 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8988 | val)) | |
f475dadf | 8989 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8990 | mutex_unlock(&dev_priv->rps.hw_lock); |
8991 | } else { | |
9ccd5aeb PZ |
8992 | I915_WRITE(D_COMP_BDW, val); |
8993 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8994 | } |
be256dc7 PZ |
8995 | } |
8996 | ||
8997 | /* | |
8998 | * This function implements pieces of two sequences from BSpec: | |
8999 | * - Sequence for display software to disable LCPLL | |
9000 | * - Sequence for display software to allow package C8+ | |
9001 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9002 | * register. Callers should take care of disabling all the display engine | |
9003 | * functions, doing the mode unset, fixing interrupts, etc. | |
9004 | */ | |
6ff58d53 PZ |
9005 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9006 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9007 | { |
9008 | uint32_t val; | |
9009 | ||
9010 | assert_can_disable_lcpll(dev_priv); | |
9011 | ||
9012 | val = I915_READ(LCPLL_CTL); | |
9013 | ||
9014 | if (switch_to_fclk) { | |
9015 | val |= LCPLL_CD_SOURCE_FCLK; | |
9016 | I915_WRITE(LCPLL_CTL, val); | |
9017 | ||
9018 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9019 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9020 | DRM_ERROR("Switching to FCLK failed\n"); | |
9021 | ||
9022 | val = I915_READ(LCPLL_CTL); | |
9023 | } | |
9024 | ||
9025 | val |= LCPLL_PLL_DISABLE; | |
9026 | I915_WRITE(LCPLL_CTL, val); | |
9027 | POSTING_READ(LCPLL_CTL); | |
9028 | ||
9029 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9030 | DRM_ERROR("LCPLL still locked\n"); | |
9031 | ||
9ccd5aeb | 9032 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9033 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9034 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9035 | ndelay(100); |
9036 | ||
9ccd5aeb PZ |
9037 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9038 | 1)) | |
be256dc7 PZ |
9039 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9040 | ||
9041 | if (allow_power_down) { | |
9042 | val = I915_READ(LCPLL_CTL); | |
9043 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9044 | I915_WRITE(LCPLL_CTL, val); | |
9045 | POSTING_READ(LCPLL_CTL); | |
9046 | } | |
9047 | } | |
9048 | ||
9049 | /* | |
9050 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9051 | * source. | |
9052 | */ | |
6ff58d53 | 9053 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9054 | { |
9055 | uint32_t val; | |
9056 | ||
9057 | val = I915_READ(LCPLL_CTL); | |
9058 | ||
9059 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9060 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9061 | return; | |
9062 | ||
a8a8bd54 PZ |
9063 | /* |
9064 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9065 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9066 | */ |
59bad947 | 9067 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9068 | |
be256dc7 PZ |
9069 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9070 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9071 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9072 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9073 | } |
9074 | ||
9ccd5aeb | 9075 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9076 | val |= D_COMP_COMP_FORCE; |
9077 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9078 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9079 | |
9080 | val = I915_READ(LCPLL_CTL); | |
9081 | val &= ~LCPLL_PLL_DISABLE; | |
9082 | I915_WRITE(LCPLL_CTL, val); | |
9083 | ||
9084 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9085 | DRM_ERROR("LCPLL not locked yet\n"); | |
9086 | ||
9087 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9088 | val = I915_READ(LCPLL_CTL); | |
9089 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9090 | I915_WRITE(LCPLL_CTL, val); | |
9091 | ||
9092 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9093 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9094 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9095 | } | |
215733fa | 9096 | |
59bad947 | 9097 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
9098 | } |
9099 | ||
765dab67 PZ |
9100 | /* |
9101 | * Package states C8 and deeper are really deep PC states that can only be | |
9102 | * reached when all the devices on the system allow it, so even if the graphics | |
9103 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9104 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9105 | * | |
9106 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9107 | * well is disabled and most interrupts are disabled, and these are also | |
9108 | * requirements for runtime PM. When these conditions are met, we manually do | |
9109 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9110 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9111 | * hang the machine. | |
9112 | * | |
9113 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9114 | * the state of some registers, so when we come back from PC8+ we need to | |
9115 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9116 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9117 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9118 | * because of the runtime PM support). | |
9119 | * | |
9120 | * For more, read "Display Sequences for Package C8" on the hardware | |
9121 | * documentation. | |
9122 | */ | |
a14cb6fc | 9123 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9124 | { |
c67a470b PZ |
9125 | struct drm_device *dev = dev_priv->dev; |
9126 | uint32_t val; | |
9127 | ||
c67a470b PZ |
9128 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9129 | ||
c67a470b PZ |
9130 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
9131 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9132 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9133 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9134 | } | |
9135 | ||
9136 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9137 | hsw_disable_lcpll(dev_priv, true, true); |
9138 | } | |
9139 | ||
a14cb6fc | 9140 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9141 | { |
9142 | struct drm_device *dev = dev_priv->dev; | |
9143 | uint32_t val; | |
9144 | ||
c67a470b PZ |
9145 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9146 | ||
9147 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9148 | lpt_init_pch_refclk(dev); |
9149 | ||
9150 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
9151 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9152 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9153 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9154 | } | |
9155 | ||
9156 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9157 | } |
9158 | ||
a821fc46 | 9159 | static void broxton_modeset_global_resources(struct drm_atomic_state *old_state) |
f8437dd1 | 9160 | { |
a821fc46 | 9161 | struct drm_device *dev = old_state->dev; |
f8437dd1 | 9162 | struct drm_i915_private *dev_priv = dev->dev_private; |
a821fc46 | 9163 | int max_pixclk = intel_mode_max_pixclk(dev, NULL); |
f8437dd1 VK |
9164 | int req_cdclk; |
9165 | ||
9166 | /* see the comment in valleyview_modeset_global_resources */ | |
9167 | if (WARN_ON(max_pixclk < 0)) | |
9168 | return; | |
9169 | ||
9170 | req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
9171 | ||
9172 | if (req_cdclk != dev_priv->cdclk_freq) | |
9173 | broxton_set_cdclk(dev, req_cdclk); | |
9174 | } | |
9175 | ||
190f68c5 ACO |
9176 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9177 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9178 | { |
190f68c5 | 9179 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9180 | return -EINVAL; |
716c2e55 | 9181 | |
c7653199 | 9182 | crtc->lowfreq_avail = false; |
644cef34 | 9183 | |
c8f7a0db | 9184 | return 0; |
79e53945 JB |
9185 | } |
9186 | ||
3760b59c S |
9187 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9188 | enum port port, | |
9189 | struct intel_crtc_state *pipe_config) | |
9190 | { | |
9191 | switch (port) { | |
9192 | case PORT_A: | |
9193 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9194 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9195 | break; | |
9196 | case PORT_B: | |
9197 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9198 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9199 | break; | |
9200 | case PORT_C: | |
9201 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9202 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9203 | break; | |
9204 | default: | |
9205 | DRM_ERROR("Incorrect port type\n"); | |
9206 | } | |
9207 | } | |
9208 | ||
96b7dfb7 S |
9209 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9210 | enum port port, | |
5cec258b | 9211 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9212 | { |
3148ade7 | 9213 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9214 | |
9215 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9216 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9217 | ||
9218 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9219 | case SKL_DPLL0: |
9220 | /* | |
9221 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9222 | * of the shared DPLL framework and thus needs to be read out | |
9223 | * separately | |
9224 | */ | |
9225 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9226 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9227 | break; | |
96b7dfb7 S |
9228 | case SKL_DPLL1: |
9229 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9230 | break; | |
9231 | case SKL_DPLL2: | |
9232 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9233 | break; | |
9234 | case SKL_DPLL3: | |
9235 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9236 | break; | |
96b7dfb7 S |
9237 | } |
9238 | } | |
9239 | ||
7d2c8175 DL |
9240 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9241 | enum port port, | |
5cec258b | 9242 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9243 | { |
9244 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9245 | ||
9246 | switch (pipe_config->ddi_pll_sel) { | |
9247 | case PORT_CLK_SEL_WRPLL1: | |
9248 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9249 | break; | |
9250 | case PORT_CLK_SEL_WRPLL2: | |
9251 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9252 | break; | |
9253 | } | |
9254 | } | |
9255 | ||
26804afd | 9256 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9257 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9258 | { |
9259 | struct drm_device *dev = crtc->base.dev; | |
9260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9261 | struct intel_shared_dpll *pll; |
26804afd DV |
9262 | enum port port; |
9263 | uint32_t tmp; | |
9264 | ||
9265 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9266 | ||
9267 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9268 | ||
96b7dfb7 S |
9269 | if (IS_SKYLAKE(dev)) |
9270 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
3760b59c S |
9271 | else if (IS_BROXTON(dev)) |
9272 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9273 | else |
9274 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9275 | |
d452c5b6 DV |
9276 | if (pipe_config->shared_dpll >= 0) { |
9277 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9278 | ||
9279 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9280 | &pipe_config->dpll_hw_state)); | |
9281 | } | |
9282 | ||
26804afd DV |
9283 | /* |
9284 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9285 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9286 | * the PCH transcoder is on. | |
9287 | */ | |
ca370455 DL |
9288 | if (INTEL_INFO(dev)->gen < 9 && |
9289 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9290 | pipe_config->has_pch_encoder = true; |
9291 | ||
9292 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9293 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9294 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9295 | ||
9296 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9297 | } | |
9298 | } | |
9299 | ||
0e8ffe1b | 9300 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9301 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9302 | { |
9303 | struct drm_device *dev = crtc->base.dev; | |
9304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9305 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9306 | uint32_t tmp; |
9307 | ||
f458ebbc | 9308 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9309 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9310 | return false; | |
9311 | ||
e143a21c | 9312 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9313 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9314 | ||
eccb140b DV |
9315 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9316 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9317 | enum pipe trans_edp_pipe; | |
9318 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9319 | default: | |
9320 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9321 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9322 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9323 | trans_edp_pipe = PIPE_A; | |
9324 | break; | |
9325 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9326 | trans_edp_pipe = PIPE_B; | |
9327 | break; | |
9328 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9329 | trans_edp_pipe = PIPE_C; | |
9330 | break; | |
9331 | } | |
9332 | ||
9333 | if (trans_edp_pipe == crtc->pipe) | |
9334 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9335 | } | |
9336 | ||
f458ebbc | 9337 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9338 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9339 | return false; |
9340 | ||
eccb140b | 9341 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9342 | if (!(tmp & PIPECONF_ENABLE)) |
9343 | return false; | |
9344 | ||
26804afd | 9345 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9346 | |
1bd1bd80 DV |
9347 | intel_get_pipe_timings(crtc, pipe_config); |
9348 | ||
a1b2278e CK |
9349 | if (INTEL_INFO(dev)->gen >= 9) { |
9350 | skl_init_scalers(dev, crtc, pipe_config); | |
9351 | } | |
9352 | ||
2fa2fe9a | 9353 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f | 9354 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
ff6d9f55 | 9355 | if (INTEL_INFO(dev)->gen == 9) |
bd2e244f | 9356 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9357 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 9358 | ironlake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 JB |
9359 | else |
9360 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
9361 | ||
a1b2278e CK |
9362 | } else { |
9363 | pipe_config->scaler_state.scaler_id = -1; | |
9364 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f | 9365 | } |
88adfff1 | 9366 | |
e59150dc JB |
9367 | if (IS_HASWELL(dev)) |
9368 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9369 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9370 | |
ebb69c95 CT |
9371 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9372 | pipe_config->pixel_multiplier = | |
9373 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9374 | } else { | |
9375 | pipe_config->pixel_multiplier = 1; | |
9376 | } | |
6c49f241 | 9377 | |
0e8ffe1b DV |
9378 | return true; |
9379 | } | |
9380 | ||
560b85bb CW |
9381 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9382 | { | |
9383 | struct drm_device *dev = crtc->dev; | |
9384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9386 | uint32_t cntl = 0, size = 0; |
560b85bb | 9387 | |
dc41c154 | 9388 | if (base) { |
3dd512fb MR |
9389 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9390 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9391 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9392 | ||
9393 | switch (stride) { | |
9394 | default: | |
9395 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9396 | width, stride); | |
9397 | stride = 256; | |
9398 | /* fallthrough */ | |
9399 | case 256: | |
9400 | case 512: | |
9401 | case 1024: | |
9402 | case 2048: | |
9403 | break; | |
4b0e333e CW |
9404 | } |
9405 | ||
dc41c154 VS |
9406 | cntl |= CURSOR_ENABLE | |
9407 | CURSOR_GAMMA_ENABLE | | |
9408 | CURSOR_FORMAT_ARGB | | |
9409 | CURSOR_STRIDE(stride); | |
9410 | ||
9411 | size = (height << 12) | width; | |
4b0e333e | 9412 | } |
560b85bb | 9413 | |
dc41c154 VS |
9414 | if (intel_crtc->cursor_cntl != 0 && |
9415 | (intel_crtc->cursor_base != base || | |
9416 | intel_crtc->cursor_size != size || | |
9417 | intel_crtc->cursor_cntl != cntl)) { | |
9418 | /* On these chipsets we can only modify the base/size/stride | |
9419 | * whilst the cursor is disabled. | |
9420 | */ | |
9421 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 9422 | POSTING_READ(_CURACNTR); |
dc41c154 | 9423 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9424 | } |
560b85bb | 9425 | |
99d1f387 | 9426 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 9427 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
9428 | intel_crtc->cursor_base = base; |
9429 | } | |
4726e0b0 | 9430 | |
dc41c154 VS |
9431 | if (intel_crtc->cursor_size != size) { |
9432 | I915_WRITE(CURSIZE, size); | |
9433 | intel_crtc->cursor_size = size; | |
4b0e333e | 9434 | } |
560b85bb | 9435 | |
4b0e333e | 9436 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
9437 | I915_WRITE(_CURACNTR, cntl); |
9438 | POSTING_READ(_CURACNTR); | |
4b0e333e | 9439 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9440 | } |
560b85bb CW |
9441 | } |
9442 | ||
560b85bb | 9443 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9444 | { |
9445 | struct drm_device *dev = crtc->dev; | |
9446 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9447 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9448 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9449 | uint32_t cntl; |
9450 | ||
9451 | cntl = 0; | |
9452 | if (base) { | |
9453 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 9454 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
9455 | case 64: |
9456 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9457 | break; | |
9458 | case 128: | |
9459 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9460 | break; | |
9461 | case 256: | |
9462 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9463 | break; | |
9464 | default: | |
3dd512fb | 9465 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 9466 | return; |
65a21cd6 | 9467 | } |
4b0e333e | 9468 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
9469 | |
9470 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
9471 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 9472 | } |
65a21cd6 | 9473 | |
8e7d688b | 9474 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
9475 | cntl |= CURSOR_ROTATE_180; |
9476 | ||
4b0e333e CW |
9477 | if (intel_crtc->cursor_cntl != cntl) { |
9478 | I915_WRITE(CURCNTR(pipe), cntl); | |
9479 | POSTING_READ(CURCNTR(pipe)); | |
9480 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9481 | } |
4b0e333e | 9482 | |
65a21cd6 | 9483 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9484 | I915_WRITE(CURBASE(pipe), base); |
9485 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9486 | |
9487 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9488 | } |
9489 | ||
cda4b7d3 | 9490 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
9491 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
9492 | bool on) | |
cda4b7d3 CW |
9493 | { |
9494 | struct drm_device *dev = crtc->dev; | |
9495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9496 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9497 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
9498 | int x = crtc->cursor_x; |
9499 | int y = crtc->cursor_y; | |
d6e4db15 | 9500 | u32 base = 0, pos = 0; |
cda4b7d3 | 9501 | |
d6e4db15 | 9502 | if (on) |
cda4b7d3 | 9503 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 9504 | |
6e3c9717 | 9505 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
9506 | base = 0; |
9507 | ||
6e3c9717 | 9508 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
9509 | base = 0; |
9510 | ||
9511 | if (x < 0) { | |
3dd512fb | 9512 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
9513 | base = 0; |
9514 | ||
9515 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9516 | x = -x; | |
9517 | } | |
9518 | pos |= x << CURSOR_X_SHIFT; | |
9519 | ||
9520 | if (y < 0) { | |
3dd512fb | 9521 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
9522 | base = 0; |
9523 | ||
9524 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9525 | y = -y; | |
9526 | } | |
9527 | pos |= y << CURSOR_Y_SHIFT; | |
9528 | ||
4b0e333e | 9529 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
9530 | return; |
9531 | ||
5efb3e28 VS |
9532 | I915_WRITE(CURPOS(pipe), pos); |
9533 | ||
4398ad45 VS |
9534 | /* ILK+ do this automagically */ |
9535 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 9536 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
9537 | base += (intel_crtc->base.cursor->state->crtc_h * |
9538 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
9539 | } |
9540 | ||
8ac54669 | 9541 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
9542 | i845_update_cursor(crtc, base); |
9543 | else | |
9544 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
9545 | } |
9546 | ||
dc41c154 VS |
9547 | static bool cursor_size_ok(struct drm_device *dev, |
9548 | uint32_t width, uint32_t height) | |
9549 | { | |
9550 | if (width == 0 || height == 0) | |
9551 | return false; | |
9552 | ||
9553 | /* | |
9554 | * 845g/865g are special in that they are only limited by | |
9555 | * the width of their cursors, the height is arbitrary up to | |
9556 | * the precision of the register. Everything else requires | |
9557 | * square cursors, limited to a few power-of-two sizes. | |
9558 | */ | |
9559 | if (IS_845G(dev) || IS_I865G(dev)) { | |
9560 | if ((width & 63) != 0) | |
9561 | return false; | |
9562 | ||
9563 | if (width > (IS_845G(dev) ? 64 : 512)) | |
9564 | return false; | |
9565 | ||
9566 | if (height > 1023) | |
9567 | return false; | |
9568 | } else { | |
9569 | switch (width | height) { | |
9570 | case 256: | |
9571 | case 128: | |
9572 | if (IS_GEN2(dev)) | |
9573 | return false; | |
9574 | case 64: | |
9575 | break; | |
9576 | default: | |
9577 | return false; | |
9578 | } | |
9579 | } | |
9580 | ||
9581 | return true; | |
9582 | } | |
9583 | ||
79e53945 | 9584 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 9585 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 9586 | { |
7203425a | 9587 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 9588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 9589 | |
7203425a | 9590 | for (i = start; i < end; i++) { |
79e53945 JB |
9591 | intel_crtc->lut_r[i] = red[i] >> 8; |
9592 | intel_crtc->lut_g[i] = green[i] >> 8; | |
9593 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
9594 | } | |
9595 | ||
9596 | intel_crtc_load_lut(crtc); | |
9597 | } | |
9598 | ||
79e53945 JB |
9599 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9600 | static struct drm_display_mode load_detect_mode = { | |
9601 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9602 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9603 | }; | |
9604 | ||
a8bb6818 DV |
9605 | struct drm_framebuffer * |
9606 | __intel_framebuffer_create(struct drm_device *dev, | |
9607 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9608 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
9609 | { |
9610 | struct intel_framebuffer *intel_fb; | |
9611 | int ret; | |
9612 | ||
9613 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
9614 | if (!intel_fb) { | |
6ccb81f2 | 9615 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
9616 | return ERR_PTR(-ENOMEM); |
9617 | } | |
9618 | ||
9619 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
9620 | if (ret) |
9621 | goto err; | |
d2dff872 CW |
9622 | |
9623 | return &intel_fb->base; | |
dd4916c5 | 9624 | err: |
6ccb81f2 | 9625 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
9626 | kfree(intel_fb); |
9627 | ||
9628 | return ERR_PTR(ret); | |
d2dff872 CW |
9629 | } |
9630 | ||
b5ea642a | 9631 | static struct drm_framebuffer * |
a8bb6818 DV |
9632 | intel_framebuffer_create(struct drm_device *dev, |
9633 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9634 | struct drm_i915_gem_object *obj) | |
9635 | { | |
9636 | struct drm_framebuffer *fb; | |
9637 | int ret; | |
9638 | ||
9639 | ret = i915_mutex_lock_interruptible(dev); | |
9640 | if (ret) | |
9641 | return ERR_PTR(ret); | |
9642 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
9643 | mutex_unlock(&dev->struct_mutex); | |
9644 | ||
9645 | return fb; | |
9646 | } | |
9647 | ||
d2dff872 CW |
9648 | static u32 |
9649 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9650 | { | |
9651 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9652 | return ALIGN(pitch, 64); | |
9653 | } | |
9654 | ||
9655 | static u32 | |
9656 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9657 | { | |
9658 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9659 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9660 | } |
9661 | ||
9662 | static struct drm_framebuffer * | |
9663 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9664 | struct drm_display_mode *mode, | |
9665 | int depth, int bpp) | |
9666 | { | |
9667 | struct drm_i915_gem_object *obj; | |
0fed39bd | 9668 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
9669 | |
9670 | obj = i915_gem_alloc_object(dev, | |
9671 | intel_framebuffer_size_for_mode(mode, bpp)); | |
9672 | if (obj == NULL) | |
9673 | return ERR_PTR(-ENOMEM); | |
9674 | ||
9675 | mode_cmd.width = mode->hdisplay; | |
9676 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9677 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9678 | bpp); | |
5ca0c34a | 9679 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
9680 | |
9681 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
9682 | } | |
9683 | ||
9684 | static struct drm_framebuffer * | |
9685 | mode_fits_in_fbdev(struct drm_device *dev, | |
9686 | struct drm_display_mode *mode) | |
9687 | { | |
4520f53a | 9688 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
9689 | struct drm_i915_private *dev_priv = dev->dev_private; |
9690 | struct drm_i915_gem_object *obj; | |
9691 | struct drm_framebuffer *fb; | |
9692 | ||
4c0e5528 | 9693 | if (!dev_priv->fbdev) |
d2dff872 CW |
9694 | return NULL; |
9695 | ||
4c0e5528 | 9696 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9697 | return NULL; |
9698 | ||
4c0e5528 DV |
9699 | obj = dev_priv->fbdev->fb->obj; |
9700 | BUG_ON(!obj); | |
9701 | ||
8bcd4553 | 9702 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
9703 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
9704 | fb->bits_per_pixel)) | |
d2dff872 CW |
9705 | return NULL; |
9706 | ||
01f2c773 | 9707 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9708 | return NULL; |
9709 | ||
9710 | return fb; | |
4520f53a DV |
9711 | #else |
9712 | return NULL; | |
9713 | #endif | |
d2dff872 CW |
9714 | } |
9715 | ||
d3a40d1b ACO |
9716 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9717 | struct drm_crtc *crtc, | |
9718 | struct drm_display_mode *mode, | |
9719 | struct drm_framebuffer *fb, | |
9720 | int x, int y) | |
9721 | { | |
9722 | struct drm_plane_state *plane_state; | |
9723 | int hdisplay, vdisplay; | |
9724 | int ret; | |
9725 | ||
9726 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9727 | if (IS_ERR(plane_state)) | |
9728 | return PTR_ERR(plane_state); | |
9729 | ||
9730 | if (mode) | |
9731 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
9732 | else | |
9733 | hdisplay = vdisplay = 0; | |
9734 | ||
9735 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9736 | if (ret) | |
9737 | return ret; | |
9738 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9739 | plane_state->crtc_x = 0; | |
9740 | plane_state->crtc_y = 0; | |
9741 | plane_state->crtc_w = hdisplay; | |
9742 | plane_state->crtc_h = vdisplay; | |
9743 | plane_state->src_x = x << 16; | |
9744 | plane_state->src_y = y << 16; | |
9745 | plane_state->src_w = hdisplay << 16; | |
9746 | plane_state->src_h = vdisplay << 16; | |
9747 | ||
9748 | return 0; | |
9749 | } | |
9750 | ||
d2434ab7 | 9751 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9752 | struct drm_display_mode *mode, |
51fd371b RC |
9753 | struct intel_load_detect_pipe *old, |
9754 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9755 | { |
9756 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9757 | struct intel_encoder *intel_encoder = |
9758 | intel_attached_encoder(connector); | |
79e53945 | 9759 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9760 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9761 | struct drm_crtc *crtc = NULL; |
9762 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 9763 | struct drm_framebuffer *fb; |
51fd371b | 9764 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 9765 | struct drm_atomic_state *state = NULL; |
944b0c76 | 9766 | struct drm_connector_state *connector_state; |
4be07317 | 9767 | struct intel_crtc_state *crtc_state; |
51fd371b | 9768 | int ret, i = -1; |
79e53945 | 9769 | |
d2dff872 | 9770 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9771 | connector->base.id, connector->name, |
8e329a03 | 9772 | encoder->base.id, encoder->name); |
d2dff872 | 9773 | |
51fd371b RC |
9774 | retry: |
9775 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9776 | if (ret) | |
9777 | goto fail_unlock; | |
6e9f798d | 9778 | |
79e53945 JB |
9779 | /* |
9780 | * Algorithm gets a little messy: | |
7a5e4805 | 9781 | * |
79e53945 JB |
9782 | * - if the connector already has an assigned crtc, use it (but make |
9783 | * sure it's on first) | |
7a5e4805 | 9784 | * |
79e53945 JB |
9785 | * - try to find the first unused crtc that can drive this connector, |
9786 | * and use that if we find one | |
79e53945 JB |
9787 | */ |
9788 | ||
9789 | /* See if we already have a CRTC for this connector */ | |
9790 | if (encoder->crtc) { | |
9791 | crtc = encoder->crtc; | |
8261b191 | 9792 | |
51fd371b | 9793 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
9794 | if (ret) |
9795 | goto fail_unlock; | |
9796 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
9797 | if (ret) |
9798 | goto fail_unlock; | |
7b24056b | 9799 | |
24218aac | 9800 | old->dpms_mode = connector->dpms; |
8261b191 CW |
9801 | old->load_detect_temp = false; |
9802 | ||
9803 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
9804 | if (connector->dpms != DRM_MODE_DPMS_ON) |
9805 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 9806 | |
7173188d | 9807 | return true; |
79e53945 JB |
9808 | } |
9809 | ||
9810 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9811 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9812 | i++; |
9813 | if (!(encoder->possible_crtcs & (1 << i))) | |
9814 | continue; | |
83d65738 | 9815 | if (possible_crtc->state->enable) |
a459249c VS |
9816 | continue; |
9817 | /* This can occur when applying the pipe A quirk on resume. */ | |
9818 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
9819 | continue; | |
9820 | ||
9821 | crtc = possible_crtc; | |
9822 | break; | |
79e53945 JB |
9823 | } |
9824 | ||
9825 | /* | |
9826 | * If we didn't find an unused CRTC, don't use any. | |
9827 | */ | |
9828 | if (!crtc) { | |
7173188d | 9829 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 9830 | goto fail_unlock; |
79e53945 JB |
9831 | } |
9832 | ||
51fd371b RC |
9833 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
9834 | if (ret) | |
4d02e2de DV |
9835 | goto fail_unlock; |
9836 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
9837 | if (ret) | |
51fd371b | 9838 | goto fail_unlock; |
fc303101 DV |
9839 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
9840 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
9841 | |
9842 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 9843 | intel_crtc->new_enabled = true; |
24218aac | 9844 | old->dpms_mode = connector->dpms; |
8261b191 | 9845 | old->load_detect_temp = true; |
d2dff872 | 9846 | old->release_fb = NULL; |
79e53945 | 9847 | |
83a57153 ACO |
9848 | state = drm_atomic_state_alloc(dev); |
9849 | if (!state) | |
9850 | return false; | |
9851 | ||
9852 | state->acquire_ctx = ctx; | |
9853 | ||
944b0c76 ACO |
9854 | connector_state = drm_atomic_get_connector_state(state, connector); |
9855 | if (IS_ERR(connector_state)) { | |
9856 | ret = PTR_ERR(connector_state); | |
9857 | goto fail; | |
9858 | } | |
9859 | ||
9860 | connector_state->crtc = crtc; | |
9861 | connector_state->best_encoder = &intel_encoder->base; | |
9862 | ||
4be07317 ACO |
9863 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9864 | if (IS_ERR(crtc_state)) { | |
9865 | ret = PTR_ERR(crtc_state); | |
9866 | goto fail; | |
9867 | } | |
9868 | ||
9869 | crtc_state->base.enable = true; | |
9870 | ||
6492711d CW |
9871 | if (!mode) |
9872 | mode = &load_detect_mode; | |
79e53945 | 9873 | |
d2dff872 CW |
9874 | /* We need a framebuffer large enough to accommodate all accesses |
9875 | * that the plane may generate whilst we perform load detection. | |
9876 | * We can not rely on the fbcon either being present (we get called | |
9877 | * during its initialisation to detect all boot displays, or it may | |
9878 | * not even exist) or that it is large enough to satisfy the | |
9879 | * requested mode. | |
9880 | */ | |
94352cf9 DV |
9881 | fb = mode_fits_in_fbdev(dev, mode); |
9882 | if (fb == NULL) { | |
d2dff872 | 9883 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
9884 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
9885 | old->release_fb = fb; | |
d2dff872 CW |
9886 | } else |
9887 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9888 | if (IS_ERR(fb)) { |
d2dff872 | 9889 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9890 | goto fail; |
79e53945 | 9891 | } |
79e53945 | 9892 | |
d3a40d1b ACO |
9893 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
9894 | if (ret) | |
9895 | goto fail; | |
9896 | ||
8c7b5ccb ACO |
9897 | drm_mode_copy(&crtc_state->base.mode, mode); |
9898 | ||
9899 | if (intel_set_mode(crtc, state)) { | |
6492711d | 9900 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
9901 | if (old->release_fb) |
9902 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 9903 | goto fail; |
79e53945 | 9904 | } |
9128b040 | 9905 | crtc->primary->crtc = crtc; |
7173188d | 9906 | |
79e53945 | 9907 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 9908 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 9909 | return true; |
412b61d8 VS |
9910 | |
9911 | fail: | |
83d65738 | 9912 | intel_crtc->new_enabled = crtc->state->enable; |
51fd371b | 9913 | fail_unlock: |
e5d958ef ACO |
9914 | drm_atomic_state_free(state); |
9915 | state = NULL; | |
83a57153 | 9916 | |
51fd371b RC |
9917 | if (ret == -EDEADLK) { |
9918 | drm_modeset_backoff(ctx); | |
9919 | goto retry; | |
9920 | } | |
9921 | ||
412b61d8 | 9922 | return false; |
79e53945 JB |
9923 | } |
9924 | ||
d2434ab7 | 9925 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9926 | struct intel_load_detect_pipe *old, |
9927 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9928 | { |
83a57153 | 9929 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
9930 | struct intel_encoder *intel_encoder = |
9931 | intel_attached_encoder(connector); | |
4ef69c7a | 9932 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 9933 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 9934 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 9935 | struct drm_atomic_state *state; |
944b0c76 | 9936 | struct drm_connector_state *connector_state; |
4be07317 | 9937 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 9938 | int ret; |
79e53945 | 9939 | |
d2dff872 | 9940 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9941 | connector->base.id, connector->name, |
8e329a03 | 9942 | encoder->base.id, encoder->name); |
d2dff872 | 9943 | |
8261b191 | 9944 | if (old->load_detect_temp) { |
83a57153 | 9945 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
9946 | if (!state) |
9947 | goto fail; | |
83a57153 ACO |
9948 | |
9949 | state->acquire_ctx = ctx; | |
9950 | ||
944b0c76 ACO |
9951 | connector_state = drm_atomic_get_connector_state(state, connector); |
9952 | if (IS_ERR(connector_state)) | |
9953 | goto fail; | |
9954 | ||
4be07317 ACO |
9955 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9956 | if (IS_ERR(crtc_state)) | |
9957 | goto fail; | |
9958 | ||
fc303101 DV |
9959 | to_intel_connector(connector)->new_encoder = NULL; |
9960 | intel_encoder->new_crtc = NULL; | |
412b61d8 | 9961 | intel_crtc->new_enabled = false; |
944b0c76 ACO |
9962 | |
9963 | connector_state->best_encoder = NULL; | |
9964 | connector_state->crtc = NULL; | |
9965 | ||
4be07317 ACO |
9966 | crtc_state->base.enable = false; |
9967 | ||
d3a40d1b ACO |
9968 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
9969 | 0, 0); | |
9970 | if (ret) | |
9971 | goto fail; | |
9972 | ||
2bfb4627 ACO |
9973 | ret = intel_set_mode(crtc, state); |
9974 | if (ret) | |
9975 | goto fail; | |
d2dff872 | 9976 | |
36206361 DV |
9977 | if (old->release_fb) { |
9978 | drm_framebuffer_unregister_private(old->release_fb); | |
9979 | drm_framebuffer_unreference(old->release_fb); | |
9980 | } | |
d2dff872 | 9981 | |
0622a53c | 9982 | return; |
79e53945 JB |
9983 | } |
9984 | ||
c751ce4f | 9985 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
9986 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
9987 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
9988 | |
9989 | return; | |
9990 | fail: | |
9991 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
9992 | drm_atomic_state_free(state); | |
79e53945 JB |
9993 | } |
9994 | ||
da4a1efa | 9995 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9996 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
9997 | { |
9998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9999 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10000 | ||
10001 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10002 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10003 | else if (HAS_PCH_SPLIT(dev)) |
10004 | return 120000; | |
10005 | else if (!IS_GEN2(dev)) | |
10006 | return 96000; | |
10007 | else | |
10008 | return 48000; | |
10009 | } | |
10010 | ||
79e53945 | 10011 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10012 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10013 | struct intel_crtc_state *pipe_config) |
79e53945 | 10014 | { |
f1f644dc | 10015 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10016 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10017 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10018 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10019 | u32 fp; |
10020 | intel_clock_t clock; | |
da4a1efa | 10021 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10022 | |
10023 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10024 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10025 | else |
293623f7 | 10026 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10027 | |
10028 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10029 | if (IS_PINEVIEW(dev)) { |
10030 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10031 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10032 | } else { |
10033 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10034 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10035 | } | |
10036 | ||
a6c45cf0 | 10037 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10038 | if (IS_PINEVIEW(dev)) |
10039 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10040 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10041 | else |
10042 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10043 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10044 | ||
10045 | switch (dpll & DPLL_MODE_MASK) { | |
10046 | case DPLLB_MODE_DAC_SERIAL: | |
10047 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10048 | 5 : 10; | |
10049 | break; | |
10050 | case DPLLB_MODE_LVDS: | |
10051 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10052 | 7 : 14; | |
10053 | break; | |
10054 | default: | |
28c97730 | 10055 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10056 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10057 | return; |
79e53945 JB |
10058 | } |
10059 | ||
ac58c3f0 | 10060 | if (IS_PINEVIEW(dev)) |
da4a1efa | 10061 | pineview_clock(refclk, &clock); |
ac58c3f0 | 10062 | else |
da4a1efa | 10063 | i9xx_clock(refclk, &clock); |
79e53945 | 10064 | } else { |
0fb58223 | 10065 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10066 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10067 | |
10068 | if (is_lvds) { | |
10069 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10070 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10071 | |
10072 | if (lvds & LVDS_CLKB_POWER_UP) | |
10073 | clock.p2 = 7; | |
10074 | else | |
10075 | clock.p2 = 14; | |
79e53945 JB |
10076 | } else { |
10077 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10078 | clock.p1 = 2; | |
10079 | else { | |
10080 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10081 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10082 | } | |
10083 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10084 | clock.p2 = 4; | |
10085 | else | |
10086 | clock.p2 = 2; | |
79e53945 | 10087 | } |
da4a1efa VS |
10088 | |
10089 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
10090 | } |
10091 | ||
18442d08 VS |
10092 | /* |
10093 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10094 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10095 | * encoder's get_config() function. |
10096 | */ | |
10097 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
10098 | } |
10099 | ||
6878da05 VS |
10100 | int intel_dotclock_calculate(int link_freq, |
10101 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10102 | { |
f1f644dc JB |
10103 | /* |
10104 | * The calculation for the data clock is: | |
1041a02f | 10105 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10106 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10107 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10108 | * |
10109 | * and the link clock is simpler: | |
1041a02f | 10110 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10111 | */ |
10112 | ||
6878da05 VS |
10113 | if (!m_n->link_n) |
10114 | return 0; | |
f1f644dc | 10115 | |
6878da05 VS |
10116 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10117 | } | |
f1f644dc | 10118 | |
18442d08 | 10119 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10120 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10121 | { |
10122 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10123 | |
18442d08 VS |
10124 | /* read out port_clock from the DPLL */ |
10125 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10126 | |
f1f644dc | 10127 | /* |
18442d08 | 10128 | * This value does not include pixel_multiplier. |
241bfc38 | 10129 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10130 | * agree once we know their relationship in the encoder's |
10131 | * get_config() function. | |
79e53945 | 10132 | */ |
2d112de7 | 10133 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10134 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10135 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10136 | } |
10137 | ||
10138 | /** Returns the currently programmed mode of the given pipe. */ | |
10139 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10140 | struct drm_crtc *crtc) | |
10141 | { | |
548f245b | 10142 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10143 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10144 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10145 | struct drm_display_mode *mode; |
5cec258b | 10146 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10147 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10148 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10149 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10150 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10151 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10152 | |
10153 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10154 | if (!mode) | |
10155 | return NULL; | |
10156 | ||
f1f644dc JB |
10157 | /* |
10158 | * Construct a pipe_config sufficient for getting the clock info | |
10159 | * back out of crtc_clock_get. | |
10160 | * | |
10161 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10162 | * to use a real value here instead. | |
10163 | */ | |
293623f7 | 10164 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10165 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10166 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10167 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10168 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10169 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10170 | ||
773ae034 | 10171 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10172 | mode->hdisplay = (htot & 0xffff) + 1; |
10173 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10174 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10175 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10176 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10177 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10178 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10179 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10180 | ||
10181 | drm_mode_set_name(mode); | |
79e53945 JB |
10182 | |
10183 | return mode; | |
10184 | } | |
10185 | ||
652c393a JB |
10186 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
10187 | { | |
10188 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10189 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10190 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 10191 | |
baff296c | 10192 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
10193 | return; |
10194 | ||
10195 | if (!dev_priv->lvds_downclock_avail) | |
10196 | return; | |
10197 | ||
10198 | /* | |
10199 | * Since this is called by a timer, we should never get here in | |
10200 | * the manual case. | |
10201 | */ | |
10202 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
10203 | int pipe = intel_crtc->pipe; |
10204 | int dpll_reg = DPLL(pipe); | |
10205 | int dpll; | |
f6e5b160 | 10206 | |
44d98a61 | 10207 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 10208 | |
8ac5a6d5 | 10209 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 10210 | |
dc257cf1 | 10211 | dpll = I915_READ(dpll_reg); |
652c393a JB |
10212 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
10213 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 10214 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
10215 | dpll = I915_READ(dpll_reg); |
10216 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 10217 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
10218 | } |
10219 | ||
10220 | } | |
10221 | ||
f047e395 CW |
10222 | void intel_mark_busy(struct drm_device *dev) |
10223 | { | |
c67a470b PZ |
10224 | struct drm_i915_private *dev_priv = dev->dev_private; |
10225 | ||
f62a0076 CW |
10226 | if (dev_priv->mm.busy) |
10227 | return; | |
10228 | ||
43694d69 | 10229 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10230 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10231 | if (INTEL_INFO(dev)->gen >= 6) |
10232 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10233 | dev_priv->mm.busy = true; |
f047e395 CW |
10234 | } |
10235 | ||
10236 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10237 | { |
c67a470b | 10238 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10239 | struct drm_crtc *crtc; |
652c393a | 10240 | |
f62a0076 CW |
10241 | if (!dev_priv->mm.busy) |
10242 | return; | |
10243 | ||
10244 | dev_priv->mm.busy = false; | |
10245 | ||
70e1e0ec | 10246 | for_each_crtc(dev, crtc) { |
f4510a27 | 10247 | if (!crtc->primary->fb) |
652c393a JB |
10248 | continue; |
10249 | ||
725a5b54 | 10250 | intel_decrease_pllclock(crtc); |
652c393a | 10251 | } |
b29c19b6 | 10252 | |
3d13ef2e | 10253 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10254 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10255 | |
43694d69 | 10256 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10257 | } |
10258 | ||
f5de6e07 ACO |
10259 | static void intel_crtc_set_state(struct intel_crtc *crtc, |
10260 | struct intel_crtc_state *crtc_state) | |
10261 | { | |
10262 | kfree(crtc->config); | |
10263 | crtc->config = crtc_state; | |
16f3f658 | 10264 | crtc->base.state = &crtc_state->base; |
f5de6e07 ACO |
10265 | } |
10266 | ||
79e53945 JB |
10267 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10268 | { | |
10269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10270 | struct drm_device *dev = crtc->dev; |
10271 | struct intel_unpin_work *work; | |
67e77c5a | 10272 | |
5e2d7afc | 10273 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10274 | work = intel_crtc->unpin_work; |
10275 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10276 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10277 | |
10278 | if (work) { | |
10279 | cancel_work_sync(&work->work); | |
10280 | kfree(work); | |
10281 | } | |
79e53945 | 10282 | |
f5de6e07 | 10283 | intel_crtc_set_state(intel_crtc, NULL); |
79e53945 | 10284 | drm_crtc_cleanup(crtc); |
67e77c5a | 10285 | |
79e53945 JB |
10286 | kfree(intel_crtc); |
10287 | } | |
10288 | ||
6b95a207 KH |
10289 | static void intel_unpin_work_fn(struct work_struct *__work) |
10290 | { | |
10291 | struct intel_unpin_work *work = | |
10292 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 10293 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 10294 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 10295 | |
b4a98e57 | 10296 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 10297 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 10298 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10299 | |
7ff0ebcc | 10300 | intel_fbc_update(dev); |
f06cc1b9 JH |
10301 | |
10302 | if (work->flip_queued_req) | |
146d84f0 | 10303 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10304 | mutex_unlock(&dev->struct_mutex); |
10305 | ||
f99d7069 | 10306 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 10307 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10308 | |
b4a98e57 CW |
10309 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
10310 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
10311 | ||
6b95a207 KH |
10312 | kfree(work); |
10313 | } | |
10314 | ||
1afe3e9d | 10315 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10316 | struct drm_crtc *crtc) |
6b95a207 | 10317 | { |
6b95a207 KH |
10318 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10319 | struct intel_unpin_work *work; | |
6b95a207 KH |
10320 | unsigned long flags; |
10321 | ||
10322 | /* Ignore early vblank irqs */ | |
10323 | if (intel_crtc == NULL) | |
10324 | return; | |
10325 | ||
f326038a DV |
10326 | /* |
10327 | * This is called both by irq handlers and the reset code (to complete | |
10328 | * lost pageflips) so needs the full irqsave spinlocks. | |
10329 | */ | |
6b95a207 KH |
10330 | spin_lock_irqsave(&dev->event_lock, flags); |
10331 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10332 | |
10333 | /* Ensure we don't miss a work->pending update ... */ | |
10334 | smp_rmb(); | |
10335 | ||
10336 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10337 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10338 | return; | |
10339 | } | |
10340 | ||
d6bbafa1 | 10341 | page_flip_completed(intel_crtc); |
0af7e4df | 10342 | |
6b95a207 | 10343 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10344 | } |
10345 | ||
1afe3e9d JB |
10346 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10347 | { | |
fbee40df | 10348 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10349 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10350 | ||
49b14a5c | 10351 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10352 | } |
10353 | ||
10354 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10355 | { | |
fbee40df | 10356 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10357 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10358 | ||
49b14a5c | 10359 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10360 | } |
10361 | ||
75f7f3ec VS |
10362 | /* Is 'a' after or equal to 'b'? */ |
10363 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10364 | { | |
10365 | return !((a - b) & 0x80000000); | |
10366 | } | |
10367 | ||
10368 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10369 | { | |
10370 | struct drm_device *dev = crtc->base.dev; | |
10371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10372 | ||
bdfa7542 VS |
10373 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10374 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10375 | return true; | |
10376 | ||
75f7f3ec VS |
10377 | /* |
10378 | * The relevant registers doen't exist on pre-ctg. | |
10379 | * As the flip done interrupt doesn't trigger for mmio | |
10380 | * flips on gmch platforms, a flip count check isn't | |
10381 | * really needed there. But since ctg has the registers, | |
10382 | * include it in the check anyway. | |
10383 | */ | |
10384 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10385 | return true; | |
10386 | ||
10387 | /* | |
10388 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10389 | * used the same base address. In that case the mmio flip might | |
10390 | * have completed, but the CS hasn't even executed the flip yet. | |
10391 | * | |
10392 | * A flip count check isn't enough as the CS might have updated | |
10393 | * the base address just after start of vblank, but before we | |
10394 | * managed to process the interrupt. This means we'd complete the | |
10395 | * CS flip too soon. | |
10396 | * | |
10397 | * Combining both checks should get us a good enough result. It may | |
10398 | * still happen that the CS flip has been executed, but has not | |
10399 | * yet actually completed. But in case the base address is the same | |
10400 | * anyway, we don't really care. | |
10401 | */ | |
10402 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10403 | crtc->unpin_work->gtt_offset && | |
10404 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10405 | crtc->unpin_work->flip_count); | |
10406 | } | |
10407 | ||
6b95a207 KH |
10408 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10409 | { | |
fbee40df | 10410 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10411 | struct intel_crtc *intel_crtc = |
10412 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10413 | unsigned long flags; | |
10414 | ||
f326038a DV |
10415 | |
10416 | /* | |
10417 | * This is called both by irq handlers and the reset code (to complete | |
10418 | * lost pageflips) so needs the full irqsave spinlocks. | |
10419 | * | |
10420 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10421 | * generate a page-flip completion irq, i.e. every modeset |
10422 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10423 | */ | |
6b95a207 | 10424 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10425 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10426 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10427 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10428 | } | |
10429 | ||
eba905b2 | 10430 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10431 | { |
10432 | /* Ensure that the work item is consistent when activating it ... */ | |
10433 | smp_wmb(); | |
10434 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10435 | /* and that it is marked active as soon as the irq could fire. */ | |
10436 | smp_wmb(); | |
10437 | } | |
10438 | ||
8c9f3aaf JB |
10439 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10440 | struct drm_crtc *crtc, | |
10441 | struct drm_framebuffer *fb, | |
ed8d1975 | 10442 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10443 | struct intel_engine_cs *ring, |
ed8d1975 | 10444 | uint32_t flags) |
8c9f3aaf | 10445 | { |
8c9f3aaf | 10446 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10447 | u32 flip_mask; |
10448 | int ret; | |
10449 | ||
6d90c952 | 10450 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10451 | if (ret) |
4fa62c89 | 10452 | return ret; |
8c9f3aaf JB |
10453 | |
10454 | /* Can't queue multiple flips, so wait for the previous | |
10455 | * one to finish before executing the next. | |
10456 | */ | |
10457 | if (intel_crtc->plane) | |
10458 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10459 | else | |
10460 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10461 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10462 | intel_ring_emit(ring, MI_NOOP); | |
10463 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10464 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10465 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10466 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10467 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
10468 | |
10469 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10470 | __intel_ring_advance(ring); |
83d4092b | 10471 | return 0; |
8c9f3aaf JB |
10472 | } |
10473 | ||
10474 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10475 | struct drm_crtc *crtc, | |
10476 | struct drm_framebuffer *fb, | |
ed8d1975 | 10477 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10478 | struct intel_engine_cs *ring, |
ed8d1975 | 10479 | uint32_t flags) |
8c9f3aaf | 10480 | { |
8c9f3aaf | 10481 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10482 | u32 flip_mask; |
10483 | int ret; | |
10484 | ||
6d90c952 | 10485 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10486 | if (ret) |
4fa62c89 | 10487 | return ret; |
8c9f3aaf JB |
10488 | |
10489 | if (intel_crtc->plane) | |
10490 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10491 | else | |
10492 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10493 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10494 | intel_ring_emit(ring, MI_NOOP); | |
10495 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10496 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10497 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10498 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10499 | intel_ring_emit(ring, MI_NOOP); |
10500 | ||
e7d841ca | 10501 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 10502 | __intel_ring_advance(ring); |
83d4092b | 10503 | return 0; |
8c9f3aaf JB |
10504 | } |
10505 | ||
10506 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10507 | struct drm_crtc *crtc, | |
10508 | struct drm_framebuffer *fb, | |
ed8d1975 | 10509 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10510 | struct intel_engine_cs *ring, |
ed8d1975 | 10511 | uint32_t flags) |
8c9f3aaf JB |
10512 | { |
10513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10514 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10515 | uint32_t pf, pipesrc; | |
10516 | int ret; | |
10517 | ||
6d90c952 | 10518 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10519 | if (ret) |
4fa62c89 | 10520 | return ret; |
8c9f3aaf JB |
10521 | |
10522 | /* i965+ uses the linear or tiled offsets from the | |
10523 | * Display Registers (which do not change across a page-flip) | |
10524 | * so we need only reprogram the base address. | |
10525 | */ | |
6d90c952 DV |
10526 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10527 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10528 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10529 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 10530 | obj->tiling_mode); |
8c9f3aaf JB |
10531 | |
10532 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10533 | * untested on non-native modes, so ignore it for now. | |
10534 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10535 | */ | |
10536 | pf = 0; | |
10537 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 10538 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10539 | |
10540 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10541 | __intel_ring_advance(ring); |
83d4092b | 10542 | return 0; |
8c9f3aaf JB |
10543 | } |
10544 | ||
10545 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10546 | struct drm_crtc *crtc, | |
10547 | struct drm_framebuffer *fb, | |
ed8d1975 | 10548 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10549 | struct intel_engine_cs *ring, |
ed8d1975 | 10550 | uint32_t flags) |
8c9f3aaf JB |
10551 | { |
10552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10553 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10554 | uint32_t pf, pipesrc; | |
10555 | int ret; | |
10556 | ||
6d90c952 | 10557 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10558 | if (ret) |
4fa62c89 | 10559 | return ret; |
8c9f3aaf | 10560 | |
6d90c952 DV |
10561 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10562 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10563 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 10564 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 10565 | |
dc257cf1 DV |
10566 | /* Contrary to the suggestions in the documentation, |
10567 | * "Enable Panel Fitter" does not seem to be required when page | |
10568 | * flipping with a non-native mode, and worse causes a normal | |
10569 | * modeset to fail. | |
10570 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10571 | */ | |
10572 | pf = 0; | |
8c9f3aaf | 10573 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 10574 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10575 | |
10576 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10577 | __intel_ring_advance(ring); |
83d4092b | 10578 | return 0; |
8c9f3aaf JB |
10579 | } |
10580 | ||
7c9017e5 JB |
10581 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10582 | struct drm_crtc *crtc, | |
10583 | struct drm_framebuffer *fb, | |
ed8d1975 | 10584 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10585 | struct intel_engine_cs *ring, |
ed8d1975 | 10586 | uint32_t flags) |
7c9017e5 | 10587 | { |
7c9017e5 | 10588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 10589 | uint32_t plane_bit = 0; |
ffe74d75 CW |
10590 | int len, ret; |
10591 | ||
eba905b2 | 10592 | switch (intel_crtc->plane) { |
cb05d8de DV |
10593 | case PLANE_A: |
10594 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10595 | break; | |
10596 | case PLANE_B: | |
10597 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10598 | break; | |
10599 | case PLANE_C: | |
10600 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10601 | break; | |
10602 | default: | |
10603 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 10604 | return -ENODEV; |
cb05d8de DV |
10605 | } |
10606 | ||
ffe74d75 | 10607 | len = 4; |
f476828a | 10608 | if (ring->id == RCS) { |
ffe74d75 | 10609 | len += 6; |
f476828a DL |
10610 | /* |
10611 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10612 | * 48bits addresses, and we need a NOOP for the batch size to | |
10613 | * stay even. | |
10614 | */ | |
10615 | if (IS_GEN8(dev)) | |
10616 | len += 2; | |
10617 | } | |
ffe74d75 | 10618 | |
f66fab8e VS |
10619 | /* |
10620 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10621 | * "The full packet must be contained within the same cache line." | |
10622 | * | |
10623 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10624 | * cacheline, if we ever start emitting more commands before | |
10625 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10626 | * then do the cacheline alignment, and finally emit the | |
10627 | * MI_DISPLAY_FLIP. | |
10628 | */ | |
10629 | ret = intel_ring_cacheline_align(ring); | |
10630 | if (ret) | |
4fa62c89 | 10631 | return ret; |
f66fab8e | 10632 | |
ffe74d75 | 10633 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 10634 | if (ret) |
4fa62c89 | 10635 | return ret; |
7c9017e5 | 10636 | |
ffe74d75 CW |
10637 | /* Unmask the flip-done completion message. Note that the bspec says that |
10638 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10639 | * more than one flip event at any time (or ensure that one flip message | |
10640 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10641 | * Experimentation says that BCS works despite DERRMR masking all | |
10642 | * flip-done completion events and that unmasking all planes at once | |
10643 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10644 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10645 | */ | |
10646 | if (ring->id == RCS) { | |
10647 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
10648 | intel_ring_emit(ring, DERRMR); | |
10649 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10650 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10651 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
10652 | if (IS_GEN8(dev)) |
10653 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
10654 | MI_SRM_LRM_GLOBAL_GTT); | |
10655 | else | |
10656 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
10657 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
10658 | intel_ring_emit(ring, DERRMR); |
10659 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
10660 | if (IS_GEN8(dev)) { |
10661 | intel_ring_emit(ring, 0); | |
10662 | intel_ring_emit(ring, MI_NOOP); | |
10663 | } | |
ffe74d75 CW |
10664 | } |
10665 | ||
cb05d8de | 10666 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 10667 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 10668 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 10669 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
10670 | |
10671 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10672 | __intel_ring_advance(ring); |
83d4092b | 10673 | return 0; |
7c9017e5 JB |
10674 | } |
10675 | ||
84c33a64 SG |
10676 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
10677 | struct drm_i915_gem_object *obj) | |
10678 | { | |
10679 | /* | |
10680 | * This is not being used for older platforms, because | |
10681 | * non-availability of flip done interrupt forces us to use | |
10682 | * CS flips. Older platforms derive flip done using some clever | |
10683 | * tricks involving the flip_pending status bits and vblank irqs. | |
10684 | * So using MMIO flips there would disrupt this mechanism. | |
10685 | */ | |
10686 | ||
8e09bf83 CW |
10687 | if (ring == NULL) |
10688 | return true; | |
10689 | ||
84c33a64 SG |
10690 | if (INTEL_INFO(ring->dev)->gen < 5) |
10691 | return false; | |
10692 | ||
10693 | if (i915.use_mmio_flip < 0) | |
10694 | return false; | |
10695 | else if (i915.use_mmio_flip > 0) | |
10696 | return true; | |
14bf993e OM |
10697 | else if (i915.enable_execlists) |
10698 | return true; | |
84c33a64 | 10699 | else |
41c52415 | 10700 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
10701 | } |
10702 | ||
ff944564 DL |
10703 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
10704 | { | |
10705 | struct drm_device *dev = intel_crtc->base.dev; | |
10706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10707 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 DL |
10708 | const enum pipe pipe = intel_crtc->pipe; |
10709 | u32 ctl, stride; | |
10710 | ||
10711 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10712 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
10713 | switch (fb->modifier[0]) { |
10714 | case DRM_FORMAT_MOD_NONE: | |
10715 | break; | |
10716 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 10717 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
10718 | break; |
10719 | case I915_FORMAT_MOD_Y_TILED: | |
10720 | ctl |= PLANE_CTL_TILED_Y; | |
10721 | break; | |
10722 | case I915_FORMAT_MOD_Yf_TILED: | |
10723 | ctl |= PLANE_CTL_TILED_YF; | |
10724 | break; | |
10725 | default: | |
10726 | MISSING_CASE(fb->modifier[0]); | |
10727 | } | |
ff944564 DL |
10728 | |
10729 | /* | |
10730 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
10731 | * linear buffers or in number of tiles for tiled buffers. | |
10732 | */ | |
2ebef630 TU |
10733 | stride = fb->pitches[0] / |
10734 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
10735 | fb->pixel_format); | |
ff944564 DL |
10736 | |
10737 | /* | |
10738 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10739 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10740 | */ | |
10741 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10742 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10743 | ||
10744 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
10745 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10746 | } | |
10747 | ||
10748 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
10749 | { |
10750 | struct drm_device *dev = intel_crtc->base.dev; | |
10751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10752 | struct intel_framebuffer *intel_fb = | |
10753 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
10754 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10755 | u32 dspcntr; | |
10756 | u32 reg; | |
10757 | ||
84c33a64 SG |
10758 | reg = DSPCNTR(intel_crtc->plane); |
10759 | dspcntr = I915_READ(reg); | |
10760 | ||
c5d97472 DL |
10761 | if (obj->tiling_mode != I915_TILING_NONE) |
10762 | dspcntr |= DISPPLANE_TILED; | |
10763 | else | |
10764 | dspcntr &= ~DISPPLANE_TILED; | |
10765 | ||
84c33a64 SG |
10766 | I915_WRITE(reg, dspcntr); |
10767 | ||
10768 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
10769 | intel_crtc->unpin_work->gtt_offset); | |
10770 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 10771 | |
ff944564 DL |
10772 | } |
10773 | ||
10774 | /* | |
10775 | * XXX: This is the temporary way to update the plane registers until we get | |
10776 | * around to using the usual plane update functions for MMIO flips | |
10777 | */ | |
10778 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
10779 | { | |
10780 | struct drm_device *dev = intel_crtc->base.dev; | |
10781 | bool atomic_update; | |
10782 | u32 start_vbl_count; | |
10783 | ||
10784 | intel_mark_page_flip_active(intel_crtc); | |
10785 | ||
10786 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
10787 | ||
10788 | if (INTEL_INFO(dev)->gen >= 9) | |
10789 | skl_do_mmio_flip(intel_crtc); | |
10790 | else | |
10791 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10792 | ilk_do_mmio_flip(intel_crtc); | |
10793 | ||
9362c7c5 ACO |
10794 | if (atomic_update) |
10795 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
10796 | } |
10797 | ||
9362c7c5 | 10798 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 10799 | { |
cc8c4cc2 | 10800 | struct intel_crtc *crtc = |
9362c7c5 | 10801 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 10802 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 10803 | |
cc8c4cc2 JH |
10804 | mmio_flip = &crtc->mmio_flip; |
10805 | if (mmio_flip->req) | |
9c654818 JH |
10806 | WARN_ON(__i915_wait_request(mmio_flip->req, |
10807 | crtc->reset_counter, | |
10808 | false, NULL, NULL) != 0); | |
84c33a64 | 10809 | |
cc8c4cc2 JH |
10810 | intel_do_mmio_flip(crtc); |
10811 | if (mmio_flip->req) { | |
10812 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 10813 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
10814 | mutex_unlock(&crtc->base.dev->struct_mutex); |
10815 | } | |
84c33a64 SG |
10816 | } |
10817 | ||
10818 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
10819 | struct drm_crtc *crtc, | |
10820 | struct drm_framebuffer *fb, | |
10821 | struct drm_i915_gem_object *obj, | |
10822 | struct intel_engine_cs *ring, | |
10823 | uint32_t flags) | |
10824 | { | |
84c33a64 | 10825 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 10826 | |
cc8c4cc2 JH |
10827 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
10828 | obj->last_write_req); | |
536f5b5e ACO |
10829 | |
10830 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 10831 | |
84c33a64 SG |
10832 | return 0; |
10833 | } | |
10834 | ||
8c9f3aaf JB |
10835 | static int intel_default_queue_flip(struct drm_device *dev, |
10836 | struct drm_crtc *crtc, | |
10837 | struct drm_framebuffer *fb, | |
ed8d1975 | 10838 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10839 | struct intel_engine_cs *ring, |
ed8d1975 | 10840 | uint32_t flags) |
8c9f3aaf JB |
10841 | { |
10842 | return -ENODEV; | |
10843 | } | |
10844 | ||
d6bbafa1 CW |
10845 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
10846 | struct drm_crtc *crtc) | |
10847 | { | |
10848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10849 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10850 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
10851 | u32 addr; | |
10852 | ||
10853 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
10854 | return true; | |
10855 | ||
10856 | if (!work->enable_stall_check) | |
10857 | return false; | |
10858 | ||
10859 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
10860 | if (work->flip_queued_req && |
10861 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
10862 | return false; |
10863 | ||
1e3feefd | 10864 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
10865 | } |
10866 | ||
1e3feefd | 10867 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
10868 | return false; |
10869 | ||
10870 | /* Potential stall - if we see that the flip has happened, | |
10871 | * assume a missed interrupt. */ | |
10872 | if (INTEL_INFO(dev)->gen >= 4) | |
10873 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10874 | else | |
10875 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10876 | ||
10877 | /* There is a potential issue here with a false positive after a flip | |
10878 | * to the same address. We could address this by checking for a | |
10879 | * non-incrementing frame counter. | |
10880 | */ | |
10881 | return addr == work->gtt_offset; | |
10882 | } | |
10883 | ||
10884 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
10885 | { | |
10886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10887 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
10888 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 10889 | struct intel_unpin_work *work; |
f326038a | 10890 | |
6c51d46f | 10891 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
10892 | |
10893 | if (crtc == NULL) | |
10894 | return; | |
10895 | ||
f326038a | 10896 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
10897 | work = intel_crtc->unpin_work; |
10898 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 10899 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 10900 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 10901 | page_flip_completed(intel_crtc); |
6ad790c0 | 10902 | work = NULL; |
d6bbafa1 | 10903 | } |
6ad790c0 CW |
10904 | if (work != NULL && |
10905 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
10906 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 10907 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
10908 | } |
10909 | ||
6b95a207 KH |
10910 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10911 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
10912 | struct drm_pending_vblank_event *event, |
10913 | uint32_t page_flip_flags) | |
6b95a207 KH |
10914 | { |
10915 | struct drm_device *dev = crtc->dev; | |
10916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 10917 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 10918 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 10919 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 10920 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 10921 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 10922 | struct intel_unpin_work *work; |
a4872ba6 | 10923 | struct intel_engine_cs *ring; |
cf5d8a46 | 10924 | bool mmio_flip; |
52e68630 | 10925 | int ret; |
6b95a207 | 10926 | |
2ff8fde1 MR |
10927 | /* |
10928 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10929 | * check to be safe. In the future we may enable pageflipping from | |
10930 | * a disabled primary plane. | |
10931 | */ | |
10932 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10933 | return -EBUSY; | |
10934 | ||
e6a595d2 | 10935 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 10936 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
10937 | return -EINVAL; |
10938 | ||
10939 | /* | |
10940 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10941 | * Note that pitch changes could also affect these register. | |
10942 | */ | |
10943 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
10944 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10945 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
10946 | return -EINVAL; |
10947 | ||
f900db47 CW |
10948 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
10949 | goto out_hang; | |
10950 | ||
b14c5679 | 10951 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
10952 | if (work == NULL) |
10953 | return -ENOMEM; | |
10954 | ||
6b95a207 | 10955 | work->event = event; |
b4a98e57 | 10956 | work->crtc = crtc; |
ab8d6675 | 10957 | work->old_fb = old_fb; |
6b95a207 KH |
10958 | INIT_WORK(&work->work, intel_unpin_work_fn); |
10959 | ||
87b6b101 | 10960 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
10961 | if (ret) |
10962 | goto free_work; | |
10963 | ||
6b95a207 | 10964 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 10965 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 10966 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
10967 | /* Before declaring the flip queue wedged, check if |
10968 | * the hardware completed the operation behind our backs. | |
10969 | */ | |
10970 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
10971 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10972 | page_flip_completed(intel_crtc); | |
10973 | } else { | |
10974 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 10975 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 10976 | |
d6bbafa1 CW |
10977 | drm_crtc_vblank_put(crtc); |
10978 | kfree(work); | |
10979 | return -EBUSY; | |
10980 | } | |
6b95a207 KH |
10981 | } |
10982 | intel_crtc->unpin_work = work; | |
5e2d7afc | 10983 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 10984 | |
b4a98e57 CW |
10985 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
10986 | flush_workqueue(dev_priv->wq); | |
10987 | ||
75dfca80 | 10988 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 10989 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 10990 | drm_gem_object_reference(&obj->base); |
6b95a207 | 10991 | |
f4510a27 | 10992 | crtc->primary->fb = fb; |
afd65eb4 | 10993 | update_state_fb(crtc->primary); |
1ed1f968 | 10994 | |
e1f99ce6 | 10995 | work->pending_flip_obj = obj; |
e1f99ce6 | 10996 | |
89ed88ba CW |
10997 | ret = i915_mutex_lock_interruptible(dev); |
10998 | if (ret) | |
10999 | goto cleanup; | |
11000 | ||
b4a98e57 | 11001 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11002 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11003 | |
75f7f3ec | 11004 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 11005 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 11006 | |
4fa62c89 VS |
11007 | if (IS_VALLEYVIEW(dev)) { |
11008 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 11009 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11010 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11011 | ring = NULL; | |
48bf5b2d | 11012 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11013 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11014 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 11015 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
11016 | if (ring == NULL || ring->id != RCS) |
11017 | ring = &dev_priv->ring[BCS]; | |
11018 | } else { | |
11019 | ring = &dev_priv->ring[RCS]; | |
11020 | } | |
11021 | ||
cf5d8a46 CW |
11022 | mmio_flip = use_mmio_flip(ring, obj); |
11023 | ||
11024 | /* When using CS flips, we want to emit semaphores between rings. | |
11025 | * However, when using mmio flips we will create a task to do the | |
11026 | * synchronisation, so all we want here is to pin the framebuffer | |
11027 | * into the display plane and skip any waits. | |
11028 | */ | |
82bc3b2d | 11029 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 CW |
11030 | crtc->primary->state, |
11031 | mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring); | |
8c9f3aaf JB |
11032 | if (ret) |
11033 | goto cleanup_pending; | |
6b95a207 | 11034 | |
121920fa TU |
11035 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
11036 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 11037 | |
cf5d8a46 | 11038 | if (mmio_flip) { |
84c33a64 SG |
11039 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
11040 | page_flip_flags); | |
d6bbafa1 CW |
11041 | if (ret) |
11042 | goto cleanup_unpin; | |
11043 | ||
f06cc1b9 JH |
11044 | i915_gem_request_assign(&work->flip_queued_req, |
11045 | obj->last_write_req); | |
d6bbafa1 | 11046 | } else { |
84c33a64 | 11047 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
11048 | page_flip_flags); |
11049 | if (ret) | |
11050 | goto cleanup_unpin; | |
11051 | ||
f06cc1b9 JH |
11052 | i915_gem_request_assign(&work->flip_queued_req, |
11053 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
11054 | } |
11055 | ||
1e3feefd | 11056 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11057 | work->enable_stall_check = true; |
4fa62c89 | 11058 | |
ab8d6675 | 11059 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
11060 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
11061 | ||
7ff0ebcc | 11062 | intel_fbc_disable(dev); |
f99d7069 | 11063 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
11064 | mutex_unlock(&dev->struct_mutex); |
11065 | ||
e5510fac JB |
11066 | trace_i915_flip_request(intel_crtc->plane, obj); |
11067 | ||
6b95a207 | 11068 | return 0; |
96b099fd | 11069 | |
4fa62c89 | 11070 | cleanup_unpin: |
82bc3b2d | 11071 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11072 | cleanup_pending: |
b4a98e57 | 11073 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11074 | mutex_unlock(&dev->struct_mutex); |
11075 | cleanup: | |
f4510a27 | 11076 | crtc->primary->fb = old_fb; |
afd65eb4 | 11077 | update_state_fb(crtc->primary); |
89ed88ba CW |
11078 | |
11079 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11080 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11081 | |
5e2d7afc | 11082 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11083 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11084 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11085 | |
87b6b101 | 11086 | drm_crtc_vblank_put(crtc); |
7317c75e | 11087 | free_work: |
96b099fd CW |
11088 | kfree(work); |
11089 | ||
f900db47 CW |
11090 | if (ret == -EIO) { |
11091 | out_hang: | |
53a366b9 | 11092 | ret = intel_plane_restore(primary); |
f0d3dad3 | 11093 | if (ret == 0 && event) { |
5e2d7afc | 11094 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11095 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11096 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11097 | } |
f900db47 | 11098 | } |
96b099fd | 11099 | return ret; |
6b95a207 KH |
11100 | } |
11101 | ||
65b38e0d | 11102 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11103 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11104 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11105 | .atomic_begin = intel_begin_crtc_commit, |
11106 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
11107 | }; |
11108 | ||
9a935856 DV |
11109 | /** |
11110 | * intel_modeset_update_staged_output_state | |
11111 | * | |
11112 | * Updates the staged output configuration state, e.g. after we've read out the | |
11113 | * current hw state. | |
11114 | */ | |
11115 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 11116 | { |
7668851f | 11117 | struct intel_crtc *crtc; |
9a935856 DV |
11118 | struct intel_encoder *encoder; |
11119 | struct intel_connector *connector; | |
f6e5b160 | 11120 | |
3a3371ff | 11121 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11122 | connector->new_encoder = |
11123 | to_intel_encoder(connector->base.encoder); | |
11124 | } | |
f6e5b160 | 11125 | |
b2784e15 | 11126 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11127 | encoder->new_crtc = |
11128 | to_intel_crtc(encoder->base.crtc); | |
11129 | } | |
7668851f | 11130 | |
d3fcc808 | 11131 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11132 | crtc->new_enabled = crtc->base.state->enable; |
7668851f | 11133 | } |
f6e5b160 CW |
11134 | } |
11135 | ||
d29b2f9d ACO |
11136 | /* Transitional helper to copy current connector/encoder state to |
11137 | * connector->state. This is needed so that code that is partially | |
11138 | * converted to atomic does the right thing. | |
11139 | */ | |
11140 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
11141 | { | |
11142 | struct intel_connector *connector; | |
11143 | ||
11144 | for_each_intel_connector(dev, connector) { | |
11145 | if (connector->base.encoder) { | |
11146 | connector->base.state->best_encoder = | |
11147 | connector->base.encoder; | |
11148 | connector->base.state->crtc = | |
11149 | connector->base.encoder->crtc; | |
11150 | } else { | |
11151 | connector->base.state->best_encoder = NULL; | |
11152 | connector->base.state->crtc = NULL; | |
11153 | } | |
11154 | } | |
11155 | } | |
11156 | ||
a821fc46 | 11157 | /* Fixup legacy state after an atomic state swap. |
9a935856 | 11158 | */ |
a821fc46 | 11159 | static void intel_modeset_fixup_state(struct drm_atomic_state *state) |
9a935856 | 11160 | { |
a821fc46 | 11161 | struct intel_crtc *crtc; |
9a935856 | 11162 | struct intel_encoder *encoder; |
a821fc46 | 11163 | struct intel_connector *connector; |
d5432a9d | 11164 | |
a821fc46 ACO |
11165 | for_each_intel_connector(state->dev, connector) { |
11166 | connector->base.encoder = connector->base.state->best_encoder; | |
11167 | if (connector->base.encoder) | |
11168 | connector->base.encoder->crtc = | |
11169 | connector->base.state->crtc; | |
9a935856 | 11170 | } |
f6e5b160 | 11171 | |
d5432a9d ACO |
11172 | /* Update crtc of disabled encoders */ |
11173 | for_each_intel_encoder(state->dev, encoder) { | |
11174 | int num_connectors = 0; | |
11175 | ||
a821fc46 ACO |
11176 | for_each_intel_connector(state->dev, connector) |
11177 | if (connector->base.encoder == &encoder->base) | |
d5432a9d ACO |
11178 | num_connectors++; |
11179 | ||
11180 | if (num_connectors == 0) | |
11181 | encoder->base.crtc = NULL; | |
9a935856 | 11182 | } |
7668851f | 11183 | |
a821fc46 ACO |
11184 | for_each_intel_crtc(state->dev, crtc) { |
11185 | crtc->base.enabled = crtc->base.state->enable; | |
11186 | crtc->config = to_intel_crtc_state(crtc->base.state); | |
7668851f | 11187 | } |
d29b2f9d | 11188 | |
d5432a9d ACO |
11189 | /* Copy the new configuration to the staged state, to keep the few |
11190 | * pieces of code that haven't been converted yet happy */ | |
11191 | intel_modeset_update_staged_output_state(state->dev); | |
9a935856 DV |
11192 | } |
11193 | ||
050f7aeb | 11194 | static void |
eba905b2 | 11195 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11196 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11197 | { |
11198 | int bpp = pipe_config->pipe_bpp; | |
11199 | ||
11200 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11201 | connector->base.base.id, | |
c23cc417 | 11202 | connector->base.name); |
050f7aeb DV |
11203 | |
11204 | /* Don't use an invalid EDID bpc value */ | |
11205 | if (connector->base.display_info.bpc && | |
11206 | connector->base.display_info.bpc * 3 < bpp) { | |
11207 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11208 | bpp, connector->base.display_info.bpc*3); | |
11209 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11210 | } | |
11211 | ||
11212 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11213 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11214 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11215 | bpp); | |
11216 | pipe_config->pipe_bpp = 24; | |
11217 | } | |
11218 | } | |
11219 | ||
4e53c2e0 | 11220 | static int |
050f7aeb | 11221 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11222 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11223 | { |
050f7aeb | 11224 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11225 | struct drm_atomic_state *state; |
da3ced29 ACO |
11226 | struct drm_connector *connector; |
11227 | struct drm_connector_state *connector_state; | |
1486017f | 11228 | int bpp, i; |
4e53c2e0 | 11229 | |
d328c9d7 | 11230 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11231 | bpp = 10*3; |
d328c9d7 DV |
11232 | else if (INTEL_INFO(dev)->gen >= 5) |
11233 | bpp = 12*3; | |
11234 | else | |
11235 | bpp = 8*3; | |
11236 | ||
4e53c2e0 | 11237 | |
4e53c2e0 DV |
11238 | pipe_config->pipe_bpp = bpp; |
11239 | ||
1486017f ACO |
11240 | state = pipe_config->base.state; |
11241 | ||
4e53c2e0 | 11242 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11243 | for_each_connector_in_state(state, connector, connector_state, i) { |
11244 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11245 | continue; |
11246 | ||
da3ced29 ACO |
11247 | connected_sink_compute_bpp(to_intel_connector(connector), |
11248 | pipe_config); | |
4e53c2e0 DV |
11249 | } |
11250 | ||
11251 | return bpp; | |
11252 | } | |
11253 | ||
644db711 DV |
11254 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11255 | { | |
11256 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11257 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11258 | mode->crtc_clock, |
644db711 DV |
11259 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11260 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11261 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11262 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11263 | } | |
11264 | ||
c0b03411 | 11265 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11266 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11267 | const char *context) |
11268 | { | |
6a60cd87 CK |
11269 | struct drm_device *dev = crtc->base.dev; |
11270 | struct drm_plane *plane; | |
11271 | struct intel_plane *intel_plane; | |
11272 | struct intel_plane_state *state; | |
11273 | struct drm_framebuffer *fb; | |
11274 | ||
11275 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11276 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11277 | |
11278 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11279 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11280 | pipe_config->pipe_bpp, pipe_config->dither); | |
11281 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11282 | pipe_config->has_pch_encoder, | |
11283 | pipe_config->fdi_lanes, | |
11284 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11285 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11286 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
11287 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11288 | pipe_config->has_dp_encoder, | |
11289 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
11290 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11291 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
11292 | |
11293 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
11294 | pipe_config->has_dp_encoder, | |
11295 | pipe_config->dp_m2_n2.gmch_m, | |
11296 | pipe_config->dp_m2_n2.gmch_n, | |
11297 | pipe_config->dp_m2_n2.link_m, | |
11298 | pipe_config->dp_m2_n2.link_n, | |
11299 | pipe_config->dp_m2_n2.tu); | |
11300 | ||
55072d19 DV |
11301 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11302 | pipe_config->has_audio, | |
11303 | pipe_config->has_infoframe); | |
11304 | ||
c0b03411 | 11305 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11306 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11307 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11308 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11309 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11310 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11311 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11312 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
6a60cd87 CK |
11313 | DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers); |
11314 | DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users); | |
11315 | DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11316 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11317 | pipe_config->gmch_pfit.control, | |
11318 | pipe_config->gmch_pfit.pgm_ratios, | |
11319 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11320 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11321 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11322 | pipe_config->pch_pfit.size, |
11323 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11324 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11325 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 CK |
11326 | |
11327 | DRM_DEBUG_KMS("planes on this crtc\n"); | |
11328 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
11329 | intel_plane = to_intel_plane(plane); | |
11330 | if (intel_plane->pipe != crtc->pipe) | |
11331 | continue; | |
11332 | ||
11333 | state = to_intel_plane_state(plane->state); | |
11334 | fb = state->base.fb; | |
11335 | if (!fb) { | |
11336 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
11337 | "disabled, scaler_id = %d\n", | |
11338 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11339 | plane->base.id, intel_plane->pipe, | |
11340 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
11341 | drm_plane_index(plane), state->scaler_id); | |
11342 | continue; | |
11343 | } | |
11344 | ||
11345 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
11346 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11347 | plane->base.id, intel_plane->pipe, | |
11348 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
11349 | drm_plane_index(plane)); | |
11350 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
11351 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
11352 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
11353 | state->scaler_id, | |
11354 | state->src.x1 >> 16, state->src.y1 >> 16, | |
11355 | drm_rect_width(&state->src) >> 16, | |
11356 | drm_rect_height(&state->src) >> 16, | |
11357 | state->dst.x1, state->dst.y1, | |
11358 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
11359 | } | |
c0b03411 DV |
11360 | } |
11361 | ||
bc079e8b VS |
11362 | static bool encoders_cloneable(const struct intel_encoder *a, |
11363 | const struct intel_encoder *b) | |
accfc0c5 | 11364 | { |
bc079e8b VS |
11365 | /* masks could be asymmetric, so check both ways */ |
11366 | return a == b || (a->cloneable & (1 << b->type) && | |
11367 | b->cloneable & (1 << a->type)); | |
11368 | } | |
11369 | ||
98a221da ACO |
11370 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
11371 | struct intel_crtc *crtc, | |
bc079e8b VS |
11372 | struct intel_encoder *encoder) |
11373 | { | |
bc079e8b | 11374 | struct intel_encoder *source_encoder; |
da3ced29 | 11375 | struct drm_connector *connector; |
98a221da ACO |
11376 | struct drm_connector_state *connector_state; |
11377 | int i; | |
bc079e8b | 11378 | |
da3ced29 | 11379 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da | 11380 | if (connector_state->crtc != &crtc->base) |
bc079e8b VS |
11381 | continue; |
11382 | ||
98a221da ACO |
11383 | source_encoder = |
11384 | to_intel_encoder(connector_state->best_encoder); | |
bc079e8b VS |
11385 | if (!encoders_cloneable(encoder, source_encoder)) |
11386 | return false; | |
11387 | } | |
11388 | ||
11389 | return true; | |
11390 | } | |
11391 | ||
98a221da ACO |
11392 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
11393 | struct intel_crtc *crtc) | |
bc079e8b | 11394 | { |
accfc0c5 | 11395 | struct intel_encoder *encoder; |
da3ced29 | 11396 | struct drm_connector *connector; |
98a221da ACO |
11397 | struct drm_connector_state *connector_state; |
11398 | int i; | |
accfc0c5 | 11399 | |
da3ced29 | 11400 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da ACO |
11401 | if (connector_state->crtc != &crtc->base) |
11402 | continue; | |
11403 | ||
11404 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11405 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
bc079e8b | 11406 | return false; |
accfc0c5 DV |
11407 | } |
11408 | ||
bc079e8b | 11409 | return true; |
accfc0c5 DV |
11410 | } |
11411 | ||
5448a00d | 11412 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11413 | { |
5448a00d ACO |
11414 | struct drm_device *dev = state->dev; |
11415 | struct intel_encoder *encoder; | |
da3ced29 | 11416 | struct drm_connector *connector; |
5448a00d | 11417 | struct drm_connector_state *connector_state; |
00f0b378 | 11418 | unsigned int used_ports = 0; |
5448a00d | 11419 | int i; |
00f0b378 VS |
11420 | |
11421 | /* | |
11422 | * Walk the connector list instead of the encoder | |
11423 | * list to detect the problem on ddi platforms | |
11424 | * where there's just one encoder per digital port. | |
11425 | */ | |
da3ced29 | 11426 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 11427 | if (!connector_state->best_encoder) |
00f0b378 VS |
11428 | continue; |
11429 | ||
5448a00d ACO |
11430 | encoder = to_intel_encoder(connector_state->best_encoder); |
11431 | ||
11432 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11433 | |
11434 | switch (encoder->type) { | |
11435 | unsigned int port_mask; | |
11436 | case INTEL_OUTPUT_UNKNOWN: | |
11437 | if (WARN_ON(!HAS_DDI(dev))) | |
11438 | break; | |
11439 | case INTEL_OUTPUT_DISPLAYPORT: | |
11440 | case INTEL_OUTPUT_HDMI: | |
11441 | case INTEL_OUTPUT_EDP: | |
11442 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11443 | ||
11444 | /* the same port mustn't appear more than once */ | |
11445 | if (used_ports & port_mask) | |
11446 | return false; | |
11447 | ||
11448 | used_ports |= port_mask; | |
11449 | default: | |
11450 | break; | |
11451 | } | |
11452 | } | |
11453 | ||
11454 | return true; | |
11455 | } | |
11456 | ||
83a57153 ACO |
11457 | static void |
11458 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11459 | { | |
11460 | struct drm_crtc_state tmp_state; | |
663a3640 | 11461 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
11462 | struct intel_dpll_hw_state dpll_hw_state; |
11463 | enum intel_dpll_id shared_dpll; | |
83a57153 | 11464 | |
663a3640 | 11465 | /* Clear only the intel specific part of the crtc state excluding scalers */ |
83a57153 | 11466 | tmp_state = crtc_state->base; |
663a3640 | 11467 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
11468 | shared_dpll = crtc_state->shared_dpll; |
11469 | dpll_hw_state = crtc_state->dpll_hw_state; | |
11470 | ||
83a57153 | 11471 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 11472 | |
83a57153 | 11473 | crtc_state->base = tmp_state; |
663a3640 | 11474 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
11475 | crtc_state->shared_dpll = shared_dpll; |
11476 | crtc_state->dpll_hw_state = dpll_hw_state; | |
83a57153 ACO |
11477 | } |
11478 | ||
548ee15b | 11479 | static int |
b8cecdf5 | 11480 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
548ee15b ACO |
11481 | struct drm_atomic_state *state, |
11482 | struct intel_crtc_state *pipe_config) | |
ee7b9f93 | 11483 | { |
7758a113 | 11484 | struct intel_encoder *encoder; |
da3ced29 | 11485 | struct drm_connector *connector; |
0b901879 | 11486 | struct drm_connector_state *connector_state; |
d328c9d7 | 11487 | int base_bpp, ret = -EINVAL; |
0b901879 | 11488 | int i; |
e29c22c0 | 11489 | bool retry = true; |
ee7b9f93 | 11490 | |
98a221da | 11491 | if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { |
accfc0c5 | 11492 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
548ee15b | 11493 | return -EINVAL; |
accfc0c5 DV |
11494 | } |
11495 | ||
5448a00d | 11496 | if (!check_digital_port_conflicts(state)) { |
00f0b378 | 11497 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
548ee15b | 11498 | return -EINVAL; |
00f0b378 VS |
11499 | } |
11500 | ||
83a57153 | 11501 | clear_intel_crtc_state(pipe_config); |
7758a113 | 11502 | |
e143a21c DV |
11503 | pipe_config->cpu_transcoder = |
11504 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 11505 | |
2960bc9c ID |
11506 | /* |
11507 | * Sanitize sync polarity flags based on requested ones. If neither | |
11508 | * positive or negative polarity is requested, treat this as meaning | |
11509 | * negative polarity. | |
11510 | */ | |
2d112de7 | 11511 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11512 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11513 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11514 | |
2d112de7 | 11515 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11516 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11517 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11518 | |
050f7aeb DV |
11519 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
11520 | * plane pixel format and any sink constraints into account. Returns the | |
11521 | * source plane bpp so that dithering can be selected on mismatches | |
11522 | * after encoders and crtc also have had their say. */ | |
d328c9d7 DV |
11523 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11524 | pipe_config); | |
11525 | if (base_bpp < 0) | |
4e53c2e0 DV |
11526 | goto fail; |
11527 | ||
e41a56be VS |
11528 | /* |
11529 | * Determine the real pipe dimensions. Note that stereo modes can | |
11530 | * increase the actual pipe size due to the frame doubling and | |
11531 | * insertion of additional space for blanks between the frame. This | |
11532 | * is stored in the crtc timings. We use the requested mode to do this | |
11533 | * computation to clearly distinguish it from the adjusted mode, which | |
11534 | * can be changed by the connectors in the below retry loop. | |
11535 | */ | |
2d112de7 | 11536 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11537 | &pipe_config->pipe_src_w, |
11538 | &pipe_config->pipe_src_h); | |
e41a56be | 11539 | |
e29c22c0 | 11540 | encoder_retry: |
ef1b460d | 11541 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11542 | pipe_config->port_clock = 0; |
ef1b460d | 11543 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11544 | |
135c81b8 | 11545 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11546 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11547 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11548 | |
7758a113 DV |
11549 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11550 | * adjust it according to limitations or connector properties, and also | |
11551 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11552 | */ |
da3ced29 | 11553 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 11554 | if (connector_state->crtc != crtc) |
7758a113 | 11555 | continue; |
7ae89233 | 11556 | |
0b901879 ACO |
11557 | encoder = to_intel_encoder(connector_state->best_encoder); |
11558 | ||
efea6e8e DV |
11559 | if (!(encoder->compute_config(encoder, pipe_config))) { |
11560 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
11561 | goto fail; |
11562 | } | |
ee7b9f93 | 11563 | } |
47f1c6c9 | 11564 | |
ff9a6750 DV |
11565 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11566 | * done afterwards in case the encoder adjusts the mode. */ | |
11567 | if (!pipe_config->port_clock) | |
2d112de7 | 11568 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11569 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11570 | |
a43f6e0f | 11571 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11572 | if (ret < 0) { |
7758a113 DV |
11573 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11574 | goto fail; | |
ee7b9f93 | 11575 | } |
e29c22c0 DV |
11576 | |
11577 | if (ret == RETRY) { | |
11578 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11579 | ret = -EINVAL; | |
11580 | goto fail; | |
11581 | } | |
11582 | ||
11583 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11584 | retry = false; | |
11585 | goto encoder_retry; | |
11586 | } | |
11587 | ||
d328c9d7 | 11588 | pipe_config->dither = pipe_config->pipe_bpp != base_bpp; |
4e53c2e0 | 11589 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11590 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11591 | |
548ee15b | 11592 | return 0; |
7758a113 | 11593 | fail: |
548ee15b | 11594 | return ret; |
ee7b9f93 | 11595 | } |
47f1c6c9 | 11596 | |
ea9d758d | 11597 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 11598 | { |
ea9d758d | 11599 | struct drm_encoder *encoder; |
f6e5b160 | 11600 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 11601 | |
ea9d758d DV |
11602 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
11603 | if (encoder->crtc == crtc) | |
11604 | return true; | |
11605 | ||
11606 | return false; | |
11607 | } | |
11608 | ||
0a9ab303 ACO |
11609 | static bool |
11610 | needs_modeset(struct drm_crtc_state *state) | |
11611 | { | |
11612 | return state->mode_changed || state->active_changed; | |
11613 | } | |
11614 | ||
ea9d758d | 11615 | static void |
0a9ab303 | 11616 | intel_modeset_update_state(struct drm_atomic_state *state) |
ea9d758d | 11617 | { |
0a9ab303 | 11618 | struct drm_device *dev = state->dev; |
ba41c0de | 11619 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d | 11620 | struct intel_encoder *intel_encoder; |
0a9ab303 ACO |
11621 | struct drm_crtc *crtc; |
11622 | struct drm_crtc_state *crtc_state; | |
ea9d758d | 11623 | struct drm_connector *connector; |
0a9ab303 | 11624 | int i; |
ea9d758d | 11625 | |
ba41c0de DV |
11626 | intel_shared_dpll_commit(dev_priv); |
11627 | ||
b2784e15 | 11628 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
11629 | if (!intel_encoder->base.crtc) |
11630 | continue; | |
11631 | ||
0a9ab303 ACO |
11632 | for_each_crtc_in_state(state, crtc, crtc_state, i) |
11633 | if (crtc == intel_encoder->base.crtc) | |
11634 | break; | |
11635 | ||
11636 | if (crtc != intel_encoder->base.crtc) | |
11637 | continue; | |
ea9d758d | 11638 | |
0a9ab303 | 11639 | if (crtc_state->enable && needs_modeset(crtc_state)) |
ea9d758d DV |
11640 | intel_encoder->connectors_active = false; |
11641 | } | |
11642 | ||
a821fc46 ACO |
11643 | drm_atomic_helper_swap_state(state->dev, state); |
11644 | intel_modeset_fixup_state(state); | |
ea9d758d | 11645 | |
7668851f | 11646 | /* Double check state. */ |
0a9ab303 ACO |
11647 | for_each_crtc(dev, crtc) { |
11648 | WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc)); | |
ea9d758d DV |
11649 | } |
11650 | ||
11651 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11652 | if (!connector->encoder || !connector->encoder->crtc) | |
11653 | continue; | |
11654 | ||
0a9ab303 ACO |
11655 | for_each_crtc_in_state(state, crtc, crtc_state, i) |
11656 | if (crtc == connector->encoder->crtc) | |
11657 | break; | |
11658 | ||
11659 | if (crtc != connector->encoder->crtc) | |
11660 | continue; | |
ea9d758d | 11661 | |
a821fc46 | 11662 | if (crtc->state->enable && needs_modeset(crtc->state)) { |
68d34720 DV |
11663 | struct drm_property *dpms_property = |
11664 | dev->mode_config.dpms_property; | |
11665 | ||
ea9d758d | 11666 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 11667 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
11668 | dpms_property, |
11669 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
11670 | |
11671 | intel_encoder = to_intel_encoder(connector->encoder); | |
11672 | intel_encoder->connectors_active = true; | |
11673 | } | |
11674 | } | |
11675 | ||
11676 | } | |
11677 | ||
3bd26263 | 11678 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11679 | { |
3bd26263 | 11680 | int diff; |
f1f644dc JB |
11681 | |
11682 | if (clock1 == clock2) | |
11683 | return true; | |
11684 | ||
11685 | if (!clock1 || !clock2) | |
11686 | return false; | |
11687 | ||
11688 | diff = abs(clock1 - clock2); | |
11689 | ||
11690 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11691 | return true; | |
11692 | ||
11693 | return false; | |
11694 | } | |
11695 | ||
25c5b266 DV |
11696 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
11697 | list_for_each_entry((intel_crtc), \ | |
11698 | &(dev)->mode_config.crtc_list, \ | |
11699 | base.head) \ | |
0973f18f | 11700 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 11701 | |
0e8ffe1b | 11702 | static bool |
2fa2fe9a | 11703 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
11704 | struct intel_crtc_state *current_config, |
11705 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 11706 | { |
66e985c0 DV |
11707 | #define PIPE_CONF_CHECK_X(name) \ |
11708 | if (current_config->name != pipe_config->name) { \ | |
11709 | DRM_ERROR("mismatch in " #name " " \ | |
11710 | "(expected 0x%08x, found 0x%08x)\n", \ | |
11711 | current_config->name, \ | |
11712 | pipe_config->name); \ | |
11713 | return false; \ | |
11714 | } | |
11715 | ||
08a24034 DV |
11716 | #define PIPE_CONF_CHECK_I(name) \ |
11717 | if (current_config->name != pipe_config->name) { \ | |
11718 | DRM_ERROR("mismatch in " #name " " \ | |
11719 | "(expected %i, found %i)\n", \ | |
11720 | current_config->name, \ | |
11721 | pipe_config->name); \ | |
11722 | return false; \ | |
88adfff1 DV |
11723 | } |
11724 | ||
b95af8be VK |
11725 | /* This is required for BDW+ where there is only one set of registers for |
11726 | * switching between high and low RR. | |
11727 | * This macro can be used whenever a comparison has to be made between one | |
11728 | * hw state and multiple sw state variables. | |
11729 | */ | |
11730 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
11731 | if ((current_config->name != pipe_config->name) && \ | |
11732 | (current_config->alt_name != pipe_config->name)) { \ | |
11733 | DRM_ERROR("mismatch in " #name " " \ | |
11734 | "(expected %i or %i, found %i)\n", \ | |
11735 | current_config->name, \ | |
11736 | current_config->alt_name, \ | |
11737 | pipe_config->name); \ | |
11738 | return false; \ | |
11739 | } | |
11740 | ||
1bd1bd80 DV |
11741 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11742 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 11743 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
11744 | "(expected %i, found %i)\n", \ |
11745 | current_config->name & (mask), \ | |
11746 | pipe_config->name & (mask)); \ | |
11747 | return false; \ | |
11748 | } | |
11749 | ||
5e550656 VS |
11750 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11751 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
11752 | DRM_ERROR("mismatch in " #name " " \ | |
11753 | "(expected %i, found %i)\n", \ | |
11754 | current_config->name, \ | |
11755 | pipe_config->name); \ | |
11756 | return false; \ | |
11757 | } | |
11758 | ||
bb760063 DV |
11759 | #define PIPE_CONF_QUIRK(quirk) \ |
11760 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11761 | ||
eccb140b DV |
11762 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11763 | ||
08a24034 DV |
11764 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11765 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
11766 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
11767 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
11768 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
11769 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
11770 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 11771 | |
eb14cb74 | 11772 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
11773 | |
11774 | if (INTEL_INFO(dev)->gen < 8) { | |
11775 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
11776 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
11777 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
11778 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
11779 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
11780 | ||
11781 | if (current_config->has_drrs) { | |
11782 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
11783 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
11784 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
11785 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
11786 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
11787 | } | |
11788 | } else { | |
11789 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
11790 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
11791 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
11792 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
11793 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
11794 | } | |
eb14cb74 | 11795 | |
2d112de7 ACO |
11796 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11797 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11798 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11799 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11800 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11801 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11802 | |
2d112de7 ACO |
11803 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11804 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11805 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11806 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11807 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11808 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11809 | |
c93f54cf | 11810 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11811 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
11812 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
11813 | IS_VALLEYVIEW(dev)) | |
11814 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 11815 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11816 | |
9ed109a7 DV |
11817 | PIPE_CONF_CHECK_I(has_audio); |
11818 | ||
2d112de7 | 11819 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11820 | DRM_MODE_FLAG_INTERLACE); |
11821 | ||
bb760063 | 11822 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11823 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11824 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11825 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11826 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11827 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11828 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11829 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11830 | DRM_MODE_FLAG_NVSYNC); |
11831 | } | |
045ac3b5 | 11832 | |
37327abd VS |
11833 | PIPE_CONF_CHECK_I(pipe_src_w); |
11834 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 11835 | |
9953599b DV |
11836 | /* |
11837 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
11838 | * screen. Since we don't yet re-compute the pipe config when moving | |
11839 | * just the lvds port away to another pipe the sw tracking won't match. | |
11840 | * | |
11841 | * Proper atomic modesets with recomputed global state will fix this. | |
11842 | * Until then just don't check gmch state for inherited modes. | |
11843 | */ | |
11844 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
11845 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
11846 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
11847 | if (INTEL_INFO(dev)->gen < 4) | |
11848 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
11849 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
11850 | } | |
11851 | ||
fd4daa9c CW |
11852 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
11853 | if (current_config->pch_pfit.enabled) { | |
11854 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
11855 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
11856 | } | |
2fa2fe9a | 11857 | |
a1b2278e CK |
11858 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
11859 | ||
e59150dc JB |
11860 | /* BDW+ don't expose a synchronous way to read the state */ |
11861 | if (IS_HASWELL(dev)) | |
11862 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 11863 | |
282740f7 VS |
11864 | PIPE_CONF_CHECK_I(double_wide); |
11865 | ||
26804afd DV |
11866 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
11867 | ||
c0d43d62 | 11868 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 11869 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11870 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11871 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11872 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11873 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
11874 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11875 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11876 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11877 | |
42571aef VS |
11878 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
11879 | PIPE_CONF_CHECK_I(pipe_bpp); | |
11880 | ||
2d112de7 | 11881 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11882 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11883 | |
66e985c0 | 11884 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11885 | #undef PIPE_CONF_CHECK_I |
b95af8be | 11886 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 11887 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11888 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11889 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11890 | |
0e8ffe1b DV |
11891 | return true; |
11892 | } | |
11893 | ||
08db6652 DL |
11894 | static void check_wm_state(struct drm_device *dev) |
11895 | { | |
11896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11897 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
11898 | struct intel_crtc *intel_crtc; | |
11899 | int plane; | |
11900 | ||
11901 | if (INTEL_INFO(dev)->gen < 9) | |
11902 | return; | |
11903 | ||
11904 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
11905 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11906 | ||
11907 | for_each_intel_crtc(dev, intel_crtc) { | |
11908 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
11909 | const enum pipe pipe = intel_crtc->pipe; | |
11910 | ||
11911 | if (!intel_crtc->active) | |
11912 | continue; | |
11913 | ||
11914 | /* planes */ | |
dd740780 | 11915 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
11916 | hw_entry = &hw_ddb.plane[pipe][plane]; |
11917 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
11918 | ||
11919 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11920 | continue; | |
11921 | ||
11922 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
11923 | "(expected (%u,%u), found (%u,%u))\n", | |
11924 | pipe_name(pipe), plane + 1, | |
11925 | sw_entry->start, sw_entry->end, | |
11926 | hw_entry->start, hw_entry->end); | |
11927 | } | |
11928 | ||
11929 | /* cursor */ | |
11930 | hw_entry = &hw_ddb.cursor[pipe]; | |
11931 | sw_entry = &sw_ddb->cursor[pipe]; | |
11932 | ||
11933 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11934 | continue; | |
11935 | ||
11936 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
11937 | "(expected (%u,%u), found (%u,%u))\n", | |
11938 | pipe_name(pipe), | |
11939 | sw_entry->start, sw_entry->end, | |
11940 | hw_entry->start, hw_entry->end); | |
11941 | } | |
11942 | } | |
11943 | ||
91d1b4bd DV |
11944 | static void |
11945 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 11946 | { |
8af6cf88 DV |
11947 | struct intel_connector *connector; |
11948 | ||
3a3371ff | 11949 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11950 | /* This also checks the encoder/connector hw state with the |
11951 | * ->get_hw_state callbacks. */ | |
11952 | intel_connector_check_state(connector); | |
11953 | ||
e2c719b7 | 11954 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
11955 | "connector's staged encoder doesn't match current encoder\n"); |
11956 | } | |
91d1b4bd DV |
11957 | } |
11958 | ||
11959 | static void | |
11960 | check_encoder_state(struct drm_device *dev) | |
11961 | { | |
11962 | struct intel_encoder *encoder; | |
11963 | struct intel_connector *connector; | |
8af6cf88 | 11964 | |
b2784e15 | 11965 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11966 | bool enabled = false; |
11967 | bool active = false; | |
11968 | enum pipe pipe, tracked_pipe; | |
11969 | ||
11970 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11971 | encoder->base.base.id, | |
8e329a03 | 11972 | encoder->base.name); |
8af6cf88 | 11973 | |
e2c719b7 | 11974 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 11975 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 11976 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
11977 | "encoder's active_connectors set, but no crtc\n"); |
11978 | ||
3a3371ff | 11979 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11980 | if (connector->base.encoder != &encoder->base) |
11981 | continue; | |
11982 | enabled = true; | |
11983 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
11984 | active = true; | |
11985 | } | |
0e32b39c DA |
11986 | /* |
11987 | * for MST connectors if we unplug the connector is gone | |
11988 | * away but the encoder is still connected to a crtc | |
11989 | * until a modeset happens in response to the hotplug. | |
11990 | */ | |
11991 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
11992 | continue; | |
11993 | ||
e2c719b7 | 11994 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11995 | "encoder's enabled state mismatch " |
11996 | "(expected %i, found %i)\n", | |
11997 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 11998 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
11999 | "active encoder with no crtc\n"); |
12000 | ||
e2c719b7 | 12001 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
12002 | "encoder's computed active state doesn't match tracked active state " |
12003 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
12004 | ||
12005 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 12006 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
12007 | "encoder's hw state doesn't match sw tracking " |
12008 | "(expected %i, found %i)\n", | |
12009 | encoder->connectors_active, active); | |
12010 | ||
12011 | if (!encoder->base.crtc) | |
12012 | continue; | |
12013 | ||
12014 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 12015 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
12016 | "active encoder's pipe doesn't match" |
12017 | "(expected %i, found %i)\n", | |
12018 | tracked_pipe, pipe); | |
12019 | ||
12020 | } | |
91d1b4bd DV |
12021 | } |
12022 | ||
12023 | static void | |
12024 | check_crtc_state(struct drm_device *dev) | |
12025 | { | |
fbee40df | 12026 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12027 | struct intel_crtc *crtc; |
12028 | struct intel_encoder *encoder; | |
5cec258b | 12029 | struct intel_crtc_state pipe_config; |
8af6cf88 | 12030 | |
d3fcc808 | 12031 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
12032 | bool enabled = false; |
12033 | bool active = false; | |
12034 | ||
045ac3b5 JB |
12035 | memset(&pipe_config, 0, sizeof(pipe_config)); |
12036 | ||
8af6cf88 DV |
12037 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12038 | crtc->base.base.id); | |
12039 | ||
83d65738 | 12040 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
12041 | "active crtc, but not enabled in sw tracking\n"); |
12042 | ||
b2784e15 | 12043 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12044 | if (encoder->base.crtc != &crtc->base) |
12045 | continue; | |
12046 | enabled = true; | |
12047 | if (encoder->connectors_active) | |
12048 | active = true; | |
12049 | } | |
6c49f241 | 12050 | |
e2c719b7 | 12051 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
12052 | "crtc's computed active state doesn't match tracked active state " |
12053 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 12054 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 12055 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
12056 | "(expected %i, found %i)\n", enabled, |
12057 | crtc->base.state->enable); | |
8af6cf88 | 12058 | |
0e8ffe1b DV |
12059 | active = dev_priv->display.get_pipe_config(crtc, |
12060 | &pipe_config); | |
d62cf62a | 12061 | |
b6b5d049 VS |
12062 | /* hw state is inconsistent with the pipe quirk */ |
12063 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12064 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
12065 | active = crtc->active; |
12066 | ||
b2784e15 | 12067 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 12068 | enum pipe pipe; |
6c49f241 DV |
12069 | if (encoder->base.crtc != &crtc->base) |
12070 | continue; | |
1d37b689 | 12071 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
12072 | encoder->get_config(encoder, &pipe_config); |
12073 | } | |
12074 | ||
e2c719b7 | 12075 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
12076 | "crtc active state doesn't match with hw state " |
12077 | "(expected %i, found %i)\n", crtc->active, active); | |
12078 | ||
c0b03411 | 12079 | if (active && |
6e3c9717 | 12080 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 12081 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
12082 | intel_dump_pipe_config(crtc, &pipe_config, |
12083 | "[hw state]"); | |
6e3c9717 | 12084 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
12085 | "[sw state]"); |
12086 | } | |
8af6cf88 DV |
12087 | } |
12088 | } | |
12089 | ||
91d1b4bd DV |
12090 | static void |
12091 | check_shared_dpll_state(struct drm_device *dev) | |
12092 | { | |
fbee40df | 12093 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12094 | struct intel_crtc *crtc; |
12095 | struct intel_dpll_hw_state dpll_hw_state; | |
12096 | int i; | |
5358901f DV |
12097 | |
12098 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12099 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12100 | int enabled_crtcs = 0, active_crtcs = 0; | |
12101 | bool active; | |
12102 | ||
12103 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12104 | ||
12105 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12106 | ||
12107 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12108 | ||
e2c719b7 | 12109 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12110 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12111 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12112 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12113 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12114 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12115 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12116 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12117 | "pll on state mismatch (expected %i, found %i)\n", |
12118 | pll->on, active); | |
12119 | ||
d3fcc808 | 12120 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12121 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12122 | enabled_crtcs++; |
12123 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12124 | active_crtcs++; | |
12125 | } | |
e2c719b7 | 12126 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12127 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12128 | pll->active, active_crtcs); | |
e2c719b7 | 12129 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12130 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12131 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12132 | |
e2c719b7 | 12133 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12134 | sizeof(dpll_hw_state)), |
12135 | "pll hw state mismatch\n"); | |
5358901f | 12136 | } |
8af6cf88 DV |
12137 | } |
12138 | ||
91d1b4bd DV |
12139 | void |
12140 | intel_modeset_check_state(struct drm_device *dev) | |
12141 | { | |
08db6652 | 12142 | check_wm_state(dev); |
91d1b4bd DV |
12143 | check_connector_state(dev); |
12144 | check_encoder_state(dev); | |
12145 | check_crtc_state(dev); | |
12146 | check_shared_dpll_state(dev); | |
12147 | } | |
12148 | ||
5cec258b | 12149 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12150 | int dotclock) |
12151 | { | |
12152 | /* | |
12153 | * FDI already provided one idea for the dotclock. | |
12154 | * Yell if the encoder disagrees. | |
12155 | */ | |
2d112de7 | 12156 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12157 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12158 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12159 | } |
12160 | ||
80715b2f VS |
12161 | static void update_scanline_offset(struct intel_crtc *crtc) |
12162 | { | |
12163 | struct drm_device *dev = crtc->base.dev; | |
12164 | ||
12165 | /* | |
12166 | * The scanline counter increments at the leading edge of hsync. | |
12167 | * | |
12168 | * On most platforms it starts counting from vtotal-1 on the | |
12169 | * first active line. That means the scanline counter value is | |
12170 | * always one less than what we would expect. Ie. just after | |
12171 | * start of vblank, which also occurs at start of hsync (on the | |
12172 | * last active line), the scanline counter will read vblank_start-1. | |
12173 | * | |
12174 | * On gen2 the scanline counter starts counting from 1 instead | |
12175 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12176 | * to keep the value positive), instead of adding one. | |
12177 | * | |
12178 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12179 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12180 | * there's an extra 1 line difference. So we need to add two instead of | |
12181 | * one to the value. | |
12182 | */ | |
12183 | if (IS_GEN2(dev)) { | |
6e3c9717 | 12184 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12185 | int vtotal; |
12186 | ||
12187 | vtotal = mode->crtc_vtotal; | |
12188 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
12189 | vtotal /= 2; | |
12190 | ||
12191 | crtc->scanline_offset = vtotal - 1; | |
12192 | } else if (HAS_DDI(dev) && | |
409ee761 | 12193 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12194 | crtc->scanline_offset = 2; |
12195 | } else | |
12196 | crtc->scanline_offset = 1; | |
12197 | } | |
12198 | ||
5cec258b | 12199 | static struct intel_crtc_state * |
7f27126e | 12200 | intel_modeset_compute_config(struct drm_crtc *crtc, |
0a9ab303 | 12201 | struct drm_atomic_state *state) |
7f27126e | 12202 | { |
548ee15b | 12203 | struct intel_crtc_state *pipe_config; |
0b901879 ACO |
12204 | int ret = 0; |
12205 | ||
12206 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12207 | if (ret) | |
12208 | return ERR_PTR(ret); | |
7f27126e | 12209 | |
8c7b5ccb ACO |
12210 | ret = drm_atomic_helper_check_modeset(state->dev, state); |
12211 | if (ret) | |
12212 | return ERR_PTR(ret); | |
7f27126e | 12213 | |
7f27126e JB |
12214 | /* |
12215 | * Note this needs changes when we start tracking multiple modes | |
12216 | * and crtcs. At that point we'll need to compute the whole config | |
12217 | * (i.e. one pipe_config for each crtc) rather than just the one | |
12218 | * for this crtc. | |
12219 | */ | |
548ee15b ACO |
12220 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
12221 | if (IS_ERR(pipe_config)) | |
12222 | return pipe_config; | |
83a57153 | 12223 | |
4fed33f6 | 12224 | if (!pipe_config->base.enable) |
548ee15b | 12225 | return pipe_config; |
7f27126e | 12226 | |
8c7b5ccb | 12227 | ret = intel_modeset_pipe_config(crtc, state, pipe_config); |
548ee15b ACO |
12228 | if (ret) |
12229 | return ERR_PTR(ret); | |
12230 | ||
8d8c9b51 ACO |
12231 | /* Check things that can only be changed through modeset */ |
12232 | if (pipe_config->has_audio != | |
12233 | to_intel_crtc(crtc)->config->has_audio) | |
12234 | pipe_config->base.mode_changed = true; | |
12235 | ||
12236 | /* | |
12237 | * Note we have an issue here with infoframes: current code | |
12238 | * only updates them on the full mode set path per hw | |
12239 | * requirements. So here we should be checking for any | |
12240 | * required changes and forcing a mode set. | |
12241 | */ | |
12242 | ||
548ee15b | 12243 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]"); |
db7542dd | 12244 | |
8c7b5ccb ACO |
12245 | ret = drm_atomic_helper_check_planes(state->dev, state); |
12246 | if (ret) | |
12247 | return ERR_PTR(ret); | |
12248 | ||
548ee15b | 12249 | return pipe_config; |
7f27126e JB |
12250 | } |
12251 | ||
0a9ab303 | 12252 | static int __intel_set_mode_setup_plls(struct drm_atomic_state *state) |
ed6739ef | 12253 | { |
225da59b | 12254 | struct drm_device *dev = state->dev; |
ed6739ef | 12255 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 12256 | unsigned clear_pipes = 0; |
ed6739ef | 12257 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
12258 | struct intel_crtc_state *intel_crtc_state; |
12259 | struct drm_crtc *crtc; | |
12260 | struct drm_crtc_state *crtc_state; | |
ed6739ef | 12261 | int ret = 0; |
0a9ab303 | 12262 | int i; |
ed6739ef ACO |
12263 | |
12264 | if (!dev_priv->display.crtc_compute_clock) | |
12265 | return 0; | |
12266 | ||
0a9ab303 ACO |
12267 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12268 | intel_crtc = to_intel_crtc(crtc); | |
4978cc93 | 12269 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
0a9ab303 | 12270 | |
4978cc93 | 12271 | if (needs_modeset(crtc_state)) { |
0a9ab303 | 12272 | clear_pipes |= 1 << intel_crtc->pipe; |
4978cc93 ACO |
12273 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
12274 | memset(&intel_crtc_state->dpll_hw_state, 0, | |
12275 | sizeof(intel_crtc_state->dpll_hw_state)); | |
12276 | } | |
0a9ab303 ACO |
12277 | } |
12278 | ||
ed6739ef ACO |
12279 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); |
12280 | if (ret) | |
12281 | goto done; | |
12282 | ||
0a9ab303 ACO |
12283 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12284 | if (!needs_modeset(crtc_state) || !crtc_state->enable) | |
225da59b ACO |
12285 | continue; |
12286 | ||
0a9ab303 ACO |
12287 | intel_crtc = to_intel_crtc(crtc); |
12288 | intel_crtc_state = to_intel_crtc_state(crtc_state); | |
12289 | ||
ed6739ef | 12290 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
0a9ab303 | 12291 | intel_crtc_state); |
ed6739ef ACO |
12292 | if (ret) { |
12293 | intel_shared_dpll_abort_config(dev_priv); | |
12294 | goto done; | |
12295 | } | |
12296 | } | |
12297 | ||
12298 | done: | |
12299 | return ret; | |
12300 | } | |
12301 | ||
054518dd ACO |
12302 | /* Code that should eventually be part of atomic_check() */ |
12303 | static int __intel_set_mode_checks(struct drm_atomic_state *state) | |
12304 | { | |
12305 | struct drm_device *dev = state->dev; | |
12306 | int ret; | |
12307 | ||
12308 | /* | |
12309 | * See if the config requires any additional preparation, e.g. | |
12310 | * to adjust global state with pipes off. We need to do this | |
12311 | * here so we can get the modeset_pipe updated config for the new | |
12312 | * mode set on this crtc. For other crtcs we need to use the | |
12313 | * adjusted_mode bits in the crtc directly. | |
12314 | */ | |
12315 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { | |
12316 | ret = valleyview_modeset_global_pipes(state); | |
12317 | if (ret) | |
12318 | return ret; | |
12319 | } | |
12320 | ||
12321 | ret = __intel_set_mode_setup_plls(state); | |
12322 | if (ret) | |
12323 | return ret; | |
12324 | ||
12325 | return 0; | |
12326 | } | |
12327 | ||
0a9ab303 | 12328 | static int __intel_set_mode(struct drm_crtc *modeset_crtc, |
0a9ab303 | 12329 | struct intel_crtc_state *pipe_config) |
a6778b3c | 12330 | { |
0a9ab303 | 12331 | struct drm_device *dev = modeset_crtc->dev; |
fbee40df | 12332 | struct drm_i915_private *dev_priv = dev->dev_private; |
304603f4 | 12333 | struct drm_atomic_state *state = pipe_config->base.state; |
0a9ab303 ACO |
12334 | struct drm_crtc *crtc; |
12335 | struct drm_crtc_state *crtc_state; | |
c0c36b94 | 12336 | int ret = 0; |
0a9ab303 | 12337 | int i; |
a6778b3c | 12338 | |
054518dd ACO |
12339 | ret = __intel_set_mode_checks(state); |
12340 | if (ret < 0) | |
12341 | return ret; | |
12342 | ||
d4afb8cc ACO |
12343 | ret = drm_atomic_helper_prepare_planes(dev, state); |
12344 | if (ret) | |
12345 | return ret; | |
12346 | ||
0a9ab303 ACO |
12347 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12348 | if (!needs_modeset(crtc_state)) | |
12349 | continue; | |
460da916 | 12350 | |
0a9ab303 ACO |
12351 | if (!crtc_state->enable) { |
12352 | intel_crtc_disable(crtc); | |
12353 | } else if (crtc->state->enable) { | |
12354 | intel_crtc_disable_planes(crtc); | |
12355 | dev_priv->display.crtc_disable(crtc); | |
ce22dba9 | 12356 | } |
ea9d758d | 12357 | } |
a6778b3c | 12358 | |
6c4c86f5 DV |
12359 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
12360 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
12361 | * |
12362 | * Note we'll need to fix this up when we start tracking multiple | |
12363 | * pipes; here we assume a single modeset_pipe and only track the | |
12364 | * single crtc and mode. | |
f6e5b160 | 12365 | */ |
0a9ab303 | 12366 | if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) { |
8c7b5ccb | 12367 | modeset_crtc->mode = pipe_config->base.mode; |
c326c0a9 VS |
12368 | |
12369 | /* | |
12370 | * Calculate and store various constants which | |
12371 | * are later needed by vblank and swap-completion | |
12372 | * timestamping. They are derived from true hwmode. | |
12373 | */ | |
0a9ab303 | 12374 | drm_calc_timestamping_constants(modeset_crtc, |
2d112de7 | 12375 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 12376 | } |
7758a113 | 12377 | |
ea9d758d DV |
12378 | /* Only after disabling all output pipelines that will be changed can we |
12379 | * update the the output configuration. */ | |
0a9ab303 | 12380 | intel_modeset_update_state(state); |
f6e5b160 | 12381 | |
a821fc46 ACO |
12382 | /* The state has been swaped above, so state actually contains the |
12383 | * old state now. */ | |
12384 | ||
304603f4 | 12385 | modeset_update_crtc_power_domains(state); |
47fab737 | 12386 | |
d4afb8cc | 12387 | drm_atomic_helper_commit_planes(dev, state); |
a6778b3c DV |
12388 | |
12389 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
0a9ab303 | 12390 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a821fc46 | 12391 | if (!needs_modeset(crtc->state) || !crtc->state->enable) |
0a9ab303 ACO |
12392 | continue; |
12393 | ||
12394 | update_scanline_offset(to_intel_crtc(crtc)); | |
80715b2f | 12395 | |
0a9ab303 ACO |
12396 | dev_priv->display.crtc_enable(crtc); |
12397 | intel_crtc_enable_planes(crtc); | |
80715b2f | 12398 | } |
a6778b3c | 12399 | |
a6778b3c | 12400 | /* FIXME: add subpixel order */ |
83a57153 | 12401 | |
d4afb8cc ACO |
12402 | drm_atomic_helper_cleanup_planes(dev, state); |
12403 | ||
2bfb4627 ACO |
12404 | drm_atomic_state_free(state); |
12405 | ||
9eb45f22 | 12406 | return 0; |
f6e5b160 CW |
12407 | } |
12408 | ||
0a9ab303 | 12409 | static int intel_set_mode_with_config(struct drm_crtc *crtc, |
0a9ab303 | 12410 | struct intel_crtc_state *pipe_config) |
f30da187 DV |
12411 | { |
12412 | int ret; | |
12413 | ||
8c7b5ccb | 12414 | ret = __intel_set_mode(crtc, pipe_config); |
f30da187 DV |
12415 | |
12416 | if (ret == 0) | |
12417 | intel_modeset_check_state(crtc->dev); | |
12418 | ||
12419 | return ret; | |
12420 | } | |
12421 | ||
7f27126e | 12422 | static int intel_set_mode(struct drm_crtc *crtc, |
83a57153 | 12423 | struct drm_atomic_state *state) |
7f27126e | 12424 | { |
5cec258b | 12425 | struct intel_crtc_state *pipe_config; |
83a57153 | 12426 | int ret = 0; |
7f27126e | 12427 | |
8c7b5ccb | 12428 | pipe_config = intel_modeset_compute_config(crtc, state); |
83a57153 ACO |
12429 | if (IS_ERR(pipe_config)) { |
12430 | ret = PTR_ERR(pipe_config); | |
12431 | goto out; | |
12432 | } | |
12433 | ||
8c7b5ccb | 12434 | ret = intel_set_mode_with_config(crtc, pipe_config); |
83a57153 ACO |
12435 | if (ret) |
12436 | goto out; | |
7f27126e | 12437 | |
83a57153 ACO |
12438 | out: |
12439 | return ret; | |
7f27126e JB |
12440 | } |
12441 | ||
c0c36b94 CW |
12442 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
12443 | { | |
83a57153 ACO |
12444 | struct drm_device *dev = crtc->dev; |
12445 | struct drm_atomic_state *state; | |
4be07317 | 12446 | struct intel_crtc *intel_crtc; |
83a57153 ACO |
12447 | struct intel_encoder *encoder; |
12448 | struct intel_connector *connector; | |
12449 | struct drm_connector_state *connector_state; | |
4be07317 | 12450 | struct intel_crtc_state *crtc_state; |
2bfb4627 | 12451 | int ret; |
83a57153 ACO |
12452 | |
12453 | state = drm_atomic_state_alloc(dev); | |
12454 | if (!state) { | |
12455 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
12456 | crtc->base.id); | |
12457 | return; | |
12458 | } | |
12459 | ||
12460 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12461 | ||
12462 | /* The force restore path in the HW readout code relies on the staged | |
12463 | * config still keeping the user requested config while the actual | |
12464 | * state has been overwritten by the configuration read from HW. We | |
12465 | * need to copy the staged config to the atomic state, otherwise the | |
12466 | * mode set will just reapply the state the HW is already in. */ | |
12467 | for_each_intel_encoder(dev, encoder) { | |
12468 | if (&encoder->new_crtc->base != crtc) | |
12469 | continue; | |
12470 | ||
12471 | for_each_intel_connector(dev, connector) { | |
12472 | if (connector->new_encoder != encoder) | |
12473 | continue; | |
12474 | ||
12475 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
12476 | if (IS_ERR(connector_state)) { | |
12477 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
12478 | connector->base.base.id, | |
12479 | connector->base.name, | |
12480 | PTR_ERR(connector_state)); | |
12481 | continue; | |
12482 | } | |
12483 | ||
12484 | connector_state->crtc = crtc; | |
12485 | connector_state->best_encoder = &encoder->base; | |
12486 | } | |
12487 | } | |
12488 | ||
4be07317 ACO |
12489 | for_each_intel_crtc(dev, intel_crtc) { |
12490 | if (intel_crtc->new_enabled == intel_crtc->base.enabled) | |
12491 | continue; | |
12492 | ||
12493 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
12494 | if (IS_ERR(crtc_state)) { | |
12495 | DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n", | |
12496 | intel_crtc->base.base.id, | |
12497 | PTR_ERR(crtc_state)); | |
12498 | continue; | |
12499 | } | |
12500 | ||
12501 | crtc_state->base.enable = intel_crtc->new_enabled; | |
8c7b5ccb ACO |
12502 | |
12503 | if (&intel_crtc->base == crtc) | |
12504 | drm_mode_copy(&crtc_state->base.mode, &crtc->mode); | |
4be07317 ACO |
12505 | } |
12506 | ||
d3a40d1b ACO |
12507 | intel_modeset_setup_plane_state(state, crtc, &crtc->mode, |
12508 | crtc->primary->fb, crtc->x, crtc->y); | |
12509 | ||
2bfb4627 ACO |
12510 | ret = intel_set_mode(crtc, state); |
12511 | if (ret) | |
12512 | drm_atomic_state_free(state); | |
c0c36b94 CW |
12513 | } |
12514 | ||
25c5b266 DV |
12515 | #undef for_each_intel_crtc_masked |
12516 | ||
b7885264 ACO |
12517 | static bool intel_connector_in_mode_set(struct intel_connector *connector, |
12518 | struct drm_mode_set *set) | |
12519 | { | |
12520 | int ro; | |
12521 | ||
12522 | for (ro = 0; ro < set->num_connectors; ro++) | |
12523 | if (set->connectors[ro] == &connector->base) | |
12524 | return true; | |
12525 | ||
12526 | return false; | |
12527 | } | |
12528 | ||
2e431051 | 12529 | static int |
9a935856 DV |
12530 | intel_modeset_stage_output_state(struct drm_device *dev, |
12531 | struct drm_mode_set *set, | |
944b0c76 | 12532 | struct drm_atomic_state *state) |
50f56119 | 12533 | { |
9a935856 | 12534 | struct intel_connector *connector; |
d5432a9d | 12535 | struct drm_connector *drm_connector; |
944b0c76 | 12536 | struct drm_connector_state *connector_state; |
d5432a9d ACO |
12537 | struct drm_crtc *crtc; |
12538 | struct drm_crtc_state *crtc_state; | |
12539 | int i, ret; | |
50f56119 | 12540 | |
9abdda74 | 12541 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
12542 | * of connectors. For paranoia, double-check this. */ |
12543 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
12544 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
12545 | ||
3a3371ff | 12546 | for_each_intel_connector(dev, connector) { |
b7885264 ACO |
12547 | bool in_mode_set = intel_connector_in_mode_set(connector, set); |
12548 | ||
d5432a9d ACO |
12549 | if (!in_mode_set && connector->base.state->crtc != set->crtc) |
12550 | continue; | |
12551 | ||
12552 | connector_state = | |
12553 | drm_atomic_get_connector_state(state, &connector->base); | |
12554 | if (IS_ERR(connector_state)) | |
12555 | return PTR_ERR(connector_state); | |
12556 | ||
b7885264 ACO |
12557 | if (in_mode_set) { |
12558 | int pipe = to_intel_crtc(set->crtc)->pipe; | |
d5432a9d ACO |
12559 | connector_state->best_encoder = |
12560 | &intel_find_encoder(connector, pipe)->base; | |
50f56119 DV |
12561 | } |
12562 | ||
d5432a9d | 12563 | if (connector->base.state->crtc != set->crtc) |
b7885264 ACO |
12564 | continue; |
12565 | ||
9a935856 DV |
12566 | /* If we disable the crtc, disable all its connectors. Also, if |
12567 | * the connector is on the changing crtc but not on the new | |
12568 | * connector list, disable it. */ | |
b7885264 | 12569 | if (!set->fb || !in_mode_set) { |
d5432a9d | 12570 | connector_state->best_encoder = NULL; |
9a935856 DV |
12571 | |
12572 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
12573 | connector->base.base.id, | |
c23cc417 | 12574 | connector->base.name); |
9a935856 | 12575 | } |
50f56119 | 12576 | } |
9a935856 | 12577 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 12578 | |
d5432a9d ACO |
12579 | for_each_connector_in_state(state, drm_connector, connector_state, i) { |
12580 | connector = to_intel_connector(drm_connector); | |
12581 | ||
12582 | if (!connector_state->best_encoder) { | |
12583 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
12584 | NULL); | |
12585 | if (ret) | |
12586 | return ret; | |
7668851f | 12587 | |
50f56119 | 12588 | continue; |
d5432a9d | 12589 | } |
50f56119 | 12590 | |
d5432a9d ACO |
12591 | if (intel_connector_in_mode_set(connector, set)) { |
12592 | struct drm_crtc *crtc = connector->base.state->crtc; | |
12593 | ||
12594 | /* If this connector was in a previous crtc, add it | |
12595 | * to the state. We might need to disable it. */ | |
12596 | if (crtc) { | |
12597 | crtc_state = | |
12598 | drm_atomic_get_crtc_state(state, crtc); | |
12599 | if (IS_ERR(crtc_state)) | |
12600 | return PTR_ERR(crtc_state); | |
12601 | } | |
12602 | ||
12603 | ret = drm_atomic_set_crtc_for_connector(connector_state, | |
12604 | set->crtc); | |
12605 | if (ret) | |
12606 | return ret; | |
12607 | } | |
50f56119 DV |
12608 | |
12609 | /* Make sure the new CRTC will work with the encoder */ | |
d5432a9d ACO |
12610 | if (!drm_encoder_crtc_ok(connector_state->best_encoder, |
12611 | connector_state->crtc)) { | |
5e2b584e | 12612 | return -EINVAL; |
50f56119 | 12613 | } |
944b0c76 | 12614 | |
9a935856 DV |
12615 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
12616 | connector->base.base.id, | |
c23cc417 | 12617 | connector->base.name, |
d5432a9d | 12618 | connector_state->crtc->base.id); |
944b0c76 | 12619 | |
d5432a9d ACO |
12620 | if (connector_state->best_encoder != &connector->encoder->base) |
12621 | connector->encoder = | |
12622 | to_intel_encoder(connector_state->best_encoder); | |
0e32b39c | 12623 | } |
7668851f | 12624 | |
d5432a9d ACO |
12625 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12626 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12627 | if (ret) | |
12628 | return ret; | |
4be07317 | 12629 | |
d5432a9d | 12630 | crtc_state->enable = drm_atomic_connectors_for_crtc(state, crtc); |
7668851f VS |
12631 | } |
12632 | ||
8c7b5ccb ACO |
12633 | ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode, |
12634 | set->fb, set->x, set->y); | |
12635 | if (ret) | |
12636 | return ret; | |
12637 | ||
12638 | crtc_state = drm_atomic_get_crtc_state(state, set->crtc); | |
12639 | if (IS_ERR(crtc_state)) | |
12640 | return PTR_ERR(crtc_state); | |
12641 | ||
12642 | if (set->mode) | |
12643 | drm_mode_copy(&crtc_state->mode, set->mode); | |
12644 | ||
12645 | if (set->num_connectors) | |
12646 | crtc_state->active = true; | |
12647 | ||
2e431051 DV |
12648 | return 0; |
12649 | } | |
12650 | ||
bb546623 ACO |
12651 | static bool primary_plane_visible(struct drm_crtc *crtc) |
12652 | { | |
12653 | struct intel_plane_state *plane_state = | |
12654 | to_intel_plane_state(crtc->primary->state); | |
12655 | ||
12656 | return plane_state->visible; | |
12657 | } | |
12658 | ||
2e431051 DV |
12659 | static int intel_crtc_set_config(struct drm_mode_set *set) |
12660 | { | |
12661 | struct drm_device *dev; | |
83a57153 | 12662 | struct drm_atomic_state *state = NULL; |
5cec258b | 12663 | struct intel_crtc_state *pipe_config; |
bb546623 | 12664 | bool primary_plane_was_visible; |
2e431051 | 12665 | int ret; |
2e431051 | 12666 | |
8d3e375e DV |
12667 | BUG_ON(!set); |
12668 | BUG_ON(!set->crtc); | |
12669 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 12670 | |
7e53f3a4 DV |
12671 | /* Enforce sane interface api - has been abused by the fb helper. */ |
12672 | BUG_ON(!set->mode && set->fb); | |
12673 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 12674 | |
2e431051 DV |
12675 | if (set->fb) { |
12676 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
12677 | set->crtc->base.id, set->fb->base.id, | |
12678 | (int)set->num_connectors, set->x, set->y); | |
12679 | } else { | |
12680 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
12681 | } |
12682 | ||
12683 | dev = set->crtc->dev; | |
12684 | ||
83a57153 | 12685 | state = drm_atomic_state_alloc(dev); |
7cbf41d6 ACO |
12686 | if (!state) |
12687 | return -ENOMEM; | |
83a57153 ACO |
12688 | |
12689 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12690 | ||
462a425a | 12691 | ret = intel_modeset_stage_output_state(dev, set, state); |
2e431051 | 12692 | if (ret) |
7cbf41d6 | 12693 | goto out; |
2e431051 | 12694 | |
8c7b5ccb | 12695 | pipe_config = intel_modeset_compute_config(set->crtc, state); |
20664591 | 12696 | if (IS_ERR(pipe_config)) { |
6ac0483b | 12697 | ret = PTR_ERR(pipe_config); |
7cbf41d6 | 12698 | goto out; |
20664591 | 12699 | } |
50f52756 | 12700 | |
1f9954d0 JB |
12701 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
12702 | ||
bb546623 ACO |
12703 | primary_plane_was_visible = primary_plane_visible(set->crtc); |
12704 | ||
8c7b5ccb | 12705 | ret = intel_set_mode_with_config(set->crtc, pipe_config); |
bb546623 ACO |
12706 | |
12707 | if (ret == 0 && | |
12708 | pipe_config->base.enable && | |
12709 | pipe_config->base.planes_changed && | |
12710 | !needs_modeset(&pipe_config->base)) { | |
3b150f08 | 12711 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
3b150f08 MR |
12712 | |
12713 | /* | |
12714 | * We need to make sure the primary plane is re-enabled if it | |
12715 | * has previously been turned off. | |
12716 | */ | |
bb546623 ACO |
12717 | if (ret == 0 && !primary_plane_was_visible && |
12718 | primary_plane_visible(set->crtc)) { | |
3b150f08 | 12719 | WARN_ON(!intel_crtc->active); |
87d4300a | 12720 | intel_post_enable_primary(set->crtc); |
3b150f08 MR |
12721 | } |
12722 | ||
7ca51a3a JB |
12723 | /* |
12724 | * In the fastboot case this may be our only check of the | |
12725 | * state after boot. It would be better to only do it on | |
12726 | * the first update, but we don't have a nice way of doing that | |
12727 | * (and really, set_config isn't used much for high freq page | |
12728 | * flipping, so increasing its cost here shouldn't be a big | |
12729 | * deal). | |
12730 | */ | |
d330a953 | 12731 | if (i915.fastboot && ret == 0) |
7ca51a3a | 12732 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
12733 | } |
12734 | ||
2d05eae1 | 12735 | if (ret) { |
bf67dfeb DV |
12736 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
12737 | set->crtc->base.id, ret); | |
2d05eae1 | 12738 | } |
50f56119 | 12739 | |
7cbf41d6 | 12740 | out: |
2bfb4627 ACO |
12741 | if (ret) |
12742 | drm_atomic_state_free(state); | |
50f56119 DV |
12743 | return ret; |
12744 | } | |
f6e5b160 CW |
12745 | |
12746 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 12747 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 12748 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
12749 | .destroy = intel_crtc_destroy, |
12750 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
12751 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12752 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
12753 | }; |
12754 | ||
5358901f DV |
12755 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
12756 | struct intel_shared_dpll *pll, | |
12757 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 12758 | { |
5358901f | 12759 | uint32_t val; |
ee7b9f93 | 12760 | |
f458ebbc | 12761 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
12762 | return false; |
12763 | ||
5358901f | 12764 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
12765 | hw_state->dpll = val; |
12766 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
12767 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
12768 | |
12769 | return val & DPLL_VCO_ENABLE; | |
12770 | } | |
12771 | ||
15bdd4cf DV |
12772 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
12773 | struct intel_shared_dpll *pll) | |
12774 | { | |
3e369b76 ACO |
12775 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
12776 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
12777 | } |
12778 | ||
e7b903d2 DV |
12779 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
12780 | struct intel_shared_dpll *pll) | |
12781 | { | |
e7b903d2 | 12782 | /* PCH refclock must be enabled first */ |
89eff4be | 12783 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 12784 | |
3e369b76 | 12785 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
12786 | |
12787 | /* Wait for the clocks to stabilize. */ | |
12788 | POSTING_READ(PCH_DPLL(pll->id)); | |
12789 | udelay(150); | |
12790 | ||
12791 | /* The pixel multiplier can only be updated once the | |
12792 | * DPLL is enabled and the clocks are stable. | |
12793 | * | |
12794 | * So write it again. | |
12795 | */ | |
3e369b76 | 12796 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 12797 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
12798 | udelay(200); |
12799 | } | |
12800 | ||
12801 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
12802 | struct intel_shared_dpll *pll) | |
12803 | { | |
12804 | struct drm_device *dev = dev_priv->dev; | |
12805 | struct intel_crtc *crtc; | |
e7b903d2 DV |
12806 | |
12807 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 12808 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
12809 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
12810 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
12811 | } |
12812 | ||
15bdd4cf DV |
12813 | I915_WRITE(PCH_DPLL(pll->id), 0); |
12814 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
12815 | udelay(200); |
12816 | } | |
12817 | ||
46edb027 DV |
12818 | static char *ibx_pch_dpll_names[] = { |
12819 | "PCH DPLL A", | |
12820 | "PCH DPLL B", | |
12821 | }; | |
12822 | ||
7c74ade1 | 12823 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 12824 | { |
e7b903d2 | 12825 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
12826 | int i; |
12827 | ||
7c74ade1 | 12828 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 12829 | |
e72f9fbf | 12830 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
12831 | dev_priv->shared_dplls[i].id = i; |
12832 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 12833 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
12834 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
12835 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
12836 | dev_priv->shared_dplls[i].get_hw_state = |
12837 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
12838 | } |
12839 | } | |
12840 | ||
7c74ade1 DV |
12841 | static void intel_shared_dpll_init(struct drm_device *dev) |
12842 | { | |
e7b903d2 | 12843 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 12844 | |
9cd86933 DV |
12845 | if (HAS_DDI(dev)) |
12846 | intel_ddi_pll_init(dev); | |
12847 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
12848 | ibx_pch_dpll_init(dev); |
12849 | else | |
12850 | dev_priv->num_shared_dpll = 0; | |
12851 | ||
12852 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
12853 | } |
12854 | ||
1fc0a8f7 TU |
12855 | /** |
12856 | * intel_wm_need_update - Check whether watermarks need updating | |
12857 | * @plane: drm plane | |
12858 | * @state: new plane state | |
12859 | * | |
12860 | * Check current plane state versus the new one to determine whether | |
12861 | * watermarks need to be recalculated. | |
12862 | * | |
12863 | * Returns true or false. | |
12864 | */ | |
12865 | bool intel_wm_need_update(struct drm_plane *plane, | |
12866 | struct drm_plane_state *state) | |
12867 | { | |
12868 | /* Update watermarks on tiling changes. */ | |
12869 | if (!plane->state->fb || !state->fb || | |
12870 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
12871 | plane->state->rotation != state->rotation) | |
12872 | return true; | |
12873 | ||
12874 | return false; | |
12875 | } | |
12876 | ||
6beb8c23 MR |
12877 | /** |
12878 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12879 | * @plane: drm plane to prepare for | |
12880 | * @fb: framebuffer to prepare for presentation | |
12881 | * | |
12882 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12883 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12884 | * bits. Some older platforms need special physical address handling for | |
12885 | * cursor planes. | |
12886 | * | |
12887 | * Returns 0 on success, negative error code on failure. | |
12888 | */ | |
12889 | int | |
12890 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12891 | struct drm_framebuffer *fb, |
12892 | const struct drm_plane_state *new_state) | |
465c120c MR |
12893 | { |
12894 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
12895 | struct intel_plane *intel_plane = to_intel_plane(plane); |
12896 | enum pipe pipe = intel_plane->pipe; | |
12897 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12898 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
12899 | unsigned frontbuffer_bits = 0; | |
12900 | int ret = 0; | |
465c120c | 12901 | |
ea2c67bb | 12902 | if (!obj) |
465c120c MR |
12903 | return 0; |
12904 | ||
6beb8c23 MR |
12905 | switch (plane->type) { |
12906 | case DRM_PLANE_TYPE_PRIMARY: | |
12907 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
12908 | break; | |
12909 | case DRM_PLANE_TYPE_CURSOR: | |
12910 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
12911 | break; | |
12912 | case DRM_PLANE_TYPE_OVERLAY: | |
12913 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
12914 | break; | |
12915 | } | |
465c120c | 12916 | |
6beb8c23 | 12917 | mutex_lock(&dev->struct_mutex); |
465c120c | 12918 | |
6beb8c23 MR |
12919 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12920 | INTEL_INFO(dev)->cursor_needs_physical) { | |
12921 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
12922 | ret = i915_gem_object_attach_phys(obj, align); | |
12923 | if (ret) | |
12924 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
12925 | } else { | |
82bc3b2d | 12926 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 12927 | } |
465c120c | 12928 | |
6beb8c23 MR |
12929 | if (ret == 0) |
12930 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 12931 | |
4c34574f | 12932 | mutex_unlock(&dev->struct_mutex); |
465c120c | 12933 | |
6beb8c23 MR |
12934 | return ret; |
12935 | } | |
12936 | ||
38f3ce3a MR |
12937 | /** |
12938 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12939 | * @plane: drm plane to clean up for | |
12940 | * @fb: old framebuffer that was on plane | |
12941 | * | |
12942 | * Cleans up a framebuffer that has just been removed from a plane. | |
12943 | */ | |
12944 | void | |
12945 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12946 | struct drm_framebuffer *fb, |
12947 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
12948 | { |
12949 | struct drm_device *dev = plane->dev; | |
12950 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12951 | ||
12952 | if (WARN_ON(!obj)) | |
12953 | return; | |
12954 | ||
12955 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
12956 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
12957 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 12958 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
12959 | mutex_unlock(&dev->struct_mutex); |
12960 | } | |
465c120c MR |
12961 | } |
12962 | ||
6156a456 CK |
12963 | int |
12964 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
12965 | { | |
12966 | int max_scale; | |
12967 | struct drm_device *dev; | |
12968 | struct drm_i915_private *dev_priv; | |
12969 | int crtc_clock, cdclk; | |
12970 | ||
12971 | if (!intel_crtc || !crtc_state) | |
12972 | return DRM_PLANE_HELPER_NO_SCALING; | |
12973 | ||
12974 | dev = intel_crtc->base.dev; | |
12975 | dev_priv = dev->dev_private; | |
12976 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
12977 | cdclk = dev_priv->display.get_display_clock_speed(dev); | |
12978 | ||
12979 | if (!crtc_clock || !cdclk) | |
12980 | return DRM_PLANE_HELPER_NO_SCALING; | |
12981 | ||
12982 | /* | |
12983 | * skl max scale is lower of: | |
12984 | * close to 3 but not 3, -1 is for that purpose | |
12985 | * or | |
12986 | * cdclk/crtc_clock | |
12987 | */ | |
12988 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
12989 | ||
12990 | return max_scale; | |
12991 | } | |
12992 | ||
465c120c | 12993 | static int |
3c692a41 GP |
12994 | intel_check_primary_plane(struct drm_plane *plane, |
12995 | struct intel_plane_state *state) | |
12996 | { | |
32b7eeec MR |
12997 | struct drm_device *dev = plane->dev; |
12998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 12999 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13000 | struct intel_crtc *intel_crtc; |
6156a456 | 13001 | struct intel_crtc_state *crtc_state; |
2b875c22 | 13002 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
13003 | struct drm_rect *dest = &state->dst; |
13004 | struct drm_rect *src = &state->src; | |
13005 | const struct drm_rect *clip = &state->clip; | |
d8106366 | 13006 | bool can_position = false; |
6156a456 CK |
13007 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13008 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
465c120c MR |
13009 | int ret; |
13010 | ||
ea2c67bb MR |
13011 | crtc = crtc ? crtc : plane->crtc; |
13012 | intel_crtc = to_intel_crtc(crtc); | |
6156a456 CK |
13013 | crtc_state = state->base.state ? |
13014 | intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; | |
ea2c67bb | 13015 | |
6156a456 CK |
13016 | if (INTEL_INFO(dev)->gen >= 9) { |
13017 | min_scale = 1; | |
13018 | max_scale = skl_max_scale(intel_crtc, crtc_state); | |
d8106366 | 13019 | can_position = true; |
6156a456 | 13020 | } |
d8106366 | 13021 | |
c59cb179 MR |
13022 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
13023 | src, dest, clip, | |
6156a456 CK |
13024 | min_scale, |
13025 | max_scale, | |
d8106366 SJ |
13026 | can_position, true, |
13027 | &state->visible); | |
c59cb179 MR |
13028 | if (ret) |
13029 | return ret; | |
465c120c | 13030 | |
32b7eeec | 13031 | if (intel_crtc->active) { |
b70709a6 ML |
13032 | struct intel_plane_state *old_state = |
13033 | to_intel_plane_state(plane->state); | |
13034 | ||
32b7eeec MR |
13035 | intel_crtc->atomic.wait_for_flips = true; |
13036 | ||
13037 | /* | |
13038 | * FBC does not work on some platforms for rotated | |
13039 | * planes, so disable it when rotation is not 0 and | |
13040 | * update it when rotation is set back to 0. | |
13041 | * | |
13042 | * FIXME: This is redundant with the fbc update done in | |
13043 | * the primary plane enable function except that that | |
13044 | * one is done too late. We eventually need to unify | |
13045 | * this. | |
13046 | */ | |
b70709a6 | 13047 | if (state->visible && |
32b7eeec | 13048 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
e35fef21 | 13049 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 13050 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
13051 | intel_crtc->atomic.disable_fbc = true; |
13052 | } | |
13053 | ||
b70709a6 | 13054 | if (state->visible && !old_state->visible) { |
32b7eeec MR |
13055 | /* |
13056 | * BDW signals flip done immediately if the plane | |
13057 | * is disabled, even if the plane enable is already | |
13058 | * armed to occur at the next vblank :( | |
13059 | */ | |
b70709a6 | 13060 | if (IS_BROADWELL(dev)) |
32b7eeec MR |
13061 | intel_crtc->atomic.wait_vblank = true; |
13062 | } | |
13063 | ||
13064 | intel_crtc->atomic.fb_bits |= | |
13065 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
13066 | ||
13067 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 13068 | |
1fc0a8f7 | 13069 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 13070 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
13071 | } |
13072 | ||
6156a456 CK |
13073 | if (INTEL_INFO(dev)->gen >= 9) { |
13074 | ret = skl_update_scaler_users(intel_crtc, crtc_state, | |
13075 | to_intel_plane(plane), state, 0); | |
13076 | if (ret) | |
13077 | return ret; | |
13078 | } | |
13079 | ||
14af293f GP |
13080 | return 0; |
13081 | } | |
13082 | ||
13083 | static void | |
13084 | intel_commit_primary_plane(struct drm_plane *plane, | |
13085 | struct intel_plane_state *state) | |
13086 | { | |
2b875c22 MR |
13087 | struct drm_crtc *crtc = state->base.crtc; |
13088 | struct drm_framebuffer *fb = state->base.fb; | |
13089 | struct drm_device *dev = plane->dev; | |
14af293f | 13090 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13091 | struct intel_crtc *intel_crtc; |
14af293f GP |
13092 | struct drm_rect *src = &state->src; |
13093 | ||
ea2c67bb MR |
13094 | crtc = crtc ? crtc : plane->crtc; |
13095 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13096 | |
13097 | plane->fb = fb; | |
9dc806fc MR |
13098 | crtc->x = src->x1 >> 16; |
13099 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13100 | |
ccc759dc | 13101 | if (intel_crtc->active) { |
27321ae8 | 13102 | if (state->visible) |
ccc759dc GP |
13103 | /* FIXME: kill this fastboot hack */ |
13104 | intel_update_pipe_size(intel_crtc); | |
465c120c | 13105 | |
27321ae8 ML |
13106 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
13107 | crtc->x, crtc->y); | |
ccc759dc | 13108 | } |
465c120c MR |
13109 | } |
13110 | ||
a8ad0d8e ML |
13111 | static void |
13112 | intel_disable_primary_plane(struct drm_plane *plane, | |
13113 | struct drm_crtc *crtc, | |
13114 | bool force) | |
13115 | { | |
13116 | struct drm_device *dev = plane->dev; | |
13117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13118 | ||
a8ad0d8e ML |
13119 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13120 | } | |
13121 | ||
32b7eeec | 13122 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 13123 | { |
32b7eeec | 13124 | struct drm_device *dev = crtc->dev; |
140fd38d | 13125 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 13126 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
13127 | struct intel_plane *intel_plane; |
13128 | struct drm_plane *p; | |
13129 | unsigned fb_bits = 0; | |
13130 | ||
13131 | /* Track fb's for any planes being disabled */ | |
13132 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
13133 | intel_plane = to_intel_plane(p); | |
13134 | ||
13135 | if (intel_crtc->atomic.disabled_planes & | |
13136 | (1 << drm_plane_index(p))) { | |
13137 | switch (p->type) { | |
13138 | case DRM_PLANE_TYPE_PRIMARY: | |
13139 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
13140 | break; | |
13141 | case DRM_PLANE_TYPE_CURSOR: | |
13142 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
13143 | break; | |
13144 | case DRM_PLANE_TYPE_OVERLAY: | |
13145 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
13146 | break; | |
13147 | } | |
3c692a41 | 13148 | |
ea2c67bb MR |
13149 | mutex_lock(&dev->struct_mutex); |
13150 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
13151 | mutex_unlock(&dev->struct_mutex); | |
13152 | } | |
13153 | } | |
3c692a41 | 13154 | |
32b7eeec MR |
13155 | if (intel_crtc->atomic.wait_for_flips) |
13156 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 13157 | |
32b7eeec MR |
13158 | if (intel_crtc->atomic.disable_fbc) |
13159 | intel_fbc_disable(dev); | |
3c692a41 | 13160 | |
32b7eeec MR |
13161 | if (intel_crtc->atomic.pre_disable_primary) |
13162 | intel_pre_disable_primary(crtc); | |
3c692a41 | 13163 | |
32b7eeec MR |
13164 | if (intel_crtc->atomic.update_wm) |
13165 | intel_update_watermarks(crtc); | |
3c692a41 | 13166 | |
32b7eeec | 13167 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 13168 | |
c34c9ee4 MR |
13169 | /* Perform vblank evasion around commit operation */ |
13170 | if (intel_crtc->active) | |
13171 | intel_crtc->atomic.evade = | |
13172 | intel_pipe_update_start(intel_crtc, | |
13173 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
13174 | } |
13175 | ||
13176 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
13177 | { | |
13178 | struct drm_device *dev = crtc->dev; | |
13179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13181 | struct drm_plane *p; | |
13182 | ||
c34c9ee4 MR |
13183 | if (intel_crtc->atomic.evade) |
13184 | intel_pipe_update_end(intel_crtc, | |
13185 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 13186 | |
140fd38d | 13187 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 13188 | |
32b7eeec MR |
13189 | if (intel_crtc->atomic.wait_vblank) |
13190 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
13191 | ||
13192 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
13193 | ||
13194 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 13195 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 13196 | intel_fbc_update(dev); |
ccc759dc | 13197 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 13198 | } |
3c692a41 | 13199 | |
32b7eeec MR |
13200 | if (intel_crtc->atomic.post_enable_primary) |
13201 | intel_post_enable_primary(crtc); | |
3c692a41 | 13202 | |
32b7eeec MR |
13203 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
13204 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
13205 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
13206 | false, false); | |
13207 | ||
13208 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
13209 | } |
13210 | ||
cf4c7c12 | 13211 | /** |
4a3b8769 MR |
13212 | * intel_plane_destroy - destroy a plane |
13213 | * @plane: plane to destroy | |
cf4c7c12 | 13214 | * |
4a3b8769 MR |
13215 | * Common destruction function for all types of planes (primary, cursor, |
13216 | * sprite). | |
cf4c7c12 | 13217 | */ |
4a3b8769 | 13218 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13219 | { |
13220 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13221 | drm_plane_cleanup(plane); | |
13222 | kfree(intel_plane); | |
13223 | } | |
13224 | ||
65a3fea0 | 13225 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13226 | .update_plane = drm_atomic_helper_update_plane, |
13227 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13228 | .destroy = intel_plane_destroy, |
c196e1d6 | 13229 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13230 | .atomic_get_property = intel_plane_atomic_get_property, |
13231 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13232 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13233 | .atomic_destroy_state = intel_plane_destroy_state, | |
13234 | ||
465c120c MR |
13235 | }; |
13236 | ||
13237 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13238 | int pipe) | |
13239 | { | |
13240 | struct intel_plane *primary; | |
8e7d688b | 13241 | struct intel_plane_state *state; |
465c120c MR |
13242 | const uint32_t *intel_primary_formats; |
13243 | int num_formats; | |
13244 | ||
13245 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13246 | if (primary == NULL) | |
13247 | return NULL; | |
13248 | ||
8e7d688b MR |
13249 | state = intel_create_plane_state(&primary->base); |
13250 | if (!state) { | |
ea2c67bb MR |
13251 | kfree(primary); |
13252 | return NULL; | |
13253 | } | |
8e7d688b | 13254 | primary->base.state = &state->base; |
ea2c67bb | 13255 | |
465c120c MR |
13256 | primary->can_scale = false; |
13257 | primary->max_downscale = 1; | |
6156a456 CK |
13258 | if (INTEL_INFO(dev)->gen >= 9) { |
13259 | primary->can_scale = true; | |
13260 | } | |
549e2bfb | 13261 | state->scaler_id = -1; |
465c120c MR |
13262 | primary->pipe = pipe; |
13263 | primary->plane = pipe; | |
c59cb179 MR |
13264 | primary->check_plane = intel_check_primary_plane; |
13265 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13266 | primary->disable_plane = intel_disable_primary_plane; |
08e221fb | 13267 | primary->ckey.flags = I915_SET_COLORKEY_NONE; |
465c120c MR |
13268 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13269 | primary->plane = !pipe; | |
13270 | ||
13271 | if (INTEL_INFO(dev)->gen <= 3) { | |
13272 | intel_primary_formats = intel_primary_formats_gen2; | |
13273 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
13274 | } else { | |
13275 | intel_primary_formats = intel_primary_formats_gen4; | |
13276 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
13277 | } | |
13278 | ||
13279 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13280 | &intel_plane_funcs, |
465c120c MR |
13281 | intel_primary_formats, num_formats, |
13282 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13283 | |
3b7a5119 SJ |
13284 | if (INTEL_INFO(dev)->gen >= 4) |
13285 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13286 | |
ea2c67bb MR |
13287 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13288 | ||
465c120c MR |
13289 | return &primary->base; |
13290 | } | |
13291 | ||
3b7a5119 SJ |
13292 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13293 | { | |
13294 | if (!dev->mode_config.rotation_property) { | |
13295 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13296 | BIT(DRM_ROTATE_180); | |
13297 | ||
13298 | if (INTEL_INFO(dev)->gen >= 9) | |
13299 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13300 | ||
13301 | dev->mode_config.rotation_property = | |
13302 | drm_mode_create_rotation_property(dev, flags); | |
13303 | } | |
13304 | if (dev->mode_config.rotation_property) | |
13305 | drm_object_attach_property(&plane->base.base, | |
13306 | dev->mode_config.rotation_property, | |
13307 | plane->base.state->rotation); | |
13308 | } | |
13309 | ||
3d7d6510 | 13310 | static int |
852e787c GP |
13311 | intel_check_cursor_plane(struct drm_plane *plane, |
13312 | struct intel_plane_state *state) | |
3d7d6510 | 13313 | { |
2b875c22 | 13314 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13315 | struct drm_device *dev = plane->dev; |
2b875c22 | 13316 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
13317 | struct drm_rect *dest = &state->dst; |
13318 | struct drm_rect *src = &state->src; | |
13319 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 13320 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 13321 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
13322 | unsigned stride; |
13323 | int ret; | |
3d7d6510 | 13324 | |
ea2c67bb MR |
13325 | crtc = crtc ? crtc : plane->crtc; |
13326 | intel_crtc = to_intel_crtc(crtc); | |
13327 | ||
757f9a3e | 13328 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 13329 | src, dest, clip, |
3d7d6510 MR |
13330 | DRM_PLANE_HELPER_NO_SCALING, |
13331 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13332 | true, true, &state->visible); |
757f9a3e GP |
13333 | if (ret) |
13334 | return ret; | |
13335 | ||
13336 | ||
13337 | /* if we want to turn off the cursor ignore width and height */ | |
13338 | if (!obj) | |
32b7eeec | 13339 | goto finish; |
757f9a3e | 13340 | |
757f9a3e | 13341 | /* Check for which cursor types we support */ |
ea2c67bb MR |
13342 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
13343 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
13344 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13345 | return -EINVAL; |
13346 | } | |
13347 | ||
ea2c67bb MR |
13348 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13349 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13350 | DRM_DEBUG_KMS("buffer is too small\n"); |
13351 | return -ENOMEM; | |
13352 | } | |
13353 | ||
3a656b54 | 13354 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
13355 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
13356 | ret = -EINVAL; | |
13357 | } | |
757f9a3e | 13358 | |
32b7eeec MR |
13359 | finish: |
13360 | if (intel_crtc->active) { | |
3749f463 | 13361 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
13362 | intel_crtc->atomic.update_wm = true; |
13363 | ||
13364 | intel_crtc->atomic.fb_bits |= | |
13365 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
13366 | } | |
13367 | ||
757f9a3e | 13368 | return ret; |
852e787c | 13369 | } |
3d7d6510 | 13370 | |
a8ad0d8e ML |
13371 | static void |
13372 | intel_disable_cursor_plane(struct drm_plane *plane, | |
13373 | struct drm_crtc *crtc, | |
13374 | bool force) | |
13375 | { | |
13376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13377 | ||
13378 | if (!force) { | |
13379 | plane->fb = NULL; | |
13380 | intel_crtc->cursor_bo = NULL; | |
13381 | intel_crtc->cursor_addr = 0; | |
13382 | } | |
13383 | ||
13384 | intel_crtc_update_cursor(crtc, false); | |
13385 | } | |
13386 | ||
f4a2cf29 | 13387 | static void |
852e787c GP |
13388 | intel_commit_cursor_plane(struct drm_plane *plane, |
13389 | struct intel_plane_state *state) | |
13390 | { | |
2b875c22 | 13391 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13392 | struct drm_device *dev = plane->dev; |
13393 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13394 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13395 | uint32_t addr; |
852e787c | 13396 | |
ea2c67bb MR |
13397 | crtc = crtc ? crtc : plane->crtc; |
13398 | intel_crtc = to_intel_crtc(crtc); | |
13399 | ||
2b875c22 | 13400 | plane->fb = state->base.fb; |
ea2c67bb MR |
13401 | crtc->cursor_x = state->base.crtc_x; |
13402 | crtc->cursor_y = state->base.crtc_y; | |
13403 | ||
a912f12f GP |
13404 | if (intel_crtc->cursor_bo == obj) |
13405 | goto update; | |
4ed91096 | 13406 | |
f4a2cf29 | 13407 | if (!obj) |
a912f12f | 13408 | addr = 0; |
f4a2cf29 | 13409 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13410 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13411 | else |
a912f12f | 13412 | addr = obj->phys_handle->busaddr; |
852e787c | 13413 | |
a912f12f GP |
13414 | intel_crtc->cursor_addr = addr; |
13415 | intel_crtc->cursor_bo = obj; | |
13416 | update: | |
852e787c | 13417 | |
32b7eeec | 13418 | if (intel_crtc->active) |
a912f12f | 13419 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13420 | } |
13421 | ||
3d7d6510 MR |
13422 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13423 | int pipe) | |
13424 | { | |
13425 | struct intel_plane *cursor; | |
8e7d688b | 13426 | struct intel_plane_state *state; |
3d7d6510 MR |
13427 | |
13428 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13429 | if (cursor == NULL) | |
13430 | return NULL; | |
13431 | ||
8e7d688b MR |
13432 | state = intel_create_plane_state(&cursor->base); |
13433 | if (!state) { | |
ea2c67bb MR |
13434 | kfree(cursor); |
13435 | return NULL; | |
13436 | } | |
8e7d688b | 13437 | cursor->base.state = &state->base; |
ea2c67bb | 13438 | |
3d7d6510 MR |
13439 | cursor->can_scale = false; |
13440 | cursor->max_downscale = 1; | |
13441 | cursor->pipe = pipe; | |
13442 | cursor->plane = pipe; | |
549e2bfb | 13443 | state->scaler_id = -1; |
c59cb179 MR |
13444 | cursor->check_plane = intel_check_cursor_plane; |
13445 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 13446 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
13447 | |
13448 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13449 | &intel_plane_funcs, |
3d7d6510 MR |
13450 | intel_cursor_formats, |
13451 | ARRAY_SIZE(intel_cursor_formats), | |
13452 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13453 | |
13454 | if (INTEL_INFO(dev)->gen >= 4) { | |
13455 | if (!dev->mode_config.rotation_property) | |
13456 | dev->mode_config.rotation_property = | |
13457 | drm_mode_create_rotation_property(dev, | |
13458 | BIT(DRM_ROTATE_0) | | |
13459 | BIT(DRM_ROTATE_180)); | |
13460 | if (dev->mode_config.rotation_property) | |
13461 | drm_object_attach_property(&cursor->base.base, | |
13462 | dev->mode_config.rotation_property, | |
8e7d688b | 13463 | state->base.rotation); |
4398ad45 VS |
13464 | } |
13465 | ||
ea2c67bb MR |
13466 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13467 | ||
3d7d6510 MR |
13468 | return &cursor->base; |
13469 | } | |
13470 | ||
549e2bfb CK |
13471 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13472 | struct intel_crtc_state *crtc_state) | |
13473 | { | |
13474 | int i; | |
13475 | struct intel_scaler *intel_scaler; | |
13476 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13477 | ||
13478 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13479 | intel_scaler = &scaler_state->scalers[i]; | |
13480 | intel_scaler->in_use = 0; | |
13481 | intel_scaler->id = i; | |
13482 | ||
13483 | intel_scaler->mode = PS_SCALER_MODE_DYN; | |
13484 | } | |
13485 | ||
13486 | scaler_state->scaler_id = -1; | |
13487 | } | |
13488 | ||
b358d0a6 | 13489 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13490 | { |
fbee40df | 13491 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13492 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13493 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13494 | struct drm_plane *primary = NULL; |
13495 | struct drm_plane *cursor = NULL; | |
465c120c | 13496 | int i, ret; |
79e53945 | 13497 | |
955382f3 | 13498 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13499 | if (intel_crtc == NULL) |
13500 | return; | |
13501 | ||
f5de6e07 ACO |
13502 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13503 | if (!crtc_state) | |
13504 | goto fail; | |
13505 | intel_crtc_set_state(intel_crtc, crtc_state); | |
07878248 | 13506 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13507 | |
549e2bfb CK |
13508 | /* initialize shared scalers */ |
13509 | if (INTEL_INFO(dev)->gen >= 9) { | |
13510 | if (pipe == PIPE_C) | |
13511 | intel_crtc->num_scalers = 1; | |
13512 | else | |
13513 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13514 | ||
13515 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13516 | } | |
13517 | ||
465c120c | 13518 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13519 | if (!primary) |
13520 | goto fail; | |
13521 | ||
13522 | cursor = intel_cursor_plane_create(dev, pipe); | |
13523 | if (!cursor) | |
13524 | goto fail; | |
13525 | ||
465c120c | 13526 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13527 | cursor, &intel_crtc_funcs); |
13528 | if (ret) | |
13529 | goto fail; | |
79e53945 JB |
13530 | |
13531 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13532 | for (i = 0; i < 256; i++) { |
13533 | intel_crtc->lut_r[i] = i; | |
13534 | intel_crtc->lut_g[i] = i; | |
13535 | intel_crtc->lut_b[i] = i; | |
13536 | } | |
13537 | ||
1f1c2e24 VS |
13538 | /* |
13539 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13540 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13541 | */ |
80824003 JB |
13542 | intel_crtc->pipe = pipe; |
13543 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13544 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13545 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13546 | intel_crtc->plane = !pipe; |
80824003 JB |
13547 | } |
13548 | ||
4b0e333e CW |
13549 | intel_crtc->cursor_base = ~0; |
13550 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13551 | intel_crtc->cursor_size = ~0; |
8d7849db | 13552 | |
22fd0fab JB |
13553 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13554 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13555 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13556 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13557 | ||
9362c7c5 ACO |
13558 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
13559 | ||
79e53945 | 13560 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13561 | |
13562 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13563 | return; |
13564 | ||
13565 | fail: | |
13566 | if (primary) | |
13567 | drm_plane_cleanup(primary); | |
13568 | if (cursor) | |
13569 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13570 | kfree(crtc_state); |
3d7d6510 | 13571 | kfree(intel_crtc); |
79e53945 JB |
13572 | } |
13573 | ||
752aa88a JB |
13574 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13575 | { | |
13576 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13577 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13578 | |
51fd371b | 13579 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13580 | |
d3babd3f | 13581 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13582 | return INVALID_PIPE; |
13583 | ||
13584 | return to_intel_crtc(encoder->crtc)->pipe; | |
13585 | } | |
13586 | ||
08d7b3d1 | 13587 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13588 | struct drm_file *file) |
08d7b3d1 | 13589 | { |
08d7b3d1 | 13590 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13591 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13592 | struct intel_crtc *crtc; |
08d7b3d1 | 13593 | |
7707e653 | 13594 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13595 | |
7707e653 | 13596 | if (!drmmode_crtc) { |
08d7b3d1 | 13597 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13598 | return -ENOENT; |
08d7b3d1 CW |
13599 | } |
13600 | ||
7707e653 | 13601 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13602 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13603 | |
c05422d5 | 13604 | return 0; |
08d7b3d1 CW |
13605 | } |
13606 | ||
66a9278e | 13607 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13608 | { |
66a9278e DV |
13609 | struct drm_device *dev = encoder->base.dev; |
13610 | struct intel_encoder *source_encoder; | |
79e53945 | 13611 | int index_mask = 0; |
79e53945 JB |
13612 | int entry = 0; |
13613 | ||
b2784e15 | 13614 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13615 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13616 | index_mask |= (1 << entry); |
13617 | ||
79e53945 JB |
13618 | entry++; |
13619 | } | |
4ef69c7a | 13620 | |
79e53945 JB |
13621 | return index_mask; |
13622 | } | |
13623 | ||
4d302442 CW |
13624 | static bool has_edp_a(struct drm_device *dev) |
13625 | { | |
13626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13627 | ||
13628 | if (!IS_MOBILE(dev)) | |
13629 | return false; | |
13630 | ||
13631 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13632 | return false; | |
13633 | ||
e3589908 | 13634 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13635 | return false; |
13636 | ||
13637 | return true; | |
13638 | } | |
13639 | ||
84b4e042 JB |
13640 | static bool intel_crt_present(struct drm_device *dev) |
13641 | { | |
13642 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13643 | ||
884497ed DL |
13644 | if (INTEL_INFO(dev)->gen >= 9) |
13645 | return false; | |
13646 | ||
cf404ce4 | 13647 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13648 | return false; |
13649 | ||
13650 | if (IS_CHERRYVIEW(dev)) | |
13651 | return false; | |
13652 | ||
13653 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
13654 | return false; | |
13655 | ||
13656 | return true; | |
13657 | } | |
13658 | ||
79e53945 JB |
13659 | static void intel_setup_outputs(struct drm_device *dev) |
13660 | { | |
725e30ad | 13661 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13662 | struct intel_encoder *encoder; |
cb0953d7 | 13663 | bool dpd_is_edp = false; |
79e53945 | 13664 | |
c9093354 | 13665 | intel_lvds_init(dev); |
79e53945 | 13666 | |
84b4e042 | 13667 | if (intel_crt_present(dev)) |
79935fca | 13668 | intel_crt_init(dev); |
cb0953d7 | 13669 | |
c776eb2e VK |
13670 | if (IS_BROXTON(dev)) { |
13671 | /* | |
13672 | * FIXME: Broxton doesn't support port detection via the | |
13673 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13674 | * detect the ports. | |
13675 | */ | |
13676 | intel_ddi_init(dev, PORT_A); | |
13677 | intel_ddi_init(dev, PORT_B); | |
13678 | intel_ddi_init(dev, PORT_C); | |
13679 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
13680 | int found; |
13681 | ||
de31facd JB |
13682 | /* |
13683 | * Haswell uses DDI functions to detect digital outputs. | |
13684 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13685 | * it's there. | |
13686 | */ | |
0e72a5b5 | 13687 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
13688 | /* WaIgnoreDDIAStrap: skl */ |
13689 | if (found || | |
13690 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
13691 | intel_ddi_init(dev, PORT_A); |
13692 | ||
13693 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13694 | * register */ | |
13695 | found = I915_READ(SFUSE_STRAP); | |
13696 | ||
13697 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
13698 | intel_ddi_init(dev, PORT_B); | |
13699 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
13700 | intel_ddi_init(dev, PORT_C); | |
13701 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
13702 | intel_ddi_init(dev, PORT_D); | |
13703 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 13704 | int found; |
5d8a7752 | 13705 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
13706 | |
13707 | if (has_edp_a(dev)) | |
13708 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 13709 | |
dc0fa718 | 13710 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13711 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 13712 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 13713 | if (!found) |
e2debe91 | 13714 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 13715 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 13716 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13717 | } |
13718 | ||
dc0fa718 | 13719 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 13720 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 13721 | |
dc0fa718 | 13722 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 13723 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 13724 | |
5eb08b69 | 13725 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 13726 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 13727 | |
270b3042 | 13728 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 13729 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 13730 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
13731 | /* |
13732 | * The DP_DETECTED bit is the latched state of the DDC | |
13733 | * SDA pin at boot. However since eDP doesn't require DDC | |
13734 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13735 | * eDP ports may have been muxed to an alternate function. | |
13736 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13737 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13738 | * detect eDP ports. | |
13739 | */ | |
d2182a66 VS |
13740 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
13741 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
13742 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
13743 | PORT_B); | |
e17ac6db VS |
13744 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
13745 | intel_dp_is_edp(dev, PORT_B)) | |
13746 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 13747 | |
d2182a66 VS |
13748 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
13749 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
13750 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
13751 | PORT_C); | |
e17ac6db VS |
13752 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
13753 | intel_dp_is_edp(dev, PORT_C)) | |
13754 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 13755 | |
9418c1f1 | 13756 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 13757 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
13758 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
13759 | PORT_D); | |
e17ac6db VS |
13760 | /* eDP not supported on port D, so don't check VBT */ |
13761 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
13762 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
13763 | } |
13764 | ||
3cfca973 | 13765 | intel_dsi_init(dev); |
103a196f | 13766 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 13767 | bool found = false; |
7d57382e | 13768 | |
e2debe91 | 13769 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13770 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 13771 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
13772 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
13773 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 13774 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13775 | } |
27185ae1 | 13776 | |
e7281eab | 13777 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13778 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 13779 | } |
13520b05 KH |
13780 | |
13781 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13782 | |
e2debe91 | 13783 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13784 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 13785 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 13786 | } |
27185ae1 | 13787 | |
e2debe91 | 13788 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13789 | |
b01f2c3a JB |
13790 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
13791 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 13792 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13793 | } |
e7281eab | 13794 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13795 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 13796 | } |
27185ae1 | 13797 | |
b01f2c3a | 13798 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 13799 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 13800 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 13801 | } else if (IS_GEN2(dev)) |
79e53945 JB |
13802 | intel_dvo_init(dev); |
13803 | ||
103a196f | 13804 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
13805 | intel_tv_init(dev); |
13806 | ||
0bc12bcb | 13807 | intel_psr_init(dev); |
7c8f8a70 | 13808 | |
b2784e15 | 13809 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
13810 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13811 | encoder->base.possible_clones = | |
66a9278e | 13812 | intel_encoder_clones(encoder); |
79e53945 | 13813 | } |
47356eb6 | 13814 | |
dde86e2d | 13815 | intel_init_pch_refclk(dev); |
270b3042 DV |
13816 | |
13817 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
13818 | } |
13819 | ||
13820 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13821 | { | |
60a5ca01 | 13822 | struct drm_device *dev = fb->dev; |
79e53945 | 13823 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 13824 | |
ef2d633e | 13825 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 13826 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 13827 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
13828 | drm_gem_object_unreference(&intel_fb->obj->base); |
13829 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13830 | kfree(intel_fb); |
13831 | } | |
13832 | ||
13833 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13834 | struct drm_file *file, |
79e53945 JB |
13835 | unsigned int *handle) |
13836 | { | |
13837 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13838 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13839 | |
05394f39 | 13840 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13841 | } |
13842 | ||
13843 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
13844 | .destroy = intel_user_framebuffer_destroy, | |
13845 | .create_handle = intel_user_framebuffer_create_handle, | |
13846 | }; | |
13847 | ||
b321803d DL |
13848 | static |
13849 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
13850 | uint32_t pixel_format) | |
13851 | { | |
13852 | u32 gen = INTEL_INFO(dev)->gen; | |
13853 | ||
13854 | if (gen >= 9) { | |
13855 | /* "The stride in bytes must not exceed the of the size of 8K | |
13856 | * pixels and 32K bytes." | |
13857 | */ | |
13858 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
13859 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
13860 | return 32*1024; | |
13861 | } else if (gen >= 4) { | |
13862 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13863 | return 16*1024; | |
13864 | else | |
13865 | return 32*1024; | |
13866 | } else if (gen >= 3) { | |
13867 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13868 | return 8*1024; | |
13869 | else | |
13870 | return 16*1024; | |
13871 | } else { | |
13872 | /* XXX DSPC is limited to 4k tiled */ | |
13873 | return 8*1024; | |
13874 | } | |
13875 | } | |
13876 | ||
b5ea642a DV |
13877 | static int intel_framebuffer_init(struct drm_device *dev, |
13878 | struct intel_framebuffer *intel_fb, | |
13879 | struct drm_mode_fb_cmd2 *mode_cmd, | |
13880 | struct drm_i915_gem_object *obj) | |
79e53945 | 13881 | { |
6761dd31 | 13882 | unsigned int aligned_height; |
79e53945 | 13883 | int ret; |
b321803d | 13884 | u32 pitch_limit, stride_alignment; |
79e53945 | 13885 | |
dd4916c5 DV |
13886 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
13887 | ||
2a80eada DV |
13888 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
13889 | /* Enforce that fb modifier and tiling mode match, but only for | |
13890 | * X-tiled. This is needed for FBC. */ | |
13891 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
13892 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
13893 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
13894 | return -EINVAL; | |
13895 | } | |
13896 | } else { | |
13897 | if (obj->tiling_mode == I915_TILING_X) | |
13898 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
13899 | else if (obj->tiling_mode == I915_TILING_Y) { | |
13900 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
13901 | return -EINVAL; | |
13902 | } | |
13903 | } | |
13904 | ||
9a8f0a12 TU |
13905 | /* Passed in modifier sanity checking. */ |
13906 | switch (mode_cmd->modifier[0]) { | |
13907 | case I915_FORMAT_MOD_Y_TILED: | |
13908 | case I915_FORMAT_MOD_Yf_TILED: | |
13909 | if (INTEL_INFO(dev)->gen < 9) { | |
13910 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
13911 | mode_cmd->modifier[0]); | |
13912 | return -EINVAL; | |
13913 | } | |
13914 | case DRM_FORMAT_MOD_NONE: | |
13915 | case I915_FORMAT_MOD_X_TILED: | |
13916 | break; | |
13917 | default: | |
c0f40428 JB |
13918 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
13919 | mode_cmd->modifier[0]); | |
57cd6508 | 13920 | return -EINVAL; |
c16ed4be | 13921 | } |
57cd6508 | 13922 | |
b321803d DL |
13923 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
13924 | mode_cmd->pixel_format); | |
13925 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
13926 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
13927 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 13928 | return -EINVAL; |
c16ed4be | 13929 | } |
57cd6508 | 13930 | |
b321803d DL |
13931 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
13932 | mode_cmd->pixel_format); | |
a35cdaa0 | 13933 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
13934 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
13935 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 13936 | "tiled" : "linear", |
a35cdaa0 | 13937 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 13938 | return -EINVAL; |
c16ed4be | 13939 | } |
5d7bd705 | 13940 | |
2a80eada | 13941 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
13942 | mode_cmd->pitches[0] != obj->stride) { |
13943 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
13944 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 13945 | return -EINVAL; |
c16ed4be | 13946 | } |
5d7bd705 | 13947 | |
57779d06 | 13948 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13949 | switch (mode_cmd->pixel_format) { |
57779d06 | 13950 | case DRM_FORMAT_C8: |
04b3924d VS |
13951 | case DRM_FORMAT_RGB565: |
13952 | case DRM_FORMAT_XRGB8888: | |
13953 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13954 | break; |
13955 | case DRM_FORMAT_XRGB1555: | |
13956 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 13957 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
13958 | DRM_DEBUG("unsupported pixel format: %s\n", |
13959 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13960 | return -EINVAL; |
c16ed4be | 13961 | } |
57779d06 VS |
13962 | break; |
13963 | case DRM_FORMAT_XBGR8888: | |
13964 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
13965 | case DRM_FORMAT_XRGB2101010: |
13966 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
13967 | case DRM_FORMAT_XBGR2101010: |
13968 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 13969 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
13970 | DRM_DEBUG("unsupported pixel format: %s\n", |
13971 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13972 | return -EINVAL; |
c16ed4be | 13973 | } |
b5626747 | 13974 | break; |
04b3924d VS |
13975 | case DRM_FORMAT_YUYV: |
13976 | case DRM_FORMAT_UYVY: | |
13977 | case DRM_FORMAT_YVYU: | |
13978 | case DRM_FORMAT_VYUY: | |
c16ed4be | 13979 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
13980 | DRM_DEBUG("unsupported pixel format: %s\n", |
13981 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13982 | return -EINVAL; |
c16ed4be | 13983 | } |
57cd6508 CW |
13984 | break; |
13985 | default: | |
4ee62c76 VS |
13986 | DRM_DEBUG("unsupported pixel format: %s\n", |
13987 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
13988 | return -EINVAL; |
13989 | } | |
13990 | ||
90f9a336 VS |
13991 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
13992 | if (mode_cmd->offsets[0] != 0) | |
13993 | return -EINVAL; | |
13994 | ||
ec2c981e | 13995 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
13996 | mode_cmd->pixel_format, |
13997 | mode_cmd->modifier[0]); | |
53155c0a DV |
13998 | /* FIXME drm helper for size checks (especially planar formats)? */ |
13999 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14000 | return -EINVAL; | |
14001 | ||
c7d73f6a DV |
14002 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14003 | intel_fb->obj = obj; | |
80075d49 | 14004 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14005 | |
79e53945 JB |
14006 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14007 | if (ret) { | |
14008 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14009 | return ret; | |
14010 | } | |
14011 | ||
79e53945 JB |
14012 | return 0; |
14013 | } | |
14014 | ||
79e53945 JB |
14015 | static struct drm_framebuffer * |
14016 | intel_user_framebuffer_create(struct drm_device *dev, | |
14017 | struct drm_file *filp, | |
308e5bcb | 14018 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14019 | { |
05394f39 | 14020 | struct drm_i915_gem_object *obj; |
79e53945 | 14021 | |
308e5bcb JB |
14022 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14023 | mode_cmd->handles[0])); | |
c8725226 | 14024 | if (&obj->base == NULL) |
cce13ff7 | 14025 | return ERR_PTR(-ENOENT); |
79e53945 | 14026 | |
d2dff872 | 14027 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14028 | } |
14029 | ||
4520f53a | 14030 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 14031 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14032 | { |
14033 | } | |
14034 | #endif | |
14035 | ||
79e53945 | 14036 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14037 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14038 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14039 | .atomic_check = intel_atomic_check, |
14040 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
14041 | }; |
14042 | ||
e70236a8 JB |
14043 | /* Set up chip specific display functions */ |
14044 | static void intel_init_display(struct drm_device *dev) | |
14045 | { | |
14046 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14047 | ||
ee9300bb DV |
14048 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14049 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14050 | else if (IS_CHERRYVIEW(dev)) |
14051 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14052 | else if (IS_VALLEYVIEW(dev)) |
14053 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14054 | else if (IS_PINEVIEW(dev)) | |
14055 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14056 | else | |
14057 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14058 | ||
bc8d7dff DL |
14059 | if (INTEL_INFO(dev)->gen >= 9) { |
14060 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14061 | dev_priv->display.get_initial_plane_config = |
14062 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14063 | dev_priv->display.crtc_compute_clock = |
14064 | haswell_crtc_compute_clock; | |
14065 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14066 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
14067 | dev_priv->display.off = ironlake_crtc_off; | |
14068 | dev_priv->display.update_primary_plane = | |
14069 | skylake_update_primary_plane; | |
14070 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14071 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14072 | dev_priv->display.get_initial_plane_config = |
14073 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14074 | dev_priv->display.crtc_compute_clock = |
14075 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14076 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14077 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 14078 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
14079 | dev_priv->display.update_primary_plane = |
14080 | ironlake_update_primary_plane; | |
09b4ddf9 | 14081 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14082 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14083 | dev_priv->display.get_initial_plane_config = |
14084 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14085 | dev_priv->display.crtc_compute_clock = |
14086 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14087 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14088 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 14089 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
14090 | dev_priv->display.update_primary_plane = |
14091 | ironlake_update_primary_plane; | |
89b667f8 JB |
14092 | } else if (IS_VALLEYVIEW(dev)) { |
14093 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14094 | dev_priv->display.get_initial_plane_config = |
14095 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14096 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14097 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14098 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14099 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
14100 | dev_priv->display.update_primary_plane = |
14101 | i9xx_update_primary_plane; | |
f564048e | 14102 | } else { |
0e8ffe1b | 14103 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14104 | dev_priv->display.get_initial_plane_config = |
14105 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14106 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14107 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14108 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 14109 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
14110 | dev_priv->display.update_primary_plane = |
14111 | i9xx_update_primary_plane; | |
f564048e | 14112 | } |
e70236a8 | 14113 | |
e70236a8 | 14114 | /* Returns the core display clock speed */ |
1652d19e VS |
14115 | if (IS_SKYLAKE(dev)) |
14116 | dev_priv->display.get_display_clock_speed = | |
14117 | skylake_get_display_clock_speed; | |
14118 | else if (IS_BROADWELL(dev)) | |
14119 | dev_priv->display.get_display_clock_speed = | |
14120 | broadwell_get_display_clock_speed; | |
14121 | else if (IS_HASWELL(dev)) | |
14122 | dev_priv->display.get_display_clock_speed = | |
14123 | haswell_get_display_clock_speed; | |
14124 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14125 | dev_priv->display.get_display_clock_speed = |
14126 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14127 | else if (IS_GEN5(dev)) |
14128 | dev_priv->display.get_display_clock_speed = | |
14129 | ilk_get_display_clock_speed; | |
a7c66cd8 VS |
14130 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
14131 | IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
14132 | dev_priv->display.get_display_clock_speed = |
14133 | i945_get_display_clock_speed; | |
14134 | else if (IS_I915G(dev)) | |
14135 | dev_priv->display.get_display_clock_speed = | |
14136 | i915_get_display_clock_speed; | |
257a7ffc | 14137 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14138 | dev_priv->display.get_display_clock_speed = |
14139 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14140 | else if (IS_PINEVIEW(dev)) |
14141 | dev_priv->display.get_display_clock_speed = | |
14142 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14143 | else if (IS_I915GM(dev)) |
14144 | dev_priv->display.get_display_clock_speed = | |
14145 | i915gm_get_display_clock_speed; | |
14146 | else if (IS_I865G(dev)) | |
14147 | dev_priv->display.get_display_clock_speed = | |
14148 | i865_get_display_clock_speed; | |
f0f8a9ce | 14149 | else if (IS_I85X(dev)) |
e70236a8 JB |
14150 | dev_priv->display.get_display_clock_speed = |
14151 | i855_get_display_clock_speed; | |
14152 | else /* 852, 830 */ | |
14153 | dev_priv->display.get_display_clock_speed = | |
14154 | i830_get_display_clock_speed; | |
14155 | ||
7c10a2b5 | 14156 | if (IS_GEN5(dev)) { |
3bb11b53 | 14157 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14158 | } else if (IS_GEN6(dev)) { |
14159 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14160 | } else if (IS_IVYBRIDGE(dev)) { |
14161 | /* FIXME: detect B0+ stepping and use auto training */ | |
14162 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14163 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14164 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
14165 | } else if (IS_VALLEYVIEW(dev)) { |
14166 | dev_priv->display.modeset_global_resources = | |
14167 | valleyview_modeset_global_resources; | |
f8437dd1 VK |
14168 | } else if (IS_BROXTON(dev)) { |
14169 | dev_priv->display.modeset_global_resources = | |
14170 | broxton_modeset_global_resources; | |
e70236a8 | 14171 | } |
8c9f3aaf | 14172 | |
8c9f3aaf JB |
14173 | switch (INTEL_INFO(dev)->gen) { |
14174 | case 2: | |
14175 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14176 | break; | |
14177 | ||
14178 | case 3: | |
14179 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14180 | break; | |
14181 | ||
14182 | case 4: | |
14183 | case 5: | |
14184 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14185 | break; | |
14186 | ||
14187 | case 6: | |
14188 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14189 | break; | |
7c9017e5 | 14190 | case 7: |
4e0bbc31 | 14191 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14192 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14193 | break; | |
830c81db | 14194 | case 9: |
ba343e02 TU |
14195 | /* Drop through - unsupported since execlist only. */ |
14196 | default: | |
14197 | /* Default just returns -ENODEV to indicate unsupported */ | |
14198 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14199 | } |
7bd688cd JN |
14200 | |
14201 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14202 | |
14203 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14204 | } |
14205 | ||
b690e96c JB |
14206 | /* |
14207 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14208 | * resume, or other times. This quirk makes sure that's the case for | |
14209 | * affected systems. | |
14210 | */ | |
0206e353 | 14211 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14212 | { |
14213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14214 | ||
14215 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14216 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14217 | } |
14218 | ||
b6b5d049 VS |
14219 | static void quirk_pipeb_force(struct drm_device *dev) |
14220 | { | |
14221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14222 | ||
14223 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14224 | DRM_INFO("applying pipe b force quirk\n"); | |
14225 | } | |
14226 | ||
435793df KP |
14227 | /* |
14228 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14229 | */ | |
14230 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14231 | { | |
14232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14233 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14234 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14235 | } |
14236 | ||
4dca20ef | 14237 | /* |
5a15ab5b CE |
14238 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14239 | * brightness value | |
4dca20ef CE |
14240 | */ |
14241 | static void quirk_invert_brightness(struct drm_device *dev) | |
14242 | { | |
14243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14244 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14245 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14246 | } |
14247 | ||
9c72cc6f SD |
14248 | /* Some VBT's incorrectly indicate no backlight is present */ |
14249 | static void quirk_backlight_present(struct drm_device *dev) | |
14250 | { | |
14251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14252 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14253 | DRM_INFO("applying backlight present quirk\n"); | |
14254 | } | |
14255 | ||
b690e96c JB |
14256 | struct intel_quirk { |
14257 | int device; | |
14258 | int subsystem_vendor; | |
14259 | int subsystem_device; | |
14260 | void (*hook)(struct drm_device *dev); | |
14261 | }; | |
14262 | ||
5f85f176 EE |
14263 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14264 | struct intel_dmi_quirk { | |
14265 | void (*hook)(struct drm_device *dev); | |
14266 | const struct dmi_system_id (*dmi_id_list)[]; | |
14267 | }; | |
14268 | ||
14269 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14270 | { | |
14271 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14272 | return 1; | |
14273 | } | |
14274 | ||
14275 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14276 | { | |
14277 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14278 | { | |
14279 | .callback = intel_dmi_reverse_brightness, | |
14280 | .ident = "NCR Corporation", | |
14281 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14282 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14283 | }, | |
14284 | }, | |
14285 | { } /* terminating entry */ | |
14286 | }, | |
14287 | .hook = quirk_invert_brightness, | |
14288 | }, | |
14289 | }; | |
14290 | ||
c43b5634 | 14291 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 14292 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 14293 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 14294 | |
b690e96c JB |
14295 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14296 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14297 | ||
b690e96c JB |
14298 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14299 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14300 | ||
5f080c0f VS |
14301 | /* 830 needs to leave pipe A & dpll A up */ |
14302 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14303 | ||
b6b5d049 VS |
14304 | /* 830 needs to leave pipe B & dpll B up */ |
14305 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14306 | ||
435793df KP |
14307 | /* Lenovo U160 cannot use SSC on LVDS */ |
14308 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14309 | |
14310 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14311 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14312 | |
be505f64 AH |
14313 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14314 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14315 | ||
14316 | /* Acer/eMachines G725 */ | |
14317 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14318 | ||
14319 | /* Acer/eMachines e725 */ | |
14320 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14321 | ||
14322 | /* Acer/Packard Bell NCL20 */ | |
14323 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14324 | ||
14325 | /* Acer Aspire 4736Z */ | |
14326 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14327 | |
14328 | /* Acer Aspire 5336 */ | |
14329 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14330 | |
14331 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14332 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14333 | |
dfb3d47b SD |
14334 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14335 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14336 | ||
b2a9601c | 14337 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14338 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14339 | ||
d4967d8c SD |
14340 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14341 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14342 | |
14343 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14344 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14345 | |
14346 | /* Dell Chromebook 11 */ | |
14347 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14348 | }; |
14349 | ||
14350 | static void intel_init_quirks(struct drm_device *dev) | |
14351 | { | |
14352 | struct pci_dev *d = dev->pdev; | |
14353 | int i; | |
14354 | ||
14355 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14356 | struct intel_quirk *q = &intel_quirks[i]; | |
14357 | ||
14358 | if (d->device == q->device && | |
14359 | (d->subsystem_vendor == q->subsystem_vendor || | |
14360 | q->subsystem_vendor == PCI_ANY_ID) && | |
14361 | (d->subsystem_device == q->subsystem_device || | |
14362 | q->subsystem_device == PCI_ANY_ID)) | |
14363 | q->hook(dev); | |
14364 | } | |
5f85f176 EE |
14365 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14366 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14367 | intel_dmi_quirks[i].hook(dev); | |
14368 | } | |
b690e96c JB |
14369 | } |
14370 | ||
9cce37f4 JB |
14371 | /* Disable the VGA plane that we never use */ |
14372 | static void i915_disable_vga(struct drm_device *dev) | |
14373 | { | |
14374 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14375 | u8 sr1; | |
766aa1c4 | 14376 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14377 | |
2b37c616 | 14378 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14379 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14380 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14381 | sr1 = inb(VGA_SR_DATA); |
14382 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14383 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14384 | udelay(300); | |
14385 | ||
01f5a626 | 14386 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14387 | POSTING_READ(vga_reg); |
14388 | } | |
14389 | ||
f817586c DV |
14390 | void intel_modeset_init_hw(struct drm_device *dev) |
14391 | { | |
a8f78b58 ED |
14392 | intel_prepare_ddi(dev); |
14393 | ||
f8bf63fd VS |
14394 | if (IS_VALLEYVIEW(dev)) |
14395 | vlv_update_cdclk(dev); | |
14396 | ||
f817586c DV |
14397 | intel_init_clock_gating(dev); |
14398 | ||
8090c6b9 | 14399 | intel_enable_gt_powersave(dev); |
f817586c DV |
14400 | } |
14401 | ||
79e53945 JB |
14402 | void intel_modeset_init(struct drm_device *dev) |
14403 | { | |
652c393a | 14404 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14405 | int sprite, ret; |
8cc87b75 | 14406 | enum pipe pipe; |
46f297fb | 14407 | struct intel_crtc *crtc; |
79e53945 JB |
14408 | |
14409 | drm_mode_config_init(dev); | |
14410 | ||
14411 | dev->mode_config.min_width = 0; | |
14412 | dev->mode_config.min_height = 0; | |
14413 | ||
019d96cb DA |
14414 | dev->mode_config.preferred_depth = 24; |
14415 | dev->mode_config.prefer_shadow = 1; | |
14416 | ||
25bab385 TU |
14417 | dev->mode_config.allow_fb_modifiers = true; |
14418 | ||
e6ecefaa | 14419 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14420 | |
b690e96c JB |
14421 | intel_init_quirks(dev); |
14422 | ||
1fa61106 ED |
14423 | intel_init_pm(dev); |
14424 | ||
e3c74757 BW |
14425 | if (INTEL_INFO(dev)->num_pipes == 0) |
14426 | return; | |
14427 | ||
e70236a8 | 14428 | intel_init_display(dev); |
7c10a2b5 | 14429 | intel_init_audio(dev); |
e70236a8 | 14430 | |
a6c45cf0 CW |
14431 | if (IS_GEN2(dev)) { |
14432 | dev->mode_config.max_width = 2048; | |
14433 | dev->mode_config.max_height = 2048; | |
14434 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14435 | dev->mode_config.max_width = 4096; |
14436 | dev->mode_config.max_height = 4096; | |
79e53945 | 14437 | } else { |
a6c45cf0 CW |
14438 | dev->mode_config.max_width = 8192; |
14439 | dev->mode_config.max_height = 8192; | |
79e53945 | 14440 | } |
068be561 | 14441 | |
dc41c154 VS |
14442 | if (IS_845G(dev) || IS_I865G(dev)) { |
14443 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14444 | dev->mode_config.cursor_height = 1023; | |
14445 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14446 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14447 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14448 | } else { | |
14449 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14450 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14451 | } | |
14452 | ||
5d4545ae | 14453 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 14454 | |
28c97730 | 14455 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14456 | INTEL_INFO(dev)->num_pipes, |
14457 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14458 | |
055e393f | 14459 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14460 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14461 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14462 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14463 | if (ret) |
06da8da2 | 14464 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14465 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14466 | } |
79e53945 JB |
14467 | } |
14468 | ||
f42bb70d JB |
14469 | intel_init_dpio(dev); |
14470 | ||
e72f9fbf | 14471 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14472 | |
9cce37f4 JB |
14473 | /* Just disable it once at startup */ |
14474 | i915_disable_vga(dev); | |
79e53945 | 14475 | intel_setup_outputs(dev); |
11be49eb CW |
14476 | |
14477 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 14478 | intel_fbc_disable(dev); |
fa9fa083 | 14479 | |
6e9f798d | 14480 | drm_modeset_lock_all(dev); |
fa9fa083 | 14481 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 14482 | drm_modeset_unlock_all(dev); |
46f297fb | 14483 | |
d3fcc808 | 14484 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
14485 | if (!crtc->active) |
14486 | continue; | |
14487 | ||
46f297fb | 14488 | /* |
46f297fb JB |
14489 | * Note that reserving the BIOS fb up front prevents us |
14490 | * from stuffing other stolen allocations like the ring | |
14491 | * on top. This prevents some ugliness at boot time, and | |
14492 | * can even allow for smooth boot transitions if the BIOS | |
14493 | * fb is large enough for the active pipe configuration. | |
14494 | */ | |
5724dbd1 DL |
14495 | if (dev_priv->display.get_initial_plane_config) { |
14496 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
14497 | &crtc->plane_config); |
14498 | /* | |
14499 | * If the fb is shared between multiple heads, we'll | |
14500 | * just get the first one. | |
14501 | */ | |
f6936e29 | 14502 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 14503 | } |
46f297fb | 14504 | } |
2c7111db CW |
14505 | } |
14506 | ||
7fad798e DV |
14507 | static void intel_enable_pipe_a(struct drm_device *dev) |
14508 | { | |
14509 | struct intel_connector *connector; | |
14510 | struct drm_connector *crt = NULL; | |
14511 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14512 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14513 | |
14514 | /* We can't just switch on the pipe A, we need to set things up with a | |
14515 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14516 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14517 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14518 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14519 | crt = &connector->base; | |
14520 | break; | |
14521 | } | |
14522 | } | |
14523 | ||
14524 | if (!crt) | |
14525 | return; | |
14526 | ||
208bf9fd | 14527 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14528 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14529 | } |
14530 | ||
fa555837 DV |
14531 | static bool |
14532 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14533 | { | |
7eb552ae BW |
14534 | struct drm_device *dev = crtc->base.dev; |
14535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14536 | u32 reg, val; |
14537 | ||
7eb552ae | 14538 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
14539 | return true; |
14540 | ||
14541 | reg = DSPCNTR(!crtc->plane); | |
14542 | val = I915_READ(reg); | |
14543 | ||
14544 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14545 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14546 | return false; | |
14547 | ||
14548 | return true; | |
14549 | } | |
14550 | ||
24929352 DV |
14551 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
14552 | { | |
14553 | struct drm_device *dev = crtc->base.dev; | |
14554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 14555 | u32 reg; |
24929352 | 14556 | |
24929352 | 14557 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 14558 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
14559 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
14560 | ||
d3eaf884 | 14561 | /* restore vblank interrupts to correct state */ |
9625604c | 14562 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
14563 | if (crtc->active) { |
14564 | update_scanline_offset(crtc); | |
9625604c DV |
14565 | drm_crtc_vblank_on(&crtc->base); |
14566 | } | |
d3eaf884 | 14567 | |
24929352 | 14568 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14569 | * disable the crtc (and hence change the state) if it is wrong. Note |
14570 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
14571 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
14572 | struct intel_connector *connector; |
14573 | bool plane; | |
14574 | ||
24929352 DV |
14575 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
14576 | crtc->base.base.id); | |
14577 | ||
14578 | /* Pipe has the wrong plane attached and the plane is active. | |
14579 | * Temporarily change the plane mapping and disable everything | |
14580 | * ... */ | |
14581 | plane = crtc->plane; | |
b70709a6 | 14582 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 14583 | crtc->plane = !plane; |
ce22dba9 | 14584 | intel_crtc_disable_planes(&crtc->base); |
24929352 DV |
14585 | dev_priv->display.crtc_disable(&crtc->base); |
14586 | crtc->plane = plane; | |
14587 | ||
14588 | /* ... and break all links. */ | |
3a3371ff | 14589 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14590 | if (connector->encoder->base.crtc != &crtc->base) |
14591 | continue; | |
14592 | ||
7f1950fb EE |
14593 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14594 | connector->base.encoder = NULL; | |
24929352 | 14595 | } |
7f1950fb EE |
14596 | /* multiple connectors may have the same encoder: |
14597 | * handle them and break crtc link separately */ | |
3a3371ff | 14598 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
14599 | if (connector->encoder->base.crtc == &crtc->base) { |
14600 | connector->encoder->base.crtc = NULL; | |
14601 | connector->encoder->connectors_active = false; | |
14602 | } | |
24929352 DV |
14603 | |
14604 | WARN_ON(crtc->active); | |
83d65738 | 14605 | crtc->base.state->enable = false; |
24929352 DV |
14606 | crtc->base.enabled = false; |
14607 | } | |
24929352 | 14608 | |
7fad798e DV |
14609 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
14610 | crtc->pipe == PIPE_A && !crtc->active) { | |
14611 | /* BIOS forgot to enable pipe A, this mostly happens after | |
14612 | * resume. Force-enable the pipe to fix this, the update_dpms | |
14613 | * call below we restore the pipe to the right state, but leave | |
14614 | * the required bits on. */ | |
14615 | intel_enable_pipe_a(dev); | |
14616 | } | |
14617 | ||
24929352 DV |
14618 | /* Adjust the state of the output pipe according to whether we |
14619 | * have active connectors/encoders. */ | |
14620 | intel_crtc_update_dpms(&crtc->base); | |
14621 | ||
83d65738 | 14622 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
14623 | struct intel_encoder *encoder; |
14624 | ||
14625 | /* This can happen either due to bugs in the get_hw_state | |
14626 | * functions or because the pipe is force-enabled due to the | |
14627 | * pipe A quirk. */ | |
14628 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
14629 | crtc->base.base.id, | |
83d65738 | 14630 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
14631 | crtc->active ? "enabled" : "disabled"); |
14632 | ||
83d65738 | 14633 | crtc->base.state->enable = crtc->active; |
24929352 DV |
14634 | crtc->base.enabled = crtc->active; |
14635 | ||
14636 | /* Because we only establish the connector -> encoder -> | |
14637 | * crtc links if something is active, this means the | |
14638 | * crtc is now deactivated. Break the links. connector | |
14639 | * -> encoder links are only establish when things are | |
14640 | * actually up, hence no need to break them. */ | |
14641 | WARN_ON(crtc->active); | |
14642 | ||
14643 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
14644 | WARN_ON(encoder->connectors_active); | |
14645 | encoder->base.crtc = NULL; | |
14646 | } | |
14647 | } | |
c5ab3bc0 | 14648 | |
a3ed6aad | 14649 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
14650 | /* |
14651 | * We start out with underrun reporting disabled to avoid races. | |
14652 | * For correct bookkeeping mark this on active crtcs. | |
14653 | * | |
c5ab3bc0 DV |
14654 | * Also on gmch platforms we dont have any hardware bits to |
14655 | * disable the underrun reporting. Which means we need to start | |
14656 | * out with underrun reporting disabled also on inactive pipes, | |
14657 | * since otherwise we'll complain about the garbage we read when | |
14658 | * e.g. coming up after runtime pm. | |
14659 | * | |
4cc31489 DV |
14660 | * No protection against concurrent access is required - at |
14661 | * worst a fifo underrun happens which also sets this to false. | |
14662 | */ | |
14663 | crtc->cpu_fifo_underrun_disabled = true; | |
14664 | crtc->pch_fifo_underrun_disabled = true; | |
14665 | } | |
24929352 DV |
14666 | } |
14667 | ||
14668 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14669 | { | |
14670 | struct intel_connector *connector; | |
14671 | struct drm_device *dev = encoder->base.dev; | |
14672 | ||
14673 | /* We need to check both for a crtc link (meaning that the | |
14674 | * encoder is active and trying to read from a pipe) and the | |
14675 | * pipe itself being active. */ | |
14676 | bool has_active_crtc = encoder->base.crtc && | |
14677 | to_intel_crtc(encoder->base.crtc)->active; | |
14678 | ||
14679 | if (encoder->connectors_active && !has_active_crtc) { | |
14680 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
14681 | encoder->base.base.id, | |
8e329a03 | 14682 | encoder->base.name); |
24929352 DV |
14683 | |
14684 | /* Connector is active, but has no active pipe. This is | |
14685 | * fallout from our resume register restoring. Disable | |
14686 | * the encoder manually again. */ | |
14687 | if (encoder->base.crtc) { | |
14688 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
14689 | encoder->base.base.id, | |
8e329a03 | 14690 | encoder->base.name); |
24929352 | 14691 | encoder->disable(encoder); |
a62d1497 VS |
14692 | if (encoder->post_disable) |
14693 | encoder->post_disable(encoder); | |
24929352 | 14694 | } |
7f1950fb EE |
14695 | encoder->base.crtc = NULL; |
14696 | encoder->connectors_active = false; | |
24929352 DV |
14697 | |
14698 | /* Inconsistent output/port/pipe state happens presumably due to | |
14699 | * a bug in one of the get_hw_state functions. Or someplace else | |
14700 | * in our code, like the register restore mess on resume. Clamp | |
14701 | * things to off as a safer default. */ | |
3a3371ff | 14702 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14703 | if (connector->encoder != encoder) |
14704 | continue; | |
7f1950fb EE |
14705 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14706 | connector->base.encoder = NULL; | |
24929352 DV |
14707 | } |
14708 | } | |
14709 | /* Enabled encoders without active connectors will be fixed in | |
14710 | * the crtc fixup. */ | |
14711 | } | |
14712 | ||
04098753 | 14713 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
14714 | { |
14715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 14716 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 14717 | |
04098753 ID |
14718 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14719 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
14720 | i915_disable_vga(dev); | |
14721 | } | |
14722 | } | |
14723 | ||
14724 | void i915_redisable_vga(struct drm_device *dev) | |
14725 | { | |
14726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14727 | ||
8dc8a27c PZ |
14728 | /* This function can be called both from intel_modeset_setup_hw_state or |
14729 | * at a very early point in our resume sequence, where the power well | |
14730 | * structures are not yet restored. Since this function is at a very | |
14731 | * paranoid "someone might have enabled VGA while we were not looking" | |
14732 | * level, just check if the power well is enabled instead of trying to | |
14733 | * follow the "don't touch the power well if we don't need it" policy | |
14734 | * the rest of the driver uses. */ | |
f458ebbc | 14735 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14736 | return; |
14737 | ||
04098753 | 14738 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
14739 | } |
14740 | ||
98ec7739 VS |
14741 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
14742 | { | |
14743 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
14744 | ||
14745 | if (!crtc->active) | |
14746 | return false; | |
14747 | ||
14748 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
14749 | } | |
14750 | ||
30e984df | 14751 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
14752 | { |
14753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14754 | enum pipe pipe; | |
24929352 DV |
14755 | struct intel_crtc *crtc; |
14756 | struct intel_encoder *encoder; | |
14757 | struct intel_connector *connector; | |
5358901f | 14758 | int i; |
24929352 | 14759 | |
d3fcc808 | 14760 | for_each_intel_crtc(dev, crtc) { |
b70709a6 ML |
14761 | struct drm_plane *primary = crtc->base.primary; |
14762 | struct intel_plane_state *plane_state; | |
14763 | ||
6e3c9717 | 14764 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 14765 | |
6e3c9717 | 14766 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 14767 | |
0e8ffe1b | 14768 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 14769 | crtc->config); |
24929352 | 14770 | |
83d65738 | 14771 | crtc->base.state->enable = crtc->active; |
24929352 | 14772 | crtc->base.enabled = crtc->active; |
b70709a6 ML |
14773 | |
14774 | plane_state = to_intel_plane_state(primary->state); | |
14775 | plane_state->visible = primary_get_hw_state(crtc); | |
24929352 DV |
14776 | |
14777 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
14778 | crtc->base.base.id, | |
14779 | crtc->active ? "enabled" : "disabled"); | |
14780 | } | |
14781 | ||
5358901f DV |
14782 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14783 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14784 | ||
3e369b76 ACO |
14785 | pll->on = pll->get_hw_state(dev_priv, pll, |
14786 | &pll->config.hw_state); | |
5358901f | 14787 | pll->active = 0; |
3e369b76 | 14788 | pll->config.crtc_mask = 0; |
d3fcc808 | 14789 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 14790 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 14791 | pll->active++; |
3e369b76 | 14792 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 14793 | } |
5358901f | 14794 | } |
5358901f | 14795 | |
1e6f2ddc | 14796 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 14797 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 14798 | |
3e369b76 | 14799 | if (pll->config.crtc_mask) |
bd2bb1b9 | 14800 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
14801 | } |
14802 | ||
b2784e15 | 14803 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14804 | pipe = 0; |
14805 | ||
14806 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
14807 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14808 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 14809 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
14810 | } else { |
14811 | encoder->base.crtc = NULL; | |
14812 | } | |
14813 | ||
14814 | encoder->connectors_active = false; | |
6f2bcceb | 14815 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 14816 | encoder->base.base.id, |
8e329a03 | 14817 | encoder->base.name, |
24929352 | 14818 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 14819 | pipe_name(pipe)); |
24929352 DV |
14820 | } |
14821 | ||
3a3371ff | 14822 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14823 | if (connector->get_hw_state(connector)) { |
14824 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
14825 | connector->encoder->connectors_active = true; | |
14826 | connector->base.encoder = &connector->encoder->base; | |
14827 | } else { | |
14828 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14829 | connector->base.encoder = NULL; | |
14830 | } | |
14831 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
14832 | connector->base.base.id, | |
c23cc417 | 14833 | connector->base.name, |
24929352 DV |
14834 | connector->base.encoder ? "enabled" : "disabled"); |
14835 | } | |
30e984df DV |
14836 | } |
14837 | ||
14838 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
14839 | * and i915 state tracking structures. */ | |
14840 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
14841 | bool force_restore) | |
14842 | { | |
14843 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14844 | enum pipe pipe; | |
30e984df DV |
14845 | struct intel_crtc *crtc; |
14846 | struct intel_encoder *encoder; | |
35c95375 | 14847 | int i; |
30e984df DV |
14848 | |
14849 | intel_modeset_readout_hw_state(dev); | |
24929352 | 14850 | |
babea61d JB |
14851 | /* |
14852 | * Now that we have the config, copy it to each CRTC struct | |
14853 | * Note that this could go away if we move to using crtc_config | |
14854 | * checking everywhere. | |
14855 | */ | |
d3fcc808 | 14856 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 14857 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
14858 | intel_mode_from_pipe_config(&crtc->base.mode, |
14859 | crtc->config); | |
babea61d JB |
14860 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
14861 | crtc->base.base.id); | |
14862 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
14863 | } | |
14864 | } | |
14865 | ||
24929352 | 14866 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 14867 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14868 | intel_sanitize_encoder(encoder); |
14869 | } | |
14870 | ||
055e393f | 14871 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
14872 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14873 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
14874 | intel_dump_pipe_config(crtc, crtc->config, |
14875 | "[setup_hw_state]"); | |
24929352 | 14876 | } |
9a935856 | 14877 | |
d29b2f9d ACO |
14878 | intel_modeset_update_connector_atomic_state(dev); |
14879 | ||
35c95375 DV |
14880 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14881 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14882 | ||
14883 | if (!pll->on || pll->active) | |
14884 | continue; | |
14885 | ||
14886 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
14887 | ||
14888 | pll->disable(dev_priv, pll); | |
14889 | pll->on = false; | |
14890 | } | |
14891 | ||
3078999f PB |
14892 | if (IS_GEN9(dev)) |
14893 | skl_wm_get_hw_state(dev); | |
14894 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
14895 | ilk_wm_get_hw_state(dev); |
14896 | ||
45e2b5f6 | 14897 | if (force_restore) { |
7d0bc1ea VS |
14898 | i915_redisable_vga(dev); |
14899 | ||
f30da187 DV |
14900 | /* |
14901 | * We need to use raw interfaces for restoring state to avoid | |
14902 | * checking (bogus) intermediate states. | |
14903 | */ | |
055e393f | 14904 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
14905 | struct drm_crtc *crtc = |
14906 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 14907 | |
83a57153 | 14908 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
14909 | } |
14910 | } else { | |
14911 | intel_modeset_update_staged_output_state(dev); | |
14912 | } | |
8af6cf88 DV |
14913 | |
14914 | intel_modeset_check_state(dev); | |
2c7111db CW |
14915 | } |
14916 | ||
14917 | void intel_modeset_gem_init(struct drm_device *dev) | |
14918 | { | |
92122789 | 14919 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 14920 | struct drm_crtc *c; |
2ff8fde1 | 14921 | struct drm_i915_gem_object *obj; |
e0d6149b | 14922 | int ret; |
484b41dd | 14923 | |
ae48434c ID |
14924 | mutex_lock(&dev->struct_mutex); |
14925 | intel_init_gt_powersave(dev); | |
14926 | mutex_unlock(&dev->struct_mutex); | |
14927 | ||
92122789 JB |
14928 | /* |
14929 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14930 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14931 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14932 | * indicates as much. | |
14933 | */ | |
14934 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
14935 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14936 | DREF_SSC1_ENABLE); | |
14937 | ||
1833b134 | 14938 | intel_modeset_init_hw(dev); |
02e792fb DV |
14939 | |
14940 | intel_setup_overlay(dev); | |
484b41dd JB |
14941 | |
14942 | /* | |
14943 | * Make sure any fbs we allocated at startup are properly | |
14944 | * pinned & fenced. When we do the allocation it's too early | |
14945 | * for this. | |
14946 | */ | |
70e1e0ec | 14947 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
14948 | obj = intel_fb_obj(c->primary->fb); |
14949 | if (obj == NULL) | |
484b41dd JB |
14950 | continue; |
14951 | ||
e0d6149b TU |
14952 | mutex_lock(&dev->struct_mutex); |
14953 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
14954 | c->primary->fb, | |
14955 | c->primary->state, | |
14956 | NULL); | |
14957 | mutex_unlock(&dev->struct_mutex); | |
14958 | if (ret) { | |
484b41dd JB |
14959 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
14960 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
14961 | drm_framebuffer_unreference(c->primary->fb); |
14962 | c->primary->fb = NULL; | |
afd65eb4 | 14963 | update_state_fb(c->primary); |
484b41dd JB |
14964 | } |
14965 | } | |
0962c3c9 VS |
14966 | |
14967 | intel_backlight_register(dev); | |
79e53945 JB |
14968 | } |
14969 | ||
4932e2c3 ID |
14970 | void intel_connector_unregister(struct intel_connector *intel_connector) |
14971 | { | |
14972 | struct drm_connector *connector = &intel_connector->base; | |
14973 | ||
14974 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 14975 | drm_connector_unregister(connector); |
4932e2c3 ID |
14976 | } |
14977 | ||
79e53945 JB |
14978 | void intel_modeset_cleanup(struct drm_device *dev) |
14979 | { | |
652c393a | 14980 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 14981 | struct drm_connector *connector; |
652c393a | 14982 | |
2eb5252e ID |
14983 | intel_disable_gt_powersave(dev); |
14984 | ||
0962c3c9 VS |
14985 | intel_backlight_unregister(dev); |
14986 | ||
fd0c0642 DV |
14987 | /* |
14988 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 14989 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
14990 | * experience fancy races otherwise. |
14991 | */ | |
2aeb7d3a | 14992 | intel_irq_uninstall(dev_priv); |
eb21b92b | 14993 | |
fd0c0642 DV |
14994 | /* |
14995 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
14996 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
14997 | */ | |
f87ea761 | 14998 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 14999 | |
652c393a JB |
15000 | mutex_lock(&dev->struct_mutex); |
15001 | ||
723bfd70 JB |
15002 | intel_unregister_dsm_handler(); |
15003 | ||
7ff0ebcc | 15004 | intel_fbc_disable(dev); |
e70236a8 | 15005 | |
69341a5e KH |
15006 | mutex_unlock(&dev->struct_mutex); |
15007 | ||
1630fe75 CW |
15008 | /* flush any delayed tasks or pending work */ |
15009 | flush_scheduled_work(); | |
15010 | ||
db31af1d JN |
15011 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15012 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15013 | struct intel_connector *intel_connector; |
15014 | ||
15015 | intel_connector = to_intel_connector(connector); | |
15016 | intel_connector->unregister(intel_connector); | |
db31af1d | 15017 | } |
d9255d57 | 15018 | |
79e53945 | 15019 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15020 | |
15021 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15022 | |
15023 | mutex_lock(&dev->struct_mutex); | |
15024 | intel_cleanup_gt_powersave(dev); | |
15025 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15026 | } |
15027 | ||
f1c79df3 ZW |
15028 | /* |
15029 | * Return which encoder is currently attached for connector. | |
15030 | */ | |
df0e9248 | 15031 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15032 | { |
df0e9248 CW |
15033 | return &intel_attached_encoder(connector)->base; |
15034 | } | |
f1c79df3 | 15035 | |
df0e9248 CW |
15036 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15037 | struct intel_encoder *encoder) | |
15038 | { | |
15039 | connector->encoder = encoder; | |
15040 | drm_mode_connector_attach_encoder(&connector->base, | |
15041 | &encoder->base); | |
79e53945 | 15042 | } |
28d52043 DA |
15043 | |
15044 | /* | |
15045 | * set vga decode state - true == enable VGA decode | |
15046 | */ | |
15047 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15048 | { | |
15049 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15050 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15051 | u16 gmch_ctrl; |
15052 | ||
75fa041d CW |
15053 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15054 | DRM_ERROR("failed to read control word\n"); | |
15055 | return -EIO; | |
15056 | } | |
15057 | ||
c0cc8a55 CW |
15058 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15059 | return 0; | |
15060 | ||
28d52043 DA |
15061 | if (state) |
15062 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15063 | else | |
15064 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15065 | |
15066 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15067 | DRM_ERROR("failed to write control word\n"); | |
15068 | return -EIO; | |
15069 | } | |
15070 | ||
28d52043 DA |
15071 | return 0; |
15072 | } | |
c4a1d9e4 | 15073 | |
c4a1d9e4 | 15074 | struct intel_display_error_state { |
ff57f1b0 PZ |
15075 | |
15076 | u32 power_well_driver; | |
15077 | ||
63b66e5b CW |
15078 | int num_transcoders; |
15079 | ||
c4a1d9e4 CW |
15080 | struct intel_cursor_error_state { |
15081 | u32 control; | |
15082 | u32 position; | |
15083 | u32 base; | |
15084 | u32 size; | |
52331309 | 15085 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15086 | |
15087 | struct intel_pipe_error_state { | |
ddf9c536 | 15088 | bool power_domain_on; |
c4a1d9e4 | 15089 | u32 source; |
f301b1e1 | 15090 | u32 stat; |
52331309 | 15091 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15092 | |
15093 | struct intel_plane_error_state { | |
15094 | u32 control; | |
15095 | u32 stride; | |
15096 | u32 size; | |
15097 | u32 pos; | |
15098 | u32 addr; | |
15099 | u32 surface; | |
15100 | u32 tile_offset; | |
52331309 | 15101 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15102 | |
15103 | struct intel_transcoder_error_state { | |
ddf9c536 | 15104 | bool power_domain_on; |
63b66e5b CW |
15105 | enum transcoder cpu_transcoder; |
15106 | ||
15107 | u32 conf; | |
15108 | ||
15109 | u32 htotal; | |
15110 | u32 hblank; | |
15111 | u32 hsync; | |
15112 | u32 vtotal; | |
15113 | u32 vblank; | |
15114 | u32 vsync; | |
15115 | } transcoder[4]; | |
c4a1d9e4 CW |
15116 | }; |
15117 | ||
15118 | struct intel_display_error_state * | |
15119 | intel_display_capture_error_state(struct drm_device *dev) | |
15120 | { | |
fbee40df | 15121 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15122 | struct intel_display_error_state *error; |
63b66e5b CW |
15123 | int transcoders[] = { |
15124 | TRANSCODER_A, | |
15125 | TRANSCODER_B, | |
15126 | TRANSCODER_C, | |
15127 | TRANSCODER_EDP, | |
15128 | }; | |
c4a1d9e4 CW |
15129 | int i; |
15130 | ||
63b66e5b CW |
15131 | if (INTEL_INFO(dev)->num_pipes == 0) |
15132 | return NULL; | |
15133 | ||
9d1cb914 | 15134 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15135 | if (error == NULL) |
15136 | return NULL; | |
15137 | ||
190be112 | 15138 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15139 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15140 | ||
055e393f | 15141 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15142 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15143 | __intel_display_power_is_enabled(dev_priv, |
15144 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15145 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15146 | continue; |
15147 | ||
5efb3e28 VS |
15148 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15149 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15150 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15151 | |
15152 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15153 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15154 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15155 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15156 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15157 | } | |
ca291363 PZ |
15158 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15159 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15160 | if (INTEL_INFO(dev)->gen >= 4) { |
15161 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15162 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15163 | } | |
15164 | ||
c4a1d9e4 | 15165 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15166 | |
3abfce77 | 15167 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15168 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15169 | } |
15170 | ||
15171 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15172 | if (HAS_DDI(dev_priv->dev)) | |
15173 | error->num_transcoders++; /* Account for eDP. */ | |
15174 | ||
15175 | for (i = 0; i < error->num_transcoders; i++) { | |
15176 | enum transcoder cpu_transcoder = transcoders[i]; | |
15177 | ||
ddf9c536 | 15178 | error->transcoder[i].power_domain_on = |
f458ebbc | 15179 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15180 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15181 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15182 | continue; |
15183 | ||
63b66e5b CW |
15184 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15185 | ||
15186 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15187 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15188 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15189 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15190 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15191 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15192 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15193 | } |
15194 | ||
15195 | return error; | |
15196 | } | |
15197 | ||
edc3d884 MK |
15198 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15199 | ||
c4a1d9e4 | 15200 | void |
edc3d884 | 15201 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15202 | struct drm_device *dev, |
15203 | struct intel_display_error_state *error) | |
15204 | { | |
055e393f | 15205 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15206 | int i; |
15207 | ||
63b66e5b CW |
15208 | if (!error) |
15209 | return; | |
15210 | ||
edc3d884 | 15211 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15212 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15213 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15214 | error->power_well_driver); |
055e393f | 15215 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15216 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15217 | err_printf(m, " Power: %s\n", |
15218 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15219 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15220 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15221 | |
15222 | err_printf(m, "Plane [%d]:\n", i); | |
15223 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15224 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15225 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15226 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15227 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15228 | } |
4b71a570 | 15229 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15230 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15231 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15232 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15233 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15234 | } |
15235 | ||
edc3d884 MK |
15236 | err_printf(m, "Cursor [%d]:\n", i); |
15237 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15238 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15239 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15240 | } |
63b66e5b CW |
15241 | |
15242 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15243 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15244 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15245 | err_printf(m, " Power: %s\n", |
15246 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15247 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15248 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15249 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15250 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15251 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15252 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15253 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15254 | } | |
c4a1d9e4 | 15255 | } |
e2fcdaa9 VS |
15256 | |
15257 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15258 | { | |
15259 | struct intel_crtc *crtc; | |
15260 | ||
15261 | for_each_intel_crtc(dev, crtc) { | |
15262 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15263 | |
5e2d7afc | 15264 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15265 | |
15266 | work = crtc->unpin_work; | |
15267 | ||
15268 | if (work && work->event && | |
15269 | work->event->base.file_priv == file) { | |
15270 | kfree(work->event); | |
15271 | work->event = NULL; | |
15272 | } | |
15273 | ||
5e2d7afc | 15274 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15275 | } |
15276 | } |