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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
c1c7af60 JB |
27 | #include <linux/module.h> |
28 | #include <linux/input.h> | |
79e53945 | 29 | #include <linux/i2c.h> |
7662c8bd | 30 | #include <linux/kernel.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
9cce37f4 | 32 | #include <linux/vgaarb.h> |
79e53945 JB |
33 | #include "drmP.h" |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
e5510fac | 37 | #include "i915_trace.h" |
ab2c0672 | 38 | #include "drm_dp_helper.h" |
79e53945 JB |
39 | |
40 | #include "drm_crtc_helper.h" | |
41 | ||
32f9d658 ZW |
42 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
43 | ||
79e53945 | 44 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); |
7662c8bd | 45 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 46 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 47 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
48 | |
49 | typedef struct { | |
50 | /* given values */ | |
51 | int n; | |
52 | int m1, m2; | |
53 | int p1, p2; | |
54 | /* derived values */ | |
55 | int dot; | |
56 | int vco; | |
57 | int m; | |
58 | int p; | |
59 | } intel_clock_t; | |
60 | ||
61 | typedef struct { | |
62 | int min, max; | |
63 | } intel_range_t; | |
64 | ||
65 | typedef struct { | |
66 | int dot_limit; | |
67 | int p2_slow, p2_fast; | |
68 | } intel_p2_t; | |
69 | ||
70 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
71 | typedef struct intel_limit intel_limit_t; |
72 | struct intel_limit { | |
79e53945 JB |
73 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
74 | intel_p2_t p2; | |
d4906093 ML |
75 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
76 | int, int, intel_clock_t *); | |
77 | }; | |
79e53945 JB |
78 | |
79 | #define I8XX_DOT_MIN 25000 | |
80 | #define I8XX_DOT_MAX 350000 | |
81 | #define I8XX_VCO_MIN 930000 | |
82 | #define I8XX_VCO_MAX 1400000 | |
83 | #define I8XX_N_MIN 3 | |
84 | #define I8XX_N_MAX 16 | |
85 | #define I8XX_M_MIN 96 | |
86 | #define I8XX_M_MAX 140 | |
87 | #define I8XX_M1_MIN 18 | |
88 | #define I8XX_M1_MAX 26 | |
89 | #define I8XX_M2_MIN 6 | |
90 | #define I8XX_M2_MAX 16 | |
91 | #define I8XX_P_MIN 4 | |
92 | #define I8XX_P_MAX 128 | |
93 | #define I8XX_P1_MIN 2 | |
94 | #define I8XX_P1_MAX 33 | |
95 | #define I8XX_P1_LVDS_MIN 1 | |
96 | #define I8XX_P1_LVDS_MAX 6 | |
97 | #define I8XX_P2_SLOW 4 | |
98 | #define I8XX_P2_FAST 2 | |
99 | #define I8XX_P2_LVDS_SLOW 14 | |
0c2e3952 | 100 | #define I8XX_P2_LVDS_FAST 7 |
79e53945 JB |
101 | #define I8XX_P2_SLOW_LIMIT 165000 |
102 | ||
103 | #define I9XX_DOT_MIN 20000 | |
104 | #define I9XX_DOT_MAX 400000 | |
105 | #define I9XX_VCO_MIN 1400000 | |
106 | #define I9XX_VCO_MAX 2800000 | |
f2b115e6 AJ |
107 | #define PINEVIEW_VCO_MIN 1700000 |
108 | #define PINEVIEW_VCO_MAX 3500000 | |
f3cade5c KH |
109 | #define I9XX_N_MIN 1 |
110 | #define I9XX_N_MAX 6 | |
f2b115e6 AJ |
111 | /* Pineview's Ncounter is a ring counter */ |
112 | #define PINEVIEW_N_MIN 3 | |
113 | #define PINEVIEW_N_MAX 6 | |
79e53945 JB |
114 | #define I9XX_M_MIN 70 |
115 | #define I9XX_M_MAX 120 | |
f2b115e6 AJ |
116 | #define PINEVIEW_M_MIN 2 |
117 | #define PINEVIEW_M_MAX 256 | |
79e53945 | 118 | #define I9XX_M1_MIN 10 |
f3cade5c | 119 | #define I9XX_M1_MAX 22 |
79e53945 JB |
120 | #define I9XX_M2_MIN 5 |
121 | #define I9XX_M2_MAX 9 | |
f2b115e6 AJ |
122 | /* Pineview M1 is reserved, and must be 0 */ |
123 | #define PINEVIEW_M1_MIN 0 | |
124 | #define PINEVIEW_M1_MAX 0 | |
125 | #define PINEVIEW_M2_MIN 0 | |
126 | #define PINEVIEW_M2_MAX 254 | |
79e53945 JB |
127 | #define I9XX_P_SDVO_DAC_MIN 5 |
128 | #define I9XX_P_SDVO_DAC_MAX 80 | |
129 | #define I9XX_P_LVDS_MIN 7 | |
130 | #define I9XX_P_LVDS_MAX 98 | |
f2b115e6 AJ |
131 | #define PINEVIEW_P_LVDS_MIN 7 |
132 | #define PINEVIEW_P_LVDS_MAX 112 | |
79e53945 JB |
133 | #define I9XX_P1_MIN 1 |
134 | #define I9XX_P1_MAX 8 | |
135 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
136 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
137 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
138 | #define I9XX_P2_LVDS_SLOW 14 | |
139 | #define I9XX_P2_LVDS_FAST 7 | |
140 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
141 | ||
044c7c41 ML |
142 | /*The parameter is for SDVO on G4x platform*/ |
143 | #define G4X_DOT_SDVO_MIN 25000 | |
144 | #define G4X_DOT_SDVO_MAX 270000 | |
145 | #define G4X_VCO_MIN 1750000 | |
146 | #define G4X_VCO_MAX 3500000 | |
147 | #define G4X_N_SDVO_MIN 1 | |
148 | #define G4X_N_SDVO_MAX 4 | |
149 | #define G4X_M_SDVO_MIN 104 | |
150 | #define G4X_M_SDVO_MAX 138 | |
151 | #define G4X_M1_SDVO_MIN 17 | |
152 | #define G4X_M1_SDVO_MAX 23 | |
153 | #define G4X_M2_SDVO_MIN 5 | |
154 | #define G4X_M2_SDVO_MAX 11 | |
155 | #define G4X_P_SDVO_MIN 10 | |
156 | #define G4X_P_SDVO_MAX 30 | |
157 | #define G4X_P1_SDVO_MIN 1 | |
158 | #define G4X_P1_SDVO_MAX 3 | |
159 | #define G4X_P2_SDVO_SLOW 10 | |
160 | #define G4X_P2_SDVO_FAST 10 | |
161 | #define G4X_P2_SDVO_LIMIT 270000 | |
162 | ||
163 | /*The parameter is for HDMI_DAC on G4x platform*/ | |
164 | #define G4X_DOT_HDMI_DAC_MIN 22000 | |
165 | #define G4X_DOT_HDMI_DAC_MAX 400000 | |
166 | #define G4X_N_HDMI_DAC_MIN 1 | |
167 | #define G4X_N_HDMI_DAC_MAX 4 | |
168 | #define G4X_M_HDMI_DAC_MIN 104 | |
169 | #define G4X_M_HDMI_DAC_MAX 138 | |
170 | #define G4X_M1_HDMI_DAC_MIN 16 | |
171 | #define G4X_M1_HDMI_DAC_MAX 23 | |
172 | #define G4X_M2_HDMI_DAC_MIN 5 | |
173 | #define G4X_M2_HDMI_DAC_MAX 11 | |
174 | #define G4X_P_HDMI_DAC_MIN 5 | |
175 | #define G4X_P_HDMI_DAC_MAX 80 | |
176 | #define G4X_P1_HDMI_DAC_MIN 1 | |
177 | #define G4X_P1_HDMI_DAC_MAX 8 | |
178 | #define G4X_P2_HDMI_DAC_SLOW 10 | |
179 | #define G4X_P2_HDMI_DAC_FAST 5 | |
180 | #define G4X_P2_HDMI_DAC_LIMIT 165000 | |
181 | ||
182 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ | |
183 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 | |
184 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 | |
185 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 | |
186 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 | |
187 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 | |
188 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 | |
189 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 | |
190 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 | |
191 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 | |
192 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 | |
193 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 | |
194 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 | |
195 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 | |
196 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 | |
197 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 | |
198 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 | |
199 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 | |
200 | ||
201 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ | |
202 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 | |
203 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 | |
204 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 | |
205 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 | |
206 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 | |
207 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 | |
208 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 | |
209 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 | |
210 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 | |
211 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 | |
212 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 | |
213 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 | |
214 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 | |
215 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 | |
216 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 | |
217 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 | |
218 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 | |
219 | ||
a4fc5ed6 KP |
220 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
221 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 | |
222 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 | |
223 | #define G4X_N_DISPLAY_PORT_MIN 1 | |
224 | #define G4X_N_DISPLAY_PORT_MAX 2 | |
225 | #define G4X_M_DISPLAY_PORT_MIN 97 | |
226 | #define G4X_M_DISPLAY_PORT_MAX 108 | |
227 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 | |
228 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 | |
229 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 | |
230 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 | |
231 | #define G4X_P_DISPLAY_PORT_MIN 10 | |
232 | #define G4X_P_DISPLAY_PORT_MAX 20 | |
233 | #define G4X_P1_DISPLAY_PORT_MIN 1 | |
234 | #define G4X_P1_DISPLAY_PORT_MAX 2 | |
235 | #define G4X_P2_DISPLAY_PORT_SLOW 10 | |
236 | #define G4X_P2_DISPLAY_PORT_FAST 10 | |
237 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 | |
238 | ||
bad720ff | 239 | /* Ironlake / Sandybridge */ |
2c07245f ZW |
240 | /* as we calculate clock using (register_value + 2) for |
241 | N/M1/M2, so here the range value for them is (actual_value-2). | |
242 | */ | |
f2b115e6 AJ |
243 | #define IRONLAKE_DOT_MIN 25000 |
244 | #define IRONLAKE_DOT_MAX 350000 | |
245 | #define IRONLAKE_VCO_MIN 1760000 | |
246 | #define IRONLAKE_VCO_MAX 3510000 | |
f2b115e6 | 247 | #define IRONLAKE_M1_MIN 12 |
a59e385e | 248 | #define IRONLAKE_M1_MAX 22 |
f2b115e6 AJ |
249 | #define IRONLAKE_M2_MIN 5 |
250 | #define IRONLAKE_M2_MAX 9 | |
f2b115e6 | 251 | #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ |
2c07245f | 252 | |
b91ad0ec ZW |
253 | /* We have parameter ranges for different type of outputs. */ |
254 | ||
255 | /* DAC & HDMI Refclk 120Mhz */ | |
256 | #define IRONLAKE_DAC_N_MIN 1 | |
257 | #define IRONLAKE_DAC_N_MAX 5 | |
258 | #define IRONLAKE_DAC_M_MIN 79 | |
259 | #define IRONLAKE_DAC_M_MAX 127 | |
260 | #define IRONLAKE_DAC_P_MIN 5 | |
261 | #define IRONLAKE_DAC_P_MAX 80 | |
262 | #define IRONLAKE_DAC_P1_MIN 1 | |
263 | #define IRONLAKE_DAC_P1_MAX 8 | |
264 | #define IRONLAKE_DAC_P2_SLOW 10 | |
265 | #define IRONLAKE_DAC_P2_FAST 5 | |
266 | ||
267 | /* LVDS single-channel 120Mhz refclk */ | |
268 | #define IRONLAKE_LVDS_S_N_MIN 1 | |
269 | #define IRONLAKE_LVDS_S_N_MAX 3 | |
270 | #define IRONLAKE_LVDS_S_M_MIN 79 | |
271 | #define IRONLAKE_LVDS_S_M_MAX 118 | |
272 | #define IRONLAKE_LVDS_S_P_MIN 28 | |
273 | #define IRONLAKE_LVDS_S_P_MAX 112 | |
274 | #define IRONLAKE_LVDS_S_P1_MIN 2 | |
275 | #define IRONLAKE_LVDS_S_P1_MAX 8 | |
276 | #define IRONLAKE_LVDS_S_P2_SLOW 14 | |
277 | #define IRONLAKE_LVDS_S_P2_FAST 14 | |
278 | ||
279 | /* LVDS dual-channel 120Mhz refclk */ | |
280 | #define IRONLAKE_LVDS_D_N_MIN 1 | |
281 | #define IRONLAKE_LVDS_D_N_MAX 3 | |
282 | #define IRONLAKE_LVDS_D_M_MIN 79 | |
283 | #define IRONLAKE_LVDS_D_M_MAX 127 | |
284 | #define IRONLAKE_LVDS_D_P_MIN 14 | |
285 | #define IRONLAKE_LVDS_D_P_MAX 56 | |
286 | #define IRONLAKE_LVDS_D_P1_MIN 2 | |
287 | #define IRONLAKE_LVDS_D_P1_MAX 8 | |
288 | #define IRONLAKE_LVDS_D_P2_SLOW 7 | |
289 | #define IRONLAKE_LVDS_D_P2_FAST 7 | |
290 | ||
291 | /* LVDS single-channel 100Mhz refclk */ | |
292 | #define IRONLAKE_LVDS_S_SSC_N_MIN 1 | |
293 | #define IRONLAKE_LVDS_S_SSC_N_MAX 2 | |
294 | #define IRONLAKE_LVDS_S_SSC_M_MIN 79 | |
295 | #define IRONLAKE_LVDS_S_SSC_M_MAX 126 | |
296 | #define IRONLAKE_LVDS_S_SSC_P_MIN 28 | |
297 | #define IRONLAKE_LVDS_S_SSC_P_MAX 112 | |
298 | #define IRONLAKE_LVDS_S_SSC_P1_MIN 2 | |
299 | #define IRONLAKE_LVDS_S_SSC_P1_MAX 8 | |
300 | #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14 | |
301 | #define IRONLAKE_LVDS_S_SSC_P2_FAST 14 | |
302 | ||
303 | /* LVDS dual-channel 100Mhz refclk */ | |
304 | #define IRONLAKE_LVDS_D_SSC_N_MIN 1 | |
305 | #define IRONLAKE_LVDS_D_SSC_N_MAX 3 | |
306 | #define IRONLAKE_LVDS_D_SSC_M_MIN 79 | |
307 | #define IRONLAKE_LVDS_D_SSC_M_MAX 126 | |
308 | #define IRONLAKE_LVDS_D_SSC_P_MIN 14 | |
309 | #define IRONLAKE_LVDS_D_SSC_P_MAX 42 | |
310 | #define IRONLAKE_LVDS_D_SSC_P1_MIN 2 | |
311 | #define IRONLAKE_LVDS_D_SSC_P1_MAX 6 | |
312 | #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7 | |
313 | #define IRONLAKE_LVDS_D_SSC_P2_FAST 7 | |
314 | ||
315 | /* DisplayPort */ | |
316 | #define IRONLAKE_DP_N_MIN 1 | |
317 | #define IRONLAKE_DP_N_MAX 2 | |
318 | #define IRONLAKE_DP_M_MIN 81 | |
319 | #define IRONLAKE_DP_M_MAX 90 | |
320 | #define IRONLAKE_DP_P_MIN 10 | |
321 | #define IRONLAKE_DP_P_MAX 20 | |
322 | #define IRONLAKE_DP_P2_FAST 10 | |
323 | #define IRONLAKE_DP_P2_SLOW 10 | |
324 | #define IRONLAKE_DP_P2_LIMIT 0 | |
325 | #define IRONLAKE_DP_P1_MIN 1 | |
326 | #define IRONLAKE_DP_P1_MAX 2 | |
4547668a | 327 | |
2377b741 JB |
328 | /* FDI */ |
329 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
330 | ||
d4906093 ML |
331 | static bool |
332 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
333 | int target, int refclk, intel_clock_t *best_clock); | |
334 | static bool | |
335 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
336 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 | 337 | |
a4fc5ed6 KP |
338 | static bool |
339 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
340 | int target, int refclk, intel_clock_t *best_clock); | |
5eb08b69 | 341 | static bool |
f2b115e6 AJ |
342 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
343 | int target, int refclk, intel_clock_t *best_clock); | |
a4fc5ed6 | 344 | |
021357ac CW |
345 | static inline u32 /* units of 100MHz */ |
346 | intel_fdi_link_freq(struct drm_device *dev) | |
347 | { | |
8b99e68c CW |
348 | if (IS_GEN5(dev)) { |
349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
350 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
351 | } else | |
352 | return 27; | |
021357ac CW |
353 | } |
354 | ||
e4b36699 | 355 | static const intel_limit_t intel_limits_i8xx_dvo = { |
79e53945 JB |
356 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
357 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
358 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
359 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
360 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
361 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
362 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
363 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
364 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
365 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
d4906093 | 366 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
367 | }; |
368 | ||
369 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
79e53945 JB |
370 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
371 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
372 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
373 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
374 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
375 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
376 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
377 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
378 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
379 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
d4906093 | 380 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
381 | }; |
382 | ||
383 | static const intel_limit_t intel_limits_i9xx_sdvo = { | |
79e53945 JB |
384 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
385 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
386 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
387 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
388 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
389 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
390 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
391 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
392 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
393 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
d4906093 | 394 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
395 | }; |
396 | ||
397 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
79e53945 JB |
398 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
399 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
400 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
401 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
402 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
403 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
404 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
405 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
406 | /* The single-channel range is 25-112Mhz, and dual-channel | |
407 | * is 80-224Mhz. Prefer single channel as much as possible. | |
408 | */ | |
409 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
410 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
d4906093 | 411 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
412 | }; |
413 | ||
044c7c41 | 414 | /* below parameter and function is for G4X Chipset Family*/ |
e4b36699 | 415 | static const intel_limit_t intel_limits_g4x_sdvo = { |
044c7c41 ML |
416 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
417 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
418 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, | |
419 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, | |
420 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, | |
421 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, | |
422 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, | |
423 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, | |
424 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, | |
425 | .p2_slow = G4X_P2_SDVO_SLOW, | |
426 | .p2_fast = G4X_P2_SDVO_FAST | |
427 | }, | |
d4906093 | 428 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
429 | }; |
430 | ||
431 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
044c7c41 ML |
432 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
433 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
434 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, | |
435 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, | |
436 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, | |
437 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, | |
438 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, | |
439 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, | |
440 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, | |
441 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, | |
442 | .p2_fast = G4X_P2_HDMI_DAC_FAST | |
443 | }, | |
d4906093 | 444 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
445 | }; |
446 | ||
447 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
044c7c41 ML |
448 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
449 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, | |
450 | .vco = { .min = G4X_VCO_MIN, | |
451 | .max = G4X_VCO_MAX }, | |
452 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, | |
453 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, | |
454 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, | |
455 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, | |
456 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, | |
457 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, | |
458 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, | |
459 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, | |
460 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, | |
461 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, | |
462 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, | |
463 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, | |
464 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, | |
465 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, | |
466 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST | |
467 | }, | |
d4906093 | 468 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
469 | }; |
470 | ||
471 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
044c7c41 ML |
472 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
473 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, | |
474 | .vco = { .min = G4X_VCO_MIN, | |
475 | .max = G4X_VCO_MAX }, | |
476 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, | |
477 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, | |
478 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, | |
479 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, | |
480 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, | |
481 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, | |
482 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, | |
483 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, | |
484 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, | |
485 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, | |
486 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, | |
487 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, | |
488 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, | |
489 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, | |
490 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST | |
491 | }, | |
d4906093 | 492 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
493 | }; |
494 | ||
495 | static const intel_limit_t intel_limits_g4x_display_port = { | |
a4fc5ed6 KP |
496 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
497 | .max = G4X_DOT_DISPLAY_PORT_MAX }, | |
498 | .vco = { .min = G4X_VCO_MIN, | |
499 | .max = G4X_VCO_MAX}, | |
500 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, | |
501 | .max = G4X_N_DISPLAY_PORT_MAX }, | |
502 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, | |
503 | .max = G4X_M_DISPLAY_PORT_MAX }, | |
504 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, | |
505 | .max = G4X_M1_DISPLAY_PORT_MAX }, | |
506 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, | |
507 | .max = G4X_M2_DISPLAY_PORT_MAX }, | |
508 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, | |
509 | .max = G4X_P_DISPLAY_PORT_MAX }, | |
510 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, | |
511 | .max = G4X_P1_DISPLAY_PORT_MAX}, | |
512 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, | |
513 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, | |
514 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, | |
515 | .find_pll = intel_find_pll_g4x_dp, | |
e4b36699 KP |
516 | }; |
517 | ||
f2b115e6 | 518 | static const intel_limit_t intel_limits_pineview_sdvo = { |
2177832f | 519 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
f2b115e6 AJ |
520 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
521 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
522 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
523 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
524 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
2177832f SL |
525 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
526 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
527 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
528 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
6115707b | 529 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
530 | }; |
531 | ||
f2b115e6 | 532 | static const intel_limit_t intel_limits_pineview_lvds = { |
2177832f | 533 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
f2b115e6 AJ |
534 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
535 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
536 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
537 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
538 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
539 | .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX }, | |
2177832f | 540 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
f2b115e6 | 541 | /* Pineview only supports single-channel mode. */ |
2177832f SL |
542 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
543 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, | |
6115707b | 544 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
545 | }; |
546 | ||
b91ad0ec | 547 | static const intel_limit_t intel_limits_ironlake_dac = { |
f2b115e6 AJ |
548 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
549 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
550 | .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX }, |
551 | .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX }, | |
f2b115e6 AJ |
552 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
553 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
554 | .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX }, |
555 | .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX }, | |
f2b115e6 | 556 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
557 | .p2_slow = IRONLAKE_DAC_P2_SLOW, |
558 | .p2_fast = IRONLAKE_DAC_P2_FAST }, | |
4547668a | 559 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
560 | }; |
561 | ||
b91ad0ec | 562 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
f2b115e6 AJ |
563 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
564 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
565 | .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX }, |
566 | .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX }, | |
f2b115e6 AJ |
567 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
568 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
569 | .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX }, |
570 | .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX }, | |
f2b115e6 | 571 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
572 | .p2_slow = IRONLAKE_LVDS_S_P2_SLOW, |
573 | .p2_fast = IRONLAKE_LVDS_S_P2_FAST }, | |
574 | .find_pll = intel_g4x_find_best_PLL, | |
575 | }; | |
576 | ||
577 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
578 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
579 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
580 | .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX }, | |
581 | .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX }, | |
582 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
583 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
584 | .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX }, | |
585 | .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX }, | |
586 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
587 | .p2_slow = IRONLAKE_LVDS_D_P2_SLOW, | |
588 | .p2_fast = IRONLAKE_LVDS_D_P2_FAST }, | |
589 | .find_pll = intel_g4x_find_best_PLL, | |
590 | }; | |
591 | ||
592 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { | |
593 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
594 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
595 | .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX }, | |
596 | .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX }, | |
597 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
598 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
599 | .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX }, | |
600 | .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX }, | |
601 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
602 | .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW, | |
603 | .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST }, | |
604 | .find_pll = intel_g4x_find_best_PLL, | |
605 | }; | |
606 | ||
607 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
608 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
609 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
610 | .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX }, | |
611 | .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX }, | |
612 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
613 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
614 | .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX }, | |
615 | .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX }, | |
616 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
617 | .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW, | |
618 | .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST }, | |
4547668a ZY |
619 | .find_pll = intel_g4x_find_best_PLL, |
620 | }; | |
621 | ||
622 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
623 | .dot = { .min = IRONLAKE_DOT_MIN, | |
624 | .max = IRONLAKE_DOT_MAX }, | |
625 | .vco = { .min = IRONLAKE_VCO_MIN, | |
626 | .max = IRONLAKE_VCO_MAX}, | |
b91ad0ec ZW |
627 | .n = { .min = IRONLAKE_DP_N_MIN, |
628 | .max = IRONLAKE_DP_N_MAX }, | |
629 | .m = { .min = IRONLAKE_DP_M_MIN, | |
630 | .max = IRONLAKE_DP_M_MAX }, | |
4547668a ZY |
631 | .m1 = { .min = IRONLAKE_M1_MIN, |
632 | .max = IRONLAKE_M1_MAX }, | |
633 | .m2 = { .min = IRONLAKE_M2_MIN, | |
634 | .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
635 | .p = { .min = IRONLAKE_DP_P_MIN, |
636 | .max = IRONLAKE_DP_P_MAX }, | |
637 | .p1 = { .min = IRONLAKE_DP_P1_MIN, | |
638 | .max = IRONLAKE_DP_P1_MAX}, | |
639 | .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT, | |
640 | .p2_slow = IRONLAKE_DP_P2_SLOW, | |
641 | .p2_fast = IRONLAKE_DP_P2_FAST }, | |
4547668a | 642 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
643 | }; |
644 | ||
1b894b59 CW |
645 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
646 | int refclk) | |
2c07245f | 647 | { |
b91ad0ec ZW |
648 | struct drm_device *dev = crtc->dev; |
649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 650 | const intel_limit_t *limit; |
b91ad0ec ZW |
651 | |
652 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b91ad0ec ZW |
653 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
654 | LVDS_CLKB_POWER_UP) { | |
655 | /* LVDS dual channel */ | |
1b894b59 | 656 | if (refclk == 100000) |
b91ad0ec ZW |
657 | limit = &intel_limits_ironlake_dual_lvds_100m; |
658 | else | |
659 | limit = &intel_limits_ironlake_dual_lvds; | |
660 | } else { | |
1b894b59 | 661 | if (refclk == 100000) |
b91ad0ec ZW |
662 | limit = &intel_limits_ironlake_single_lvds_100m; |
663 | else | |
664 | limit = &intel_limits_ironlake_single_lvds; | |
665 | } | |
666 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
667 | HAS_eDP) |
668 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 669 | else |
b91ad0ec | 670 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
671 | |
672 | return limit; | |
673 | } | |
674 | ||
044c7c41 ML |
675 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
676 | { | |
677 | struct drm_device *dev = crtc->dev; | |
678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
679 | const intel_limit_t *limit; | |
680 | ||
681 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
682 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
683 | LVDS_CLKB_POWER_UP) | |
684 | /* LVDS with dual channel */ | |
e4b36699 | 685 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
686 | else |
687 | /* LVDS with dual channel */ | |
e4b36699 | 688 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
689 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
690 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 691 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 692 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 693 | limit = &intel_limits_g4x_sdvo; |
a4fc5ed6 | 694 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 695 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 696 | } else /* The option is for other outputs */ |
e4b36699 | 697 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
698 | |
699 | return limit; | |
700 | } | |
701 | ||
1b894b59 | 702 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
703 | { |
704 | struct drm_device *dev = crtc->dev; | |
705 | const intel_limit_t *limit; | |
706 | ||
bad720ff | 707 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 708 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 709 | else if (IS_G4X(dev)) { |
044c7c41 | 710 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 711 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 712 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 713 | limit = &intel_limits_pineview_lvds; |
2177832f | 714 | else |
f2b115e6 | 715 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
716 | } else if (!IS_GEN2(dev)) { |
717 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
718 | limit = &intel_limits_i9xx_lvds; | |
719 | else | |
720 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
721 | } else { |
722 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 723 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 724 | else |
e4b36699 | 725 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
726 | } |
727 | return limit; | |
728 | } | |
729 | ||
f2b115e6 AJ |
730 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
731 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 732 | { |
2177832f SL |
733 | clock->m = clock->m2 + 2; |
734 | clock->p = clock->p1 * clock->p2; | |
735 | clock->vco = refclk * clock->m / clock->n; | |
736 | clock->dot = clock->vco / clock->p; | |
737 | } | |
738 | ||
739 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
740 | { | |
f2b115e6 AJ |
741 | if (IS_PINEVIEW(dev)) { |
742 | pineview_clock(refclk, clock); | |
2177832f SL |
743 | return; |
744 | } | |
79e53945 JB |
745 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
746 | clock->p = clock->p1 * clock->p2; | |
747 | clock->vco = refclk * clock->m / (clock->n + 2); | |
748 | clock->dot = clock->vco / clock->p; | |
749 | } | |
750 | ||
79e53945 JB |
751 | /** |
752 | * Returns whether any output on the specified pipe is of the specified type | |
753 | */ | |
4ef69c7a | 754 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 755 | { |
4ef69c7a CW |
756 | struct drm_device *dev = crtc->dev; |
757 | struct drm_mode_config *mode_config = &dev->mode_config; | |
758 | struct intel_encoder *encoder; | |
759 | ||
760 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
761 | if (encoder->base.crtc == crtc && encoder->type == type) | |
762 | return true; | |
763 | ||
764 | return false; | |
79e53945 JB |
765 | } |
766 | ||
7c04d1d9 | 767 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
768 | /** |
769 | * Returns whether the given set of divisors are valid for a given refclk with | |
770 | * the given connectors. | |
771 | */ | |
772 | ||
1b894b59 CW |
773 | static bool intel_PLL_is_valid(struct drm_device *dev, |
774 | const intel_limit_t *limit, | |
775 | const intel_clock_t *clock) | |
79e53945 | 776 | { |
79e53945 JB |
777 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
778 | INTELPllInvalid ("p1 out of range\n"); | |
779 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
780 | INTELPllInvalid ("p out of range\n"); | |
781 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
782 | INTELPllInvalid ("m2 out of range\n"); | |
783 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
784 | INTELPllInvalid ("m1 out of range\n"); | |
f2b115e6 | 785 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
79e53945 JB |
786 | INTELPllInvalid ("m1 <= m2\n"); |
787 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
788 | INTELPllInvalid ("m out of range\n"); | |
789 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
790 | INTELPllInvalid ("n out of range\n"); | |
791 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
792 | INTELPllInvalid ("vco out of range\n"); | |
793 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
794 | * connector, etc., rather than just a single range. | |
795 | */ | |
796 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
797 | INTELPllInvalid ("dot out of range\n"); | |
798 | ||
799 | return true; | |
800 | } | |
801 | ||
d4906093 ML |
802 | static bool |
803 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
804 | int target, int refclk, intel_clock_t *best_clock) | |
805 | ||
79e53945 JB |
806 | { |
807 | struct drm_device *dev = crtc->dev; | |
808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
809 | intel_clock_t clock; | |
79e53945 JB |
810 | int err = target; |
811 | ||
bc5e5718 | 812 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 813 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
814 | /* |
815 | * For LVDS, if the panel is on, just rely on its current | |
816 | * settings for dual-channel. We haven't figured out how to | |
817 | * reliably set up different single/dual channel state, if we | |
818 | * even can. | |
819 | */ | |
820 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
821 | LVDS_CLKB_POWER_UP) | |
822 | clock.p2 = limit->p2.p2_fast; | |
823 | else | |
824 | clock.p2 = limit->p2.p2_slow; | |
825 | } else { | |
826 | if (target < limit->p2.dot_limit) | |
827 | clock.p2 = limit->p2.p2_slow; | |
828 | else | |
829 | clock.p2 = limit->p2.p2_fast; | |
830 | } | |
831 | ||
832 | memset (best_clock, 0, sizeof (*best_clock)); | |
833 | ||
42158660 ZY |
834 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
835 | clock.m1++) { | |
836 | for (clock.m2 = limit->m2.min; | |
837 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
838 | /* m1 is always 0 in Pineview */ |
839 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
840 | break; |
841 | for (clock.n = limit->n.min; | |
842 | clock.n <= limit->n.max; clock.n++) { | |
843 | for (clock.p1 = limit->p1.min; | |
844 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
845 | int this_err; |
846 | ||
2177832f | 847 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
848 | if (!intel_PLL_is_valid(dev, limit, |
849 | &clock)) | |
79e53945 JB |
850 | continue; |
851 | ||
852 | this_err = abs(clock.dot - target); | |
853 | if (this_err < err) { | |
854 | *best_clock = clock; | |
855 | err = this_err; | |
856 | } | |
857 | } | |
858 | } | |
859 | } | |
860 | } | |
861 | ||
862 | return (err != target); | |
863 | } | |
864 | ||
d4906093 ML |
865 | static bool |
866 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
867 | int target, int refclk, intel_clock_t *best_clock) | |
868 | { | |
869 | struct drm_device *dev = crtc->dev; | |
870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
871 | intel_clock_t clock; | |
872 | int max_n; | |
873 | bool found; | |
6ba770dc AJ |
874 | /* approximately equals target * 0.00585 */ |
875 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
876 | found = false; |
877 | ||
878 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
879 | int lvds_reg; |
880 | ||
c619eed4 | 881 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
882 | lvds_reg = PCH_LVDS; |
883 | else | |
884 | lvds_reg = LVDS; | |
885 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
886 | LVDS_CLKB_POWER_UP) |
887 | clock.p2 = limit->p2.p2_fast; | |
888 | else | |
889 | clock.p2 = limit->p2.p2_slow; | |
890 | } else { | |
891 | if (target < limit->p2.dot_limit) | |
892 | clock.p2 = limit->p2.p2_slow; | |
893 | else | |
894 | clock.p2 = limit->p2.p2_fast; | |
895 | } | |
896 | ||
897 | memset(best_clock, 0, sizeof(*best_clock)); | |
898 | max_n = limit->n.max; | |
f77f13e2 | 899 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 900 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 901 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
902 | for (clock.m1 = limit->m1.max; |
903 | clock.m1 >= limit->m1.min; clock.m1--) { | |
904 | for (clock.m2 = limit->m2.max; | |
905 | clock.m2 >= limit->m2.min; clock.m2--) { | |
906 | for (clock.p1 = limit->p1.max; | |
907 | clock.p1 >= limit->p1.min; clock.p1--) { | |
908 | int this_err; | |
909 | ||
2177832f | 910 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
911 | if (!intel_PLL_is_valid(dev, limit, |
912 | &clock)) | |
d4906093 | 913 | continue; |
1b894b59 CW |
914 | |
915 | this_err = abs(clock.dot - target); | |
d4906093 ML |
916 | if (this_err < err_most) { |
917 | *best_clock = clock; | |
918 | err_most = this_err; | |
919 | max_n = clock.n; | |
920 | found = true; | |
921 | } | |
922 | } | |
923 | } | |
924 | } | |
925 | } | |
2c07245f ZW |
926 | return found; |
927 | } | |
928 | ||
5eb08b69 | 929 | static bool |
f2b115e6 AJ |
930 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
931 | int target, int refclk, intel_clock_t *best_clock) | |
5eb08b69 ZW |
932 | { |
933 | struct drm_device *dev = crtc->dev; | |
934 | intel_clock_t clock; | |
4547668a | 935 | |
5eb08b69 ZW |
936 | if (target < 200000) { |
937 | clock.n = 1; | |
938 | clock.p1 = 2; | |
939 | clock.p2 = 10; | |
940 | clock.m1 = 12; | |
941 | clock.m2 = 9; | |
942 | } else { | |
943 | clock.n = 2; | |
944 | clock.p1 = 1; | |
945 | clock.p2 = 10; | |
946 | clock.m1 = 14; | |
947 | clock.m2 = 8; | |
948 | } | |
949 | intel_clock(dev, refclk, &clock); | |
950 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
951 | return true; | |
952 | } | |
953 | ||
a4fc5ed6 KP |
954 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
955 | static bool | |
956 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
957 | int target, int refclk, intel_clock_t *best_clock) | |
958 | { | |
5eddb70b CW |
959 | intel_clock_t clock; |
960 | if (target < 200000) { | |
961 | clock.p1 = 2; | |
962 | clock.p2 = 10; | |
963 | clock.n = 2; | |
964 | clock.m1 = 23; | |
965 | clock.m2 = 8; | |
966 | } else { | |
967 | clock.p1 = 1; | |
968 | clock.p2 = 10; | |
969 | clock.n = 1; | |
970 | clock.m1 = 14; | |
971 | clock.m2 = 2; | |
972 | } | |
973 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
974 | clock.p = (clock.p1 * clock.p2); | |
975 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
976 | clock.vco = 0; | |
977 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
978 | return true; | |
a4fc5ed6 KP |
979 | } |
980 | ||
9d0498a2 JB |
981 | /** |
982 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
983 | * @dev: drm device | |
984 | * @pipe: pipe to wait for | |
985 | * | |
986 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
987 | * mode setting code. | |
988 | */ | |
989 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 990 | { |
9d0498a2 JB |
991 | struct drm_i915_private *dev_priv = dev->dev_private; |
992 | int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT); | |
993 | ||
300387c0 CW |
994 | /* Clear existing vblank status. Note this will clear any other |
995 | * sticky status fields as well. | |
996 | * | |
997 | * This races with i915_driver_irq_handler() with the result | |
998 | * that either function could miss a vblank event. Here it is not | |
999 | * fatal, as we will either wait upon the next vblank interrupt or | |
1000 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
1001 | * called during modeset at which time the GPU should be idle and | |
1002 | * should *not* be performing page flips and thus not waiting on | |
1003 | * vblanks... | |
1004 | * Currently, the result of us stealing a vblank from the irq | |
1005 | * handler is that a single frame will be skipped during swapbuffers. | |
1006 | */ | |
1007 | I915_WRITE(pipestat_reg, | |
1008 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
1009 | ||
9d0498a2 | 1010 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
1011 | if (wait_for(I915_READ(pipestat_reg) & |
1012 | PIPE_VBLANK_INTERRUPT_STATUS, | |
1013 | 50)) | |
9d0498a2 JB |
1014 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
1015 | } | |
1016 | ||
ab7ad7f6 KP |
1017 | /* |
1018 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
1019 | * @dev: drm device |
1020 | * @pipe: pipe to wait for | |
1021 | * | |
1022 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1023 | * spinning on the vblank interrupt status bit, since we won't actually | |
1024 | * see an interrupt when the pipe is disabled. | |
1025 | * | |
ab7ad7f6 KP |
1026 | * On Gen4 and above: |
1027 | * wait for the pipe register state bit to turn off | |
1028 | * | |
1029 | * Otherwise: | |
1030 | * wait for the display line value to settle (it usually | |
1031 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1032 | * |
9d0498a2 | 1033 | */ |
58e10eb9 | 1034 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
1035 | { |
1036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
1037 | |
1038 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 1039 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
1040 | |
1041 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1042 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1043 | 100)) | |
ab7ad7f6 KP |
1044 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
1045 | } else { | |
1046 | u32 last_line; | |
58e10eb9 | 1047 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
1048 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
1049 | ||
1050 | /* Wait for the display line to settle */ | |
1051 | do { | |
58e10eb9 | 1052 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 1053 | mdelay(5); |
58e10eb9 | 1054 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
1055 | time_after(timeout, jiffies)); |
1056 | if (time_after(jiffies, timeout)) | |
1057 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
1058 | } | |
79e53945 JB |
1059 | } |
1060 | ||
b24e7179 JB |
1061 | static const char *state_string(bool enabled) |
1062 | { | |
1063 | return enabled ? "on" : "off"; | |
1064 | } | |
1065 | ||
1066 | /* Only for pre-ILK configs */ | |
1067 | static void assert_pll(struct drm_i915_private *dev_priv, | |
1068 | enum pipe pipe, bool state) | |
1069 | { | |
1070 | int reg; | |
1071 | u32 val; | |
1072 | bool cur_state; | |
1073 | ||
1074 | reg = DPLL(pipe); | |
1075 | val = I915_READ(reg); | |
1076 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1077 | WARN(cur_state != state, | |
1078 | "PLL state assertion failure (expected %s, current %s)\n", | |
1079 | state_string(state), state_string(cur_state)); | |
1080 | } | |
1081 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1082 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
1083 | ||
1084 | static void assert_pipe_enabled(struct drm_i915_private *dev_priv, | |
1085 | enum pipe pipe) | |
1086 | { | |
1087 | int reg; | |
1088 | u32 val; | |
1089 | ||
1090 | reg = PIPECONF(pipe); | |
1091 | val = I915_READ(reg); | |
1092 | WARN(!(val & PIPECONF_ENABLE), | |
1093 | "pipe %c assertion failure, should be active but is disabled\n", | |
1094 | pipe ? 'B' : 'A'); | |
1095 | } | |
1096 | ||
1097 | static void assert_plane_enabled(struct drm_i915_private *dev_priv, | |
1098 | enum plane plane) | |
1099 | { | |
1100 | int reg; | |
1101 | u32 val; | |
1102 | ||
1103 | reg = DSPCNTR(plane); | |
1104 | val = I915_READ(reg); | |
1105 | WARN(!(val & DISPLAY_PLANE_ENABLE), | |
1106 | "plane %c assertion failure, should be active but is disabled\n", | |
1107 | plane ? 'B' : 'A'); | |
1108 | } | |
1109 | ||
1110 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, | |
1111 | enum pipe pipe) | |
1112 | { | |
1113 | int reg, i; | |
1114 | u32 val; | |
1115 | int cur_pipe; | |
1116 | ||
1117 | /* Need to check both planes against the pipe */ | |
1118 | for (i = 0; i < 2; i++) { | |
1119 | reg = DSPCNTR(i); | |
1120 | val = I915_READ(reg); | |
1121 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1122 | DISPPLANE_SEL_PIPE_SHIFT; | |
1123 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
1124 | "plane %d assertion failure, should be off on pipe %c but is still active\n", | |
1125 | i, pipe ? 'B' : 'A'); | |
1126 | } | |
1127 | } | |
1128 | ||
1129 | /** | |
1130 | * intel_enable_pipe - enable a pipe, assertiing requirements | |
1131 | * @dev_priv: i915 private structure | |
1132 | * @pipe: pipe to enable | |
1133 | * | |
1134 | * Enable @pipe, making sure that various hardware specific requirements | |
1135 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1136 | * | |
1137 | * @pipe should be %PIPE_A or %PIPE_B. | |
1138 | * | |
1139 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1140 | * returning. | |
1141 | */ | |
1142 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1143 | { | |
1144 | int reg; | |
1145 | u32 val; | |
1146 | ||
1147 | /* | |
1148 | * A pipe without a PLL won't actually be able to drive bits from | |
1149 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1150 | * need the check. | |
1151 | */ | |
1152 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1153 | assert_pll_enabled(dev_priv, pipe); | |
1154 | ||
1155 | reg = PIPECONF(pipe); | |
1156 | val = I915_READ(reg); | |
1157 | val |= PIPECONF_ENABLE; | |
1158 | I915_WRITE(reg, val); | |
1159 | POSTING_READ(reg); | |
1160 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1161 | } | |
1162 | ||
1163 | /** | |
1164 | * intel_disable_pipe - disable a pipe, assertiing requirements | |
1165 | * @dev_priv: i915 private structure | |
1166 | * @pipe: pipe to disable | |
1167 | * | |
1168 | * Disable @pipe, making sure that various hardware specific requirements | |
1169 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1170 | * | |
1171 | * @pipe should be %PIPE_A or %PIPE_B. | |
1172 | * | |
1173 | * Will wait until the pipe has shut down before returning. | |
1174 | */ | |
1175 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1176 | enum pipe pipe) | |
1177 | { | |
1178 | int reg; | |
1179 | u32 val; | |
1180 | ||
1181 | /* | |
1182 | * Make sure planes won't keep trying to pump pixels to us, | |
1183 | * or we might hang the display. | |
1184 | */ | |
1185 | assert_planes_disabled(dev_priv, pipe); | |
1186 | ||
1187 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1188 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1189 | return; | |
1190 | ||
1191 | reg = PIPECONF(pipe); | |
1192 | val = I915_READ(reg); | |
1193 | val &= ~PIPECONF_ENABLE; | |
1194 | I915_WRITE(reg, val); | |
1195 | POSTING_READ(reg); | |
1196 | intel_wait_for_pipe_off(dev_priv->dev, pipe); | |
1197 | } | |
1198 | ||
1199 | /** | |
1200 | * intel_enable_plane - enable a display plane on a given pipe | |
1201 | * @dev_priv: i915 private structure | |
1202 | * @plane: plane to enable | |
1203 | * @pipe: pipe being fed | |
1204 | * | |
1205 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1206 | */ | |
1207 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1208 | enum plane plane, enum pipe pipe) | |
1209 | { | |
1210 | int reg; | |
1211 | u32 val; | |
1212 | ||
1213 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1214 | assert_pipe_enabled(dev_priv, pipe); | |
1215 | ||
1216 | reg = DSPCNTR(plane); | |
1217 | val = I915_READ(reg); | |
1218 | val |= DISPLAY_PLANE_ENABLE; | |
1219 | I915_WRITE(reg, val); | |
1220 | POSTING_READ(reg); | |
1221 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1222 | } | |
1223 | ||
1224 | /* | |
1225 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1226 | * trigger in order to latch. The display address reg provides this. | |
1227 | */ | |
1228 | static void intel_flush_display_plane(struct drm_i915_private *dev_priv, | |
1229 | enum plane plane) | |
1230 | { | |
1231 | u32 reg = DSPADDR(plane); | |
1232 | I915_WRITE(reg, I915_READ(reg)); | |
1233 | } | |
1234 | ||
1235 | /** | |
1236 | * intel_disable_plane - disable a display plane | |
1237 | * @dev_priv: i915 private structure | |
1238 | * @plane: plane to disable | |
1239 | * @pipe: pipe consuming the data | |
1240 | * | |
1241 | * Disable @plane; should be an independent operation. | |
1242 | */ | |
1243 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1244 | enum plane plane, enum pipe pipe) | |
1245 | { | |
1246 | int reg; | |
1247 | u32 val; | |
1248 | ||
1249 | reg = DSPCNTR(plane); | |
1250 | val = I915_READ(reg); | |
1251 | val &= ~DISPLAY_PLANE_ENABLE; | |
1252 | I915_WRITE(reg, val); | |
1253 | POSTING_READ(reg); | |
1254 | intel_flush_display_plane(dev_priv, plane); | |
1255 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1256 | } | |
1257 | ||
80824003 JB |
1258 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1259 | { | |
1260 | struct drm_device *dev = crtc->dev; | |
1261 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1262 | struct drm_framebuffer *fb = crtc->fb; | |
1263 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1264 | struct drm_i915_gem_object *obj = intel_fb->obj; |
80824003 JB |
1265 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1266 | int plane, i; | |
1267 | u32 fbc_ctl, fbc_ctl2; | |
1268 | ||
bed4a673 | 1269 | if (fb->pitch == dev_priv->cfb_pitch && |
05394f39 | 1270 | obj->fence_reg == dev_priv->cfb_fence && |
bed4a673 CW |
1271 | intel_crtc->plane == dev_priv->cfb_plane && |
1272 | I915_READ(FBC_CONTROL) & FBC_CTL_EN) | |
1273 | return; | |
1274 | ||
1275 | i8xx_disable_fbc(dev); | |
1276 | ||
80824003 JB |
1277 | dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
1278 | ||
1279 | if (fb->pitch < dev_priv->cfb_pitch) | |
1280 | dev_priv->cfb_pitch = fb->pitch; | |
1281 | ||
1282 | /* FBC_CTL wants 64B units */ | |
1283 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; | |
05394f39 | 1284 | dev_priv->cfb_fence = obj->fence_reg; |
80824003 JB |
1285 | dev_priv->cfb_plane = intel_crtc->plane; |
1286 | plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
1287 | ||
1288 | /* Clear old tags */ | |
1289 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1290 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1291 | ||
1292 | /* Set it up... */ | |
1293 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane; | |
05394f39 | 1294 | if (obj->tiling_mode != I915_TILING_NONE) |
80824003 JB |
1295 | fbc_ctl2 |= FBC_CTL_CPU_FENCE; |
1296 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
1297 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1298 | ||
1299 | /* enable it... */ | |
1300 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1301 | if (IS_I945GM(dev)) |
49677901 | 1302 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
80824003 JB |
1303 | fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
1304 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; | |
05394f39 | 1305 | if (obj->tiling_mode != I915_TILING_NONE) |
80824003 JB |
1306 | fbc_ctl |= dev_priv->cfb_fence; |
1307 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1308 | ||
28c97730 | 1309 | DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ", |
5eddb70b | 1310 | dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); |
80824003 JB |
1311 | } |
1312 | ||
1313 | void i8xx_disable_fbc(struct drm_device *dev) | |
1314 | { | |
1315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1316 | u32 fbc_ctl; | |
1317 | ||
1318 | /* Disable compression */ | |
1319 | fbc_ctl = I915_READ(FBC_CONTROL); | |
a5cad620 CW |
1320 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
1321 | return; | |
1322 | ||
80824003 JB |
1323 | fbc_ctl &= ~FBC_CTL_EN; |
1324 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1325 | ||
1326 | /* Wait for compressing bit to clear */ | |
481b6af3 | 1327 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
913d8d11 CW |
1328 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
1329 | return; | |
9517a92f | 1330 | } |
80824003 | 1331 | |
28c97730 | 1332 | DRM_DEBUG_KMS("disabled FBC\n"); |
80824003 JB |
1333 | } |
1334 | ||
ee5382ae | 1335 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1336 | { |
80824003 JB |
1337 | struct drm_i915_private *dev_priv = dev->dev_private; |
1338 | ||
1339 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1340 | } | |
1341 | ||
74dff282 JB |
1342 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1343 | { | |
1344 | struct drm_device *dev = crtc->dev; | |
1345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1346 | struct drm_framebuffer *fb = crtc->fb; | |
1347 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1348 | struct drm_i915_gem_object *obj = intel_fb->obj; |
74dff282 | 1349 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1350 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1351 | unsigned long stall_watermark = 200; |
1352 | u32 dpfc_ctl; | |
1353 | ||
bed4a673 CW |
1354 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
1355 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1356 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
05394f39 | 1357 | dev_priv->cfb_fence == obj->fence_reg && |
bed4a673 CW |
1358 | dev_priv->cfb_plane == intel_crtc->plane && |
1359 | dev_priv->cfb_y == crtc->y) | |
1360 | return; | |
1361 | ||
1362 | I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
1363 | POSTING_READ(DPFC_CONTROL); | |
1364 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1365 | } | |
1366 | ||
74dff282 | 1367 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
05394f39 | 1368 | dev_priv->cfb_fence = obj->fence_reg; |
74dff282 | 1369 | dev_priv->cfb_plane = intel_crtc->plane; |
bed4a673 | 1370 | dev_priv->cfb_y = crtc->y; |
74dff282 JB |
1371 | |
1372 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; | |
05394f39 | 1373 | if (obj->tiling_mode != I915_TILING_NONE) { |
74dff282 JB |
1374 | dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence; |
1375 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1376 | } else { | |
1377 | I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1378 | } | |
1379 | ||
74dff282 JB |
1380 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1381 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1382 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1383 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1384 | ||
1385 | /* enable it... */ | |
1386 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1387 | ||
28c97730 | 1388 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1389 | } |
1390 | ||
1391 | void g4x_disable_fbc(struct drm_device *dev) | |
1392 | { | |
1393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1394 | u32 dpfc_ctl; | |
1395 | ||
1396 | /* Disable compression */ | |
1397 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1398 | if (dpfc_ctl & DPFC_CTL_EN) { |
1399 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1400 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1401 | |
bed4a673 CW |
1402 | DRM_DEBUG_KMS("disabled FBC\n"); |
1403 | } | |
74dff282 JB |
1404 | } |
1405 | ||
ee5382ae | 1406 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1407 | { |
74dff282 JB |
1408 | struct drm_i915_private *dev_priv = dev->dev_private; |
1409 | ||
1410 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1411 | } | |
1412 | ||
b52eb4dc ZY |
1413 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1414 | { | |
1415 | struct drm_device *dev = crtc->dev; | |
1416 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1417 | struct drm_framebuffer *fb = crtc->fb; | |
1418 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1419 | struct drm_i915_gem_object *obj = intel_fb->obj; |
b52eb4dc | 1420 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1421 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1422 | unsigned long stall_watermark = 200; |
1423 | u32 dpfc_ctl; | |
1424 | ||
bed4a673 CW |
1425 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
1426 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1427 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
05394f39 | 1428 | dev_priv->cfb_fence == obj->fence_reg && |
bed4a673 | 1429 | dev_priv->cfb_plane == intel_crtc->plane && |
05394f39 | 1430 | dev_priv->cfb_offset == obj->gtt_offset && |
bed4a673 CW |
1431 | dev_priv->cfb_y == crtc->y) |
1432 | return; | |
1433 | ||
1434 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
1435 | POSTING_READ(ILK_DPFC_CONTROL); | |
1436 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1437 | } | |
1438 | ||
b52eb4dc | 1439 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
05394f39 | 1440 | dev_priv->cfb_fence = obj->fence_reg; |
b52eb4dc | 1441 | dev_priv->cfb_plane = intel_crtc->plane; |
05394f39 | 1442 | dev_priv->cfb_offset = obj->gtt_offset; |
bed4a673 | 1443 | dev_priv->cfb_y = crtc->y; |
b52eb4dc | 1444 | |
b52eb4dc ZY |
1445 | dpfc_ctl &= DPFC_RESERVED; |
1446 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
05394f39 | 1447 | if (obj->tiling_mode != I915_TILING_NONE) { |
b52eb4dc ZY |
1448 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence); |
1449 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1450 | } else { | |
1451 | I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1452 | } | |
1453 | ||
b52eb4dc ZY |
1454 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1455 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1456 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1457 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
05394f39 | 1458 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
b52eb4dc | 1459 | /* enable it... */ |
bed4a673 | 1460 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc | 1461 | |
9c04f015 YL |
1462 | if (IS_GEN6(dev)) { |
1463 | I915_WRITE(SNB_DPFC_CTL_SA, | |
1464 | SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence); | |
1465 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
1466 | } | |
1467 | ||
b52eb4dc ZY |
1468 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
1469 | } | |
1470 | ||
1471 | void ironlake_disable_fbc(struct drm_device *dev) | |
1472 | { | |
1473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1474 | u32 dpfc_ctl; | |
1475 | ||
1476 | /* Disable compression */ | |
1477 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1478 | if (dpfc_ctl & DPFC_CTL_EN) { |
1479 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1480 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1481 | |
bed4a673 CW |
1482 | DRM_DEBUG_KMS("disabled FBC\n"); |
1483 | } | |
b52eb4dc ZY |
1484 | } |
1485 | ||
1486 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1487 | { | |
1488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1489 | ||
1490 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1491 | } | |
1492 | ||
ee5382ae AJ |
1493 | bool intel_fbc_enabled(struct drm_device *dev) |
1494 | { | |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1496 | ||
1497 | if (!dev_priv->display.fbc_enabled) | |
1498 | return false; | |
1499 | ||
1500 | return dev_priv->display.fbc_enabled(dev); | |
1501 | } | |
1502 | ||
1503 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
1504 | { | |
1505 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1506 | ||
1507 | if (!dev_priv->display.enable_fbc) | |
1508 | return; | |
1509 | ||
1510 | dev_priv->display.enable_fbc(crtc, interval); | |
1511 | } | |
1512 | ||
1513 | void intel_disable_fbc(struct drm_device *dev) | |
1514 | { | |
1515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1516 | ||
1517 | if (!dev_priv->display.disable_fbc) | |
1518 | return; | |
1519 | ||
1520 | dev_priv->display.disable_fbc(dev); | |
1521 | } | |
1522 | ||
80824003 JB |
1523 | /** |
1524 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1525 | * @dev: the drm_device |
80824003 JB |
1526 | * |
1527 | * Set up the framebuffer compression hardware at mode set time. We | |
1528 | * enable it if possible: | |
1529 | * - plane A only (on pre-965) | |
1530 | * - no pixel mulitply/line duplication | |
1531 | * - no alpha buffer discard | |
1532 | * - no dual wide | |
1533 | * - framebuffer <= 2048 in width, 1536 in height | |
1534 | * | |
1535 | * We can't assume that any compression will take place (worst case), | |
1536 | * so the compressed buffer has to be the same size as the uncompressed | |
1537 | * one. It also must reside (along with the line length buffer) in | |
1538 | * stolen memory. | |
1539 | * | |
1540 | * We need to enable/disable FBC on a global basis. | |
1541 | */ | |
bed4a673 | 1542 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1543 | { |
80824003 | 1544 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1545 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1546 | struct intel_crtc *intel_crtc; | |
1547 | struct drm_framebuffer *fb; | |
80824003 | 1548 | struct intel_framebuffer *intel_fb; |
05394f39 | 1549 | struct drm_i915_gem_object *obj; |
9c928d16 JB |
1550 | |
1551 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1552 | |
1553 | if (!i915_powersave) | |
1554 | return; | |
1555 | ||
ee5382ae | 1556 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1557 | return; |
1558 | ||
80824003 JB |
1559 | /* |
1560 | * If FBC is already on, we just have to verify that we can | |
1561 | * keep it that way... | |
1562 | * Need to disable if: | |
9c928d16 | 1563 | * - more than one pipe is active |
80824003 JB |
1564 | * - changing FBC params (stride, fence, mode) |
1565 | * - new fb is too large to fit in compressed buffer | |
1566 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1567 | */ | |
9c928d16 | 1568 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
bed4a673 CW |
1569 | if (tmp_crtc->enabled) { |
1570 | if (crtc) { | |
1571 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1572 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1573 | goto out_disable; | |
1574 | } | |
1575 | crtc = tmp_crtc; | |
1576 | } | |
9c928d16 | 1577 | } |
bed4a673 CW |
1578 | |
1579 | if (!crtc || crtc->fb == NULL) { | |
1580 | DRM_DEBUG_KMS("no output, disabling\n"); | |
1581 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
1582 | goto out_disable; |
1583 | } | |
bed4a673 CW |
1584 | |
1585 | intel_crtc = to_intel_crtc(crtc); | |
1586 | fb = crtc->fb; | |
1587 | intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1588 | obj = intel_fb->obj; |
bed4a673 | 1589 | |
05394f39 | 1590 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
28c97730 | 1591 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 1592 | "compression\n"); |
b5e50c3f | 1593 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1594 | goto out_disable; |
1595 | } | |
bed4a673 CW |
1596 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
1597 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 1598 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 1599 | "disabling\n"); |
b5e50c3f | 1600 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
1601 | goto out_disable; |
1602 | } | |
bed4a673 CW |
1603 | if ((crtc->mode.hdisplay > 2048) || |
1604 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 1605 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 1606 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
1607 | goto out_disable; |
1608 | } | |
bed4a673 | 1609 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 1610 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 1611 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
1612 | goto out_disable; |
1613 | } | |
05394f39 | 1614 | if (obj->tiling_mode != I915_TILING_X) { |
28c97730 | 1615 | DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); |
b5e50c3f | 1616 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
1617 | goto out_disable; |
1618 | } | |
1619 | ||
c924b934 JW |
1620 | /* If the kernel debugger is active, always disable compression */ |
1621 | if (in_dbg_master()) | |
1622 | goto out_disable; | |
1623 | ||
bed4a673 | 1624 | intel_enable_fbc(crtc, 500); |
80824003 JB |
1625 | return; |
1626 | ||
1627 | out_disable: | |
80824003 | 1628 | /* Multiple disables should be harmless */ |
a939406f CW |
1629 | if (intel_fbc_enabled(dev)) { |
1630 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 1631 | intel_disable_fbc(dev); |
a939406f | 1632 | } |
80824003 JB |
1633 | } |
1634 | ||
127bd2ac | 1635 | int |
48b956c5 | 1636 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1637 | struct drm_i915_gem_object *obj, |
919926ae | 1638 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1639 | { |
6b95a207 KH |
1640 | u32 alignment; |
1641 | int ret; | |
1642 | ||
05394f39 | 1643 | switch (obj->tiling_mode) { |
6b95a207 | 1644 | case I915_TILING_NONE: |
534843da CW |
1645 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1646 | alignment = 128 * 1024; | |
a6c45cf0 | 1647 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1648 | alignment = 4 * 1024; |
1649 | else | |
1650 | alignment = 64 * 1024; | |
6b95a207 KH |
1651 | break; |
1652 | case I915_TILING_X: | |
1653 | /* pin() will align the object as required by fence */ | |
1654 | alignment = 0; | |
1655 | break; | |
1656 | case I915_TILING_Y: | |
1657 | /* FIXME: Is this true? */ | |
1658 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1659 | return -EINVAL; | |
1660 | default: | |
1661 | BUG(); | |
1662 | } | |
1663 | ||
75e9e915 | 1664 | ret = i915_gem_object_pin(obj, alignment, true); |
48b956c5 | 1665 | if (ret) |
6b95a207 KH |
1666 | return ret; |
1667 | ||
48b956c5 CW |
1668 | ret = i915_gem_object_set_to_display_plane(obj, pipelined); |
1669 | if (ret) | |
1670 | goto err_unpin; | |
7213342d | 1671 | |
6b95a207 KH |
1672 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1673 | * fence, whereas 965+ only requires a fence if using | |
1674 | * framebuffer compression. For simplicity, we always install | |
1675 | * a fence as the cost is not that onerous. | |
1676 | */ | |
05394f39 | 1677 | if (obj->tiling_mode != I915_TILING_NONE) { |
d9e86c0e | 1678 | ret = i915_gem_object_get_fence(obj, pipelined, false); |
48b956c5 CW |
1679 | if (ret) |
1680 | goto err_unpin; | |
6b95a207 KH |
1681 | } |
1682 | ||
1683 | return 0; | |
48b956c5 CW |
1684 | |
1685 | err_unpin: | |
1686 | i915_gem_object_unpin(obj); | |
1687 | return ret; | |
6b95a207 KH |
1688 | } |
1689 | ||
81255565 JB |
1690 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
1691 | static int | |
1692 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
21c74a8e | 1693 | int x, int y, enum mode_set_atomic state) |
81255565 JB |
1694 | { |
1695 | struct drm_device *dev = crtc->dev; | |
1696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1697 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1698 | struct intel_framebuffer *intel_fb; | |
05394f39 | 1699 | struct drm_i915_gem_object *obj; |
81255565 JB |
1700 | int plane = intel_crtc->plane; |
1701 | unsigned long Start, Offset; | |
81255565 | 1702 | u32 dspcntr; |
5eddb70b | 1703 | u32 reg; |
81255565 JB |
1704 | |
1705 | switch (plane) { | |
1706 | case 0: | |
1707 | case 1: | |
1708 | break; | |
1709 | default: | |
1710 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
1711 | return -EINVAL; | |
1712 | } | |
1713 | ||
1714 | intel_fb = to_intel_framebuffer(fb); | |
1715 | obj = intel_fb->obj; | |
81255565 | 1716 | |
5eddb70b CW |
1717 | reg = DSPCNTR(plane); |
1718 | dspcntr = I915_READ(reg); | |
81255565 JB |
1719 | /* Mask out pixel format bits in case we change it */ |
1720 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
1721 | switch (fb->bits_per_pixel) { | |
1722 | case 8: | |
1723 | dspcntr |= DISPPLANE_8BPP; | |
1724 | break; | |
1725 | case 16: | |
1726 | if (fb->depth == 15) | |
1727 | dspcntr |= DISPPLANE_15_16BPP; | |
1728 | else | |
1729 | dspcntr |= DISPPLANE_16BPP; | |
1730 | break; | |
1731 | case 24: | |
1732 | case 32: | |
1733 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
1734 | break; | |
1735 | default: | |
1736 | DRM_ERROR("Unknown color depth\n"); | |
1737 | return -EINVAL; | |
1738 | } | |
a6c45cf0 | 1739 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 1740 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
1741 | dspcntr |= DISPPLANE_TILED; |
1742 | else | |
1743 | dspcntr &= ~DISPPLANE_TILED; | |
1744 | } | |
1745 | ||
4e6cfefc | 1746 | if (HAS_PCH_SPLIT(dev)) |
81255565 JB |
1747 | /* must disable */ |
1748 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
1749 | ||
5eddb70b | 1750 | I915_WRITE(reg, dspcntr); |
81255565 | 1751 | |
05394f39 | 1752 | Start = obj->gtt_offset; |
81255565 JB |
1753 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); |
1754 | ||
4e6cfefc CW |
1755 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
1756 | Start, Offset, x, y, fb->pitch); | |
5eddb70b | 1757 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); |
a6c45cf0 | 1758 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
1759 | I915_WRITE(DSPSURF(plane), Start); |
1760 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
1761 | I915_WRITE(DSPADDR(plane), Offset); | |
1762 | } else | |
1763 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
1764 | POSTING_READ(reg); | |
81255565 | 1765 | |
bed4a673 | 1766 | intel_update_fbc(dev); |
3dec0095 | 1767 | intel_increase_pllclock(crtc); |
81255565 JB |
1768 | |
1769 | return 0; | |
1770 | } | |
1771 | ||
5c3b82e2 | 1772 | static int |
3c4fdcfb KH |
1773 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
1774 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
1775 | { |
1776 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
1777 | struct drm_i915_master_private *master_priv; |
1778 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 1779 | int ret; |
79e53945 JB |
1780 | |
1781 | /* no fb bound */ | |
1782 | if (!crtc->fb) { | |
28c97730 | 1783 | DRM_DEBUG_KMS("No FB bound\n"); |
5c3b82e2 CW |
1784 | return 0; |
1785 | } | |
1786 | ||
265db958 | 1787 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
1788 | case 0: |
1789 | case 1: | |
1790 | break; | |
1791 | default: | |
5c3b82e2 | 1792 | return -EINVAL; |
79e53945 JB |
1793 | } |
1794 | ||
5c3b82e2 | 1795 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
1796 | ret = intel_pin_and_fence_fb_obj(dev, |
1797 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 1798 | NULL); |
5c3b82e2 CW |
1799 | if (ret != 0) { |
1800 | mutex_unlock(&dev->struct_mutex); | |
1801 | return ret; | |
1802 | } | |
79e53945 | 1803 | |
265db958 | 1804 | if (old_fb) { |
e6c3a2a6 | 1805 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1806 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
265db958 | 1807 | |
e6c3a2a6 | 1808 | wait_event(dev_priv->pending_flip_queue, |
05394f39 | 1809 | atomic_read(&obj->pending_flip) == 0); |
85345517 CW |
1810 | |
1811 | /* Big Hammer, we also need to ensure that any pending | |
1812 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
1813 | * current scanout is retired before unpinning the old | |
1814 | * framebuffer. | |
1815 | */ | |
05394f39 | 1816 | ret = i915_gem_object_flush_gpu(obj, false); |
85345517 CW |
1817 | if (ret) { |
1818 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); | |
1819 | mutex_unlock(&dev->struct_mutex); | |
1820 | return ret; | |
1821 | } | |
265db958 CW |
1822 | } |
1823 | ||
21c74a8e JW |
1824 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, |
1825 | LEAVE_ATOMIC_MODE_SET); | |
4e6cfefc | 1826 | if (ret) { |
265db958 | 1827 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 1828 | mutex_unlock(&dev->struct_mutex); |
4e6cfefc | 1829 | return ret; |
79e53945 | 1830 | } |
3c4fdcfb | 1831 | |
b7f1de28 CW |
1832 | if (old_fb) { |
1833 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
265db958 | 1834 | i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 1835 | } |
652c393a | 1836 | |
5c3b82e2 | 1837 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
1838 | |
1839 | if (!dev->primary->master) | |
5c3b82e2 | 1840 | return 0; |
79e53945 JB |
1841 | |
1842 | master_priv = dev->primary->master->driver_priv; | |
1843 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 1844 | return 0; |
79e53945 | 1845 | |
265db958 | 1846 | if (intel_crtc->pipe) { |
79e53945 JB |
1847 | master_priv->sarea_priv->pipeB_x = x; |
1848 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
1849 | } else { |
1850 | master_priv->sarea_priv->pipeA_x = x; | |
1851 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 1852 | } |
5c3b82e2 CW |
1853 | |
1854 | return 0; | |
79e53945 JB |
1855 | } |
1856 | ||
5eddb70b | 1857 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
1858 | { |
1859 | struct drm_device *dev = crtc->dev; | |
1860 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1861 | u32 dpa_ctl; | |
1862 | ||
28c97730 | 1863 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
1864 | dpa_ctl = I915_READ(DP_A); |
1865 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
1866 | ||
1867 | if (clock < 200000) { | |
1868 | u32 temp; | |
1869 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
1870 | /* workaround for 160Mhz: | |
1871 | 1) program 0x4600c bits 15:0 = 0x8124 | |
1872 | 2) program 0x46010 bit 0 = 1 | |
1873 | 3) program 0x46034 bit 24 = 1 | |
1874 | 4) program 0x64000 bit 14 = 1 | |
1875 | */ | |
1876 | temp = I915_READ(0x4600c); | |
1877 | temp &= 0xffff0000; | |
1878 | I915_WRITE(0x4600c, temp | 0x8124); | |
1879 | ||
1880 | temp = I915_READ(0x46010); | |
1881 | I915_WRITE(0x46010, temp | 1); | |
1882 | ||
1883 | temp = I915_READ(0x46034); | |
1884 | I915_WRITE(0x46034, temp | (1 << 24)); | |
1885 | } else { | |
1886 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
1887 | } | |
1888 | I915_WRITE(DP_A, dpa_ctl); | |
1889 | ||
5eddb70b | 1890 | POSTING_READ(DP_A); |
32f9d658 ZW |
1891 | udelay(500); |
1892 | } | |
1893 | ||
5e84e1a4 ZW |
1894 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
1895 | { | |
1896 | struct drm_device *dev = crtc->dev; | |
1897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1898 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1899 | int pipe = intel_crtc->pipe; | |
1900 | u32 reg, temp; | |
1901 | ||
1902 | /* enable normal train */ | |
1903 | reg = FDI_TX_CTL(pipe); | |
1904 | temp = I915_READ(reg); | |
1905 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1906 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
1907 | I915_WRITE(reg, temp); | |
1908 | ||
1909 | reg = FDI_RX_CTL(pipe); | |
1910 | temp = I915_READ(reg); | |
1911 | if (HAS_PCH_CPT(dev)) { | |
1912 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1913 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
1914 | } else { | |
1915 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1916 | temp |= FDI_LINK_TRAIN_NONE; | |
1917 | } | |
1918 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
1919 | ||
1920 | /* wait one idle pattern time */ | |
1921 | POSTING_READ(reg); | |
1922 | udelay(1000); | |
1923 | } | |
1924 | ||
8db9d77b ZW |
1925 | /* The FDI link training functions for ILK/Ibexpeak. */ |
1926 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
1927 | { | |
1928 | struct drm_device *dev = crtc->dev; | |
1929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1930 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1931 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1932 | u32 reg, temp, tries; |
8db9d77b | 1933 | |
e1a44743 AJ |
1934 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
1935 | for train result */ | |
5eddb70b CW |
1936 | reg = FDI_RX_IMR(pipe); |
1937 | temp = I915_READ(reg); | |
e1a44743 AJ |
1938 | temp &= ~FDI_RX_SYMBOL_LOCK; |
1939 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
1940 | I915_WRITE(reg, temp); |
1941 | I915_READ(reg); | |
e1a44743 AJ |
1942 | udelay(150); |
1943 | ||
8db9d77b | 1944 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
1945 | reg = FDI_TX_CTL(pipe); |
1946 | temp = I915_READ(reg); | |
77ffb597 AJ |
1947 | temp &= ~(7 << 19); |
1948 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
1949 | temp &= ~FDI_LINK_TRAIN_NONE; |
1950 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 1951 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 1952 | |
5eddb70b CW |
1953 | reg = FDI_RX_CTL(pipe); |
1954 | temp = I915_READ(reg); | |
8db9d77b ZW |
1955 | temp &= ~FDI_LINK_TRAIN_NONE; |
1956 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
1957 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
1958 | ||
1959 | POSTING_READ(reg); | |
8db9d77b ZW |
1960 | udelay(150); |
1961 | ||
5b2adf89 JB |
1962 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
1963 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE); | |
1964 | ||
5eddb70b | 1965 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 1966 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 1967 | temp = I915_READ(reg); |
8db9d77b ZW |
1968 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1969 | ||
1970 | if ((temp & FDI_RX_BIT_LOCK)) { | |
1971 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 1972 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
1973 | break; |
1974 | } | |
8db9d77b | 1975 | } |
e1a44743 | 1976 | if (tries == 5) |
5eddb70b | 1977 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
1978 | |
1979 | /* Train 2 */ | |
5eddb70b CW |
1980 | reg = FDI_TX_CTL(pipe); |
1981 | temp = I915_READ(reg); | |
8db9d77b ZW |
1982 | temp &= ~FDI_LINK_TRAIN_NONE; |
1983 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 1984 | I915_WRITE(reg, temp); |
8db9d77b | 1985 | |
5eddb70b CW |
1986 | reg = FDI_RX_CTL(pipe); |
1987 | temp = I915_READ(reg); | |
8db9d77b ZW |
1988 | temp &= ~FDI_LINK_TRAIN_NONE; |
1989 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 1990 | I915_WRITE(reg, temp); |
8db9d77b | 1991 | |
5eddb70b CW |
1992 | POSTING_READ(reg); |
1993 | udelay(150); | |
8db9d77b | 1994 | |
5eddb70b | 1995 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 1996 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 1997 | temp = I915_READ(reg); |
8db9d77b ZW |
1998 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1999 | ||
2000 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2001 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2002 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2003 | break; | |
2004 | } | |
8db9d77b | 2005 | } |
e1a44743 | 2006 | if (tries == 5) |
5eddb70b | 2007 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2008 | |
2009 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2010 | |
8db9d77b ZW |
2011 | } |
2012 | ||
5eddb70b | 2013 | static const int const snb_b_fdi_train_param [] = { |
8db9d77b ZW |
2014 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2015 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2016 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2017 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2018 | }; | |
2019 | ||
2020 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2021 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2022 | { | |
2023 | struct drm_device *dev = crtc->dev; | |
2024 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2025 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2026 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2027 | u32 reg, temp, i; |
8db9d77b | 2028 | |
e1a44743 AJ |
2029 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2030 | for train result */ | |
5eddb70b CW |
2031 | reg = FDI_RX_IMR(pipe); |
2032 | temp = I915_READ(reg); | |
e1a44743 AJ |
2033 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2034 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2035 | I915_WRITE(reg, temp); |
2036 | ||
2037 | POSTING_READ(reg); | |
e1a44743 AJ |
2038 | udelay(150); |
2039 | ||
8db9d77b | 2040 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2041 | reg = FDI_TX_CTL(pipe); |
2042 | temp = I915_READ(reg); | |
77ffb597 AJ |
2043 | temp &= ~(7 << 19); |
2044 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2045 | temp &= ~FDI_LINK_TRAIN_NONE; |
2046 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2047 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2048 | /* SNB-B */ | |
2049 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2050 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2051 | |
5eddb70b CW |
2052 | reg = FDI_RX_CTL(pipe); |
2053 | temp = I915_READ(reg); | |
8db9d77b ZW |
2054 | if (HAS_PCH_CPT(dev)) { |
2055 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2056 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2057 | } else { | |
2058 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2059 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2060 | } | |
5eddb70b CW |
2061 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2062 | ||
2063 | POSTING_READ(reg); | |
8db9d77b ZW |
2064 | udelay(150); |
2065 | ||
8db9d77b | 2066 | for (i = 0; i < 4; i++ ) { |
5eddb70b CW |
2067 | reg = FDI_TX_CTL(pipe); |
2068 | temp = I915_READ(reg); | |
8db9d77b ZW |
2069 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2070 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2071 | I915_WRITE(reg, temp); |
2072 | ||
2073 | POSTING_READ(reg); | |
8db9d77b ZW |
2074 | udelay(500); |
2075 | ||
5eddb70b CW |
2076 | reg = FDI_RX_IIR(pipe); |
2077 | temp = I915_READ(reg); | |
8db9d77b ZW |
2078 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2079 | ||
2080 | if (temp & FDI_RX_BIT_LOCK) { | |
5eddb70b | 2081 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2082 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2083 | break; | |
2084 | } | |
2085 | } | |
2086 | if (i == 4) | |
5eddb70b | 2087 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2088 | |
2089 | /* Train 2 */ | |
5eddb70b CW |
2090 | reg = FDI_TX_CTL(pipe); |
2091 | temp = I915_READ(reg); | |
8db9d77b ZW |
2092 | temp &= ~FDI_LINK_TRAIN_NONE; |
2093 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2094 | if (IS_GEN6(dev)) { | |
2095 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2096 | /* SNB-B */ | |
2097 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2098 | } | |
5eddb70b | 2099 | I915_WRITE(reg, temp); |
8db9d77b | 2100 | |
5eddb70b CW |
2101 | reg = FDI_RX_CTL(pipe); |
2102 | temp = I915_READ(reg); | |
8db9d77b ZW |
2103 | if (HAS_PCH_CPT(dev)) { |
2104 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2105 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2106 | } else { | |
2107 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2108 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2109 | } | |
5eddb70b CW |
2110 | I915_WRITE(reg, temp); |
2111 | ||
2112 | POSTING_READ(reg); | |
8db9d77b ZW |
2113 | udelay(150); |
2114 | ||
2115 | for (i = 0; i < 4; i++ ) { | |
5eddb70b CW |
2116 | reg = FDI_TX_CTL(pipe); |
2117 | temp = I915_READ(reg); | |
8db9d77b ZW |
2118 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2119 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2120 | I915_WRITE(reg, temp); |
2121 | ||
2122 | POSTING_READ(reg); | |
8db9d77b ZW |
2123 | udelay(500); |
2124 | ||
5eddb70b CW |
2125 | reg = FDI_RX_IIR(pipe); |
2126 | temp = I915_READ(reg); | |
8db9d77b ZW |
2127 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2128 | ||
2129 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2130 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2131 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2132 | break; | |
2133 | } | |
2134 | } | |
2135 | if (i == 4) | |
5eddb70b | 2136 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2137 | |
2138 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2139 | } | |
2140 | ||
0e23b99d | 2141 | static void ironlake_fdi_enable(struct drm_crtc *crtc) |
2c07245f ZW |
2142 | { |
2143 | struct drm_device *dev = crtc->dev; | |
2144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2146 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2147 | u32 reg, temp; |
79e53945 | 2148 | |
c64e311e | 2149 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
2150 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2151 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 2152 | |
c98e9dcf | 2153 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2154 | reg = FDI_RX_CTL(pipe); |
2155 | temp = I915_READ(reg); | |
2156 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2157 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2158 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2159 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2160 | ||
2161 | POSTING_READ(reg); | |
c98e9dcf JB |
2162 | udelay(200); |
2163 | ||
2164 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2165 | temp = I915_READ(reg); |
2166 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2167 | ||
2168 | POSTING_READ(reg); | |
c98e9dcf JB |
2169 | udelay(200); |
2170 | ||
2171 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
2172 | reg = FDI_TX_CTL(pipe); |
2173 | temp = I915_READ(reg); | |
c98e9dcf | 2174 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
2175 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2176 | ||
2177 | POSTING_READ(reg); | |
c98e9dcf | 2178 | udelay(100); |
6be4a607 | 2179 | } |
0e23b99d JB |
2180 | } |
2181 | ||
6b383a7f CW |
2182 | /* |
2183 | * When we disable a pipe, we need to clear any pending scanline wait events | |
2184 | * to avoid hanging the ring, which we assume we are waiting on. | |
2185 | */ | |
2186 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
2187 | { | |
2188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168bd48 | 2189 | struct intel_ring_buffer *ring; |
6b383a7f CW |
2190 | u32 tmp; |
2191 | ||
2192 | if (IS_GEN2(dev)) | |
2193 | /* Can't break the hang on i8xx */ | |
2194 | return; | |
2195 | ||
1ec14ad3 | 2196 | ring = LP_RING(dev_priv); |
8168bd48 CW |
2197 | tmp = I915_READ_CTL(ring); |
2198 | if (tmp & RING_WAIT) | |
2199 | I915_WRITE_CTL(ring, tmp); | |
6b383a7f CW |
2200 | } |
2201 | ||
e6c3a2a6 CW |
2202 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2203 | { | |
05394f39 | 2204 | struct drm_i915_gem_object *obj; |
e6c3a2a6 CW |
2205 | struct drm_i915_private *dev_priv; |
2206 | ||
2207 | if (crtc->fb == NULL) | |
2208 | return; | |
2209 | ||
05394f39 | 2210 | obj = to_intel_framebuffer(crtc->fb)->obj; |
e6c3a2a6 CW |
2211 | dev_priv = crtc->dev->dev_private; |
2212 | wait_event(dev_priv->pending_flip_queue, | |
05394f39 | 2213 | atomic_read(&obj->pending_flip) == 0); |
e6c3a2a6 CW |
2214 | } |
2215 | ||
0e23b99d JB |
2216 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
2217 | { | |
2218 | struct drm_device *dev = crtc->dev; | |
2219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2220 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2221 | int pipe = intel_crtc->pipe; | |
2222 | int plane = intel_crtc->plane; | |
5eddb70b | 2223 | u32 reg, temp; |
0e23b99d | 2224 | |
f7abfe8b CW |
2225 | if (intel_crtc->active) |
2226 | return; | |
2227 | ||
2228 | intel_crtc->active = true; | |
6b383a7f CW |
2229 | intel_update_watermarks(dev); |
2230 | ||
0e23b99d JB |
2231 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
2232 | temp = I915_READ(PCH_LVDS); | |
5eddb70b | 2233 | if ((temp & LVDS_PORT_EN) == 0) |
0e23b99d | 2234 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
0e23b99d JB |
2235 | } |
2236 | ||
2237 | ironlake_fdi_enable(crtc); | |
2c07245f | 2238 | |
6be4a607 JB |
2239 | /* Enable panel fitting for LVDS */ |
2240 | if (dev_priv->pch_pf_size && | |
1d850362 | 2241 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { |
6be4a607 JB |
2242 | /* Force use of hard-coded filter coefficients |
2243 | * as some pre-programmed values are broken, | |
2244 | * e.g. x201. | |
2245 | */ | |
2246 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, | |
2247 | PF_ENABLE | PF_FILTER_MED_3x3); | |
2248 | I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS, | |
2249 | dev_priv->pch_pf_pos); | |
2250 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, | |
2251 | dev_priv->pch_pf_size); | |
2252 | } | |
2c07245f | 2253 | |
b24e7179 JB |
2254 | intel_enable_pipe(dev_priv, pipe); |
2255 | intel_enable_plane(dev_priv, plane, pipe); | |
2c07245f | 2256 | |
c98e9dcf JB |
2257 | /* For PCH output, training FDI link */ |
2258 | if (IS_GEN6(dev)) | |
2259 | gen6_fdi_link_train(crtc); | |
2260 | else | |
2261 | ironlake_fdi_link_train(crtc); | |
2c07245f | 2262 | |
c98e9dcf | 2263 | /* enable PCH DPLL */ |
5eddb70b CW |
2264 | reg = PCH_DPLL(pipe); |
2265 | temp = I915_READ(reg); | |
c98e9dcf | 2266 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
5eddb70b CW |
2267 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); |
2268 | POSTING_READ(reg); | |
8c4223be | 2269 | udelay(200); |
c98e9dcf | 2270 | } |
8db9d77b | 2271 | |
c98e9dcf JB |
2272 | if (HAS_PCH_CPT(dev)) { |
2273 | /* Be sure PCH DPLL SEL is set */ | |
2274 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2275 | if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0) |
c98e9dcf | 2276 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
5eddb70b | 2277 | else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0) |
c98e9dcf JB |
2278 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
2279 | I915_WRITE(PCH_DPLL_SEL, temp); | |
c98e9dcf | 2280 | } |
5eddb70b | 2281 | |
c98e9dcf | 2282 | /* set transcoder timing */ |
5eddb70b CW |
2283 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
2284 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
2285 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 2286 | |
5eddb70b CW |
2287 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
2288 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
2289 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
8db9d77b | 2290 | |
5e84e1a4 ZW |
2291 | intel_fdi_normal_train(crtc); |
2292 | ||
c98e9dcf JB |
2293 | /* For PCH DP, enable TRANS_DP_CTL */ |
2294 | if (HAS_PCH_CPT(dev) && | |
2295 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5eddb70b CW |
2296 | reg = TRANS_DP_CTL(pipe); |
2297 | temp = I915_READ(reg); | |
2298 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
2299 | TRANS_DP_SYNC_MASK | |
2300 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
2301 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
2302 | TRANS_DP_ENH_FRAMING); | |
220cad3c | 2303 | temp |= TRANS_DP_8BPC; |
c98e9dcf JB |
2304 | |
2305 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 2306 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 2307 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 2308 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
2309 | |
2310 | switch (intel_trans_dp_port_sel(crtc)) { | |
2311 | case PCH_DP_B: | |
5eddb70b | 2312 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
2313 | break; |
2314 | case PCH_DP_C: | |
5eddb70b | 2315 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
2316 | break; |
2317 | case PCH_DP_D: | |
5eddb70b | 2318 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
2319 | break; |
2320 | default: | |
2321 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 2322 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 2323 | break; |
32f9d658 | 2324 | } |
2c07245f | 2325 | |
5eddb70b | 2326 | I915_WRITE(reg, temp); |
6be4a607 | 2327 | } |
b52eb4dc | 2328 | |
c98e9dcf | 2329 | /* enable PCH transcoder */ |
5eddb70b CW |
2330 | reg = TRANSCONF(pipe); |
2331 | temp = I915_READ(reg); | |
c98e9dcf JB |
2332 | /* |
2333 | * make the BPC in transcoder be consistent with | |
2334 | * that in pipeconf reg. | |
2335 | */ | |
2336 | temp &= ~PIPE_BPC_MASK; | |
5eddb70b CW |
2337 | temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; |
2338 | I915_WRITE(reg, temp | TRANS_ENABLE); | |
2339 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
17f6766c | 2340 | DRM_ERROR("failed to enable transcoder %d\n", pipe); |
c98e9dcf | 2341 | |
6be4a607 | 2342 | intel_crtc_load_lut(crtc); |
bed4a673 | 2343 | intel_update_fbc(dev); |
6b383a7f | 2344 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
2345 | } |
2346 | ||
2347 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
2348 | { | |
2349 | struct drm_device *dev = crtc->dev; | |
2350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2351 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2352 | int pipe = intel_crtc->pipe; | |
2353 | int plane = intel_crtc->plane; | |
5eddb70b | 2354 | u32 reg, temp; |
b52eb4dc | 2355 | |
f7abfe8b CW |
2356 | if (!intel_crtc->active) |
2357 | return; | |
2358 | ||
e6c3a2a6 | 2359 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 2360 | drm_vblank_off(dev, pipe); |
6b383a7f | 2361 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 2362 | |
b24e7179 | 2363 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 2364 | |
6be4a607 JB |
2365 | if (dev_priv->cfb_plane == plane && |
2366 | dev_priv->display.disable_fbc) | |
2367 | dev_priv->display.disable_fbc(dev); | |
2c07245f | 2368 | |
b24e7179 | 2369 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 2370 | |
6be4a607 JB |
2371 | /* Disable PF */ |
2372 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0); | |
2373 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0); | |
2c07245f | 2374 | |
6be4a607 | 2375 | /* disable CPU FDI tx and PCH FDI rx */ |
5eddb70b CW |
2376 | reg = FDI_TX_CTL(pipe); |
2377 | temp = I915_READ(reg); | |
2378 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2379 | POSTING_READ(reg); | |
249c0e64 | 2380 | |
5eddb70b CW |
2381 | reg = FDI_RX_CTL(pipe); |
2382 | temp = I915_READ(reg); | |
2383 | temp &= ~(0x7 << 16); | |
2384 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2385 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
6be4a607 | 2386 | |
5eddb70b | 2387 | POSTING_READ(reg); |
6be4a607 JB |
2388 | udelay(100); |
2389 | ||
5b2adf89 | 2390 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
e07ac3a0 ZW |
2391 | if (HAS_PCH_IBX(dev)) |
2392 | I915_WRITE(FDI_RX_CHICKEN(pipe), | |
2393 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
2394 | ~FDI_RX_PHASE_SYNC_POINTER_ENABLE)); | |
5b2adf89 | 2395 | |
6be4a607 | 2396 | /* still set train pattern 1 */ |
5eddb70b CW |
2397 | reg = FDI_TX_CTL(pipe); |
2398 | temp = I915_READ(reg); | |
6be4a607 JB |
2399 | temp &= ~FDI_LINK_TRAIN_NONE; |
2400 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2401 | I915_WRITE(reg, temp); |
6be4a607 | 2402 | |
5eddb70b CW |
2403 | reg = FDI_RX_CTL(pipe); |
2404 | temp = I915_READ(reg); | |
6be4a607 JB |
2405 | if (HAS_PCH_CPT(dev)) { |
2406 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2407 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2408 | } else { | |
2c07245f ZW |
2409 | temp &= ~FDI_LINK_TRAIN_NONE; |
2410 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
6be4a607 | 2411 | } |
5eddb70b CW |
2412 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2413 | temp &= ~(0x07 << 16); | |
2414 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2415 | I915_WRITE(reg, temp); | |
2c07245f | 2416 | |
5eddb70b | 2417 | POSTING_READ(reg); |
6be4a607 | 2418 | udelay(100); |
2c07245f | 2419 | |
6be4a607 JB |
2420 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
2421 | temp = I915_READ(PCH_LVDS); | |
5eddb70b CW |
2422 | if (temp & LVDS_PORT_EN) { |
2423 | I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN); | |
2424 | POSTING_READ(PCH_LVDS); | |
2425 | udelay(100); | |
2426 | } | |
6be4a607 | 2427 | } |
249c0e64 | 2428 | |
6be4a607 | 2429 | /* disable PCH transcoder */ |
5eddb70b CW |
2430 | reg = TRANSCONF(plane); |
2431 | temp = I915_READ(reg); | |
2432 | if (temp & TRANS_ENABLE) { | |
2433 | I915_WRITE(reg, temp & ~TRANS_ENABLE); | |
6be4a607 | 2434 | /* wait for PCH transcoder off, transcoder state */ |
5eddb70b | 2435 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
6be4a607 JB |
2436 | DRM_ERROR("failed to disable transcoder\n"); |
2437 | } | |
913d8d11 | 2438 | |
6be4a607 JB |
2439 | if (HAS_PCH_CPT(dev)) { |
2440 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
2441 | reg = TRANS_DP_CTL(pipe); |
2442 | temp = I915_READ(reg); | |
2443 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
2444 | I915_WRITE(reg, temp); | |
6be4a607 JB |
2445 | |
2446 | /* disable DPLL_SEL */ | |
2447 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2448 | if (pipe == 0) |
6be4a607 JB |
2449 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
2450 | else | |
2451 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); | |
2452 | I915_WRITE(PCH_DPLL_SEL, temp); | |
6be4a607 | 2453 | } |
e3421a18 | 2454 | |
6be4a607 | 2455 | /* disable PCH DPLL */ |
5eddb70b CW |
2456 | reg = PCH_DPLL(pipe); |
2457 | temp = I915_READ(reg); | |
2458 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); | |
8db9d77b | 2459 | |
6be4a607 | 2460 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
2461 | reg = FDI_RX_CTL(pipe); |
2462 | temp = I915_READ(reg); | |
2463 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 2464 | |
6be4a607 | 2465 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
2466 | reg = FDI_TX_CTL(pipe); |
2467 | temp = I915_READ(reg); | |
2468 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2469 | ||
2470 | POSTING_READ(reg); | |
6be4a607 | 2471 | udelay(100); |
8db9d77b | 2472 | |
5eddb70b CW |
2473 | reg = FDI_RX_CTL(pipe); |
2474 | temp = I915_READ(reg); | |
2475 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 2476 | |
6be4a607 | 2477 | /* Wait for the clocks to turn off. */ |
5eddb70b | 2478 | POSTING_READ(reg); |
6be4a607 | 2479 | udelay(100); |
6b383a7f | 2480 | |
f7abfe8b | 2481 | intel_crtc->active = false; |
6b383a7f CW |
2482 | intel_update_watermarks(dev); |
2483 | intel_update_fbc(dev); | |
2484 | intel_clear_scanline_wait(dev); | |
6be4a607 | 2485 | } |
1b3c7a47 | 2486 | |
6be4a607 JB |
2487 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
2488 | { | |
2489 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2490 | int pipe = intel_crtc->pipe; | |
2491 | int plane = intel_crtc->plane; | |
8db9d77b | 2492 | |
6be4a607 JB |
2493 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
2494 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2495 | */ | |
2496 | switch (mode) { | |
2497 | case DRM_MODE_DPMS_ON: | |
2498 | case DRM_MODE_DPMS_STANDBY: | |
2499 | case DRM_MODE_DPMS_SUSPEND: | |
2500 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
2501 | ironlake_crtc_enable(crtc); | |
2502 | break; | |
1b3c7a47 | 2503 | |
6be4a607 JB |
2504 | case DRM_MODE_DPMS_OFF: |
2505 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
2506 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
2507 | break; |
2508 | } | |
2509 | } | |
2510 | ||
02e792fb DV |
2511 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
2512 | { | |
02e792fb | 2513 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 2514 | struct drm_device *dev = intel_crtc->base.dev; |
03f77ea5 | 2515 | |
23f09ce3 CW |
2516 | mutex_lock(&dev->struct_mutex); |
2517 | (void) intel_overlay_switch_off(intel_crtc->overlay, false); | |
2518 | mutex_unlock(&dev->struct_mutex); | |
02e792fb | 2519 | } |
02e792fb | 2520 | |
5dcdbcb0 CW |
2521 | /* Let userspace switch the overlay on again. In most cases userspace |
2522 | * has to recompute where to put it anyway. | |
2523 | */ | |
02e792fb DV |
2524 | } |
2525 | ||
0b8765c6 | 2526 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
2527 | { |
2528 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2529 | struct drm_i915_private *dev_priv = dev->dev_private; |
2530 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2531 | int pipe = intel_crtc->pipe; | |
80824003 | 2532 | int plane = intel_crtc->plane; |
5eddb70b | 2533 | u32 reg, temp; |
79e53945 | 2534 | |
f7abfe8b CW |
2535 | if (intel_crtc->active) |
2536 | return; | |
2537 | ||
2538 | intel_crtc->active = true; | |
6b383a7f CW |
2539 | intel_update_watermarks(dev); |
2540 | ||
0b8765c6 | 2541 | /* Enable the DPLL */ |
5eddb70b CW |
2542 | reg = DPLL(pipe); |
2543 | temp = I915_READ(reg); | |
0b8765c6 | 2544 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
5eddb70b CW |
2545 | I915_WRITE(reg, temp); |
2546 | ||
0b8765c6 | 2547 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2548 | POSTING_READ(reg); |
0b8765c6 | 2549 | udelay(150); |
5eddb70b CW |
2550 | |
2551 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); | |
2552 | ||
0b8765c6 | 2553 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2554 | POSTING_READ(reg); |
0b8765c6 | 2555 | udelay(150); |
5eddb70b CW |
2556 | |
2557 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); | |
2558 | ||
0b8765c6 | 2559 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2560 | POSTING_READ(reg); |
0b8765c6 JB |
2561 | udelay(150); |
2562 | } | |
79e53945 | 2563 | |
b24e7179 JB |
2564 | intel_enable_pipe(dev_priv, pipe); |
2565 | intel_enable_plane(dev_priv, plane, pipe); | |
79e53945 | 2566 | |
0b8765c6 | 2567 | intel_crtc_load_lut(crtc); |
bed4a673 | 2568 | intel_update_fbc(dev); |
79e53945 | 2569 | |
0b8765c6 JB |
2570 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
2571 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 2572 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 2573 | } |
79e53945 | 2574 | |
0b8765c6 JB |
2575 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
2576 | { | |
2577 | struct drm_device *dev = crtc->dev; | |
2578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2579 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2580 | int pipe = intel_crtc->pipe; | |
2581 | int plane = intel_crtc->plane; | |
5eddb70b | 2582 | u32 reg, temp; |
b690e96c | 2583 | |
f7abfe8b CW |
2584 | if (!intel_crtc->active) |
2585 | return; | |
2586 | ||
0b8765c6 | 2587 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
2588 | intel_crtc_wait_for_pending_flips(crtc); |
2589 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 2590 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 2591 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 JB |
2592 | |
2593 | if (dev_priv->cfb_plane == plane && | |
2594 | dev_priv->display.disable_fbc) | |
2595 | dev_priv->display.disable_fbc(dev); | |
79e53945 | 2596 | |
b24e7179 | 2597 | intel_disable_plane(dev_priv, plane, pipe); |
79e53945 | 2598 | |
0b8765c6 | 2599 | /* Don't disable pipe A or pipe A PLLs if needed */ |
5eddb70b | 2600 | if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
6b383a7f | 2601 | goto done; |
0b8765c6 | 2602 | |
b24e7179 | 2603 | intel_disable_pipe(dev_priv, pipe); |
0b8765c6 | 2604 | |
5eddb70b CW |
2605 | reg = DPLL(pipe); |
2606 | temp = I915_READ(reg); | |
2607 | if (temp & DPLL_VCO_ENABLE) { | |
2608 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); | |
0b8765c6 | 2609 | |
5eddb70b CW |
2610 | /* Wait for the clocks to turn off. */ |
2611 | POSTING_READ(reg); | |
2612 | udelay(150); | |
0b8765c6 | 2613 | } |
6b383a7f CW |
2614 | |
2615 | done: | |
f7abfe8b | 2616 | intel_crtc->active = false; |
6b383a7f CW |
2617 | intel_update_fbc(dev); |
2618 | intel_update_watermarks(dev); | |
2619 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
2620 | } |
2621 | ||
2622 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2623 | { | |
2624 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
2625 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2626 | */ | |
2627 | switch (mode) { | |
2628 | case DRM_MODE_DPMS_ON: | |
2629 | case DRM_MODE_DPMS_STANDBY: | |
2630 | case DRM_MODE_DPMS_SUSPEND: | |
2631 | i9xx_crtc_enable(crtc); | |
2632 | break; | |
2633 | case DRM_MODE_DPMS_OFF: | |
2634 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
2635 | break; |
2636 | } | |
2c07245f ZW |
2637 | } |
2638 | ||
2639 | /** | |
2640 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
2641 | */ |
2642 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2643 | { | |
2644 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 2645 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
2646 | struct drm_i915_master_private *master_priv; |
2647 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2648 | int pipe = intel_crtc->pipe; | |
2649 | bool enabled; | |
2650 | ||
032d2a0d CW |
2651 | if (intel_crtc->dpms_mode == mode) |
2652 | return; | |
2653 | ||
65655d4a | 2654 | intel_crtc->dpms_mode = mode; |
debcaddc | 2655 | |
e70236a8 | 2656 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
2657 | |
2658 | if (!dev->primary->master) | |
2659 | return; | |
2660 | ||
2661 | master_priv = dev->primary->master->driver_priv; | |
2662 | if (!master_priv->sarea_priv) | |
2663 | return; | |
2664 | ||
2665 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
2666 | ||
2667 | switch (pipe) { | |
2668 | case 0: | |
2669 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
2670 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
2671 | break; | |
2672 | case 1: | |
2673 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
2674 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
2675 | break; | |
2676 | default: | |
2677 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
2678 | break; | |
2679 | } | |
79e53945 JB |
2680 | } |
2681 | ||
cdd59983 CW |
2682 | static void intel_crtc_disable(struct drm_crtc *crtc) |
2683 | { | |
2684 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
2685 | struct drm_device *dev = crtc->dev; | |
2686 | ||
2687 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
2688 | ||
2689 | if (crtc->fb) { | |
2690 | mutex_lock(&dev->struct_mutex); | |
2691 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); | |
2692 | mutex_unlock(&dev->struct_mutex); | |
2693 | } | |
2694 | } | |
2695 | ||
7e7d76c3 JB |
2696 | /* Prepare for a mode set. |
2697 | * | |
2698 | * Note we could be a lot smarter here. We need to figure out which outputs | |
2699 | * will be enabled, which disabled (in short, how the config will changes) | |
2700 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
2701 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
2702 | * panel fitting is in the proper state, etc. | |
2703 | */ | |
2704 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 2705 | { |
7e7d76c3 | 2706 | i9xx_crtc_disable(crtc); |
79e53945 JB |
2707 | } |
2708 | ||
7e7d76c3 | 2709 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 2710 | { |
7e7d76c3 | 2711 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
2712 | } |
2713 | ||
2714 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
2715 | { | |
7e7d76c3 | 2716 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
2717 | } |
2718 | ||
2719 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
2720 | { | |
7e7d76c3 | 2721 | ironlake_crtc_enable(crtc); |
79e53945 JB |
2722 | } |
2723 | ||
2724 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
2725 | { | |
2726 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2727 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
2728 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
2729 | } | |
2730 | ||
2731 | void intel_encoder_commit (struct drm_encoder *encoder) | |
2732 | { | |
2733 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2734 | /* lvds has its own version of commit see intel_lvds_commit */ | |
2735 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
2736 | } | |
2737 | ||
ea5b213a CW |
2738 | void intel_encoder_destroy(struct drm_encoder *encoder) |
2739 | { | |
4ef69c7a | 2740 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 2741 | |
ea5b213a CW |
2742 | drm_encoder_cleanup(encoder); |
2743 | kfree(intel_encoder); | |
2744 | } | |
2745 | ||
79e53945 JB |
2746 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
2747 | struct drm_display_mode *mode, | |
2748 | struct drm_display_mode *adjusted_mode) | |
2749 | { | |
2c07245f | 2750 | struct drm_device *dev = crtc->dev; |
89749350 | 2751 | |
bad720ff | 2752 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 2753 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
2754 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
2755 | return false; | |
2c07245f | 2756 | } |
89749350 CW |
2757 | |
2758 | /* XXX some encoders set the crtcinfo, others don't. | |
2759 | * Obviously we need some form of conflict resolution here... | |
2760 | */ | |
2761 | if (adjusted_mode->crtc_htotal == 0) | |
2762 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
2763 | ||
79e53945 JB |
2764 | return true; |
2765 | } | |
2766 | ||
e70236a8 JB |
2767 | static int i945_get_display_clock_speed(struct drm_device *dev) |
2768 | { | |
2769 | return 400000; | |
2770 | } | |
79e53945 | 2771 | |
e70236a8 | 2772 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 2773 | { |
e70236a8 JB |
2774 | return 333000; |
2775 | } | |
79e53945 | 2776 | |
e70236a8 JB |
2777 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
2778 | { | |
2779 | return 200000; | |
2780 | } | |
79e53945 | 2781 | |
e70236a8 JB |
2782 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
2783 | { | |
2784 | u16 gcfgc = 0; | |
79e53945 | 2785 | |
e70236a8 JB |
2786 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
2787 | ||
2788 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
2789 | return 133000; | |
2790 | else { | |
2791 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
2792 | case GC_DISPLAY_CLOCK_333_MHZ: | |
2793 | return 333000; | |
2794 | default: | |
2795 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
2796 | return 190000; | |
79e53945 | 2797 | } |
e70236a8 JB |
2798 | } |
2799 | } | |
2800 | ||
2801 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
2802 | { | |
2803 | return 266000; | |
2804 | } | |
2805 | ||
2806 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
2807 | { | |
2808 | u16 hpllcc = 0; | |
2809 | /* Assume that the hardware is in the high speed state. This | |
2810 | * should be the default. | |
2811 | */ | |
2812 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
2813 | case GC_CLOCK_133_200: | |
2814 | case GC_CLOCK_100_200: | |
2815 | return 200000; | |
2816 | case GC_CLOCK_166_250: | |
2817 | return 250000; | |
2818 | case GC_CLOCK_100_133: | |
79e53945 | 2819 | return 133000; |
e70236a8 | 2820 | } |
79e53945 | 2821 | |
e70236a8 JB |
2822 | /* Shouldn't happen */ |
2823 | return 0; | |
2824 | } | |
79e53945 | 2825 | |
e70236a8 JB |
2826 | static int i830_get_display_clock_speed(struct drm_device *dev) |
2827 | { | |
2828 | return 133000; | |
79e53945 JB |
2829 | } |
2830 | ||
2c07245f ZW |
2831 | struct fdi_m_n { |
2832 | u32 tu; | |
2833 | u32 gmch_m; | |
2834 | u32 gmch_n; | |
2835 | u32 link_m; | |
2836 | u32 link_n; | |
2837 | }; | |
2838 | ||
2839 | static void | |
2840 | fdi_reduce_ratio(u32 *num, u32 *den) | |
2841 | { | |
2842 | while (*num > 0xffffff || *den > 0xffffff) { | |
2843 | *num >>= 1; | |
2844 | *den >>= 1; | |
2845 | } | |
2846 | } | |
2847 | ||
2c07245f | 2848 | static void |
f2b115e6 AJ |
2849 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
2850 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 2851 | { |
2c07245f ZW |
2852 | m_n->tu = 64; /* default size */ |
2853 | ||
22ed1113 CW |
2854 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
2855 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
2856 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
2857 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
2858 | ||
22ed1113 CW |
2859 | m_n->link_m = pixel_clock; |
2860 | m_n->link_n = link_clock; | |
2c07245f ZW |
2861 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
2862 | } | |
2863 | ||
2864 | ||
7662c8bd SL |
2865 | struct intel_watermark_params { |
2866 | unsigned long fifo_size; | |
2867 | unsigned long max_wm; | |
2868 | unsigned long default_wm; | |
2869 | unsigned long guard_size; | |
2870 | unsigned long cacheline_size; | |
2871 | }; | |
2872 | ||
f2b115e6 AJ |
2873 | /* Pineview has different values for various configs */ |
2874 | static struct intel_watermark_params pineview_display_wm = { | |
2875 | PINEVIEW_DISPLAY_FIFO, | |
2876 | PINEVIEW_MAX_WM, | |
2877 | PINEVIEW_DFT_WM, | |
2878 | PINEVIEW_GUARD_WM, | |
2879 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2880 | }; |
f2b115e6 AJ |
2881 | static struct intel_watermark_params pineview_display_hplloff_wm = { |
2882 | PINEVIEW_DISPLAY_FIFO, | |
2883 | PINEVIEW_MAX_WM, | |
2884 | PINEVIEW_DFT_HPLLOFF_WM, | |
2885 | PINEVIEW_GUARD_WM, | |
2886 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2887 | }; |
f2b115e6 AJ |
2888 | static struct intel_watermark_params pineview_cursor_wm = { |
2889 | PINEVIEW_CURSOR_FIFO, | |
2890 | PINEVIEW_CURSOR_MAX_WM, | |
2891 | PINEVIEW_CURSOR_DFT_WM, | |
2892 | PINEVIEW_CURSOR_GUARD_WM, | |
2893 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 2894 | }; |
f2b115e6 AJ |
2895 | static struct intel_watermark_params pineview_cursor_hplloff_wm = { |
2896 | PINEVIEW_CURSOR_FIFO, | |
2897 | PINEVIEW_CURSOR_MAX_WM, | |
2898 | PINEVIEW_CURSOR_DFT_WM, | |
2899 | PINEVIEW_CURSOR_GUARD_WM, | |
2900 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2901 | }; |
0e442c60 JB |
2902 | static struct intel_watermark_params g4x_wm_info = { |
2903 | G4X_FIFO_SIZE, | |
2904 | G4X_MAX_WM, | |
2905 | G4X_MAX_WM, | |
2906 | 2, | |
2907 | G4X_FIFO_LINE_SIZE, | |
2908 | }; | |
4fe5e611 ZY |
2909 | static struct intel_watermark_params g4x_cursor_wm_info = { |
2910 | I965_CURSOR_FIFO, | |
2911 | I965_CURSOR_MAX_WM, | |
2912 | I965_CURSOR_DFT_WM, | |
2913 | 2, | |
2914 | G4X_FIFO_LINE_SIZE, | |
2915 | }; | |
2916 | static struct intel_watermark_params i965_cursor_wm_info = { | |
2917 | I965_CURSOR_FIFO, | |
2918 | I965_CURSOR_MAX_WM, | |
2919 | I965_CURSOR_DFT_WM, | |
2920 | 2, | |
2921 | I915_FIFO_LINE_SIZE, | |
2922 | }; | |
7662c8bd | 2923 | static struct intel_watermark_params i945_wm_info = { |
dff33cfc | 2924 | I945_FIFO_SIZE, |
7662c8bd SL |
2925 | I915_MAX_WM, |
2926 | 1, | |
dff33cfc JB |
2927 | 2, |
2928 | I915_FIFO_LINE_SIZE | |
7662c8bd SL |
2929 | }; |
2930 | static struct intel_watermark_params i915_wm_info = { | |
dff33cfc | 2931 | I915_FIFO_SIZE, |
7662c8bd SL |
2932 | I915_MAX_WM, |
2933 | 1, | |
dff33cfc | 2934 | 2, |
7662c8bd SL |
2935 | I915_FIFO_LINE_SIZE |
2936 | }; | |
2937 | static struct intel_watermark_params i855_wm_info = { | |
2938 | I855GM_FIFO_SIZE, | |
2939 | I915_MAX_WM, | |
2940 | 1, | |
dff33cfc | 2941 | 2, |
7662c8bd SL |
2942 | I830_FIFO_LINE_SIZE |
2943 | }; | |
2944 | static struct intel_watermark_params i830_wm_info = { | |
2945 | I830_FIFO_SIZE, | |
2946 | I915_MAX_WM, | |
2947 | 1, | |
dff33cfc | 2948 | 2, |
7662c8bd SL |
2949 | I830_FIFO_LINE_SIZE |
2950 | }; | |
2951 | ||
7f8a8569 ZW |
2952 | static struct intel_watermark_params ironlake_display_wm_info = { |
2953 | ILK_DISPLAY_FIFO, | |
2954 | ILK_DISPLAY_MAXWM, | |
2955 | ILK_DISPLAY_DFTWM, | |
2956 | 2, | |
2957 | ILK_FIFO_LINE_SIZE | |
2958 | }; | |
2959 | ||
c936f44d ZY |
2960 | static struct intel_watermark_params ironlake_cursor_wm_info = { |
2961 | ILK_CURSOR_FIFO, | |
2962 | ILK_CURSOR_MAXWM, | |
2963 | ILK_CURSOR_DFTWM, | |
2964 | 2, | |
2965 | ILK_FIFO_LINE_SIZE | |
2966 | }; | |
2967 | ||
7f8a8569 ZW |
2968 | static struct intel_watermark_params ironlake_display_srwm_info = { |
2969 | ILK_DISPLAY_SR_FIFO, | |
2970 | ILK_DISPLAY_MAX_SRWM, | |
2971 | ILK_DISPLAY_DFT_SRWM, | |
2972 | 2, | |
2973 | ILK_FIFO_LINE_SIZE | |
2974 | }; | |
2975 | ||
2976 | static struct intel_watermark_params ironlake_cursor_srwm_info = { | |
2977 | ILK_CURSOR_SR_FIFO, | |
2978 | ILK_CURSOR_MAX_SRWM, | |
2979 | ILK_CURSOR_DFT_SRWM, | |
2980 | 2, | |
2981 | ILK_FIFO_LINE_SIZE | |
2982 | }; | |
2983 | ||
1398261a YL |
2984 | static struct intel_watermark_params sandybridge_display_wm_info = { |
2985 | SNB_DISPLAY_FIFO, | |
2986 | SNB_DISPLAY_MAXWM, | |
2987 | SNB_DISPLAY_DFTWM, | |
2988 | 2, | |
2989 | SNB_FIFO_LINE_SIZE | |
2990 | }; | |
2991 | ||
2992 | static struct intel_watermark_params sandybridge_cursor_wm_info = { | |
2993 | SNB_CURSOR_FIFO, | |
2994 | SNB_CURSOR_MAXWM, | |
2995 | SNB_CURSOR_DFTWM, | |
2996 | 2, | |
2997 | SNB_FIFO_LINE_SIZE | |
2998 | }; | |
2999 | ||
3000 | static struct intel_watermark_params sandybridge_display_srwm_info = { | |
3001 | SNB_DISPLAY_SR_FIFO, | |
3002 | SNB_DISPLAY_MAX_SRWM, | |
3003 | SNB_DISPLAY_DFT_SRWM, | |
3004 | 2, | |
3005 | SNB_FIFO_LINE_SIZE | |
3006 | }; | |
3007 | ||
3008 | static struct intel_watermark_params sandybridge_cursor_srwm_info = { | |
3009 | SNB_CURSOR_SR_FIFO, | |
3010 | SNB_CURSOR_MAX_SRWM, | |
3011 | SNB_CURSOR_DFT_SRWM, | |
3012 | 2, | |
3013 | SNB_FIFO_LINE_SIZE | |
3014 | }; | |
3015 | ||
3016 | ||
dff33cfc JB |
3017 | /** |
3018 | * intel_calculate_wm - calculate watermark level | |
3019 | * @clock_in_khz: pixel clock | |
3020 | * @wm: chip FIFO params | |
3021 | * @pixel_size: display pixel size | |
3022 | * @latency_ns: memory latency for the platform | |
3023 | * | |
3024 | * Calculate the watermark level (the level at which the display plane will | |
3025 | * start fetching from memory again). Each chip has a different display | |
3026 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
3027 | * in the correct intel_watermark_params structure. | |
3028 | * | |
3029 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
3030 | * on the pixel size. When it reaches the watermark level, it'll start | |
3031 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
3032 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
3033 | * will occur, and a display engine hang could result. | |
3034 | */ | |
7662c8bd SL |
3035 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
3036 | struct intel_watermark_params *wm, | |
3037 | int pixel_size, | |
3038 | unsigned long latency_ns) | |
3039 | { | |
390c4dd4 | 3040 | long entries_required, wm_size; |
dff33cfc | 3041 | |
d660467c JB |
3042 | /* |
3043 | * Note: we need to make sure we don't overflow for various clock & | |
3044 | * latency values. | |
3045 | * clocks go from a few thousand to several hundred thousand. | |
3046 | * latency is usually a few thousand | |
3047 | */ | |
3048 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
3049 | 1000; | |
8de9b311 | 3050 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 3051 | |
28c97730 | 3052 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); |
dff33cfc JB |
3053 | |
3054 | wm_size = wm->fifo_size - (entries_required + wm->guard_size); | |
3055 | ||
28c97730 | 3056 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); |
7662c8bd | 3057 | |
390c4dd4 JB |
3058 | /* Don't promote wm_size to unsigned... */ |
3059 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 3060 | wm_size = wm->max_wm; |
c3add4b6 | 3061 | if (wm_size <= 0) |
7662c8bd SL |
3062 | wm_size = wm->default_wm; |
3063 | return wm_size; | |
3064 | } | |
3065 | ||
3066 | struct cxsr_latency { | |
3067 | int is_desktop; | |
95534263 | 3068 | int is_ddr3; |
7662c8bd SL |
3069 | unsigned long fsb_freq; |
3070 | unsigned long mem_freq; | |
3071 | unsigned long display_sr; | |
3072 | unsigned long display_hpll_disable; | |
3073 | unsigned long cursor_sr; | |
3074 | unsigned long cursor_hpll_disable; | |
3075 | }; | |
3076 | ||
403c89ff | 3077 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
3078 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
3079 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
3080 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
3081 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
3082 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
3083 | ||
3084 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
3085 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
3086 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
3087 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
3088 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
3089 | ||
3090 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
3091 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
3092 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
3093 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
3094 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
3095 | ||
3096 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
3097 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
3098 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
3099 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
3100 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
3101 | ||
3102 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
3103 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
3104 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
3105 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
3106 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
3107 | ||
3108 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
3109 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
3110 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
3111 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
3112 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
3113 | }; |
3114 | ||
403c89ff CW |
3115 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
3116 | int is_ddr3, | |
3117 | int fsb, | |
3118 | int mem) | |
7662c8bd | 3119 | { |
403c89ff | 3120 | const struct cxsr_latency *latency; |
7662c8bd | 3121 | int i; |
7662c8bd SL |
3122 | |
3123 | if (fsb == 0 || mem == 0) | |
3124 | return NULL; | |
3125 | ||
3126 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
3127 | latency = &cxsr_latency_table[i]; | |
3128 | if (is_desktop == latency->is_desktop && | |
95534263 | 3129 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
3130 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
3131 | return latency; | |
7662c8bd | 3132 | } |
decbbcda | 3133 | |
28c97730 | 3134 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
3135 | |
3136 | return NULL; | |
7662c8bd SL |
3137 | } |
3138 | ||
f2b115e6 | 3139 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
3140 | { |
3141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
3142 | |
3143 | /* deactivate cxsr */ | |
3e33d94d | 3144 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
3145 | } |
3146 | ||
bcc24fb4 JB |
3147 | /* |
3148 | * Latency for FIFO fetches is dependent on several factors: | |
3149 | * - memory configuration (speed, channels) | |
3150 | * - chipset | |
3151 | * - current MCH state | |
3152 | * It can be fairly high in some situations, so here we assume a fairly | |
3153 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
3154 | * set this value too high, the FIFO will fetch frequently to stay full) | |
3155 | * and power consumption (set it too low to save power and we might see | |
3156 | * FIFO underruns and display "flicker"). | |
3157 | * | |
3158 | * A value of 5us seems to be a good balance; safe for very low end | |
3159 | * platforms but not overly aggressive on lower latency configs. | |
3160 | */ | |
69e302a9 | 3161 | static const int latency_ns = 5000; |
7662c8bd | 3162 | |
e70236a8 | 3163 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
3164 | { |
3165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3166 | uint32_t dsparb = I915_READ(DSPARB); | |
3167 | int size; | |
3168 | ||
8de9b311 CW |
3169 | size = dsparb & 0x7f; |
3170 | if (plane) | |
3171 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 3172 | |
28c97730 | 3173 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3174 | plane ? "B" : "A", size); |
dff33cfc JB |
3175 | |
3176 | return size; | |
3177 | } | |
7662c8bd | 3178 | |
e70236a8 JB |
3179 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
3180 | { | |
3181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3182 | uint32_t dsparb = I915_READ(DSPARB); | |
3183 | int size; | |
3184 | ||
8de9b311 CW |
3185 | size = dsparb & 0x1ff; |
3186 | if (plane) | |
3187 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 3188 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 3189 | |
28c97730 | 3190 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3191 | plane ? "B" : "A", size); |
dff33cfc JB |
3192 | |
3193 | return size; | |
3194 | } | |
7662c8bd | 3195 | |
e70236a8 JB |
3196 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
3197 | { | |
3198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3199 | uint32_t dsparb = I915_READ(DSPARB); | |
3200 | int size; | |
3201 | ||
3202 | size = dsparb & 0x7f; | |
3203 | size >>= 2; /* Convert to cachelines */ | |
3204 | ||
28c97730 | 3205 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
3206 | plane ? "B" : "A", |
3207 | size); | |
e70236a8 JB |
3208 | |
3209 | return size; | |
3210 | } | |
3211 | ||
3212 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
3213 | { | |
3214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3215 | uint32_t dsparb = I915_READ(DSPARB); | |
3216 | int size; | |
3217 | ||
3218 | size = dsparb & 0x7f; | |
3219 | size >>= 1; /* Convert to cachelines */ | |
3220 | ||
28c97730 | 3221 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3222 | plane ? "B" : "A", size); |
e70236a8 JB |
3223 | |
3224 | return size; | |
3225 | } | |
3226 | ||
d4294342 | 3227 | static void pineview_update_wm(struct drm_device *dev, int planea_clock, |
5eddb70b CW |
3228 | int planeb_clock, int sr_hdisplay, int unused, |
3229 | int pixel_size) | |
d4294342 ZY |
3230 | { |
3231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
403c89ff | 3232 | const struct cxsr_latency *latency; |
d4294342 ZY |
3233 | u32 reg; |
3234 | unsigned long wm; | |
d4294342 ZY |
3235 | int sr_clock; |
3236 | ||
403c89ff | 3237 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3238 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3239 | if (!latency) { |
3240 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3241 | pineview_disable_cxsr(dev); | |
3242 | return; | |
3243 | } | |
3244 | ||
3245 | if (!planea_clock || !planeb_clock) { | |
3246 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
3247 | ||
3248 | /* Display SR */ | |
3249 | wm = intel_calculate_wm(sr_clock, &pineview_display_wm, | |
3250 | pixel_size, latency->display_sr); | |
3251 | reg = I915_READ(DSPFW1); | |
3252 | reg &= ~DSPFW_SR_MASK; | |
3253 | reg |= wm << DSPFW_SR_SHIFT; | |
3254 | I915_WRITE(DSPFW1, reg); | |
3255 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3256 | ||
3257 | /* cursor SR */ | |
3258 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm, | |
3259 | pixel_size, latency->cursor_sr); | |
3260 | reg = I915_READ(DSPFW3); | |
3261 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3262 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3263 | I915_WRITE(DSPFW3, reg); | |
3264 | ||
3265 | /* Display HPLL off SR */ | |
3266 | wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm, | |
3267 | pixel_size, latency->display_hpll_disable); | |
3268 | reg = I915_READ(DSPFW3); | |
3269 | reg &= ~DSPFW_HPLL_SR_MASK; | |
3270 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
3271 | I915_WRITE(DSPFW3, reg); | |
3272 | ||
3273 | /* cursor HPLL off SR */ | |
3274 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm, | |
3275 | pixel_size, latency->cursor_hpll_disable); | |
3276 | reg = I915_READ(DSPFW3); | |
3277 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
3278 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
3279 | I915_WRITE(DSPFW3, reg); | |
3280 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
3281 | ||
3282 | /* activate cxsr */ | |
3e33d94d CW |
3283 | I915_WRITE(DSPFW3, |
3284 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
3285 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
3286 | } else { | |
3287 | pineview_disable_cxsr(dev); | |
3288 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
3289 | } | |
3290 | } | |
3291 | ||
0e442c60 | 3292 | static void g4x_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3293 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3294 | int pixel_size) | |
652c393a JB |
3295 | { |
3296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e442c60 JB |
3297 | int total_size, cacheline_size; |
3298 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr; | |
3299 | struct intel_watermark_params planea_params, planeb_params; | |
3300 | unsigned long line_time_us; | |
3301 | int sr_clock, sr_entries = 0, entries_required; | |
652c393a | 3302 | |
0e442c60 JB |
3303 | /* Create copies of the base settings for each pipe */ |
3304 | planea_params = planeb_params = g4x_wm_info; | |
3305 | ||
3306 | /* Grab a couple of global values before we overwrite them */ | |
3307 | total_size = planea_params.fifo_size; | |
3308 | cacheline_size = planea_params.cacheline_size; | |
3309 | ||
3310 | /* | |
3311 | * Note: we need to make sure we don't overflow for various clock & | |
3312 | * latency values. | |
3313 | * clocks go from a few thousand to several hundred thousand. | |
3314 | * latency is usually a few thousand | |
3315 | */ | |
3316 | entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) / | |
3317 | 1000; | |
8de9b311 | 3318 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3319 | planea_wm = entries_required + planea_params.guard_size; |
3320 | ||
3321 | entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) / | |
3322 | 1000; | |
8de9b311 | 3323 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3324 | planeb_wm = entries_required + planeb_params.guard_size; |
3325 | ||
3326 | cursora_wm = cursorb_wm = 16; | |
3327 | cursor_sr = 32; | |
3328 | ||
3329 | DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
3330 | ||
3331 | /* Calc sr entries for one plane configs */ | |
3332 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3333 | /* self-refresh has much higher latency */ | |
69e302a9 | 3334 | static const int sr_latency_ns = 12000; |
0e442c60 JB |
3335 | |
3336 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3337 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
0e442c60 JB |
3338 | |
3339 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3340 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3341 | pixel_size * sr_hdisplay; |
8de9b311 | 3342 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
4fe5e611 ZY |
3343 | |
3344 | entries_required = (((sr_latency_ns / line_time_us) + | |
3345 | 1000) / 1000) * pixel_size * 64; | |
8de9b311 | 3346 | entries_required = DIV_ROUND_UP(entries_required, |
5eddb70b | 3347 | g4x_cursor_wm_info.cacheline_size); |
4fe5e611 ZY |
3348 | cursor_sr = entries_required + g4x_cursor_wm_info.guard_size; |
3349 | ||
3350 | if (cursor_sr > g4x_cursor_wm_info.max_wm) | |
3351 | cursor_sr = g4x_cursor_wm_info.max_wm; | |
3352 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3353 | "cursor %d\n", sr_entries, cursor_sr); | |
3354 | ||
0e442c60 | 3355 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3356 | } else { |
3357 | /* Turn off self refresh if both pipes are enabled */ | |
3358 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
5eddb70b | 3359 | & ~FW_BLC_SELF_EN); |
0e442c60 JB |
3360 | } |
3361 | ||
3362 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", | |
3363 | planea_wm, planeb_wm, sr_entries); | |
3364 | ||
3365 | planea_wm &= 0x3f; | |
3366 | planeb_wm &= 0x3f; | |
3367 | ||
3368 | I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) | | |
3369 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
3370 | (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm); | |
3371 | I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
3372 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
3373 | /* HPLL off in SR has some issues on G4x... disable it */ | |
3374 | I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
3375 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
652c393a JB |
3376 | } |
3377 | ||
1dc7546d | 3378 | static void i965_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3379 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3380 | int pixel_size) | |
7662c8bd SL |
3381 | { |
3382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dc7546d JB |
3383 | unsigned long line_time_us; |
3384 | int sr_clock, sr_entries, srwm = 1; | |
4fe5e611 | 3385 | int cursor_sr = 16; |
1dc7546d JB |
3386 | |
3387 | /* Calc sr entries for one plane configs */ | |
3388 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3389 | /* self-refresh has much higher latency */ | |
69e302a9 | 3390 | static const int sr_latency_ns = 12000; |
1dc7546d JB |
3391 | |
3392 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3393 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
1dc7546d JB |
3394 | |
3395 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3396 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3397 | pixel_size * sr_hdisplay; |
8de9b311 | 3398 | sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE); |
1dc7546d | 3399 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
1b07e04e | 3400 | srwm = I965_FIFO_SIZE - sr_entries; |
1dc7546d JB |
3401 | if (srwm < 0) |
3402 | srwm = 1; | |
1b07e04e | 3403 | srwm &= 0x1ff; |
4fe5e611 ZY |
3404 | |
3405 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
5eddb70b | 3406 | pixel_size * 64; |
8de9b311 CW |
3407 | sr_entries = DIV_ROUND_UP(sr_entries, |
3408 | i965_cursor_wm_info.cacheline_size); | |
4fe5e611 | 3409 | cursor_sr = i965_cursor_wm_info.fifo_size - |
5eddb70b | 3410 | (sr_entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
3411 | |
3412 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
3413 | cursor_sr = i965_cursor_wm_info.max_wm; | |
3414 | ||
3415 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3416 | "cursor %d\n", srwm, cursor_sr); | |
3417 | ||
a6c45cf0 | 3418 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 3419 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3420 | } else { |
3421 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 3422 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
3423 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
3424 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 3425 | } |
7662c8bd | 3426 | |
1dc7546d JB |
3427 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
3428 | srwm); | |
7662c8bd SL |
3429 | |
3430 | /* 965 has limitations... */ | |
1dc7546d JB |
3431 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) | |
3432 | (8 << 0)); | |
7662c8bd | 3433 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
3434 | /* update cursor SR watermark */ |
3435 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
3436 | } |
3437 | ||
3438 | static void i9xx_update_wm(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
3439 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3440 | int pixel_size) | |
7662c8bd SL |
3441 | { |
3442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dff33cfc JB |
3443 | uint32_t fwater_lo; |
3444 | uint32_t fwater_hi; | |
3445 | int total_size, cacheline_size, cwm, srwm = 1; | |
3446 | int planea_wm, planeb_wm; | |
3447 | struct intel_watermark_params planea_params, planeb_params; | |
7662c8bd SL |
3448 | unsigned long line_time_us; |
3449 | int sr_clock, sr_entries = 0; | |
3450 | ||
dff33cfc | 3451 | /* Create copies of the base settings for each pipe */ |
a6c45cf0 | 3452 | if (IS_CRESTLINE(dev) || IS_I945GM(dev)) |
dff33cfc | 3453 | planea_params = planeb_params = i945_wm_info; |
a6c45cf0 | 3454 | else if (!IS_GEN2(dev)) |
dff33cfc | 3455 | planea_params = planeb_params = i915_wm_info; |
7662c8bd | 3456 | else |
dff33cfc | 3457 | planea_params = planeb_params = i855_wm_info; |
7662c8bd | 3458 | |
dff33cfc JB |
3459 | /* Grab a couple of global values before we overwrite them */ |
3460 | total_size = planea_params.fifo_size; | |
3461 | cacheline_size = planea_params.cacheline_size; | |
7662c8bd | 3462 | |
dff33cfc | 3463 | /* Update per-plane FIFO sizes */ |
e70236a8 JB |
3464 | planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
3465 | planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
7662c8bd | 3466 | |
dff33cfc JB |
3467 | planea_wm = intel_calculate_wm(planea_clock, &planea_params, |
3468 | pixel_size, latency_ns); | |
3469 | planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, | |
3470 | pixel_size, latency_ns); | |
28c97730 | 3471 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
3472 | |
3473 | /* | |
3474 | * Overlay gets an aggressive default since video jitter is bad. | |
3475 | */ | |
3476 | cwm = 2; | |
3477 | ||
dff33cfc | 3478 | /* Calc sr entries for one plane configs */ |
652c393a JB |
3479 | if (HAS_FW_BLC(dev) && sr_hdisplay && |
3480 | (!planea_clock || !planeb_clock)) { | |
dff33cfc | 3481 | /* self-refresh has much higher latency */ |
69e302a9 | 3482 | static const int sr_latency_ns = 6000; |
dff33cfc | 3483 | |
7662c8bd | 3484 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
fa143215 | 3485 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
dff33cfc JB |
3486 | |
3487 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3488 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3489 | pixel_size * sr_hdisplay; |
8de9b311 | 3490 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
28c97730 | 3491 | DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries); |
dff33cfc JB |
3492 | srwm = total_size - sr_entries; |
3493 | if (srwm < 0) | |
3494 | srwm = 1; | |
ee980b80 LP |
3495 | |
3496 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
3497 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
3498 | else if (IS_I915GM(dev)) { | |
3499 | /* 915M has a smaller SRWM field */ | |
3500 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
3501 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
3502 | } | |
33c5fd12 DJ |
3503 | } else { |
3504 | /* Turn off self refresh if both pipes are enabled */ | |
ee980b80 LP |
3505 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
3506 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
3507 | & ~FW_BLC_SELF_EN); | |
3508 | } else if (IS_I915GM(dev)) { | |
3509 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
3510 | } | |
7662c8bd SL |
3511 | } |
3512 | ||
28c97730 | 3513 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 3514 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 3515 | |
dff33cfc JB |
3516 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
3517 | fwater_hi = (cwm & 0x1f); | |
3518 | ||
3519 | /* Set request length to 8 cachelines per fetch */ | |
3520 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
3521 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
3522 | |
3523 | I915_WRITE(FW_BLC, fwater_lo); | |
3524 | I915_WRITE(FW_BLC2, fwater_hi); | |
7662c8bd SL |
3525 | } |
3526 | ||
e70236a8 | 3527 | static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused, |
fa143215 | 3528 | int unused2, int unused3, int pixel_size) |
7662c8bd SL |
3529 | { |
3530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f3601326 | 3531 | uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
dff33cfc | 3532 | int planea_wm; |
7662c8bd | 3533 | |
e70236a8 | 3534 | i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
7662c8bd | 3535 | |
dff33cfc JB |
3536 | planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, |
3537 | pixel_size, latency_ns); | |
f3601326 JB |
3538 | fwater_lo |= (3<<8) | planea_wm; |
3539 | ||
28c97730 | 3540 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
3541 | |
3542 | I915_WRITE(FW_BLC, fwater_lo); | |
3543 | } | |
3544 | ||
7f8a8569 | 3545 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 3546 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 3547 | |
4ed765f9 CW |
3548 | static bool ironlake_compute_wm0(struct drm_device *dev, |
3549 | int pipe, | |
1398261a | 3550 | const struct intel_watermark_params *display, |
a0fa62d3 | 3551 | int display_latency_ns, |
1398261a | 3552 | const struct intel_watermark_params *cursor, |
a0fa62d3 | 3553 | int cursor_latency_ns, |
4ed765f9 CW |
3554 | int *plane_wm, |
3555 | int *cursor_wm) | |
7f8a8569 | 3556 | { |
c936f44d | 3557 | struct drm_crtc *crtc; |
db66e37d CW |
3558 | int htotal, hdisplay, clock, pixel_size; |
3559 | int line_time_us, line_count; | |
3560 | int entries, tlb_miss; | |
c936f44d | 3561 | |
4ed765f9 CW |
3562 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
3563 | if (crtc->fb == NULL || !crtc->enabled) | |
3564 | return false; | |
7f8a8569 | 3565 | |
4ed765f9 CW |
3566 | htotal = crtc->mode.htotal; |
3567 | hdisplay = crtc->mode.hdisplay; | |
3568 | clock = crtc->mode.clock; | |
3569 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3570 | ||
3571 | /* Use the small buffer method to calculate plane watermark */ | |
a0fa62d3 | 3572 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
db66e37d CW |
3573 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
3574 | if (tlb_miss > 0) | |
3575 | entries += tlb_miss; | |
1398261a YL |
3576 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
3577 | *plane_wm = entries + display->guard_size; | |
3578 | if (*plane_wm > (int)display->max_wm) | |
3579 | *plane_wm = display->max_wm; | |
4ed765f9 CW |
3580 | |
3581 | /* Use the large buffer method to calculate cursor watermark */ | |
3582 | line_time_us = ((htotal * 1000) / clock); | |
a0fa62d3 | 3583 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
4ed765f9 | 3584 | entries = line_count * 64 * pixel_size; |
db66e37d CW |
3585 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
3586 | if (tlb_miss > 0) | |
3587 | entries += tlb_miss; | |
1398261a YL |
3588 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
3589 | *cursor_wm = entries + cursor->guard_size; | |
3590 | if (*cursor_wm > (int)cursor->max_wm) | |
3591 | *cursor_wm = (int)cursor->max_wm; | |
7f8a8569 | 3592 | |
4ed765f9 CW |
3593 | return true; |
3594 | } | |
c936f44d | 3595 | |
1398261a YL |
3596 | /* |
3597 | * Check the wm result. | |
3598 | * | |
3599 | * If any calculated watermark values is larger than the maximum value that | |
3600 | * can be programmed into the associated watermark register, that watermark | |
3601 | * must be disabled. | |
1398261a | 3602 | */ |
b79d4990 JB |
3603 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
3604 | int fbc_wm, int display_wm, int cursor_wm, | |
3605 | const struct intel_watermark_params *display, | |
3606 | const struct intel_watermark_params *cursor) | |
1398261a YL |
3607 | { |
3608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3609 | ||
3610 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," | |
3611 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); | |
3612 | ||
3613 | if (fbc_wm > SNB_FBC_MAX_SRWM) { | |
3614 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", | |
b79d4990 | 3615 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1398261a YL |
3616 | |
3617 | /* fbc has it's own way to disable FBC WM */ | |
3618 | I915_WRITE(DISP_ARB_CTL, | |
3619 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); | |
3620 | return false; | |
3621 | } | |
3622 | ||
b79d4990 | 3623 | if (display_wm > display->max_wm) { |
1398261a | 3624 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 3625 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1398261a YL |
3626 | return false; |
3627 | } | |
3628 | ||
b79d4990 | 3629 | if (cursor_wm > cursor->max_wm) { |
1398261a | 3630 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 3631 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1398261a YL |
3632 | return false; |
3633 | } | |
3634 | ||
3635 | if (!(fbc_wm || display_wm || cursor_wm)) { | |
3636 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); | |
3637 | return false; | |
3638 | } | |
3639 | ||
3640 | return true; | |
3641 | } | |
3642 | ||
3643 | /* | |
3644 | * Compute watermark values of WM[1-3], | |
3645 | */ | |
b79d4990 JB |
3646 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, |
3647 | int hdisplay, int htotal, | |
3648 | int pixel_size, int clock, int latency_ns, | |
3649 | const struct intel_watermark_params *display, | |
3650 | const struct intel_watermark_params *cursor, | |
3651 | int *fbc_wm, int *display_wm, int *cursor_wm) | |
1398261a YL |
3652 | { |
3653 | ||
3654 | unsigned long line_time_us; | |
b79d4990 | 3655 | int line_count, line_size; |
1398261a YL |
3656 | int small, large; |
3657 | int entries; | |
1398261a YL |
3658 | |
3659 | if (!latency_ns) { | |
3660 | *fbc_wm = *display_wm = *cursor_wm = 0; | |
3661 | return false; | |
3662 | } | |
3663 | ||
3664 | line_time_us = (htotal * 1000) / clock; | |
3665 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
3666 | line_size = hdisplay * pixel_size; | |
3667 | ||
3668 | /* Use the minimum of the small and large buffer method for primary */ | |
3669 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
3670 | large = line_count * line_size; | |
3671 | ||
b79d4990 JB |
3672 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
3673 | *display_wm = entries + display->guard_size; | |
1398261a YL |
3674 | |
3675 | /* | |
b79d4990 | 3676 | * Spec says: |
1398261a YL |
3677 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
3678 | */ | |
3679 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; | |
3680 | ||
3681 | /* calculate the self-refresh watermark for display cursor */ | |
3682 | entries = line_count * pixel_size * 64; | |
b79d4990 JB |
3683 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
3684 | *cursor_wm = entries + cursor->guard_size; | |
1398261a | 3685 | |
b79d4990 JB |
3686 | return ironlake_check_srwm(dev, level, |
3687 | *fbc_wm, *display_wm, *cursor_wm, | |
3688 | display, cursor); | |
3689 | } | |
3690 | ||
3691 | static void ironlake_update_wm(struct drm_device *dev, | |
3692 | int planea_clock, int planeb_clock, | |
3693 | int hdisplay, int htotal, | |
3694 | int pixel_size) | |
3695 | { | |
3696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3697 | int fbc_wm, plane_wm, cursor_wm, enabled; | |
3698 | int clock; | |
3699 | ||
3700 | enabled = 0; | |
3701 | if (ironlake_compute_wm0(dev, 0, | |
3702 | &ironlake_display_wm_info, | |
3703 | ILK_LP0_PLANE_LATENCY, | |
3704 | &ironlake_cursor_wm_info, | |
3705 | ILK_LP0_CURSOR_LATENCY, | |
3706 | &plane_wm, &cursor_wm)) { | |
3707 | I915_WRITE(WM0_PIPEA_ILK, | |
3708 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3709 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
3710 | " plane %d, " "cursor: %d\n", | |
3711 | plane_wm, cursor_wm); | |
3712 | enabled++; | |
3713 | } | |
3714 | ||
3715 | if (ironlake_compute_wm0(dev, 1, | |
3716 | &ironlake_display_wm_info, | |
3717 | ILK_LP0_PLANE_LATENCY, | |
3718 | &ironlake_cursor_wm_info, | |
3719 | ILK_LP0_CURSOR_LATENCY, | |
3720 | &plane_wm, &cursor_wm)) { | |
3721 | I915_WRITE(WM0_PIPEB_ILK, | |
3722 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3723 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
3724 | " plane %d, cursor: %d\n", | |
3725 | plane_wm, cursor_wm); | |
3726 | enabled++; | |
3727 | } | |
3728 | ||
3729 | /* | |
3730 | * Calculate and update the self-refresh watermark only when one | |
3731 | * display plane is used. | |
3732 | */ | |
3733 | I915_WRITE(WM3_LP_ILK, 0); | |
3734 | I915_WRITE(WM2_LP_ILK, 0); | |
3735 | I915_WRITE(WM1_LP_ILK, 0); | |
3736 | ||
3737 | if (enabled != 1) | |
3738 | return; | |
3739 | ||
3740 | clock = planea_clock ? planea_clock : planeb_clock; | |
3741 | ||
3742 | /* WM1 */ | |
3743 | if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size, | |
3744 | clock, ILK_READ_WM1_LATENCY() * 500, | |
3745 | &ironlake_display_srwm_info, | |
3746 | &ironlake_cursor_srwm_info, | |
3747 | &fbc_wm, &plane_wm, &cursor_wm)) | |
3748 | return; | |
3749 | ||
3750 | I915_WRITE(WM1_LP_ILK, | |
3751 | WM1_LP_SR_EN | | |
3752 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
3753 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
3754 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3755 | cursor_wm); | |
3756 | ||
3757 | /* WM2 */ | |
3758 | if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size, | |
3759 | clock, ILK_READ_WM2_LATENCY() * 500, | |
3760 | &ironlake_display_srwm_info, | |
3761 | &ironlake_cursor_srwm_info, | |
3762 | &fbc_wm, &plane_wm, &cursor_wm)) | |
3763 | return; | |
3764 | ||
3765 | I915_WRITE(WM2_LP_ILK, | |
3766 | WM2_LP_EN | | |
3767 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
3768 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
3769 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3770 | cursor_wm); | |
3771 | ||
3772 | /* | |
3773 | * WM3 is unsupported on ILK, probably because we don't have latency | |
3774 | * data for that power state | |
3775 | */ | |
1398261a YL |
3776 | } |
3777 | ||
3778 | static void sandybridge_update_wm(struct drm_device *dev, | |
3779 | int planea_clock, int planeb_clock, | |
3780 | int hdisplay, int htotal, | |
3781 | int pixel_size) | |
3782 | { | |
3783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a0fa62d3 | 3784 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
1398261a YL |
3785 | int fbc_wm, plane_wm, cursor_wm, enabled; |
3786 | int clock; | |
3787 | ||
3788 | enabled = 0; | |
3789 | if (ironlake_compute_wm0(dev, 0, | |
3790 | &sandybridge_display_wm_info, latency, | |
3791 | &sandybridge_cursor_wm_info, latency, | |
3792 | &plane_wm, &cursor_wm)) { | |
3793 | I915_WRITE(WM0_PIPEA_ILK, | |
3794 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3795 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
3796 | " plane %d, " "cursor: %d\n", | |
3797 | plane_wm, cursor_wm); | |
3798 | enabled++; | |
3799 | } | |
3800 | ||
3801 | if (ironlake_compute_wm0(dev, 1, | |
3802 | &sandybridge_display_wm_info, latency, | |
3803 | &sandybridge_cursor_wm_info, latency, | |
3804 | &plane_wm, &cursor_wm)) { | |
3805 | I915_WRITE(WM0_PIPEB_ILK, | |
3806 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3807 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
3808 | " plane %d, cursor: %d\n", | |
3809 | plane_wm, cursor_wm); | |
3810 | enabled++; | |
3811 | } | |
3812 | ||
3813 | /* | |
3814 | * Calculate and update the self-refresh watermark only when one | |
3815 | * display plane is used. | |
3816 | * | |
3817 | * SNB support 3 levels of watermark. | |
3818 | * | |
3819 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
3820 | * and disabled in the descending order | |
3821 | * | |
3822 | */ | |
3823 | I915_WRITE(WM3_LP_ILK, 0); | |
3824 | I915_WRITE(WM2_LP_ILK, 0); | |
3825 | I915_WRITE(WM1_LP_ILK, 0); | |
3826 | ||
3827 | if (enabled != 1) | |
3828 | return; | |
3829 | ||
3830 | clock = planea_clock ? planea_clock : planeb_clock; | |
3831 | ||
3832 | /* WM1 */ | |
b79d4990 JB |
3833 | if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size, |
3834 | clock, SNB_READ_WM1_LATENCY() * 500, | |
3835 | &sandybridge_display_srwm_info, | |
3836 | &sandybridge_cursor_srwm_info, | |
3837 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
3838 | return; |
3839 | ||
3840 | I915_WRITE(WM1_LP_ILK, | |
3841 | WM1_LP_SR_EN | | |
3842 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
3843 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
3844 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3845 | cursor_wm); | |
3846 | ||
3847 | /* WM2 */ | |
b79d4990 JB |
3848 | if (!ironlake_compute_srwm(dev, 2, |
3849 | hdisplay, htotal, pixel_size, | |
3850 | clock, SNB_READ_WM2_LATENCY() * 500, | |
3851 | &sandybridge_display_srwm_info, | |
3852 | &sandybridge_cursor_srwm_info, | |
3853 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
3854 | return; |
3855 | ||
3856 | I915_WRITE(WM2_LP_ILK, | |
3857 | WM2_LP_EN | | |
3858 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
3859 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
3860 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3861 | cursor_wm); | |
3862 | ||
3863 | /* WM3 */ | |
b79d4990 JB |
3864 | if (!ironlake_compute_srwm(dev, 3, |
3865 | hdisplay, htotal, pixel_size, | |
3866 | clock, SNB_READ_WM3_LATENCY() * 500, | |
3867 | &sandybridge_display_srwm_info, | |
3868 | &sandybridge_cursor_srwm_info, | |
3869 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
3870 | return; |
3871 | ||
3872 | I915_WRITE(WM3_LP_ILK, | |
3873 | WM3_LP_EN | | |
3874 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
3875 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
3876 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3877 | cursor_wm); | |
3878 | } | |
3879 | ||
7662c8bd SL |
3880 | /** |
3881 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3882 | * | |
3883 | * Calculate watermark values for the various WM regs based on current mode | |
3884 | * and plane configuration. | |
3885 | * | |
3886 | * There are several cases to deal with here: | |
3887 | * - normal (i.e. non-self-refresh) | |
3888 | * - self-refresh (SR) mode | |
3889 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3890 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3891 | * lines), so need to account for TLB latency | |
3892 | * | |
3893 | * The normal calculation is: | |
3894 | * watermark = dotclock * bytes per pixel * latency | |
3895 | * where latency is platform & configuration dependent (we assume pessimal | |
3896 | * values here). | |
3897 | * | |
3898 | * The SR calculation is: | |
3899 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3900 | * bytes per pixel | |
3901 | * where | |
3902 | * line time = htotal / dotclock | |
fa143215 | 3903 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
3904 | * and latency is assumed to be high, as above. |
3905 | * | |
3906 | * The final value programmed to the register should always be rounded up, | |
3907 | * and include an extra 2 entries to account for clock crossings. | |
3908 | * | |
3909 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3910 | * to set the non-SR watermarks to 8. | |
5eddb70b | 3911 | */ |
7662c8bd SL |
3912 | static void intel_update_watermarks(struct drm_device *dev) |
3913 | { | |
e70236a8 | 3914 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 3915 | struct drm_crtc *crtc; |
7662c8bd SL |
3916 | int sr_hdisplay = 0; |
3917 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; | |
3918 | int enabled = 0, pixel_size = 0; | |
fa143215 | 3919 | int sr_htotal = 0; |
7662c8bd | 3920 | |
c03342fa ZW |
3921 | if (!dev_priv->display.update_wm) |
3922 | return; | |
3923 | ||
7662c8bd SL |
3924 | /* Get the clock config from both planes */ |
3925 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
debcaddc | 3926 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f7abfe8b | 3927 | if (intel_crtc->active) { |
7662c8bd SL |
3928 | enabled++; |
3929 | if (intel_crtc->plane == 0) { | |
28c97730 | 3930 | DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", |
5eddb70b | 3931 | intel_crtc->pipe, crtc->mode.clock); |
7662c8bd SL |
3932 | planea_clock = crtc->mode.clock; |
3933 | } else { | |
28c97730 | 3934 | DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n", |
5eddb70b | 3935 | intel_crtc->pipe, crtc->mode.clock); |
7662c8bd SL |
3936 | planeb_clock = crtc->mode.clock; |
3937 | } | |
3938 | sr_hdisplay = crtc->mode.hdisplay; | |
3939 | sr_clock = crtc->mode.clock; | |
fa143215 | 3940 | sr_htotal = crtc->mode.htotal; |
7662c8bd SL |
3941 | if (crtc->fb) |
3942 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3943 | else | |
3944 | pixel_size = 4; /* by default */ | |
3945 | } | |
3946 | } | |
3947 | ||
3948 | if (enabled <= 0) | |
3949 | return; | |
3950 | ||
e70236a8 | 3951 | dev_priv->display.update_wm(dev, planea_clock, planeb_clock, |
fa143215 | 3952 | sr_hdisplay, sr_htotal, pixel_size); |
7662c8bd SL |
3953 | } |
3954 | ||
a7615030 CW |
3955 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
3956 | { | |
3957 | return dev_priv->lvds_use_ssc && i915_panel_use_ssc; | |
3958 | } | |
3959 | ||
5c3b82e2 CW |
3960 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
3961 | struct drm_display_mode *mode, | |
3962 | struct drm_display_mode *adjusted_mode, | |
3963 | int x, int y, | |
3964 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
3965 | { |
3966 | struct drm_device *dev = crtc->dev; | |
3967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3968 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3969 | int pipe = intel_crtc->pipe; | |
80824003 | 3970 | int plane = intel_crtc->plane; |
5eddb70b | 3971 | u32 fp_reg, dpll_reg; |
c751ce4f | 3972 | int refclk, num_connectors = 0; |
652c393a | 3973 | intel_clock_t clock, reduced_clock; |
5eddb70b | 3974 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
652c393a | 3975 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
a4fc5ed6 | 3976 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 3977 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 3978 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 3979 | struct intel_encoder *encoder; |
d4906093 | 3980 | const intel_limit_t *limit; |
5c3b82e2 | 3981 | int ret; |
2c07245f | 3982 | struct fdi_m_n m_n = {0}; |
5eddb70b | 3983 | u32 reg, temp; |
5eb08b69 | 3984 | int target_clock; |
79e53945 JB |
3985 | |
3986 | drm_vblank_pre_modeset(dev, pipe); | |
3987 | ||
5eddb70b CW |
3988 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
3989 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
3990 | continue; |
3991 | ||
5eddb70b | 3992 | switch (encoder->type) { |
79e53945 JB |
3993 | case INTEL_OUTPUT_LVDS: |
3994 | is_lvds = true; | |
3995 | break; | |
3996 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 3997 | case INTEL_OUTPUT_HDMI: |
79e53945 | 3998 | is_sdvo = true; |
5eddb70b | 3999 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4000 | is_tv = true; |
79e53945 JB |
4001 | break; |
4002 | case INTEL_OUTPUT_DVO: | |
4003 | is_dvo = true; | |
4004 | break; | |
4005 | case INTEL_OUTPUT_TVOUT: | |
4006 | is_tv = true; | |
4007 | break; | |
4008 | case INTEL_OUTPUT_ANALOG: | |
4009 | is_crt = true; | |
4010 | break; | |
a4fc5ed6 KP |
4011 | case INTEL_OUTPUT_DISPLAYPORT: |
4012 | is_dp = true; | |
4013 | break; | |
32f9d658 | 4014 | case INTEL_OUTPUT_EDP: |
5eddb70b | 4015 | has_edp_encoder = encoder; |
32f9d658 | 4016 | break; |
79e53945 | 4017 | } |
43565a06 | 4018 | |
c751ce4f | 4019 | num_connectors++; |
79e53945 JB |
4020 | } |
4021 | ||
a7615030 | 4022 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
43565a06 | 4023 | refclk = dev_priv->lvds_ssc_freq * 1000; |
28c97730 | 4024 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5eddb70b | 4025 | refclk / 1000); |
a6c45cf0 | 4026 | } else if (!IS_GEN2(dev)) { |
79e53945 | 4027 | refclk = 96000; |
1cb1b75e JB |
4028 | if (HAS_PCH_SPLIT(dev) && |
4029 | (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base))) | |
2c07245f | 4030 | refclk = 120000; /* 120Mhz refclk */ |
79e53945 JB |
4031 | } else { |
4032 | refclk = 48000; | |
4033 | } | |
4034 | ||
d4906093 ML |
4035 | /* |
4036 | * Returns a set of divisors for the desired target clock with the given | |
4037 | * refclk, or FALSE. The returned values represent the clock equation: | |
4038 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4039 | */ | |
1b894b59 | 4040 | limit = intel_limit(crtc, refclk); |
d4906093 | 4041 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); |
79e53945 JB |
4042 | if (!ok) { |
4043 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
1f803ee5 | 4044 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 4045 | return -EINVAL; |
79e53945 JB |
4046 | } |
4047 | ||
cda4b7d3 | 4048 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4049 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4050 | |
ddc9003c ZY |
4051 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4052 | has_reduced_clock = limit->find_pll(limit, crtc, | |
5eddb70b CW |
4053 | dev_priv->lvds_downclock, |
4054 | refclk, | |
4055 | &reduced_clock); | |
18f9ed12 ZY |
4056 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
4057 | /* | |
4058 | * If the different P is found, it means that we can't | |
4059 | * switch the display clock by using the FP0/FP1. | |
4060 | * In such case we will disable the LVDS downclock | |
4061 | * feature. | |
4062 | */ | |
4063 | DRM_DEBUG_KMS("Different P is found for " | |
5eddb70b | 4064 | "LVDS clock/downclock\n"); |
18f9ed12 ZY |
4065 | has_reduced_clock = 0; |
4066 | } | |
652c393a | 4067 | } |
7026d4ac ZW |
4068 | /* SDVO TV has fixed PLL values depend on its clock range, |
4069 | this mirrors vbios setting. */ | |
4070 | if (is_sdvo && is_tv) { | |
4071 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 4072 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
4073 | clock.p1 = 2; |
4074 | clock.p2 = 10; | |
4075 | clock.n = 3; | |
4076 | clock.m1 = 16; | |
4077 | clock.m2 = 8; | |
4078 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 4079 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
4080 | clock.p1 = 1; |
4081 | clock.p2 = 10; | |
4082 | clock.n = 6; | |
4083 | clock.m1 = 12; | |
4084 | clock.m2 = 8; | |
4085 | } | |
4086 | } | |
4087 | ||
2c07245f | 4088 | /* FDI link */ |
bad720ff | 4089 | if (HAS_PCH_SPLIT(dev)) { |
49078f7d | 4090 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
77ffb597 | 4091 | int lane = 0, link_bw, bpp; |
5c5313c8 | 4092 | /* CPU eDP doesn't require FDI link, so just set DP M/N |
32f9d658 | 4093 | according to current link config */ |
858bc21f | 4094 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
5eb08b69 | 4095 | target_clock = mode->clock; |
8e647a27 CW |
4096 | intel_edp_link_config(has_edp_encoder, |
4097 | &lane, &link_bw); | |
32f9d658 | 4098 | } else { |
5c5313c8 | 4099 | /* [e]DP over FDI requires target mode clock |
32f9d658 | 4100 | instead of link clock */ |
5c5313c8 | 4101 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) |
32f9d658 ZW |
4102 | target_clock = mode->clock; |
4103 | else | |
4104 | target_clock = adjusted_mode->clock; | |
021357ac CW |
4105 | |
4106 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
4107 | * each output octet as 10 bits. The actual frequency | |
4108 | * is stored as a divider into a 100MHz clock, and the | |
4109 | * mode pixel clock is stored in units of 1KHz. | |
4110 | * Hence the bw of each lane in terms of the mode signal | |
4111 | * is: | |
4112 | */ | |
4113 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
32f9d658 | 4114 | } |
58a27471 ZW |
4115 | |
4116 | /* determine panel color depth */ | |
5eddb70b | 4117 | temp = I915_READ(PIPECONF(pipe)); |
e5a95eb7 ZY |
4118 | temp &= ~PIPE_BPC_MASK; |
4119 | if (is_lvds) { | |
e5a95eb7 | 4120 | /* the BPC will be 6 if it is 18-bit LVDS panel */ |
5eddb70b | 4121 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) |
e5a95eb7 ZY |
4122 | temp |= PIPE_8BPC; |
4123 | else | |
4124 | temp |= PIPE_6BPC; | |
1d850362 | 4125 | } else if (has_edp_encoder) { |
5ceb0f9b | 4126 | switch (dev_priv->edp.bpp/3) { |
885a5fb5 ZW |
4127 | case 8: |
4128 | temp |= PIPE_8BPC; | |
4129 | break; | |
4130 | case 10: | |
4131 | temp |= PIPE_10BPC; | |
4132 | break; | |
4133 | case 6: | |
4134 | temp |= PIPE_6BPC; | |
4135 | break; | |
4136 | case 12: | |
4137 | temp |= PIPE_12BPC; | |
4138 | break; | |
4139 | } | |
e5a95eb7 ZY |
4140 | } else |
4141 | temp |= PIPE_8BPC; | |
5eddb70b | 4142 | I915_WRITE(PIPECONF(pipe), temp); |
58a27471 ZW |
4143 | |
4144 | switch (temp & PIPE_BPC_MASK) { | |
4145 | case PIPE_8BPC: | |
4146 | bpp = 24; | |
4147 | break; | |
4148 | case PIPE_10BPC: | |
4149 | bpp = 30; | |
4150 | break; | |
4151 | case PIPE_6BPC: | |
4152 | bpp = 18; | |
4153 | break; | |
4154 | case PIPE_12BPC: | |
4155 | bpp = 36; | |
4156 | break; | |
4157 | default: | |
4158 | DRM_ERROR("unknown pipe bpc value\n"); | |
4159 | bpp = 24; | |
4160 | } | |
4161 | ||
77ffb597 AJ |
4162 | if (!lane) { |
4163 | /* | |
4164 | * Account for spread spectrum to avoid | |
4165 | * oversubscribing the link. Max center spread | |
4166 | * is 2.5%; use 5% for safety's sake. | |
4167 | */ | |
4168 | u32 bps = target_clock * bpp * 21 / 20; | |
4169 | lane = bps / (link_bw * 8) + 1; | |
4170 | } | |
4171 | ||
4172 | intel_crtc->fdi_lanes = lane; | |
4173 | ||
49078f7d CW |
4174 | if (pixel_multiplier > 1) |
4175 | link_bw *= pixel_multiplier; | |
f2b115e6 | 4176 | ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); |
5eb08b69 | 4177 | } |
2c07245f | 4178 | |
c038e51e ZW |
4179 | /* Ironlake: try to setup display ref clock before DPLL |
4180 | * enabling. This is only under driver's control after | |
4181 | * PCH B stepping, previous chipset stepping should be | |
4182 | * ignoring this setting. | |
4183 | */ | |
bad720ff | 4184 | if (HAS_PCH_SPLIT(dev)) { |
c038e51e ZW |
4185 | temp = I915_READ(PCH_DREF_CONTROL); |
4186 | /* Always enable nonspread source */ | |
4187 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
4188 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
c038e51e ZW |
4189 | temp &= ~DREF_SSC_SOURCE_MASK; |
4190 | temp |= DREF_SSC_SOURCE_ENABLE; | |
4191 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
c038e51e | 4192 | |
5eddb70b | 4193 | POSTING_READ(PCH_DREF_CONTROL); |
c038e51e ZW |
4194 | udelay(200); |
4195 | ||
8e647a27 | 4196 | if (has_edp_encoder) { |
a7615030 | 4197 | if (intel_panel_use_ssc(dev_priv)) { |
c038e51e ZW |
4198 | temp |= DREF_SSC1_ENABLE; |
4199 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
c038e51e | 4200 | |
5eddb70b | 4201 | POSTING_READ(PCH_DREF_CONTROL); |
c038e51e | 4202 | udelay(200); |
7f823282 JB |
4203 | } |
4204 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
4205 | ||
4206 | /* Enable CPU source on CPU attached eDP */ | |
4207 | if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
a7615030 | 4208 | if (intel_panel_use_ssc(dev_priv)) |
7f823282 JB |
4209 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
4210 | else | |
4211 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
c038e51e | 4212 | } else { |
7f823282 | 4213 | /* Enable SSC on PCH eDP if needed */ |
a7615030 | 4214 | if (intel_panel_use_ssc(dev_priv)) { |
7f823282 JB |
4215 | DRM_ERROR("enabling SSC on PCH\n"); |
4216 | temp |= DREF_SUPERSPREAD_SOURCE_ENABLE; | |
4217 | } | |
c038e51e | 4218 | } |
5eddb70b | 4219 | I915_WRITE(PCH_DREF_CONTROL, temp); |
7f823282 JB |
4220 | POSTING_READ(PCH_DREF_CONTROL); |
4221 | udelay(200); | |
c038e51e ZW |
4222 | } |
4223 | } | |
4224 | ||
f2b115e6 | 4225 | if (IS_PINEVIEW(dev)) { |
2177832f | 4226 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
4227 | if (has_reduced_clock) |
4228 | fp2 = (1 << reduced_clock.n) << 16 | | |
4229 | reduced_clock.m1 << 8 | reduced_clock.m2; | |
4230 | } else { | |
2177832f | 4231 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
4232 | if (has_reduced_clock) |
4233 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
4234 | reduced_clock.m2; | |
4235 | } | |
79e53945 | 4236 | |
c1858123 CW |
4237 | /* Enable autotuning of the PLL clock (if permissible) */ |
4238 | if (HAS_PCH_SPLIT(dev)) { | |
4239 | int factor = 21; | |
4240 | ||
4241 | if (is_lvds) { | |
a7615030 | 4242 | if ((intel_panel_use_ssc(dev_priv) && |
c1858123 CW |
4243 | dev_priv->lvds_ssc_freq == 100) || |
4244 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
4245 | factor = 25; | |
4246 | } else if (is_sdvo && is_tv) | |
4247 | factor = 20; | |
4248 | ||
4249 | if (clock.m1 < factor * clock.n) | |
4250 | fp |= FP_CB_TUNE; | |
4251 | } | |
4252 | ||
5eddb70b | 4253 | dpll = 0; |
bad720ff | 4254 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
4255 | dpll = DPLL_VGA_MODE_DIS; |
4256 | ||
a6c45cf0 | 4257 | if (!IS_GEN2(dev)) { |
79e53945 JB |
4258 | if (is_lvds) |
4259 | dpll |= DPLLB_MODE_LVDS; | |
4260 | else | |
4261 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4262 | if (is_sdvo) { | |
6c9547ff CW |
4263 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4264 | if (pixel_multiplier > 1) { | |
4265 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4266 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
4267 | else if (HAS_PCH_SPLIT(dev)) | |
4268 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
4269 | } | |
79e53945 | 4270 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 4271 | } |
83240120 | 4272 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) |
a4fc5ed6 | 4273 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 JB |
4274 | |
4275 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
4276 | if (IS_PINEVIEW(dev)) |
4277 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 4278 | else { |
2177832f | 4279 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
2c07245f | 4280 | /* also FPA1 */ |
bad720ff | 4281 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 4282 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
652c393a JB |
4283 | if (IS_G4X(dev) && has_reduced_clock) |
4284 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 4285 | } |
79e53945 JB |
4286 | switch (clock.p2) { |
4287 | case 5: | |
4288 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4289 | break; | |
4290 | case 7: | |
4291 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4292 | break; | |
4293 | case 10: | |
4294 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4295 | break; | |
4296 | case 14: | |
4297 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4298 | break; | |
4299 | } | |
a6c45cf0 | 4300 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) |
79e53945 JB |
4301 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
4302 | } else { | |
4303 | if (is_lvds) { | |
4304 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4305 | } else { | |
4306 | if (clock.p1 == 2) | |
4307 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4308 | else | |
4309 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4310 | if (clock.p2 == 4) | |
4311 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4312 | } | |
4313 | } | |
4314 | ||
43565a06 KH |
4315 | if (is_sdvo && is_tv) |
4316 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4317 | else if (is_tv) | |
79e53945 | 4318 | /* XXX: just matching BIOS for now */ |
43565a06 | 4319 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 4320 | dpll |= 3; |
a7615030 | 4321 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 4322 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
4323 | else |
4324 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4325 | ||
4326 | /* setup pipeconf */ | |
5eddb70b | 4327 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4328 | |
4329 | /* Set up the display plane register */ | |
4330 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4331 | ||
f2b115e6 | 4332 | /* Ironlake's plane is forced to pipe, bit 24 is to |
2c07245f | 4333 | enable color space conversion */ |
bad720ff | 4334 | if (!HAS_PCH_SPLIT(dev)) { |
2c07245f | 4335 | if (pipe == 0) |
80824003 | 4336 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
2c07245f ZW |
4337 | else |
4338 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4339 | } | |
79e53945 | 4340 | |
a6c45cf0 | 4341 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
4342 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4343 | * core speed. | |
4344 | * | |
4345 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4346 | * pipe == 0 check? | |
4347 | */ | |
e70236a8 JB |
4348 | if (mode->clock > |
4349 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 4350 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 4351 | else |
5eddb70b | 4352 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
4353 | } |
4354 | ||
b24e7179 | 4355 | if (!HAS_PCH_SPLIT(dev)) |
65993d64 | 4356 | dpll |= DPLL_VCO_ENABLE; |
8d86dc6a | 4357 | |
28c97730 | 4358 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
4359 | drm_mode_debug_printmodeline(mode); |
4360 | ||
f2b115e6 | 4361 | /* assign to Ironlake registers */ |
bad720ff | 4362 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4363 | fp_reg = PCH_FP0(pipe); |
4364 | dpll_reg = PCH_DPLL(pipe); | |
4365 | } else { | |
4366 | fp_reg = FP0(pipe); | |
4367 | dpll_reg = DPLL(pipe); | |
2c07245f | 4368 | } |
79e53945 | 4369 | |
5c5313c8 JB |
4370 | /* PCH eDP needs FDI, but CPU eDP does not */ |
4371 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
79e53945 JB |
4372 | I915_WRITE(fp_reg, fp); |
4373 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
5eddb70b CW |
4374 | |
4375 | POSTING_READ(dpll_reg); | |
79e53945 JB |
4376 | udelay(150); |
4377 | } | |
4378 | ||
8db9d77b ZW |
4379 | /* enable transcoder DPLL */ |
4380 | if (HAS_PCH_CPT(dev)) { | |
4381 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b CW |
4382 | if (pipe == 0) |
4383 | temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; | |
8db9d77b | 4384 | else |
5eddb70b | 4385 | temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; |
8db9d77b | 4386 | I915_WRITE(PCH_DPLL_SEL, temp); |
5eddb70b CW |
4387 | |
4388 | POSTING_READ(PCH_DPLL_SEL); | |
8db9d77b ZW |
4389 | udelay(150); |
4390 | } | |
4391 | ||
79e53945 JB |
4392 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4393 | * This is an exception to the general rule that mode_set doesn't turn | |
4394 | * things on. | |
4395 | */ | |
4396 | if (is_lvds) { | |
5eddb70b | 4397 | reg = LVDS; |
bad720ff | 4398 | if (HAS_PCH_SPLIT(dev)) |
5eddb70b | 4399 | reg = PCH_LVDS; |
541998a1 | 4400 | |
5eddb70b CW |
4401 | temp = I915_READ(reg); |
4402 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
b3b095b3 ZW |
4403 | if (pipe == 1) { |
4404 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 4405 | temp |= PORT_TRANS_B_SEL_CPT; |
b3b095b3 | 4406 | else |
5eddb70b | 4407 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 ZW |
4408 | } else { |
4409 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 4410 | temp &= ~PORT_TRANS_SEL_MASK; |
b3b095b3 | 4411 | else |
5eddb70b | 4412 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 4413 | } |
a3e17eb8 | 4414 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 4415 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
4416 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
4417 | * set the DPLLs for dual-channel mode or not. | |
4418 | */ | |
4419 | if (clock.p2 == 7) | |
5eddb70b | 4420 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 4421 | else |
5eddb70b | 4422 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
4423 | |
4424 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
4425 | * appropriately here, but we need to look more thoroughly into how | |
4426 | * panels behave in the two modes. | |
4427 | */ | |
434ed097 | 4428 | /* set the dithering flag on non-PCH LVDS as needed */ |
a6c45cf0 | 4429 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
434ed097 | 4430 | if (dev_priv->lvds_dither) |
5eddb70b | 4431 | temp |= LVDS_ENABLE_DITHER; |
434ed097 | 4432 | else |
5eddb70b | 4433 | temp &= ~LVDS_ENABLE_DITHER; |
898822ce | 4434 | } |
5eddb70b | 4435 | I915_WRITE(reg, temp); |
79e53945 | 4436 | } |
434ed097 JB |
4437 | |
4438 | /* set the dithering flag and clear for anything other than a panel. */ | |
4439 | if (HAS_PCH_SPLIT(dev)) { | |
4440 | pipeconf &= ~PIPECONF_DITHER_EN; | |
4441 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
4442 | if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) { | |
4443 | pipeconf |= PIPECONF_DITHER_EN; | |
4444 | pipeconf |= PIPECONF_DITHER_TYPE_ST1; | |
4445 | } | |
4446 | } | |
4447 | ||
5c5313c8 | 4448 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
a4fc5ed6 | 4449 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
5c5313c8 | 4450 | } else if (HAS_PCH_SPLIT(dev)) { |
8db9d77b ZW |
4451 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
4452 | if (pipe == 0) { | |
4453 | I915_WRITE(TRANSA_DATA_M1, 0); | |
4454 | I915_WRITE(TRANSA_DATA_N1, 0); | |
4455 | I915_WRITE(TRANSA_DP_LINK_M1, 0); | |
4456 | I915_WRITE(TRANSA_DP_LINK_N1, 0); | |
4457 | } else { | |
4458 | I915_WRITE(TRANSB_DATA_M1, 0); | |
4459 | I915_WRITE(TRANSB_DATA_N1, 0); | |
4460 | I915_WRITE(TRANSB_DP_LINK_M1, 0); | |
4461 | I915_WRITE(TRANSB_DP_LINK_N1, 0); | |
4462 | } | |
4463 | } | |
79e53945 | 4464 | |
5c5313c8 | 4465 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
79e53945 | 4466 | I915_WRITE(dpll_reg, dpll); |
5eddb70b | 4467 | |
32f9d658 | 4468 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 4469 | POSTING_READ(dpll_reg); |
32f9d658 ZW |
4470 | udelay(150); |
4471 | ||
a6c45cf0 | 4472 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
5eddb70b | 4473 | temp = 0; |
bb66c512 | 4474 | if (is_sdvo) { |
5eddb70b CW |
4475 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
4476 | if (temp > 1) | |
4477 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6c9547ff | 4478 | else |
5eddb70b CW |
4479 | temp = 0; |
4480 | } | |
4481 | I915_WRITE(DPLL_MD(pipe), temp); | |
32f9d658 | 4482 | } else { |
a589b9f4 CW |
4483 | /* The pixel multiplier can only be updated once the |
4484 | * DPLL is enabled and the clocks are stable. | |
4485 | * | |
4486 | * So write it again. | |
4487 | */ | |
32f9d658 ZW |
4488 | I915_WRITE(dpll_reg, dpll); |
4489 | } | |
79e53945 | 4490 | } |
79e53945 | 4491 | |
5eddb70b | 4492 | intel_crtc->lowfreq_avail = false; |
652c393a JB |
4493 | if (is_lvds && has_reduced_clock && i915_powersave) { |
4494 | I915_WRITE(fp_reg + 4, fp2); | |
4495 | intel_crtc->lowfreq_avail = true; | |
4496 | if (HAS_PIPE_CXSR(dev)) { | |
28c97730 | 4497 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a JB |
4498 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4499 | } | |
4500 | } else { | |
4501 | I915_WRITE(fp_reg + 4, fp); | |
652c393a | 4502 | if (HAS_PIPE_CXSR(dev)) { |
28c97730 | 4503 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
4504 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4505 | } | |
4506 | } | |
4507 | ||
734b4157 KH |
4508 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4509 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
4510 | /* the chip adds 2 halflines automatically */ | |
4511 | adjusted_mode->crtc_vdisplay -= 1; | |
4512 | adjusted_mode->crtc_vtotal -= 1; | |
4513 | adjusted_mode->crtc_vblank_start -= 1; | |
4514 | adjusted_mode->crtc_vblank_end -= 1; | |
4515 | adjusted_mode->crtc_vsync_end -= 1; | |
4516 | adjusted_mode->crtc_vsync_start -= 1; | |
4517 | } else | |
4518 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
4519 | ||
5eddb70b CW |
4520 | I915_WRITE(HTOTAL(pipe), |
4521 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 4522 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
4523 | I915_WRITE(HBLANK(pipe), |
4524 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 4525 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
4526 | I915_WRITE(HSYNC(pipe), |
4527 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 4528 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
4529 | |
4530 | I915_WRITE(VTOTAL(pipe), | |
4531 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 4532 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
4533 | I915_WRITE(VBLANK(pipe), |
4534 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 4535 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
4536 | I915_WRITE(VSYNC(pipe), |
4537 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 4538 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
4539 | |
4540 | /* pipesrc and dspsize control the size that is scaled from, | |
4541 | * which should always be the user's requested size. | |
79e53945 | 4542 | */ |
bad720ff | 4543 | if (!HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4544 | I915_WRITE(DSPSIZE(plane), |
4545 | ((mode->vdisplay - 1) << 16) | | |
4546 | (mode->hdisplay - 1)); | |
4547 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 4548 | } |
5eddb70b CW |
4549 | I915_WRITE(PIPESRC(pipe), |
4550 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 4551 | |
bad720ff | 4552 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4553 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
4554 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
4555 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
4556 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 4557 | |
5c5313c8 | 4558 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
f2b115e6 | 4559 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
32f9d658 | 4560 | } |
2c07245f ZW |
4561 | } |
4562 | ||
5eddb70b CW |
4563 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4564 | POSTING_READ(PIPECONF(pipe)); | |
b24e7179 JB |
4565 | if (!HAS_PCH_SPLIT(dev)) |
4566 | intel_enable_pipe(dev_priv, pipe); | |
79e53945 | 4567 | |
9d0498a2 | 4568 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 4569 | |
f00a3ddf | 4570 | if (IS_GEN5(dev)) { |
553bd149 ZW |
4571 | /* enable address swizzle for tiling buffer */ |
4572 | temp = I915_READ(DISP_ARB_CTL); | |
4573 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | |
4574 | } | |
4575 | ||
5eddb70b | 4576 | I915_WRITE(DSPCNTR(plane), dspcntr); |
b24e7179 JB |
4577 | POSTING_READ(DSPCNTR(plane)); |
4578 | if (!HAS_PCH_SPLIT(dev)) | |
4579 | intel_enable_plane(dev_priv, plane, pipe); | |
79e53945 | 4580 | |
5c3b82e2 | 4581 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
4582 | |
4583 | intel_update_watermarks(dev); | |
4584 | ||
79e53945 | 4585 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 4586 | |
1f803ee5 | 4587 | return ret; |
79e53945 JB |
4588 | } |
4589 | ||
4590 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4591 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4592 | { | |
4593 | struct drm_device *dev = crtc->dev; | |
4594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4595 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4596 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; | |
4597 | int i; | |
4598 | ||
4599 | /* The clocks have to be on to load the palette. */ | |
4600 | if (!crtc->enabled) | |
4601 | return; | |
4602 | ||
f2b115e6 | 4603 | /* use legacy palette for Ironlake */ |
bad720ff | 4604 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
4605 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : |
4606 | LGC_PALETTE_B; | |
4607 | ||
79e53945 JB |
4608 | for (i = 0; i < 256; i++) { |
4609 | I915_WRITE(palreg + 4 * i, | |
4610 | (intel_crtc->lut_r[i] << 16) | | |
4611 | (intel_crtc->lut_g[i] << 8) | | |
4612 | intel_crtc->lut_b[i]); | |
4613 | } | |
4614 | } | |
4615 | ||
560b85bb CW |
4616 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
4617 | { | |
4618 | struct drm_device *dev = crtc->dev; | |
4619 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4620 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4621 | bool visible = base != 0; | |
4622 | u32 cntl; | |
4623 | ||
4624 | if (intel_crtc->cursor_visible == visible) | |
4625 | return; | |
4626 | ||
4627 | cntl = I915_READ(CURACNTR); | |
4628 | if (visible) { | |
4629 | /* On these chipsets we can only modify the base whilst | |
4630 | * the cursor is disabled. | |
4631 | */ | |
4632 | I915_WRITE(CURABASE, base); | |
4633 | ||
4634 | cntl &= ~(CURSOR_FORMAT_MASK); | |
4635 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
4636 | cntl |= CURSOR_ENABLE | | |
4637 | CURSOR_GAMMA_ENABLE | | |
4638 | CURSOR_FORMAT_ARGB; | |
4639 | } else | |
4640 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
4641 | I915_WRITE(CURACNTR, cntl); | |
4642 | ||
4643 | intel_crtc->cursor_visible = visible; | |
4644 | } | |
4645 | ||
4646 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
4647 | { | |
4648 | struct drm_device *dev = crtc->dev; | |
4649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4650 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4651 | int pipe = intel_crtc->pipe; | |
4652 | bool visible = base != 0; | |
4653 | ||
4654 | if (intel_crtc->cursor_visible != visible) { | |
4655 | uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); | |
4656 | if (base) { | |
4657 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
4658 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
4659 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
4660 | } else { | |
4661 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
4662 | cntl |= CURSOR_MODE_DISABLE; | |
4663 | } | |
4664 | I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl); | |
4665 | ||
4666 | intel_crtc->cursor_visible = visible; | |
4667 | } | |
4668 | /* and commit changes on next vblank */ | |
4669 | I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base); | |
4670 | } | |
4671 | ||
cda4b7d3 | 4672 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
4673 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
4674 | bool on) | |
cda4b7d3 CW |
4675 | { |
4676 | struct drm_device *dev = crtc->dev; | |
4677 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4679 | int pipe = intel_crtc->pipe; | |
4680 | int x = intel_crtc->cursor_x; | |
4681 | int y = intel_crtc->cursor_y; | |
560b85bb | 4682 | u32 base, pos; |
cda4b7d3 CW |
4683 | bool visible; |
4684 | ||
4685 | pos = 0; | |
4686 | ||
6b383a7f | 4687 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
4688 | base = intel_crtc->cursor_addr; |
4689 | if (x > (int) crtc->fb->width) | |
4690 | base = 0; | |
4691 | ||
4692 | if (y > (int) crtc->fb->height) | |
4693 | base = 0; | |
4694 | } else | |
4695 | base = 0; | |
4696 | ||
4697 | if (x < 0) { | |
4698 | if (x + intel_crtc->cursor_width < 0) | |
4699 | base = 0; | |
4700 | ||
4701 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
4702 | x = -x; | |
4703 | } | |
4704 | pos |= x << CURSOR_X_SHIFT; | |
4705 | ||
4706 | if (y < 0) { | |
4707 | if (y + intel_crtc->cursor_height < 0) | |
4708 | base = 0; | |
4709 | ||
4710 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
4711 | y = -y; | |
4712 | } | |
4713 | pos |= y << CURSOR_Y_SHIFT; | |
4714 | ||
4715 | visible = base != 0; | |
560b85bb | 4716 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
4717 | return; |
4718 | ||
4719 | I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); | |
560b85bb CW |
4720 | if (IS_845G(dev) || IS_I865G(dev)) |
4721 | i845_update_cursor(crtc, base); | |
4722 | else | |
4723 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
4724 | |
4725 | if (visible) | |
4726 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
4727 | } | |
4728 | ||
79e53945 | 4729 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 4730 | struct drm_file *file, |
79e53945 JB |
4731 | uint32_t handle, |
4732 | uint32_t width, uint32_t height) | |
4733 | { | |
4734 | struct drm_device *dev = crtc->dev; | |
4735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4736 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 4737 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 4738 | uint32_t addr; |
3f8bc370 | 4739 | int ret; |
79e53945 | 4740 | |
28c97730 | 4741 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
4742 | |
4743 | /* if we want to turn off the cursor ignore width and height */ | |
4744 | if (!handle) { | |
28c97730 | 4745 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 4746 | addr = 0; |
05394f39 | 4747 | obj = NULL; |
5004417d | 4748 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 4749 | goto finish; |
79e53945 JB |
4750 | } |
4751 | ||
4752 | /* Currently we only support 64x64 cursors */ | |
4753 | if (width != 64 || height != 64) { | |
4754 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
4755 | return -EINVAL; | |
4756 | } | |
4757 | ||
05394f39 CW |
4758 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
4759 | if (!obj) | |
79e53945 JB |
4760 | return -ENOENT; |
4761 | ||
05394f39 | 4762 | if (obj->base.size < width * height * 4) { |
79e53945 | 4763 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
4764 | ret = -ENOMEM; |
4765 | goto fail; | |
79e53945 JB |
4766 | } |
4767 | ||
71acb5eb | 4768 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 4769 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 4770 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
4771 | if (obj->tiling_mode) { |
4772 | DRM_ERROR("cursor cannot be tiled\n"); | |
4773 | ret = -EINVAL; | |
4774 | goto fail_locked; | |
4775 | } | |
4776 | ||
05394f39 | 4777 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
71acb5eb DA |
4778 | if (ret) { |
4779 | DRM_ERROR("failed to pin cursor bo\n"); | |
7f9872e0 | 4780 | goto fail_locked; |
71acb5eb | 4781 | } |
e7b526bb | 4782 | |
05394f39 | 4783 | ret = i915_gem_object_set_to_gtt_domain(obj, 0); |
e7b526bb CW |
4784 | if (ret) { |
4785 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
4786 | goto fail_unpin; | |
4787 | } | |
4788 | ||
d9e86c0e CW |
4789 | ret = i915_gem_object_put_fence(obj); |
4790 | if (ret) { | |
4791 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
4792 | goto fail_unpin; | |
4793 | } | |
4794 | ||
05394f39 | 4795 | addr = obj->gtt_offset; |
71acb5eb | 4796 | } else { |
6eeefaf3 | 4797 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 4798 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
4799 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
4800 | align); | |
71acb5eb DA |
4801 | if (ret) { |
4802 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 4803 | goto fail_locked; |
71acb5eb | 4804 | } |
05394f39 | 4805 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
4806 | } |
4807 | ||
a6c45cf0 | 4808 | if (IS_GEN2(dev)) |
14b60391 JB |
4809 | I915_WRITE(CURSIZE, (height << 12) | width); |
4810 | ||
3f8bc370 | 4811 | finish: |
3f8bc370 | 4812 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 4813 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 4814 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
4815 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
4816 | } else | |
4817 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 4818 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 4819 | } |
80824003 | 4820 | |
7f9872e0 | 4821 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
4822 | |
4823 | intel_crtc->cursor_addr = addr; | |
05394f39 | 4824 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
4825 | intel_crtc->cursor_width = width; |
4826 | intel_crtc->cursor_height = height; | |
4827 | ||
6b383a7f | 4828 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 4829 | |
79e53945 | 4830 | return 0; |
e7b526bb | 4831 | fail_unpin: |
05394f39 | 4832 | i915_gem_object_unpin(obj); |
7f9872e0 | 4833 | fail_locked: |
34b8686e | 4834 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 4835 | fail: |
05394f39 | 4836 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 4837 | return ret; |
79e53945 JB |
4838 | } |
4839 | ||
4840 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
4841 | { | |
79e53945 | 4842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4843 | |
cda4b7d3 CW |
4844 | intel_crtc->cursor_x = x; |
4845 | intel_crtc->cursor_y = y; | |
652c393a | 4846 | |
6b383a7f | 4847 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
4848 | |
4849 | return 0; | |
4850 | } | |
4851 | ||
4852 | /** Sets the color ramps on behalf of RandR */ | |
4853 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
4854 | u16 blue, int regno) | |
4855 | { | |
4856 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4857 | ||
4858 | intel_crtc->lut_r[regno] = red >> 8; | |
4859 | intel_crtc->lut_g[regno] = green >> 8; | |
4860 | intel_crtc->lut_b[regno] = blue >> 8; | |
4861 | } | |
4862 | ||
b8c00ac5 DA |
4863 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
4864 | u16 *blue, int regno) | |
4865 | { | |
4866 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4867 | ||
4868 | *red = intel_crtc->lut_r[regno] << 8; | |
4869 | *green = intel_crtc->lut_g[regno] << 8; | |
4870 | *blue = intel_crtc->lut_b[regno] << 8; | |
4871 | } | |
4872 | ||
79e53945 | 4873 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 4874 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 4875 | { |
7203425a | 4876 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 4877 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4878 | |
7203425a | 4879 | for (i = start; i < end; i++) { |
79e53945 JB |
4880 | intel_crtc->lut_r[i] = red[i] >> 8; |
4881 | intel_crtc->lut_g[i] = green[i] >> 8; | |
4882 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
4883 | } | |
4884 | ||
4885 | intel_crtc_load_lut(crtc); | |
4886 | } | |
4887 | ||
4888 | /** | |
4889 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
4890 | * detection. | |
4891 | * | |
4892 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 4893 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 4894 | * |
c751ce4f | 4895 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
4896 | * configured for it. In the future, it could choose to temporarily disable |
4897 | * some outputs to free up a pipe for its use. | |
4898 | * | |
4899 | * \return crtc, or NULL if no pipes are available. | |
4900 | */ | |
4901 | ||
4902 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
4903 | static struct drm_display_mode load_detect_mode = { | |
4904 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
4905 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
4906 | }; | |
4907 | ||
21d40d37 | 4908 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
c1c43977 | 4909 | struct drm_connector *connector, |
79e53945 JB |
4910 | struct drm_display_mode *mode, |
4911 | int *dpms_mode) | |
4912 | { | |
4913 | struct intel_crtc *intel_crtc; | |
4914 | struct drm_crtc *possible_crtc; | |
4915 | struct drm_crtc *supported_crtc =NULL; | |
4ef69c7a | 4916 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4917 | struct drm_crtc *crtc = NULL; |
4918 | struct drm_device *dev = encoder->dev; | |
4919 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
4920 | struct drm_crtc_helper_funcs *crtc_funcs; | |
4921 | int i = -1; | |
4922 | ||
4923 | /* | |
4924 | * Algorithm gets a little messy: | |
4925 | * - if the connector already has an assigned crtc, use it (but make | |
4926 | * sure it's on first) | |
4927 | * - try to find the first unused crtc that can drive this connector, | |
4928 | * and use that if we find one | |
4929 | * - if there are no unused crtcs available, try to use the first | |
4930 | * one we found that supports the connector | |
4931 | */ | |
4932 | ||
4933 | /* See if we already have a CRTC for this connector */ | |
4934 | if (encoder->crtc) { | |
4935 | crtc = encoder->crtc; | |
4936 | /* Make sure the crtc and connector are running */ | |
4937 | intel_crtc = to_intel_crtc(crtc); | |
4938 | *dpms_mode = intel_crtc->dpms_mode; | |
4939 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4940 | crtc_funcs = crtc->helper_private; | |
4941 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4942 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
4943 | } | |
4944 | return crtc; | |
4945 | } | |
4946 | ||
4947 | /* Find an unused one (if possible) */ | |
4948 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
4949 | i++; | |
4950 | if (!(encoder->possible_crtcs & (1 << i))) | |
4951 | continue; | |
4952 | if (!possible_crtc->enabled) { | |
4953 | crtc = possible_crtc; | |
4954 | break; | |
4955 | } | |
4956 | if (!supported_crtc) | |
4957 | supported_crtc = possible_crtc; | |
4958 | } | |
4959 | ||
4960 | /* | |
4961 | * If we didn't find an unused CRTC, don't use any. | |
4962 | */ | |
4963 | if (!crtc) { | |
4964 | return NULL; | |
4965 | } | |
4966 | ||
4967 | encoder->crtc = crtc; | |
c1c43977 | 4968 | connector->encoder = encoder; |
21d40d37 | 4969 | intel_encoder->load_detect_temp = true; |
79e53945 JB |
4970 | |
4971 | intel_crtc = to_intel_crtc(crtc); | |
4972 | *dpms_mode = intel_crtc->dpms_mode; | |
4973 | ||
4974 | if (!crtc->enabled) { | |
4975 | if (!mode) | |
4976 | mode = &load_detect_mode; | |
3c4fdcfb | 4977 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
79e53945 JB |
4978 | } else { |
4979 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4980 | crtc_funcs = crtc->helper_private; | |
4981 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4982 | } | |
4983 | ||
4984 | /* Add this connector to the crtc */ | |
4985 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); | |
4986 | encoder_funcs->commit(encoder); | |
4987 | } | |
4988 | /* let the connector get through one full cycle before testing */ | |
9d0498a2 | 4989 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 JB |
4990 | |
4991 | return crtc; | |
4992 | } | |
4993 | ||
c1c43977 ZW |
4994 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
4995 | struct drm_connector *connector, int dpms_mode) | |
79e53945 | 4996 | { |
4ef69c7a | 4997 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4998 | struct drm_device *dev = encoder->dev; |
4999 | struct drm_crtc *crtc = encoder->crtc; | |
5000 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
5001 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
5002 | ||
21d40d37 | 5003 | if (intel_encoder->load_detect_temp) { |
79e53945 | 5004 | encoder->crtc = NULL; |
c1c43977 | 5005 | connector->encoder = NULL; |
21d40d37 | 5006 | intel_encoder->load_detect_temp = false; |
79e53945 JB |
5007 | crtc->enabled = drm_helper_crtc_in_use(crtc); |
5008 | drm_helper_disable_unused_functions(dev); | |
5009 | } | |
5010 | ||
c751ce4f | 5011 | /* Switch crtc and encoder back off if necessary */ |
79e53945 JB |
5012 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { |
5013 | if (encoder->crtc == crtc) | |
5014 | encoder_funcs->dpms(encoder, dpms_mode); | |
5015 | crtc_funcs->dpms(crtc, dpms_mode); | |
5016 | } | |
5017 | } | |
5018 | ||
5019 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
5020 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
5021 | { | |
5022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5023 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5024 | int pipe = intel_crtc->pipe; | |
5025 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); | |
5026 | u32 fp; | |
5027 | intel_clock_t clock; | |
5028 | ||
5029 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
5030 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); | |
5031 | else | |
5032 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); | |
5033 | ||
5034 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
5035 | if (IS_PINEVIEW(dev)) { |
5036 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
5037 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
5038 | } else { |
5039 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
5040 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
5041 | } | |
5042 | ||
a6c45cf0 | 5043 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
5044 | if (IS_PINEVIEW(dev)) |
5045 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
5046 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
5047 | else |
5048 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
5049 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
5050 | ||
5051 | switch (dpll & DPLL_MODE_MASK) { | |
5052 | case DPLLB_MODE_DAC_SERIAL: | |
5053 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
5054 | 5 : 10; | |
5055 | break; | |
5056 | case DPLLB_MODE_LVDS: | |
5057 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
5058 | 7 : 14; | |
5059 | break; | |
5060 | default: | |
28c97730 | 5061 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
5062 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
5063 | return 0; | |
5064 | } | |
5065 | ||
5066 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 5067 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
5068 | } else { |
5069 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
5070 | ||
5071 | if (is_lvds) { | |
5072 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
5073 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
5074 | clock.p2 = 14; | |
5075 | ||
5076 | if ((dpll & PLL_REF_INPUT_MASK) == | |
5077 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
5078 | /* XXX: might not be 66MHz */ | |
2177832f | 5079 | intel_clock(dev, 66000, &clock); |
79e53945 | 5080 | } else |
2177832f | 5081 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
5082 | } else { |
5083 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
5084 | clock.p1 = 2; | |
5085 | else { | |
5086 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
5087 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
5088 | } | |
5089 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
5090 | clock.p2 = 4; | |
5091 | else | |
5092 | clock.p2 = 2; | |
5093 | ||
2177832f | 5094 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
5095 | } |
5096 | } | |
5097 | ||
5098 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
5099 | * i830PllIsValid() because it relies on the xf86_config connector | |
5100 | * configuration being accurate, which it isn't necessarily. | |
5101 | */ | |
5102 | ||
5103 | return clock.dot; | |
5104 | } | |
5105 | ||
5106 | /** Returns the currently programmed mode of the given pipe. */ | |
5107 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
5108 | struct drm_crtc *crtc) | |
5109 | { | |
5110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5111 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5112 | int pipe = intel_crtc->pipe; | |
5113 | struct drm_display_mode *mode; | |
5114 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); | |
5115 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); | |
5116 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); | |
5117 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); | |
5118 | ||
5119 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
5120 | if (!mode) | |
5121 | return NULL; | |
5122 | ||
5123 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
5124 | mode->hdisplay = (htot & 0xffff) + 1; | |
5125 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
5126 | mode->hsync_start = (hsync & 0xffff) + 1; | |
5127 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
5128 | mode->vdisplay = (vtot & 0xffff) + 1; | |
5129 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
5130 | mode->vsync_start = (vsync & 0xffff) + 1; | |
5131 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
5132 | ||
5133 | drm_mode_set_name(mode); | |
5134 | drm_mode_set_crtcinfo(mode, 0); | |
5135 | ||
5136 | return mode; | |
5137 | } | |
5138 | ||
652c393a JB |
5139 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
5140 | ||
5141 | /* When this timer fires, we've been idle for awhile */ | |
5142 | static void intel_gpu_idle_timer(unsigned long arg) | |
5143 | { | |
5144 | struct drm_device *dev = (struct drm_device *)arg; | |
5145 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5146 | ||
ff7ea4c0 CW |
5147 | if (!list_empty(&dev_priv->mm.active_list)) { |
5148 | /* Still processing requests, so just re-arm the timer. */ | |
5149 | mod_timer(&dev_priv->idle_timer, jiffies + | |
5150 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
5151 | return; | |
5152 | } | |
652c393a | 5153 | |
ff7ea4c0 | 5154 | dev_priv->busy = false; |
01dfba93 | 5155 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
5156 | } |
5157 | ||
652c393a JB |
5158 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
5159 | ||
5160 | static void intel_crtc_idle_timer(unsigned long arg) | |
5161 | { | |
5162 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
5163 | struct drm_crtc *crtc = &intel_crtc->base; | |
5164 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 5165 | struct intel_framebuffer *intel_fb; |
652c393a | 5166 | |
ff7ea4c0 CW |
5167 | intel_fb = to_intel_framebuffer(crtc->fb); |
5168 | if (intel_fb && intel_fb->obj->active) { | |
5169 | /* The framebuffer is still being accessed by the GPU. */ | |
5170 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
5171 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
5172 | return; | |
5173 | } | |
652c393a | 5174 | |
ff7ea4c0 | 5175 | intel_crtc->busy = false; |
01dfba93 | 5176 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
5177 | } |
5178 | ||
3dec0095 | 5179 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
5180 | { |
5181 | struct drm_device *dev = crtc->dev; | |
5182 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5184 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
5185 | int dpll_reg = DPLL(pipe); |
5186 | int dpll; | |
652c393a | 5187 | |
bad720ff | 5188 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
5189 | return; |
5190 | ||
5191 | if (!dev_priv->lvds_downclock_avail) | |
5192 | return; | |
5193 | ||
dbdc6479 | 5194 | dpll = I915_READ(dpll_reg); |
652c393a | 5195 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 5196 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a JB |
5197 | |
5198 | /* Unlock panel regs */ | |
dbdc6479 JB |
5199 | I915_WRITE(PP_CONTROL, |
5200 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
652c393a JB |
5201 | |
5202 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
5203 | I915_WRITE(dpll_reg, dpll); | |
dbdc6479 | 5204 | POSTING_READ(dpll_reg); |
9d0498a2 | 5205 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 5206 | |
652c393a JB |
5207 | dpll = I915_READ(dpll_reg); |
5208 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 5209 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
5210 | |
5211 | /* ...and lock them again */ | |
5212 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
5213 | } | |
5214 | ||
5215 | /* Schedule downclock */ | |
3dec0095 DV |
5216 | mod_timer(&intel_crtc->idle_timer, jiffies + |
5217 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
5218 | } |
5219 | ||
5220 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
5221 | { | |
5222 | struct drm_device *dev = crtc->dev; | |
5223 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5225 | int pipe = intel_crtc->pipe; | |
5226 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
5227 | int dpll = I915_READ(dpll_reg); | |
5228 | ||
bad720ff | 5229 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
5230 | return; |
5231 | ||
5232 | if (!dev_priv->lvds_downclock_avail) | |
5233 | return; | |
5234 | ||
5235 | /* | |
5236 | * Since this is called by a timer, we should never get here in | |
5237 | * the manual case. | |
5238 | */ | |
5239 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 5240 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a JB |
5241 | |
5242 | /* Unlock panel regs */ | |
4a655f04 JB |
5243 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
5244 | PANEL_UNLOCK_REGS); | |
652c393a JB |
5245 | |
5246 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
5247 | I915_WRITE(dpll_reg, dpll); | |
5248 | dpll = I915_READ(dpll_reg); | |
9d0498a2 | 5249 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
5250 | dpll = I915_READ(dpll_reg); |
5251 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 5252 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
5253 | |
5254 | /* ...and lock them again */ | |
5255 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
5256 | } | |
5257 | ||
5258 | } | |
5259 | ||
5260 | /** | |
5261 | * intel_idle_update - adjust clocks for idleness | |
5262 | * @work: work struct | |
5263 | * | |
5264 | * Either the GPU or display (or both) went idle. Check the busy status | |
5265 | * here and adjust the CRTC and GPU clocks as necessary. | |
5266 | */ | |
5267 | static void intel_idle_update(struct work_struct *work) | |
5268 | { | |
5269 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
5270 | idle_work); | |
5271 | struct drm_device *dev = dev_priv->dev; | |
5272 | struct drm_crtc *crtc; | |
5273 | struct intel_crtc *intel_crtc; | |
45ac22c8 | 5274 | int enabled = 0; |
652c393a JB |
5275 | |
5276 | if (!i915_powersave) | |
5277 | return; | |
5278 | ||
5279 | mutex_lock(&dev->struct_mutex); | |
5280 | ||
7648fa99 JB |
5281 | i915_update_gfx_val(dev_priv); |
5282 | ||
652c393a JB |
5283 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
5284 | /* Skip inactive CRTCs */ | |
5285 | if (!crtc->fb) | |
5286 | continue; | |
5287 | ||
45ac22c8 | 5288 | enabled++; |
652c393a JB |
5289 | intel_crtc = to_intel_crtc(crtc); |
5290 | if (!intel_crtc->busy) | |
5291 | intel_decrease_pllclock(crtc); | |
5292 | } | |
5293 | ||
45ac22c8 LP |
5294 | if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) { |
5295 | DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); | |
5296 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
5297 | } | |
5298 | ||
652c393a JB |
5299 | mutex_unlock(&dev->struct_mutex); |
5300 | } | |
5301 | ||
5302 | /** | |
5303 | * intel_mark_busy - mark the GPU and possibly the display busy | |
5304 | * @dev: drm device | |
5305 | * @obj: object we're operating on | |
5306 | * | |
5307 | * Callers can use this function to indicate that the GPU is busy processing | |
5308 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
5309 | * buffer), we'll also mark the display as busy, so we know to increase its | |
5310 | * clock frequency. | |
5311 | */ | |
05394f39 | 5312 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
5313 | { |
5314 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5315 | struct drm_crtc *crtc = NULL; | |
5316 | struct intel_framebuffer *intel_fb; | |
5317 | struct intel_crtc *intel_crtc; | |
5318 | ||
5e17ee74 ZW |
5319 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
5320 | return; | |
5321 | ||
060e645a LP |
5322 | if (!dev_priv->busy) { |
5323 | if (IS_I945G(dev) || IS_I945GM(dev)) { | |
5324 | u32 fw_blc_self; | |
ee980b80 | 5325 | |
060e645a LP |
5326 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); |
5327 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
5328 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
5329 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
5330 | } | |
28cf798f | 5331 | dev_priv->busy = true; |
060e645a | 5332 | } else |
28cf798f CW |
5333 | mod_timer(&dev_priv->idle_timer, jiffies + |
5334 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
5335 | |
5336 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
5337 | if (!crtc->fb) | |
5338 | continue; | |
5339 | ||
5340 | intel_crtc = to_intel_crtc(crtc); | |
5341 | intel_fb = to_intel_framebuffer(crtc->fb); | |
5342 | if (intel_fb->obj == obj) { | |
5343 | if (!intel_crtc->busy) { | |
060e645a LP |
5344 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
5345 | u32 fw_blc_self; | |
5346 | ||
5347 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); | |
5348 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
5349 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
5350 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
5351 | } | |
652c393a | 5352 | /* Non-busy -> busy, upclock */ |
3dec0095 | 5353 | intel_increase_pllclock(crtc); |
652c393a JB |
5354 | intel_crtc->busy = true; |
5355 | } else { | |
5356 | /* Busy -> busy, put off timer */ | |
5357 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
5358 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
5359 | } | |
5360 | } | |
5361 | } | |
5362 | } | |
5363 | ||
79e53945 JB |
5364 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
5365 | { | |
5366 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
5367 | struct drm_device *dev = crtc->dev; |
5368 | struct intel_unpin_work *work; | |
5369 | unsigned long flags; | |
5370 | ||
5371 | spin_lock_irqsave(&dev->event_lock, flags); | |
5372 | work = intel_crtc->unpin_work; | |
5373 | intel_crtc->unpin_work = NULL; | |
5374 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5375 | ||
5376 | if (work) { | |
5377 | cancel_work_sync(&work->work); | |
5378 | kfree(work); | |
5379 | } | |
79e53945 JB |
5380 | |
5381 | drm_crtc_cleanup(crtc); | |
67e77c5a | 5382 | |
79e53945 JB |
5383 | kfree(intel_crtc); |
5384 | } | |
5385 | ||
6b95a207 KH |
5386 | static void intel_unpin_work_fn(struct work_struct *__work) |
5387 | { | |
5388 | struct intel_unpin_work *work = | |
5389 | container_of(__work, struct intel_unpin_work, work); | |
5390 | ||
5391 | mutex_lock(&work->dev->struct_mutex); | |
b1b87f6b | 5392 | i915_gem_object_unpin(work->old_fb_obj); |
05394f39 CW |
5393 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
5394 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 5395 | |
6b95a207 KH |
5396 | mutex_unlock(&work->dev->struct_mutex); |
5397 | kfree(work); | |
5398 | } | |
5399 | ||
1afe3e9d | 5400 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 5401 | struct drm_crtc *crtc) |
6b95a207 KH |
5402 | { |
5403 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
5404 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5405 | struct intel_unpin_work *work; | |
05394f39 | 5406 | struct drm_i915_gem_object *obj; |
6b95a207 | 5407 | struct drm_pending_vblank_event *e; |
49b14a5c | 5408 | struct timeval tnow, tvbl; |
6b95a207 KH |
5409 | unsigned long flags; |
5410 | ||
5411 | /* Ignore early vblank irqs */ | |
5412 | if (intel_crtc == NULL) | |
5413 | return; | |
5414 | ||
49b14a5c MK |
5415 | do_gettimeofday(&tnow); |
5416 | ||
6b95a207 KH |
5417 | spin_lock_irqsave(&dev->event_lock, flags); |
5418 | work = intel_crtc->unpin_work; | |
5419 | if (work == NULL || !work->pending) { | |
5420 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5421 | return; | |
5422 | } | |
5423 | ||
5424 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
5425 | |
5426 | if (work->event) { | |
5427 | e = work->event; | |
49b14a5c | 5428 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
5429 | |
5430 | /* Called before vblank count and timestamps have | |
5431 | * been updated for the vblank interval of flip | |
5432 | * completion? Need to increment vblank count and | |
5433 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
5434 | * to account for this. We assume this happened if we |
5435 | * get called over 0.9 frame durations after the last | |
5436 | * timestamped vblank. | |
5437 | * | |
5438 | * This calculation can not be used with vrefresh rates | |
5439 | * below 5Hz (10Hz to be on the safe side) without | |
5440 | * promoting to 64 integers. | |
0af7e4df | 5441 | */ |
49b14a5c MK |
5442 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
5443 | 9 * crtc->framedur_ns) { | |
0af7e4df | 5444 | e->event.sequence++; |
49b14a5c MK |
5445 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
5446 | crtc->framedur_ns); | |
0af7e4df MK |
5447 | } |
5448 | ||
49b14a5c MK |
5449 | e->event.tv_sec = tvbl.tv_sec; |
5450 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 5451 | |
6b95a207 KH |
5452 | list_add_tail(&e->base.link, |
5453 | &e->base.file_priv->event_list); | |
5454 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
5455 | } | |
5456 | ||
0af7e4df MK |
5457 | drm_vblank_put(dev, intel_crtc->pipe); |
5458 | ||
6b95a207 KH |
5459 | spin_unlock_irqrestore(&dev->event_lock, flags); |
5460 | ||
05394f39 | 5461 | obj = work->old_fb_obj; |
d9e86c0e | 5462 | |
e59f2bac | 5463 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
5464 | &obj->pending_flip.counter); |
5465 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 5466 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 5467 | |
6b95a207 | 5468 | schedule_work(&work->work); |
e5510fac JB |
5469 | |
5470 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
5471 | } |
5472 | ||
1afe3e9d JB |
5473 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
5474 | { | |
5475 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5476 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
5477 | ||
49b14a5c | 5478 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
5479 | } |
5480 | ||
5481 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
5482 | { | |
5483 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5484 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
5485 | ||
49b14a5c | 5486 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
5487 | } |
5488 | ||
6b95a207 KH |
5489 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
5490 | { | |
5491 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5492 | struct intel_crtc *intel_crtc = | |
5493 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
5494 | unsigned long flags; | |
5495 | ||
5496 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 5497 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
5498 | if ((++intel_crtc->unpin_work->pending) > 1) |
5499 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
5500 | } else { |
5501 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
5502 | } | |
6b95a207 KH |
5503 | spin_unlock_irqrestore(&dev->event_lock, flags); |
5504 | } | |
5505 | ||
5506 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
5507 | struct drm_framebuffer *fb, | |
5508 | struct drm_pending_vblank_event *event) | |
5509 | { | |
5510 | struct drm_device *dev = crtc->dev; | |
5511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5512 | struct intel_framebuffer *intel_fb; | |
05394f39 | 5513 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
5514 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5515 | struct intel_unpin_work *work; | |
be9a3dbf | 5516 | unsigned long flags, offset; |
52e68630 | 5517 | int pipe = intel_crtc->pipe; |
20f0cd55 | 5518 | u32 pf, pipesrc; |
52e68630 | 5519 | int ret; |
6b95a207 KH |
5520 | |
5521 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
5522 | if (work == NULL) | |
5523 | return -ENOMEM; | |
5524 | ||
6b95a207 KH |
5525 | work->event = event; |
5526 | work->dev = crtc->dev; | |
5527 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 5528 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
5529 | INIT_WORK(&work->work, intel_unpin_work_fn); |
5530 | ||
5531 | /* We borrow the event spin lock for protecting unpin_work */ | |
5532 | spin_lock_irqsave(&dev->event_lock, flags); | |
5533 | if (intel_crtc->unpin_work) { | |
5534 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5535 | kfree(work); | |
468f0b44 CW |
5536 | |
5537 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
5538 | return -EBUSY; |
5539 | } | |
5540 | intel_crtc->unpin_work = work; | |
5541 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5542 | ||
5543 | intel_fb = to_intel_framebuffer(fb); | |
5544 | obj = intel_fb->obj; | |
5545 | ||
468f0b44 | 5546 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 | 5547 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); |
96b099fd CW |
5548 | if (ret) |
5549 | goto cleanup_work; | |
6b95a207 | 5550 | |
75dfca80 | 5551 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
5552 | drm_gem_object_reference(&work->old_fb_obj->base); |
5553 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
5554 | |
5555 | crtc->fb = fb; | |
96b099fd CW |
5556 | |
5557 | ret = drm_vblank_get(dev, intel_crtc->pipe); | |
5558 | if (ret) | |
5559 | goto cleanup_objs; | |
5560 | ||
c7f9f9a8 CW |
5561 | if (IS_GEN3(dev) || IS_GEN2(dev)) { |
5562 | u32 flip_mask; | |
48b956c5 | 5563 | |
c7f9f9a8 CW |
5564 | /* Can't queue multiple flips, so wait for the previous |
5565 | * one to finish before executing the next. | |
5566 | */ | |
e1f99ce6 CW |
5567 | ret = BEGIN_LP_RING(2); |
5568 | if (ret) | |
5569 | goto cleanup_objs; | |
5570 | ||
c7f9f9a8 CW |
5571 | if (intel_crtc->plane) |
5572 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
5573 | else | |
5574 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
5575 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
5576 | OUT_RING(MI_NOOP); | |
6146b3d6 DV |
5577 | ADVANCE_LP_RING(); |
5578 | } | |
83f7fd05 | 5579 | |
e1f99ce6 | 5580 | work->pending_flip_obj = obj; |
e1f99ce6 | 5581 | |
4e5359cd SF |
5582 | work->enable_stall_check = true; |
5583 | ||
be9a3dbf | 5584 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
52e68630 | 5585 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; |
be9a3dbf | 5586 | |
e1f99ce6 CW |
5587 | ret = BEGIN_LP_RING(4); |
5588 | if (ret) | |
5589 | goto cleanup_objs; | |
5590 | ||
5591 | /* Block clients from rendering to the new back buffer until | |
5592 | * the flip occurs and the object is no longer visible. | |
5593 | */ | |
05394f39 | 5594 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 CW |
5595 | |
5596 | switch (INTEL_INFO(dev)->gen) { | |
52e68630 | 5597 | case 2: |
1afe3e9d JB |
5598 | OUT_RING(MI_DISPLAY_FLIP | |
5599 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5600 | OUT_RING(fb->pitch); | |
05394f39 | 5601 | OUT_RING(obj->gtt_offset + offset); |
52e68630 CW |
5602 | OUT_RING(MI_NOOP); |
5603 | break; | |
5604 | ||
5605 | case 3: | |
1afe3e9d JB |
5606 | OUT_RING(MI_DISPLAY_FLIP_I915 | |
5607 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5608 | OUT_RING(fb->pitch); | |
05394f39 | 5609 | OUT_RING(obj->gtt_offset + offset); |
22fd0fab | 5610 | OUT_RING(MI_NOOP); |
52e68630 CW |
5611 | break; |
5612 | ||
5613 | case 4: | |
5614 | case 5: | |
5615 | /* i965+ uses the linear or tiled offsets from the | |
5616 | * Display Registers (which do not change across a page-flip) | |
5617 | * so we need only reprogram the base address. | |
5618 | */ | |
69d0b96c DV |
5619 | OUT_RING(MI_DISPLAY_FLIP | |
5620 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5621 | OUT_RING(fb->pitch); | |
05394f39 | 5622 | OUT_RING(obj->gtt_offset | obj->tiling_mode); |
52e68630 CW |
5623 | |
5624 | /* XXX Enabling the panel-fitter across page-flip is so far | |
5625 | * untested on non-native modes, so ignore it for now. | |
5626 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5627 | */ | |
5628 | pf = 0; | |
5629 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5630 | OUT_RING(pf | pipesrc); | |
5631 | break; | |
5632 | ||
5633 | case 6: | |
5634 | OUT_RING(MI_DISPLAY_FLIP | | |
5635 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
05394f39 CW |
5636 | OUT_RING(fb->pitch | obj->tiling_mode); |
5637 | OUT_RING(obj->gtt_offset); | |
52e68630 CW |
5638 | |
5639 | pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5640 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5641 | OUT_RING(pf | pipesrc); | |
5642 | break; | |
22fd0fab | 5643 | } |
6b95a207 KH |
5644 | ADVANCE_LP_RING(); |
5645 | ||
5646 | mutex_unlock(&dev->struct_mutex); | |
5647 | ||
e5510fac JB |
5648 | trace_i915_flip_request(intel_crtc->plane, obj); |
5649 | ||
6b95a207 | 5650 | return 0; |
96b099fd CW |
5651 | |
5652 | cleanup_objs: | |
05394f39 CW |
5653 | drm_gem_object_unreference(&work->old_fb_obj->base); |
5654 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
5655 | cleanup_work: |
5656 | mutex_unlock(&dev->struct_mutex); | |
5657 | ||
5658 | spin_lock_irqsave(&dev->event_lock, flags); | |
5659 | intel_crtc->unpin_work = NULL; | |
5660 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5661 | ||
5662 | kfree(work); | |
5663 | ||
5664 | return ret; | |
6b95a207 KH |
5665 | } |
5666 | ||
7e7d76c3 | 5667 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
79e53945 JB |
5668 | .dpms = intel_crtc_dpms, |
5669 | .mode_fixup = intel_crtc_mode_fixup, | |
5670 | .mode_set = intel_crtc_mode_set, | |
5671 | .mode_set_base = intel_pipe_set_base, | |
81255565 | 5672 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
068143d3 | 5673 | .load_lut = intel_crtc_load_lut, |
cdd59983 | 5674 | .disable = intel_crtc_disable, |
79e53945 JB |
5675 | }; |
5676 | ||
5677 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
5678 | .cursor_set = intel_crtc_cursor_set, | |
5679 | .cursor_move = intel_crtc_cursor_move, | |
5680 | .gamma_set = intel_crtc_gamma_set, | |
5681 | .set_config = drm_crtc_helper_set_config, | |
5682 | .destroy = intel_crtc_destroy, | |
6b95a207 | 5683 | .page_flip = intel_crtc_page_flip, |
79e53945 JB |
5684 | }; |
5685 | ||
47f1c6c9 CW |
5686 | static void intel_sanitize_modesetting(struct drm_device *dev, |
5687 | int pipe, int plane) | |
5688 | { | |
5689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5690 | u32 reg, val; | |
5691 | ||
5692 | if (HAS_PCH_SPLIT(dev)) | |
5693 | return; | |
5694 | ||
5695 | /* Who knows what state these registers were left in by the BIOS or | |
5696 | * grub? | |
5697 | * | |
5698 | * If we leave the registers in a conflicting state (e.g. with the | |
5699 | * display plane reading from the other pipe than the one we intend | |
5700 | * to use) then when we attempt to teardown the active mode, we will | |
5701 | * not disable the pipes and planes in the correct order -- leaving | |
5702 | * a plane reading from a disabled pipe and possibly leading to | |
5703 | * undefined behaviour. | |
5704 | */ | |
5705 | ||
5706 | reg = DSPCNTR(plane); | |
5707 | val = I915_READ(reg); | |
5708 | ||
5709 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
5710 | return; | |
5711 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
5712 | return; | |
5713 | ||
5714 | /* This display plane is active and attached to the other CPU pipe. */ | |
5715 | pipe = !pipe; | |
5716 | ||
5717 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
b24e7179 JB |
5718 | intel_disable_plane(dev_priv, plane, pipe); |
5719 | intel_disable_pipe(dev_priv, pipe); | |
47f1c6c9 | 5720 | } |
79e53945 | 5721 | |
b358d0a6 | 5722 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 5723 | { |
22fd0fab | 5724 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
5725 | struct intel_crtc *intel_crtc; |
5726 | int i; | |
5727 | ||
5728 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
5729 | if (intel_crtc == NULL) | |
5730 | return; | |
5731 | ||
5732 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
5733 | ||
5734 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
5735 | for (i = 0; i < 256; i++) { |
5736 | intel_crtc->lut_r[i] = i; | |
5737 | intel_crtc->lut_g[i] = i; | |
5738 | intel_crtc->lut_b[i] = i; | |
5739 | } | |
5740 | ||
80824003 JB |
5741 | /* Swap pipes & planes for FBC on pre-965 */ |
5742 | intel_crtc->pipe = pipe; | |
5743 | intel_crtc->plane = pipe; | |
e2e767ab | 5744 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 5745 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 5746 | intel_crtc->plane = !pipe; |
80824003 JB |
5747 | } |
5748 | ||
22fd0fab JB |
5749 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
5750 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
5751 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
5752 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
5753 | ||
79e53945 | 5754 | intel_crtc->cursor_addr = 0; |
032d2a0d | 5755 | intel_crtc->dpms_mode = -1; |
e65d9305 | 5756 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
7e7d76c3 JB |
5757 | |
5758 | if (HAS_PCH_SPLIT(dev)) { | |
5759 | intel_helper_funcs.prepare = ironlake_crtc_prepare; | |
5760 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
5761 | } else { | |
5762 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
5763 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
5764 | } | |
5765 | ||
79e53945 JB |
5766 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
5767 | ||
652c393a JB |
5768 | intel_crtc->busy = false; |
5769 | ||
5770 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
5771 | (unsigned long)intel_crtc); | |
47f1c6c9 CW |
5772 | |
5773 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
79e53945 JB |
5774 | } |
5775 | ||
08d7b3d1 | 5776 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 5777 | struct drm_file *file) |
08d7b3d1 CW |
5778 | { |
5779 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5780 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
5781 | struct drm_mode_object *drmmode_obj; |
5782 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
5783 | |
5784 | if (!dev_priv) { | |
5785 | DRM_ERROR("called with no initialization\n"); | |
5786 | return -EINVAL; | |
5787 | } | |
5788 | ||
c05422d5 DV |
5789 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
5790 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 5791 | |
c05422d5 | 5792 | if (!drmmode_obj) { |
08d7b3d1 CW |
5793 | DRM_ERROR("no such CRTC id\n"); |
5794 | return -EINVAL; | |
5795 | } | |
5796 | ||
c05422d5 DV |
5797 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
5798 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 5799 | |
c05422d5 | 5800 | return 0; |
08d7b3d1 CW |
5801 | } |
5802 | ||
c5e4df33 | 5803 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 5804 | { |
4ef69c7a | 5805 | struct intel_encoder *encoder; |
79e53945 | 5806 | int index_mask = 0; |
79e53945 JB |
5807 | int entry = 0; |
5808 | ||
4ef69c7a CW |
5809 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5810 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
5811 | index_mask |= (1 << entry); |
5812 | entry++; | |
5813 | } | |
4ef69c7a | 5814 | |
79e53945 JB |
5815 | return index_mask; |
5816 | } | |
5817 | ||
4d302442 CW |
5818 | static bool has_edp_a(struct drm_device *dev) |
5819 | { | |
5820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5821 | ||
5822 | if (!IS_MOBILE(dev)) | |
5823 | return false; | |
5824 | ||
5825 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
5826 | return false; | |
5827 | ||
5828 | if (IS_GEN5(dev) && | |
5829 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
5830 | return false; | |
5831 | ||
5832 | return true; | |
5833 | } | |
5834 | ||
79e53945 JB |
5835 | static void intel_setup_outputs(struct drm_device *dev) |
5836 | { | |
725e30ad | 5837 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 5838 | struct intel_encoder *encoder; |
cb0953d7 | 5839 | bool dpd_is_edp = false; |
c5d1b51d | 5840 | bool has_lvds = false; |
79e53945 | 5841 | |
541998a1 | 5842 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
c5d1b51d CW |
5843 | has_lvds = intel_lvds_init(dev); |
5844 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { | |
5845 | /* disable the panel fitter on everything but LVDS */ | |
5846 | I915_WRITE(PFIT_CONTROL, 0); | |
5847 | } | |
79e53945 | 5848 | |
bad720ff | 5849 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 5850 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 5851 | |
4d302442 | 5852 | if (has_edp_a(dev)) |
32f9d658 ZW |
5853 | intel_dp_init(dev, DP_A); |
5854 | ||
cb0953d7 AJ |
5855 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5856 | intel_dp_init(dev, PCH_DP_D); | |
5857 | } | |
5858 | ||
5859 | intel_crt_init(dev); | |
5860 | ||
5861 | if (HAS_PCH_SPLIT(dev)) { | |
5862 | int found; | |
5863 | ||
30ad48b7 | 5864 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca ZY |
5865 | /* PCH SDVOB multiplex with HDMIB */ |
5866 | found = intel_sdvo_init(dev, PCH_SDVOB); | |
30ad48b7 ZW |
5867 | if (!found) |
5868 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
5869 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
5870 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
5871 | } |
5872 | ||
5873 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
5874 | intel_hdmi_init(dev, HDMIC); | |
5875 | ||
5876 | if (I915_READ(HDMID) & PORT_DETECTED) | |
5877 | intel_hdmi_init(dev, HDMID); | |
5878 | ||
5eb08b69 ZW |
5879 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
5880 | intel_dp_init(dev, PCH_DP_C); | |
5881 | ||
cb0953d7 | 5882 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
5883 | intel_dp_init(dev, PCH_DP_D); |
5884 | ||
103a196f | 5885 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 5886 | bool found = false; |
7d57382e | 5887 | |
725e30ad | 5888 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 5889 | DRM_DEBUG_KMS("probing SDVOB\n"); |
725e30ad | 5890 | found = intel_sdvo_init(dev, SDVOB); |
b01f2c3a JB |
5891 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
5892 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 5893 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 5894 | } |
27185ae1 | 5895 | |
b01f2c3a JB |
5896 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
5897 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 5898 | intel_dp_init(dev, DP_B); |
b01f2c3a | 5899 | } |
725e30ad | 5900 | } |
13520b05 KH |
5901 | |
5902 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 5903 | |
b01f2c3a JB |
5904 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
5905 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
725e30ad | 5906 | found = intel_sdvo_init(dev, SDVOC); |
b01f2c3a | 5907 | } |
27185ae1 ML |
5908 | |
5909 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
5910 | ||
b01f2c3a JB |
5911 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
5912 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 5913 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
5914 | } |
5915 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
5916 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 5917 | intel_dp_init(dev, DP_C); |
b01f2c3a | 5918 | } |
725e30ad | 5919 | } |
27185ae1 | 5920 | |
b01f2c3a JB |
5921 | if (SUPPORTS_INTEGRATED_DP(dev) && |
5922 | (I915_READ(DP_D) & DP_DETECTED)) { | |
5923 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 5924 | intel_dp_init(dev, DP_D); |
b01f2c3a | 5925 | } |
bad720ff | 5926 | } else if (IS_GEN2(dev)) |
79e53945 JB |
5927 | intel_dvo_init(dev); |
5928 | ||
103a196f | 5929 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
5930 | intel_tv_init(dev); |
5931 | ||
4ef69c7a CW |
5932 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5933 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
5934 | encoder->base.possible_clones = | |
5935 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 | 5936 | } |
47356eb6 CW |
5937 | |
5938 | intel_panel_setup_backlight(dev); | |
79e53945 JB |
5939 | } |
5940 | ||
5941 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
5942 | { | |
5943 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
5944 | |
5945 | drm_framebuffer_cleanup(fb); | |
05394f39 | 5946 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
5947 | |
5948 | kfree(intel_fb); | |
5949 | } | |
5950 | ||
5951 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 5952 | struct drm_file *file, |
79e53945 JB |
5953 | unsigned int *handle) |
5954 | { | |
5955 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 5956 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 5957 | |
05394f39 | 5958 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
5959 | } |
5960 | ||
5961 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
5962 | .destroy = intel_user_framebuffer_destroy, | |
5963 | .create_handle = intel_user_framebuffer_create_handle, | |
5964 | }; | |
5965 | ||
38651674 DA |
5966 | int intel_framebuffer_init(struct drm_device *dev, |
5967 | struct intel_framebuffer *intel_fb, | |
5968 | struct drm_mode_fb_cmd *mode_cmd, | |
05394f39 | 5969 | struct drm_i915_gem_object *obj) |
79e53945 | 5970 | { |
79e53945 JB |
5971 | int ret; |
5972 | ||
05394f39 | 5973 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
5974 | return -EINVAL; |
5975 | ||
5976 | if (mode_cmd->pitch & 63) | |
5977 | return -EINVAL; | |
5978 | ||
5979 | switch (mode_cmd->bpp) { | |
5980 | case 8: | |
5981 | case 16: | |
5982 | case 24: | |
5983 | case 32: | |
5984 | break; | |
5985 | default: | |
5986 | return -EINVAL; | |
5987 | } | |
5988 | ||
79e53945 JB |
5989 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
5990 | if (ret) { | |
5991 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
5992 | return ret; | |
5993 | } | |
5994 | ||
5995 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 5996 | intel_fb->obj = obj; |
79e53945 JB |
5997 | return 0; |
5998 | } | |
5999 | ||
79e53945 JB |
6000 | static struct drm_framebuffer * |
6001 | intel_user_framebuffer_create(struct drm_device *dev, | |
6002 | struct drm_file *filp, | |
6003 | struct drm_mode_fb_cmd *mode_cmd) | |
6004 | { | |
05394f39 | 6005 | struct drm_i915_gem_object *obj; |
38651674 | 6006 | struct intel_framebuffer *intel_fb; |
79e53945 JB |
6007 | int ret; |
6008 | ||
05394f39 | 6009 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle)); |
79e53945 | 6010 | if (!obj) |
cce13ff7 | 6011 | return ERR_PTR(-ENOENT); |
79e53945 | 6012 | |
38651674 DA |
6013 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
6014 | if (!intel_fb) | |
cce13ff7 | 6015 | return ERR_PTR(-ENOMEM); |
38651674 | 6016 | |
05394f39 | 6017 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
79e53945 | 6018 | if (ret) { |
05394f39 | 6019 | drm_gem_object_unreference_unlocked(&obj->base); |
38651674 | 6020 | kfree(intel_fb); |
cce13ff7 | 6021 | return ERR_PTR(ret); |
79e53945 JB |
6022 | } |
6023 | ||
38651674 | 6024 | return &intel_fb->base; |
79e53945 JB |
6025 | } |
6026 | ||
79e53945 | 6027 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 6028 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 6029 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
6030 | }; |
6031 | ||
05394f39 | 6032 | static struct drm_i915_gem_object * |
aa40d6bb | 6033 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 6034 | { |
05394f39 | 6035 | struct drm_i915_gem_object *ctx; |
9ea8d059 CW |
6036 | int ret; |
6037 | ||
aa40d6bb ZN |
6038 | ctx = i915_gem_alloc_object(dev, 4096); |
6039 | if (!ctx) { | |
9ea8d059 CW |
6040 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
6041 | return NULL; | |
6042 | } | |
6043 | ||
6044 | mutex_lock(&dev->struct_mutex); | |
75e9e915 | 6045 | ret = i915_gem_object_pin(ctx, 4096, true); |
9ea8d059 CW |
6046 | if (ret) { |
6047 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
6048 | goto err_unref; | |
6049 | } | |
6050 | ||
aa40d6bb | 6051 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
6052 | if (ret) { |
6053 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
6054 | goto err_unpin; | |
6055 | } | |
6056 | mutex_unlock(&dev->struct_mutex); | |
6057 | ||
aa40d6bb | 6058 | return ctx; |
9ea8d059 CW |
6059 | |
6060 | err_unpin: | |
aa40d6bb | 6061 | i915_gem_object_unpin(ctx); |
9ea8d059 | 6062 | err_unref: |
05394f39 | 6063 | drm_gem_object_unreference(&ctx->base); |
9ea8d059 CW |
6064 | mutex_unlock(&dev->struct_mutex); |
6065 | return NULL; | |
6066 | } | |
6067 | ||
7648fa99 JB |
6068 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
6069 | { | |
6070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6071 | u16 rgvswctl; | |
6072 | ||
6073 | rgvswctl = I915_READ16(MEMSWCTL); | |
6074 | if (rgvswctl & MEMCTL_CMD_STS) { | |
6075 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
6076 | return false; /* still busy with another command */ | |
6077 | } | |
6078 | ||
6079 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
6080 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
6081 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
6082 | POSTING_READ16(MEMSWCTL); | |
6083 | ||
6084 | rgvswctl |= MEMCTL_CMD_STS; | |
6085 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
6086 | ||
6087 | return true; | |
6088 | } | |
6089 | ||
f97108d1 JB |
6090 | void ironlake_enable_drps(struct drm_device *dev) |
6091 | { | |
6092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 6093 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 6094 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 6095 | |
ea056c14 JB |
6096 | /* Enable temp reporting */ |
6097 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
6098 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
6099 | ||
f97108d1 JB |
6100 | /* 100ms RC evaluation intervals */ |
6101 | I915_WRITE(RCUPEI, 100000); | |
6102 | I915_WRITE(RCDNEI, 100000); | |
6103 | ||
6104 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
6105 | I915_WRITE(RCBMAXAVG, 90000); | |
6106 | I915_WRITE(RCBMINAVG, 80000); | |
6107 | ||
6108 | I915_WRITE(MEMIHYST, 1); | |
6109 | ||
6110 | /* Set up min, max, and cur for interrupt handling */ | |
6111 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
6112 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
6113 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
6114 | MEMMODE_FSTART_SHIFT; | |
7648fa99 | 6115 | |
f97108d1 JB |
6116 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
6117 | PXVFREQ_PX_SHIFT; | |
6118 | ||
80dbf4b7 | 6119 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
7648fa99 JB |
6120 | dev_priv->fstart = fstart; |
6121 | ||
80dbf4b7 | 6122 | dev_priv->max_delay = fstart; |
f97108d1 JB |
6123 | dev_priv->min_delay = fmin; |
6124 | dev_priv->cur_delay = fstart; | |
6125 | ||
80dbf4b7 JB |
6126 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
6127 | fmax, fmin, fstart); | |
7648fa99 | 6128 | |
f97108d1 JB |
6129 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
6130 | ||
6131 | /* | |
6132 | * Interrupts will be enabled in ironlake_irq_postinstall | |
6133 | */ | |
6134 | ||
6135 | I915_WRITE(VIDSTART, vstart); | |
6136 | POSTING_READ(VIDSTART); | |
6137 | ||
6138 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
6139 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
6140 | ||
481b6af3 | 6141 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 6142 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
6143 | msleep(1); |
6144 | ||
7648fa99 | 6145 | ironlake_set_drps(dev, fstart); |
f97108d1 | 6146 | |
7648fa99 JB |
6147 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
6148 | I915_READ(0x112e0); | |
6149 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
6150 | dev_priv->last_count2 = I915_READ(0x112f4); | |
6151 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
6152 | } |
6153 | ||
6154 | void ironlake_disable_drps(struct drm_device *dev) | |
6155 | { | |
6156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 6157 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
6158 | |
6159 | /* Ack interrupts, disable EFC interrupt */ | |
6160 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
6161 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
6162 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
6163 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
6164 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
6165 | ||
6166 | /* Go back to the starting frequency */ | |
7648fa99 | 6167 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
6168 | msleep(1); |
6169 | rgvswctl |= MEMCTL_CMD_STS; | |
6170 | I915_WRITE(MEMSWCTL, rgvswctl); | |
6171 | msleep(1); | |
6172 | ||
6173 | } | |
6174 | ||
3b8d8d91 JB |
6175 | void gen6_set_rps(struct drm_device *dev, u8 val) |
6176 | { | |
6177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6178 | u32 swreq; | |
6179 | ||
6180 | swreq = (val & 0x3ff) << 25; | |
6181 | I915_WRITE(GEN6_RPNSWREQ, swreq); | |
6182 | } | |
6183 | ||
6184 | void gen6_disable_rps(struct drm_device *dev) | |
6185 | { | |
6186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6187 | ||
6188 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); | |
6189 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
6190 | I915_WRITE(GEN6_PMIER, 0); | |
6191 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); | |
6192 | } | |
6193 | ||
7648fa99 JB |
6194 | static unsigned long intel_pxfreq(u32 vidfreq) |
6195 | { | |
6196 | unsigned long freq; | |
6197 | int div = (vidfreq & 0x3f0000) >> 16; | |
6198 | int post = (vidfreq & 0x3000) >> 12; | |
6199 | int pre = (vidfreq & 0x7); | |
6200 | ||
6201 | if (!pre) | |
6202 | return 0; | |
6203 | ||
6204 | freq = ((div * 133333) / ((1<<post) * pre)); | |
6205 | ||
6206 | return freq; | |
6207 | } | |
6208 | ||
6209 | void intel_init_emon(struct drm_device *dev) | |
6210 | { | |
6211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6212 | u32 lcfuse; | |
6213 | u8 pxw[16]; | |
6214 | int i; | |
6215 | ||
6216 | /* Disable to program */ | |
6217 | I915_WRITE(ECR, 0); | |
6218 | POSTING_READ(ECR); | |
6219 | ||
6220 | /* Program energy weights for various events */ | |
6221 | I915_WRITE(SDEW, 0x15040d00); | |
6222 | I915_WRITE(CSIEW0, 0x007f0000); | |
6223 | I915_WRITE(CSIEW1, 0x1e220004); | |
6224 | I915_WRITE(CSIEW2, 0x04000004); | |
6225 | ||
6226 | for (i = 0; i < 5; i++) | |
6227 | I915_WRITE(PEW + (i * 4), 0); | |
6228 | for (i = 0; i < 3; i++) | |
6229 | I915_WRITE(DEW + (i * 4), 0); | |
6230 | ||
6231 | /* Program P-state weights to account for frequency power adjustment */ | |
6232 | for (i = 0; i < 16; i++) { | |
6233 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
6234 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
6235 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
6236 | PXVFREQ_PX_SHIFT; | |
6237 | unsigned long val; | |
6238 | ||
6239 | val = vid * vid; | |
6240 | val *= (freq / 1000); | |
6241 | val *= 255; | |
6242 | val /= (127*127*900); | |
6243 | if (val > 0xff) | |
6244 | DRM_ERROR("bad pxval: %ld\n", val); | |
6245 | pxw[i] = val; | |
6246 | } | |
6247 | /* Render standby states get 0 weight */ | |
6248 | pxw[14] = 0; | |
6249 | pxw[15] = 0; | |
6250 | ||
6251 | for (i = 0; i < 4; i++) { | |
6252 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
6253 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
6254 | I915_WRITE(PXW + (i * 4), val); | |
6255 | } | |
6256 | ||
6257 | /* Adjust magic regs to magic values (more experimental results) */ | |
6258 | I915_WRITE(OGW0, 0); | |
6259 | I915_WRITE(OGW1, 0); | |
6260 | I915_WRITE(EG0, 0x00007f00); | |
6261 | I915_WRITE(EG1, 0x0000000e); | |
6262 | I915_WRITE(EG2, 0x000e0000); | |
6263 | I915_WRITE(EG3, 0x68000300); | |
6264 | I915_WRITE(EG4, 0x42000000); | |
6265 | I915_WRITE(EG5, 0x00140031); | |
6266 | I915_WRITE(EG6, 0); | |
6267 | I915_WRITE(EG7, 0); | |
6268 | ||
6269 | for (i = 0; i < 8; i++) | |
6270 | I915_WRITE(PXWL + (i * 4), 0); | |
6271 | ||
6272 | /* Enable PMON + select events */ | |
6273 | I915_WRITE(ECR, 0x80000019); | |
6274 | ||
6275 | lcfuse = I915_READ(LCFUSE02); | |
6276 | ||
6277 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
6278 | } | |
6279 | ||
3b8d8d91 | 6280 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
8fd26859 | 6281 | { |
a6044e23 JB |
6282 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
6283 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
6284 | u32 pcu_mbox; | |
6285 | int cur_freq, min_freq, max_freq; | |
8fd26859 CW |
6286 | int i; |
6287 | ||
6288 | /* Here begins a magic sequence of register writes to enable | |
6289 | * auto-downclocking. | |
6290 | * | |
6291 | * Perhaps there might be some value in exposing these to | |
6292 | * userspace... | |
6293 | */ | |
6294 | I915_WRITE(GEN6_RC_STATE, 0); | |
6295 | __gen6_force_wake_get(dev_priv); | |
6296 | ||
3b8d8d91 | 6297 | /* disable the counters and set deterministic thresholds */ |
8fd26859 CW |
6298 | I915_WRITE(GEN6_RC_CONTROL, 0); |
6299 | ||
6300 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
6301 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
6302 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
6303 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
6304 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
6305 | ||
6306 | for (i = 0; i < I915_NUM_RINGS; i++) | |
6307 | I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); | |
6308 | ||
6309 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
6310 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
6311 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
6312 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); | |
6313 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ | |
6314 | ||
6315 | I915_WRITE(GEN6_RC_CONTROL, | |
6316 | GEN6_RC_CTL_RC6p_ENABLE | | |
6317 | GEN6_RC_CTL_RC6_ENABLE | | |
9c3d2f7f | 6318 | GEN6_RC_CTL_EI_MODE(1) | |
8fd26859 CW |
6319 | GEN6_RC_CTL_HW_ENABLE); |
6320 | ||
3b8d8d91 | 6321 | I915_WRITE(GEN6_RPNSWREQ, |
8fd26859 CW |
6322 | GEN6_FREQUENCY(10) | |
6323 | GEN6_OFFSET(0) | | |
6324 | GEN6_AGGRESSIVE_TURBO); | |
6325 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
6326 | GEN6_FREQUENCY(12)); | |
6327 | ||
6328 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
6329 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
6330 | 18 << 24 | | |
6331 | 6 << 16); | |
6332 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000); | |
6333 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000); | |
6334 | I915_WRITE(GEN6_RP_UP_EI, 100000); | |
6335 | I915_WRITE(GEN6_RP_DOWN_EI, 300000); | |
6336 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6337 | I915_WRITE(GEN6_RP_CONTROL, | |
6338 | GEN6_RP_MEDIA_TURBO | | |
6339 | GEN6_RP_USE_NORMAL_FREQ | | |
6340 | GEN6_RP_MEDIA_IS_GFX | | |
6341 | GEN6_RP_ENABLE | | |
6342 | GEN6_RP_UP_BUSY_MAX | | |
6343 | GEN6_RP_DOWN_BUSY_MIN); | |
6344 | ||
6345 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6346 | 500)) | |
6347 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
6348 | ||
6349 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6350 | I915_WRITE(GEN6_PCODE_MAILBOX, | |
6351 | GEN6_PCODE_READY | | |
6352 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
6353 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6354 | 500)) | |
6355 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
6356 | ||
a6044e23 JB |
6357 | min_freq = (rp_state_cap & 0xff0000) >> 16; |
6358 | max_freq = rp_state_cap & 0xff; | |
6359 | cur_freq = (gt_perf_status & 0xff00) >> 8; | |
6360 | ||
6361 | /* Check for overclock support */ | |
6362 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6363 | 500)) | |
6364 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
6365 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); | |
6366 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); | |
6367 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6368 | 500)) | |
6369 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
6370 | if (pcu_mbox & (1<<31)) { /* OC supported */ | |
6371 | max_freq = pcu_mbox & 0xff; | |
6372 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100); | |
6373 | } | |
6374 | ||
6375 | /* In units of 100MHz */ | |
6376 | dev_priv->max_delay = max_freq; | |
6377 | dev_priv->min_delay = min_freq; | |
6378 | dev_priv->cur_delay = cur_freq; | |
6379 | ||
8fd26859 CW |
6380 | /* requires MSI enabled */ |
6381 | I915_WRITE(GEN6_PMIER, | |
6382 | GEN6_PM_MBOX_EVENT | | |
6383 | GEN6_PM_THERMAL_EVENT | | |
6384 | GEN6_PM_RP_DOWN_TIMEOUT | | |
6385 | GEN6_PM_RP_UP_THRESHOLD | | |
6386 | GEN6_PM_RP_DOWN_THRESHOLD | | |
6387 | GEN6_PM_RP_UP_EI_EXPIRED | | |
6388 | GEN6_PM_RP_DOWN_EI_EXPIRED); | |
3b8d8d91 JB |
6389 | I915_WRITE(GEN6_PMIMR, 0); |
6390 | /* enable all PM interrupts */ | |
6391 | I915_WRITE(GEN6_PMINTRMSK, 0); | |
8fd26859 CW |
6392 | |
6393 | __gen6_force_wake_put(dev_priv); | |
6394 | } | |
6395 | ||
0cdab21f | 6396 | void intel_enable_clock_gating(struct drm_device *dev) |
652c393a JB |
6397 | { |
6398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6399 | ||
6400 | /* | |
6401 | * Disable clock gating reported to work incorrectly according to the | |
6402 | * specs, but enable as much else as we can. | |
6403 | */ | |
bad720ff | 6404 | if (HAS_PCH_SPLIT(dev)) { |
8956c8bb EA |
6405 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
6406 | ||
f00a3ddf | 6407 | if (IS_GEN5(dev)) { |
8956c8bb EA |
6408 | /* Required for FBC */ |
6409 | dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; | |
6410 | /* Required for CxSR */ | |
6411 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
6412 | ||
6413 | I915_WRITE(PCH_3DCGDIS0, | |
6414 | MARIUNIT_CLOCK_GATE_DISABLE | | |
6415 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
06f37751 EA |
6416 | I915_WRITE(PCH_3DCGDIS1, |
6417 | VFMUNIT_CLOCK_GATE_DISABLE); | |
8956c8bb EA |
6418 | } |
6419 | ||
6420 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
7f8a8569 | 6421 | |
382b0936 JB |
6422 | /* |
6423 | * On Ibex Peak and Cougar Point, we need to disable clock | |
6424 | * gating for the panel power sequencer or it will fail to | |
6425 | * start up when no ports are active. | |
6426 | */ | |
6427 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
6428 | ||
7f8a8569 ZW |
6429 | /* |
6430 | * According to the spec the following bits should be set in | |
6431 | * order to enable memory self-refresh | |
6432 | * The bit 22/21 of 0x42004 | |
6433 | * The bit 5 of 0x42020 | |
6434 | * The bit 15 of 0x45000 | |
6435 | */ | |
f00a3ddf | 6436 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
6437 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6438 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6439 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
6440 | I915_WRITE(ILK_DSPCLK_GATE, | |
6441 | (I915_READ(ILK_DSPCLK_GATE) | | |
6442 | ILK_DPARB_CLK_GATE)); | |
6443 | I915_WRITE(DISP_ARB_CTL, | |
6444 | (I915_READ(DISP_ARB_CTL) | | |
6445 | DISP_FBC_WM_DIS)); | |
1398261a YL |
6446 | I915_WRITE(WM3_LP_ILK, 0); |
6447 | I915_WRITE(WM2_LP_ILK, 0); | |
6448 | I915_WRITE(WM1_LP_ILK, 0); | |
7f8a8569 | 6449 | } |
b52eb4dc ZY |
6450 | /* |
6451 | * Based on the document from hardware guys the following bits | |
6452 | * should be set unconditionally in order to enable FBC. | |
6453 | * The bit 22 of 0x42000 | |
6454 | * The bit 22 of 0x42004 | |
6455 | * The bit 7,8,9 of 0x42020. | |
6456 | */ | |
6457 | if (IS_IRONLAKE_M(dev)) { | |
6458 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
6459 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
6460 | ILK_FBCQ_DIS); | |
6461 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6462 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6463 | ILK_DPARB_GATE); | |
6464 | I915_WRITE(ILK_DSPCLK_GATE, | |
6465 | I915_READ(ILK_DSPCLK_GATE) | | |
6466 | ILK_DPFC_DIS1 | | |
6467 | ILK_DPFC_DIS2 | | |
6468 | ILK_CLK_FBC); | |
6469 | } | |
de6e2eaf | 6470 | |
67e92af0 EA |
6471 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6472 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6473 | ILK_ELPIN_409_SELECT); | |
6474 | ||
de6e2eaf EA |
6475 | if (IS_GEN5(dev)) { |
6476 | I915_WRITE(_3D_CHICKEN2, | |
6477 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
6478 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
6479 | } | |
8fd26859 | 6480 | |
1398261a YL |
6481 | if (IS_GEN6(dev)) { |
6482 | I915_WRITE(WM3_LP_ILK, 0); | |
6483 | I915_WRITE(WM2_LP_ILK, 0); | |
6484 | I915_WRITE(WM1_LP_ILK, 0); | |
6485 | ||
6486 | /* | |
6487 | * According to the spec the following bits should be | |
6488 | * set in order to enable memory self-refresh and fbc: | |
6489 | * The bit21 and bit22 of 0x42000 | |
6490 | * The bit21 and bit22 of 0x42004 | |
6491 | * The bit5 and bit7 of 0x42020 | |
6492 | * The bit14 of 0x70180 | |
6493 | * The bit14 of 0x71180 | |
6494 | */ | |
6495 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
6496 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
6497 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
6498 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6499 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6500 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
6501 | I915_WRITE(ILK_DSPCLK_GATE, | |
6502 | I915_READ(ILK_DSPCLK_GATE) | | |
6503 | ILK_DPARB_CLK_GATE | | |
6504 | ILK_DPFD_CLK_GATE); | |
6505 | ||
6506 | I915_WRITE(DSPACNTR, | |
6507 | I915_READ(DSPACNTR) | | |
6508 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
6509 | I915_WRITE(DSPBCNTR, | |
6510 | I915_READ(DSPBCNTR) | | |
6511 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
6512 | } | |
c03342fa | 6513 | } else if (IS_G4X(dev)) { |
652c393a JB |
6514 | uint32_t dspclk_gate; |
6515 | I915_WRITE(RENCLK_GATE_D1, 0); | |
6516 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
6517 | GS_UNIT_CLOCK_GATE_DISABLE | | |
6518 | CL_UNIT_CLOCK_GATE_DISABLE); | |
6519 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6520 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
6521 | OVRUNIT_CLOCK_GATE_DISABLE | | |
6522 | OVCUNIT_CLOCK_GATE_DISABLE; | |
6523 | if (IS_GM45(dev)) | |
6524 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
6525 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
a6c45cf0 | 6526 | } else if (IS_CRESTLINE(dev)) { |
652c393a JB |
6527 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
6528 | I915_WRITE(RENCLK_GATE_D2, 0); | |
6529 | I915_WRITE(DSPCLK_GATE_D, 0); | |
6530 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6531 | I915_WRITE16(DEUC, 0); | |
a6c45cf0 | 6532 | } else if (IS_BROADWATER(dev)) { |
652c393a JB |
6533 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
6534 | I965_RCC_CLOCK_GATE_DISABLE | | |
6535 | I965_RCPB_CLOCK_GATE_DISABLE | | |
6536 | I965_ISC_CLOCK_GATE_DISABLE | | |
6537 | I965_FBC_CLOCK_GATE_DISABLE); | |
6538 | I915_WRITE(RENCLK_GATE_D2, 0); | |
a6c45cf0 | 6539 | } else if (IS_GEN3(dev)) { |
652c393a JB |
6540 | u32 dstate = I915_READ(D_STATE); |
6541 | ||
6542 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
6543 | DSTATE_DOT_CLOCK_GATING; | |
6544 | I915_WRITE(D_STATE, dstate); | |
f0f8a9ce | 6545 | } else if (IS_I85X(dev) || IS_I865G(dev)) { |
652c393a JB |
6546 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
6547 | } else if (IS_I830(dev)) { | |
6548 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
6549 | } | |
6550 | } | |
6551 | ||
0cdab21f CW |
6552 | void intel_disable_clock_gating(struct drm_device *dev) |
6553 | { | |
6554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6555 | ||
6556 | if (dev_priv->renderctx) { | |
6557 | struct drm_i915_gem_object *obj = dev_priv->renderctx; | |
6558 | ||
6559 | I915_WRITE(CCID, 0); | |
6560 | POSTING_READ(CCID); | |
6561 | ||
6562 | i915_gem_object_unpin(obj); | |
6563 | drm_gem_object_unreference(&obj->base); | |
6564 | dev_priv->renderctx = NULL; | |
6565 | } | |
6566 | ||
6567 | if (dev_priv->pwrctx) { | |
6568 | struct drm_i915_gem_object *obj = dev_priv->pwrctx; | |
6569 | ||
6570 | I915_WRITE(PWRCTXA, 0); | |
6571 | POSTING_READ(PWRCTXA); | |
6572 | ||
6573 | i915_gem_object_unpin(obj); | |
6574 | drm_gem_object_unreference(&obj->base); | |
6575 | dev_priv->pwrctx = NULL; | |
6576 | } | |
6577 | } | |
6578 | ||
d5bb081b JB |
6579 | static void ironlake_disable_rc6(struct drm_device *dev) |
6580 | { | |
6581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6582 | ||
6583 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
6584 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
6585 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
6586 | 10); | |
6587 | POSTING_READ(CCID); | |
6588 | I915_WRITE(PWRCTXA, 0); | |
6589 | POSTING_READ(PWRCTXA); | |
6590 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
6591 | POSTING_READ(RSTDBYCTL); | |
6592 | i915_gem_object_unpin(dev_priv->renderctx); | |
6593 | drm_gem_object_unreference(&dev_priv->renderctx->base); | |
6594 | dev_priv->renderctx = NULL; | |
6595 | i915_gem_object_unpin(dev_priv->pwrctx); | |
6596 | drm_gem_object_unreference(&dev_priv->pwrctx->base); | |
6597 | dev_priv->pwrctx = NULL; | |
6598 | } | |
6599 | ||
6600 | void ironlake_enable_rc6(struct drm_device *dev) | |
6601 | { | |
6602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6603 | int ret; | |
6604 | ||
6605 | /* | |
6606 | * GPU can automatically power down the render unit if given a page | |
6607 | * to save state. | |
6608 | */ | |
6609 | ret = BEGIN_LP_RING(6); | |
6610 | if (ret) { | |
6611 | ironlake_disable_rc6(dev); | |
6612 | return; | |
6613 | } | |
6614 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); | |
6615 | OUT_RING(MI_SET_CONTEXT); | |
6616 | OUT_RING(dev_priv->renderctx->gtt_offset | | |
6617 | MI_MM_SPACE_GTT | | |
6618 | MI_SAVE_EXT_STATE_EN | | |
6619 | MI_RESTORE_EXT_STATE_EN | | |
6620 | MI_RESTORE_INHIBIT); | |
6621 | OUT_RING(MI_SUSPEND_FLUSH); | |
6622 | OUT_RING(MI_NOOP); | |
6623 | OUT_RING(MI_FLUSH); | |
6624 | ADVANCE_LP_RING(); | |
6625 | ||
6626 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); | |
6627 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
6628 | } | |
6629 | ||
e70236a8 JB |
6630 | /* Set up chip specific display functions */ |
6631 | static void intel_init_display(struct drm_device *dev) | |
6632 | { | |
6633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6634 | ||
6635 | /* We always want a DPMS function */ | |
bad720ff | 6636 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 6637 | dev_priv->display.dpms = ironlake_crtc_dpms; |
e70236a8 JB |
6638 | else |
6639 | dev_priv->display.dpms = i9xx_crtc_dpms; | |
6640 | ||
ee5382ae | 6641 | if (I915_HAS_FBC(dev)) { |
9c04f015 | 6642 | if (HAS_PCH_SPLIT(dev)) { |
b52eb4dc ZY |
6643 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
6644 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
6645 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
6646 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
6647 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
6648 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
6649 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 6650 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
6651 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
6652 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
6653 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
6654 | } | |
74dff282 | 6655 | /* 855GM needs testing */ |
e70236a8 JB |
6656 | } |
6657 | ||
6658 | /* Returns the core display clock speed */ | |
f2b115e6 | 6659 | if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev))) |
e70236a8 JB |
6660 | dev_priv->display.get_display_clock_speed = |
6661 | i945_get_display_clock_speed; | |
6662 | else if (IS_I915G(dev)) | |
6663 | dev_priv->display.get_display_clock_speed = | |
6664 | i915_get_display_clock_speed; | |
f2b115e6 | 6665 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
6666 | dev_priv->display.get_display_clock_speed = |
6667 | i9xx_misc_get_display_clock_speed; | |
6668 | else if (IS_I915GM(dev)) | |
6669 | dev_priv->display.get_display_clock_speed = | |
6670 | i915gm_get_display_clock_speed; | |
6671 | else if (IS_I865G(dev)) | |
6672 | dev_priv->display.get_display_clock_speed = | |
6673 | i865_get_display_clock_speed; | |
f0f8a9ce | 6674 | else if (IS_I85X(dev)) |
e70236a8 JB |
6675 | dev_priv->display.get_display_clock_speed = |
6676 | i855_get_display_clock_speed; | |
6677 | else /* 852, 830 */ | |
6678 | dev_priv->display.get_display_clock_speed = | |
6679 | i830_get_display_clock_speed; | |
6680 | ||
6681 | /* For FIFO watermark updates */ | |
7f8a8569 | 6682 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 6683 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
6684 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
6685 | dev_priv->display.update_wm = ironlake_update_wm; | |
6686 | else { | |
6687 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
6688 | "Disable CxSR\n"); | |
6689 | dev_priv->display.update_wm = NULL; | |
1398261a YL |
6690 | } |
6691 | } else if (IS_GEN6(dev)) { | |
6692 | if (SNB_READ_WM0_LATENCY()) { | |
6693 | dev_priv->display.update_wm = sandybridge_update_wm; | |
6694 | } else { | |
6695 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
6696 | "Disable CxSR\n"); | |
6697 | dev_priv->display.update_wm = NULL; | |
7f8a8569 ZW |
6698 | } |
6699 | } else | |
6700 | dev_priv->display.update_wm = NULL; | |
6701 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 6702 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 6703 | dev_priv->is_ddr3, |
d4294342 ZY |
6704 | dev_priv->fsb_freq, |
6705 | dev_priv->mem_freq)) { | |
6706 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 6707 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 6708 | "disabling CxSR\n", |
95534263 | 6709 | (dev_priv->is_ddr3 == 1) ? "3": "2", |
d4294342 ZY |
6710 | dev_priv->fsb_freq, dev_priv->mem_freq); |
6711 | /* Disable CxSR and never update its watermark again */ | |
6712 | pineview_disable_cxsr(dev); | |
6713 | dev_priv->display.update_wm = NULL; | |
6714 | } else | |
6715 | dev_priv->display.update_wm = pineview_update_wm; | |
6716 | } else if (IS_G4X(dev)) | |
e70236a8 | 6717 | dev_priv->display.update_wm = g4x_update_wm; |
a6c45cf0 | 6718 | else if (IS_GEN4(dev)) |
e70236a8 | 6719 | dev_priv->display.update_wm = i965_update_wm; |
a6c45cf0 | 6720 | else if (IS_GEN3(dev)) { |
e70236a8 JB |
6721 | dev_priv->display.update_wm = i9xx_update_wm; |
6722 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
8f4695ed AJ |
6723 | } else if (IS_I85X(dev)) { |
6724 | dev_priv->display.update_wm = i9xx_update_wm; | |
6725 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
e70236a8 | 6726 | } else { |
8f4695ed AJ |
6727 | dev_priv->display.update_wm = i830_update_wm; |
6728 | if (IS_845G(dev)) | |
e70236a8 JB |
6729 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
6730 | else | |
6731 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 JB |
6732 | } |
6733 | } | |
6734 | ||
b690e96c JB |
6735 | /* |
6736 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
6737 | * resume, or other times. This quirk makes sure that's the case for | |
6738 | * affected systems. | |
6739 | */ | |
6740 | static void quirk_pipea_force (struct drm_device *dev) | |
6741 | { | |
6742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6743 | ||
6744 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
6745 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
6746 | } | |
6747 | ||
6748 | struct intel_quirk { | |
6749 | int device; | |
6750 | int subsystem_vendor; | |
6751 | int subsystem_device; | |
6752 | void (*hook)(struct drm_device *dev); | |
6753 | }; | |
6754 | ||
6755 | struct intel_quirk intel_quirks[] = { | |
6756 | /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ | |
6757 | { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, | |
6758 | /* HP Mini needs pipe A force quirk (LP: #322104) */ | |
6759 | { 0x27ae,0x103c, 0x361a, quirk_pipea_force }, | |
6760 | ||
6761 | /* Thinkpad R31 needs pipe A force quirk */ | |
6762 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
6763 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
6764 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
6765 | ||
6766 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
6767 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
6768 | /* ThinkPad X40 needs pipe A force quirk */ | |
6769 | ||
6770 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
6771 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
6772 | ||
6773 | /* 855 & before need to leave pipe A & dpll A up */ | |
6774 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
6775 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
6776 | }; | |
6777 | ||
6778 | static void intel_init_quirks(struct drm_device *dev) | |
6779 | { | |
6780 | struct pci_dev *d = dev->pdev; | |
6781 | int i; | |
6782 | ||
6783 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
6784 | struct intel_quirk *q = &intel_quirks[i]; | |
6785 | ||
6786 | if (d->device == q->device && | |
6787 | (d->subsystem_vendor == q->subsystem_vendor || | |
6788 | q->subsystem_vendor == PCI_ANY_ID) && | |
6789 | (d->subsystem_device == q->subsystem_device || | |
6790 | q->subsystem_device == PCI_ANY_ID)) | |
6791 | q->hook(dev); | |
6792 | } | |
6793 | } | |
6794 | ||
9cce37f4 JB |
6795 | /* Disable the VGA plane that we never use */ |
6796 | static void i915_disable_vga(struct drm_device *dev) | |
6797 | { | |
6798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6799 | u8 sr1; | |
6800 | u32 vga_reg; | |
6801 | ||
6802 | if (HAS_PCH_SPLIT(dev)) | |
6803 | vga_reg = CPU_VGACNTRL; | |
6804 | else | |
6805 | vga_reg = VGACNTRL; | |
6806 | ||
6807 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6808 | outb(1, VGA_SR_INDEX); | |
6809 | sr1 = inb(VGA_SR_DATA); | |
6810 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
6811 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6812 | udelay(300); | |
6813 | ||
6814 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
6815 | POSTING_READ(vga_reg); | |
6816 | } | |
6817 | ||
79e53945 JB |
6818 | void intel_modeset_init(struct drm_device *dev) |
6819 | { | |
652c393a | 6820 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6821 | int i; |
6822 | ||
6823 | drm_mode_config_init(dev); | |
6824 | ||
6825 | dev->mode_config.min_width = 0; | |
6826 | dev->mode_config.min_height = 0; | |
6827 | ||
6828 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
6829 | ||
b690e96c JB |
6830 | intel_init_quirks(dev); |
6831 | ||
e70236a8 JB |
6832 | intel_init_display(dev); |
6833 | ||
a6c45cf0 CW |
6834 | if (IS_GEN2(dev)) { |
6835 | dev->mode_config.max_width = 2048; | |
6836 | dev->mode_config.max_height = 2048; | |
6837 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
6838 | dev->mode_config.max_width = 4096; |
6839 | dev->mode_config.max_height = 4096; | |
79e53945 | 6840 | } else { |
a6c45cf0 CW |
6841 | dev->mode_config.max_width = 8192; |
6842 | dev->mode_config.max_height = 8192; | |
79e53945 | 6843 | } |
35c3047a | 6844 | dev->mode_config.fb_base = dev->agp->base; |
79e53945 | 6845 | |
a6c45cf0 | 6846 | if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
a3524f1b | 6847 | dev_priv->num_pipe = 2; |
79e53945 | 6848 | else |
a3524f1b | 6849 | dev_priv->num_pipe = 1; |
28c97730 | 6850 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 6851 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 6852 | |
a3524f1b | 6853 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 JB |
6854 | intel_crtc_init(dev, i); |
6855 | } | |
6856 | ||
6857 | intel_setup_outputs(dev); | |
652c393a | 6858 | |
0cdab21f | 6859 | intel_enable_clock_gating(dev); |
652c393a | 6860 | |
9cce37f4 JB |
6861 | /* Just disable it once at startup */ |
6862 | i915_disable_vga(dev); | |
6863 | ||
7648fa99 | 6864 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 6865 | ironlake_enable_drps(dev); |
7648fa99 JB |
6866 | intel_init_emon(dev); |
6867 | } | |
f97108d1 | 6868 | |
3b8d8d91 JB |
6869 | if (IS_GEN6(dev)) |
6870 | gen6_enable_rps(dev_priv); | |
6871 | ||
d5bb081b JB |
6872 | if (IS_IRONLAKE_M(dev)) { |
6873 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
6874 | if (!dev_priv->renderctx) | |
6875 | goto skip_rc6; | |
6876 | dev_priv->pwrctx = intel_alloc_context_page(dev); | |
6877 | if (!dev_priv->pwrctx) { | |
6878 | i915_gem_object_unpin(dev_priv->renderctx); | |
6879 | drm_gem_object_unreference(&dev_priv->renderctx->base); | |
6880 | dev_priv->renderctx = NULL; | |
6881 | goto skip_rc6; | |
6882 | } | |
6883 | ironlake_enable_rc6(dev); | |
6884 | } | |
6885 | ||
6886 | skip_rc6: | |
652c393a JB |
6887 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
6888 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
6889 | (unsigned long)dev); | |
02e792fb DV |
6890 | |
6891 | intel_setup_overlay(dev); | |
79e53945 JB |
6892 | } |
6893 | ||
6894 | void intel_modeset_cleanup(struct drm_device *dev) | |
6895 | { | |
652c393a JB |
6896 | struct drm_i915_private *dev_priv = dev->dev_private; |
6897 | struct drm_crtc *crtc; | |
6898 | struct intel_crtc *intel_crtc; | |
6899 | ||
f87ea761 | 6900 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
6901 | mutex_lock(&dev->struct_mutex); |
6902 | ||
723bfd70 JB |
6903 | intel_unregister_dsm_handler(); |
6904 | ||
6905 | ||
652c393a JB |
6906 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6907 | /* Skip inactive CRTCs */ | |
6908 | if (!crtc->fb) | |
6909 | continue; | |
6910 | ||
6911 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 6912 | intel_increase_pllclock(crtc); |
652c393a JB |
6913 | } |
6914 | ||
e70236a8 JB |
6915 | if (dev_priv->display.disable_fbc) |
6916 | dev_priv->display.disable_fbc(dev); | |
6917 | ||
f97108d1 JB |
6918 | if (IS_IRONLAKE_M(dev)) |
6919 | ironlake_disable_drps(dev); | |
3b8d8d91 JB |
6920 | if (IS_GEN6(dev)) |
6921 | gen6_disable_rps(dev); | |
f97108d1 | 6922 | |
d5bb081b JB |
6923 | if (IS_IRONLAKE_M(dev)) |
6924 | ironlake_disable_rc6(dev); | |
0cdab21f | 6925 | |
69341a5e KH |
6926 | mutex_unlock(&dev->struct_mutex); |
6927 | ||
6c0d9350 DV |
6928 | /* Disable the irq before mode object teardown, for the irq might |
6929 | * enqueue unpin/hotplug work. */ | |
6930 | drm_irq_uninstall(dev); | |
6931 | cancel_work_sync(&dev_priv->hotplug_work); | |
6932 | ||
3dec0095 DV |
6933 | /* Shut off idle work before the crtcs get freed. */ |
6934 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
6935 | intel_crtc = to_intel_crtc(crtc); | |
6936 | del_timer_sync(&intel_crtc->idle_timer); | |
6937 | } | |
6938 | del_timer_sync(&dev_priv->idle_timer); | |
6939 | cancel_work_sync(&dev_priv->idle_work); | |
6940 | ||
79e53945 JB |
6941 | drm_mode_config_cleanup(dev); |
6942 | } | |
6943 | ||
f1c79df3 ZW |
6944 | /* |
6945 | * Return which encoder is currently attached for connector. | |
6946 | */ | |
df0e9248 | 6947 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 6948 | { |
df0e9248 CW |
6949 | return &intel_attached_encoder(connector)->base; |
6950 | } | |
f1c79df3 | 6951 | |
df0e9248 CW |
6952 | void intel_connector_attach_encoder(struct intel_connector *connector, |
6953 | struct intel_encoder *encoder) | |
6954 | { | |
6955 | connector->encoder = encoder; | |
6956 | drm_mode_connector_attach_encoder(&connector->base, | |
6957 | &encoder->base); | |
79e53945 | 6958 | } |
28d52043 DA |
6959 | |
6960 | /* | |
6961 | * set vga decode state - true == enable VGA decode | |
6962 | */ | |
6963 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
6964 | { | |
6965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6966 | u16 gmch_ctrl; | |
6967 | ||
6968 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
6969 | if (state) | |
6970 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
6971 | else | |
6972 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
6973 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
6974 | return 0; | |
6975 | } | |
c4a1d9e4 CW |
6976 | |
6977 | #ifdef CONFIG_DEBUG_FS | |
6978 | #include <linux/seq_file.h> | |
6979 | ||
6980 | struct intel_display_error_state { | |
6981 | struct intel_cursor_error_state { | |
6982 | u32 control; | |
6983 | u32 position; | |
6984 | u32 base; | |
6985 | u32 size; | |
6986 | } cursor[2]; | |
6987 | ||
6988 | struct intel_pipe_error_state { | |
6989 | u32 conf; | |
6990 | u32 source; | |
6991 | ||
6992 | u32 htotal; | |
6993 | u32 hblank; | |
6994 | u32 hsync; | |
6995 | u32 vtotal; | |
6996 | u32 vblank; | |
6997 | u32 vsync; | |
6998 | } pipe[2]; | |
6999 | ||
7000 | struct intel_plane_error_state { | |
7001 | u32 control; | |
7002 | u32 stride; | |
7003 | u32 size; | |
7004 | u32 pos; | |
7005 | u32 addr; | |
7006 | u32 surface; | |
7007 | u32 tile_offset; | |
7008 | } plane[2]; | |
7009 | }; | |
7010 | ||
7011 | struct intel_display_error_state * | |
7012 | intel_display_capture_error_state(struct drm_device *dev) | |
7013 | { | |
7014 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7015 | struct intel_display_error_state *error; | |
7016 | int i; | |
7017 | ||
7018 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
7019 | if (error == NULL) | |
7020 | return NULL; | |
7021 | ||
7022 | for (i = 0; i < 2; i++) { | |
7023 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
7024 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
7025 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
7026 | ||
7027 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
7028 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
7029 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
7030 | error->plane[i].pos= I915_READ(DSPPOS(i)); | |
7031 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
7032 | if (INTEL_INFO(dev)->gen >= 4) { | |
7033 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
7034 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
7035 | } | |
7036 | ||
7037 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
7038 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
7039 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
7040 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
7041 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
7042 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
7043 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
7044 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
7045 | } | |
7046 | ||
7047 | return error; | |
7048 | } | |
7049 | ||
7050 | void | |
7051 | intel_display_print_error_state(struct seq_file *m, | |
7052 | struct drm_device *dev, | |
7053 | struct intel_display_error_state *error) | |
7054 | { | |
7055 | int i; | |
7056 | ||
7057 | for (i = 0; i < 2; i++) { | |
7058 | seq_printf(m, "Pipe [%d]:\n", i); | |
7059 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
7060 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
7061 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
7062 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
7063 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
7064 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
7065 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
7066 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
7067 | ||
7068 | seq_printf(m, "Plane [%d]:\n", i); | |
7069 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
7070 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
7071 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
7072 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
7073 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
7074 | if (INTEL_INFO(dev)->gen >= 4) { | |
7075 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
7076 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
7077 | } | |
7078 | ||
7079 | seq_printf(m, "Cursor [%d]:\n", i); | |
7080 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
7081 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
7082 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
7083 | } | |
7084 | } | |
7085 | #endif |