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drm/i915/bxt: Fix eDP panel fitting (v2)
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
ea916ea0
KM		 75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
465c120c
MR		 79};
80
3d7d6510
MR		 81/* Cursor formats */
82static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84};
85
6b383a7f 86static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 87
f1f644dc 88static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 89 struct intel_crtc_state *pipe_config);
18442d08 90static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 91 struct intel_crtc_state *pipe_config);
f1f644dc 92
eb1bfe80
JB		 93static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
5b18e57c
DV		 97static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 99static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
29407aab 102static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 103static void haswell_set_pipeconf(struct drm_crtc *crtc);
104static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 105static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
d288f65f 107static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 108 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 109static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 111static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
bfd16b2a
ML		 115static void skylake_pfit_enable(struct intel_crtc *crtc);
116static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117static void ironlake_pfit_enable(struct intel_crtc *crtc);
043e9bda 118static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 119
79e53945 120typedef struct {
0206e353 121 int min, max;
79e53945
JB		 122} intel_range_t;
123
124typedef struct {
0206e353
AJ		 125 int dot_limit;
126 int p2_slow, p2_fast;
79e53945
JB		 127} intel_p2_t;
128
d4906093
ML		 129typedef struct intel_limit intel_limit_t;
130struct intel_limit {
0206e353
AJ		 131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
d4906093 133};
79e53945 134
bfa7df01
VS		 135/* returns HPLL frequency in kHz */
136static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137{
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147}
148
149static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151{
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169}
170
d2acd215
DV		 171int
172intel_pch_rawclk(struct drm_device *dev)
173{
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179}
180
79e50a4f
JN		 181/* hrawclock is 1/4 the FSB frequency */
182int intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
bfa7df01
VS		 214static void intel_update_czclk(struct drm_i915_private *dev_priv)
215{
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223}
224
021357ac
CW		 225static inline u32 /* units of 100MHz */
226intel_fdi_link_freq(struct drm_device *dev)
227{
8b99e68c
CW		 228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
021357ac
CW		 233}
234
5d536e28 235static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 236 .dot = { .min = 25000, .max = 350000 },
9c333719 237 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 238 .n = { .min = 2, .max = 16 },
0206e353
AJ		 239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 246};
247
5d536e28
DV		 248static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
9c333719 250 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 251 .n = { .min = 2, .max = 16 },
5d536e28
DV		 252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259};
260
e4b36699 261static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 262 .dot = { .min = 25000, .max = 350000 },
9c333719 263 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 264 .n = { .min = 2, .max = 16 },
0206e353
AJ		 265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
e4b36699 272};
273e27ca 273
e4b36699 274static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 285};
286
287static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 298};
299
273e27ca 300
e4b36699 301static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
044c7c41 313 },
e4b36699
KP		 314};
315
316static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 327};
328
329static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
044c7c41 340 },
e4b36699
KP		 341};
342
343static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
044c7c41 354 },
e4b36699
KP		 355};
356
f2b115e6 357static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 360 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
273e27ca 363 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 370};
371
f2b115e6 372static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 383};
384
273e27ca
EA		 385/* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
b91ad0ec 390static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 401};
402
b91ad0ec 403static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 414};
415
416static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 427};
428
273e27ca 429/* LVDS 100mhz refclk limits. */
b91ad0ec 430static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
0206e353 438 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 441};
442
443static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
0206e353 451 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 454};
455
dc730512 456static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 464 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 465 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
b99ab663 468 .p1 = { .min = 2, .max = 3 },
5fdc9c49 469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 470};
471
ef9348c8
CML		 472static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 480 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486};
487
5ab7b0b7
ID		 488static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
e6292556 491 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498};
499
cdba954e
ACO		 500static bool
501needs_modeset(struct drm_crtc_state *state)
502{
fc596660 503 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 504}
505
e0638cdf
PZ		 506/**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
4093561b 509bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 510{
409ee761 511 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 512 struct intel_encoder *encoder;
513
409ee761 514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 515 if (encoder->type == type)
516 return true;
517
518 return false;
519}
520
d0737e1d
ACO		 521/**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
a93e255f
ACO		 527static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
d0737e1d 529{
a93e255f 530 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 531 struct drm_connector *connector;
a93e255f 532 struct drm_connector_state *connector_state;
d0737e1d 533 struct intel_encoder *encoder;
a93e255f
ACO		 534 int i, num_connectors = 0;
535
da3ced29 536 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
d0737e1d 541
a93e255f
ACO		 542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
d0737e1d 544 return true;
a93e255f
ACO		 545 }
546
547 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 548
549 return false;
550}
551
a93e255f
ACO		 552static const intel_limit_t *
553intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 554{
a93e255f 555 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 556 const intel_limit_t *limit;
b91ad0ec 557
a93e255f 558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 559 if (intel_is_dual_link_lvds(dev)) {
1b894b59 560 if (refclk == 100000)
b91ad0ec
ZW		 561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
1b894b59 565 if (refclk == 100000)
b91ad0ec
ZW		 566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
c6bb3538 570 } else
b91ad0ec 571 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 572
573 return limit;
574}
575
a93e255f
ACO		 576static const intel_limit_t *
577intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 578{
a93e255f 579 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 580 const intel_limit_t *limit;
581
a93e255f 582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 583 if (intel_is_dual_link_lvds(dev))
e4b36699 584 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 585 else
e4b36699 586 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 589 limit = &intel_limits_g4x_hdmi;
a93e255f 590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 591 limit = &intel_limits_g4x_sdvo;
044c7c41 592 } else /* The option is for other outputs */
e4b36699 593 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 594
595 return limit;
596}
597
a93e255f
ACO		 598static const intel_limit_t *
599intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 600{
a93e255f 601 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 602 const intel_limit_t *limit;
603
5ab7b0b7
ID		 604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
a93e255f 607 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 608 else if (IS_G4X(dev)) {
a93e255f 609 limit = intel_g4x_limit(crtc_state);
f2b115e6 610 } else if (IS_PINEVIEW(dev)) {
a93e255f 611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 612 limit = &intel_limits_pineview_lvds;
2177832f 613 else
f2b115e6 614 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
a0c4da24 617 } else if (IS_VALLEYVIEW(dev)) {
dc730512 618 limit = &intel_limits_vlv;
a6c45cf0 619 } else if (!IS_GEN2(dev)) {
a93e255f 620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
79e53945 624 } else {
a93e255f 625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 626 limit = &intel_limits_i8xx_lvds;
a93e255f 627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 628 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 629 else
630 limit = &intel_limits_i8xx_dac;
79e53945
JB		 631 }
632 return limit;
633}
634
dccbea3b
ID		 635/*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
f2b115e6 643/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 644static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 645{
2177832f
SL		 646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
ed5ca77e 648 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 649 return 0;
fb03ac01
VS		 650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 652
653 return clock->dot;
2177832f
SL		 654}
655
7429e9d4
DV		 656static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657{
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659}
660
dccbea3b 661static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 662{
7429e9d4 663 clock->m = i9xx_dpll_compute_m(clock);
79e53945 664 clock->p = clock->p1 * clock->p2;
ed5ca77e 665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 666 return 0;
fb03ac01
VS		 667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 669
670 return clock->dot;
79e53945
JB		 671}
672
dccbea3b 673static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 674{
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 678 return 0;
589eca67
ID		 679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 681
682 return clock->dot / 5;
589eca67
ID		 683}
684
dccbea3b 685int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 686{
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 690 return 0;
ef9348c8
CML		 691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 694
695 return clock->dot / 5;
ef9348c8
CML		 696}
697
7c04d1d9 698#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 699/**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
1b894b59
CW		 704static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
79e53945 707{
f01b7962
VS		 708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
79e53945 710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 711 INTELPllInvalid("p1 out of range\n");
79e53945 712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 713 INTELPllInvalid("m2 out of range\n");
79e53945 714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 715 INTELPllInvalid("m1 out of range\n");
f01b7962 716
5ab7b0b7 717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
5ab7b0b7 721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
79e53945 728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 729 INTELPllInvalid("vco out of range\n");
79e53945
JB		 730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 734 INTELPllInvalid("dot out of range\n");
79e53945
JB		 735
736 return true;
737}
738
3b1429d9
VS		 739static int
740i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
79e53945 743{
3b1429d9 744 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 745
a93e255f 746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 747 /*
a210b028
DV		 748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
79e53945 751 */
1974cad0 752 if (intel_is_dual_link_lvds(dev))
3b1429d9 753 return limit->p2.p2_fast;
79e53945 754 else
3b1429d9 755 return limit->p2.p2_slow;
79e53945
JB		 756 } else {
757 if (target < limit->p2.dot_limit)
3b1429d9 758 return limit->p2.p2_slow;
79e53945 759 else
3b1429d9 760 return limit->p2.p2_fast;
79e53945 761 }
3b1429d9
VS		 762}
763
764static bool
765i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769{
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
79e53945 773
0206e353 774 memset(best_clock, 0, sizeof(*best_clock));
79e53945 775
3b1429d9
VS		 776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
42158660
ZY		 778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 782 if (clock.m2 >= clock.m1)
42158660
ZY		 783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 788 int this_err;
789
dccbea3b 790 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809}
810
811static bool
a93e255f
ACO		 812pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
79e53945 816{
3b1429d9 817 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 818 intel_clock_t clock;
79e53945
JB		 819 int err = target;
820
0206e353 821 memset(best_clock, 0, sizeof(*best_clock));
79e53945 822
3b1429d9
VS		 823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
42158660
ZY		 825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 833 int this_err;
834
dccbea3b 835 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
79e53945 838 continue;
cec2f356
SP		 839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
79e53945
JB		 842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854}
855
d4906093 856static bool
a93e255f
ACO		 857g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
d4906093 861{
3b1429d9 862 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 863 intel_clock_t clock;
864 int max_n;
3b1429d9 865 bool found = false;
6ba770dc
AJ		 866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 868
869 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
d4906093 873 max_n = limit->n.max;
f77f13e2 874 /* based on hardware requirement, prefer smaller n to precision */
d4906093 875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 876 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
dccbea3b 885 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
d4906093 888 continue;
1b894b59
CW		 889
890 this_err = abs(clock.dot - target);
d4906093
ML		 891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
2c07245f
ZW		 901 return found;
902}
903
d5dd62bd
ID		 904/*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913{
9ca3ba01
ID		 914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
24be4e46
ID		 924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
d5dd62bd
ID		 927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942}
943
a0c4da24 944static bool
a93e255f
ACO		 945vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
a0c4da24 949{
a93e255f 950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 951 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 952 intel_clock_t clock;
69e4f900 953 unsigned int bestppm = 1000000;
27e639bf
VS		 954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 956 bool found = false;
a0c4da24 957
6b4bf1c4
VS		 958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 961
962 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 967 clock.p = clock.p1 * clock.p2;
a0c4da24 968 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 970 unsigned int ppm;
69e4f900 971
6b4bf1c4
VS		 972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
dccbea3b 975 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 976
f01b7962
VS		 977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
43b0ac53
VS		 979 continue;
980
d5dd62bd
ID		 981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
6b4bf1c4 986
d5dd62bd
ID		 987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
a0c4da24
JB		 990 }
991 }
992 }
993 }
a0c4da24 994
49e497ef 995 return found;
a0c4da24 996}
a4fc5ed6 997
ef9348c8 998static bool
a93e255f
ACO		 999chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003{
a93e255f 1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 1005 struct drm_device *dev = crtc->base.dev;
9ca3ba01 1006 unsigned int best_error_ppm;
ef9348c8
CML		 1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 1012 best_error_ppm = 1000000;
ef9348c8
CML		 1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 1026 unsigned int error_ppm;
ef9348c8
CML		 1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
dccbea3b 1038 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
9ca3ba01
ID		 1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
ef9348c8
CML		 1050 }
1051 }
1052
1053 return found;
1054}
1055
5ab7b0b7
ID		 1056bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058{
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063}
1064
20ddf665
VS		 1065bool intel_crtc_active(struct drm_crtc *crtc)
1066{
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
241bfc38 1072 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 1073 * as Haswell has gained clock readout/fastboot support.
1074 *
66e514c1 1075 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1076 * properly reconstruct framebuffers.
c3d1f436
MR		 1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
20ddf665 1081 */
c3d1f436 1082 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1084}
1085
a5c961d1
PZ		 1086enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088{
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
6e3c9717 1092 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1093}
1094
fbf49ea2
VS		 1095static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096{
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1108 msleep(5);
fbf49ea2
VS		 1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112}
1113
ab7ad7f6
KP		 1114/*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1116 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
ab7ad7f6
KP		 1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
58e10eb9 1128 *
9d0498a2 1129 */
575f7ab7 1130static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1131{
575f7ab7 1132 struct drm_device *dev = crtc->base.dev;
9d0498a2 1133 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1135 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1138 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1139
1140 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
284637d9 1143 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1144 } else {
ab7ad7f6 1145 /* Wait for the display line to settle */
fbf49ea2 1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1147 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1148 }
79e53945
JB		 1149}
1150
b24e7179
JB		 1151static const char *state_string(bool enabled)
1152{
1153 return enabled ? "on" : "off";
1154}
1155
1156/* Only for pre-ILK configs */
55607e8a
DV		 1157void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
b24e7179 1159{
b24e7179
JB		 1160 u32 val;
1161 bool cur_state;
1162
649636ef 1163 val = I915_READ(DPLL(pipe));
b24e7179 1164 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1165 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1168}
b24e7179 1169
23538ef1
JN		 1170/* XXX: the dsi pll is shared between MIPI DSI ports */
1171static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172{
1173 u32 val;
1174 bool cur_state;
1175
a580516d 1176 mutex_lock(&dev_priv->sb_lock);
23538ef1 1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1178 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1179
1180 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1181 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184}
1185#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
55607e8a 1188struct intel_shared_dpll *
e2b78267
DV		 1189intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190{
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
6e3c9717 1193 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1194 return NULL;
1195
6e3c9717 1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1197}
1198
040484af 1199/* For ILK+ */
55607e8a
DV		 1200void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1202 bool state)
040484af 1203{
040484af 1204 bool cur_state;
5358901f 1205 struct intel_dpll_hw_state hw_state;
040484af 1206
92b27b08 1207 if (WARN (!pll,
46edb027 1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1209 return;
ee7b9f93 1210
5358901f 1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1212 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
040484af 1215}
040484af
JB		 1216
1217static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219{
040484af 1220 bool cur_state;
ad80a810
PZ		 1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222 pipe);
040484af 1223
affa9354
PZ		 1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
649636ef 1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
ad80a810 1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7 1228 } else {
649636ef 1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
bf507ef7
ED		 1230 cur_state = !!(val & FDI_TX_ENABLE);
1231 }
e2c719b7 1232 I915_STATE_WARN(cur_state != state,
040484af
JB		 1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1235}
1236#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241{
040484af
JB		 1242 u32 val;
1243 bool cur_state;
1244
649636ef 1245 val = I915_READ(FDI_RX_CTL(pipe));
d63fa0dc 1246 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1247 I915_STATE_WARN(cur_state != state,
040484af
JB		 1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1250}
1251#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256{
040484af
JB		 1257 u32 val;
1258
1259 /* ILK FDI PLL is always enabled */
3d13ef2e 1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1261 return;
1262
bf507ef7 1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1264 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1265 return;
1266
649636ef 1267 val = I915_READ(FDI_TX_CTL(pipe));
e2c719b7 1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1269}
1270
55607e8a
DV		 1271void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
040484af 1273{
040484af 1274 u32 val;
55607e8a 1275 bool cur_state;
040484af 1276
649636ef 1277 val = I915_READ(FDI_RX_CTL(pipe));
55607e8a 1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1279 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
040484af
JB		 1282}
1283
b680c37a
DV		 1284void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
ea0760cf 1286{
bedd4dba
JN		 1287 struct drm_device *dev = dev_priv->dev;
1288 int pp_reg;
ea0760cf
JB		 1289 u32 val;
1290 enum pipe panel_pipe = PIPE_A;
0de3b485 1291 bool locked = true;
ea0760cf 1292
bedd4dba
JN		 1293 if (WARN_ON(HAS_DDI(dev)))
1294 return;
1295
1296 if (HAS_PCH_SPLIT(dev)) {
1297 u32 port_sel;
1298
ea0760cf 1299 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309 panel_pipe = pipe;
ea0760cf
JB		 1310 } else {
1311 pp_reg = PP_CONTROL;
bedd4dba
JN		 1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
ea0760cf
JB		 1314 }
1315
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1319 locked = false;
1320
e2c719b7 1321 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1322 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1323 pipe_name(pipe));
ea0760cf
JB		 1324}
1325
93ce0ba6
JN		 1326static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328{
1329 struct drm_device *dev = dev_priv->dev;
1330 bool cur_state;
1331
d9d82081 1332 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
d9d82081 1334 else
5efb3e28 1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1336
e2c719b7 1337 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340}
1341#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
b840d907
JB		 1344void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
b24e7179 1346{
63d7bbe9 1347 bool cur_state;
702e7a56
PZ		 1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349 pipe);
b24e7179 1350
b6b5d049
VS		 1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1354 state = true;
1355
f458ebbc 1356 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1358 cur_state = false;
1359 } else {
649636ef 1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
69310161
PZ		 1361 cur_state = !!(val & PIPECONF_ENABLE);
1362 }
1363
e2c719b7 1364 I915_STATE_WARN(cur_state != state,
63d7bbe9 1365 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1366 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1367}
1368
931872fc
CW		 1369static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
b24e7179 1371{
b24e7179 1372 u32 val;
931872fc 1373 bool cur_state;
b24e7179 1374
649636ef 1375 val = I915_READ(DSPCNTR(plane));
931872fc 1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1377 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1380}
1381
931872fc
CW		 1382#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
b24e7179
JB		 1385static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387{
653e1026 1388 struct drm_device *dev = dev_priv->dev;
649636ef 1389 int i;
b24e7179 1390
653e1026
VS		 1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
649636ef 1393 u32 val = I915_READ(DSPCNTR(pipe));
e2c719b7 1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1395 "plane %c assertion failure, should be disabled but not\n",
1396 plane_name(pipe));
19ec1358 1397 return;
28c05794 1398 }
19ec1358 1399
b24e7179 1400 /* Need to check both planes against the pipe */
055e393f 1401 for_each_pipe(dev_priv, i) {
649636ef
VS		 1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
b24e7179 1404 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1408 }
1409}
1410
19332d7a
JB		 1411static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413{
20674eef 1414 struct drm_device *dev = dev_priv->dev;
649636ef 1415 int sprite;
19332d7a 1416
7feb8b88 1417 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1418 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1423 }
1424 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1425 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
e2c719b7 1427 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1429 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1430 }
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
649636ef 1432 u32 val = I915_READ(SPRCTL(pipe));
e2c719b7 1433 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
649636ef 1437 u32 val = I915_READ(DVSCNTR(pipe));
e2c719b7 1438 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1440 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1441 }
1442}
1443
08c71e5e
VS		 1444static void assert_vblank_disabled(struct drm_crtc *crtc)
1445{
e2c719b7 1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1447 drm_crtc_vblank_put(crtc);
1448}
1449
89eff4be 1450static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1451{
1452 u32 val;
1453 bool enabled;
1454
e2c719b7 1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1456
92f2584a
JB		 1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1461}
1462
ab9412ba
DV		 1463static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
92f2584a 1465{
92f2584a
JB		 1466 u32 val;
1467 bool enabled;
1468
649636ef 1469 val = I915_READ(PCH_TRANSCONF(pipe));
92f2584a 1470 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1471 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 pipe_name(pipe));
92f2584a
JB		 1474}
1475
4e634389
KP		 1476static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1478{
1479 if ((val & DP_PORT_EN) == 0)
1480 return false;
1481
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486 return false;
44f37d1f
CML		 1487 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489 return false;
f0575e92
KP		 1490 } else {
1491 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492 return false;
1493 }
1494 return true;
1495}
1496
1519b995
KP		 1497static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499{
dc0fa718 1500 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1501 return false;
1502
1503 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1504 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1505 return false;
44f37d1f
CML		 1506 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508 return false;
1519b995 1509 } else {
dc0fa718 1510 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1511 return false;
1512 }
1513 return true;
1514}
1515
1516static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517 enum pipe pipe, u32 val)
1518{
1519 if ((val & LVDS_PORT_EN) == 0)
1520 return false;
1521
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527 return false;
1528 }
1529 return true;
1530}
1531
1532static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, u32 val)
1534{
1535 if ((val & ADPA_DAC_ENABLE) == 0)
1536 return false;
1537 if (HAS_PCH_CPT(dev_priv->dev)) {
1538 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539 return false;
1540 } else {
1541 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542 return false;
1543 }
1544 return true;
1545}
1546
291906f1 1547static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1548 enum pipe pipe, int reg, u32 port_sel)
291906f1 1549{
47a05eca 1550 u32 val = I915_READ(reg);
e2c719b7 1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1553 reg, pipe_name(pipe));
de9a35ab 1554
e2c719b7 1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1556 && (val & DP_PIPEB_SELECT),
de9a35ab 1557 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1558}
1559
1560static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, int reg)
1562{
47a05eca 1563 u32 val = I915_READ(reg);
e2c719b7 1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1566 reg, pipe_name(pipe));
de9a35ab 1567
e2c719b7 1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1569 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1570 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1571}
1572
1573static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575{
291906f1 1576 u32 val;
291906f1 1577
f0575e92
KP		 1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1 1581
649636ef 1582 val = I915_READ(PCH_ADPA);
e2c719b7 1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
649636ef 1587 val = I915_READ(PCH_LVDS);
e2c719b7 1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1590 pipe_name(pipe));
291906f1 1591
e2debe91
PZ		 1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1595}
1596
d288f65f 1597static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1598 const struct intel_crtc_state *pipe_config)
87442f73 1599{
426115cf
DV		 1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
d288f65f 1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1604
426115cf 1605 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1611 if (IS_MOBILE(dev_priv->dev))
426115cf 1612 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1613
426115cf
DV		 1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
d288f65f 1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1622 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1623
1624 /* We do this three times for luck */
426115cf 1625 I915_WRITE(reg, dpll);
87442f73
DV		 1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
426115cf 1628 I915_WRITE(reg, dpll);
87442f73
DV		 1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
426115cf 1631 I915_WRITE(reg, dpll);
87442f73
DV		 1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634}
1635
d288f65f 1636static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1637 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1638{
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
a580516d 1649 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
54433e91
VS		 1656 mutex_unlock(&dev_priv->sb_lock);
1657
9d556c99
CML		 1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
d288f65f 1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1665
1666 /* Check PLL is locked */
a11b0703 1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
a11b0703 1670 /* not sure when this should be written */
d288f65f 1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1672 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1673}
1674
1c4e0274
VS		 1675static int intel_num_dvo_pipes(struct drm_device *dev)
1676{
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
3538b9df 1681 count += crtc->base.state->active &&
409ee761 1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1683
1684 return count;
1685}
1686
66e3d5c0 1687static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1688{
66e3d5c0
DV		 1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
6e3c9717 1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1693
66e3d5c0 1694 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1695
63d7bbe9 1696 /* No really, not for ILK+ */
3d13ef2e 1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1698
1699 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1702
1c4e0274
VS		 1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
66e3d5c0
DV		 1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1722 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
63d7bbe9
JB		 1731
1732 /* We do this three times for luck */
66e3d5c0 1733 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
66e3d5c0 1736 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
66e3d5c0 1739 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742}
1743
1744/**
50b44a44 1745 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1c4e0274 1753static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1754{
1c4e0274
VS		 1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
409ee761 1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1762 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
b6b5d049
VS		 1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
b8afb911 1777 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1778 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1779}
1780
f6071166
JB		 1781static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782{
b8afb911 1783 u32 val;
f6071166
JB		 1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
e5cbfbfb
ID		 1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
b8afb911 1792 val = DPLL_VGA_MODE_DIS;
f6071166 1793 if (pipe == PIPE_B)
60bfe44f 1794 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1795 I915_WRITE(DPLL(pipe), val);
1796 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1797
1798}
1799
1800static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801{
d752048d 1802 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1803 u32 val;
1804
a11b0703
VS		 1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1807
a11b0703 1808 /* Set PLL en = 0 */
60bfe44f
VS		 1809 val = DPLL_SSC_REF_CLK_CHV |
1810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1811 if (pipe != PIPE_A)
1812 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813 I915_WRITE(DPLL(pipe), val);
1814 POSTING_READ(DPLL(pipe));
d752048d 1815
a580516d 1816 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1817
1818 /* Disable 10bit clock to display controller */
1819 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820 val &= ~DPIO_DCLKP_EN;
1821 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
a580516d 1823 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1824}
1825
e4607fcf 1826void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1827 struct intel_digital_port *dport,
1828 unsigned int expected_mask)
89b667f8
JB		 1829{
1830 u32 port_mask;
00fc31b7 1831 int dpll_reg;
89b667f8 1832
e4607fcf
CML		 1833 switch (dport->port) {
1834 case PORT_B:
89b667f8 1835 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1836 dpll_reg = DPLL(0);
e4607fcf
CML		 1837 break;
1838 case PORT_C:
89b667f8 1839 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1840 dpll_reg = DPLL(0);
9b6de0a1 1841 expected_mask <<= 4;
00fc31b7
CML		 1842 break;
1843 case PORT_D:
1844 port_mask = DPLL_PORTD_READY_MASK;
1845 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1846 break;
1847 default:
1848 BUG();
1849 }
89b667f8 1850
9b6de0a1
VS		 1851 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1854}
1855
b14b1055
DV		 1856static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857{
1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
be19f0ff
CW		 1862 if (WARN_ON(pll == NULL))
1863 return;
1864
3e369b76 1865 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1866 if (pll->active == 0) {
1867 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868 WARN_ON(pll->on);
1869 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871 pll->mode_set(dev_priv, pll);
1872 }
1873}
1874
92f2584a 1875/**
85b3894f 1876 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1877 * @dev_priv: i915 private structure
1878 * @pipe: pipe PLL to enable
1879 *
1880 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881 * drives the transcoder clock.
1882 */
85b3894f 1883static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1884{
3d13ef2e
DL		 1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1888
87a875bb 1889 if (WARN_ON(pll == NULL))
48da64a8
CW		 1890 return;
1891
3e369b76 1892 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1893 return;
ee7b9f93 1894
74dd6928 1895 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1896 pll->name, pll->active, pll->on,
e2b78267 1897 crtc->base.base.id);
92f2584a 1898
cdbd2316
DV		 1899 if (pll->active++) {
1900 WARN_ON(!pll->on);
e9d6944e 1901 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1902 return;
1903 }
f4a091c7 1904 WARN_ON(pll->on);
ee7b9f93 1905
bd2bb1b9
PZ		 1906 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
46edb027 1908 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1909 pll->enable(dev_priv, pll);
ee7b9f93 1910 pll->on = true;
92f2584a
JB		 1911}
1912
f6daaec2 1913static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1914{
3d13ef2e
DL		 1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1918
92f2584a 1919 /* PCH only available on ILK+ */
80aa9312
JB		 1920 if (INTEL_INFO(dev)->gen < 5)
1921 return;
1922
eddfcbcd
ML		 1923 if (pll == NULL)
1924 return;
92f2584a 1925
eddfcbcd 1926 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1927 return;
7a419866 1928
46edb027
DV		 1929 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930 pll->name, pll->active, pll->on,
e2b78267 1931 crtc->base.base.id);
7a419866 1932
48da64a8 1933 if (WARN_ON(pll->active == 0)) {
e9d6944e 1934 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1935 return;
1936 }
1937
e9d6944e 1938 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1939 WARN_ON(!pll->on);
cdbd2316 1940 if (--pll->active)
7a419866 1941 return;
ee7b9f93 1942
46edb027 1943 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1944 pll->disable(dev_priv, pll);
ee7b9f93 1945 pll->on = false;
bd2bb1b9
PZ		 1946
1947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1948}
1949
b8a4f404
PZ		 1950static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951 enum pipe pipe)
040484af 1952{
23670b32 1953 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1956 uint32_t reg, val, pipeconf_val;
040484af
JB		 1957
1958 /* PCH only available on ILK+ */
55522f37 1959 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1960
1961 /* Make sure PCH DPLL is enabled */
e72f9fbf 1962 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1963 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1964
1965 /* FDI must be feeding us bits for PCH ports */
1966 assert_fdi_tx_enabled(dev_priv, pipe);
1967 assert_fdi_rx_enabled(dev_priv, pipe);
1968
23670b32
DV		 1969 if (HAS_PCH_CPT(dev)) {
1970 /* Workaround: Set the timing override bit before enabling the
1971 * pch transcoder. */
1972 reg = TRANS_CHICKEN2(pipe);
1973 val = I915_READ(reg);
1974 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1975 I915_WRITE(reg, val);
59c859d6 1976 }
23670b32 1977
ab9412ba 1978 reg = PCH_TRANSCONF(pipe);
040484af 1979 val = I915_READ(reg);
5f7f726d 1980 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1981
1982 if (HAS_PCH_IBX(dev_priv->dev)) {
1983 /*
c5de7c6f
VS		 1984 * Make the BPC in transcoder be consistent with
1985 * that in pipeconf reg. For HDMI we must use 8bpc
1986 * here for both 8bpc and 12bpc.
e9bcff5c 1987 */
dfd07d72 1988 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1989 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1990 val |= PIPECONF_8BPC;
1991 else
1992 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1993 }
5f7f726d
PZ		 1994
1995 val &= ~TRANS_INTERLACE_MASK;
1996 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1997 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1998 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1999 val |= TRANS_LEGACY_INTERLACED_ILK;
2000 else
2001 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2002 else
2003 val |= TRANS_PROGRESSIVE;
2004
040484af
JB		 2005 I915_WRITE(reg, val | TRANS_ENABLE);
2006 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2007 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2008}
2009
8fb033d7 2010static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2011 enum transcoder cpu_transcoder)
040484af 2012{
8fb033d7 2013 u32 val, pipeconf_val;
8fb033d7
PZ		 2014
2015 /* PCH only available on ILK+ */
55522f37 2016 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2017
8fb033d7 2018 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2019 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2020 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2021
223a6fdf 2022 /* Workaround: set timing override bit. */
36c0d0cf 2023 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2024 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2025 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
223a6fdf 2026
25f3ef11 2027 val = TRANS_ENABLE;
937bb610 2028 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2029
9a76b1c6
PZ		 2030 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2031 PIPECONF_INTERLACED_ILK)
a35f2679 2032 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2033 else
2034 val |= TRANS_PROGRESSIVE;
2035
ab9412ba
DV		 2036 I915_WRITE(LPT_TRANSCONF, val);
2037 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2038 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2039}
2040
b8a4f404
PZ		 2041static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2042 enum pipe pipe)
040484af 2043{
23670b32
DV		 2044 struct drm_device *dev = dev_priv->dev;
2045 uint32_t reg, val;
040484af
JB		 2046
2047 /* FDI relies on the transcoder */
2048 assert_fdi_tx_disabled(dev_priv, pipe);
2049 assert_fdi_rx_disabled(dev_priv, pipe);
2050
291906f1
JB		 2051 /* Ports must be off as well */
2052 assert_pch_ports_disabled(dev_priv, pipe);
2053
ab9412ba 2054 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2055 val = I915_READ(reg);
2056 val &= ~TRANS_ENABLE;
2057 I915_WRITE(reg, val);
2058 /* wait for PCH transcoder off, transcoder state */
2059 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2060 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2061
2062 if (!HAS_PCH_IBX(dev)) {
2063 /* Workaround: Clear the timing override chicken bit again. */
2064 reg = TRANS_CHICKEN2(pipe);
2065 val = I915_READ(reg);
2066 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2067 I915_WRITE(reg, val);
2068 }
040484af
JB		 2069}
2070
ab4d966c 2071static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2072{
8fb033d7
PZ		 2073 u32 val;
2074
ab9412ba 2075 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2076 val &= ~TRANS_ENABLE;
ab9412ba 2077 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2078 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2079 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2080 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2081
2082 /* Workaround: clear timing override bit. */
36c0d0cf 2083 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2085 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
040484af
JB		 2086}
2087
b24e7179 2088/**
309cfea8 2089 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2090 * @crtc: crtc responsible for the pipe
b24e7179 2091 *
0372264a 2092 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2093 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2094 */
e1fdc473 2095static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2096{
0372264a
PZ		 2097 struct drm_device *dev = crtc->base.dev;
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2100 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2101 pipe);
1a240d4d 2102 enum pipe pch_transcoder;
b24e7179
JB		 2103 int reg;
2104 u32 val;
2105
9e2ee2dd
VS		 2106 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2107
58c6eaa2 2108 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2109 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2110 assert_sprites_disabled(dev_priv, pipe);
2111
681e5811 2112 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2113 pch_transcoder = TRANSCODER_A;
2114 else
2115 pch_transcoder = pipe;
2116
b24e7179
JB		 2117 /*
2118 * A pipe without a PLL won't actually be able to drive bits from
2119 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2120 * need the check.
2121 */
50360403 2122 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2123 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2124 assert_dsi_pll_enabled(dev_priv);
2125 else
2126 assert_pll_enabled(dev_priv, pipe);
040484af 2127 else {
6e3c9717 2128 if (crtc->config->has_pch_encoder) {
040484af 2129 /* if driving the PCH, we need FDI enabled */
cc391bbb 2130 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2131 assert_fdi_tx_pll_enabled(dev_priv,
2132 (enum pipe) cpu_transcoder);
040484af
JB		 2133 }
2134 /* FIXME: assert CPU port conditions for SNB+ */
2135 }
b24e7179 2136
702e7a56 2137 reg = PIPECONF(cpu_transcoder);
b24e7179 2138 val = I915_READ(reg);
7ad25d48 2139 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2140 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2141 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2142 return;
7ad25d48 2143 }
00d70b15
CW		 2144
2145 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2146 POSTING_READ(reg);
b24e7179
JB		 2147}
2148
2149/**
309cfea8 2150 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2151 * @crtc: crtc whose pipes is to be disabled
b24e7179 2152 *
575f7ab7
VS		 2153 * Disable the pipe of @crtc, making sure that various hardware
2154 * specific requirements are met, if applicable, e.g. plane
2155 * disabled, panel fitter off, etc.
b24e7179
JB		 2156 *
2157 * Will wait until the pipe has shut down before returning.
2158 */
575f7ab7 2159static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2160{
575f7ab7 2161 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2162 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2163 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2164 int reg;
2165 u32 val;
2166
9e2ee2dd
VS		 2167 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2168
b24e7179
JB		 2169 /*
2170 * Make sure planes won't keep trying to pump pixels to us,
2171 * or we might hang the display.
2172 */
2173 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2174 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2175 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2176
702e7a56 2177 reg = PIPECONF(cpu_transcoder);
b24e7179 2178 val = I915_READ(reg);
00d70b15
CW		 2179 if ((val & PIPECONF_ENABLE) == 0)
2180 return;
2181
67adc644
VS		 2182 /*
2183 * Double wide has implications for planes
2184 * so best keep it disabled when not needed.
2185 */
6e3c9717 2186 if (crtc->config->double_wide)
67adc644
VS		 2187 val &= ~PIPECONF_DOUBLE_WIDE;
2188
2189 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2190 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2191 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2192 val &= ~PIPECONF_ENABLE;
2193
2194 I915_WRITE(reg, val);
2195 if ((val & PIPECONF_ENABLE) == 0)
2196 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2197}
2198
693db184
CW		 2199static bool need_vtd_wa(struct drm_device *dev)
2200{
2201#ifdef CONFIG_INTEL_IOMMU
2202 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2203 return true;
2204#endif
2205 return false;
2206}
2207
50470bb0 2208unsigned int
6761dd31 2209intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
fe47ea0c 2210 uint64_t fb_format_modifier, unsigned int plane)
a57ce0b2 2211{
6761dd31
TU		 2212 unsigned int tile_height;
2213 uint32_t pixel_bytes;
a57ce0b2 2214
b5d0e9bf
DL		 2215 switch (fb_format_modifier) {
2216 case DRM_FORMAT_MOD_NONE:
2217 tile_height = 1;
2218 break;
2219 case I915_FORMAT_MOD_X_TILED:
2220 tile_height = IS_GEN2(dev) ? 16 : 8;
2221 break;
2222 case I915_FORMAT_MOD_Y_TILED:
2223 tile_height = 32;
2224 break;
2225 case I915_FORMAT_MOD_Yf_TILED:
fe47ea0c 2226 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
6761dd31 2227 switch (pixel_bytes) {
b5d0e9bf 2228 default:
6761dd31 2229 case 1:
b5d0e9bf
DL		 2230 tile_height = 64;
2231 break;
6761dd31
TU		 2232 case 2:
2233 case 4:
b5d0e9bf
DL		 2234 tile_height = 32;
2235 break;
6761dd31 2236 case 8:
b5d0e9bf
DL		 2237 tile_height = 16;
2238 break;
6761dd31 2239 case 16:
b5d0e9bf
DL		 2240 WARN_ONCE(1,
2241 "128-bit pixels are not supported for display!");
2242 tile_height = 16;
2243 break;
2244 }
2245 break;
2246 default:
2247 MISSING_CASE(fb_format_modifier);
2248 tile_height = 1;
2249 break;
2250 }
091df6cb 2251
6761dd31
TU		 2252 return tile_height;
2253}
2254
2255unsigned int
2256intel_fb_align_height(struct drm_device *dev, unsigned int height,
2257 uint32_t pixel_format, uint64_t fb_format_modifier)
2258{
2259 return ALIGN(height, intel_tile_height(dev, pixel_format,
fe47ea0c 2260 fb_format_modifier, 0));
a57ce0b2
JB		 2261}
2262
f64b98cd
TU		 2263static int
2264intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2265 const struct drm_plane_state *plane_state)
2266{
50470bb0 2267 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2268 unsigned int tile_height, tile_pitch;
50470bb0 2269
f64b98cd
TU		 2270 *view = i915_ggtt_view_normal;
2271
50470bb0
TU		 2272 if (!plane_state)
2273 return 0;
2274
121920fa 2275 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2276 return 0;
2277
9abc4648 2278 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2279
2280 info->height = fb->height;
2281 info->pixel_format = fb->pixel_format;
2282 info->pitch = fb->pitches[0];
89e3e142 2283 info->uv_offset = fb->offsets[1];
50470bb0
TU		 2284 info->fb_modifier = fb->modifier[0];
2285
84fe03f7 2286 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
fe47ea0c 2287 fb->modifier[0], 0);
84fe03f7
TU		 2288 tile_pitch = PAGE_SIZE / tile_height;
2289 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2290 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2291 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2292
89e3e142
TU		 2293 if (info->pixel_format == DRM_FORMAT_NV12) {
2294 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2295 fb->modifier[0], 1);
2296 tile_pitch = PAGE_SIZE / tile_height;
2297 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2298 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2299 tile_height);
2300 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2301 PAGE_SIZE;
2302 }
2303
f64b98cd
TU		 2304 return 0;
2305}
2306
4e9a86b6
VS		 2307static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2308{
2309 if (INTEL_INFO(dev_priv)->gen >= 9)
2310 return 256 * 1024;
985b8bb4
VS		 2311 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2312 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2313 return 128 * 1024;
2314 else if (INTEL_INFO(dev_priv)->gen >= 4)
2315 return 4 * 1024;
2316 else
44c5905e 2317 return 0;
4e9a86b6
VS		 2318}
2319
127bd2ac 2320int
850c4cdc
TU		 2321intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2322 struct drm_framebuffer *fb,
7580d774 2323 const struct drm_plane_state *plane_state)
6b95a207 2324{
850c4cdc 2325 struct drm_device *dev = fb->dev;
ce453d81 2326 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2327 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2328 struct i915_ggtt_view view;
6b95a207
KH		 2329 u32 alignment;
2330 int ret;
2331
ebcdd39e
MR		 2332 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2333
7b911adc
TU		 2334 switch (fb->modifier[0]) {
2335 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2336 alignment = intel_linear_alignment(dev_priv);
6b95a207 2337 break;
7b911adc 2338 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2339 if (INTEL_INFO(dev)->gen >= 9)
2340 alignment = 256 * 1024;
2341 else {
2342 /* pin() will align the object as required by fence */
2343 alignment = 0;
2344 }
6b95a207 2345 break;
7b911adc 2346 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2347 case I915_FORMAT_MOD_Yf_TILED:
2348 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2349 "Y tiling bo slipped through, driver bug!\n"))
2350 return -EINVAL;
2351 alignment = 1 * 1024 * 1024;
2352 break;
6b95a207 2353 default:
7b911adc
TU		 2354 MISSING_CASE(fb->modifier[0]);
2355 return -EINVAL;
6b95a207
KH		 2356 }
2357
f64b98cd
TU		 2358 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2359 if (ret)
2360 return ret;
2361
693db184
CW		 2362 /* Note that the w/a also requires 64 PTE of padding following the
2363 * bo. We currently fill all unused PTE with the shadow page and so
2364 * we should always have valid PTE following the scanout preventing
2365 * the VT-d warning.
2366 */
2367 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2368 alignment = 256 * 1024;
2369
d6dd6843
PZ		 2370 /*
2371 * Global gtt pte registers are special registers which actually forward
2372 * writes to a chunk of system memory. Which means that there is no risk
2373 * that the register values disappear as soon as we call
2374 * intel_runtime_pm_put(), so it is correct to wrap only the
2375 * pin/unpin/fence and not more.
2376 */
2377 intel_runtime_pm_get(dev_priv);
2378
7580d774
ML		 2379 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2380 &view);
48b956c5 2381 if (ret)
b26a6b35 2382 goto err_pm;
6b95a207
KH		 2383
2384 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2385 * fence, whereas 965+ only requires a fence if using
2386 * framebuffer compression. For simplicity, we always install
2387 * a fence as the cost is not that onerous.
2388 */
06d98131 2389 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2390 if (ret == -EDEADLK) {
2391 /*
2392 * -EDEADLK means there are no free fences
2393 * no pending flips.
2394 *
2395 * This is propagated to atomic, but it uses
2396 * -EDEADLK to force a locking recovery, so
2397 * change the returned error to -EBUSY.
2398 */
2399 ret = -EBUSY;
2400 goto err_unpin;
2401 } else if (ret)
9a5a53b3 2402 goto err_unpin;
1690e1eb 2403
9a5a53b3 2404 i915_gem_object_pin_fence(obj);
6b95a207 2405
d6dd6843 2406 intel_runtime_pm_put(dev_priv);
6b95a207 2407 return 0;
48b956c5
CW		 2408
2409err_unpin:
f64b98cd 2410 i915_gem_object_unpin_from_display_plane(obj, &view);
b26a6b35 2411err_pm:
d6dd6843 2412 intel_runtime_pm_put(dev_priv);
48b956c5 2413 return ret;
6b95a207
KH		 2414}
2415
82bc3b2d
TU		 2416static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2417 const struct drm_plane_state *plane_state)
1690e1eb 2418{
82bc3b2d 2419 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2420 struct i915_ggtt_view view;
2421 int ret;
82bc3b2d 2422
ebcdd39e
MR		 2423 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2424
f64b98cd
TU		 2425 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2426 WARN_ONCE(ret, "Couldn't get view from plane state!");
2427
1690e1eb 2428 i915_gem_object_unpin_fence(obj);
f64b98cd 2429 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2430}
2431
c2c75131
DV		 2432/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2433 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2434unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2435 int *x, int *y,
bc752862
CW		 2436 unsigned int tiling_mode,
2437 unsigned int cpp,
2438 unsigned int pitch)
c2c75131 2439{
bc752862
CW		 2440 if (tiling_mode != I915_TILING_NONE) {
2441 unsigned int tile_rows, tiles;
c2c75131 2442
bc752862
CW		 2443 tile_rows = *y / 8;
2444 *y %= 8;
c2c75131 2445
bc752862
CW		 2446 tiles = *x / (512/cpp);
2447 *x %= 512/cpp;
2448
2449 return tile_rows * pitch * 8 + tiles * 4096;
2450 } else {
4e9a86b6 2451 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2452 unsigned int offset;
2453
2454 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2455 *y = (offset & alignment) / pitch;
2456 *x = ((offset & alignment) - *y * pitch) / cpp;
2457 return offset & ~alignment;
bc752862 2458 }
c2c75131
DV		 2459}
2460
b35d63fa 2461static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2462{
2463 switch (format) {
2464 case DISPPLANE_8BPP:
2465 return DRM_FORMAT_C8;
2466 case DISPPLANE_BGRX555:
2467 return DRM_FORMAT_XRGB1555;
2468 case DISPPLANE_BGRX565:
2469 return DRM_FORMAT_RGB565;
2470 default:
2471 case DISPPLANE_BGRX888:
2472 return DRM_FORMAT_XRGB8888;
2473 case DISPPLANE_RGBX888:
2474 return DRM_FORMAT_XBGR8888;
2475 case DISPPLANE_BGRX101010:
2476 return DRM_FORMAT_XRGB2101010;
2477 case DISPPLANE_RGBX101010:
2478 return DRM_FORMAT_XBGR2101010;
2479 }
2480}
2481
bc8d7dff
DL		 2482static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2483{
2484 switch (format) {
2485 case PLANE_CTL_FORMAT_RGB_565:
2486 return DRM_FORMAT_RGB565;
2487 default:
2488 case PLANE_CTL_FORMAT_XRGB_8888:
2489 if (rgb_order) {
2490 if (alpha)
2491 return DRM_FORMAT_ABGR8888;
2492 else
2493 return DRM_FORMAT_XBGR8888;
2494 } else {
2495 if (alpha)
2496 return DRM_FORMAT_ARGB8888;
2497 else
2498 return DRM_FORMAT_XRGB8888;
2499 }
2500 case PLANE_CTL_FORMAT_XRGB_2101010:
2501 if (rgb_order)
2502 return DRM_FORMAT_XBGR2101010;
2503 else
2504 return DRM_FORMAT_XRGB2101010;
2505 }
2506}
2507
5724dbd1 2508static bool
f6936e29
DV		 2509intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2510 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2511{
2512 struct drm_device *dev = crtc->base.dev;
3badb49f 2513 struct drm_i915_private *dev_priv = to_i915(dev);
46f297fb
JB		 2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2516 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
46f297fb 2522
ff2652ea
CW		 2523 if (plane_config->size == 0)
2524 return false;
2525
3badb49f
PZ		 2526 /* If the FB is too big, just don't use it since fbdev is not very
2527 * important and we should probably use that space with FBC or other
2528 * features. */
2529 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2530 return false;
2531
f37b5c2b
DV		 2532 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2533 base_aligned,
2534 base_aligned,
2535 size_aligned);
46f297fb 2536 if (!obj)
484b41dd 2537 return false;
46f297fb 2538
49af449b
DL		 2539 obj->tiling_mode = plane_config->tiling;
2540 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2541 obj->stride = fb->pitches[0];
46f297fb 2542
6bf129df
DL		 2543 mode_cmd.pixel_format = fb->pixel_format;
2544 mode_cmd.width = fb->width;
2545 mode_cmd.height = fb->height;
2546 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2547 mode_cmd.modifier[0] = fb->modifier[0];
2548 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2549
2550 mutex_lock(&dev->struct_mutex);
6bf129df 2551 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2552 &mode_cmd, obj)) {
46f297fb
JB		 2553 DRM_DEBUG_KMS("intel fb init failed\n");
2554 goto out_unref_obj;
2555 }
46f297fb 2556 mutex_unlock(&dev->struct_mutex);
484b41dd 2557
f6936e29 2558 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2559 return true;
46f297fb
JB		 2560
2561out_unref_obj:
2562 drm_gem_object_unreference(&obj->base);
2563 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2564 return false;
2565}
2566
afd65eb4
MR		 2567/* Update plane->state->fb to match plane->fb after driver-internal updates */
2568static void
2569update_state_fb(struct drm_plane *plane)
2570{
2571 if (plane->fb == plane->state->fb)
2572 return;
2573
2574 if (plane->state->fb)
2575 drm_framebuffer_unreference(plane->state->fb);
2576 plane->state->fb = plane->fb;
2577 if (plane->state->fb)
2578 drm_framebuffer_reference(plane->state->fb);
2579}
2580
5724dbd1 2581static void
f6936e29
DV		 2582intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2583 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2584{
2585 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2586 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2587 struct drm_crtc *c;
2588 struct intel_crtc *i;
2ff8fde1 2589 struct drm_i915_gem_object *obj;
88595ac9 2590 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2591 struct drm_plane_state *plane_state = primary->state;
88595ac9 2592 struct drm_framebuffer *fb;
484b41dd 2593
2d14030b 2594 if (!plane_config->fb)
484b41dd
JB		 2595 return;
2596
f6936e29 2597 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2598 fb = &plane_config->fb->base;
2599 goto valid_fb;
f55548b5 2600 }
484b41dd 2601
2d14030b 2602 kfree(plane_config->fb);
484b41dd
JB		 2603
2604 /*
2605 * Failed to alloc the obj, check to see if we should share
2606 * an fb with another CRTC instead
2607 */
70e1e0ec 2608 for_each_crtc(dev, c) {
484b41dd
JB		 2609 i = to_intel_crtc(c);
2610
2611 if (c == &intel_crtc->base)
2612 continue;
2613
2ff8fde1
MR		 2614 if (!i->active)
2615 continue;
2616
88595ac9
DV		 2617 fb = c->primary->fb;
2618 if (!fb)
484b41dd
JB		 2619 continue;
2620
88595ac9 2621 obj = intel_fb_obj(fb);
2ff8fde1 2622 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2623 drm_framebuffer_reference(fb);
2624 goto valid_fb;
484b41dd
JB		 2625 }
2626 }
88595ac9
DV		 2627
2628 return;
2629
2630valid_fb:
be5651f2
ML		 2631 plane_state->src_x = plane_state->src_y = 0;
2632 plane_state->src_w = fb->width << 16;
2633 plane_state->src_h = fb->height << 16;
2634
2635 plane_state->crtc_x = plane_state->src_y = 0;
2636 plane_state->crtc_w = fb->width;
2637 plane_state->crtc_h = fb->height;
2638
88595ac9
DV		 2639 obj = intel_fb_obj(fb);
2640 if (obj->tiling_mode != I915_TILING_NONE)
2641 dev_priv->preserve_bios_swizzle = true;
2642
be5651f2
ML		 2643 drm_framebuffer_reference(fb);
2644 primary->fb = primary->state->fb = fb;
36750f28 2645 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2646 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2647 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2648}
2649
29b9bde6
DV		 2650static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2651 struct drm_framebuffer *fb,
2652 int x, int y)
81255565
JB		 2653{
2654 struct drm_device *dev = crtc->dev;
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2657 struct drm_plane *primary = crtc->primary;
2658 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2659 struct drm_i915_gem_object *obj;
81255565 2660 int plane = intel_crtc->plane;
e506a0c6 2661 unsigned long linear_offset;
81255565 2662 u32 dspcntr;
f45651ba 2663 u32 reg = DSPCNTR(plane);
48404c1e 2664 int pixel_size;
f45651ba 2665
b70709a6 2666 if (!visible || !fb) {
fdd508a6
VS		 2667 I915_WRITE(reg, 0);
2668 if (INTEL_INFO(dev)->gen >= 4)
2669 I915_WRITE(DSPSURF(plane), 0);
2670 else
2671 I915_WRITE(DSPADDR(plane), 0);
2672 POSTING_READ(reg);
2673 return;
2674 }
2675
c9ba6fad
VS		 2676 obj = intel_fb_obj(fb);
2677 if (WARN_ON(obj == NULL))
2678 return;
2679
2680 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2681
f45651ba
VS		 2682 dspcntr = DISPPLANE_GAMMA_ENABLE;
2683
fdd508a6 2684 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2685
2686 if (INTEL_INFO(dev)->gen < 4) {
2687 if (intel_crtc->pipe == PIPE_B)
2688 dspcntr |= DISPPLANE_SEL_PIPE_B;
2689
2690 /* pipesrc and dspsize control the size that is scaled from,
2691 * which should always be the user's requested size.
2692 */
2693 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2694 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2695 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2696 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2697 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2698 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2699 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2700 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2701 I915_WRITE(PRIMPOS(plane), 0);
2702 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2703 }
81255565 2704
57779d06
VS		 2705 switch (fb->pixel_format) {
2706 case DRM_FORMAT_C8:
81255565
JB		 2707 dspcntr |= DISPPLANE_8BPP;
2708 break;
57779d06 2709 case DRM_FORMAT_XRGB1555:
57779d06 2710 dspcntr |= DISPPLANE_BGRX555;
81255565 2711 break;
57779d06
VS		 2712 case DRM_FORMAT_RGB565:
2713 dspcntr |= DISPPLANE_BGRX565;
2714 break;
2715 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2716 dspcntr |= DISPPLANE_BGRX888;
2717 break;
2718 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2719 dspcntr |= DISPPLANE_RGBX888;
2720 break;
2721 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2722 dspcntr |= DISPPLANE_BGRX101010;
2723 break;
2724 case DRM_FORMAT_XBGR2101010:
57779d06 2725 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2726 break;
2727 default:
baba133a 2728 BUG();
81255565 2729 }
57779d06 2730
f45651ba
VS		 2731 if (INTEL_INFO(dev)->gen >= 4 &&
2732 obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
81255565 2734
de1aa629
VS		 2735 if (IS_G4X(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
b9897127 2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2739
c2c75131
DV		 2740 if (INTEL_INFO(dev)->gen >= 4) {
2741 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2742 intel_gen4_compute_page_offset(dev_priv,
2743 &x, &y, obj->tiling_mode,
b9897127 2744 pixel_size,
bc752862 2745 fb->pitches[0]);
c2c75131
DV		 2746 linear_offset -= intel_crtc->dspaddr_offset;
2747 } else {
e506a0c6 2748 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2749 }
e506a0c6 2750
8e7d688b 2751 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2752 dspcntr |= DISPPLANE_ROTATE_180;
2753
6e3c9717
ACO		 2754 x += (intel_crtc->config->pipe_src_w - 1);
2755 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2756
2757 /* Finding the last pixel of the last line of the display
2758 data and adding to linear_offset*/
2759 linear_offset +=
6e3c9717
ACO		 2760 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2761 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2762 }
2763
2db3366b
PZ		 2764 intel_crtc->adjusted_x = x;
2765 intel_crtc->adjusted_y = y;
2766
48404c1e
SJ		 2767 I915_WRITE(reg, dspcntr);
2768
01f2c773 2769 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2770 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2771 I915_WRITE(DSPSURF(plane),
2772 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2773 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2774 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2775 } else
f343c5f6 2776 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2777 POSTING_READ(reg);
17638cd6
JB		 2778}
2779
29b9bde6
DV		 2780static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2781 struct drm_framebuffer *fb,
2782 int x, int y)
17638cd6
JB		 2783{
2784 struct drm_device *dev = crtc->dev;
2785 struct drm_i915_private *dev_priv = dev->dev_private;
2786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2787 struct drm_plane *primary = crtc->primary;
2788 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2789 struct drm_i915_gem_object *obj;
17638cd6 2790 int plane = intel_crtc->plane;
e506a0c6 2791 unsigned long linear_offset;
17638cd6 2792 u32 dspcntr;
f45651ba 2793 u32 reg = DSPCNTR(plane);
48404c1e 2794 int pixel_size;
f45651ba 2795
b70709a6 2796 if (!visible || !fb) {
fdd508a6
VS		 2797 I915_WRITE(reg, 0);
2798 I915_WRITE(DSPSURF(plane), 0);
2799 POSTING_READ(reg);
2800 return;
2801 }
2802
c9ba6fad
VS		 2803 obj = intel_fb_obj(fb);
2804 if (WARN_ON(obj == NULL))
2805 return;
2806
2807 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2808
f45651ba
VS		 2809 dspcntr = DISPPLANE_GAMMA_ENABLE;
2810
fdd508a6 2811 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2812
2813 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2814 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2815
57779d06
VS		 2816 switch (fb->pixel_format) {
2817 case DRM_FORMAT_C8:
17638cd6
JB		 2818 dspcntr |= DISPPLANE_8BPP;
2819 break;
57779d06
VS		 2820 case DRM_FORMAT_RGB565:
2821 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2822 break;
57779d06 2823 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2824 dspcntr |= DISPPLANE_BGRX888;
2825 break;
2826 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2827 dspcntr |= DISPPLANE_RGBX888;
2828 break;
2829 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2830 dspcntr |= DISPPLANE_BGRX101010;
2831 break;
2832 case DRM_FORMAT_XBGR2101010:
57779d06 2833 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2834 break;
2835 default:
baba133a 2836 BUG();
17638cd6
JB		 2837 }
2838
2839 if (obj->tiling_mode != I915_TILING_NONE)
2840 dspcntr |= DISPPLANE_TILED;
17638cd6 2841
f45651ba 2842 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2843 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2844
b9897127 2845 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2846 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2847 intel_gen4_compute_page_offset(dev_priv,
2848 &x, &y, obj->tiling_mode,
b9897127 2849 pixel_size,
bc752862 2850 fb->pitches[0]);
c2c75131 2851 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2852 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2853 dspcntr |= DISPPLANE_ROTATE_180;
2854
2855 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2856 x += (intel_crtc->config->pipe_src_w - 1);
2857 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2858
2859 /* Finding the last pixel of the last line of the display
2860 data and adding to linear_offset*/
2861 linear_offset +=
6e3c9717
ACO		 2862 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2863 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2864 }
2865 }
2866
2db3366b
PZ		 2867 intel_crtc->adjusted_x = x;
2868 intel_crtc->adjusted_y = y;
2869
48404c1e 2870 I915_WRITE(reg, dspcntr);
17638cd6 2871
01f2c773 2872 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2873 I915_WRITE(DSPSURF(plane),
2874 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2875 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2876 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2877 } else {
2878 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2879 I915_WRITE(DSPLINOFF(plane), linear_offset);
2880 }
17638cd6 2881 POSTING_READ(reg);
17638cd6
JB		 2882}
2883
b321803d
DL		 2884u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2885 uint32_t pixel_format)
2886{
2887 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2888
2889 /*
2890 * The stride is either expressed as a multiple of 64 bytes
2891 * chunks for linear buffers or in number of tiles for tiled
2892 * buffers.
2893 */
2894 switch (fb_modifier) {
2895 case DRM_FORMAT_MOD_NONE:
2896 return 64;
2897 case I915_FORMAT_MOD_X_TILED:
2898 if (INTEL_INFO(dev)->gen == 2)
2899 return 128;
2900 return 512;
2901 case I915_FORMAT_MOD_Y_TILED:
2902 /* No need to check for old gens and Y tiling since this is
2903 * about the display engine and those will be blocked before
2904 * we get here.
2905 */
2906 return 128;
2907 case I915_FORMAT_MOD_Yf_TILED:
2908 if (bits_per_pixel == 8)
2909 return 64;
2910 else
2911 return 128;
2912 default:
2913 MISSING_CASE(fb_modifier);
2914 return 64;
2915 }
2916}
2917
121920fa 2918unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
dedf278c
TU		 2919 struct drm_i915_gem_object *obj,
2920 unsigned int plane)
121920fa 2921{
9abc4648 2922 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
dedf278c
TU		 2923 struct i915_vma *vma;
2924 unsigned char *offset;
121920fa
TU		 2925
2926 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2927 view = &i915_ggtt_view_rotated;
121920fa 2928
dedf278c
TU		 2929 vma = i915_gem_obj_to_ggtt_view(obj, view);
2930 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2931 view->type))
2932 return -1;
2933
2934 offset = (unsigned char *)vma->node.start;
2935
2936 if (plane == 1) {
2937 offset += vma->ggtt_view.rotation_info.uv_start_page *
2938 PAGE_SIZE;
2939 }
2940
2941 return (unsigned long)offset;
121920fa
TU		 2942}
2943
e435d6e5
ML		 2944static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2945{
2946 struct drm_device *dev = intel_crtc->base.dev;
2947 struct drm_i915_private *dev_priv = dev->dev_private;
2948
2949 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2950 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2951 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2952}
2953
a1b2278e
CK		 2954/*
2955 * This function detaches (aka. unbinds) unused scalers in hardware
2956 */
0583236e 2957static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2958{
a1b2278e
CK		 2959 struct intel_crtc_scaler_state *scaler_state;
2960 int i;
2961
a1b2278e
CK		 2962 scaler_state = &intel_crtc->config->scaler_state;
2963
2964 /* loop through and disable scalers that aren't in use */
2965 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2966 if (!scaler_state->scalers[i].in_use)
2967 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2968 }
2969}
2970
6156a456 2971u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2972{
6156a456 2973 switch (pixel_format) {
d161cf7a 2974 case DRM_FORMAT_C8:
c34ce3d1 2975 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2976 case DRM_FORMAT_RGB565:
c34ce3d1 2977 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2978 case DRM_FORMAT_XBGR8888:
c34ce3d1 2979 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2980 case DRM_FORMAT_XRGB8888:
c34ce3d1 2981 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2982 /*
2983 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2984 * to be already pre-multiplied. We need to add a knob (or a different
2985 * DRM_FORMAT) for user-space to configure that.
2986 */
f75fb42a 2987 case DRM_FORMAT_ABGR8888:
c34ce3d1 2988 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2989 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2990 case DRM_FORMAT_ARGB8888:
c34ce3d1 2991 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2992 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2993 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2994 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2995 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2996 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2997 case DRM_FORMAT_YUYV:
c34ce3d1 2998 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2999 case DRM_FORMAT_YVYU:
c34ce3d1 3000 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 3001 case DRM_FORMAT_UYVY:
c34ce3d1 3002 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 3003 case DRM_FORMAT_VYUY:
c34ce3d1 3004 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 3005 default:
4249eeef 3006 MISSING_CASE(pixel_format);
70d21f0e 3007 }
8cfcba41 3008
c34ce3d1 3009 return 0;
6156a456 3010}
70d21f0e 3011
6156a456
CK		 3012u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3013{
6156a456 3014 switch (fb_modifier) {
30af77c4 3015 case DRM_FORMAT_MOD_NONE:
70d21f0e 3016 break;
30af77c4 3017 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3018 return PLANE_CTL_TILED_X;
b321803d 3019 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3020 return PLANE_CTL_TILED_Y;
b321803d 3021 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3022 return PLANE_CTL_TILED_YF;
70d21f0e 3023 default:
6156a456 3024 MISSING_CASE(fb_modifier);
70d21f0e 3025 }
8cfcba41 3026
c34ce3d1 3027 return 0;
6156a456 3028}
70d21f0e 3029
6156a456
CK		 3030u32 skl_plane_ctl_rotation(unsigned int rotation)
3031{
3b7a5119 3032 switch (rotation) {
6156a456
CK		 3033 case BIT(DRM_ROTATE_0):
3034 break;
1e8df167
SJ		 3035 /*
3036 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3037 * while i915 HW rotation is clockwise, thats why this swapping.
3038 */
3b7a5119 3039 case BIT(DRM_ROTATE_90):
1e8df167 3040 return PLANE_CTL_ROTATE_270;
3b7a5119 3041 case BIT(DRM_ROTATE_180):
c34ce3d1 3042 return PLANE_CTL_ROTATE_180;
3b7a5119 3043 case BIT(DRM_ROTATE_270):
1e8df167 3044 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3045 default:
3046 MISSING_CASE(rotation);
3047 }
3048
c34ce3d1 3049 return 0;
6156a456
CK		 3050}
3051
3052static void skylake_update_primary_plane(struct drm_crtc *crtc,
3053 struct drm_framebuffer *fb,
3054 int x, int y)
3055{
3056 struct drm_device *dev = crtc->dev;
3057 struct drm_i915_private *dev_priv = dev->dev_private;
3058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3059 struct drm_plane *plane = crtc->primary;
3060 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3061 struct drm_i915_gem_object *obj;
3062 int pipe = intel_crtc->pipe;
3063 u32 plane_ctl, stride_div, stride;
3064 u32 tile_height, plane_offset, plane_size;
3065 unsigned int rotation;
3066 int x_offset, y_offset;
3067 unsigned long surf_addr;
6156a456
CK		 3068 struct intel_crtc_state *crtc_state = intel_crtc->config;
3069 struct intel_plane_state *plane_state;
3070 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3071 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3072 int scaler_id = -1;
3073
6156a456
CK		 3074 plane_state = to_intel_plane_state(plane->state);
3075
b70709a6 3076 if (!visible || !fb) {
6156a456
CK		 3077 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3078 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3079 POSTING_READ(PLANE_CTL(pipe, 0));
3080 return;
3b7a5119 3081 }
70d21f0e 3082
6156a456
CK		 3083 plane_ctl = PLANE_CTL_ENABLE |
3084 PLANE_CTL_PIPE_GAMMA_ENABLE |
3085 PLANE_CTL_PIPE_CSC_ENABLE;
3086
3087 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3088 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3089 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3090
3091 rotation = plane->state->rotation;
3092 plane_ctl |= skl_plane_ctl_rotation(rotation);
3093
b321803d
DL		 3094 obj = intel_fb_obj(fb);
3095 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3096 fb->pixel_format);
dedf278c 3097 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3b7a5119 3098
a42e5a23
PZ		 3099 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3100
3101 scaler_id = plane_state->scaler_id;
3102 src_x = plane_state->src.x1 >> 16;
3103 src_y = plane_state->src.y1 >> 16;
3104 src_w = drm_rect_width(&plane_state->src) >> 16;
3105 src_h = drm_rect_height(&plane_state->src) >> 16;
3106 dst_x = plane_state->dst.x1;
3107 dst_y = plane_state->dst.y1;
3108 dst_w = drm_rect_width(&plane_state->dst);
3109 dst_h = drm_rect_height(&plane_state->dst);
3110
3111 WARN_ON(x != src_x || y != src_y);
6156a456 3112
3b7a5119
SJ		 3113 if (intel_rotation_90_or_270(rotation)) {
3114 /* stride = Surface height in tiles */
2614f17d 3115 tile_height = intel_tile_height(dev, fb->pixel_format,
fe47ea0c 3116 fb->modifier[0], 0);
3b7a5119 3117 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3118 x_offset = stride * tile_height - y - src_h;
3b7a5119 3119 y_offset = x;
6156a456 3120 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3121 } else {
3122 stride = fb->pitches[0] / stride_div;
3123 x_offset = x;
3124 y_offset = y;
6156a456 3125 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3126 }
3127 plane_offset = y_offset << 16 | x_offset;
b321803d 3128
2db3366b
PZ		 3129 intel_crtc->adjusted_x = x_offset;
3130 intel_crtc->adjusted_y = y_offset;
3131
70d21f0e 3132 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3133 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3134 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3135 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3136
3137 if (scaler_id >= 0) {
3138 uint32_t ps_ctrl = 0;
3139
3140 WARN_ON(!dst_w || !dst_h);
3141 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3142 crtc_state->scaler_state.scalers[scaler_id].mode;
3143 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3144 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3145 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3146 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3147 I915_WRITE(PLANE_POS(pipe, 0), 0);
3148 } else {
3149 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3150 }
3151
121920fa 3152 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3153
3154 POSTING_READ(PLANE_SURF(pipe, 0));
3155}
3156
17638cd6
JB		 3157/* Assume fb object is pinned & idle & fenced and just update base pointers */
3158static int
3159intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3160 int x, int y, enum mode_set_atomic state)
3161{
3162 struct drm_device *dev = crtc->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3164
ff2a3117 3165 if (dev_priv->fbc.disable_fbc)
7733b49b 3166 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3167
29b9bde6
DV		 3168 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3169
3170 return 0;
81255565
JB		 3171}
3172
7514747d 3173static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3174{
96a02917
VS		 3175 struct drm_crtc *crtc;
3176
70e1e0ec 3177 for_each_crtc(dev, crtc) {
96a02917
VS		 3178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3179 enum plane plane = intel_crtc->plane;
3180
3181 intel_prepare_page_flip(dev, plane);
3182 intel_finish_page_flip_plane(dev, plane);
3183 }
7514747d
VS		 3184}
3185
3186static void intel_update_primary_planes(struct drm_device *dev)
3187{
7514747d 3188 struct drm_crtc *crtc;
96a02917 3189
70e1e0ec 3190 for_each_crtc(dev, crtc) {
11c22da6
ML		 3191 struct intel_plane *plane = to_intel_plane(crtc->primary);
3192 struct intel_plane_state *plane_state;
96a02917 3193
11c22da6 3194 drm_modeset_lock_crtc(crtc, &plane->base);
11c22da6
ML		 3195 plane_state = to_intel_plane_state(plane->base.state);
3196
f029ee82 3197 if (crtc->state->active && plane_state->base.fb)
11c22da6
ML		 3198 plane->commit_plane(&plane->base, plane_state);
3199
3200 drm_modeset_unlock_crtc(crtc);
96a02917
VS		 3201 }
3202}
3203
7514747d
VS		 3204void intel_prepare_reset(struct drm_device *dev)
3205{
3206 /* no reset support for gen2 */
3207 if (IS_GEN2(dev))
3208 return;
3209
3210 /* reset doesn't touch the display */
3211 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3212 return;
3213
3214 drm_modeset_lock_all(dev);
f98ce92f
VS		 3215 /*
3216 * Disabling the crtcs gracefully seems nicer. Also the
3217 * g33 docs say we should at least disable all the planes.
3218 */
6b72d486 3219 intel_display_suspend(dev);
7514747d
VS		 3220}
3221
3222void intel_finish_reset(struct drm_device *dev)
3223{
3224 struct drm_i915_private *dev_priv = to_i915(dev);
3225
3226 /*
3227 * Flips in the rings will be nuked by the reset,
3228 * so complete all pending flips so that user space
3229 * will get its events and not get stuck.
3230 */
3231 intel_complete_page_flips(dev);
3232
3233 /* no reset support for gen2 */
3234 if (IS_GEN2(dev))
3235 return;
3236
3237 /* reset doesn't touch the display */
3238 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3239 /*
3240 * Flips in the rings have been nuked by the reset,
3241 * so update the base address of all primary
3242 * planes to the the last fb to make sure we're
3243 * showing the correct fb after a reset.
11c22da6
ML		 3244 *
3245 * FIXME: Atomic will make this obsolete since we won't schedule
3246 * CS-based flips (which might get lost in gpu resets) any more.
7514747d
VS		 3247 */
3248 intel_update_primary_planes(dev);
3249 return;
3250 }
3251
3252 /*
3253 * The display has been reset as well,
3254 * so need a full re-initialization.
3255 */
3256 intel_runtime_pm_disable_interrupts(dev_priv);
3257 intel_runtime_pm_enable_interrupts(dev_priv);
3258
3259 intel_modeset_init_hw(dev);
3260
3261 spin_lock_irq(&dev_priv->irq_lock);
3262 if (dev_priv->display.hpd_irq_setup)
3263 dev_priv->display.hpd_irq_setup(dev);
3264 spin_unlock_irq(&dev_priv->irq_lock);
3265
043e9bda 3266 intel_display_resume(dev);
7514747d
VS		 3267
3268 intel_hpd_init(dev_priv);
3269
3270 drm_modeset_unlock_all(dev);
3271}
3272
7d5e3799
CW		 3273static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3274{
3275 struct drm_device *dev = crtc->dev;
3276 struct drm_i915_private *dev_priv = dev->dev_private;
3277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3278 bool pending;
3279
3280 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3281 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3282 return false;
3283
5e2d7afc 3284 spin_lock_irq(&dev->event_lock);
7d5e3799 3285 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3286 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3287
3288 return pending;
3289}
3290
bfd16b2a
ML		 3291static void intel_update_pipe_config(struct intel_crtc *crtc,
3292 struct intel_crtc_state *old_crtc_state)
e30e8f75
GP		 3293{
3294 struct drm_device *dev = crtc->base.dev;
3295 struct drm_i915_private *dev_priv = dev->dev_private;
bfd16b2a
ML		 3296 struct intel_crtc_state *pipe_config =
3297 to_intel_crtc_state(crtc->base.state);
e30e8f75 3298
bfd16b2a
ML		 3299 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3300 crtc->base.mode = crtc->base.state->mode;
3301
3302 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3303 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3304 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
e30e8f75 3305
44522d85
ML		 3306 if (HAS_DDI(dev))
3307 intel_set_pipe_csc(&crtc->base);
3308
e30e8f75
GP		 3309 /*
3310 * Update pipe size and adjust fitter if needed: the reason for this is
3311 * that in compute_mode_changes we check the native mode (not the pfit
3312 * mode) to see if we can flip rather than do a full mode set. In the
3313 * fastboot case, we'll flip, but if we don't update the pipesrc and
3314 * pfit state, we'll end up with a big fb scanned out into the wrong
3315 * sized surface.
e30e8f75
GP		 3316 */
3317
e30e8f75 3318 I915_WRITE(PIPESRC(crtc->pipe),
bfd16b2a
ML		 3319 ((pipe_config->pipe_src_w - 1) << 16) |
3320 (pipe_config->pipe_src_h - 1));
3321
3322 /* on skylake this is done by detaching scalers */
3323 if (INTEL_INFO(dev)->gen >= 9) {
3324 skl_detach_scalers(crtc);
3325
3326 if (pipe_config->pch_pfit.enabled)
3327 skylake_pfit_enable(crtc);
3328 } else if (HAS_PCH_SPLIT(dev)) {
3329 if (pipe_config->pch_pfit.enabled)
3330 ironlake_pfit_enable(crtc);
3331 else if (old_crtc_state->pch_pfit.enabled)
3332 ironlake_pfit_disable(crtc, true);
e30e8f75 3333 }
e30e8f75
GP		 3334}
3335
5e84e1a4
ZW		 3336static void intel_fdi_normal_train(struct drm_crtc *crtc)
3337{
3338 struct drm_device *dev = crtc->dev;
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3341 int pipe = intel_crtc->pipe;
3342 u32 reg, temp;
3343
3344 /* enable normal train */
3345 reg = FDI_TX_CTL(pipe);
3346 temp = I915_READ(reg);
61e499bf 3347 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3348 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3350 } else {
3351 temp &= ~FDI_LINK_TRAIN_NONE;
3352 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3353 }
5e84e1a4
ZW		 3354 I915_WRITE(reg, temp);
3355
3356 reg = FDI_RX_CTL(pipe);
3357 temp = I915_READ(reg);
3358 if (HAS_PCH_CPT(dev)) {
3359 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3360 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3361 } else {
3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_NONE;
3364 }
3365 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3366
3367 /* wait one idle pattern time */
3368 POSTING_READ(reg);
3369 udelay(1000);
357555c0
JB		 3370
3371 /* IVB wants error correction enabled */
3372 if (IS_IVYBRIDGE(dev))
3373 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3374 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3375}
3376
8db9d77b
ZW		 3377/* The FDI link training functions for ILK/Ibexpeak. */
3378static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3379{
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383 int pipe = intel_crtc->pipe;
5eddb70b 3384 u32 reg, temp, tries;
8db9d77b 3385
1c8562f6 3386 /* FDI needs bits from pipe first */
0fc932b8 3387 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3388
e1a44743
AJ		 3389 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3390 for train result */
5eddb70b
CW		 3391 reg = FDI_RX_IMR(pipe);
3392 temp = I915_READ(reg);
e1a44743
AJ		 3393 temp &= ~FDI_RX_SYMBOL_LOCK;
3394 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3395 I915_WRITE(reg, temp);
3396 I915_READ(reg);
e1a44743
AJ		 3397 udelay(150);
3398
8db9d77b 3399 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3400 reg = FDI_TX_CTL(pipe);
3401 temp = I915_READ(reg);
627eb5a3 3402 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3403 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3406 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3407
5eddb70b
CW		 3408 reg = FDI_RX_CTL(pipe);
3409 temp = I915_READ(reg);
8db9d77b
ZW		 3410 temp &= ~FDI_LINK_TRAIN_NONE;
3411 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3412 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3413
3414 POSTING_READ(reg);
8db9d77b
ZW		 3415 udelay(150);
3416
5b2adf89 3417 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3418 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3419 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3420 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3421
5eddb70b 3422 reg = FDI_RX_IIR(pipe);
e1a44743 3423 for (tries = 0; tries < 5; tries++) {
5eddb70b 3424 temp = I915_READ(reg);
8db9d77b
ZW		 3425 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3426
3427 if ((temp & FDI_RX_BIT_LOCK)) {
3428 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3429 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3430 break;
3431 }
8db9d77b 3432 }
e1a44743 3433 if (tries == 5)
5eddb70b 3434 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3435
3436 /* Train 2 */
5eddb70b
CW		 3437 reg = FDI_TX_CTL(pipe);
3438 temp = I915_READ(reg);
8db9d77b
ZW		 3439 temp &= ~FDI_LINK_TRAIN_NONE;
3440 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3441 I915_WRITE(reg, temp);
8db9d77b 3442
5eddb70b
CW		 3443 reg = FDI_RX_CTL(pipe);
3444 temp = I915_READ(reg);
8db9d77b
ZW		 3445 temp &= ~FDI_LINK_TRAIN_NONE;
3446 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3447 I915_WRITE(reg, temp);
8db9d77b 3448
5eddb70b
CW		 3449 POSTING_READ(reg);
3450 udelay(150);
8db9d77b 3451
5eddb70b 3452 reg = FDI_RX_IIR(pipe);
e1a44743 3453 for (tries = 0; tries < 5; tries++) {
5eddb70b 3454 temp = I915_READ(reg);
8db9d77b
ZW		 3455 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3456
3457 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3458 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3459 DRM_DEBUG_KMS("FDI train 2 done.\n");
3460 break;
3461 }
8db9d77b 3462 }
e1a44743 3463 if (tries == 5)
5eddb70b 3464 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3465
3466 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3467
8db9d77b
ZW		 3468}
3469
0206e353 3470static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3471 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3472 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3473 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3474 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3475};
3476
3477/* The FDI link training functions for SNB/Cougarpoint. */
3478static void gen6_fdi_link_train(struct drm_crtc *crtc)
3479{
3480 struct drm_device *dev = crtc->dev;
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3483 int pipe = intel_crtc->pipe;
fa37d39e 3484 u32 reg, temp, i, retry;
8db9d77b 3485
e1a44743
AJ		 3486 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3487 for train result */
5eddb70b
CW		 3488 reg = FDI_RX_IMR(pipe);
3489 temp = I915_READ(reg);
e1a44743
AJ		 3490 temp &= ~FDI_RX_SYMBOL_LOCK;
3491 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3492 I915_WRITE(reg, temp);
3493
3494 POSTING_READ(reg);
e1a44743
AJ		 3495 udelay(150);
3496
8db9d77b 3497 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3498 reg = FDI_TX_CTL(pipe);
3499 temp = I915_READ(reg);
627eb5a3 3500 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3501 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3502 temp &= ~FDI_LINK_TRAIN_NONE;
3503 temp |= FDI_LINK_TRAIN_PATTERN_1;
3504 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3505 /* SNB-B */
3506 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3507 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3508
d74cf324
DV		 3509 I915_WRITE(FDI_RX_MISC(pipe),
3510 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3511
5eddb70b
CW		 3512 reg = FDI_RX_CTL(pipe);
3513 temp = I915_READ(reg);
8db9d77b
ZW		 3514 if (HAS_PCH_CPT(dev)) {
3515 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3516 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3517 } else {
3518 temp &= ~FDI_LINK_TRAIN_NONE;
3519 temp |= FDI_LINK_TRAIN_PATTERN_1;
3520 }
5eddb70b
CW		 3521 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3522
3523 POSTING_READ(reg);
8db9d77b
ZW		 3524 udelay(150);
3525
0206e353 3526 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3527 reg = FDI_TX_CTL(pipe);
3528 temp = I915_READ(reg);
8db9d77b
ZW		 3529 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3530 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3531 I915_WRITE(reg, temp);
3532
3533 POSTING_READ(reg);
8db9d77b
ZW		 3534 udelay(500);
3535
fa37d39e
SP		 3536 for (retry = 0; retry < 5; retry++) {
3537 reg = FDI_RX_IIR(pipe);
3538 temp = I915_READ(reg);
3539 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3540 if (temp & FDI_RX_BIT_LOCK) {
3541 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3542 DRM_DEBUG_KMS("FDI train 1 done.\n");
3543 break;
3544 }
3545 udelay(50);
8db9d77b 3546 }
fa37d39e
SP		 3547 if (retry < 5)
3548 break;
8db9d77b
ZW		 3549 }
3550 if (i == 4)
5eddb70b 3551 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3552
3553 /* Train 2 */
5eddb70b
CW		 3554 reg = FDI_TX_CTL(pipe);
3555 temp = I915_READ(reg);
8db9d77b
ZW		 3556 temp &= ~FDI_LINK_TRAIN_NONE;
3557 temp |= FDI_LINK_TRAIN_PATTERN_2;
3558 if (IS_GEN6(dev)) {
3559 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3560 /* SNB-B */
3561 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3562 }
5eddb70b 3563 I915_WRITE(reg, temp);
8db9d77b 3564
5eddb70b
CW		 3565 reg = FDI_RX_CTL(pipe);
3566 temp = I915_READ(reg);
8db9d77b
ZW		 3567 if (HAS_PCH_CPT(dev)) {
3568 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3569 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3570 } else {
3571 temp &= ~FDI_LINK_TRAIN_NONE;
3572 temp |= FDI_LINK_TRAIN_PATTERN_2;
3573 }
5eddb70b
CW		 3574 I915_WRITE(reg, temp);
3575
3576 POSTING_READ(reg);
8db9d77b
ZW		 3577 udelay(150);
3578
0206e353 3579 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3580 reg = FDI_TX_CTL(pipe);
3581 temp = I915_READ(reg);
8db9d77b
ZW		 3582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3583 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3584 I915_WRITE(reg, temp);
3585
3586 POSTING_READ(reg);
8db9d77b
ZW		 3587 udelay(500);
3588
fa37d39e
SP		 3589 for (retry = 0; retry < 5; retry++) {
3590 reg = FDI_RX_IIR(pipe);
3591 temp = I915_READ(reg);
3592 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3593 if (temp & FDI_RX_SYMBOL_LOCK) {
3594 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3595 DRM_DEBUG_KMS("FDI train 2 done.\n");
3596 break;
3597 }
3598 udelay(50);
8db9d77b 3599 }
fa37d39e
SP		 3600 if (retry < 5)
3601 break;
8db9d77b
ZW		 3602 }
3603 if (i == 4)
5eddb70b 3604 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3605
3606 DRM_DEBUG_KMS("FDI train done.\n");
3607}
3608
357555c0
JB		 3609/* Manual link training for Ivy Bridge A0 parts */
3610static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3611{
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615 int pipe = intel_crtc->pipe;
139ccd3f 3616 u32 reg, temp, i, j;
357555c0
JB		 3617
3618 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3619 for train result */
3620 reg = FDI_RX_IMR(pipe);
3621 temp = I915_READ(reg);
3622 temp &= ~FDI_RX_SYMBOL_LOCK;
3623 temp &= ~FDI_RX_BIT_LOCK;
3624 I915_WRITE(reg, temp);
3625
3626 POSTING_READ(reg);
3627 udelay(150);
3628
01a415fd
DV		 3629 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3630 I915_READ(FDI_RX_IIR(pipe)));
3631
139ccd3f
JB		 3632 /* Try each vswing and preemphasis setting twice before moving on */
3633 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3634 /* disable first in case we need to retry */
3635 reg = FDI_TX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3638 temp &= ~FDI_TX_ENABLE;
3639 I915_WRITE(reg, temp);
357555c0 3640
139ccd3f
JB		 3641 reg = FDI_RX_CTL(pipe);
3642 temp = I915_READ(reg);
3643 temp &= ~FDI_LINK_TRAIN_AUTO;
3644 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3645 temp &= ~FDI_RX_ENABLE;
3646 I915_WRITE(reg, temp);
357555c0 3647
139ccd3f 3648 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
139ccd3f 3651 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3652 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3653 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3654 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3655 temp |= snb_b_fdi_train_param[j/2];
3656 temp |= FDI_COMPOSITE_SYNC;
3657 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3658
139ccd3f
JB		 3659 I915_WRITE(FDI_RX_MISC(pipe),
3660 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3661
139ccd3f 3662 reg = FDI_RX_CTL(pipe);
357555c0 3663 temp = I915_READ(reg);
139ccd3f
JB		 3664 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3665 temp |= FDI_COMPOSITE_SYNC;
3666 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3667
139ccd3f
JB		 3668 POSTING_READ(reg);
3669 udelay(1); /* should be 0.5us */
357555c0 3670
139ccd3f
JB		 3671 for (i = 0; i < 4; i++) {
3672 reg = FDI_RX_IIR(pipe);
3673 temp = I915_READ(reg);
3674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3675
139ccd3f
JB		 3676 if (temp & FDI_RX_BIT_LOCK ||
3677 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3678 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3679 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3680 i);
3681 break;
3682 }
3683 udelay(1); /* should be 0.5us */
3684 }
3685 if (i == 4) {
3686 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3687 continue;
3688 }
357555c0 3689
139ccd3f 3690 /* Train 2 */
357555c0
JB		 3691 reg = FDI_TX_CTL(pipe);
3692 temp = I915_READ(reg);
139ccd3f
JB		 3693 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3694 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3695 I915_WRITE(reg, temp);
3696
3697 reg = FDI_RX_CTL(pipe);
3698 temp = I915_READ(reg);
3699 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3700 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3701 I915_WRITE(reg, temp);
3702
3703 POSTING_READ(reg);
139ccd3f 3704 udelay(2); /* should be 1.5us */
357555c0 3705
139ccd3f
JB		 3706 for (i = 0; i < 4; i++) {
3707 reg = FDI_RX_IIR(pipe);
3708 temp = I915_READ(reg);
3709 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3710
139ccd3f
JB		 3711 if (temp & FDI_RX_SYMBOL_LOCK ||
3712 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3713 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3714 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3715 i);
3716 goto train_done;
3717 }
3718 udelay(2); /* should be 1.5us */
357555c0 3719 }
139ccd3f
JB		 3720 if (i == 4)
3721 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3722 }
357555c0 3723
139ccd3f 3724train_done:
357555c0
JB		 3725 DRM_DEBUG_KMS("FDI train done.\n");
3726}
3727
88cefb6c 3728static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3729{
88cefb6c 3730 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3731 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3732 int pipe = intel_crtc->pipe;
5eddb70b 3733 u32 reg, temp;
79e53945 3734
c64e311e 3735
c98e9dcf 3736 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3737 reg = FDI_RX_CTL(pipe);
3738 temp = I915_READ(reg);
627eb5a3 3739 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3740 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3741 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3742 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3743
3744 POSTING_READ(reg);
c98e9dcf
JB		 3745 udelay(200);
3746
3747 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3748 temp = I915_READ(reg);
3749 I915_WRITE(reg, temp | FDI_PCDCLK);
3750
3751 POSTING_READ(reg);
c98e9dcf
JB		 3752 udelay(200);
3753
20749730
PZ		 3754 /* Enable CPU FDI TX PLL, always on for Ironlake */
3755 reg = FDI_TX_CTL(pipe);
3756 temp = I915_READ(reg);
3757 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3758 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3759
20749730
PZ		 3760 POSTING_READ(reg);
3761 udelay(100);
6be4a607 3762 }
0e23b99d
JB		 3763}
3764
88cefb6c
DV		 3765static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3766{
3767 struct drm_device *dev = intel_crtc->base.dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769 int pipe = intel_crtc->pipe;
3770 u32 reg, temp;
3771
3772 /* Switch from PCDclk to Rawclk */
3773 reg = FDI_RX_CTL(pipe);
3774 temp = I915_READ(reg);
3775 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3776
3777 /* Disable CPU FDI TX PLL */
3778 reg = FDI_TX_CTL(pipe);
3779 temp = I915_READ(reg);
3780 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3781
3782 POSTING_READ(reg);
3783 udelay(100);
3784
3785 reg = FDI_RX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3788
3789 /* Wait for the clocks to turn off. */
3790 POSTING_READ(reg);
3791 udelay(100);
3792}
3793
0fc932b8
JB		 3794static void ironlake_fdi_disable(struct drm_crtc *crtc)
3795{
3796 struct drm_device *dev = crtc->dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3799 int pipe = intel_crtc->pipe;
3800 u32 reg, temp;
3801
3802 /* disable CPU FDI tx and PCH FDI rx */
3803 reg = FDI_TX_CTL(pipe);
3804 temp = I915_READ(reg);
3805 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3806 POSTING_READ(reg);
3807
3808 reg = FDI_RX_CTL(pipe);
3809 temp = I915_READ(reg);
3810 temp &= ~(0x7 << 16);
dfd07d72 3811 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3812 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3813
3814 POSTING_READ(reg);
3815 udelay(100);
3816
3817 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3818 if (HAS_PCH_IBX(dev))
6f06ce18 3819 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3820
3821 /* still set train pattern 1 */
3822 reg = FDI_TX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~FDI_LINK_TRAIN_NONE;
3825 temp |= FDI_LINK_TRAIN_PATTERN_1;
3826 I915_WRITE(reg, temp);
3827
3828 reg = FDI_RX_CTL(pipe);
3829 temp = I915_READ(reg);
3830 if (HAS_PCH_CPT(dev)) {
3831 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3832 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3833 } else {
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_1;
3836 }
3837 /* BPC in FDI rx is consistent with that in PIPECONF */
3838 temp &= ~(0x07 << 16);
dfd07d72 3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3840 I915_WRITE(reg, temp);
3841
3842 POSTING_READ(reg);
3843 udelay(100);
3844}
3845
5dce5b93
CW		 3846bool intel_has_pending_fb_unpin(struct drm_device *dev)
3847{
3848 struct intel_crtc *crtc;
3849
3850 /* Note that we don't need to be called with mode_config.lock here
3851 * as our list of CRTC objects is static for the lifetime of the
3852 * device and so cannot disappear as we iterate. Similarly, we can
3853 * happily treat the predicates as racy, atomic checks as userspace
3854 * cannot claim and pin a new fb without at least acquring the
3855 * struct_mutex and so serialising with us.
3856 */
d3fcc808 3857 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3858 if (atomic_read(&crtc->unpin_work_count) == 0)
3859 continue;
3860
3861 if (crtc->unpin_work)
3862 intel_wait_for_vblank(dev, crtc->pipe);
3863
3864 return true;
3865 }
3866
3867 return false;
3868}
3869
d6bbafa1
CW		 3870static void page_flip_completed(struct intel_crtc *intel_crtc)
3871{
3872 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3873 struct intel_unpin_work *work = intel_crtc->unpin_work;
3874
3875 /* ensure that the unpin work is consistent wrt ->pending. */
3876 smp_rmb();
3877 intel_crtc->unpin_work = NULL;
3878
3879 if (work->event)
3880 drm_send_vblank_event(intel_crtc->base.dev,
3881 intel_crtc->pipe,
3882 work->event);
3883
3884 drm_crtc_vblank_put(&intel_crtc->base);
3885
3886 wake_up_all(&dev_priv->pending_flip_queue);
3887 queue_work(dev_priv->wq, &work->work);
3888
3889 trace_i915_flip_complete(intel_crtc->plane,
3890 work->pending_flip_obj);
3891}
3892
5008e874 3893static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3894{
0f91128d 3895 struct drm_device *dev = crtc->dev;
5bb61643 3896 struct drm_i915_private *dev_priv = dev->dev_private;
5008e874 3897 long ret;
e6c3a2a6 3898
2c10d571 3899 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
5008e874
ML		 3900
3901 ret = wait_event_interruptible_timeout(
3902 dev_priv->pending_flip_queue,
3903 !intel_crtc_has_pending_flip(crtc),
3904 60*HZ);
3905
3906 if (ret < 0)
3907 return ret;
3908
3909 if (ret == 0) {
9c787942 3910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3911
5e2d7afc 3912 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3913 if (intel_crtc->unpin_work) {
3914 WARN_ONCE(1, "Removing stuck page flip\n");
3915 page_flip_completed(intel_crtc);
3916 }
5e2d7afc 3917 spin_unlock_irq(&dev->event_lock);
9c787942 3918 }
5bb61643 3919
5008e874 3920 return 0;
e6c3a2a6
CW		 3921}
3922
e615efe4
ED		 3923/* Program iCLKIP clock to the desired frequency */
3924static void lpt_program_iclkip(struct drm_crtc *crtc)
3925{
3926 struct drm_device *dev = crtc->dev;
3927 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3928 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3929 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3930 u32 temp;
3931
a580516d 3932 mutex_lock(&dev_priv->sb_lock);
09153000 3933
e615efe4
ED		 3934 /* It is necessary to ungate the pixclk gate prior to programming
3935 * the divisors, and gate it back when it is done.
3936 */
3937 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3938
3939 /* Disable SSCCTL */
3940 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3941 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3942 SBI_SSCCTL_DISABLE,
3943 SBI_ICLK);
e615efe4
ED		 3944
3945 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3946 if (clock == 20000) {
e615efe4
ED		 3947 auxdiv = 1;
3948 divsel = 0x41;
3949 phaseinc = 0x20;
3950 } else {
3951 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3952 * but the adjusted_mode->crtc_clock in in KHz. To get the
3953 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3954 * convert the virtual clock precision to KHz here for higher
3955 * precision.
3956 */
3957 u32 iclk_virtual_root_freq = 172800 * 1000;
3958 u32 iclk_pi_range = 64;
3959 u32 desired_divisor, msb_divisor_value, pi_value;
3960
12d7ceed 3961 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3962 msb_divisor_value = desired_divisor / iclk_pi_range;
3963 pi_value = desired_divisor % iclk_pi_range;
3964
3965 auxdiv = 0;
3966 divsel = msb_divisor_value - 2;
3967 phaseinc = pi_value;
3968 }
3969
3970 /* This should not happen with any sane values */
3971 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3972 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3973 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3974 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3975
3976 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3977 clock,
e615efe4
ED		 3978 auxdiv,
3979 divsel,
3980 phasedir,
3981 phaseinc);
3982
3983 /* Program SSCDIVINTPHASE6 */
988d6ee8 3984 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3985 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3986 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3987 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3988 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3989 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3990 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3991 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3992
3993 /* Program SSCAUXDIV */
988d6ee8 3994 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3995 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3996 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3997 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3998
3999 /* Enable modulator and associated divider */
988d6ee8 4000 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4001 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4002 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4003
4004 /* Wait for initialization time */
4005 udelay(24);
4006
4007 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4008
a580516d 4009 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4010}
4011
275f01b2
DV		 4012static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4013 enum pipe pch_transcoder)
4014{
4015 struct drm_device *dev = crtc->base.dev;
4016 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4017 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4018
4019 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4020 I915_READ(HTOTAL(cpu_transcoder)));
4021 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4022 I915_READ(HBLANK(cpu_transcoder)));
4023 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4024 I915_READ(HSYNC(cpu_transcoder)));
4025
4026 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4027 I915_READ(VTOTAL(cpu_transcoder)));
4028 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4029 I915_READ(VBLANK(cpu_transcoder)));
4030 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4031 I915_READ(VSYNC(cpu_transcoder)));
4032 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4033 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4034}
4035
003632d9 4036static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4037{
4038 struct drm_i915_private *dev_priv = dev->dev_private;
4039 uint32_t temp;
4040
4041 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4042 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4043 return;
4044
4045 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4046 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4047
003632d9
ACO		 4048 temp &= ~FDI_BC_BIFURCATION_SELECT;
4049 if (enable)
4050 temp |= FDI_BC_BIFURCATION_SELECT;
4051
4052 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4053 I915_WRITE(SOUTH_CHICKEN1, temp);
4054 POSTING_READ(SOUTH_CHICKEN1);
4055}
4056
4057static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4058{
4059 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4060
4061 switch (intel_crtc->pipe) {
4062 case PIPE_A:
4063 break;
4064 case PIPE_B:
6e3c9717 4065 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4066 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4067 else
003632d9 4068 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4069
4070 break;
4071 case PIPE_C:
003632d9 4072 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4073
4074 break;
4075 default:
4076 BUG();
4077 }
4078}
4079
f67a559d
JB		 4080/*
4081 * Enable PCH resources required for PCH ports:
4082 * - PCH PLLs
4083 * - FDI training & RX/TX
4084 * - update transcoder timings
4085 * - DP transcoding bits
4086 * - transcoder
4087 */
4088static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4089{
4090 struct drm_device *dev = crtc->dev;
4091 struct drm_i915_private *dev_priv = dev->dev_private;
4092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093 int pipe = intel_crtc->pipe;
ee7b9f93 4094 u32 reg, temp;
2c07245f 4095
ab9412ba 4096 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4097
1fbc0d78
DV		 4098 if (IS_IVYBRIDGE(dev))
4099 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4100
cd986abb
DV		 4101 /* Write the TU size bits before fdi link training, so that error
4102 * detection works. */
4103 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4104 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4105
c98e9dcf 4106 /* For PCH output, training FDI link */
674cf967 4107 dev_priv->display.fdi_link_train(crtc);
2c07245f 4108
3ad8a208
DV		 4109 /* We need to program the right clock selection before writing the pixel
4110 * mutliplier into the DPLL. */
303b81e0 4111 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4112 u32 sel;
4b645f14 4113
c98e9dcf 4114 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4115 temp |= TRANS_DPLL_ENABLE(pipe);
4116 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4117 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4118 temp |= sel;
4119 else
4120 temp &= ~sel;
c98e9dcf 4121 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4122 }
5eddb70b 4123
3ad8a208
DV		 4124 /* XXX: pch pll's can be enabled any time before we enable the PCH
4125 * transcoder, and we actually should do this to not upset any PCH
4126 * transcoder that already use the clock when we share it.
4127 *
4128 * Note that enable_shared_dpll tries to do the right thing, but
4129 * get_shared_dpll unconditionally resets the pll - we need that to have
4130 * the right LVDS enable sequence. */
85b3894f 4131 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4132
d9b6cb56
JB		 4133 /* set transcoder timing, panel must allow it */
4134 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4135 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4136
303b81e0 4137 intel_fdi_normal_train(crtc);
5e84e1a4 4138
c98e9dcf 4139 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4140 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4141 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4142 reg = TRANS_DP_CTL(pipe);
4143 temp = I915_READ(reg);
4144 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4145 TRANS_DP_SYNC_MASK |
4146 TRANS_DP_BPC_MASK);
e3ef4479 4147 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4148 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4149
4150 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4151 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4152 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4153 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4154
4155 switch (intel_trans_dp_port_sel(crtc)) {
4156 case PCH_DP_B:
5eddb70b 4157 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4158 break;
4159 case PCH_DP_C:
5eddb70b 4160 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4161 break;
4162 case PCH_DP_D:
5eddb70b 4163 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4164 break;
4165 default:
e95d41e1 4166 BUG();
32f9d658 4167 }
2c07245f 4168
5eddb70b 4169 I915_WRITE(reg, temp);
6be4a607 4170 }
b52eb4dc 4171
b8a4f404 4172 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4173}
4174
1507e5bd
PZ		 4175static void lpt_pch_enable(struct drm_crtc *crtc)
4176{
4177 struct drm_device *dev = crtc->dev;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4180 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4181
ab9412ba 4182 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4183
8c52b5e8 4184 lpt_program_iclkip(crtc);
1507e5bd 4185
0540e488 4186 /* Set transcoder timing. */
275f01b2 4187 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4188
937bb610 4189 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4190}
4191
190f68c5
ACO		 4192struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4193 struct intel_crtc_state *crtc_state)
ee7b9f93 4194{
e2b78267 4195 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4196 struct intel_shared_dpll *pll;
de419ab6 4197 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4198 enum intel_dpll_id i;
ee7b9f93 4199
de419ab6
ML		 4200 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4201
98b6bd99
DV		 4202 if (HAS_PCH_IBX(dev_priv->dev)) {
4203 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4204 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4205 pll = &dev_priv->shared_dplls[i];
98b6bd99 4206
46edb027
DV		 4207 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4208 crtc->base.base.id, pll->name);
98b6bd99 4209
de419ab6 4210 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4211
98b6bd99
DV		 4212 goto found;
4213 }
4214
bcddf610
S		 4215 if (IS_BROXTON(dev_priv->dev)) {
4216 /* PLL is attached to port in bxt */
4217 struct intel_encoder *encoder;
4218 struct intel_digital_port *intel_dig_port;
4219
4220 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4221 if (WARN_ON(!encoder))
4222 return NULL;
4223
4224 intel_dig_port = enc_to_dig_port(&encoder->base);
4225 /* 1:1 mapping between ports and PLLs */
4226 i = (enum intel_dpll_id)intel_dig_port->port;
4227 pll = &dev_priv->shared_dplls[i];
4228 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4229 crtc->base.base.id, pll->name);
de419ab6 4230 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4231
4232 goto found;
4233 }
4234
e72f9fbf
DV		 4235 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4236 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4237
4238 /* Only want to check enabled timings first */
de419ab6 4239 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4240 continue;
4241
190f68c5 4242 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4243 &shared_dpll[i].hw_state,
4244 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4245 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4246 crtc->base.base.id, pll->name,
de419ab6 4247 shared_dpll[i].crtc_mask,
8bd31e67 4248 pll->active);
ee7b9f93
JB		 4249 goto found;
4250 }
4251 }
4252
4253 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4254 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4255 pll = &dev_priv->shared_dplls[i];
de419ab6 4256 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4257 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4258 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4259 goto found;
4260 }
4261 }
4262
4263 return NULL;
4264
4265found:
de419ab6
ML		 4266 if (shared_dpll[i].crtc_mask == 0)
4267 shared_dpll[i].hw_state =
4268 crtc_state->dpll_hw_state;
f2a69f44 4269
190f68c5 4270 crtc_state->shared_dpll = i;
46edb027
DV		 4271 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4272 pipe_name(crtc->pipe));
ee7b9f93 4273
de419ab6 4274 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4275
ee7b9f93
JB		 4276 return pll;
4277}
4278
de419ab6 4279static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4280{
de419ab6
ML		 4281 struct drm_i915_private *dev_priv = to_i915(state->dev);
4282 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4283 struct intel_shared_dpll *pll;
4284 enum intel_dpll_id i;
4285
de419ab6
ML		 4286 if (!to_intel_atomic_state(state)->dpll_set)
4287 return;
8bd31e67 4288
de419ab6 4289 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4290 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4291 pll = &dev_priv->shared_dplls[i];
de419ab6 4292 pll->config = shared_dpll[i];
8bd31e67
ACO		 4293 }
4294}
4295
a1520318 4296static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4297{
4298 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4299 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4300 u32 temp;
4301
4302 temp = I915_READ(dslreg);
4303 udelay(500);
4304 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4305 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4306 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4307 }
4308}
4309
86adf9d7
ML		 4310static int
4311skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4312 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4313 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4314{
86adf9d7
ML		 4315 struct intel_crtc_scaler_state *scaler_state =
4316 &crtc_state->scaler_state;
4317 struct intel_crtc *intel_crtc =
4318 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4319 int need_scaling;
6156a456
CK		 4320
4321 need_scaling = intel_rotation_90_or_270(rotation) ?
4322 (src_h != dst_w || src_w != dst_h):
4323 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4324
4325 /*
4326 * if plane is being disabled or scaler is no more required or force detach
4327 * - free scaler binded to this plane/crtc
4328 * - in order to do this, update crtc->scaler_usage
4329 *
4330 * Here scaler state in crtc_state is set free so that
4331 * scaler can be assigned to other user. Actual register
4332 * update to free the scaler is done in plane/panel-fit programming.
4333 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4334 */
86adf9d7 4335 if (force_detach || !need_scaling) {
a1b2278e 4336 if (*scaler_id >= 0) {
86adf9d7 4337 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4338 scaler_state->scalers[*scaler_id].in_use = 0;
4339
86adf9d7
ML		 4340 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4341 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4342 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4343 scaler_state->scaler_users);
4344 *scaler_id = -1;
4345 }
4346 return 0;
4347 }
4348
4349 /* range checks */
4350 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4351 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4352
4353 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4354 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4355 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4356 "size is out of scaler range\n",
86adf9d7 4357 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4358 return -EINVAL;
4359 }
4360
86adf9d7
ML		 4361 /* mark this plane as a scaler user in crtc_state */
4362 scaler_state->scaler_users |= (1 << scaler_user);
4363 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4364 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4365 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4366 scaler_state->scaler_users);
4367
4368 return 0;
4369}
4370
4371/**
4372 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4373 *
4374 * @state: crtc's scaler state
86adf9d7
ML		 4375 *
4376 * Return
4377 * 0 - scaler_usage updated successfully
4378 * error - requested scaling cannot be supported or other error condition
4379 */
e435d6e5 4380int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4381{
4382 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
7c5f93b0 4383 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
86adf9d7
ML		 4384
4385 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4386 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4387
e435d6e5 4388 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4389 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4390 state->pipe_src_w, state->pipe_src_h,
aad941d5 4391 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
86adf9d7
ML		 4392}
4393
4394/**
4395 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4396 *
4397 * @state: crtc's scaler state
86adf9d7
ML		 4398 * @plane_state: atomic plane state to update
4399 *
4400 * Return
4401 * 0 - scaler_usage updated successfully
4402 * error - requested scaling cannot be supported or other error condition
4403 */
da20eabd
ML		 4404static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4405 struct intel_plane_state *plane_state)
86adf9d7
ML		 4406{
4407
4408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4409 struct intel_plane *intel_plane =
4410 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4411 struct drm_framebuffer *fb = plane_state->base.fb;
4412 int ret;
4413
4414 bool force_detach = !fb || !plane_state->visible;
4415
4416 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4417 intel_plane->base.base.id, intel_crtc->pipe,
4418 drm_plane_index(&intel_plane->base));
4419
4420 ret = skl_update_scaler(crtc_state, force_detach,
4421 drm_plane_index(&intel_plane->base),
4422 &plane_state->scaler_id,
4423 plane_state->base.rotation,
4424 drm_rect_width(&plane_state->src) >> 16,
4425 drm_rect_height(&plane_state->src) >> 16,
4426 drm_rect_width(&plane_state->dst),
4427 drm_rect_height(&plane_state->dst));
4428
4429 if (ret || plane_state->scaler_id < 0)
4430 return ret;
4431
a1b2278e 4432 /* check colorkey */
818ed961 4433 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4434 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4435 intel_plane->base.base.id);
a1b2278e
CK		 4436 return -EINVAL;
4437 }
4438
4439 /* Check src format */
86adf9d7
ML		 4440 switch (fb->pixel_format) {
4441 case DRM_FORMAT_RGB565:
4442 case DRM_FORMAT_XBGR8888:
4443 case DRM_FORMAT_XRGB8888:
4444 case DRM_FORMAT_ABGR8888:
4445 case DRM_FORMAT_ARGB8888:
4446 case DRM_FORMAT_XRGB2101010:
4447 case DRM_FORMAT_XBGR2101010:
4448 case DRM_FORMAT_YUYV:
4449 case DRM_FORMAT_YVYU:
4450 case DRM_FORMAT_UYVY:
4451 case DRM_FORMAT_VYUY:
4452 break;
4453 default:
4454 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4455 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4456 return -EINVAL;
a1b2278e
CK		 4457 }
4458
a1b2278e
CK		 4459 return 0;
4460}
4461
e435d6e5
ML		 4462static void skylake_scaler_disable(struct intel_crtc *crtc)
4463{
4464 int i;
4465
4466 for (i = 0; i < crtc->num_scalers; i++)
4467 skl_detach_scaler(crtc, i);
4468}
4469
4470static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4471{
4472 struct drm_device *dev = crtc->base.dev;
4473 struct drm_i915_private *dev_priv = dev->dev_private;
4474 int pipe = crtc->pipe;
a1b2278e
CK		 4475 struct intel_crtc_scaler_state *scaler_state =
4476 &crtc->config->scaler_state;
4477
4478 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4479
6e3c9717 4480 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4481 int id;
4482
4483 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4484 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4485 return;
4486 }
4487
4488 id = scaler_state->scaler_id;
4489 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4490 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4491 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4492 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4493
4494 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4495 }
4496}
4497
b074cec8
JB		 4498static void ironlake_pfit_enable(struct intel_crtc *crtc)
4499{
4500 struct drm_device *dev = crtc->base.dev;
4501 struct drm_i915_private *dev_priv = dev->dev_private;
4502 int pipe = crtc->pipe;
4503
6e3c9717 4504 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4505 /* Force use of hard-coded filter coefficients
4506 * as some pre-programmed values are broken,
4507 * e.g. x201.
4508 */
4509 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4510 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4511 PF_PIPE_SEL_IVB(pipe));
4512 else
4513 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4514 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4515 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4516 }
4517}
4518
20bc8673 4519void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4520{
cea165c3
VS		 4521 struct drm_device *dev = crtc->base.dev;
4522 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4523
6e3c9717 4524 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4525 return;
4526
cea165c3
VS		 4527 /* We can only enable IPS after we enable a plane and wait for a vblank */
4528 intel_wait_for_vblank(dev, crtc->pipe);
4529
d77e4531 4530 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4531 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4532 mutex_lock(&dev_priv->rps.hw_lock);
4533 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4534 mutex_unlock(&dev_priv->rps.hw_lock);
4535 /* Quoting Art Runyan: "its not safe to expect any particular
4536 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4537 * mailbox." Moreover, the mailbox may return a bogus state,
4538 * so we need to just enable it and continue on.
2a114cc1
BW		 4539 */
4540 } else {
4541 I915_WRITE(IPS_CTL, IPS_ENABLE);
4542 /* The bit only becomes 1 in the next vblank, so this wait here
4543 * is essentially intel_wait_for_vblank. If we don't have this
4544 * and don't wait for vblanks until the end of crtc_enable, then
4545 * the HW state readout code will complain that the expected
4546 * IPS_CTL value is not the one we read. */
4547 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4548 DRM_ERROR("Timed out waiting for IPS enable\n");
4549 }
d77e4531
PZ		 4550}
4551
20bc8673 4552void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4553{
4554 struct drm_device *dev = crtc->base.dev;
4555 struct drm_i915_private *dev_priv = dev->dev_private;
4556
6e3c9717 4557 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4558 return;
4559
4560 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4561 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4562 mutex_lock(&dev_priv->rps.hw_lock);
4563 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4564 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4565 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4566 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4567 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4568 } else {
2a114cc1 4569 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4570 POSTING_READ(IPS_CTL);
4571 }
d77e4531
PZ		 4572
4573 /* We need to wait for a vblank before we can disable the plane. */
4574 intel_wait_for_vblank(dev, crtc->pipe);
4575}
4576
4577/** Loads the palette/gamma unit for the CRTC with the prepared values */
4578static void intel_crtc_load_lut(struct drm_crtc *crtc)
4579{
4580 struct drm_device *dev = crtc->dev;
4581 struct drm_i915_private *dev_priv = dev->dev_private;
4582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4583 enum pipe pipe = intel_crtc->pipe;
d77e4531
PZ		 4584 int i;
4585 bool reenable_ips = false;
4586
4587 /* The clocks have to be on to load the palette. */
53d9f4e9 4588 if (!crtc->state->active)
d77e4531
PZ		 4589 return;
4590
50360403 4591 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4592 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4593 assert_dsi_pll_enabled(dev_priv);
4594 else
4595 assert_pll_enabled(dev_priv, pipe);
4596 }
4597
d77e4531
PZ		 4598 /* Workaround : Do not read or write the pipe palette/gamma data while
4599 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4600 */
6e3c9717 4601 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4602 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4603 GAMMA_MODE_MODE_SPLIT)) {
4604 hsw_disable_ips(intel_crtc);
4605 reenable_ips = true;
4606 }
4607
4608 for (i = 0; i < 256; i++) {
f65a9c5b
VS		 4609 u32 palreg;
4610
4611 if (HAS_GMCH_DISPLAY(dev))
4612 palreg = PALETTE(pipe, i);
4613 else
4614 palreg = LGC_PALETTE(pipe, i);
4615
4616 I915_WRITE(palreg,
d77e4531
PZ		 4617 (intel_crtc->lut_r[i] << 16) |
4618 (intel_crtc->lut_g[i] << 8) |
4619 intel_crtc->lut_b[i]);
4620 }
4621
4622 if (reenable_ips)
4623 hsw_enable_ips(intel_crtc);
4624}
4625
7cac945f 4626static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4627{
7cac945f 4628 if (intel_crtc->overlay) {
d3eedb1a
VS		 4629 struct drm_device *dev = intel_crtc->base.dev;
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631
4632 mutex_lock(&dev->struct_mutex);
4633 dev_priv->mm.interruptible = false;
4634 (void) intel_overlay_switch_off(intel_crtc->overlay);
4635 dev_priv->mm.interruptible = true;
4636 mutex_unlock(&dev->struct_mutex);
4637 }
4638
4639 /* Let userspace switch the overlay on again. In most cases userspace
4640 * has to recompute where to put it anyway.
4641 */
4642}
4643
87d4300a
ML		 4644/**
4645 * intel_post_enable_primary - Perform operations after enabling primary plane
4646 * @crtc: the CRTC whose primary plane was just enabled
4647 *
4648 * Performs potentially sleeping operations that must be done after the primary
4649 * plane is enabled, such as updating FBC and IPS. Note that this may be
4650 * called due to an explicit primary plane update, or due to an implicit
4651 * re-enable that is caused when a sprite plane is updated to no longer
4652 * completely hide the primary plane.
4653 */
4654static void
4655intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4656{
4657 struct drm_device *dev = crtc->dev;
87d4300a 4658 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4660 int pipe = intel_crtc->pipe;
a5c4d7bc 4661
87d4300a
ML		 4662 /*
4663 * BDW signals flip done immediately if the plane
4664 * is disabled, even if the plane enable is already
4665 * armed to occur at the next vblank :(
4666 */
4667 if (IS_BROADWELL(dev))
4668 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4669
87d4300a
ML		 4670 /*
4671 * FIXME IPS should be fine as long as one plane is
4672 * enabled, but in practice it seems to have problems
4673 * when going from primary only to sprite only and vice
4674 * versa.
4675 */
a5c4d7bc
VS		 4676 hsw_enable_ips(intel_crtc);
4677
f99d7069 4678 /*
87d4300a
ML		 4679 * Gen2 reports pipe underruns whenever all planes are disabled.
4680 * So don't enable underrun reporting before at least some planes
4681 * are enabled.
4682 * FIXME: Need to fix the logic to work when we turn off all planes
4683 * but leave the pipe running.
f99d7069 4684 */
87d4300a
ML		 4685 if (IS_GEN2(dev))
4686 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4687
4688 /* Underruns don't raise interrupts, so check manually. */
4689 if (HAS_GMCH_DISPLAY(dev))
4690 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4691}
4692
87d4300a
ML		 4693/**
4694 * intel_pre_disable_primary - Perform operations before disabling primary plane
4695 * @crtc: the CRTC whose primary plane is to be disabled
4696 *
4697 * Performs potentially sleeping operations that must be done before the
4698 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4699 * be called due to an explicit primary plane update, or due to an implicit
4700 * disable that is caused when a sprite plane completely hides the primary
4701 * plane.
4702 */
4703static void
4704intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4705{
4706 struct drm_device *dev = crtc->dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709 int pipe = intel_crtc->pipe;
a5c4d7bc 4710
87d4300a
ML		 4711 /*
4712 * Gen2 reports pipe underruns whenever all planes are disabled.
4713 * So diasble underrun reporting before all the planes get disabled.
4714 * FIXME: Need to fix the logic to work when we turn off all planes
4715 * but leave the pipe running.
4716 */
4717 if (IS_GEN2(dev))
4718 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4719
87d4300a
ML		 4720 /*
4721 * Vblank time updates from the shadow to live plane control register
4722 * are blocked if the memory self-refresh mode is active at that
4723 * moment. So to make sure the plane gets truly disabled, disable
4724 * first the self-refresh mode. The self-refresh enable bit in turn
4725 * will be checked/applied by the HW only at the next frame start
4726 * event which is after the vblank start event, so we need to have a
4727 * wait-for-vblank between disabling the plane and the pipe.
4728 */
262cd2e1 4729 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4730 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4731 dev_priv->wm.vlv.cxsr = false;
4732 intel_wait_for_vblank(dev, pipe);
4733 }
87d4300a 4734
87d4300a
ML		 4735 /*
4736 * FIXME IPS should be fine as long as one plane is
4737 * enabled, but in practice it seems to have problems
4738 * when going from primary only to sprite only and vice
4739 * versa.
4740 */
a5c4d7bc 4741 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4742}
4743
ac21b225
ML		 4744static void intel_post_plane_update(struct intel_crtc *crtc)
4745{
4746 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4747 struct drm_device *dev = crtc->base.dev;
7733b49b 4748 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4749
4750 if (atomic->wait_vblank)
4751 intel_wait_for_vblank(dev, crtc->pipe);
4752
4753 intel_frontbuffer_flip(dev, atomic->fb_bits);
4754
852eb00d
VS		 4755 if (atomic->disable_cxsr)
4756 crtc->wm.cxsr_allowed = true;
4757
f015c551
VS		 4758 if (crtc->atomic.update_wm_post)
4759 intel_update_watermarks(&crtc->base);
4760
c80ac854 4761 if (atomic->update_fbc)
7733b49b 4762 intel_fbc_update(dev_priv);
ac21b225
ML		 4763
4764 if (atomic->post_enable_primary)
4765 intel_post_enable_primary(&crtc->base);
4766
ac21b225
ML		 4767 memset(atomic, 0, sizeof(*atomic));
4768}
4769
4770static void intel_pre_plane_update(struct intel_crtc *crtc)
4771{
4772 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4773 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225 4774 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
ac21b225 4775
c80ac854 4776 if (atomic->disable_fbc)
25ad93fd 4777 intel_fbc_disable_crtc(crtc);
ac21b225 4778
066cf55b
RV		 4779 if (crtc->atomic.disable_ips)
4780 hsw_disable_ips(crtc);
4781
ac21b225
ML		 4782 if (atomic->pre_disable_primary)
4783 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4784
4785 if (atomic->disable_cxsr) {
4786 crtc->wm.cxsr_allowed = false;
4787 intel_set_memory_cxsr(dev_priv, false);
4788 }
ac21b225
ML		 4789}
4790
d032ffa0 4791static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4792{
4793 struct drm_device *dev = crtc->dev;
4794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4795 struct drm_plane *p;
87d4300a
ML		 4796 int pipe = intel_crtc->pipe;
4797
7cac945f 4798 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4799
d032ffa0
ML		 4800 drm_for_each_plane_mask(p, dev, plane_mask)
4801 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4802
f99d7069
DV		 4803 /*
4804 * FIXME: Once we grow proper nuclear flip support out of this we need
4805 * to compute the mask of flip planes precisely. For the time being
4806 * consider this a flip to a NULL plane.
4807 */
4808 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4809}
4810
f67a559d
JB		 4811static void ironlake_crtc_enable(struct drm_crtc *crtc)
4812{
4813 struct drm_device *dev = crtc->dev;
4814 struct drm_i915_private *dev_priv = dev->dev_private;
4815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4816 struct intel_encoder *encoder;
f67a559d 4817 int pipe = intel_crtc->pipe;
f67a559d 4818
53d9f4e9 4819 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4820 return;
4821
6e3c9717 4822 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4823 intel_prepare_shared_dpll(intel_crtc);
4824
6e3c9717 4825 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4826 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4827
4828 intel_set_pipe_timings(intel_crtc);
4829
6e3c9717 4830 if (intel_crtc->config->has_pch_encoder) {
29407aab 4831 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4832 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4833 }
4834
4835 ironlake_set_pipeconf(crtc);
4836
f67a559d 4837 intel_crtc->active = true;
8664281b 4838
a72e4c9f
DV		 4839 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4840 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4841
f6736a1a 4842 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4843 if (encoder->pre_enable)
4844 encoder->pre_enable(encoder);
f67a559d 4845
6e3c9717 4846 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4847 /* Note: FDI PLL enabling _must_ be done before we enable the
4848 * cpu pipes, hence this is separate from all the other fdi/pch
4849 * enabling. */
88cefb6c 4850 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4851 } else {
4852 assert_fdi_tx_disabled(dev_priv, pipe);
4853 assert_fdi_rx_disabled(dev_priv, pipe);
4854 }
f67a559d 4855
b074cec8 4856 ironlake_pfit_enable(intel_crtc);
f67a559d 4857
9c54c0dd
JB		 4858 /*
4859 * On ILK+ LUT must be loaded before the pipe is running but with
4860 * clocks enabled
4861 */
4862 intel_crtc_load_lut(crtc);
4863
f37fcc2a 4864 intel_update_watermarks(crtc);
e1fdc473 4865 intel_enable_pipe(intel_crtc);
f67a559d 4866
6e3c9717 4867 if (intel_crtc->config->has_pch_encoder)
f67a559d 4868 ironlake_pch_enable(crtc);
c98e9dcf 4869
f9b61ff6
DV		 4870 assert_vblank_disabled(crtc);
4871 drm_crtc_vblank_on(crtc);
4872
fa5c73b1
DV		 4873 for_each_encoder_on_crtc(dev, crtc, encoder)
4874 encoder->enable(encoder);
61b77ddd
DV		 4875
4876 if (HAS_PCH_CPT(dev))
a1520318 4877 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4878}
4879
42db64ef
PZ		 4880/* IPS only exists on ULT machines and is tied to pipe A. */
4881static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4882{
f5adf94e 4883 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4884}
4885
4f771f10
PZ		 4886static void haswell_crtc_enable(struct drm_crtc *crtc)
4887{
4888 struct drm_device *dev = crtc->dev;
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4891 struct intel_encoder *encoder;
99d736a2
ML		 4892 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4893 struct intel_crtc_state *pipe_config =
4894 to_intel_crtc_state(crtc->state);
7d4aefd0 4895 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4f771f10 4896
53d9f4e9 4897 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4898 return;
4899
df8ad70c
DV		 4900 if (intel_crtc_to_shared_dpll(intel_crtc))
4901 intel_enable_shared_dpll(intel_crtc);
4902
6e3c9717 4903 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4904 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4905
4906 intel_set_pipe_timings(intel_crtc);
4907
6e3c9717
ACO		 4908 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4909 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4910 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4911 }
4912
6e3c9717 4913 if (intel_crtc->config->has_pch_encoder) {
229fca97 4914 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4915 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4916 }
4917
4918 haswell_set_pipeconf(crtc);
4919
4920 intel_set_pipe_csc(crtc);
4921
4f771f10 4922 intel_crtc->active = true;
8664281b 4923
a72e4c9f 4924 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7d4aefd0
SS		 4925 for_each_encoder_on_crtc(dev, crtc, encoder) {
4926 if (encoder->pre_pll_enable)
4927 encoder->pre_pll_enable(encoder);
4f771f10
PZ		 4928 if (encoder->pre_enable)
4929 encoder->pre_enable(encoder);
7d4aefd0 4930 }
4f771f10 4931
6e3c9717 4932 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4933 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4934 true);
4fe9467d
ID		 4935 dev_priv->display.fdi_link_train(crtc);
4936 }
4937
7d4aefd0
SS		 4938 if (!is_dsi)
4939 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4940
1c132b44 4941 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 4942 skylake_pfit_enable(intel_crtc);
ff6d9f55 4943 else
1c132b44 4944 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4945
4946 /*
4947 * On ILK+ LUT must be loaded before the pipe is running but with
4948 * clocks enabled
4949 */
4950 intel_crtc_load_lut(crtc);
4951
1f544388 4952 intel_ddi_set_pipe_settings(crtc);
7d4aefd0
SS		 4953 if (!is_dsi)
4954 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4955
f37fcc2a 4956 intel_update_watermarks(crtc);
e1fdc473 4957 intel_enable_pipe(intel_crtc);
42db64ef 4958
6e3c9717 4959 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4960 lpt_pch_enable(crtc);
4f771f10 4961
7d4aefd0 4962 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
0e32b39c
DA		 4963 intel_ddi_set_vc_payload_alloc(crtc, true);
4964
f9b61ff6
DV		 4965 assert_vblank_disabled(crtc);
4966 drm_crtc_vblank_on(crtc);
4967
8807e55b 4968 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4969 encoder->enable(encoder);
8807e55b
JN		 4970 intel_opregion_notify_encoder(encoder, true);
4971 }
4f771f10 4972
e4916946
PZ		 4973 /* If we change the relative order between pipe/planes enabling, we need
4974 * to change the workaround. */
99d736a2
ML		 4975 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4976 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4977 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4978 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4979 }
4f771f10
PZ		 4980}
4981
bfd16b2a 4982static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
3f8dce3a
DV		 4983{
4984 struct drm_device *dev = crtc->base.dev;
4985 struct drm_i915_private *dev_priv = dev->dev_private;
4986 int pipe = crtc->pipe;
4987
4988 /* To avoid upsetting the power well on haswell only disable the pfit if
4989 * it's in use. The hw state code will make sure we get this right. */
bfd16b2a 4990 if (force || crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4991 I915_WRITE(PF_CTL(pipe), 0);
4992 I915_WRITE(PF_WIN_POS(pipe), 0);
4993 I915_WRITE(PF_WIN_SZ(pipe), 0);
4994 }
4995}
4996
6be4a607
JB		 4997static void ironlake_crtc_disable(struct drm_crtc *crtc)
4998{
4999 struct drm_device *dev = crtc->dev;
5000 struct drm_i915_private *dev_priv = dev->dev_private;
5001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5002 struct intel_encoder *encoder;
6be4a607 5003 int pipe = intel_crtc->pipe;
5eddb70b 5004 u32 reg, temp;
b52eb4dc 5005
ea9d758d
DV		 5006 for_each_encoder_on_crtc(dev, crtc, encoder)
5007 encoder->disable(encoder);
5008
f9b61ff6
DV		 5009 drm_crtc_vblank_off(crtc);
5010 assert_vblank_disabled(crtc);
5011
6e3c9717 5012 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5013 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5014
575f7ab7 5015 intel_disable_pipe(intel_crtc);
32f9d658 5016
bfd16b2a 5017 ironlake_pfit_disable(intel_crtc, false);
2c07245f 5018
5a74f70a
VS		 5019 if (intel_crtc->config->has_pch_encoder)
5020 ironlake_fdi_disable(crtc);
5021
bf49ec8c
DV		 5022 for_each_encoder_on_crtc(dev, crtc, encoder)
5023 if (encoder->post_disable)
5024 encoder->post_disable(encoder);
2c07245f 5025
6e3c9717 5026 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5027 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5028
d925c59a
DV		 5029 if (HAS_PCH_CPT(dev)) {
5030 /* disable TRANS_DP_CTL */
5031 reg = TRANS_DP_CTL(pipe);
5032 temp = I915_READ(reg);
5033 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5034 TRANS_DP_PORT_SEL_MASK);
5035 temp |= TRANS_DP_PORT_SEL_NONE;
5036 I915_WRITE(reg, temp);
5037
5038 /* disable DPLL_SEL */
5039 temp = I915_READ(PCH_DPLL_SEL);
11887397 5040 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5041 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5042 }
e3421a18 5043
d925c59a
DV		 5044 ironlake_fdi_pll_disable(intel_crtc);
5045 }
6be4a607 5046}
1b3c7a47 5047
4f771f10 5048static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5049{
4f771f10
PZ		 5050 struct drm_device *dev = crtc->dev;
5051 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5053 struct intel_encoder *encoder;
6e3c9717 5054 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7d4aefd0 5055 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
ee7b9f93 5056
8807e55b
JN		 5057 for_each_encoder_on_crtc(dev, crtc, encoder) {
5058 intel_opregion_notify_encoder(encoder, false);
4f771f10 5059 encoder->disable(encoder);
8807e55b 5060 }
4f771f10 5061
f9b61ff6
DV		 5062 drm_crtc_vblank_off(crtc);
5063 assert_vblank_disabled(crtc);
5064
6e3c9717 5065 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5066 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5067 false);
575f7ab7 5068 intel_disable_pipe(intel_crtc);
4f771f10 5069
6e3c9717 5070 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5071 intel_ddi_set_vc_payload_alloc(crtc, false);
5072
7d4aefd0
SS		 5073 if (!is_dsi)
5074 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5075
1c132b44 5076 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5077 skylake_scaler_disable(intel_crtc);
ff6d9f55 5078 else
bfd16b2a 5079 ironlake_pfit_disable(intel_crtc, false);
4f771f10 5080
7d4aefd0
SS		 5081 if (!is_dsi)
5082 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5083
6e3c9717 5084 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5085 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5086 intel_ddi_fdi_disable(crtc);
83616634 5087 }
4f771f10 5088
97b040aa
ID		 5089 for_each_encoder_on_crtc(dev, crtc, encoder)
5090 if (encoder->post_disable)
5091 encoder->post_disable(encoder);
4f771f10
PZ		 5092}
5093
2dd24552
JB		 5094static void i9xx_pfit_enable(struct intel_crtc *crtc)
5095{
5096 struct drm_device *dev = crtc->base.dev;
5097 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5098 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5099
681a8504 5100 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5101 return;
5102
2dd24552 5103 /*
c0b03411
DV		 5104 * The panel fitter should only be adjusted whilst the pipe is disabled,
5105 * according to register description and PRM.
2dd24552 5106 */
c0b03411
DV		 5107 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5108 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5109
b074cec8
JB		 5110 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5111 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5112
5113 /* Border color in case we don't scale up to the full screen. Black by
5114 * default, change to something else for debugging. */
5115 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5116}
5117
d05410f9
DA		 5118static enum intel_display_power_domain port_to_power_domain(enum port port)
5119{
5120 switch (port) {
5121 case PORT_A:
5122 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5123 case PORT_B:
5124 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5125 case PORT_C:
5126 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5127 case PORT_D:
5128 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ		 5129 case PORT_E:
5130 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA		 5131 default:
5132 WARN_ON_ONCE(1);
5133 return POWER_DOMAIN_PORT_OTHER;
5134 }
5135}
5136
77d22dca
ID		 5137#define for_each_power_domain(domain, mask) \
5138 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5139 if ((1 << (domain)) & (mask))
5140
319be8ae
ID		 5141enum intel_display_power_domain
5142intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5143{
5144 struct drm_device *dev = intel_encoder->base.dev;
5145 struct intel_digital_port *intel_dig_port;
5146
5147 switch (intel_encoder->type) {
5148 case INTEL_OUTPUT_UNKNOWN:
5149 /* Only DDI platforms should ever use this output type */
5150 WARN_ON_ONCE(!HAS_DDI(dev));
5151 case INTEL_OUTPUT_DISPLAYPORT:
5152 case INTEL_OUTPUT_HDMI:
5153 case INTEL_OUTPUT_EDP:
5154 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5155 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5156 case INTEL_OUTPUT_DP_MST:
5157 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5158 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5159 case INTEL_OUTPUT_ANALOG:
5160 return POWER_DOMAIN_PORT_CRT;
5161 case INTEL_OUTPUT_DSI:
5162 return POWER_DOMAIN_PORT_DSI;
5163 default:
5164 return POWER_DOMAIN_PORT_OTHER;
5165 }
5166}
5167
5168static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5169{
319be8ae
ID		 5170 struct drm_device *dev = crtc->dev;
5171 struct intel_encoder *intel_encoder;
5172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5173 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5174 unsigned long mask;
5175 enum transcoder transcoder;
5176
292b990e
ML		 5177 if (!crtc->state->active)
5178 return 0;
5179
77d22dca
ID		 5180 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5181
5182 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5183 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5184 if (intel_crtc->config->pch_pfit.enabled ||
5185 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5186 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5187
319be8ae
ID		 5188 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5189 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5190
77d22dca
ID		 5191 return mask;
5192}
5193
292b990e 5194static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5195{
292b990e
ML		 5196 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5198 enum intel_display_power_domain domain;
5199 unsigned long domains, new_domains, old_domains;
77d22dca 5200
292b990e
ML		 5201 old_domains = intel_crtc->enabled_power_domains;
5202 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5203
292b990e
ML		 5204 domains = new_domains & ~old_domains;
5205
5206 for_each_power_domain(domain, domains)
5207 intel_display_power_get(dev_priv, domain);
5208
5209 return old_domains & ~new_domains;
5210}
5211
5212static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5213 unsigned long domains)
5214{
5215 enum intel_display_power_domain domain;
5216
5217 for_each_power_domain(domain, domains)
5218 intel_display_power_put(dev_priv, domain);
5219}
77d22dca 5220
292b990e
ML		 5221static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5222{
5223 struct drm_device *dev = state->dev;
5224 struct drm_i915_private *dev_priv = dev->dev_private;
5225 unsigned long put_domains[I915_MAX_PIPES] = {};
5226 struct drm_crtc_state *crtc_state;
5227 struct drm_crtc *crtc;
5228 int i;
77d22dca 5229
292b990e
ML		 5230 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5231 if (needs_modeset(crtc->state))
5232 put_domains[to_intel_crtc(crtc)->pipe] =
5233 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5234 }
5235
27c329ed
ML		 5236 if (dev_priv->display.modeset_commit_cdclk) {
5237 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5238
5239 if (cdclk != dev_priv->cdclk_freq &&
5240 !WARN_ON(!state->allow_modeset))
5241 dev_priv->display.modeset_commit_cdclk(state);
5242 }
50f6e502 5243
292b990e
ML		 5244 for (i = 0; i < I915_MAX_PIPES; i++)
5245 if (put_domains[i])
5246 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5247}
5248
adafdc6f
MK		 5249static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5250{
5251 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5252
5253 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5254 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5255 return max_cdclk_freq;
5256 else if (IS_CHERRYVIEW(dev_priv))
5257 return max_cdclk_freq*95/100;
5258 else if (INTEL_INFO(dev_priv)->gen < 4)
5259 return 2*max_cdclk_freq*90/100;
5260 else
5261 return max_cdclk_freq*90/100;
5262}
5263
560a7ae4
DL		 5264static void intel_update_max_cdclk(struct drm_device *dev)
5265{
5266 struct drm_i915_private *dev_priv = dev->dev_private;
5267
ef11bdb3 5268 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
560a7ae4
DL		 5269 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5270
5271 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5272 dev_priv->max_cdclk_freq = 675000;
5273 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5274 dev_priv->max_cdclk_freq = 540000;
5275 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5276 dev_priv->max_cdclk_freq = 450000;
5277 else
5278 dev_priv->max_cdclk_freq = 337500;
5279 } else if (IS_BROADWELL(dev)) {
5280 /*
5281 * FIXME with extra cooling we can allow
5282 * 540 MHz for ULX and 675 Mhz for ULT.
5283 * How can we know if extra cooling is
5284 * available? PCI ID, VTB, something else?
5285 */
5286 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5287 dev_priv->max_cdclk_freq = 450000;
5288 else if (IS_BDW_ULX(dev))
5289 dev_priv->max_cdclk_freq = 450000;
5290 else if (IS_BDW_ULT(dev))
5291 dev_priv->max_cdclk_freq = 540000;
5292 else
5293 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5294 } else if (IS_CHERRYVIEW(dev)) {
5295 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5296 } else if (IS_VALLEYVIEW(dev)) {
5297 dev_priv->max_cdclk_freq = 400000;
5298 } else {
5299 /* otherwise assume cdclk is fixed */
5300 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5301 }
5302
adafdc6f
MK		 5303 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5304
560a7ae4
DL		 5305 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5306 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5307
5308 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5309 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5310}
5311
5312static void intel_update_cdclk(struct drm_device *dev)
5313{
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315
5316 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5317 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5318 dev_priv->cdclk_freq);
5319
5320 /*
5321 * Program the gmbus_freq based on the cdclk frequency.
5322 * BSpec erroneously claims we should aim for 4MHz, but
5323 * in fact 1MHz is the correct frequency.
5324 */
5325 if (IS_VALLEYVIEW(dev)) {
5326 /*
5327 * Program the gmbus_freq based on the cdclk frequency.
5328 * BSpec erroneously claims we should aim for 4MHz, but
5329 * in fact 1MHz is the correct frequency.
5330 */
5331 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5332 }
5333
5334 if (dev_priv->max_cdclk_freq == 0)
5335 intel_update_max_cdclk(dev);
5336}
5337
70d0c574 5338static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5339{
5340 struct drm_i915_private *dev_priv = dev->dev_private;
5341 uint32_t divider;
5342 uint32_t ratio;
5343 uint32_t current_freq;
5344 int ret;
5345
5346 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5347 switch (frequency) {
5348 case 144000:
5349 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5350 ratio = BXT_DE_PLL_RATIO(60);
5351 break;
5352 case 288000:
5353 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5354 ratio = BXT_DE_PLL_RATIO(60);
5355 break;
5356 case 384000:
5357 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5358 ratio = BXT_DE_PLL_RATIO(60);
5359 break;
5360 case 576000:
5361 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5362 ratio = BXT_DE_PLL_RATIO(60);
5363 break;
5364 case 624000:
5365 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5366 ratio = BXT_DE_PLL_RATIO(65);
5367 break;
5368 case 19200:
5369 /*
5370 * Bypass frequency with DE PLL disabled. Init ratio, divider
5371 * to suppress GCC warning.
5372 */
5373 ratio = 0;
5374 divider = 0;
5375 break;
5376 default:
5377 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5378
5379 return;
5380 }
5381
5382 mutex_lock(&dev_priv->rps.hw_lock);
5383 /* Inform power controller of upcoming frequency change */
5384 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5385 0x80000000);
5386 mutex_unlock(&dev_priv->rps.hw_lock);
5387
5388 if (ret) {
5389 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5390 ret, frequency);
5391 return;
5392 }
5393
5394 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5395 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5396 current_freq = current_freq * 500 + 1000;
5397
5398 /*
5399 * DE PLL has to be disabled when
5400 * - setting to 19.2MHz (bypass, PLL isn't used)
5401 * - before setting to 624MHz (PLL needs toggling)
5402 * - before setting to any frequency from 624MHz (PLL needs toggling)
5403 */
5404 if (frequency == 19200 || frequency == 624000 ||
5405 current_freq == 624000) {
5406 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5407 /* Timeout 200us */
5408 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5409 1))
5410 DRM_ERROR("timout waiting for DE PLL unlock\n");
5411 }
5412
5413 if (frequency != 19200) {
5414 uint32_t val;
5415
5416 val = I915_READ(BXT_DE_PLL_CTL);
5417 val &= ~BXT_DE_PLL_RATIO_MASK;
5418 val |= ratio;
5419 I915_WRITE(BXT_DE_PLL_CTL, val);
5420
5421 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5422 /* Timeout 200us */
5423 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5424 DRM_ERROR("timeout waiting for DE PLL lock\n");
5425
5426 val = I915_READ(CDCLK_CTL);
5427 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5428 val |= divider;
5429 /*
5430 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5431 * enable otherwise.
5432 */
5433 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5434 if (frequency >= 500000)
5435 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5436
5437 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5438 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5439 val |= (frequency - 1000) / 500;
5440 I915_WRITE(CDCLK_CTL, val);
5441 }
5442
5443 mutex_lock(&dev_priv->rps.hw_lock);
5444 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5445 DIV_ROUND_UP(frequency, 25000));
5446 mutex_unlock(&dev_priv->rps.hw_lock);
5447
5448 if (ret) {
5449 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5450 ret, frequency);
5451 return;
5452 }
5453
a47871bd 5454 intel_update_cdclk(dev);
f8437dd1
VK		 5455}
5456
5457void broxton_init_cdclk(struct drm_device *dev)
5458{
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460 uint32_t val;
5461
5462 /*
5463 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5464 * or else the reset will hang because there is no PCH to respond.
5465 * Move the handshake programming to initialization sequence.
5466 * Previously was left up to BIOS.
5467 */
5468 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5469 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5470 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5471
5472 /* Enable PG1 for cdclk */
5473 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5474
5475 /* check if cd clock is enabled */
5476 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5477 DRM_DEBUG_KMS("Display already initialized\n");
5478 return;
5479 }
5480
5481 /*
5482 * FIXME:
5483 * - The initial CDCLK needs to be read from VBT.
5484 * Need to make this change after VBT has changes for BXT.
5485 * - check if setting the max (or any) cdclk freq is really necessary
5486 * here, it belongs to modeset time
5487 */
5488 broxton_set_cdclk(dev, 624000);
5489
5490 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5491 POSTING_READ(DBUF_CTL);
5492
f8437dd1
VK		 5493 udelay(10);
5494
5495 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5496 DRM_ERROR("DBuf power enable timeout!\n");
5497}
5498
5499void broxton_uninit_cdclk(struct drm_device *dev)
5500{
5501 struct drm_i915_private *dev_priv = dev->dev_private;
5502
5503 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5504 POSTING_READ(DBUF_CTL);
5505
f8437dd1
VK		 5506 udelay(10);
5507
5508 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5509 DRM_ERROR("DBuf power disable timeout!\n");
5510
5511 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5512 broxton_set_cdclk(dev, 19200);
5513
5514 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5515}
5516
5d96d8af
DL		 5517static const struct skl_cdclk_entry {
5518 unsigned int freq;
5519 unsigned int vco;
5520} skl_cdclk_frequencies[] = {
5521 { .freq = 308570, .vco = 8640 },
5522 { .freq = 337500, .vco = 8100 },
5523 { .freq = 432000, .vco = 8640 },
5524 { .freq = 450000, .vco = 8100 },
5525 { .freq = 540000, .vco = 8100 },
5526 { .freq = 617140, .vco = 8640 },
5527 { .freq = 675000, .vco = 8100 },
5528};
5529
5530static unsigned int skl_cdclk_decimal(unsigned int freq)
5531{
5532 return (freq - 1000) / 500;
5533}
5534
5535static unsigned int skl_cdclk_get_vco(unsigned int freq)
5536{
5537 unsigned int i;
5538
5539 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5540 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5541
5542 if (e->freq == freq)
5543 return e->vco;
5544 }
5545
5546 return 8100;
5547}
5548
5549static void
5550skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5551{
5552 unsigned int min_freq;
5553 u32 val;
5554
5555 /* select the minimum CDCLK before enabling DPLL 0 */
5556 val = I915_READ(CDCLK_CTL);
5557 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5558 val |= CDCLK_FREQ_337_308;
5559
5560 if (required_vco == 8640)
5561 min_freq = 308570;
5562 else
5563 min_freq = 337500;
5564
5565 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5566
5567 I915_WRITE(CDCLK_CTL, val);
5568 POSTING_READ(CDCLK_CTL);
5569
5570 /*
5571 * We always enable DPLL0 with the lowest link rate possible, but still
5572 * taking into account the VCO required to operate the eDP panel at the
5573 * desired frequency. The usual DP link rates operate with a VCO of
5574 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5575 * The modeset code is responsible for the selection of the exact link
5576 * rate later on, with the constraint of choosing a frequency that
5577 * works with required_vco.
5578 */
5579 val = I915_READ(DPLL_CTRL1);
5580
5581 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5582 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5583 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5584 if (required_vco == 8640)
5585 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5586 SKL_DPLL0);
5587 else
5588 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5589 SKL_DPLL0);
5590
5591 I915_WRITE(DPLL_CTRL1, val);
5592 POSTING_READ(DPLL_CTRL1);
5593
5594 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5595
5596 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5597 DRM_ERROR("DPLL0 not locked\n");
5598}
5599
5600static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5601{
5602 int ret;
5603 u32 val;
5604
5605 /* inform PCU we want to change CDCLK */
5606 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5607 mutex_lock(&dev_priv->rps.hw_lock);
5608 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5609 mutex_unlock(&dev_priv->rps.hw_lock);
5610
5611 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5612}
5613
5614static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5615{
5616 unsigned int i;
5617
5618 for (i = 0; i < 15; i++) {
5619 if (skl_cdclk_pcu_ready(dev_priv))
5620 return true;
5621 udelay(10);
5622 }
5623
5624 return false;
5625}
5626
5627static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5628{
560a7ae4 5629 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5630 u32 freq_select, pcu_ack;
5631
5632 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5633
5634 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5635 DRM_ERROR("failed to inform PCU about cdclk change\n");
5636 return;
5637 }
5638
5639 /* set CDCLK_CTL */
5640 switch(freq) {
5641 case 450000:
5642 case 432000:
5643 freq_select = CDCLK_FREQ_450_432;
5644 pcu_ack = 1;
5645 break;
5646 case 540000:
5647 freq_select = CDCLK_FREQ_540;
5648 pcu_ack = 2;
5649 break;
5650 case 308570:
5651 case 337500:
5652 default:
5653 freq_select = CDCLK_FREQ_337_308;
5654 pcu_ack = 0;
5655 break;
5656 case 617140:
5657 case 675000:
5658 freq_select = CDCLK_FREQ_675_617;
5659 pcu_ack = 3;
5660 break;
5661 }
5662
5663 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5664 POSTING_READ(CDCLK_CTL);
5665
5666 /* inform PCU of the change */
5667 mutex_lock(&dev_priv->rps.hw_lock);
5668 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5669 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5670
5671 intel_update_cdclk(dev);
5d96d8af
DL		 5672}
5673
5674void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5675{
5676 /* disable DBUF power */
5677 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5678 POSTING_READ(DBUF_CTL);
5679
5680 udelay(10);
5681
5682 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5683 DRM_ERROR("DBuf power disable timeout\n");
5684
4e961e42
AM		 5685 /*
5686 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5687 */
5688 if (dev_priv->csr.dmc_payload) {
5689 /* disable DPLL0 */
5690 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5691 ~LCPLL_PLL_ENABLE);
5692 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5693 DRM_ERROR("Couldn't disable DPLL0\n");
5694 }
5d96d8af
DL		 5695
5696 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5697}
5698
5699void skl_init_cdclk(struct drm_i915_private *dev_priv)
5700{
5701 u32 val;
5702 unsigned int required_vco;
5703
5704 /* enable PCH reset handshake */
5705 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5706 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5707
5708 /* enable PG1 and Misc I/O */
5709 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5710
39d9b85a
GW		 5711 /* DPLL0 not enabled (happens on early BIOS versions) */
5712 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5713 /* enable DPLL0 */
5714 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5715 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5716 }
5717
5d96d8af
DL		 5718 /* set CDCLK to the frequency the BIOS chose */
5719 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5720
5721 /* enable DBUF power */
5722 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5723 POSTING_READ(DBUF_CTL);
5724
5725 udelay(10);
5726
5727 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5728 DRM_ERROR("DBuf power enable timeout\n");
5729}
5730
c73666f3
SK		 5731int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5732{
5733 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5734 uint32_t cdctl = I915_READ(CDCLK_CTL);
5735 int freq = dev_priv->skl_boot_cdclk;
5736
5737 /* Is PLL enabled and locked ? */
5738 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5739 goto sanitize;
5740
5741 /* DPLL okay; verify the cdclock
5742 *
5743 * Noticed in some instances that the freq selection is correct but
5744 * decimal part is programmed wrong from BIOS where pre-os does not
5745 * enable display. Verify the same as well.
5746 */
5747 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5748 /* All well; nothing to sanitize */
5749 return false;
5750sanitize:
5751 /*
5752 * As of now initialize with max cdclk till
5753 * we get dynamic cdclk support
5754 * */
5755 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5756 skl_init_cdclk(dev_priv);
5757
5758 /* we did have to sanitize */
5759 return true;
5760}
5761
30a970c6
JB		 5762/* Adjust CDclk dividers to allow high res or save power if possible */
5763static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5764{
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 u32 val, cmd;
5767
164dfd28
VK		 5768 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5769 != dev_priv->cdclk_freq);
d60c4473 5770
dfcab17e 5771 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5772 cmd = 2;
dfcab17e 5773 else if (cdclk == 266667)
30a970c6
JB		 5774 cmd = 1;
5775 else
5776 cmd = 0;
5777
5778 mutex_lock(&dev_priv->rps.hw_lock);
5779 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5780 val &= ~DSPFREQGUAR_MASK;
5781 val |= (cmd << DSPFREQGUAR_SHIFT);
5782 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5783 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5784 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5785 50)) {
5786 DRM_ERROR("timed out waiting for CDclk change\n");
5787 }
5788 mutex_unlock(&dev_priv->rps.hw_lock);
5789
54433e91
VS		 5790 mutex_lock(&dev_priv->sb_lock);
5791
dfcab17e 5792 if (cdclk == 400000) {
6bcda4f0 5793 u32 divider;
30a970c6 5794
6bcda4f0 5795 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5796
30a970c6
JB		 5797 /* adjust cdclk divider */
5798 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
87d5d259 5799 val &= ~CCK_FREQUENCY_VALUES;
30a970c6
JB		 5800 val |= divider;
5801 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5802
5803 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
87d5d259 5804 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
a877e801
VS		 5805 50))
5806 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5807 }
5808
30a970c6
JB		 5809 /* adjust self-refresh exit latency value */
5810 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5811 val &= ~0x7f;
5812
5813 /*
5814 * For high bandwidth configs, we set a higher latency in the bunit
5815 * so that the core display fetch happens in time to avoid underruns.
5816 */
dfcab17e 5817 if (cdclk == 400000)
30a970c6
JB		 5818 val |= 4500 / 250; /* 4.5 usec */
5819 else
5820 val |= 3000 / 250; /* 3.0 usec */
5821 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5822
a580516d 5823 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5824
b6283055 5825 intel_update_cdclk(dev);
30a970c6
JB		 5826}
5827
383c5a6a
VS		 5828static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5829{
5830 struct drm_i915_private *dev_priv = dev->dev_private;
5831 u32 val, cmd;
5832
164dfd28
VK		 5833 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5834 != dev_priv->cdclk_freq);
383c5a6a
VS		 5835
5836 switch (cdclk) {
383c5a6a
VS		 5837 case 333333:
5838 case 320000:
383c5a6a 5839 case 266667:
383c5a6a 5840 case 200000:
383c5a6a
VS		 5841 break;
5842 default:
5f77eeb0 5843 MISSING_CASE(cdclk);
383c5a6a
VS		 5844 return;
5845 }
5846
9d0d3fda
VS		 5847 /*
5848 * Specs are full of misinformation, but testing on actual
5849 * hardware has shown that we just need to write the desired
5850 * CCK divider into the Punit register.
5851 */
5852 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5853
383c5a6a
VS		 5854 mutex_lock(&dev_priv->rps.hw_lock);
5855 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5856 val &= ~DSPFREQGUAR_MASK_CHV;
5857 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5858 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5859 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5860 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5861 50)) {
5862 DRM_ERROR("timed out waiting for CDclk change\n");
5863 }
5864 mutex_unlock(&dev_priv->rps.hw_lock);
5865
b6283055 5866 intel_update_cdclk(dev);
383c5a6a
VS		 5867}
5868
30a970c6
JB		 5869static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5870 int max_pixclk)
5871{
6bcda4f0 5872 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5873 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5874
30a970c6
JB		 5875 /*
5876 * Really only a few cases to deal with, as only 4 CDclks are supported:
5877 * 200MHz
5878 * 267MHz
29dc7ef3 5879 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5880 * 400MHz (VLV only)
5881 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5882 * of the lower bin and adjust if needed.
e37c67a1
VS		 5883 *
5884 * We seem to get an unstable or solid color picture at 200MHz.
5885 * Not sure what's wrong. For now use 200MHz only when all pipes
5886 * are off.
30a970c6 5887 */
6cca3195
VS		 5888 if (!IS_CHERRYVIEW(dev_priv) &&
5889 max_pixclk > freq_320*limit/100)
dfcab17e 5890 return 400000;
6cca3195 5891 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5892 return freq_320;
e37c67a1 5893 else if (max_pixclk > 0)
dfcab17e 5894 return 266667;
e37c67a1
VS		 5895 else
5896 return 200000;
30a970c6
JB		 5897}
5898
f8437dd1
VK		 5899static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5900 int max_pixclk)
5901{
5902 /*
5903 * FIXME:
5904 * - remove the guardband, it's not needed on BXT
5905 * - set 19.2MHz bypass frequency if there are no active pipes
5906 */
5907 if (max_pixclk > 576000*9/10)
5908 return 624000;
5909 else if (max_pixclk > 384000*9/10)
5910 return 576000;
5911 else if (max_pixclk > 288000*9/10)
5912 return 384000;
5913 else if (max_pixclk > 144000*9/10)
5914 return 288000;
5915 else
5916 return 144000;
5917}
5918
a821fc46
ACO		 5919/* Compute the max pixel clock for new configuration. Uses atomic state if
5920 * that's non-NULL, look at current state otherwise. */
5921static int intel_mode_max_pixclk(struct drm_device *dev,
5922 struct drm_atomic_state *state)
30a970c6 5923{
30a970c6 5924 struct intel_crtc *intel_crtc;
304603f4 5925 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5926 int max_pixclk = 0;
5927
d3fcc808 5928 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5929 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5930 if (IS_ERR(crtc_state))
5931 return PTR_ERR(crtc_state);
5932
5933 if (!crtc_state->base.enable)
5934 continue;
5935
5936 max_pixclk = max(max_pixclk,
5937 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5938 }
5939
5940 return max_pixclk;
5941}
5942
27c329ed 5943static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5944{
27c329ed
ML		 5945 struct drm_device *dev = state->dev;
5946 struct drm_i915_private *dev_priv = dev->dev_private;
5947 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5948
304603f4
ACO		 5949 if (max_pixclk < 0)
5950 return max_pixclk;
30a970c6 5951
27c329ed
ML		 5952 to_intel_atomic_state(state)->cdclk =
5953 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5954
27c329ed
ML		 5955 return 0;
5956}
304603f4 5957
27c329ed
ML		 5958static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5959{
5960 struct drm_device *dev = state->dev;
5961 struct drm_i915_private *dev_priv = dev->dev_private;
5962 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5963
27c329ed
ML		 5964 if (max_pixclk < 0)
5965 return max_pixclk;
85a96e7a 5966
27c329ed
ML		 5967 to_intel_atomic_state(state)->cdclk =
5968 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5969
27c329ed 5970 return 0;
30a970c6
JB		 5971}
5972
1e69cd74
VS		 5973static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5974{
5975 unsigned int credits, default_credits;
5976
5977 if (IS_CHERRYVIEW(dev_priv))
5978 default_credits = PFI_CREDIT(12);
5979 else
5980 default_credits = PFI_CREDIT(8);
5981
bfa7df01 5982 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
1e69cd74
VS		 5983 /* CHV suggested value is 31 or 63 */
5984 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5985 credits = PFI_CREDIT_63;
1e69cd74
VS		 5986 else
5987 credits = PFI_CREDIT(15);
5988 } else {
5989 credits = default_credits;
5990 }
5991
5992 /*
5993 * WA - write default credits before re-programming
5994 * FIXME: should we also set the resend bit here?
5995 */
5996 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5997 default_credits);
5998
5999 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6000 credits | PFI_CREDIT_RESEND);
6001
6002 /*
6003 * FIXME is this guaranteed to clear
6004 * immediately or should we poll for it?
6005 */
6006 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6007}
6008
27c329ed 6009static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 6010{
a821fc46 6011 struct drm_device *dev = old_state->dev;
27c329ed 6012 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 6013 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 6014
27c329ed
ML		 6015 /*
6016 * FIXME: We can end up here with all power domains off, yet
6017 * with a CDCLK frequency other than the minimum. To account
6018 * for this take the PIPE-A power domain, which covers the HW
6019 * blocks needed for the following programming. This can be
6020 * removed once it's guaranteed that we get here either with
6021 * the minimum CDCLK set, or the required power domains
6022 * enabled.
6023 */
6024 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6025
27c329ed
ML		 6026 if (IS_CHERRYVIEW(dev))
6027 cherryview_set_cdclk(dev, req_cdclk);
6028 else
6029 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6030
27c329ed 6031 vlv_program_pfi_credits(dev_priv);
1e69cd74 6032
27c329ed 6033 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6034}
6035
89b667f8
JB		 6036static void valleyview_crtc_enable(struct drm_crtc *crtc)
6037{
6038 struct drm_device *dev = crtc->dev;
a72e4c9f 6039 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6041 struct intel_encoder *encoder;
6042 int pipe = intel_crtc->pipe;
23538ef1 6043 bool is_dsi;
89b667f8 6044
53d9f4e9 6045 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6046 return;
6047
409ee761 6048 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6049
6e3c9717 6050 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6051 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6052
6053 intel_set_pipe_timings(intel_crtc);
6054
c14b0485
VS		 6055 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6056 struct drm_i915_private *dev_priv = dev->dev_private;
6057
6058 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6059 I915_WRITE(CHV_CANVAS(pipe), 0);
6060 }
6061
5b18e57c
DV		 6062 i9xx_set_pipeconf(intel_crtc);
6063
89b667f8 6064 intel_crtc->active = true;
89b667f8 6065
a72e4c9f 6066 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6067
89b667f8
JB		 6068 for_each_encoder_on_crtc(dev, crtc, encoder)
6069 if (encoder->pre_pll_enable)
6070 encoder->pre_pll_enable(encoder);
6071
9d556c99 6072 if (!is_dsi) {
c0b4c660
VS		 6073 if (IS_CHERRYVIEW(dev)) {
6074 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6075 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6076 } else {
6077 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6078 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6079 }
9d556c99 6080 }
89b667f8
JB		 6081
6082 for_each_encoder_on_crtc(dev, crtc, encoder)
6083 if (encoder->pre_enable)
6084 encoder->pre_enable(encoder);
6085
2dd24552
JB		 6086 i9xx_pfit_enable(intel_crtc);
6087
63cbb074
VS		 6088 intel_crtc_load_lut(crtc);
6089
e1fdc473 6090 intel_enable_pipe(intel_crtc);
be6a6f8e 6091
4b3a9526
VS		 6092 assert_vblank_disabled(crtc);
6093 drm_crtc_vblank_on(crtc);
6094
f9b61ff6
DV		 6095 for_each_encoder_on_crtc(dev, crtc, encoder)
6096 encoder->enable(encoder);
89b667f8
JB		 6097}
6098
f13c2ef3
DV		 6099static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6100{
6101 struct drm_device *dev = crtc->base.dev;
6102 struct drm_i915_private *dev_priv = dev->dev_private;
6103
6e3c9717
ACO		 6104 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6105 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6106}
6107
0b8765c6 6108static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6109{
6110 struct drm_device *dev = crtc->dev;
a72e4c9f 6111 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6113 struct intel_encoder *encoder;
79e53945 6114 int pipe = intel_crtc->pipe;
79e53945 6115
53d9f4e9 6116 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6117 return;
6118
f13c2ef3
DV		 6119 i9xx_set_pll_dividers(intel_crtc);
6120
6e3c9717 6121 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6122 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6123
6124 intel_set_pipe_timings(intel_crtc);
6125
5b18e57c
DV		 6126 i9xx_set_pipeconf(intel_crtc);
6127
f7abfe8b 6128 intel_crtc->active = true;
6b383a7f 6129
4a3436e8 6130 if (!IS_GEN2(dev))
a72e4c9f 6131 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6132
9d6d9f19
MK		 6133 for_each_encoder_on_crtc(dev, crtc, encoder)
6134 if (encoder->pre_enable)
6135 encoder->pre_enable(encoder);
6136
f6736a1a
DV		 6137 i9xx_enable_pll(intel_crtc);
6138
2dd24552
JB		 6139 i9xx_pfit_enable(intel_crtc);
6140
63cbb074
VS		 6141 intel_crtc_load_lut(crtc);
6142
f37fcc2a 6143 intel_update_watermarks(crtc);
e1fdc473 6144 intel_enable_pipe(intel_crtc);
be6a6f8e 6145
4b3a9526
VS		 6146 assert_vblank_disabled(crtc);
6147 drm_crtc_vblank_on(crtc);
6148
f9b61ff6
DV		 6149 for_each_encoder_on_crtc(dev, crtc, encoder)
6150 encoder->enable(encoder);
0b8765c6 6151}
79e53945 6152
87476d63
DV		 6153static void i9xx_pfit_disable(struct intel_crtc *crtc)
6154{
6155 struct drm_device *dev = crtc->base.dev;
6156 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6157
6e3c9717 6158 if (!crtc->config->gmch_pfit.control)
328d8e82 6159 return;
87476d63 6160
328d8e82 6161 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6162
328d8e82
DV		 6163 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6164 I915_READ(PFIT_CONTROL));
6165 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6166}
6167
0b8765c6
JB		 6168static void i9xx_crtc_disable(struct drm_crtc *crtc)
6169{
6170 struct drm_device *dev = crtc->dev;
6171 struct drm_i915_private *dev_priv = dev->dev_private;
6172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6173 struct intel_encoder *encoder;
0b8765c6 6174 int pipe = intel_crtc->pipe;
ef9c3aee 6175
6304cd91
VS		 6176 /*
6177 * On gen2 planes are double buffered but the pipe isn't, so we must
6178 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6179 * We also need to wait on all gmch platforms because of the
6180 * self-refresh mode constraint explained above.
6304cd91 6181 */
564ed191 6182 intel_wait_for_vblank(dev, pipe);
6304cd91 6183
4b3a9526
VS		 6184 for_each_encoder_on_crtc(dev, crtc, encoder)
6185 encoder->disable(encoder);
6186
f9b61ff6
DV		 6187 drm_crtc_vblank_off(crtc);
6188 assert_vblank_disabled(crtc);
6189
575f7ab7 6190 intel_disable_pipe(intel_crtc);
24a1f16d 6191
87476d63 6192 i9xx_pfit_disable(intel_crtc);
24a1f16d 6193
89b667f8
JB		 6194 for_each_encoder_on_crtc(dev, crtc, encoder)
6195 if (encoder->post_disable)
6196 encoder->post_disable(encoder);
6197
409ee761 6198 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6199 if (IS_CHERRYVIEW(dev))
6200 chv_disable_pll(dev_priv, pipe);
6201 else if (IS_VALLEYVIEW(dev))
6202 vlv_disable_pll(dev_priv, pipe);
6203 else
1c4e0274 6204 i9xx_disable_pll(intel_crtc);
076ed3b2 6205 }
0b8765c6 6206
d6db995f
VS		 6207 for_each_encoder_on_crtc(dev, crtc, encoder)
6208 if (encoder->post_pll_disable)
6209 encoder->post_pll_disable(encoder);
6210
4a3436e8 6211 if (!IS_GEN2(dev))
a72e4c9f 6212 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6213}
6214
b17d48e2
ML		 6215static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6216{
6217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6218 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6219 enum intel_display_power_domain domain;
6220 unsigned long domains;
6221
6222 if (!intel_crtc->active)
6223 return;
6224
a539205a 6225 if (to_intel_plane_state(crtc->primary->state)->visible) {
fc32b1fd
ML		 6226 WARN_ON(intel_crtc->unpin_work);
6227
a539205a
ML		 6228 intel_pre_disable_primary(crtc);
6229 }
6230
d032ffa0 6231 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6232 dev_priv->display.crtc_disable(crtc);
37d9078b
MR		 6233 intel_crtc->active = false;
6234 intel_update_watermarks(crtc);
1f7457b1 6235 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6236
6237 domains = intel_crtc->enabled_power_domains;
6238 for_each_power_domain(domain, domains)
6239 intel_display_power_put(dev_priv, domain);
6240 intel_crtc->enabled_power_domains = 0;
6241}
6242
6b72d486
ML		 6243/*
6244 * turn all crtc's off, but do not adjust state
6245 * This has to be paired with a call to intel_modeset_setup_hw_state.
6246 */
70e0bd74 6247int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6248{
70e0bd74
ML		 6249 struct drm_mode_config *config = &dev->mode_config;
6250 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6251 struct drm_atomic_state *state;
6b72d486 6252 struct drm_crtc *crtc;
70e0bd74
ML		 6253 unsigned crtc_mask = 0;
6254 int ret = 0;
6255
6256 if (WARN_ON(!ctx))
6257 return 0;
6258
6259 lockdep_assert_held(&ctx->ww_ctx);
6260 state = drm_atomic_state_alloc(dev);
6261 if (WARN_ON(!state))
6262 return -ENOMEM;
6263
6264 state->acquire_ctx = ctx;
6265 state->allow_modeset = true;
6266
6267 for_each_crtc(dev, crtc) {
6268 struct drm_crtc_state *crtc_state =
6269 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6270
70e0bd74
ML		 6271 ret = PTR_ERR_OR_ZERO(crtc_state);
6272 if (ret)
6273 goto free;
6274
6275 if (!crtc_state->active)
6276 continue;
6277
6278 crtc_state->active = false;
6279 crtc_mask |= 1 << drm_crtc_index(crtc);
6280 }
6281
6282 if (crtc_mask) {
74c090b1 6283 ret = drm_atomic_commit(state);
70e0bd74
ML		 6284
6285 if (!ret) {
6286 for_each_crtc(dev, crtc)
6287 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6288 crtc->state->active = true;
6289
6290 return ret;
6291 }
6292 }
6293
6294free:
6295 if (ret)
6296 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6297 drm_atomic_state_free(state);
6298 return ret;
ee7b9f93
JB		 6299}
6300
ea5b213a 6301void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6302{
4ef69c7a 6303 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6304
ea5b213a
CW		 6305 drm_encoder_cleanup(encoder);
6306 kfree(intel_encoder);
7e7d76c3
JB		 6307}
6308
0a91ca29
DV		 6309/* Cross check the actual hw state with our own modeset state tracking (and it's
6310 * internal consistency). */
b980514c 6311static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6312{
35dd3c64
ML		 6313 struct drm_crtc *crtc = connector->base.state->crtc;
6314
6315 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6316 connector->base.base.id,
6317 connector->base.name);
6318
0a91ca29 6319 if (connector->get_hw_state(connector)) {
e85376cb 6320 struct intel_encoder *encoder = connector->encoder;
35dd3c64 6321 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6322
35dd3c64
ML		 6323 I915_STATE_WARN(!crtc,
6324 "connector enabled without attached crtc\n");
0a91ca29 6325
35dd3c64
ML		 6326 if (!crtc)
6327 return;
6328
6329 I915_STATE_WARN(!crtc->state->active,
6330 "connector is active, but attached crtc isn't\n");
6331
e85376cb 6332 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
35dd3c64
ML		 6333 return;
6334
e85376cb 6335 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
35dd3c64
ML		 6336 "atomic encoder doesn't match attached encoder\n");
6337
e85376cb 6338 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
35dd3c64
ML		 6339 "attached encoder crtc differs from connector crtc\n");
6340 } else {
4d688a2a
ML		 6341 I915_STATE_WARN(crtc && crtc->state->active,
6342 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6343 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6344 "best encoder set without crtc!\n");
0a91ca29 6345 }
79e53945
JB		 6346}
6347
08d9bc92
ACO		 6348int intel_connector_init(struct intel_connector *connector)
6349{
6350 struct drm_connector_state *connector_state;
6351
6352 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6353 if (!connector_state)
6354 return -ENOMEM;
6355
6356 connector->base.state = connector_state;
6357 return 0;
6358}
6359
6360struct intel_connector *intel_connector_alloc(void)
6361{
6362 struct intel_connector *connector;
6363
6364 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6365 if (!connector)
6366 return NULL;
6367
6368 if (intel_connector_init(connector) < 0) {
6369 kfree(connector);
6370 return NULL;
6371 }
6372
6373 return connector;
6374}
6375
f0947c37
DV		 6376/* Simple connector->get_hw_state implementation for encoders that support only
6377 * one connector and no cloning and hence the encoder state determines the state
6378 * of the connector. */
6379bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6380{
24929352 6381 enum pipe pipe = 0;
f0947c37 6382 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6383
f0947c37 6384 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6385}
6386
6d293983 6387static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6388{
6d293983
ACO		 6389 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6390 return crtc_state->fdi_lanes;
d272ddfa
VS		 6391
6392 return 0;
6393}
6394
6d293983 6395static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6396 struct intel_crtc_state *pipe_config)
1857e1da 6397{
6d293983
ACO		 6398 struct drm_atomic_state *state = pipe_config->base.state;
6399 struct intel_crtc *other_crtc;
6400 struct intel_crtc_state *other_crtc_state;
6401
1857e1da
DV		 6402 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6403 pipe_name(pipe), pipe_config->fdi_lanes);
6404 if (pipe_config->fdi_lanes > 4) {
6405 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6406 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6407 return -EINVAL;
1857e1da
DV		 6408 }
6409
bafb6553 6410 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6411 if (pipe_config->fdi_lanes > 2) {
6412 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6413 pipe_config->fdi_lanes);
6d293983 6414 return -EINVAL;
1857e1da 6415 } else {
6d293983 6416 return 0;
1857e1da
DV		 6417 }
6418 }
6419
6420 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6421 return 0;
1857e1da
DV		 6422
6423 /* Ivybridge 3 pipe is really complicated */
6424 switch (pipe) {
6425 case PIPE_A:
6d293983 6426 return 0;
1857e1da 6427 case PIPE_B:
6d293983
ACO		 6428 if (pipe_config->fdi_lanes <= 2)
6429 return 0;
6430
6431 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6432 other_crtc_state =
6433 intel_atomic_get_crtc_state(state, other_crtc);
6434 if (IS_ERR(other_crtc_state))
6435 return PTR_ERR(other_crtc_state);
6436
6437 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6438 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6439 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6440 return -EINVAL;
1857e1da 6441 }
6d293983 6442 return 0;
1857e1da 6443 case PIPE_C:
251cc67c
VS		 6444 if (pipe_config->fdi_lanes > 2) {
6445 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6446 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6447 return -EINVAL;
251cc67c 6448 }
6d293983
ACO		 6449
6450 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6451 other_crtc_state =
6452 intel_atomic_get_crtc_state(state, other_crtc);
6453 if (IS_ERR(other_crtc_state))
6454 return PTR_ERR(other_crtc_state);
6455
6456 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6457 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6458 return -EINVAL;
1857e1da 6459 }
6d293983 6460 return 0;
1857e1da
DV		 6461 default:
6462 BUG();
6463 }
6464}
6465
e29c22c0
DV		 6466#define RETRY 1
6467static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6468 struct intel_crtc_state *pipe_config)
877d48d5 6469{
1857e1da 6470 struct drm_device *dev = intel_crtc->base.dev;
7c5f93b0 6471 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6472 int lane, link_bw, fdi_dotclock, ret;
6473 bool needs_recompute = false;
877d48d5 6474
e29c22c0 6475retry:
877d48d5
DV		 6476 /* FDI is a binary signal running at ~2.7GHz, encoding
6477 * each output octet as 10 bits. The actual frequency
6478 * is stored as a divider into a 100MHz clock, and the
6479 * mode pixel clock is stored in units of 1KHz.
6480 * Hence the bw of each lane in terms of the mode signal
6481 * is:
6482 */
6483 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6484
241bfc38 6485 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6486
2bd89a07 6487 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6488 pipe_config->pipe_bpp);
6489
6490 pipe_config->fdi_lanes = lane;
6491
2bd89a07 6492 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6493 link_bw, &pipe_config->fdi_m_n);
1857e1da 6494
6d293983
ACO		 6495 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6496 intel_crtc->pipe, pipe_config);
6497 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6498 pipe_config->pipe_bpp -= 2*3;
6499 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6500 pipe_config->pipe_bpp);
6501 needs_recompute = true;
6502 pipe_config->bw_constrained = true;
6503
6504 goto retry;
6505 }
6506
6507 if (needs_recompute)
6508 return RETRY;
6509
6d293983 6510 return ret;
877d48d5
DV		 6511}
6512
8cfb3407
VS		 6513static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6514 struct intel_crtc_state *pipe_config)
6515{
6516 if (pipe_config->pipe_bpp > 24)
6517 return false;
6518
6519 /* HSW can handle pixel rate up to cdclk? */
6520 if (IS_HASWELL(dev_priv->dev))
6521 return true;
6522
6523 /*
b432e5cf
VS		 6524 * We compare against max which means we must take
6525 * the increased cdclk requirement into account when
6526 * calculating the new cdclk.
6527 *
6528 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6529 */
6530 return ilk_pipe_pixel_rate(pipe_config) <=
6531 dev_priv->max_cdclk_freq * 95 / 100;
6532}
6533
42db64ef 6534static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6535 struct intel_crtc_state *pipe_config)
42db64ef 6536{
8cfb3407
VS		 6537 struct drm_device *dev = crtc->base.dev;
6538 struct drm_i915_private *dev_priv = dev->dev_private;
6539
d330a953 6540 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6541 hsw_crtc_supports_ips(crtc) &&
6542 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6543}
6544
a43f6e0f 6545static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6546 struct intel_crtc_state *pipe_config)
79e53945 6547{
a43f6e0f 6548 struct drm_device *dev = crtc->base.dev;
8bd31e67 6549 struct drm_i915_private *dev_priv = dev->dev_private;
7c5f93b0 6550 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6551
ad3a4479 6552 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6553 if (INTEL_INFO(dev)->gen < 4) {
44913155 6554 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6555
6556 /*
6557 * Enable pixel doubling when the dot clock
6558 * is > 90% of the (display) core speed.
6559 *
b397c96b
VS		 6560 * GDG double wide on either pipe,
6561 * otherwise pipe A only.
cf532bb2 6562 */
b397c96b 6563 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6564 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6565 clock_limit *= 2;
cf532bb2 6566 pipe_config->double_wide = true;
ad3a4479
VS		 6567 }
6568
241bfc38 6569 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6570 return -EINVAL;
2c07245f 6571 }
89749350 6572
1d1d0e27
VS		 6573 /*
6574 * Pipe horizontal size must be even in:
6575 * - DVO ganged mode
6576 * - LVDS dual channel mode
6577 * - Double wide pipe
6578 */
a93e255f 6579 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6580 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6581 pipe_config->pipe_src_w &= ~1;
6582
8693a824
DL		 6583 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6584 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6585 */
6586 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
aad941d5 6587 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
e29c22c0 6588 return -EINVAL;
44f46b42 6589
f5adf94e 6590 if (HAS_IPS(dev))
a43f6e0f
DV		 6591 hsw_compute_ips_config(crtc, pipe_config);
6592
877d48d5 6593 if (pipe_config->has_pch_encoder)
a43f6e0f 6594 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6595
cf5a15be 6596 return 0;
79e53945
JB		 6597}
6598
1652d19e
VS		 6599static int skylake_get_display_clock_speed(struct drm_device *dev)
6600{
6601 struct drm_i915_private *dev_priv = to_i915(dev);
6602 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6603 uint32_t cdctl = I915_READ(CDCLK_CTL);
6604 uint32_t linkrate;
6605
414355a7 6606 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6607 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6608
6609 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6610 return 540000;
6611
6612 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6613 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6614
71cd8423
DL		 6615 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6616 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6617 /* vco 8640 */
6618 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6619 case CDCLK_FREQ_450_432:
6620 return 432000;
6621 case CDCLK_FREQ_337_308:
6622 return 308570;
6623 case CDCLK_FREQ_675_617:
6624 return 617140;
6625 default:
6626 WARN(1, "Unknown cd freq selection\n");
6627 }
6628 } else {
6629 /* vco 8100 */
6630 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6631 case CDCLK_FREQ_450_432:
6632 return 450000;
6633 case CDCLK_FREQ_337_308:
6634 return 337500;
6635 case CDCLK_FREQ_675_617:
6636 return 675000;
6637 default:
6638 WARN(1, "Unknown cd freq selection\n");
6639 }
6640 }
6641
6642 /* error case, do as if DPLL0 isn't enabled */
6643 return 24000;
6644}
6645
acd3f3d3
BP		 6646static int broxton_get_display_clock_speed(struct drm_device *dev)
6647{
6648 struct drm_i915_private *dev_priv = to_i915(dev);
6649 uint32_t cdctl = I915_READ(CDCLK_CTL);
6650 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6651 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6652 int cdclk;
6653
6654 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6655 return 19200;
6656
6657 cdclk = 19200 * pll_ratio / 2;
6658
6659 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6660 case BXT_CDCLK_CD2X_DIV_SEL_1:
6661 return cdclk; /* 576MHz or 624MHz */
6662 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6663 return cdclk * 2 / 3; /* 384MHz */
6664 case BXT_CDCLK_CD2X_DIV_SEL_2:
6665 return cdclk / 2; /* 288MHz */
6666 case BXT_CDCLK_CD2X_DIV_SEL_4:
6667 return cdclk / 4; /* 144MHz */
6668 }
6669
6670 /* error case, do as if DE PLL isn't enabled */
6671 return 19200;
6672}
6673
1652d19e
VS		 6674static int broadwell_get_display_clock_speed(struct drm_device *dev)
6675{
6676 struct drm_i915_private *dev_priv = dev->dev_private;
6677 uint32_t lcpll = I915_READ(LCPLL_CTL);
6678 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6679
6680 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6681 return 800000;
6682 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6683 return 450000;
6684 else if (freq == LCPLL_CLK_FREQ_450)
6685 return 450000;
6686 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6687 return 540000;
6688 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6689 return 337500;
6690 else
6691 return 675000;
6692}
6693
6694static int haswell_get_display_clock_speed(struct drm_device *dev)
6695{
6696 struct drm_i915_private *dev_priv = dev->dev_private;
6697 uint32_t lcpll = I915_READ(LCPLL_CTL);
6698 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6699
6700 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6701 return 800000;
6702 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6703 return 450000;
6704 else if (freq == LCPLL_CLK_FREQ_450)
6705 return 450000;
6706 else if (IS_HSW_ULT(dev))
6707 return 337500;
6708 else
6709 return 540000;
79e53945
JB		 6710}
6711
25eb05fc
JB		 6712static int valleyview_get_display_clock_speed(struct drm_device *dev)
6713{
bfa7df01
VS		 6714 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6715 CCK_DISPLAY_CLOCK_CONTROL);
25eb05fc
JB		 6716}
6717
b37a6434
VS		 6718static int ilk_get_display_clock_speed(struct drm_device *dev)
6719{
6720 return 450000;
6721}
6722
e70236a8
JB		 6723static int i945_get_display_clock_speed(struct drm_device *dev)
6724{
6725 return 400000;
6726}
79e53945 6727
e70236a8 6728static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6729{
e907f170 6730 return 333333;
e70236a8 6731}
79e53945 6732
e70236a8
JB		 6733static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6734{
6735 return 200000;
6736}
79e53945 6737
257a7ffc
DV		 6738static int pnv_get_display_clock_speed(struct drm_device *dev)
6739{
6740 u16 gcfgc = 0;
6741
6742 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6743
6744 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6745 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6746 return 266667;
257a7ffc 6747 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6748 return 333333;
257a7ffc 6749 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6750 return 444444;
257a7ffc
DV		 6751 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6752 return 200000;
6753 default:
6754 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6755 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6756 return 133333;
257a7ffc 6757 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6758 return 166667;
257a7ffc
DV		 6759 }
6760}
6761
e70236a8
JB		 6762static int i915gm_get_display_clock_speed(struct drm_device *dev)
6763{
6764 u16 gcfgc = 0;
79e53945 6765
e70236a8
JB		 6766 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6767
6768 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6769 return 133333;
e70236a8
JB		 6770 else {
6771 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6772 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6773 return 333333;
e70236a8
JB		 6774 default:
6775 case GC_DISPLAY_CLOCK_190_200_MHZ:
6776 return 190000;
79e53945 6777 }
e70236a8
JB		 6778 }
6779}
6780
6781static int i865_get_display_clock_speed(struct drm_device *dev)
6782{
e907f170 6783 return 266667;
e70236a8
JB		 6784}
6785
1b1d2716 6786static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6787{
6788 u16 hpllcc = 0;
1b1d2716 6789
65cd2b3f
VS		 6790 /*
6791 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6792 * encoding is different :(
6793 * FIXME is this the right way to detect 852GM/852GMV?
6794 */
6795 if (dev->pdev->revision == 0x1)
6796 return 133333;
6797
1b1d2716
VS		 6798 pci_bus_read_config_word(dev->pdev->bus,
6799 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6800
e70236a8
JB		 6801 /* Assume that the hardware is in the high speed state. This
6802 * should be the default.
6803 */
6804 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6805 case GC_CLOCK_133_200:
1b1d2716 6806 case GC_CLOCK_133_200_2:
e70236a8
JB		 6807 case GC_CLOCK_100_200:
6808 return 200000;
6809 case GC_CLOCK_166_250:
6810 return 250000;
6811 case GC_CLOCK_100_133:
e907f170 6812 return 133333;
1b1d2716
VS		 6813 case GC_CLOCK_133_266:
6814 case GC_CLOCK_133_266_2:
6815 case GC_CLOCK_166_266:
6816 return 266667;
e70236a8 6817 }
79e53945 6818
e70236a8
JB		 6819 /* Shouldn't happen */
6820 return 0;
6821}
79e53945 6822
e70236a8
JB		 6823static int i830_get_display_clock_speed(struct drm_device *dev)
6824{
e907f170 6825 return 133333;
79e53945
JB		 6826}
6827
34edce2f
VS		 6828static unsigned int intel_hpll_vco(struct drm_device *dev)
6829{
6830 struct drm_i915_private *dev_priv = dev->dev_private;
6831 static const unsigned int blb_vco[8] = {
6832 [0] = 3200000,
6833 [1] = 4000000,
6834 [2] = 5333333,
6835 [3] = 4800000,
6836 [4] = 6400000,
6837 };
6838 static const unsigned int pnv_vco[8] = {
6839 [0] = 3200000,
6840 [1] = 4000000,
6841 [2] = 5333333,
6842 [3] = 4800000,
6843 [4] = 2666667,
6844 };
6845 static const unsigned int cl_vco[8] = {
6846 [0] = 3200000,
6847 [1] = 4000000,
6848 [2] = 5333333,
6849 [3] = 6400000,
6850 [4] = 3333333,
6851 [5] = 3566667,
6852 [6] = 4266667,
6853 };
6854 static const unsigned int elk_vco[8] = {
6855 [0] = 3200000,
6856 [1] = 4000000,
6857 [2] = 5333333,
6858 [3] = 4800000,
6859 };
6860 static const unsigned int ctg_vco[8] = {
6861 [0] = 3200000,
6862 [1] = 4000000,
6863 [2] = 5333333,
6864 [3] = 6400000,
6865 [4] = 2666667,
6866 [5] = 4266667,
6867 };
6868 const unsigned int *vco_table;
6869 unsigned int vco;
6870 uint8_t tmp = 0;
6871
6872 /* FIXME other chipsets? */
6873 if (IS_GM45(dev))
6874 vco_table = ctg_vco;
6875 else if (IS_G4X(dev))
6876 vco_table = elk_vco;
6877 else if (IS_CRESTLINE(dev))
6878 vco_table = cl_vco;
6879 else if (IS_PINEVIEW(dev))
6880 vco_table = pnv_vco;
6881 else if (IS_G33(dev))
6882 vco_table = blb_vco;
6883 else
6884 return 0;
6885
6886 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6887
6888 vco = vco_table[tmp & 0x7];
6889 if (vco == 0)
6890 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6891 else
6892 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6893
6894 return vco;
6895}
6896
6897static int gm45_get_display_clock_speed(struct drm_device *dev)
6898{
6899 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6900 uint16_t tmp = 0;
6901
6902 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6903
6904 cdclk_sel = (tmp >> 12) & 0x1;
6905
6906 switch (vco) {
6907 case 2666667:
6908 case 4000000:
6909 case 5333333:
6910 return cdclk_sel ? 333333 : 222222;
6911 case 3200000:
6912 return cdclk_sel ? 320000 : 228571;
6913 default:
6914 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6915 return 222222;
6916 }
6917}
6918
6919static int i965gm_get_display_clock_speed(struct drm_device *dev)
6920{
6921 static const uint8_t div_3200[] = { 16, 10, 8 };
6922 static const uint8_t div_4000[] = { 20, 12, 10 };
6923 static const uint8_t div_5333[] = { 24, 16, 14 };
6924 const uint8_t *div_table;
6925 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6926 uint16_t tmp = 0;
6927
6928 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6929
6930 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6931
6932 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6933 goto fail;
6934
6935 switch (vco) {
6936 case 3200000:
6937 div_table = div_3200;
6938 break;
6939 case 4000000:
6940 div_table = div_4000;
6941 break;
6942 case 5333333:
6943 div_table = div_5333;
6944 break;
6945 default:
6946 goto fail;
6947 }
6948
6949 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6950
caf4e252 6951fail:
34edce2f
VS		 6952 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6953 return 200000;
6954}
6955
6956static int g33_get_display_clock_speed(struct drm_device *dev)
6957{
6958 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6959 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6960 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6961 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6962 const uint8_t *div_table;
6963 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6964 uint16_t tmp = 0;
6965
6966 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6967
6968 cdclk_sel = (tmp >> 4) & 0x7;
6969
6970 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6971 goto fail;
6972
6973 switch (vco) {
6974 case 3200000:
6975 div_table = div_3200;
6976 break;
6977 case 4000000:
6978 div_table = div_4000;
6979 break;
6980 case 4800000:
6981 div_table = div_4800;
6982 break;
6983 case 5333333:
6984 div_table = div_5333;
6985 break;
6986 default:
6987 goto fail;
6988 }
6989
6990 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6991
caf4e252 6992fail:
34edce2f
VS		 6993 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6994 return 190476;
6995}
6996
2c07245f 6997static void
a65851af 6998intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6999{
a65851af
VS		 7000 while (*num > DATA_LINK_M_N_MASK ||
7001 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7002 *num >>= 1;
7003 *den >>= 1;
7004 }
7005}
7006
a65851af
VS		 7007static void compute_m_n(unsigned int m, unsigned int n,
7008 uint32_t *ret_m, uint32_t *ret_n)
7009{
7010 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7011 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7012 intel_reduce_m_n_ratio(ret_m, ret_n);
7013}
7014
e69d0bc1
DV		 7015void
7016intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7017 int pixel_clock, int link_clock,
7018 struct intel_link_m_n *m_n)
2c07245f 7019{
e69d0bc1 7020 m_n->tu = 64;
a65851af
VS		 7021
7022 compute_m_n(bits_per_pixel * pixel_clock,
7023 link_clock * nlanes * 8,
7024 &m_n->gmch_m, &m_n->gmch_n);
7025
7026 compute_m_n(pixel_clock, link_clock,
7027 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7028}
7029
a7615030
CW		 7030static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7031{
d330a953
JN		 7032 if (i915.panel_use_ssc >= 0)
7033 return i915.panel_use_ssc != 0;
41aa3448 7034 return dev_priv->vbt.lvds_use_ssc
435793df 7035 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7036}
7037
a93e255f
ACO		 7038static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7039 int num_connectors)
c65d77d8 7040{
a93e255f 7041 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7042 struct drm_i915_private *dev_priv = dev->dev_private;
7043 int refclk;
7044
a93e255f
ACO		 7045 WARN_ON(!crtc_state->base.state);
7046
5ab7b0b7 7047 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7048 refclk = 100000;
a93e255f 7049 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7050 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7051 refclk = dev_priv->vbt.lvds_ssc_freq;
7052 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7053 } else if (!IS_GEN2(dev)) {
7054 refclk = 96000;
7055 } else {
7056 refclk = 48000;
7057 }
7058
7059 return refclk;
7060}
7061
7429e9d4 7062static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7063{
7df00d7a 7064 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7065}
f47709a9 7066
7429e9d4
DV		 7067static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7068{
7069 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7070}
7071
f47709a9 7072static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7073 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7074 intel_clock_t *reduced_clock)
7075{
f47709a9 7076 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7077 u32 fp, fp2 = 0;
7078
7079 if (IS_PINEVIEW(dev)) {
190f68c5 7080 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7081 if (reduced_clock)
7429e9d4 7082 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7083 } else {
190f68c5 7084 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7085 if (reduced_clock)
7429e9d4 7086 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7087 }
7088
190f68c5 7089 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7090
f47709a9 7091 crtc->lowfreq_avail = false;
a93e255f 7092 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7093 reduced_clock) {
190f68c5 7094 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7095 crtc->lowfreq_avail = true;
a7516a05 7096 } else {
190f68c5 7097 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7098 }
7099}
7100
5e69f97f
CML		 7101static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7102 pipe)
89b667f8
JB		 7103{
7104 u32 reg_val;
7105
7106 /*
7107 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7108 * and set it to a reasonable value instead.
7109 */
ab3c759a 7110 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7111 reg_val &= 0xffffff00;
7112 reg_val |= 0x00000030;
ab3c759a 7113 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7114
ab3c759a 7115 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7116 reg_val &= 0x8cffffff;
7117 reg_val = 0x8c000000;
ab3c759a 7118 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7119
ab3c759a 7120 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7121 reg_val &= 0xffffff00;
ab3c759a 7122 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7123
ab3c759a 7124 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7125 reg_val &= 0x00ffffff;
7126 reg_val |= 0xb0000000;
ab3c759a 7127 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7128}
7129
b551842d
DV		 7130static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7131 struct intel_link_m_n *m_n)
7132{
7133 struct drm_device *dev = crtc->base.dev;
7134 struct drm_i915_private *dev_priv = dev->dev_private;
7135 int pipe = crtc->pipe;
7136
e3b95f1e
DV		 7137 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7138 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7139 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7140 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7141}
7142
7143static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7144 struct intel_link_m_n *m_n,
7145 struct intel_link_m_n *m2_n2)
b551842d
DV		 7146{
7147 struct drm_device *dev = crtc->base.dev;
7148 struct drm_i915_private *dev_priv = dev->dev_private;
7149 int pipe = crtc->pipe;
6e3c9717 7150 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7151
7152 if (INTEL_INFO(dev)->gen >= 5) {
7153 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7154 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7155 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7156 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7157 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7158 * for gen < 8) and if DRRS is supported (to make sure the
7159 * registers are not unnecessarily accessed).
7160 */
44395bfe 7161 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7162 crtc->config->has_drrs) {
f769cd24
VK		 7163 I915_WRITE(PIPE_DATA_M2(transcoder),
7164 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7165 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7166 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7167 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7168 }
b551842d 7169 } else {
e3b95f1e
DV		 7170 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7171 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7172 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7173 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7174 }
7175}
7176
fe3cd48d 7177void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7178{
fe3cd48d
R		 7179 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7180
7181 if (m_n == M1_N1) {
7182 dp_m_n = &crtc->config->dp_m_n;
7183 dp_m2_n2 = &crtc->config->dp_m2_n2;
7184 } else if (m_n == M2_N2) {
7185
7186 /*
7187 * M2_N2 registers are not supported. Hence m2_n2 divider value
7188 * needs to be programmed into M1_N1.
7189 */
7190 dp_m_n = &crtc->config->dp_m2_n2;
7191 } else {
7192 DRM_ERROR("Unsupported divider value\n");
7193 return;
7194 }
7195
6e3c9717
ACO		 7196 if (crtc->config->has_pch_encoder)
7197 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7198 else
fe3cd48d 7199 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7200}
7201
251ac862
DV		 7202static void vlv_compute_dpll(struct intel_crtc *crtc,
7203 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7204{
7205 u32 dpll, dpll_md;
7206
7207 /*
7208 * Enable DPIO clock input. We should never disable the reference
7209 * clock for pipe B, since VGA hotplug / manual detection depends
7210 * on it.
7211 */
60bfe44f
VS		 7212 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7213 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7214 /* We should never disable this, set it here for state tracking */
7215 if (crtc->pipe == PIPE_B)
7216 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7217 dpll |= DPLL_VCO_ENABLE;
d288f65f 7218 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7219
d288f65f 7220 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7221 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7222 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7223}
7224
d288f65f 7225static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7226 const struct intel_crtc_state *pipe_config)
a0c4da24 7227{
f47709a9 7228 struct drm_device *dev = crtc->base.dev;
a0c4da24 7229 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7230 int pipe = crtc->pipe;
bdd4b6a6 7231 u32 mdiv;
a0c4da24 7232 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7233 u32 coreclk, reg_val;
a0c4da24 7234
a580516d 7235 mutex_lock(&dev_priv->sb_lock);
09153000 7236
d288f65f
VS		 7237 bestn = pipe_config->dpll.n;
7238 bestm1 = pipe_config->dpll.m1;
7239 bestm2 = pipe_config->dpll.m2;
7240 bestp1 = pipe_config->dpll.p1;
7241 bestp2 = pipe_config->dpll.p2;
a0c4da24 7242
89b667f8
JB		 7243 /* See eDP HDMI DPIO driver vbios notes doc */
7244
7245 /* PLL B needs special handling */
bdd4b6a6 7246 if (pipe == PIPE_B)
5e69f97f 7247 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7248
7249 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7250 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7251
7252 /* Disable target IRef on PLL */
ab3c759a 7253 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7254 reg_val &= 0x00ffffff;
ab3c759a 7255 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7256
7257 /* Disable fast lock */
ab3c759a 7258 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7259
7260 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7261 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7262 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7263 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7264 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7265
7266 /*
7267 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7268 * but we don't support that).
7269 * Note: don't use the DAC post divider as it seems unstable.
7270 */
7271 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7272 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7273
a0c4da24 7274 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7276
89b667f8 7277 /* Set HBR and RBR LPF coefficients */
d288f65f 7278 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7279 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7280 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7281 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7282 0x009f0003);
89b667f8 7283 else
ab3c759a 7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7285 0x00d0000f);
7286
681a8504 7287 if (pipe_config->has_dp_encoder) {
89b667f8 7288 /* Use SSC source */
bdd4b6a6 7289 if (pipe == PIPE_A)
ab3c759a 7290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7291 0x0df40000);
7292 else
ab3c759a 7293 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7294 0x0df70000);
7295 } else { /* HDMI or VGA */
7296 /* Use bend source */
bdd4b6a6 7297 if (pipe == PIPE_A)
ab3c759a 7298 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7299 0x0df70000);
7300 else
ab3c759a 7301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7302 0x0df40000);
7303 }
a0c4da24 7304
ab3c759a 7305 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7306 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7307 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7308 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7309 coreclk |= 0x01000000;
ab3c759a 7310 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7311
ab3c759a 7312 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7313 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7314}
7315
251ac862
DV		 7316static void chv_compute_dpll(struct intel_crtc *crtc,
7317 struct intel_crtc_state *pipe_config)
1ae0d137 7318{
60bfe44f
VS		 7319 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7320 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7321 DPLL_VCO_ENABLE;
7322 if (crtc->pipe != PIPE_A)
d288f65f 7323 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7324
d288f65f
VS		 7325 pipe_config->dpll_hw_state.dpll_md =
7326 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7327}
7328
d288f65f 7329static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7330 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7331{
7332 struct drm_device *dev = crtc->base.dev;
7333 struct drm_i915_private *dev_priv = dev->dev_private;
7334 int pipe = crtc->pipe;
7335 int dpll_reg = DPLL(crtc->pipe);
7336 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7337 u32 loopfilter, tribuf_calcntr;
9d556c99 7338 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7339 u32 dpio_val;
9cbe40c1 7340 int vco;
9d556c99 7341
d288f65f
VS		 7342 bestn = pipe_config->dpll.n;
7343 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7344 bestm1 = pipe_config->dpll.m1;
7345 bestm2 = pipe_config->dpll.m2 >> 22;
7346 bestp1 = pipe_config->dpll.p1;
7347 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7348 vco = pipe_config->dpll.vco;
a945ce7e 7349 dpio_val = 0;
9cbe40c1 7350 loopfilter = 0;
9d556c99
CML		 7351
7352 /*
7353 * Enable Refclk and SSC
7354 */
a11b0703 7355 I915_WRITE(dpll_reg,
d288f65f 7356 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7357
a580516d 7358 mutex_lock(&dev_priv->sb_lock);
9d556c99 7359
9d556c99
CML		 7360 /* p1 and p2 divider */
7361 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7362 5 << DPIO_CHV_S1_DIV_SHIFT |
7363 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7364 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7365 1 << DPIO_CHV_K_DIV_SHIFT);
7366
7367 /* Feedback post-divider - m2 */
7368 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7369
7370 /* Feedback refclk divider - n and m1 */
7371 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7372 DPIO_CHV_M1_DIV_BY_2 |
7373 1 << DPIO_CHV_N_DIV_SHIFT);
7374
7375 /* M2 fraction division */
25a25dfc 7376 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7377
7378 /* M2 fraction division enable */
a945ce7e
VP		 7379 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7380 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7381 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7382 if (bestm2_frac)
7383 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7384 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7385
de3a0fde
VP		 7386 /* Program digital lock detect threshold */
7387 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7388 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7389 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7390 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7391 if (!bestm2_frac)
7392 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7393 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7394
9d556c99 7395 /* Loop filter */
9cbe40c1
VP		 7396 if (vco == 5400000) {
7397 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7398 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7399 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7400 tribuf_calcntr = 0x9;
7401 } else if (vco <= 6200000) {
7402 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7403 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7404 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7405 tribuf_calcntr = 0x9;
7406 } else if (vco <= 6480000) {
7407 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7408 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7409 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7410 tribuf_calcntr = 0x8;
7411 } else {
7412 /* Not supported. Apply the same limits as in the max case */
7413 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7414 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7415 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7416 tribuf_calcntr = 0;
7417 }
9d556c99
CML		 7418 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7419
968040b2 7420 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7421 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7422 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7423 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7424
9d556c99
CML		 7425 /* AFC Recal */
7426 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7427 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7428 DPIO_AFC_RECAL);
7429
a580516d 7430 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7431}
7432
d288f65f
VS		 7433/**
7434 * vlv_force_pll_on - forcibly enable just the PLL
7435 * @dev_priv: i915 private structure
7436 * @pipe: pipe PLL to enable
7437 * @dpll: PLL configuration
7438 *
7439 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7440 * in cases where we need the PLL enabled even when @pipe is not going to
7441 * be enabled.
7442 */
7443void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7444 const struct dpll *dpll)
7445{
7446 struct intel_crtc *crtc =
7447 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7448 struct intel_crtc_state pipe_config = {
a93e255f 7449 .base.crtc = &crtc->base,
d288f65f
VS		 7450 .pixel_multiplier = 1,
7451 .dpll = *dpll,
7452 };
7453
7454 if (IS_CHERRYVIEW(dev)) {
251ac862 7455 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7456 chv_prepare_pll(crtc, &pipe_config);
7457 chv_enable_pll(crtc, &pipe_config);
7458 } else {
251ac862 7459 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7460 vlv_prepare_pll(crtc, &pipe_config);
7461 vlv_enable_pll(crtc, &pipe_config);
7462 }
7463}
7464
7465/**
7466 * vlv_force_pll_off - forcibly disable just the PLL
7467 * @dev_priv: i915 private structure
7468 * @pipe: pipe PLL to disable
7469 *
7470 * Disable the PLL for @pipe. To be used in cases where we need
7471 * the PLL enabled even when @pipe is not going to be enabled.
7472 */
7473void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7474{
7475 if (IS_CHERRYVIEW(dev))
7476 chv_disable_pll(to_i915(dev), pipe);
7477 else
7478 vlv_disable_pll(to_i915(dev), pipe);
7479}
7480
251ac862
DV		 7481static void i9xx_compute_dpll(struct intel_crtc *crtc,
7482 struct intel_crtc_state *crtc_state,
7483 intel_clock_t *reduced_clock,
7484 int num_connectors)
eb1cbe48 7485{
f47709a9 7486 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7487 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7488 u32 dpll;
7489 bool is_sdvo;
190f68c5 7490 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7491
190f68c5 7492 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7493
a93e255f
ACO		 7494 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7495 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7496
7497 dpll = DPLL_VGA_MODE_DIS;
7498
a93e255f 7499 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7500 dpll |= DPLLB_MODE_LVDS;
7501 else
7502 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7503
ef1b460d 7504 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7505 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7506 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7507 }
198a037f
DV		 7508
7509 if (is_sdvo)
4a33e48d 7510 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7511
190f68c5 7512 if (crtc_state->has_dp_encoder)
4a33e48d 7513 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7514
7515 /* compute bitmask from p1 value */
7516 if (IS_PINEVIEW(dev))
7517 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7518 else {
7519 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7520 if (IS_G4X(dev) && reduced_clock)
7521 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7522 }
7523 switch (clock->p2) {
7524 case 5:
7525 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7526 break;
7527 case 7:
7528 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7529 break;
7530 case 10:
7531 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7532 break;
7533 case 14:
7534 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7535 break;
7536 }
7537 if (INTEL_INFO(dev)->gen >= 4)
7538 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7539
190f68c5 7540 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7541 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7542 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7543 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7544 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7545 else
7546 dpll |= PLL_REF_INPUT_DREFCLK;
7547
7548 dpll |= DPLL_VCO_ENABLE;
190f68c5 7549 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7550
eb1cbe48 7551 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7552 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7553 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7554 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7555 }
7556}
7557
251ac862
DV		 7558static void i8xx_compute_dpll(struct intel_crtc *crtc,
7559 struct intel_crtc_state *crtc_state,
7560 intel_clock_t *reduced_clock,
7561 int num_connectors)
eb1cbe48 7562{
f47709a9 7563 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7564 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7565 u32 dpll;
190f68c5 7566 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7567
190f68c5 7568 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7569
eb1cbe48
DV		 7570 dpll = DPLL_VGA_MODE_DIS;
7571
a93e255f 7572 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7573 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7574 } else {
7575 if (clock->p1 == 2)
7576 dpll |= PLL_P1_DIVIDE_BY_TWO;
7577 else
7578 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7579 if (clock->p2 == 4)
7580 dpll |= PLL_P2_DIVIDE_BY_4;
7581 }
7582
a93e255f 7583 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7584 dpll |= DPLL_DVO_2X_MODE;
7585
a93e255f 7586 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7587 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7588 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7589 else
7590 dpll |= PLL_REF_INPUT_DREFCLK;
7591
7592 dpll |= DPLL_VCO_ENABLE;
190f68c5 7593 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7594}
7595
8a654f3b 7596static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7597{
7598 struct drm_device *dev = intel_crtc->base.dev;
7599 struct drm_i915_private *dev_priv = dev->dev_private;
7600 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7601 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7c5f93b0 7602 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7603 uint32_t crtc_vtotal, crtc_vblank_end;
7604 int vsyncshift = 0;
4d8a62ea
DV		 7605
7606 /* We need to be careful not to changed the adjusted mode, for otherwise
7607 * the hw state checker will get angry at the mismatch. */
7608 crtc_vtotal = adjusted_mode->crtc_vtotal;
7609 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7610
609aeaca 7611 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7612 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7613 crtc_vtotal -= 1;
7614 crtc_vblank_end -= 1;
609aeaca 7615
409ee761 7616 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7617 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7618 else
7619 vsyncshift = adjusted_mode->crtc_hsync_start -
7620 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7621 if (vsyncshift < 0)
7622 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7623 }
7624
7625 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7626 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7627
fe2b8f9d 7628 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7629 (adjusted_mode->crtc_hdisplay - 1) |
7630 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7631 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7632 (adjusted_mode->crtc_hblank_start - 1) |
7633 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7634 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7635 (adjusted_mode->crtc_hsync_start - 1) |
7636 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7637
fe2b8f9d 7638 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7639 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7640 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7641 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7642 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7643 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7644 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7645 (adjusted_mode->crtc_vsync_start - 1) |
7646 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7647
b5e508d4
PZ		 7648 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7649 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7650 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7651 * bits. */
7652 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7653 (pipe == PIPE_B || pipe == PIPE_C))
7654 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7655
b0e77b9c
PZ		 7656 /* pipesrc controls the size that is scaled from, which should
7657 * always be the user's requested size.
7658 */
7659 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7660 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7661 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7662}
7663
1bd1bd80 7664static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7665 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7666{
7667 struct drm_device *dev = crtc->base.dev;
7668 struct drm_i915_private *dev_priv = dev->dev_private;
7669 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7670 uint32_t tmp;
7671
7672 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7673 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7674 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7675 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7676 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7677 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7678 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7679 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7680 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7681
7682 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7683 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7684 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7685 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7686 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7687 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7688 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7689 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7690 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7691
7692 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7693 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7694 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7695 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7696 }
7697
7698 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7699 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7700 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7701
2d112de7
ACO		 7702 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7703 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7704}
7705
f6a83288 7706void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7707 struct intel_crtc_state *pipe_config)
babea61d 7708{
2d112de7
ACO		 7709 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7710 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7711 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7712 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7713
2d112de7
ACO		 7714 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7715 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7716 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7717 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7718
2d112de7 7719 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7720 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7721
2d112de7
ACO		 7722 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7723 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7724
7725 mode->hsync = drm_mode_hsync(mode);
7726 mode->vrefresh = drm_mode_vrefresh(mode);
7727 drm_mode_set_name(mode);
babea61d
JB		 7728}
7729
84b046f3
DV		 7730static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7731{
7732 struct drm_device *dev = intel_crtc->base.dev;
7733 struct drm_i915_private *dev_priv = dev->dev_private;
7734 uint32_t pipeconf;
7735
9f11a9e4 7736 pipeconf = 0;
84b046f3 7737
b6b5d049
VS		 7738 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7739 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7740 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7741
6e3c9717 7742 if (intel_crtc->config->double_wide)
cf532bb2 7743 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7744
ff9ce46e
DV		 7745 /* only g4x and later have fancy bpc/dither controls */
7746 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7747 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7748 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7749 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7750 PIPECONF_DITHER_TYPE_SP;
84b046f3 7751
6e3c9717 7752 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7753 case 18:
7754 pipeconf |= PIPECONF_6BPC;
7755 break;
7756 case 24:
7757 pipeconf |= PIPECONF_8BPC;
7758 break;
7759 case 30:
7760 pipeconf |= PIPECONF_10BPC;
7761 break;
7762 default:
7763 /* Case prevented by intel_choose_pipe_bpp_dither. */
7764 BUG();
84b046f3
DV		 7765 }
7766 }
7767
7768 if (HAS_PIPE_CXSR(dev)) {
7769 if (intel_crtc->lowfreq_avail) {
7770 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7771 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7772 } else {
7773 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7774 }
7775 }
7776
6e3c9717 7777 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7778 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7779 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7780 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7781 else
7782 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7783 } else
84b046f3
DV		 7784 pipeconf |= PIPECONF_PROGRESSIVE;
7785
6e3c9717 7786 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7787 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7788
84b046f3
DV		 7789 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7790 POSTING_READ(PIPECONF(intel_crtc->pipe));
7791}
7792
190f68c5
ACO		 7793static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7794 struct intel_crtc_state *crtc_state)
79e53945 7795{
c7653199 7796 struct drm_device *dev = crtc->base.dev;
79e53945 7797 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7798 int refclk, num_connectors = 0;
c329a4ec
DV		 7799 intel_clock_t clock;
7800 bool ok;
7801 bool is_dsi = false;
5eddb70b 7802 struct intel_encoder *encoder;
d4906093 7803 const intel_limit_t *limit;
55bb9992 7804 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7805 struct drm_connector *connector;
55bb9992
ACO		 7806 struct drm_connector_state *connector_state;
7807 int i;
79e53945 7808
dd3cd74a
ACO		 7809 memset(&crtc_state->dpll_hw_state, 0,
7810 sizeof(crtc_state->dpll_hw_state));
7811
da3ced29 7812 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7813 if (connector_state->crtc != &crtc->base)
7814 continue;
7815
7816 encoder = to_intel_encoder(connector_state->best_encoder);
7817
5eddb70b 7818 switch (encoder->type) {
e9fd1c02
JN		 7819 case INTEL_OUTPUT_DSI:
7820 is_dsi = true;
7821 break;
6847d71b
PZ		 7822 default:
7823 break;
79e53945 7824 }
43565a06 7825
c751ce4f 7826 num_connectors++;
79e53945
JB		 7827 }
7828
f2335330 7829 if (is_dsi)
5b18e57c 7830 return 0;
f2335330 7831
190f68c5 7832 if (!crtc_state->clock_set) {
a93e255f 7833 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7834
e9fd1c02
JN		 7835 /*
7836 * Returns a set of divisors for the desired target clock with
7837 * the given refclk, or FALSE. The returned values represent
7838 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7839 * 2) / p1 / p2.
7840 */
a93e255f
ACO		 7841 limit = intel_limit(crtc_state, refclk);
7842 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7843 crtc_state->port_clock,
e9fd1c02 7844 refclk, NULL, &clock);
f2335330 7845 if (!ok) {
e9fd1c02
JN		 7846 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7847 return -EINVAL;
7848 }
79e53945 7849
f2335330 7850 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7851 crtc_state->dpll.n = clock.n;
7852 crtc_state->dpll.m1 = clock.m1;
7853 crtc_state->dpll.m2 = clock.m2;
7854 crtc_state->dpll.p1 = clock.p1;
7855 crtc_state->dpll.p2 = clock.p2;
f47709a9 7856 }
7026d4ac 7857
e9fd1c02 7858 if (IS_GEN2(dev)) {
c329a4ec 7859 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7860 num_connectors);
9d556c99 7861 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7862 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7863 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7864 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7865 } else {
c329a4ec 7866 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7867 num_connectors);
e9fd1c02 7868 }
79e53945 7869
c8f7a0db 7870 return 0;
f564048e
EA		 7871}
7872
2fa2fe9a 7873static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7874 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7875{
7876 struct drm_device *dev = crtc->base.dev;
7877 struct drm_i915_private *dev_priv = dev->dev_private;
7878 uint32_t tmp;
7879
dc9e7dec
VS		 7880 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7881 return;
7882
2fa2fe9a 7883 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7884 if (!(tmp & PFIT_ENABLE))
7885 return;
2fa2fe9a 7886
06922821 7887 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7888 if (INTEL_INFO(dev)->gen < 4) {
7889 if (crtc->pipe != PIPE_B)
7890 return;
2fa2fe9a
DV		 7891 } else {
7892 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7893 return;
7894 }
7895
06922821 7896 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7897 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7898 if (INTEL_INFO(dev)->gen < 5)
7899 pipe_config->gmch_pfit.lvds_border_bits =
7900 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7901}
7902
acbec814 7903static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7904 struct intel_crtc_state *pipe_config)
acbec814
JB		 7905{
7906 struct drm_device *dev = crtc->base.dev;
7907 struct drm_i915_private *dev_priv = dev->dev_private;
7908 int pipe = pipe_config->cpu_transcoder;
7909 intel_clock_t clock;
7910 u32 mdiv;
662c6ecb 7911 int refclk = 100000;
acbec814 7912
f573de5a
SK		 7913 /* In case of MIPI DPLL will not even be used */
7914 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7915 return;
7916
a580516d 7917 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7918 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7919 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7920
7921 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7922 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7923 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7924 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7925 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7926
dccbea3b 7927 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7928}
7929
5724dbd1
DL		 7930static void
7931i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7932 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7933{
7934 struct drm_device *dev = crtc->base.dev;
7935 struct drm_i915_private *dev_priv = dev->dev_private;
7936 u32 val, base, offset;
7937 int pipe = crtc->pipe, plane = crtc->plane;
7938 int fourcc, pixel_format;
6761dd31 7939 unsigned int aligned_height;
b113d5ee 7940 struct drm_framebuffer *fb;
1b842c89 7941 struct intel_framebuffer *intel_fb;
1ad292b5 7942
42a7b088
DL		 7943 val = I915_READ(DSPCNTR(plane));
7944 if (!(val & DISPLAY_PLANE_ENABLE))
7945 return;
7946
d9806c9f 7947 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7948 if (!intel_fb) {
1ad292b5
JB		 7949 DRM_DEBUG_KMS("failed to alloc fb\n");
7950 return;
7951 }
7952
1b842c89
DL		 7953 fb = &intel_fb->base;
7954
18c5247e
DV		 7955 if (INTEL_INFO(dev)->gen >= 4) {
7956 if (val & DISPPLANE_TILED) {
49af449b 7957 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7958 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7959 }
7960 }
1ad292b5
JB		 7961
7962 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7963 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7964 fb->pixel_format = fourcc;
7965 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7966
7967 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7968 if (plane_config->tiling)
1ad292b5
JB		 7969 offset = I915_READ(DSPTILEOFF(plane));
7970 else
7971 offset = I915_READ(DSPLINOFF(plane));
7972 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7973 } else {
7974 base = I915_READ(DSPADDR(plane));
7975 }
7976 plane_config->base = base;
7977
7978 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7979 fb->width = ((val >> 16) & 0xfff) + 1;
7980 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7981
7982 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7983 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7984
b113d5ee 7985 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7986 fb->pixel_format,
7987 fb->modifier[0]);
1ad292b5 7988
f37b5c2b 7989 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7990
2844a921
DL		 7991 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7992 pipe_name(pipe), plane, fb->width, fb->height,
7993 fb->bits_per_pixel, base, fb->pitches[0],
7994 plane_config->size);
1ad292b5 7995
2d14030b 7996 plane_config->fb = intel_fb;
1ad292b5
JB		 7997}
7998
70b23a98 7999static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8000 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8001{
8002 struct drm_device *dev = crtc->base.dev;
8003 struct drm_i915_private *dev_priv = dev->dev_private;
8004 int pipe = pipe_config->cpu_transcoder;
8005 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8006 intel_clock_t clock;
0d7b6b11 8007 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 8008 int refclk = 100000;
8009
a580516d 8010 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8011 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8012 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8013 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8014 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8015 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8016 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8017
8018 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8019 clock.m2 = (pll_dw0 & 0xff) << 22;
8020 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8021 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8022 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8023 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8024 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8025
dccbea3b 8026 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8027}
8028
0e8ffe1b 8029static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8030 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8031{
8032 struct drm_device *dev = crtc->base.dev;
8033 struct drm_i915_private *dev_priv = dev->dev_private;
8034 uint32_t tmp;
8035
f458ebbc
DV		 8036 if (!intel_display_power_is_enabled(dev_priv,
8037 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8038 return false;
8039
e143a21c 8040 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8041 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8042
0e8ffe1b
DV		 8043 tmp = I915_READ(PIPECONF(crtc->pipe));
8044 if (!(tmp & PIPECONF_ENABLE))
8045 return false;
8046
42571aef
VS		 8047 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8048 switch (tmp & PIPECONF_BPC_MASK) {
8049 case PIPECONF_6BPC:
8050 pipe_config->pipe_bpp = 18;
8051 break;
8052 case PIPECONF_8BPC:
8053 pipe_config->pipe_bpp = 24;
8054 break;
8055 case PIPECONF_10BPC:
8056 pipe_config->pipe_bpp = 30;
8057 break;
8058 default:
8059 break;
8060 }
8061 }
8062
b5a9fa09
DV		 8063 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8064 pipe_config->limited_color_range = true;
8065
282740f7
VS		 8066 if (INTEL_INFO(dev)->gen < 4)
8067 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8068
1bd1bd80
DV		 8069 intel_get_pipe_timings(crtc, pipe_config);
8070
2fa2fe9a
DV		 8071 i9xx_get_pfit_config(crtc, pipe_config);
8072
6c49f241
DV		 8073 if (INTEL_INFO(dev)->gen >= 4) {
8074 tmp = I915_READ(DPLL_MD(crtc->pipe));
8075 pipe_config->pixel_multiplier =
8076 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8077 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8078 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8079 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8080 tmp = I915_READ(DPLL(crtc->pipe));
8081 pipe_config->pixel_multiplier =
8082 ((tmp & SDVO_MULTIPLIER_MASK)
8083 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8084 } else {
8085 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8086 * port and will be fixed up in the encoder->get_config
8087 * function. */
8088 pipe_config->pixel_multiplier = 1;
8089 }
8bcc2795
DV		 8090 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8091 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8092 /*
8093 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8094 * on 830. Filter it out here so that we don't
8095 * report errors due to that.
8096 */
8097 if (IS_I830(dev))
8098 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8099
8bcc2795
DV		 8100 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8101 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8102 } else {
8103 /* Mask out read-only status bits. */
8104 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8105 DPLL_PORTC_READY_MASK |
8106 DPLL_PORTB_READY_MASK);
8bcc2795 8107 }
6c49f241 8108
70b23a98
VS		 8109 if (IS_CHERRYVIEW(dev))
8110 chv_crtc_clock_get(crtc, pipe_config);
8111 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8112 vlv_crtc_clock_get(crtc, pipe_config);
8113 else
8114 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8115
0f64614d
VS		 8116 /*
8117 * Normally the dotclock is filled in by the encoder .get_config()
8118 * but in case the pipe is enabled w/o any ports we need a sane
8119 * default.
8120 */
8121 pipe_config->base.adjusted_mode.crtc_clock =
8122 pipe_config->port_clock / pipe_config->pixel_multiplier;
8123
0e8ffe1b
DV		 8124 return true;
8125}
8126
dde86e2d 8127static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8128{
8129 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8130 struct intel_encoder *encoder;
74cfd7ac 8131 u32 val, final;
13d83a67 8132 bool has_lvds = false;
199e5d79 8133 bool has_cpu_edp = false;
199e5d79 8134 bool has_panel = false;
99eb6a01
KP		 8135 bool has_ck505 = false;
8136 bool can_ssc = false;
13d83a67
JB		 8137
8138 /* We need to take the global config into account */
b2784e15 8139 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8140 switch (encoder->type) {
8141 case INTEL_OUTPUT_LVDS:
8142 has_panel = true;
8143 has_lvds = true;
8144 break;
8145 case INTEL_OUTPUT_EDP:
8146 has_panel = true;
2de6905f 8147 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8148 has_cpu_edp = true;
8149 break;
6847d71b
PZ		 8150 default:
8151 break;
13d83a67
JB		 8152 }
8153 }
8154
99eb6a01 8155 if (HAS_PCH_IBX(dev)) {
41aa3448 8156 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8157 can_ssc = has_ck505;
8158 } else {
8159 has_ck505 = false;
8160 can_ssc = true;
8161 }
8162
2de6905f
ID		 8163 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8164 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8165
8166 /* Ironlake: try to setup display ref clock before DPLL
8167 * enabling. This is only under driver's control after
8168 * PCH B stepping, previous chipset stepping should be
8169 * ignoring this setting.
8170 */
74cfd7ac
CW		 8171 val = I915_READ(PCH_DREF_CONTROL);
8172
8173 /* As we must carefully and slowly disable/enable each source in turn,
8174 * compute the final state we want first and check if we need to
8175 * make any changes at all.
8176 */
8177 final = val;
8178 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8179 if (has_ck505)
8180 final |= DREF_NONSPREAD_CK505_ENABLE;
8181 else
8182 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8183
8184 final &= ~DREF_SSC_SOURCE_MASK;
8185 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8186 final &= ~DREF_SSC1_ENABLE;
8187
8188 if (has_panel) {
8189 final |= DREF_SSC_SOURCE_ENABLE;
8190
8191 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8192 final |= DREF_SSC1_ENABLE;
8193
8194 if (has_cpu_edp) {
8195 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8196 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8197 else
8198 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8199 } else
8200 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8201 } else {
8202 final |= DREF_SSC_SOURCE_DISABLE;
8203 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8204 }
8205
8206 if (final == val)
8207 return;
8208
13d83a67 8209 /* Always enable nonspread source */
74cfd7ac 8210 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8211
99eb6a01 8212 if (has_ck505)
74cfd7ac 8213 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8214 else
74cfd7ac 8215 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8216
199e5d79 8217 if (has_panel) {
74cfd7ac
CW		 8218 val &= ~DREF_SSC_SOURCE_MASK;
8219 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8220
199e5d79 8221 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8222 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8223 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8224 val |= DREF_SSC1_ENABLE;
e77166b5 8225 } else
74cfd7ac 8226 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8227
8228 /* Get SSC going before enabling the outputs */
74cfd7ac 8229 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8230 POSTING_READ(PCH_DREF_CONTROL);
8231 udelay(200);
8232
74cfd7ac 8233 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8234
8235 /* Enable CPU source on CPU attached eDP */
199e5d79 8236 if (has_cpu_edp) {
99eb6a01 8237 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8238 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8239 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8240 } else
74cfd7ac 8241 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8242 } else
74cfd7ac 8243 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8244
74cfd7ac 8245 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8246 POSTING_READ(PCH_DREF_CONTROL);
8247 udelay(200);
8248 } else {
8249 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8250
74cfd7ac 8251 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8252
8253 /* Turn off CPU output */
74cfd7ac 8254 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8255
74cfd7ac 8256 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8257 POSTING_READ(PCH_DREF_CONTROL);
8258 udelay(200);
8259
8260 /* Turn off the SSC source */
74cfd7ac
CW		 8261 val &= ~DREF_SSC_SOURCE_MASK;
8262 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8263
8264 /* Turn off SSC1 */
74cfd7ac 8265 val &= ~DREF_SSC1_ENABLE;
199e5d79 8266
74cfd7ac 8267 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8268 POSTING_READ(PCH_DREF_CONTROL);
8269 udelay(200);
8270 }
74cfd7ac
CW		 8271
8272 BUG_ON(val != final);
13d83a67
JB		 8273}
8274
f31f2d55 8275static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8276{
f31f2d55 8277 uint32_t tmp;
dde86e2d 8278
0ff066a9
PZ		 8279 tmp = I915_READ(SOUTH_CHICKEN2);
8280 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8281 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8282
0ff066a9
PZ		 8283 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8284 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8285 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8286
0ff066a9
PZ		 8287 tmp = I915_READ(SOUTH_CHICKEN2);
8288 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8289 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8290
0ff066a9
PZ		 8291 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8292 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8293 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8294}
8295
8296/* WaMPhyProgramming:hsw */
8297static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8298{
8299 uint32_t tmp;
dde86e2d
PZ		 8300
8301 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8302 tmp &= ~(0xFF << 24);
8303 tmp |= (0x12 << 24);
8304 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8305
dde86e2d
PZ		 8306 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8307 tmp |= (1 << 11);
8308 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8309
8310 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8311 tmp |= (1 << 11);
8312 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8313
dde86e2d
PZ		 8314 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8315 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8316 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8317
8318 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8319 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8320 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8321
0ff066a9
PZ		 8322 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8323 tmp &= ~(7 << 13);
8324 tmp |= (5 << 13);
8325 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8326
0ff066a9
PZ		 8327 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8328 tmp &= ~(7 << 13);
8329 tmp |= (5 << 13);
8330 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8331
8332 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8333 tmp &= ~0xFF;
8334 tmp |= 0x1C;
8335 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8336
8337 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8338 tmp &= ~0xFF;
8339 tmp |= 0x1C;
8340 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8341
8342 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8343 tmp &= ~(0xFF << 16);
8344 tmp |= (0x1C << 16);
8345 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8346
8347 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8348 tmp &= ~(0xFF << 16);
8349 tmp |= (0x1C << 16);
8350 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8351
0ff066a9
PZ		 8352 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8353 tmp |= (1 << 27);
8354 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8355
0ff066a9
PZ		 8356 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8357 tmp |= (1 << 27);
8358 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8359
0ff066a9
PZ		 8360 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8361 tmp &= ~(0xF << 28);
8362 tmp |= (4 << 28);
8363 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8364
0ff066a9
PZ		 8365 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8366 tmp &= ~(0xF << 28);
8367 tmp |= (4 << 28);
8368 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8369}
8370
2fa86a1f
PZ		 8371/* Implements 3 different sequences from BSpec chapter "Display iCLK
8372 * Programming" based on the parameters passed:
8373 * - Sequence to enable CLKOUT_DP
8374 * - Sequence to enable CLKOUT_DP without spread
8375 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8376 */
8377static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8378 bool with_fdi)
f31f2d55
PZ		 8379{
8380 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8381 uint32_t reg, tmp;
8382
8383 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8384 with_spread = true;
c2699524 8385 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8386 with_fdi = false;
f31f2d55 8387
a580516d 8388 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8389
8390 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8391 tmp &= ~SBI_SSCCTL_DISABLE;
8392 tmp |= SBI_SSCCTL_PATHALT;
8393 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8394
8395 udelay(24);
8396
2fa86a1f
PZ		 8397 if (with_spread) {
8398 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8399 tmp &= ~SBI_SSCCTL_PATHALT;
8400 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8401
2fa86a1f
PZ		 8402 if (with_fdi) {
8403 lpt_reset_fdi_mphy(dev_priv);
8404 lpt_program_fdi_mphy(dev_priv);
8405 }
8406 }
dde86e2d 8407
c2699524 8408 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ		 8409 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8410 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8411 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8412
a580516d 8413 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8414}
8415
47701c3b
PZ		 8416/* Sequence to disable CLKOUT_DP */
8417static void lpt_disable_clkout_dp(struct drm_device *dev)
8418{
8419 struct drm_i915_private *dev_priv = dev->dev_private;
8420 uint32_t reg, tmp;
8421
a580516d 8422 mutex_lock(&dev_priv->sb_lock);
47701c3b 8423
c2699524 8424 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ		 8425 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8426 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8427 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8428
8429 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8430 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8431 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8432 tmp |= SBI_SSCCTL_PATHALT;
8433 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8434 udelay(32);
8435 }
8436 tmp |= SBI_SSCCTL_DISABLE;
8437 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8438 }
8439
a580516d 8440 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8441}
8442
bf8fa3d3
PZ		 8443static void lpt_init_pch_refclk(struct drm_device *dev)
8444{
bf8fa3d3
PZ		 8445 struct intel_encoder *encoder;
8446 bool has_vga = false;
8447
b2784e15 8448 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8449 switch (encoder->type) {
8450 case INTEL_OUTPUT_ANALOG:
8451 has_vga = true;
8452 break;
6847d71b
PZ		 8453 default:
8454 break;
bf8fa3d3
PZ		 8455 }
8456 }
8457
47701c3b
PZ		 8458 if (has_vga)
8459 lpt_enable_clkout_dp(dev, true, true);
8460 else
8461 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8462}
8463
dde86e2d
PZ		 8464/*
8465 * Initialize reference clocks when the driver loads
8466 */
8467void intel_init_pch_refclk(struct drm_device *dev)
8468{
8469 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8470 ironlake_init_pch_refclk(dev);
8471 else if (HAS_PCH_LPT(dev))
8472 lpt_init_pch_refclk(dev);
8473}
8474
55bb9992 8475static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8476{
55bb9992 8477 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8478 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8479 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8480 struct drm_connector *connector;
55bb9992 8481 struct drm_connector_state *connector_state;
d9d444cb 8482 struct intel_encoder *encoder;
55bb9992 8483 int num_connectors = 0, i;
d9d444cb
JB		 8484 bool is_lvds = false;
8485
da3ced29 8486 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8487 if (connector_state->crtc != crtc_state->base.crtc)
8488 continue;
8489
8490 encoder = to_intel_encoder(connector_state->best_encoder);
8491
d9d444cb
JB		 8492 switch (encoder->type) {
8493 case INTEL_OUTPUT_LVDS:
8494 is_lvds = true;
8495 break;
6847d71b
PZ		 8496 default:
8497 break;
d9d444cb
JB		 8498 }
8499 num_connectors++;
8500 }
8501
8502 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8503 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8504 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8505 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8506 }
8507
8508 return 120000;
8509}
8510
6ff93609 8511static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8512{
c8203565 8513 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8515 int pipe = intel_crtc->pipe;
c8203565
PZ		 8516 uint32_t val;
8517
78114071 8518 val = 0;
c8203565 8519
6e3c9717 8520 switch (intel_crtc->config->pipe_bpp) {
c8203565 8521 case 18:
dfd07d72 8522 val |= PIPECONF_6BPC;
c8203565
PZ		 8523 break;
8524 case 24:
dfd07d72 8525 val |= PIPECONF_8BPC;
c8203565
PZ		 8526 break;
8527 case 30:
dfd07d72 8528 val |= PIPECONF_10BPC;
c8203565
PZ		 8529 break;
8530 case 36:
dfd07d72 8531 val |= PIPECONF_12BPC;
c8203565
PZ		 8532 break;
8533 default:
cc769b62
PZ		 8534 /* Case prevented by intel_choose_pipe_bpp_dither. */
8535 BUG();
c8203565
PZ		 8536 }
8537
6e3c9717 8538 if (intel_crtc->config->dither)
c8203565
PZ		 8539 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8540
6e3c9717 8541 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8542 val |= PIPECONF_INTERLACED_ILK;
8543 else
8544 val |= PIPECONF_PROGRESSIVE;
8545
6e3c9717 8546 if (intel_crtc->config->limited_color_range)
3685a8f3 8547 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8548
c8203565
PZ		 8549 I915_WRITE(PIPECONF(pipe), val);
8550 POSTING_READ(PIPECONF(pipe));
8551}
8552
86d3efce
VS		 8553/*
8554 * Set up the pipe CSC unit.
8555 *
8556 * Currently only full range RGB to limited range RGB conversion
8557 * is supported, but eventually this should handle various
8558 * RGB<->YCbCr scenarios as well.
8559 */
50f3b016 8560static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8561{
8562 struct drm_device *dev = crtc->dev;
8563 struct drm_i915_private *dev_priv = dev->dev_private;
8564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8565 int pipe = intel_crtc->pipe;
8566 uint16_t coeff = 0x7800; /* 1.0 */
8567
8568 /*
8569 * TODO: Check what kind of values actually come out of the pipe
8570 * with these coeff/postoff values and adjust to get the best
8571 * accuracy. Perhaps we even need to take the bpc value into
8572 * consideration.
8573 */
8574
6e3c9717 8575 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8576 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8577
8578 /*
8579 * GY/GU and RY/RU should be the other way around according
8580 * to BSpec, but reality doesn't agree. Just set them up in
8581 * a way that results in the correct picture.
8582 */
8583 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8584 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8585
8586 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8587 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8588
8589 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8590 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8591
8592 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8593 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8594 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8595
8596 if (INTEL_INFO(dev)->gen > 6) {
8597 uint16_t postoff = 0;
8598
6e3c9717 8599 if (intel_crtc->config->limited_color_range)
32cf0cb0 8600 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8601
8602 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8603 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8604 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8605
8606 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8607 } else {
8608 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8609
6e3c9717 8610 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8611 mode |= CSC_BLACK_SCREEN_OFFSET;
8612
8613 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8614 }
8615}
8616
6ff93609 8617static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8618{
756f85cf
PZ		 8619 struct drm_device *dev = crtc->dev;
8620 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8622 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8623 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8624 uint32_t val;
8625
3eff4faa 8626 val = 0;
ee2b0b38 8627
6e3c9717 8628 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8629 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8630
6e3c9717 8631 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8632 val |= PIPECONF_INTERLACED_ILK;
8633 else
8634 val |= PIPECONF_PROGRESSIVE;
8635
702e7a56
PZ		 8636 I915_WRITE(PIPECONF(cpu_transcoder), val);
8637 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8638
8639 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8640 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8641
3cdf122c 8642 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8643 val = 0;
8644
6e3c9717 8645 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8646 case 18:
8647 val |= PIPEMISC_DITHER_6_BPC;
8648 break;
8649 case 24:
8650 val |= PIPEMISC_DITHER_8_BPC;
8651 break;
8652 case 30:
8653 val |= PIPEMISC_DITHER_10_BPC;
8654 break;
8655 case 36:
8656 val |= PIPEMISC_DITHER_12_BPC;
8657 break;
8658 default:
8659 /* Case prevented by pipe_config_set_bpp. */
8660 BUG();
8661 }
8662
6e3c9717 8663 if (intel_crtc->config->dither)
756f85cf
PZ		 8664 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8665
8666 I915_WRITE(PIPEMISC(pipe), val);
8667 }
ee2b0b38
PZ		 8668}
8669
6591c6e4 8670static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8671 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8672 intel_clock_t *clock,
8673 bool *has_reduced_clock,
8674 intel_clock_t *reduced_clock)
8675{
8676 struct drm_device *dev = crtc->dev;
8677 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8678 int refclk;
d4906093 8679 const intel_limit_t *limit;
c329a4ec 8680 bool ret;
79e53945 8681
55bb9992 8682 refclk = ironlake_get_refclk(crtc_state);
79e53945 8683
d4906093
ML		 8684 /*
8685 * Returns a set of divisors for the desired target clock with the given
8686 * refclk, or FALSE. The returned values represent the clock equation:
8687 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8688 */
a93e255f
ACO		 8689 limit = intel_limit(crtc_state, refclk);
8690 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8691 crtc_state->port_clock,
ee9300bb 8692 refclk, NULL, clock);
6591c6e4
PZ		 8693 if (!ret)
8694 return false;
cda4b7d3 8695
6591c6e4
PZ		 8696 return true;
8697}
8698
d4b1931c
PZ		 8699int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8700{
8701 /*
8702 * Account for spread spectrum to avoid
8703 * oversubscribing the link. Max center spread
8704 * is 2.5%; use 5% for safety's sake.
8705 */
8706 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8707 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8708}
8709
7429e9d4 8710static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8711{
7429e9d4 8712 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8713}
8714
de13a2e3 8715static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8716 struct intel_crtc_state *crtc_state,
7429e9d4 8717 u32 *fp,
9a7c7890 8718 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8719{
de13a2e3 8720 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8721 struct drm_device *dev = crtc->dev;
8722 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8723 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8724 struct drm_connector *connector;
55bb9992
ACO		 8725 struct drm_connector_state *connector_state;
8726 struct intel_encoder *encoder;
de13a2e3 8727 uint32_t dpll;
55bb9992 8728 int factor, num_connectors = 0, i;
09ede541 8729 bool is_lvds = false, is_sdvo = false;
79e53945 8730
da3ced29 8731 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8732 if (connector_state->crtc != crtc_state->base.crtc)
8733 continue;
8734
8735 encoder = to_intel_encoder(connector_state->best_encoder);
8736
8737 switch (encoder->type) {
79e53945
JB		 8738 case INTEL_OUTPUT_LVDS:
8739 is_lvds = true;
8740 break;
8741 case INTEL_OUTPUT_SDVO:
7d57382e 8742 case INTEL_OUTPUT_HDMI:
79e53945 8743 is_sdvo = true;
79e53945 8744 break;
6847d71b
PZ		 8745 default:
8746 break;
79e53945 8747 }
43565a06 8748
c751ce4f 8749 num_connectors++;
79e53945 8750 }
79e53945 8751
c1858123 8752 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8753 factor = 21;
8754 if (is_lvds) {
8755 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8756 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8757 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8758 factor = 25;
190f68c5 8759 } else if (crtc_state->sdvo_tv_clock)
8febb297 8760 factor = 20;
c1858123 8761
190f68c5 8762 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8763 *fp |= FP_CB_TUNE;
2c07245f 8764
9a7c7890
DV		 8765 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8766 *fp2 |= FP_CB_TUNE;
8767
5eddb70b 8768 dpll = 0;
2c07245f 8769
a07d6787
EA		 8770 if (is_lvds)
8771 dpll |= DPLLB_MODE_LVDS;
8772 else
8773 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8774
190f68c5 8775 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8776 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8777
8778 if (is_sdvo)
4a33e48d 8779 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8780 if (crtc_state->has_dp_encoder)
4a33e48d 8781 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8782
a07d6787 8783 /* compute bitmask from p1 value */
190f68c5 8784 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8785 /* also FPA1 */
190f68c5 8786 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8787
190f68c5 8788 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8789 case 5:
8790 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8791 break;
8792 case 7:
8793 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8794 break;
8795 case 10:
8796 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8797 break;
8798 case 14:
8799 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8800 break;
79e53945
JB		 8801 }
8802
b4c09f3b 8803 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8804 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8805 else
8806 dpll |= PLL_REF_INPUT_DREFCLK;
8807
959e16d6 8808 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8809}
8810
190f68c5
ACO		 8811static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8812 struct intel_crtc_state *crtc_state)
de13a2e3 8813{
c7653199 8814 struct drm_device *dev = crtc->base.dev;
de13a2e3 8815 intel_clock_t clock, reduced_clock;
cbbab5bd 8816 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8817 bool ok, has_reduced_clock = false;
8b47047b 8818 bool is_lvds = false;
e2b78267 8819 struct intel_shared_dpll *pll;
de13a2e3 8820
dd3cd74a
ACO		 8821 memset(&crtc_state->dpll_hw_state, 0,
8822 sizeof(crtc_state->dpll_hw_state));
8823
409ee761 8824 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8825
5dc5298b
PZ		 8826 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8827 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8828
190f68c5 8829 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8830 &has_reduced_clock, &reduced_clock);
190f68c5 8831 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8832 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8833 return -EINVAL;
79e53945 8834 }
f47709a9 8835 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8836 if (!crtc_state->clock_set) {
8837 crtc_state->dpll.n = clock.n;
8838 crtc_state->dpll.m1 = clock.m1;
8839 crtc_state->dpll.m2 = clock.m2;
8840 crtc_state->dpll.p1 = clock.p1;
8841 crtc_state->dpll.p2 = clock.p2;
f47709a9 8842 }
79e53945 8843
5dc5298b 8844 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8845 if (crtc_state->has_pch_encoder) {
8846 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8847 if (has_reduced_clock)
7429e9d4 8848 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8849
190f68c5 8850 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8851 &fp, &reduced_clock,
8852 has_reduced_clock ? &fp2 : NULL);
8853
190f68c5
ACO		 8854 crtc_state->dpll_hw_state.dpll = dpll;
8855 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8856 if (has_reduced_clock)
190f68c5 8857 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8858 else
190f68c5 8859 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8860
190f68c5 8861 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8862 if (pll == NULL) {
84f44ce7 8863 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8864 pipe_name(crtc->pipe));
4b645f14
JB		 8865 return -EINVAL;
8866 }
3fb37703 8867 }
79e53945 8868
ab585dea 8869 if (is_lvds && has_reduced_clock)
c7653199 8870 crtc->lowfreq_avail = true;
bcd644e0 8871 else
c7653199 8872 crtc->lowfreq_avail = false;
e2b78267 8873
c8f7a0db 8874 return 0;
79e53945
JB		 8875}
8876
eb14cb74
VS		 8877static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8878 struct intel_link_m_n *m_n)
8879{
8880 struct drm_device *dev = crtc->base.dev;
8881 struct drm_i915_private *dev_priv = dev->dev_private;
8882 enum pipe pipe = crtc->pipe;
8883
8884 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8885 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8886 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8887 & ~TU_SIZE_MASK;
8888 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8889 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8890 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8891}
8892
8893static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8894 enum transcoder transcoder,
b95af8be
VK		 8895 struct intel_link_m_n *m_n,
8896 struct intel_link_m_n *m2_n2)
72419203
DV		 8897{
8898 struct drm_device *dev = crtc->base.dev;
8899 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8900 enum pipe pipe = crtc->pipe;
72419203 8901
eb14cb74
VS		 8902 if (INTEL_INFO(dev)->gen >= 5) {
8903 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8904 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8905 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8906 & ~TU_SIZE_MASK;
8907 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8908 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8909 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8910 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8911 * gen < 8) and if DRRS is supported (to make sure the
8912 * registers are not unnecessarily read).
8913 */
8914 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8915 crtc->config->has_drrs) {
b95af8be
VK		 8916 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8917 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8918 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8919 & ~TU_SIZE_MASK;
8920 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8921 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8922 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8923 }
eb14cb74
VS		 8924 } else {
8925 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8926 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8927 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8928 & ~TU_SIZE_MASK;
8929 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8930 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8931 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8932 }
8933}
8934
8935void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8936 struct intel_crtc_state *pipe_config)
eb14cb74 8937{
681a8504 8938 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8939 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8940 else
8941 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8942 &pipe_config->dp_m_n,
8943 &pipe_config->dp_m2_n2);
eb14cb74 8944}
72419203 8945
eb14cb74 8946static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8947 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8948{
8949 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8950 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8951}
8952
bd2e244f 8953static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8954 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8955{
8956 struct drm_device *dev = crtc->base.dev;
8957 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8958 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8959 uint32_t ps_ctrl = 0;
8960 int id = -1;
8961 int i;
bd2e244f 8962
a1b2278e
CK		 8963 /* find scaler attached to this pipe */
8964 for (i = 0; i < crtc->num_scalers; i++) {
8965 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8966 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8967 id = i;
8968 pipe_config->pch_pfit.enabled = true;
8969 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8970 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8971 break;
8972 }
8973 }
bd2e244f 8974
a1b2278e
CK		 8975 scaler_state->scaler_id = id;
8976 if (id >= 0) {
8977 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8978 } else {
8979 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8980 }
8981}
8982
5724dbd1
DL		 8983static void
8984skylake_get_initial_plane_config(struct intel_crtc *crtc,
8985 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8986{
8987 struct drm_device *dev = crtc->base.dev;
8988 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8989 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8990 int pipe = crtc->pipe;
8991 int fourcc, pixel_format;
6761dd31 8992 unsigned int aligned_height;
bc8d7dff 8993 struct drm_framebuffer *fb;
1b842c89 8994 struct intel_framebuffer *intel_fb;
bc8d7dff 8995
d9806c9f 8996 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8997 if (!intel_fb) {
bc8d7dff
DL		 8998 DRM_DEBUG_KMS("failed to alloc fb\n");
8999 return;
9000 }
9001
1b842c89
DL		 9002 fb = &intel_fb->base;
9003
bc8d7dff 9004 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9005 if (!(val & PLANE_CTL_ENABLE))
9006 goto error;
9007
bc8d7dff
DL		 9008 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9009 fourcc = skl_format_to_fourcc(pixel_format,
9010 val & PLANE_CTL_ORDER_RGBX,
9011 val & PLANE_CTL_ALPHA_MASK);
9012 fb->pixel_format = fourcc;
9013 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9014
40f46283
DL		 9015 tiling = val & PLANE_CTL_TILED_MASK;
9016 switch (tiling) {
9017 case PLANE_CTL_TILED_LINEAR:
9018 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9019 break;
9020 case PLANE_CTL_TILED_X:
9021 plane_config->tiling = I915_TILING_X;
9022 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9023 break;
9024 case PLANE_CTL_TILED_Y:
9025 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9026 break;
9027 case PLANE_CTL_TILED_YF:
9028 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9029 break;
9030 default:
9031 MISSING_CASE(tiling);
9032 goto error;
9033 }
9034
bc8d7dff
DL		 9035 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9036 plane_config->base = base;
9037
9038 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9039
9040 val = I915_READ(PLANE_SIZE(pipe, 0));
9041 fb->height = ((val >> 16) & 0xfff) + 1;
9042 fb->width = ((val >> 0) & 0x1fff) + 1;
9043
9044 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9045 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9046 fb->pixel_format);
bc8d7dff
DL		 9047 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9048
9049 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9050 fb->pixel_format,
9051 fb->modifier[0]);
bc8d7dff 9052
f37b5c2b 9053 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9054
9055 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9056 pipe_name(pipe), fb->width, fb->height,
9057 fb->bits_per_pixel, base, fb->pitches[0],
9058 plane_config->size);
9059
2d14030b 9060 plane_config->fb = intel_fb;
bc8d7dff
DL		 9061 return;
9062
9063error:
9064 kfree(fb);
9065}
9066
2fa2fe9a 9067static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9068 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9069{
9070 struct drm_device *dev = crtc->base.dev;
9071 struct drm_i915_private *dev_priv = dev->dev_private;
9072 uint32_t tmp;
9073
9074 tmp = I915_READ(PF_CTL(crtc->pipe));
9075
9076 if (tmp & PF_ENABLE) {
fd4daa9c 9077 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9078 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9079 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9080
9081 /* We currently do not free assignements of panel fitters on
9082 * ivb/hsw (since we don't use the higher upscaling modes which
9083 * differentiates them) so just WARN about this case for now. */
9084 if (IS_GEN7(dev)) {
9085 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9086 PF_PIPE_SEL_IVB(crtc->pipe));
9087 }
2fa2fe9a 9088 }
79e53945
JB		 9089}
9090
5724dbd1
DL		 9091static void
9092ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9093 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9094{
9095 struct drm_device *dev = crtc->base.dev;
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097 u32 val, base, offset;
aeee5a49 9098 int pipe = crtc->pipe;
4c6baa59 9099 int fourcc, pixel_format;
6761dd31 9100 unsigned int aligned_height;
b113d5ee 9101 struct drm_framebuffer *fb;
1b842c89 9102 struct intel_framebuffer *intel_fb;
4c6baa59 9103
42a7b088
DL		 9104 val = I915_READ(DSPCNTR(pipe));
9105 if (!(val & DISPLAY_PLANE_ENABLE))
9106 return;
9107
d9806c9f 9108 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9109 if (!intel_fb) {
4c6baa59
JB		 9110 DRM_DEBUG_KMS("failed to alloc fb\n");
9111 return;
9112 }
9113
1b842c89
DL		 9114 fb = &intel_fb->base;
9115
18c5247e
DV		 9116 if (INTEL_INFO(dev)->gen >= 4) {
9117 if (val & DISPPLANE_TILED) {
49af449b 9118 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9119 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9120 }
9121 }
4c6baa59
JB		 9122
9123 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9124 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9125 fb->pixel_format = fourcc;
9126 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9127
aeee5a49 9128 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9129 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9130 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9131 } else {
49af449b 9132 if (plane_config->tiling)
aeee5a49 9133 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9134 else
aeee5a49 9135 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9136 }
9137 plane_config->base = base;
9138
9139 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9140 fb->width = ((val >> 16) & 0xfff) + 1;
9141 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9142
9143 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9144 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9145
b113d5ee 9146 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9147 fb->pixel_format,
9148 fb->modifier[0]);
4c6baa59 9149
f37b5c2b 9150 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9151
2844a921
DL		 9152 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9153 pipe_name(pipe), fb->width, fb->height,
9154 fb->bits_per_pixel, base, fb->pitches[0],
9155 plane_config->size);
b113d5ee 9156
2d14030b 9157 plane_config->fb = intel_fb;
4c6baa59
JB		 9158}
9159
0e8ffe1b 9160static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9161 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9162{
9163 struct drm_device *dev = crtc->base.dev;
9164 struct drm_i915_private *dev_priv = dev->dev_private;
9165 uint32_t tmp;
9166
f458ebbc
DV		 9167 if (!intel_display_power_is_enabled(dev_priv,
9168 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9169 return false;
9170
e143a21c 9171 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9172 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9173
0e8ffe1b
DV		 9174 tmp = I915_READ(PIPECONF(crtc->pipe));
9175 if (!(tmp & PIPECONF_ENABLE))
9176 return false;
9177
42571aef
VS		 9178 switch (tmp & PIPECONF_BPC_MASK) {
9179 case PIPECONF_6BPC:
9180 pipe_config->pipe_bpp = 18;
9181 break;
9182 case PIPECONF_8BPC:
9183 pipe_config->pipe_bpp = 24;
9184 break;
9185 case PIPECONF_10BPC:
9186 pipe_config->pipe_bpp = 30;
9187 break;
9188 case PIPECONF_12BPC:
9189 pipe_config->pipe_bpp = 36;
9190 break;
9191 default:
9192 break;
9193 }
9194
b5a9fa09
DV		 9195 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9196 pipe_config->limited_color_range = true;
9197
ab9412ba 9198 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9199 struct intel_shared_dpll *pll;
9200
88adfff1
DV		 9201 pipe_config->has_pch_encoder = true;
9202
627eb5a3
DV		 9203 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9204 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9205 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9206
9207 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9208
c0d43d62 9209 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9210 pipe_config->shared_dpll =
9211 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9212 } else {
9213 tmp = I915_READ(PCH_DPLL_SEL);
9214 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9215 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9216 else
9217 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9218 }
66e985c0
DV		 9219
9220 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9221
9222 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9223 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9224
9225 tmp = pipe_config->dpll_hw_state.dpll;
9226 pipe_config->pixel_multiplier =
9227 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9228 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9229
9230 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9231 } else {
9232 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9233 }
9234
1bd1bd80
DV		 9235 intel_get_pipe_timings(crtc, pipe_config);
9236
2fa2fe9a
DV		 9237 ironlake_get_pfit_config(crtc, pipe_config);
9238
0e8ffe1b
DV		 9239 return true;
9240}
9241
be256dc7
PZ		 9242static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9243{
9244 struct drm_device *dev = dev_priv->dev;
be256dc7 9245 struct intel_crtc *crtc;
be256dc7 9246
d3fcc808 9247 for_each_intel_crtc(dev, crtc)
e2c719b7 9248 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9249 pipe_name(crtc->pipe));
9250
e2c719b7
RC		 9251 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9252 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
01403de3
VS		 9253 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9254 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
e2c719b7
RC		 9255 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9256 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9257 "CPU PWM1 enabled\n");
c5107b87 9258 if (IS_HASWELL(dev))
e2c719b7 9259 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9260 "CPU PWM2 enabled\n");
e2c719b7 9261 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9262 "PCH PWM1 enabled\n");
e2c719b7 9263 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9264 "Utility pin enabled\n");
e2c719b7 9265 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9266
9926ada1
PZ		 9267 /*
9268 * In theory we can still leave IRQs enabled, as long as only the HPD
9269 * interrupts remain enabled. We used to check for that, but since it's
9270 * gen-specific and since we only disable LCPLL after we fully disable
9271 * the interrupts, the check below should be enough.
9272 */
e2c719b7 9273 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9274}
9275
9ccd5aeb
PZ		 9276static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9277{
9278 struct drm_device *dev = dev_priv->dev;
9279
9280 if (IS_HASWELL(dev))
9281 return I915_READ(D_COMP_HSW);
9282 else
9283 return I915_READ(D_COMP_BDW);
9284}
9285
3c4c9b81
PZ		 9286static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9287{
9288 struct drm_device *dev = dev_priv->dev;
9289
9290 if (IS_HASWELL(dev)) {
9291 mutex_lock(&dev_priv->rps.hw_lock);
9292 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9293 val))
f475dadf 9294 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9295 mutex_unlock(&dev_priv->rps.hw_lock);
9296 } else {
9ccd5aeb
PZ		 9297 I915_WRITE(D_COMP_BDW, val);
9298 POSTING_READ(D_COMP_BDW);
3c4c9b81 9299 }
be256dc7
PZ		 9300}
9301
9302/*
9303 * This function implements pieces of two sequences from BSpec:
9304 * - Sequence for display software to disable LCPLL
9305 * - Sequence for display software to allow package C8+
9306 * The steps implemented here are just the steps that actually touch the LCPLL
9307 * register. Callers should take care of disabling all the display engine
9308 * functions, doing the mode unset, fixing interrupts, etc.
9309 */
6ff58d53
PZ		 9310static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9311 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9312{
9313 uint32_t val;
9314
9315 assert_can_disable_lcpll(dev_priv);
9316
9317 val = I915_READ(LCPLL_CTL);
9318
9319 if (switch_to_fclk) {
9320 val |= LCPLL_CD_SOURCE_FCLK;
9321 I915_WRITE(LCPLL_CTL, val);
9322
9323 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9324 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9325 DRM_ERROR("Switching to FCLK failed\n");
9326
9327 val = I915_READ(LCPLL_CTL);
9328 }
9329
9330 val |= LCPLL_PLL_DISABLE;
9331 I915_WRITE(LCPLL_CTL, val);
9332 POSTING_READ(LCPLL_CTL);
9333
9334 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9335 DRM_ERROR("LCPLL still locked\n");
9336
9ccd5aeb 9337 val = hsw_read_dcomp(dev_priv);
be256dc7 9338 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9339 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9340 ndelay(100);
9341
9ccd5aeb
PZ		 9342 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9343 1))
be256dc7
PZ		 9344 DRM_ERROR("D_COMP RCOMP still in progress\n");
9345
9346 if (allow_power_down) {
9347 val = I915_READ(LCPLL_CTL);
9348 val |= LCPLL_POWER_DOWN_ALLOW;
9349 I915_WRITE(LCPLL_CTL, val);
9350 POSTING_READ(LCPLL_CTL);
9351 }
9352}
9353
9354/*
9355 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9356 * source.
9357 */
6ff58d53 9358static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9359{
9360 uint32_t val;
9361
9362 val = I915_READ(LCPLL_CTL);
9363
9364 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9365 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9366 return;
9367
a8a8bd54
PZ		 9368 /*
9369 * Make sure we're not on PC8 state before disabling PC8, otherwise
9370 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9371 */
59bad947 9372 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9373
be256dc7
PZ		 9374 if (val & LCPLL_POWER_DOWN_ALLOW) {
9375 val &= ~LCPLL_POWER_DOWN_ALLOW;
9376 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9377 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9378 }
9379
9ccd5aeb 9380 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9381 val |= D_COMP_COMP_FORCE;
9382 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9383 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9384
9385 val = I915_READ(LCPLL_CTL);
9386 val &= ~LCPLL_PLL_DISABLE;
9387 I915_WRITE(LCPLL_CTL, val);
9388
9389 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9390 DRM_ERROR("LCPLL not locked yet\n");
9391
9392 if (val & LCPLL_CD_SOURCE_FCLK) {
9393 val = I915_READ(LCPLL_CTL);
9394 val &= ~LCPLL_CD_SOURCE_FCLK;
9395 I915_WRITE(LCPLL_CTL, val);
9396
9397 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9398 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9399 DRM_ERROR("Switching back to LCPLL failed\n");
9400 }
215733fa 9401
59bad947 9402 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9403 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9404}
9405
765dab67
PZ		 9406/*
9407 * Package states C8 and deeper are really deep PC states that can only be
9408 * reached when all the devices on the system allow it, so even if the graphics
9409 * device allows PC8+, it doesn't mean the system will actually get to these
9410 * states. Our driver only allows PC8+ when going into runtime PM.
9411 *
9412 * The requirements for PC8+ are that all the outputs are disabled, the power
9413 * well is disabled and most interrupts are disabled, and these are also
9414 * requirements for runtime PM. When these conditions are met, we manually do
9415 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9416 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9417 * hang the machine.
9418 *
9419 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9420 * the state of some registers, so when we come back from PC8+ we need to
9421 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9422 * need to take care of the registers kept by RC6. Notice that this happens even
9423 * if we don't put the device in PCI D3 state (which is what currently happens
9424 * because of the runtime PM support).
9425 *
9426 * For more, read "Display Sequences for Package C8" on the hardware
9427 * documentation.
9428 */
a14cb6fc 9429void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9430{
c67a470b
PZ		 9431 struct drm_device *dev = dev_priv->dev;
9432 uint32_t val;
9433
c67a470b
PZ		 9434 DRM_DEBUG_KMS("Enabling package C8+\n");
9435
c2699524 9436 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9437 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9438 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9439 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9440 }
9441
9442 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9443 hsw_disable_lcpll(dev_priv, true, true);
9444}
9445
a14cb6fc 9446void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9447{
9448 struct drm_device *dev = dev_priv->dev;
9449 uint32_t val;
9450
c67a470b
PZ		 9451 DRM_DEBUG_KMS("Disabling package C8+\n");
9452
9453 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9454 lpt_init_pch_refclk(dev);
9455
c2699524 9456 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9457 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9458 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9459 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9460 }
9461
9462 intel_prepare_ddi(dev);
c67a470b
PZ		 9463}
9464
27c329ed 9465static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9466{
a821fc46 9467 struct drm_device *dev = old_state->dev;
27c329ed 9468 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9469
27c329ed 9470 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9471}
9472
b432e5cf 9473/* compute the max rate for new configuration */
27c329ed 9474static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9475{
b432e5cf 9476 struct intel_crtc *intel_crtc;
27c329ed 9477 struct intel_crtc_state *crtc_state;
b432e5cf 9478 int max_pixel_rate = 0;
b432e5cf 9479
27c329ed
ML		 9480 for_each_intel_crtc(state->dev, intel_crtc) {
9481 int pixel_rate;
9482
9483 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9484 if (IS_ERR(crtc_state))
9485 return PTR_ERR(crtc_state);
9486
9487 if (!crtc_state->base.enable)
b432e5cf
VS		 9488 continue;
9489
27c329ed 9490 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9491
9492 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9493 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9494 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9495
9496 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9497 }
9498
9499 return max_pixel_rate;
9500}
9501
9502static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9503{
9504 struct drm_i915_private *dev_priv = dev->dev_private;
9505 uint32_t val, data;
9506 int ret;
9507
9508 if (WARN((I915_READ(LCPLL_CTL) &
9509 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9510 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9511 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9512 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9513 "trying to change cdclk frequency with cdclk not enabled\n"))
9514 return;
9515
9516 mutex_lock(&dev_priv->rps.hw_lock);
9517 ret = sandybridge_pcode_write(dev_priv,
9518 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9519 mutex_unlock(&dev_priv->rps.hw_lock);
9520 if (ret) {
9521 DRM_ERROR("failed to inform pcode about cdclk change\n");
9522 return;
9523 }
9524
9525 val = I915_READ(LCPLL_CTL);
9526 val |= LCPLL_CD_SOURCE_FCLK;
9527 I915_WRITE(LCPLL_CTL, val);
9528
9529 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9530 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9531 DRM_ERROR("Switching to FCLK failed\n");
9532
9533 val = I915_READ(LCPLL_CTL);
9534 val &= ~LCPLL_CLK_FREQ_MASK;
9535
9536 switch (cdclk) {
9537 case 450000:
9538 val |= LCPLL_CLK_FREQ_450;
9539 data = 0;
9540 break;
9541 case 540000:
9542 val |= LCPLL_CLK_FREQ_54O_BDW;
9543 data = 1;
9544 break;
9545 case 337500:
9546 val |= LCPLL_CLK_FREQ_337_5_BDW;
9547 data = 2;
9548 break;
9549 case 675000:
9550 val |= LCPLL_CLK_FREQ_675_BDW;
9551 data = 3;
9552 break;
9553 default:
9554 WARN(1, "invalid cdclk frequency\n");
9555 return;
9556 }
9557
9558 I915_WRITE(LCPLL_CTL, val);
9559
9560 val = I915_READ(LCPLL_CTL);
9561 val &= ~LCPLL_CD_SOURCE_FCLK;
9562 I915_WRITE(LCPLL_CTL, val);
9563
9564 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9565 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9566 DRM_ERROR("Switching back to LCPLL failed\n");
9567
9568 mutex_lock(&dev_priv->rps.hw_lock);
9569 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9570 mutex_unlock(&dev_priv->rps.hw_lock);
9571
9572 intel_update_cdclk(dev);
9573
9574 WARN(cdclk != dev_priv->cdclk_freq,
9575 "cdclk requested %d kHz but got %d kHz\n",
9576 cdclk, dev_priv->cdclk_freq);
9577}
9578
27c329ed 9579static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9580{
27c329ed
ML		 9581 struct drm_i915_private *dev_priv = to_i915(state->dev);
9582 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9583 int cdclk;
9584
9585 /*
9586 * FIXME should also account for plane ratio
9587 * once 64bpp pixel formats are supported.
9588 */
27c329ed 9589 if (max_pixclk > 540000)
b432e5cf 9590 cdclk = 675000;
27c329ed 9591 else if (max_pixclk > 450000)
b432e5cf 9592 cdclk = 540000;
27c329ed 9593 else if (max_pixclk > 337500)
b432e5cf
VS		 9594 cdclk = 450000;
9595 else
9596 cdclk = 337500;
9597
9598 /*
9599 * FIXME move the cdclk caclulation to
9600 * compute_config() so we can fail gracegully.
9601 */
9602 if (cdclk > dev_priv->max_cdclk_freq) {
9603 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9604 cdclk, dev_priv->max_cdclk_freq);
9605 cdclk = dev_priv->max_cdclk_freq;
9606 }
9607
27c329ed 9608 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9609
9610 return 0;
9611}
9612
27c329ed 9613static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9614{
27c329ed
ML		 9615 struct drm_device *dev = old_state->dev;
9616 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9617
27c329ed 9618 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9619}
9620
190f68c5
ACO		 9621static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9622 struct intel_crtc_state *crtc_state)
09b4ddf9 9623{
190f68c5 9624 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9625 return -EINVAL;
716c2e55 9626
c7653199 9627 crtc->lowfreq_avail = false;
644cef34 9628
c8f7a0db 9629 return 0;
79e53945
JB		 9630}
9631
3760b59c
S		 9632static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9633 enum port port,
9634 struct intel_crtc_state *pipe_config)
9635{
9636 switch (port) {
9637 case PORT_A:
9638 pipe_config->ddi_pll_sel = SKL_DPLL0;
9639 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9640 break;
9641 case PORT_B:
9642 pipe_config->ddi_pll_sel = SKL_DPLL1;
9643 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9644 break;
9645 case PORT_C:
9646 pipe_config->ddi_pll_sel = SKL_DPLL2;
9647 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9648 break;
9649 default:
9650 DRM_ERROR("Incorrect port type\n");
9651 }
9652}
9653
96b7dfb7
S		 9654static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9655 enum port port,
5cec258b 9656 struct intel_crtc_state *pipe_config)
96b7dfb7 9657{
3148ade7 9658 u32 temp, dpll_ctl1;
96b7dfb7
S		 9659
9660 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9661 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9662
9663 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9664 case SKL_DPLL0:
9665 /*
9666 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9667 * of the shared DPLL framework and thus needs to be read out
9668 * separately
9669 */
9670 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9671 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9672 break;
96b7dfb7
S		 9673 case SKL_DPLL1:
9674 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9675 break;
9676 case SKL_DPLL2:
9677 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9678 break;
9679 case SKL_DPLL3:
9680 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9681 break;
96b7dfb7
S		 9682 }
9683}
9684
7d2c8175
DL		 9685static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9686 enum port port,
5cec258b 9687 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9688{
9689 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9690
9691 switch (pipe_config->ddi_pll_sel) {
9692 case PORT_CLK_SEL_WRPLL1:
9693 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9694 break;
9695 case PORT_CLK_SEL_WRPLL2:
9696 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9697 break;
9698 }
9699}
9700
26804afd 9701static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9702 struct intel_crtc_state *pipe_config)
26804afd
DV		 9703{
9704 struct drm_device *dev = crtc->base.dev;
9705 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9706 struct intel_shared_dpll *pll;
26804afd
DV		 9707 enum port port;
9708 uint32_t tmp;
9709
9710 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9711
9712 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9713
ef11bdb3 9714 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
96b7dfb7 9715 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9716 else if (IS_BROXTON(dev))
9717 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9718 else
9719 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9720
d452c5b6
DV		 9721 if (pipe_config->shared_dpll >= 0) {
9722 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9723
9724 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9725 &pipe_config->dpll_hw_state));
9726 }
9727
26804afd
DV		 9728 /*
9729 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9730 * DDI E. So just check whether this pipe is wired to DDI E and whether
9731 * the PCH transcoder is on.
9732 */
ca370455
DL		 9733 if (INTEL_INFO(dev)->gen < 9 &&
9734 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9735 pipe_config->has_pch_encoder = true;
9736
9737 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9738 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9739 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9740
9741 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9742 }
9743}
9744
0e8ffe1b 9745static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9746 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9747{
9748 struct drm_device *dev = crtc->base.dev;
9749 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9750 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9751 uint32_t tmp;
9752
f458ebbc 9753 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9754 POWER_DOMAIN_PIPE(crtc->pipe)))
9755 return false;
9756
e143a21c 9757 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9758 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9759
eccb140b
DV		 9760 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9761 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9762 enum pipe trans_edp_pipe;
9763 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9764 default:
9765 WARN(1, "unknown pipe linked to edp transcoder\n");
9766 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9767 case TRANS_DDI_EDP_INPUT_A_ON:
9768 trans_edp_pipe = PIPE_A;
9769 break;
9770 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9771 trans_edp_pipe = PIPE_B;
9772 break;
9773 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9774 trans_edp_pipe = PIPE_C;
9775 break;
9776 }
9777
9778 if (trans_edp_pipe == crtc->pipe)
9779 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9780 }
9781
f458ebbc 9782 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9783 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9784 return false;
9785
eccb140b 9786 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9787 if (!(tmp & PIPECONF_ENABLE))
9788 return false;
9789
26804afd 9790 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9791
1bd1bd80
DV		 9792 intel_get_pipe_timings(crtc, pipe_config);
9793
a1b2278e
CK		 9794 if (INTEL_INFO(dev)->gen >= 9) {
9795 skl_init_scalers(dev, crtc, pipe_config);
9796 }
9797
2fa2fe9a 9798 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9799
9800 if (INTEL_INFO(dev)->gen >= 9) {
9801 pipe_config->scaler_state.scaler_id = -1;
9802 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9803 }
9804
bd2e244f 9805 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
1c132b44 9806 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 9807 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9808 else
1c132b44 9809 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 9810 }
88adfff1 9811
e59150dc
JB		 9812 if (IS_HASWELL(dev))
9813 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9814 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9815
ebb69c95
CT		 9816 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9817 pipe_config->pixel_multiplier =
9818 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9819 } else {
9820 pipe_config->pixel_multiplier = 1;
9821 }
6c49f241 9822
0e8ffe1b
DV		 9823 return true;
9824}
9825
560b85bb
CW		 9826static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9827{
9828 struct drm_device *dev = crtc->dev;
9829 struct drm_i915_private *dev_priv = dev->dev_private;
9830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9831 uint32_t cntl = 0, size = 0;
560b85bb 9832
dc41c154 9833 if (base) {
3dd512fb
MR		 9834 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9835 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9836 unsigned int stride = roundup_pow_of_two(width) * 4;
9837
9838 switch (stride) {
9839 default:
9840 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9841 width, stride);
9842 stride = 256;
9843 /* fallthrough */
9844 case 256:
9845 case 512:
9846 case 1024:
9847 case 2048:
9848 break;
4b0e333e
CW		 9849 }
9850
dc41c154
VS		 9851 cntl |= CURSOR_ENABLE |
9852 CURSOR_GAMMA_ENABLE |
9853 CURSOR_FORMAT_ARGB |
9854 CURSOR_STRIDE(stride);
9855
9856 size = (height << 12) | width;
4b0e333e 9857 }
560b85bb 9858
dc41c154
VS		 9859 if (intel_crtc->cursor_cntl != 0 &&
9860 (intel_crtc->cursor_base != base ||
9861 intel_crtc->cursor_size != size ||
9862 intel_crtc->cursor_cntl != cntl)) {
9863 /* On these chipsets we can only modify the base/size/stride
9864 * whilst the cursor is disabled.
9865 */
0b87c24e
VS		 9866 I915_WRITE(CURCNTR(PIPE_A), 0);
9867 POSTING_READ(CURCNTR(PIPE_A));
dc41c154 9868 intel_crtc->cursor_cntl = 0;
4b0e333e 9869 }
560b85bb 9870
99d1f387 9871 if (intel_crtc->cursor_base != base) {
0b87c24e 9872 I915_WRITE(CURBASE(PIPE_A), base);
99d1f387
VS		 9873 intel_crtc->cursor_base = base;
9874 }
4726e0b0 9875
dc41c154
VS		 9876 if (intel_crtc->cursor_size != size) {
9877 I915_WRITE(CURSIZE, size);
9878 intel_crtc->cursor_size = size;
4b0e333e 9879 }
560b85bb 9880
4b0e333e 9881 if (intel_crtc->cursor_cntl != cntl) {
0b87c24e
VS		 9882 I915_WRITE(CURCNTR(PIPE_A), cntl);
9883 POSTING_READ(CURCNTR(PIPE_A));
4b0e333e 9884 intel_crtc->cursor_cntl = cntl;
560b85bb 9885 }
560b85bb
CW		 9886}
9887
560b85bb 9888static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9889{
9890 struct drm_device *dev = crtc->dev;
9891 struct drm_i915_private *dev_priv = dev->dev_private;
9892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9893 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9894 uint32_t cntl;
9895
9896 cntl = 0;
9897 if (base) {
9898 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9899 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9900 case 64:
9901 cntl |= CURSOR_MODE_64_ARGB_AX;
9902 break;
9903 case 128:
9904 cntl |= CURSOR_MODE_128_ARGB_AX;
9905 break;
9906 case 256:
9907 cntl |= CURSOR_MODE_256_ARGB_AX;
9908 break;
9909 default:
3dd512fb 9910 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9911 return;
65a21cd6 9912 }
4b0e333e 9913 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7 9914
fc6f93bc 9915 if (HAS_DDI(dev))
47bf17a7 9916 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9917 }
65a21cd6 9918
8e7d688b 9919 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9920 cntl |= CURSOR_ROTATE_180;
9921
4b0e333e
CW		 9922 if (intel_crtc->cursor_cntl != cntl) {
9923 I915_WRITE(CURCNTR(pipe), cntl);
9924 POSTING_READ(CURCNTR(pipe));
9925 intel_crtc->cursor_cntl = cntl;
65a21cd6 9926 }
4b0e333e 9927
65a21cd6 9928 /* and commit changes on next vblank */
5efb3e28
VS		 9929 I915_WRITE(CURBASE(pipe), base);
9930 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9931
9932 intel_crtc->cursor_base = base;
65a21cd6
JB		 9933}
9934
cda4b7d3 9935/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9936static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9937 bool on)
cda4b7d3
CW		 9938{
9939 struct drm_device *dev = crtc->dev;
9940 struct drm_i915_private *dev_priv = dev->dev_private;
9941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9942 int pipe = intel_crtc->pipe;
9b4101be
ML		 9943 struct drm_plane_state *cursor_state = crtc->cursor->state;
9944 int x = cursor_state->crtc_x;
9945 int y = cursor_state->crtc_y;
d6e4db15 9946 u32 base = 0, pos = 0;
cda4b7d3 9947
d6e4db15 9948 if (on)
cda4b7d3 9949 base = intel_crtc->cursor_addr;
cda4b7d3 9950
6e3c9717 9951 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9952 base = 0;
9953
6e3c9717 9954 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9955 base = 0;
9956
9957 if (x < 0) {
9b4101be 9958 if (x + cursor_state->crtc_w <= 0)
cda4b7d3
CW		 9959 base = 0;
9960
9961 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9962 x = -x;
9963 }
9964 pos |= x << CURSOR_X_SHIFT;
9965
9966 if (y < 0) {
9b4101be 9967 if (y + cursor_state->crtc_h <= 0)
cda4b7d3
CW		 9968 base = 0;
9969
9970 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9971 y = -y;
9972 }
9973 pos |= y << CURSOR_Y_SHIFT;
9974
4b0e333e 9975 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9976 return;
9977
5efb3e28
VS		 9978 I915_WRITE(CURPOS(pipe), pos);
9979
4398ad45
VS		 9980 /* ILK+ do this automagically */
9981 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9982 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9b4101be
ML		 9983 base += (cursor_state->crtc_h *
9984 cursor_state->crtc_w - 1) * 4;
4398ad45
VS		 9985 }
9986
8ac54669 9987 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9988 i845_update_cursor(crtc, base);
9989 else
9990 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9991}
9992
dc41c154
VS		 9993static bool cursor_size_ok(struct drm_device *dev,
9994 uint32_t width, uint32_t height)
9995{
9996 if (width == 0 || height == 0)
9997 return false;
9998
9999 /*
10000 * 845g/865g are special in that they are only limited by
10001 * the width of their cursors, the height is arbitrary up to
10002 * the precision of the register. Everything else requires
10003 * square cursors, limited to a few power-of-two sizes.
10004 */
10005 if (IS_845G(dev) || IS_I865G(dev)) {
10006 if ((width & 63) != 0)
10007 return false;
10008
10009 if (width > (IS_845G(dev) ? 64 : 512))
10010 return false;
10011
10012 if (height > 1023)
10013 return false;
10014 } else {
10015 switch (width | height) {
10016 case 256:
10017 case 128:
10018 if (IS_GEN2(dev))
10019 return false;
10020 case 64:
10021 break;
10022 default:
10023 return false;
10024 }
10025 }
10026
10027 return true;
10028}
10029
79e53945 10030static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10031 u16 *blue, uint32_t start, uint32_t size)
79e53945 10032{
7203425a 10033 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10035
7203425a 10036 for (i = start; i < end; i++) {
79e53945
JB		 10037 intel_crtc->lut_r[i] = red[i] >> 8;
10038 intel_crtc->lut_g[i] = green[i] >> 8;
10039 intel_crtc->lut_b[i] = blue[i] >> 8;
10040 }
10041
10042 intel_crtc_load_lut(crtc);
10043}
10044
79e53945
JB		 10045/* VESA 640x480x72Hz mode to set on the pipe */
10046static struct drm_display_mode load_detect_mode = {
10047 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10048 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10049};
10050
a8bb6818
DV		 10051struct drm_framebuffer *
10052__intel_framebuffer_create(struct drm_device *dev,
10053 struct drm_mode_fb_cmd2 *mode_cmd,
10054 struct drm_i915_gem_object *obj)
d2dff872
CW		 10055{
10056 struct intel_framebuffer *intel_fb;
10057 int ret;
10058
10059 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10060 if (!intel_fb) {
6ccb81f2 10061 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10062 return ERR_PTR(-ENOMEM);
10063 }
10064
10065 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10066 if (ret)
10067 goto err;
d2dff872
CW		 10068
10069 return &intel_fb->base;
dd4916c5 10070err:
6ccb81f2 10071 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10072 kfree(intel_fb);
10073
10074 return ERR_PTR(ret);
d2dff872
CW		 10075}
10076
b5ea642a 10077static struct drm_framebuffer *
a8bb6818
DV		 10078intel_framebuffer_create(struct drm_device *dev,
10079 struct drm_mode_fb_cmd2 *mode_cmd,
10080 struct drm_i915_gem_object *obj)
10081{
10082 struct drm_framebuffer *fb;
10083 int ret;
10084
10085 ret = i915_mutex_lock_interruptible(dev);
10086 if (ret)
10087 return ERR_PTR(ret);
10088 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10089 mutex_unlock(&dev->struct_mutex);
10090
10091 return fb;
10092}
10093
d2dff872
CW		 10094static u32
10095intel_framebuffer_pitch_for_width(int width, int bpp)
10096{
10097 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10098 return ALIGN(pitch, 64);
10099}
10100
10101static u32
10102intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10103{
10104 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10105 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10106}
10107
10108static struct drm_framebuffer *
10109intel_framebuffer_create_for_mode(struct drm_device *dev,
10110 struct drm_display_mode *mode,
10111 int depth, int bpp)
10112{
10113 struct drm_i915_gem_object *obj;
0fed39bd 10114 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10115
10116 obj = i915_gem_alloc_object(dev,
10117 intel_framebuffer_size_for_mode(mode, bpp));
10118 if (obj == NULL)
10119 return ERR_PTR(-ENOMEM);
10120
10121 mode_cmd.width = mode->hdisplay;
10122 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10123 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10124 bpp);
5ca0c34a 10125 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10126
10127 return intel_framebuffer_create(dev, &mode_cmd, obj);
10128}
10129
10130static struct drm_framebuffer *
10131mode_fits_in_fbdev(struct drm_device *dev,
10132 struct drm_display_mode *mode)
10133{
0695726e 10134#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10135 struct drm_i915_private *dev_priv = dev->dev_private;
10136 struct drm_i915_gem_object *obj;
10137 struct drm_framebuffer *fb;
10138
4c0e5528 10139 if (!dev_priv->fbdev)
d2dff872
CW		 10140 return NULL;
10141
4c0e5528 10142 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10143 return NULL;
10144
4c0e5528
DV		 10145 obj = dev_priv->fbdev->fb->obj;
10146 BUG_ON(!obj);
10147
8bcd4553 10148 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10149 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10150 fb->bits_per_pixel))
d2dff872
CW		 10151 return NULL;
10152
01f2c773 10153 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10154 return NULL;
10155
10156 return fb;
4520f53a
DV		 10157#else
10158 return NULL;
10159#endif
d2dff872
CW		 10160}
10161
d3a40d1b
ACO		 10162static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10163 struct drm_crtc *crtc,
10164 struct drm_display_mode *mode,
10165 struct drm_framebuffer *fb,
10166 int x, int y)
10167{
10168 struct drm_plane_state *plane_state;
10169 int hdisplay, vdisplay;
10170 int ret;
10171
10172 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10173 if (IS_ERR(plane_state))
10174 return PTR_ERR(plane_state);
10175
10176 if (mode)
10177 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10178 else
10179 hdisplay = vdisplay = 0;
10180
10181 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10182 if (ret)
10183 return ret;
10184 drm_atomic_set_fb_for_plane(plane_state, fb);
10185 plane_state->crtc_x = 0;
10186 plane_state->crtc_y = 0;
10187 plane_state->crtc_w = hdisplay;
10188 plane_state->crtc_h = vdisplay;
10189 plane_state->src_x = x << 16;
10190 plane_state->src_y = y << 16;
10191 plane_state->src_w = hdisplay << 16;
10192 plane_state->src_h = vdisplay << 16;
10193
10194 return 0;
10195}
10196
d2434ab7 10197bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10198 struct drm_display_mode *mode,
51fd371b
RC		 10199 struct intel_load_detect_pipe *old,
10200 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10201{
10202 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10203 struct intel_encoder *intel_encoder =
10204 intel_attached_encoder(connector);
79e53945 10205 struct drm_crtc *possible_crtc;
4ef69c7a 10206 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10207 struct drm_crtc *crtc = NULL;
10208 struct drm_device *dev = encoder->dev;
94352cf9 10209 struct drm_framebuffer *fb;
51fd371b 10210 struct drm_mode_config *config = &dev->mode_config;
83a57153 10211 struct drm_atomic_state *state = NULL;
944b0c76 10212 struct drm_connector_state *connector_state;
4be07317 10213 struct intel_crtc_state *crtc_state;
51fd371b 10214 int ret, i = -1;
79e53945 10215
d2dff872 10216 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10217 connector->base.id, connector->name,
8e329a03 10218 encoder->base.id, encoder->name);
d2dff872 10219
51fd371b
RC		 10220retry:
10221 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10222 if (ret)
ad3c558f 10223 goto fail;
6e9f798d 10224
79e53945
JB		 10225 /*
10226 * Algorithm gets a little messy:
7a5e4805 10227 *
79e53945
JB		 10228 * - if the connector already has an assigned crtc, use it (but make
10229 * sure it's on first)
7a5e4805 10230 *
79e53945
JB		 10231 * - try to find the first unused crtc that can drive this connector,
10232 * and use that if we find one
79e53945
JB		 10233 */
10234
10235 /* See if we already have a CRTC for this connector */
10236 if (encoder->crtc) {
10237 crtc = encoder->crtc;
8261b191 10238
51fd371b 10239 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10240 if (ret)
ad3c558f 10241 goto fail;
4d02e2de 10242 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10243 if (ret)
ad3c558f 10244 goto fail;
7b24056b 10245
24218aac 10246 old->dpms_mode = connector->dpms;
8261b191
CW		 10247 old->load_detect_temp = false;
10248
10249 /* Make sure the crtc and connector are running */
24218aac
DV		 10250 if (connector->dpms != DRM_MODE_DPMS_ON)
10251 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10252
7173188d 10253 return true;
79e53945
JB		 10254 }
10255
10256 /* Find an unused one (if possible) */
70e1e0ec 10257 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10258 i++;
10259 if (!(encoder->possible_crtcs & (1 << i)))
10260 continue;
83d65738 10261 if (possible_crtc->state->enable)
a459249c 10262 continue;
a459249c
VS		 10263
10264 crtc = possible_crtc;
10265 break;
79e53945
JB		 10266 }
10267
10268 /*
10269 * If we didn't find an unused CRTC, don't use any.
10270 */
10271 if (!crtc) {
7173188d 10272 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10273 goto fail;
79e53945
JB		 10274 }
10275
51fd371b
RC		 10276 ret = drm_modeset_lock(&crtc->mutex, ctx);
10277 if (ret)
ad3c558f 10278 goto fail;
4d02e2de
DV		 10279 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10280 if (ret)
ad3c558f 10281 goto fail;
79e53945
JB		 10282
10283 intel_crtc = to_intel_crtc(crtc);
24218aac 10284 old->dpms_mode = connector->dpms;
8261b191 10285 old->load_detect_temp = true;
d2dff872 10286 old->release_fb = NULL;
79e53945 10287
83a57153
ACO		 10288 state = drm_atomic_state_alloc(dev);
10289 if (!state)
10290 return false;
10291
10292 state->acquire_ctx = ctx;
10293
944b0c76
ACO		 10294 connector_state = drm_atomic_get_connector_state(state, connector);
10295 if (IS_ERR(connector_state)) {
10296 ret = PTR_ERR(connector_state);
10297 goto fail;
10298 }
10299
10300 connector_state->crtc = crtc;
10301 connector_state->best_encoder = &intel_encoder->base;
10302
4be07317
ACO		 10303 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10304 if (IS_ERR(crtc_state)) {
10305 ret = PTR_ERR(crtc_state);
10306 goto fail;
10307 }
10308
49d6fa21 10309 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10310
6492711d
CW		 10311 if (!mode)
10312 mode = &load_detect_mode;
79e53945 10313
d2dff872
CW		 10314 /* We need a framebuffer large enough to accommodate all accesses
10315 * that the plane may generate whilst we perform load detection.
10316 * We can not rely on the fbcon either being present (we get called
10317 * during its initialisation to detect all boot displays, or it may
10318 * not even exist) or that it is large enough to satisfy the
10319 * requested mode.
10320 */
94352cf9
DV		 10321 fb = mode_fits_in_fbdev(dev, mode);
10322 if (fb == NULL) {
d2dff872 10323 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10324 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10325 old->release_fb = fb;
d2dff872
CW		 10326 } else
10327 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10328 if (IS_ERR(fb)) {
d2dff872 10329 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10330 goto fail;
79e53945 10331 }
79e53945 10332
d3a40d1b
ACO		 10333 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10334 if (ret)
10335 goto fail;
10336
8c7b5ccb
ACO		 10337 drm_mode_copy(&crtc_state->base.mode, mode);
10338
74c090b1 10339 if (drm_atomic_commit(state)) {
6492711d 10340 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10341 if (old->release_fb)
10342 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10343 goto fail;
79e53945 10344 }
9128b040 10345 crtc->primary->crtc = crtc;
7173188d 10346
79e53945 10347 /* let the connector get through one full cycle before testing */
9d0498a2 10348 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10349 return true;
412b61d8 10350
ad3c558f 10351fail:
e5d958ef
ACO		 10352 drm_atomic_state_free(state);
10353 state = NULL;
83a57153 10354
51fd371b
RC		 10355 if (ret == -EDEADLK) {
10356 drm_modeset_backoff(ctx);
10357 goto retry;
10358 }
10359
412b61d8 10360 return false;
79e53945
JB		 10361}
10362
d2434ab7 10363void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10364 struct intel_load_detect_pipe *old,
10365 struct drm_modeset_acquire_ctx *ctx)
79e53945 10366{
83a57153 10367 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10368 struct intel_encoder *intel_encoder =
10369 intel_attached_encoder(connector);
4ef69c7a 10370 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10371 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10373 struct drm_atomic_state *state;
944b0c76 10374 struct drm_connector_state *connector_state;
4be07317 10375 struct intel_crtc_state *crtc_state;
d3a40d1b 10376 int ret;
79e53945 10377
d2dff872 10378 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10379 connector->base.id, connector->name,
8e329a03 10380 encoder->base.id, encoder->name);
d2dff872 10381
8261b191 10382 if (old->load_detect_temp) {
83a57153 10383 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10384 if (!state)
10385 goto fail;
83a57153
ACO		 10386
10387 state->acquire_ctx = ctx;
10388
944b0c76
ACO		 10389 connector_state = drm_atomic_get_connector_state(state, connector);
10390 if (IS_ERR(connector_state))
10391 goto fail;
10392
4be07317
ACO		 10393 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10394 if (IS_ERR(crtc_state))
10395 goto fail;
10396
944b0c76
ACO		 10397 connector_state->best_encoder = NULL;
10398 connector_state->crtc = NULL;
10399
49d6fa21 10400 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10401
d3a40d1b
ACO		 10402 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10403 0, 0);
10404 if (ret)
10405 goto fail;
10406
74c090b1 10407 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10408 if (ret)
10409 goto fail;
d2dff872 10410
36206361
DV		 10411 if (old->release_fb) {
10412 drm_framebuffer_unregister_private(old->release_fb);
10413 drm_framebuffer_unreference(old->release_fb);
10414 }
d2dff872 10415
0622a53c 10416 return;
79e53945
JB		 10417 }
10418
c751ce4f 10419 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10420 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10421 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10422
10423 return;
10424fail:
10425 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10426 drm_atomic_state_free(state);
79e53945
JB		 10427}
10428
da4a1efa 10429static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10430 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10431{
10432 struct drm_i915_private *dev_priv = dev->dev_private;
10433 u32 dpll = pipe_config->dpll_hw_state.dpll;
10434
10435 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10436 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10437 else if (HAS_PCH_SPLIT(dev))
10438 return 120000;
10439 else if (!IS_GEN2(dev))
10440 return 96000;
10441 else
10442 return 48000;
10443}
10444
79e53945 10445/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10446static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10447 struct intel_crtc_state *pipe_config)
79e53945 10448{
f1f644dc 10449 struct drm_device *dev = crtc->base.dev;
79e53945 10450 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10451 int pipe = pipe_config->cpu_transcoder;
293623f7 10452 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10453 u32 fp;
10454 intel_clock_t clock;
dccbea3b 10455 int port_clock;
da4a1efa 10456 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10457
10458 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10459 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10460 else
293623f7 10461 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10462
10463 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10464 if (IS_PINEVIEW(dev)) {
10465 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10466 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10467 } else {
10468 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10469 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10470 }
10471
a6c45cf0 10472 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10473 if (IS_PINEVIEW(dev))
10474 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10475 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10476 else
10477 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10478 DPLL_FPA01_P1_POST_DIV_SHIFT);
10479
10480 switch (dpll & DPLL_MODE_MASK) {
10481 case DPLLB_MODE_DAC_SERIAL:
10482 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10483 5 : 10;
10484 break;
10485 case DPLLB_MODE_LVDS:
10486 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10487 7 : 14;
10488 break;
10489 default:
28c97730 10490 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10491 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10492 return;
79e53945
JB		 10493 }
10494
ac58c3f0 10495 if (IS_PINEVIEW(dev))
dccbea3b 10496 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10497 else
dccbea3b 10498 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10499 } else {
0fb58223 10500 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10501 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10502
10503 if (is_lvds) {
10504 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10505 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10506
10507 if (lvds & LVDS_CLKB_POWER_UP)
10508 clock.p2 = 7;
10509 else
10510 clock.p2 = 14;
79e53945
JB		 10511 } else {
10512 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10513 clock.p1 = 2;
10514 else {
10515 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10516 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10517 }
10518 if (dpll & PLL_P2_DIVIDE_BY_4)
10519 clock.p2 = 4;
10520 else
10521 clock.p2 = 2;
79e53945 10522 }
da4a1efa 10523
dccbea3b 10524 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10525 }
10526
18442d08
VS		 10527 /*
10528 * This value includes pixel_multiplier. We will use
241bfc38 10529 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10530 * encoder's get_config() function.
10531 */
dccbea3b 10532 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10533}
10534
6878da05
VS		 10535int intel_dotclock_calculate(int link_freq,
10536 const struct intel_link_m_n *m_n)
f1f644dc 10537{
f1f644dc
JB		 10538 /*
10539 * The calculation for the data clock is:
1041a02f 10540 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10541 * But we want to avoid losing precison if possible, so:
1041a02f 10542 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10543 *
10544 * and the link clock is simpler:
1041a02f 10545 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10546 */
10547
6878da05
VS		 10548 if (!m_n->link_n)
10549 return 0;
f1f644dc 10550
6878da05
VS		 10551 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10552}
f1f644dc 10553
18442d08 10554static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10555 struct intel_crtc_state *pipe_config)
6878da05
VS		 10556{
10557 struct drm_device *dev = crtc->base.dev;
79e53945 10558
18442d08
VS		 10559 /* read out port_clock from the DPLL */
10560 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10561
f1f644dc 10562 /*
18442d08 10563 * This value does not include pixel_multiplier.
241bfc38 10564 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10565 * agree once we know their relationship in the encoder's
10566 * get_config() function.
79e53945 10567 */
2d112de7 10568 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10569 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10570 &pipe_config->fdi_m_n);
79e53945
JB		 10571}
10572
10573/** Returns the currently programmed mode of the given pipe. */
10574struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10575 struct drm_crtc *crtc)
10576{
548f245b 10577 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10579 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10580 struct drm_display_mode *mode;
5cec258b 10581 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10582 int htot = I915_READ(HTOTAL(cpu_transcoder));
10583 int hsync = I915_READ(HSYNC(cpu_transcoder));
10584 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10585 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10586 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10587
10588 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10589 if (!mode)
10590 return NULL;
10591
f1f644dc
JB		 10592 /*
10593 * Construct a pipe_config sufficient for getting the clock info
10594 * back out of crtc_clock_get.
10595 *
10596 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10597 * to use a real value here instead.
10598 */
293623f7 10599 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10600 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10601 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10602 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10603 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10604 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10605
773ae034 10606 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10607 mode->hdisplay = (htot & 0xffff) + 1;
10608 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10609 mode->hsync_start = (hsync & 0xffff) + 1;
10610 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10611 mode->vdisplay = (vtot & 0xffff) + 1;
10612 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10613 mode->vsync_start = (vsync & 0xffff) + 1;
10614 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10615
10616 drm_mode_set_name(mode);
79e53945
JB		 10617
10618 return mode;
10619}
10620
f047e395
CW		 10621void intel_mark_busy(struct drm_device *dev)
10622{
c67a470b
PZ		 10623 struct drm_i915_private *dev_priv = dev->dev_private;
10624
f62a0076
CW		 10625 if (dev_priv->mm.busy)
10626 return;
10627
43694d69 10628 intel_runtime_pm_get(dev_priv);
c67a470b 10629 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10630 if (INTEL_INFO(dev)->gen >= 6)
10631 gen6_rps_busy(dev_priv);
f62a0076 10632 dev_priv->mm.busy = true;
f047e395
CW		 10633}
10634
10635void intel_mark_idle(struct drm_device *dev)
652c393a 10636{
c67a470b 10637 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10638
f62a0076
CW		 10639 if (!dev_priv->mm.busy)
10640 return;
10641
10642 dev_priv->mm.busy = false;
10643
3d13ef2e 10644 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10645 gen6_rps_idle(dev->dev_private);
bb4cdd53 10646
43694d69 10647 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10648}
10649
79e53945
JB		 10650static void intel_crtc_destroy(struct drm_crtc *crtc)
10651{
10652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10653 struct drm_device *dev = crtc->dev;
10654 struct intel_unpin_work *work;
67e77c5a 10655
5e2d7afc 10656 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10657 work = intel_crtc->unpin_work;
10658 intel_crtc->unpin_work = NULL;
5e2d7afc 10659 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10660
10661 if (work) {
10662 cancel_work_sync(&work->work);
10663 kfree(work);
10664 }
79e53945
JB		 10665
10666 drm_crtc_cleanup(crtc);
67e77c5a 10667
79e53945
JB		 10668 kfree(intel_crtc);
10669}
10670
6b95a207
KH		 10671static void intel_unpin_work_fn(struct work_struct *__work)
10672{
10673 struct intel_unpin_work *work =
10674 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10675 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10676 struct drm_device *dev = crtc->base.dev;
10677 struct drm_plane *primary = crtc->base.primary;
6b95a207 10678
b4a98e57 10679 mutex_lock(&dev->struct_mutex);
a9ff8714 10680 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10681 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10682
f06cc1b9 10683 if (work->flip_queued_req)
146d84f0 10684 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10685 mutex_unlock(&dev->struct_mutex);
10686
a9ff8714 10687 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10688 drm_framebuffer_unreference(work->old_fb);
f99d7069 10689
a9ff8714
VS		 10690 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10691 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10692
6b95a207
KH		 10693 kfree(work);
10694}
10695
1afe3e9d 10696static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10697 struct drm_crtc *crtc)
6b95a207 10698{
6b95a207
KH		 10699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10700 struct intel_unpin_work *work;
6b95a207
KH		 10701 unsigned long flags;
10702
10703 /* Ignore early vblank irqs */
10704 if (intel_crtc == NULL)
10705 return;
10706
f326038a
DV		 10707 /*
10708 * This is called both by irq handlers and the reset code (to complete
10709 * lost pageflips) so needs the full irqsave spinlocks.
10710 */
6b95a207
KH		 10711 spin_lock_irqsave(&dev->event_lock, flags);
10712 work = intel_crtc->unpin_work;
e7d841ca
CW		 10713
10714 /* Ensure we don't miss a work->pending update ... */
10715 smp_rmb();
10716
10717 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10718 spin_unlock_irqrestore(&dev->event_lock, flags);
10719 return;
10720 }
10721
d6bbafa1 10722 page_flip_completed(intel_crtc);
0af7e4df 10723
6b95a207 10724 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10725}
10726
1afe3e9d
JB		 10727void intel_finish_page_flip(struct drm_device *dev, int pipe)
10728{
fbee40df 10729 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10730 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10731
49b14a5c 10732 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10733}
10734
10735void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10736{
fbee40df 10737 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10738 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10739
49b14a5c 10740 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10741}
10742
75f7f3ec
VS		 10743/* Is 'a' after or equal to 'b'? */
10744static bool g4x_flip_count_after_eq(u32 a, u32 b)
10745{
10746 return !((a - b) & 0x80000000);
10747}
10748
10749static bool page_flip_finished(struct intel_crtc *crtc)
10750{
10751 struct drm_device *dev = crtc->base.dev;
10752 struct drm_i915_private *dev_priv = dev->dev_private;
10753
bdfa7542
VS		 10754 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10755 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10756 return true;
10757
75f7f3ec
VS		 10758 /*
10759 * The relevant registers doen't exist on pre-ctg.
10760 * As the flip done interrupt doesn't trigger for mmio
10761 * flips on gmch platforms, a flip count check isn't
10762 * really needed there. But since ctg has the registers,
10763 * include it in the check anyway.
10764 */
10765 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10766 return true;
10767
10768 /*
10769 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10770 * used the same base address. In that case the mmio flip might
10771 * have completed, but the CS hasn't even executed the flip yet.
10772 *
10773 * A flip count check isn't enough as the CS might have updated
10774 * the base address just after start of vblank, but before we
10775 * managed to process the interrupt. This means we'd complete the
10776 * CS flip too soon.
10777 *
10778 * Combining both checks should get us a good enough result. It may
10779 * still happen that the CS flip has been executed, but has not
10780 * yet actually completed. But in case the base address is the same
10781 * anyway, we don't really care.
10782 */
10783 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10784 crtc->unpin_work->gtt_offset &&
fd8f507c 10785 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
75f7f3ec
VS		 10786 crtc->unpin_work->flip_count);
10787}
10788
6b95a207
KH		 10789void intel_prepare_page_flip(struct drm_device *dev, int plane)
10790{
fbee40df 10791 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10792 struct intel_crtc *intel_crtc =
10793 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10794 unsigned long flags;
10795
f326038a
DV		 10796
10797 /*
10798 * This is called both by irq handlers and the reset code (to complete
10799 * lost pageflips) so needs the full irqsave spinlocks.
10800 *
10801 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10802 * generate a page-flip completion irq, i.e. every modeset
10803 * is also accompanied by a spurious intel_prepare_page_flip().
10804 */
6b95a207 10805 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10806 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10807 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10808 spin_unlock_irqrestore(&dev->event_lock, flags);
10809}
10810
6042639c 10811static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
e7d841ca
CW		 10812{
10813 /* Ensure that the work item is consistent when activating it ... */
10814 smp_wmb();
6042639c 10815 atomic_set(&work->pending, INTEL_FLIP_PENDING);
e7d841ca
CW		 10816 /* and that it is marked active as soon as the irq could fire. */
10817 smp_wmb();
10818}
10819
8c9f3aaf
JB		 10820static int intel_gen2_queue_flip(struct drm_device *dev,
10821 struct drm_crtc *crtc,
10822 struct drm_framebuffer *fb,
ed8d1975 10823 struct drm_i915_gem_object *obj,
6258fbe2 10824 struct drm_i915_gem_request *req,
ed8d1975 10825 uint32_t flags)
8c9f3aaf 10826{
6258fbe2 10827 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10829 u32 flip_mask;
10830 int ret;
10831
5fb9de1a 10832 ret = intel_ring_begin(req, 6);
8c9f3aaf 10833 if (ret)
4fa62c89 10834 return ret;
8c9f3aaf
JB		 10835
10836 /* Can't queue multiple flips, so wait for the previous
10837 * one to finish before executing the next.
10838 */
10839 if (intel_crtc->plane)
10840 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10841 else
10842 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10843 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10844 intel_ring_emit(ring, MI_NOOP);
10845 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10846 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10847 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10848 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10849 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca 10850
6042639c 10851 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10852 return 0;
8c9f3aaf
JB		 10853}
10854
10855static int intel_gen3_queue_flip(struct drm_device *dev,
10856 struct drm_crtc *crtc,
10857 struct drm_framebuffer *fb,
ed8d1975 10858 struct drm_i915_gem_object *obj,
6258fbe2 10859 struct drm_i915_gem_request *req,
ed8d1975 10860 uint32_t flags)
8c9f3aaf 10861{
6258fbe2 10862 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10864 u32 flip_mask;
10865 int ret;
10866
5fb9de1a 10867 ret = intel_ring_begin(req, 6);
8c9f3aaf 10868 if (ret)
4fa62c89 10869 return ret;
8c9f3aaf
JB		 10870
10871 if (intel_crtc->plane)
10872 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10873 else
10874 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10875 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10876 intel_ring_emit(ring, MI_NOOP);
10877 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10878 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10879 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10880 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10881 intel_ring_emit(ring, MI_NOOP);
10882
6042639c 10883 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10884 return 0;
8c9f3aaf
JB		 10885}
10886
10887static int intel_gen4_queue_flip(struct drm_device *dev,
10888 struct drm_crtc *crtc,
10889 struct drm_framebuffer *fb,
ed8d1975 10890 struct drm_i915_gem_object *obj,
6258fbe2 10891 struct drm_i915_gem_request *req,
ed8d1975 10892 uint32_t flags)
8c9f3aaf 10893{
6258fbe2 10894 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10895 struct drm_i915_private *dev_priv = dev->dev_private;
10896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10897 uint32_t pf, pipesrc;
10898 int ret;
10899
5fb9de1a 10900 ret = intel_ring_begin(req, 4);
8c9f3aaf 10901 if (ret)
4fa62c89 10902 return ret;
8c9f3aaf
JB		 10903
10904 /* i965+ uses the linear or tiled offsets from the
10905 * Display Registers (which do not change across a page-flip)
10906 * so we need only reprogram the base address.
10907 */
6d90c952
DV		 10908 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10909 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10910 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10911 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10912 obj->tiling_mode);
8c9f3aaf
JB		 10913
10914 /* XXX Enabling the panel-fitter across page-flip is so far
10915 * untested on non-native modes, so ignore it for now.
10916 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10917 */
10918 pf = 0;
10919 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10920 intel_ring_emit(ring, pf | pipesrc);
e7d841ca 10921
6042639c 10922 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10923 return 0;
8c9f3aaf
JB		 10924}
10925
10926static int intel_gen6_queue_flip(struct drm_device *dev,
10927 struct drm_crtc *crtc,
10928 struct drm_framebuffer *fb,
ed8d1975 10929 struct drm_i915_gem_object *obj,
6258fbe2 10930 struct drm_i915_gem_request *req,
ed8d1975 10931 uint32_t flags)
8c9f3aaf 10932{
6258fbe2 10933 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10934 struct drm_i915_private *dev_priv = dev->dev_private;
10935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10936 uint32_t pf, pipesrc;
10937 int ret;
10938
5fb9de1a 10939 ret = intel_ring_begin(req, 4);
8c9f3aaf 10940 if (ret)
4fa62c89 10941 return ret;
8c9f3aaf 10942
6d90c952
DV		 10943 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10944 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10945 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10946 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10947
dc257cf1
DV		 10948 /* Contrary to the suggestions in the documentation,
10949 * "Enable Panel Fitter" does not seem to be required when page
10950 * flipping with a non-native mode, and worse causes a normal
10951 * modeset to fail.
10952 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10953 */
10954 pf = 0;
8c9f3aaf 10955 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10956 intel_ring_emit(ring, pf | pipesrc);
e7d841ca 10957
6042639c 10958 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10959 return 0;
8c9f3aaf
JB		 10960}
10961
7c9017e5
JB		 10962static int intel_gen7_queue_flip(struct drm_device *dev,
10963 struct drm_crtc *crtc,
10964 struct drm_framebuffer *fb,
ed8d1975 10965 struct drm_i915_gem_object *obj,
6258fbe2 10966 struct drm_i915_gem_request *req,
ed8d1975 10967 uint32_t flags)
7c9017e5 10968{
6258fbe2 10969 struct intel_engine_cs *ring = req->ring;
7c9017e5 10970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10971 uint32_t plane_bit = 0;
ffe74d75
CW		 10972 int len, ret;
10973
eba905b2 10974 switch (intel_crtc->plane) {
cb05d8de
DV		 10975 case PLANE_A:
10976 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10977 break;
10978 case PLANE_B:
10979 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10980 break;
10981 case PLANE_C:
10982 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10983 break;
10984 default:
10985 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10986 return -ENODEV;
cb05d8de
DV		 10987 }
10988
ffe74d75 10989 len = 4;
f476828a 10990 if (ring->id == RCS) {
ffe74d75 10991 len += 6;
f476828a
DL		 10992 /*
10993 * On Gen 8, SRM is now taking an extra dword to accommodate
10994 * 48bits addresses, and we need a NOOP for the batch size to
10995 * stay even.
10996 */
10997 if (IS_GEN8(dev))
10998 len += 2;
10999 }
ffe74d75 11000
f66fab8e
VS		 11001 /*
11002 * BSpec MI_DISPLAY_FLIP for IVB:
11003 * "The full packet must be contained within the same cache line."
11004 *
11005 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11006 * cacheline, if we ever start emitting more commands before
11007 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11008 * then do the cacheline alignment, and finally emit the
11009 * MI_DISPLAY_FLIP.
11010 */
bba09b12 11011 ret = intel_ring_cacheline_align(req);
f66fab8e 11012 if (ret)
4fa62c89 11013 return ret;
f66fab8e 11014
5fb9de1a 11015 ret = intel_ring_begin(req, len);
7c9017e5 11016 if (ret)
4fa62c89 11017 return ret;
7c9017e5 11018
ffe74d75
CW		 11019 /* Unmask the flip-done completion message. Note that the bspec says that
11020 * we should do this for both the BCS and RCS, and that we must not unmask
11021 * more than one flip event at any time (or ensure that one flip message
11022 * can be sent by waiting for flip-done prior to queueing new flips).
11023 * Experimentation says that BCS works despite DERRMR masking all
11024 * flip-done completion events and that unmasking all planes at once
11025 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11026 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11027 */
11028 if (ring->id == RCS) {
11029 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11030 intel_ring_emit(ring, DERRMR);
11031 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11032 DERRMR_PIPEB_PRI_FLIP_DONE |
11033 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11034 if (IS_GEN8(dev))
f1afe24f 11035 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11036 MI_SRM_LRM_GLOBAL_GTT);
11037 else
f1afe24f 11038 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11039 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11040 intel_ring_emit(ring, DERRMR);
11041 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11042 if (IS_GEN8(dev)) {
11043 intel_ring_emit(ring, 0);
11044 intel_ring_emit(ring, MI_NOOP);
11045 }
ffe74d75
CW		 11046 }
11047
cb05d8de 11048 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11049 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11050 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11051 intel_ring_emit(ring, (MI_NOOP));
e7d841ca 11052
6042639c 11053 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 11054 return 0;
7c9017e5
JB		 11055}
11056
84c33a64
SG		 11057static bool use_mmio_flip(struct intel_engine_cs *ring,
11058 struct drm_i915_gem_object *obj)
11059{
11060 /*
11061 * This is not being used for older platforms, because
11062 * non-availability of flip done interrupt forces us to use
11063 * CS flips. Older platforms derive flip done using some clever
11064 * tricks involving the flip_pending status bits and vblank irqs.
11065 * So using MMIO flips there would disrupt this mechanism.
11066 */
11067
8e09bf83
CW		 11068 if (ring == NULL)
11069 return true;
11070
84c33a64
SG		 11071 if (INTEL_INFO(ring->dev)->gen < 5)
11072 return false;
11073
11074 if (i915.use_mmio_flip < 0)
11075 return false;
11076 else if (i915.use_mmio_flip > 0)
11077 return true;
14bf993e
OM		 11078 else if (i915.enable_execlists)
11079 return true;
84c33a64 11080 else
b4716185 11081 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11082}
11083
6042639c 11084static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
86efe24a 11085 unsigned int rotation,
6042639c 11086 struct intel_unpin_work *work)
ff944564
DL		 11087{
11088 struct drm_device *dev = intel_crtc->base.dev;
11089 struct drm_i915_private *dev_priv = dev->dev_private;
11090 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564 11091 const enum pipe pipe = intel_crtc->pipe;
86efe24a 11092 u32 ctl, stride, tile_height;
ff944564
DL		 11093
11094 ctl = I915_READ(PLANE_CTL(pipe, 0));
11095 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11096 switch (fb->modifier[0]) {
11097 case DRM_FORMAT_MOD_NONE:
11098 break;
11099 case I915_FORMAT_MOD_X_TILED:
ff944564 11100 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11101 break;
11102 case I915_FORMAT_MOD_Y_TILED:
11103 ctl |= PLANE_CTL_TILED_Y;
11104 break;
11105 case I915_FORMAT_MOD_Yf_TILED:
11106 ctl |= PLANE_CTL_TILED_YF;
11107 break;
11108 default:
11109 MISSING_CASE(fb->modifier[0]);
11110 }
ff944564
DL		 11111
11112 /*
11113 * The stride is either expressed as a multiple of 64 bytes chunks for
11114 * linear buffers or in number of tiles for tiled buffers.
11115 */
86efe24a
TU		 11116 if (intel_rotation_90_or_270(rotation)) {
11117 /* stride = Surface height in tiles */
11118 tile_height = intel_tile_height(dev, fb->pixel_format,
11119 fb->modifier[0], 0);
11120 stride = DIV_ROUND_UP(fb->height, tile_height);
11121 } else {
11122 stride = fb->pitches[0] /
11123 intel_fb_stride_alignment(dev, fb->modifier[0],
11124 fb->pixel_format);
11125 }
ff944564
DL		 11126
11127 /*
11128 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11129 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11130 */
11131 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11132 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11133
6042639c 11134 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
ff944564
DL		 11135 POSTING_READ(PLANE_SURF(pipe, 0));
11136}
11137
6042639c
CW		 11138static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11139 struct intel_unpin_work *work)
84c33a64
SG		 11140{
11141 struct drm_device *dev = intel_crtc->base.dev;
11142 struct drm_i915_private *dev_priv = dev->dev_private;
11143 struct intel_framebuffer *intel_fb =
11144 to_intel_framebuffer(intel_crtc->base.primary->fb);
11145 struct drm_i915_gem_object *obj = intel_fb->obj;
11146 u32 dspcntr;
11147 u32 reg;
11148
84c33a64
SG		 11149 reg = DSPCNTR(intel_crtc->plane);
11150 dspcntr = I915_READ(reg);
11151
c5d97472
DL		 11152 if (obj->tiling_mode != I915_TILING_NONE)
11153 dspcntr |= DISPPLANE_TILED;
11154 else
11155 dspcntr &= ~DISPPLANE_TILED;
11156
84c33a64
SG		 11157 I915_WRITE(reg, dspcntr);
11158
6042639c 11159 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
84c33a64 11160 POSTING_READ(DSPSURF(intel_crtc->plane));
ff944564
DL		 11161}
11162
11163/*
11164 * XXX: This is the temporary way to update the plane registers until we get
11165 * around to using the usual plane update functions for MMIO flips
11166 */
6042639c 11167static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
ff944564 11168{
6042639c
CW		 11169 struct intel_crtc *crtc = mmio_flip->crtc;
11170 struct intel_unpin_work *work;
11171
11172 spin_lock_irq(&crtc->base.dev->event_lock);
11173 work = crtc->unpin_work;
11174 spin_unlock_irq(&crtc->base.dev->event_lock);
11175 if (work == NULL)
11176 return;
ff944564 11177
6042639c 11178 intel_mark_page_flip_active(work);
ff944564 11179
6042639c 11180 intel_pipe_update_start(crtc);
ff944564 11181
6042639c 11182 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
86efe24a 11183 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
ff944564
DL		 11184 else
11185 /* use_mmio_flip() retricts MMIO flips to ilk+ */
6042639c 11186 ilk_do_mmio_flip(crtc, work);
ff944564 11187
6042639c 11188 intel_pipe_update_end(crtc);
84c33a64
SG		 11189}
11190
9362c7c5 11191static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11192{
b2cfe0ab
CW		 11193 struct intel_mmio_flip *mmio_flip =
11194 container_of(work, struct intel_mmio_flip, work);
84c33a64 11195
6042639c 11196 if (mmio_flip->req) {
eed29a5b 11197 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11198 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11199 false, NULL,
11200 &mmio_flip->i915->rps.mmioflips));
6042639c
CW		 11201 i915_gem_request_unreference__unlocked(mmio_flip->req);
11202 }
84c33a64 11203
6042639c 11204 intel_do_mmio_flip(mmio_flip);
b2cfe0ab 11205 kfree(mmio_flip);
84c33a64
SG		 11206}
11207
11208static int intel_queue_mmio_flip(struct drm_device *dev,
11209 struct drm_crtc *crtc,
86efe24a 11210 struct drm_i915_gem_object *obj)
84c33a64 11211{
b2cfe0ab
CW		 11212 struct intel_mmio_flip *mmio_flip;
11213
11214 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11215 if (mmio_flip == NULL)
11216 return -ENOMEM;
84c33a64 11217
bcafc4e3 11218 mmio_flip->i915 = to_i915(dev);
eed29a5b 11219 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11220 mmio_flip->crtc = to_intel_crtc(crtc);
86efe24a 11221 mmio_flip->rotation = crtc->primary->state->rotation;
536f5b5e 11222
b2cfe0ab
CW		 11223 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11224 schedule_work(&mmio_flip->work);
84c33a64 11225
84c33a64
SG		 11226 return 0;
11227}
11228
8c9f3aaf
JB		 11229static int intel_default_queue_flip(struct drm_device *dev,
11230 struct drm_crtc *crtc,
11231 struct drm_framebuffer *fb,
ed8d1975 11232 struct drm_i915_gem_object *obj,
6258fbe2 11233 struct drm_i915_gem_request *req,
ed8d1975 11234 uint32_t flags)
8c9f3aaf
JB		 11235{
11236 return -ENODEV;
11237}
11238
d6bbafa1
CW		 11239static bool __intel_pageflip_stall_check(struct drm_device *dev,
11240 struct drm_crtc *crtc)
11241{
11242 struct drm_i915_private *dev_priv = dev->dev_private;
11243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11244 struct intel_unpin_work *work = intel_crtc->unpin_work;
11245 u32 addr;
11246
11247 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11248 return true;
11249
908565c2
CW		 11250 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11251 return false;
11252
d6bbafa1
CW		 11253 if (!work->enable_stall_check)
11254 return false;
11255
11256 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11257 if (work->flip_queued_req &&
11258 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11259 return false;
11260
1e3feefd 11261 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11262 }
11263
1e3feefd 11264 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11265 return false;
11266
11267 /* Potential stall - if we see that the flip has happened,
11268 * assume a missed interrupt. */
11269 if (INTEL_INFO(dev)->gen >= 4)
11270 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11271 else
11272 addr = I915_READ(DSPADDR(intel_crtc->plane));
11273
11274 /* There is a potential issue here with a false positive after a flip
11275 * to the same address. We could address this by checking for a
11276 * non-incrementing frame counter.
11277 */
11278 return addr == work->gtt_offset;
11279}
11280
11281void intel_check_page_flip(struct drm_device *dev, int pipe)
11282{
11283 struct drm_i915_private *dev_priv = dev->dev_private;
11284 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11286 struct intel_unpin_work *work;
f326038a 11287
6c51d46f 11288 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11289
11290 if (crtc == NULL)
11291 return;
11292
f326038a 11293 spin_lock(&dev->event_lock);
6ad790c0
CW		 11294 work = intel_crtc->unpin_work;
11295 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11296 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11297 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11298 page_flip_completed(intel_crtc);
6ad790c0 11299 work = NULL;
d6bbafa1 11300 }
6ad790c0
CW		 11301 if (work != NULL &&
11302 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11303 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11304 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11305}
11306
6b95a207
KH		 11307static int intel_crtc_page_flip(struct drm_crtc *crtc,
11308 struct drm_framebuffer *fb,
ed8d1975
KP		 11309 struct drm_pending_vblank_event *event,
11310 uint32_t page_flip_flags)
6b95a207
KH		 11311{
11312 struct drm_device *dev = crtc->dev;
11313 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11314 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11315 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11317 struct drm_plane *primary = crtc->primary;
a071fa00 11318 enum pipe pipe = intel_crtc->pipe;
6b95a207 11319 struct intel_unpin_work *work;
a4872ba6 11320 struct intel_engine_cs *ring;
cf5d8a46 11321 bool mmio_flip;
91af127f 11322 struct drm_i915_gem_request *request = NULL;
52e68630 11323 int ret;
6b95a207 11324
2ff8fde1
MR		 11325 /*
11326 * drm_mode_page_flip_ioctl() should already catch this, but double
11327 * check to be safe. In the future we may enable pageflipping from
11328 * a disabled primary plane.
11329 */
11330 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11331 return -EBUSY;
11332
e6a595d2 11333 /* Can't change pixel format via MI display flips. */
f4510a27 11334 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11335 return -EINVAL;
11336
11337 /*
11338 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11339 * Note that pitch changes could also affect these register.
11340 */
11341 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11342 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11343 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11344 return -EINVAL;
11345
f900db47
CW		 11346 if (i915_terminally_wedged(&dev_priv->gpu_error))
11347 goto out_hang;
11348
b14c5679 11349 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11350 if (work == NULL)
11351 return -ENOMEM;
11352
6b95a207 11353 work->event = event;
b4a98e57 11354 work->crtc = crtc;
ab8d6675 11355 work->old_fb = old_fb;
6b95a207
KH		 11356 INIT_WORK(&work->work, intel_unpin_work_fn);
11357
87b6b101 11358 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11359 if (ret)
11360 goto free_work;
11361
6b95a207 11362 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11363 spin_lock_irq(&dev->event_lock);
6b95a207 11364 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11365 /* Before declaring the flip queue wedged, check if
11366 * the hardware completed the operation behind our backs.
11367 */
11368 if (__intel_pageflip_stall_check(dev, crtc)) {
11369 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11370 page_flip_completed(intel_crtc);
11371 } else {
11372 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11373 spin_unlock_irq(&dev->event_lock);
468f0b44 11374
d6bbafa1
CW		 11375 drm_crtc_vblank_put(crtc);
11376 kfree(work);
11377 return -EBUSY;
11378 }
6b95a207
KH		 11379 }
11380 intel_crtc->unpin_work = work;
5e2d7afc 11381 spin_unlock_irq(&dev->event_lock);
6b95a207 11382
b4a98e57
CW		 11383 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11384 flush_workqueue(dev_priv->wq);
11385
75dfca80 11386 /* Reference the objects for the scheduled work. */
ab8d6675 11387 drm_framebuffer_reference(work->old_fb);
05394f39 11388 drm_gem_object_reference(&obj->base);
6b95a207 11389
f4510a27 11390 crtc->primary->fb = fb;
afd65eb4 11391 update_state_fb(crtc->primary);
1ed1f968 11392
e1f99ce6 11393 work->pending_flip_obj = obj;
e1f99ce6 11394
89ed88ba
CW		 11395 ret = i915_mutex_lock_interruptible(dev);
11396 if (ret)
11397 goto cleanup;
11398
b4a98e57 11399 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11400 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11401
75f7f3ec 11402 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
fd8f507c 11403 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
75f7f3ec 11404
4fa62c89
VS		 11405 if (IS_VALLEYVIEW(dev)) {
11406 ring = &dev_priv->ring[BCS];
ab8d6675 11407 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11408 /* vlv: DISPLAY_FLIP fails to change tiling */
11409 ring = NULL;
48bf5b2d 11410 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11411 ring = &dev_priv->ring[BCS];
4fa62c89 11412 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11413 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11414 if (ring == NULL || ring->id != RCS)
11415 ring = &dev_priv->ring[BCS];
11416 } else {
11417 ring = &dev_priv->ring[RCS];
11418 }
11419
cf5d8a46
CW		 11420 mmio_flip = use_mmio_flip(ring, obj);
11421
11422 /* When using CS flips, we want to emit semaphores between rings.
11423 * However, when using mmio flips we will create a task to do the
11424 * synchronisation, so all we want here is to pin the framebuffer
11425 * into the display plane and skip any waits.
11426 */
7580d774
ML		 11427 if (!mmio_flip) {
11428 ret = i915_gem_object_sync(obj, ring, &request);
11429 if (ret)
11430 goto cleanup_pending;
11431 }
11432
82bc3b2d 11433 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
7580d774 11434 crtc->primary->state);
8c9f3aaf
JB		 11435 if (ret)
11436 goto cleanup_pending;
6b95a207 11437
dedf278c
TU		 11438 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11439 obj, 0);
11440 work->gtt_offset += intel_crtc->dspaddr_offset;
4fa62c89 11441
cf5d8a46 11442 if (mmio_flip) {
86efe24a 11443 ret = intel_queue_mmio_flip(dev, crtc, obj);
d6bbafa1
CW		 11444 if (ret)
11445 goto cleanup_unpin;
11446
f06cc1b9
JH		 11447 i915_gem_request_assign(&work->flip_queued_req,
11448 obj->last_write_req);
d6bbafa1 11449 } else {
6258fbe2
JH		 11450 if (!request) {
11451 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11452 if (ret)
11453 goto cleanup_unpin;
11454 }
11455
11456 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11457 page_flip_flags);
11458 if (ret)
11459 goto cleanup_unpin;
11460
6258fbe2 11461 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11462 }
11463
91af127f 11464 if (request)
75289874 11465 i915_add_request_no_flush(request);
91af127f 11466
1e3feefd 11467 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11468 work->enable_stall_check = true;
4fa62c89 11469
ab8d6675 11470 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11471 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11472 mutex_unlock(&dev->struct_mutex);
a071fa00 11473
4e1e26f1 11474 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11475 intel_frontbuffer_flip_prepare(dev,
11476 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11477
e5510fac
JB		 11478 trace_i915_flip_request(intel_crtc->plane, obj);
11479
6b95a207 11480 return 0;
96b099fd 11481
4fa62c89 11482cleanup_unpin:
82bc3b2d 11483 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11484cleanup_pending:
91af127f
JH		 11485 if (request)
11486 i915_gem_request_cancel(request);
b4a98e57 11487 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11488 mutex_unlock(&dev->struct_mutex);
11489cleanup:
f4510a27 11490 crtc->primary->fb = old_fb;
afd65eb4 11491 update_state_fb(crtc->primary);
89ed88ba
CW		 11492
11493 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11494 drm_framebuffer_unreference(work->old_fb);
96b099fd 11495
5e2d7afc 11496 spin_lock_irq(&dev->event_lock);
96b099fd 11497 intel_crtc->unpin_work = NULL;
5e2d7afc 11498 spin_unlock_irq(&dev->event_lock);
96b099fd 11499
87b6b101 11500 drm_crtc_vblank_put(crtc);
7317c75e 11501free_work:
96b099fd
CW		 11502 kfree(work);
11503
f900db47 11504 if (ret == -EIO) {
02e0efb5
ML		 11505 struct drm_atomic_state *state;
11506 struct drm_plane_state *plane_state;
11507
f900db47 11508out_hang:
02e0efb5
ML		 11509 state = drm_atomic_state_alloc(dev);
11510 if (!state)
11511 return -ENOMEM;
11512 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11513
11514retry:
11515 plane_state = drm_atomic_get_plane_state(state, primary);
11516 ret = PTR_ERR_OR_ZERO(plane_state);
11517 if (!ret) {
11518 drm_atomic_set_fb_for_plane(plane_state, fb);
11519
11520 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11521 if (!ret)
11522 ret = drm_atomic_commit(state);
11523 }
11524
11525 if (ret == -EDEADLK) {
11526 drm_modeset_backoff(state->acquire_ctx);
11527 drm_atomic_state_clear(state);
11528 goto retry;
11529 }
11530
11531 if (ret)
11532 drm_atomic_state_free(state);
11533
f0d3dad3 11534 if (ret == 0 && event) {
5e2d7afc 11535 spin_lock_irq(&dev->event_lock);
a071fa00 11536 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11537 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11538 }
f900db47 11539 }
96b099fd 11540 return ret;
6b95a207
KH		 11541}
11542
da20eabd
ML		 11543
11544/**
11545 * intel_wm_need_update - Check whether watermarks need updating
11546 * @plane: drm plane
11547 * @state: new plane state
11548 *
11549 * Check current plane state versus the new one to determine whether
11550 * watermarks need to be recalculated.
11551 *
11552 * Returns true or false.
11553 */
11554static bool intel_wm_need_update(struct drm_plane *plane,
11555 struct drm_plane_state *state)
11556{
d21fbe87
MR		 11557 struct intel_plane_state *new = to_intel_plane_state(state);
11558 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11559
11560 /* Update watermarks on tiling or size changes. */
da20eabd
ML		 11561 if (!plane->state->fb || !state->fb ||
11562 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
d21fbe87
MR		 11563 plane->state->rotation != state->rotation ||
11564 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11565 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11566 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11567 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
2791a16c 11568 return true;
7809e5ae 11569
2791a16c 11570 return false;
7809e5ae
MR		 11571}
11572
d21fbe87
MR		 11573static bool needs_scaling(struct intel_plane_state *state)
11574{
11575 int src_w = drm_rect_width(&state->src) >> 16;
11576 int src_h = drm_rect_height(&state->src) >> 16;
11577 int dst_w = drm_rect_width(&state->dst);
11578 int dst_h = drm_rect_height(&state->dst);
11579
11580 return (src_w != dst_w || src_h != dst_h);
11581}
11582
da20eabd
ML		 11583int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11584 struct drm_plane_state *plane_state)
11585{
11586 struct drm_crtc *crtc = crtc_state->crtc;
11587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11588 struct drm_plane *plane = plane_state->plane;
11589 struct drm_device *dev = crtc->dev;
11590 struct drm_i915_private *dev_priv = dev->dev_private;
11591 struct intel_plane_state *old_plane_state =
11592 to_intel_plane_state(plane->state);
11593 int idx = intel_crtc->base.base.id, ret;
11594 int i = drm_plane_index(plane);
11595 bool mode_changed = needs_modeset(crtc_state);
11596 bool was_crtc_enabled = crtc->state->active;
11597 bool is_crtc_enabled = crtc_state->active;
da20eabd
ML		 11598 bool turn_off, turn_on, visible, was_visible;
11599 struct drm_framebuffer *fb = plane_state->fb;
11600
11601 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11602 plane->type != DRM_PLANE_TYPE_CURSOR) {
11603 ret = skl_update_scaler_plane(
11604 to_intel_crtc_state(crtc_state),
11605 to_intel_plane_state(plane_state));
11606 if (ret)
11607 return ret;
11608 }
11609
da20eabd
ML		 11610 was_visible = old_plane_state->visible;
11611 visible = to_intel_plane_state(plane_state)->visible;
11612
11613 if (!was_crtc_enabled && WARN_ON(was_visible))
11614 was_visible = false;
11615
11616 if (!is_crtc_enabled && WARN_ON(visible))
11617 visible = false;
11618
11619 if (!was_visible && !visible)
11620 return 0;
11621
11622 turn_off = was_visible && (!visible || mode_changed);
11623 turn_on = visible && (!was_visible || mode_changed);
11624
11625 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11626 plane->base.id, fb ? fb->base.id : -1);
11627
11628 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11629 plane->base.id, was_visible, visible,
11630 turn_off, turn_on, mode_changed);
11631
852eb00d 11632 if (turn_on) {
f015c551 11633 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11634 /* must disable cxsr around plane enable/disable */
11635 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11636 intel_crtc->atomic.disable_cxsr = true;
11637 /* to potentially re-enable cxsr */
11638 intel_crtc->atomic.wait_vblank = true;
11639 intel_crtc->atomic.update_wm_post = true;
11640 }
11641 } else if (turn_off) {
f015c551 11642 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11643 /* must disable cxsr around plane enable/disable */
11644 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11645 if (is_crtc_enabled)
11646 intel_crtc->atomic.wait_vblank = true;
11647 intel_crtc->atomic.disable_cxsr = true;
11648 }
11649 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11650 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11651 }
da20eabd 11652
8be6ca85 11653 if (visible || was_visible)
a9ff8714
VS		 11654 intel_crtc->atomic.fb_bits |=
11655 to_intel_plane(plane)->frontbuffer_bit;
11656
da20eabd
ML		 11657 switch (plane->type) {
11658 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11659 intel_crtc->atomic.pre_disable_primary = turn_off;
11660 intel_crtc->atomic.post_enable_primary = turn_on;
11661
066cf55b
RV		 11662 if (turn_off) {
11663 /*
11664 * FIXME: Actually if we will still have any other
11665 * plane enabled on the pipe we could let IPS enabled
11666 * still, but for now lets consider that when we make
11667 * primary invisible by setting DSPCNTR to 0 on
11668 * update_primary_plane function IPS needs to be
11669 * disable.
11670 */
11671 intel_crtc->atomic.disable_ips = true;
11672
da20eabd 11673 intel_crtc->atomic.disable_fbc = true;
066cf55b 11674 }
da20eabd
ML		 11675
11676 /*
11677 * FBC does not work on some platforms for rotated
11678 * planes, so disable it when rotation is not 0 and
11679 * update it when rotation is set back to 0.
11680 *
11681 * FIXME: This is redundant with the fbc update done in
11682 * the primary plane enable function except that that
11683 * one is done too late. We eventually need to unify
11684 * this.
11685 */
11686
11687 if (visible &&
11688 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11689 dev_priv->fbc.crtc == intel_crtc &&
11690 plane_state->rotation != BIT(DRM_ROTATE_0))
11691 intel_crtc->atomic.disable_fbc = true;
11692
11693 /*
11694 * BDW signals flip done immediately if the plane
11695 * is disabled, even if the plane enable is already
11696 * armed to occur at the next vblank :(
11697 */
11698 if (turn_on && IS_BROADWELL(dev))
11699 intel_crtc->atomic.wait_vblank = true;
11700
11701 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11702 break;
11703 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11704 break;
11705 case DRM_PLANE_TYPE_OVERLAY:
d21fbe87
MR		 11706 /*
11707 * WaCxSRDisabledForSpriteScaling:ivb
11708 *
11709 * cstate->update_wm was already set above, so this flag will
11710 * take effect when we commit and program watermarks.
11711 */
11712 if (IS_IVYBRIDGE(dev) &&
11713 needs_scaling(to_intel_plane_state(plane_state)) &&
11714 !needs_scaling(old_plane_state)) {
11715 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11716 } else if (turn_off && !mode_changed) {
da20eabd
ML		 11717 intel_crtc->atomic.wait_vblank = true;
11718 intel_crtc->atomic.update_sprite_watermarks |=
11719 1 << i;
11720 }
d21fbe87
MR		 11721
11722 break;
da20eabd
ML		 11723 }
11724 return 0;
11725}
11726
6d3a1ce7
ML		 11727static bool encoders_cloneable(const struct intel_encoder *a,
11728 const struct intel_encoder *b)
11729{
11730 /* masks could be asymmetric, so check both ways */
11731 return a == b || (a->cloneable & (1 << b->type) &&
11732 b->cloneable & (1 << a->type));
11733}
11734
11735static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11736 struct intel_crtc *crtc,
11737 struct intel_encoder *encoder)
11738{
11739 struct intel_encoder *source_encoder;
11740 struct drm_connector *connector;
11741 struct drm_connector_state *connector_state;
11742 int i;
11743
11744 for_each_connector_in_state(state, connector, connector_state, i) {
11745 if (connector_state->crtc != &crtc->base)
11746 continue;
11747
11748 source_encoder =
11749 to_intel_encoder(connector_state->best_encoder);
11750 if (!encoders_cloneable(encoder, source_encoder))
11751 return false;
11752 }
11753
11754 return true;
11755}
11756
11757static bool check_encoder_cloning(struct drm_atomic_state *state,
11758 struct intel_crtc *crtc)
11759{
11760 struct intel_encoder *encoder;
11761 struct drm_connector *connector;
11762 struct drm_connector_state *connector_state;
11763 int i;
11764
11765 for_each_connector_in_state(state, connector, connector_state, i) {
11766 if (connector_state->crtc != &crtc->base)
11767 continue;
11768
11769 encoder = to_intel_encoder(connector_state->best_encoder);
11770 if (!check_single_encoder_cloning(state, crtc, encoder))
11771 return false;
11772 }
11773
11774 return true;
11775}
11776
11777static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11778 struct drm_crtc_state *crtc_state)
11779{
cf5a15be 11780 struct drm_device *dev = crtc->dev;
ad421372 11781 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11783 struct intel_crtc_state *pipe_config =
11784 to_intel_crtc_state(crtc_state);
6d3a1ce7 11785 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11786 int ret;
6d3a1ce7
ML		 11787 bool mode_changed = needs_modeset(crtc_state);
11788
11789 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11790 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11791 return -EINVAL;
11792 }
11793
852eb00d
VS		 11794 if (mode_changed && !crtc_state->active)
11795 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11796
ad421372
ML		 11797 if (mode_changed && crtc_state->enable &&
11798 dev_priv->display.crtc_compute_clock &&
11799 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11800 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11801 pipe_config);
11802 if (ret)
11803 return ret;
11804 }
11805
e435d6e5 11806 ret = 0;
86c8bbbe
MR		 11807 if (dev_priv->display.compute_pipe_wm) {
11808 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11809 if (ret)
11810 return ret;
11811 }
11812
e435d6e5
ML		 11813 if (INTEL_INFO(dev)->gen >= 9) {
11814 if (mode_changed)
11815 ret = skl_update_scaler_crtc(pipe_config);
11816
11817 if (!ret)
11818 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11819 pipe_config);
11820 }
11821
11822 return ret;
6d3a1ce7
ML		 11823}
11824
65b38e0d 11825static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11826 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11827 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11828 .atomic_begin = intel_begin_crtc_commit,
11829 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11830 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11831};
11832
d29b2f9d
ACO		 11833static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11834{
11835 struct intel_connector *connector;
11836
11837 for_each_intel_connector(dev, connector) {
11838 if (connector->base.encoder) {
11839 connector->base.state->best_encoder =
11840 connector->base.encoder;
11841 connector->base.state->crtc =
11842 connector->base.encoder->crtc;
11843 } else {
11844 connector->base.state->best_encoder = NULL;
11845 connector->base.state->crtc = NULL;
11846 }
11847 }
11848}
11849
050f7aeb 11850static void
eba905b2 11851connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11852 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11853{
11854 int bpp = pipe_config->pipe_bpp;
11855
11856 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11857 connector->base.base.id,
c23cc417 11858 connector->base.name);
050f7aeb
DV		 11859
11860 /* Don't use an invalid EDID bpc value */
11861 if (connector->base.display_info.bpc &&
11862 connector->base.display_info.bpc * 3 < bpp) {
11863 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11864 bpp, connector->base.display_info.bpc*3);
11865 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11866 }
11867
11868 /* Clamp bpp to 8 on screens without EDID 1.4 */
11869 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11870 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11871 bpp);
11872 pipe_config->pipe_bpp = 24;
11873 }
11874}
11875
4e53c2e0 11876static int
050f7aeb 11877compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11878 struct intel_crtc_state *pipe_config)
4e53c2e0 11879{
050f7aeb 11880 struct drm_device *dev = crtc->base.dev;
1486017f 11881 struct drm_atomic_state *state;
da3ced29
ACO		 11882 struct drm_connector *connector;
11883 struct drm_connector_state *connector_state;
1486017f 11884 int bpp, i;
4e53c2e0 11885
d328c9d7 11886 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11887 bpp = 10*3;
d328c9d7
DV		 11888 else if (INTEL_INFO(dev)->gen >= 5)
11889 bpp = 12*3;
11890 else
11891 bpp = 8*3;
11892
4e53c2e0 11893
4e53c2e0
DV		 11894 pipe_config->pipe_bpp = bpp;
11895
1486017f
ACO		 11896 state = pipe_config->base.state;
11897
4e53c2e0 11898 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11899 for_each_connector_in_state(state, connector, connector_state, i) {
11900 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11901 continue;
11902
da3ced29
ACO		 11903 connected_sink_compute_bpp(to_intel_connector(connector),
11904 pipe_config);
4e53c2e0
DV		 11905 }
11906
11907 return bpp;
11908}
11909
644db711
DV		 11910static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11911{
11912 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11913 "type: 0x%x flags: 0x%x\n",
1342830c 11914 mode->crtc_clock,
644db711
DV		 11915 mode->crtc_hdisplay, mode->crtc_hsync_start,
11916 mode->crtc_hsync_end, mode->crtc_htotal,
11917 mode->crtc_vdisplay, mode->crtc_vsync_start,
11918 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11919}
11920
c0b03411 11921static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11922 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11923 const char *context)
11924{
6a60cd87
CK		 11925 struct drm_device *dev = crtc->base.dev;
11926 struct drm_plane *plane;
11927 struct intel_plane *intel_plane;
11928 struct intel_plane_state *state;
11929 struct drm_framebuffer *fb;
11930
11931 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11932 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11933
11934 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11935 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11936 pipe_config->pipe_bpp, pipe_config->dither);
11937 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11938 pipe_config->has_pch_encoder,
11939 pipe_config->fdi_lanes,
11940 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11941 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11942 pipe_config->fdi_m_n.tu);
90a6b7b0 11943 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11944 pipe_config->has_dp_encoder,
90a6b7b0 11945 pipe_config->lane_count,
eb14cb74
VS		 11946 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11947 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11948 pipe_config->dp_m_n.tu);
b95af8be 11949
90a6b7b0 11950 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11951 pipe_config->has_dp_encoder,
90a6b7b0 11952 pipe_config->lane_count,
b95af8be
VK		 11953 pipe_config->dp_m2_n2.gmch_m,
11954 pipe_config->dp_m2_n2.gmch_n,
11955 pipe_config->dp_m2_n2.link_m,
11956 pipe_config->dp_m2_n2.link_n,
11957 pipe_config->dp_m2_n2.tu);
11958
55072d19
DV		 11959 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11960 pipe_config->has_audio,
11961 pipe_config->has_infoframe);
11962
c0b03411 11963 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11964 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11965 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11966 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11967 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11968 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11969 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11970 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11971 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11972 crtc->num_scalers,
11973 pipe_config->scaler_state.scaler_users,
11974 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11975 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11976 pipe_config->gmch_pfit.control,
11977 pipe_config->gmch_pfit.pgm_ratios,
11978 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11979 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11980 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11981 pipe_config->pch_pfit.size,
11982 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11983 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11984 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11985
415ff0f6 11986 if (IS_BROXTON(dev)) {
05712c15 11987 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11988 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11989 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 11990 pipe_config->ddi_pll_sel,
11991 pipe_config->dpll_hw_state.ebb0,
05712c15 11992 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 11993 pipe_config->dpll_hw_state.pll0,
11994 pipe_config->dpll_hw_state.pll1,
11995 pipe_config->dpll_hw_state.pll2,
11996 pipe_config->dpll_hw_state.pll3,
11997 pipe_config->dpll_hw_state.pll6,
11998 pipe_config->dpll_hw_state.pll8,
05712c15 11999 pipe_config->dpll_hw_state.pll9,
c8453338 12000 pipe_config->dpll_hw_state.pll10,
415ff0f6 12001 pipe_config->dpll_hw_state.pcsdw12);
ef11bdb3 12002 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
415ff0f6
TU		 12003 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12004 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12005 pipe_config->ddi_pll_sel,
12006 pipe_config->dpll_hw_state.ctrl1,
12007 pipe_config->dpll_hw_state.cfgcr1,
12008 pipe_config->dpll_hw_state.cfgcr2);
12009 } else if (HAS_DDI(dev)) {
12010 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12011 pipe_config->ddi_pll_sel,
12012 pipe_config->dpll_hw_state.wrpll);
12013 } else {
12014 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12015 "fp0: 0x%x, fp1: 0x%x\n",
12016 pipe_config->dpll_hw_state.dpll,
12017 pipe_config->dpll_hw_state.dpll_md,
12018 pipe_config->dpll_hw_state.fp0,
12019 pipe_config->dpll_hw_state.fp1);
12020 }
12021
6a60cd87
CK		 12022 DRM_DEBUG_KMS("planes on this crtc\n");
12023 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12024 intel_plane = to_intel_plane(plane);
12025 if (intel_plane->pipe != crtc->pipe)
12026 continue;
12027
12028 state = to_intel_plane_state(plane->state);
12029 fb = state->base.fb;
12030 if (!fb) {
12031 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12032 "disabled, scaler_id = %d\n",
12033 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12034 plane->base.id, intel_plane->pipe,
12035 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12036 drm_plane_index(plane), state->scaler_id);
12037 continue;
12038 }
12039
12040 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12041 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12042 plane->base.id, intel_plane->pipe,
12043 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12044 drm_plane_index(plane));
12045 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12046 fb->base.id, fb->width, fb->height, fb->pixel_format);
12047 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12048 state->scaler_id,
12049 state->src.x1 >> 16, state->src.y1 >> 16,
12050 drm_rect_width(&state->src) >> 16,
12051 drm_rect_height(&state->src) >> 16,
12052 state->dst.x1, state->dst.y1,
12053 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12054 }
c0b03411
DV		 12055}
12056
5448a00d 12057static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12058{
5448a00d
ACO		 12059 struct drm_device *dev = state->dev;
12060 struct intel_encoder *encoder;
da3ced29 12061 struct drm_connector *connector;
5448a00d 12062 struct drm_connector_state *connector_state;
00f0b378 12063 unsigned int used_ports = 0;
5448a00d 12064 int i;
00f0b378
VS		 12065
12066 /*
12067 * Walk the connector list instead of the encoder
12068 * list to detect the problem on ddi platforms
12069 * where there's just one encoder per digital port.
12070 */
da3ced29 12071 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12072 if (!connector_state->best_encoder)
00f0b378
VS		 12073 continue;
12074
5448a00d
ACO		 12075 encoder = to_intel_encoder(connector_state->best_encoder);
12076
12077 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12078
12079 switch (encoder->type) {
12080 unsigned int port_mask;
12081 case INTEL_OUTPUT_UNKNOWN:
12082 if (WARN_ON(!HAS_DDI(dev)))
12083 break;
12084 case INTEL_OUTPUT_DISPLAYPORT:
12085 case INTEL_OUTPUT_HDMI:
12086 case INTEL_OUTPUT_EDP:
12087 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12088
12089 /* the same port mustn't appear more than once */
12090 if (used_ports & port_mask)
12091 return false;
12092
12093 used_ports |= port_mask;
12094 default:
12095 break;
12096 }
12097 }
12098
12099 return true;
12100}
12101
83a57153
ACO		 12102static void
12103clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12104{
12105 struct drm_crtc_state tmp_state;
663a3640 12106 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12107 struct intel_dpll_hw_state dpll_hw_state;
12108 enum intel_dpll_id shared_dpll;
8504c74c 12109 uint32_t ddi_pll_sel;
c4e2d043 12110 bool force_thru;
83a57153 12111
7546a384
ACO		 12112 /* FIXME: before the switch to atomic started, a new pipe_config was
12113 * kzalloc'd. Code that depends on any field being zero should be
12114 * fixed, so that the crtc_state can be safely duplicated. For now,
12115 * only fields that are know to not cause problems are preserved. */
12116
83a57153 12117 tmp_state = crtc_state->base;
663a3640 12118 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12119 shared_dpll = crtc_state->shared_dpll;
12120 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12121 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12122 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12123
83a57153 12124 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12125
83a57153 12126 crtc_state->base = tmp_state;
663a3640 12127 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12128 crtc_state->shared_dpll = shared_dpll;
12129 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12130 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12131 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12132}
12133
548ee15b 12134static int
b8cecdf5 12135intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12136 struct intel_crtc_state *pipe_config)
ee7b9f93 12137{
b359283a 12138 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12139 struct intel_encoder *encoder;
da3ced29 12140 struct drm_connector *connector;
0b901879 12141 struct drm_connector_state *connector_state;
d328c9d7 12142 int base_bpp, ret = -EINVAL;
0b901879 12143 int i;
e29c22c0 12144 bool retry = true;
ee7b9f93 12145
83a57153 12146 clear_intel_crtc_state(pipe_config);
7758a113 12147
e143a21c
DV		 12148 pipe_config->cpu_transcoder =
12149 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12150
2960bc9c
ID		 12151 /*
12152 * Sanitize sync polarity flags based on requested ones. If neither
12153 * positive or negative polarity is requested, treat this as meaning
12154 * negative polarity.
12155 */
2d112de7 12156 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12157 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12158 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12159
2d112de7 12160 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12161 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12162 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12163
d328c9d7
DV		 12164 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12165 pipe_config);
12166 if (base_bpp < 0)
4e53c2e0
DV		 12167 goto fail;
12168
e41a56be
VS		 12169 /*
12170 * Determine the real pipe dimensions. Note that stereo modes can
12171 * increase the actual pipe size due to the frame doubling and
12172 * insertion of additional space for blanks between the frame. This
12173 * is stored in the crtc timings. We use the requested mode to do this
12174 * computation to clearly distinguish it from the adjusted mode, which
12175 * can be changed by the connectors in the below retry loop.
12176 */
2d112de7 12177 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12178 &pipe_config->pipe_src_w,
12179 &pipe_config->pipe_src_h);
e41a56be 12180
e29c22c0 12181encoder_retry:
ef1b460d 12182 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12183 pipe_config->port_clock = 0;
ef1b460d 12184 pipe_config->pixel_multiplier = 1;
ff9a6750 12185
135c81b8 12186 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12187 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12188 CRTC_STEREO_DOUBLE);
135c81b8 12189
7758a113
DV		 12190 /* Pass our mode to the connectors and the CRTC to give them a chance to
12191 * adjust it according to limitations or connector properties, and also
12192 * a chance to reject the mode entirely.
47f1c6c9 12193 */
da3ced29 12194 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12195 if (connector_state->crtc != crtc)
7758a113 12196 continue;
7ae89233 12197
0b901879
ACO		 12198 encoder = to_intel_encoder(connector_state->best_encoder);
12199
efea6e8e
DV		 12200 if (!(encoder->compute_config(encoder, pipe_config))) {
12201 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12202 goto fail;
12203 }
ee7b9f93 12204 }
47f1c6c9 12205
ff9a6750
DV		 12206 /* Set default port clock if not overwritten by the encoder. Needs to be
12207 * done afterwards in case the encoder adjusts the mode. */
12208 if (!pipe_config->port_clock)
2d112de7 12209 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12210 * pipe_config->pixel_multiplier;
ff9a6750 12211
a43f6e0f 12212 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12213 if (ret < 0) {
7758a113
DV		 12214 DRM_DEBUG_KMS("CRTC fixup failed\n");
12215 goto fail;
ee7b9f93 12216 }
e29c22c0
DV		 12217
12218 if (ret == RETRY) {
12219 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12220 ret = -EINVAL;
12221 goto fail;
12222 }
12223
12224 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12225 retry = false;
12226 goto encoder_retry;
12227 }
12228
e8fa4270
DV		 12229 /* Dithering seems to not pass-through bits correctly when it should, so
12230 * only enable it on 6bpc panels. */
12231 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12232 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12233 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12234
7758a113 12235fail:
548ee15b 12236 return ret;
ee7b9f93 12237}
47f1c6c9 12238
ea9d758d 12239static void
4740b0f2 12240intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12241{
0a9ab303
ACO		 12242 struct drm_crtc *crtc;
12243 struct drm_crtc_state *crtc_state;
8a75d157 12244 int i;
ea9d758d 12245
7668851f 12246 /* Double check state. */
8a75d157 12247 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12248 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12249
12250 /* Update hwmode for vblank functions */
12251 if (crtc->state->active)
12252 crtc->hwmode = crtc->state->adjusted_mode;
12253 else
12254 crtc->hwmode.crtc_clock = 0;
61067a5e
ML		 12255
12256 /*
12257 * Update legacy state to satisfy fbc code. This can
12258 * be removed when fbc uses the atomic state.
12259 */
12260 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12261 struct drm_plane_state *plane_state = crtc->primary->state;
12262
12263 crtc->primary->fb = plane_state->fb;
12264 crtc->x = plane_state->src_x >> 16;
12265 crtc->y = plane_state->src_y >> 16;
12266 }
ea9d758d 12267 }
ea9d758d
DV		 12268}
12269
3bd26263 12270static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12271{
3bd26263 12272 int diff;
f1f644dc
JB		 12273
12274 if (clock1 == clock2)
12275 return true;
12276
12277 if (!clock1 || !clock2)
12278 return false;
12279
12280 diff = abs(clock1 - clock2);
12281
12282 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12283 return true;
12284
12285 return false;
12286}
12287
25c5b266
DV		 12288#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12289 list_for_each_entry((intel_crtc), \
12290 &(dev)->mode_config.crtc_list, \
12291 base.head) \
0973f18f 12292 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12293
cfb23ed6
ML		 12294static bool
12295intel_compare_m_n(unsigned int m, unsigned int n,
12296 unsigned int m2, unsigned int n2,
12297 bool exact)
12298{
12299 if (m == m2 && n == n2)
12300 return true;
12301
12302 if (exact || !m || !n || !m2 || !n2)
12303 return false;
12304
12305 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12306
12307 if (m > m2) {
12308 while (m > m2) {
12309 m2 <<= 1;
12310 n2 <<= 1;
12311 }
12312 } else if (m < m2) {
12313 while (m < m2) {
12314 m <<= 1;
12315 n <<= 1;
12316 }
12317 }
12318
12319 return m == m2 && n == n2;
12320}
12321
12322static bool
12323intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12324 struct intel_link_m_n *m2_n2,
12325 bool adjust)
12326{
12327 if (m_n->tu == m2_n2->tu &&
12328 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12329 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12330 intel_compare_m_n(m_n->link_m, m_n->link_n,
12331 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12332 if (adjust)
12333 *m2_n2 = *m_n;
12334
12335 return true;
12336 }
12337
12338 return false;
12339}
12340
0e8ffe1b 12341static bool
2fa2fe9a 12342intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12343 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12344 struct intel_crtc_state *pipe_config,
12345 bool adjust)
0e8ffe1b 12346{
cfb23ed6
ML		 12347 bool ret = true;
12348
12349#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12350 do { \
12351 if (!adjust) \
12352 DRM_ERROR(fmt, ##__VA_ARGS__); \
12353 else \
12354 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12355 } while (0)
12356
66e985c0
DV		 12357#define PIPE_CONF_CHECK_X(name) \
12358 if (current_config->name != pipe_config->name) { \
cfb23ed6 12359 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12360 "(expected 0x%08x, found 0x%08x)\n", \
12361 current_config->name, \
12362 pipe_config->name); \
cfb23ed6 12363 ret = false; \
66e985c0
DV		 12364 }
12365
08a24034
DV		 12366#define PIPE_CONF_CHECK_I(name) \
12367 if (current_config->name != pipe_config->name) { \
cfb23ed6 12368 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12369 "(expected %i, found %i)\n", \
12370 current_config->name, \
12371 pipe_config->name); \
cfb23ed6
ML		 12372 ret = false; \
12373 }
12374
12375#define PIPE_CONF_CHECK_M_N(name) \
12376 if (!intel_compare_link_m_n(&current_config->name, \
12377 &pipe_config->name,\
12378 adjust)) { \
12379 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12380 "(expected tu %i gmch %i/%i link %i/%i, " \
12381 "found tu %i, gmch %i/%i link %i/%i)\n", \
12382 current_config->name.tu, \
12383 current_config->name.gmch_m, \
12384 current_config->name.gmch_n, \
12385 current_config->name.link_m, \
12386 current_config->name.link_n, \
12387 pipe_config->name.tu, \
12388 pipe_config->name.gmch_m, \
12389 pipe_config->name.gmch_n, \
12390 pipe_config->name.link_m, \
12391 pipe_config->name.link_n); \
12392 ret = false; \
12393 }
12394
12395#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12396 if (!intel_compare_link_m_n(&current_config->name, \
12397 &pipe_config->name, adjust) && \
12398 !intel_compare_link_m_n(&current_config->alt_name, \
12399 &pipe_config->name, adjust)) { \
12400 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12401 "(expected tu %i gmch %i/%i link %i/%i, " \
12402 "or tu %i gmch %i/%i link %i/%i, " \
12403 "found tu %i, gmch %i/%i link %i/%i)\n", \
12404 current_config->name.tu, \
12405 current_config->name.gmch_m, \
12406 current_config->name.gmch_n, \
12407 current_config->name.link_m, \
12408 current_config->name.link_n, \
12409 current_config->alt_name.tu, \
12410 current_config->alt_name.gmch_m, \
12411 current_config->alt_name.gmch_n, \
12412 current_config->alt_name.link_m, \
12413 current_config->alt_name.link_n, \
12414 pipe_config->name.tu, \
12415 pipe_config->name.gmch_m, \
12416 pipe_config->name.gmch_n, \
12417 pipe_config->name.link_m, \
12418 pipe_config->name.link_n); \
12419 ret = false; \
88adfff1
DV		 12420 }
12421
b95af8be
VK		 12422/* This is required for BDW+ where there is only one set of registers for
12423 * switching between high and low RR.
12424 * This macro can be used whenever a comparison has to be made between one
12425 * hw state and multiple sw state variables.
12426 */
12427#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12428 if ((current_config->name != pipe_config->name) && \
12429 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12430 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12431 "(expected %i or %i, found %i)\n", \
12432 current_config->name, \
12433 current_config->alt_name, \
12434 pipe_config->name); \
cfb23ed6 12435 ret = false; \
b95af8be
VK		 12436 }
12437
1bd1bd80
DV		 12438#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12439 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12440 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12441 "(expected %i, found %i)\n", \
12442 current_config->name & (mask), \
12443 pipe_config->name & (mask)); \
cfb23ed6 12444 ret = false; \
1bd1bd80
DV		 12445 }
12446
5e550656
VS		 12447#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12448 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12449 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12450 "(expected %i, found %i)\n", \
12451 current_config->name, \
12452 pipe_config->name); \
cfb23ed6 12453 ret = false; \
5e550656
VS		 12454 }
12455
bb760063
DV		 12456#define PIPE_CONF_QUIRK(quirk) \
12457 ((current_config->quirks | pipe_config->quirks) & (quirk))
12458
eccb140b
DV		 12459 PIPE_CONF_CHECK_I(cpu_transcoder);
12460
08a24034
DV		 12461 PIPE_CONF_CHECK_I(has_pch_encoder);
12462 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12463 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12464
eb14cb74 12465 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12466 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12467
12468 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12469 PIPE_CONF_CHECK_M_N(dp_m_n);
12470
12471 PIPE_CONF_CHECK_I(has_drrs);
12472 if (current_config->has_drrs)
12473 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12474 } else
12475 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12476
2d112de7
ACO		 12477 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12478 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12479 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12480 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12481 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12482 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12483
2d112de7
ACO		 12484 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12485 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12486 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12487 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12488 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12489 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12490
c93f54cf 12491 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12492 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12493 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12494 IS_VALLEYVIEW(dev))
12495 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12496 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12497
9ed109a7
DV		 12498 PIPE_CONF_CHECK_I(has_audio);
12499
2d112de7 12500 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12501 DRM_MODE_FLAG_INTERLACE);
12502
bb760063 12503 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12504 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12505 DRM_MODE_FLAG_PHSYNC);
2d112de7 12506 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12507 DRM_MODE_FLAG_NHSYNC);
2d112de7 12508 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12509 DRM_MODE_FLAG_PVSYNC);
2d112de7 12510 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12511 DRM_MODE_FLAG_NVSYNC);
12512 }
045ac3b5 12513
333b8ca8 12514 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV		 12515 /* pfit ratios are autocomputed by the hw on gen4+ */
12516 if (INTEL_INFO(dev)->gen < 4)
12517 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
333b8ca8 12518 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12519
bfd16b2a
ML		 12520 if (!adjust) {
12521 PIPE_CONF_CHECK_I(pipe_src_w);
12522 PIPE_CONF_CHECK_I(pipe_src_h);
12523
12524 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12525 if (current_config->pch_pfit.enabled) {
12526 PIPE_CONF_CHECK_X(pch_pfit.pos);
12527 PIPE_CONF_CHECK_X(pch_pfit.size);
12528 }
2fa2fe9a 12529
7aefe2b5
ML		 12530 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12531 }
a1b2278e 12532
e59150dc
JB		 12533 /* BDW+ don't expose a synchronous way to read the state */
12534 if (IS_HASWELL(dev))
12535 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12536
282740f7
VS		 12537 PIPE_CONF_CHECK_I(double_wide);
12538
26804afd
DV		 12539 PIPE_CONF_CHECK_X(ddi_pll_sel);
12540
c0d43d62 12541 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12542 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12543 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12544 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12545 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12546 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12547 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12548 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12549 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12550
42571aef
VS		 12551 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12552 PIPE_CONF_CHECK_I(pipe_bpp);
12553
2d112de7 12554 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12555 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12556
66e985c0 12557#undef PIPE_CONF_CHECK_X
08a24034 12558#undef PIPE_CONF_CHECK_I
b95af8be 12559#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12560#undef PIPE_CONF_CHECK_FLAGS
5e550656 12561#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12562#undef PIPE_CONF_QUIRK
cfb23ed6 12563#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12564
cfb23ed6 12565 return ret;
0e8ffe1b
DV		 12566}
12567
08db6652
DL		 12568static void check_wm_state(struct drm_device *dev)
12569{
12570 struct drm_i915_private *dev_priv = dev->dev_private;
12571 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12572 struct intel_crtc *intel_crtc;
12573 int plane;
12574
12575 if (INTEL_INFO(dev)->gen < 9)
12576 return;
12577
12578 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12579 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12580
12581 for_each_intel_crtc(dev, intel_crtc) {
12582 struct skl_ddb_entry *hw_entry, *sw_entry;
12583 const enum pipe pipe = intel_crtc->pipe;
12584
12585 if (!intel_crtc->active)
12586 continue;
12587
12588 /* planes */
dd740780 12589 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12590 hw_entry = &hw_ddb.plane[pipe][plane];
12591 sw_entry = &sw_ddb->plane[pipe][plane];
12592
12593 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12594 continue;
12595
12596 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12597 "(expected (%u,%u), found (%u,%u))\n",
12598 pipe_name(pipe), plane + 1,
12599 sw_entry->start, sw_entry->end,
12600 hw_entry->start, hw_entry->end);
12601 }
12602
12603 /* cursor */
4969d33e
MR		 12604 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12605 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
08db6652
DL		 12606
12607 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12608 continue;
12609
12610 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12611 "(expected (%u,%u), found (%u,%u))\n",
12612 pipe_name(pipe),
12613 sw_entry->start, sw_entry->end,
12614 hw_entry->start, hw_entry->end);
12615 }
12616}
12617
91d1b4bd 12618static void
35dd3c64
ML		 12619check_connector_state(struct drm_device *dev,
12620 struct drm_atomic_state *old_state)
8af6cf88 12621{
35dd3c64
ML		 12622 struct drm_connector_state *old_conn_state;
12623 struct drm_connector *connector;
12624 int i;
8af6cf88 12625
35dd3c64
ML		 12626 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12627 struct drm_encoder *encoder = connector->encoder;
12628 struct drm_connector_state *state = connector->state;
ad3c558f 12629
8af6cf88
DV		 12630 /* This also checks the encoder/connector hw state with the
12631 * ->get_hw_state callbacks. */
35dd3c64 12632 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12633
ad3c558f 12634 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12635 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12636 }
91d1b4bd
DV		 12637}
12638
12639static void
12640check_encoder_state(struct drm_device *dev)
12641{
12642 struct intel_encoder *encoder;
12643 struct intel_connector *connector;
8af6cf88 12644
b2784e15 12645 for_each_intel_encoder(dev, encoder) {
8af6cf88 12646 bool enabled = false;
4d20cd86 12647 enum pipe pipe;
8af6cf88
DV		 12648
12649 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12650 encoder->base.base.id,
8e329a03 12651 encoder->base.name);
8af6cf88 12652
3a3371ff 12653 for_each_intel_connector(dev, connector) {
4d20cd86 12654 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12655 continue;
12656 enabled = true;
ad3c558f
ML		 12657
12658 I915_STATE_WARN(connector->base.state->crtc !=
12659 encoder->base.crtc,
12660 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12661 }
0e32b39c 12662
e2c719b7 12663 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12664 "encoder's enabled state mismatch "
12665 "(expected %i, found %i)\n",
12666 !!encoder->base.crtc, enabled);
7c60d198
ML		 12667
12668 if (!encoder->base.crtc) {
4d20cd86 12669 bool active;
7c60d198 12670
4d20cd86
ML		 12671 active = encoder->get_hw_state(encoder, &pipe);
12672 I915_STATE_WARN(active,
12673 "encoder detached but still enabled on pipe %c.\n",
12674 pipe_name(pipe));
7c60d198 12675 }
8af6cf88 12676 }
91d1b4bd
DV		 12677}
12678
12679static void
4d20cd86 12680check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12681{
fbee40df 12682 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12683 struct intel_encoder *encoder;
4d20cd86
ML		 12684 struct drm_crtc_state *old_crtc_state;
12685 struct drm_crtc *crtc;
12686 int i;
8af6cf88 12687
4d20cd86
ML		 12688 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12690 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12691 bool active;
8af6cf88 12692
bfd16b2a
ML		 12693 if (!needs_modeset(crtc->state) &&
12694 !to_intel_crtc_state(crtc->state)->update_pipe)
4d20cd86 12695 continue;
045ac3b5 12696
4d20cd86
ML		 12697 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12698 pipe_config = to_intel_crtc_state(old_crtc_state);
12699 memset(pipe_config, 0, sizeof(*pipe_config));
12700 pipe_config->base.crtc = crtc;
12701 pipe_config->base.state = old_state;
8af6cf88 12702
4d20cd86
ML		 12703 DRM_DEBUG_KMS("[CRTC:%d]\n",
12704 crtc->base.id);
8af6cf88 12705
4d20cd86
ML		 12706 active = dev_priv->display.get_pipe_config(intel_crtc,
12707 pipe_config);
d62cf62a 12708
b6b5d049 12709 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12710 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12711 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12712 active = crtc->state->active;
6c49f241 12713
4d20cd86 12714 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12715 "crtc active state doesn't match with hw state "
4d20cd86 12716 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12717
4d20cd86 12718 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12719 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12720 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12721
12722 for_each_encoder_on_crtc(dev, crtc, encoder) {
12723 enum pipe pipe;
12724
12725 active = encoder->get_hw_state(encoder, &pipe);
12726 I915_STATE_WARN(active != crtc->state->active,
12727 "[ENCODER:%i] active %i with crtc active %i\n",
12728 encoder->base.base.id, active, crtc->state->active);
12729
12730 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12731 "Encoder connected to wrong pipe %c\n",
12732 pipe_name(pipe));
12733
12734 if (active)
12735 encoder->get_config(encoder, pipe_config);
12736 }
53d9f4e9 12737
4d20cd86 12738 if (!crtc->state->active)
cfb23ed6
ML		 12739 continue;
12740
4d20cd86
ML		 12741 sw_config = to_intel_crtc_state(crtc->state);
12742 if (!intel_pipe_config_compare(dev, sw_config,
12743 pipe_config, false)) {
e2c719b7 12744 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12745 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12746 "[hw state]");
4d20cd86 12747 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12748 "[sw state]");
12749 }
8af6cf88
DV		 12750 }
12751}
12752
91d1b4bd
DV		 12753static void
12754check_shared_dpll_state(struct drm_device *dev)
12755{
fbee40df 12756 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12757 struct intel_crtc *crtc;
12758 struct intel_dpll_hw_state dpll_hw_state;
12759 int i;
5358901f
DV		 12760
12761 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12762 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12763 int enabled_crtcs = 0, active_crtcs = 0;
12764 bool active;
12765
12766 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12767
12768 DRM_DEBUG_KMS("%s\n", pll->name);
12769
12770 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12771
e2c719b7 12772 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12773 "more active pll users than references: %i vs %i\n",
3e369b76 12774 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12775 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12776 "pll in active use but not on in sw tracking\n");
e2c719b7 12777 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12778 "pll in on but not on in use in sw tracking\n");
e2c719b7 12779 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12780 "pll on state mismatch (expected %i, found %i)\n",
12781 pll->on, active);
12782
d3fcc808 12783 for_each_intel_crtc(dev, crtc) {
83d65738 12784 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12785 enabled_crtcs++;
12786 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12787 active_crtcs++;
12788 }
e2c719b7 12789 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12790 "pll active crtcs mismatch (expected %i, found %i)\n",
12791 pll->active, active_crtcs);
e2c719b7 12792 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12793 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12794 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12795
e2c719b7 12796 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12797 sizeof(dpll_hw_state)),
12798 "pll hw state mismatch\n");
5358901f 12799 }
8af6cf88
DV		 12800}
12801
ee165b1a
ML		 12802static void
12803intel_modeset_check_state(struct drm_device *dev,
12804 struct drm_atomic_state *old_state)
91d1b4bd 12805{
08db6652 12806 check_wm_state(dev);
35dd3c64 12807 check_connector_state(dev, old_state);
91d1b4bd 12808 check_encoder_state(dev);
4d20cd86 12809 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12810 check_shared_dpll_state(dev);
12811}
12812
5cec258b 12813void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12814 int dotclock)
12815{
12816 /*
12817 * FDI already provided one idea for the dotclock.
12818 * Yell if the encoder disagrees.
12819 */
2d112de7 12820 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12821 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12822 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12823}
12824
80715b2f
VS		 12825static void update_scanline_offset(struct intel_crtc *crtc)
12826{
12827 struct drm_device *dev = crtc->base.dev;
12828
12829 /*
12830 * The scanline counter increments at the leading edge of hsync.
12831 *
12832 * On most platforms it starts counting from vtotal-1 on the
12833 * first active line. That means the scanline counter value is
12834 * always one less than what we would expect. Ie. just after
12835 * start of vblank, which also occurs at start of hsync (on the
12836 * last active line), the scanline counter will read vblank_start-1.
12837 *
12838 * On gen2 the scanline counter starts counting from 1 instead
12839 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12840 * to keep the value positive), instead of adding one.
12841 *
12842 * On HSW+ the behaviour of the scanline counter depends on the output
12843 * type. For DP ports it behaves like most other platforms, but on HDMI
12844 * there's an extra 1 line difference. So we need to add two instead of
12845 * one to the value.
12846 */
12847 if (IS_GEN2(dev)) {
124abe07 12848 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12849 int vtotal;
12850
124abe07
VS		 12851 vtotal = adjusted_mode->crtc_vtotal;
12852 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
80715b2f
VS		 12853 vtotal /= 2;
12854
12855 crtc->scanline_offset = vtotal - 1;
12856 } else if (HAS_DDI(dev) &&
409ee761 12857 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12858 crtc->scanline_offset = 2;
12859 } else
12860 crtc->scanline_offset = 1;
12861}
12862
ad421372 12863static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12864{
225da59b 12865 struct drm_device *dev = state->dev;
ed6739ef 12866 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12867 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12868 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12869 struct intel_crtc_state *intel_crtc_state;
12870 struct drm_crtc *crtc;
12871 struct drm_crtc_state *crtc_state;
0a9ab303 12872 int i;
ed6739ef
ACO		 12873
12874 if (!dev_priv->display.crtc_compute_clock)
ad421372 12875 return;
ed6739ef 12876
0a9ab303 12877 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12878 int dpll;
12879
0a9ab303 12880 intel_crtc = to_intel_crtc(crtc);
4978cc93 12881 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12882 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12883
ad421372 12884 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12885 continue;
12886
ad421372 12887 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12888
ad421372
ML		 12889 if (!shared_dpll)
12890 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12891
ad421372
ML		 12892 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12893 }
ed6739ef
ACO		 12894}
12895
99d736a2
ML		 12896/*
12897 * This implements the workaround described in the "notes" section of the mode
12898 * set sequence documentation. When going from no pipes or single pipe to
12899 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12900 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12901 */
12902static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12903{
12904 struct drm_crtc_state *crtc_state;
12905 struct intel_crtc *intel_crtc;
12906 struct drm_crtc *crtc;
12907 struct intel_crtc_state *first_crtc_state = NULL;
12908 struct intel_crtc_state *other_crtc_state = NULL;
12909 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12910 int i;
12911
12912 /* look at all crtc's that are going to be enabled in during modeset */
12913 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12914 intel_crtc = to_intel_crtc(crtc);
12915
12916 if (!crtc_state->active || !needs_modeset(crtc_state))
12917 continue;
12918
12919 if (first_crtc_state) {
12920 other_crtc_state = to_intel_crtc_state(crtc_state);
12921 break;
12922 } else {
12923 first_crtc_state = to_intel_crtc_state(crtc_state);
12924 first_pipe = intel_crtc->pipe;
12925 }
12926 }
12927
12928 /* No workaround needed? */
12929 if (!first_crtc_state)
12930 return 0;
12931
12932 /* w/a possibly needed, check how many crtc's are already enabled. */
12933 for_each_intel_crtc(state->dev, intel_crtc) {
12934 struct intel_crtc_state *pipe_config;
12935
12936 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12937 if (IS_ERR(pipe_config))
12938 return PTR_ERR(pipe_config);
12939
12940 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12941
12942 if (!pipe_config->base.active ||
12943 needs_modeset(&pipe_config->base))
12944 continue;
12945
12946 /* 2 or more enabled crtcs means no need for w/a */
12947 if (enabled_pipe != INVALID_PIPE)
12948 return 0;
12949
12950 enabled_pipe = intel_crtc->pipe;
12951 }
12952
12953 if (enabled_pipe != INVALID_PIPE)
12954 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12955 else if (other_crtc_state)
12956 other_crtc_state->hsw_workaround_pipe = first_pipe;
12957
12958 return 0;
12959}
12960
27c329ed
ML		 12961static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12962{
12963 struct drm_crtc *crtc;
12964 struct drm_crtc_state *crtc_state;
12965 int ret = 0;
12966
12967 /* add all active pipes to the state */
12968 for_each_crtc(state->dev, crtc) {
12969 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12970 if (IS_ERR(crtc_state))
12971 return PTR_ERR(crtc_state);
12972
12973 if (!crtc_state->active || needs_modeset(crtc_state))
12974 continue;
12975
12976 crtc_state->mode_changed = true;
12977
12978 ret = drm_atomic_add_affected_connectors(state, crtc);
12979 if (ret)
12980 break;
12981
12982 ret = drm_atomic_add_affected_planes(state, crtc);
12983 if (ret)
12984 break;
12985 }
12986
12987 return ret;
12988}
12989
c347a676 12990static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12991{
12992 struct drm_device *dev = state->dev;
27c329ed 12993 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12994 int ret;
12995
b359283a
ML		 12996 if (!check_digital_port_conflicts(state)) {
12997 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12998 return -EINVAL;
12999 }
13000
054518dd
ACO		 13001 /*
13002 * See if the config requires any additional preparation, e.g.
13003 * to adjust global state with pipes off. We need to do this
13004 * here so we can get the modeset_pipe updated config for the new
13005 * mode set on this crtc. For other crtcs we need to use the
13006 * adjusted_mode bits in the crtc directly.
13007 */
27c329ed
ML		 13008 if (dev_priv->display.modeset_calc_cdclk) {
13009 unsigned int cdclk;
b432e5cf 13010
27c329ed
ML		 13011 ret = dev_priv->display.modeset_calc_cdclk(state);
13012
13013 cdclk = to_intel_atomic_state(state)->cdclk;
13014 if (!ret && cdclk != dev_priv->cdclk_freq)
13015 ret = intel_modeset_all_pipes(state);
13016
13017 if (ret < 0)
054518dd 13018 return ret;
27c329ed
ML		 13019 } else
13020 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13021
ad421372 13022 intel_modeset_clear_plls(state);
054518dd 13023
99d736a2 13024 if (IS_HASWELL(dev))
ad421372 13025 return haswell_mode_set_planes_workaround(state);
99d736a2 13026
ad421372 13027 return 0;
c347a676
ACO		 13028}
13029
aa363136
MR		 13030/*
13031 * Handle calculation of various watermark data at the end of the atomic check
13032 * phase. The code here should be run after the per-crtc and per-plane 'check'
13033 * handlers to ensure that all derived state has been updated.
13034 */
13035static void calc_watermark_data(struct drm_atomic_state *state)
13036{
13037 struct drm_device *dev = state->dev;
13038 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13039 struct drm_crtc *crtc;
13040 struct drm_crtc_state *cstate;
13041 struct drm_plane *plane;
13042 struct drm_plane_state *pstate;
13043
13044 /*
13045 * Calculate watermark configuration details now that derived
13046 * plane/crtc state is all properly updated.
13047 */
13048 drm_for_each_crtc(crtc, dev) {
13049 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13050 crtc->state;
13051
13052 if (cstate->active)
13053 intel_state->wm_config.num_pipes_active++;
13054 }
13055 drm_for_each_legacy_plane(plane, dev) {
13056 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13057 plane->state;
13058
13059 if (!to_intel_plane_state(pstate)->visible)
13060 continue;
13061
13062 intel_state->wm_config.sprites_enabled = true;
13063 if (pstate->crtc_w != pstate->src_w >> 16 ||
13064 pstate->crtc_h != pstate->src_h >> 16)
13065 intel_state->wm_config.sprites_scaled = true;
13066 }
13067}
13068
74c090b1
ML		 13069/**
13070 * intel_atomic_check - validate state object
13071 * @dev: drm device
13072 * @state: state to validate
13073 */
13074static int intel_atomic_check(struct drm_device *dev,
13075 struct drm_atomic_state *state)
c347a676 13076{
aa363136 13077 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
c347a676
ACO		 13078 struct drm_crtc *crtc;
13079 struct drm_crtc_state *crtc_state;
13080 int ret, i;
61333b60 13081 bool any_ms = false;
c347a676 13082
74c090b1 13083 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 13084 if (ret)
13085 return ret;
13086
c347a676 13087 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 13088 struct intel_crtc_state *pipe_config =
13089 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 13090
13091 /* Catch I915_MODE_FLAG_INHERITED */
13092 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13093 crtc_state->mode_changed = true;
cfb23ed6 13094
61333b60
ML		 13095 if (!crtc_state->enable) {
13096 if (needs_modeset(crtc_state))
13097 any_ms = true;
c347a676 13098 continue;
61333b60 13099 }
c347a676 13100
26495481 13101 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 13102 continue;
13103
26495481
DV		 13104 /* FIXME: For only active_changed we shouldn't need to do any
13105 * state recomputation at all. */
13106
1ed51de9
DV		 13107 ret = drm_atomic_add_affected_connectors(state, crtc);
13108 if (ret)
13109 return ret;
b359283a 13110
cfb23ed6 13111 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13112 if (ret)
13113 return ret;
13114
6764e9f8 13115 if (intel_pipe_config_compare(state->dev,
cfb23ed6 13116 to_intel_crtc_state(crtc->state),
1ed51de9 13117 pipe_config, true)) {
26495481 13118 crtc_state->mode_changed = false;
bfd16b2a 13119 to_intel_crtc_state(crtc_state)->update_pipe = true;
26495481
DV		 13120 }
13121
13122 if (needs_modeset(crtc_state)) {
13123 any_ms = true;
cfb23ed6
ML		 13124
13125 ret = drm_atomic_add_affected_planes(state, crtc);
13126 if (ret)
13127 return ret;
13128 }
61333b60 13129
26495481
DV		 13130 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13131 needs_modeset(crtc_state) ?
13132 "[modeset]" : "[fastset]");
c347a676
ACO		 13133 }
13134
61333b60
ML		 13135 if (any_ms) {
13136 ret = intel_modeset_checks(state);
13137
13138 if (ret)
13139 return ret;
27c329ed 13140 } else
aa363136 13141 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
76305b1a 13142
aa363136
MR		 13143 ret = drm_atomic_helper_check_planes(state->dev, state);
13144 if (ret)
13145 return ret;
13146
13147 calc_watermark_data(state);
13148
13149 return 0;
054518dd
ACO		 13150}
13151
5008e874
ML		 13152static int intel_atomic_prepare_commit(struct drm_device *dev,
13153 struct drm_atomic_state *state,
13154 bool async)
13155{
7580d774
ML		 13156 struct drm_i915_private *dev_priv = dev->dev_private;
13157 struct drm_plane_state *plane_state;
5008e874 13158 struct drm_crtc_state *crtc_state;
7580d774 13159 struct drm_plane *plane;
5008e874
ML		 13160 struct drm_crtc *crtc;
13161 int i, ret;
13162
13163 if (async) {
13164 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13165 return -EINVAL;
13166 }
13167
13168 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13169 ret = intel_crtc_wait_for_pending_flips(crtc);
13170 if (ret)
13171 return ret;
7580d774
ML		 13172
13173 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13174 flush_workqueue(dev_priv->wq);
5008e874
ML		 13175 }
13176
f935675f
ML		 13177 ret = mutex_lock_interruptible(&dev->struct_mutex);
13178 if (ret)
13179 return ret;
13180
5008e874 13181 ret = drm_atomic_helper_prepare_planes(dev, state);
7580d774
ML		 13182 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13183 u32 reset_counter;
13184
13185 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13186 mutex_unlock(&dev->struct_mutex);
13187
13188 for_each_plane_in_state(state, plane, plane_state, i) {
13189 struct intel_plane_state *intel_plane_state =
13190 to_intel_plane_state(plane_state);
13191
13192 if (!intel_plane_state->wait_req)
13193 continue;
13194
13195 ret = __i915_wait_request(intel_plane_state->wait_req,
13196 reset_counter, true,
13197 NULL, NULL);
13198
13199 /* Swallow -EIO errors to allow updates during hw lockup. */
13200 if (ret == -EIO)
13201 ret = 0;
13202
13203 if (ret)
13204 break;
13205 }
13206
13207 if (!ret)
13208 return 0;
13209
13210 mutex_lock(&dev->struct_mutex);
13211 drm_atomic_helper_cleanup_planes(dev, state);
13212 }
5008e874 13213
f935675f 13214 mutex_unlock(&dev->struct_mutex);
5008e874
ML		 13215 return ret;
13216}
13217
74c090b1
ML		 13218/**
13219 * intel_atomic_commit - commit validated state object
13220 * @dev: DRM device
13221 * @state: the top-level driver state object
13222 * @async: asynchronous commit
13223 *
13224 * This function commits a top-level state object that has been validated
13225 * with drm_atomic_helper_check().
13226 *
13227 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13228 * we can only handle plane-related operations and do not yet support
13229 * asynchronous commit.
13230 *
13231 * RETURNS
13232 * Zero for success or -errno.
13233 */
13234static int intel_atomic_commit(struct drm_device *dev,
13235 struct drm_atomic_state *state,
13236 bool async)
a6778b3c 13237{
fbee40df 13238 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303 13239 struct drm_crtc_state *crtc_state;
7580d774 13240 struct drm_crtc *crtc;
c0c36b94 13241 int ret = 0;
0a9ab303 13242 int i;
61333b60 13243 bool any_ms = false;
a6778b3c 13244
5008e874 13245 ret = intel_atomic_prepare_commit(dev, state, async);
7580d774
ML		 13246 if (ret) {
13247 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
d4afb8cc 13248 return ret;
7580d774 13249 }
d4afb8cc 13250
1c5e19f8 13251 drm_atomic_helper_swap_state(dev, state);
aa363136 13252 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
1c5e19f8 13253
0a9ab303 13254 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13256
61333b60
ML		 13257 if (!needs_modeset(crtc->state))
13258 continue;
13259
13260 any_ms = true;
a539205a 13261 intel_pre_plane_update(intel_crtc);
460da916 13262
a539205a
ML		 13263 if (crtc_state->active) {
13264 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13265 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13266 intel_crtc->active = false;
13267 intel_disable_shared_dpll(intel_crtc);
a539205a 13268 }
b8cecdf5 13269 }
7758a113 13270
ea9d758d
DV		 13271 /* Only after disabling all output pipelines that will be changed can we
13272 * update the the output configuration. */
4740b0f2 13273 intel_modeset_update_crtc_state(state);
f6e5b160 13274
4740b0f2
ML		 13275 if (any_ms) {
13276 intel_shared_dpll_commit(state);
13277
13278 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13279 modeset_update_crtc_power_domains(state);
4740b0f2 13280 }
47fab737 13281
a6778b3c 13282 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13283 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13285 bool modeset = needs_modeset(crtc->state);
bfd16b2a
ML		 13286 bool update_pipe = !modeset &&
13287 to_intel_crtc_state(crtc->state)->update_pipe;
13288 unsigned long put_domains = 0;
f6ac4b2a
ML		 13289
13290 if (modeset && crtc->state->active) {
a539205a
ML		 13291 update_scanline_offset(to_intel_crtc(crtc));
13292 dev_priv->display.crtc_enable(crtc);
13293 }
80715b2f 13294
bfd16b2a
ML		 13295 if (update_pipe) {
13296 put_domains = modeset_get_crtc_power_domains(crtc);
13297
13298 /* make sure intel_modeset_check_state runs */
13299 any_ms = true;
13300 }
13301
f6ac4b2a
ML		 13302 if (!modeset)
13303 intel_pre_plane_update(intel_crtc);
13304
6173ee28
ML		 13305 if (crtc->state->active &&
13306 (crtc->state->planes_changed || update_pipe))
62852622 13307 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
bfd16b2a
ML		 13308
13309 if (put_domains)
13310 modeset_put_power_domains(dev_priv, put_domains);
13311
f6ac4b2a 13312 intel_post_plane_update(intel_crtc);
80715b2f 13313 }
a6778b3c 13314
a6778b3c 13315 /* FIXME: add subpixel order */
83a57153 13316
74c090b1 13317 drm_atomic_helper_wait_for_vblanks(dev, state);
f935675f
ML		 13318
13319 mutex_lock(&dev->struct_mutex);
d4afb8cc 13320 drm_atomic_helper_cleanup_planes(dev, state);
f935675f 13321 mutex_unlock(&dev->struct_mutex);
2bfb4627 13322
74c090b1 13323 if (any_ms)
ee165b1a
ML		 13324 intel_modeset_check_state(dev, state);
13325
13326 drm_atomic_state_free(state);
f30da187 13327
74c090b1 13328 return 0;
7f27126e
JB		 13329}
13330
c0c36b94
CW		 13331void intel_crtc_restore_mode(struct drm_crtc *crtc)
13332{
83a57153
ACO		 13333 struct drm_device *dev = crtc->dev;
13334 struct drm_atomic_state *state;
e694eb02 13335 struct drm_crtc_state *crtc_state;
2bfb4627 13336 int ret;
83a57153
ACO		 13337
13338 state = drm_atomic_state_alloc(dev);
13339 if (!state) {
e694eb02 13340 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13341 crtc->base.id);
13342 return;
13343 }
13344
e694eb02 13345 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13346
e694eb02
ML		 13347retry:
13348 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13349 ret = PTR_ERR_OR_ZERO(crtc_state);
13350 if (!ret) {
13351 if (!crtc_state->active)
13352 goto out;
83a57153 13353
e694eb02 13354 crtc_state->mode_changed = true;
74c090b1 13355 ret = drm_atomic_commit(state);
83a57153
ACO		 13356 }
13357
e694eb02
ML		 13358 if (ret == -EDEADLK) {
13359 drm_atomic_state_clear(state);
13360 drm_modeset_backoff(state->acquire_ctx);
13361 goto retry;
4ed9fb37 13362 }
4be07317 13363
2bfb4627 13364 if (ret)
e694eb02 13365out:
2bfb4627 13366 drm_atomic_state_free(state);
c0c36b94
CW		 13367}
13368
25c5b266
DV		 13369#undef for_each_intel_crtc_masked
13370
f6e5b160 13371static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13372 .gamma_set = intel_crtc_gamma_set,
74c090b1 13373 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13374 .destroy = intel_crtc_destroy,
13375 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13376 .atomic_duplicate_state = intel_crtc_duplicate_state,
13377 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13378};
13379
5358901f
DV		 13380static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13381 struct intel_shared_dpll *pll,
13382 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13383{
5358901f 13384 uint32_t val;
ee7b9f93 13385
f458ebbc 13386 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13387 return false;
13388
5358901f 13389 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13390 hw_state->dpll = val;
13391 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13392 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13393
13394 return val & DPLL_VCO_ENABLE;
13395}
13396
15bdd4cf
DV		 13397static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13398 struct intel_shared_dpll *pll)
13399{
3e369b76
ACO		 13400 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13401 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13402}
13403
e7b903d2
DV		 13404static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13405 struct intel_shared_dpll *pll)
13406{
e7b903d2 13407 /* PCH refclock must be enabled first */
89eff4be 13408 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13409
3e369b76 13410 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13411
13412 /* Wait for the clocks to stabilize. */
13413 POSTING_READ(PCH_DPLL(pll->id));
13414 udelay(150);
13415
13416 /* The pixel multiplier can only be updated once the
13417 * DPLL is enabled and the clocks are stable.
13418 *
13419 * So write it again.
13420 */
3e369b76 13421 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13422 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13423 udelay(200);
13424}
13425
13426static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13427 struct intel_shared_dpll *pll)
13428{
13429 struct drm_device *dev = dev_priv->dev;
13430 struct intel_crtc *crtc;
e7b903d2
DV		 13431
13432 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13433 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13434 if (intel_crtc_to_shared_dpll(crtc) == pll)
13435 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13436 }
13437
15bdd4cf
DV		 13438 I915_WRITE(PCH_DPLL(pll->id), 0);
13439 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13440 udelay(200);
13441}
13442
46edb027
DV		 13443static char *ibx_pch_dpll_names[] = {
13444 "PCH DPLL A",
13445 "PCH DPLL B",
13446};
13447
7c74ade1 13448static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13449{
e7b903d2 13450 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13451 int i;
13452
7c74ade1 13453 dev_priv->num_shared_dpll = 2;
ee7b9f93 13454
e72f9fbf 13455 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13456 dev_priv->shared_dplls[i].id = i;
13457 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13458 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13459 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13460 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13461 dev_priv->shared_dplls[i].get_hw_state =
13462 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13463 }
13464}
13465
7c74ade1
DV		 13466static void intel_shared_dpll_init(struct drm_device *dev)
13467{
e7b903d2 13468 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13469
9cd86933
DV		 13470 if (HAS_DDI(dev))
13471 intel_ddi_pll_init(dev);
13472 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13473 ibx_pch_dpll_init(dev);
13474 else
13475 dev_priv->num_shared_dpll = 0;
13476
13477 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13478}
13479
6beb8c23
MR		 13480/**
13481 * intel_prepare_plane_fb - Prepare fb for usage on plane
13482 * @plane: drm plane to prepare for
13483 * @fb: framebuffer to prepare for presentation
13484 *
13485 * Prepares a framebuffer for usage on a display plane. Generally this
13486 * involves pinning the underlying object and updating the frontbuffer tracking
13487 * bits. Some older platforms need special physical address handling for
13488 * cursor planes.
13489 *
f935675f
ML		 13490 * Must be called with struct_mutex held.
13491 *
6beb8c23
MR		 13492 * Returns 0 on success, negative error code on failure.
13493 */
13494int
13495intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee 13496 const struct drm_plane_state *new_state)
465c120c
MR		 13497{
13498 struct drm_device *dev = plane->dev;
844f9111 13499 struct drm_framebuffer *fb = new_state->fb;
6beb8c23 13500 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23 13501 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1ee49399 13502 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
6beb8c23 13503 int ret = 0;
465c120c 13504
1ee49399 13505 if (!obj && !old_obj)
465c120c
MR		 13506 return 0;
13507
5008e874
ML		 13508 if (old_obj) {
13509 struct drm_crtc_state *crtc_state =
13510 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13511
13512 /* Big Hammer, we also need to ensure that any pending
13513 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13514 * current scanout is retired before unpinning the old
13515 * framebuffer. Note that we rely on userspace rendering
13516 * into the buffer attached to the pipe they are waiting
13517 * on. If not, userspace generates a GPU hang with IPEHR
13518 * point to the MI_WAIT_FOR_EVENT.
13519 *
13520 * This should only fail upon a hung GPU, in which case we
13521 * can safely continue.
13522 */
13523 if (needs_modeset(crtc_state))
13524 ret = i915_gem_object_wait_rendering(old_obj, true);
13525
13526 /* Swallow -EIO errors to allow updates during hw lockup. */
13527 if (ret && ret != -EIO)
f935675f 13528 return ret;
5008e874
ML		 13529 }
13530
1ee49399
ML		 13531 if (!obj) {
13532 ret = 0;
13533 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
6beb8c23
MR		 13534 INTEL_INFO(dev)->cursor_needs_physical) {
13535 int align = IS_I830(dev) ? 16 * 1024 : 256;
13536 ret = i915_gem_object_attach_phys(obj, align);
13537 if (ret)
13538 DRM_DEBUG_KMS("failed to attach phys object\n");
13539 } else {
7580d774 13540 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
6beb8c23 13541 }
465c120c 13542
7580d774
ML		 13543 if (ret == 0) {
13544 if (obj) {
13545 struct intel_plane_state *plane_state =
13546 to_intel_plane_state(new_state);
13547
13548 i915_gem_request_assign(&plane_state->wait_req,
13549 obj->last_write_req);
13550 }
13551
a9ff8714 13552 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
7580d774 13553 }
fdd508a6 13554
6beb8c23
MR		 13555 return ret;
13556}
13557
38f3ce3a
MR		 13558/**
13559 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13560 * @plane: drm plane to clean up for
13561 * @fb: old framebuffer that was on plane
13562 *
13563 * Cleans up a framebuffer that has just been removed from a plane.
f935675f
ML		 13564 *
13565 * Must be called with struct_mutex held.
38f3ce3a
MR		 13566 */
13567void
13568intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee 13569 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13570{
13571 struct drm_device *dev = plane->dev;
1ee49399 13572 struct intel_plane *intel_plane = to_intel_plane(plane);
7580d774 13573 struct intel_plane_state *old_intel_state;
1ee49399
ML		 13574 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13575 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
38f3ce3a 13576
7580d774
ML		 13577 old_intel_state = to_intel_plane_state(old_state);
13578
1ee49399 13579 if (!obj && !old_obj)
38f3ce3a
MR		 13580 return;
13581
1ee49399
ML		 13582 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13583 !INTEL_INFO(dev)->cursor_needs_physical))
844f9111 13584 intel_unpin_fb_obj(old_state->fb, old_state);
1ee49399
ML		 13585
13586 /* prepare_fb aborted? */
13587 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13588 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13589 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
7580d774
ML		 13590
13591 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13592
465c120c
MR		 13593}
13594
6156a456
CK		 13595int
13596skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13597{
13598 int max_scale;
13599 struct drm_device *dev;
13600 struct drm_i915_private *dev_priv;
13601 int crtc_clock, cdclk;
13602
13603 if (!intel_crtc || !crtc_state)
13604 return DRM_PLANE_HELPER_NO_SCALING;
13605
13606 dev = intel_crtc->base.dev;
13607 dev_priv = dev->dev_private;
13608 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13609 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456 13610
54bf1ce6 13611 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
6156a456
CK		 13612 return DRM_PLANE_HELPER_NO_SCALING;
13613
13614 /*
13615 * skl max scale is lower of:
13616 * close to 3 but not 3, -1 is for that purpose
13617 * or
13618 * cdclk/crtc_clock
13619 */
13620 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13621
13622 return max_scale;
13623}
13624
465c120c 13625static int
3c692a41 13626intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13627 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13628 struct intel_plane_state *state)
13629{
2b875c22
MR		 13630 struct drm_crtc *crtc = state->base.crtc;
13631 struct drm_framebuffer *fb = state->base.fb;
6156a456 13632 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13633 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13634 bool can_position = false;
465c120c 13635
061e4b8d
ML		 13636 /* use scaler when colorkey is not required */
13637 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13638 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13639 min_scale = 1;
13640 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13641 can_position = true;
6156a456 13642 }
d8106366 13643
061e4b8d
ML		 13644 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13645 &state->dst, &state->clip,
da20eabd
ML		 13646 min_scale, max_scale,
13647 can_position, true,
13648 &state->visible);
14af293f
GP		 13649}
13650
13651static void
13652intel_commit_primary_plane(struct drm_plane *plane,
13653 struct intel_plane_state *state)
13654{
2b875c22
MR		 13655 struct drm_crtc *crtc = state->base.crtc;
13656 struct drm_framebuffer *fb = state->base.fb;
13657 struct drm_device *dev = plane->dev;
14af293f 13658 struct drm_i915_private *dev_priv = dev->dev_private;
14af293f 13659
ea2c67bb 13660 crtc = crtc ? crtc : plane->crtc;
ccc759dc 13661
d4b08630
ML		 13662 dev_priv->display.update_primary_plane(crtc, fb,
13663 state->src.x1 >> 16,
13664 state->src.y1 >> 16);
465c120c
MR		 13665}
13666
a8ad0d8e
ML		 13667static void
13668intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13669 struct drm_crtc *crtc)
a8ad0d8e
ML		 13670{
13671 struct drm_device *dev = plane->dev;
13672 struct drm_i915_private *dev_priv = dev->dev_private;
13673
a8ad0d8e
ML		 13674 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13675}
13676
613d2b27
ML		 13677static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13678 struct drm_crtc_state *old_crtc_state)
3c692a41 13679{
32b7eeec 13680 struct drm_device *dev = crtc->dev;
3c692a41 13681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
bfd16b2a
ML		 13682 struct intel_crtc_state *old_intel_state =
13683 to_intel_crtc_state(old_crtc_state);
13684 bool modeset = needs_modeset(crtc->state);
3c692a41 13685
f015c551 13686 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13687 intel_update_watermarks(crtc);
3c692a41 13688
c34c9ee4 13689 /* Perform vblank evasion around commit operation */
62852622 13690 intel_pipe_update_start(intel_crtc);
0583236e 13691
bfd16b2a
ML		 13692 if (modeset)
13693 return;
13694
13695 if (to_intel_crtc_state(crtc->state)->update_pipe)
13696 intel_update_pipe_config(intel_crtc, old_intel_state);
13697 else if (INTEL_INFO(dev)->gen >= 9)
0583236e 13698 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13699}
13700
613d2b27
ML		 13701static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13702 struct drm_crtc_state *old_crtc_state)
32b7eeec 13703{
32b7eeec 13704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13705
62852622 13706 intel_pipe_update_end(intel_crtc);
3c692a41
GP		 13707}
13708
cf4c7c12 13709/**
4a3b8769
MR		 13710 * intel_plane_destroy - destroy a plane
13711 * @plane: plane to destroy
cf4c7c12 13712 *
4a3b8769
MR		 13713 * Common destruction function for all types of planes (primary, cursor,
13714 * sprite).
cf4c7c12 13715 */
4a3b8769 13716void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13717{
13718 struct intel_plane *intel_plane = to_intel_plane(plane);
13719 drm_plane_cleanup(plane);
13720 kfree(intel_plane);
13721}
13722
65a3fea0 13723const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13724 .update_plane = drm_atomic_helper_update_plane,
13725 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13726 .destroy = intel_plane_destroy,
c196e1d6 13727 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13728 .atomic_get_property = intel_plane_atomic_get_property,
13729 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13730 .atomic_duplicate_state = intel_plane_duplicate_state,
13731 .atomic_destroy_state = intel_plane_destroy_state,
13732
465c120c
MR		 13733};
13734
13735static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13736 int pipe)
13737{
13738 struct intel_plane *primary;
8e7d688b 13739 struct intel_plane_state *state;
465c120c 13740 const uint32_t *intel_primary_formats;
45e3743a 13741 unsigned int num_formats;
465c120c
MR		 13742
13743 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13744 if (primary == NULL)
13745 return NULL;
13746
8e7d688b
MR		 13747 state = intel_create_plane_state(&primary->base);
13748 if (!state) {
ea2c67bb
MR		 13749 kfree(primary);
13750 return NULL;
13751 }
8e7d688b 13752 primary->base.state = &state->base;
ea2c67bb 13753
465c120c
MR		 13754 primary->can_scale = false;
13755 primary->max_downscale = 1;
6156a456
CK		 13756 if (INTEL_INFO(dev)->gen >= 9) {
13757 primary->can_scale = true;
af99ceda 13758 state->scaler_id = -1;
6156a456 13759 }
465c120c
MR		 13760 primary->pipe = pipe;
13761 primary->plane = pipe;
a9ff8714 13762 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13763 primary->check_plane = intel_check_primary_plane;
13764 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13765 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13766 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13767 primary->plane = !pipe;
13768
6c0fd451
DL		 13769 if (INTEL_INFO(dev)->gen >= 9) {
13770 intel_primary_formats = skl_primary_formats;
13771 num_formats = ARRAY_SIZE(skl_primary_formats);
13772 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13773 intel_primary_formats = i965_primary_formats;
13774 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13775 } else {
13776 intel_primary_formats = i8xx_primary_formats;
13777 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13778 }
13779
13780 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13781 &intel_plane_funcs,
465c120c
MR		 13782 intel_primary_formats, num_formats,
13783 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13784
3b7a5119
SJ		 13785 if (INTEL_INFO(dev)->gen >= 4)
13786 intel_create_rotation_property(dev, primary);
48404c1e 13787
ea2c67bb
MR		 13788 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13789
465c120c
MR		 13790 return &primary->base;
13791}
13792
3b7a5119
SJ		 13793void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13794{
13795 if (!dev->mode_config.rotation_property) {
13796 unsigned long flags = BIT(DRM_ROTATE_0) |
13797 BIT(DRM_ROTATE_180);
13798
13799 if (INTEL_INFO(dev)->gen >= 9)
13800 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13801
13802 dev->mode_config.rotation_property =
13803 drm_mode_create_rotation_property(dev, flags);
13804 }
13805 if (dev->mode_config.rotation_property)
13806 drm_object_attach_property(&plane->base.base,
13807 dev->mode_config.rotation_property,
13808 plane->base.state->rotation);
13809}
13810
3d7d6510 13811static int
852e787c 13812intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13813 struct intel_crtc_state *crtc_state,
852e787c 13814 struct intel_plane_state *state)
3d7d6510 13815{
061e4b8d 13816 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13817 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13818 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13819 unsigned stride;
13820 int ret;
3d7d6510 13821
061e4b8d
ML		 13822 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13823 &state->dst, &state->clip,
3d7d6510
MR		 13824 DRM_PLANE_HELPER_NO_SCALING,
13825 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13826 true, true, &state->visible);
757f9a3e
GP		 13827 if (ret)
13828 return ret;
13829
757f9a3e
GP		 13830 /* if we want to turn off the cursor ignore width and height */
13831 if (!obj)
da20eabd 13832 return 0;
757f9a3e 13833
757f9a3e 13834 /* Check for which cursor types we support */
061e4b8d 13835 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13836 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13837 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13838 return -EINVAL;
13839 }
13840
ea2c67bb
MR		 13841 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13842 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13843 DRM_DEBUG_KMS("buffer is too small\n");
13844 return -ENOMEM;
13845 }
13846
3a656b54 13847 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13848 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13849 return -EINVAL;
32b7eeec
MR		 13850 }
13851
da20eabd 13852 return 0;
852e787c 13853}
3d7d6510 13854
a8ad0d8e
ML		 13855static void
13856intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13857 struct drm_crtc *crtc)
a8ad0d8e 13858{
a8ad0d8e
ML		 13859 intel_crtc_update_cursor(crtc, false);
13860}
13861
f4a2cf29 13862static void
852e787c
GP		 13863intel_commit_cursor_plane(struct drm_plane *plane,
13864 struct intel_plane_state *state)
13865{
2b875c22 13866 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13867 struct drm_device *dev = plane->dev;
13868 struct intel_crtc *intel_crtc;
2b875c22 13869 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13870 uint32_t addr;
852e787c 13871
ea2c67bb
MR		 13872 crtc = crtc ? crtc : plane->crtc;
13873 intel_crtc = to_intel_crtc(crtc);
13874
a912f12f
GP		 13875 if (intel_crtc->cursor_bo == obj)
13876 goto update;
4ed91096 13877
f4a2cf29 13878 if (!obj)
a912f12f 13879 addr = 0;
f4a2cf29 13880 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13881 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13882 else
a912f12f 13883 addr = obj->phys_handle->busaddr;
852e787c 13884
a912f12f
GP		 13885 intel_crtc->cursor_addr = addr;
13886 intel_crtc->cursor_bo = obj;
852e787c 13887
302d19ac 13888update:
62852622 13889 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13890}
13891
3d7d6510
MR		 13892static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13893 int pipe)
13894{
13895 struct intel_plane *cursor;
8e7d688b 13896 struct intel_plane_state *state;
3d7d6510
MR		 13897
13898 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13899 if (cursor == NULL)
13900 return NULL;
13901
8e7d688b
MR		 13902 state = intel_create_plane_state(&cursor->base);
13903 if (!state) {
ea2c67bb
MR		 13904 kfree(cursor);
13905 return NULL;
13906 }
8e7d688b 13907 cursor->base.state = &state->base;
ea2c67bb 13908
3d7d6510
MR		 13909 cursor->can_scale = false;
13910 cursor->max_downscale = 1;
13911 cursor->pipe = pipe;
13912 cursor->plane = pipe;
a9ff8714 13913 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13914 cursor->check_plane = intel_check_cursor_plane;
13915 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13916 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13917
13918 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13919 &intel_plane_funcs,
3d7d6510
MR		 13920 intel_cursor_formats,
13921 ARRAY_SIZE(intel_cursor_formats),
13922 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13923
13924 if (INTEL_INFO(dev)->gen >= 4) {
13925 if (!dev->mode_config.rotation_property)
13926 dev->mode_config.rotation_property =
13927 drm_mode_create_rotation_property(dev,
13928 BIT(DRM_ROTATE_0) |
13929 BIT(DRM_ROTATE_180));
13930 if (dev->mode_config.rotation_property)
13931 drm_object_attach_property(&cursor->base.base,
13932 dev->mode_config.rotation_property,
8e7d688b 13933 state->base.rotation);
4398ad45
VS		 13934 }
13935
af99ceda
CK		 13936 if (INTEL_INFO(dev)->gen >=9)
13937 state->scaler_id = -1;
13938
ea2c67bb
MR		 13939 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13940
3d7d6510
MR		 13941 return &cursor->base;
13942}
13943
549e2bfb
CK		 13944static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13945 struct intel_crtc_state *crtc_state)
13946{
13947 int i;
13948 struct intel_scaler *intel_scaler;
13949 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13950
13951 for (i = 0; i < intel_crtc->num_scalers; i++) {
13952 intel_scaler = &scaler_state->scalers[i];
13953 intel_scaler->in_use = 0;
549e2bfb
CK		 13954 intel_scaler->mode = PS_SCALER_MODE_DYN;
13955 }
13956
13957 scaler_state->scaler_id = -1;
13958}
13959
b358d0a6 13960static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13961{
fbee40df 13962 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13963 struct intel_crtc *intel_crtc;
f5de6e07 13964 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13965 struct drm_plane *primary = NULL;
13966 struct drm_plane *cursor = NULL;
465c120c 13967 int i, ret;
79e53945 13968
955382f3 13969 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13970 if (intel_crtc == NULL)
13971 return;
13972
f5de6e07
ACO		 13973 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13974 if (!crtc_state)
13975 goto fail;
550acefd
ACO		 13976 intel_crtc->config = crtc_state;
13977 intel_crtc->base.state = &crtc_state->base;
07878248 13978 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13979
549e2bfb
CK		 13980 /* initialize shared scalers */
13981 if (INTEL_INFO(dev)->gen >= 9) {
13982 if (pipe == PIPE_C)
13983 intel_crtc->num_scalers = 1;
13984 else
13985 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13986
13987 skl_init_scalers(dev, intel_crtc, crtc_state);
13988 }
13989
465c120c 13990 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13991 if (!primary)
13992 goto fail;
13993
13994 cursor = intel_cursor_plane_create(dev, pipe);
13995 if (!cursor)
13996 goto fail;
13997
465c120c 13998 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13999 cursor, &intel_crtc_funcs);
14000 if (ret)
14001 goto fail;
79e53945
JB		 14002
14003 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14004 for (i = 0; i < 256; i++) {
14005 intel_crtc->lut_r[i] = i;
14006 intel_crtc->lut_g[i] = i;
14007 intel_crtc->lut_b[i] = i;
14008 }
14009
1f1c2e24
VS		 14010 /*
14011 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14012 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14013 */
80824003
JB		 14014 intel_crtc->pipe = pipe;
14015 intel_crtc->plane = pipe;
3a77c4c4 14016 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14017 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14018 intel_crtc->plane = !pipe;
80824003
JB		 14019 }
14020
4b0e333e
CW		 14021 intel_crtc->cursor_base = ~0;
14022 intel_crtc->cursor_cntl = ~0;
dc41c154 14023 intel_crtc->cursor_size = ~0;
8d7849db 14024
852eb00d
VS		 14025 intel_crtc->wm.cxsr_allowed = true;
14026
22fd0fab
JB		 14027 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14028 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14029 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14030 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14031
79e53945 14032 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14033
14034 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14035 return;
14036
14037fail:
14038 if (primary)
14039 drm_plane_cleanup(primary);
14040 if (cursor)
14041 drm_plane_cleanup(cursor);
f5de6e07 14042 kfree(crtc_state);
3d7d6510 14043 kfree(intel_crtc);
79e53945
JB		 14044}
14045
752aa88a
JB		 14046enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14047{
14048 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14049 struct drm_device *dev = connector->base.dev;
752aa88a 14050
51fd371b 14051 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14052
d3babd3f 14053 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14054 return INVALID_PIPE;
14055
14056 return to_intel_crtc(encoder->crtc)->pipe;
14057}
14058
08d7b3d1 14059int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14060 struct drm_file *file)
08d7b3d1 14061{
08d7b3d1 14062 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14063 struct drm_crtc *drmmode_crtc;
c05422d5 14064 struct intel_crtc *crtc;
08d7b3d1 14065
7707e653 14066 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14067
7707e653 14068 if (!drmmode_crtc) {
08d7b3d1 14069 DRM_ERROR("no such CRTC id\n");
3f2c2057 14070 return -ENOENT;
08d7b3d1
CW		 14071 }
14072
7707e653 14073 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14074 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14075
c05422d5 14076 return 0;
08d7b3d1
CW		 14077}
14078
66a9278e 14079static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14080{
66a9278e
DV		 14081 struct drm_device *dev = encoder->base.dev;
14082 struct intel_encoder *source_encoder;
79e53945 14083 int index_mask = 0;
79e53945
JB		 14084 int entry = 0;
14085
b2784e15 14086 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14087 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14088 index_mask |= (1 << entry);
14089
79e53945
JB		 14090 entry++;
14091 }
4ef69c7a 14092
79e53945
JB		 14093 return index_mask;
14094}
14095
4d302442
CW		 14096static bool has_edp_a(struct drm_device *dev)
14097{
14098 struct drm_i915_private *dev_priv = dev->dev_private;
14099
14100 if (!IS_MOBILE(dev))
14101 return false;
14102
14103 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14104 return false;
14105
e3589908 14106 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14107 return false;
14108
14109 return true;
14110}
14111
84b4e042
JB		 14112static bool intel_crt_present(struct drm_device *dev)
14113{
14114 struct drm_i915_private *dev_priv = dev->dev_private;
14115
884497ed
DL		 14116 if (INTEL_INFO(dev)->gen >= 9)
14117 return false;
14118
cf404ce4 14119 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14120 return false;
14121
14122 if (IS_CHERRYVIEW(dev))
14123 return false;
14124
14125 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14126 return false;
14127
14128 return true;
14129}
14130
79e53945
JB		 14131static void intel_setup_outputs(struct drm_device *dev)
14132{
725e30ad 14133 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14134 struct intel_encoder *encoder;
cb0953d7 14135 bool dpd_is_edp = false;
79e53945 14136
c9093354 14137 intel_lvds_init(dev);
79e53945 14138
84b4e042 14139 if (intel_crt_present(dev))
79935fca 14140 intel_crt_init(dev);
cb0953d7 14141
c776eb2e
VK		 14142 if (IS_BROXTON(dev)) {
14143 /*
14144 * FIXME: Broxton doesn't support port detection via the
14145 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14146 * detect the ports.
14147 */
14148 intel_ddi_init(dev, PORT_A);
14149 intel_ddi_init(dev, PORT_B);
14150 intel_ddi_init(dev, PORT_C);
14151 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14152 int found;
14153
de31facd
JB		 14154 /*
14155 * Haswell uses DDI functions to detect digital outputs.
14156 * On SKL pre-D0 the strap isn't connected, so we assume
14157 * it's there.
14158 */
77179400 14159 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
de31facd 14160 /* WaIgnoreDDIAStrap: skl */
ef11bdb3 14161 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
0e72a5b5
ED		 14162 intel_ddi_init(dev, PORT_A);
14163
14164 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14165 * register */
14166 found = I915_READ(SFUSE_STRAP);
14167
14168 if (found & SFUSE_STRAP_DDIB_DETECTED)
14169 intel_ddi_init(dev, PORT_B);
14170 if (found & SFUSE_STRAP_DDIC_DETECTED)
14171 intel_ddi_init(dev, PORT_C);
14172 if (found & SFUSE_STRAP_DDID_DETECTED)
14173 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 14174 /*
14175 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14176 */
ef11bdb3 14177 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
2800e4c2
RV		 14178 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14179 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14180 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14181 intel_ddi_init(dev, PORT_E);
14182
0e72a5b5 14183 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14184 int found;
5d8a7752 14185 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14186
14187 if (has_edp_a(dev))
14188 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14189
dc0fa718 14190 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14191 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14192 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14193 if (!found)
e2debe91 14194 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14195 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14196 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14197 }
14198
dc0fa718 14199 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14200 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14201
dc0fa718 14202 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14203 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14204
5eb08b69 14205 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14206 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14207
270b3042 14208 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14209 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14210 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14211 /*
14212 * The DP_DETECTED bit is the latched state of the DDC
14213 * SDA pin at boot. However since eDP doesn't require DDC
14214 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14215 * eDP ports may have been muxed to an alternate function.
14216 * Thus we can't rely on the DP_DETECTED bit alone to detect
14217 * eDP ports. Consult the VBT as well as DP_DETECTED to
14218 * detect eDP ports.
14219 */
e66eb81d 14220 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
d2182a66 14221 !intel_dp_is_edp(dev, PORT_B))
e66eb81d
VS		 14222 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14223 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
e17ac6db 14224 intel_dp_is_edp(dev, PORT_B))
e66eb81d 14225 intel_dp_init(dev, VLV_DP_B, PORT_B);
585a94b8 14226
e66eb81d 14227 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
d2182a66 14228 !intel_dp_is_edp(dev, PORT_C))
e66eb81d
VS		 14229 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14230 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
e17ac6db 14231 intel_dp_is_edp(dev, PORT_C))
e66eb81d 14232 intel_dp_init(dev, VLV_DP_C, PORT_C);
19c03924 14233
9418c1f1 14234 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14235 /* eDP not supported on port D, so don't check VBT */
e66eb81d
VS		 14236 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14237 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14238 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14239 intel_dp_init(dev, CHV_DP_D, PORT_D);
9418c1f1
VS		 14240 }
14241
3cfca973 14242 intel_dsi_init(dev);
09da55dc 14243 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14244 bool found = false;
7d57382e 14245
e2debe91 14246 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14247 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14248 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14249 if (!found && IS_G4X(dev)) {
b01f2c3a 14250 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14251 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14252 }
27185ae1 14253
3fec3d2f 14254 if (!found && IS_G4X(dev))
ab9d7c30 14255 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14256 }
13520b05
KH		 14257
14258 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14259
e2debe91 14260 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14261 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14262 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14263 }
27185ae1 14264
e2debe91 14265 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14266
3fec3d2f 14267 if (IS_G4X(dev)) {
b01f2c3a 14268 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14269 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14270 }
3fec3d2f 14271 if (IS_G4X(dev))
ab9d7c30 14272 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14273 }
27185ae1 14274
3fec3d2f 14275 if (IS_G4X(dev) &&
e7281eab 14276 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14277 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14278 } else if (IS_GEN2(dev))
79e53945
JB		 14279 intel_dvo_init(dev);
14280
103a196f 14281 if (SUPPORTS_TV(dev))
79e53945
JB		 14282 intel_tv_init(dev);
14283
0bc12bcb 14284 intel_psr_init(dev);
7c8f8a70 14285
b2784e15 14286 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14287 encoder->base.possible_crtcs = encoder->crtc_mask;
14288 encoder->base.possible_clones =
66a9278e 14289 intel_encoder_clones(encoder);
79e53945 14290 }
47356eb6 14291
dde86e2d 14292 intel_init_pch_refclk(dev);
270b3042
DV		 14293
14294 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14295}
14296
14297static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14298{
60a5ca01 14299 struct drm_device *dev = fb->dev;
79e53945 14300 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14301
ef2d633e 14302 drm_framebuffer_cleanup(fb);
60a5ca01 14303 mutex_lock(&dev->struct_mutex);
ef2d633e 14304 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14305 drm_gem_object_unreference(&intel_fb->obj->base);
14306 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14307 kfree(intel_fb);
14308}
14309
14310static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14311 struct drm_file *file,
79e53945
JB		 14312 unsigned int *handle)
14313{
14314 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14315 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14316
05394f39 14317 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14318}
14319
86c98588
RV		 14320static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14321 struct drm_file *file,
14322 unsigned flags, unsigned color,
14323 struct drm_clip_rect *clips,
14324 unsigned num_clips)
14325{
14326 struct drm_device *dev = fb->dev;
14327 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14328 struct drm_i915_gem_object *obj = intel_fb->obj;
14329
14330 mutex_lock(&dev->struct_mutex);
74b4ea1e 14331 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14332 mutex_unlock(&dev->struct_mutex);
14333
14334 return 0;
14335}
14336
79e53945
JB		 14337static const struct drm_framebuffer_funcs intel_fb_funcs = {
14338 .destroy = intel_user_framebuffer_destroy,
14339 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14340 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14341};
14342
b321803d
DL		 14343static
14344u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14345 uint32_t pixel_format)
14346{
14347 u32 gen = INTEL_INFO(dev)->gen;
14348
14349 if (gen >= 9) {
14350 /* "The stride in bytes must not exceed the of the size of 8K
14351 * pixels and 32K bytes."
14352 */
14353 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14354 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14355 return 32*1024;
14356 } else if (gen >= 4) {
14357 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14358 return 16*1024;
14359 else
14360 return 32*1024;
14361 } else if (gen >= 3) {
14362 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14363 return 8*1024;
14364 else
14365 return 16*1024;
14366 } else {
14367 /* XXX DSPC is limited to 4k tiled */
14368 return 8*1024;
14369 }
14370}
14371
b5ea642a
DV		 14372static int intel_framebuffer_init(struct drm_device *dev,
14373 struct intel_framebuffer *intel_fb,
14374 struct drm_mode_fb_cmd2 *mode_cmd,
14375 struct drm_i915_gem_object *obj)
79e53945 14376{
6761dd31 14377 unsigned int aligned_height;
79e53945 14378 int ret;
b321803d 14379 u32 pitch_limit, stride_alignment;
79e53945 14380
dd4916c5
DV		 14381 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14382
2a80eada
DV		 14383 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14384 /* Enforce that fb modifier and tiling mode match, but only for
14385 * X-tiled. This is needed for FBC. */
14386 if (!!(obj->tiling_mode == I915_TILING_X) !=
14387 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14388 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14389 return -EINVAL;
14390 }
14391 } else {
14392 if (obj->tiling_mode == I915_TILING_X)
14393 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14394 else if (obj->tiling_mode == I915_TILING_Y) {
14395 DRM_DEBUG("No Y tiling for legacy addfb\n");
14396 return -EINVAL;
14397 }
14398 }
14399
9a8f0a12
TU		 14400 /* Passed in modifier sanity checking. */
14401 switch (mode_cmd->modifier[0]) {
14402 case I915_FORMAT_MOD_Y_TILED:
14403 case I915_FORMAT_MOD_Yf_TILED:
14404 if (INTEL_INFO(dev)->gen < 9) {
14405 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14406 mode_cmd->modifier[0]);
14407 return -EINVAL;
14408 }
14409 case DRM_FORMAT_MOD_NONE:
14410 case I915_FORMAT_MOD_X_TILED:
14411 break;
14412 default:
c0f40428
JB		 14413 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14414 mode_cmd->modifier[0]);
57cd6508 14415 return -EINVAL;
c16ed4be 14416 }
57cd6508 14417
b321803d
DL		 14418 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14419 mode_cmd->pixel_format);
14420 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14421 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14422 mode_cmd->pitches[0], stride_alignment);
57cd6508 14423 return -EINVAL;
c16ed4be 14424 }
57cd6508 14425
b321803d
DL		 14426 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14427 mode_cmd->pixel_format);
a35cdaa0 14428 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14429 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14430 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14431 "tiled" : "linear",
a35cdaa0 14432 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14433 return -EINVAL;
c16ed4be 14434 }
5d7bd705 14435
2a80eada 14436 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14437 mode_cmd->pitches[0] != obj->stride) {
14438 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14439 mode_cmd->pitches[0], obj->stride);
5d7bd705 14440 return -EINVAL;
c16ed4be 14441 }
5d7bd705 14442
57779d06 14443 /* Reject formats not supported by any plane early. */
308e5bcb 14444 switch (mode_cmd->pixel_format) {
57779d06 14445 case DRM_FORMAT_C8:
04b3924d
VS		 14446 case DRM_FORMAT_RGB565:
14447 case DRM_FORMAT_XRGB8888:
14448 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14449 break;
14450 case DRM_FORMAT_XRGB1555:
c16ed4be 14451 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14452 DRM_DEBUG("unsupported pixel format: %s\n",
14453 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14454 return -EINVAL;
c16ed4be 14455 }
57779d06 14456 break;
57779d06 14457 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14458 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14459 DRM_DEBUG("unsupported pixel format: %s\n",
14460 drm_get_format_name(mode_cmd->pixel_format));
14461 return -EINVAL;
14462 }
14463 break;
14464 case DRM_FORMAT_XBGR8888:
04b3924d 14465 case DRM_FORMAT_XRGB2101010:
57779d06 14466 case DRM_FORMAT_XBGR2101010:
c16ed4be 14467 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14468 DRM_DEBUG("unsupported pixel format: %s\n",
14469 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14470 return -EINVAL;
c16ed4be 14471 }
b5626747 14472 break;
7531208b
DL		 14473 case DRM_FORMAT_ABGR2101010:
14474 if (!IS_VALLEYVIEW(dev)) {
14475 DRM_DEBUG("unsupported pixel format: %s\n",
14476 drm_get_format_name(mode_cmd->pixel_format));
14477 return -EINVAL;
14478 }
14479 break;
04b3924d
VS		 14480 case DRM_FORMAT_YUYV:
14481 case DRM_FORMAT_UYVY:
14482 case DRM_FORMAT_YVYU:
14483 case DRM_FORMAT_VYUY:
c16ed4be 14484 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14485 DRM_DEBUG("unsupported pixel format: %s\n",
14486 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14487 return -EINVAL;
c16ed4be 14488 }
57cd6508
CW		 14489 break;
14490 default:
4ee62c76
VS		 14491 DRM_DEBUG("unsupported pixel format: %s\n",
14492 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14493 return -EINVAL;
14494 }
14495
90f9a336
VS		 14496 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14497 if (mode_cmd->offsets[0] != 0)
14498 return -EINVAL;
14499
ec2c981e 14500 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14501 mode_cmd->pixel_format,
14502 mode_cmd->modifier[0]);
53155c0a
DV		 14503 /* FIXME drm helper for size checks (especially planar formats)? */
14504 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14505 return -EINVAL;
14506
c7d73f6a
DV		 14507 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14508 intel_fb->obj = obj;
80075d49 14509 intel_fb->obj->framebuffer_references++;
c7d73f6a 14510
79e53945
JB		 14511 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14512 if (ret) {
14513 DRM_ERROR("framebuffer init failed %d\n", ret);
14514 return ret;
14515 }
14516
79e53945
JB		 14517 return 0;
14518}
14519
79e53945
JB		 14520static struct drm_framebuffer *
14521intel_user_framebuffer_create(struct drm_device *dev,
14522 struct drm_file *filp,
308e5bcb 14523 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14524{
05394f39 14525 struct drm_i915_gem_object *obj;
79e53945 14526
308e5bcb
JB		 14527 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14528 mode_cmd->handles[0]));
c8725226 14529 if (&obj->base == NULL)
cce13ff7 14530 return ERR_PTR(-ENOENT);
79e53945 14531
d2dff872 14532 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14533}
14534
0695726e 14535#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14536static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14537{
14538}
14539#endif
14540
79e53945 14541static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14542 .fb_create = intel_user_framebuffer_create,
0632fef6 14543 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14544 .atomic_check = intel_atomic_check,
14545 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14546 .atomic_state_alloc = intel_atomic_state_alloc,
14547 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14548};
14549
e70236a8
JB		 14550/* Set up chip specific display functions */
14551static void intel_init_display(struct drm_device *dev)
14552{
14553 struct drm_i915_private *dev_priv = dev->dev_private;
14554
ee9300bb
DV		 14555 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14556 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14557 else if (IS_CHERRYVIEW(dev))
14558 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14559 else if (IS_VALLEYVIEW(dev))
14560 dev_priv->display.find_dpll = vlv_find_best_dpll;
14561 else if (IS_PINEVIEW(dev))
14562 dev_priv->display.find_dpll = pnv_find_best_dpll;
14563 else
14564 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14565
bc8d7dff
DL		 14566 if (INTEL_INFO(dev)->gen >= 9) {
14567 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14568 dev_priv->display.get_initial_plane_config =
14569 skylake_get_initial_plane_config;
bc8d7dff
DL		 14570 dev_priv->display.crtc_compute_clock =
14571 haswell_crtc_compute_clock;
14572 dev_priv->display.crtc_enable = haswell_crtc_enable;
14573 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14574 dev_priv->display.update_primary_plane =
14575 skylake_update_primary_plane;
14576 } else if (HAS_DDI(dev)) {
0e8ffe1b 14577 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14578 dev_priv->display.get_initial_plane_config =
14579 ironlake_get_initial_plane_config;
797d0259
ACO		 14580 dev_priv->display.crtc_compute_clock =
14581 haswell_crtc_compute_clock;
4f771f10
PZ		 14582 dev_priv->display.crtc_enable = haswell_crtc_enable;
14583 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14584 dev_priv->display.update_primary_plane =
14585 ironlake_update_primary_plane;
09b4ddf9 14586 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14587 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14588 dev_priv->display.get_initial_plane_config =
14589 ironlake_get_initial_plane_config;
3fb37703
ACO		 14590 dev_priv->display.crtc_compute_clock =
14591 ironlake_crtc_compute_clock;
76e5a89c
DV		 14592 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14593 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14594 dev_priv->display.update_primary_plane =
14595 ironlake_update_primary_plane;
89b667f8
JB		 14596 } else if (IS_VALLEYVIEW(dev)) {
14597 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14598 dev_priv->display.get_initial_plane_config =
14599 i9xx_get_initial_plane_config;
d6dfee7a 14600 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14601 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14602 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14603 dev_priv->display.update_primary_plane =
14604 i9xx_update_primary_plane;
f564048e 14605 } else {
0e8ffe1b 14606 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14607 dev_priv->display.get_initial_plane_config =
14608 i9xx_get_initial_plane_config;
d6dfee7a 14609 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14610 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14611 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14612 dev_priv->display.update_primary_plane =
14613 i9xx_update_primary_plane;
f564048e 14614 }
e70236a8 14615
e70236a8 14616 /* Returns the core display clock speed */
ef11bdb3 14617 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1652d19e
VS		 14618 dev_priv->display.get_display_clock_speed =
14619 skylake_get_display_clock_speed;
acd3f3d3
BP		 14620 else if (IS_BROXTON(dev))
14621 dev_priv->display.get_display_clock_speed =
14622 broxton_get_display_clock_speed;
1652d19e
VS		 14623 else if (IS_BROADWELL(dev))
14624 dev_priv->display.get_display_clock_speed =
14625 broadwell_get_display_clock_speed;
14626 else if (IS_HASWELL(dev))
14627 dev_priv->display.get_display_clock_speed =
14628 haswell_get_display_clock_speed;
14629 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14630 dev_priv->display.get_display_clock_speed =
14631 valleyview_get_display_clock_speed;
b37a6434
VS		 14632 else if (IS_GEN5(dev))
14633 dev_priv->display.get_display_clock_speed =
14634 ilk_get_display_clock_speed;
a7c66cd8 14635 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14636 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14637 dev_priv->display.get_display_clock_speed =
14638 i945_get_display_clock_speed;
34edce2f
VS		 14639 else if (IS_GM45(dev))
14640 dev_priv->display.get_display_clock_speed =
14641 gm45_get_display_clock_speed;
14642 else if (IS_CRESTLINE(dev))
14643 dev_priv->display.get_display_clock_speed =
14644 i965gm_get_display_clock_speed;
14645 else if (IS_PINEVIEW(dev))
14646 dev_priv->display.get_display_clock_speed =
14647 pnv_get_display_clock_speed;
14648 else if (IS_G33(dev) || IS_G4X(dev))
14649 dev_priv->display.get_display_clock_speed =
14650 g33_get_display_clock_speed;
e70236a8
JB		 14651 else if (IS_I915G(dev))
14652 dev_priv->display.get_display_clock_speed =
14653 i915_get_display_clock_speed;
257a7ffc 14654 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14655 dev_priv->display.get_display_clock_speed =
14656 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14657 else if (IS_PINEVIEW(dev))
14658 dev_priv->display.get_display_clock_speed =
14659 pnv_get_display_clock_speed;
e70236a8
JB		 14660 else if (IS_I915GM(dev))
14661 dev_priv->display.get_display_clock_speed =
14662 i915gm_get_display_clock_speed;
14663 else if (IS_I865G(dev))
14664 dev_priv->display.get_display_clock_speed =
14665 i865_get_display_clock_speed;
f0f8a9ce 14666 else if (IS_I85X(dev))
e70236a8 14667 dev_priv->display.get_display_clock_speed =
1b1d2716 14668 i85x_get_display_clock_speed;
623e01e5
VS		 14669 else { /* 830 */
14670 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14671 dev_priv->display.get_display_clock_speed =
14672 i830_get_display_clock_speed;
623e01e5 14673 }
e70236a8 14674
7c10a2b5 14675 if (IS_GEN5(dev)) {
3bb11b53 14676 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14677 } else if (IS_GEN6(dev)) {
14678 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14679 } else if (IS_IVYBRIDGE(dev)) {
14680 /* FIXME: detect B0+ stepping and use auto training */
14681 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14682 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14683 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14684 if (IS_BROADWELL(dev)) {
14685 dev_priv->display.modeset_commit_cdclk =
14686 broadwell_modeset_commit_cdclk;
14687 dev_priv->display.modeset_calc_cdclk =
14688 broadwell_modeset_calc_cdclk;
14689 }
30a970c6 14690 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14691 dev_priv->display.modeset_commit_cdclk =
14692 valleyview_modeset_commit_cdclk;
14693 dev_priv->display.modeset_calc_cdclk =
14694 valleyview_modeset_calc_cdclk;
f8437dd1 14695 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14696 dev_priv->display.modeset_commit_cdclk =
14697 broxton_modeset_commit_cdclk;
14698 dev_priv->display.modeset_calc_cdclk =
14699 broxton_modeset_calc_cdclk;
e70236a8 14700 }
8c9f3aaf 14701
8c9f3aaf
JB		 14702 switch (INTEL_INFO(dev)->gen) {
14703 case 2:
14704 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14705 break;
14706
14707 case 3:
14708 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14709 break;
14710
14711 case 4:
14712 case 5:
14713 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14714 break;
14715
14716 case 6:
14717 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14718 break;
7c9017e5 14719 case 7:
4e0bbc31 14720 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14721 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14722 break;
830c81db 14723 case 9:
ba343e02
TU		 14724 /* Drop through - unsupported since execlist only. */
14725 default:
14726 /* Default just returns -ENODEV to indicate unsupported */
14727 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14728 }
7bd688cd 14729
e39b999a 14730 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14731}
14732
b690e96c
JB		 14733/*
14734 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14735 * resume, or other times. This quirk makes sure that's the case for
14736 * affected systems.
14737 */
0206e353 14738static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14739{
14740 struct drm_i915_private *dev_priv = dev->dev_private;
14741
14742 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14743 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14744}
14745
b6b5d049
VS		 14746static void quirk_pipeb_force(struct drm_device *dev)
14747{
14748 struct drm_i915_private *dev_priv = dev->dev_private;
14749
14750 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14751 DRM_INFO("applying pipe b force quirk\n");
14752}
14753
435793df
KP		 14754/*
14755 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14756 */
14757static void quirk_ssc_force_disable(struct drm_device *dev)
14758{
14759 struct drm_i915_private *dev_priv = dev->dev_private;
14760 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14761 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14762}
14763
4dca20ef 14764/*
5a15ab5b
CE		 14765 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14766 * brightness value
4dca20ef
CE		 14767 */
14768static void quirk_invert_brightness(struct drm_device *dev)
14769{
14770 struct drm_i915_private *dev_priv = dev->dev_private;
14771 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14772 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14773}
14774
9c72cc6f
SD		 14775/* Some VBT's incorrectly indicate no backlight is present */
14776static void quirk_backlight_present(struct drm_device *dev)
14777{
14778 struct drm_i915_private *dev_priv = dev->dev_private;
14779 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14780 DRM_INFO("applying backlight present quirk\n");
14781}
14782
b690e96c
JB		 14783struct intel_quirk {
14784 int device;
14785 int subsystem_vendor;
14786 int subsystem_device;
14787 void (*hook)(struct drm_device *dev);
14788};
14789
5f85f176
EE		 14790/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14791struct intel_dmi_quirk {
14792 void (*hook)(struct drm_device *dev);
14793 const struct dmi_system_id (*dmi_id_list)[];
14794};
14795
14796static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14797{
14798 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14799 return 1;
14800}
14801
14802static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14803 {
14804 .dmi_id_list = &(const struct dmi_system_id[]) {
14805 {
14806 .callback = intel_dmi_reverse_brightness,
14807 .ident = "NCR Corporation",
14808 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14809 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14810 },
14811 },
14812 { } /* terminating entry */
14813 },
14814 .hook = quirk_invert_brightness,
14815 },
14816};
14817
c43b5634 14818static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14819 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14820 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14821
b690e96c
JB		 14822 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14823 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14824
5f080c0f
VS		 14825 /* 830 needs to leave pipe A & dpll A up */
14826 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14827
b6b5d049
VS		 14828 /* 830 needs to leave pipe B & dpll B up */
14829 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14830
435793df
KP		 14831 /* Lenovo U160 cannot use SSC on LVDS */
14832 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14833
14834 /* Sony Vaio Y cannot use SSC on LVDS */
14835 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14836
be505f64
AH		 14837 /* Acer Aspire 5734Z must invert backlight brightness */
14838 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14839
14840 /* Acer/eMachines G725 */
14841 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14842
14843 /* Acer/eMachines e725 */
14844 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14845
14846 /* Acer/Packard Bell NCL20 */
14847 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14848
14849 /* Acer Aspire 4736Z */
14850 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14851
14852 /* Acer Aspire 5336 */
14853 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14854
14855 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14856 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14857
dfb3d47b
SD		 14858 /* Acer C720 Chromebook (Core i3 4005U) */
14859 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14860
b2a9601c 14861 /* Apple Macbook 2,1 (Core 2 T7400) */
14862 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14863
d4967d8c
SD		 14864 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14865 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14866
14867 /* HP Chromebook 14 (Celeron 2955U) */
14868 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14869
14870 /* Dell Chromebook 11 */
14871 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14872};
14873
14874static void intel_init_quirks(struct drm_device *dev)
14875{
14876 struct pci_dev *d = dev->pdev;
14877 int i;
14878
14879 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14880 struct intel_quirk *q = &intel_quirks[i];
14881
14882 if (d->device == q->device &&
14883 (d->subsystem_vendor == q->subsystem_vendor ||
14884 q->subsystem_vendor == PCI_ANY_ID) &&
14885 (d->subsystem_device == q->subsystem_device ||
14886 q->subsystem_device == PCI_ANY_ID))
14887 q->hook(dev);
14888 }
5f85f176
EE		 14889 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14890 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14891 intel_dmi_quirks[i].hook(dev);
14892 }
b690e96c
JB		 14893}
14894
9cce37f4
JB		 14895/* Disable the VGA plane that we never use */
14896static void i915_disable_vga(struct drm_device *dev)
14897{
14898 struct drm_i915_private *dev_priv = dev->dev_private;
14899 u8 sr1;
766aa1c4 14900 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14901
2b37c616 14902 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14903 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14904 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14905 sr1 = inb(VGA_SR_DATA);
14906 outb(sr1 | 1<<5, VGA_SR_DATA);
14907 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14908 udelay(300);
14909
01f5a626 14910 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14911 POSTING_READ(vga_reg);
14912}
14913
f817586c
DV		 14914void intel_modeset_init_hw(struct drm_device *dev)
14915{
b6283055 14916 intel_update_cdclk(dev);
a8f78b58 14917 intel_prepare_ddi(dev);
f817586c 14918 intel_init_clock_gating(dev);
8090c6b9 14919 intel_enable_gt_powersave(dev);
f817586c
DV		 14920}
14921
79e53945
JB		 14922void intel_modeset_init(struct drm_device *dev)
14923{
652c393a 14924 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14925 int sprite, ret;
8cc87b75 14926 enum pipe pipe;
46f297fb 14927 struct intel_crtc *crtc;
79e53945
JB		 14928
14929 drm_mode_config_init(dev);
14930
14931 dev->mode_config.min_width = 0;
14932 dev->mode_config.min_height = 0;
14933
019d96cb
DA		 14934 dev->mode_config.preferred_depth = 24;
14935 dev->mode_config.prefer_shadow = 1;
14936
25bab385
TU		 14937 dev->mode_config.allow_fb_modifiers = true;
14938
e6ecefaa 14939 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14940
b690e96c
JB		 14941 intel_init_quirks(dev);
14942
1fa61106
ED		 14943 intel_init_pm(dev);
14944
e3c74757
BW		 14945 if (INTEL_INFO(dev)->num_pipes == 0)
14946 return;
14947
69f92f67
LW		 14948 /*
14949 * There may be no VBT; and if the BIOS enabled SSC we can
14950 * just keep using it to avoid unnecessary flicker. Whereas if the
14951 * BIOS isn't using it, don't assume it will work even if the VBT
14952 * indicates as much.
14953 */
14954 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14955 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14956 DREF_SSC1_ENABLE);
14957
14958 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14959 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14960 bios_lvds_use_ssc ? "en" : "dis",
14961 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14962 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14963 }
14964 }
14965
e70236a8 14966 intel_init_display(dev);
7c10a2b5 14967 intel_init_audio(dev);
e70236a8 14968
a6c45cf0
CW		 14969 if (IS_GEN2(dev)) {
14970 dev->mode_config.max_width = 2048;
14971 dev->mode_config.max_height = 2048;
14972 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14973 dev->mode_config.max_width = 4096;
14974 dev->mode_config.max_height = 4096;
79e53945 14975 } else {
a6c45cf0
CW		 14976 dev->mode_config.max_width = 8192;
14977 dev->mode_config.max_height = 8192;
79e53945 14978 }
068be561 14979
dc41c154
VS		 14980 if (IS_845G(dev) || IS_I865G(dev)) {
14981 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14982 dev->mode_config.cursor_height = 1023;
14983 } else if (IS_GEN2(dev)) {
068be561
DL		 14984 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14985 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14986 } else {
14987 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14988 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14989 }
14990
5d4545ae 14991 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14992
28c97730 14993 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14994 INTEL_INFO(dev)->num_pipes,
14995 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14996
055e393f 14997 for_each_pipe(dev_priv, pipe) {
8cc87b75 14998 intel_crtc_init(dev, pipe);
3bdcfc0c 14999 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15000 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15001 if (ret)
06da8da2 15002 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15003 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15004 }
79e53945
JB		 15005 }
15006
bfa7df01
VS		 15007 intel_update_czclk(dev_priv);
15008 intel_update_cdclk(dev);
15009
e72f9fbf 15010 intel_shared_dpll_init(dev);
ee7b9f93 15011
9cce37f4
JB		 15012 /* Just disable it once at startup */
15013 i915_disable_vga(dev);
79e53945 15014 intel_setup_outputs(dev);
11be49eb
CW		 15015
15016 /* Just in case the BIOS is doing something questionable. */
7733b49b 15017 intel_fbc_disable(dev_priv);
fa9fa083 15018
6e9f798d 15019 drm_modeset_lock_all(dev);
043e9bda 15020 intel_modeset_setup_hw_state(dev);
6e9f798d 15021 drm_modeset_unlock_all(dev);
46f297fb 15022
d3fcc808 15023 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 15024 struct intel_initial_plane_config plane_config = {};
15025
46f297fb
JB		 15026 if (!crtc->active)
15027 continue;
15028
46f297fb 15029 /*
46f297fb
JB		 15030 * Note that reserving the BIOS fb up front prevents us
15031 * from stuffing other stolen allocations like the ring
15032 * on top. This prevents some ugliness at boot time, and
15033 * can even allow for smooth boot transitions if the BIOS
15034 * fb is large enough for the active pipe configuration.
15035 */
eeebeac5
ML		 15036 dev_priv->display.get_initial_plane_config(crtc,
15037 &plane_config);
15038
15039 /*
15040 * If the fb is shared between multiple heads, we'll
15041 * just get the first one.
15042 */
15043 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 15044 }
2c7111db
CW		 15045}
15046
7fad798e
DV		 15047static void intel_enable_pipe_a(struct drm_device *dev)
15048{
15049 struct intel_connector *connector;
15050 struct drm_connector *crt = NULL;
15051 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15052 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15053
15054 /* We can't just switch on the pipe A, we need to set things up with a
15055 * proper mode and output configuration. As a gross hack, enable pipe A
15056 * by enabling the load detect pipe once. */
3a3371ff 15057 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15058 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15059 crt = &connector->base;
15060 break;
15061 }
15062 }
15063
15064 if (!crt)
15065 return;
15066
208bf9fd 15067 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15068 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15069}
15070
fa555837
DV		 15071static bool
15072intel_check_plane_mapping(struct intel_crtc *crtc)
15073{
7eb552ae
BW		 15074 struct drm_device *dev = crtc->base.dev;
15075 struct drm_i915_private *dev_priv = dev->dev_private;
649636ef 15076 u32 val;
fa555837 15077
7eb552ae 15078 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15079 return true;
15080
649636ef 15081 val = I915_READ(DSPCNTR(!crtc->plane));
fa555837
DV		 15082
15083 if ((val & DISPLAY_PLANE_ENABLE) &&
15084 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15085 return false;
15086
15087 return true;
15088}
15089
02e93c35
VS		 15090static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15091{
15092 struct drm_device *dev = crtc->base.dev;
15093 struct intel_encoder *encoder;
15094
15095 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15096 return true;
15097
15098 return false;
15099}
15100
24929352
DV		 15101static void intel_sanitize_crtc(struct intel_crtc *crtc)
15102{
15103 struct drm_device *dev = crtc->base.dev;
15104 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15105 u32 reg;
24929352 15106
24929352 15107 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15108 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15109 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15110
d3eaf884 15111 /* restore vblank interrupts to correct state */
9625604c 15112 drm_crtc_vblank_reset(&crtc->base);
d297e103 15113 if (crtc->active) {
f9cd7b88
VS		 15114 struct intel_plane *plane;
15115
9625604c 15116 drm_crtc_vblank_on(&crtc->base);
f9cd7b88
VS		 15117
15118 /* Disable everything but the primary plane */
15119 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15120 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15121 continue;
15122
15123 plane->disable_plane(&plane->base, &crtc->base);
15124 }
9625604c 15125 }
d3eaf884 15126
24929352 15127 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15128 * disable the crtc (and hence change the state) if it is wrong. Note
15129 * that gen4+ has a fixed plane -> pipe mapping. */
15130 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15131 bool plane;
15132
24929352
DV		 15133 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15134 crtc->base.base.id);
15135
15136 /* Pipe has the wrong plane attached and the plane is active.
15137 * Temporarily change the plane mapping and disable everything
15138 * ... */
15139 plane = crtc->plane;
b70709a6 15140 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15141 crtc->plane = !plane;
b17d48e2 15142 intel_crtc_disable_noatomic(&crtc->base);
24929352 15143 crtc->plane = plane;
24929352 15144 }
24929352 15145
7fad798e
DV		 15146 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15147 crtc->pipe == PIPE_A && !crtc->active) {
15148 /* BIOS forgot to enable pipe A, this mostly happens after
15149 * resume. Force-enable the pipe to fix this, the update_dpms
15150 * call below we restore the pipe to the right state, but leave
15151 * the required bits on. */
15152 intel_enable_pipe_a(dev);
15153 }
15154
24929352
DV		 15155 /* Adjust the state of the output pipe according to whether we
15156 * have active connectors/encoders. */
02e93c35 15157 if (!intel_crtc_has_encoders(crtc))
b17d48e2 15158 intel_crtc_disable_noatomic(&crtc->base);
24929352 15159
53d9f4e9 15160 if (crtc->active != crtc->base.state->active) {
02e93c35 15161 struct intel_encoder *encoder;
24929352
DV		 15162
15163 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15164 * functions or because of calls to intel_crtc_disable_noatomic,
15165 * or because the pipe is force-enabled due to the
24929352
DV		 15166 * pipe A quirk. */
15167 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15168 crtc->base.base.id,
83d65738 15169 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15170 crtc->active ? "enabled" : "disabled");
15171
4be40c98 15172 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 15173 crtc->base.state->active = crtc->active;
24929352
DV		 15174 crtc->base.enabled = crtc->active;
15175
15176 /* Because we only establish the connector -> encoder ->
15177 * crtc links if something is active, this means the
15178 * crtc is now deactivated. Break the links. connector
15179 * -> encoder links are only establish when things are
15180 * actually up, hence no need to break them. */
15181 WARN_ON(crtc->active);
15182
2d406bb0 15183 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 15184 encoder->base.crtc = NULL;
24929352 15185 }
c5ab3bc0 15186
a3ed6aad 15187 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15188 /*
15189 * We start out with underrun reporting disabled to avoid races.
15190 * For correct bookkeeping mark this on active crtcs.
15191 *
c5ab3bc0
DV		 15192 * Also on gmch platforms we dont have any hardware bits to
15193 * disable the underrun reporting. Which means we need to start
15194 * out with underrun reporting disabled also on inactive pipes,
15195 * since otherwise we'll complain about the garbage we read when
15196 * e.g. coming up after runtime pm.
15197 *
4cc31489
DV		 15198 * No protection against concurrent access is required - at
15199 * worst a fifo underrun happens which also sets this to false.
15200 */
15201 crtc->cpu_fifo_underrun_disabled = true;
15202 crtc->pch_fifo_underrun_disabled = true;
15203 }
24929352
DV		 15204}
15205
15206static void intel_sanitize_encoder(struct intel_encoder *encoder)
15207{
15208 struct intel_connector *connector;
15209 struct drm_device *dev = encoder->base.dev;
873ffe69 15210 bool active = false;
24929352
DV		 15211
15212 /* We need to check both for a crtc link (meaning that the
15213 * encoder is active and trying to read from a pipe) and the
15214 * pipe itself being active. */
15215 bool has_active_crtc = encoder->base.crtc &&
15216 to_intel_crtc(encoder->base.crtc)->active;
15217
873ffe69
ML		 15218 for_each_intel_connector(dev, connector) {
15219 if (connector->base.encoder != &encoder->base)
15220 continue;
15221
15222 active = true;
15223 break;
15224 }
15225
15226 if (active && !has_active_crtc) {
24929352
DV		 15227 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15228 encoder->base.base.id,
8e329a03 15229 encoder->base.name);
24929352
DV		 15230
15231 /* Connector is active, but has no active pipe. This is
15232 * fallout from our resume register restoring. Disable
15233 * the encoder manually again. */
15234 if (encoder->base.crtc) {
15235 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15236 encoder->base.base.id,
8e329a03 15237 encoder->base.name);
24929352 15238 encoder->disable(encoder);
a62d1497
VS		 15239 if (encoder->post_disable)
15240 encoder->post_disable(encoder);
24929352 15241 }
7f1950fb 15242 encoder->base.crtc = NULL;
24929352
DV		 15243
15244 /* Inconsistent output/port/pipe state happens presumably due to
15245 * a bug in one of the get_hw_state functions. Or someplace else
15246 * in our code, like the register restore mess on resume. Clamp
15247 * things to off as a safer default. */
3a3371ff 15248 for_each_intel_connector(dev, connector) {
24929352
DV		 15249 if (connector->encoder != encoder)
15250 continue;
7f1950fb
EE		 15251 connector->base.dpms = DRM_MODE_DPMS_OFF;
15252 connector->base.encoder = NULL;
24929352
DV		 15253 }
15254 }
15255 /* Enabled encoders without active connectors will be fixed in
15256 * the crtc fixup. */
15257}
15258
04098753 15259void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15260{
15261 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15262 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15263
04098753
ID		 15264 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15265 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15266 i915_disable_vga(dev);
15267 }
15268}
15269
15270void i915_redisable_vga(struct drm_device *dev)
15271{
15272 struct drm_i915_private *dev_priv = dev->dev_private;
15273
8dc8a27c
PZ		 15274 /* This function can be called both from intel_modeset_setup_hw_state or
15275 * at a very early point in our resume sequence, where the power well
15276 * structures are not yet restored. Since this function is at a very
15277 * paranoid "someone might have enabled VGA while we were not looking"
15278 * level, just check if the power well is enabled instead of trying to
15279 * follow the "don't touch the power well if we don't need it" policy
15280 * the rest of the driver uses. */
f458ebbc 15281 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15282 return;
15283
04098753 15284 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15285}
15286
f9cd7b88 15287static bool primary_get_hw_state(struct intel_plane *plane)
98ec7739 15288{
f9cd7b88 15289 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
98ec7739 15290
f9cd7b88 15291 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
d032ffa0
ML		 15292}
15293
f9cd7b88
VS		 15294/* FIXME read out full plane state for all planes */
15295static void readout_plane_state(struct intel_crtc *crtc)
d032ffa0 15296{
b26d3ea3 15297 struct drm_plane *primary = crtc->base.primary;
f9cd7b88 15298 struct intel_plane_state *plane_state =
b26d3ea3 15299 to_intel_plane_state(primary->state);
d032ffa0 15300
19b8d387 15301 plane_state->visible = crtc->active &&
b26d3ea3
ML		 15302 primary_get_hw_state(to_intel_plane(primary));
15303
15304 if (plane_state->visible)
15305 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
98ec7739
VS		 15306}
15307
30e984df 15308static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15309{
15310 struct drm_i915_private *dev_priv = dev->dev_private;
15311 enum pipe pipe;
24929352
DV		 15312 struct intel_crtc *crtc;
15313 struct intel_encoder *encoder;
15314 struct intel_connector *connector;
5358901f 15315 int i;
24929352 15316
d3fcc808 15317 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15318 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15319 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15320 crtc->config->base.crtc = &crtc->base;
3b117c8f 15321
0e8ffe1b 15322 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15323 crtc->config);
24929352 15324
49d6fa21 15325 crtc->base.state->active = crtc->active;
24929352 15326 crtc->base.enabled = crtc->active;
b70709a6 15327
f9cd7b88 15328 readout_plane_state(crtc);
24929352
DV		 15329
15330 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15331 crtc->base.base.id,
15332 crtc->active ? "enabled" : "disabled");
15333 }
15334
5358901f
DV		 15335 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15336 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15337
3e369b76
ACO		 15338 pll->on = pll->get_hw_state(dev_priv, pll,
15339 &pll->config.hw_state);
5358901f 15340 pll->active = 0;
3e369b76 15341 pll->config.crtc_mask = 0;
d3fcc808 15342 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15343 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15344 pll->active++;
3e369b76 15345 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15346 }
5358901f 15347 }
5358901f 15348
1e6f2ddc 15349 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15350 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15351
3e369b76 15352 if (pll->config.crtc_mask)
bd2bb1b9 15353 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15354 }
15355
b2784e15 15356 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15357 pipe = 0;
15358
15359 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15360 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15361 encoder->base.crtc = &crtc->base;
6e3c9717 15362 encoder->get_config(encoder, crtc->config);
24929352
DV		 15363 } else {
15364 encoder->base.crtc = NULL;
15365 }
15366
6f2bcceb 15367 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15368 encoder->base.base.id,
8e329a03 15369 encoder->base.name,
24929352 15370 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15371 pipe_name(pipe));
24929352
DV		 15372 }
15373
3a3371ff 15374 for_each_intel_connector(dev, connector) {
24929352
DV		 15375 if (connector->get_hw_state(connector)) {
15376 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15377 connector->base.encoder = &connector->encoder->base;
15378 } else {
15379 connector->base.dpms = DRM_MODE_DPMS_OFF;
15380 connector->base.encoder = NULL;
15381 }
15382 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15383 connector->base.base.id,
c23cc417 15384 connector->base.name,
24929352
DV		 15385 connector->base.encoder ? "enabled" : "disabled");
15386 }
7f4c6284
VS		 15387
15388 for_each_intel_crtc(dev, crtc) {
15389 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15390
15391 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15392 if (crtc->base.state->active) {
15393 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15394 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15395 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15396
15397 /*
15398 * The initial mode needs to be set in order to keep
15399 * the atomic core happy. It wants a valid mode if the
15400 * crtc's enabled, so we do the above call.
15401 *
15402 * At this point some state updated by the connectors
15403 * in their ->detect() callback has not run yet, so
15404 * no recalculation can be done yet.
15405 *
15406 * Even if we could do a recalculation and modeset
15407 * right now it would cause a double modeset if
15408 * fbdev or userspace chooses a different initial mode.
15409 *
15410 * If that happens, someone indicated they wanted a
15411 * mode change, which means it's safe to do a full
15412 * recalculation.
15413 */
15414 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
9eca6832
VS		 15415
15416 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15417 update_scanline_offset(crtc);
7f4c6284
VS		 15418 }
15419 }
30e984df
DV		 15420}
15421
043e9bda
ML		 15422/* Scan out the current hw modeset state,
15423 * and sanitizes it to the current state
15424 */
15425static void
15426intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15427{
15428 struct drm_i915_private *dev_priv = dev->dev_private;
15429 enum pipe pipe;
30e984df
DV		 15430 struct intel_crtc *crtc;
15431 struct intel_encoder *encoder;
35c95375 15432 int i;
30e984df
DV		 15433
15434 intel_modeset_readout_hw_state(dev);
24929352
DV		 15435
15436 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15437 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15438 intel_sanitize_encoder(encoder);
15439 }
15440
055e393f 15441 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15442 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15443 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15444 intel_dump_pipe_config(crtc, crtc->config,
15445 "[setup_hw_state]");
24929352 15446 }
9a935856 15447
d29b2f9d
ACO		 15448 intel_modeset_update_connector_atomic_state(dev);
15449
35c95375
DV		 15450 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15451 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15452
15453 if (!pll->on || pll->active)
15454 continue;
15455
15456 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15457
15458 pll->disable(dev_priv, pll);
15459 pll->on = false;
15460 }
15461
26e1fe4f 15462 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15463 vlv_wm_get_hw_state(dev);
15464 else if (IS_GEN9(dev))
3078999f
PB		 15465 skl_wm_get_hw_state(dev);
15466 else if (HAS_PCH_SPLIT(dev))
243e6a44 15467 ilk_wm_get_hw_state(dev);
292b990e
ML		 15468
15469 for_each_intel_crtc(dev, crtc) {
15470 unsigned long put_domains;
15471
15472 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15473 if (WARN_ON(put_domains))
15474 modeset_put_power_domains(dev_priv, put_domains);
15475 }
15476 intel_display_set_init_power(dev_priv, false);
043e9bda 15477}
7d0bc1ea 15478
043e9bda
ML		 15479void intel_display_resume(struct drm_device *dev)
15480{
15481 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15482 struct intel_connector *conn;
15483 struct intel_plane *plane;
15484 struct drm_crtc *crtc;
15485 int ret;
f30da187 15486
043e9bda
ML		 15487 if (!state)
15488 return;
15489
15490 state->acquire_ctx = dev->mode_config.acquire_ctx;
15491
15492 /* preserve complete old state, including dpll */
15493 intel_atomic_get_shared_dpll_state(state);
15494
15495 for_each_crtc(dev, crtc) {
15496 struct drm_crtc_state *crtc_state =
15497 drm_atomic_get_crtc_state(state, crtc);
15498
15499 ret = PTR_ERR_OR_ZERO(crtc_state);
15500 if (ret)
15501 goto err;
15502
15503 /* force a restore */
15504 crtc_state->mode_changed = true;
45e2b5f6 15505 }
8af6cf88 15506
043e9bda
ML		 15507 for_each_intel_plane(dev, plane) {
15508 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15509 if (ret)
15510 goto err;
15511 }
15512
15513 for_each_intel_connector(dev, conn) {
15514 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15515 if (ret)
15516 goto err;
15517 }
15518
15519 intel_modeset_setup_hw_state(dev);
15520
15521 i915_redisable_vga(dev);
74c090b1 15522 ret = drm_atomic_commit(state);
043e9bda
ML		 15523 if (!ret)
15524 return;
15525
15526err:
15527 DRM_ERROR("Restoring old state failed with %i\n", ret);
15528 drm_atomic_state_free(state);
2c7111db
CW		 15529}
15530
15531void intel_modeset_gem_init(struct drm_device *dev)
15532{
484b41dd 15533 struct drm_crtc *c;
2ff8fde1 15534 struct drm_i915_gem_object *obj;
e0d6149b 15535 int ret;
484b41dd 15536
ae48434c
ID		 15537 mutex_lock(&dev->struct_mutex);
15538 intel_init_gt_powersave(dev);
15539 mutex_unlock(&dev->struct_mutex);
15540
1833b134 15541 intel_modeset_init_hw(dev);
02e792fb
DV		 15542
15543 intel_setup_overlay(dev);
484b41dd
JB		 15544
15545 /*
15546 * Make sure any fbs we allocated at startup are properly
15547 * pinned & fenced. When we do the allocation it's too early
15548 * for this.
15549 */
70e1e0ec 15550 for_each_crtc(dev, c) {
2ff8fde1
MR		 15551 obj = intel_fb_obj(c->primary->fb);
15552 if (obj == NULL)
484b41dd
JB		 15553 continue;
15554
e0d6149b
TU		 15555 mutex_lock(&dev->struct_mutex);
15556 ret = intel_pin_and_fence_fb_obj(c->primary,
15557 c->primary->fb,
7580d774 15558 c->primary->state);
e0d6149b
TU		 15559 mutex_unlock(&dev->struct_mutex);
15560 if (ret) {
484b41dd
JB		 15561 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15562 to_intel_crtc(c)->pipe);
66e514c1
DA		 15563 drm_framebuffer_unreference(c->primary->fb);
15564 c->primary->fb = NULL;
36750f28 15565 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15566 update_state_fb(c->primary);
36750f28 15567 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15568 }
15569 }
0962c3c9
VS		 15570
15571 intel_backlight_register(dev);
79e53945
JB		 15572}
15573
4932e2c3
ID		 15574void intel_connector_unregister(struct intel_connector *intel_connector)
15575{
15576 struct drm_connector *connector = &intel_connector->base;
15577
15578 intel_panel_destroy_backlight(connector);
34ea3d38 15579 drm_connector_unregister(connector);
4932e2c3
ID		 15580}
15581
79e53945
JB		 15582void intel_modeset_cleanup(struct drm_device *dev)
15583{
652c393a 15584 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15585 struct drm_connector *connector;
652c393a 15586
2eb5252e
ID		 15587 intel_disable_gt_powersave(dev);
15588
0962c3c9
VS		 15589 intel_backlight_unregister(dev);
15590
fd0c0642
DV		 15591 /*
15592 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15593 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15594 * experience fancy races otherwise.
15595 */
2aeb7d3a 15596 intel_irq_uninstall(dev_priv);
eb21b92b 15597
fd0c0642
DV		 15598 /*
15599 * Due to the hpd irq storm handling the hotplug work can re-arm the
15600 * poll handlers. Hence disable polling after hpd handling is shut down.
15601 */
f87ea761 15602 drm_kms_helper_poll_fini(dev);
fd0c0642 15603
723bfd70
JB		 15604 intel_unregister_dsm_handler();
15605
7733b49b 15606 intel_fbc_disable(dev_priv);
69341a5e 15607
1630fe75
CW		 15608 /* flush any delayed tasks or pending work */
15609 flush_scheduled_work();
15610
db31af1d
JN		 15611 /* destroy the backlight and sysfs files before encoders/connectors */
15612 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15613 struct intel_connector *intel_connector;
15614
15615 intel_connector = to_intel_connector(connector);
15616 intel_connector->unregister(intel_connector);
db31af1d 15617 }
d9255d57 15618
79e53945 15619 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15620
15621 intel_cleanup_overlay(dev);
ae48434c
ID		 15622
15623 mutex_lock(&dev->struct_mutex);
15624 intel_cleanup_gt_powersave(dev);
15625 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15626}
15627
f1c79df3
ZW		 15628/*
15629 * Return which encoder is currently attached for connector.
15630 */
df0e9248 15631struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15632{
df0e9248
CW		 15633 return &intel_attached_encoder(connector)->base;
15634}
f1c79df3 15635
df0e9248
CW		 15636void intel_connector_attach_encoder(struct intel_connector *connector,
15637 struct intel_encoder *encoder)
15638{
15639 connector->encoder = encoder;
15640 drm_mode_connector_attach_encoder(&connector->base,
15641 &encoder->base);
79e53945 15642}
28d52043
DA		 15643
15644/*
15645 * set vga decode state - true == enable VGA decode
15646 */
15647int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15648{
15649 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15650 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15651 u16 gmch_ctrl;
15652
75fa041d
CW		 15653 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15654 DRM_ERROR("failed to read control word\n");
15655 return -EIO;
15656 }
15657
c0cc8a55
CW		 15658 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15659 return 0;
15660
28d52043
DA		 15661 if (state)
15662 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15663 else
15664 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15665
15666 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15667 DRM_ERROR("failed to write control word\n");
15668 return -EIO;
15669 }
15670
28d52043
DA		 15671 return 0;
15672}
c4a1d9e4 15673
c4a1d9e4 15674struct intel_display_error_state {
ff57f1b0
PZ		 15675
15676 u32 power_well_driver;
15677
63b66e5b
CW		 15678 int num_transcoders;
15679
c4a1d9e4
CW		 15680 struct intel_cursor_error_state {
15681 u32 control;
15682 u32 position;
15683 u32 base;
15684 u32 size;
52331309 15685 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15686
15687 struct intel_pipe_error_state {
ddf9c536 15688 bool power_domain_on;
c4a1d9e4 15689 u32 source;
f301b1e1 15690 u32 stat;
52331309 15691 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15692
15693 struct intel_plane_error_state {
15694 u32 control;
15695 u32 stride;
15696 u32 size;
15697 u32 pos;
15698 u32 addr;
15699 u32 surface;
15700 u32 tile_offset;
52331309 15701 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15702
15703 struct intel_transcoder_error_state {
ddf9c536 15704 bool power_domain_on;
63b66e5b
CW		 15705 enum transcoder cpu_transcoder;
15706
15707 u32 conf;
15708
15709 u32 htotal;
15710 u32 hblank;
15711 u32 hsync;
15712 u32 vtotal;
15713 u32 vblank;
15714 u32 vsync;
15715 } transcoder[4];
c4a1d9e4
CW		 15716};
15717
15718struct intel_display_error_state *
15719intel_display_capture_error_state(struct drm_device *dev)
15720{
fbee40df 15721 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15722 struct intel_display_error_state *error;
63b66e5b
CW		 15723 int transcoders[] = {
15724 TRANSCODER_A,
15725 TRANSCODER_B,
15726 TRANSCODER_C,
15727 TRANSCODER_EDP,
15728 };
c4a1d9e4
CW		 15729 int i;
15730
63b66e5b
CW		 15731 if (INTEL_INFO(dev)->num_pipes == 0)
15732 return NULL;
15733
9d1cb914 15734 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15735 if (error == NULL)
15736 return NULL;
15737
190be112 15738 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15739 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15740
055e393f 15741 for_each_pipe(dev_priv, i) {
ddf9c536 15742 error->pipe[i].power_domain_on =
f458ebbc
DV		 15743 __intel_display_power_is_enabled(dev_priv,
15744 POWER_DOMAIN_PIPE(i));
ddf9c536 15745 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15746 continue;
15747
5efb3e28
VS		 15748 error->cursor[i].control = I915_READ(CURCNTR(i));
15749 error->cursor[i].position = I915_READ(CURPOS(i));
15750 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15751
15752 error->plane[i].control = I915_READ(DSPCNTR(i));
15753 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15754 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15755 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15756 error->plane[i].pos = I915_READ(DSPPOS(i));
15757 }
ca291363
PZ		 15758 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15759 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15760 if (INTEL_INFO(dev)->gen >= 4) {
15761 error->plane[i].surface = I915_READ(DSPSURF(i));
15762 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15763 }
15764
c4a1d9e4 15765 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15766
3abfce77 15767 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15768 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15769 }
15770
15771 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15772 if (HAS_DDI(dev_priv->dev))
15773 error->num_transcoders++; /* Account for eDP. */
15774
15775 for (i = 0; i < error->num_transcoders; i++) {
15776 enum transcoder cpu_transcoder = transcoders[i];
15777
ddf9c536 15778 error->transcoder[i].power_domain_on =
f458ebbc 15779 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15780 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15781 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15782 continue;
15783
63b66e5b
CW		 15784 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15785
15786 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15787 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15788 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15789 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15790 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15791 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15792 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15793 }
15794
15795 return error;
15796}
15797
edc3d884
MK		 15798#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15799
c4a1d9e4 15800void
edc3d884 15801intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15802 struct drm_device *dev,
15803 struct intel_display_error_state *error)
15804{
055e393f 15805 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15806 int i;
15807
63b66e5b
CW		 15808 if (!error)
15809 return;
15810
edc3d884 15811 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15812 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15813 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15814 error->power_well_driver);
055e393f 15815 for_each_pipe(dev_priv, i) {
edc3d884 15816 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15817 err_printf(m, " Power: %s\n",
15818 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15819 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15820 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15821
15822 err_printf(m, "Plane [%d]:\n", i);
15823 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15824 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15825 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15826 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15827 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15828 }
4b71a570 15829 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15830 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15831 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15832 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15833 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15834 }
15835
edc3d884
MK		 15836 err_printf(m, "Cursor [%d]:\n", i);
15837 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15838 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15839 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15840 }
63b66e5b
CW		 15841
15842 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15843 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15844 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15845 err_printf(m, " Power: %s\n",
15846 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15847 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15848 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15849 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15850 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15851 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15852 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15853 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15854 }
c4a1d9e4 15855}
e2fcdaa9
VS		 15856
15857void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15858{
15859 struct intel_crtc *crtc;
15860
15861 for_each_intel_crtc(dev, crtc) {
15862 struct intel_unpin_work *work;
e2fcdaa9 15863
5e2d7afc 15864 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15865
15866 work = crtc->unpin_work;
15867
15868 if (work && work->event &&
15869 work->event->base.file_priv == file) {
15870 kfree(work->event);
15871 work->event = NULL;
15872 }
15873
5e2d7afc 15874 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15875 }
15876}
Linux kernel - Deliverables
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