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drm/i915: Wait upon the last request seqno, rather than a future seqno
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
419 unsigned long flags;
420 u32 val = 0;
421
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
425 goto out_unlock;
426 }
427
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430 DPIO_BYTE);
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
433 goto out_unlock;
434 }
435 val = I915_READ(DPIO_DATA);
436
437out_unlock:
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439 return val;
440}
441
a0c4da24
JB		 442static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443 u32 val)
444{
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
450 goto out_unlock;
451 }
452
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456 DPIO_BYTE);
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
459
460out_unlock:
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462}
463
57f350b6
JB		 464static void vlv_init_dpio(struct drm_device *dev)
465{
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
473}
474
618563e3
DV		 475static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
476{
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
478 return 1;
479}
480
481static const struct dmi_system_id intel_dual_link_lvds[] = {
482 {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
485 .matches = {
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
488 },
489 },
490 { } /* terminating entry */
491};
492
b0354385
TI		 493static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
494 unsigned int reg)
495{
496 unsigned int val;
497
121d527a
TI		 498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
501
618563e3
DV		 502 if (dmi_check_system(intel_dual_link_lvds))
503 return true;
504
b0354385
TI		 505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
507 else {
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
512 */
513 val = I915_READ(reg);
14d94a3d 514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
517 }
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
519}
520
1b894b59
CW		 521static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
522 int refclk)
2c07245f 523{
b91ad0ec
ZW		 524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 526 const intel_limit_t *limit;
b91ad0ec
ZW		 527
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 530 /* LVDS dual channel */
1b894b59 531 if (refclk == 100000)
b91ad0ec
ZW		 532 limit = &intel_limits_ironlake_dual_lvds_100m;
533 else
534 limit = &intel_limits_ironlake_dual_lvds;
535 } else {
1b894b59 536 if (refclk == 100000)
b91ad0ec
ZW		 537 limit = &intel_limits_ironlake_single_lvds_100m;
538 else
539 limit = &intel_limits_ironlake_single_lvds;
540 }
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 543 limit = &intel_limits_ironlake_display_port;
2c07245f 544 else
b91ad0ec 545 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 546
547 return limit;
548}
549
044c7c41
ML		 550static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
551{
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 557 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 558 /* LVDS with dual channel */
e4b36699 559 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 560 else
561 /* LVDS with dual channel */
e4b36699 562 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 565 limit = &intel_limits_g4x_hdmi;
044c7c41 566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 567 limit = &intel_limits_g4x_sdvo;
0206e353 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 569 limit = &intel_limits_g4x_display_port;
044c7c41 570 } else /* The option is for other outputs */
e4b36699 571 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 572
573 return limit;
574}
575
1b894b59 576static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 577{
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
580
bad720ff 581 if (HAS_PCH_SPLIT(dev))
1b894b59 582 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 583 else if (IS_G4X(dev)) {
044c7c41 584 limit = intel_g4x_limit(crtc);
f2b115e6 585 } else if (IS_PINEVIEW(dev)) {
2177832f 586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 587 limit = &intel_limits_pineview_lvds;
2177832f 588 else
f2b115e6 589 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
595 else
596 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
600 else
601 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 602 } else {
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 604 limit = &intel_limits_i8xx_lvds;
79e53945 605 else
e4b36699 606 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 607 }
608 return limit;
609}
610
f2b115e6
AJ		 611/* m1 is reserved as 0 in Pineview, n is a ring counter */
612static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 613{
2177832f
SL		 614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
618}
619
620static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
621{
f2b115e6
AJ		 622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
2177832f
SL		 624 return;
625 }
79e53945
JB		 626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
630}
631
79e53945
JB		 632/**
633 * Returns whether any output on the specified pipe is of the specified type
634 */
4ef69c7a 635bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 636{
4ef69c7a 637 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 638 struct intel_encoder *encoder;
639
6c2b7c12
DV		 640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
4ef69c7a
CW		 642 return true;
643
644 return false;
79e53945
JB		 645}
646
7c04d1d9 647#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 648/**
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
651 */
652
1b894b59
CW		 653static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
79e53945 656{
79e53945 657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 658 INTELPllInvalid("p1 out of range\n");
79e53945 659 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 660 INTELPllInvalid("p out of range\n");
79e53945 661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 662 INTELPllInvalid("m2 out of range\n");
79e53945 663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 664 INTELPllInvalid("m1 out of range\n");
f2b115e6 665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 666 INTELPllInvalid("m1 <= m2\n");
79e53945 667 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 668 INTELPllInvalid("m out of range\n");
79e53945 669 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 670 INTELPllInvalid("n out of range\n");
79e53945 671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 672 INTELPllInvalid("vco out of range\n");
79e53945
JB		 673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
675 */
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 677 INTELPllInvalid("dot out of range\n");
79e53945
JB		 678
679 return true;
680}
681
d4906093
ML		 682static bool
683intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
d4906093 686
79e53945
JB		 687{
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 intel_clock_t clock;
79e53945
JB		 691 int err = target;
692
bc5e5718 693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 694 (I915_READ(LVDS)) != 0) {
79e53945
JB		 695 /*
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
699 * even can.
700 */
b0354385 701 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
0206e353 712 memset(best_clock, 0, sizeof(*best_clock));
79e53945 713
42158660
ZY		 714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 718 /* m1 is always 0 in Pineview */
719 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 720 break;
721 for (clock.n = limit->n.min;
722 clock.n <= limit->n.max; clock.n++) {
723 for (clock.p1 = limit->p1.min;
724 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 725 int this_err;
726
2177832f 727 intel_clock(dev, refclk, &clock);
1b894b59
CW		 728 if (!intel_PLL_is_valid(dev, limit,
729 &clock))
79e53945 730 continue;
cec2f356
SP		 731 if (match_clock &&
732 clock.p != match_clock->p)
733 continue;
79e53945
JB		 734
735 this_err = abs(clock.dot - target);
736 if (this_err < err) {
737 *best_clock = clock;
738 err = this_err;
739 }
740 }
741 }
742 }
743 }
744
745 return (err != target);
746}
747
d4906093
ML		 748static bool
749intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
d4906093
ML		 752{
753 struct drm_device *dev = crtc->dev;
754 struct drm_i915_private *dev_priv = dev->dev_private;
755 intel_clock_t clock;
756 int max_n;
757 bool found;
6ba770dc
AJ		 758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 760 found = false;
761
762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 763 int lvds_reg;
764
c619eed4 765 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 766 lvds_reg = PCH_LVDS;
767 else
768 lvds_reg = LVDS;
769 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 770 LVDS_CLKB_POWER_UP)
771 clock.p2 = limit->p2.p2_fast;
772 else
773 clock.p2 = limit->p2.p2_slow;
774 } else {
775 if (target < limit->p2.dot_limit)
776 clock.p2 = limit->p2.p2_slow;
777 else
778 clock.p2 = limit->p2.p2_fast;
779 }
780
781 memset(best_clock, 0, sizeof(*best_clock));
782 max_n = limit->n.max;
f77f13e2 783 /* based on hardware requirement, prefer smaller n to precision */
d4906093 784 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 785 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 786 for (clock.m1 = limit->m1.max;
787 clock.m1 >= limit->m1.min; clock.m1--) {
788 for (clock.m2 = limit->m2.max;
789 clock.m2 >= limit->m2.min; clock.m2--) {
790 for (clock.p1 = limit->p1.max;
791 clock.p1 >= limit->p1.min; clock.p1--) {
792 int this_err;
793
2177832f 794 intel_clock(dev, refclk, &clock);
1b894b59
CW		 795 if (!intel_PLL_is_valid(dev, limit,
796 &clock))
d4906093 797 continue;
cec2f356
SP		 798 if (match_clock &&
799 clock.p != match_clock->p)
800 continue;
1b894b59
CW		 801
802 this_err = abs(clock.dot - target);
d4906093
ML		 803 if (this_err < err_most) {
804 *best_clock = clock;
805 err_most = this_err;
806 max_n = clock.n;
807 found = true;
808 }
809 }
810 }
811 }
812 }
2c07245f
ZW		 813 return found;
814}
815
5eb08b69 816static bool
f2b115e6 817intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
5eb08b69
ZW		 820{
821 struct drm_device *dev = crtc->dev;
822 intel_clock_t clock;
4547668a 823
5eb08b69
ZW		 824 if (target < 200000) {
825 clock.n = 1;
826 clock.p1 = 2;
827 clock.p2 = 10;
828 clock.m1 = 12;
829 clock.m2 = 9;
830 } else {
831 clock.n = 2;
832 clock.p1 = 1;
833 clock.p2 = 10;
834 clock.m1 = 14;
835 clock.m2 = 8;
836 }
837 intel_clock(dev, refclk, &clock);
838 memcpy(best_clock, &clock, sizeof(intel_clock_t));
839 return true;
840}
841
a4fc5ed6
KP		 842/* DisplayPort has only two frequencies, 162MHz and 270MHz */
843static bool
844intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 845 int target, int refclk, intel_clock_t *match_clock,
846 intel_clock_t *best_clock)
a4fc5ed6 847{
5eddb70b
CW		 848 intel_clock_t clock;
849 if (target < 200000) {
850 clock.p1 = 2;
851 clock.p2 = 10;
852 clock.n = 2;
853 clock.m1 = 23;
854 clock.m2 = 8;
855 } else {
856 clock.p1 = 1;
857 clock.p2 = 10;
858 clock.n = 1;
859 clock.m1 = 14;
860 clock.m2 = 2;
861 }
862 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863 clock.p = (clock.p1 * clock.p2);
864 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
865 clock.vco = 0;
866 memcpy(best_clock, &clock, sizeof(intel_clock_t));
867 return true;
a4fc5ed6 868}
a0c4da24
JB		 869static bool
870intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *match_clock,
872 intel_clock_t *best_clock)
873{
874 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
875 u32 m, n, fastclk;
876 u32 updrate, minupdate, fracbits, p;
877 unsigned long bestppm, ppm, absppm;
878 int dotclk, flag;
879
af447bd3 880 flag = 0;
a0c4da24
JB		 881 dotclk = target * 1000;
882 bestppm = 1000000;
883 ppm = absppm = 0;
884 fastclk = dotclk / (2*100);
885 updrate = 0;
886 minupdate = 19200;
887 fracbits = 1;
888 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889 bestm1 = bestm2 = bestp1 = bestp2 = 0;
890
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893 updrate = refclk / n;
894 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
896 if (p2 > 10)
897 p2 = p2 - 1;
898 p = p1 * p2;
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901 m2 = (((2*(fastclk * p * n / m1 )) +
902 refclk) / (2*refclk));
903 m = m1 * m2;
904 vco = updrate * m;
905 if (vco >= limit->vco.min && vco < limit->vco.max) {
906 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907 absppm = (ppm > 0) ? ppm : (-ppm);
908 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
909 bestppm = 0;
910 flag = 1;
911 }
912 if (absppm < bestppm - 10) {
913 bestppm = absppm;
914 flag = 1;
915 }
916 if (flag) {
917 bestn = n;
918 bestm1 = m1;
919 bestm2 = m2;
920 bestp1 = p1;
921 bestp2 = p2;
922 flag = 0;
923 }
924 }
925 }
926 }
927 }
928 }
929 best_clock->n = bestn;
930 best_clock->m1 = bestm1;
931 best_clock->m2 = bestm2;
932 best_clock->p1 = bestp1;
933 best_clock->p2 = bestp2;
934
935 return true;
936}
a4fc5ed6 937
a5c961d1
PZ		 938enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
939 enum pipe pipe)
940{
941 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
943
944 return intel_crtc->cpu_transcoder;
945}
946
a928d536
PZ		 947static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
948{
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 frame, frame_reg = PIPEFRAME(pipe);
951
952 frame = I915_READ(frame_reg);
953
954 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
956}
957
9d0498a2
JB		 958/**
959 * intel_wait_for_vblank - wait for vblank on a given pipe
960 * @dev: drm device
961 * @pipe: pipe to wait for
962 *
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
964 * mode setting code.
965 */
966void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 967{
9d0498a2 968 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 969 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 970
a928d536
PZ		 971 if (INTEL_INFO(dev)->gen >= 5) {
972 ironlake_wait_for_vblank(dev, pipe);
973 return;
974 }
975
300387c0
CW		 976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
978 *
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
985 * vblanks...
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
988 */
989 I915_WRITE(pipestat_reg,
990 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
991
9d0498a2 992 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 993 if (wait_for(I915_READ(pipestat_reg) &
994 PIPE_VBLANK_INTERRUPT_STATUS,
995 50))
9d0498a2
JB		 996 DRM_DEBUG_KMS("vblank wait timed out\n");
997}
998
ab7ad7f6
KP		 999/*
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1001 * @dev: drm device
1002 * @pipe: pipe to wait for
1003 *
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1007 *
ab7ad7f6
KP		 1008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1010 *
1011 * Otherwise:
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
58e10eb9 1014 *
9d0498a2 1015 */
58e10eb9 1016void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1017{
1018 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020 pipe);
ab7ad7f6
KP		 1021
1022 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1023 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1024
1025 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1026 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027 100))
284637d9 1028 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1029 } else {
837ba00f 1030 u32 last_line, line_mask;
58e10eb9 1031 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
837ba00f
PZ		 1034 if (IS_GEN2(dev))
1035 line_mask = DSL_LINEMASK_GEN2;
1036 else
1037 line_mask = DSL_LINEMASK_GEN3;
1038
ab7ad7f6
KP		 1039 /* Wait for the display line to settle */
1040 do {
837ba00f 1041 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1042 mdelay(5);
837ba00f 1043 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1044 time_after(timeout, jiffies));
1045 if (time_after(jiffies, timeout))
284637d9 1046 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1047 }
79e53945
JB		 1048}
1049
b24e7179
JB		 1050static const char *state_string(bool enabled)
1051{
1052 return enabled ? "on" : "off";
1053}
1054
1055/* Only for pre-ILK configs */
1056static void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058{
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069}
1070#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
040484af
JB		 1073/* For ILK+ */
1074static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1075 struct intel_pch_pll *pll,
1076 struct intel_crtc *crtc,
1077 bool state)
040484af 1078{
040484af
JB		 1079 u32 val;
1080 bool cur_state;
1081
9d82aa17
ED		 1082 if (HAS_PCH_LPT(dev_priv->dev)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 return;
1085 }
1086
92b27b08
CW		 1087 if (WARN (!pll,
1088 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1089 return;
ee7b9f93 1090
92b27b08
CW		 1091 val = I915_READ(pll->pll_reg);
1092 cur_state = !!(val & DPLL_VCO_ENABLE);
1093 WARN(cur_state != state,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1099 u32 pch_dpll;
1100
1101 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1102 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state, crtc->pipe, pch_dpll)) {
1106 cur_state = !!(val >> (4*crtc->pipe + 3));
1107 WARN(cur_state != state,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll->pll_reg == _PCH_DPLL_B,
1110 state_string(state),
1111 crtc->pipe,
1112 val);
1113 }
d3ccbe86 1114 }
040484af 1115}
92b27b08
CW		 1116#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1118
1119static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121{
1122 int reg;
1123 u32 val;
1124 bool cur_state;
ad80a810
PZ		 1125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126 pipe);
040484af 1127
bf507ef7
ED		 1128 if (IS_HASWELL(dev_priv->dev)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1130 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1131 val = I915_READ(reg);
ad80a810 1132 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1133 } else {
1134 reg = FDI_TX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147{
1148 int reg;
1149 u32 val;
1150 bool cur_state;
1151
d63fa0dc
PZ		 1152 reg = FDI_RX_CTL(pipe);
1153 val = I915_READ(reg);
1154 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1155 WARN(cur_state != state,
1156 "FDI RX state assertion failure (expected %s, current %s)\n",
1157 state_string(state), state_string(cur_state));
1158}
1159#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161
1162static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164{
1165 int reg;
1166 u32 val;
1167
1168 /* ILK FDI PLL is always enabled */
1169 if (dev_priv->info->gen == 5)
1170 return;
1171
bf507ef7
ED		 1172 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173 if (IS_HASWELL(dev_priv->dev))
1174 return;
1175
040484af
JB		 1176 reg = FDI_TX_CTL(pipe);
1177 val = I915_READ(reg);
1178 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1179}
1180
1181static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe)
1183{
1184 int reg;
1185 u32 val;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1190}
1191
ea0760cf
JB		 1192static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
1194{
1195 int pp_reg, lvds_reg;
1196 u32 val;
1197 enum pipe panel_pipe = PIPE_A;
0de3b485 1198 bool locked = true;
ea0760cf
JB		 1199
1200 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201 pp_reg = PCH_PP_CONTROL;
1202 lvds_reg = PCH_LVDS;
1203 } else {
1204 pp_reg = PP_CONTROL;
1205 lvds_reg = LVDS;
1206 }
1207
1208 val = I915_READ(pp_reg);
1209 if (!(val & PANEL_POWER_ON) ||
1210 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211 locked = false;
1212
1213 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214 panel_pipe = PIPE_B;
1215
1216 WARN(panel_pipe == pipe && locked,
1217 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1218 pipe_name(pipe));
ea0760cf
JB		 1219}
1220
b840d907
JB		 1221void assert_pipe(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
b24e7179
JB		 1223{
1224 int reg;
1225 u32 val;
63d7bbe9 1226 bool cur_state;
702e7a56
PZ		 1227 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228 pipe);
b24e7179 1229
8e636784
DV		 1230 /* if we need the pipe A quirk it must be always on */
1231 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1232 state = true;
1233
702e7a56 1234 reg = PIPECONF(cpu_transcoder);
b24e7179 1235 val = I915_READ(reg);
63d7bbe9
JB		 1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 WARN(cur_state != state,
1238 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1239 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1240}
1241
931872fc
CW		 1242static void assert_plane(struct drm_i915_private *dev_priv,
1243 enum plane plane, bool state)
b24e7179
JB		 1244{
1245 int reg;
1246 u32 val;
931872fc 1247 bool cur_state;
b24e7179
JB		 1248
1249 reg = DSPCNTR(plane);
1250 val = I915_READ(reg);
931872fc
CW		 1251 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252 WARN(cur_state != state,
1253 "plane %c assertion failure (expected %s, current %s)\n",
1254 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1255}
1256
931872fc
CW		 1257#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1259
b24e7179
JB		 1260static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1261 enum pipe pipe)
1262{
1263 int reg, i;
1264 u32 val;
1265 int cur_pipe;
1266
19ec1358 1267 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1268 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269 reg = DSPCNTR(pipe);
1270 val = I915_READ(reg);
1271 WARN((val & DISPLAY_PLANE_ENABLE),
1272 "plane %c assertion failure, should be disabled but not\n",
1273 plane_name(pipe));
19ec1358 1274 return;
28c05794 1275 }
19ec1358 1276
b24e7179
JB		 1277 /* Need to check both planes against the pipe */
1278 for (i = 0; i < 2; i++) {
1279 reg = DSPCNTR(i);
1280 val = I915_READ(reg);
1281 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282 DISPPLANE_SEL_PIPE_SHIFT;
1283 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1284 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1286 }
1287}
1288
92f2584a
JB		 1289static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1290{
1291 u32 val;
1292 bool enabled;
1293
9d82aa17
ED		 1294 if (HAS_PCH_LPT(dev_priv->dev)) {
1295 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1296 return;
1297 }
1298
92f2584a
JB		 1299 val = I915_READ(PCH_DREF_CONTROL);
1300 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301 DREF_SUPERSPREAD_SOURCE_MASK));
1302 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1303}
1304
1305static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1306 enum pipe pipe)
1307{
1308 int reg;
1309 u32 val;
1310 bool enabled;
1311
1312 reg = TRANSCONF(pipe);
1313 val = I915_READ(reg);
1314 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1315 WARN(enabled,
1316 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1317 pipe_name(pipe));
92f2584a
JB		 1318}
1319
4e634389
KP		 1320static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1322{
1323 if ((val & DP_PORT_EN) == 0)
1324 return false;
1325
1326 if (HAS_PCH_CPT(dev_priv->dev)) {
1327 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1330 return false;
1331 } else {
1332 if ((val & DP_PIPE_MASK) != (pipe << 30))
1333 return false;
1334 }
1335 return true;
1336}
1337
1519b995
KP		 1338static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe, u32 val)
1340{
1341 if ((val & PORT_ENABLE) == 0)
1342 return false;
1343
1344 if (HAS_PCH_CPT(dev_priv->dev)) {
1345 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1346 return false;
1347 } else {
1348 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1349 return false;
1350 }
1351 return true;
1352}
1353
1354static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe, u32 val)
1356{
1357 if ((val & LVDS_PORT_EN) == 0)
1358 return false;
1359
1360 if (HAS_PCH_CPT(dev_priv->dev)) {
1361 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1362 return false;
1363 } else {
1364 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1365 return false;
1366 }
1367 return true;
1368}
1369
1370static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 val)
1372{
1373 if ((val & ADPA_DAC_ENABLE) == 0)
1374 return false;
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377 return false;
1378 } else {
1379 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1380 return false;
1381 }
1382 return true;
1383}
1384
291906f1 1385static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1386 enum pipe pipe, int reg, u32 port_sel)
291906f1 1387{
47a05eca 1388 u32 val = I915_READ(reg);
4e634389 1389 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1390 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1391 reg, pipe_name(pipe));
de9a35ab 1392
75c5da27
DV		 1393 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394 && (val & DP_PIPEB_SELECT),
de9a35ab 1395 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1396}
1397
1398static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe, int reg)
1400{
47a05eca 1401 u32 val = I915_READ(reg);
b70ad586 1402 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1403 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1404 reg, pipe_name(pipe));
de9a35ab 1405
75c5da27
DV		 1406 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1408 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1409}
1410
1411static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413{
1414 int reg;
1415 u32 val;
291906f1 1416
f0575e92
KP		 1417 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1420
1421 reg = PCH_ADPA;
1422 val = I915_READ(reg);
b70ad586 1423 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1424 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1425 pipe_name(pipe));
291906f1
JB		 1426
1427 reg = PCH_LVDS;
1428 val = I915_READ(reg);
b70ad586 1429 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1430 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1431 pipe_name(pipe));
291906f1
JB		 1432
1433 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1436}
1437
63d7bbe9
JB		 1438/**
1439 * intel_enable_pll - enable a PLL
1440 * @dev_priv: i915 private structure
1441 * @pipe: pipe PLL to enable
1442 *
1443 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1444 * make sure the PLL reg is writable first though, since the panel write
1445 * protect mechanism may be enabled.
1446 *
1447 * Note! This is for pre-ILK only.
7434a255
TR		 1448 *
1449 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1450 */
1451static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1452{
1453 int reg;
1454 u32 val;
1455
1456 /* No really, not for ILK+ */
a0c4da24 1457 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1458
1459 /* PLL is protected by panel, make sure we can write it */
1460 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461 assert_panel_unlocked(dev_priv, pipe);
1462
1463 reg = DPLL(pipe);
1464 val = I915_READ(reg);
1465 val |= DPLL_VCO_ENABLE;
1466
1467 /* We do this three times for luck */
1468 I915_WRITE(reg, val);
1469 POSTING_READ(reg);
1470 udelay(150); /* wait for warmup */
1471 I915_WRITE(reg, val);
1472 POSTING_READ(reg);
1473 udelay(150); /* wait for warmup */
1474 I915_WRITE(reg, val);
1475 POSTING_READ(reg);
1476 udelay(150); /* wait for warmup */
1477}
1478
1479/**
1480 * intel_disable_pll - disable a PLL
1481 * @dev_priv: i915 private structure
1482 * @pipe: pipe PLL to disable
1483 *
1484 * Disable the PLL for @pipe, making sure the pipe is off first.
1485 *
1486 * Note! This is for pre-ILK only.
1487 */
1488static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1489{
1490 int reg;
1491 u32 val;
1492
1493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495 return;
1496
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv, pipe);
1499
1500 reg = DPLL(pipe);
1501 val = I915_READ(reg);
1502 val &= ~DPLL_VCO_ENABLE;
1503 I915_WRITE(reg, val);
1504 POSTING_READ(reg);
1505}
1506
a416edef
ED		 1507/* SBI access */
1508static void
1509intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1510{
1511 unsigned long flags;
1512
1513 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1514 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1515 100)) {
1516 DRM_ERROR("timeout waiting for SBI to become ready\n");
1517 goto out_unlock;
1518 }
1519
1520 I915_WRITE(SBI_ADDR,
1521 (reg << 16));
1522 I915_WRITE(SBI_DATA,
1523 value);
1524 I915_WRITE(SBI_CTL_STAT,
1525 SBI_BUSY |
1526 SBI_CTL_OP_CRWR);
1527
39fb50f6 1528 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1529 100)) {
1530 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1531 goto out_unlock;
1532 }
1533
1534out_unlock:
1535 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1536}
1537
1538static u32
1539intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1540{
1541 unsigned long flags;
39fb50f6 1542 u32 value = 0;
a416edef
ED		 1543
1544 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1545 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1546 100)) {
1547 DRM_ERROR("timeout waiting for SBI to become ready\n");
1548 goto out_unlock;
1549 }
1550
1551 I915_WRITE(SBI_ADDR,
1552 (reg << 16));
1553 I915_WRITE(SBI_CTL_STAT,
1554 SBI_BUSY |
1555 SBI_CTL_OP_CRRD);
1556
39fb50f6 1557 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1558 100)) {
1559 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1560 goto out_unlock;
1561 }
1562
1563 value = I915_READ(SBI_DATA);
1564
1565out_unlock:
1566 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1567 return value;
1568}
1569
92f2584a 1570/**
b6b4e185 1571 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1574 *
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1577 */
b6b4e185 1578static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1579{
ee7b9f93 1580 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1581 struct intel_pch_pll *pll;
92f2584a
JB		 1582 int reg;
1583 u32 val;
1584
48da64a8 1585 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1586 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1587 pll = intel_crtc->pch_pll;
1588 if (pll == NULL)
1589 return;
1590
1591 if (WARN_ON(pll->refcount == 0))
1592 return;
ee7b9f93
JB		 1593
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll->pll_reg, pll->active, pll->on,
1596 intel_crtc->base.base.id);
92f2584a
JB		 1597
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv);
1600
ee7b9f93 1601 if (pll->active++ && pll->on) {
92b27b08 1602 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1603 return;
1604 }
1605
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608 reg = pll->pll_reg;
92f2584a
JB		 1609 val = I915_READ(reg);
1610 val |= DPLL_VCO_ENABLE;
1611 I915_WRITE(reg, val);
1612 POSTING_READ(reg);
1613 udelay(200);
ee7b9f93
JB		 1614
1615 pll->on = true;
92f2584a
JB		 1616}
1617
ee7b9f93 1618static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1619{
ee7b9f93
JB		 1620 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1622 int reg;
ee7b9f93 1623 u32 val;
4c609cb8 1624
92f2584a
JB		 1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1627 if (pll == NULL)
1628 return;
92f2584a 1629
48da64a8
CW		 1630 if (WARN_ON(pll->refcount == 0))
1631 return;
7a419866 1632
ee7b9f93
JB		 1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll->pll_reg, pll->active, pll->on,
1635 intel_crtc->base.base.id);
7a419866 1636
48da64a8 1637 if (WARN_ON(pll->active == 0)) {
92b27b08 1638 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1639 return;
1640 }
1641
ee7b9f93 1642 if (--pll->active) {
92b27b08 1643 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1644 return;
ee7b9f93
JB		 1645 }
1646
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1651
ee7b9f93 1652 reg = pll->pll_reg;
92f2584a
JB		 1653 val = I915_READ(reg);
1654 val &= ~DPLL_VCO_ENABLE;
1655 I915_WRITE(reg, val);
1656 POSTING_READ(reg);
1657 udelay(200);
ee7b9f93
JB		 1658
1659 pll->on = false;
92f2584a
JB		 1660}
1661
b8a4f404
PZ		 1662static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
040484af 1664{
23670b32 1665 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1666 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1667 uint32_t reg, val, pipeconf_val;
040484af
JB		 1668
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv->info->gen < 5);
1671
1672 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1673 assert_pch_pll_enabled(dev_priv,
1674 to_intel_crtc(crtc)->pch_pll,
1675 to_intel_crtc(crtc));
040484af
JB		 1676
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv, pipe);
1679 assert_fdi_rx_enabled(dev_priv, pipe);
1680
23670b32
DV		 1681 if (HAS_PCH_CPT(dev)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
59c859d6 1688 }
23670b32 1689
040484af
JB		 1690 reg = TRANSCONF(pipe);
1691 val = I915_READ(reg);
5f7f726d 1692 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1693
1694 if (HAS_PCH_IBX(dev_priv->dev)) {
1695 /*
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1698 */
1699 val &= ~PIPE_BPC_MASK;
5f7f726d 1700 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1701 }
5f7f726d
PZ		 1702
1703 val &= ~TRANS_INTERLACE_MASK;
1704 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1705 if (HAS_PCH_IBX(dev_priv->dev) &&
1706 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707 val |= TRANS_LEGACY_INTERLACED_ILK;
1708 else
1709 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1710 else
1711 val |= TRANS_PROGRESSIVE;
1712
040484af
JB		 1713 I915_WRITE(reg, val | TRANS_ENABLE);
1714 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716}
1717
8fb033d7 1718static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1719 enum transcoder cpu_transcoder)
040484af 1720{
8fb033d7 1721 u32 val, pipeconf_val;
8fb033d7
PZ		 1722
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv->info->gen < 5);
1725
8fb033d7 1726 /* FDI must be feeding us bits for PCH ports */
937bb610
PZ		 1727 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1728 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1729
223a6fdf
PZ		 1730 /* Workaround: set timing override bit. */
1731 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1732 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1733 I915_WRITE(_TRANSA_CHICKEN2, val);
1734
25f3ef11 1735 val = TRANS_ENABLE;
937bb610 1736 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1737
9a76b1c6
PZ		 1738 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739 PIPECONF_INTERLACED_ILK)
a35f2679 1740 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1741 else
1742 val |= TRANS_PROGRESSIVE;
1743
25f3ef11 1744 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1745 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1747}
1748
b8a4f404
PZ		 1749static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750 enum pipe pipe)
040484af 1751{
23670b32
DV		 1752 struct drm_device *dev = dev_priv->dev;
1753 uint32_t reg, val;
040484af
JB		 1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe);
1757 assert_fdi_rx_disabled(dev_priv, pipe);
1758
291906f1
JB		 1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
040484af
JB		 1762 reg = TRANSCONF(pipe);
1763 val = I915_READ(reg);
1764 val &= ~TRANS_ENABLE;
1765 I915_WRITE(reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1768 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1769
1770 if (!HAS_PCH_IBX(dev)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg = TRANS_CHICKEN2(pipe);
1773 val = I915_READ(reg);
1774 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775 I915_WRITE(reg, val);
1776 }
040484af
JB		 1777}
1778
ab4d966c 1779static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1780{
8fb033d7
PZ		 1781 u32 val;
1782
8a52fd9f 1783 val = I915_READ(_TRANSACONF);
8fb033d7 1784 val &= ~TRANS_ENABLE;
8a52fd9f 1785 I915_WRITE(_TRANSACONF, val);
8fb033d7 1786 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1787 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1789
1790 /* Workaround: clear timing override bit. */
1791 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1792 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1793 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1794}
1795
b24e7179 1796/**
309cfea8 1797 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
040484af 1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1801 *
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1808 * returning.
1809 */
040484af
JB		 1810static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811 bool pch_port)
b24e7179 1812{
702e7a56
PZ		 1813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814 pipe);
cc391bbb 1815 enum transcoder pch_transcoder;
b24e7179
JB		 1816 int reg;
1817 u32 val;
1818
cc391bbb
PZ		 1819 if (IS_HASWELL(dev_priv->dev))
1820 pch_transcoder = TRANSCODER_A;
1821 else
1822 pch_transcoder = pipe;
1823
b24e7179
JB		 1824 /*
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1827 * need the check.
1828 */
1829 if (!HAS_PCH_SPLIT(dev_priv->dev))
1830 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1831 else {
1832 if (pch_port) {
1833 /* if driving the PCH, we need FDI enabled */
cc391bbb
PZ		 1834 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1835 assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
040484af
JB		 1836 }
1837 /* FIXME: assert CPU port conditions for SNB+ */
1838 }
b24e7179 1839
702e7a56 1840 reg = PIPECONF(cpu_transcoder);
b24e7179 1841 val = I915_READ(reg);
00d70b15
CW		 1842 if (val & PIPECONF_ENABLE)
1843 return;
1844
1845 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1846 intel_wait_for_vblank(dev_priv->dev, pipe);
1847}
1848
1849/**
309cfea8 1850 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1851 * @dev_priv: i915 private structure
1852 * @pipe: pipe to disable
1853 *
1854 * Disable @pipe, making sure that various hardware specific requirements
1855 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1856 *
1857 * @pipe should be %PIPE_A or %PIPE_B.
1858 *
1859 * Will wait until the pipe has shut down before returning.
1860 */
1861static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1862 enum pipe pipe)
1863{
702e7a56
PZ		 1864 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1865 pipe);
b24e7179
JB		 1866 int reg;
1867 u32 val;
1868
1869 /*
1870 * Make sure planes won't keep trying to pump pixels to us,
1871 * or we might hang the display.
1872 */
1873 assert_planes_disabled(dev_priv, pipe);
1874
1875 /* Don't disable pipe A or pipe A PLLs if needed */
1876 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1877 return;
1878
702e7a56 1879 reg = PIPECONF(cpu_transcoder);
b24e7179 1880 val = I915_READ(reg);
00d70b15
CW		 1881 if ((val & PIPECONF_ENABLE) == 0)
1882 return;
1883
1884 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1885 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1886}
1887
d74362c9
KP		 1888/*
1889 * Plane regs are double buffered, going from enabled->disabled needs a
1890 * trigger in order to latch. The display address reg provides this.
1891 */
6f1d69b0 1892void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1893 enum plane plane)
1894{
14f86147
DL		 1895 if (dev_priv->info->gen >= 4)
1896 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1897 else
1898 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1899}
1900
b24e7179
JB		 1901/**
1902 * intel_enable_plane - enable a display plane on a given pipe
1903 * @dev_priv: i915 private structure
1904 * @plane: plane to enable
1905 * @pipe: pipe being fed
1906 *
1907 * Enable @plane on @pipe, making sure that @pipe is running first.
1908 */
1909static void intel_enable_plane(struct drm_i915_private *dev_priv,
1910 enum plane plane, enum pipe pipe)
1911{
1912 int reg;
1913 u32 val;
1914
1915 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1916 assert_pipe_enabled(dev_priv, pipe);
1917
1918 reg = DSPCNTR(plane);
1919 val = I915_READ(reg);
00d70b15
CW		 1920 if (val & DISPLAY_PLANE_ENABLE)
1921 return;
1922
1923 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1924 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1925 intel_wait_for_vblank(dev_priv->dev, pipe);
1926}
1927
b24e7179
JB		 1928/**
1929 * intel_disable_plane - disable a display plane
1930 * @dev_priv: i915 private structure
1931 * @plane: plane to disable
1932 * @pipe: pipe consuming the data
1933 *
1934 * Disable @plane; should be an independent operation.
1935 */
1936static void intel_disable_plane(struct drm_i915_private *dev_priv,
1937 enum plane plane, enum pipe pipe)
1938{
1939 int reg;
1940 u32 val;
1941
1942 reg = DSPCNTR(plane);
1943 val = I915_READ(reg);
00d70b15
CW		 1944 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1945 return;
1946
1947 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1948 intel_flush_display_plane(dev_priv, plane);
1949 intel_wait_for_vblank(dev_priv->dev, pipe);
1950}
1951
127bd2ac 1952int
48b956c5 1953intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1954 struct drm_i915_gem_object *obj,
919926ae 1955 struct intel_ring_buffer *pipelined)
6b95a207 1956{
ce453d81 1957 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1958 u32 alignment;
1959 int ret;
1960
05394f39 1961 switch (obj->tiling_mode) {
6b95a207 1962 case I915_TILING_NONE:
534843da
CW		 1963 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1964 alignment = 128 * 1024;
a6c45cf0 1965 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1966 alignment = 4 * 1024;
1967 else
1968 alignment = 64 * 1024;
6b95a207
KH		 1969 break;
1970 case I915_TILING_X:
1971 /* pin() will align the object as required by fence */
1972 alignment = 0;
1973 break;
1974 case I915_TILING_Y:
1975 /* FIXME: Is this true? */
1976 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1977 return -EINVAL;
1978 default:
1979 BUG();
1980 }
1981
ce453d81 1982 dev_priv->mm.interruptible = false;
2da3b9b9 1983 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1984 if (ret)
ce453d81 1985 goto err_interruptible;
6b95a207
KH		 1986
1987 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1988 * fence, whereas 965+ only requires a fence if using
1989 * framebuffer compression. For simplicity, we always install
1990 * a fence as the cost is not that onerous.
1991 */
06d98131 1992 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1993 if (ret)
1994 goto err_unpin;
1690e1eb 1995
9a5a53b3 1996 i915_gem_object_pin_fence(obj);
6b95a207 1997
ce453d81 1998 dev_priv->mm.interruptible = true;
6b95a207 1999 return 0;
48b956c5
CW		 2000
2001err_unpin:
2002 i915_gem_object_unpin(obj);
ce453d81
CW		 2003err_interruptible:
2004 dev_priv->mm.interruptible = true;
48b956c5 2005 return ret;
6b95a207
KH		 2006}
2007
1690e1eb
CW		 2008void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2009{
2010 i915_gem_object_unpin_fence(obj);
2011 i915_gem_object_unpin(obj);
2012}
2013
c2c75131
DV		 2014/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2015 * is assumed to be a power-of-two. */
5a35e99e
DL		 2016unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2017 unsigned int bpp,
2018 unsigned int pitch)
c2c75131
DV		 2019{
2020 int tile_rows, tiles;
2021
2022 tile_rows = *y / 8;
2023 *y %= 8;
2024 tiles = *x / (512/bpp);
2025 *x %= 512/bpp;
2026
2027 return tile_rows * pitch * 8 + tiles * 4096;
2028}
2029
17638cd6
JB		 2030static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2031 int x, int y)
81255565
JB		 2032{
2033 struct drm_device *dev = crtc->dev;
2034 struct drm_i915_private *dev_priv = dev->dev_private;
2035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2036 struct intel_framebuffer *intel_fb;
05394f39 2037 struct drm_i915_gem_object *obj;
81255565 2038 int plane = intel_crtc->plane;
e506a0c6 2039 unsigned long linear_offset;
81255565 2040 u32 dspcntr;
5eddb70b 2041 u32 reg;
81255565
JB		 2042
2043 switch (plane) {
2044 case 0:
2045 case 1:
2046 break;
2047 default:
2048 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2049 return -EINVAL;
2050 }
2051
2052 intel_fb = to_intel_framebuffer(fb);
2053 obj = intel_fb->obj;
81255565 2054
5eddb70b
CW		 2055 reg = DSPCNTR(plane);
2056 dspcntr = I915_READ(reg);
81255565
JB		 2057 /* Mask out pixel format bits in case we change it */
2058 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2059 switch (fb->pixel_format) {
2060 case DRM_FORMAT_C8:
81255565
JB		 2061 dspcntr |= DISPPLANE_8BPP;
2062 break;
57779d06
VS		 2063 case DRM_FORMAT_XRGB1555:
2064 case DRM_FORMAT_ARGB1555:
2065 dspcntr |= DISPPLANE_BGRX555;
81255565 2066 break;
57779d06
VS		 2067 case DRM_FORMAT_RGB565:
2068 dspcntr |= DISPPLANE_BGRX565;
2069 break;
2070 case DRM_FORMAT_XRGB8888:
2071 case DRM_FORMAT_ARGB8888:
2072 dspcntr |= DISPPLANE_BGRX888;
2073 break;
2074 case DRM_FORMAT_XBGR8888:
2075 case DRM_FORMAT_ABGR8888:
2076 dspcntr |= DISPPLANE_RGBX888;
2077 break;
2078 case DRM_FORMAT_XRGB2101010:
2079 case DRM_FORMAT_ARGB2101010:
2080 dspcntr |= DISPPLANE_BGRX101010;
2081 break;
2082 case DRM_FORMAT_XBGR2101010:
2083 case DRM_FORMAT_ABGR2101010:
2084 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2085 break;
2086 default:
57779d06 2087 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2088 return -EINVAL;
2089 }
57779d06 2090
a6c45cf0 2091 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2092 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2093 dspcntr |= DISPPLANE_TILED;
2094 else
2095 dspcntr &= ~DISPPLANE_TILED;
2096 }
2097
5eddb70b 2098 I915_WRITE(reg, dspcntr);
81255565 2099
e506a0c6 2100 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2101
c2c75131
DV		 2102 if (INTEL_INFO(dev)->gen >= 4) {
2103 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2104 intel_gen4_compute_offset_xtiled(&x, &y,
2105 fb->bits_per_pixel / 8,
2106 fb->pitches[0]);
c2c75131
DV		 2107 linear_offset -= intel_crtc->dspaddr_offset;
2108 } else {
e506a0c6 2109 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2110 }
e506a0c6
DV		 2111
2112 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2113 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2114 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2115 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2116 I915_MODIFY_DISPBASE(DSPSURF(plane),
2117 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2118 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2119 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2120 } else
e506a0c6 2121 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2122 POSTING_READ(reg);
81255565 2123
17638cd6
JB		 2124 return 0;
2125}
2126
2127static int ironlake_update_plane(struct drm_crtc *crtc,
2128 struct drm_framebuffer *fb, int x, int y)
2129{
2130 struct drm_device *dev = crtc->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133 struct intel_framebuffer *intel_fb;
2134 struct drm_i915_gem_object *obj;
2135 int plane = intel_crtc->plane;
e506a0c6 2136 unsigned long linear_offset;
17638cd6
JB		 2137 u32 dspcntr;
2138 u32 reg;
2139
2140 switch (plane) {
2141 case 0:
2142 case 1:
27f8227b 2143 case 2:
17638cd6
JB		 2144 break;
2145 default:
2146 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2147 return -EINVAL;
2148 }
2149
2150 intel_fb = to_intel_framebuffer(fb);
2151 obj = intel_fb->obj;
2152
2153 reg = DSPCNTR(plane);
2154 dspcntr = I915_READ(reg);
2155 /* Mask out pixel format bits in case we change it */
2156 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2157 switch (fb->pixel_format) {
2158 case DRM_FORMAT_C8:
17638cd6
JB		 2159 dspcntr |= DISPPLANE_8BPP;
2160 break;
57779d06
VS		 2161 case DRM_FORMAT_RGB565:
2162 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2163 break;
57779d06
VS		 2164 case DRM_FORMAT_XRGB8888:
2165 case DRM_FORMAT_ARGB8888:
2166 dspcntr |= DISPPLANE_BGRX888;
2167 break;
2168 case DRM_FORMAT_XBGR8888:
2169 case DRM_FORMAT_ABGR8888:
2170 dspcntr |= DISPPLANE_RGBX888;
2171 break;
2172 case DRM_FORMAT_XRGB2101010:
2173 case DRM_FORMAT_ARGB2101010:
2174 dspcntr |= DISPPLANE_BGRX101010;
2175 break;
2176 case DRM_FORMAT_XBGR2101010:
2177 case DRM_FORMAT_ABGR2101010:
2178 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2179 break;
2180 default:
57779d06 2181 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2182 return -EINVAL;
2183 }
2184
2185 if (obj->tiling_mode != I915_TILING_NONE)
2186 dspcntr |= DISPPLANE_TILED;
2187 else
2188 dspcntr &= ~DISPPLANE_TILED;
2189
2190 /* must disable */
2191 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2192
2193 I915_WRITE(reg, dspcntr);
2194
e506a0c6 2195 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2196 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2197 intel_gen4_compute_offset_xtiled(&x, &y,
2198 fb->bits_per_pixel / 8,
2199 fb->pitches[0]);
c2c75131 2200 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2201
e506a0c6
DV		 2202 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2203 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2204 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2205 I915_MODIFY_DISPBASE(DSPSURF(plane),
2206 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2207 if (IS_HASWELL(dev)) {
2208 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2209 } else {
2210 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2211 I915_WRITE(DSPLINOFF(plane), linear_offset);
2212 }
17638cd6
JB		 2213 POSTING_READ(reg);
2214
2215 return 0;
2216}
2217
2218/* Assume fb object is pinned & idle & fenced and just update base pointers */
2219static int
2220intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2221 int x, int y, enum mode_set_atomic state)
2222{
2223 struct drm_device *dev = crtc->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2225
6b8e6ed0
CW		 2226 if (dev_priv->display.disable_fbc)
2227 dev_priv->display.disable_fbc(dev);
3dec0095 2228 intel_increase_pllclock(crtc);
81255565 2229
6b8e6ed0 2230 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2231}
2232
14667a4b
CW		 2233static int
2234intel_finish_fb(struct drm_framebuffer *old_fb)
2235{
2236 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2237 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2238 bool was_interruptible = dev_priv->mm.interruptible;
2239 int ret;
2240
2241 wait_event(dev_priv->pending_flip_queue,
2242 atomic_read(&dev_priv->mm.wedged) ||
2243 atomic_read(&obj->pending_flip) == 0);
2244
2245 /* Big Hammer, we also need to ensure that any pending
2246 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2247 * current scanout is retired before unpinning the old
2248 * framebuffer.
2249 *
2250 * This should only fail upon a hung GPU, in which case we
2251 * can safely continue.
2252 */
2253 dev_priv->mm.interruptible = false;
2254 ret = i915_gem_object_finish_gpu(obj);
2255 dev_priv->mm.interruptible = was_interruptible;
2256
2257 return ret;
2258}
2259
198598d0
VS		 2260static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2261{
2262 struct drm_device *dev = crtc->dev;
2263 struct drm_i915_master_private *master_priv;
2264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265
2266 if (!dev->primary->master)
2267 return;
2268
2269 master_priv = dev->primary->master->driver_priv;
2270 if (!master_priv->sarea_priv)
2271 return;
2272
2273 switch (intel_crtc->pipe) {
2274 case 0:
2275 master_priv->sarea_priv->pipeA_x = x;
2276 master_priv->sarea_priv->pipeA_y = y;
2277 break;
2278 case 1:
2279 master_priv->sarea_priv->pipeB_x = x;
2280 master_priv->sarea_priv->pipeB_y = y;
2281 break;
2282 default:
2283 break;
2284 }
2285}
2286
5c3b82e2 2287static int
3c4fdcfb 2288intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2289 struct drm_framebuffer *fb)
79e53945
JB		 2290{
2291 struct drm_device *dev = crtc->dev;
6b8e6ed0 2292 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2294 struct drm_framebuffer *old_fb;
5c3b82e2 2295 int ret;
79e53945
JB		 2296
2297 /* no fb bound */
94352cf9 2298 if (!fb) {
a5071c2f 2299 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2300 return 0;
2301 }
2302
5826eca5
ED		 2303 if(intel_crtc->plane > dev_priv->num_pipe) {
2304 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2305 intel_crtc->plane,
2306 dev_priv->num_pipe);
5c3b82e2 2307 return -EINVAL;
79e53945
JB		 2308 }
2309
5c3b82e2 2310 mutex_lock(&dev->struct_mutex);
265db958 2311 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2312 to_intel_framebuffer(fb)->obj,
919926ae 2313 NULL);
5c3b82e2
CW		 2314 if (ret != 0) {
2315 mutex_unlock(&dev->struct_mutex);
a5071c2f 2316 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2317 return ret;
2318 }
79e53945 2319
94352cf9
DV		 2320 if (crtc->fb)
2321 intel_finish_fb(crtc->fb);
265db958 2322
94352cf9 2323 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2324 if (ret) {
94352cf9 2325 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2326 mutex_unlock(&dev->struct_mutex);
a5071c2f 2327 DRM_ERROR("failed to update base address\n");
4e6cfefc 2328 return ret;
79e53945 2329 }
3c4fdcfb 2330
94352cf9
DV		 2331 old_fb = crtc->fb;
2332 crtc->fb = fb;
6c4c86f5
DV		 2333 crtc->x = x;
2334 crtc->y = y;
94352cf9 2335
b7f1de28
CW		 2336 if (old_fb) {
2337 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2338 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2339 }
652c393a 2340
6b8e6ed0 2341 intel_update_fbc(dev);
5c3b82e2 2342 mutex_unlock(&dev->struct_mutex);
79e53945 2343
198598d0 2344 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2345
2346 return 0;
79e53945
JB		 2347}
2348
5eddb70b 2349static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2350{
2351 struct drm_device *dev = crtc->dev;
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 dpa_ctl;
2354
28c97730 2355 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2356 dpa_ctl = I915_READ(DP_A);
2357 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2358
2359 if (clock < 200000) {
2360 u32 temp;
2361 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2362 /* workaround for 160Mhz:
2363 1) program 0x4600c bits 15:0 = 0x8124
2364 2) program 0x46010 bit 0 = 1
2365 3) program 0x46034 bit 24 = 1
2366 4) program 0x64000 bit 14 = 1
2367 */
2368 temp = I915_READ(0x4600c);
2369 temp &= 0xffff0000;
2370 I915_WRITE(0x4600c, temp | 0x8124);
2371
2372 temp = I915_READ(0x46010);
2373 I915_WRITE(0x46010, temp | 1);
2374
2375 temp = I915_READ(0x46034);
2376 I915_WRITE(0x46034, temp | (1 << 24));
2377 } else {
2378 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2379 }
2380 I915_WRITE(DP_A, dpa_ctl);
2381
5eddb70b 2382 POSTING_READ(DP_A);
32f9d658
ZW		 2383 udelay(500);
2384}
2385
5e84e1a4
ZW		 2386static void intel_fdi_normal_train(struct drm_crtc *crtc)
2387{
2388 struct drm_device *dev = crtc->dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391 int pipe = intel_crtc->pipe;
2392 u32 reg, temp;
2393
2394 /* enable normal train */
2395 reg = FDI_TX_CTL(pipe);
2396 temp = I915_READ(reg);
61e499bf 2397 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2398 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2399 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2400 } else {
2401 temp &= ~FDI_LINK_TRAIN_NONE;
2402 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2403 }
5e84e1a4
ZW		 2404 I915_WRITE(reg, temp);
2405
2406 reg = FDI_RX_CTL(pipe);
2407 temp = I915_READ(reg);
2408 if (HAS_PCH_CPT(dev)) {
2409 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2410 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2411 } else {
2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_NONE;
2414 }
2415 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2416
2417 /* wait one idle pattern time */
2418 POSTING_READ(reg);
2419 udelay(1000);
357555c0
JB		 2420
2421 /* IVB wants error correction enabled */
2422 if (IS_IVYBRIDGE(dev))
2423 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2424 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2425}
2426
291427f5
JB		 2427static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2428{
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 u32 flags = I915_READ(SOUTH_CHICKEN1);
2431
2432 flags |= FDI_PHASE_SYNC_OVR(pipe);
2433 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2434 flags |= FDI_PHASE_SYNC_EN(pipe);
2435 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2436 POSTING_READ(SOUTH_CHICKEN1);
2437}
2438
01a415fd
DV		 2439static void ivb_modeset_global_resources(struct drm_device *dev)
2440{
2441 struct drm_i915_private *dev_priv = dev->dev_private;
2442 struct intel_crtc *pipe_B_crtc =
2443 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2444 struct intel_crtc *pipe_C_crtc =
2445 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2446 uint32_t temp;
2447
2448 /* When everything is off disable fdi C so that we could enable fdi B
2449 * with all lanes. XXX: This misses the case where a pipe is not using
2450 * any pch resources and so doesn't need any fdi lanes. */
2451 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2452 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2453 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2454
2455 temp = I915_READ(SOUTH_CHICKEN1);
2456 temp &= ~FDI_BC_BIFURCATION_SELECT;
2457 DRM_DEBUG_KMS("disabling fdi C rx\n");
2458 I915_WRITE(SOUTH_CHICKEN1, temp);
2459 }
2460}
2461
8db9d77b
ZW		 2462/* The FDI link training functions for ILK/Ibexpeak. */
2463static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2464{
2465 struct drm_device *dev = crtc->dev;
2466 struct drm_i915_private *dev_priv = dev->dev_private;
2467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468 int pipe = intel_crtc->pipe;
0fc932b8 2469 int plane = intel_crtc->plane;
5eddb70b 2470 u32 reg, temp, tries;
8db9d77b 2471
0fc932b8
JB		 2472 /* FDI needs bits from pipe & plane first */
2473 assert_pipe_enabled(dev_priv, pipe);
2474 assert_plane_enabled(dev_priv, plane);
2475
e1a44743
AJ		 2476 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2477 for train result */
5eddb70b
CW		 2478 reg = FDI_RX_IMR(pipe);
2479 temp = I915_READ(reg);
e1a44743
AJ		 2480 temp &= ~FDI_RX_SYMBOL_LOCK;
2481 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2482 I915_WRITE(reg, temp);
2483 I915_READ(reg);
e1a44743
AJ		 2484 udelay(150);
2485
8db9d77b 2486 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
77ffb597
AJ		 2489 temp &= ~(7 << 19);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2493 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2494
5eddb70b
CW		 2495 reg = FDI_RX_CTL(pipe);
2496 temp = I915_READ(reg);
8db9d77b
ZW		 2497 temp &= ~FDI_LINK_TRAIN_NONE;
2498 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2499 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2500
2501 POSTING_READ(reg);
8db9d77b
ZW		 2502 udelay(150);
2503
5b2adf89 2504 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2505 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2506 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2507 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2508
5eddb70b 2509 reg = FDI_RX_IIR(pipe);
e1a44743 2510 for (tries = 0; tries < 5; tries++) {
5eddb70b 2511 temp = I915_READ(reg);
8db9d77b
ZW		 2512 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513
2514 if ((temp & FDI_RX_BIT_LOCK)) {
2515 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2516 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2517 break;
2518 }
8db9d77b 2519 }
e1a44743 2520 if (tries == 5)
5eddb70b 2521 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2522
2523 /* Train 2 */
5eddb70b
CW		 2524 reg = FDI_TX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2528 I915_WRITE(reg, temp);
8db9d77b 2529
5eddb70b
CW		 2530 reg = FDI_RX_CTL(pipe);
2531 temp = I915_READ(reg);
8db9d77b
ZW		 2532 temp &= ~FDI_LINK_TRAIN_NONE;
2533 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2534 I915_WRITE(reg, temp);
8db9d77b 2535
5eddb70b
CW		 2536 POSTING_READ(reg);
2537 udelay(150);
8db9d77b 2538
5eddb70b 2539 reg = FDI_RX_IIR(pipe);
e1a44743 2540 for (tries = 0; tries < 5; tries++) {
5eddb70b 2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2543
2544 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2545 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2546 DRM_DEBUG_KMS("FDI train 2 done.\n");
2547 break;
2548 }
8db9d77b 2549 }
e1a44743 2550 if (tries == 5)
5eddb70b 2551 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2552
2553 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2554
8db9d77b
ZW		 2555}
2556
0206e353 2557static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2558 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2559 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2560 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2561 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2562};
2563
2564/* The FDI link training functions for SNB/Cougarpoint. */
2565static void gen6_fdi_link_train(struct drm_crtc *crtc)
2566{
2567 struct drm_device *dev = crtc->dev;
2568 struct drm_i915_private *dev_priv = dev->dev_private;
2569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2570 int pipe = intel_crtc->pipe;
fa37d39e 2571 u32 reg, temp, i, retry;
8db9d77b 2572
e1a44743
AJ		 2573 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2574 for train result */
5eddb70b
CW		 2575 reg = FDI_RX_IMR(pipe);
2576 temp = I915_READ(reg);
e1a44743
AJ		 2577 temp &= ~FDI_RX_SYMBOL_LOCK;
2578 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2579 I915_WRITE(reg, temp);
2580
2581 POSTING_READ(reg);
e1a44743
AJ		 2582 udelay(150);
2583
8db9d77b 2584 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2585 reg = FDI_TX_CTL(pipe);
2586 temp = I915_READ(reg);
77ffb597
AJ		 2587 temp &= ~(7 << 19);
2588 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2589 temp &= ~FDI_LINK_TRAIN_NONE;
2590 temp |= FDI_LINK_TRAIN_PATTERN_1;
2591 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2592 /* SNB-B */
2593 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2594 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2595
d74cf324
DV		 2596 I915_WRITE(FDI_RX_MISC(pipe),
2597 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2598
5eddb70b
CW		 2599 reg = FDI_RX_CTL(pipe);
2600 temp = I915_READ(reg);
8db9d77b
ZW		 2601 if (HAS_PCH_CPT(dev)) {
2602 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2603 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2604 } else {
2605 temp &= ~FDI_LINK_TRAIN_NONE;
2606 temp |= FDI_LINK_TRAIN_PATTERN_1;
2607 }
5eddb70b
CW		 2608 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2609
2610 POSTING_READ(reg);
8db9d77b
ZW		 2611 udelay(150);
2612
8f5718a6 2613 cpt_phase_pointer_enable(dev, pipe);
291427f5 2614
0206e353 2615 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
8db9d77b
ZW		 2618 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2620 I915_WRITE(reg, temp);
2621
2622 POSTING_READ(reg);
8db9d77b
ZW		 2623 udelay(500);
2624
fa37d39e
SP		 2625 for (retry = 0; retry < 5; retry++) {
2626 reg = FDI_RX_IIR(pipe);
2627 temp = I915_READ(reg);
2628 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629 if (temp & FDI_RX_BIT_LOCK) {
2630 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2631 DRM_DEBUG_KMS("FDI train 1 done.\n");
2632 break;
2633 }
2634 udelay(50);
8db9d77b 2635 }
fa37d39e
SP		 2636 if (retry < 5)
2637 break;
8db9d77b
ZW		 2638 }
2639 if (i == 4)
5eddb70b 2640 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2641
2642 /* Train 2 */
5eddb70b
CW		 2643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
8db9d77b
ZW		 2645 temp &= ~FDI_LINK_TRAIN_NONE;
2646 temp |= FDI_LINK_TRAIN_PATTERN_2;
2647 if (IS_GEN6(dev)) {
2648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 /* SNB-B */
2650 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2651 }
5eddb70b 2652 I915_WRITE(reg, temp);
8db9d77b 2653
5eddb70b
CW		 2654 reg = FDI_RX_CTL(pipe);
2655 temp = I915_READ(reg);
8db9d77b
ZW		 2656 if (HAS_PCH_CPT(dev)) {
2657 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2658 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2659 } else {
2660 temp &= ~FDI_LINK_TRAIN_NONE;
2661 temp |= FDI_LINK_TRAIN_PATTERN_2;
2662 }
5eddb70b
CW		 2663 I915_WRITE(reg, temp);
2664
2665 POSTING_READ(reg);
8db9d77b
ZW		 2666 udelay(150);
2667
0206e353 2668 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
8db9d77b
ZW		 2671 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2673 I915_WRITE(reg, temp);
2674
2675 POSTING_READ(reg);
8db9d77b
ZW		 2676 udelay(500);
2677
fa37d39e
SP		 2678 for (retry = 0; retry < 5; retry++) {
2679 reg = FDI_RX_IIR(pipe);
2680 temp = I915_READ(reg);
2681 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2682 if (temp & FDI_RX_SYMBOL_LOCK) {
2683 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2684 DRM_DEBUG_KMS("FDI train 2 done.\n");
2685 break;
2686 }
2687 udelay(50);
8db9d77b 2688 }
fa37d39e
SP		 2689 if (retry < 5)
2690 break;
8db9d77b
ZW		 2691 }
2692 if (i == 4)
5eddb70b 2693 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2694
2695 DRM_DEBUG_KMS("FDI train done.\n");
2696}
2697
357555c0
JB		 2698/* Manual link training for Ivy Bridge A0 parts */
2699static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2700{
2701 struct drm_device *dev = crtc->dev;
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2704 int pipe = intel_crtc->pipe;
2705 u32 reg, temp, i;
2706
2707 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2708 for train result */
2709 reg = FDI_RX_IMR(pipe);
2710 temp = I915_READ(reg);
2711 temp &= ~FDI_RX_SYMBOL_LOCK;
2712 temp &= ~FDI_RX_BIT_LOCK;
2713 I915_WRITE(reg, temp);
2714
2715 POSTING_READ(reg);
2716 udelay(150);
2717
01a415fd
DV		 2718 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2719 I915_READ(FDI_RX_IIR(pipe)));
2720
357555c0
JB		 2721 /* enable CPU FDI TX and PCH FDI RX */
2722 reg = FDI_TX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~(7 << 19);
2725 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2726 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2727 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2728 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2729 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2730 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2731 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2732
d74cf324
DV		 2733 I915_WRITE(FDI_RX_MISC(pipe),
2734 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2735
357555c0
JB		 2736 reg = FDI_RX_CTL(pipe);
2737 temp = I915_READ(reg);
2738 temp &= ~FDI_LINK_TRAIN_AUTO;
2739 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2740 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2741 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2742 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2743
2744 POSTING_READ(reg);
2745 udelay(150);
2746
8f5718a6 2747 cpt_phase_pointer_enable(dev, pipe);
291427f5 2748
0206e353 2749 for (i = 0; i < 4; i++) {
357555c0
JB		 2750 reg = FDI_TX_CTL(pipe);
2751 temp = I915_READ(reg);
2752 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2753 temp |= snb_b_fdi_train_param[i];
2754 I915_WRITE(reg, temp);
2755
2756 POSTING_READ(reg);
2757 udelay(500);
2758
2759 reg = FDI_RX_IIR(pipe);
2760 temp = I915_READ(reg);
2761 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2762
2763 if (temp & FDI_RX_BIT_LOCK ||
2764 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2765 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2766 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2767 break;
2768 }
2769 }
2770 if (i == 4)
2771 DRM_ERROR("FDI train 1 fail!\n");
2772
2773 /* Train 2 */
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2777 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2778 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2780 I915_WRITE(reg, temp);
2781
2782 reg = FDI_RX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2785 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2786 I915_WRITE(reg, temp);
2787
2788 POSTING_READ(reg);
2789 udelay(150);
2790
0206e353 2791 for (i = 0; i < 4; i++) {
357555c0
JB		 2792 reg = FDI_TX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2795 temp |= snb_b_fdi_train_param[i];
2796 I915_WRITE(reg, temp);
2797
2798 POSTING_READ(reg);
2799 udelay(500);
2800
2801 reg = FDI_RX_IIR(pipe);
2802 temp = I915_READ(reg);
2803 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2804
2805 if (temp & FDI_RX_SYMBOL_LOCK) {
2806 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2807 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2808 break;
2809 }
2810 }
2811 if (i == 4)
2812 DRM_ERROR("FDI train 2 fail!\n");
2813
2814 DRM_DEBUG_KMS("FDI train done.\n");
2815}
2816
88cefb6c 2817static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2818{
88cefb6c 2819 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2820 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2821 int pipe = intel_crtc->pipe;
5eddb70b 2822 u32 reg, temp;
79e53945 2823
c64e311e 2824
c98e9dcf 2825 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2829 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2830 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2831 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2832
2833 POSTING_READ(reg);
c98e9dcf
JB		 2834 udelay(200);
2835
2836 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2837 temp = I915_READ(reg);
2838 I915_WRITE(reg, temp | FDI_PCDCLK);
2839
2840 POSTING_READ(reg);
c98e9dcf
JB		 2841 udelay(200);
2842
bf507ef7
ED		 2843 /* On Haswell, the PLL configuration for ports and pipes is handled
2844 * separately, as part of DDI setup */
2845 if (!IS_HASWELL(dev)) {
2846 /* Enable CPU FDI TX PLL, always on for Ironlake */
2847 reg = FDI_TX_CTL(pipe);
2848 temp = I915_READ(reg);
2849 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2850 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2851
bf507ef7
ED		 2852 POSTING_READ(reg);
2853 udelay(100);
2854 }
6be4a607 2855 }
0e23b99d
JB		 2856}
2857
88cefb6c
DV		 2858static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2859{
2860 struct drm_device *dev = intel_crtc->base.dev;
2861 struct drm_i915_private *dev_priv = dev->dev_private;
2862 int pipe = intel_crtc->pipe;
2863 u32 reg, temp;
2864
2865 /* Switch from PCDclk to Rawclk */
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2869
2870 /* Disable CPU FDI TX PLL */
2871 reg = FDI_TX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2874
2875 POSTING_READ(reg);
2876 udelay(100);
2877
2878 reg = FDI_RX_CTL(pipe);
2879 temp = I915_READ(reg);
2880 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2881
2882 /* Wait for the clocks to turn off. */
2883 POSTING_READ(reg);
2884 udelay(100);
2885}
2886
291427f5
JB		 2887static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2888{
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2890 u32 flags = I915_READ(SOUTH_CHICKEN1);
2891
2892 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2893 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2894 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2895 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2896 POSTING_READ(SOUTH_CHICKEN1);
2897}
0fc932b8
JB		 2898static void ironlake_fdi_disable(struct drm_crtc *crtc)
2899{
2900 struct drm_device *dev = crtc->dev;
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903 int pipe = intel_crtc->pipe;
2904 u32 reg, temp;
2905
2906 /* disable CPU FDI tx and PCH FDI rx */
2907 reg = FDI_TX_CTL(pipe);
2908 temp = I915_READ(reg);
2909 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2910 POSTING_READ(reg);
2911
2912 reg = FDI_RX_CTL(pipe);
2913 temp = I915_READ(reg);
2914 temp &= ~(0x7 << 16);
2915 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2916 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2917
2918 POSTING_READ(reg);
2919 udelay(100);
2920
2921 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2922 if (HAS_PCH_IBX(dev)) {
2923 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
291427f5
JB		 2924 } else if (HAS_PCH_CPT(dev)) {
2925 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2926 }
0fc932b8
JB		 2927
2928 /* still set train pattern 1 */
2929 reg = FDI_TX_CTL(pipe);
2930 temp = I915_READ(reg);
2931 temp &= ~FDI_LINK_TRAIN_NONE;
2932 temp |= FDI_LINK_TRAIN_PATTERN_1;
2933 I915_WRITE(reg, temp);
2934
2935 reg = FDI_RX_CTL(pipe);
2936 temp = I915_READ(reg);
2937 if (HAS_PCH_CPT(dev)) {
2938 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2939 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2940 } else {
2941 temp &= ~FDI_LINK_TRAIN_NONE;
2942 temp |= FDI_LINK_TRAIN_PATTERN_1;
2943 }
2944 /* BPC in FDI rx is consistent with that in PIPECONF */
2945 temp &= ~(0x07 << 16);
2946 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2947 I915_WRITE(reg, temp);
2948
2949 POSTING_READ(reg);
2950 udelay(100);
2951}
2952
5bb61643
CW		 2953static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2954{
2955 struct drm_device *dev = crtc->dev;
2956 struct drm_i915_private *dev_priv = dev->dev_private;
2957 unsigned long flags;
2958 bool pending;
2959
2960 if (atomic_read(&dev_priv->mm.wedged))
2961 return false;
2962
2963 spin_lock_irqsave(&dev->event_lock, flags);
2964 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2965 spin_unlock_irqrestore(&dev->event_lock, flags);
2966
2967 return pending;
2968}
2969
e6c3a2a6
CW		 2970static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2971{
0f91128d 2972 struct drm_device *dev = crtc->dev;
5bb61643 2973 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2974
2975 if (crtc->fb == NULL)
2976 return;
2977
5bb61643
CW		 2978 wait_event(dev_priv->pending_flip_queue,
2979 !intel_crtc_has_pending_flip(crtc));
2980
0f91128d
CW		 2981 mutex_lock(&dev->struct_mutex);
2982 intel_finish_fb(crtc->fb);
2983 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2984}
2985
fc316cbe 2986static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2987{
2988 struct drm_device *dev = crtc->dev;
228d3e36 2989 struct intel_encoder *intel_encoder;
040484af
JB		 2990
2991 /*
2992 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2993 * must be driven by its own crtc; no sharing is possible.
2994 */
228d3e36 2995 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2996 switch (intel_encoder->type) {
040484af 2997 case INTEL_OUTPUT_EDP:
228d3e36 2998 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2999 return false;
3000 continue;
3001 }
3002 }
3003
3004 return true;
3005}
3006
fc316cbe
PZ		 3007static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3008{
3009 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3010}
3011
e615efe4
ED		 3012/* Program iCLKIP clock to the desired frequency */
3013static void lpt_program_iclkip(struct drm_crtc *crtc)
3014{
3015 struct drm_device *dev = crtc->dev;
3016 struct drm_i915_private *dev_priv = dev->dev_private;
3017 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3018 u32 temp;
3019
3020 /* It is necessary to ungate the pixclk gate prior to programming
3021 * the divisors, and gate it back when it is done.
3022 */
3023 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3024
3025 /* Disable SSCCTL */
3026 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3027 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3028 SBI_SSCCTL_DISABLE);
3029
3030 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3031 if (crtc->mode.clock == 20000) {
3032 auxdiv = 1;
3033 divsel = 0x41;
3034 phaseinc = 0x20;
3035 } else {
3036 /* The iCLK virtual clock root frequency is in MHz,
3037 * but the crtc->mode.clock in in KHz. To get the divisors,
3038 * it is necessary to divide one by another, so we
3039 * convert the virtual clock precision to KHz here for higher
3040 * precision.
3041 */
3042 u32 iclk_virtual_root_freq = 172800 * 1000;
3043 u32 iclk_pi_range = 64;
3044 u32 desired_divisor, msb_divisor_value, pi_value;
3045
3046 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3047 msb_divisor_value = desired_divisor / iclk_pi_range;
3048 pi_value = desired_divisor % iclk_pi_range;
3049
3050 auxdiv = 0;
3051 divsel = msb_divisor_value - 2;
3052 phaseinc = pi_value;
3053 }
3054
3055 /* This should not happen with any sane values */
3056 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3057 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3058 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3059 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3060
3061 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3062 crtc->mode.clock,
3063 auxdiv,
3064 divsel,
3065 phasedir,
3066 phaseinc);
3067
3068 /* Program SSCDIVINTPHASE6 */
3069 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3070 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3071 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3072 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3073 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3074 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3075 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3076
3077 intel_sbi_write(dev_priv,
3078 SBI_SSCDIVINTPHASE6,
3079 temp);
3080
3081 /* Program SSCAUXDIV */
3082 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3083 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3084 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3085 intel_sbi_write(dev_priv,
3086 SBI_SSCAUXDIV6,
3087 temp);
3088
3089
3090 /* Enable modulator and associated divider */
3091 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3092 temp &= ~SBI_SSCCTL_DISABLE;
3093 intel_sbi_write(dev_priv,
3094 SBI_SSCCTL6,
3095 temp);
3096
3097 /* Wait for initialization time */
3098 udelay(24);
3099
3100 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3101}
3102
f67a559d
JB		 3103/*
3104 * Enable PCH resources required for PCH ports:
3105 * - PCH PLLs
3106 * - FDI training & RX/TX
3107 * - update transcoder timings
3108 * - DP transcoding bits
3109 * - transcoder
3110 */
3111static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3112{
3113 struct drm_device *dev = crtc->dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3116 int pipe = intel_crtc->pipe;
ee7b9f93 3117 u32 reg, temp;
2c07245f 3118
e7e164db
CW		 3119 assert_transcoder_disabled(dev_priv, pipe);
3120
cd986abb
DV		 3121 /* Write the TU size bits before fdi link training, so that error
3122 * detection works. */
3123 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3124 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3125
c98e9dcf 3126 /* For PCH output, training FDI link */
674cf967 3127 dev_priv->display.fdi_link_train(crtc);
2c07245f 3128
572deb37
DV		 3129 /* XXX: pch pll's can be enabled any time before we enable the PCH
3130 * transcoder, and we actually should do this to not upset any PCH
3131 * transcoder that already use the clock when we share it.
3132 *
3133 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3134 * unconditionally resets the pll - we need that to have the right LVDS
3135 * enable sequence. */
b6b4e185 3136 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3137
303b81e0 3138 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3139 u32 sel;
4b645f14 3140
c98e9dcf 3141 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3142 switch (pipe) {
3143 default:
3144 case 0:
3145 temp |= TRANSA_DPLL_ENABLE;
3146 sel = TRANSA_DPLLB_SEL;
3147 break;
3148 case 1:
3149 temp |= TRANSB_DPLL_ENABLE;
3150 sel = TRANSB_DPLLB_SEL;
3151 break;
3152 case 2:
3153 temp |= TRANSC_DPLL_ENABLE;
3154 sel = TRANSC_DPLLB_SEL;
3155 break;
d64311ab 3156 }
ee7b9f93
JB		 3157 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3158 temp |= sel;
3159 else
3160 temp &= ~sel;
c98e9dcf 3161 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3162 }
5eddb70b 3163
d9b6cb56
JB		 3164 /* set transcoder timing, panel must allow it */
3165 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3166 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3167 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3168 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3169
5eddb70b
CW		 3170 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3171 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3172 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3173 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3174
303b81e0 3175 intel_fdi_normal_train(crtc);
5e84e1a4 3176
c98e9dcf
JB		 3177 /* For PCH DP, enable TRANS_DP_CTL */
3178 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3179 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3180 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3181 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3182 reg = TRANS_DP_CTL(pipe);
3183 temp = I915_READ(reg);
3184 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3185 TRANS_DP_SYNC_MASK |
3186 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3187 temp |= (TRANS_DP_OUTPUT_ENABLE |
3188 TRANS_DP_ENH_FRAMING);
9325c9f0 3189 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3190
3191 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3192 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3193 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3194 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3195
3196 switch (intel_trans_dp_port_sel(crtc)) {
3197 case PCH_DP_B:
5eddb70b 3198 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3199 break;
3200 case PCH_DP_C:
5eddb70b 3201 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3202 break;
3203 case PCH_DP_D:
5eddb70b 3204 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3205 break;
3206 default:
e95d41e1 3207 BUG();
32f9d658 3208 }
2c07245f 3209
5eddb70b 3210 I915_WRITE(reg, temp);
6be4a607 3211 }
b52eb4dc 3212
b8a4f404 3213 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3214}
3215
1507e5bd
PZ		 3216static void lpt_pch_enable(struct drm_crtc *crtc)
3217{
3218 struct drm_device *dev = crtc->dev;
3219 struct drm_i915_private *dev_priv = dev->dev_private;
3220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3221 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3222
daed2dbb 3223 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3224
8c52b5e8 3225 lpt_program_iclkip(crtc);
1507e5bd 3226
0540e488 3227 /* Set transcoder timing. */
daed2dbb
PZ		 3228 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3229 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3230 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3231
daed2dbb
PZ		 3232 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3233 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3234 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3235 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3236
937bb610 3237 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3238}
3239
ee7b9f93
JB		 3240static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3241{
3242 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3243
3244 if (pll == NULL)
3245 return;
3246
3247 if (pll->refcount == 0) {
3248 WARN(1, "bad PCH PLL refcount\n");
3249 return;
3250 }
3251
3252 --pll->refcount;
3253 intel_crtc->pch_pll = NULL;
3254}
3255
3256static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3257{
3258 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3259 struct intel_pch_pll *pll;
3260 int i;
3261
3262 pll = intel_crtc->pch_pll;
3263 if (pll) {
3264 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3265 intel_crtc->base.base.id, pll->pll_reg);
3266 goto prepare;
3267 }
3268
98b6bd99
DV		 3269 if (HAS_PCH_IBX(dev_priv->dev)) {
3270 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3271 i = intel_crtc->pipe;
3272 pll = &dev_priv->pch_plls[i];
3273
3274 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3275 intel_crtc->base.base.id, pll->pll_reg);
3276
3277 goto found;
3278 }
3279
ee7b9f93
JB		 3280 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3281 pll = &dev_priv->pch_plls[i];
3282
3283 /* Only want to check enabled timings first */
3284 if (pll->refcount == 0)
3285 continue;
3286
3287 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3288 fp == I915_READ(pll->fp0_reg)) {
3289 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3290 intel_crtc->base.base.id,
3291 pll->pll_reg, pll->refcount, pll->active);
3292
3293 goto found;
3294 }
3295 }
3296
3297 /* Ok no matching timings, maybe there's a free one? */
3298 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3299 pll = &dev_priv->pch_plls[i];
3300 if (pll->refcount == 0) {
3301 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3302 intel_crtc->base.base.id, pll->pll_reg);
3303 goto found;
3304 }
3305 }
3306
3307 return NULL;
3308
3309found:
3310 intel_crtc->pch_pll = pll;
3311 pll->refcount++;
3312 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3313prepare: /* separate function? */
3314 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3315
e04c7350
CW		 3316 /* Wait for the clocks to stabilize before rewriting the regs */
3317 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3318 POSTING_READ(pll->pll_reg);
3319 udelay(150);
e04c7350
CW		 3320
3321 I915_WRITE(pll->fp0_reg, fp);
3322 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3323 pll->on = false;
3324 return pll;
3325}
3326
d4270e57
JB		 3327void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3328{
3329 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3330 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3331 u32 temp;
3332
3333 temp = I915_READ(dslreg);
3334 udelay(500);
3335 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3336 if (wait_for(I915_READ(dslreg) != temp, 5))
3337 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3338 }
3339}
3340
f67a559d
JB		 3341static void ironlake_crtc_enable(struct drm_crtc *crtc)
3342{
3343 struct drm_device *dev = crtc->dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3346 struct intel_encoder *encoder;
f67a559d
JB		 3347 int pipe = intel_crtc->pipe;
3348 int plane = intel_crtc->plane;
3349 u32 temp;
3350 bool is_pch_port;
3351
08a48469
DV		 3352 WARN_ON(!crtc->enabled);
3353
f67a559d
JB		 3354 if (intel_crtc->active)
3355 return;
3356
3357 intel_crtc->active = true;
3358 intel_update_watermarks(dev);
3359
3360 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3361 temp = I915_READ(PCH_LVDS);
3362 if ((temp & LVDS_PORT_EN) == 0)
3363 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3364 }
3365
fc316cbe 3366 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3367
46b6f814 3368 if (is_pch_port) {
fff367c7
DV		 3369 /* Note: FDI PLL enabling _must_ be done before we enable the
3370 * cpu pipes, hence this is separate from all the other fdi/pch
3371 * enabling. */
88cefb6c 3372 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3373 } else {
3374 assert_fdi_tx_disabled(dev_priv, pipe);
3375 assert_fdi_rx_disabled(dev_priv, pipe);
3376 }
f67a559d 3377
bf49ec8c
DV		 3378 for_each_encoder_on_crtc(dev, crtc, encoder)
3379 if (encoder->pre_enable)
3380 encoder->pre_enable(encoder);
f67a559d
JB		 3381
3382 /* Enable panel fitting for LVDS */
3383 if (dev_priv->pch_pf_size &&
547dc041
JN		 3384 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3385 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3386 /* Force use of hard-coded filter coefficients
3387 * as some pre-programmed values are broken,
3388 * e.g. x201.
3389 */
13888d78
PZ		 3390 if (IS_IVYBRIDGE(dev))
3391 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3392 PF_PIPE_SEL_IVB(pipe));
3393 else
3394 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3395 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3396 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3397 }
3398
9c54c0dd
JB		 3399 /*
3400 * On ILK+ LUT must be loaded before the pipe is running but with
3401 * clocks enabled
3402 */
3403 intel_crtc_load_lut(crtc);
3404
f67a559d
JB		 3405 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3406 intel_enable_plane(dev_priv, plane, pipe);
3407
3408 if (is_pch_port)
3409 ironlake_pch_enable(crtc);
c98e9dcf 3410
d1ebd816 3411 mutex_lock(&dev->struct_mutex);
bed4a673 3412 intel_update_fbc(dev);
d1ebd816
BW		 3413 mutex_unlock(&dev->struct_mutex);
3414
6b383a7f 3415 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3416
fa5c73b1
DV		 3417 for_each_encoder_on_crtc(dev, crtc, encoder)
3418 encoder->enable(encoder);
61b77ddd
DV		 3419
3420 if (HAS_PCH_CPT(dev))
3421 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3422
3423 /*
3424 * There seems to be a race in PCH platform hw (at least on some
3425 * outputs) where an enabled pipe still completes any pageflip right
3426 * away (as if the pipe is off) instead of waiting for vblank. As soon
3427 * as the first vblank happend, everything works as expected. Hence just
3428 * wait for one vblank before returning to avoid strange things
3429 * happening.
3430 */
3431 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3432}
3433
4f771f10
PZ		 3434static void haswell_crtc_enable(struct drm_crtc *crtc)
3435{
3436 struct drm_device *dev = crtc->dev;
3437 struct drm_i915_private *dev_priv = dev->dev_private;
3438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3439 struct intel_encoder *encoder;
3440 int pipe = intel_crtc->pipe;
3441 int plane = intel_crtc->plane;
4f771f10
PZ		 3442 bool is_pch_port;
3443
3444 WARN_ON(!crtc->enabled);
3445
3446 if (intel_crtc->active)
3447 return;
3448
3449 intel_crtc->active = true;
3450 intel_update_watermarks(dev);
3451
fc316cbe 3452 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3453
83616634 3454 if (is_pch_port)
04945641 3455 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3456
3457 for_each_encoder_on_crtc(dev, crtc, encoder)
3458 if (encoder->pre_enable)
3459 encoder->pre_enable(encoder);
3460
1f544388 3461 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3462
1f544388 3463 /* Enable panel fitting for eDP */
547dc041
JN		 3464 if (dev_priv->pch_pf_size &&
3465 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3466 /* Force use of hard-coded filter coefficients
3467 * as some pre-programmed values are broken,
3468 * e.g. x201.
3469 */
54075a7d
PZ		 3470 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3471 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3472 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3473 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3474 }
3475
3476 /*
3477 * On ILK+ LUT must be loaded before the pipe is running but with
3478 * clocks enabled
3479 */
3480 intel_crtc_load_lut(crtc);
3481
1f544388
PZ		 3482 intel_ddi_set_pipe_settings(crtc);
3483 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3484
3485 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3486 intel_enable_plane(dev_priv, plane, pipe);
3487
3488 if (is_pch_port)
1507e5bd 3489 lpt_pch_enable(crtc);
4f771f10
PZ		 3490
3491 mutex_lock(&dev->struct_mutex);
3492 intel_update_fbc(dev);
3493 mutex_unlock(&dev->struct_mutex);
3494
3495 intel_crtc_update_cursor(crtc, true);
3496
3497 for_each_encoder_on_crtc(dev, crtc, encoder)
3498 encoder->enable(encoder);
3499
4f771f10
PZ		 3500 /*
3501 * There seems to be a race in PCH platform hw (at least on some
3502 * outputs) where an enabled pipe still completes any pageflip right
3503 * away (as if the pipe is off) instead of waiting for vblank. As soon
3504 * as the first vblank happend, everything works as expected. Hence just
3505 * wait for one vblank before returning to avoid strange things
3506 * happening.
3507 */
3508 intel_wait_for_vblank(dev, intel_crtc->pipe);
3509}
3510
6be4a607
JB		 3511static void ironlake_crtc_disable(struct drm_crtc *crtc)
3512{
3513 struct drm_device *dev = crtc->dev;
3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3516 struct intel_encoder *encoder;
6be4a607
JB		 3517 int pipe = intel_crtc->pipe;
3518 int plane = intel_crtc->plane;
5eddb70b 3519 u32 reg, temp;
b52eb4dc 3520
ef9c3aee 3521
f7abfe8b
CW		 3522 if (!intel_crtc->active)
3523 return;
3524
ea9d758d
DV		 3525 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 encoder->disable(encoder);
3527
e6c3a2a6 3528 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3529 drm_vblank_off(dev, pipe);
6b383a7f 3530 intel_crtc_update_cursor(crtc, false);
5eddb70b 3531
b24e7179 3532 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3533
973d04f9
CW		 3534 if (dev_priv->cfb_plane == plane)
3535 intel_disable_fbc(dev);
2c07245f 3536
b24e7179 3537 intel_disable_pipe(dev_priv, pipe);
32f9d658 3538
6be4a607 3539 /* Disable PF */
9db4a9c7
JB		 3540 I915_WRITE(PF_CTL(pipe), 0);
3541 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3542
bf49ec8c
DV		 3543 for_each_encoder_on_crtc(dev, crtc, encoder)
3544 if (encoder->post_disable)
3545 encoder->post_disable(encoder);
2c07245f 3546
0fc932b8 3547 ironlake_fdi_disable(crtc);
249c0e64 3548
b8a4f404 3549 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3550
6be4a607
JB		 3551 if (HAS_PCH_CPT(dev)) {
3552 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3553 reg = TRANS_DP_CTL(pipe);
3554 temp = I915_READ(reg);
3555 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3556 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3557 I915_WRITE(reg, temp);
6be4a607
JB		 3558
3559 /* disable DPLL_SEL */
3560 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3561 switch (pipe) {
3562 case 0:
d64311ab 3563 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3564 break;
3565 case 1:
6be4a607 3566 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3567 break;
3568 case 2:
4b645f14 3569 /* C shares PLL A or B */
d64311ab 3570 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3571 break;
3572 default:
3573 BUG(); /* wtf */
3574 }
6be4a607 3575 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3576 }
e3421a18 3577
6be4a607 3578 /* disable PCH DPLL */
ee7b9f93 3579 intel_disable_pch_pll(intel_crtc);
8db9d77b 3580
88cefb6c 3581 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3582
f7abfe8b 3583 intel_crtc->active = false;
6b383a7f 3584 intel_update_watermarks(dev);
d1ebd816
BW		 3585
3586 mutex_lock(&dev->struct_mutex);
6b383a7f 3587 intel_update_fbc(dev);
d1ebd816 3588 mutex_unlock(&dev->struct_mutex);
6be4a607 3589}
1b3c7a47 3590
4f771f10 3591static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3592{
4f771f10
PZ		 3593 struct drm_device *dev = crtc->dev;
3594 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3596 struct intel_encoder *encoder;
3597 int pipe = intel_crtc->pipe;
3598 int plane = intel_crtc->plane;
ad80a810 3599 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3600 bool is_pch_port;
ee7b9f93 3601
4f771f10
PZ		 3602 if (!intel_crtc->active)
3603 return;
3604
83616634
PZ		 3605 is_pch_port = haswell_crtc_driving_pch(crtc);
3606
4f771f10
PZ		 3607 for_each_encoder_on_crtc(dev, crtc, encoder)
3608 encoder->disable(encoder);
3609
3610 intel_crtc_wait_for_pending_flips(crtc);
3611 drm_vblank_off(dev, pipe);
3612 intel_crtc_update_cursor(crtc, false);
3613
3614 intel_disable_plane(dev_priv, plane, pipe);
3615
3616 if (dev_priv->cfb_plane == plane)
3617 intel_disable_fbc(dev);
3618
3619 intel_disable_pipe(dev_priv, pipe);
3620
ad80a810 3621 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3622
3623 /* Disable PF */
3624 I915_WRITE(PF_CTL(pipe), 0);
3625 I915_WRITE(PF_WIN_SZ(pipe), 0);
3626
1f544388 3627 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3628
3629 for_each_encoder_on_crtc(dev, crtc, encoder)
3630 if (encoder->post_disable)
3631 encoder->post_disable(encoder);
3632
83616634 3633 if (is_pch_port) {
ab4d966c 3634 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3635 intel_ddi_fdi_disable(crtc);
83616634 3636 }
4f771f10
PZ		 3637
3638 intel_crtc->active = false;
3639 intel_update_watermarks(dev);
3640
3641 mutex_lock(&dev->struct_mutex);
3642 intel_update_fbc(dev);
3643 mutex_unlock(&dev->struct_mutex);
3644}
3645
ee7b9f93
JB		 3646static void ironlake_crtc_off(struct drm_crtc *crtc)
3647{
3648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3649 intel_put_pch_pll(intel_crtc);
3650}
3651
6441ab5f
PZ		 3652static void haswell_crtc_off(struct drm_crtc *crtc)
3653{
a5c961d1
PZ		 3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655
3656 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3657 * start using it. */
3658 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3659
6441ab5f
PZ		 3660 intel_ddi_put_crtc_pll(crtc);
3661}
3662
02e792fb
DV		 3663static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3664{
02e792fb 3665 if (!enable && intel_crtc->overlay) {
23f09ce3 3666 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3667 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3668
23f09ce3 3669 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3670 dev_priv->mm.interruptible = false;
3671 (void) intel_overlay_switch_off(intel_crtc->overlay);
3672 dev_priv->mm.interruptible = true;
23f09ce3 3673 mutex_unlock(&dev->struct_mutex);
02e792fb 3674 }
02e792fb 3675
5dcdbcb0
CW		 3676 /* Let userspace switch the overlay on again. In most cases userspace
3677 * has to recompute where to put it anyway.
3678 */
02e792fb
DV		 3679}
3680
0b8765c6 3681static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3682{
3683 struct drm_device *dev = crtc->dev;
79e53945
JB		 3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3686 struct intel_encoder *encoder;
79e53945 3687 int pipe = intel_crtc->pipe;
80824003 3688 int plane = intel_crtc->plane;
79e53945 3689
08a48469
DV		 3690 WARN_ON(!crtc->enabled);
3691
f7abfe8b
CW		 3692 if (intel_crtc->active)
3693 return;
3694
3695 intel_crtc->active = true;
6b383a7f
CW		 3696 intel_update_watermarks(dev);
3697
63d7bbe9 3698 intel_enable_pll(dev_priv, pipe);
040484af 3699 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3700 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3701
0b8765c6 3702 intel_crtc_load_lut(crtc);
bed4a673 3703 intel_update_fbc(dev);
79e53945 3704
0b8765c6
JB		 3705 /* Give the overlay scaler a chance to enable if it's on this pipe */
3706 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3707 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3708
fa5c73b1
DV		 3709 for_each_encoder_on_crtc(dev, crtc, encoder)
3710 encoder->enable(encoder);
0b8765c6 3711}
79e53945 3712
0b8765c6
JB		 3713static void i9xx_crtc_disable(struct drm_crtc *crtc)
3714{
3715 struct drm_device *dev = crtc->dev;
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3718 struct intel_encoder *encoder;
0b8765c6
JB		 3719 int pipe = intel_crtc->pipe;
3720 int plane = intel_crtc->plane;
b690e96c 3721
ef9c3aee 3722
f7abfe8b
CW		 3723 if (!intel_crtc->active)
3724 return;
3725
ea9d758d
DV		 3726 for_each_encoder_on_crtc(dev, crtc, encoder)
3727 encoder->disable(encoder);
3728
0b8765c6 3729 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3730 intel_crtc_wait_for_pending_flips(crtc);
3731 drm_vblank_off(dev, pipe);
0b8765c6 3732 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3733 intel_crtc_update_cursor(crtc, false);
0b8765c6 3734
973d04f9
CW		 3735 if (dev_priv->cfb_plane == plane)
3736 intel_disable_fbc(dev);
79e53945 3737
b24e7179 3738 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3739 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3740 intel_disable_pll(dev_priv, pipe);
0b8765c6 3741
f7abfe8b 3742 intel_crtc->active = false;
6b383a7f
CW		 3743 intel_update_fbc(dev);
3744 intel_update_watermarks(dev);
0b8765c6
JB		 3745}
3746
ee7b9f93
JB		 3747static void i9xx_crtc_off(struct drm_crtc *crtc)
3748{
3749}
3750
976f8a20
DV		 3751static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3752 bool enabled)
2c07245f
ZW		 3753{
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_master_private *master_priv;
3756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3757 int pipe = intel_crtc->pipe;
79e53945
JB		 3758
3759 if (!dev->primary->master)
3760 return;
3761
3762 master_priv = dev->primary->master->driver_priv;
3763 if (!master_priv->sarea_priv)
3764 return;
3765
79e53945
JB		 3766 switch (pipe) {
3767 case 0:
3768 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3769 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3770 break;
3771 case 1:
3772 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3773 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3774 break;
3775 default:
9db4a9c7 3776 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3777 break;
3778 }
79e53945
JB		 3779}
3780
976f8a20
DV		 3781/**
3782 * Sets the power management mode of the pipe and plane.
3783 */
3784void intel_crtc_update_dpms(struct drm_crtc *crtc)
3785{
3786 struct drm_device *dev = crtc->dev;
3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788 struct intel_encoder *intel_encoder;
3789 bool enable = false;
3790
3791 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3792 enable |= intel_encoder->connectors_active;
3793
3794 if (enable)
3795 dev_priv->display.crtc_enable(crtc);
3796 else
3797 dev_priv->display.crtc_disable(crtc);
3798
3799 intel_crtc_update_sarea(crtc, enable);
3800}
3801
3802static void intel_crtc_noop(struct drm_crtc *crtc)
3803{
3804}
3805
cdd59983
CW		 3806static void intel_crtc_disable(struct drm_crtc *crtc)
3807{
cdd59983 3808 struct drm_device *dev = crtc->dev;
976f8a20 3809 struct drm_connector *connector;
ee7b9f93 3810 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3811
976f8a20
DV		 3812 /* crtc should still be enabled when we disable it. */
3813 WARN_ON(!crtc->enabled);
3814
3815 dev_priv->display.crtc_disable(crtc);
3816 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3817 dev_priv->display.off(crtc);
3818
931872fc
CW		 3819 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3820 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3821
3822 if (crtc->fb) {
3823 mutex_lock(&dev->struct_mutex);
1690e1eb 3824 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3825 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3826 crtc->fb = NULL;
3827 }
3828
3829 /* Update computed state. */
3830 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3831 if (!connector->encoder || !connector->encoder->crtc)
3832 continue;
3833
3834 if (connector->encoder->crtc != crtc)
3835 continue;
3836
3837 connector->dpms = DRM_MODE_DPMS_OFF;
3838 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3839 }
3840}
3841
a261b246 3842void intel_modeset_disable(struct drm_device *dev)
79e53945 3843{
a261b246
DV		 3844 struct drm_crtc *crtc;
3845
3846 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3847 if (crtc->enabled)
3848 intel_crtc_disable(crtc);
3849 }
79e53945
JB		 3850}
3851
1f703855 3852void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3853{
7e7d76c3
JB		 3854}
3855
ea5b213a 3856void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3857{
4ef69c7a 3858 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3859
ea5b213a
CW		 3860 drm_encoder_cleanup(encoder);
3861 kfree(intel_encoder);
7e7d76c3
JB		 3862}
3863
5ab432ef
DV		 3864/* Simple dpms helper for encodres with just one connector, no cloning and only
3865 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3866 * state of the entire output pipe. */
3867void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3868{
5ab432ef
DV		 3869 if (mode == DRM_MODE_DPMS_ON) {
3870 encoder->connectors_active = true;
3871
b2cabb0e 3872 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3873 } else {
3874 encoder->connectors_active = false;
3875
b2cabb0e 3876 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3877 }
79e53945
JB		 3878}
3879
0a91ca29
DV		 3880/* Cross check the actual hw state with our own modeset state tracking (and it's
3881 * internal consistency). */
b980514c 3882static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3883{
0a91ca29
DV		 3884 if (connector->get_hw_state(connector)) {
3885 struct intel_encoder *encoder = connector->encoder;
3886 struct drm_crtc *crtc;
3887 bool encoder_enabled;
3888 enum pipe pipe;
3889
3890 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3891 connector->base.base.id,
3892 drm_get_connector_name(&connector->base));
3893
3894 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3895 "wrong connector dpms state\n");
3896 WARN(connector->base.encoder != &encoder->base,
3897 "active connector not linked to encoder\n");
3898 WARN(!encoder->connectors_active,
3899 "encoder->connectors_active not set\n");
3900
3901 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3902 WARN(!encoder_enabled, "encoder not enabled\n");
3903 if (WARN_ON(!encoder->base.crtc))
3904 return;
3905
3906 crtc = encoder->base.crtc;
3907
3908 WARN(!crtc->enabled, "crtc not enabled\n");
3909 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3910 WARN(pipe != to_intel_crtc(crtc)->pipe,
3911 "encoder active on the wrong pipe\n");
3912 }
79e53945
JB		 3913}
3914
5ab432ef
DV		 3915/* Even simpler default implementation, if there's really no special case to
3916 * consider. */
3917void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3918{
5ab432ef 3919 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3920
5ab432ef
DV		 3921 /* All the simple cases only support two dpms states. */
3922 if (mode != DRM_MODE_DPMS_ON)
3923 mode = DRM_MODE_DPMS_OFF;
d4270e57 3924
5ab432ef
DV		 3925 if (mode == connector->dpms)
3926 return;
3927
3928 connector->dpms = mode;
3929
3930 /* Only need to change hw state when actually enabled */
3931 if (encoder->base.crtc)
3932 intel_encoder_dpms(encoder, mode);
3933 else
8af6cf88 3934 WARN_ON(encoder->connectors_active != false);
0a91ca29 3935
b980514c 3936 intel_modeset_check_state(connector->dev);
79e53945
JB		 3937}
3938
f0947c37
DV		 3939/* Simple connector->get_hw_state implementation for encoders that support only
3940 * one connector and no cloning and hence the encoder state determines the state
3941 * of the connector. */
3942bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3943{
24929352 3944 enum pipe pipe = 0;
f0947c37 3945 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3946
f0947c37 3947 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3948}
3949
79e53945 3950static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3951 const struct drm_display_mode *mode,
79e53945
JB		 3952 struct drm_display_mode *adjusted_mode)
3953{
2c07245f 3954 struct drm_device *dev = crtc->dev;
89749350 3955
bad720ff 3956 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3957 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3958 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3959 return false;
2c07245f 3960 }
89749350 3961
f9bef081
DV		 3962 /* All interlaced capable intel hw wants timings in frames. Note though
3963 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3964 * timings, so we need to be careful not to clobber these.*/
3965 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3966 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3967
44f46b42
CW		 3968 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3969 * with a hsync front porch of 0.
3970 */
3971 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3972 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3973 return false;
3974
79e53945
JB		 3975 return true;
3976}
3977
25eb05fc
JB		 3978static int valleyview_get_display_clock_speed(struct drm_device *dev)
3979{
3980 return 400000; /* FIXME */
3981}
3982
e70236a8
JB		 3983static int i945_get_display_clock_speed(struct drm_device *dev)
3984{
3985 return 400000;
3986}
79e53945 3987
e70236a8 3988static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3989{
e70236a8
JB		 3990 return 333000;
3991}
79e53945 3992
e70236a8
JB		 3993static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3994{
3995 return 200000;
3996}
79e53945 3997
e70236a8
JB		 3998static int i915gm_get_display_clock_speed(struct drm_device *dev)
3999{
4000 u16 gcfgc = 0;
79e53945 4001
e70236a8
JB		 4002 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4003
4004 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4005 return 133000;
4006 else {
4007 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4008 case GC_DISPLAY_CLOCK_333_MHZ:
4009 return 333000;
4010 default:
4011 case GC_DISPLAY_CLOCK_190_200_MHZ:
4012 return 190000;
79e53945 4013 }
e70236a8
JB		 4014 }
4015}
4016
4017static int i865_get_display_clock_speed(struct drm_device *dev)
4018{
4019 return 266000;
4020}
4021
4022static int i855_get_display_clock_speed(struct drm_device *dev)
4023{
4024 u16 hpllcc = 0;
4025 /* Assume that the hardware is in the high speed state. This
4026 * should be the default.
4027 */
4028 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4029 case GC_CLOCK_133_200:
4030 case GC_CLOCK_100_200:
4031 return 200000;
4032 case GC_CLOCK_166_250:
4033 return 250000;
4034 case GC_CLOCK_100_133:
79e53945 4035 return 133000;
e70236a8 4036 }
79e53945 4037
e70236a8
JB		 4038 /* Shouldn't happen */
4039 return 0;
4040}
79e53945 4041
e70236a8
JB		 4042static int i830_get_display_clock_speed(struct drm_device *dev)
4043{
4044 return 133000;
79e53945
JB		 4045}
4046
2c07245f
ZW		 4047struct fdi_m_n {
4048 u32 tu;
4049 u32 gmch_m;
4050 u32 gmch_n;
4051 u32 link_m;
4052 u32 link_n;
4053};
4054
4055static void
4056fdi_reduce_ratio(u32 *num, u32 *den)
4057{
4058 while (*num > 0xffffff || *den > 0xffffff) {
4059 *num >>= 1;
4060 *den >>= 1;
4061 }
4062}
4063
2c07245f 4064static void
f2b115e6
AJ		 4065ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4066 int link_clock, struct fdi_m_n *m_n)
2c07245f 4067{
2c07245f
ZW		 4068 m_n->tu = 64; /* default size */
4069
22ed1113
CW		 4070 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4071 m_n->gmch_m = bits_per_pixel * pixel_clock;
4072 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4073 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4074
22ed1113
CW		 4075 m_n->link_m = pixel_clock;
4076 m_n->link_n = link_clock;
2c07245f
ZW		 4077 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4078}
4079
a7615030
CW		 4080static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4081{
72bbe58c
KP		 4082 if (i915_panel_use_ssc >= 0)
4083 return i915_panel_use_ssc != 0;
4084 return dev_priv->lvds_use_ssc
435793df 4085 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4086}
4087
5a354204
JB		 4088/**
4089 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4090 * @crtc: CRTC structure
3b5c78a3 4091 * @mode: requested mode
5a354204
JB		 4092 *
4093 * A pipe may be connected to one or more outputs. Based on the depth of the
4094 * attached framebuffer, choose a good color depth to use on the pipe.
4095 *
4096 * If possible, match the pipe depth to the fb depth. In some cases, this
4097 * isn't ideal, because the connected output supports a lesser or restricted
4098 * set of depths. Resolve that here:
4099 * LVDS typically supports only 6bpc, so clamp down in that case
4100 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4101 * Displays may support a restricted set as well, check EDID and clamp as
4102 * appropriate.
3b5c78a3 4103 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4104 *
4105 * RETURNS:
4106 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4107 * true if they don't match).
4108 */
4109static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4110 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4111 unsigned int *pipe_bpp,
4112 struct drm_display_mode *mode)
5a354204
JB		 4113{
4114 struct drm_device *dev = crtc->dev;
4115 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4116 struct drm_connector *connector;
6c2b7c12 4117 struct intel_encoder *intel_encoder;
5a354204
JB		 4118 unsigned int display_bpc = UINT_MAX, bpc;
4119
4120 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4121 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4122
4123 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4124 unsigned int lvds_bpc;
4125
4126 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4127 LVDS_A3_POWER_UP)
4128 lvds_bpc = 8;
4129 else
4130 lvds_bpc = 6;
4131
4132 if (lvds_bpc < display_bpc) {
82820490 4133 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4134 display_bpc = lvds_bpc;
4135 }
4136 continue;
4137 }
4138
5a354204
JB		 4139 /* Not one of the known troublemakers, check the EDID */
4140 list_for_each_entry(connector, &dev->mode_config.connector_list,
4141 head) {
6c2b7c12 4142 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4143 continue;
4144
62ac41a6
JB		 4145 /* Don't use an invalid EDID bpc value */
4146 if (connector->display_info.bpc &&
4147 connector->display_info.bpc < display_bpc) {
82820490 4148 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4149 display_bpc = connector->display_info.bpc;
4150 }
4151 }
4152
4153 /*
4154 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4155 * through, clamp it down. (Note: >12bpc will be caught below.)
4156 */
4157 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4158 if (display_bpc > 8 && display_bpc < 12) {
82820490 4159 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4160 display_bpc = 12;
4161 } else {
82820490 4162 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4163 display_bpc = 8;
4164 }
4165 }
4166 }
4167
3b5c78a3
AJ		 4168 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4169 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4170 display_bpc = 6;
4171 }
4172
5a354204
JB		 4173 /*
4174 * We could just drive the pipe at the highest bpc all the time and
4175 * enable dithering as needed, but that costs bandwidth. So choose
4176 * the minimum value that expresses the full color range of the fb but
4177 * also stays within the max display bpc discovered above.
4178 */
4179
94352cf9 4180 switch (fb->depth) {
5a354204
JB		 4181 case 8:
4182 bpc = 8; /* since we go through a colormap */
4183 break;
4184 case 15:
4185 case 16:
4186 bpc = 6; /* min is 18bpp */
4187 break;
4188 case 24:
578393cd 4189 bpc = 8;
5a354204
JB		 4190 break;
4191 case 30:
578393cd 4192 bpc = 10;
5a354204
JB		 4193 break;
4194 case 48:
578393cd 4195 bpc = 12;
5a354204
JB		 4196 break;
4197 default:
4198 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4199 bpc = min((unsigned int)8, display_bpc);
4200 break;
4201 }
4202
578393cd
KP		 4203 display_bpc = min(display_bpc, bpc);
4204
82820490
AJ		 4205 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4206 bpc, display_bpc);
5a354204 4207
578393cd 4208 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4209
4210 return display_bpc != bpc;
4211}
4212
a0c4da24
JB		 4213static int vlv_get_refclk(struct drm_crtc *crtc)
4214{
4215 struct drm_device *dev = crtc->dev;
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217 int refclk = 27000; /* for DP & HDMI */
4218
4219 return 100000; /* only one validated so far */
4220
4221 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4222 refclk = 96000;
4223 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4224 if (intel_panel_use_ssc(dev_priv))
4225 refclk = 100000;
4226 else
4227 refclk = 96000;
4228 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4229 refclk = 100000;
4230 }
4231
4232 return refclk;
4233}
4234
c65d77d8
JB		 4235static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4236{
4237 struct drm_device *dev = crtc->dev;
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239 int refclk;
4240
a0c4da24
JB		 4241 if (IS_VALLEYVIEW(dev)) {
4242 refclk = vlv_get_refclk(crtc);
4243 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4244 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4245 refclk = dev_priv->lvds_ssc_freq * 1000;
4246 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4247 refclk / 1000);
4248 } else if (!IS_GEN2(dev)) {
4249 refclk = 96000;
4250 } else {
4251 refclk = 48000;
4252 }
4253
4254 return refclk;
4255}
4256
4257static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4258 intel_clock_t *clock)
4259{
4260 /* SDVO TV has fixed PLL values depend on its clock range,
4261 this mirrors vbios setting. */
4262 if (adjusted_mode->clock >= 100000
4263 && adjusted_mode->clock < 140500) {
4264 clock->p1 = 2;
4265 clock->p2 = 10;
4266 clock->n = 3;
4267 clock->m1 = 16;
4268 clock->m2 = 8;
4269 } else if (adjusted_mode->clock >= 140500
4270 && adjusted_mode->clock <= 200000) {
4271 clock->p1 = 1;
4272 clock->p2 = 10;
4273 clock->n = 6;
4274 clock->m1 = 12;
4275 clock->m2 = 8;
4276 }
4277}
4278
a7516a05
JB		 4279static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4280 intel_clock_t *clock,
4281 intel_clock_t *reduced_clock)
4282{
4283 struct drm_device *dev = crtc->dev;
4284 struct drm_i915_private *dev_priv = dev->dev_private;
4285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4286 int pipe = intel_crtc->pipe;
4287 u32 fp, fp2 = 0;
4288
4289 if (IS_PINEVIEW(dev)) {
4290 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4291 if (reduced_clock)
4292 fp2 = (1 << reduced_clock->n) << 16 |
4293 reduced_clock->m1 << 8 | reduced_clock->m2;
4294 } else {
4295 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4296 if (reduced_clock)
4297 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4298 reduced_clock->m2;
4299 }
4300
4301 I915_WRITE(FP0(pipe), fp);
4302
4303 intel_crtc->lowfreq_avail = false;
4304 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4305 reduced_clock && i915_powersave) {
4306 I915_WRITE(FP1(pipe), fp2);
4307 intel_crtc->lowfreq_avail = true;
4308 } else {
4309 I915_WRITE(FP1(pipe), fp);
4310 }
4311}
4312
93e537a1
DV		 4313static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4314 struct drm_display_mode *adjusted_mode)
4315{
4316 struct drm_device *dev = crtc->dev;
4317 struct drm_i915_private *dev_priv = dev->dev_private;
4318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4319 int pipe = intel_crtc->pipe;
284d5df5 4320 u32 temp;
93e537a1
DV		 4321
4322 temp = I915_READ(LVDS);
4323 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4324 if (pipe == 1) {
4325 temp |= LVDS_PIPEB_SELECT;
4326 } else {
4327 temp &= ~LVDS_PIPEB_SELECT;
4328 }
4329 /* set the corresponsding LVDS_BORDER bit */
4330 temp |= dev_priv->lvds_border_bits;
4331 /* Set the B0-B3 data pairs corresponding to whether we're going to
4332 * set the DPLLs for dual-channel mode or not.
4333 */
4334 if (clock->p2 == 7)
4335 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4336 else
4337 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4338
4339 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4340 * appropriately here, but we need to look more thoroughly into how
4341 * panels behave in the two modes.
4342 */
4343 /* set the dithering flag on LVDS as needed */
4344 if (INTEL_INFO(dev)->gen >= 4) {
4345 if (dev_priv->lvds_dither)
4346 temp |= LVDS_ENABLE_DITHER;
4347 else
4348 temp &= ~LVDS_ENABLE_DITHER;
4349 }
284d5df5 4350 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4351 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4352 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4353 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4354 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4355 I915_WRITE(LVDS, temp);
4356}
4357
a0c4da24
JB		 4358static void vlv_update_pll(struct drm_crtc *crtc,
4359 struct drm_display_mode *mode,
4360 struct drm_display_mode *adjusted_mode,
4361 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4362 int num_connectors)
a0c4da24
JB		 4363{
4364 struct drm_device *dev = crtc->dev;
4365 struct drm_i915_private *dev_priv = dev->dev_private;
4366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4367 int pipe = intel_crtc->pipe;
4368 u32 dpll, mdiv, pdiv;
4369 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4370 bool is_sdvo;
4371 u32 temp;
a0c4da24 4372
2a8f64ca
VP		 4373 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4374 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4375
2a8f64ca
VP		 4376 dpll = DPLL_VGA_MODE_DIS;
4377 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4378 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4379 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4380
4381 I915_WRITE(DPLL(pipe), dpll);
4382 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4383
4384 bestn = clock->n;
4385 bestm1 = clock->m1;
4386 bestm2 = clock->m2;
4387 bestp1 = clock->p1;
4388 bestp2 = clock->p2;
4389
2a8f64ca
VP		 4390 /*
4391 * In Valleyview PLL and program lane counter registers are exposed
4392 * through DPIO interface
4393 */
a0c4da24
JB		 4394 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4395 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4396 mdiv |= ((bestn << DPIO_N_SHIFT));
4397 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4398 mdiv |= (1 << DPIO_K_SHIFT);
4399 mdiv |= DPIO_ENABLE_CALIBRATION;
4400 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4401
4402 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4403
2a8f64ca 4404 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4405 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4406 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4407 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4408 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4409
2a8f64ca 4410 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4411
4412 dpll |= DPLL_VCO_ENABLE;
4413 I915_WRITE(DPLL(pipe), dpll);
4414 POSTING_READ(DPLL(pipe));
4415 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4416 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4417
2a8f64ca
VP		 4418 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4419
4420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4421 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4422
4423 I915_WRITE(DPLL(pipe), dpll);
4424
4425 /* Wait for the clocks to stabilize. */
4426 POSTING_READ(DPLL(pipe));
4427 udelay(150);
a0c4da24 4428
2a8f64ca
VP		 4429 temp = 0;
4430 if (is_sdvo) {
4431 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4432 if (temp > 1)
4433 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4434 else
4435 temp = 0;
a0c4da24 4436 }
2a8f64ca
VP		 4437 I915_WRITE(DPLL_MD(pipe), temp);
4438 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4439
2a8f64ca
VP		 4440 /* Now program lane control registers */
4441 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4442 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4443 {
4444 temp = 0x1000C4;
4445 if(pipe == 1)
4446 temp |= (1 << 21);
4447 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4448 }
4449 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4450 {
4451 temp = 0x1000C4;
4452 if(pipe == 1)
4453 temp |= (1 << 21);
4454 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4455 }
a0c4da24
JB		 4456}
4457
eb1cbe48
DV		 4458static void i9xx_update_pll(struct drm_crtc *crtc,
4459 struct drm_display_mode *mode,
4460 struct drm_display_mode *adjusted_mode,
4461 intel_clock_t *clock, intel_clock_t *reduced_clock,
4462 int num_connectors)
4463{
4464 struct drm_device *dev = crtc->dev;
4465 struct drm_i915_private *dev_priv = dev->dev_private;
4466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4467 int pipe = intel_crtc->pipe;
4468 u32 dpll;
4469 bool is_sdvo;
4470
2a8f64ca
VP		 4471 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4472
eb1cbe48
DV		 4473 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4474 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4475
4476 dpll = DPLL_VGA_MODE_DIS;
4477
4478 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4479 dpll |= DPLLB_MODE_LVDS;
4480 else
4481 dpll |= DPLLB_MODE_DAC_SERIAL;
4482 if (is_sdvo) {
4483 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4484 if (pixel_multiplier > 1) {
4485 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4486 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4487 }
4488 dpll |= DPLL_DVO_HIGH_SPEED;
4489 }
4490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4491 dpll |= DPLL_DVO_HIGH_SPEED;
4492
4493 /* compute bitmask from p1 value */
4494 if (IS_PINEVIEW(dev))
4495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4496 else {
4497 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4498 if (IS_G4X(dev) && reduced_clock)
4499 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4500 }
4501 switch (clock->p2) {
4502 case 5:
4503 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4504 break;
4505 case 7:
4506 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4507 break;
4508 case 10:
4509 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4510 break;
4511 case 14:
4512 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4513 break;
4514 }
4515 if (INTEL_INFO(dev)->gen >= 4)
4516 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4517
4518 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4519 dpll |= PLL_REF_INPUT_TVCLKINBC;
4520 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4521 /* XXX: just matching BIOS for now */
4522 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4523 dpll |= 3;
4524 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4525 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4526 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4527 else
4528 dpll |= PLL_REF_INPUT_DREFCLK;
4529
4530 dpll |= DPLL_VCO_ENABLE;
4531 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4532 POSTING_READ(DPLL(pipe));
4533 udelay(150);
4534
4535 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4536 * This is an exception to the general rule that mode_set doesn't turn
4537 * things on.
4538 */
4539 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4540 intel_update_lvds(crtc, clock, adjusted_mode);
4541
4542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4543 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4544
4545 I915_WRITE(DPLL(pipe), dpll);
4546
4547 /* Wait for the clocks to stabilize. */
4548 POSTING_READ(DPLL(pipe));
4549 udelay(150);
4550
4551 if (INTEL_INFO(dev)->gen >= 4) {
4552 u32 temp = 0;
4553 if (is_sdvo) {
4554 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4555 if (temp > 1)
4556 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4557 else
4558 temp = 0;
4559 }
4560 I915_WRITE(DPLL_MD(pipe), temp);
4561 } else {
4562 /* The pixel multiplier can only be updated once the
4563 * DPLL is enabled and the clocks are stable.
4564 *
4565 * So write it again.
4566 */
4567 I915_WRITE(DPLL(pipe), dpll);
4568 }
4569}
4570
4571static void i8xx_update_pll(struct drm_crtc *crtc,
4572 struct drm_display_mode *adjusted_mode,
2a8f64ca 4573 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4574 int num_connectors)
4575{
4576 struct drm_device *dev = crtc->dev;
4577 struct drm_i915_private *dev_priv = dev->dev_private;
4578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4579 int pipe = intel_crtc->pipe;
4580 u32 dpll;
4581
2a8f64ca
VP		 4582 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4583
eb1cbe48
DV		 4584 dpll = DPLL_VGA_MODE_DIS;
4585
4586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4587 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4588 } else {
4589 if (clock->p1 == 2)
4590 dpll |= PLL_P1_DIVIDE_BY_TWO;
4591 else
4592 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4593 if (clock->p2 == 4)
4594 dpll |= PLL_P2_DIVIDE_BY_4;
4595 }
4596
4597 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4598 /* XXX: just matching BIOS for now */
4599 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4600 dpll |= 3;
4601 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4602 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4603 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4604 else
4605 dpll |= PLL_REF_INPUT_DREFCLK;
4606
4607 dpll |= DPLL_VCO_ENABLE;
4608 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4609 POSTING_READ(DPLL(pipe));
4610 udelay(150);
4611
eb1cbe48
DV		 4612 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4613 * This is an exception to the general rule that mode_set doesn't turn
4614 * things on.
4615 */
4616 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4617 intel_update_lvds(crtc, clock, adjusted_mode);
4618
5b5896e4
DV		 4619 I915_WRITE(DPLL(pipe), dpll);
4620
4621 /* Wait for the clocks to stabilize. */
4622 POSTING_READ(DPLL(pipe));
4623 udelay(150);
4624
eb1cbe48
DV		 4625 /* The pixel multiplier can only be updated once the
4626 * DPLL is enabled and the clocks are stable.
4627 *
4628 * So write it again.
4629 */
4630 I915_WRITE(DPLL(pipe), dpll);
4631}
4632
b0e77b9c
PZ		 4633static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4634 struct drm_display_mode *mode,
4635 struct drm_display_mode *adjusted_mode)
4636{
4637 struct drm_device *dev = intel_crtc->base.dev;
4638 struct drm_i915_private *dev_priv = dev->dev_private;
4639 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4640 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4641 uint32_t vsyncshift;
4642
4643 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4644 /* the chip adds 2 halflines automatically */
4645 adjusted_mode->crtc_vtotal -= 1;
4646 adjusted_mode->crtc_vblank_end -= 1;
4647 vsyncshift = adjusted_mode->crtc_hsync_start
4648 - adjusted_mode->crtc_htotal / 2;
4649 } else {
4650 vsyncshift = 0;
4651 }
4652
4653 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4654 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4655
fe2b8f9d 4656 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4657 (adjusted_mode->crtc_hdisplay - 1) |
4658 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4659 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4660 (adjusted_mode->crtc_hblank_start - 1) |
4661 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4662 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4663 (adjusted_mode->crtc_hsync_start - 1) |
4664 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4665
fe2b8f9d 4666 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4667 (adjusted_mode->crtc_vdisplay - 1) |
4668 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4669 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4670 (adjusted_mode->crtc_vblank_start - 1) |
4671 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4672 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4673 (adjusted_mode->crtc_vsync_start - 1) |
4674 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4675
b5e508d4
PZ		 4676 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4677 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4678 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4679 * bits. */
4680 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4681 (pipe == PIPE_B || pipe == PIPE_C))
4682 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4683
b0e77b9c
PZ		 4684 /* pipesrc controls the size that is scaled from, which should
4685 * always be the user's requested size.
4686 */
4687 I915_WRITE(PIPESRC(pipe),
4688 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4689}
4690
f564048e
EA		 4691static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4692 struct drm_display_mode *mode,
4693 struct drm_display_mode *adjusted_mode,
4694 int x, int y,
94352cf9 4695 struct drm_framebuffer *fb)
79e53945
JB		 4696{
4697 struct drm_device *dev = crtc->dev;
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4700 int pipe = intel_crtc->pipe;
80824003 4701 int plane = intel_crtc->plane;
c751ce4f 4702 int refclk, num_connectors = 0;
652c393a 4703 intel_clock_t clock, reduced_clock;
b0e77b9c 4704 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4705 bool ok, has_reduced_clock = false, is_sdvo = false;
4706 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4707 struct intel_encoder *encoder;
d4906093 4708 const intel_limit_t *limit;
5c3b82e2 4709 int ret;
79e53945 4710
6c2b7c12 4711 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4712 switch (encoder->type) {
79e53945
JB		 4713 case INTEL_OUTPUT_LVDS:
4714 is_lvds = true;
4715 break;
4716 case INTEL_OUTPUT_SDVO:
7d57382e 4717 case INTEL_OUTPUT_HDMI:
79e53945 4718 is_sdvo = true;
5eddb70b 4719 if (encoder->needs_tv_clock)
e2f0ba97 4720 is_tv = true;
79e53945 4721 break;
79e53945
JB		 4722 case INTEL_OUTPUT_TVOUT:
4723 is_tv = true;
4724 break;
a4fc5ed6
KP		 4725 case INTEL_OUTPUT_DISPLAYPORT:
4726 is_dp = true;
4727 break;
79e53945 4728 }
43565a06 4729
c751ce4f 4730 num_connectors++;
79e53945
JB		 4731 }
4732
c65d77d8 4733 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4734
d4906093
ML		 4735 /*
4736 * Returns a set of divisors for the desired target clock with the given
4737 * refclk, or FALSE. The returned values represent the clock equation:
4738 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4739 */
1b894b59 4740 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4741 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4742 &clock);
79e53945
JB		 4743 if (!ok) {
4744 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4745 return -EINVAL;
79e53945
JB		 4746 }
4747
cda4b7d3 4748 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4749 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4750
ddc9003c 4751 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4752 /*
4753 * Ensure we match the reduced clock's P to the target clock.
4754 * If the clocks don't match, we can't switch the display clock
4755 * by using the FP0/FP1. In such case we will disable the LVDS
4756 * downclock feature.
4757 */
ddc9003c 4758 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4759 dev_priv->lvds_downclock,
4760 refclk,
cec2f356 4761 &clock,
5eddb70b 4762 &reduced_clock);
7026d4ac
ZW		 4763 }
4764
c65d77d8
JB		 4765 if (is_sdvo && is_tv)
4766 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4767
eb1cbe48 4768 if (IS_GEN2(dev))
2a8f64ca
VP		 4769 i8xx_update_pll(crtc, adjusted_mode, &clock,
4770 has_reduced_clock ? &reduced_clock : NULL,
4771 num_connectors);
a0c4da24 4772 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4773 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4774 has_reduced_clock ? &reduced_clock : NULL,
4775 num_connectors);
79e53945 4776 else
eb1cbe48
DV		 4777 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4778 has_reduced_clock ? &reduced_clock : NULL,
4779 num_connectors);
79e53945
JB		 4780
4781 /* setup pipeconf */
5eddb70b 4782 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4783
4784 /* Set up the display plane register */
4785 dspcntr = DISPPLANE_GAMMA_ENABLE;
4786
929c77fb
EA		 4787 if (pipe == 0)
4788 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4789 else
4790 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4791
a6c45cf0 4792 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4793 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4794 * core speed.
4795 *
4796 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4797 * pipe == 0 check?
4798 */
e70236a8
JB		 4799 if (mode->clock >
4800 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4801 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4802 else
5eddb70b 4803 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4804 }
4805
3b5c78a3
AJ		 4806 /* default to 8bpc */
4807 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4808 if (is_dp) {
0c96c65b 4809 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4810 pipeconf |= PIPECONF_BPP_6 |
4811 PIPECONF_DITHER_EN |
4812 PIPECONF_DITHER_TYPE_SP;
4813 }
4814 }
4815
19c03924
GB		 4816 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4817 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4818 pipeconf |= PIPECONF_BPP_6 |
4819 PIPECONF_ENABLE |
4820 I965_PIPECONF_ACTIVE;
4821 }
4822 }
4823
28c97730 4824 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4825 drm_mode_debug_printmodeline(mode);
4826
a7516a05
JB		 4827 if (HAS_PIPE_CXSR(dev)) {
4828 if (intel_crtc->lowfreq_avail) {
28c97730 4829 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4830 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4831 } else {
28c97730 4832 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4833 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4834 }
4835 }
4836
617cf884 4837 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4838 if (!IS_GEN2(dev) &&
b0e77b9c 4839 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4840 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4841 else
617cf884 4842 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4843
b0e77b9c 4844 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4845
4846 /* pipesrc and dspsize control the size that is scaled from,
4847 * which should always be the user's requested size.
79e53945 4848 */
929c77fb
EA		 4849 I915_WRITE(DSPSIZE(plane),
4850 ((mode->vdisplay - 1) << 16) |
4851 (mode->hdisplay - 1));
4852 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4853
f564048e
EA		 4854 I915_WRITE(PIPECONF(pipe), pipeconf);
4855 POSTING_READ(PIPECONF(pipe));
929c77fb 4856 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4857
4858 intel_wait_for_vblank(dev, pipe);
4859
f564048e
EA		 4860 I915_WRITE(DSPCNTR(plane), dspcntr);
4861 POSTING_READ(DSPCNTR(plane));
4862
94352cf9 4863 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4864
4865 intel_update_watermarks(dev);
4866
f564048e
EA		 4867 return ret;
4868}
4869
9fb526db
KP		 4870/*
4871 * Initialize reference clocks when the driver loads
4872 */
4873void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4874{
4875 struct drm_i915_private *dev_priv = dev->dev_private;
4876 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4877 struct intel_encoder *encoder;
13d83a67
JB		 4878 u32 temp;
4879 bool has_lvds = false;
199e5d79
KP		 4880 bool has_cpu_edp = false;
4881 bool has_pch_edp = false;
4882 bool has_panel = false;
99eb6a01
KP		 4883 bool has_ck505 = false;
4884 bool can_ssc = false;
13d83a67
JB		 4885
4886 /* We need to take the global config into account */
199e5d79
KP		 4887 list_for_each_entry(encoder, &mode_config->encoder_list,
4888 base.head) {
4889 switch (encoder->type) {
4890 case INTEL_OUTPUT_LVDS:
4891 has_panel = true;
4892 has_lvds = true;
4893 break;
4894 case INTEL_OUTPUT_EDP:
4895 has_panel = true;
4896 if (intel_encoder_is_pch_edp(&encoder->base))
4897 has_pch_edp = true;
4898 else
4899 has_cpu_edp = true;
4900 break;
13d83a67
JB		 4901 }
4902 }
4903
99eb6a01
KP		 4904 if (HAS_PCH_IBX(dev)) {
4905 has_ck505 = dev_priv->display_clock_mode;
4906 can_ssc = has_ck505;
4907 } else {
4908 has_ck505 = false;
4909 can_ssc = true;
4910 }
4911
4912 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4913 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4914 has_ck505);
13d83a67
JB		 4915
4916 /* Ironlake: try to setup display ref clock before DPLL
4917 * enabling. This is only under driver's control after
4918 * PCH B stepping, previous chipset stepping should be
4919 * ignoring this setting.
4920 */
4921 temp = I915_READ(PCH_DREF_CONTROL);
4922 /* Always enable nonspread source */
4923 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4924
99eb6a01
KP		 4925 if (has_ck505)
4926 temp |= DREF_NONSPREAD_CK505_ENABLE;
4927 else
4928 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4929
199e5d79
KP		 4930 if (has_panel) {
4931 temp &= ~DREF_SSC_SOURCE_MASK;
4932 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4933
199e5d79 4934 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4935 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4936 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4937 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4938 } else
4939 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4940
4941 /* Get SSC going before enabling the outputs */
4942 I915_WRITE(PCH_DREF_CONTROL, temp);
4943 POSTING_READ(PCH_DREF_CONTROL);
4944 udelay(200);
4945
13d83a67
JB		 4946 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4947
4948 /* Enable CPU source on CPU attached eDP */
199e5d79 4949 if (has_cpu_edp) {
99eb6a01 4950 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4951 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4952 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4953 }
13d83a67
JB		 4954 else
4955 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4956 } else
4957 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4958
4959 I915_WRITE(PCH_DREF_CONTROL, temp);
4960 POSTING_READ(PCH_DREF_CONTROL);
4961 udelay(200);
4962 } else {
4963 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4964
4965 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4966
4967 /* Turn off CPU output */
4968 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4969
4970 I915_WRITE(PCH_DREF_CONTROL, temp);
4971 POSTING_READ(PCH_DREF_CONTROL);
4972 udelay(200);
4973
4974 /* Turn off the SSC source */
4975 temp &= ~DREF_SSC_SOURCE_MASK;
4976 temp |= DREF_SSC_SOURCE_DISABLE;
4977
4978 /* Turn off SSC1 */
4979 temp &= ~ DREF_SSC1_ENABLE;
4980
13d83a67
JB		 4981 I915_WRITE(PCH_DREF_CONTROL, temp);
4982 POSTING_READ(PCH_DREF_CONTROL);
4983 udelay(200);
4984 }
4985}
4986
d9d444cb
JB		 4987static int ironlake_get_refclk(struct drm_crtc *crtc)
4988{
4989 struct drm_device *dev = crtc->dev;
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 struct intel_encoder *encoder;
d9d444cb
JB		 4992 struct intel_encoder *edp_encoder = NULL;
4993 int num_connectors = 0;
4994 bool is_lvds = false;
4995
6c2b7c12 4996 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4997 switch (encoder->type) {
4998 case INTEL_OUTPUT_LVDS:
4999 is_lvds = true;
5000 break;
5001 case INTEL_OUTPUT_EDP:
5002 edp_encoder = encoder;
5003 break;
5004 }
5005 num_connectors++;
5006 }
5007
5008 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5009 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5010 dev_priv->lvds_ssc_freq);
5011 return dev_priv->lvds_ssc_freq * 1000;
5012 }
5013
5014 return 120000;
5015}
5016
c8203565 5017static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5018 struct drm_display_mode *adjusted_mode,
c8203565 5019 bool dither)
79e53945 5020{
c8203565 5021 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5023 int pipe = intel_crtc->pipe;
c8203565
PZ		 5024 uint32_t val;
5025
5026 val = I915_READ(PIPECONF(pipe));
5027
5028 val &= ~PIPE_BPC_MASK;
5029 switch (intel_crtc->bpp) {
5030 case 18:
5031 val |= PIPE_6BPC;
5032 break;
5033 case 24:
5034 val |= PIPE_8BPC;
5035 break;
5036 case 30:
5037 val |= PIPE_10BPC;
5038 break;
5039 case 36:
5040 val |= PIPE_12BPC;
5041 break;
5042 default:
cc769b62
PZ		 5043 /* Case prevented by intel_choose_pipe_bpp_dither. */
5044 BUG();
c8203565
PZ		 5045 }
5046
5047 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5048 if (dither)
5049 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5050
5051 val &= ~PIPECONF_INTERLACE_MASK;
5052 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5053 val |= PIPECONF_INTERLACED_ILK;
5054 else
5055 val |= PIPECONF_PROGRESSIVE;
5056
5057 I915_WRITE(PIPECONF(pipe), val);
5058 POSTING_READ(PIPECONF(pipe));
5059}
5060
ee2b0b38
PZ		 5061static void haswell_set_pipeconf(struct drm_crtc *crtc,
5062 struct drm_display_mode *adjusted_mode,
5063 bool dither)
5064{
5065 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5067 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5068 uint32_t val;
5069
702e7a56 5070 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5071
5072 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5073 if (dither)
5074 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5075
5076 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5077 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5078 val |= PIPECONF_INTERLACED_ILK;
5079 else
5080 val |= PIPECONF_PROGRESSIVE;
5081
702e7a56
PZ		 5082 I915_WRITE(PIPECONF(cpu_transcoder), val);
5083 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5084}
5085
6591c6e4
PZ		 5086static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5087 struct drm_display_mode *adjusted_mode,
5088 intel_clock_t *clock,
5089 bool *has_reduced_clock,
5090 intel_clock_t *reduced_clock)
5091{
5092 struct drm_device *dev = crtc->dev;
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct intel_encoder *intel_encoder;
5095 int refclk;
d4906093 5096 const intel_limit_t *limit;
6591c6e4 5097 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5098
6591c6e4
PZ		 5099 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5100 switch (intel_encoder->type) {
79e53945
JB		 5101 case INTEL_OUTPUT_LVDS:
5102 is_lvds = true;
5103 break;
5104 case INTEL_OUTPUT_SDVO:
7d57382e 5105 case INTEL_OUTPUT_HDMI:
79e53945 5106 is_sdvo = true;
6591c6e4 5107 if (intel_encoder->needs_tv_clock)
e2f0ba97 5108 is_tv = true;
79e53945 5109 break;
79e53945
JB		 5110 case INTEL_OUTPUT_TVOUT:
5111 is_tv = true;
5112 break;
79e53945
JB		 5113 }
5114 }
5115
d9d444cb 5116 refclk = ironlake_get_refclk(crtc);
79e53945 5117
d4906093
ML		 5118 /*
5119 * Returns a set of divisors for the desired target clock with the given
5120 * refclk, or FALSE. The returned values represent the clock equation:
5121 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5122 */
1b894b59 5123 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5124 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5125 clock);
5126 if (!ret)
5127 return false;
cda4b7d3 5128
ddc9003c 5129 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5130 /*
5131 * Ensure we match the reduced clock's P to the target clock.
5132 * If the clocks don't match, we can't switch the display clock
5133 * by using the FP0/FP1. In such case we will disable the LVDS
5134 * downclock feature.
5135 */
6591c6e4
PZ		 5136 *has_reduced_clock = limit->find_pll(limit, crtc,
5137 dev_priv->lvds_downclock,
5138 refclk,
5139 clock,
5140 reduced_clock);
652c393a 5141 }
61e9653f
DV		 5142
5143 if (is_sdvo && is_tv)
6591c6e4
PZ		 5144 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5145
5146 return true;
5147}
5148
01a415fd
DV		 5149static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5150{
5151 struct drm_i915_private *dev_priv = dev->dev_private;
5152 uint32_t temp;
5153
5154 temp = I915_READ(SOUTH_CHICKEN1);
5155 if (temp & FDI_BC_BIFURCATION_SELECT)
5156 return;
5157
5158 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5159 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5160
5161 temp |= FDI_BC_BIFURCATION_SELECT;
5162 DRM_DEBUG_KMS("enabling fdi C rx\n");
5163 I915_WRITE(SOUTH_CHICKEN1, temp);
5164 POSTING_READ(SOUTH_CHICKEN1);
5165}
5166
5167static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5168{
5169 struct drm_device *dev = intel_crtc->base.dev;
5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171 struct intel_crtc *pipe_B_crtc =
5172 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5173
5174 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5175 intel_crtc->pipe, intel_crtc->fdi_lanes);
5176 if (intel_crtc->fdi_lanes > 4) {
5177 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5178 intel_crtc->pipe, intel_crtc->fdi_lanes);
5179 /* Clamp lanes to avoid programming the hw with bogus values. */
5180 intel_crtc->fdi_lanes = 4;
5181
5182 return false;
5183 }
5184
5185 if (dev_priv->num_pipe == 2)
5186 return true;
5187
5188 switch (intel_crtc->pipe) {
5189 case PIPE_A:
5190 return true;
5191 case PIPE_B:
5192 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5193 intel_crtc->fdi_lanes > 2) {
5194 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5195 intel_crtc->pipe, intel_crtc->fdi_lanes);
5196 /* Clamp lanes to avoid programming the hw with bogus values. */
5197 intel_crtc->fdi_lanes = 2;
5198
5199 return false;
5200 }
5201
5202 if (intel_crtc->fdi_lanes > 2)
5203 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5204 else
5205 cpt_enable_fdi_bc_bifurcation(dev);
5206
5207 return true;
5208 case PIPE_C:
5209 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5210 if (intel_crtc->fdi_lanes > 2) {
5211 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5212 intel_crtc->pipe, intel_crtc->fdi_lanes);
5213 /* Clamp lanes to avoid programming the hw with bogus values. */
5214 intel_crtc->fdi_lanes = 2;
5215
5216 return false;
5217 }
5218 } else {
5219 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5220 return false;
5221 }
5222
5223 cpt_enable_fdi_bc_bifurcation(dev);
5224
5225 return true;
5226 default:
5227 BUG();
5228 }
5229}
5230
f48d8f23
PZ		 5231static void ironlake_set_m_n(struct drm_crtc *crtc,
5232 struct drm_display_mode *mode,
5233 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5234{
5235 struct drm_device *dev = crtc->dev;
5236 struct drm_i915_private *dev_priv = dev->dev_private;
5237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5238 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5239 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
2c07245f 5240 struct fdi_m_n m_n = {0};
f48d8f23
PZ		 5241 int target_clock, pixel_multiplier, lane, link_bw;
5242 bool is_dp = false, is_cpu_edp = false;
79e53945 5243
f48d8f23
PZ		 5244 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5245 switch (intel_encoder->type) {
a4fc5ed6
KP		 5246 case INTEL_OUTPUT_DISPLAYPORT:
5247 is_dp = true;
5248 break;
32f9d658 5249 case INTEL_OUTPUT_EDP:
e3aef172 5250 is_dp = true;
f48d8f23 5251 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5252 is_cpu_edp = true;
f48d8f23 5253 edp_encoder = intel_encoder;
32f9d658 5254 break;
79e53945 5255 }
79e53945 5256 }
61e9653f 5257
2c07245f 5258 /* FDI link */
8febb297
EA		 5259 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5260 lane = 0;
5261 /* CPU eDP doesn't require FDI link, so just set DP M/N
5262 according to current link config */
e3aef172 5263 if (is_cpu_edp) {
e3aef172 5264 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5265 } else {
8febb297
EA		 5266 /* FDI is a binary signal running at ~2.7GHz, encoding
5267 * each output octet as 10 bits. The actual frequency
5268 * is stored as a divider into a 100MHz clock, and the
5269 * mode pixel clock is stored in units of 1KHz.
5270 * Hence the bw of each lane in terms of the mode signal
5271 * is:
5272 */
5273 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5274 }
58a27471 5275
94bf2ced
DV		 5276 /* [e]DP over FDI requires target mode clock instead of link clock. */
5277 if (edp_encoder)
5278 target_clock = intel_edp_target_clock(edp_encoder, mode);
5279 else if (is_dp)
5280 target_clock = mode->clock;
5281 else
5282 target_clock = adjusted_mode->clock;
5283
8febb297
EA		 5284 if (!lane) {
5285 /*
5286 * Account for spread spectrum to avoid
5287 * oversubscribing the link. Max center spread
5288 * is 2.5%; use 5% for safety's sake.
5289 */
5a354204 5290 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5291 lane = bps / (link_bw * 8) + 1;
5eb08b69 5292 }
2c07245f 5293
8febb297
EA		 5294 intel_crtc->fdi_lanes = lane;
5295
5296 if (pixel_multiplier > 1)
5297 link_bw *= pixel_multiplier;
5a354204
JB		 5298 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5299 &m_n);
8febb297 5300
afe2fcf5
PZ		 5301 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5302 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5303 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5304 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5305}
5306
de13a2e3
PZ		 5307static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5308 struct drm_display_mode *adjusted_mode,
5309 intel_clock_t *clock, u32 fp)
79e53945 5310{
de13a2e3 5311 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5312 struct drm_device *dev = crtc->dev;
5313 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5314 struct intel_encoder *intel_encoder;
5315 uint32_t dpll;
5316 int factor, pixel_multiplier, num_connectors = 0;
5317 bool is_lvds = false, is_sdvo = false, is_tv = false;
5318 bool is_dp = false, is_cpu_edp = false;
79e53945 5319
de13a2e3
PZ		 5320 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5321 switch (intel_encoder->type) {
79e53945
JB		 5322 case INTEL_OUTPUT_LVDS:
5323 is_lvds = true;
5324 break;
5325 case INTEL_OUTPUT_SDVO:
7d57382e 5326 case INTEL_OUTPUT_HDMI:
79e53945 5327 is_sdvo = true;
de13a2e3 5328 if (intel_encoder->needs_tv_clock)
e2f0ba97 5329 is_tv = true;
79e53945 5330 break;
79e53945
JB		 5331 case INTEL_OUTPUT_TVOUT:
5332 is_tv = true;
5333 break;
a4fc5ed6
KP		 5334 case INTEL_OUTPUT_DISPLAYPORT:
5335 is_dp = true;
5336 break;
32f9d658 5337 case INTEL_OUTPUT_EDP:
e3aef172 5338 is_dp = true;
de13a2e3 5339 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5340 is_cpu_edp = true;
32f9d658 5341 break;
79e53945 5342 }
43565a06 5343
c751ce4f 5344 num_connectors++;
79e53945 5345 }
79e53945 5346
c1858123 5347 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5348 factor = 21;
5349 if (is_lvds) {
5350 if ((intel_panel_use_ssc(dev_priv) &&
5351 dev_priv->lvds_ssc_freq == 100) ||
5352 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5353 factor = 25;
5354 } else if (is_sdvo && is_tv)
5355 factor = 20;
c1858123 5356
de13a2e3 5357 if (clock->m < factor * clock->n)
8febb297 5358 fp |= FP_CB_TUNE;
2c07245f 5359
5eddb70b 5360 dpll = 0;
2c07245f 5361
a07d6787
EA		 5362 if (is_lvds)
5363 dpll |= DPLLB_MODE_LVDS;
5364 else
5365 dpll |= DPLLB_MODE_DAC_SERIAL;
5366 if (is_sdvo) {
de13a2e3 5367 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5368 if (pixel_multiplier > 1) {
5369 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5370 }
a07d6787
EA		 5371 dpll |= DPLL_DVO_HIGH_SPEED;
5372 }
e3aef172 5373 if (is_dp && !is_cpu_edp)
a07d6787 5374 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5375
a07d6787 5376 /* compute bitmask from p1 value */
de13a2e3 5377 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5378 /* also FPA1 */
de13a2e3 5379 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5380
de13a2e3 5381 switch (clock->p2) {
a07d6787
EA		 5382 case 5:
5383 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5384 break;
5385 case 7:
5386 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5387 break;
5388 case 10:
5389 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5390 break;
5391 case 14:
5392 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5393 break;
79e53945
JB		 5394 }
5395
43565a06
KH		 5396 if (is_sdvo && is_tv)
5397 dpll |= PLL_REF_INPUT_TVCLKINBC;
5398 else if (is_tv)
79e53945 5399 /* XXX: just matching BIOS for now */
43565a06 5400 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5401 dpll |= 3;
a7615030 5402 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5403 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5404 else
5405 dpll |= PLL_REF_INPUT_DREFCLK;
5406
de13a2e3
PZ		 5407 return dpll;
5408}
5409
5410static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5411 struct drm_display_mode *mode,
5412 struct drm_display_mode *adjusted_mode,
5413 int x, int y,
5414 struct drm_framebuffer *fb)
5415{
5416 struct drm_device *dev = crtc->dev;
5417 struct drm_i915_private *dev_priv = dev->dev_private;
5418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5419 int pipe = intel_crtc->pipe;
5420 int plane = intel_crtc->plane;
5421 int num_connectors = 0;
5422 intel_clock_t clock, reduced_clock;
5423 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5424 bool ok, has_reduced_clock = false;
5425 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5426 struct intel_encoder *encoder;
5427 u32 temp;
5428 int ret;
01a415fd 5429 bool dither, fdi_config_ok;
de13a2e3
PZ		 5430
5431 for_each_encoder_on_crtc(dev, crtc, encoder) {
5432 switch (encoder->type) {
5433 case INTEL_OUTPUT_LVDS:
5434 is_lvds = true;
5435 break;
de13a2e3
PZ		 5436 case INTEL_OUTPUT_DISPLAYPORT:
5437 is_dp = true;
5438 break;
5439 case INTEL_OUTPUT_EDP:
5440 is_dp = true;
e2f12b07 5441 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5442 is_cpu_edp = true;
5443 break;
5444 }
5445
5446 num_connectors++;
a07d6787 5447 }
79e53945 5448
5dc5298b
PZ		 5449 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5450 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5451
de13a2e3
PZ		 5452 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5453 &has_reduced_clock, &reduced_clock);
5454 if (!ok) {
5455 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5456 return -EINVAL;
79e53945
JB		 5457 }
5458
de13a2e3
PZ		 5459 /* Ensure that the cursor is valid for the new mode before changing... */
5460 intel_crtc_update_cursor(crtc, true);
5461
5462 /* determine panel color depth */
c8241969
JN		 5463 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5464 adjusted_mode);
de13a2e3
PZ		 5465 if (is_lvds && dev_priv->lvds_dither)
5466 dither = true;
5467
5468 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5469 if (has_reduced_clock)
5470 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5471 reduced_clock.m2;
5472
5473 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5474
f7cb34d4 5475 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5476 drm_mode_debug_printmodeline(mode);
5477
5dc5298b
PZ		 5478 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5479 if (!is_cpu_edp) {
ee7b9f93 5480 struct intel_pch_pll *pll;
4b645f14 5481
ee7b9f93
JB		 5482 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5483 if (pll == NULL) {
5484 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5485 pipe);
4b645f14
JB		 5486 return -EINVAL;
5487 }
ee7b9f93
JB		 5488 } else
5489 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5490
5491 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5492 * This is an exception to the general rule that mode_set doesn't turn
5493 * things on.
5494 */
5495 if (is_lvds) {
fae14981 5496 temp = I915_READ(PCH_LVDS);
5eddb70b 5497 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5498 if (HAS_PCH_CPT(dev)) {
5499 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5500 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5501 } else {
5502 if (pipe == 1)
5503 temp |= LVDS_PIPEB_SELECT;
5504 else
5505 temp &= ~LVDS_PIPEB_SELECT;
5506 }
4b645f14 5507
a3e17eb8 5508 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5509 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5510 /* Set the B0-B3 data pairs corresponding to whether we're going to
5511 * set the DPLLs for dual-channel mode or not.
5512 */
5513 if (clock.p2 == 7)
5eddb70b 5514 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5515 else
5eddb70b 5516 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5517
5518 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5519 * appropriately here, but we need to look more thoroughly into how
5520 * panels behave in the two modes.
5521 */
284d5df5 5522 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5523 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5524 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5525 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5526 temp |= LVDS_VSYNC_POLARITY;
fae14981 5527 I915_WRITE(PCH_LVDS, temp);
79e53945 5528 }
434ed097 5529
e3aef172 5530 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5531 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5532 } else {
8db9d77b 5533 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5534 I915_WRITE(TRANSDATA_M1(pipe), 0);
5535 I915_WRITE(TRANSDATA_N1(pipe), 0);
5536 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5537 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5538 }
79e53945 5539
ee7b9f93
JB		 5540 if (intel_crtc->pch_pll) {
5541 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5542
32f9d658 5543 /* Wait for the clocks to stabilize. */
ee7b9f93 5544 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5545 udelay(150);
5546
8febb297
EA		 5547 /* The pixel multiplier can only be updated once the
5548 * DPLL is enabled and the clocks are stable.
5549 *
5550 * So write it again.
5551 */
ee7b9f93 5552 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5553 }
79e53945 5554
5eddb70b 5555 intel_crtc->lowfreq_avail = false;
ee7b9f93 5556 if (intel_crtc->pch_pll) {
4b645f14 5557 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5558 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5559 intel_crtc->lowfreq_avail = true;
4b645f14 5560 } else {
ee7b9f93 5561 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5562 }
5563 }
5564
b0e77b9c 5565 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5566
01a415fd
DV		 5567 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5568 * ironlake_check_fdi_lanes. */
f48d8f23 5569 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5570
01a415fd 5571 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5572
e3aef172 5573 if (is_cpu_edp)
8febb297 5574 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5575
c8203565 5576 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5577
9d0498a2 5578 intel_wait_for_vblank(dev, pipe);
79e53945 5579
a1f9e77e
PZ		 5580 /* Set up the display plane register */
5581 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5582 POSTING_READ(DSPCNTR(plane));
79e53945 5583
94352cf9 5584 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5585
5586 intel_update_watermarks(dev);
5587
1f8eeabf
ED		 5588 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5589
01a415fd 5590 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5591}
5592
09b4ddf9
PZ		 5593static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5594 struct drm_display_mode *mode,
5595 struct drm_display_mode *adjusted_mode,
5596 int x, int y,
5597 struct drm_framebuffer *fb)
5598{
5599 struct drm_device *dev = crtc->dev;
5600 struct drm_i915_private *dev_priv = dev->dev_private;
5601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5602 int pipe = intel_crtc->pipe;
5603 int plane = intel_crtc->plane;
5604 int num_connectors = 0;
5605 intel_clock_t clock, reduced_clock;
5dc5298b 5606 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5607 bool ok, has_reduced_clock = false;
5608 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5609 struct intel_encoder *encoder;
5610 u32 temp;
5611 int ret;
5612 bool dither;
5613
5614 for_each_encoder_on_crtc(dev, crtc, encoder) {
5615 switch (encoder->type) {
5616 case INTEL_OUTPUT_LVDS:
5617 is_lvds = true;
5618 break;
5619 case INTEL_OUTPUT_DISPLAYPORT:
5620 is_dp = true;
5621 break;
5622 case INTEL_OUTPUT_EDP:
5623 is_dp = true;
5624 if (!intel_encoder_is_pch_edp(&encoder->base))
5625 is_cpu_edp = true;
5626 break;
5627 }
5628
5629 num_connectors++;
5630 }
5631
a5c961d1
PZ		 5632 if (is_cpu_edp)
5633 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5634 else
5635 intel_crtc->cpu_transcoder = pipe;
5636
5dc5298b
PZ		 5637 /* We are not sure yet this won't happen. */
5638 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5639 INTEL_PCH_TYPE(dev));
5640
5641 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5642 num_connectors, pipe_name(pipe));
5643
702e7a56 5644 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5645 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5646
5647 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5648
6441ab5f
PZ		 5649 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5650 return -EINVAL;
5651
5dc5298b
PZ		 5652 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5653 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5654 &has_reduced_clock,
5655 &reduced_clock);
5656 if (!ok) {
5657 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5658 return -EINVAL;
5659 }
09b4ddf9
PZ		 5660 }
5661
5662 /* Ensure that the cursor is valid for the new mode before changing... */
5663 intel_crtc_update_cursor(crtc, true);
5664
5665 /* determine panel color depth */
c8241969
JN		 5666 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5667 adjusted_mode);
09b4ddf9
PZ		 5668 if (is_lvds && dev_priv->lvds_dither)
5669 dither = true;
5670
09b4ddf9
PZ		 5671 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5672 drm_mode_debug_printmodeline(mode);
5673
5dc5298b
PZ		 5674 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5675 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5676 if (has_reduced_clock)
5677 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5678 reduced_clock.m2;
5679
5680 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5681 fp);
5682
5683 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5684 * own on pre-Haswell/LPT generation */
5685 if (!is_cpu_edp) {
5686 struct intel_pch_pll *pll;
5687
5688 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5689 if (pll == NULL) {
5690 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5691 pipe);
5692 return -EINVAL;
5693 }
5694 } else
5695 intel_put_pch_pll(intel_crtc);
09b4ddf9 5696
5dc5298b
PZ		 5697 /* The LVDS pin pair needs to be on before the DPLLs are
5698 * enabled. This is an exception to the general rule that
5699 * mode_set doesn't turn things on.
5700 */
5701 if (is_lvds) {
5702 temp = I915_READ(PCH_LVDS);
5703 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5704 if (HAS_PCH_CPT(dev)) {
5705 temp &= ~PORT_TRANS_SEL_MASK;
5706 temp |= PORT_TRANS_SEL_CPT(pipe);
5707 } else {
5708 if (pipe == 1)
5709 temp |= LVDS_PIPEB_SELECT;
5710 else
5711 temp &= ~LVDS_PIPEB_SELECT;
5712 }
09b4ddf9 5713
5dc5298b
PZ		 5714 /* set the corresponsding LVDS_BORDER bit */
5715 temp |= dev_priv->lvds_border_bits;
5716 /* Set the B0-B3 data pairs corresponding to whether
5717 * we're going to set the DPLLs for dual-channel mode or
5718 * not.
5719 */
5720 if (clock.p2 == 7)
5721 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5722 else
5dc5298b
PZ		 5723 temp &= ~(LVDS_B0B3_POWER_UP |
5724 LVDS_CLKB_POWER_UP);
5725
5726 /* It would be nice to set 24 vs 18-bit mode
5727 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5728 * look more thoroughly into how panels behave in the
5729 * two modes.
5730 */
5731 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5732 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5733 temp |= LVDS_HSYNC_POLARITY;
5734 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5735 temp |= LVDS_VSYNC_POLARITY;
5736 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5737 }
09b4ddf9
PZ		 5738 }
5739
5740 if (is_dp && !is_cpu_edp) {
5741 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5742 } else {
5dc5298b
PZ		 5743 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5744 /* For non-DP output, clear any trans DP clock recovery
5745 * setting.*/
5746 I915_WRITE(TRANSDATA_M1(pipe), 0);
5747 I915_WRITE(TRANSDATA_N1(pipe), 0);
5748 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5749 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5750 }
09b4ddf9
PZ		 5751 }
5752
5753 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5754 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5755 if (intel_crtc->pch_pll) {
5756 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5757
5758 /* Wait for the clocks to stabilize. */
5759 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5760 udelay(150);
5761
5762 /* The pixel multiplier can only be updated once the
5763 * DPLL is enabled and the clocks are stable.
5764 *
5765 * So write it again.
5766 */
5767 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5768 }
5769
5770 if (intel_crtc->pch_pll) {
5771 if (is_lvds && has_reduced_clock && i915_powersave) {
5772 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5773 intel_crtc->lowfreq_avail = true;
5774 } else {
5775 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5776 }
09b4ddf9
PZ		 5777 }
5778 }
5779
5780 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5781
1eb8dfec
PZ		 5782 if (!is_dp || is_cpu_edp)
5783 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5784
5dc5298b
PZ		 5785 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5786 if (is_cpu_edp)
5787 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5788
ee2b0b38 5789 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5790
09b4ddf9
PZ		 5791 /* Set up the display plane register */
5792 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5793 POSTING_READ(DSPCNTR(plane));
5794
5795 ret = intel_pipe_set_base(crtc, x, y, fb);
5796
5797 intel_update_watermarks(dev);
5798
5799 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5800
1f803ee5 5801 return ret;
79e53945
JB		 5802}
5803
f564048e
EA		 5804static int intel_crtc_mode_set(struct drm_crtc *crtc,
5805 struct drm_display_mode *mode,
5806 struct drm_display_mode *adjusted_mode,
5807 int x, int y,
94352cf9 5808 struct drm_framebuffer *fb)
f564048e
EA		 5809{
5810 struct drm_device *dev = crtc->dev;
5811 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5812 struct drm_encoder_helper_funcs *encoder_funcs;
5813 struct intel_encoder *encoder;
0b701d27
EA		 5814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5815 int pipe = intel_crtc->pipe;
f564048e
EA		 5816 int ret;
5817
0b701d27 5818 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5819
f564048e 5820 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5821 x, y, fb);
79e53945 5822 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5823
9256aa19
DV		 5824 if (ret != 0)
5825 return ret;
5826
5827 for_each_encoder_on_crtc(dev, crtc, encoder) {
5828 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5829 encoder->base.base.id,
5830 drm_get_encoder_name(&encoder->base),
5831 mode->base.id, mode->name);
5832 encoder_funcs = encoder->base.helper_private;
5833 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5834 }
5835
5836 return 0;
79e53945
JB		 5837}
5838
3a9627f4
WF		 5839static bool intel_eld_uptodate(struct drm_connector *connector,
5840 int reg_eldv, uint32_t bits_eldv,
5841 int reg_elda, uint32_t bits_elda,
5842 int reg_edid)
5843{
5844 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5845 uint8_t *eld = connector->eld;
5846 uint32_t i;
5847
5848 i = I915_READ(reg_eldv);
5849 i &= bits_eldv;
5850
5851 if (!eld[0])
5852 return !i;
5853
5854 if (!i)
5855 return false;
5856
5857 i = I915_READ(reg_elda);
5858 i &= ~bits_elda;
5859 I915_WRITE(reg_elda, i);
5860
5861 for (i = 0; i < eld[2]; i++)
5862 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5863 return false;
5864
5865 return true;
5866}
5867
e0dac65e
WF		 5868static void g4x_write_eld(struct drm_connector *connector,
5869 struct drm_crtc *crtc)
5870{
5871 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5872 uint8_t *eld = connector->eld;
5873 uint32_t eldv;
5874 uint32_t len;
5875 uint32_t i;
5876
5877 i = I915_READ(G4X_AUD_VID_DID);
5878
5879 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5880 eldv = G4X_ELDV_DEVCL_DEVBLC;
5881 else
5882 eldv = G4X_ELDV_DEVCTG;
5883
3a9627f4
WF		 5884 if (intel_eld_uptodate(connector,
5885 G4X_AUD_CNTL_ST, eldv,
5886 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5887 G4X_HDMIW_HDMIEDID))
5888 return;
5889
e0dac65e
WF		 5890 i = I915_READ(G4X_AUD_CNTL_ST);
5891 i &= ~(eldv | G4X_ELD_ADDR);
5892 len = (i >> 9) & 0x1f; /* ELD buffer size */
5893 I915_WRITE(G4X_AUD_CNTL_ST, i);
5894
5895 if (!eld[0])
5896 return;
5897
5898 len = min_t(uint8_t, eld[2], len);
5899 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5900 for (i = 0; i < len; i++)
5901 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5902
5903 i = I915_READ(G4X_AUD_CNTL_ST);
5904 i |= eldv;
5905 I915_WRITE(G4X_AUD_CNTL_ST, i);
5906}
5907
83358c85
WX		 5908static void haswell_write_eld(struct drm_connector *connector,
5909 struct drm_crtc *crtc)
5910{
5911 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5912 uint8_t *eld = connector->eld;
5913 struct drm_device *dev = crtc->dev;
5914 uint32_t eldv;
5915 uint32_t i;
5916 int len;
5917 int pipe = to_intel_crtc(crtc)->pipe;
5918 int tmp;
5919
5920 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5921 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5922 int aud_config = HSW_AUD_CFG(pipe);
5923 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5924
5925
5926 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5927
5928 /* Audio output enable */
5929 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5930 tmp = I915_READ(aud_cntrl_st2);
5931 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5932 I915_WRITE(aud_cntrl_st2, tmp);
5933
5934 /* Wait for 1 vertical blank */
5935 intel_wait_for_vblank(dev, pipe);
5936
5937 /* Set ELD valid state */
5938 tmp = I915_READ(aud_cntrl_st2);
5939 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5940 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5941 I915_WRITE(aud_cntrl_st2, tmp);
5942 tmp = I915_READ(aud_cntrl_st2);
5943 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5944
5945 /* Enable HDMI mode */
5946 tmp = I915_READ(aud_config);
5947 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5948 /* clear N_programing_enable and N_value_index */
5949 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5950 I915_WRITE(aud_config, tmp);
5951
5952 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5953
5954 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5955
5956 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5957 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5958 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5959 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5960 } else
5961 I915_WRITE(aud_config, 0);
5962
5963 if (intel_eld_uptodate(connector,
5964 aud_cntrl_st2, eldv,
5965 aud_cntl_st, IBX_ELD_ADDRESS,
5966 hdmiw_hdmiedid))
5967 return;
5968
5969 i = I915_READ(aud_cntrl_st2);
5970 i &= ~eldv;
5971 I915_WRITE(aud_cntrl_st2, i);
5972
5973 if (!eld[0])
5974 return;
5975
5976 i = I915_READ(aud_cntl_st);
5977 i &= ~IBX_ELD_ADDRESS;
5978 I915_WRITE(aud_cntl_st, i);
5979 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5980 DRM_DEBUG_DRIVER("port num:%d\n", i);
5981
5982 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5983 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5984 for (i = 0; i < len; i++)
5985 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5986
5987 i = I915_READ(aud_cntrl_st2);
5988 i |= eldv;
5989 I915_WRITE(aud_cntrl_st2, i);
5990
5991}
5992
e0dac65e
WF		 5993static void ironlake_write_eld(struct drm_connector *connector,
5994 struct drm_crtc *crtc)
5995{
5996 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5997 uint8_t *eld = connector->eld;
5998 uint32_t eldv;
5999 uint32_t i;
6000 int len;
6001 int hdmiw_hdmiedid;
b6daa025 6002 int aud_config;
e0dac65e
WF		 6003 int aud_cntl_st;
6004 int aud_cntrl_st2;
9b138a83 6005 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6006
b3f33cbf 6007 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6008 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6009 aud_config = IBX_AUD_CFG(pipe);
6010 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6011 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6012 } else {
9b138a83
WX		 6013 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6014 aud_config = CPT_AUD_CFG(pipe);
6015 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6016 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6017 }
6018
9b138a83 6019 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6020
6021 i = I915_READ(aud_cntl_st);
9b138a83 6022 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6023 if (!i) {
6024 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6025 /* operate blindly on all ports */
1202b4c6
WF		 6026 eldv = IBX_ELD_VALIDB;
6027 eldv |= IBX_ELD_VALIDB << 4;
6028 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6029 } else {
6030 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6031 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6032 }
6033
3a9627f4
WF		 6034 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6035 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6036 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6037 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6038 } else
6039 I915_WRITE(aud_config, 0);
e0dac65e 6040
3a9627f4
WF		 6041 if (intel_eld_uptodate(connector,
6042 aud_cntrl_st2, eldv,
6043 aud_cntl_st, IBX_ELD_ADDRESS,
6044 hdmiw_hdmiedid))
6045 return;
6046
e0dac65e
WF		 6047 i = I915_READ(aud_cntrl_st2);
6048 i &= ~eldv;
6049 I915_WRITE(aud_cntrl_st2, i);
6050
6051 if (!eld[0])
6052 return;
6053
e0dac65e 6054 i = I915_READ(aud_cntl_st);
1202b4c6 6055 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6056 I915_WRITE(aud_cntl_st, i);
6057
6058 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6059 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6060 for (i = 0; i < len; i++)
6061 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6062
6063 i = I915_READ(aud_cntrl_st2);
6064 i |= eldv;
6065 I915_WRITE(aud_cntrl_st2, i);
6066}
6067
6068void intel_write_eld(struct drm_encoder *encoder,
6069 struct drm_display_mode *mode)
6070{
6071 struct drm_crtc *crtc = encoder->crtc;
6072 struct drm_connector *connector;
6073 struct drm_device *dev = encoder->dev;
6074 struct drm_i915_private *dev_priv = dev->dev_private;
6075
6076 connector = drm_select_eld(encoder, mode);
6077 if (!connector)
6078 return;
6079
6080 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6081 connector->base.id,
6082 drm_get_connector_name(connector),
6083 connector->encoder->base.id,
6084 drm_get_encoder_name(connector->encoder));
6085
6086 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6087
6088 if (dev_priv->display.write_eld)
6089 dev_priv->display.write_eld(connector, crtc);
6090}
6091
79e53945
JB		 6092/** Loads the palette/gamma unit for the CRTC with the prepared values */
6093void intel_crtc_load_lut(struct drm_crtc *crtc)
6094{
6095 struct drm_device *dev = crtc->dev;
6096 struct drm_i915_private *dev_priv = dev->dev_private;
6097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6098 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6099 int i;
6100
6101 /* The clocks have to be on to load the palette. */
aed3f09d 6102 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6103 return;
6104
f2b115e6 6105 /* use legacy palette for Ironlake */
bad720ff 6106 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6107 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6108
79e53945
JB		 6109 for (i = 0; i < 256; i++) {
6110 I915_WRITE(palreg + 4 * i,
6111 (intel_crtc->lut_r[i] << 16) |
6112 (intel_crtc->lut_g[i] << 8) |
6113 intel_crtc->lut_b[i]);
6114 }
6115}
6116
560b85bb
CW		 6117static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6118{
6119 struct drm_device *dev = crtc->dev;
6120 struct drm_i915_private *dev_priv = dev->dev_private;
6121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122 bool visible = base != 0;
6123 u32 cntl;
6124
6125 if (intel_crtc->cursor_visible == visible)
6126 return;
6127
9db4a9c7 6128 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6129 if (visible) {
6130 /* On these chipsets we can only modify the base whilst
6131 * the cursor is disabled.
6132 */
9db4a9c7 6133 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6134
6135 cntl &= ~(CURSOR_FORMAT_MASK);
6136 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6137 cntl |= CURSOR_ENABLE |
6138 CURSOR_GAMMA_ENABLE |
6139 CURSOR_FORMAT_ARGB;
6140 } else
6141 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6142 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6143
6144 intel_crtc->cursor_visible = visible;
6145}
6146
6147static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6148{
6149 struct drm_device *dev = crtc->dev;
6150 struct drm_i915_private *dev_priv = dev->dev_private;
6151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152 int pipe = intel_crtc->pipe;
6153 bool visible = base != 0;
6154
6155 if (intel_crtc->cursor_visible != visible) {
548f245b 6156 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6157 if (base) {
6158 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6159 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6160 cntl |= pipe << 28; /* Connect to correct pipe */
6161 } else {
6162 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6163 cntl |= CURSOR_MODE_DISABLE;
6164 }
9db4a9c7 6165 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6166
6167 intel_crtc->cursor_visible = visible;
6168 }
6169 /* and commit changes on next vblank */
9db4a9c7 6170 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6171}
6172
65a21cd6
JB		 6173static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6174{
6175 struct drm_device *dev = crtc->dev;
6176 struct drm_i915_private *dev_priv = dev->dev_private;
6177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6178 int pipe = intel_crtc->pipe;
6179 bool visible = base != 0;
6180
6181 if (intel_crtc->cursor_visible != visible) {
6182 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6183 if (base) {
6184 cntl &= ~CURSOR_MODE;
6185 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6186 } else {
6187 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6188 cntl |= CURSOR_MODE_DISABLE;
6189 }
6190 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6191
6192 intel_crtc->cursor_visible = visible;
6193 }
6194 /* and commit changes on next vblank */
6195 I915_WRITE(CURBASE_IVB(pipe), base);
6196}
6197
cda4b7d3 6198/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6199static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6200 bool on)
cda4b7d3
CW		 6201{
6202 struct drm_device *dev = crtc->dev;
6203 struct drm_i915_private *dev_priv = dev->dev_private;
6204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6205 int pipe = intel_crtc->pipe;
6206 int x = intel_crtc->cursor_x;
6207 int y = intel_crtc->cursor_y;
560b85bb 6208 u32 base, pos;
cda4b7d3
CW		 6209 bool visible;
6210
6211 pos = 0;
6212
6b383a7f 6213 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6214 base = intel_crtc->cursor_addr;
6215 if (x > (int) crtc->fb->width)
6216 base = 0;
6217
6218 if (y > (int) crtc->fb->height)
6219 base = 0;
6220 } else
6221 base = 0;
6222
6223 if (x < 0) {
6224 if (x + intel_crtc->cursor_width < 0)
6225 base = 0;
6226
6227 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6228 x = -x;
6229 }
6230 pos |= x << CURSOR_X_SHIFT;
6231
6232 if (y < 0) {
6233 if (y + intel_crtc->cursor_height < 0)
6234 base = 0;
6235
6236 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6237 y = -y;
6238 }
6239 pos |= y << CURSOR_Y_SHIFT;
6240
6241 visible = base != 0;
560b85bb 6242 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6243 return;
6244
0cd83aa9 6245 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6246 I915_WRITE(CURPOS_IVB(pipe), pos);
6247 ivb_update_cursor(crtc, base);
6248 } else {
6249 I915_WRITE(CURPOS(pipe), pos);
6250 if (IS_845G(dev) || IS_I865G(dev))
6251 i845_update_cursor(crtc, base);
6252 else
6253 i9xx_update_cursor(crtc, base);
6254 }
cda4b7d3
CW		 6255}
6256
79e53945 6257static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6258 struct drm_file *file,
79e53945
JB		 6259 uint32_t handle,
6260 uint32_t width, uint32_t height)
6261{
6262 struct drm_device *dev = crtc->dev;
6263 struct drm_i915_private *dev_priv = dev->dev_private;
6264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6265 struct drm_i915_gem_object *obj;
cda4b7d3 6266 uint32_t addr;
3f8bc370 6267 int ret;
79e53945 6268
79e53945
JB		 6269 /* if we want to turn off the cursor ignore width and height */
6270 if (!handle) {
28c97730 6271 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6272 addr = 0;
05394f39 6273 obj = NULL;
5004417d 6274 mutex_lock(&dev->struct_mutex);
3f8bc370 6275 goto finish;
79e53945
JB		 6276 }
6277
6278 /* Currently we only support 64x64 cursors */
6279 if (width != 64 || height != 64) {
6280 DRM_ERROR("we currently only support 64x64 cursors\n");
6281 return -EINVAL;
6282 }
6283
05394f39 6284 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6285 if (&obj->base == NULL)
79e53945
JB		 6286 return -ENOENT;
6287
05394f39 6288 if (obj->base.size < width * height * 4) {
79e53945 6289 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6290 ret = -ENOMEM;
6291 goto fail;
79e53945
JB		 6292 }
6293
71acb5eb 6294 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6295 mutex_lock(&dev->struct_mutex);
b295d1b6 6296 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6297 if (obj->tiling_mode) {
6298 DRM_ERROR("cursor cannot be tiled\n");
6299 ret = -EINVAL;
6300 goto fail_locked;
6301 }
6302
2da3b9b9 6303 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6304 if (ret) {
6305 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6306 goto fail_locked;
e7b526bb
CW		 6307 }
6308
d9e86c0e
CW		 6309 ret = i915_gem_object_put_fence(obj);
6310 if (ret) {
2da3b9b9 6311 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6312 goto fail_unpin;
6313 }
6314
05394f39 6315 addr = obj->gtt_offset;
71acb5eb 6316 } else {
6eeefaf3 6317 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6318 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6319 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6320 align);
71acb5eb
DA		 6321 if (ret) {
6322 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6323 goto fail_locked;
71acb5eb 6324 }
05394f39 6325 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6326 }
6327
a6c45cf0 6328 if (IS_GEN2(dev))
14b60391
JB		 6329 I915_WRITE(CURSIZE, (height << 12) | width);
6330
3f8bc370 6331 finish:
3f8bc370 6332 if (intel_crtc->cursor_bo) {
b295d1b6 6333 if (dev_priv->info->cursor_needs_physical) {
05394f39 6334 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6335 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6336 } else
6337 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6338 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6339 }
80824003 6340
7f9872e0 6341 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6342
6343 intel_crtc->cursor_addr = addr;
05394f39 6344 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6345 intel_crtc->cursor_width = width;
6346 intel_crtc->cursor_height = height;
6347
6b383a7f 6348 intel_crtc_update_cursor(crtc, true);
3f8bc370 6349
79e53945 6350 return 0;
e7b526bb 6351fail_unpin:
05394f39 6352 i915_gem_object_unpin(obj);
7f9872e0 6353fail_locked:
34b8686e 6354 mutex_unlock(&dev->struct_mutex);
bc9025bd 6355fail:
05394f39 6356 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6357 return ret;
79e53945
JB		 6358}
6359
6360static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6361{
79e53945 6362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6363
cda4b7d3
CW		 6364 intel_crtc->cursor_x = x;
6365 intel_crtc->cursor_y = y;
652c393a 6366
6b383a7f 6367 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6368
6369 return 0;
6370}
6371
6372/** Sets the color ramps on behalf of RandR */
6373void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6374 u16 blue, int regno)
6375{
6376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6377
6378 intel_crtc->lut_r[regno] = red >> 8;
6379 intel_crtc->lut_g[regno] = green >> 8;
6380 intel_crtc->lut_b[regno] = blue >> 8;
6381}
6382
b8c00ac5
DA		 6383void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6384 u16 *blue, int regno)
6385{
6386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6387
6388 *red = intel_crtc->lut_r[regno] << 8;
6389 *green = intel_crtc->lut_g[regno] << 8;
6390 *blue = intel_crtc->lut_b[regno] << 8;
6391}
6392
79e53945 6393static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6394 u16 *blue, uint32_t start, uint32_t size)
79e53945 6395{
7203425a 6396 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6398
7203425a 6399 for (i = start; i < end; i++) {
79e53945
JB		 6400 intel_crtc->lut_r[i] = red[i] >> 8;
6401 intel_crtc->lut_g[i] = green[i] >> 8;
6402 intel_crtc->lut_b[i] = blue[i] >> 8;
6403 }
6404
6405 intel_crtc_load_lut(crtc);
6406}
6407
6408/**
6409 * Get a pipe with a simple mode set on it for doing load-based monitor
6410 * detection.
6411 *
6412 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6413 * its requirements. The pipe will be connected to no other encoders.
79e53945 6414 *
c751ce4f 6415 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6416 * configured for it. In the future, it could choose to temporarily disable
6417 * some outputs to free up a pipe for its use.
6418 *
6419 * \return crtc, or NULL if no pipes are available.
6420 */
6421
6422/* VESA 640x480x72Hz mode to set on the pipe */
6423static struct drm_display_mode load_detect_mode = {
6424 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6425 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6426};
6427
d2dff872
CW		 6428static struct drm_framebuffer *
6429intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6430 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6431 struct drm_i915_gem_object *obj)
6432{
6433 struct intel_framebuffer *intel_fb;
6434 int ret;
6435
6436 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6437 if (!intel_fb) {
6438 drm_gem_object_unreference_unlocked(&obj->base);
6439 return ERR_PTR(-ENOMEM);
6440 }
6441
6442 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6443 if (ret) {
6444 drm_gem_object_unreference_unlocked(&obj->base);
6445 kfree(intel_fb);
6446 return ERR_PTR(ret);
6447 }
6448
6449 return &intel_fb->base;
6450}
6451
6452static u32
6453intel_framebuffer_pitch_for_width(int width, int bpp)
6454{
6455 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6456 return ALIGN(pitch, 64);
6457}
6458
6459static u32
6460intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6461{
6462 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6463 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6464}
6465
6466static struct drm_framebuffer *
6467intel_framebuffer_create_for_mode(struct drm_device *dev,
6468 struct drm_display_mode *mode,
6469 int depth, int bpp)
6470{
6471 struct drm_i915_gem_object *obj;
0fed39bd 6472 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6473
6474 obj = i915_gem_alloc_object(dev,
6475 intel_framebuffer_size_for_mode(mode, bpp));
6476 if (obj == NULL)
6477 return ERR_PTR(-ENOMEM);
6478
6479 mode_cmd.width = mode->hdisplay;
6480 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6481 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6482 bpp);
5ca0c34a 6483 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6484
6485 return intel_framebuffer_create(dev, &mode_cmd, obj);
6486}
6487
6488static struct drm_framebuffer *
6489mode_fits_in_fbdev(struct drm_device *dev,
6490 struct drm_display_mode *mode)
6491{
6492 struct drm_i915_private *dev_priv = dev->dev_private;
6493 struct drm_i915_gem_object *obj;
6494 struct drm_framebuffer *fb;
6495
6496 if (dev_priv->fbdev == NULL)
6497 return NULL;
6498
6499 obj = dev_priv->fbdev->ifb.obj;
6500 if (obj == NULL)
6501 return NULL;
6502
6503 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6504 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6505 fb->bits_per_pixel))
d2dff872
CW		 6506 return NULL;
6507
01f2c773 6508 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6509 return NULL;
6510
6511 return fb;
6512}
6513
d2434ab7 6514bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6515 struct drm_display_mode *mode,
8261b191 6516 struct intel_load_detect_pipe *old)
79e53945
JB		 6517{
6518 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6519 struct intel_encoder *intel_encoder =
6520 intel_attached_encoder(connector);
79e53945 6521 struct drm_crtc *possible_crtc;
4ef69c7a 6522 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6523 struct drm_crtc *crtc = NULL;
6524 struct drm_device *dev = encoder->dev;
94352cf9 6525 struct drm_framebuffer *fb;
79e53945
JB		 6526 int i = -1;
6527
d2dff872
CW		 6528 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6529 connector->base.id, drm_get_connector_name(connector),
6530 encoder->base.id, drm_get_encoder_name(encoder));
6531
79e53945
JB		 6532 /*
6533 * Algorithm gets a little messy:
7a5e4805 6534 *
79e53945
JB		 6535 * - if the connector already has an assigned crtc, use it (but make
6536 * sure it's on first)
7a5e4805 6537 *
79e53945
JB		 6538 * - try to find the first unused crtc that can drive this connector,
6539 * and use that if we find one
79e53945
JB		 6540 */
6541
6542 /* See if we already have a CRTC for this connector */
6543 if (encoder->crtc) {
6544 crtc = encoder->crtc;
8261b191 6545
24218aac 6546 old->dpms_mode = connector->dpms;
8261b191
CW		 6547 old->load_detect_temp = false;
6548
6549 /* Make sure the crtc and connector are running */
24218aac
DV		 6550 if (connector->dpms != DRM_MODE_DPMS_ON)
6551 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6552
7173188d 6553 return true;
79e53945
JB		 6554 }
6555
6556 /* Find an unused one (if possible) */
6557 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6558 i++;
6559 if (!(encoder->possible_crtcs & (1 << i)))
6560 continue;
6561 if (!possible_crtc->enabled) {
6562 crtc = possible_crtc;
6563 break;
6564 }
79e53945
JB		 6565 }
6566
6567 /*
6568 * If we didn't find an unused CRTC, don't use any.
6569 */
6570 if (!crtc) {
7173188d
CW		 6571 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6572 return false;
79e53945
JB		 6573 }
6574
fc303101
DV		 6575 intel_encoder->new_crtc = to_intel_crtc(crtc);
6576 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6577
6578 intel_crtc = to_intel_crtc(crtc);
24218aac 6579 old->dpms_mode = connector->dpms;
8261b191 6580 old->load_detect_temp = true;
d2dff872 6581 old->release_fb = NULL;
79e53945 6582
6492711d
CW		 6583 if (!mode)
6584 mode = &load_detect_mode;
79e53945 6585
d2dff872
CW		 6586 /* We need a framebuffer large enough to accommodate all accesses
6587 * that the plane may generate whilst we perform load detection.
6588 * We can not rely on the fbcon either being present (we get called
6589 * during its initialisation to detect all boot displays, or it may
6590 * not even exist) or that it is large enough to satisfy the
6591 * requested mode.
6592 */
94352cf9
DV		 6593 fb = mode_fits_in_fbdev(dev, mode);
6594 if (fb == NULL) {
d2dff872 6595 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6596 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6597 old->release_fb = fb;
d2dff872
CW		 6598 } else
6599 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6600 if (IS_ERR(fb)) {
d2dff872 6601 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
0e8b3d3e 6602 return false;
79e53945 6603 }
79e53945 6604
94352cf9 6605 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6606 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6607 if (old->release_fb)
6608 old->release_fb->funcs->destroy(old->release_fb);
0e8b3d3e 6609 return false;
79e53945 6610 }
7173188d 6611
79e53945 6612 /* let the connector get through one full cycle before testing */
9d0498a2 6613 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6614 return true;
79e53945
JB		 6615}
6616
d2434ab7 6617void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6618 struct intel_load_detect_pipe *old)
79e53945 6619{
d2434ab7
DV		 6620 struct intel_encoder *intel_encoder =
6621 intel_attached_encoder(connector);
4ef69c7a 6622 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6623
d2dff872
CW		 6624 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6625 connector->base.id, drm_get_connector_name(connector),
6626 encoder->base.id, drm_get_encoder_name(encoder));
6627
8261b191 6628 if (old->load_detect_temp) {
fc303101
DV		 6629 struct drm_crtc *crtc = encoder->crtc;
6630
6631 to_intel_connector(connector)->new_encoder = NULL;
6632 intel_encoder->new_crtc = NULL;
6633 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6634
6635 if (old->release_fb)
6636 old->release_fb->funcs->destroy(old->release_fb);
6637
0622a53c 6638 return;
79e53945
JB		 6639 }
6640
c751ce4f 6641 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6642 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6643 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6644}
6645
6646/* Returns the clock of the currently programmed mode of the given pipe. */
6647static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6648{
6649 struct drm_i915_private *dev_priv = dev->dev_private;
6650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6651 int pipe = intel_crtc->pipe;
548f245b 6652 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6653 u32 fp;
6654 intel_clock_t clock;
6655
6656 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6657 fp = I915_READ(FP0(pipe));
79e53945 6658 else
39adb7a5 6659 fp = I915_READ(FP1(pipe));
79e53945
JB		 6660
6661 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6662 if (IS_PINEVIEW(dev)) {
6663 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6664 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6665 } else {
6666 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6667 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6668 }
6669
a6c45cf0 6670 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6671 if (IS_PINEVIEW(dev))
6672 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6673 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6674 else
6675 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6676 DPLL_FPA01_P1_POST_DIV_SHIFT);
6677
6678 switch (dpll & DPLL_MODE_MASK) {
6679 case DPLLB_MODE_DAC_SERIAL:
6680 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6681 5 : 10;
6682 break;
6683 case DPLLB_MODE_LVDS:
6684 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6685 7 : 14;
6686 break;
6687 default:
28c97730 6688 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6689 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6690 return 0;
6691 }
6692
6693 /* XXX: Handle the 100Mhz refclk */
2177832f 6694 intel_clock(dev, 96000, &clock);
79e53945
JB		 6695 } else {
6696 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6697
6698 if (is_lvds) {
6699 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6700 DPLL_FPA01_P1_POST_DIV_SHIFT);
6701 clock.p2 = 14;
6702
6703 if ((dpll & PLL_REF_INPUT_MASK) ==
6704 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6705 /* XXX: might not be 66MHz */
2177832f 6706 intel_clock(dev, 66000, &clock);
79e53945 6707 } else
2177832f 6708 intel_clock(dev, 48000, &clock);
79e53945
JB		 6709 } else {
6710 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6711 clock.p1 = 2;
6712 else {
6713 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6714 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6715 }
6716 if (dpll & PLL_P2_DIVIDE_BY_4)
6717 clock.p2 = 4;
6718 else
6719 clock.p2 = 2;
6720
2177832f 6721 intel_clock(dev, 48000, &clock);
79e53945
JB		 6722 }
6723 }
6724
6725 /* XXX: It would be nice to validate the clocks, but we can't reuse
6726 * i830PllIsValid() because it relies on the xf86_config connector
6727 * configuration being accurate, which it isn't necessarily.
6728 */
6729
6730 return clock.dot;
6731}
6732
6733/** Returns the currently programmed mode of the given pipe. */
6734struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6735 struct drm_crtc *crtc)
6736{
548f245b 6737 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6739 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6740 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6741 int htot = I915_READ(HTOTAL(cpu_transcoder));
6742 int hsync = I915_READ(HSYNC(cpu_transcoder));
6743 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6744 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6745
6746 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6747 if (!mode)
6748 return NULL;
6749
6750 mode->clock = intel_crtc_clock_get(dev, crtc);
6751 mode->hdisplay = (htot & 0xffff) + 1;
6752 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6753 mode->hsync_start = (hsync & 0xffff) + 1;
6754 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6755 mode->vdisplay = (vtot & 0xffff) + 1;
6756 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6757 mode->vsync_start = (vsync & 0xffff) + 1;
6758 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6759
6760 drm_mode_set_name(mode);
79e53945
JB		 6761
6762 return mode;
6763}
6764
3dec0095 6765static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6766{
6767 struct drm_device *dev = crtc->dev;
6768 drm_i915_private_t *dev_priv = dev->dev_private;
6769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6770 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6771 int dpll_reg = DPLL(pipe);
6772 int dpll;
652c393a 6773
bad720ff 6774 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6775 return;
6776
6777 if (!dev_priv->lvds_downclock_avail)
6778 return;
6779
dbdc6479 6780 dpll = I915_READ(dpll_reg);
652c393a 6781 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6782 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6783
8ac5a6d5 6784 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6785
6786 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6787 I915_WRITE(dpll_reg, dpll);
9d0498a2 6788 intel_wait_for_vblank(dev, pipe);
dbdc6479 6789
652c393a
JB		 6790 dpll = I915_READ(dpll_reg);
6791 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6792 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6793 }
652c393a
JB		 6794}
6795
6796static void intel_decrease_pllclock(struct drm_crtc *crtc)
6797{
6798 struct drm_device *dev = crtc->dev;
6799 drm_i915_private_t *dev_priv = dev->dev_private;
6800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6801
bad720ff 6802 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6803 return;
6804
6805 if (!dev_priv->lvds_downclock_avail)
6806 return;
6807
6808 /*
6809 * Since this is called by a timer, we should never get here in
6810 * the manual case.
6811 */
6812 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6813 int pipe = intel_crtc->pipe;
6814 int dpll_reg = DPLL(pipe);
6815 int dpll;
f6e5b160 6816
44d98a61 6817 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6818
8ac5a6d5 6819 assert_panel_unlocked(dev_priv, pipe);
652c393a 6820
dc257cf1 6821 dpll = I915_READ(dpll_reg);
652c393a
JB		 6822 dpll |= DISPLAY_RATE_SELECT_FPA1;
6823 I915_WRITE(dpll_reg, dpll);
9d0498a2 6824 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6825 dpll = I915_READ(dpll_reg);
6826 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6827 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6828 }
6829
6830}
6831
f047e395
CW		 6832void intel_mark_busy(struct drm_device *dev)
6833{
f047e395
CW		 6834 i915_update_gfx_val(dev->dev_private);
6835}
6836
6837void intel_mark_idle(struct drm_device *dev)
652c393a 6838{
f047e395
CW		 6839}
6840
6841void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6842{
6843 struct drm_device *dev = obj->base.dev;
652c393a 6844 struct drm_crtc *crtc;
652c393a
JB		 6845
6846 if (!i915_powersave)
6847 return;
6848
652c393a 6849 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6850 if (!crtc->fb)
6851 continue;
6852
f047e395
CW		 6853 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6854 intel_increase_pllclock(crtc);
652c393a 6855 }
652c393a
JB		 6856}
6857
f047e395 6858void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6859{
f047e395
CW		 6860 struct drm_device *dev = obj->base.dev;
6861 struct drm_crtc *crtc;
652c393a 6862
f047e395 6863 if (!i915_powersave)
acb87dfb
CW		 6864 return;
6865
652c393a
JB		 6866 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6867 if (!crtc->fb)
6868 continue;
6869
f047e395
CW		 6870 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6871 intel_decrease_pllclock(crtc);
652c393a
JB		 6872 }
6873}
6874
79e53945
JB		 6875static void intel_crtc_destroy(struct drm_crtc *crtc)
6876{
6877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6878 struct drm_device *dev = crtc->dev;
6879 struct intel_unpin_work *work;
6880 unsigned long flags;
6881
6882 spin_lock_irqsave(&dev->event_lock, flags);
6883 work = intel_crtc->unpin_work;
6884 intel_crtc->unpin_work = NULL;
6885 spin_unlock_irqrestore(&dev->event_lock, flags);
6886
6887 if (work) {
6888 cancel_work_sync(&work->work);
6889 kfree(work);
6890 }
79e53945
JB		 6891
6892 drm_crtc_cleanup(crtc);
67e77c5a 6893
79e53945
JB		 6894 kfree(intel_crtc);
6895}
6896
6b95a207
KH		 6897static void intel_unpin_work_fn(struct work_struct *__work)
6898{
6899 struct intel_unpin_work *work =
6900 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6901 struct drm_device *dev = work->crtc->dev;
6b95a207 6902
b4a98e57 6903 mutex_lock(&dev->struct_mutex);
1690e1eb 6904 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6905 drm_gem_object_unreference(&work->pending_flip_obj->base);
6906 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6907
b4a98e57
CW		 6908 intel_update_fbc(dev);
6909 mutex_unlock(&dev->struct_mutex);
6910
6911 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6912 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6913
6b95a207
KH		 6914 kfree(work);
6915}
6916
1afe3e9d 6917static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6918 struct drm_crtc *crtc)
6b95a207
KH		 6919{
6920 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6922 struct intel_unpin_work *work;
05394f39 6923 struct drm_i915_gem_object *obj;
6b95a207
KH		 6924 unsigned long flags;
6925
6926 /* Ignore early vblank irqs */
6927 if (intel_crtc == NULL)
6928 return;
6929
6930 spin_lock_irqsave(&dev->event_lock, flags);
6931 work = intel_crtc->unpin_work;
6932 if (work == NULL || !work->pending) {
6933 spin_unlock_irqrestore(&dev->event_lock, flags);
6934 return;
6935 }
6936
6937 intel_crtc->unpin_work = NULL;
6b95a207 6938
45a066eb
RC		 6939 if (work->event)
6940 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6941
0af7e4df
MK		 6942 drm_vblank_put(dev, intel_crtc->pipe);
6943
6b95a207
KH		 6944 spin_unlock_irqrestore(&dev->event_lock, flags);
6945
05394f39 6946 obj = work->old_fb_obj;
d9e86c0e 6947
e59f2bac 6948 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6949 &obj->pending_flip.counter);
5bb61643 6950 wake_up(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6951
6952 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6953
6954 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6955}
6956
1afe3e9d
JB		 6957void intel_finish_page_flip(struct drm_device *dev, int pipe)
6958{
6959 drm_i915_private_t *dev_priv = dev->dev_private;
6960 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6961
49b14a5c 6962 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6963}
6964
6965void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6966{
6967 drm_i915_private_t *dev_priv = dev->dev_private;
6968 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6969
49b14a5c 6970 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6971}
6972
6b95a207
KH		 6973void intel_prepare_page_flip(struct drm_device *dev, int plane)
6974{
6975 drm_i915_private_t *dev_priv = dev->dev_private;
6976 struct intel_crtc *intel_crtc =
6977 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6978 unsigned long flags;
6979
6980 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6981 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6982 if ((++intel_crtc->unpin_work->pending) > 1)
6983 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6984 } else {
6985 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6986 }
6b95a207
KH		 6987 spin_unlock_irqrestore(&dev->event_lock, flags);
6988}
6989
8c9f3aaf
JB		 6990static int intel_gen2_queue_flip(struct drm_device *dev,
6991 struct drm_crtc *crtc,
6992 struct drm_framebuffer *fb,
6993 struct drm_i915_gem_object *obj)
6994{
6995 struct drm_i915_private *dev_priv = dev->dev_private;
6996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6997 u32 flip_mask;
6d90c952 6998 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6999 int ret;
7000
6d90c952 7001 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7002 if (ret)
83d4092b 7003 goto err;
8c9f3aaf 7004
6d90c952 7005 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7006 if (ret)
83d4092b 7007 goto err_unpin;
8c9f3aaf
JB		 7008
7009 /* Can't queue multiple flips, so wait for the previous
7010 * one to finish before executing the next.
7011 */
7012 if (intel_crtc->plane)
7013 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7014 else
7015 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7016 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7017 intel_ring_emit(ring, MI_NOOP);
7018 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7019 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7020 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7021 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7022 intel_ring_emit(ring, 0); /* aux display base address, unused */
7023 intel_ring_advance(ring);
83d4092b
CW		 7024 return 0;
7025
7026err_unpin:
7027 intel_unpin_fb_obj(obj);
7028err:
8c9f3aaf
JB		 7029 return ret;
7030}
7031
7032static int intel_gen3_queue_flip(struct drm_device *dev,
7033 struct drm_crtc *crtc,
7034 struct drm_framebuffer *fb,
7035 struct drm_i915_gem_object *obj)
7036{
7037 struct drm_i915_private *dev_priv = dev->dev_private;
7038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7039 u32 flip_mask;
6d90c952 7040 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7041 int ret;
7042
6d90c952 7043 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7044 if (ret)
83d4092b 7045 goto err;
8c9f3aaf 7046
6d90c952 7047 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7048 if (ret)
83d4092b 7049 goto err_unpin;
8c9f3aaf
JB		 7050
7051 if (intel_crtc->plane)
7052 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7053 else
7054 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7055 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7056 intel_ring_emit(ring, MI_NOOP);
7057 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7058 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7059 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7060 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7061 intel_ring_emit(ring, MI_NOOP);
7062
7063 intel_ring_advance(ring);
83d4092b
CW		 7064 return 0;
7065
7066err_unpin:
7067 intel_unpin_fb_obj(obj);
7068err:
8c9f3aaf
JB		 7069 return ret;
7070}
7071
7072static int intel_gen4_queue_flip(struct drm_device *dev,
7073 struct drm_crtc *crtc,
7074 struct drm_framebuffer *fb,
7075 struct drm_i915_gem_object *obj)
7076{
7077 struct drm_i915_private *dev_priv = dev->dev_private;
7078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7079 uint32_t pf, pipesrc;
6d90c952 7080 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7081 int ret;
7082
6d90c952 7083 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7084 if (ret)
83d4092b 7085 goto err;
8c9f3aaf 7086
6d90c952 7087 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7088 if (ret)
83d4092b 7089 goto err_unpin;
8c9f3aaf
JB		 7090
7091 /* i965+ uses the linear or tiled offsets from the
7092 * Display Registers (which do not change across a page-flip)
7093 * so we need only reprogram the base address.
7094 */
6d90c952
DV		 7095 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7096 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7097 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7098 intel_ring_emit(ring,
7099 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7100 obj->tiling_mode);
8c9f3aaf
JB		 7101
7102 /* XXX Enabling the panel-fitter across page-flip is so far
7103 * untested on non-native modes, so ignore it for now.
7104 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7105 */
7106 pf = 0;
7107 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7108 intel_ring_emit(ring, pf | pipesrc);
7109 intel_ring_advance(ring);
83d4092b
CW		 7110 return 0;
7111
7112err_unpin:
7113 intel_unpin_fb_obj(obj);
7114err:
8c9f3aaf
JB		 7115 return ret;
7116}
7117
7118static int intel_gen6_queue_flip(struct drm_device *dev,
7119 struct drm_crtc *crtc,
7120 struct drm_framebuffer *fb,
7121 struct drm_i915_gem_object *obj)
7122{
7123 struct drm_i915_private *dev_priv = dev->dev_private;
7124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7125 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7126 uint32_t pf, pipesrc;
7127 int ret;
7128
6d90c952 7129 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7130 if (ret)
83d4092b 7131 goto err;
8c9f3aaf 7132
6d90c952 7133 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7134 if (ret)
83d4092b 7135 goto err_unpin;
8c9f3aaf 7136
6d90c952
DV		 7137 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7138 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7139 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7140 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7141
dc257cf1
DV		 7142 /* Contrary to the suggestions in the documentation,
7143 * "Enable Panel Fitter" does not seem to be required when page
7144 * flipping with a non-native mode, and worse causes a normal
7145 * modeset to fail.
7146 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7147 */
7148 pf = 0;
8c9f3aaf 7149 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7150 intel_ring_emit(ring, pf | pipesrc);
7151 intel_ring_advance(ring);
83d4092b
CW		 7152 return 0;
7153
7154err_unpin:
7155 intel_unpin_fb_obj(obj);
7156err:
8c9f3aaf
JB		 7157 return ret;
7158}
7159
7c9017e5
JB		 7160/*
7161 * On gen7 we currently use the blit ring because (in early silicon at least)
7162 * the render ring doesn't give us interrpts for page flip completion, which
7163 * means clients will hang after the first flip is queued. Fortunately the
7164 * blit ring generates interrupts properly, so use it instead.
7165 */
7166static int intel_gen7_queue_flip(struct drm_device *dev,
7167 struct drm_crtc *crtc,
7168 struct drm_framebuffer *fb,
7169 struct drm_i915_gem_object *obj)
7170{
7171 struct drm_i915_private *dev_priv = dev->dev_private;
7172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7173 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7174 uint32_t plane_bit = 0;
7c9017e5
JB		 7175 int ret;
7176
7177 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7178 if (ret)
83d4092b 7179 goto err;
7c9017e5 7180
cb05d8de
DV		 7181 switch(intel_crtc->plane) {
7182 case PLANE_A:
7183 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7184 break;
7185 case PLANE_B:
7186 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7187 break;
7188 case PLANE_C:
7189 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7190 break;
7191 default:
7192 WARN_ONCE(1, "unknown plane in flip command\n");
7193 ret = -ENODEV;
ab3951eb 7194 goto err_unpin;
cb05d8de
DV		 7195 }
7196
7c9017e5
JB		 7197 ret = intel_ring_begin(ring, 4);
7198 if (ret)
83d4092b 7199 goto err_unpin;
7c9017e5 7200
cb05d8de 7201 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7202 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7203 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7204 intel_ring_emit(ring, (MI_NOOP));
7205 intel_ring_advance(ring);
83d4092b
CW		 7206 return 0;
7207
7208err_unpin:
7209 intel_unpin_fb_obj(obj);
7210err:
7c9017e5
JB		 7211 return ret;
7212}
7213
8c9f3aaf
JB		 7214static int intel_default_queue_flip(struct drm_device *dev,
7215 struct drm_crtc *crtc,
7216 struct drm_framebuffer *fb,
7217 struct drm_i915_gem_object *obj)
7218{
7219 return -ENODEV;
7220}
7221
6b95a207
KH		 7222static int intel_crtc_page_flip(struct drm_crtc *crtc,
7223 struct drm_framebuffer *fb,
7224 struct drm_pending_vblank_event *event)
7225{
7226 struct drm_device *dev = crtc->dev;
7227 struct drm_i915_private *dev_priv = dev->dev_private;
7228 struct intel_framebuffer *intel_fb;
05394f39 7229 struct drm_i915_gem_object *obj;
6b95a207
KH		 7230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7231 struct intel_unpin_work *work;
8c9f3aaf 7232 unsigned long flags;
52e68630 7233 int ret;
6b95a207 7234
e6a595d2
VS		 7235 /* Can't change pixel format via MI display flips. */
7236 if (fb->pixel_format != crtc->fb->pixel_format)
7237 return -EINVAL;
7238
7239 /*
7240 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7241 * Note that pitch changes could also affect these register.
7242 */
7243 if (INTEL_INFO(dev)->gen > 3 &&
7244 (fb->offsets[0] != crtc->fb->offsets[0] ||
7245 fb->pitches[0] != crtc->fb->pitches[0]))
7246 return -EINVAL;
7247
6b95a207
KH		 7248 work = kzalloc(sizeof *work, GFP_KERNEL);
7249 if (work == NULL)
7250 return -ENOMEM;
7251
6b95a207 7252 work->event = event;
b4a98e57 7253 work->crtc = crtc;
6b95a207 7254 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7255 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7256 INIT_WORK(&work->work, intel_unpin_work_fn);
7257
7317c75e
JB		 7258 ret = drm_vblank_get(dev, intel_crtc->pipe);
7259 if (ret)
7260 goto free_work;
7261
6b95a207
KH		 7262 /* We borrow the event spin lock for protecting unpin_work */
7263 spin_lock_irqsave(&dev->event_lock, flags);
7264 if (intel_crtc->unpin_work) {
7265 spin_unlock_irqrestore(&dev->event_lock, flags);
7266 kfree(work);
7317c75e 7267 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7268
7269 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7270 return -EBUSY;
7271 }
7272 intel_crtc->unpin_work = work;
7273 spin_unlock_irqrestore(&dev->event_lock, flags);
7274
7275 intel_fb = to_intel_framebuffer(fb);
7276 obj = intel_fb->obj;
7277
b4a98e57
CW		 7278 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7279 flush_workqueue(dev_priv->wq);
7280
79158103
CW		 7281 ret = i915_mutex_lock_interruptible(dev);
7282 if (ret)
7283 goto cleanup;
6b95a207 7284
75dfca80 7285 /* Reference the objects for the scheduled work. */
05394f39
CW		 7286 drm_gem_object_reference(&work->old_fb_obj->base);
7287 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7288
7289 crtc->fb = fb;
96b099fd 7290
e1f99ce6 7291 work->pending_flip_obj = obj;
e1f99ce6 7292
4e5359cd
SF		 7293 work->enable_stall_check = true;
7294
e1f99ce6
CW		 7295 /* Block clients from rendering to the new back buffer until
7296 * the flip occurs and the object is no longer visible.
7297 */
05394f39 7298 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
b4a98e57 7299 atomic_inc(&intel_crtc->unpin_work_count);
e1f99ce6 7300
8c9f3aaf
JB		 7301 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7302 if (ret)
7303 goto cleanup_pending;
6b95a207 7304
7782de3b 7305 intel_disable_fbc(dev);
f047e395 7306 intel_mark_fb_busy(obj);
6b95a207
KH		 7307 mutex_unlock(&dev->struct_mutex);
7308
e5510fac
JB		 7309 trace_i915_flip_request(intel_crtc->plane, obj);
7310
6b95a207 7311 return 0;
96b099fd 7312
8c9f3aaf 7313cleanup_pending:
b4a98e57 7314 atomic_dec(&intel_crtc->unpin_work_count);
8c9f3aaf 7315 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7316 drm_gem_object_unreference(&work->old_fb_obj->base);
7317 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7318 mutex_unlock(&dev->struct_mutex);
7319
79158103 7320cleanup:
96b099fd
CW		 7321 spin_lock_irqsave(&dev->event_lock, flags);
7322 intel_crtc->unpin_work = NULL;
7323 spin_unlock_irqrestore(&dev->event_lock, flags);
7324
7317c75e
JB		 7325 drm_vblank_put(dev, intel_crtc->pipe);
7326free_work:
96b099fd
CW		 7327 kfree(work);
7328
7329 return ret;
6b95a207
KH		 7330}
7331
f6e5b160 7332static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7333 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7334 .load_lut = intel_crtc_load_lut,
976f8a20 7335 .disable = intel_crtc_noop,
f6e5b160
CW		 7336};
7337
6ed0f796 7338bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7339{
6ed0f796
DV		 7340 struct intel_encoder *other_encoder;
7341 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7342
6ed0f796
DV		 7343 if (WARN_ON(!crtc))
7344 return false;
7345
7346 list_for_each_entry(other_encoder,
7347 &crtc->dev->mode_config.encoder_list,
7348 base.head) {
7349
7350 if (&other_encoder->new_crtc->base != crtc ||
7351 encoder == other_encoder)
7352 continue;
7353 else
7354 return true;
f47166d2
CW		 7355 }
7356
6ed0f796
DV		 7357 return false;
7358}
47f1c6c9 7359
50f56119
DV		 7360static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7361 struct drm_crtc *crtc)
7362{
7363 struct drm_device *dev;
7364 struct drm_crtc *tmp;
7365 int crtc_mask = 1;
47f1c6c9 7366
50f56119 7367 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7368
50f56119 7369 dev = crtc->dev;
47f1c6c9 7370
50f56119
DV		 7371 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7372 if (tmp == crtc)
7373 break;
7374 crtc_mask <<= 1;
7375 }
47f1c6c9 7376
50f56119
DV		 7377 if (encoder->possible_crtcs & crtc_mask)
7378 return true;
7379 return false;
47f1c6c9 7380}
79e53945 7381
9a935856
DV		 7382/**
7383 * intel_modeset_update_staged_output_state
7384 *
7385 * Updates the staged output configuration state, e.g. after we've read out the
7386 * current hw state.
7387 */
7388static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7389{
9a935856
DV		 7390 struct intel_encoder *encoder;
7391 struct intel_connector *connector;
f6e5b160 7392
9a935856
DV		 7393 list_for_each_entry(connector, &dev->mode_config.connector_list,
7394 base.head) {
7395 connector->new_encoder =
7396 to_intel_encoder(connector->base.encoder);
7397 }
f6e5b160 7398
9a935856
DV		 7399 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7400 base.head) {
7401 encoder->new_crtc =
7402 to_intel_crtc(encoder->base.crtc);
7403 }
f6e5b160
CW		 7404}
7405
9a935856
DV		 7406/**
7407 * intel_modeset_commit_output_state
7408 *
7409 * This function copies the stage display pipe configuration to the real one.
7410 */
7411static void intel_modeset_commit_output_state(struct drm_device *dev)
7412{
7413 struct intel_encoder *encoder;
7414 struct intel_connector *connector;
f6e5b160 7415
9a935856
DV		 7416 list_for_each_entry(connector, &dev->mode_config.connector_list,
7417 base.head) {
7418 connector->base.encoder = &connector->new_encoder->base;
7419 }
f6e5b160 7420
9a935856
DV		 7421 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7422 base.head) {
7423 encoder->base.crtc = &encoder->new_crtc->base;
7424 }
7425}
7426
7758a113
DV		 7427static struct drm_display_mode *
7428intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7429 struct drm_display_mode *mode)
ee7b9f93 7430{
7758a113
DV		 7431 struct drm_device *dev = crtc->dev;
7432 struct drm_display_mode *adjusted_mode;
7433 struct drm_encoder_helper_funcs *encoder_funcs;
7434 struct intel_encoder *encoder;
ee7b9f93 7435
7758a113
DV		 7436 adjusted_mode = drm_mode_duplicate(dev, mode);
7437 if (!adjusted_mode)
7438 return ERR_PTR(-ENOMEM);
7439
7440 /* Pass our mode to the connectors and the CRTC to give them a chance to
7441 * adjust it according to limitations or connector properties, and also
7442 * a chance to reject the mode entirely.
47f1c6c9 7443 */
7758a113
DV		 7444 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7445 base.head) {
47f1c6c9 7446
7758a113
DV		 7447 if (&encoder->new_crtc->base != crtc)
7448 continue;
7449 encoder_funcs = encoder->base.helper_private;
7450 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7451 adjusted_mode))) {
7452 DRM_DEBUG_KMS("Encoder fixup failed\n");
7453 goto fail;
7454 }
ee7b9f93 7455 }
47f1c6c9 7456
7758a113
DV		 7457 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7458 DRM_DEBUG_KMS("CRTC fixup failed\n");
7459 goto fail;
ee7b9f93 7460 }
7758a113 7461 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7462
7758a113
DV		 7463 return adjusted_mode;
7464fail:
7465 drm_mode_destroy(dev, adjusted_mode);
7466 return ERR_PTR(-EINVAL);
ee7b9f93 7467}
47f1c6c9 7468
e2e1ed41
DV		 7469/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7470 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7471static void
7472intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7473 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7474{
7475 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7476 struct drm_device *dev = crtc->dev;
7477 struct intel_encoder *encoder;
7478 struct intel_connector *connector;
7479 struct drm_crtc *tmp_crtc;
79e53945 7480
e2e1ed41 7481 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7482
e2e1ed41
DV		 7483 /* Check which crtcs have changed outputs connected to them, these need
7484 * to be part of the prepare_pipes mask. We don't (yet) support global
7485 * modeset across multiple crtcs, so modeset_pipes will only have one
7486 * bit set at most. */
7487 list_for_each_entry(connector, &dev->mode_config.connector_list,
7488 base.head) {
7489 if (connector->base.encoder == &connector->new_encoder->base)
7490 continue;
79e53945 7491
e2e1ed41
DV		 7492 if (connector->base.encoder) {
7493 tmp_crtc = connector->base.encoder->crtc;
7494
7495 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7496 }
7497
7498 if (connector->new_encoder)
7499 *prepare_pipes |=
7500 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7501 }
7502
e2e1ed41
DV		 7503 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7504 base.head) {
7505 if (encoder->base.crtc == &encoder->new_crtc->base)
7506 continue;
7507
7508 if (encoder->base.crtc) {
7509 tmp_crtc = encoder->base.crtc;
7510
7511 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7512 }
7513
7514 if (encoder->new_crtc)
7515 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7516 }
7517
e2e1ed41
DV		 7518 /* Check for any pipes that will be fully disabled ... */
7519 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7520 base.head) {
7521 bool used = false;
22fd0fab 7522
e2e1ed41
DV		 7523 /* Don't try to disable disabled crtcs. */
7524 if (!intel_crtc->base.enabled)
7525 continue;
7e7d76c3 7526
e2e1ed41
DV		 7527 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7528 base.head) {
7529 if (encoder->new_crtc == intel_crtc)
7530 used = true;
7531 }
7532
7533 if (!used)
7534 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7535 }
7536
e2e1ed41
DV		 7537
7538 /* set_mode is also used to update properties on life display pipes. */
7539 intel_crtc = to_intel_crtc(crtc);
7540 if (crtc->enabled)
7541 *prepare_pipes |= 1 << intel_crtc->pipe;
7542
7543 /* We only support modeset on one single crtc, hence we need to do that
7544 * only for the passed in crtc iff we change anything else than just
7545 * disable crtcs.
7546 *
7547 * This is actually not true, to be fully compatible with the old crtc
7548 * helper we automatically disable _any_ output (i.e. doesn't need to be
7549 * connected to the crtc we're modesetting on) if it's disconnected.
7550 * Which is a rather nutty api (since changed the output configuration
7551 * without userspace's explicit request can lead to confusion), but
7552 * alas. Hence we currently need to modeset on all pipes we prepare. */
7553 if (*prepare_pipes)
7554 *modeset_pipes = *prepare_pipes;
7555
7556 /* ... and mask these out. */
7557 *modeset_pipes &= ~(*disable_pipes);
7558 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7559}
79e53945 7560
ea9d758d 7561static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7562{
ea9d758d 7563 struct drm_encoder *encoder;
f6e5b160 7564 struct drm_device *dev = crtc->dev;
f6e5b160 7565
ea9d758d
DV		 7566 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7567 if (encoder->crtc == crtc)
7568 return true;
7569
7570 return false;
7571}
7572
7573static void
7574intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7575{
7576 struct intel_encoder *intel_encoder;
7577 struct intel_crtc *intel_crtc;
7578 struct drm_connector *connector;
7579
7580 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7581 base.head) {
7582 if (!intel_encoder->base.crtc)
7583 continue;
7584
7585 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7586
7587 if (prepare_pipes & (1 << intel_crtc->pipe))
7588 intel_encoder->connectors_active = false;
7589 }
7590
7591 intel_modeset_commit_output_state(dev);
7592
7593 /* Update computed state. */
7594 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7595 base.head) {
7596 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7597 }
7598
7599 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7600 if (!connector->encoder || !connector->encoder->crtc)
7601 continue;
7602
7603 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7604
7605 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7606 struct drm_property *dpms_property =
7607 dev->mode_config.dpms_property;
7608
ea9d758d 7609 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7610 drm_object_property_set_value(&connector->base,
68d34720
DV		 7611 dpms_property,
7612 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7613
7614 intel_encoder = to_intel_encoder(connector->encoder);
7615 intel_encoder->connectors_active = true;
7616 }
7617 }
7618
7619}
7620
25c5b266
DV		 7621#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7622 list_for_each_entry((intel_crtc), \
7623 &(dev)->mode_config.crtc_list, \
7624 base.head) \
7625 if (mask & (1 <<(intel_crtc)->pipe)) \
7626
b980514c 7627void
8af6cf88
DV		 7628intel_modeset_check_state(struct drm_device *dev)
7629{
7630 struct intel_crtc *crtc;
7631 struct intel_encoder *encoder;
7632 struct intel_connector *connector;
7633
7634 list_for_each_entry(connector, &dev->mode_config.connector_list,
7635 base.head) {
7636 /* This also checks the encoder/connector hw state with the
7637 * ->get_hw_state callbacks. */
7638 intel_connector_check_state(connector);
7639
7640 WARN(&connector->new_encoder->base != connector->base.encoder,
7641 "connector's staged encoder doesn't match current encoder\n");
7642 }
7643
7644 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7645 base.head) {
7646 bool enabled = false;
7647 bool active = false;
7648 enum pipe pipe, tracked_pipe;
7649
7650 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7651 encoder->base.base.id,
7652 drm_get_encoder_name(&encoder->base));
7653
7654 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7655 "encoder's stage crtc doesn't match current crtc\n");
7656 WARN(encoder->connectors_active && !encoder->base.crtc,
7657 "encoder's active_connectors set, but no crtc\n");
7658
7659 list_for_each_entry(connector, &dev->mode_config.connector_list,
7660 base.head) {
7661 if (connector->base.encoder != &encoder->base)
7662 continue;
7663 enabled = true;
7664 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7665 active = true;
7666 }
7667 WARN(!!encoder->base.crtc != enabled,
7668 "encoder's enabled state mismatch "
7669 "(expected %i, found %i)\n",
7670 !!encoder->base.crtc, enabled);
7671 WARN(active && !encoder->base.crtc,
7672 "active encoder with no crtc\n");
7673
7674 WARN(encoder->connectors_active != active,
7675 "encoder's computed active state doesn't match tracked active state "
7676 "(expected %i, found %i)\n", active, encoder->connectors_active);
7677
7678 active = encoder->get_hw_state(encoder, &pipe);
7679 WARN(active != encoder->connectors_active,
7680 "encoder's hw state doesn't match sw tracking "
7681 "(expected %i, found %i)\n",
7682 encoder->connectors_active, active);
7683
7684 if (!encoder->base.crtc)
7685 continue;
7686
7687 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7688 WARN(active && pipe != tracked_pipe,
7689 "active encoder's pipe doesn't match"
7690 "(expected %i, found %i)\n",
7691 tracked_pipe, pipe);
7692
7693 }
7694
7695 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7696 base.head) {
7697 bool enabled = false;
7698 bool active = false;
7699
7700 DRM_DEBUG_KMS("[CRTC:%d]\n",
7701 crtc->base.base.id);
7702
7703 WARN(crtc->active && !crtc->base.enabled,
7704 "active crtc, but not enabled in sw tracking\n");
7705
7706 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7707 base.head) {
7708 if (encoder->base.crtc != &crtc->base)
7709 continue;
7710 enabled = true;
7711 if (encoder->connectors_active)
7712 active = true;
7713 }
7714 WARN(active != crtc->active,
7715 "crtc's computed active state doesn't match tracked active state "
7716 "(expected %i, found %i)\n", active, crtc->active);
7717 WARN(enabled != crtc->base.enabled,
7718 "crtc's computed enabled state doesn't match tracked enabled state "
7719 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7720
7721 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7722 }
7723}
7724
a6778b3c
DV		 7725bool intel_set_mode(struct drm_crtc *crtc,
7726 struct drm_display_mode *mode,
94352cf9 7727 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7728{
7729 struct drm_device *dev = crtc->dev;
dbf2b54e 7730 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7731 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7732 struct intel_crtc *intel_crtc;
7733 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7734 bool ret = true;
7735
e2e1ed41 7736 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7737 &prepare_pipes, &disable_pipes);
7738
7739 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7740 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7741
976f8a20
DV		 7742 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7743 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7744
a6778b3c
DV		 7745 saved_hwmode = crtc->hwmode;
7746 saved_mode = crtc->mode;
a6778b3c 7747
25c5b266
DV		 7748 /* Hack: Because we don't (yet) support global modeset on multiple
7749 * crtcs, we don't keep track of the new mode for more than one crtc.
7750 * Hence simply check whether any bit is set in modeset_pipes in all the
7751 * pieces of code that are not yet converted to deal with mutliple crtcs
7752 * changing their mode at the same time. */
7753 adjusted_mode = NULL;
7754 if (modeset_pipes) {
7755 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7756 if (IS_ERR(adjusted_mode)) {
7757 return false;
7758 }
25c5b266 7759 }
a6778b3c 7760
ea9d758d
DV		 7761 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7762 if (intel_crtc->base.enabled)
7763 dev_priv->display.crtc_disable(&intel_crtc->base);
7764 }
a6778b3c 7765
6c4c86f5
DV		 7766 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7767 * to set it here already despite that we pass it down the callchain.
f6e5b160 7768 */
6c4c86f5 7769 if (modeset_pipes)
25c5b266 7770 crtc->mode = *mode;
7758a113 7771
ea9d758d
DV		 7772 /* Only after disabling all output pipelines that will be changed can we
7773 * update the the output configuration. */
7774 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7775
47fab737
DV		 7776 if (dev_priv->display.modeset_global_resources)
7777 dev_priv->display.modeset_global_resources(dev);
7778
a6778b3c
DV		 7779 /* Set up the DPLL and any encoders state that needs to adjust or depend
7780 * on the DPLL.
f6e5b160 7781 */
25c5b266
DV		 7782 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7783 ret = !intel_crtc_mode_set(&intel_crtc->base,
7784 mode, adjusted_mode,
7785 x, y, fb);
7786 if (!ret)
7787 goto done;
a6778b3c
DV		 7788 }
7789
7790 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7791 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7792 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7793
25c5b266
DV		 7794 if (modeset_pipes) {
7795 /* Store real post-adjustment hardware mode. */
7796 crtc->hwmode = *adjusted_mode;
a6778b3c 7797
25c5b266
DV		 7798 /* Calculate and store various constants which
7799 * are later needed by vblank and swap-completion
7800 * timestamping. They are derived from true hwmode.
7801 */
7802 drm_calc_timestamping_constants(crtc);
7803 }
a6778b3c
DV		 7804
7805 /* FIXME: add subpixel order */
7806done:
7807 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7808 if (!ret && crtc->enabled) {
a6778b3c
DV		 7809 crtc->hwmode = saved_hwmode;
7810 crtc->mode = saved_mode;
8af6cf88
DV		 7811 } else {
7812 intel_modeset_check_state(dev);
a6778b3c
DV		 7813 }
7814
7815 return ret;
f6e5b160
CW		 7816}
7817
25c5b266
DV		 7818#undef for_each_intel_crtc_masked
7819
d9e55608
DV		 7820static void intel_set_config_free(struct intel_set_config *config)
7821{
7822 if (!config)
7823 return;
7824
1aa4b628
DV		 7825 kfree(config->save_connector_encoders);
7826 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7827 kfree(config);
7828}
7829
85f9eb71
DV		 7830static int intel_set_config_save_state(struct drm_device *dev,
7831 struct intel_set_config *config)
7832{
85f9eb71
DV		 7833 struct drm_encoder *encoder;
7834 struct drm_connector *connector;
7835 int count;
7836
1aa4b628
DV		 7837 config->save_encoder_crtcs =
7838 kcalloc(dev->mode_config.num_encoder,
7839 sizeof(struct drm_crtc *), GFP_KERNEL);
7840 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7841 return -ENOMEM;
7842
1aa4b628
DV		 7843 config->save_connector_encoders =
7844 kcalloc(dev->mode_config.num_connector,
7845 sizeof(struct drm_encoder *), GFP_KERNEL);
7846 if (!config->save_connector_encoders)
85f9eb71
DV		 7847 return -ENOMEM;
7848
7849 /* Copy data. Note that driver private data is not affected.
7850 * Should anything bad happen only the expected state is
7851 * restored, not the drivers personal bookkeeping.
7852 */
85f9eb71
DV		 7853 count = 0;
7854 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7855 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7856 }
7857
7858 count = 0;
7859 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7860 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7861 }
7862
7863 return 0;
7864}
7865
7866static void intel_set_config_restore_state(struct drm_device *dev,
7867 struct intel_set_config *config)
7868{
9a935856
DV		 7869 struct intel_encoder *encoder;
7870 struct intel_connector *connector;
85f9eb71
DV		 7871 int count;
7872
85f9eb71 7873 count = 0;
9a935856
DV		 7874 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7875 encoder->new_crtc =
7876 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7877 }
7878
7879 count = 0;
9a935856
DV		 7880 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7881 connector->new_encoder =
7882 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7883 }
7884}
7885
5e2b584e
DV		 7886static void
7887intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7888 struct intel_set_config *config)
7889{
7890
7891 /* We should be able to check here if the fb has the same properties
7892 * and then just flip_or_move it */
7893 if (set->crtc->fb != set->fb) {
7894 /* If we have no fb then treat it as a full mode set */
7895 if (set->crtc->fb == NULL) {
7896 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7897 config->mode_changed = true;
7898 } else if (set->fb == NULL) {
7899 config->mode_changed = true;
7900 } else if (set->fb->depth != set->crtc->fb->depth) {
7901 config->mode_changed = true;
7902 } else if (set->fb->bits_per_pixel !=
7903 set->crtc->fb->bits_per_pixel) {
7904 config->mode_changed = true;
7905 } else
7906 config->fb_changed = true;
7907 }
7908
835c5873 7909 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7910 config->fb_changed = true;
7911
7912 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7913 DRM_DEBUG_KMS("modes are different, full mode set\n");
7914 drm_mode_debug_printmodeline(&set->crtc->mode);
7915 drm_mode_debug_printmodeline(set->mode);
7916 config->mode_changed = true;
7917 }
7918}
7919
2e431051 7920static int
9a935856
DV		 7921intel_modeset_stage_output_state(struct drm_device *dev,
7922 struct drm_mode_set *set,
7923 struct intel_set_config *config)
50f56119 7924{
85f9eb71 7925 struct drm_crtc *new_crtc;
9a935856
DV		 7926 struct intel_connector *connector;
7927 struct intel_encoder *encoder;
2e431051 7928 int count, ro;
50f56119 7929
9a935856
DV		 7930 /* The upper layers ensure that we either disabl a crtc or have a list
7931 * of connectors. For paranoia, double-check this. */
7932 WARN_ON(!set->fb && (set->num_connectors != 0));
7933 WARN_ON(set->fb && (set->num_connectors == 0));
7934
50f56119 7935 count = 0;
9a935856
DV		 7936 list_for_each_entry(connector, &dev->mode_config.connector_list,
7937 base.head) {
7938 /* Otherwise traverse passed in connector list and get encoders
7939 * for them. */
50f56119 7940 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7941 if (set->connectors[ro] == &connector->base) {
7942 connector->new_encoder = connector->encoder;
50f56119
DV		 7943 break;
7944 }
7945 }
7946
9a935856
DV		 7947 /* If we disable the crtc, disable all its connectors. Also, if
7948 * the connector is on the changing crtc but not on the new
7949 * connector list, disable it. */
7950 if ((!set->fb || ro == set->num_connectors) &&
7951 connector->base.encoder &&
7952 connector->base.encoder->crtc == set->crtc) {
7953 connector->new_encoder = NULL;
7954
7955 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7956 connector->base.base.id,
7957 drm_get_connector_name(&connector->base));
7958 }
7959
7960
7961 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7962 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7963 config->mode_changed = true;
50f56119 7964 }
9a935856
DV		 7965
7966 /* Disable all disconnected encoders. */
7967 if (connector->base.status == connector_status_disconnected)
7968 connector->new_encoder = NULL;
50f56119 7969 }
9a935856 7970 /* connector->new_encoder is now updated for all connectors. */
50f56119 7971
9a935856 7972 /* Update crtc of enabled connectors. */
50f56119 7973 count = 0;
9a935856
DV		 7974 list_for_each_entry(connector, &dev->mode_config.connector_list,
7975 base.head) {
7976 if (!connector->new_encoder)
50f56119
DV		 7977 continue;
7978
9a935856 7979 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7980
7981 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7982 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7983 new_crtc = set->crtc;
7984 }
7985
7986 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7987 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7988 new_crtc)) {
5e2b584e 7989 return -EINVAL;
50f56119 7990 }
9a935856
DV		 7991 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7992
7993 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7994 connector->base.base.id,
7995 drm_get_connector_name(&connector->base),
7996 new_crtc->base.id);
7997 }
7998
7999 /* Check for any encoders that needs to be disabled. */
8000 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8001 base.head) {
8002 list_for_each_entry(connector,
8003 &dev->mode_config.connector_list,
8004 base.head) {
8005 if (connector->new_encoder == encoder) {
8006 WARN_ON(!connector->new_encoder->new_crtc);
8007
8008 goto next_encoder;
8009 }
8010 }
8011 encoder->new_crtc = NULL;
8012next_encoder:
8013 /* Only now check for crtc changes so we don't miss encoders
8014 * that will be disabled. */
8015 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8016 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8017 config->mode_changed = true;
50f56119
DV		 8018 }
8019 }
9a935856 8020 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8021
2e431051
DV		 8022 return 0;
8023}
8024
8025static int intel_crtc_set_config(struct drm_mode_set *set)
8026{
8027 struct drm_device *dev;
2e431051
DV		 8028 struct drm_mode_set save_set;
8029 struct intel_set_config *config;
8030 int ret;
2e431051 8031
8d3e375e
DV		 8032 BUG_ON(!set);
8033 BUG_ON(!set->crtc);
8034 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8035
8036 if (!set->mode)
8037 set->fb = NULL;
8038
431e50f7
DV		 8039 /* The fb helper likes to play gross jokes with ->mode_set_config.
8040 * Unfortunately the crtc helper doesn't do much at all for this case,
8041 * so we have to cope with this madness until the fb helper is fixed up. */
8042 if (set->fb && set->num_connectors == 0)
8043 return 0;
8044
2e431051
DV		 8045 if (set->fb) {
8046 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8047 set->crtc->base.id, set->fb->base.id,
8048 (int)set->num_connectors, set->x, set->y);
8049 } else {
8050 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8051 }
8052
8053 dev = set->crtc->dev;
8054
8055 ret = -ENOMEM;
8056 config = kzalloc(sizeof(*config), GFP_KERNEL);
8057 if (!config)
8058 goto out_config;
8059
8060 ret = intel_set_config_save_state(dev, config);
8061 if (ret)
8062 goto out_config;
8063
8064 save_set.crtc = set->crtc;
8065 save_set.mode = &set->crtc->mode;
8066 save_set.x = set->crtc->x;
8067 save_set.y = set->crtc->y;
8068 save_set.fb = set->crtc->fb;
8069
8070 /* Compute whether we need a full modeset, only an fb base update or no
8071 * change at all. In the future we might also check whether only the
8072 * mode changed, e.g. for LVDS where we only change the panel fitter in
8073 * such cases. */
8074 intel_set_config_compute_mode_changes(set, config);
8075
9a935856 8076 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8077 if (ret)
8078 goto fail;
8079
5e2b584e 8080 if (config->mode_changed) {
87f1faa6 8081 if (set->mode) {
50f56119
DV		 8082 DRM_DEBUG_KMS("attempting to set mode from"
8083 " userspace\n");
8084 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8085 }
8086
8087 if (!intel_set_mode(set->crtc, set->mode,
8088 set->x, set->y, set->fb)) {
8089 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8090 set->crtc->base.id);
8091 ret = -EINVAL;
8092 goto fail;
8093 }
5e2b584e 8094 } else if (config->fb_changed) {
4f660f49 8095 ret = intel_pipe_set_base(set->crtc,
94352cf9 8096 set->x, set->y, set->fb);
50f56119
DV		 8097 }
8098
d9e55608
DV		 8099 intel_set_config_free(config);
8100
50f56119
DV		 8101 return 0;
8102
8103fail:
85f9eb71 8104 intel_set_config_restore_state(dev, config);
50f56119
DV		 8105
8106 /* Try to restore the config */
5e2b584e 8107 if (config->mode_changed &&
a6778b3c
DV		 8108 !intel_set_mode(save_set.crtc, save_set.mode,
8109 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8110 DRM_ERROR("failed to restore config after modeset failure\n");
8111
d9e55608
DV		 8112out_config:
8113 intel_set_config_free(config);
50f56119
DV		 8114 return ret;
8115}
f6e5b160
CW		 8116
8117static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8118 .cursor_set = intel_crtc_cursor_set,
8119 .cursor_move = intel_crtc_cursor_move,
8120 .gamma_set = intel_crtc_gamma_set,
50f56119 8121 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8122 .destroy = intel_crtc_destroy,
8123 .page_flip = intel_crtc_page_flip,
8124};
8125
79f689aa
PZ		 8126static void intel_cpu_pll_init(struct drm_device *dev)
8127{
8128 if (IS_HASWELL(dev))
8129 intel_ddi_pll_init(dev);
8130}
8131
ee7b9f93
JB		 8132static void intel_pch_pll_init(struct drm_device *dev)
8133{
8134 drm_i915_private_t *dev_priv = dev->dev_private;
8135 int i;
8136
8137 if (dev_priv->num_pch_pll == 0) {
8138 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8139 return;
8140 }
8141
8142 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8143 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8144 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8145 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8146 }
8147}
8148
b358d0a6 8149static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8150{
22fd0fab 8151 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8152 struct intel_crtc *intel_crtc;
8153 int i;
8154
8155 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8156 if (intel_crtc == NULL)
8157 return;
8158
8159 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8160
8161 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8162 for (i = 0; i < 256; i++) {
8163 intel_crtc->lut_r[i] = i;
8164 intel_crtc->lut_g[i] = i;
8165 intel_crtc->lut_b[i] = i;
8166 }
8167
80824003
JB		 8168 /* Swap pipes & planes for FBC on pre-965 */
8169 intel_crtc->pipe = pipe;
8170 intel_crtc->plane = pipe;
a5c961d1 8171 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8172 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8173 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8174 intel_crtc->plane = !pipe;
80824003
JB		 8175 }
8176
22fd0fab
JB		 8177 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8178 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8179 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8180 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8181
5a354204 8182 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8183
79e53945 8184 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8185}
8186
08d7b3d1 8187int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8188 struct drm_file *file)
08d7b3d1 8189{
08d7b3d1 8190 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8191 struct drm_mode_object *drmmode_obj;
8192 struct intel_crtc *crtc;
08d7b3d1 8193
1cff8f6b
DV		 8194 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8195 return -ENODEV;
08d7b3d1 8196
c05422d5
DV		 8197 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8198 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8199
c05422d5 8200 if (!drmmode_obj) {
08d7b3d1
CW		 8201 DRM_ERROR("no such CRTC id\n");
8202 return -EINVAL;
8203 }
8204
c05422d5
DV		 8205 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8206 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8207
c05422d5 8208 return 0;
08d7b3d1
CW		 8209}
8210
66a9278e 8211static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8212{
66a9278e
DV		 8213 struct drm_device *dev = encoder->base.dev;
8214 struct intel_encoder *source_encoder;
79e53945 8215 int index_mask = 0;
79e53945
JB		 8216 int entry = 0;
8217
66a9278e
DV		 8218 list_for_each_entry(source_encoder,
8219 &dev->mode_config.encoder_list, base.head) {
8220
8221 if (encoder == source_encoder)
79e53945 8222 index_mask |= (1 << entry);
66a9278e
DV		 8223
8224 /* Intel hw has only one MUX where enocoders could be cloned. */
8225 if (encoder->cloneable && source_encoder->cloneable)
8226 index_mask |= (1 << entry);
8227
79e53945
JB		 8228 entry++;
8229 }
4ef69c7a 8230
79e53945
JB		 8231 return index_mask;
8232}
8233
4d302442
CW		 8234static bool has_edp_a(struct drm_device *dev)
8235{
8236 struct drm_i915_private *dev_priv = dev->dev_private;
8237
8238 if (!IS_MOBILE(dev))
8239 return false;
8240
8241 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8242 return false;
8243
8244 if (IS_GEN5(dev) &&
8245 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8246 return false;
8247
8248 return true;
8249}
8250
79e53945
JB		 8251static void intel_setup_outputs(struct drm_device *dev)
8252{
725e30ad 8253 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8254 struct intel_encoder *encoder;
cb0953d7 8255 bool dpd_is_edp = false;
f3cfcba6 8256 bool has_lvds;
79e53945 8257
f3cfcba6 8258 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8259 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8260 /* disable the panel fitter on everything but LVDS */
8261 I915_WRITE(PFIT_CONTROL, 0);
8262 }
79e53945 8263
79935fca
PZ		 8264 if (!(IS_HASWELL(dev) &&
8265 (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8266 intel_crt_init(dev);
cb0953d7 8267
0e72a5b5
ED		 8268 if (IS_HASWELL(dev)) {
8269 int found;
8270
8271 /* Haswell uses DDI functions to detect digital outputs */
8272 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8273 /* DDI A only supports eDP */
8274 if (found)
8275 intel_ddi_init(dev, PORT_A);
8276
8277 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8278 * register */
8279 found = I915_READ(SFUSE_STRAP);
8280
8281 if (found & SFUSE_STRAP_DDIB_DETECTED)
8282 intel_ddi_init(dev, PORT_B);
8283 if (found & SFUSE_STRAP_DDIC_DETECTED)
8284 intel_ddi_init(dev, PORT_C);
8285 if (found & SFUSE_STRAP_DDID_DETECTED)
8286 intel_ddi_init(dev, PORT_D);
8287 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8288 int found;
270b3042
DV		 8289 dpd_is_edp = intel_dpd_is_edp(dev);
8290
8291 if (has_edp_a(dev))
8292 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8293
30ad48b7 8294 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8295 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8296 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8297 if (!found)
08d644ad 8298 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8299 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8300 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8301 }
8302
8303 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8304 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8305
b708a1d5 8306 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8307 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8308
5eb08b69 8309 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8310 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8311
270b3042 8312 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8313 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8314 } else if (IS_VALLEYVIEW(dev)) {
8315 int found;
8316
19c03924
GB		 8317 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8318 if (I915_READ(DP_C) & DP_DETECTED)
8319 intel_dp_init(dev, DP_C, PORT_C);
8320
4a87d65d
JB		 8321 if (I915_READ(SDVOB) & PORT_DETECTED) {
8322 /* SDVOB multiplex with HDMIB */
8323 found = intel_sdvo_init(dev, SDVOB, true);
8324 if (!found)
08d644ad 8325 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8326 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8327 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8328 }
8329
8330 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8331 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8332
103a196f 8333 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8334 bool found = false;
7d57382e 8335
725e30ad 8336 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8337 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8338 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8339 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8340 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8341 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8342 }
27185ae1 8343
b01f2c3a
JB		 8344 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8345 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8346 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8347 }
725e30ad 8348 }
13520b05
KH		 8349
8350 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8351
b01f2c3a
JB		 8352 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8353 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8354 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8355 }
27185ae1
ML		 8356
8357 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8358
b01f2c3a
JB		 8359 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8360 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8361 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8362 }
8363 if (SUPPORTS_INTEGRATED_DP(dev)) {
8364 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8365 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8366 }
725e30ad 8367 }
27185ae1 8368
b01f2c3a
JB		 8369 if (SUPPORTS_INTEGRATED_DP(dev) &&
8370 (I915_READ(DP_D) & DP_DETECTED)) {
8371 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8372 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8373 }
bad720ff 8374 } else if (IS_GEN2(dev))
79e53945
JB		 8375 intel_dvo_init(dev);
8376
103a196f 8377 if (SUPPORTS_TV(dev))
79e53945
JB		 8378 intel_tv_init(dev);
8379
4ef69c7a
CW		 8380 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8381 encoder->base.possible_crtcs = encoder->crtc_mask;
8382 encoder->base.possible_clones =
66a9278e 8383 intel_encoder_clones(encoder);
79e53945 8384 }
47356eb6 8385
40579abe 8386 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8387 ironlake_init_pch_refclk(dev);
270b3042
DV		 8388
8389 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8390}
8391
8392static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8393{
8394 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8395
8396 drm_framebuffer_cleanup(fb);
05394f39 8397 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8398
8399 kfree(intel_fb);
8400}
8401
8402static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8403 struct drm_file *file,
79e53945
JB		 8404 unsigned int *handle)
8405{
8406 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8407 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8408
05394f39 8409 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8410}
8411
8412static const struct drm_framebuffer_funcs intel_fb_funcs = {
8413 .destroy = intel_user_framebuffer_destroy,
8414 .create_handle = intel_user_framebuffer_create_handle,
8415};
8416
38651674
DA		 8417int intel_framebuffer_init(struct drm_device *dev,
8418 struct intel_framebuffer *intel_fb,
308e5bcb 8419 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8420 struct drm_i915_gem_object *obj)
79e53945 8421{
79e53945
JB		 8422 int ret;
8423
05394f39 8424 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8425 return -EINVAL;
8426
308e5bcb 8427 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8428 return -EINVAL;
8429
5d7bd705
VS		 8430 /* FIXME <= Gen4 stride limits are bit unclear */
8431 if (mode_cmd->pitches[0] > 32768)
8432 return -EINVAL;
8433
8434 if (obj->tiling_mode != I915_TILING_NONE &&
8435 mode_cmd->pitches[0] != obj->stride)
8436 return -EINVAL;
8437
57779d06 8438 /* Reject formats not supported by any plane early. */
308e5bcb 8439 switch (mode_cmd->pixel_format) {
57779d06 8440 case DRM_FORMAT_C8:
04b3924d
VS		 8441 case DRM_FORMAT_RGB565:
8442 case DRM_FORMAT_XRGB8888:
8443 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8444 break;
8445 case DRM_FORMAT_XRGB1555:
8446 case DRM_FORMAT_ARGB1555:
8447 if (INTEL_INFO(dev)->gen > 3)
8448 return -EINVAL;
8449 break;
8450 case DRM_FORMAT_XBGR8888:
8451 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8452 case DRM_FORMAT_XRGB2101010:
8453 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8454 case DRM_FORMAT_XBGR2101010:
8455 case DRM_FORMAT_ABGR2101010:
8456 if (INTEL_INFO(dev)->gen < 4)
8457 return -EINVAL;
b5626747 8458 break;
04b3924d
VS		 8459 case DRM_FORMAT_YUYV:
8460 case DRM_FORMAT_UYVY:
8461 case DRM_FORMAT_YVYU:
8462 case DRM_FORMAT_VYUY:
57779d06
VS		 8463 if (INTEL_INFO(dev)->gen < 6)
8464 return -EINVAL;
57cd6508
CW		 8465 break;
8466 default:
57779d06 8467 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8468 return -EINVAL;
8469 }
8470
90f9a336
VS		 8471 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8472 if (mode_cmd->offsets[0] != 0)
8473 return -EINVAL;
8474
79e53945
JB		 8475 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8476 if (ret) {
8477 DRM_ERROR("framebuffer init failed %d\n", ret);
8478 return ret;
8479 }
8480
8481 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8482 intel_fb->obj = obj;
79e53945
JB		 8483 return 0;
8484}
8485
79e53945
JB		 8486static struct drm_framebuffer *
8487intel_user_framebuffer_create(struct drm_device *dev,
8488 struct drm_file *filp,
308e5bcb 8489 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8490{
05394f39 8491 struct drm_i915_gem_object *obj;
79e53945 8492
308e5bcb
JB		 8493 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8494 mode_cmd->handles[0]));
c8725226 8495 if (&obj->base == NULL)
cce13ff7 8496 return ERR_PTR(-ENOENT);
79e53945 8497
d2dff872 8498 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8499}
8500
79e53945 8501static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8502 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8503 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8504};
8505
e70236a8
JB		 8506/* Set up chip specific display functions */
8507static void intel_init_display(struct drm_device *dev)
8508{
8509 struct drm_i915_private *dev_priv = dev->dev_private;
8510
8511 /* We always want a DPMS function */
09b4ddf9
PZ		 8512 if (IS_HASWELL(dev)) {
8513 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8514 dev_priv->display.crtc_enable = haswell_crtc_enable;
8515 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8516 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8517 dev_priv->display.update_plane = ironlake_update_plane;
8518 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8519 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8520 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8521 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8522 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8523 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8524 } else {
f564048e 8525 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8526 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8527 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8528 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8529 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8530 }
e70236a8 8531
e70236a8 8532 /* Returns the core display clock speed */
25eb05fc
JB		 8533 if (IS_VALLEYVIEW(dev))
8534 dev_priv->display.get_display_clock_speed =
8535 valleyview_get_display_clock_speed;
8536 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8537 dev_priv->display.get_display_clock_speed =
8538 i945_get_display_clock_speed;
8539 else if (IS_I915G(dev))
8540 dev_priv->display.get_display_clock_speed =
8541 i915_get_display_clock_speed;
f2b115e6 8542 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8543 dev_priv->display.get_display_clock_speed =
8544 i9xx_misc_get_display_clock_speed;
8545 else if (IS_I915GM(dev))
8546 dev_priv->display.get_display_clock_speed =
8547 i915gm_get_display_clock_speed;
8548 else if (IS_I865G(dev))
8549 dev_priv->display.get_display_clock_speed =
8550 i865_get_display_clock_speed;
f0f8a9ce 8551 else if (IS_I85X(dev))
e70236a8
JB		 8552 dev_priv->display.get_display_clock_speed =
8553 i855_get_display_clock_speed;
8554 else /* 852, 830 */
8555 dev_priv->display.get_display_clock_speed =
8556 i830_get_display_clock_speed;
8557
7f8a8569 8558 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8559 if (IS_GEN5(dev)) {
674cf967 8560 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8561 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8562 } else if (IS_GEN6(dev)) {
674cf967 8563 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8564 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8565 } else if (IS_IVYBRIDGE(dev)) {
8566 /* FIXME: detect B0+ stepping and use auto training */
8567 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8568 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8569 dev_priv->display.modeset_global_resources =
8570 ivb_modeset_global_resources;
c82e4d26
ED		 8571 } else if (IS_HASWELL(dev)) {
8572 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8573 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8574 } else
8575 dev_priv->display.update_wm = NULL;
6067aaea 8576 } else if (IS_G4X(dev)) {
e0dac65e 8577 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8578 }
8c9f3aaf
JB		 8579
8580 /* Default just returns -ENODEV to indicate unsupported */
8581 dev_priv->display.queue_flip = intel_default_queue_flip;
8582
8583 switch (INTEL_INFO(dev)->gen) {
8584 case 2:
8585 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8586 break;
8587
8588 case 3:
8589 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8590 break;
8591
8592 case 4:
8593 case 5:
8594 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8595 break;
8596
8597 case 6:
8598 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8599 break;
7c9017e5
JB		 8600 case 7:
8601 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8602 break;
8c9f3aaf 8603 }
e70236a8
JB		 8604}
8605
b690e96c
JB		 8606/*
8607 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8608 * resume, or other times. This quirk makes sure that's the case for
8609 * affected systems.
8610 */
0206e353 8611static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8612{
8613 struct drm_i915_private *dev_priv = dev->dev_private;
8614
8615 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8616 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8617}
8618
435793df
KP		 8619/*
8620 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8621 */
8622static void quirk_ssc_force_disable(struct drm_device *dev)
8623{
8624 struct drm_i915_private *dev_priv = dev->dev_private;
8625 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8626 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8627}
8628
4dca20ef 8629/*
5a15ab5b
CE		 8630 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8631 * brightness value
4dca20ef
CE		 8632 */
8633static void quirk_invert_brightness(struct drm_device *dev)
8634{
8635 struct drm_i915_private *dev_priv = dev->dev_private;
8636 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8637 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8638}
8639
b690e96c
JB		 8640struct intel_quirk {
8641 int device;
8642 int subsystem_vendor;
8643 int subsystem_device;
8644 void (*hook)(struct drm_device *dev);
8645};
8646
5f85f176
EE		 8647/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8648struct intel_dmi_quirk {
8649 void (*hook)(struct drm_device *dev);
8650 const struct dmi_system_id (*dmi_id_list)[];
8651};
8652
8653static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8654{
8655 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8656 return 1;
8657}
8658
8659static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8660 {
8661 .dmi_id_list = &(const struct dmi_system_id[]) {
8662 {
8663 .callback = intel_dmi_reverse_brightness,
8664 .ident = "NCR Corporation",
8665 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8666 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8667 },
8668 },
8669 { } /* terminating entry */
8670 },
8671 .hook = quirk_invert_brightness,
8672 },
8673};
8674
c43b5634 8675static struct intel_quirk intel_quirks[] = {
b690e96c 8676 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8677 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8678
b690e96c
JB		 8679 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8680 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8681
b690e96c
JB		 8682 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8683 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8684
ccd0d36e 8685 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8686 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8687 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8688
8689 /* Lenovo U160 cannot use SSC on LVDS */
8690 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8691
8692 /* Sony Vaio Y cannot use SSC on LVDS */
8693 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8694
8695 /* Acer Aspire 5734Z must invert backlight brightness */
8696 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8697};
8698
8699static void intel_init_quirks(struct drm_device *dev)
8700{
8701 struct pci_dev *d = dev->pdev;
8702 int i;
8703
8704 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8705 struct intel_quirk *q = &intel_quirks[i];
8706
8707 if (d->device == q->device &&
8708 (d->subsystem_vendor == q->subsystem_vendor ||
8709 q->subsystem_vendor == PCI_ANY_ID) &&
8710 (d->subsystem_device == q->subsystem_device ||
8711 q->subsystem_device == PCI_ANY_ID))
8712 q->hook(dev);
8713 }
5f85f176
EE		 8714 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8715 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8716 intel_dmi_quirks[i].hook(dev);
8717 }
b690e96c
JB		 8718}
8719
9cce37f4
JB		 8720/* Disable the VGA plane that we never use */
8721static void i915_disable_vga(struct drm_device *dev)
8722{
8723 struct drm_i915_private *dev_priv = dev->dev_private;
8724 u8 sr1;
8725 u32 vga_reg;
8726
8727 if (HAS_PCH_SPLIT(dev))
8728 vga_reg = CPU_VGACNTRL;
8729 else
8730 vga_reg = VGACNTRL;
8731
8732 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8733 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8734 sr1 = inb(VGA_SR_DATA);
8735 outb(sr1 | 1<<5, VGA_SR_DATA);
8736 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8737 udelay(300);
8738
8739 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8740 POSTING_READ(vga_reg);
8741}
8742
f817586c
DV		 8743void intel_modeset_init_hw(struct drm_device *dev)
8744{
0232e927
ED		 8745 /* We attempt to init the necessary power wells early in the initialization
8746 * time, so the subsystems that expect power to be enabled can work.
8747 */
8748 intel_init_power_wells(dev);
8749
a8f78b58
ED		 8750 intel_prepare_ddi(dev);
8751
f817586c
DV		 8752 intel_init_clock_gating(dev);
8753
79f5b2c7 8754 mutex_lock(&dev->struct_mutex);
8090c6b9 8755 intel_enable_gt_powersave(dev);
79f5b2c7 8756 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8757}
8758
79e53945
JB		 8759void intel_modeset_init(struct drm_device *dev)
8760{
652c393a 8761 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8762 int i, ret;
79e53945
JB		 8763
8764 drm_mode_config_init(dev);
8765
8766 dev->mode_config.min_width = 0;
8767 dev->mode_config.min_height = 0;
8768
019d96cb
DA		 8769 dev->mode_config.preferred_depth = 24;
8770 dev->mode_config.prefer_shadow = 1;
8771
e6ecefaa 8772 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8773
b690e96c
JB		 8774 intel_init_quirks(dev);
8775
1fa61106
ED		 8776 intel_init_pm(dev);
8777
e70236a8
JB		 8778 intel_init_display(dev);
8779
a6c45cf0
CW		 8780 if (IS_GEN2(dev)) {
8781 dev->mode_config.max_width = 2048;
8782 dev->mode_config.max_height = 2048;
8783 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8784 dev->mode_config.max_width = 4096;
8785 dev->mode_config.max_height = 4096;
79e53945 8786 } else {
a6c45cf0
CW		 8787 dev->mode_config.max_width = 8192;
8788 dev->mode_config.max_height = 8192;
79e53945 8789 }
dd2757f8 8790 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8791
28c97730 8792 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8793 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8794
a3524f1b 8795 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8796 intel_crtc_init(dev, i);
00c2064b
JB		 8797 ret = intel_plane_init(dev, i);
8798 if (ret)
8799 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8800 }
8801
79f689aa 8802 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8803 intel_pch_pll_init(dev);
8804
9cce37f4
JB		 8805 /* Just disable it once at startup */
8806 i915_disable_vga(dev);
79e53945 8807 intel_setup_outputs(dev);
2c7111db
CW		 8808}
8809
24929352
DV		 8810static void
8811intel_connector_break_all_links(struct intel_connector *connector)
8812{
8813 connector->base.dpms = DRM_MODE_DPMS_OFF;
8814 connector->base.encoder = NULL;
8815 connector->encoder->connectors_active = false;
8816 connector->encoder->base.crtc = NULL;
8817}
8818
7fad798e
DV		 8819static void intel_enable_pipe_a(struct drm_device *dev)
8820{
8821 struct intel_connector *connector;
8822 struct drm_connector *crt = NULL;
8823 struct intel_load_detect_pipe load_detect_temp;
8824
8825 /* We can't just switch on the pipe A, we need to set things up with a
8826 * proper mode and output configuration. As a gross hack, enable pipe A
8827 * by enabling the load detect pipe once. */
8828 list_for_each_entry(connector,
8829 &dev->mode_config.connector_list,
8830 base.head) {
8831 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8832 crt = &connector->base;
8833 break;
8834 }
8835 }
8836
8837 if (!crt)
8838 return;
8839
8840 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8841 intel_release_load_detect_pipe(crt, &load_detect_temp);
8842
652c393a 8843
7fad798e
DV		 8844}
8845
fa555837
DV		 8846static bool
8847intel_check_plane_mapping(struct intel_crtc *crtc)
8848{
8849 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8850 u32 reg, val;
8851
8852 if (dev_priv->num_pipe == 1)
8853 return true;
8854
8855 reg = DSPCNTR(!crtc->plane);
8856 val = I915_READ(reg);
8857
8858 if ((val & DISPLAY_PLANE_ENABLE) &&
8859 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8860 return false;
8861
8862 return true;
8863}
8864
24929352
DV		 8865static void intel_sanitize_crtc(struct intel_crtc *crtc)
8866{
8867 struct drm_device *dev = crtc->base.dev;
8868 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8869 u32 reg;
24929352 8870
24929352 8871 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8872 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8873 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8874
8875 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8876 * disable the crtc (and hence change the state) if it is wrong. Note
8877 * that gen4+ has a fixed plane -> pipe mapping. */
8878 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8879 struct intel_connector *connector;
8880 bool plane;
8881
24929352
DV		 8882 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8883 crtc->base.base.id);
8884
8885 /* Pipe has the wrong plane attached and the plane is active.
8886 * Temporarily change the plane mapping and disable everything
8887 * ... */
8888 plane = crtc->plane;
8889 crtc->plane = !plane;
8890 dev_priv->display.crtc_disable(&crtc->base);
8891 crtc->plane = plane;
8892
8893 /* ... and break all links. */
8894 list_for_each_entry(connector, &dev->mode_config.connector_list,
8895 base.head) {
8896 if (connector->encoder->base.crtc != &crtc->base)
8897 continue;
8898
8899 intel_connector_break_all_links(connector);
8900 }
8901
8902 WARN_ON(crtc->active);
8903 crtc->base.enabled = false;
8904 }
24929352 8905
7fad798e
DV		 8906 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8907 crtc->pipe == PIPE_A && !crtc->active) {
8908 /* BIOS forgot to enable pipe A, this mostly happens after
8909 * resume. Force-enable the pipe to fix this, the update_dpms
8910 * call below we restore the pipe to the right state, but leave
8911 * the required bits on. */
8912 intel_enable_pipe_a(dev);
8913 }
8914
24929352
DV		 8915 /* Adjust the state of the output pipe according to whether we
8916 * have active connectors/encoders. */
8917 intel_crtc_update_dpms(&crtc->base);
8918
8919 if (crtc->active != crtc->base.enabled) {
8920 struct intel_encoder *encoder;
8921
8922 /* This can happen either due to bugs in the get_hw_state
8923 * functions or because the pipe is force-enabled due to the
8924 * pipe A quirk. */
8925 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8926 crtc->base.base.id,
8927 crtc->base.enabled ? "enabled" : "disabled",
8928 crtc->active ? "enabled" : "disabled");
8929
8930 crtc->base.enabled = crtc->active;
8931
8932 /* Because we only establish the connector -> encoder ->
8933 * crtc links if something is active, this means the
8934 * crtc is now deactivated. Break the links. connector
8935 * -> encoder links are only establish when things are
8936 * actually up, hence no need to break them. */
8937 WARN_ON(crtc->active);
8938
8939 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8940 WARN_ON(encoder->connectors_active);
8941 encoder->base.crtc = NULL;
8942 }
8943 }
8944}
8945
8946static void intel_sanitize_encoder(struct intel_encoder *encoder)
8947{
8948 struct intel_connector *connector;
8949 struct drm_device *dev = encoder->base.dev;
8950
8951 /* We need to check both for a crtc link (meaning that the
8952 * encoder is active and trying to read from a pipe) and the
8953 * pipe itself being active. */
8954 bool has_active_crtc = encoder->base.crtc &&
8955 to_intel_crtc(encoder->base.crtc)->active;
8956
8957 if (encoder->connectors_active && !has_active_crtc) {
8958 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8959 encoder->base.base.id,
8960 drm_get_encoder_name(&encoder->base));
8961
8962 /* Connector is active, but has no active pipe. This is
8963 * fallout from our resume register restoring. Disable
8964 * the encoder manually again. */
8965 if (encoder->base.crtc) {
8966 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8967 encoder->base.base.id,
8968 drm_get_encoder_name(&encoder->base));
8969 encoder->disable(encoder);
8970 }
8971
8972 /* Inconsistent output/port/pipe state happens presumably due to
8973 * a bug in one of the get_hw_state functions. Or someplace else
8974 * in our code, like the register restore mess on resume. Clamp
8975 * things to off as a safer default. */
8976 list_for_each_entry(connector,
8977 &dev->mode_config.connector_list,
8978 base.head) {
8979 if (connector->encoder != encoder)
8980 continue;
8981
8982 intel_connector_break_all_links(connector);
8983 }
8984 }
8985 /* Enabled encoders without active connectors will be fixed in
8986 * the crtc fixup. */
8987}
8988
8989/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8990 * and i915 state tracking structures. */
8991void intel_modeset_setup_hw_state(struct drm_device *dev)
8992{
8993 struct drm_i915_private *dev_priv = dev->dev_private;
8994 enum pipe pipe;
8995 u32 tmp;
8996 struct intel_crtc *crtc;
8997 struct intel_encoder *encoder;
8998 struct intel_connector *connector;
8999
e28d54cb
PZ		 9000 if (IS_HASWELL(dev)) {
9001 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9002
9003 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9004 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9005 case TRANS_DDI_EDP_INPUT_A_ON:
9006 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9007 pipe = PIPE_A;
9008 break;
9009 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9010 pipe = PIPE_B;
9011 break;
9012 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9013 pipe = PIPE_C;
9014 break;
9015 }
9016
9017 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9018 crtc->cpu_transcoder = TRANSCODER_EDP;
9019
9020 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9021 pipe_name(pipe));
9022 }
9023 }
9024
24929352
DV		 9025 for_each_pipe(pipe) {
9026 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9027
702e7a56 9028 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9029 if (tmp & PIPECONF_ENABLE)
9030 crtc->active = true;
9031 else
9032 crtc->active = false;
9033
9034 crtc->base.enabled = crtc->active;
9035
9036 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9037 crtc->base.base.id,
9038 crtc->active ? "enabled" : "disabled");
9039 }
9040
6441ab5f
PZ		 9041 if (IS_HASWELL(dev))
9042 intel_ddi_setup_hw_pll_state(dev);
9043
24929352
DV		 9044 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9045 base.head) {
9046 pipe = 0;
9047
9048 if (encoder->get_hw_state(encoder, &pipe)) {
9049 encoder->base.crtc =
9050 dev_priv->pipe_to_crtc_mapping[pipe];
9051 } else {
9052 encoder->base.crtc = NULL;
9053 }
9054
9055 encoder->connectors_active = false;
9056 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9057 encoder->base.base.id,
9058 drm_get_encoder_name(&encoder->base),
9059 encoder->base.crtc ? "enabled" : "disabled",
9060 pipe);
9061 }
9062
9063 list_for_each_entry(connector, &dev->mode_config.connector_list,
9064 base.head) {
9065 if (connector->get_hw_state(connector)) {
9066 connector->base.dpms = DRM_MODE_DPMS_ON;
9067 connector->encoder->connectors_active = true;
9068 connector->base.encoder = &connector->encoder->base;
9069 } else {
9070 connector->base.dpms = DRM_MODE_DPMS_OFF;
9071 connector->base.encoder = NULL;
9072 }
9073 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9074 connector->base.base.id,
9075 drm_get_connector_name(&connector->base),
9076 connector->base.encoder ? "enabled" : "disabled");
9077 }
9078
9079 /* HW state is read out, now we need to sanitize this mess. */
9080 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9081 base.head) {
9082 intel_sanitize_encoder(encoder);
9083 }
9084
9085 for_each_pipe(pipe) {
9086 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9087 intel_sanitize_crtc(crtc);
9088 }
9a935856
DV		 9089
9090 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 9091
9092 intel_modeset_check_state(dev);
2e938892
DV		 9093
9094 drm_mode_config_reset(dev);
2c7111db
CW		 9095}
9096
9097void intel_modeset_gem_init(struct drm_device *dev)
9098{
1833b134 9099 intel_modeset_init_hw(dev);
02e792fb
DV		 9100
9101 intel_setup_overlay(dev);
24929352
DV		 9102
9103 intel_modeset_setup_hw_state(dev);
79e53945
JB		 9104}
9105
9106void intel_modeset_cleanup(struct drm_device *dev)
9107{
652c393a
JB		 9108 struct drm_i915_private *dev_priv = dev->dev_private;
9109 struct drm_crtc *crtc;
9110 struct intel_crtc *intel_crtc;
9111
f87ea761 9112 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9113 mutex_lock(&dev->struct_mutex);
9114
723bfd70
JB		 9115 intel_unregister_dsm_handler();
9116
9117
652c393a
JB		 9118 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9119 /* Skip inactive CRTCs */
9120 if (!crtc->fb)
9121 continue;
9122
9123 intel_crtc = to_intel_crtc(crtc);
3dec0095 9124 intel_increase_pllclock(crtc);
652c393a
JB		 9125 }
9126
973d04f9 9127 intel_disable_fbc(dev);
e70236a8 9128
8090c6b9 9129 intel_disable_gt_powersave(dev);
0cdab21f 9130
930ebb46
DV		 9131 ironlake_teardown_rc6(dev);
9132
57f350b6
JB		 9133 if (IS_VALLEYVIEW(dev))
9134 vlv_init_dpio(dev);
9135
69341a5e
KH		 9136 mutex_unlock(&dev->struct_mutex);
9137
6c0d9350
DV		 9138 /* Disable the irq before mode object teardown, for the irq might
9139 * enqueue unpin/hotplug work. */
9140 drm_irq_uninstall(dev);
9141 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9142 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9143
1630fe75
CW		 9144 /* flush any delayed tasks or pending work */
9145 flush_scheduled_work();
9146
79e53945
JB		 9147 drm_mode_config_cleanup(dev);
9148}
9149
f1c79df3
ZW		 9150/*
9151 * Return which encoder is currently attached for connector.
9152 */
df0e9248 9153struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9154{
df0e9248
CW		 9155 return &intel_attached_encoder(connector)->base;
9156}
f1c79df3 9157
df0e9248
CW		 9158void intel_connector_attach_encoder(struct intel_connector *connector,
9159 struct intel_encoder *encoder)
9160{
9161 connector->encoder = encoder;
9162 drm_mode_connector_attach_encoder(&connector->base,
9163 &encoder->base);
79e53945 9164}
28d52043
DA		 9165
9166/*
9167 * set vga decode state - true == enable VGA decode
9168 */
9169int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9170{
9171 struct drm_i915_private *dev_priv = dev->dev_private;
9172 u16 gmch_ctrl;
9173
9174 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9175 if (state)
9176 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9177 else
9178 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9179 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9180 return 0;
9181}
c4a1d9e4
CW		 9182
9183#ifdef CONFIG_DEBUG_FS
9184#include <linux/seq_file.h>
9185
9186struct intel_display_error_state {
9187 struct intel_cursor_error_state {
9188 u32 control;
9189 u32 position;
9190 u32 base;
9191 u32 size;
52331309 9192 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9193
9194 struct intel_pipe_error_state {
9195 u32 conf;
9196 u32 source;
9197
9198 u32 htotal;
9199 u32 hblank;
9200 u32 hsync;
9201 u32 vtotal;
9202 u32 vblank;
9203 u32 vsync;
52331309 9204 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9205
9206 struct intel_plane_error_state {
9207 u32 control;
9208 u32 stride;
9209 u32 size;
9210 u32 pos;
9211 u32 addr;
9212 u32 surface;
9213 u32 tile_offset;
52331309 9214 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9215};
9216
9217struct intel_display_error_state *
9218intel_display_capture_error_state(struct drm_device *dev)
9219{
0206e353 9220 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9221 struct intel_display_error_state *error;
702e7a56 9222 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9223 int i;
9224
9225 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9226 if (error == NULL)
9227 return NULL;
9228
52331309 9229 for_each_pipe(i) {
702e7a56
PZ		 9230 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9231
c4a1d9e4
CW		 9232 error->cursor[i].control = I915_READ(CURCNTR(i));
9233 error->cursor[i].position = I915_READ(CURPOS(i));
9234 error->cursor[i].base = I915_READ(CURBASE(i));
9235
9236 error->plane[i].control = I915_READ(DSPCNTR(i));
9237 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9238 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9239 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9240 error->plane[i].addr = I915_READ(DSPADDR(i));
9241 if (INTEL_INFO(dev)->gen >= 4) {
9242 error->plane[i].surface = I915_READ(DSPSURF(i));
9243 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9244 }
9245
702e7a56 9246 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9247 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9248 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9249 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9250 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9251 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9252 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9253 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9254 }
9255
9256 return error;
9257}
9258
9259void
9260intel_display_print_error_state(struct seq_file *m,
9261 struct drm_device *dev,
9262 struct intel_display_error_state *error)
9263{
52331309 9264 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9265 int i;
9266
52331309
DL		 9267 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9268 for_each_pipe(i) {
c4a1d9e4
CW		 9269 seq_printf(m, "Pipe [%d]:\n", i);
9270 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9271 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9272 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9273 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9274 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9275 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9276 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9277 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9278
9279 seq_printf(m, "Plane [%d]:\n", i);
9280 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9281 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9282 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9283 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9284 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9285 if (INTEL_INFO(dev)->gen >= 4) {
9286 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9287 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9288 }
9289
9290 seq_printf(m, "Cursor [%d]:\n", i);
9291 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9292 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9293 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9294 }
9295}
9296#endif
Linux kernel - Deliverables
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