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drm/i915: intel_unregister_dsm_handler() doesn't need struct_mutex
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
568c634a 89static int intel_set_mode(struct drm_atomic_state *state);
eb1bfe80
JB		 90static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
5b18e57c
DV		 94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
29407aab 99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 102static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
d288f65f 104static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 105 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 106static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 108static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
e7457a9a 112
0e32b39c
DA		 113static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114{
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119}
120
79e53945 121typedef struct {
0206e353 122 int min, max;
79e53945
JB		 123} intel_range_t;
124
125typedef struct {
0206e353
AJ		 126 int dot_limit;
127 int p2_slow, p2_fast;
79e53945
JB		 128} intel_p2_t;
129
d4906093
ML		 130typedef struct intel_limit intel_limit_t;
131struct intel_limit {
0206e353
AJ		 132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
d4906093 134};
79e53945 135
d2acd215
DV		 136int
137intel_pch_rawclk(struct drm_device *dev)
138{
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144}
145
021357ac
CW		 146static inline u32 /* units of 100MHz */
147intel_fdi_link_freq(struct drm_device *dev)
148{
8b99e68c
CW		 149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
021357ac
CW		 154}
155
5d536e28 156static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 157 .dot = { .min = 25000, .max = 350000 },
9c333719 158 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 159 .n = { .min = 2, .max = 16 },
0206e353
AJ		 160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 167};
168
5d536e28
DV		 169static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
9c333719 171 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 172 .n = { .min = 2, .max = 16 },
5d536e28
DV		 173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180};
181
e4b36699 182static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 183 .dot = { .min = 25000, .max = 350000 },
9c333719 184 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 185 .n = { .min = 2, .max = 16 },
0206e353
AJ		 186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
e4b36699 193};
273e27ca 194
e4b36699 195static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 219};
220
273e27ca 221
e4b36699 222static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
044c7c41 234 },
e4b36699
KP		 235};
236
237static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 248};
249
250static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
044c7c41 261 },
e4b36699
KP		 262};
263
264static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
044c7c41 275 },
e4b36699
KP		 276};
277
f2b115e6 278static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 281 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
273e27ca 284 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 291};
292
f2b115e6 293static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 304};
305
273e27ca
EA		 306/* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
b91ad0ec 311static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 322};
323
b91ad0ec 324static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 335};
336
337static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 348};
349
273e27ca 350/* LVDS 100mhz refclk limits. */
b91ad0ec 351static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
0206e353 359 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 362};
363
364static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
0206e353 372 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 375};
376
dc730512 377static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 385 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 386 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
b99ab663 389 .p1 = { .min = 2, .max = 3 },
5fdc9c49 390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 391};
392
ef9348c8
CML		 393static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 401 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407};
408
5ab7b0b7
ID		 409static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
e6292556 412 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419};
420
cdba954e
ACO		 421static bool
422needs_modeset(struct drm_crtc_state *state)
423{
424 return state->mode_changed || state->active_changed;
425}
426
e0638cdf
PZ		 427/**
428 * Returns whether any output on the specified pipe is of the specified type
429 */
4093561b 430bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 431{
409ee761 432 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 433 struct intel_encoder *encoder;
434
409ee761 435 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 436 if (encoder->type == type)
437 return true;
438
439 return false;
440}
441
d0737e1d
ACO		 442/**
443 * Returns whether any output on the specified pipe will have the specified
444 * type after a staged modeset is complete, i.e., the same as
445 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
446 * encoder->crtc.
447 */
a93e255f
ACO		 448static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
449 int type)
d0737e1d 450{
a93e255f 451 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 452 struct drm_connector *connector;
a93e255f 453 struct drm_connector_state *connector_state;
d0737e1d 454 struct intel_encoder *encoder;
a93e255f
ACO		 455 int i, num_connectors = 0;
456
da3ced29 457 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 458 if (connector_state->crtc != crtc_state->base.crtc)
459 continue;
460
461 num_connectors++;
d0737e1d 462
a93e255f
ACO		 463 encoder = to_intel_encoder(connector_state->best_encoder);
464 if (encoder->type == type)
d0737e1d 465 return true;
a93e255f
ACO		 466 }
467
468 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 469
470 return false;
471}
472
a93e255f
ACO		 473static const intel_limit_t *
474intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 475{
a93e255f 476 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 477 const intel_limit_t *limit;
b91ad0ec 478
a93e255f 479 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 480 if (intel_is_dual_link_lvds(dev)) {
1b894b59 481 if (refclk == 100000)
b91ad0ec
ZW		 482 limit = &intel_limits_ironlake_dual_lvds_100m;
483 else
484 limit = &intel_limits_ironlake_dual_lvds;
485 } else {
1b894b59 486 if (refclk == 100000)
b91ad0ec
ZW		 487 limit = &intel_limits_ironlake_single_lvds_100m;
488 else
489 limit = &intel_limits_ironlake_single_lvds;
490 }
c6bb3538 491 } else
b91ad0ec 492 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 493
494 return limit;
495}
496
a93e255f
ACO		 497static const intel_limit_t *
498intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 499{
a93e255f 500 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 501 const intel_limit_t *limit;
502
a93e255f 503 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 504 if (intel_is_dual_link_lvds(dev))
e4b36699 505 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 506 else
e4b36699 507 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 508 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
509 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 510 limit = &intel_limits_g4x_hdmi;
a93e255f 511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 512 limit = &intel_limits_g4x_sdvo;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
a93e255f
ACO		 519static const intel_limit_t *
520intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 521{
a93e255f 522 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 523 const intel_limit_t *limit;
524
5ab7b0b7
ID		 525 if (IS_BROXTON(dev))
526 limit = &intel_limits_bxt;
527 else if (HAS_PCH_SPLIT(dev))
a93e255f 528 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 529 else if (IS_G4X(dev)) {
a93e255f 530 limit = intel_g4x_limit(crtc_state);
f2b115e6 531 } else if (IS_PINEVIEW(dev)) {
a93e255f 532 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 533 limit = &intel_limits_pineview_lvds;
2177832f 534 else
f2b115e6 535 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 536 } else if (IS_CHERRYVIEW(dev)) {
537 limit = &intel_limits_chv;
a0c4da24 538 } else if (IS_VALLEYVIEW(dev)) {
dc730512 539 limit = &intel_limits_vlv;
a6c45cf0 540 } else if (!IS_GEN2(dev)) {
a93e255f 541 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945 545 } else {
a93e255f 546 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
a93e255f 548 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 549 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 550 else
551 limit = &intel_limits_i8xx_dac;
79e53945
JB		 552 }
553 return limit;
554}
555
dccbea3b
ID		 556/*
557 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
558 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
559 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
560 * The helpers' return value is the rate of the clock that is fed to the
561 * display engine's pipe which can be the above fast dot clock rate or a
562 * divided-down version of it.
563 */
f2b115e6 564/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 565static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 566{
2177832f
SL		 567 clock->m = clock->m2 + 2;
568 clock->p = clock->p1 * clock->p2;
ed5ca77e 569 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 570 return 0;
fb03ac01
VS		 571 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
572 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 573
574 return clock->dot;
2177832f
SL		 575}
576
7429e9d4
DV		 577static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
578{
579 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
580}
581
dccbea3b 582static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 583{
7429e9d4 584 clock->m = i9xx_dpll_compute_m(clock);
79e53945 585 clock->p = clock->p1 * clock->p2;
ed5ca77e 586 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 587 return 0;
fb03ac01
VS		 588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 590
591 return clock->dot;
79e53945
JB		 592}
593
dccbea3b 594static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 595{
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 599 return 0;
589eca67
ID		 600 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
601 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 602
603 return clock->dot / 5;
589eca67
ID		 604}
605
dccbea3b 606int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 607{
608 clock->m = clock->m1 * clock->m2;
609 clock->p = clock->p1 * clock->p2;
610 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 611 return 0;
ef9348c8
CML		 612 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
613 clock->n << 22);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 615
616 return clock->dot / 5;
ef9348c8
CML		 617}
618
7c04d1d9 619#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 620/**
621 * Returns whether the given set of divisors are valid for a given refclk with
622 * the given connectors.
623 */
624
1b894b59
CW		 625static bool intel_PLL_is_valid(struct drm_device *dev,
626 const intel_limit_t *limit,
627 const intel_clock_t *clock)
79e53945 628{
f01b7962
VS		 629 if (clock->n < limit->n.min || limit->n.max < clock->n)
630 INTELPllInvalid("n out of range\n");
79e53945 631 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 632 INTELPllInvalid("p1 out of range\n");
79e53945 633 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 634 INTELPllInvalid("m2 out of range\n");
79e53945 635 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 636 INTELPllInvalid("m1 out of range\n");
f01b7962 637
5ab7b0b7 638 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 639 if (clock->m1 <= clock->m2)
640 INTELPllInvalid("m1 <= m2\n");
641
5ab7b0b7 642 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 643 if (clock->p < limit->p.min || limit->p.max < clock->p)
644 INTELPllInvalid("p out of range\n");
645 if (clock->m < limit->m.min || limit->m.max < clock->m)
646 INTELPllInvalid("m out of range\n");
647 }
648
79e53945 649 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 650 INTELPllInvalid("vco out of range\n");
79e53945
JB		 651 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
652 * connector, etc., rather than just a single range.
653 */
654 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 655 INTELPllInvalid("dot out of range\n");
79e53945
JB		 656
657 return true;
658}
659
3b1429d9
VS		 660static int
661i9xx_select_p2_div(const intel_limit_t *limit,
662 const struct intel_crtc_state *crtc_state,
663 int target)
79e53945 664{
3b1429d9 665 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 666
a93e255f 667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 668 /*
a210b028
DV		 669 * For LVDS just rely on its current settings for dual-channel.
670 * We haven't figured out how to reliably set up different
671 * single/dual channel state, if we even can.
79e53945 672 */
1974cad0 673 if (intel_is_dual_link_lvds(dev))
3b1429d9 674 return limit->p2.p2_fast;
79e53945 675 else
3b1429d9 676 return limit->p2.p2_slow;
79e53945
JB		 677 } else {
678 if (target < limit->p2.dot_limit)
3b1429d9 679 return limit->p2.p2_slow;
79e53945 680 else
3b1429d9 681 return limit->p2.p2_fast;
79e53945 682 }
3b1429d9
VS		 683}
684
685static bool
686i9xx_find_best_dpll(const intel_limit_t *limit,
687 struct intel_crtc_state *crtc_state,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
690{
691 struct drm_device *dev = crtc_state->base.crtc->dev;
692 intel_clock_t clock;
693 int err = target;
79e53945 694
0206e353 695 memset(best_clock, 0, sizeof(*best_clock));
79e53945 696
3b1429d9
VS		 697 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
698
42158660
ZY		 699 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
700 clock.m1++) {
701 for (clock.m2 = limit->m2.min;
702 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 703 if (clock.m2 >= clock.m1)
42158660
ZY		 704 break;
705 for (clock.n = limit->n.min;
706 clock.n <= limit->n.max; clock.n++) {
707 for (clock.p1 = limit->p1.min;
708 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 709 int this_err;
710
dccbea3b 711 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
714 continue;
715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
718
719 this_err = abs(clock.dot - target);
720 if (this_err < err) {
721 *best_clock = clock;
722 err = this_err;
723 }
724 }
725 }
726 }
727 }
728
729 return (err != target);
730}
731
732static bool
a93e255f
ACO		 733pnv_find_best_dpll(const intel_limit_t *limit,
734 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
79e53945 737{
3b1429d9 738 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 739 intel_clock_t clock;
79e53945
JB		 740 int err = target;
741
0206e353 742 memset(best_clock, 0, sizeof(*best_clock));
79e53945 743
3b1429d9
VS		 744 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745
42158660
ZY		 746 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
747 clock.m1++) {
748 for (clock.m2 = limit->m2.min;
749 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 750 for (clock.n = limit->n.min;
751 clock.n <= limit->n.max; clock.n++) {
752 for (clock.p1 = limit->p1.min;
753 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 754 int this_err;
755
dccbea3b 756 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
79e53945 759 continue;
cec2f356
SP		 760 if (match_clock &&
761 clock.p != match_clock->p)
762 continue;
79e53945
JB		 763
764 this_err = abs(clock.dot - target);
765 if (this_err < err) {
766 *best_clock = clock;
767 err = this_err;
768 }
769 }
770 }
771 }
772 }
773
774 return (err != target);
775}
776
d4906093 777static bool
a93e255f
ACO		 778g4x_find_best_dpll(const intel_limit_t *limit,
779 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
d4906093 782{
3b1429d9 783 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 784 intel_clock_t clock;
785 int max_n;
3b1429d9 786 bool found = false;
6ba770dc
AJ		 787 /* approximately equals target * 0.00585 */
788 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 789
790 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 791
792 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
793
d4906093 794 max_n = limit->n.max;
f77f13e2 795 /* based on hardware requirement, prefer smaller n to precision */
d4906093 796 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 797 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 798 for (clock.m1 = limit->m1.max;
799 clock.m1 >= limit->m1.min; clock.m1--) {
800 for (clock.m2 = limit->m2.max;
801 clock.m2 >= limit->m2.min; clock.m2--) {
802 for (clock.p1 = limit->p1.max;
803 clock.p1 >= limit->p1.min; clock.p1--) {
804 int this_err;
805
dccbea3b 806 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 807 if (!intel_PLL_is_valid(dev, limit,
808 &clock))
d4906093 809 continue;
1b894b59
CW		 810
811 this_err = abs(clock.dot - target);
d4906093
ML		 812 if (this_err < err_most) {
813 *best_clock = clock;
814 err_most = this_err;
815 max_n = clock.n;
816 found = true;
817 }
818 }
819 }
820 }
821 }
2c07245f
ZW		 822 return found;
823}
824
d5dd62bd
ID		 825/*
826 * Check if the calculated PLL configuration is more optimal compared to the
827 * best configuration and error found so far. Return the calculated error.
828 */
829static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
830 const intel_clock_t *calculated_clock,
831 const intel_clock_t *best_clock,
832 unsigned int best_error_ppm,
833 unsigned int *error_ppm)
834{
9ca3ba01
ID		 835 /*
836 * For CHV ignore the error and consider only the P value.
837 * Prefer a bigger P value based on HW requirements.
838 */
839 if (IS_CHERRYVIEW(dev)) {
840 *error_ppm = 0;
841
842 return calculated_clock->p > best_clock->p;
843 }
844
24be4e46
ID		 845 if (WARN_ON_ONCE(!target_freq))
846 return false;
847
d5dd62bd
ID		 848 *error_ppm = div_u64(1000000ULL *
849 abs(target_freq - calculated_clock->dot),
850 target_freq);
851 /*
852 * Prefer a better P value over a better (smaller) error if the error
853 * is small. Ensure this preference for future configurations too by
854 * setting the error to 0.
855 */
856 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
857 *error_ppm = 0;
858
859 return true;
860 }
861
862 return *error_ppm + 10 < best_error_ppm;
863}
864
a0c4da24 865static bool
a93e255f
ACO		 866vlv_find_best_dpll(const intel_limit_t *limit,
867 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 868 int target, int refclk, intel_clock_t *match_clock,
869 intel_clock_t *best_clock)
a0c4da24 870{
a93e255f 871 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 872 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 873 intel_clock_t clock;
69e4f900 874 unsigned int bestppm = 1000000;
27e639bf
VS		 875 /* min update 19.2 MHz */
876 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 877 bool found = false;
a0c4da24 878
6b4bf1c4
VS		 879 target *= 5; /* fast clock */
880
881 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 882
883 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 884 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 885 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 886 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 887 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 888 clock.p = clock.p1 * clock.p2;
a0c4da24 889 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 890 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 891 unsigned int ppm;
69e4f900 892
6b4bf1c4
VS		 893 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
894 refclk * clock.m1);
895
dccbea3b 896 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 897
f01b7962
VS		 898 if (!intel_PLL_is_valid(dev, limit,
899 &clock))
43b0ac53
VS		 900 continue;
901
d5dd62bd
ID		 902 if (!vlv_PLL_is_optimal(dev, target,
903 &clock,
904 best_clock,
905 bestppm, &ppm))
906 continue;
6b4bf1c4 907
d5dd62bd
ID		 908 *best_clock = clock;
909 bestppm = ppm;
910 found = true;
a0c4da24
JB		 911 }
912 }
913 }
914 }
a0c4da24 915
49e497ef 916 return found;
a0c4da24 917}
a4fc5ed6 918
ef9348c8 919static bool
a93e255f
ACO		 920chv_find_best_dpll(const intel_limit_t *limit,
921 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 922 int target, int refclk, intel_clock_t *match_clock,
923 intel_clock_t *best_clock)
924{
a93e255f 925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 926 struct drm_device *dev = crtc->base.dev;
9ca3ba01 927 unsigned int best_error_ppm;
ef9348c8
CML		 928 intel_clock_t clock;
929 uint64_t m2;
930 int found = false;
931
932 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 933 best_error_ppm = 1000000;
ef9348c8
CML		 934
935 /*
936 * Based on hardware doc, the n always set to 1, and m1 always
937 * set to 2. If requires to support 200Mhz refclk, we need to
938 * revisit this because n may not 1 anymore.
939 */
940 clock.n = 1, clock.m1 = 2;
941 target *= 5; /* fast clock */
942
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
944 for (clock.p2 = limit->p2.p2_fast;
945 clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 947 unsigned int error_ppm;
ef9348c8
CML		 948
949 clock.p = clock.p1 * clock.p2;
950
951 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
952 clock.n) << 22, refclk * clock.m1);
953
954 if (m2 > INT_MAX/clock.m1)
955 continue;
956
957 clock.m2 = m2;
958
dccbea3b 959 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 960
961 if (!intel_PLL_is_valid(dev, limit, &clock))
962 continue;
963
9ca3ba01
ID		 964 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
965 best_error_ppm, &error_ppm))
966 continue;
967
968 *best_clock = clock;
969 best_error_ppm = error_ppm;
970 found = true;
ef9348c8
CML		 971 }
972 }
973
974 return found;
975}
976
5ab7b0b7
ID		 977bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
978 intel_clock_t *best_clock)
979{
980 int refclk = i9xx_get_refclk(crtc_state, 0);
981
982 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
983 target_clock, refclk, NULL, best_clock);
984}
985
20ddf665
VS		 986bool intel_crtc_active(struct drm_crtc *crtc)
987{
988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
989
990 /* Be paranoid as we can arrive here with only partial
991 * state retrieved from the hardware during setup.
992 *
241bfc38 993 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 994 * as Haswell has gained clock readout/fastboot support.
995 *
66e514c1 996 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 997 * properly reconstruct framebuffers.
c3d1f436
MR		 998 *
999 * FIXME: The intel_crtc->active here should be switched to
1000 * crtc->state->active once we have proper CRTC states wired up
1001 * for atomic.
20ddf665 1002 */
c3d1f436 1003 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1004 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1005}
1006
a5c961d1
PZ		 1007enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1008 enum pipe pipe)
1009{
1010 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1012
6e3c9717 1013 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1014}
1015
fbf49ea2
VS		 1016static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1017{
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 reg = PIPEDSL(pipe);
1020 u32 line1, line2;
1021 u32 line_mask;
1022
1023 if (IS_GEN2(dev))
1024 line_mask = DSL_LINEMASK_GEN2;
1025 else
1026 line_mask = DSL_LINEMASK_GEN3;
1027
1028 line1 = I915_READ(reg) & line_mask;
1029 mdelay(5);
1030 line2 = I915_READ(reg) & line_mask;
1031
1032 return line1 == line2;
1033}
1034
ab7ad7f6
KP		 1035/*
1036 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1037 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1038 *
1039 * After disabling a pipe, we can't wait for vblank in the usual way,
1040 * spinning on the vblank interrupt status bit, since we won't actually
1041 * see an interrupt when the pipe is disabled.
1042 *
ab7ad7f6
KP		 1043 * On Gen4 and above:
1044 * wait for the pipe register state bit to turn off
1045 *
1046 * Otherwise:
1047 * wait for the display line value to settle (it usually
1048 * ends up stopping at the start of the next frame).
58e10eb9 1049 *
9d0498a2 1050 */
575f7ab7 1051static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1052{
575f7ab7 1053 struct drm_device *dev = crtc->base.dev;
9d0498a2 1054 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1055 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1056 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1057
1058 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1059 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1060
1061 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1062 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1063 100))
284637d9 1064 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1065 } else {
ab7ad7f6 1066 /* Wait for the display line to settle */
fbf49ea2 1067 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1068 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1069 }
79e53945
JB		 1070}
1071
b0ea7d37
DL		 1072/*
1073 * ibx_digital_port_connected - is the specified port connected?
1074 * @dev_priv: i915 private structure
1075 * @port: the port to test
1076 *
1077 * Returns true if @port is connected, false otherwise.
1078 */
1079bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1080 struct intel_digital_port *port)
1081{
1082 u32 bit;
1083
c36346e3 1084 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1085 switch (port->port) {
c36346e3
DL		 1086 case PORT_B:
1087 bit = SDE_PORTB_HOTPLUG;
1088 break;
1089 case PORT_C:
1090 bit = SDE_PORTC_HOTPLUG;
1091 break;
1092 case PORT_D:
1093 bit = SDE_PORTD_HOTPLUG;
1094 break;
1095 default:
1096 return true;
1097 }
1098 } else {
eba905b2 1099 switch (port->port) {
c36346e3
DL		 1100 case PORT_B:
1101 bit = SDE_PORTB_HOTPLUG_CPT;
1102 break;
1103 case PORT_C:
1104 bit = SDE_PORTC_HOTPLUG_CPT;
1105 break;
1106 case PORT_D:
1107 bit = SDE_PORTD_HOTPLUG_CPT;
1108 break;
1109 default:
1110 return true;
1111 }
b0ea7d37
DL		 1112 }
1113
1114 return I915_READ(SDEISR) & bit;
1115}
1116
b24e7179
JB		 1117static const char *state_string(bool enabled)
1118{
1119 return enabled ? "on" : "off";
1120}
1121
1122/* Only for pre-ILK configs */
55607e8a
DV		 1123void assert_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
b24e7179
JB		 1125{
1126 int reg;
1127 u32 val;
1128 bool cur_state;
1129
1130 reg = DPLL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1133 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1134 "PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136}
b24e7179 1137
23538ef1
JN		 1138/* XXX: the dsi pll is shared between MIPI DSI ports */
1139static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1140{
1141 u32 val;
1142 bool cur_state;
1143
a580516d 1144 mutex_lock(&dev_priv->sb_lock);
23538ef1 1145 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1146 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1147
1148 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1149 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1150 "DSI PLL state assertion failure (expected %s, current %s)\n",
1151 state_string(state), state_string(cur_state));
1152}
1153#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1154#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1155
55607e8a 1156struct intel_shared_dpll *
e2b78267
DV		 1157intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1158{
1159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1160
6e3c9717 1161 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1162 return NULL;
1163
6e3c9717 1164 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1165}
1166
040484af 1167/* For ILK+ */
55607e8a
DV		 1168void assert_shared_dpll(struct drm_i915_private *dev_priv,
1169 struct intel_shared_dpll *pll,
1170 bool state)
040484af 1171{
040484af 1172 bool cur_state;
5358901f 1173 struct intel_dpll_hw_state hw_state;
040484af 1174
92b27b08 1175 if (WARN (!pll,
46edb027 1176 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1177 return;
ee7b9f93 1178
5358901f 1179 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1180 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1181 "%s assertion failure (expected %s, current %s)\n",
1182 pll->name, state_string(state), state_string(cur_state));
040484af 1183}
040484af
JB		 1184
1185static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187{
1188 int reg;
1189 u32 val;
1190 bool cur_state;
ad80a810
PZ		 1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192 pipe);
040484af 1193
affa9354
PZ		 1194 if (HAS_DDI(dev_priv->dev)) {
1195 /* DDI does not have a specific FDI_TX register */
ad80a810 1196 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1197 val = I915_READ(reg);
ad80a810 1198 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1199 } else {
1200 reg = FDI_TX_CTL(pipe);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & FDI_TX_ENABLE);
1203 }
e2c719b7 1204 I915_STATE_WARN(cur_state != state,
040484af
JB		 1205 "FDI TX state assertion failure (expected %s, current %s)\n",
1206 state_string(state), state_string(cur_state));
1207}
1208#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1209#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1210
1211static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1212 enum pipe pipe, bool state)
1213{
1214 int reg;
1215 u32 val;
1216 bool cur_state;
1217
d63fa0dc
PZ		 1218 reg = FDI_RX_CTL(pipe);
1219 val = I915_READ(reg);
1220 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1221 I915_STATE_WARN(cur_state != state,
040484af
JB		 1222 "FDI RX state assertion failure (expected %s, current %s)\n",
1223 state_string(state), state_string(cur_state));
1224}
1225#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1226#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1227
1228static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230{
1231 int reg;
1232 u32 val;
1233
1234 /* ILK FDI PLL is always enabled */
3d13ef2e 1235 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1236 return;
1237
bf507ef7 1238 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1239 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1240 return;
1241
040484af
JB		 1242 reg = FDI_TX_CTL(pipe);
1243 val = I915_READ(reg);
e2c719b7 1244 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1245}
1246
55607e8a
DV		 1247void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1248 enum pipe pipe, bool state)
040484af
JB		 1249{
1250 int reg;
1251 u32 val;
55607e8a 1252 bool cur_state;
040484af
JB		 1253
1254 reg = FDI_RX_CTL(pipe);
1255 val = I915_READ(reg);
55607e8a 1256 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1257 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1258 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1259 state_string(state), state_string(cur_state));
040484af
JB		 1260}
1261
b680c37a
DV		 1262void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
ea0760cf 1264{
bedd4dba
JN		 1265 struct drm_device *dev = dev_priv->dev;
1266 int pp_reg;
ea0760cf
JB		 1267 u32 val;
1268 enum pipe panel_pipe = PIPE_A;
0de3b485 1269 bool locked = true;
ea0760cf 1270
bedd4dba
JN		 1271 if (WARN_ON(HAS_DDI(dev)))
1272 return;
1273
1274 if (HAS_PCH_SPLIT(dev)) {
1275 u32 port_sel;
1276
ea0760cf 1277 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1278 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1279
1280 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1281 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1282 panel_pipe = PIPE_B;
1283 /* XXX: else fix for eDP */
1284 } else if (IS_VALLEYVIEW(dev)) {
1285 /* presumably write lock depends on pipe, not port select */
1286 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1287 panel_pipe = pipe;
ea0760cf
JB		 1288 } else {
1289 pp_reg = PP_CONTROL;
bedd4dba
JN		 1290 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1291 panel_pipe = PIPE_B;
ea0760cf
JB		 1292 }
1293
1294 val = I915_READ(pp_reg);
1295 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1296 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1297 locked = false;
1298
e2c719b7 1299 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1300 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1301 pipe_name(pipe));
ea0760cf
JB		 1302}
1303
93ce0ba6
JN		 1304static void assert_cursor(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, bool state)
1306{
1307 struct drm_device *dev = dev_priv->dev;
1308 bool cur_state;
1309
d9d82081 1310 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1311 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1312 else
5efb3e28 1313 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1314
e2c719b7 1315 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1316 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe), state_string(state), state_string(cur_state));
1318}
1319#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1320#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1321
b840d907
JB		 1322void assert_pipe(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
b24e7179
JB		 1324{
1325 int reg;
1326 u32 val;
63d7bbe9 1327 bool cur_state;
702e7a56
PZ		 1328 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1329 pipe);
b24e7179 1330
b6b5d049
VS		 1331 /* if we need the pipe quirk it must be always on */
1332 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1333 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1334 state = true;
1335
f458ebbc 1336 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1337 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1338 cur_state = false;
1339 } else {
1340 reg = PIPECONF(cpu_transcoder);
1341 val = I915_READ(reg);
1342 cur_state = !!(val & PIPECONF_ENABLE);
1343 }
1344
e2c719b7 1345 I915_STATE_WARN(cur_state != state,
63d7bbe9 1346 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1347 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1348}
1349
931872fc
CW		 1350static void assert_plane(struct drm_i915_private *dev_priv,
1351 enum plane plane, bool state)
b24e7179
JB		 1352{
1353 int reg;
1354 u32 val;
931872fc 1355 bool cur_state;
b24e7179
JB		 1356
1357 reg = DSPCNTR(plane);
1358 val = I915_READ(reg);
931872fc 1359 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1360 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1361 "plane %c assertion failure (expected %s, current %s)\n",
1362 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1363}
1364
931872fc
CW		 1365#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1366#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1367
b24e7179
JB		 1368static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370{
653e1026 1371 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1372 int reg, i;
1373 u32 val;
1374 int cur_pipe;
1375
653e1026
VS		 1376 /* Primary planes are fixed to pipes on gen4+ */
1377 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1378 reg = DSPCNTR(pipe);
1379 val = I915_READ(reg);
e2c719b7 1380 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1381 "plane %c assertion failure, should be disabled but not\n",
1382 plane_name(pipe));
19ec1358 1383 return;
28c05794 1384 }
19ec1358 1385
b24e7179 1386 /* Need to check both planes against the pipe */
055e393f 1387 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1388 reg = DSPCNTR(i);
1389 val = I915_READ(reg);
1390 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1391 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1392 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1393 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1394 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1395 }
1396}
1397
19332d7a
JB		 1398static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe)
1400{
20674eef 1401 struct drm_device *dev = dev_priv->dev;
1fe47785 1402 int reg, sprite;
19332d7a
JB		 1403 u32 val;
1404
7feb8b88 1405 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1406 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1407 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1408 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1409 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1410 sprite, pipe_name(pipe));
1411 }
1412 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1413 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1414 reg = SPCNTR(pipe, sprite);
20674eef 1415 val = I915_READ(reg);
e2c719b7 1416 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1418 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1419 }
1420 } else if (INTEL_INFO(dev)->gen >= 7) {
1421 reg = SPRCTL(pipe);
19332d7a 1422 val = I915_READ(reg);
e2c719b7 1423 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1425 plane_name(pipe), pipe_name(pipe));
1426 } else if (INTEL_INFO(dev)->gen >= 5) {
1427 reg = DVSCNTR(pipe);
19332d7a 1428 val = I915_READ(reg);
e2c719b7 1429 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1431 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1432 }
1433}
1434
08c71e5e
VS		 1435static void assert_vblank_disabled(struct drm_crtc *crtc)
1436{
e2c719b7 1437 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1438 drm_crtc_vblank_put(crtc);
1439}
1440
89eff4be 1441static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1442{
1443 u32 val;
1444 bool enabled;
1445
e2c719b7 1446 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1447
92f2584a
JB		 1448 val = I915_READ(PCH_DREF_CONTROL);
1449 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1450 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1451 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1452}
1453
ab9412ba
DV		 1454static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1455 enum pipe pipe)
92f2584a
JB		 1456{
1457 int reg;
1458 u32 val;
1459 bool enabled;
1460
ab9412ba 1461 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1462 val = I915_READ(reg);
1463 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1464 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1465 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1466 pipe_name(pipe));
92f2584a
JB		 1467}
1468
4e634389
KP		 1469static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1471{
1472 if ((val & DP_PORT_EN) == 0)
1473 return false;
1474
1475 if (HAS_PCH_CPT(dev_priv->dev)) {
1476 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1477 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1478 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1479 return false;
44f37d1f
CML		 1480 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1481 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1482 return false;
f0575e92
KP		 1483 } else {
1484 if ((val & DP_PIPE_MASK) != (pipe << 30))
1485 return false;
1486 }
1487 return true;
1488}
1489
1519b995
KP		 1490static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1491 enum pipe pipe, u32 val)
1492{
dc0fa718 1493 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1494 return false;
1495
1496 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1497 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1498 return false;
44f37d1f
CML		 1499 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1500 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1501 return false;
1519b995 1502 } else {
dc0fa718 1503 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1504 return false;
1505 }
1506 return true;
1507}
1508
1509static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511{
1512 if ((val & LVDS_PORT_EN) == 0)
1513 return false;
1514
1515 if (HAS_PCH_CPT(dev_priv->dev)) {
1516 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1517 return false;
1518 } else {
1519 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1520 return false;
1521 }
1522 return true;
1523}
1524
1525static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1526 enum pipe pipe, u32 val)
1527{
1528 if ((val & ADPA_DAC_ENABLE) == 0)
1529 return false;
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
1531 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1532 return false;
1533 } else {
1534 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1535 return false;
1536 }
1537 return true;
1538}
1539
291906f1 1540static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1541 enum pipe pipe, int reg, u32 port_sel)
291906f1 1542{
47a05eca 1543 u32 val = I915_READ(reg);
e2c719b7 1544 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1545 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1546 reg, pipe_name(pipe));
de9a35ab 1547
e2c719b7 1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1549 && (val & DP_PIPEB_SELECT),
de9a35ab 1550 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1551}
1552
1553static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1554 enum pipe pipe, int reg)
1555{
47a05eca 1556 u32 val = I915_READ(reg);
e2c719b7 1557 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1558 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1559 reg, pipe_name(pipe));
de9a35ab 1560
e2c719b7 1561 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1562 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1563 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1564}
1565
1566static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
1568{
1569 int reg;
1570 u32 val;
291906f1 1571
f0575e92
KP		 1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1575
1576 reg = PCH_ADPA;
1577 val = I915_READ(reg);
e2c719b7 1578 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1579 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1580 pipe_name(pipe));
291906f1
JB		 1581
1582 reg = PCH_LVDS;
1583 val = I915_READ(reg);
e2c719b7 1584 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1585 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1586 pipe_name(pipe));
291906f1 1587
e2debe91
PZ		 1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1591}
1592
40e9cf64
JB		 1593static void intel_init_dpio(struct drm_device *dev)
1594{
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597 if (!IS_VALLEYVIEW(dev))
1598 return;
1599
a09caddd
CML		 1600 /*
1601 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1602 * CHV x1 PHY (DP/HDMI D)
1603 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1604 */
1605 if (IS_CHERRYVIEW(dev)) {
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1607 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1608 } else {
1609 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1610 }
5382f5f3
JB		 1611}
1612
d288f65f 1613static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1614 const struct intel_crtc_state *pipe_config)
87442f73 1615{
426115cf
DV		 1616 struct drm_device *dev = crtc->base.dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 int reg = DPLL(crtc->pipe);
d288f65f 1619 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1620
426115cf 1621 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1622
1623 /* No really, not for ILK+ */
1624 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1625
1626 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1627 if (IS_MOBILE(dev_priv->dev))
426115cf 1628 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1629
426115cf
DV		 1630 I915_WRITE(reg, dpll);
1631 POSTING_READ(reg);
1632 udelay(150);
1633
1634 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1636
d288f65f 1637 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1638 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1639
1640 /* We do this three times for luck */
426115cf 1641 I915_WRITE(reg, dpll);
87442f73
DV		 1642 POSTING_READ(reg);
1643 udelay(150); /* wait for warmup */
426115cf 1644 I915_WRITE(reg, dpll);
87442f73
DV		 1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
426115cf 1647 I915_WRITE(reg, dpll);
87442f73
DV		 1648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
1650}
1651
d288f65f 1652static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1653 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1654{
1655 struct drm_device *dev = crtc->base.dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 int pipe = crtc->pipe;
1658 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1659 u32 tmp;
1660
1661 assert_pipe_disabled(dev_priv, crtc->pipe);
1662
1663 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1664
a580516d 1665 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1666
1667 /* Enable back the 10bit clock to display controller */
1668 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1669 tmp |= DPIO_DCLKP_EN;
1670 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1671
54433e91
VS		 1672 mutex_unlock(&dev_priv->sb_lock);
1673
9d556c99
CML		 1674 /*
1675 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1676 */
1677 udelay(1);
1678
1679 /* Enable PLL */
d288f65f 1680 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1681
1682 /* Check PLL is locked */
a11b0703 1683 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1684 DRM_ERROR("PLL %d failed to lock\n", pipe);
1685
a11b0703 1686 /* not sure when this should be written */
d288f65f 1687 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1688 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1689}
1690
1c4e0274
VS		 1691static int intel_num_dvo_pipes(struct drm_device *dev)
1692{
1693 struct intel_crtc *crtc;
1694 int count = 0;
1695
1696 for_each_intel_crtc(dev, crtc)
3538b9df 1697 count += crtc->base.state->active &&
409ee761 1698 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1699
1700 return count;
1701}
1702
66e3d5c0 1703static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1704{
66e3d5c0
DV		 1705 struct drm_device *dev = crtc->base.dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 int reg = DPLL(crtc->pipe);
6e3c9717 1708 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1709
66e3d5c0 1710 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1711
63d7bbe9 1712 /* No really, not for ILK+ */
3d13ef2e 1713 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1714
1715 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1716 if (IS_MOBILE(dev) && !IS_I830(dev))
1717 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1718
1c4e0274
VS		 1719 /* Enable DVO 2x clock on both PLLs if necessary */
1720 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1721 /*
1722 * It appears to be important that we don't enable this
1723 * for the current pipe before otherwise configuring the
1724 * PLL. No idea how this should be handled if multiple
1725 * DVO outputs are enabled simultaneosly.
1726 */
1727 dpll |= DPLL_DVO_2X_MODE;
1728 I915_WRITE(DPLL(!crtc->pipe),
1729 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1730 }
66e3d5c0
DV		 1731
1732 /* Wait for the clocks to stabilize. */
1733 POSTING_READ(reg);
1734 udelay(150);
1735
1736 if (INTEL_INFO(dev)->gen >= 4) {
1737 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1738 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1739 } else {
1740 /* The pixel multiplier can only be updated once the
1741 * DPLL is enabled and the clocks are stable.
1742 *
1743 * So write it again.
1744 */
1745 I915_WRITE(reg, dpll);
1746 }
63d7bbe9
JB		 1747
1748 /* We do this three times for luck */
66e3d5c0 1749 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1750 POSTING_READ(reg);
1751 udelay(150); /* wait for warmup */
66e3d5c0 1752 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1753 POSTING_READ(reg);
1754 udelay(150); /* wait for warmup */
66e3d5c0 1755 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1756 POSTING_READ(reg);
1757 udelay(150); /* wait for warmup */
1758}
1759
1760/**
50b44a44 1761 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1762 * @dev_priv: i915 private structure
1763 * @pipe: pipe PLL to disable
1764 *
1765 * Disable the PLL for @pipe, making sure the pipe is off first.
1766 *
1767 * Note! This is for pre-ILK only.
1768 */
1c4e0274 1769static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1770{
1c4e0274
VS		 1771 struct drm_device *dev = crtc->base.dev;
1772 struct drm_i915_private *dev_priv = dev->dev_private;
1773 enum pipe pipe = crtc->pipe;
1774
1775 /* Disable DVO 2x clock on both PLLs if necessary */
1776 if (IS_I830(dev) &&
409ee761 1777 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1778 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1779 I915_WRITE(DPLL(PIPE_B),
1780 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1781 I915_WRITE(DPLL(PIPE_A),
1782 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1783 }
1784
b6b5d049
VS		 1785 /* Don't disable pipe or pipe PLLs if needed */
1786 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1787 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1788 return;
1789
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
1792
50b44a44
DV		 1793 I915_WRITE(DPLL(pipe), 0);
1794 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1795}
1796
f6071166
JB		 1797static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1798{
1799 u32 val = 0;
1800
1801 /* Make sure the pipe isn't still relying on us */
1802 assert_pipe_disabled(dev_priv, pipe);
1803
e5cbfbfb
ID		 1804 /*
1805 * Leave integrated clock source and reference clock enabled for pipe B.
1806 * The latter is needed for VGA hotplug / manual detection.
1807 */
f6071166 1808 if (pipe == PIPE_B)
e5cbfbfb 1809 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1810 I915_WRITE(DPLL(pipe), val);
1811 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1812
1813}
1814
1815static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1816{
d752048d 1817 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1818 u32 val;
1819
a11b0703
VS		 1820 /* Make sure the pipe isn't still relying on us */
1821 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1822
a11b0703 1823 /* Set PLL en = 0 */
d17ec4ce 1824 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1825 if (pipe != PIPE_A)
1826 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1827 I915_WRITE(DPLL(pipe), val);
1828 POSTING_READ(DPLL(pipe));
d752048d 1829
a580516d 1830 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1831
1832 /* Disable 10bit clock to display controller */
1833 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1834 val &= ~DPIO_DCLKP_EN;
1835 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1836
61407f6d
VS		 1837 /* disable left/right clock distribution */
1838 if (pipe != PIPE_B) {
1839 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1840 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1841 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1842 } else {
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1844 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1846 }
1847
a580516d 1848 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1849}
1850
e4607fcf 1851void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1852 struct intel_digital_port *dport,
1853 unsigned int expected_mask)
89b667f8
JB		 1854{
1855 u32 port_mask;
00fc31b7 1856 int dpll_reg;
89b667f8 1857
e4607fcf
CML		 1858 switch (dport->port) {
1859 case PORT_B:
89b667f8 1860 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1861 dpll_reg = DPLL(0);
e4607fcf
CML		 1862 break;
1863 case PORT_C:
89b667f8 1864 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1865 dpll_reg = DPLL(0);
9b6de0a1 1866 expected_mask <<= 4;
00fc31b7
CML		 1867 break;
1868 case PORT_D:
1869 port_mask = DPLL_PORTD_READY_MASK;
1870 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1871 break;
1872 default:
1873 BUG();
1874 }
89b667f8 1875
9b6de0a1
VS		 1876 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1877 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1878 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1879}
1880
b14b1055
DV		 1881static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1882{
1883 struct drm_device *dev = crtc->base.dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1886
be19f0ff
CW		 1887 if (WARN_ON(pll == NULL))
1888 return;
1889
3e369b76 1890 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1891 if (pll->active == 0) {
1892 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1893 WARN_ON(pll->on);
1894 assert_shared_dpll_disabled(dev_priv, pll);
1895
1896 pll->mode_set(dev_priv, pll);
1897 }
1898}
1899
92f2584a 1900/**
85b3894f 1901 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1902 * @dev_priv: i915 private structure
1903 * @pipe: pipe PLL to enable
1904 *
1905 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1906 * drives the transcoder clock.
1907 */
85b3894f 1908static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1909{
3d13ef2e
DL		 1910 struct drm_device *dev = crtc->base.dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1912 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1913
87a875bb 1914 if (WARN_ON(pll == NULL))
48da64a8
CW		 1915 return;
1916
3e369b76 1917 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1918 return;
ee7b9f93 1919
74dd6928 1920 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1921 pll->name, pll->active, pll->on,
e2b78267 1922 crtc->base.base.id);
92f2584a 1923
cdbd2316
DV		 1924 if (pll->active++) {
1925 WARN_ON(!pll->on);
e9d6944e 1926 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1927 return;
1928 }
f4a091c7 1929 WARN_ON(pll->on);
ee7b9f93 1930
bd2bb1b9
PZ		 1931 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1932
46edb027 1933 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1934 pll->enable(dev_priv, pll);
ee7b9f93 1935 pll->on = true;
92f2584a
JB		 1936}
1937
f6daaec2 1938static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1939{
3d13ef2e
DL		 1940 struct drm_device *dev = crtc->base.dev;
1941 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1942 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1943
92f2584a 1944 /* PCH only available on ILK+ */
3d13ef2e 1945 BUG_ON(INTEL_INFO(dev)->gen < 5);
eddfcbcd
ML		 1946 if (pll == NULL)
1947 return;
92f2584a 1948
eddfcbcd 1949 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1950 return;
7a419866 1951
46edb027
DV		 1952 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1953 pll->name, pll->active, pll->on,
e2b78267 1954 crtc->base.base.id);
7a419866 1955
48da64a8 1956 if (WARN_ON(pll->active == 0)) {
e9d6944e 1957 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1958 return;
1959 }
1960
e9d6944e 1961 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1962 WARN_ON(!pll->on);
cdbd2316 1963 if (--pll->active)
7a419866 1964 return;
ee7b9f93 1965
46edb027 1966 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1967 pll->disable(dev_priv, pll);
ee7b9f93 1968 pll->on = false;
bd2bb1b9
PZ		 1969
1970 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1971}
1972
b8a4f404
PZ		 1973static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1974 enum pipe pipe)
040484af 1975{
23670b32 1976 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1977 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1979 uint32_t reg, val, pipeconf_val;
040484af
JB		 1980
1981 /* PCH only available on ILK+ */
55522f37 1982 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1983
1984 /* Make sure PCH DPLL is enabled */
e72f9fbf 1985 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1986 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1987
1988 /* FDI must be feeding us bits for PCH ports */
1989 assert_fdi_tx_enabled(dev_priv, pipe);
1990 assert_fdi_rx_enabled(dev_priv, pipe);
1991
23670b32
DV		 1992 if (HAS_PCH_CPT(dev)) {
1993 /* Workaround: Set the timing override bit before enabling the
1994 * pch transcoder. */
1995 reg = TRANS_CHICKEN2(pipe);
1996 val = I915_READ(reg);
1997 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1998 I915_WRITE(reg, val);
59c859d6 1999 }
23670b32 2000
ab9412ba 2001 reg = PCH_TRANSCONF(pipe);
040484af 2002 val = I915_READ(reg);
5f7f726d 2003 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2004
2005 if (HAS_PCH_IBX(dev_priv->dev)) {
2006 /*
c5de7c6f
VS		 2007 * Make the BPC in transcoder be consistent with
2008 * that in pipeconf reg. For HDMI we must use 8bpc
2009 * here for both 8bpc and 12bpc.
e9bcff5c 2010 */
dfd07d72 2011 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2012 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2013 val |= PIPECONF_8BPC;
2014 else
2015 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2016 }
5f7f726d
PZ		 2017
2018 val &= ~TRANS_INTERLACE_MASK;
2019 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2020 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2021 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2022 val |= TRANS_LEGACY_INTERLACED_ILK;
2023 else
2024 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2025 else
2026 val |= TRANS_PROGRESSIVE;
2027
040484af
JB		 2028 I915_WRITE(reg, val | TRANS_ENABLE);
2029 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2030 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2031}
2032
8fb033d7 2033static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2034 enum transcoder cpu_transcoder)
040484af 2035{
8fb033d7 2036 u32 val, pipeconf_val;
8fb033d7
PZ		 2037
2038 /* PCH only available on ILK+ */
55522f37 2039 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2040
8fb033d7 2041 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2042 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2043 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2044
223a6fdf
PZ		 2045 /* Workaround: set timing override bit. */
2046 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2047 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2048 I915_WRITE(_TRANSA_CHICKEN2, val);
2049
25f3ef11 2050 val = TRANS_ENABLE;
937bb610 2051 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2052
9a76b1c6
PZ		 2053 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2054 PIPECONF_INTERLACED_ILK)
a35f2679 2055 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2056 else
2057 val |= TRANS_PROGRESSIVE;
2058
ab9412ba
DV		 2059 I915_WRITE(LPT_TRANSCONF, val);
2060 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2061 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2062}
2063
b8a4f404
PZ		 2064static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2065 enum pipe pipe)
040484af 2066{
23670b32
DV		 2067 struct drm_device *dev = dev_priv->dev;
2068 uint32_t reg, val;
040484af
JB		 2069
2070 /* FDI relies on the transcoder */
2071 assert_fdi_tx_disabled(dev_priv, pipe);
2072 assert_fdi_rx_disabled(dev_priv, pipe);
2073
291906f1
JB		 2074 /* Ports must be off as well */
2075 assert_pch_ports_disabled(dev_priv, pipe);
2076
ab9412ba 2077 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2078 val = I915_READ(reg);
2079 val &= ~TRANS_ENABLE;
2080 I915_WRITE(reg, val);
2081 /* wait for PCH transcoder off, transcoder state */
2082 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2083 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2084
2085 if (!HAS_PCH_IBX(dev)) {
2086 /* Workaround: Clear the timing override chicken bit again. */
2087 reg = TRANS_CHICKEN2(pipe);
2088 val = I915_READ(reg);
2089 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2090 I915_WRITE(reg, val);
2091 }
040484af
JB		 2092}
2093
ab4d966c 2094static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2095{
8fb033d7
PZ		 2096 u32 val;
2097
ab9412ba 2098 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2099 val &= ~TRANS_ENABLE;
ab9412ba 2100 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2101 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2102 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2103 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2104
2105 /* Workaround: clear timing override bit. */
2106 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2107 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2108 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2109}
2110
b24e7179 2111/**
309cfea8 2112 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2113 * @crtc: crtc responsible for the pipe
b24e7179 2114 *
0372264a 2115 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2116 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2117 */
e1fdc473 2118static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2119{
0372264a
PZ		 2120 struct drm_device *dev = crtc->base.dev;
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2122 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2123 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2124 pipe);
1a240d4d 2125 enum pipe pch_transcoder;
b24e7179
JB		 2126 int reg;
2127 u32 val;
2128
9e2ee2dd
VS		 2129 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2130
58c6eaa2 2131 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2132 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2133 assert_sprites_disabled(dev_priv, pipe);
2134
681e5811 2135 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2136 pch_transcoder = TRANSCODER_A;
2137 else
2138 pch_transcoder = pipe;
2139
b24e7179
JB		 2140 /*
2141 * A pipe without a PLL won't actually be able to drive bits from
2142 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2143 * need the check.
2144 */
50360403 2145 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2146 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2147 assert_dsi_pll_enabled(dev_priv);
2148 else
2149 assert_pll_enabled(dev_priv, pipe);
040484af 2150 else {
6e3c9717 2151 if (crtc->config->has_pch_encoder) {
040484af 2152 /* if driving the PCH, we need FDI enabled */
cc391bbb 2153 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2154 assert_fdi_tx_pll_enabled(dev_priv,
2155 (enum pipe) cpu_transcoder);
040484af
JB		 2156 }
2157 /* FIXME: assert CPU port conditions for SNB+ */
2158 }
b24e7179 2159
702e7a56 2160 reg = PIPECONF(cpu_transcoder);
b24e7179 2161 val = I915_READ(reg);
7ad25d48 2162 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2163 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2164 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2165 return;
7ad25d48 2166 }
00d70b15
CW		 2167
2168 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2169 POSTING_READ(reg);
b24e7179
JB		 2170}
2171
2172/**
309cfea8 2173 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2174 * @crtc: crtc whose pipes is to be disabled
b24e7179 2175 *
575f7ab7
VS		 2176 * Disable the pipe of @crtc, making sure that various hardware
2177 * specific requirements are met, if applicable, e.g. plane
2178 * disabled, panel fitter off, etc.
b24e7179
JB		 2179 *
2180 * Will wait until the pipe has shut down before returning.
2181 */
575f7ab7 2182static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2183{
575f7ab7 2184 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2185 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2186 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2187 int reg;
2188 u32 val;
2189
9e2ee2dd
VS		 2190 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2191
b24e7179
JB		 2192 /*
2193 * Make sure planes won't keep trying to pump pixels to us,
2194 * or we might hang the display.
2195 */
2196 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2197 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2198 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2199
702e7a56 2200 reg = PIPECONF(cpu_transcoder);
b24e7179 2201 val = I915_READ(reg);
00d70b15
CW		 2202 if ((val & PIPECONF_ENABLE) == 0)
2203 return;
2204
67adc644
VS		 2205 /*
2206 * Double wide has implications for planes
2207 * so best keep it disabled when not needed.
2208 */
6e3c9717 2209 if (crtc->config->double_wide)
67adc644
VS		 2210 val &= ~PIPECONF_DOUBLE_WIDE;
2211
2212 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2213 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2214 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2215 val &= ~PIPECONF_ENABLE;
2216
2217 I915_WRITE(reg, val);
2218 if ((val & PIPECONF_ENABLE) == 0)
2219 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2220}
2221
693db184
CW		 2222static bool need_vtd_wa(struct drm_device *dev)
2223{
2224#ifdef CONFIG_INTEL_IOMMU
2225 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2226 return true;
2227#endif
2228 return false;
2229}
2230
50470bb0 2231unsigned int
6761dd31
TU		 2232intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2233 uint64_t fb_format_modifier)
a57ce0b2 2234{
6761dd31
TU		 2235 unsigned int tile_height;
2236 uint32_t pixel_bytes;
a57ce0b2 2237
b5d0e9bf
DL		 2238 switch (fb_format_modifier) {
2239 case DRM_FORMAT_MOD_NONE:
2240 tile_height = 1;
2241 break;
2242 case I915_FORMAT_MOD_X_TILED:
2243 tile_height = IS_GEN2(dev) ? 16 : 8;
2244 break;
2245 case I915_FORMAT_MOD_Y_TILED:
2246 tile_height = 32;
2247 break;
2248 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2249 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2250 switch (pixel_bytes) {
b5d0e9bf 2251 default:
6761dd31 2252 case 1:
b5d0e9bf
DL		 2253 tile_height = 64;
2254 break;
6761dd31
TU		 2255 case 2:
2256 case 4:
b5d0e9bf
DL		 2257 tile_height = 32;
2258 break;
6761dd31 2259 case 8:
b5d0e9bf
DL		 2260 tile_height = 16;
2261 break;
6761dd31 2262 case 16:
b5d0e9bf
DL		 2263 WARN_ONCE(1,
2264 "128-bit pixels are not supported for display!");
2265 tile_height = 16;
2266 break;
2267 }
2268 break;
2269 default:
2270 MISSING_CASE(fb_format_modifier);
2271 tile_height = 1;
2272 break;
2273 }
091df6cb 2274
6761dd31
TU		 2275 return tile_height;
2276}
2277
2278unsigned int
2279intel_fb_align_height(struct drm_device *dev, unsigned int height,
2280 uint32_t pixel_format, uint64_t fb_format_modifier)
2281{
2282 return ALIGN(height, intel_tile_height(dev, pixel_format,
2283 fb_format_modifier));
a57ce0b2
JB		 2284}
2285
f64b98cd
TU		 2286static int
2287intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2288 const struct drm_plane_state *plane_state)
2289{
50470bb0 2290 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2291 unsigned int tile_height, tile_pitch;
50470bb0 2292
f64b98cd
TU		 2293 *view = i915_ggtt_view_normal;
2294
50470bb0
TU		 2295 if (!plane_state)
2296 return 0;
2297
121920fa 2298 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2299 return 0;
2300
9abc4648 2301 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2302
2303 info->height = fb->height;
2304 info->pixel_format = fb->pixel_format;
2305 info->pitch = fb->pitches[0];
2306 info->fb_modifier = fb->modifier[0];
2307
84fe03f7
TU		 2308 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2309 fb->modifier[0]);
2310 tile_pitch = PAGE_SIZE / tile_height;
2311 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2312 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2313 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2314
f64b98cd
TU		 2315 return 0;
2316}
2317
4e9a86b6
VS		 2318static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2319{
2320 if (INTEL_INFO(dev_priv)->gen >= 9)
2321 return 256 * 1024;
985b8bb4
VS		 2322 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2323 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2324 return 128 * 1024;
2325 else if (INTEL_INFO(dev_priv)->gen >= 4)
2326 return 4 * 1024;
2327 else
44c5905e 2328 return 0;
4e9a86b6
VS		 2329}
2330
127bd2ac 2331int
850c4cdc
TU		 2332intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2333 struct drm_framebuffer *fb,
82bc3b2d 2334 const struct drm_plane_state *plane_state,
91af127f
JH		 2335 struct intel_engine_cs *pipelined,
2336 struct drm_i915_gem_request **pipelined_request)
6b95a207 2337{
850c4cdc 2338 struct drm_device *dev = fb->dev;
ce453d81 2339 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2340 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2341 struct i915_ggtt_view view;
6b95a207
KH		 2342 u32 alignment;
2343 int ret;
2344
ebcdd39e
MR		 2345 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2346
7b911adc
TU		 2347 switch (fb->modifier[0]) {
2348 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2349 alignment = intel_linear_alignment(dev_priv);
6b95a207 2350 break;
7b911adc 2351 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2352 if (INTEL_INFO(dev)->gen >= 9)
2353 alignment = 256 * 1024;
2354 else {
2355 /* pin() will align the object as required by fence */
2356 alignment = 0;
2357 }
6b95a207 2358 break;
7b911adc 2359 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2360 case I915_FORMAT_MOD_Yf_TILED:
2361 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2362 "Y tiling bo slipped through, driver bug!\n"))
2363 return -EINVAL;
2364 alignment = 1 * 1024 * 1024;
2365 break;
6b95a207 2366 default:
7b911adc
TU		 2367 MISSING_CASE(fb->modifier[0]);
2368 return -EINVAL;
6b95a207
KH		 2369 }
2370
f64b98cd
TU		 2371 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2372 if (ret)
2373 return ret;
2374
693db184
CW		 2375 /* Note that the w/a also requires 64 PTE of padding following the
2376 * bo. We currently fill all unused PTE with the shadow page and so
2377 * we should always have valid PTE following the scanout preventing
2378 * the VT-d warning.
2379 */
2380 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2381 alignment = 256 * 1024;
2382
d6dd6843
PZ		 2383 /*
2384 * Global gtt pte registers are special registers which actually forward
2385 * writes to a chunk of system memory. Which means that there is no risk
2386 * that the register values disappear as soon as we call
2387 * intel_runtime_pm_put(), so it is correct to wrap only the
2388 * pin/unpin/fence and not more.
2389 */
2390 intel_runtime_pm_get(dev_priv);
2391
ce453d81 2392 dev_priv->mm.interruptible = false;
e6617330 2393 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2394 pipelined_request, &view);
48b956c5 2395 if (ret)
ce453d81 2396 goto err_interruptible;
6b95a207
KH		 2397
2398 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2399 * fence, whereas 965+ only requires a fence if using
2400 * framebuffer compression. For simplicity, we always install
2401 * a fence as the cost is not that onerous.
2402 */
06d98131 2403 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2404 if (ret)
2405 goto err_unpin;
1690e1eb 2406
9a5a53b3 2407 i915_gem_object_pin_fence(obj);
6b95a207 2408
ce453d81 2409 dev_priv->mm.interruptible = true;
d6dd6843 2410 intel_runtime_pm_put(dev_priv);
6b95a207 2411 return 0;
48b956c5
CW		 2412
2413err_unpin:
f64b98cd 2414 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2415err_interruptible:
2416 dev_priv->mm.interruptible = true;
d6dd6843 2417 intel_runtime_pm_put(dev_priv);
48b956c5 2418 return ret;
6b95a207
KH		 2419}
2420
82bc3b2d
TU		 2421static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2422 const struct drm_plane_state *plane_state)
1690e1eb 2423{
82bc3b2d 2424 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2425 struct i915_ggtt_view view;
2426 int ret;
82bc3b2d 2427
ebcdd39e
MR		 2428 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2429
f64b98cd
TU		 2430 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2431 WARN_ONCE(ret, "Couldn't get view from plane state!");
2432
1690e1eb 2433 i915_gem_object_unpin_fence(obj);
f64b98cd 2434 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2435}
2436
c2c75131
DV		 2437/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2438 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2439unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2440 int *x, int *y,
bc752862
CW		 2441 unsigned int tiling_mode,
2442 unsigned int cpp,
2443 unsigned int pitch)
c2c75131 2444{
bc752862
CW		 2445 if (tiling_mode != I915_TILING_NONE) {
2446 unsigned int tile_rows, tiles;
c2c75131 2447
bc752862
CW		 2448 tile_rows = *y / 8;
2449 *y %= 8;
c2c75131 2450
bc752862
CW		 2451 tiles = *x / (512/cpp);
2452 *x %= 512/cpp;
2453
2454 return tile_rows * pitch * 8 + tiles * 4096;
2455 } else {
4e9a86b6 2456 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2457 unsigned int offset;
2458
2459 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2460 *y = (offset & alignment) / pitch;
2461 *x = ((offset & alignment) - *y * pitch) / cpp;
2462 return offset & ~alignment;
bc752862 2463 }
c2c75131
DV		 2464}
2465
b35d63fa 2466static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2467{
2468 switch (format) {
2469 case DISPPLANE_8BPP:
2470 return DRM_FORMAT_C8;
2471 case DISPPLANE_BGRX555:
2472 return DRM_FORMAT_XRGB1555;
2473 case DISPPLANE_BGRX565:
2474 return DRM_FORMAT_RGB565;
2475 default:
2476 case DISPPLANE_BGRX888:
2477 return DRM_FORMAT_XRGB8888;
2478 case DISPPLANE_RGBX888:
2479 return DRM_FORMAT_XBGR8888;
2480 case DISPPLANE_BGRX101010:
2481 return DRM_FORMAT_XRGB2101010;
2482 case DISPPLANE_RGBX101010:
2483 return DRM_FORMAT_XBGR2101010;
2484 }
2485}
2486
bc8d7dff
DL		 2487static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2488{
2489 switch (format) {
2490 case PLANE_CTL_FORMAT_RGB_565:
2491 return DRM_FORMAT_RGB565;
2492 default:
2493 case PLANE_CTL_FORMAT_XRGB_8888:
2494 if (rgb_order) {
2495 if (alpha)
2496 return DRM_FORMAT_ABGR8888;
2497 else
2498 return DRM_FORMAT_XBGR8888;
2499 } else {
2500 if (alpha)
2501 return DRM_FORMAT_ARGB8888;
2502 else
2503 return DRM_FORMAT_XRGB8888;
2504 }
2505 case PLANE_CTL_FORMAT_XRGB_2101010:
2506 if (rgb_order)
2507 return DRM_FORMAT_XBGR2101010;
2508 else
2509 return DRM_FORMAT_XRGB2101010;
2510 }
2511}
2512
5724dbd1 2513static bool
f6936e29
DV		 2514intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2515 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2516{
2517 struct drm_device *dev = crtc->base.dev;
2518 struct drm_i915_gem_object *obj = NULL;
2519 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2520 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2521 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2522 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2523 PAGE_SIZE);
2524
2525 size_aligned -= base_aligned;
46f297fb 2526
ff2652ea
CW		 2527 if (plane_config->size == 0)
2528 return false;
2529
f37b5c2b
DV		 2530 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2531 base_aligned,
2532 base_aligned,
2533 size_aligned);
46f297fb 2534 if (!obj)
484b41dd 2535 return false;
46f297fb 2536
49af449b
DL		 2537 obj->tiling_mode = plane_config->tiling;
2538 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2539 obj->stride = fb->pitches[0];
46f297fb 2540
6bf129df
DL		 2541 mode_cmd.pixel_format = fb->pixel_format;
2542 mode_cmd.width = fb->width;
2543 mode_cmd.height = fb->height;
2544 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2545 mode_cmd.modifier[0] = fb->modifier[0];
2546 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2547
2548 mutex_lock(&dev->struct_mutex);
6bf129df 2549 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2550 &mode_cmd, obj)) {
46f297fb
JB		 2551 DRM_DEBUG_KMS("intel fb init failed\n");
2552 goto out_unref_obj;
2553 }
46f297fb 2554 mutex_unlock(&dev->struct_mutex);
484b41dd 2555
f6936e29 2556 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2557 return true;
46f297fb
JB		 2558
2559out_unref_obj:
2560 drm_gem_object_unreference(&obj->base);
2561 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2562 return false;
2563}
2564
afd65eb4
MR		 2565/* Update plane->state->fb to match plane->fb after driver-internal updates */
2566static void
2567update_state_fb(struct drm_plane *plane)
2568{
2569 if (plane->fb == plane->state->fb)
2570 return;
2571
2572 if (plane->state->fb)
2573 drm_framebuffer_unreference(plane->state->fb);
2574 plane->state->fb = plane->fb;
2575 if (plane->state->fb)
2576 drm_framebuffer_reference(plane->state->fb);
2577}
2578
5724dbd1 2579static void
f6936e29
DV		 2580intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2581 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2582{
2583 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2584 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2585 struct drm_crtc *c;
2586 struct intel_crtc *i;
2ff8fde1 2587 struct drm_i915_gem_object *obj;
88595ac9
DV		 2588 struct drm_plane *primary = intel_crtc->base.primary;
2589 struct drm_framebuffer *fb;
484b41dd 2590
2d14030b 2591 if (!plane_config->fb)
484b41dd
JB		 2592 return;
2593
f6936e29 2594 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2595 fb = &plane_config->fb->base;
2596 goto valid_fb;
f55548b5 2597 }
484b41dd 2598
2d14030b 2599 kfree(plane_config->fb);
484b41dd
JB		 2600
2601 /*
2602 * Failed to alloc the obj, check to see if we should share
2603 * an fb with another CRTC instead
2604 */
70e1e0ec 2605 for_each_crtc(dev, c) {
484b41dd
JB		 2606 i = to_intel_crtc(c);
2607
2608 if (c == &intel_crtc->base)
2609 continue;
2610
2ff8fde1
MR		 2611 if (!i->active)
2612 continue;
2613
88595ac9
DV		 2614 fb = c->primary->fb;
2615 if (!fb)
484b41dd
JB		 2616 continue;
2617
88595ac9 2618 obj = intel_fb_obj(fb);
2ff8fde1 2619 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2620 drm_framebuffer_reference(fb);
2621 goto valid_fb;
484b41dd
JB		 2622 }
2623 }
88595ac9
DV		 2624
2625 return;
2626
2627valid_fb:
2628 obj = intel_fb_obj(fb);
2629 if (obj->tiling_mode != I915_TILING_NONE)
2630 dev_priv->preserve_bios_swizzle = true;
2631
2632 primary->fb = fb;
36750f28 2633 primary->crtc = primary->state->crtc = &intel_crtc->base;
88595ac9 2634 update_state_fb(primary);
36750f28 2635 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2636 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2637}
2638
29b9bde6
DV		 2639static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2640 struct drm_framebuffer *fb,
2641 int x, int y)
81255565
JB		 2642{
2643 struct drm_device *dev = crtc->dev;
2644 struct drm_i915_private *dev_priv = dev->dev_private;
2645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2646 struct drm_plane *primary = crtc->primary;
2647 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2648 struct drm_i915_gem_object *obj;
81255565 2649 int plane = intel_crtc->plane;
e506a0c6 2650 unsigned long linear_offset;
81255565 2651 u32 dspcntr;
f45651ba 2652 u32 reg = DSPCNTR(plane);
48404c1e 2653 int pixel_size;
f45651ba 2654
b70709a6 2655 if (!visible || !fb) {
fdd508a6
VS		 2656 I915_WRITE(reg, 0);
2657 if (INTEL_INFO(dev)->gen >= 4)
2658 I915_WRITE(DSPSURF(plane), 0);
2659 else
2660 I915_WRITE(DSPADDR(plane), 0);
2661 POSTING_READ(reg);
2662 return;
2663 }
2664
c9ba6fad
VS		 2665 obj = intel_fb_obj(fb);
2666 if (WARN_ON(obj == NULL))
2667 return;
2668
2669 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2670
f45651ba
VS		 2671 dspcntr = DISPPLANE_GAMMA_ENABLE;
2672
fdd508a6 2673 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2674
2675 if (INTEL_INFO(dev)->gen < 4) {
2676 if (intel_crtc->pipe == PIPE_B)
2677 dspcntr |= DISPPLANE_SEL_PIPE_B;
2678
2679 /* pipesrc and dspsize control the size that is scaled from,
2680 * which should always be the user's requested size.
2681 */
2682 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2683 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2684 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2685 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2686 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2687 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2688 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2689 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2690 I915_WRITE(PRIMPOS(plane), 0);
2691 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2692 }
81255565 2693
57779d06
VS		 2694 switch (fb->pixel_format) {
2695 case DRM_FORMAT_C8:
81255565
JB		 2696 dspcntr |= DISPPLANE_8BPP;
2697 break;
57779d06 2698 case DRM_FORMAT_XRGB1555:
57779d06 2699 dspcntr |= DISPPLANE_BGRX555;
81255565 2700 break;
57779d06
VS		 2701 case DRM_FORMAT_RGB565:
2702 dspcntr |= DISPPLANE_BGRX565;
2703 break;
2704 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2705 dspcntr |= DISPPLANE_BGRX888;
2706 break;
2707 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2708 dspcntr |= DISPPLANE_RGBX888;
2709 break;
2710 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2711 dspcntr |= DISPPLANE_BGRX101010;
2712 break;
2713 case DRM_FORMAT_XBGR2101010:
57779d06 2714 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2715 break;
2716 default:
baba133a 2717 BUG();
81255565 2718 }
57779d06 2719
f45651ba
VS		 2720 if (INTEL_INFO(dev)->gen >= 4 &&
2721 obj->tiling_mode != I915_TILING_NONE)
2722 dspcntr |= DISPPLANE_TILED;
81255565 2723
de1aa629
VS		 2724 if (IS_G4X(dev))
2725 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2726
b9897127 2727 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2728
c2c75131
DV		 2729 if (INTEL_INFO(dev)->gen >= 4) {
2730 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2731 intel_gen4_compute_page_offset(dev_priv,
2732 &x, &y, obj->tiling_mode,
b9897127 2733 pixel_size,
bc752862 2734 fb->pitches[0]);
c2c75131
DV		 2735 linear_offset -= intel_crtc->dspaddr_offset;
2736 } else {
e506a0c6 2737 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2738 }
e506a0c6 2739
8e7d688b 2740 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2741 dspcntr |= DISPPLANE_ROTATE_180;
2742
6e3c9717
ACO		 2743 x += (intel_crtc->config->pipe_src_w - 1);
2744 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2745
2746 /* Finding the last pixel of the last line of the display
2747 data and adding to linear_offset*/
2748 linear_offset +=
6e3c9717
ACO		 2749 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2750 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2751 }
2752
2753 I915_WRITE(reg, dspcntr);
2754
01f2c773 2755 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2756 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2757 I915_WRITE(DSPSURF(plane),
2758 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2759 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2760 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2761 } else
f343c5f6 2762 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2763 POSTING_READ(reg);
17638cd6
JB		 2764}
2765
29b9bde6
DV		 2766static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2767 struct drm_framebuffer *fb,
2768 int x, int y)
17638cd6
JB		 2769{
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2773 struct drm_plane *primary = crtc->primary;
2774 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2775 struct drm_i915_gem_object *obj;
17638cd6 2776 int plane = intel_crtc->plane;
e506a0c6 2777 unsigned long linear_offset;
17638cd6 2778 u32 dspcntr;
f45651ba 2779 u32 reg = DSPCNTR(plane);
48404c1e 2780 int pixel_size;
f45651ba 2781
b70709a6 2782 if (!visible || !fb) {
fdd508a6
VS		 2783 I915_WRITE(reg, 0);
2784 I915_WRITE(DSPSURF(plane), 0);
2785 POSTING_READ(reg);
2786 return;
2787 }
2788
c9ba6fad
VS		 2789 obj = intel_fb_obj(fb);
2790 if (WARN_ON(obj == NULL))
2791 return;
2792
2793 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2794
f45651ba
VS		 2795 dspcntr = DISPPLANE_GAMMA_ENABLE;
2796
fdd508a6 2797 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2798
2799 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2800 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2801
57779d06
VS		 2802 switch (fb->pixel_format) {
2803 case DRM_FORMAT_C8:
17638cd6
JB		 2804 dspcntr |= DISPPLANE_8BPP;
2805 break;
57779d06
VS		 2806 case DRM_FORMAT_RGB565:
2807 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2808 break;
57779d06 2809 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2810 dspcntr |= DISPPLANE_BGRX888;
2811 break;
2812 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2813 dspcntr |= DISPPLANE_RGBX888;
2814 break;
2815 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2816 dspcntr |= DISPPLANE_BGRX101010;
2817 break;
2818 case DRM_FORMAT_XBGR2101010:
57779d06 2819 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2820 break;
2821 default:
baba133a 2822 BUG();
17638cd6
JB		 2823 }
2824
2825 if (obj->tiling_mode != I915_TILING_NONE)
2826 dspcntr |= DISPPLANE_TILED;
17638cd6 2827
f45651ba 2828 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2829 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2830
b9897127 2831 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2832 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2833 intel_gen4_compute_page_offset(dev_priv,
2834 &x, &y, obj->tiling_mode,
b9897127 2835 pixel_size,
bc752862 2836 fb->pitches[0]);
c2c75131 2837 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2838 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2839 dspcntr |= DISPPLANE_ROTATE_180;
2840
2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2842 x += (intel_crtc->config->pipe_src_w - 1);
2843 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2844
2845 /* Finding the last pixel of the last line of the display
2846 data and adding to linear_offset*/
2847 linear_offset +=
6e3c9717
ACO		 2848 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2849 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2850 }
2851 }
2852
2853 I915_WRITE(reg, dspcntr);
17638cd6 2854
01f2c773 2855 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2856 I915_WRITE(DSPSURF(plane),
2857 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2858 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2859 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2860 } else {
2861 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2862 I915_WRITE(DSPLINOFF(plane), linear_offset);
2863 }
17638cd6 2864 POSTING_READ(reg);
17638cd6
JB		 2865}
2866
b321803d
DL		 2867u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2868 uint32_t pixel_format)
2869{
2870 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2871
2872 /*
2873 * The stride is either expressed as a multiple of 64 bytes
2874 * chunks for linear buffers or in number of tiles for tiled
2875 * buffers.
2876 */
2877 switch (fb_modifier) {
2878 case DRM_FORMAT_MOD_NONE:
2879 return 64;
2880 case I915_FORMAT_MOD_X_TILED:
2881 if (INTEL_INFO(dev)->gen == 2)
2882 return 128;
2883 return 512;
2884 case I915_FORMAT_MOD_Y_TILED:
2885 /* No need to check for old gens and Y tiling since this is
2886 * about the display engine and those will be blocked before
2887 * we get here.
2888 */
2889 return 128;
2890 case I915_FORMAT_MOD_Yf_TILED:
2891 if (bits_per_pixel == 8)
2892 return 64;
2893 else
2894 return 128;
2895 default:
2896 MISSING_CASE(fb_modifier);
2897 return 64;
2898 }
2899}
2900
121920fa
TU		 2901unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2902 struct drm_i915_gem_object *obj)
2903{
9abc4648 2904 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2905
2906 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2907 view = &i915_ggtt_view_rotated;
121920fa
TU		 2908
2909 return i915_gem_obj_ggtt_offset_view(obj, view);
2910}
2911
a1b2278e
CK		 2912/*
2913 * This function detaches (aka. unbinds) unused scalers in hardware
2914 */
0583236e 2915static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e
CK		 2916{
2917 struct drm_device *dev;
2918 struct drm_i915_private *dev_priv;
2919 struct intel_crtc_scaler_state *scaler_state;
2920 int i;
2921
a1b2278e
CK		 2922 dev = intel_crtc->base.dev;
2923 dev_priv = dev->dev_private;
2924 scaler_state = &intel_crtc->config->scaler_state;
2925
2926 /* loop through and disable scalers that aren't in use */
2927 for (i = 0; i < intel_crtc->num_scalers; i++) {
2928 if (!scaler_state->scalers[i].in_use) {
2929 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2930 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2931 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2932 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2933 intel_crtc->base.base.id, intel_crtc->pipe, i);
2934 }
2935 }
2936}
2937
6156a456 2938u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2939{
6156a456 2940 switch (pixel_format) {
d161cf7a 2941 case DRM_FORMAT_C8:
c34ce3d1 2942 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2943 case DRM_FORMAT_RGB565:
c34ce3d1 2944 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2945 case DRM_FORMAT_XBGR8888:
c34ce3d1 2946 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2947 case DRM_FORMAT_XRGB8888:
c34ce3d1 2948 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2949 /*
2950 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2951 * to be already pre-multiplied. We need to add a knob (or a different
2952 * DRM_FORMAT) for user-space to configure that.
2953 */
f75fb42a 2954 case DRM_FORMAT_ABGR8888:
c34ce3d1 2955 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2957 case DRM_FORMAT_ARGB8888:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2959 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2960 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2961 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2962 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2963 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2964 case DRM_FORMAT_YUYV:
c34ce3d1 2965 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2966 case DRM_FORMAT_YVYU:
c34ce3d1 2967 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2968 case DRM_FORMAT_UYVY:
c34ce3d1 2969 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2970 case DRM_FORMAT_VYUY:
c34ce3d1 2971 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2972 default:
4249eeef 2973 MISSING_CASE(pixel_format);
70d21f0e 2974 }
8cfcba41 2975
c34ce3d1 2976 return 0;
6156a456 2977}
70d21f0e 2978
6156a456
CK		 2979u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2980{
6156a456 2981 switch (fb_modifier) {
30af77c4 2982 case DRM_FORMAT_MOD_NONE:
70d21f0e 2983 break;
30af77c4 2984 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2985 return PLANE_CTL_TILED_X;
b321803d 2986 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2987 return PLANE_CTL_TILED_Y;
b321803d 2988 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2989 return PLANE_CTL_TILED_YF;
70d21f0e 2990 default:
6156a456 2991 MISSING_CASE(fb_modifier);
70d21f0e 2992 }
8cfcba41 2993
c34ce3d1 2994 return 0;
6156a456 2995}
70d21f0e 2996
6156a456
CK		 2997u32 skl_plane_ctl_rotation(unsigned int rotation)
2998{
3b7a5119 2999 switch (rotation) {
6156a456
CK		 3000 case BIT(DRM_ROTATE_0):
3001 break;
1e8df167
SJ		 3002 /*
3003 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3004 * while i915 HW rotation is clockwise, thats why this swapping.
3005 */
3b7a5119 3006 case BIT(DRM_ROTATE_90):
1e8df167 3007 return PLANE_CTL_ROTATE_270;
3b7a5119 3008 case BIT(DRM_ROTATE_180):
c34ce3d1 3009 return PLANE_CTL_ROTATE_180;
3b7a5119 3010 case BIT(DRM_ROTATE_270):
1e8df167 3011 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3012 default:
3013 MISSING_CASE(rotation);
3014 }
3015
c34ce3d1 3016 return 0;
6156a456
CK		 3017}
3018
3019static void skylake_update_primary_plane(struct drm_crtc *crtc,
3020 struct drm_framebuffer *fb,
3021 int x, int y)
3022{
3023 struct drm_device *dev = crtc->dev;
3024 struct drm_i915_private *dev_priv = dev->dev_private;
3025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3026 struct drm_plane *plane = crtc->primary;
3027 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3028 struct drm_i915_gem_object *obj;
3029 int pipe = intel_crtc->pipe;
3030 u32 plane_ctl, stride_div, stride;
3031 u32 tile_height, plane_offset, plane_size;
3032 unsigned int rotation;
3033 int x_offset, y_offset;
3034 unsigned long surf_addr;
6156a456
CK		 3035 struct intel_crtc_state *crtc_state = intel_crtc->config;
3036 struct intel_plane_state *plane_state;
3037 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3038 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3039 int scaler_id = -1;
3040
6156a456
CK		 3041 plane_state = to_intel_plane_state(plane->state);
3042
b70709a6 3043 if (!visible || !fb) {
6156a456
CK		 3044 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3045 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3046 POSTING_READ(PLANE_CTL(pipe, 0));
3047 return;
3b7a5119 3048 }
70d21f0e 3049
6156a456
CK		 3050 plane_ctl = PLANE_CTL_ENABLE |
3051 PLANE_CTL_PIPE_GAMMA_ENABLE |
3052 PLANE_CTL_PIPE_CSC_ENABLE;
3053
3054 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3055 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3056 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3057
3058 rotation = plane->state->rotation;
3059 plane_ctl |= skl_plane_ctl_rotation(rotation);
3060
b321803d
DL		 3061 obj = intel_fb_obj(fb);
3062 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3063 fb->pixel_format);
3b7a5119
SJ		 3064 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3065
6156a456
CK		 3066 /*
3067 * FIXME: intel_plane_state->src, dst aren't set when transitional
3068 * update_plane helpers are called from legacy paths.
3069 * Once full atomic crtc is available, below check can be avoided.
3070 */
3071 if (drm_rect_width(&plane_state->src)) {
3072 scaler_id = plane_state->scaler_id;
3073 src_x = plane_state->src.x1 >> 16;
3074 src_y = plane_state->src.y1 >> 16;
3075 src_w = drm_rect_width(&plane_state->src) >> 16;
3076 src_h = drm_rect_height(&plane_state->src) >> 16;
3077 dst_x = plane_state->dst.x1;
3078 dst_y = plane_state->dst.y1;
3079 dst_w = drm_rect_width(&plane_state->dst);
3080 dst_h = drm_rect_height(&plane_state->dst);
3081
3082 WARN_ON(x != src_x || y != src_y);
3083 } else {
3084 src_w = intel_crtc->config->pipe_src_w;
3085 src_h = intel_crtc->config->pipe_src_h;
3086 }
3087
3b7a5119
SJ		 3088 if (intel_rotation_90_or_270(rotation)) {
3089 /* stride = Surface height in tiles */
2614f17d 3090 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3091 fb->modifier[0]);
3092 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3093 x_offset = stride * tile_height - y - src_h;
3b7a5119 3094 y_offset = x;
6156a456 3095 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3096 } else {
3097 stride = fb->pitches[0] / stride_div;
3098 x_offset = x;
3099 y_offset = y;
6156a456 3100 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3101 }
3102 plane_offset = y_offset << 16 | x_offset;
b321803d 3103
70d21f0e 3104 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3105 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3106 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3107 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3108
3109 if (scaler_id >= 0) {
3110 uint32_t ps_ctrl = 0;
3111
3112 WARN_ON(!dst_w || !dst_h);
3113 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3114 crtc_state->scaler_state.scalers[scaler_id].mode;
3115 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3116 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3117 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3118 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3119 I915_WRITE(PLANE_POS(pipe, 0), 0);
3120 } else {
3121 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3122 }
3123
121920fa 3124 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3125
3126 POSTING_READ(PLANE_SURF(pipe, 0));
3127}
3128
17638cd6
JB		 3129/* Assume fb object is pinned & idle & fenced and just update base pointers */
3130static int
3131intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3132 int x, int y, enum mode_set_atomic state)
3133{
3134 struct drm_device *dev = crtc->dev;
3135 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3136
6b8e6ed0
CW		 3137 if (dev_priv->display.disable_fbc)
3138 dev_priv->display.disable_fbc(dev);
81255565 3139
29b9bde6
DV		 3140 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3141
3142 return 0;
81255565
JB		 3143}
3144
7514747d 3145static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3146{
96a02917
VS		 3147 struct drm_crtc *crtc;
3148
70e1e0ec 3149 for_each_crtc(dev, crtc) {
96a02917
VS		 3150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3151 enum plane plane = intel_crtc->plane;
3152
3153 intel_prepare_page_flip(dev, plane);
3154 intel_finish_page_flip_plane(dev, plane);
3155 }
7514747d
VS		 3156}
3157
3158static void intel_update_primary_planes(struct drm_device *dev)
3159{
3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161 struct drm_crtc *crtc;
96a02917 3162
70e1e0ec 3163 for_each_crtc(dev, crtc) {
96a02917
VS		 3164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3165
51fd371b 3166 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3167 /*
3168 * FIXME: Once we have proper support for primary planes (and
3169 * disabling them without disabling the entire crtc) allow again
66e514c1 3170 * a NULL crtc->primary->fb.
947fdaad 3171 */
f4510a27 3172 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3173 dev_priv->display.update_primary_plane(crtc,
66e514c1 3174 crtc->primary->fb,
262ca2b0
MR		 3175 crtc->x,
3176 crtc->y);
51fd371b 3177 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3178 }
3179}
3180
7514747d
VS		 3181void intel_prepare_reset(struct drm_device *dev)
3182{
3183 /* no reset support for gen2 */
3184 if (IS_GEN2(dev))
3185 return;
3186
3187 /* reset doesn't touch the display */
3188 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3189 return;
3190
3191 drm_modeset_lock_all(dev);
f98ce92f
VS		 3192 /*
3193 * Disabling the crtcs gracefully seems nicer. Also the
3194 * g33 docs say we should at least disable all the planes.
3195 */
6b72d486 3196 intel_display_suspend(dev);
7514747d
VS		 3197}
3198
3199void intel_finish_reset(struct drm_device *dev)
3200{
3201 struct drm_i915_private *dev_priv = to_i915(dev);
3202
3203 /*
3204 * Flips in the rings will be nuked by the reset,
3205 * so complete all pending flips so that user space
3206 * will get its events and not get stuck.
3207 */
3208 intel_complete_page_flips(dev);
3209
3210 /* no reset support for gen2 */
3211 if (IS_GEN2(dev))
3212 return;
3213
3214 /* reset doesn't touch the display */
3215 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3216 /*
3217 * Flips in the rings have been nuked by the reset,
3218 * so update the base address of all primary
3219 * planes to the the last fb to make sure we're
3220 * showing the correct fb after a reset.
3221 */
3222 intel_update_primary_planes(dev);
3223 return;
3224 }
3225
3226 /*
3227 * The display has been reset as well,
3228 * so need a full re-initialization.
3229 */
3230 intel_runtime_pm_disable_interrupts(dev_priv);
3231 intel_runtime_pm_enable_interrupts(dev_priv);
3232
3233 intel_modeset_init_hw(dev);
3234
3235 spin_lock_irq(&dev_priv->irq_lock);
3236 if (dev_priv->display.hpd_irq_setup)
3237 dev_priv->display.hpd_irq_setup(dev);
3238 spin_unlock_irq(&dev_priv->irq_lock);
3239
3240 intel_modeset_setup_hw_state(dev, true);
3241
3242 intel_hpd_init(dev_priv);
3243
3244 drm_modeset_unlock_all(dev);
3245}
3246
2e2f351d 3247static void
14667a4b
CW		 3248intel_finish_fb(struct drm_framebuffer *old_fb)
3249{
2ff8fde1 3250 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3251 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3252 bool was_interruptible = dev_priv->mm.interruptible;
3253 int ret;
3254
14667a4b
CW		 3255 /* Big Hammer, we also need to ensure that any pending
3256 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3257 * current scanout is retired before unpinning the old
2e2f351d
CW		 3258 * framebuffer. Note that we rely on userspace rendering
3259 * into the buffer attached to the pipe they are waiting
3260 * on. If not, userspace generates a GPU hang with IPEHR
3261 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3262 *
3263 * This should only fail upon a hung GPU, in which case we
3264 * can safely continue.
3265 */
3266 dev_priv->mm.interruptible = false;
2e2f351d 3267 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3268 dev_priv->mm.interruptible = was_interruptible;
3269
2e2f351d 3270 WARN_ON(ret);
14667a4b
CW		 3271}
3272
7d5e3799
CW		 3273static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3274{
3275 struct drm_device *dev = crtc->dev;
3276 struct drm_i915_private *dev_priv = dev->dev_private;
3277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3278 bool pending;
3279
3280 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3281 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3282 return false;
3283
5e2d7afc 3284 spin_lock_irq(&dev->event_lock);
7d5e3799 3285 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3286 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3287
3288 return pending;
3289}
3290
e30e8f75
GP		 3291static void intel_update_pipe_size(struct intel_crtc *crtc)
3292{
3293 struct drm_device *dev = crtc->base.dev;
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295 const struct drm_display_mode *adjusted_mode;
3296
3297 if (!i915.fastboot)
3298 return;
3299
3300 /*
3301 * Update pipe size and adjust fitter if needed: the reason for this is
3302 * that in compute_mode_changes we check the native mode (not the pfit
3303 * mode) to see if we can flip rather than do a full mode set. In the
3304 * fastboot case, we'll flip, but if we don't update the pipesrc and
3305 * pfit state, we'll end up with a big fb scanned out into the wrong
3306 * sized surface.
3307 *
3308 * To fix this properly, we need to hoist the checks up into
3309 * compute_mode_changes (or above), check the actual pfit state and
3310 * whether the platform allows pfit disable with pipe active, and only
3311 * then update the pipesrc and pfit state, even on the flip path.
3312 */
3313
6e3c9717 3314 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3315
3316 I915_WRITE(PIPESRC(crtc->pipe),
3317 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3318 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3319 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3320 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3321 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3322 I915_WRITE(PF_CTL(crtc->pipe), 0);
3323 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3324 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3325 }
6e3c9717
ACO		 3326 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3327 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3328}
3329
5e84e1a4
ZW		 3330static void intel_fdi_normal_train(struct drm_crtc *crtc)
3331{
3332 struct drm_device *dev = crtc->dev;
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3335 int pipe = intel_crtc->pipe;
3336 u32 reg, temp;
3337
3338 /* enable normal train */
3339 reg = FDI_TX_CTL(pipe);
3340 temp = I915_READ(reg);
61e499bf 3341 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3342 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3343 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3344 } else {
3345 temp &= ~FDI_LINK_TRAIN_NONE;
3346 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3347 }
5e84e1a4
ZW		 3348 I915_WRITE(reg, temp);
3349
3350 reg = FDI_RX_CTL(pipe);
3351 temp = I915_READ(reg);
3352 if (HAS_PCH_CPT(dev)) {
3353 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3354 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3355 } else {
3356 temp &= ~FDI_LINK_TRAIN_NONE;
3357 temp |= FDI_LINK_TRAIN_NONE;
3358 }
3359 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3360
3361 /* wait one idle pattern time */
3362 POSTING_READ(reg);
3363 udelay(1000);
357555c0
JB		 3364
3365 /* IVB wants error correction enabled */
3366 if (IS_IVYBRIDGE(dev))
3367 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3368 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3369}
3370
8db9d77b
ZW		 3371/* The FDI link training functions for ILK/Ibexpeak. */
3372static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3373{
3374 struct drm_device *dev = crtc->dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3377 int pipe = intel_crtc->pipe;
5eddb70b 3378 u32 reg, temp, tries;
8db9d77b 3379
1c8562f6 3380 /* FDI needs bits from pipe first */
0fc932b8 3381 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3382
e1a44743
AJ		 3383 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3384 for train result */
5eddb70b
CW		 3385 reg = FDI_RX_IMR(pipe);
3386 temp = I915_READ(reg);
e1a44743
AJ		 3387 temp &= ~FDI_RX_SYMBOL_LOCK;
3388 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3389 I915_WRITE(reg, temp);
3390 I915_READ(reg);
e1a44743
AJ		 3391 udelay(150);
3392
8db9d77b 3393 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3394 reg = FDI_TX_CTL(pipe);
3395 temp = I915_READ(reg);
627eb5a3 3396 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3397 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3398 temp &= ~FDI_LINK_TRAIN_NONE;
3399 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3400 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3401
5eddb70b
CW		 3402 reg = FDI_RX_CTL(pipe);
3403 temp = I915_READ(reg);
8db9d77b
ZW		 3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3406 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3407
3408 POSTING_READ(reg);
8db9d77b
ZW		 3409 udelay(150);
3410
5b2adf89 3411 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3412 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3413 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3414 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3415
5eddb70b 3416 reg = FDI_RX_IIR(pipe);
e1a44743 3417 for (tries = 0; tries < 5; tries++) {
5eddb70b 3418 temp = I915_READ(reg);
8db9d77b
ZW		 3419 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3420
3421 if ((temp & FDI_RX_BIT_LOCK)) {
3422 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3423 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3424 break;
3425 }
8db9d77b 3426 }
e1a44743 3427 if (tries == 5)
5eddb70b 3428 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3429
3430 /* Train 2 */
5eddb70b
CW		 3431 reg = FDI_TX_CTL(pipe);
3432 temp = I915_READ(reg);
8db9d77b
ZW		 3433 temp &= ~FDI_LINK_TRAIN_NONE;
3434 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3435 I915_WRITE(reg, temp);
8db9d77b 3436
5eddb70b
CW		 3437 reg = FDI_RX_CTL(pipe);
3438 temp = I915_READ(reg);
8db9d77b
ZW		 3439 temp &= ~FDI_LINK_TRAIN_NONE;
3440 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3441 I915_WRITE(reg, temp);
8db9d77b 3442
5eddb70b
CW		 3443 POSTING_READ(reg);
3444 udelay(150);
8db9d77b 3445
5eddb70b 3446 reg = FDI_RX_IIR(pipe);
e1a44743 3447 for (tries = 0; tries < 5; tries++) {
5eddb70b 3448 temp = I915_READ(reg);
8db9d77b
ZW		 3449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3450
3451 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3452 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3453 DRM_DEBUG_KMS("FDI train 2 done.\n");
3454 break;
3455 }
8db9d77b 3456 }
e1a44743 3457 if (tries == 5)
5eddb70b 3458 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3459
3460 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3461
8db9d77b
ZW		 3462}
3463
0206e353 3464static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3465 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3466 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3467 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3468 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3469};
3470
3471/* The FDI link training functions for SNB/Cougarpoint. */
3472static void gen6_fdi_link_train(struct drm_crtc *crtc)
3473{
3474 struct drm_device *dev = crtc->dev;
3475 struct drm_i915_private *dev_priv = dev->dev_private;
3476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3477 int pipe = intel_crtc->pipe;
fa37d39e 3478 u32 reg, temp, i, retry;
8db9d77b 3479
e1a44743
AJ		 3480 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3481 for train result */
5eddb70b
CW		 3482 reg = FDI_RX_IMR(pipe);
3483 temp = I915_READ(reg);
e1a44743
AJ		 3484 temp &= ~FDI_RX_SYMBOL_LOCK;
3485 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3486 I915_WRITE(reg, temp);
3487
3488 POSTING_READ(reg);
e1a44743
AJ		 3489 udelay(150);
3490
8db9d77b 3491 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3492 reg = FDI_TX_CTL(pipe);
3493 temp = I915_READ(reg);
627eb5a3 3494 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3495 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3496 temp &= ~FDI_LINK_TRAIN_NONE;
3497 temp |= FDI_LINK_TRAIN_PATTERN_1;
3498 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3499 /* SNB-B */
3500 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3501 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3502
d74cf324
DV		 3503 I915_WRITE(FDI_RX_MISC(pipe),
3504 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3505
5eddb70b
CW		 3506 reg = FDI_RX_CTL(pipe);
3507 temp = I915_READ(reg);
8db9d77b
ZW		 3508 if (HAS_PCH_CPT(dev)) {
3509 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3510 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3511 } else {
3512 temp &= ~FDI_LINK_TRAIN_NONE;
3513 temp |= FDI_LINK_TRAIN_PATTERN_1;
3514 }
5eddb70b
CW		 3515 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3516
3517 POSTING_READ(reg);
8db9d77b
ZW		 3518 udelay(150);
3519
0206e353 3520 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3521 reg = FDI_TX_CTL(pipe);
3522 temp = I915_READ(reg);
8db9d77b
ZW		 3523 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3524 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3525 I915_WRITE(reg, temp);
3526
3527 POSTING_READ(reg);
8db9d77b
ZW		 3528 udelay(500);
3529
fa37d39e
SP		 3530 for (retry = 0; retry < 5; retry++) {
3531 reg = FDI_RX_IIR(pipe);
3532 temp = I915_READ(reg);
3533 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3534 if (temp & FDI_RX_BIT_LOCK) {
3535 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3536 DRM_DEBUG_KMS("FDI train 1 done.\n");
3537 break;
3538 }
3539 udelay(50);
8db9d77b 3540 }
fa37d39e
SP		 3541 if (retry < 5)
3542 break;
8db9d77b
ZW		 3543 }
3544 if (i == 4)
5eddb70b 3545 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3546
3547 /* Train 2 */
5eddb70b
CW		 3548 reg = FDI_TX_CTL(pipe);
3549 temp = I915_READ(reg);
8db9d77b
ZW		 3550 temp &= ~FDI_LINK_TRAIN_NONE;
3551 temp |= FDI_LINK_TRAIN_PATTERN_2;
3552 if (IS_GEN6(dev)) {
3553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3554 /* SNB-B */
3555 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3556 }
5eddb70b 3557 I915_WRITE(reg, temp);
8db9d77b 3558
5eddb70b
CW		 3559 reg = FDI_RX_CTL(pipe);
3560 temp = I915_READ(reg);
8db9d77b
ZW		 3561 if (HAS_PCH_CPT(dev)) {
3562 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3563 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3564 } else {
3565 temp &= ~FDI_LINK_TRAIN_NONE;
3566 temp |= FDI_LINK_TRAIN_PATTERN_2;
3567 }
5eddb70b
CW		 3568 I915_WRITE(reg, temp);
3569
3570 POSTING_READ(reg);
8db9d77b
ZW		 3571 udelay(150);
3572
0206e353 3573 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3574 reg = FDI_TX_CTL(pipe);
3575 temp = I915_READ(reg);
8db9d77b
ZW		 3576 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3578 I915_WRITE(reg, temp);
3579
3580 POSTING_READ(reg);
8db9d77b
ZW		 3581 udelay(500);
3582
fa37d39e
SP		 3583 for (retry = 0; retry < 5; retry++) {
3584 reg = FDI_RX_IIR(pipe);
3585 temp = I915_READ(reg);
3586 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3587 if (temp & FDI_RX_SYMBOL_LOCK) {
3588 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3589 DRM_DEBUG_KMS("FDI train 2 done.\n");
3590 break;
3591 }
3592 udelay(50);
8db9d77b 3593 }
fa37d39e
SP		 3594 if (retry < 5)
3595 break;
8db9d77b
ZW		 3596 }
3597 if (i == 4)
5eddb70b 3598 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3599
3600 DRM_DEBUG_KMS("FDI train done.\n");
3601}
3602
357555c0
JB		 3603/* Manual link training for Ivy Bridge A0 parts */
3604static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3605{
3606 struct drm_device *dev = crtc->dev;
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3609 int pipe = intel_crtc->pipe;
139ccd3f 3610 u32 reg, temp, i, j;
357555c0
JB		 3611
3612 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3613 for train result */
3614 reg = FDI_RX_IMR(pipe);
3615 temp = I915_READ(reg);
3616 temp &= ~FDI_RX_SYMBOL_LOCK;
3617 temp &= ~FDI_RX_BIT_LOCK;
3618 I915_WRITE(reg, temp);
3619
3620 POSTING_READ(reg);
3621 udelay(150);
3622
01a415fd
DV		 3623 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3624 I915_READ(FDI_RX_IIR(pipe)));
3625
139ccd3f
JB		 3626 /* Try each vswing and preemphasis setting twice before moving on */
3627 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3628 /* disable first in case we need to retry */
3629 reg = FDI_TX_CTL(pipe);
3630 temp = I915_READ(reg);
3631 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3632 temp &= ~FDI_TX_ENABLE;
3633 I915_WRITE(reg, temp);
357555c0 3634
139ccd3f
JB		 3635 reg = FDI_RX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~FDI_LINK_TRAIN_AUTO;
3638 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3639 temp &= ~FDI_RX_ENABLE;
3640 I915_WRITE(reg, temp);
357555c0 3641
139ccd3f 3642 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3643 reg = FDI_TX_CTL(pipe);
3644 temp = I915_READ(reg);
139ccd3f 3645 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3646 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3647 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3649 temp |= snb_b_fdi_train_param[j/2];
3650 temp |= FDI_COMPOSITE_SYNC;
3651 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3652
139ccd3f
JB		 3653 I915_WRITE(FDI_RX_MISC(pipe),
3654 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3655
139ccd3f 3656 reg = FDI_RX_CTL(pipe);
357555c0 3657 temp = I915_READ(reg);
139ccd3f
JB		 3658 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3659 temp |= FDI_COMPOSITE_SYNC;
3660 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3661
139ccd3f
JB		 3662 POSTING_READ(reg);
3663 udelay(1); /* should be 0.5us */
357555c0 3664
139ccd3f
JB		 3665 for (i = 0; i < 4; i++) {
3666 reg = FDI_RX_IIR(pipe);
3667 temp = I915_READ(reg);
3668 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3669
139ccd3f
JB		 3670 if (temp & FDI_RX_BIT_LOCK ||
3671 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3672 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3673 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3674 i);
3675 break;
3676 }
3677 udelay(1); /* should be 0.5us */
3678 }
3679 if (i == 4) {
3680 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3681 continue;
3682 }
357555c0 3683
139ccd3f 3684 /* Train 2 */
357555c0
JB		 3685 reg = FDI_TX_CTL(pipe);
3686 temp = I915_READ(reg);
139ccd3f
JB		 3687 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3688 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3689 I915_WRITE(reg, temp);
3690
3691 reg = FDI_RX_CTL(pipe);
3692 temp = I915_READ(reg);
3693 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3694 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3695 I915_WRITE(reg, temp);
3696
3697 POSTING_READ(reg);
139ccd3f 3698 udelay(2); /* should be 1.5us */
357555c0 3699
139ccd3f
JB		 3700 for (i = 0; i < 4; i++) {
3701 reg = FDI_RX_IIR(pipe);
3702 temp = I915_READ(reg);
3703 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3704
139ccd3f
JB		 3705 if (temp & FDI_RX_SYMBOL_LOCK ||
3706 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3707 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3708 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3709 i);
3710 goto train_done;
3711 }
3712 udelay(2); /* should be 1.5us */
357555c0 3713 }
139ccd3f
JB		 3714 if (i == 4)
3715 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3716 }
357555c0 3717
139ccd3f 3718train_done:
357555c0
JB		 3719 DRM_DEBUG_KMS("FDI train done.\n");
3720}
3721
88cefb6c 3722static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3723{
88cefb6c 3724 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3725 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3726 int pipe = intel_crtc->pipe;
5eddb70b 3727 u32 reg, temp;
79e53945 3728
c64e311e 3729
c98e9dcf 3730 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3731 reg = FDI_RX_CTL(pipe);
3732 temp = I915_READ(reg);
627eb5a3 3733 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3734 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3735 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3736 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3737
3738 POSTING_READ(reg);
c98e9dcf
JB		 3739 udelay(200);
3740
3741 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3742 temp = I915_READ(reg);
3743 I915_WRITE(reg, temp | FDI_PCDCLK);
3744
3745 POSTING_READ(reg);
c98e9dcf
JB		 3746 udelay(200);
3747
20749730
PZ		 3748 /* Enable CPU FDI TX PLL, always on for Ironlake */
3749 reg = FDI_TX_CTL(pipe);
3750 temp = I915_READ(reg);
3751 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3752 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3753
20749730
PZ		 3754 POSTING_READ(reg);
3755 udelay(100);
6be4a607 3756 }
0e23b99d
JB		 3757}
3758
88cefb6c
DV		 3759static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3760{
3761 struct drm_device *dev = intel_crtc->base.dev;
3762 struct drm_i915_private *dev_priv = dev->dev_private;
3763 int pipe = intel_crtc->pipe;
3764 u32 reg, temp;
3765
3766 /* Switch from PCDclk to Rawclk */
3767 reg = FDI_RX_CTL(pipe);
3768 temp = I915_READ(reg);
3769 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3770
3771 /* Disable CPU FDI TX PLL */
3772 reg = FDI_TX_CTL(pipe);
3773 temp = I915_READ(reg);
3774 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3775
3776 POSTING_READ(reg);
3777 udelay(100);
3778
3779 reg = FDI_RX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3782
3783 /* Wait for the clocks to turn off. */
3784 POSTING_READ(reg);
3785 udelay(100);
3786}
3787
0fc932b8
JB		 3788static void ironlake_fdi_disable(struct drm_crtc *crtc)
3789{
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3793 int pipe = intel_crtc->pipe;
3794 u32 reg, temp;
3795
3796 /* disable CPU FDI tx and PCH FDI rx */
3797 reg = FDI_TX_CTL(pipe);
3798 temp = I915_READ(reg);
3799 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3800 POSTING_READ(reg);
3801
3802 reg = FDI_RX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 temp &= ~(0x7 << 16);
dfd07d72 3805 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3806 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3807
3808 POSTING_READ(reg);
3809 udelay(100);
3810
3811 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3812 if (HAS_PCH_IBX(dev))
6f06ce18 3813 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3814
3815 /* still set train pattern 1 */
3816 reg = FDI_TX_CTL(pipe);
3817 temp = I915_READ(reg);
3818 temp &= ~FDI_LINK_TRAIN_NONE;
3819 temp |= FDI_LINK_TRAIN_PATTERN_1;
3820 I915_WRITE(reg, temp);
3821
3822 reg = FDI_RX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 if (HAS_PCH_CPT(dev)) {
3825 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3826 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3827 } else {
3828 temp &= ~FDI_LINK_TRAIN_NONE;
3829 temp |= FDI_LINK_TRAIN_PATTERN_1;
3830 }
3831 /* BPC in FDI rx is consistent with that in PIPECONF */
3832 temp &= ~(0x07 << 16);
dfd07d72 3833 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3834 I915_WRITE(reg, temp);
3835
3836 POSTING_READ(reg);
3837 udelay(100);
3838}
3839
5dce5b93
CW		 3840bool intel_has_pending_fb_unpin(struct drm_device *dev)
3841{
3842 struct intel_crtc *crtc;
3843
3844 /* Note that we don't need to be called with mode_config.lock here
3845 * as our list of CRTC objects is static for the lifetime of the
3846 * device and so cannot disappear as we iterate. Similarly, we can
3847 * happily treat the predicates as racy, atomic checks as userspace
3848 * cannot claim and pin a new fb without at least acquring the
3849 * struct_mutex and so serialising with us.
3850 */
d3fcc808 3851 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3852 if (atomic_read(&crtc->unpin_work_count) == 0)
3853 continue;
3854
3855 if (crtc->unpin_work)
3856 intel_wait_for_vblank(dev, crtc->pipe);
3857
3858 return true;
3859 }
3860
3861 return false;
3862}
3863
d6bbafa1
CW		 3864static void page_flip_completed(struct intel_crtc *intel_crtc)
3865{
3866 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3867 struct intel_unpin_work *work = intel_crtc->unpin_work;
3868
3869 /* ensure that the unpin work is consistent wrt ->pending. */
3870 smp_rmb();
3871 intel_crtc->unpin_work = NULL;
3872
3873 if (work->event)
3874 drm_send_vblank_event(intel_crtc->base.dev,
3875 intel_crtc->pipe,
3876 work->event);
3877
3878 drm_crtc_vblank_put(&intel_crtc->base);
3879
3880 wake_up_all(&dev_priv->pending_flip_queue);
3881 queue_work(dev_priv->wq, &work->work);
3882
3883 trace_i915_flip_complete(intel_crtc->plane,
3884 work->pending_flip_obj);
3885}
3886
46a55d30 3887void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3888{
0f91128d 3889 struct drm_device *dev = crtc->dev;
5bb61643 3890 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3891
2c10d571 3892 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3893 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3894 !intel_crtc_has_pending_flip(crtc),
3895 60*HZ) == 0)) {
3896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3897
5e2d7afc 3898 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3899 if (intel_crtc->unpin_work) {
3900 WARN_ONCE(1, "Removing stuck page flip\n");
3901 page_flip_completed(intel_crtc);
3902 }
5e2d7afc 3903 spin_unlock_irq(&dev->event_lock);
9c787942 3904 }
5bb61643 3905
975d568a
CW		 3906 if (crtc->primary->fb) {
3907 mutex_lock(&dev->struct_mutex);
3908 intel_finish_fb(crtc->primary->fb);
3909 mutex_unlock(&dev->struct_mutex);
3910 }
e6c3a2a6
CW		 3911}
3912
e615efe4
ED		 3913/* Program iCLKIP clock to the desired frequency */
3914static void lpt_program_iclkip(struct drm_crtc *crtc)
3915{
3916 struct drm_device *dev = crtc->dev;
3917 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3918 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3919 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3920 u32 temp;
3921
a580516d 3922 mutex_lock(&dev_priv->sb_lock);
09153000 3923
e615efe4
ED		 3924 /* It is necessary to ungate the pixclk gate prior to programming
3925 * the divisors, and gate it back when it is done.
3926 */
3927 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3928
3929 /* Disable SSCCTL */
3930 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3931 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3932 SBI_SSCCTL_DISABLE,
3933 SBI_ICLK);
e615efe4
ED		 3934
3935 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3936 if (clock == 20000) {
e615efe4
ED		 3937 auxdiv = 1;
3938 divsel = 0x41;
3939 phaseinc = 0x20;
3940 } else {
3941 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3942 * but the adjusted_mode->crtc_clock in in KHz. To get the
3943 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3944 * convert the virtual clock precision to KHz here for higher
3945 * precision.
3946 */
3947 u32 iclk_virtual_root_freq = 172800 * 1000;
3948 u32 iclk_pi_range = 64;
3949 u32 desired_divisor, msb_divisor_value, pi_value;
3950
12d7ceed 3951 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3952 msb_divisor_value = desired_divisor / iclk_pi_range;
3953 pi_value = desired_divisor % iclk_pi_range;
3954
3955 auxdiv = 0;
3956 divsel = msb_divisor_value - 2;
3957 phaseinc = pi_value;
3958 }
3959
3960 /* This should not happen with any sane values */
3961 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3962 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3963 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3964 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3965
3966 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3967 clock,
e615efe4
ED		 3968 auxdiv,
3969 divsel,
3970 phasedir,
3971 phaseinc);
3972
3973 /* Program SSCDIVINTPHASE6 */
988d6ee8 3974 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3975 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3976 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3977 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3978 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3979 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3980 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3981 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3982
3983 /* Program SSCAUXDIV */
988d6ee8 3984 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3985 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3986 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3987 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3988
3989 /* Enable modulator and associated divider */
988d6ee8 3990 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3991 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3992 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3993
3994 /* Wait for initialization time */
3995 udelay(24);
3996
3997 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 3998
a580516d 3999 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4000}
4001
275f01b2
DV		 4002static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4003 enum pipe pch_transcoder)
4004{
4005 struct drm_device *dev = crtc->base.dev;
4006 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4007 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4008
4009 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4010 I915_READ(HTOTAL(cpu_transcoder)));
4011 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4012 I915_READ(HBLANK(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4014 I915_READ(HSYNC(cpu_transcoder)));
4015
4016 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4017 I915_READ(VTOTAL(cpu_transcoder)));
4018 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4019 I915_READ(VBLANK(cpu_transcoder)));
4020 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4021 I915_READ(VSYNC(cpu_transcoder)));
4022 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4023 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4024}
4025
003632d9 4026static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4027{
4028 struct drm_i915_private *dev_priv = dev->dev_private;
4029 uint32_t temp;
4030
4031 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4032 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4033 return;
4034
4035 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4036 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4037
003632d9
ACO		 4038 temp &= ~FDI_BC_BIFURCATION_SELECT;
4039 if (enable)
4040 temp |= FDI_BC_BIFURCATION_SELECT;
4041
4042 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4043 I915_WRITE(SOUTH_CHICKEN1, temp);
4044 POSTING_READ(SOUTH_CHICKEN1);
4045}
4046
4047static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4048{
4049 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4050
4051 switch (intel_crtc->pipe) {
4052 case PIPE_A:
4053 break;
4054 case PIPE_B:
6e3c9717 4055 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4056 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4057 else
003632d9 4058 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4059
4060 break;
4061 case PIPE_C:
003632d9 4062 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4063
4064 break;
4065 default:
4066 BUG();
4067 }
4068}
4069
f67a559d
JB		 4070/*
4071 * Enable PCH resources required for PCH ports:
4072 * - PCH PLLs
4073 * - FDI training & RX/TX
4074 * - update transcoder timings
4075 * - DP transcoding bits
4076 * - transcoder
4077 */
4078static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4079{
4080 struct drm_device *dev = crtc->dev;
4081 struct drm_i915_private *dev_priv = dev->dev_private;
4082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4083 int pipe = intel_crtc->pipe;
ee7b9f93 4084 u32 reg, temp;
2c07245f 4085
ab9412ba 4086 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4087
1fbc0d78
DV		 4088 if (IS_IVYBRIDGE(dev))
4089 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4090
cd986abb
DV		 4091 /* Write the TU size bits before fdi link training, so that error
4092 * detection works. */
4093 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4094 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4095
c98e9dcf 4096 /* For PCH output, training FDI link */
674cf967 4097 dev_priv->display.fdi_link_train(crtc);
2c07245f 4098
3ad8a208
DV		 4099 /* We need to program the right clock selection before writing the pixel
4100 * mutliplier into the DPLL. */
303b81e0 4101 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4102 u32 sel;
4b645f14 4103
c98e9dcf 4104 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4105 temp |= TRANS_DPLL_ENABLE(pipe);
4106 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4107 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4108 temp |= sel;
4109 else
4110 temp &= ~sel;
c98e9dcf 4111 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4112 }
5eddb70b 4113
3ad8a208
DV		 4114 /* XXX: pch pll's can be enabled any time before we enable the PCH
4115 * transcoder, and we actually should do this to not upset any PCH
4116 * transcoder that already use the clock when we share it.
4117 *
4118 * Note that enable_shared_dpll tries to do the right thing, but
4119 * get_shared_dpll unconditionally resets the pll - we need that to have
4120 * the right LVDS enable sequence. */
85b3894f 4121 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4122
d9b6cb56
JB		 4123 /* set transcoder timing, panel must allow it */
4124 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4125 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4126
303b81e0 4127 intel_fdi_normal_train(crtc);
5e84e1a4 4128
c98e9dcf 4129 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4130 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4131 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4132 reg = TRANS_DP_CTL(pipe);
4133 temp = I915_READ(reg);
4134 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4135 TRANS_DP_SYNC_MASK |
4136 TRANS_DP_BPC_MASK);
e3ef4479 4137 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4138 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4139
4140 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4141 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4142 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4143 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4144
4145 switch (intel_trans_dp_port_sel(crtc)) {
4146 case PCH_DP_B:
5eddb70b 4147 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4148 break;
4149 case PCH_DP_C:
5eddb70b 4150 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4151 break;
4152 case PCH_DP_D:
5eddb70b 4153 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4154 break;
4155 default:
e95d41e1 4156 BUG();
32f9d658 4157 }
2c07245f 4158
5eddb70b 4159 I915_WRITE(reg, temp);
6be4a607 4160 }
b52eb4dc 4161
b8a4f404 4162 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4163}
4164
1507e5bd
PZ		 4165static void lpt_pch_enable(struct drm_crtc *crtc)
4166{
4167 struct drm_device *dev = crtc->dev;
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4170 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4171
ab9412ba 4172 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4173
8c52b5e8 4174 lpt_program_iclkip(crtc);
1507e5bd 4175
0540e488 4176 /* Set transcoder timing. */
275f01b2 4177 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4178
937bb610 4179 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4180}
4181
190f68c5
ACO		 4182struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4183 struct intel_crtc_state *crtc_state)
ee7b9f93 4184{
e2b78267 4185 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4186 struct intel_shared_dpll *pll;
de419ab6 4187 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4188 enum intel_dpll_id i;
ee7b9f93 4189
de419ab6
ML		 4190 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4191
98b6bd99
DV		 4192 if (HAS_PCH_IBX(dev_priv->dev)) {
4193 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4194 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4195 pll = &dev_priv->shared_dplls[i];
98b6bd99 4196
46edb027
DV		 4197 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4198 crtc->base.base.id, pll->name);
98b6bd99 4199
de419ab6 4200 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4201
98b6bd99
DV		 4202 goto found;
4203 }
4204
bcddf610
S		 4205 if (IS_BROXTON(dev_priv->dev)) {
4206 /* PLL is attached to port in bxt */
4207 struct intel_encoder *encoder;
4208 struct intel_digital_port *intel_dig_port;
4209
4210 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4211 if (WARN_ON(!encoder))
4212 return NULL;
4213
4214 intel_dig_port = enc_to_dig_port(&encoder->base);
4215 /* 1:1 mapping between ports and PLLs */
4216 i = (enum intel_dpll_id)intel_dig_port->port;
4217 pll = &dev_priv->shared_dplls[i];
4218 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4219 crtc->base.base.id, pll->name);
de419ab6 4220 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4221
4222 goto found;
4223 }
4224
e72f9fbf
DV		 4225 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4226 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4227
4228 /* Only want to check enabled timings first */
de419ab6 4229 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4230 continue;
4231
190f68c5 4232 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4233 &shared_dpll[i].hw_state,
4234 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4235 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4236 crtc->base.base.id, pll->name,
de419ab6 4237 shared_dpll[i].crtc_mask,
8bd31e67 4238 pll->active);
ee7b9f93
JB		 4239 goto found;
4240 }
4241 }
4242
4243 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4244 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4245 pll = &dev_priv->shared_dplls[i];
de419ab6 4246 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4247 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4248 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4249 goto found;
4250 }
4251 }
4252
4253 return NULL;
4254
4255found:
de419ab6
ML		 4256 if (shared_dpll[i].crtc_mask == 0)
4257 shared_dpll[i].hw_state =
4258 crtc_state->dpll_hw_state;
f2a69f44 4259
190f68c5 4260 crtc_state->shared_dpll = i;
46edb027
DV		 4261 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4262 pipe_name(crtc->pipe));
ee7b9f93 4263
de419ab6 4264 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4265
ee7b9f93
JB		 4266 return pll;
4267}
4268
de419ab6 4269static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4270{
de419ab6
ML		 4271 struct drm_i915_private *dev_priv = to_i915(state->dev);
4272 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4273 struct intel_shared_dpll *pll;
4274 enum intel_dpll_id i;
4275
de419ab6
ML		 4276 if (!to_intel_atomic_state(state)->dpll_set)
4277 return;
8bd31e67 4278
de419ab6 4279 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4280 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4281 pll = &dev_priv->shared_dplls[i];
de419ab6 4282 pll->config = shared_dpll[i];
8bd31e67
ACO		 4283 }
4284}
4285
a1520318 4286static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4287{
4288 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4289 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4290 u32 temp;
4291
4292 temp = I915_READ(dslreg);
4293 udelay(500);
4294 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4295 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4296 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4297 }
4298}
4299
86adf9d7
ML		 4300static int
4301skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4302 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4303 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4304{
86adf9d7
ML		 4305 struct intel_crtc_scaler_state *scaler_state =
4306 &crtc_state->scaler_state;
4307 struct intel_crtc *intel_crtc =
4308 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4309 int need_scaling;
6156a456
CK		 4310
4311 need_scaling = intel_rotation_90_or_270(rotation) ?
4312 (src_h != dst_w || src_w != dst_h):
4313 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4314
4315 /*
4316 * if plane is being disabled or scaler is no more required or force detach
4317 * - free scaler binded to this plane/crtc
4318 * - in order to do this, update crtc->scaler_usage
4319 *
4320 * Here scaler state in crtc_state is set free so that
4321 * scaler can be assigned to other user. Actual register
4322 * update to free the scaler is done in plane/panel-fit programming.
4323 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4324 */
86adf9d7 4325 if (force_detach || !need_scaling) {
a1b2278e 4326 if (*scaler_id >= 0) {
86adf9d7 4327 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4328 scaler_state->scalers[*scaler_id].in_use = 0;
4329
86adf9d7
ML		 4330 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4331 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4332 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4333 scaler_state->scaler_users);
4334 *scaler_id = -1;
4335 }
4336 return 0;
4337 }
4338
4339 /* range checks */
4340 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4341 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4342
4343 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4344 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4345 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4346 "size is out of scaler range\n",
86adf9d7 4347 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4348 return -EINVAL;
4349 }
4350
86adf9d7
ML		 4351 /* mark this plane as a scaler user in crtc_state */
4352 scaler_state->scaler_users |= (1 << scaler_user);
4353 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4354 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4355 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4356 scaler_state->scaler_users);
4357
4358 return 0;
4359}
4360
4361/**
4362 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4363 *
4364 * @state: crtc's scaler state
4365 * @force_detach: whether to forcibly disable scaler
4366 *
4367 * Return
4368 * 0 - scaler_usage updated successfully
4369 * error - requested scaling cannot be supported or other error condition
4370 */
4371int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4372{
4373 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4374 struct drm_display_mode *adjusted_mode =
4375 &state->base.adjusted_mode;
4376
4377 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4378 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4379
4380 return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4381 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4382 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4383 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4384}
4385
4386/**
4387 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4388 *
4389 * @state: crtc's scaler state
86adf9d7
ML		 4390 * @plane_state: atomic plane state to update
4391 *
4392 * Return
4393 * 0 - scaler_usage updated successfully
4394 * error - requested scaling cannot be supported or other error condition
4395 */
da20eabd
ML		 4396static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4397 struct intel_plane_state *plane_state)
86adf9d7
ML		 4398{
4399
4400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4401 struct intel_plane *intel_plane =
4402 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4403 struct drm_framebuffer *fb = plane_state->base.fb;
4404 int ret;
4405
4406 bool force_detach = !fb || !plane_state->visible;
4407
4408 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4409 intel_plane->base.base.id, intel_crtc->pipe,
4410 drm_plane_index(&intel_plane->base));
4411
4412 ret = skl_update_scaler(crtc_state, force_detach,
4413 drm_plane_index(&intel_plane->base),
4414 &plane_state->scaler_id,
4415 plane_state->base.rotation,
4416 drm_rect_width(&plane_state->src) >> 16,
4417 drm_rect_height(&plane_state->src) >> 16,
4418 drm_rect_width(&plane_state->dst),
4419 drm_rect_height(&plane_state->dst));
4420
4421 if (ret || plane_state->scaler_id < 0)
4422 return ret;
4423
a1b2278e 4424 /* check colorkey */
818ed961 4425 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4426 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4427 intel_plane->base.base.id);
a1b2278e
CK		 4428 return -EINVAL;
4429 }
4430
4431 /* Check src format */
86adf9d7
ML		 4432 switch (fb->pixel_format) {
4433 case DRM_FORMAT_RGB565:
4434 case DRM_FORMAT_XBGR8888:
4435 case DRM_FORMAT_XRGB8888:
4436 case DRM_FORMAT_ABGR8888:
4437 case DRM_FORMAT_ARGB8888:
4438 case DRM_FORMAT_XRGB2101010:
4439 case DRM_FORMAT_XBGR2101010:
4440 case DRM_FORMAT_YUYV:
4441 case DRM_FORMAT_YVYU:
4442 case DRM_FORMAT_UYVY:
4443 case DRM_FORMAT_VYUY:
4444 break;
4445 default:
4446 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4447 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4448 return -EINVAL;
a1b2278e
CK		 4449 }
4450
a1b2278e
CK		 4451 return 0;
4452}
4453
4454static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4455{
4456 struct drm_device *dev = crtc->base.dev;
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458 int pipe = crtc->pipe;
a1b2278e
CK		 4459 struct intel_crtc_scaler_state *scaler_state =
4460 &crtc->config->scaler_state;
4461
4462 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4463
4464 /* To update pfit, first update scaler state */
86adf9d7 4465 skl_update_scaler_crtc(crtc->config, !enable);
a1b2278e
CK		 4466 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4467 skl_detach_scalers(crtc);
4468 if (!enable)
4469 return;
bd2e244f 4470
6e3c9717 4471 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4472 int id;
4473
4474 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4475 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4476 return;
4477 }
4478
4479 id = scaler_state->scaler_id;
4480 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4481 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4482 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4483 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4484
4485 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4486 }
4487}
4488
b074cec8
JB		 4489static void ironlake_pfit_enable(struct intel_crtc *crtc)
4490{
4491 struct drm_device *dev = crtc->base.dev;
4492 struct drm_i915_private *dev_priv = dev->dev_private;
4493 int pipe = crtc->pipe;
4494
6e3c9717 4495 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4496 /* Force use of hard-coded filter coefficients
4497 * as some pre-programmed values are broken,
4498 * e.g. x201.
4499 */
4500 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4501 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4502 PF_PIPE_SEL_IVB(pipe));
4503 else
4504 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4505 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4506 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4507 }
4508}
4509
20bc8673 4510void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4511{
cea165c3
VS		 4512 struct drm_device *dev = crtc->base.dev;
4513 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4514
6e3c9717 4515 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4516 return;
4517
cea165c3
VS		 4518 /* We can only enable IPS after we enable a plane and wait for a vblank */
4519 intel_wait_for_vblank(dev, crtc->pipe);
4520
d77e4531 4521 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4522 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4523 mutex_lock(&dev_priv->rps.hw_lock);
4524 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4525 mutex_unlock(&dev_priv->rps.hw_lock);
4526 /* Quoting Art Runyan: "its not safe to expect any particular
4527 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4528 * mailbox." Moreover, the mailbox may return a bogus state,
4529 * so we need to just enable it and continue on.
2a114cc1
BW		 4530 */
4531 } else {
4532 I915_WRITE(IPS_CTL, IPS_ENABLE);
4533 /* The bit only becomes 1 in the next vblank, so this wait here
4534 * is essentially intel_wait_for_vblank. If we don't have this
4535 * and don't wait for vblanks until the end of crtc_enable, then
4536 * the HW state readout code will complain that the expected
4537 * IPS_CTL value is not the one we read. */
4538 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4539 DRM_ERROR("Timed out waiting for IPS enable\n");
4540 }
d77e4531
PZ		 4541}
4542
20bc8673 4543void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4544{
4545 struct drm_device *dev = crtc->base.dev;
4546 struct drm_i915_private *dev_priv = dev->dev_private;
4547
6e3c9717 4548 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4549 return;
4550
4551 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4552 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4553 mutex_lock(&dev_priv->rps.hw_lock);
4554 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4555 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4556 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4557 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4558 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4559 } else {
2a114cc1 4560 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4561 POSTING_READ(IPS_CTL);
4562 }
d77e4531
PZ		 4563
4564 /* We need to wait for a vblank before we can disable the plane. */
4565 intel_wait_for_vblank(dev, crtc->pipe);
4566}
4567
4568/** Loads the palette/gamma unit for the CRTC with the prepared values */
4569static void intel_crtc_load_lut(struct drm_crtc *crtc)
4570{
4571 struct drm_device *dev = crtc->dev;
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4574 enum pipe pipe = intel_crtc->pipe;
4575 int palreg = PALETTE(pipe);
4576 int i;
4577 bool reenable_ips = false;
4578
4579 /* The clocks have to be on to load the palette. */
53d9f4e9 4580 if (!crtc->state->active)
d77e4531
PZ		 4581 return;
4582
50360403 4583 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4584 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4585 assert_dsi_pll_enabled(dev_priv);
4586 else
4587 assert_pll_enabled(dev_priv, pipe);
4588 }
4589
4590 /* use legacy palette for Ironlake */
7a1db49a 4591 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4592 palreg = LGC_PALETTE(pipe);
4593
4594 /* Workaround : Do not read or write the pipe palette/gamma data while
4595 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4596 */
6e3c9717 4597 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4598 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4599 GAMMA_MODE_MODE_SPLIT)) {
4600 hsw_disable_ips(intel_crtc);
4601 reenable_ips = true;
4602 }
4603
4604 for (i = 0; i < 256; i++) {
4605 I915_WRITE(palreg + 4 * i,
4606 (intel_crtc->lut_r[i] << 16) |
4607 (intel_crtc->lut_g[i] << 8) |
4608 intel_crtc->lut_b[i]);
4609 }
4610
4611 if (reenable_ips)
4612 hsw_enable_ips(intel_crtc);
4613}
4614
7cac945f 4615static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4616{
7cac945f 4617 if (intel_crtc->overlay) {
d3eedb1a
VS		 4618 struct drm_device *dev = intel_crtc->base.dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620
4621 mutex_lock(&dev->struct_mutex);
4622 dev_priv->mm.interruptible = false;
4623 (void) intel_overlay_switch_off(intel_crtc->overlay);
4624 dev_priv->mm.interruptible = true;
4625 mutex_unlock(&dev->struct_mutex);
4626 }
4627
4628 /* Let userspace switch the overlay on again. In most cases userspace
4629 * has to recompute where to put it anyway.
4630 */
4631}
4632
87d4300a
ML		 4633/**
4634 * intel_post_enable_primary - Perform operations after enabling primary plane
4635 * @crtc: the CRTC whose primary plane was just enabled
4636 *
4637 * Performs potentially sleeping operations that must be done after the primary
4638 * plane is enabled, such as updating FBC and IPS. Note that this may be
4639 * called due to an explicit primary plane update, or due to an implicit
4640 * re-enable that is caused when a sprite plane is updated to no longer
4641 * completely hide the primary plane.
4642 */
4643static void
4644intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4645{
4646 struct drm_device *dev = crtc->dev;
87d4300a 4647 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649 int pipe = intel_crtc->pipe;
a5c4d7bc 4650
87d4300a
ML		 4651 /*
4652 * BDW signals flip done immediately if the plane
4653 * is disabled, even if the plane enable is already
4654 * armed to occur at the next vblank :(
4655 */
4656 if (IS_BROADWELL(dev))
4657 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4658
87d4300a
ML		 4659 /*
4660 * FIXME IPS should be fine as long as one plane is
4661 * enabled, but in practice it seems to have problems
4662 * when going from primary only to sprite only and vice
4663 * versa.
4664 */
a5c4d7bc
VS		 4665 hsw_enable_ips(intel_crtc);
4666
f99d7069 4667 /*
87d4300a
ML		 4668 * Gen2 reports pipe underruns whenever all planes are disabled.
4669 * So don't enable underrun reporting before at least some planes
4670 * are enabled.
4671 * FIXME: Need to fix the logic to work when we turn off all planes
4672 * but leave the pipe running.
f99d7069 4673 */
87d4300a
ML		 4674 if (IS_GEN2(dev))
4675 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4676
4677 /* Underruns don't raise interrupts, so check manually. */
4678 if (HAS_GMCH_DISPLAY(dev))
4679 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4680}
4681
87d4300a
ML		 4682/**
4683 * intel_pre_disable_primary - Perform operations before disabling primary plane
4684 * @crtc: the CRTC whose primary plane is to be disabled
4685 *
4686 * Performs potentially sleeping operations that must be done before the
4687 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4688 * be called due to an explicit primary plane update, or due to an implicit
4689 * disable that is caused when a sprite plane completely hides the primary
4690 * plane.
4691 */
4692static void
4693intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4694{
4695 struct drm_device *dev = crtc->dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698 int pipe = intel_crtc->pipe;
a5c4d7bc 4699
87d4300a
ML		 4700 /*
4701 * Gen2 reports pipe underruns whenever all planes are disabled.
4702 * So diasble underrun reporting before all the planes get disabled.
4703 * FIXME: Need to fix the logic to work when we turn off all planes
4704 * but leave the pipe running.
4705 */
4706 if (IS_GEN2(dev))
4707 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4708
87d4300a
ML		 4709 /*
4710 * Vblank time updates from the shadow to live plane control register
4711 * are blocked if the memory self-refresh mode is active at that
4712 * moment. So to make sure the plane gets truly disabled, disable
4713 * first the self-refresh mode. The self-refresh enable bit in turn
4714 * will be checked/applied by the HW only at the next frame start
4715 * event which is after the vblank start event, so we need to have a
4716 * wait-for-vblank between disabling the plane and the pipe.
4717 */
262cd2e1 4718 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4719 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4720 dev_priv->wm.vlv.cxsr = false;
4721 intel_wait_for_vblank(dev, pipe);
4722 }
87d4300a 4723
87d4300a
ML		 4724 /*
4725 * FIXME IPS should be fine as long as one plane is
4726 * enabled, but in practice it seems to have problems
4727 * when going from primary only to sprite only and vice
4728 * versa.
4729 */
a5c4d7bc 4730 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4731}
4732
ac21b225
ML		 4733static void intel_post_plane_update(struct intel_crtc *crtc)
4734{
4735 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4736 struct drm_device *dev = crtc->base.dev;
4737 struct drm_plane *plane;
4738
4739 if (atomic->wait_vblank)
4740 intel_wait_for_vblank(dev, crtc->pipe);
4741
4742 intel_frontbuffer_flip(dev, atomic->fb_bits);
4743
852eb00d
VS		 4744 if (atomic->disable_cxsr)
4745 crtc->wm.cxsr_allowed = true;
4746
f015c551
VS		 4747 if (crtc->atomic.update_wm_post)
4748 intel_update_watermarks(&crtc->base);
4749
ac21b225
ML		 4750 if (atomic->update_fbc) {
4751 mutex_lock(&dev->struct_mutex);
4752 intel_fbc_update(dev);
4753 mutex_unlock(&dev->struct_mutex);
4754 }
4755
4756 if (atomic->post_enable_primary)
4757 intel_post_enable_primary(&crtc->base);
4758
4759 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4760 intel_update_sprite_watermarks(plane, &crtc->base,
4761 0, 0, 0, false, false);
4762
4763 memset(atomic, 0, sizeof(*atomic));
4764}
4765
4766static void intel_pre_plane_update(struct intel_crtc *crtc)
4767{
4768 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4769 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4770 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4771 struct drm_plane *p;
4772
4773 /* Track fb's for any planes being disabled */
ac21b225
ML		 4774 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4775 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4776
4777 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4778 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4779 plane->frontbuffer_bit);
ac21b225
ML		 4780 mutex_unlock(&dev->struct_mutex);
4781 }
4782
4783 if (atomic->wait_for_flips)
4784 intel_crtc_wait_for_pending_flips(&crtc->base);
4785
25ad93fd 4786 if (atomic->disable_fbc) {
eddfcbcd 4787 mutex_lock(&dev->struct_mutex);
25ad93fd 4788 intel_fbc_disable_crtc(crtc);
eddfcbcd
ML		 4789 mutex_unlock(&dev->struct_mutex);
4790 }
ac21b225 4791
066cf55b
RV		 4792 if (crtc->atomic.disable_ips)
4793 hsw_disable_ips(crtc);
4794
ac21b225
ML		 4795 if (atomic->pre_disable_primary)
4796 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4797
4798 if (atomic->disable_cxsr) {
4799 crtc->wm.cxsr_allowed = false;
4800 intel_set_memory_cxsr(dev_priv, false);
4801 }
ac21b225
ML		 4802}
4803
d032ffa0 4804static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4805{
4806 struct drm_device *dev = crtc->dev;
4807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4808 struct drm_plane *p;
87d4300a
ML		 4809 int pipe = intel_crtc->pipe;
4810
7cac945f 4811 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4812
d032ffa0
ML		 4813 drm_for_each_plane_mask(p, dev, plane_mask)
4814 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4815
f99d7069
DV		 4816 /*
4817 * FIXME: Once we grow proper nuclear flip support out of this we need
4818 * to compute the mask of flip planes precisely. For the time being
4819 * consider this a flip to a NULL plane.
4820 */
4821 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4822}
4823
f67a559d
JB		 4824static void ironlake_crtc_enable(struct drm_crtc *crtc)
4825{
4826 struct drm_device *dev = crtc->dev;
4827 struct drm_i915_private *dev_priv = dev->dev_private;
4828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4829 struct intel_encoder *encoder;
f67a559d 4830 int pipe = intel_crtc->pipe;
f67a559d 4831
53d9f4e9 4832 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4833 return;
4834
6e3c9717 4835 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4836 intel_prepare_shared_dpll(intel_crtc);
4837
6e3c9717 4838 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4839 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4840
4841 intel_set_pipe_timings(intel_crtc);
4842
6e3c9717 4843 if (intel_crtc->config->has_pch_encoder) {
29407aab 4844 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4845 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4846 }
4847
4848 ironlake_set_pipeconf(crtc);
4849
f67a559d 4850 intel_crtc->active = true;
8664281b 4851
a72e4c9f
DV		 4852 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4853 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4854
f6736a1a 4855 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4856 if (encoder->pre_enable)
4857 encoder->pre_enable(encoder);
f67a559d 4858
6e3c9717 4859 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4860 /* Note: FDI PLL enabling _must_ be done before we enable the
4861 * cpu pipes, hence this is separate from all the other fdi/pch
4862 * enabling. */
88cefb6c 4863 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4864 } else {
4865 assert_fdi_tx_disabled(dev_priv, pipe);
4866 assert_fdi_rx_disabled(dev_priv, pipe);
4867 }
f67a559d 4868
b074cec8 4869 ironlake_pfit_enable(intel_crtc);
f67a559d 4870
9c54c0dd
JB		 4871 /*
4872 * On ILK+ LUT must be loaded before the pipe is running but with
4873 * clocks enabled
4874 */
4875 intel_crtc_load_lut(crtc);
4876
f37fcc2a 4877 intel_update_watermarks(crtc);
e1fdc473 4878 intel_enable_pipe(intel_crtc);
f67a559d 4879
6e3c9717 4880 if (intel_crtc->config->has_pch_encoder)
f67a559d 4881 ironlake_pch_enable(crtc);
c98e9dcf 4882
f9b61ff6
DV		 4883 assert_vblank_disabled(crtc);
4884 drm_crtc_vblank_on(crtc);
4885
fa5c73b1
DV		 4886 for_each_encoder_on_crtc(dev, crtc, encoder)
4887 encoder->enable(encoder);
61b77ddd
DV		 4888
4889 if (HAS_PCH_CPT(dev))
a1520318 4890 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4891}
4892
42db64ef
PZ		 4893/* IPS only exists on ULT machines and is tied to pipe A. */
4894static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4895{
f5adf94e 4896 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4897}
4898
4f771f10
PZ		 4899static void haswell_crtc_enable(struct drm_crtc *crtc)
4900{
4901 struct drm_device *dev = crtc->dev;
4902 struct drm_i915_private *dev_priv = dev->dev_private;
4903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4904 struct intel_encoder *encoder;
99d736a2
ML		 4905 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4906 struct intel_crtc_state *pipe_config =
4907 to_intel_crtc_state(crtc->state);
4f771f10 4908
53d9f4e9 4909 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4910 return;
4911
df8ad70c
DV		 4912 if (intel_crtc_to_shared_dpll(intel_crtc))
4913 intel_enable_shared_dpll(intel_crtc);
4914
6e3c9717 4915 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4916 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4917
4918 intel_set_pipe_timings(intel_crtc);
4919
6e3c9717
ACO		 4920 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4921 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4922 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4923 }
4924
6e3c9717 4925 if (intel_crtc->config->has_pch_encoder) {
229fca97 4926 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4927 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4928 }
4929
4930 haswell_set_pipeconf(crtc);
4931
4932 intel_set_pipe_csc(crtc);
4933
4f771f10 4934 intel_crtc->active = true;
8664281b 4935
a72e4c9f 4936 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4937 for_each_encoder_on_crtc(dev, crtc, encoder)
4938 if (encoder->pre_enable)
4939 encoder->pre_enable(encoder);
4940
6e3c9717 4941 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4942 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4943 true);
4fe9467d
ID		 4944 dev_priv->display.fdi_link_train(crtc);
4945 }
4946
1f544388 4947 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4948
ff6d9f55 4949 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4950 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4951 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4952 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4953 else
4954 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4955
4956 /*
4957 * On ILK+ LUT must be loaded before the pipe is running but with
4958 * clocks enabled
4959 */
4960 intel_crtc_load_lut(crtc);
4961
1f544388 4962 intel_ddi_set_pipe_settings(crtc);
8228c251 4963 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4964
f37fcc2a 4965 intel_update_watermarks(crtc);
e1fdc473 4966 intel_enable_pipe(intel_crtc);
42db64ef 4967
6e3c9717 4968 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4969 lpt_pch_enable(crtc);
4f771f10 4970
6e3c9717 4971 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4972 intel_ddi_set_vc_payload_alloc(crtc, true);
4973
f9b61ff6
DV		 4974 assert_vblank_disabled(crtc);
4975 drm_crtc_vblank_on(crtc);
4976
8807e55b 4977 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4978 encoder->enable(encoder);
8807e55b
JN		 4979 intel_opregion_notify_encoder(encoder, true);
4980 }
4f771f10 4981
e4916946
PZ		 4982 /* If we change the relative order between pipe/planes enabling, we need
4983 * to change the workaround. */
99d736a2
ML		 4984 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4985 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4986 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4987 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4988 }
4f771f10
PZ		 4989}
4990
3f8dce3a
DV		 4991static void ironlake_pfit_disable(struct intel_crtc *crtc)
4992{
4993 struct drm_device *dev = crtc->base.dev;
4994 struct drm_i915_private *dev_priv = dev->dev_private;
4995 int pipe = crtc->pipe;
4996
4997 /* To avoid upsetting the power well on haswell only disable the pfit if
4998 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4999 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5000 I915_WRITE(PF_CTL(pipe), 0);
5001 I915_WRITE(PF_WIN_POS(pipe), 0);
5002 I915_WRITE(PF_WIN_SZ(pipe), 0);
5003 }
5004}
5005
6be4a607
JB		 5006static void ironlake_crtc_disable(struct drm_crtc *crtc)
5007{
5008 struct drm_device *dev = crtc->dev;
5009 struct drm_i915_private *dev_priv = dev->dev_private;
5010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5011 struct intel_encoder *encoder;
6be4a607 5012 int pipe = intel_crtc->pipe;
5eddb70b 5013 u32 reg, temp;
b52eb4dc 5014
ea9d758d
DV		 5015 for_each_encoder_on_crtc(dev, crtc, encoder)
5016 encoder->disable(encoder);
5017
f9b61ff6
DV		 5018 drm_crtc_vblank_off(crtc);
5019 assert_vblank_disabled(crtc);
5020
6e3c9717 5021 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5022 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5023
575f7ab7 5024 intel_disable_pipe(intel_crtc);
32f9d658 5025
3f8dce3a 5026 ironlake_pfit_disable(intel_crtc);
2c07245f 5027
5a74f70a
VS		 5028 if (intel_crtc->config->has_pch_encoder)
5029 ironlake_fdi_disable(crtc);
5030
bf49ec8c
DV		 5031 for_each_encoder_on_crtc(dev, crtc, encoder)
5032 if (encoder->post_disable)
5033 encoder->post_disable(encoder);
2c07245f 5034
6e3c9717 5035 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5036 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5037
d925c59a
DV		 5038 if (HAS_PCH_CPT(dev)) {
5039 /* disable TRANS_DP_CTL */
5040 reg = TRANS_DP_CTL(pipe);
5041 temp = I915_READ(reg);
5042 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5043 TRANS_DP_PORT_SEL_MASK);
5044 temp |= TRANS_DP_PORT_SEL_NONE;
5045 I915_WRITE(reg, temp);
5046
5047 /* disable DPLL_SEL */
5048 temp = I915_READ(PCH_DPLL_SEL);
11887397 5049 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5050 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5051 }
e3421a18 5052
d925c59a
DV		 5053 ironlake_fdi_pll_disable(intel_crtc);
5054 }
6be4a607 5055}
1b3c7a47 5056
4f771f10 5057static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5058{
4f771f10
PZ		 5059 struct drm_device *dev = crtc->dev;
5060 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5062 struct intel_encoder *encoder;
6e3c9717 5063 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5064
8807e55b
JN		 5065 for_each_encoder_on_crtc(dev, crtc, encoder) {
5066 intel_opregion_notify_encoder(encoder, false);
4f771f10 5067 encoder->disable(encoder);
8807e55b 5068 }
4f771f10 5069
f9b61ff6
DV		 5070 drm_crtc_vblank_off(crtc);
5071 assert_vblank_disabled(crtc);
5072
6e3c9717 5073 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5074 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5075 false);
575f7ab7 5076 intel_disable_pipe(intel_crtc);
4f771f10 5077
6e3c9717 5078 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5079 intel_ddi_set_vc_payload_alloc(crtc, false);
5080
ad80a810 5081 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5082
ff6d9f55 5083 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5084 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5085 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5086 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5087 else
5088 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5089
1f544388 5090 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5091
6e3c9717 5092 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5093 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5094 intel_ddi_fdi_disable(crtc);
83616634 5095 }
4f771f10 5096
97b040aa
ID		 5097 for_each_encoder_on_crtc(dev, crtc, encoder)
5098 if (encoder->post_disable)
5099 encoder->post_disable(encoder);
4f771f10
PZ		 5100}
5101
2dd24552
JB		 5102static void i9xx_pfit_enable(struct intel_crtc *crtc)
5103{
5104 struct drm_device *dev = crtc->base.dev;
5105 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5106 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5107
681a8504 5108 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5109 return;
5110
2dd24552 5111 /*
c0b03411
DV		 5112 * The panel fitter should only be adjusted whilst the pipe is disabled,
5113 * according to register description and PRM.
2dd24552 5114 */
c0b03411
DV		 5115 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5116 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5117
b074cec8
JB		 5118 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5119 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5120
5121 /* Border color in case we don't scale up to the full screen. Black by
5122 * default, change to something else for debugging. */
5123 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5124}
5125
d05410f9
DA		 5126static enum intel_display_power_domain port_to_power_domain(enum port port)
5127{
5128 switch (port) {
5129 case PORT_A:
5130 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5131 case PORT_B:
5132 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5133 case PORT_C:
5134 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5135 case PORT_D:
5136 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5137 default:
5138 WARN_ON_ONCE(1);
5139 return POWER_DOMAIN_PORT_OTHER;
5140 }
5141}
5142
77d22dca
ID		 5143#define for_each_power_domain(domain, mask) \
5144 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5145 if ((1 << (domain)) & (mask))
5146
319be8ae
ID		 5147enum intel_display_power_domain
5148intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5149{
5150 struct drm_device *dev = intel_encoder->base.dev;
5151 struct intel_digital_port *intel_dig_port;
5152
5153 switch (intel_encoder->type) {
5154 case INTEL_OUTPUT_UNKNOWN:
5155 /* Only DDI platforms should ever use this output type */
5156 WARN_ON_ONCE(!HAS_DDI(dev));
5157 case INTEL_OUTPUT_DISPLAYPORT:
5158 case INTEL_OUTPUT_HDMI:
5159 case INTEL_OUTPUT_EDP:
5160 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5161 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5162 case INTEL_OUTPUT_DP_MST:
5163 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5164 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5165 case INTEL_OUTPUT_ANALOG:
5166 return POWER_DOMAIN_PORT_CRT;
5167 case INTEL_OUTPUT_DSI:
5168 return POWER_DOMAIN_PORT_DSI;
5169 default:
5170 return POWER_DOMAIN_PORT_OTHER;
5171 }
5172}
5173
5174static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5175{
319be8ae
ID		 5176 struct drm_device *dev = crtc->dev;
5177 struct intel_encoder *intel_encoder;
5178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5179 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5180 unsigned long mask;
5181 enum transcoder transcoder;
5182
5183 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5184
5185 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5186 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5187 if (intel_crtc->config->pch_pfit.enabled ||
5188 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5189 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5190
319be8ae
ID		 5191 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5192 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5193
77d22dca
ID		 5194 return mask;
5195}
5196
679dacd4 5197static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5198{
679dacd4 5199 struct drm_device *dev = state->dev;
77d22dca
ID		 5200 struct drm_i915_private *dev_priv = dev->dev_private;
5201 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5202 struct intel_crtc *crtc;
5203
5204 /*
5205 * First get all needed power domains, then put all unneeded, to avoid
5206 * any unnecessary toggling of the power wells.
5207 */
d3fcc808 5208 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5209 enum intel_display_power_domain domain;
5210
83d65738 5211 if (!crtc->base.state->enable)
77d22dca
ID		 5212 continue;
5213
319be8ae 5214 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5215
5216 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5217 intel_display_power_get(dev_priv, domain);
5218 }
5219
27c329ed
ML		 5220 if (dev_priv->display.modeset_commit_cdclk) {
5221 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5222
5223 if (cdclk != dev_priv->cdclk_freq &&
5224 !WARN_ON(!state->allow_modeset))
5225 dev_priv->display.modeset_commit_cdclk(state);
5226 }
50f6e502 5227
d3fcc808 5228 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5229 enum intel_display_power_domain domain;
5230
5231 for_each_power_domain(domain, crtc->enabled_power_domains)
5232 intel_display_power_put(dev_priv, domain);
5233
5234 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5235 }
5236
5237 intel_display_set_init_power(dev_priv, false);
5238}
5239
560a7ae4
DL		 5240static void intel_update_max_cdclk(struct drm_device *dev)
5241{
5242 struct drm_i915_private *dev_priv = dev->dev_private;
5243
5244 if (IS_SKYLAKE(dev)) {
5245 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5246
5247 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5248 dev_priv->max_cdclk_freq = 675000;
5249 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5250 dev_priv->max_cdclk_freq = 540000;
5251 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5252 dev_priv->max_cdclk_freq = 450000;
5253 else
5254 dev_priv->max_cdclk_freq = 337500;
5255 } else if (IS_BROADWELL(dev)) {
5256 /*
5257 * FIXME with extra cooling we can allow
5258 * 540 MHz for ULX and 675 Mhz for ULT.
5259 * How can we know if extra cooling is
5260 * available? PCI ID, VTB, something else?
5261 */
5262 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5263 dev_priv->max_cdclk_freq = 450000;
5264 else if (IS_BDW_ULX(dev))
5265 dev_priv->max_cdclk_freq = 450000;
5266 else if (IS_BDW_ULT(dev))
5267 dev_priv->max_cdclk_freq = 540000;
5268 else
5269 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5270 } else if (IS_CHERRYVIEW(dev)) {
5271 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5272 } else if (IS_VALLEYVIEW(dev)) {
5273 dev_priv->max_cdclk_freq = 400000;
5274 } else {
5275 /* otherwise assume cdclk is fixed */
5276 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5277 }
5278
5279 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5280 dev_priv->max_cdclk_freq);
5281}
5282
5283static void intel_update_cdclk(struct drm_device *dev)
5284{
5285 struct drm_i915_private *dev_priv = dev->dev_private;
5286
5287 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5288 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5289 dev_priv->cdclk_freq);
5290
5291 /*
5292 * Program the gmbus_freq based on the cdclk frequency.
5293 * BSpec erroneously claims we should aim for 4MHz, but
5294 * in fact 1MHz is the correct frequency.
5295 */
5296 if (IS_VALLEYVIEW(dev)) {
5297 /*
5298 * Program the gmbus_freq based on the cdclk frequency.
5299 * BSpec erroneously claims we should aim for 4MHz, but
5300 * in fact 1MHz is the correct frequency.
5301 */
5302 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5303 }
5304
5305 if (dev_priv->max_cdclk_freq == 0)
5306 intel_update_max_cdclk(dev);
5307}
5308
70d0c574 5309static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5310{
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312 uint32_t divider;
5313 uint32_t ratio;
5314 uint32_t current_freq;
5315 int ret;
5316
5317 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5318 switch (frequency) {
5319 case 144000:
5320 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5321 ratio = BXT_DE_PLL_RATIO(60);
5322 break;
5323 case 288000:
5324 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5325 ratio = BXT_DE_PLL_RATIO(60);
5326 break;
5327 case 384000:
5328 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5329 ratio = BXT_DE_PLL_RATIO(60);
5330 break;
5331 case 576000:
5332 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5333 ratio = BXT_DE_PLL_RATIO(60);
5334 break;
5335 case 624000:
5336 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5337 ratio = BXT_DE_PLL_RATIO(65);
5338 break;
5339 case 19200:
5340 /*
5341 * Bypass frequency with DE PLL disabled. Init ratio, divider
5342 * to suppress GCC warning.
5343 */
5344 ratio = 0;
5345 divider = 0;
5346 break;
5347 default:
5348 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5349
5350 return;
5351 }
5352
5353 mutex_lock(&dev_priv->rps.hw_lock);
5354 /* Inform power controller of upcoming frequency change */
5355 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5356 0x80000000);
5357 mutex_unlock(&dev_priv->rps.hw_lock);
5358
5359 if (ret) {
5360 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5361 ret, frequency);
5362 return;
5363 }
5364
5365 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5366 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5367 current_freq = current_freq * 500 + 1000;
5368
5369 /*
5370 * DE PLL has to be disabled when
5371 * - setting to 19.2MHz (bypass, PLL isn't used)
5372 * - before setting to 624MHz (PLL needs toggling)
5373 * - before setting to any frequency from 624MHz (PLL needs toggling)
5374 */
5375 if (frequency == 19200 || frequency == 624000 ||
5376 current_freq == 624000) {
5377 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5378 /* Timeout 200us */
5379 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5380 1))
5381 DRM_ERROR("timout waiting for DE PLL unlock\n");
5382 }
5383
5384 if (frequency != 19200) {
5385 uint32_t val;
5386
5387 val = I915_READ(BXT_DE_PLL_CTL);
5388 val &= ~BXT_DE_PLL_RATIO_MASK;
5389 val |= ratio;
5390 I915_WRITE(BXT_DE_PLL_CTL, val);
5391
5392 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5393 /* Timeout 200us */
5394 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5395 DRM_ERROR("timeout waiting for DE PLL lock\n");
5396
5397 val = I915_READ(CDCLK_CTL);
5398 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5399 val |= divider;
5400 /*
5401 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5402 * enable otherwise.
5403 */
5404 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5405 if (frequency >= 500000)
5406 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5407
5408 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5409 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5410 val |= (frequency - 1000) / 500;
5411 I915_WRITE(CDCLK_CTL, val);
5412 }
5413
5414 mutex_lock(&dev_priv->rps.hw_lock);
5415 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5416 DIV_ROUND_UP(frequency, 25000));
5417 mutex_unlock(&dev_priv->rps.hw_lock);
5418
5419 if (ret) {
5420 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5421 ret, frequency);
5422 return;
5423 }
5424
a47871bd 5425 intel_update_cdclk(dev);
f8437dd1
VK		 5426}
5427
5428void broxton_init_cdclk(struct drm_device *dev)
5429{
5430 struct drm_i915_private *dev_priv = dev->dev_private;
5431 uint32_t val;
5432
5433 /*
5434 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5435 * or else the reset will hang because there is no PCH to respond.
5436 * Move the handshake programming to initialization sequence.
5437 * Previously was left up to BIOS.
5438 */
5439 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5440 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5441 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5442
5443 /* Enable PG1 for cdclk */
5444 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5445
5446 /* check if cd clock is enabled */
5447 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5448 DRM_DEBUG_KMS("Display already initialized\n");
5449 return;
5450 }
5451
5452 /*
5453 * FIXME:
5454 * - The initial CDCLK needs to be read from VBT.
5455 * Need to make this change after VBT has changes for BXT.
5456 * - check if setting the max (or any) cdclk freq is really necessary
5457 * here, it belongs to modeset time
5458 */
5459 broxton_set_cdclk(dev, 624000);
5460
5461 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5462 POSTING_READ(DBUF_CTL);
5463
f8437dd1
VK		 5464 udelay(10);
5465
5466 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5467 DRM_ERROR("DBuf power enable timeout!\n");
5468}
5469
5470void broxton_uninit_cdclk(struct drm_device *dev)
5471{
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473
5474 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5475 POSTING_READ(DBUF_CTL);
5476
f8437dd1
VK		 5477 udelay(10);
5478
5479 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5480 DRM_ERROR("DBuf power disable timeout!\n");
5481
5482 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5483 broxton_set_cdclk(dev, 19200);
5484
5485 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5486}
5487
5d96d8af
DL		 5488static const struct skl_cdclk_entry {
5489 unsigned int freq;
5490 unsigned int vco;
5491} skl_cdclk_frequencies[] = {
5492 { .freq = 308570, .vco = 8640 },
5493 { .freq = 337500, .vco = 8100 },
5494 { .freq = 432000, .vco = 8640 },
5495 { .freq = 450000, .vco = 8100 },
5496 { .freq = 540000, .vco = 8100 },
5497 { .freq = 617140, .vco = 8640 },
5498 { .freq = 675000, .vco = 8100 },
5499};
5500
5501static unsigned int skl_cdclk_decimal(unsigned int freq)
5502{
5503 return (freq - 1000) / 500;
5504}
5505
5506static unsigned int skl_cdclk_get_vco(unsigned int freq)
5507{
5508 unsigned int i;
5509
5510 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5511 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5512
5513 if (e->freq == freq)
5514 return e->vco;
5515 }
5516
5517 return 8100;
5518}
5519
5520static void
5521skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5522{
5523 unsigned int min_freq;
5524 u32 val;
5525
5526 /* select the minimum CDCLK before enabling DPLL 0 */
5527 val = I915_READ(CDCLK_CTL);
5528 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5529 val |= CDCLK_FREQ_337_308;
5530
5531 if (required_vco == 8640)
5532 min_freq = 308570;
5533 else
5534 min_freq = 337500;
5535
5536 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5537
5538 I915_WRITE(CDCLK_CTL, val);
5539 POSTING_READ(CDCLK_CTL);
5540
5541 /*
5542 * We always enable DPLL0 with the lowest link rate possible, but still
5543 * taking into account the VCO required to operate the eDP panel at the
5544 * desired frequency. The usual DP link rates operate with a VCO of
5545 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5546 * The modeset code is responsible for the selection of the exact link
5547 * rate later on, with the constraint of choosing a frequency that
5548 * works with required_vco.
5549 */
5550 val = I915_READ(DPLL_CTRL1);
5551
5552 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5553 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5554 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5555 if (required_vco == 8640)
5556 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5557 SKL_DPLL0);
5558 else
5559 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5560 SKL_DPLL0);
5561
5562 I915_WRITE(DPLL_CTRL1, val);
5563 POSTING_READ(DPLL_CTRL1);
5564
5565 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5566
5567 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5568 DRM_ERROR("DPLL0 not locked\n");
5569}
5570
5571static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5572{
5573 int ret;
5574 u32 val;
5575
5576 /* inform PCU we want to change CDCLK */
5577 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5578 mutex_lock(&dev_priv->rps.hw_lock);
5579 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5580 mutex_unlock(&dev_priv->rps.hw_lock);
5581
5582 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5583}
5584
5585static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5586{
5587 unsigned int i;
5588
5589 for (i = 0; i < 15; i++) {
5590 if (skl_cdclk_pcu_ready(dev_priv))
5591 return true;
5592 udelay(10);
5593 }
5594
5595 return false;
5596}
5597
5598static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5599{
560a7ae4 5600 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5601 u32 freq_select, pcu_ack;
5602
5603 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5604
5605 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5606 DRM_ERROR("failed to inform PCU about cdclk change\n");
5607 return;
5608 }
5609
5610 /* set CDCLK_CTL */
5611 switch(freq) {
5612 case 450000:
5613 case 432000:
5614 freq_select = CDCLK_FREQ_450_432;
5615 pcu_ack = 1;
5616 break;
5617 case 540000:
5618 freq_select = CDCLK_FREQ_540;
5619 pcu_ack = 2;
5620 break;
5621 case 308570:
5622 case 337500:
5623 default:
5624 freq_select = CDCLK_FREQ_337_308;
5625 pcu_ack = 0;
5626 break;
5627 case 617140:
5628 case 675000:
5629 freq_select = CDCLK_FREQ_675_617;
5630 pcu_ack = 3;
5631 break;
5632 }
5633
5634 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5635 POSTING_READ(CDCLK_CTL);
5636
5637 /* inform PCU of the change */
5638 mutex_lock(&dev_priv->rps.hw_lock);
5639 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5640 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5641
5642 intel_update_cdclk(dev);
5d96d8af
DL		 5643}
5644
5645void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5646{
5647 /* disable DBUF power */
5648 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5649 POSTING_READ(DBUF_CTL);
5650
5651 udelay(10);
5652
5653 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5654 DRM_ERROR("DBuf power disable timeout\n");
5655
5656 /* disable DPLL0 */
5657 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5658 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5659 DRM_ERROR("Couldn't disable DPLL0\n");
5660
5661 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5662}
5663
5664void skl_init_cdclk(struct drm_i915_private *dev_priv)
5665{
5666 u32 val;
5667 unsigned int required_vco;
5668
5669 /* enable PCH reset handshake */
5670 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5671 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5672
5673 /* enable PG1 and Misc I/O */
5674 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5675
5676 /* DPLL0 already enabed !? */
5677 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5678 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5679 return;
5680 }
5681
5682 /* enable DPLL0 */
5683 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5684 skl_dpll0_enable(dev_priv, required_vco);
5685
5686 /* set CDCLK to the frequency the BIOS chose */
5687 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5688
5689 /* enable DBUF power */
5690 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5691 POSTING_READ(DBUF_CTL);
5692
5693 udelay(10);
5694
5695 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5696 DRM_ERROR("DBuf power enable timeout\n");
5697}
5698
dfcab17e 5699/* returns HPLL frequency in kHz */
f8bf63fd 5700static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5701{
586f49dc 5702 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5703
586f49dc 5704 /* Obtain SKU information */
a580516d 5705 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5706 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5707 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5708 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5709
dfcab17e 5710 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5711}
5712
5713/* Adjust CDclk dividers to allow high res or save power if possible */
5714static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5715{
5716 struct drm_i915_private *dev_priv = dev->dev_private;
5717 u32 val, cmd;
5718
164dfd28
VK		 5719 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5720 != dev_priv->cdclk_freq);
d60c4473 5721
dfcab17e 5722 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5723 cmd = 2;
dfcab17e 5724 else if (cdclk == 266667)
30a970c6
JB		 5725 cmd = 1;
5726 else
5727 cmd = 0;
5728
5729 mutex_lock(&dev_priv->rps.hw_lock);
5730 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5731 val &= ~DSPFREQGUAR_MASK;
5732 val |= (cmd << DSPFREQGUAR_SHIFT);
5733 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5734 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5735 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5736 50)) {
5737 DRM_ERROR("timed out waiting for CDclk change\n");
5738 }
5739 mutex_unlock(&dev_priv->rps.hw_lock);
5740
54433e91
VS		 5741 mutex_lock(&dev_priv->sb_lock);
5742
dfcab17e 5743 if (cdclk == 400000) {
6bcda4f0 5744 u32 divider;
30a970c6 5745
6bcda4f0 5746 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5747
30a970c6
JB		 5748 /* adjust cdclk divider */
5749 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5750 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5751 val |= divider;
5752 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5753
5754 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5755 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5756 50))
5757 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5758 }
5759
30a970c6
JB		 5760 /* adjust self-refresh exit latency value */
5761 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5762 val &= ~0x7f;
5763
5764 /*
5765 * For high bandwidth configs, we set a higher latency in the bunit
5766 * so that the core display fetch happens in time to avoid underruns.
5767 */
dfcab17e 5768 if (cdclk == 400000)
30a970c6
JB		 5769 val |= 4500 / 250; /* 4.5 usec */
5770 else
5771 val |= 3000 / 250; /* 3.0 usec */
5772 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5773
a580516d 5774 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5775
b6283055 5776 intel_update_cdclk(dev);
30a970c6
JB		 5777}
5778
383c5a6a
VS		 5779static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5780{
5781 struct drm_i915_private *dev_priv = dev->dev_private;
5782 u32 val, cmd;
5783
164dfd28
VK		 5784 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5785 != dev_priv->cdclk_freq);
383c5a6a
VS		 5786
5787 switch (cdclk) {
383c5a6a
VS		 5788 case 333333:
5789 case 320000:
383c5a6a 5790 case 266667:
383c5a6a 5791 case 200000:
383c5a6a
VS		 5792 break;
5793 default:
5f77eeb0 5794 MISSING_CASE(cdclk);
383c5a6a
VS		 5795 return;
5796 }
5797
9d0d3fda
VS		 5798 /*
5799 * Specs are full of misinformation, but testing on actual
5800 * hardware has shown that we just need to write the desired
5801 * CCK divider into the Punit register.
5802 */
5803 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5804
383c5a6a
VS		 5805 mutex_lock(&dev_priv->rps.hw_lock);
5806 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5807 val &= ~DSPFREQGUAR_MASK_CHV;
5808 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5809 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5810 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5811 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5812 50)) {
5813 DRM_ERROR("timed out waiting for CDclk change\n");
5814 }
5815 mutex_unlock(&dev_priv->rps.hw_lock);
5816
b6283055 5817 intel_update_cdclk(dev);
383c5a6a
VS		 5818}
5819
30a970c6
JB		 5820static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5821 int max_pixclk)
5822{
6bcda4f0 5823 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5824 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5825
30a970c6
JB		 5826 /*
5827 * Really only a few cases to deal with, as only 4 CDclks are supported:
5828 * 200MHz
5829 * 267MHz
29dc7ef3 5830 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5831 * 400MHz (VLV only)
5832 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5833 * of the lower bin and adjust if needed.
e37c67a1
VS		 5834 *
5835 * We seem to get an unstable or solid color picture at 200MHz.
5836 * Not sure what's wrong. For now use 200MHz only when all pipes
5837 * are off.
30a970c6 5838 */
6cca3195
VS		 5839 if (!IS_CHERRYVIEW(dev_priv) &&
5840 max_pixclk > freq_320*limit/100)
dfcab17e 5841 return 400000;
6cca3195 5842 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5843 return freq_320;
e37c67a1 5844 else if (max_pixclk > 0)
dfcab17e 5845 return 266667;
e37c67a1
VS		 5846 else
5847 return 200000;
30a970c6
JB		 5848}
5849
f8437dd1
VK		 5850static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5851 int max_pixclk)
5852{
5853 /*
5854 * FIXME:
5855 * - remove the guardband, it's not needed on BXT
5856 * - set 19.2MHz bypass frequency if there are no active pipes
5857 */
5858 if (max_pixclk > 576000*9/10)
5859 return 624000;
5860 else if (max_pixclk > 384000*9/10)
5861 return 576000;
5862 else if (max_pixclk > 288000*9/10)
5863 return 384000;
5864 else if (max_pixclk > 144000*9/10)
5865 return 288000;
5866 else
5867 return 144000;
5868}
5869
a821fc46
ACO		 5870/* Compute the max pixel clock for new configuration. Uses atomic state if
5871 * that's non-NULL, look at current state otherwise. */
5872static int intel_mode_max_pixclk(struct drm_device *dev,
5873 struct drm_atomic_state *state)
30a970c6 5874{
30a970c6 5875 struct intel_crtc *intel_crtc;
304603f4 5876 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5877 int max_pixclk = 0;
5878
d3fcc808 5879 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5880 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5881 if (IS_ERR(crtc_state))
5882 return PTR_ERR(crtc_state);
5883
5884 if (!crtc_state->base.enable)
5885 continue;
5886
5887 max_pixclk = max(max_pixclk,
5888 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5889 }
5890
5891 return max_pixclk;
5892}
5893
27c329ed 5894static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5895{
27c329ed
ML		 5896 struct drm_device *dev = state->dev;
5897 struct drm_i915_private *dev_priv = dev->dev_private;
5898 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5899
304603f4
ACO		 5900 if (max_pixclk < 0)
5901 return max_pixclk;
30a970c6 5902
27c329ed
ML		 5903 to_intel_atomic_state(state)->cdclk =
5904 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5905
27c329ed
ML		 5906 return 0;
5907}
304603f4 5908
27c329ed
ML		 5909static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5910{
5911 struct drm_device *dev = state->dev;
5912 struct drm_i915_private *dev_priv = dev->dev_private;
5913 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5914
27c329ed
ML		 5915 if (max_pixclk < 0)
5916 return max_pixclk;
85a96e7a 5917
27c329ed
ML		 5918 to_intel_atomic_state(state)->cdclk =
5919 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5920
27c329ed 5921 return 0;
30a970c6
JB		 5922}
5923
1e69cd74
VS		 5924static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5925{
5926 unsigned int credits, default_credits;
5927
5928 if (IS_CHERRYVIEW(dev_priv))
5929 default_credits = PFI_CREDIT(12);
5930 else
5931 default_credits = PFI_CREDIT(8);
5932
164dfd28 5933 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5934 /* CHV suggested value is 31 or 63 */
5935 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5936 credits = PFI_CREDIT_63;
1e69cd74
VS		 5937 else
5938 credits = PFI_CREDIT(15);
5939 } else {
5940 credits = default_credits;
5941 }
5942
5943 /*
5944 * WA - write default credits before re-programming
5945 * FIXME: should we also set the resend bit here?
5946 */
5947 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5948 default_credits);
5949
5950 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5951 credits | PFI_CREDIT_RESEND);
5952
5953 /*
5954 * FIXME is this guaranteed to clear
5955 * immediately or should we poll for it?
5956 */
5957 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5958}
5959
27c329ed 5960static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5961{
a821fc46 5962 struct drm_device *dev = old_state->dev;
27c329ed 5963 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5964 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5965
27c329ed
ML		 5966 /*
5967 * FIXME: We can end up here with all power domains off, yet
5968 * with a CDCLK frequency other than the minimum. To account
5969 * for this take the PIPE-A power domain, which covers the HW
5970 * blocks needed for the following programming. This can be
5971 * removed once it's guaranteed that we get here either with
5972 * the minimum CDCLK set, or the required power domains
5973 * enabled.
5974 */
5975 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5976
27c329ed
ML		 5977 if (IS_CHERRYVIEW(dev))
5978 cherryview_set_cdclk(dev, req_cdclk);
5979 else
5980 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5981
27c329ed 5982 vlv_program_pfi_credits(dev_priv);
1e69cd74 5983
27c329ed 5984 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 5985}
5986
89b667f8
JB		 5987static void valleyview_crtc_enable(struct drm_crtc *crtc)
5988{
5989 struct drm_device *dev = crtc->dev;
a72e4c9f 5990 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5992 struct intel_encoder *encoder;
5993 int pipe = intel_crtc->pipe;
23538ef1 5994 bool is_dsi;
89b667f8 5995
53d9f4e9 5996 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 5997 return;
5998
409ee761 5999 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6000
1ae0d137
VS		 6001 if (!is_dsi) {
6002 if (IS_CHERRYVIEW(dev))
6e3c9717 6003 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6004 else
6e3c9717 6005 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6006 }
5b18e57c 6007
6e3c9717 6008 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6009 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6010
6011 intel_set_pipe_timings(intel_crtc);
6012
c14b0485
VS		 6013 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6014 struct drm_i915_private *dev_priv = dev->dev_private;
6015
6016 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6017 I915_WRITE(CHV_CANVAS(pipe), 0);
6018 }
6019
5b18e57c
DV		 6020 i9xx_set_pipeconf(intel_crtc);
6021
89b667f8 6022 intel_crtc->active = true;
89b667f8 6023
a72e4c9f 6024 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6025
89b667f8
JB		 6026 for_each_encoder_on_crtc(dev, crtc, encoder)
6027 if (encoder->pre_pll_enable)
6028 encoder->pre_pll_enable(encoder);
6029
9d556c99
CML		 6030 if (!is_dsi) {
6031 if (IS_CHERRYVIEW(dev))
6e3c9717 6032 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6033 else
6e3c9717 6034 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6035 }
89b667f8
JB		 6036
6037 for_each_encoder_on_crtc(dev, crtc, encoder)
6038 if (encoder->pre_enable)
6039 encoder->pre_enable(encoder);
6040
2dd24552
JB		 6041 i9xx_pfit_enable(intel_crtc);
6042
63cbb074
VS		 6043 intel_crtc_load_lut(crtc);
6044
e1fdc473 6045 intel_enable_pipe(intel_crtc);
be6a6f8e 6046
4b3a9526
VS		 6047 assert_vblank_disabled(crtc);
6048 drm_crtc_vblank_on(crtc);
6049
f9b61ff6
DV		 6050 for_each_encoder_on_crtc(dev, crtc, encoder)
6051 encoder->enable(encoder);
89b667f8
JB		 6052}
6053
f13c2ef3
DV		 6054static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6055{
6056 struct drm_device *dev = crtc->base.dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058
6e3c9717
ACO		 6059 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6060 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6061}
6062
0b8765c6 6063static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6064{
6065 struct drm_device *dev = crtc->dev;
a72e4c9f 6066 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6068 struct intel_encoder *encoder;
79e53945 6069 int pipe = intel_crtc->pipe;
79e53945 6070
53d9f4e9 6071 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6072 return;
6073
f13c2ef3
DV		 6074 i9xx_set_pll_dividers(intel_crtc);
6075
6e3c9717 6076 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6077 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6078
6079 intel_set_pipe_timings(intel_crtc);
6080
5b18e57c
DV		 6081 i9xx_set_pipeconf(intel_crtc);
6082
f7abfe8b 6083 intel_crtc->active = true;
6b383a7f 6084
4a3436e8 6085 if (!IS_GEN2(dev))
a72e4c9f 6086 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6087
9d6d9f19
MK		 6088 for_each_encoder_on_crtc(dev, crtc, encoder)
6089 if (encoder->pre_enable)
6090 encoder->pre_enable(encoder);
6091
f6736a1a
DV		 6092 i9xx_enable_pll(intel_crtc);
6093
2dd24552
JB		 6094 i9xx_pfit_enable(intel_crtc);
6095
63cbb074
VS		 6096 intel_crtc_load_lut(crtc);
6097
f37fcc2a 6098 intel_update_watermarks(crtc);
e1fdc473 6099 intel_enable_pipe(intel_crtc);
be6a6f8e 6100
4b3a9526
VS		 6101 assert_vblank_disabled(crtc);
6102 drm_crtc_vblank_on(crtc);
6103
f9b61ff6
DV		 6104 for_each_encoder_on_crtc(dev, crtc, encoder)
6105 encoder->enable(encoder);
0b8765c6 6106}
79e53945 6107
87476d63
DV		 6108static void i9xx_pfit_disable(struct intel_crtc *crtc)
6109{
6110 struct drm_device *dev = crtc->base.dev;
6111 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6112
6e3c9717 6113 if (!crtc->config->gmch_pfit.control)
328d8e82 6114 return;
87476d63 6115
328d8e82 6116 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6117
328d8e82
DV		 6118 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6119 I915_READ(PFIT_CONTROL));
6120 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6121}
6122
0b8765c6
JB		 6123static void i9xx_crtc_disable(struct drm_crtc *crtc)
6124{
6125 struct drm_device *dev = crtc->dev;
6126 struct drm_i915_private *dev_priv = dev->dev_private;
6127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6128 struct intel_encoder *encoder;
0b8765c6 6129 int pipe = intel_crtc->pipe;
ef9c3aee 6130
6304cd91
VS		 6131 /*
6132 * On gen2 planes are double buffered but the pipe isn't, so we must
6133 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6134 * We also need to wait on all gmch platforms because of the
6135 * self-refresh mode constraint explained above.
6304cd91 6136 */
564ed191 6137 intel_wait_for_vblank(dev, pipe);
6304cd91 6138
4b3a9526
VS		 6139 for_each_encoder_on_crtc(dev, crtc, encoder)
6140 encoder->disable(encoder);
6141
f9b61ff6
DV		 6142 drm_crtc_vblank_off(crtc);
6143 assert_vblank_disabled(crtc);
6144
575f7ab7 6145 intel_disable_pipe(intel_crtc);
24a1f16d 6146
87476d63 6147 i9xx_pfit_disable(intel_crtc);
24a1f16d 6148
89b667f8
JB		 6149 for_each_encoder_on_crtc(dev, crtc, encoder)
6150 if (encoder->post_disable)
6151 encoder->post_disable(encoder);
6152
409ee761 6153 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6154 if (IS_CHERRYVIEW(dev))
6155 chv_disable_pll(dev_priv, pipe);
6156 else if (IS_VALLEYVIEW(dev))
6157 vlv_disable_pll(dev_priv, pipe);
6158 else
1c4e0274 6159 i9xx_disable_pll(intel_crtc);
076ed3b2 6160 }
0b8765c6 6161
4a3436e8 6162 if (!IS_GEN2(dev))
a72e4c9f 6163 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6164}
6165
b17d48e2
ML		 6166static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6167{
6168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6169 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6170 enum intel_display_power_domain domain;
6171 unsigned long domains;
6172
6173 if (!intel_crtc->active)
6174 return;
6175
a539205a
ML		 6176 if (to_intel_plane_state(crtc->primary->state)->visible) {
6177 intel_crtc_wait_for_pending_flips(crtc);
6178 intel_pre_disable_primary(crtc);
6179 }
6180
d032ffa0 6181 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2
ML		 6182 dev_priv->display.crtc_disable(crtc);
6183
6184 domains = intel_crtc->enabled_power_domains;
6185 for_each_power_domain(domain, domains)
6186 intel_display_power_put(dev_priv, domain);
6187 intel_crtc->enabled_power_domains = 0;
6188}
6189
6b72d486
ML		 6190/*
6191 * turn all crtc's off, but do not adjust state
6192 * This has to be paired with a call to intel_modeset_setup_hw_state.
6193 */
9716c691 6194void intel_display_suspend(struct drm_device *dev)
ee7b9f93 6195{
6b72d486
ML		 6196 struct drm_crtc *crtc;
6197
b17d48e2
ML		 6198 for_each_crtc(dev, crtc)
6199 intel_crtc_disable_noatomic(crtc);
ee7b9f93
JB		 6200}
6201
b04c5bd6 6202/* Master function to enable/disable CRTC and corresponding power wells */
5da76e94 6203int intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6204{
6205 struct drm_device *dev = crtc->dev;
5da76e94
ML		 6206 struct drm_mode_config *config = &dev->mode_config;
6207 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
0e572fe7 6208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5da76e94
ML		 6209 struct intel_crtc_state *pipe_config;
6210 struct drm_atomic_state *state;
6211 int ret;
976f8a20 6212
1b509259 6213 if (enable == intel_crtc->active)
5da76e94 6214 return 0;
0e572fe7 6215
1b509259 6216 if (enable && !crtc->state->enable)
5da76e94 6217 return 0;
1b509259 6218
5da76e94
ML		 6219 /* this function should be called with drm_modeset_lock_all for now */
6220 if (WARN_ON(!ctx))
6221 return -EIO;
6222 lockdep_assert_held(&ctx->ww_ctx);
1b509259 6223
5da76e94
ML		 6224 state = drm_atomic_state_alloc(dev);
6225 if (WARN_ON(!state))
6226 return -ENOMEM;
1b509259 6227
5da76e94
ML		 6228 state->acquire_ctx = ctx;
6229 state->allow_modeset = true;
6230
6231 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6232 if (IS_ERR(pipe_config)) {
6233 ret = PTR_ERR(pipe_config);
6234 goto err;
0e572fe7 6235 }
5da76e94
ML		 6236 pipe_config->base.active = enable;
6237
6238 ret = intel_set_mode(state);
6239 if (!ret)
6240 return ret;
6241
6242err:
6243 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6244 drm_atomic_state_free(state);
6245 return ret;
b04c5bd6
BF		 6246}
6247
6248/**
6249 * Sets the power management mode of the pipe and plane.
6250 */
6251void intel_crtc_update_dpms(struct drm_crtc *crtc)
6252{
6253 struct drm_device *dev = crtc->dev;
6254 struct intel_encoder *intel_encoder;
6255 bool enable = false;
6256
6257 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6258 enable |= intel_encoder->connectors_active;
6259
6260 intel_crtc_control(crtc, enable);
cdd59983
CW		 6261}
6262
ea5b213a 6263void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6264{
4ef69c7a 6265 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6266
ea5b213a
CW		 6267 drm_encoder_cleanup(encoder);
6268 kfree(intel_encoder);
7e7d76c3
JB		 6269}
6270
9237329d 6271/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6272 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6273 * state of the entire output pipe. */
9237329d 6274static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6275{
5ab432ef
DV		 6276 if (mode == DRM_MODE_DPMS_ON) {
6277 encoder->connectors_active = true;
6278
b2cabb0e 6279 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6280 } else {
6281 encoder->connectors_active = false;
6282
b2cabb0e 6283 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6284 }
79e53945
JB		 6285}
6286
0a91ca29
DV		 6287/* Cross check the actual hw state with our own modeset state tracking (and it's
6288 * internal consistency). */
b980514c 6289static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6290{
0a91ca29
DV		 6291 if (connector->get_hw_state(connector)) {
6292 struct intel_encoder *encoder = connector->encoder;
6293 struct drm_crtc *crtc;
6294 bool encoder_enabled;
6295 enum pipe pipe;
6296
6297 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6298 connector->base.base.id,
c23cc417 6299 connector->base.name);
0a91ca29 6300
0e32b39c
DA		 6301 /* there is no real hw state for MST connectors */
6302 if (connector->mst_port)
6303 return;
6304
e2c719b7 6305 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6306 "wrong connector dpms state\n");
e2c719b7 6307 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6308 "active connector not linked to encoder\n");
0a91ca29 6309
36cd7444 6310 if (encoder) {
e2c719b7 6311 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6312 "encoder->connectors_active not set\n");
6313
6314 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6315 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6316 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6317 return;
0a91ca29 6318
36cd7444 6319 crtc = encoder->base.crtc;
0a91ca29 6320
83d65738
MR		 6321 I915_STATE_WARN(!crtc->state->enable,
6322 "crtc not enabled\n");
e2c719b7
RC		 6323 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6324 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6325 "encoder active on the wrong pipe\n");
6326 }
0a91ca29 6327 }
79e53945
JB		 6328}
6329
08d9bc92
ACO		 6330int intel_connector_init(struct intel_connector *connector)
6331{
6332 struct drm_connector_state *connector_state;
6333
6334 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6335 if (!connector_state)
6336 return -ENOMEM;
6337
6338 connector->base.state = connector_state;
6339 return 0;
6340}
6341
6342struct intel_connector *intel_connector_alloc(void)
6343{
6344 struct intel_connector *connector;
6345
6346 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6347 if (!connector)
6348 return NULL;
6349
6350 if (intel_connector_init(connector) < 0) {
6351 kfree(connector);
6352 return NULL;
6353 }
6354
6355 return connector;
6356}
6357
5ab432ef
DV		 6358/* Even simpler default implementation, if there's really no special case to
6359 * consider. */
6360void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6361{
5ab432ef
DV		 6362 /* All the simple cases only support two dpms states. */
6363 if (mode != DRM_MODE_DPMS_ON)
6364 mode = DRM_MODE_DPMS_OFF;
d4270e57 6365
5ab432ef
DV		 6366 if (mode == connector->dpms)
6367 return;
6368
6369 connector->dpms = mode;
6370
6371 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6372 if (connector->encoder)
6373 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6374
b980514c 6375 intel_modeset_check_state(connector->dev);
79e53945
JB		 6376}
6377
f0947c37
DV		 6378/* Simple connector->get_hw_state implementation for encoders that support only
6379 * one connector and no cloning and hence the encoder state determines the state
6380 * of the connector. */
6381bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6382{
24929352 6383 enum pipe pipe = 0;
f0947c37 6384 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6385
f0947c37 6386 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6387}
6388
6d293983 6389static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6390{
6d293983
ACO		 6391 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6392 return crtc_state->fdi_lanes;
d272ddfa
VS		 6393
6394 return 0;
6395}
6396
6d293983 6397static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6398 struct intel_crtc_state *pipe_config)
1857e1da 6399{
6d293983
ACO		 6400 struct drm_atomic_state *state = pipe_config->base.state;
6401 struct intel_crtc *other_crtc;
6402 struct intel_crtc_state *other_crtc_state;
6403
1857e1da
DV		 6404 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6405 pipe_name(pipe), pipe_config->fdi_lanes);
6406 if (pipe_config->fdi_lanes > 4) {
6407 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6408 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6409 return -EINVAL;
1857e1da
DV		 6410 }
6411
bafb6553 6412 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6413 if (pipe_config->fdi_lanes > 2) {
6414 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6415 pipe_config->fdi_lanes);
6d293983 6416 return -EINVAL;
1857e1da 6417 } else {
6d293983 6418 return 0;
1857e1da
DV		 6419 }
6420 }
6421
6422 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6423 return 0;
1857e1da
DV		 6424
6425 /* Ivybridge 3 pipe is really complicated */
6426 switch (pipe) {
6427 case PIPE_A:
6d293983 6428 return 0;
1857e1da 6429 case PIPE_B:
6d293983
ACO		 6430 if (pipe_config->fdi_lanes <= 2)
6431 return 0;
6432
6433 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6434 other_crtc_state =
6435 intel_atomic_get_crtc_state(state, other_crtc);
6436 if (IS_ERR(other_crtc_state))
6437 return PTR_ERR(other_crtc_state);
6438
6439 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6440 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6441 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6442 return -EINVAL;
1857e1da 6443 }
6d293983 6444 return 0;
1857e1da 6445 case PIPE_C:
251cc67c
VS		 6446 if (pipe_config->fdi_lanes > 2) {
6447 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6448 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6449 return -EINVAL;
251cc67c 6450 }
6d293983
ACO		 6451
6452 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6453 other_crtc_state =
6454 intel_atomic_get_crtc_state(state, other_crtc);
6455 if (IS_ERR(other_crtc_state))
6456 return PTR_ERR(other_crtc_state);
6457
6458 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6459 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6460 return -EINVAL;
1857e1da 6461 }
6d293983 6462 return 0;
1857e1da
DV		 6463 default:
6464 BUG();
6465 }
6466}
6467
e29c22c0
DV		 6468#define RETRY 1
6469static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6470 struct intel_crtc_state *pipe_config)
877d48d5 6471{
1857e1da 6472 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6473 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6474 int lane, link_bw, fdi_dotclock, ret;
6475 bool needs_recompute = false;
877d48d5 6476
e29c22c0 6477retry:
877d48d5
DV		 6478 /* FDI is a binary signal running at ~2.7GHz, encoding
6479 * each output octet as 10 bits. The actual frequency
6480 * is stored as a divider into a 100MHz clock, and the
6481 * mode pixel clock is stored in units of 1KHz.
6482 * Hence the bw of each lane in terms of the mode signal
6483 * is:
6484 */
6485 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6486
241bfc38 6487 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6488
2bd89a07 6489 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6490 pipe_config->pipe_bpp);
6491
6492 pipe_config->fdi_lanes = lane;
6493
2bd89a07 6494 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6495 link_bw, &pipe_config->fdi_m_n);
1857e1da 6496
6d293983
ACO		 6497 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6498 intel_crtc->pipe, pipe_config);
6499 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6500 pipe_config->pipe_bpp -= 2*3;
6501 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6502 pipe_config->pipe_bpp);
6503 needs_recompute = true;
6504 pipe_config->bw_constrained = true;
6505
6506 goto retry;
6507 }
6508
6509 if (needs_recompute)
6510 return RETRY;
6511
6d293983 6512 return ret;
877d48d5
DV		 6513}
6514
8cfb3407
VS		 6515static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6516 struct intel_crtc_state *pipe_config)
6517{
6518 if (pipe_config->pipe_bpp > 24)
6519 return false;
6520
6521 /* HSW can handle pixel rate up to cdclk? */
6522 if (IS_HASWELL(dev_priv->dev))
6523 return true;
6524
6525 /*
b432e5cf
VS		 6526 * We compare against max which means we must take
6527 * the increased cdclk requirement into account when
6528 * calculating the new cdclk.
6529 *
6530 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6531 */
6532 return ilk_pipe_pixel_rate(pipe_config) <=
6533 dev_priv->max_cdclk_freq * 95 / 100;
6534}
6535
42db64ef 6536static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6537 struct intel_crtc_state *pipe_config)
42db64ef 6538{
8cfb3407
VS		 6539 struct drm_device *dev = crtc->base.dev;
6540 struct drm_i915_private *dev_priv = dev->dev_private;
6541
d330a953 6542 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6543 hsw_crtc_supports_ips(crtc) &&
6544 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6545}
6546
a43f6e0f 6547static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6548 struct intel_crtc_state *pipe_config)
79e53945 6549{
a43f6e0f 6550 struct drm_device *dev = crtc->base.dev;
8bd31e67 6551 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6552 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6553
ad3a4479 6554 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6555 if (INTEL_INFO(dev)->gen < 4) {
44913155 6556 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6557
6558 /*
6559 * Enable pixel doubling when the dot clock
6560 * is > 90% of the (display) core speed.
6561 *
b397c96b
VS		 6562 * GDG double wide on either pipe,
6563 * otherwise pipe A only.
cf532bb2 6564 */
b397c96b 6565 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6566 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6567 clock_limit *= 2;
cf532bb2 6568 pipe_config->double_wide = true;
ad3a4479
VS		 6569 }
6570
241bfc38 6571 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6572 return -EINVAL;
2c07245f 6573 }
89749350 6574
1d1d0e27
VS		 6575 /*
6576 * Pipe horizontal size must be even in:
6577 * - DVO ganged mode
6578 * - LVDS dual channel mode
6579 * - Double wide pipe
6580 */
a93e255f 6581 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6582 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6583 pipe_config->pipe_src_w &= ~1;
6584
8693a824
DL		 6585 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6586 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6587 */
6588 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6589 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6590 return -EINVAL;
44f46b42 6591
f5adf94e 6592 if (HAS_IPS(dev))
a43f6e0f
DV		 6593 hsw_compute_ips_config(crtc, pipe_config);
6594
877d48d5 6595 if (pipe_config->has_pch_encoder)
a43f6e0f 6596 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6597
cf5a15be 6598 return 0;
79e53945
JB		 6599}
6600
1652d19e
VS		 6601static int skylake_get_display_clock_speed(struct drm_device *dev)
6602{
6603 struct drm_i915_private *dev_priv = to_i915(dev);
6604 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6605 uint32_t cdctl = I915_READ(CDCLK_CTL);
6606 uint32_t linkrate;
6607
414355a7 6608 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6609 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6610
6611 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6612 return 540000;
6613
6614 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6615 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6616
71cd8423
DL		 6617 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6618 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6619 /* vco 8640 */
6620 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6621 case CDCLK_FREQ_450_432:
6622 return 432000;
6623 case CDCLK_FREQ_337_308:
6624 return 308570;
6625 case CDCLK_FREQ_675_617:
6626 return 617140;
6627 default:
6628 WARN(1, "Unknown cd freq selection\n");
6629 }
6630 } else {
6631 /* vco 8100 */
6632 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6633 case CDCLK_FREQ_450_432:
6634 return 450000;
6635 case CDCLK_FREQ_337_308:
6636 return 337500;
6637 case CDCLK_FREQ_675_617:
6638 return 675000;
6639 default:
6640 WARN(1, "Unknown cd freq selection\n");
6641 }
6642 }
6643
6644 /* error case, do as if DPLL0 isn't enabled */
6645 return 24000;
6646}
6647
acd3f3d3
BP		 6648static int broxton_get_display_clock_speed(struct drm_device *dev)
6649{
6650 struct drm_i915_private *dev_priv = to_i915(dev);
6651 uint32_t cdctl = I915_READ(CDCLK_CTL);
6652 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6653 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6654 int cdclk;
6655
6656 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6657 return 19200;
6658
6659 cdclk = 19200 * pll_ratio / 2;
6660
6661 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6662 case BXT_CDCLK_CD2X_DIV_SEL_1:
6663 return cdclk; /* 576MHz or 624MHz */
6664 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6665 return cdclk * 2 / 3; /* 384MHz */
6666 case BXT_CDCLK_CD2X_DIV_SEL_2:
6667 return cdclk / 2; /* 288MHz */
6668 case BXT_CDCLK_CD2X_DIV_SEL_4:
6669 return cdclk / 4; /* 144MHz */
6670 }
6671
6672 /* error case, do as if DE PLL isn't enabled */
6673 return 19200;
6674}
6675
1652d19e
VS		 6676static int broadwell_get_display_clock_speed(struct drm_device *dev)
6677{
6678 struct drm_i915_private *dev_priv = dev->dev_private;
6679 uint32_t lcpll = I915_READ(LCPLL_CTL);
6680 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6681
6682 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6683 return 800000;
6684 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6685 return 450000;
6686 else if (freq == LCPLL_CLK_FREQ_450)
6687 return 450000;
6688 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6689 return 540000;
6690 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6691 return 337500;
6692 else
6693 return 675000;
6694}
6695
6696static int haswell_get_display_clock_speed(struct drm_device *dev)
6697{
6698 struct drm_i915_private *dev_priv = dev->dev_private;
6699 uint32_t lcpll = I915_READ(LCPLL_CTL);
6700 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6701
6702 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6703 return 800000;
6704 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6705 return 450000;
6706 else if (freq == LCPLL_CLK_FREQ_450)
6707 return 450000;
6708 else if (IS_HSW_ULT(dev))
6709 return 337500;
6710 else
6711 return 540000;
79e53945
JB		 6712}
6713
25eb05fc
JB		 6714static int valleyview_get_display_clock_speed(struct drm_device *dev)
6715{
d197b7d3 6716 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6717 u32 val;
6718 int divider;
6719
6bcda4f0
VS		 6720 if (dev_priv->hpll_freq == 0)
6721 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6722
a580516d 6723 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6724 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6725 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6726
6727 divider = val & DISPLAY_FREQUENCY_VALUES;
6728
7d007f40
VS		 6729 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6730 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6731 "cdclk change in progress\n");
6732
6bcda4f0 6733 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6734}
6735
b37a6434
VS		 6736static int ilk_get_display_clock_speed(struct drm_device *dev)
6737{
6738 return 450000;
6739}
6740
e70236a8
JB		 6741static int i945_get_display_clock_speed(struct drm_device *dev)
6742{
6743 return 400000;
6744}
79e53945 6745
e70236a8 6746static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6747{
e907f170 6748 return 333333;
e70236a8 6749}
79e53945 6750
e70236a8
JB		 6751static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6752{
6753 return 200000;
6754}
79e53945 6755
257a7ffc
DV		 6756static int pnv_get_display_clock_speed(struct drm_device *dev)
6757{
6758 u16 gcfgc = 0;
6759
6760 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6761
6762 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6763 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6764 return 266667;
257a7ffc 6765 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6766 return 333333;
257a7ffc 6767 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6768 return 444444;
257a7ffc
DV		 6769 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6770 return 200000;
6771 default:
6772 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6773 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6774 return 133333;
257a7ffc 6775 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6776 return 166667;
257a7ffc
DV		 6777 }
6778}
6779
e70236a8
JB		 6780static int i915gm_get_display_clock_speed(struct drm_device *dev)
6781{
6782 u16 gcfgc = 0;
79e53945 6783
e70236a8
JB		 6784 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6785
6786 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6787 return 133333;
e70236a8
JB		 6788 else {
6789 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6790 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6791 return 333333;
e70236a8
JB		 6792 default:
6793 case GC_DISPLAY_CLOCK_190_200_MHZ:
6794 return 190000;
79e53945 6795 }
e70236a8
JB		 6796 }
6797}
6798
6799static int i865_get_display_clock_speed(struct drm_device *dev)
6800{
e907f170 6801 return 266667;
e70236a8
JB		 6802}
6803
1b1d2716 6804static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6805{
6806 u16 hpllcc = 0;
1b1d2716 6807
65cd2b3f
VS		 6808 /*
6809 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6810 * encoding is different :(
6811 * FIXME is this the right way to detect 852GM/852GMV?
6812 */
6813 if (dev->pdev->revision == 0x1)
6814 return 133333;
6815
1b1d2716
VS		 6816 pci_bus_read_config_word(dev->pdev->bus,
6817 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6818
e70236a8
JB		 6819 /* Assume that the hardware is in the high speed state. This
6820 * should be the default.
6821 */
6822 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6823 case GC_CLOCK_133_200:
1b1d2716 6824 case GC_CLOCK_133_200_2:
e70236a8
JB		 6825 case GC_CLOCK_100_200:
6826 return 200000;
6827 case GC_CLOCK_166_250:
6828 return 250000;
6829 case GC_CLOCK_100_133:
e907f170 6830 return 133333;
1b1d2716
VS		 6831 case GC_CLOCK_133_266:
6832 case GC_CLOCK_133_266_2:
6833 case GC_CLOCK_166_266:
6834 return 266667;
e70236a8 6835 }
79e53945 6836
e70236a8
JB		 6837 /* Shouldn't happen */
6838 return 0;
6839}
79e53945 6840
e70236a8
JB		 6841static int i830_get_display_clock_speed(struct drm_device *dev)
6842{
e907f170 6843 return 133333;
79e53945
JB		 6844}
6845
34edce2f
VS		 6846static unsigned int intel_hpll_vco(struct drm_device *dev)
6847{
6848 struct drm_i915_private *dev_priv = dev->dev_private;
6849 static const unsigned int blb_vco[8] = {
6850 [0] = 3200000,
6851 [1] = 4000000,
6852 [2] = 5333333,
6853 [3] = 4800000,
6854 [4] = 6400000,
6855 };
6856 static const unsigned int pnv_vco[8] = {
6857 [0] = 3200000,
6858 [1] = 4000000,
6859 [2] = 5333333,
6860 [3] = 4800000,
6861 [4] = 2666667,
6862 };
6863 static const unsigned int cl_vco[8] = {
6864 [0] = 3200000,
6865 [1] = 4000000,
6866 [2] = 5333333,
6867 [3] = 6400000,
6868 [4] = 3333333,
6869 [5] = 3566667,
6870 [6] = 4266667,
6871 };
6872 static const unsigned int elk_vco[8] = {
6873 [0] = 3200000,
6874 [1] = 4000000,
6875 [2] = 5333333,
6876 [3] = 4800000,
6877 };
6878 static const unsigned int ctg_vco[8] = {
6879 [0] = 3200000,
6880 [1] = 4000000,
6881 [2] = 5333333,
6882 [3] = 6400000,
6883 [4] = 2666667,
6884 [5] = 4266667,
6885 };
6886 const unsigned int *vco_table;
6887 unsigned int vco;
6888 uint8_t tmp = 0;
6889
6890 /* FIXME other chipsets? */
6891 if (IS_GM45(dev))
6892 vco_table = ctg_vco;
6893 else if (IS_G4X(dev))
6894 vco_table = elk_vco;
6895 else if (IS_CRESTLINE(dev))
6896 vco_table = cl_vco;
6897 else if (IS_PINEVIEW(dev))
6898 vco_table = pnv_vco;
6899 else if (IS_G33(dev))
6900 vco_table = blb_vco;
6901 else
6902 return 0;
6903
6904 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6905
6906 vco = vco_table[tmp & 0x7];
6907 if (vco == 0)
6908 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6909 else
6910 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6911
6912 return vco;
6913}
6914
6915static int gm45_get_display_clock_speed(struct drm_device *dev)
6916{
6917 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6918 uint16_t tmp = 0;
6919
6920 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6921
6922 cdclk_sel = (tmp >> 12) & 0x1;
6923
6924 switch (vco) {
6925 case 2666667:
6926 case 4000000:
6927 case 5333333:
6928 return cdclk_sel ? 333333 : 222222;
6929 case 3200000:
6930 return cdclk_sel ? 320000 : 228571;
6931 default:
6932 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6933 return 222222;
6934 }
6935}
6936
6937static int i965gm_get_display_clock_speed(struct drm_device *dev)
6938{
6939 static const uint8_t div_3200[] = { 16, 10, 8 };
6940 static const uint8_t div_4000[] = { 20, 12, 10 };
6941 static const uint8_t div_5333[] = { 24, 16, 14 };
6942 const uint8_t *div_table;
6943 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6944 uint16_t tmp = 0;
6945
6946 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6947
6948 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6949
6950 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6951 goto fail;
6952
6953 switch (vco) {
6954 case 3200000:
6955 div_table = div_3200;
6956 break;
6957 case 4000000:
6958 div_table = div_4000;
6959 break;
6960 case 5333333:
6961 div_table = div_5333;
6962 break;
6963 default:
6964 goto fail;
6965 }
6966
6967 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6968
caf4e252 6969fail:
34edce2f
VS		 6970 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6971 return 200000;
6972}
6973
6974static int g33_get_display_clock_speed(struct drm_device *dev)
6975{
6976 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6977 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6978 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6979 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6980 const uint8_t *div_table;
6981 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6982 uint16_t tmp = 0;
6983
6984 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6985
6986 cdclk_sel = (tmp >> 4) & 0x7;
6987
6988 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6989 goto fail;
6990
6991 switch (vco) {
6992 case 3200000:
6993 div_table = div_3200;
6994 break;
6995 case 4000000:
6996 div_table = div_4000;
6997 break;
6998 case 4800000:
6999 div_table = div_4800;
7000 break;
7001 case 5333333:
7002 div_table = div_5333;
7003 break;
7004 default:
7005 goto fail;
7006 }
7007
7008 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7009
caf4e252 7010fail:
34edce2f
VS		 7011 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7012 return 190476;
7013}
7014
2c07245f 7015static void
a65851af 7016intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7017{
a65851af
VS		 7018 while (*num > DATA_LINK_M_N_MASK ||
7019 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7020 *num >>= 1;
7021 *den >>= 1;
7022 }
7023}
7024
a65851af
VS		 7025static void compute_m_n(unsigned int m, unsigned int n,
7026 uint32_t *ret_m, uint32_t *ret_n)
7027{
7028 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7029 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7030 intel_reduce_m_n_ratio(ret_m, ret_n);
7031}
7032
e69d0bc1
DV		 7033void
7034intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7035 int pixel_clock, int link_clock,
7036 struct intel_link_m_n *m_n)
2c07245f 7037{
e69d0bc1 7038 m_n->tu = 64;
a65851af
VS		 7039
7040 compute_m_n(bits_per_pixel * pixel_clock,
7041 link_clock * nlanes * 8,
7042 &m_n->gmch_m, &m_n->gmch_n);
7043
7044 compute_m_n(pixel_clock, link_clock,
7045 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7046}
7047
a7615030
CW		 7048static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7049{
d330a953
JN		 7050 if (i915.panel_use_ssc >= 0)
7051 return i915.panel_use_ssc != 0;
41aa3448 7052 return dev_priv->vbt.lvds_use_ssc
435793df 7053 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7054}
7055
a93e255f
ACO		 7056static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7057 int num_connectors)
c65d77d8 7058{
a93e255f 7059 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7060 struct drm_i915_private *dev_priv = dev->dev_private;
7061 int refclk;
7062
a93e255f
ACO		 7063 WARN_ON(!crtc_state->base.state);
7064
5ab7b0b7 7065 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7066 refclk = 100000;
a93e255f 7067 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7068 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7069 refclk = dev_priv->vbt.lvds_ssc_freq;
7070 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7071 } else if (!IS_GEN2(dev)) {
7072 refclk = 96000;
7073 } else {
7074 refclk = 48000;
7075 }
7076
7077 return refclk;
7078}
7079
7429e9d4 7080static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7081{
7df00d7a 7082 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7083}
f47709a9 7084
7429e9d4
DV		 7085static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7086{
7087 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7088}
7089
f47709a9 7090static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7091 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7092 intel_clock_t *reduced_clock)
7093{
f47709a9 7094 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7095 u32 fp, fp2 = 0;
7096
7097 if (IS_PINEVIEW(dev)) {
190f68c5 7098 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7099 if (reduced_clock)
7429e9d4 7100 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7101 } else {
190f68c5 7102 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7103 if (reduced_clock)
7429e9d4 7104 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7105 }
7106
190f68c5 7107 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7108
f47709a9 7109 crtc->lowfreq_avail = false;
a93e255f 7110 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7111 reduced_clock) {
190f68c5 7112 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7113 crtc->lowfreq_avail = true;
a7516a05 7114 } else {
190f68c5 7115 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7116 }
7117}
7118
5e69f97f
CML		 7119static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7120 pipe)
89b667f8
JB		 7121{
7122 u32 reg_val;
7123
7124 /*
7125 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7126 * and set it to a reasonable value instead.
7127 */
ab3c759a 7128 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7129 reg_val &= 0xffffff00;
7130 reg_val |= 0x00000030;
ab3c759a 7131 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7132
ab3c759a 7133 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7134 reg_val &= 0x8cffffff;
7135 reg_val = 0x8c000000;
ab3c759a 7136 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7137
ab3c759a 7138 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7139 reg_val &= 0xffffff00;
ab3c759a 7140 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7141
ab3c759a 7142 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7143 reg_val &= 0x00ffffff;
7144 reg_val |= 0xb0000000;
ab3c759a 7145 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7146}
7147
b551842d
DV		 7148static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7149 struct intel_link_m_n *m_n)
7150{
7151 struct drm_device *dev = crtc->base.dev;
7152 struct drm_i915_private *dev_priv = dev->dev_private;
7153 int pipe = crtc->pipe;
7154
e3b95f1e
DV		 7155 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7156 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7157 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7158 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7159}
7160
7161static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7162 struct intel_link_m_n *m_n,
7163 struct intel_link_m_n *m2_n2)
b551842d
DV		 7164{
7165 struct drm_device *dev = crtc->base.dev;
7166 struct drm_i915_private *dev_priv = dev->dev_private;
7167 int pipe = crtc->pipe;
6e3c9717 7168 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7169
7170 if (INTEL_INFO(dev)->gen >= 5) {
7171 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7172 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7173 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7174 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7175 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7176 * for gen < 8) and if DRRS is supported (to make sure the
7177 * registers are not unnecessarily accessed).
7178 */
44395bfe 7179 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7180 crtc->config->has_drrs) {
f769cd24
VK		 7181 I915_WRITE(PIPE_DATA_M2(transcoder),
7182 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7183 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7184 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7185 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7186 }
b551842d 7187 } else {
e3b95f1e
DV		 7188 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7189 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7190 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7191 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7192 }
7193}
7194
fe3cd48d 7195void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7196{
fe3cd48d
R		 7197 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7198
7199 if (m_n == M1_N1) {
7200 dp_m_n = &crtc->config->dp_m_n;
7201 dp_m2_n2 = &crtc->config->dp_m2_n2;
7202 } else if (m_n == M2_N2) {
7203
7204 /*
7205 * M2_N2 registers are not supported. Hence m2_n2 divider value
7206 * needs to be programmed into M1_N1.
7207 */
7208 dp_m_n = &crtc->config->dp_m2_n2;
7209 } else {
7210 DRM_ERROR("Unsupported divider value\n");
7211 return;
7212 }
7213
6e3c9717
ACO		 7214 if (crtc->config->has_pch_encoder)
7215 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7216 else
fe3cd48d 7217 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7218}
7219
251ac862
DV		 7220static void vlv_compute_dpll(struct intel_crtc *crtc,
7221 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7222{
7223 u32 dpll, dpll_md;
7224
7225 /*
7226 * Enable DPIO clock input. We should never disable the reference
7227 * clock for pipe B, since VGA hotplug / manual detection depends
7228 * on it.
7229 */
7230 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7231 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7232 /* We should never disable this, set it here for state tracking */
7233 if (crtc->pipe == PIPE_B)
7234 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7235 dpll |= DPLL_VCO_ENABLE;
d288f65f 7236 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7237
d288f65f 7238 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7239 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7240 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7241}
7242
d288f65f 7243static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7244 const struct intel_crtc_state *pipe_config)
a0c4da24 7245{
f47709a9 7246 struct drm_device *dev = crtc->base.dev;
a0c4da24 7247 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7248 int pipe = crtc->pipe;
bdd4b6a6 7249 u32 mdiv;
a0c4da24 7250 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7251 u32 coreclk, reg_val;
a0c4da24 7252
a580516d 7253 mutex_lock(&dev_priv->sb_lock);
09153000 7254
d288f65f
VS		 7255 bestn = pipe_config->dpll.n;
7256 bestm1 = pipe_config->dpll.m1;
7257 bestm2 = pipe_config->dpll.m2;
7258 bestp1 = pipe_config->dpll.p1;
7259 bestp2 = pipe_config->dpll.p2;
a0c4da24 7260
89b667f8
JB		 7261 /* See eDP HDMI DPIO driver vbios notes doc */
7262
7263 /* PLL B needs special handling */
bdd4b6a6 7264 if (pipe == PIPE_B)
5e69f97f 7265 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7266
7267 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7268 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7269
7270 /* Disable target IRef on PLL */
ab3c759a 7271 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7272 reg_val &= 0x00ffffff;
ab3c759a 7273 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7274
7275 /* Disable fast lock */
ab3c759a 7276 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7277
7278 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7279 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7280 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7281 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7282 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7283
7284 /*
7285 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7286 * but we don't support that).
7287 * Note: don't use the DAC post divider as it seems unstable.
7288 */
7289 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7291
a0c4da24 7292 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7293 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7294
89b667f8 7295 /* Set HBR and RBR LPF coefficients */
d288f65f 7296 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7297 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7298 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7300 0x009f0003);
89b667f8 7301 else
ab3c759a 7302 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7303 0x00d0000f);
7304
681a8504 7305 if (pipe_config->has_dp_encoder) {
89b667f8 7306 /* Use SSC source */
bdd4b6a6 7307 if (pipe == PIPE_A)
ab3c759a 7308 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7309 0x0df40000);
7310 else
ab3c759a 7311 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7312 0x0df70000);
7313 } else { /* HDMI or VGA */
7314 /* Use bend source */
bdd4b6a6 7315 if (pipe == PIPE_A)
ab3c759a 7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7317 0x0df70000);
7318 else
ab3c759a 7319 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7320 0x0df40000);
7321 }
a0c4da24 7322
ab3c759a 7323 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7324 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7325 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7326 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7327 coreclk |= 0x01000000;
ab3c759a 7328 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7329
ab3c759a 7330 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7331 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7332}
7333
251ac862
DV		 7334static void chv_compute_dpll(struct intel_crtc *crtc,
7335 struct intel_crtc_state *pipe_config)
1ae0d137 7336{
d288f65f 7337 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7338 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7339 DPLL_VCO_ENABLE;
7340 if (crtc->pipe != PIPE_A)
d288f65f 7341 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7342
d288f65f
VS		 7343 pipe_config->dpll_hw_state.dpll_md =
7344 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7345}
7346
d288f65f 7347static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7348 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7349{
7350 struct drm_device *dev = crtc->base.dev;
7351 struct drm_i915_private *dev_priv = dev->dev_private;
7352 int pipe = crtc->pipe;
7353 int dpll_reg = DPLL(crtc->pipe);
7354 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7355 u32 loopfilter, tribuf_calcntr;
9d556c99 7356 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7357 u32 dpio_val;
9cbe40c1 7358 int vco;
9d556c99 7359
d288f65f
VS		 7360 bestn = pipe_config->dpll.n;
7361 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7362 bestm1 = pipe_config->dpll.m1;
7363 bestm2 = pipe_config->dpll.m2 >> 22;
7364 bestp1 = pipe_config->dpll.p1;
7365 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7366 vco = pipe_config->dpll.vco;
a945ce7e 7367 dpio_val = 0;
9cbe40c1 7368 loopfilter = 0;
9d556c99
CML		 7369
7370 /*
7371 * Enable Refclk and SSC
7372 */
a11b0703 7373 I915_WRITE(dpll_reg,
d288f65f 7374 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7375
a580516d 7376 mutex_lock(&dev_priv->sb_lock);
9d556c99 7377
9d556c99
CML		 7378 /* p1 and p2 divider */
7379 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7380 5 << DPIO_CHV_S1_DIV_SHIFT |
7381 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7382 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7383 1 << DPIO_CHV_K_DIV_SHIFT);
7384
7385 /* Feedback post-divider - m2 */
7386 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7387
7388 /* Feedback refclk divider - n and m1 */
7389 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7390 DPIO_CHV_M1_DIV_BY_2 |
7391 1 << DPIO_CHV_N_DIV_SHIFT);
7392
7393 /* M2 fraction division */
a945ce7e
VP		 7394 if (bestm2_frac)
7395 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7396
7397 /* M2 fraction division enable */
a945ce7e
VP		 7398 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7399 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7400 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7401 if (bestm2_frac)
7402 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7403 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7404
de3a0fde
VP		 7405 /* Program digital lock detect threshold */
7406 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7407 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7408 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7409 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7410 if (!bestm2_frac)
7411 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7412 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7413
9d556c99 7414 /* Loop filter */
9cbe40c1
VP		 7415 if (vco == 5400000) {
7416 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7417 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7418 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7419 tribuf_calcntr = 0x9;
7420 } else if (vco <= 6200000) {
7421 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7422 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7423 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7424 tribuf_calcntr = 0x9;
7425 } else if (vco <= 6480000) {
7426 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7427 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7428 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7429 tribuf_calcntr = 0x8;
7430 } else {
7431 /* Not supported. Apply the same limits as in the max case */
7432 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7433 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7434 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7435 tribuf_calcntr = 0;
7436 }
9d556c99
CML		 7437 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7438
968040b2 7439 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7440 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7441 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7442 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7443
9d556c99
CML		 7444 /* AFC Recal */
7445 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7446 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7447 DPIO_AFC_RECAL);
7448
a580516d 7449 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7450}
7451
d288f65f
VS		 7452/**
7453 * vlv_force_pll_on - forcibly enable just the PLL
7454 * @dev_priv: i915 private structure
7455 * @pipe: pipe PLL to enable
7456 * @dpll: PLL configuration
7457 *
7458 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7459 * in cases where we need the PLL enabled even when @pipe is not going to
7460 * be enabled.
7461 */
7462void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7463 const struct dpll *dpll)
7464{
7465 struct intel_crtc *crtc =
7466 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7467 struct intel_crtc_state pipe_config = {
a93e255f 7468 .base.crtc = &crtc->base,
d288f65f
VS		 7469 .pixel_multiplier = 1,
7470 .dpll = *dpll,
7471 };
7472
7473 if (IS_CHERRYVIEW(dev)) {
251ac862 7474 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7475 chv_prepare_pll(crtc, &pipe_config);
7476 chv_enable_pll(crtc, &pipe_config);
7477 } else {
251ac862 7478 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7479 vlv_prepare_pll(crtc, &pipe_config);
7480 vlv_enable_pll(crtc, &pipe_config);
7481 }
7482}
7483
7484/**
7485 * vlv_force_pll_off - forcibly disable just the PLL
7486 * @dev_priv: i915 private structure
7487 * @pipe: pipe PLL to disable
7488 *
7489 * Disable the PLL for @pipe. To be used in cases where we need
7490 * the PLL enabled even when @pipe is not going to be enabled.
7491 */
7492void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7493{
7494 if (IS_CHERRYVIEW(dev))
7495 chv_disable_pll(to_i915(dev), pipe);
7496 else
7497 vlv_disable_pll(to_i915(dev), pipe);
7498}
7499
251ac862
DV		 7500static void i9xx_compute_dpll(struct intel_crtc *crtc,
7501 struct intel_crtc_state *crtc_state,
7502 intel_clock_t *reduced_clock,
7503 int num_connectors)
eb1cbe48 7504{
f47709a9 7505 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7506 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7507 u32 dpll;
7508 bool is_sdvo;
190f68c5 7509 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7510
190f68c5 7511 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7512
a93e255f
ACO		 7513 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7514 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7515
7516 dpll = DPLL_VGA_MODE_DIS;
7517
a93e255f 7518 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7519 dpll |= DPLLB_MODE_LVDS;
7520 else
7521 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7522
ef1b460d 7523 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7524 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7525 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7526 }
198a037f
DV		 7527
7528 if (is_sdvo)
4a33e48d 7529 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7530
190f68c5 7531 if (crtc_state->has_dp_encoder)
4a33e48d 7532 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7533
7534 /* compute bitmask from p1 value */
7535 if (IS_PINEVIEW(dev))
7536 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7537 else {
7538 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7539 if (IS_G4X(dev) && reduced_clock)
7540 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7541 }
7542 switch (clock->p2) {
7543 case 5:
7544 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7545 break;
7546 case 7:
7547 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7548 break;
7549 case 10:
7550 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7551 break;
7552 case 14:
7553 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7554 break;
7555 }
7556 if (INTEL_INFO(dev)->gen >= 4)
7557 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7558
190f68c5 7559 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7560 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7561 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7562 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7563 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7564 else
7565 dpll |= PLL_REF_INPUT_DREFCLK;
7566
7567 dpll |= DPLL_VCO_ENABLE;
190f68c5 7568 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7569
eb1cbe48 7570 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7571 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7572 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7573 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7574 }
7575}
7576
251ac862
DV		 7577static void i8xx_compute_dpll(struct intel_crtc *crtc,
7578 struct intel_crtc_state *crtc_state,
7579 intel_clock_t *reduced_clock,
7580 int num_connectors)
eb1cbe48 7581{
f47709a9 7582 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7583 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7584 u32 dpll;
190f68c5 7585 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7586
190f68c5 7587 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7588
eb1cbe48
DV		 7589 dpll = DPLL_VGA_MODE_DIS;
7590
a93e255f 7591 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7592 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7593 } else {
7594 if (clock->p1 == 2)
7595 dpll |= PLL_P1_DIVIDE_BY_TWO;
7596 else
7597 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7598 if (clock->p2 == 4)
7599 dpll |= PLL_P2_DIVIDE_BY_4;
7600 }
7601
a93e255f 7602 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7603 dpll |= DPLL_DVO_2X_MODE;
7604
a93e255f 7605 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7606 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7607 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7608 else
7609 dpll |= PLL_REF_INPUT_DREFCLK;
7610
7611 dpll |= DPLL_VCO_ENABLE;
190f68c5 7612 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7613}
7614
8a654f3b 7615static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7616{
7617 struct drm_device *dev = intel_crtc->base.dev;
7618 struct drm_i915_private *dev_priv = dev->dev_private;
7619 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7620 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7621 struct drm_display_mode *adjusted_mode =
6e3c9717 7622 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7623 uint32_t crtc_vtotal, crtc_vblank_end;
7624 int vsyncshift = 0;
4d8a62ea
DV		 7625
7626 /* We need to be careful not to changed the adjusted mode, for otherwise
7627 * the hw state checker will get angry at the mismatch. */
7628 crtc_vtotal = adjusted_mode->crtc_vtotal;
7629 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7630
609aeaca 7631 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7632 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7633 crtc_vtotal -= 1;
7634 crtc_vblank_end -= 1;
609aeaca 7635
409ee761 7636 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7637 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7638 else
7639 vsyncshift = adjusted_mode->crtc_hsync_start -
7640 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7641 if (vsyncshift < 0)
7642 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7643 }
7644
7645 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7646 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7647
fe2b8f9d 7648 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7649 (adjusted_mode->crtc_hdisplay - 1) |
7650 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7651 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7652 (adjusted_mode->crtc_hblank_start - 1) |
7653 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7654 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7655 (adjusted_mode->crtc_hsync_start - 1) |
7656 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7657
fe2b8f9d 7658 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7659 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7660 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7661 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7662 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7663 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7664 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7665 (adjusted_mode->crtc_vsync_start - 1) |
7666 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7667
b5e508d4
PZ		 7668 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7669 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7670 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7671 * bits. */
7672 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7673 (pipe == PIPE_B || pipe == PIPE_C))
7674 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7675
b0e77b9c
PZ		 7676 /* pipesrc controls the size that is scaled from, which should
7677 * always be the user's requested size.
7678 */
7679 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7680 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7681 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7682}
7683
1bd1bd80 7684static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7685 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7686{
7687 struct drm_device *dev = crtc->base.dev;
7688 struct drm_i915_private *dev_priv = dev->dev_private;
7689 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7690 uint32_t tmp;
7691
7692 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7693 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7694 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7695 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7696 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7697 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7698 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7699 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7700 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7701
7702 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7703 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7704 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7705 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7706 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7707 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7708 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7709 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7710 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7711
7712 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7713 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7714 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7715 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7716 }
7717
7718 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7719 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7720 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7721
2d112de7
ACO		 7722 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7723 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7724}
7725
f6a83288 7726void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7727 struct intel_crtc_state *pipe_config)
babea61d 7728{
2d112de7
ACO		 7729 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7730 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7731 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7732 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7733
2d112de7
ACO		 7734 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7735 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7736 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7737 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7738
2d112de7 7739 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7740
2d112de7
ACO		 7741 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7742 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7743}
7744
84b046f3
DV		 7745static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7746{
7747 struct drm_device *dev = intel_crtc->base.dev;
7748 struct drm_i915_private *dev_priv = dev->dev_private;
7749 uint32_t pipeconf;
7750
9f11a9e4 7751 pipeconf = 0;
84b046f3 7752
b6b5d049
VS		 7753 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7754 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7755 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7756
6e3c9717 7757 if (intel_crtc->config->double_wide)
cf532bb2 7758 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7759
ff9ce46e
DV		 7760 /* only g4x and later have fancy bpc/dither controls */
7761 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7762 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7763 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7764 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7765 PIPECONF_DITHER_TYPE_SP;
84b046f3 7766
6e3c9717 7767 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7768 case 18:
7769 pipeconf |= PIPECONF_6BPC;
7770 break;
7771 case 24:
7772 pipeconf |= PIPECONF_8BPC;
7773 break;
7774 case 30:
7775 pipeconf |= PIPECONF_10BPC;
7776 break;
7777 default:
7778 /* Case prevented by intel_choose_pipe_bpp_dither. */
7779 BUG();
84b046f3
DV		 7780 }
7781 }
7782
7783 if (HAS_PIPE_CXSR(dev)) {
7784 if (intel_crtc->lowfreq_avail) {
7785 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7786 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7787 } else {
7788 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7789 }
7790 }
7791
6e3c9717 7792 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7793 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7794 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7795 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7796 else
7797 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7798 } else
84b046f3
DV		 7799 pipeconf |= PIPECONF_PROGRESSIVE;
7800
6e3c9717 7801 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7802 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7803
84b046f3
DV		 7804 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7805 POSTING_READ(PIPECONF(intel_crtc->pipe));
7806}
7807
190f68c5
ACO		 7808static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7809 struct intel_crtc_state *crtc_state)
79e53945 7810{
c7653199 7811 struct drm_device *dev = crtc->base.dev;
79e53945 7812 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7813 int refclk, num_connectors = 0;
c329a4ec
DV		 7814 intel_clock_t clock;
7815 bool ok;
7816 bool is_dsi = false;
5eddb70b 7817 struct intel_encoder *encoder;
d4906093 7818 const intel_limit_t *limit;
55bb9992 7819 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7820 struct drm_connector *connector;
55bb9992
ACO		 7821 struct drm_connector_state *connector_state;
7822 int i;
79e53945 7823
dd3cd74a
ACO		 7824 memset(&crtc_state->dpll_hw_state, 0,
7825 sizeof(crtc_state->dpll_hw_state));
7826
da3ced29 7827 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7828 if (connector_state->crtc != &crtc->base)
7829 continue;
7830
7831 encoder = to_intel_encoder(connector_state->best_encoder);
7832
5eddb70b 7833 switch (encoder->type) {
e9fd1c02
JN		 7834 case INTEL_OUTPUT_DSI:
7835 is_dsi = true;
7836 break;
6847d71b
PZ		 7837 default:
7838 break;
79e53945 7839 }
43565a06 7840
c751ce4f 7841 num_connectors++;
79e53945
JB		 7842 }
7843
f2335330 7844 if (is_dsi)
5b18e57c 7845 return 0;
f2335330 7846
190f68c5 7847 if (!crtc_state->clock_set) {
a93e255f 7848 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7849
e9fd1c02
JN		 7850 /*
7851 * Returns a set of divisors for the desired target clock with
7852 * the given refclk, or FALSE. The returned values represent
7853 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7854 * 2) / p1 / p2.
7855 */
a93e255f
ACO		 7856 limit = intel_limit(crtc_state, refclk);
7857 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7858 crtc_state->port_clock,
e9fd1c02 7859 refclk, NULL, &clock);
f2335330 7860 if (!ok) {
e9fd1c02
JN		 7861 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7862 return -EINVAL;
7863 }
79e53945 7864
f2335330 7865 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7866 crtc_state->dpll.n = clock.n;
7867 crtc_state->dpll.m1 = clock.m1;
7868 crtc_state->dpll.m2 = clock.m2;
7869 crtc_state->dpll.p1 = clock.p1;
7870 crtc_state->dpll.p2 = clock.p2;
f47709a9 7871 }
7026d4ac 7872
e9fd1c02 7873 if (IS_GEN2(dev)) {
c329a4ec 7874 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7875 num_connectors);
9d556c99 7876 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7877 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7878 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7879 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7880 } else {
c329a4ec 7881 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7882 num_connectors);
e9fd1c02 7883 }
79e53945 7884
c8f7a0db 7885 return 0;
f564048e
EA		 7886}
7887
2fa2fe9a 7888static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7889 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7890{
7891 struct drm_device *dev = crtc->base.dev;
7892 struct drm_i915_private *dev_priv = dev->dev_private;
7893 uint32_t tmp;
7894
dc9e7dec
VS		 7895 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7896 return;
7897
2fa2fe9a 7898 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7899 if (!(tmp & PFIT_ENABLE))
7900 return;
2fa2fe9a 7901
06922821 7902 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7903 if (INTEL_INFO(dev)->gen < 4) {
7904 if (crtc->pipe != PIPE_B)
7905 return;
2fa2fe9a
DV		 7906 } else {
7907 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7908 return;
7909 }
7910
06922821 7911 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7912 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7913 if (INTEL_INFO(dev)->gen < 5)
7914 pipe_config->gmch_pfit.lvds_border_bits =
7915 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7916}
7917
acbec814 7918static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7919 struct intel_crtc_state *pipe_config)
acbec814
JB		 7920{
7921 struct drm_device *dev = crtc->base.dev;
7922 struct drm_i915_private *dev_priv = dev->dev_private;
7923 int pipe = pipe_config->cpu_transcoder;
7924 intel_clock_t clock;
7925 u32 mdiv;
662c6ecb 7926 int refclk = 100000;
acbec814 7927
f573de5a
SK		 7928 /* In case of MIPI DPLL will not even be used */
7929 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7930 return;
7931
a580516d 7932 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7933 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7934 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7935
7936 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7937 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7938 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7939 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7940 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7941
dccbea3b 7942 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7943}
7944
5724dbd1
DL		 7945static void
7946i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7947 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7948{
7949 struct drm_device *dev = crtc->base.dev;
7950 struct drm_i915_private *dev_priv = dev->dev_private;
7951 u32 val, base, offset;
7952 int pipe = crtc->pipe, plane = crtc->plane;
7953 int fourcc, pixel_format;
6761dd31 7954 unsigned int aligned_height;
b113d5ee 7955 struct drm_framebuffer *fb;
1b842c89 7956 struct intel_framebuffer *intel_fb;
1ad292b5 7957
42a7b088
DL		 7958 val = I915_READ(DSPCNTR(plane));
7959 if (!(val & DISPLAY_PLANE_ENABLE))
7960 return;
7961
d9806c9f 7962 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7963 if (!intel_fb) {
1ad292b5
JB		 7964 DRM_DEBUG_KMS("failed to alloc fb\n");
7965 return;
7966 }
7967
1b842c89
DL		 7968 fb = &intel_fb->base;
7969
18c5247e
DV		 7970 if (INTEL_INFO(dev)->gen >= 4) {
7971 if (val & DISPPLANE_TILED) {
49af449b 7972 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7973 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7974 }
7975 }
1ad292b5
JB		 7976
7977 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7978 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7979 fb->pixel_format = fourcc;
7980 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7981
7982 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7983 if (plane_config->tiling)
1ad292b5
JB		 7984 offset = I915_READ(DSPTILEOFF(plane));
7985 else
7986 offset = I915_READ(DSPLINOFF(plane));
7987 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7988 } else {
7989 base = I915_READ(DSPADDR(plane));
7990 }
7991 plane_config->base = base;
7992
7993 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7994 fb->width = ((val >> 16) & 0xfff) + 1;
7995 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7996
7997 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7998 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7999
b113d5ee 8000 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8001 fb->pixel_format,
8002 fb->modifier[0]);
1ad292b5 8003
f37b5c2b 8004 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8005
2844a921
DL		 8006 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8007 pipe_name(pipe), plane, fb->width, fb->height,
8008 fb->bits_per_pixel, base, fb->pitches[0],
8009 plane_config->size);
1ad292b5 8010
2d14030b 8011 plane_config->fb = intel_fb;
1ad292b5
JB		 8012}
8013
70b23a98 8014static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8015 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8016{
8017 struct drm_device *dev = crtc->base.dev;
8018 struct drm_i915_private *dev_priv = dev->dev_private;
8019 int pipe = pipe_config->cpu_transcoder;
8020 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8021 intel_clock_t clock;
8022 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8023 int refclk = 100000;
8024
a580516d 8025 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8026 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8027 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8028 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8029 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8030 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8031
8032 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8033 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8034 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8035 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8036 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8037
dccbea3b 8038 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8039}
8040
0e8ffe1b 8041static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8042 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8043{
8044 struct drm_device *dev = crtc->base.dev;
8045 struct drm_i915_private *dev_priv = dev->dev_private;
8046 uint32_t tmp;
8047
f458ebbc
DV		 8048 if (!intel_display_power_is_enabled(dev_priv,
8049 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8050 return false;
8051
e143a21c 8052 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8053 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8054
0e8ffe1b
DV		 8055 tmp = I915_READ(PIPECONF(crtc->pipe));
8056 if (!(tmp & PIPECONF_ENABLE))
8057 return false;
8058
42571aef
VS		 8059 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8060 switch (tmp & PIPECONF_BPC_MASK) {
8061 case PIPECONF_6BPC:
8062 pipe_config->pipe_bpp = 18;
8063 break;
8064 case PIPECONF_8BPC:
8065 pipe_config->pipe_bpp = 24;
8066 break;
8067 case PIPECONF_10BPC:
8068 pipe_config->pipe_bpp = 30;
8069 break;
8070 default:
8071 break;
8072 }
8073 }
8074
b5a9fa09
DV		 8075 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8076 pipe_config->limited_color_range = true;
8077
282740f7
VS		 8078 if (INTEL_INFO(dev)->gen < 4)
8079 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8080
1bd1bd80
DV		 8081 intel_get_pipe_timings(crtc, pipe_config);
8082
2fa2fe9a
DV		 8083 i9xx_get_pfit_config(crtc, pipe_config);
8084
6c49f241
DV		 8085 if (INTEL_INFO(dev)->gen >= 4) {
8086 tmp = I915_READ(DPLL_MD(crtc->pipe));
8087 pipe_config->pixel_multiplier =
8088 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8089 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8090 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8091 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8092 tmp = I915_READ(DPLL(crtc->pipe));
8093 pipe_config->pixel_multiplier =
8094 ((tmp & SDVO_MULTIPLIER_MASK)
8095 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8096 } else {
8097 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8098 * port and will be fixed up in the encoder->get_config
8099 * function. */
8100 pipe_config->pixel_multiplier = 1;
8101 }
8bcc2795
DV		 8102 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8103 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8104 /*
8105 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8106 * on 830. Filter it out here so that we don't
8107 * report errors due to that.
8108 */
8109 if (IS_I830(dev))
8110 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8111
8bcc2795
DV		 8112 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8113 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8114 } else {
8115 /* Mask out read-only status bits. */
8116 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8117 DPLL_PORTC_READY_MASK |
8118 DPLL_PORTB_READY_MASK);
8bcc2795 8119 }
6c49f241 8120
70b23a98
VS		 8121 if (IS_CHERRYVIEW(dev))
8122 chv_crtc_clock_get(crtc, pipe_config);
8123 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8124 vlv_crtc_clock_get(crtc, pipe_config);
8125 else
8126 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8127
0e8ffe1b
DV		 8128 return true;
8129}
8130
dde86e2d 8131static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8132{
8133 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8134 struct intel_encoder *encoder;
74cfd7ac 8135 u32 val, final;
13d83a67 8136 bool has_lvds = false;
199e5d79 8137 bool has_cpu_edp = false;
199e5d79 8138 bool has_panel = false;
99eb6a01
KP		 8139 bool has_ck505 = false;
8140 bool can_ssc = false;
13d83a67
JB		 8141
8142 /* We need to take the global config into account */
b2784e15 8143 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8144 switch (encoder->type) {
8145 case INTEL_OUTPUT_LVDS:
8146 has_panel = true;
8147 has_lvds = true;
8148 break;
8149 case INTEL_OUTPUT_EDP:
8150 has_panel = true;
2de6905f 8151 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8152 has_cpu_edp = true;
8153 break;
6847d71b
PZ		 8154 default:
8155 break;
13d83a67
JB		 8156 }
8157 }
8158
99eb6a01 8159 if (HAS_PCH_IBX(dev)) {
41aa3448 8160 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8161 can_ssc = has_ck505;
8162 } else {
8163 has_ck505 = false;
8164 can_ssc = true;
8165 }
8166
2de6905f
ID		 8167 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8168 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8169
8170 /* Ironlake: try to setup display ref clock before DPLL
8171 * enabling. This is only under driver's control after
8172 * PCH B stepping, previous chipset stepping should be
8173 * ignoring this setting.
8174 */
74cfd7ac
CW		 8175 val = I915_READ(PCH_DREF_CONTROL);
8176
8177 /* As we must carefully and slowly disable/enable each source in turn,
8178 * compute the final state we want first and check if we need to
8179 * make any changes at all.
8180 */
8181 final = val;
8182 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8183 if (has_ck505)
8184 final |= DREF_NONSPREAD_CK505_ENABLE;
8185 else
8186 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8187
8188 final &= ~DREF_SSC_SOURCE_MASK;
8189 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8190 final &= ~DREF_SSC1_ENABLE;
8191
8192 if (has_panel) {
8193 final |= DREF_SSC_SOURCE_ENABLE;
8194
8195 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8196 final |= DREF_SSC1_ENABLE;
8197
8198 if (has_cpu_edp) {
8199 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8200 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8201 else
8202 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8203 } else
8204 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8205 } else {
8206 final |= DREF_SSC_SOURCE_DISABLE;
8207 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8208 }
8209
8210 if (final == val)
8211 return;
8212
13d83a67 8213 /* Always enable nonspread source */
74cfd7ac 8214 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8215
99eb6a01 8216 if (has_ck505)
74cfd7ac 8217 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8218 else
74cfd7ac 8219 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8220
199e5d79 8221 if (has_panel) {
74cfd7ac
CW		 8222 val &= ~DREF_SSC_SOURCE_MASK;
8223 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8224
199e5d79 8225 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8226 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8227 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8228 val |= DREF_SSC1_ENABLE;
e77166b5 8229 } else
74cfd7ac 8230 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8231
8232 /* Get SSC going before enabling the outputs */
74cfd7ac 8233 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8234 POSTING_READ(PCH_DREF_CONTROL);
8235 udelay(200);
8236
74cfd7ac 8237 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8238
8239 /* Enable CPU source on CPU attached eDP */
199e5d79 8240 if (has_cpu_edp) {
99eb6a01 8241 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8242 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8243 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8244 } else
74cfd7ac 8245 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8246 } else
74cfd7ac 8247 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8248
74cfd7ac 8249 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8250 POSTING_READ(PCH_DREF_CONTROL);
8251 udelay(200);
8252 } else {
8253 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8254
74cfd7ac 8255 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8256
8257 /* Turn off CPU output */
74cfd7ac 8258 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8259
74cfd7ac 8260 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8261 POSTING_READ(PCH_DREF_CONTROL);
8262 udelay(200);
8263
8264 /* Turn off the SSC source */
74cfd7ac
CW		 8265 val &= ~DREF_SSC_SOURCE_MASK;
8266 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8267
8268 /* Turn off SSC1 */
74cfd7ac 8269 val &= ~DREF_SSC1_ENABLE;
199e5d79 8270
74cfd7ac 8271 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8272 POSTING_READ(PCH_DREF_CONTROL);
8273 udelay(200);
8274 }
74cfd7ac
CW		 8275
8276 BUG_ON(val != final);
13d83a67
JB		 8277}
8278
f31f2d55 8279static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8280{
f31f2d55 8281 uint32_t tmp;
dde86e2d 8282
0ff066a9
PZ		 8283 tmp = I915_READ(SOUTH_CHICKEN2);
8284 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8285 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8286
0ff066a9
PZ		 8287 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8288 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8289 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8290
0ff066a9
PZ		 8291 tmp = I915_READ(SOUTH_CHICKEN2);
8292 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8293 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8294
0ff066a9
PZ		 8295 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8296 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8297 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8298}
8299
8300/* WaMPhyProgramming:hsw */
8301static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8302{
8303 uint32_t tmp;
dde86e2d
PZ		 8304
8305 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8306 tmp &= ~(0xFF << 24);
8307 tmp |= (0x12 << 24);
8308 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8309
dde86e2d
PZ		 8310 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8311 tmp |= (1 << 11);
8312 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8313
8314 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8315 tmp |= (1 << 11);
8316 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8317
dde86e2d
PZ		 8318 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8319 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8320 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8321
8322 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8323 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8324 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8325
0ff066a9
PZ		 8326 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8327 tmp &= ~(7 << 13);
8328 tmp |= (5 << 13);
8329 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8330
0ff066a9
PZ		 8331 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8332 tmp &= ~(7 << 13);
8333 tmp |= (5 << 13);
8334 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8335
8336 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8337 tmp &= ~0xFF;
8338 tmp |= 0x1C;
8339 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8340
8341 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8342 tmp &= ~0xFF;
8343 tmp |= 0x1C;
8344 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8345
8346 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8347 tmp &= ~(0xFF << 16);
8348 tmp |= (0x1C << 16);
8349 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8350
8351 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8352 tmp &= ~(0xFF << 16);
8353 tmp |= (0x1C << 16);
8354 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8355
0ff066a9
PZ		 8356 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8357 tmp |= (1 << 27);
8358 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8359
0ff066a9
PZ		 8360 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8361 tmp |= (1 << 27);
8362 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8363
0ff066a9
PZ		 8364 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8365 tmp &= ~(0xF << 28);
8366 tmp |= (4 << 28);
8367 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8368
0ff066a9
PZ		 8369 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8370 tmp &= ~(0xF << 28);
8371 tmp |= (4 << 28);
8372 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8373}
8374
2fa86a1f
PZ		 8375/* Implements 3 different sequences from BSpec chapter "Display iCLK
8376 * Programming" based on the parameters passed:
8377 * - Sequence to enable CLKOUT_DP
8378 * - Sequence to enable CLKOUT_DP without spread
8379 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8380 */
8381static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8382 bool with_fdi)
f31f2d55
PZ		 8383{
8384 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8385 uint32_t reg, tmp;
8386
8387 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8388 with_spread = true;
8389 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8390 with_fdi, "LP PCH doesn't have FDI\n"))
8391 with_fdi = false;
f31f2d55 8392
a580516d 8393 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8394
8395 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8396 tmp &= ~SBI_SSCCTL_DISABLE;
8397 tmp |= SBI_SSCCTL_PATHALT;
8398 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8399
8400 udelay(24);
8401
2fa86a1f
PZ		 8402 if (with_spread) {
8403 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8404 tmp &= ~SBI_SSCCTL_PATHALT;
8405 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8406
2fa86a1f
PZ		 8407 if (with_fdi) {
8408 lpt_reset_fdi_mphy(dev_priv);
8409 lpt_program_fdi_mphy(dev_priv);
8410 }
8411 }
dde86e2d 8412
2fa86a1f
PZ		 8413 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8414 SBI_GEN0 : SBI_DBUFF0;
8415 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8416 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8417 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8418
a580516d 8419 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8420}
8421
47701c3b
PZ		 8422/* Sequence to disable CLKOUT_DP */
8423static void lpt_disable_clkout_dp(struct drm_device *dev)
8424{
8425 struct drm_i915_private *dev_priv = dev->dev_private;
8426 uint32_t reg, tmp;
8427
a580516d 8428 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8429
8430 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8431 SBI_GEN0 : SBI_DBUFF0;
8432 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8433 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8434 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8435
8436 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8437 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8438 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8439 tmp |= SBI_SSCCTL_PATHALT;
8440 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8441 udelay(32);
8442 }
8443 tmp |= SBI_SSCCTL_DISABLE;
8444 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8445 }
8446
a580516d 8447 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8448}
8449
bf8fa3d3
PZ		 8450static void lpt_init_pch_refclk(struct drm_device *dev)
8451{
bf8fa3d3
PZ		 8452 struct intel_encoder *encoder;
8453 bool has_vga = false;
8454
b2784e15 8455 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8456 switch (encoder->type) {
8457 case INTEL_OUTPUT_ANALOG:
8458 has_vga = true;
8459 break;
6847d71b
PZ		 8460 default:
8461 break;
bf8fa3d3
PZ		 8462 }
8463 }
8464
47701c3b
PZ		 8465 if (has_vga)
8466 lpt_enable_clkout_dp(dev, true, true);
8467 else
8468 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8469}
8470
dde86e2d
PZ		 8471/*
8472 * Initialize reference clocks when the driver loads
8473 */
8474void intel_init_pch_refclk(struct drm_device *dev)
8475{
8476 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8477 ironlake_init_pch_refclk(dev);
8478 else if (HAS_PCH_LPT(dev))
8479 lpt_init_pch_refclk(dev);
8480}
8481
55bb9992 8482static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8483{
55bb9992 8484 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8485 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8486 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8487 struct drm_connector *connector;
55bb9992 8488 struct drm_connector_state *connector_state;
d9d444cb 8489 struct intel_encoder *encoder;
55bb9992 8490 int num_connectors = 0, i;
d9d444cb
JB		 8491 bool is_lvds = false;
8492
da3ced29 8493 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8494 if (connector_state->crtc != crtc_state->base.crtc)
8495 continue;
8496
8497 encoder = to_intel_encoder(connector_state->best_encoder);
8498
d9d444cb
JB		 8499 switch (encoder->type) {
8500 case INTEL_OUTPUT_LVDS:
8501 is_lvds = true;
8502 break;
6847d71b
PZ		 8503 default:
8504 break;
d9d444cb
JB		 8505 }
8506 num_connectors++;
8507 }
8508
8509 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8510 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8511 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8512 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8513 }
8514
8515 return 120000;
8516}
8517
6ff93609 8518static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8519{
c8203565 8520 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8522 int pipe = intel_crtc->pipe;
c8203565
PZ		 8523 uint32_t val;
8524
78114071 8525 val = 0;
c8203565 8526
6e3c9717 8527 switch (intel_crtc->config->pipe_bpp) {
c8203565 8528 case 18:
dfd07d72 8529 val |= PIPECONF_6BPC;
c8203565
PZ		 8530 break;
8531 case 24:
dfd07d72 8532 val |= PIPECONF_8BPC;
c8203565
PZ		 8533 break;
8534 case 30:
dfd07d72 8535 val |= PIPECONF_10BPC;
c8203565
PZ		 8536 break;
8537 case 36:
dfd07d72 8538 val |= PIPECONF_12BPC;
c8203565
PZ		 8539 break;
8540 default:
cc769b62
PZ		 8541 /* Case prevented by intel_choose_pipe_bpp_dither. */
8542 BUG();
c8203565
PZ		 8543 }
8544
6e3c9717 8545 if (intel_crtc->config->dither)
c8203565
PZ		 8546 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8547
6e3c9717 8548 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8549 val |= PIPECONF_INTERLACED_ILK;
8550 else
8551 val |= PIPECONF_PROGRESSIVE;
8552
6e3c9717 8553 if (intel_crtc->config->limited_color_range)
3685a8f3 8554 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8555
c8203565
PZ		 8556 I915_WRITE(PIPECONF(pipe), val);
8557 POSTING_READ(PIPECONF(pipe));
8558}
8559
86d3efce
VS		 8560/*
8561 * Set up the pipe CSC unit.
8562 *
8563 * Currently only full range RGB to limited range RGB conversion
8564 * is supported, but eventually this should handle various
8565 * RGB<->YCbCr scenarios as well.
8566 */
50f3b016 8567static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8568{
8569 struct drm_device *dev = crtc->dev;
8570 struct drm_i915_private *dev_priv = dev->dev_private;
8571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8572 int pipe = intel_crtc->pipe;
8573 uint16_t coeff = 0x7800; /* 1.0 */
8574
8575 /*
8576 * TODO: Check what kind of values actually come out of the pipe
8577 * with these coeff/postoff values and adjust to get the best
8578 * accuracy. Perhaps we even need to take the bpc value into
8579 * consideration.
8580 */
8581
6e3c9717 8582 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8583 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8584
8585 /*
8586 * GY/GU and RY/RU should be the other way around according
8587 * to BSpec, but reality doesn't agree. Just set them up in
8588 * a way that results in the correct picture.
8589 */
8590 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8591 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8592
8593 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8594 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8595
8596 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8597 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8598
8599 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8600 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8601 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8602
8603 if (INTEL_INFO(dev)->gen > 6) {
8604 uint16_t postoff = 0;
8605
6e3c9717 8606 if (intel_crtc->config->limited_color_range)
32cf0cb0 8607 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8608
8609 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8610 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8611 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8612
8613 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8614 } else {
8615 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8616
6e3c9717 8617 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8618 mode |= CSC_BLACK_SCREEN_OFFSET;
8619
8620 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8621 }
8622}
8623
6ff93609 8624static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8625{
756f85cf
PZ		 8626 struct drm_device *dev = crtc->dev;
8627 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8629 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8630 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8631 uint32_t val;
8632
3eff4faa 8633 val = 0;
ee2b0b38 8634
6e3c9717 8635 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8636 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8637
6e3c9717 8638 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8639 val |= PIPECONF_INTERLACED_ILK;
8640 else
8641 val |= PIPECONF_PROGRESSIVE;
8642
702e7a56
PZ		 8643 I915_WRITE(PIPECONF(cpu_transcoder), val);
8644 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8645
8646 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8647 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8648
3cdf122c 8649 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8650 val = 0;
8651
6e3c9717 8652 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8653 case 18:
8654 val |= PIPEMISC_DITHER_6_BPC;
8655 break;
8656 case 24:
8657 val |= PIPEMISC_DITHER_8_BPC;
8658 break;
8659 case 30:
8660 val |= PIPEMISC_DITHER_10_BPC;
8661 break;
8662 case 36:
8663 val |= PIPEMISC_DITHER_12_BPC;
8664 break;
8665 default:
8666 /* Case prevented by pipe_config_set_bpp. */
8667 BUG();
8668 }
8669
6e3c9717 8670 if (intel_crtc->config->dither)
756f85cf
PZ		 8671 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8672
8673 I915_WRITE(PIPEMISC(pipe), val);
8674 }
ee2b0b38
PZ		 8675}
8676
6591c6e4 8677static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8678 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8679 intel_clock_t *clock,
8680 bool *has_reduced_clock,
8681 intel_clock_t *reduced_clock)
8682{
8683 struct drm_device *dev = crtc->dev;
8684 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8685 int refclk;
d4906093 8686 const intel_limit_t *limit;
c329a4ec 8687 bool ret;
79e53945 8688
55bb9992 8689 refclk = ironlake_get_refclk(crtc_state);
79e53945 8690
d4906093
ML		 8691 /*
8692 * Returns a set of divisors for the desired target clock with the given
8693 * refclk, or FALSE. The returned values represent the clock equation:
8694 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8695 */
a93e255f
ACO		 8696 limit = intel_limit(crtc_state, refclk);
8697 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8698 crtc_state->port_clock,
ee9300bb 8699 refclk, NULL, clock);
6591c6e4
PZ		 8700 if (!ret)
8701 return false;
cda4b7d3 8702
6591c6e4
PZ		 8703 return true;
8704}
8705
d4b1931c
PZ		 8706int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8707{
8708 /*
8709 * Account for spread spectrum to avoid
8710 * oversubscribing the link. Max center spread
8711 * is 2.5%; use 5% for safety's sake.
8712 */
8713 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8714 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8715}
8716
7429e9d4 8717static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8718{
7429e9d4 8719 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8720}
8721
de13a2e3 8722static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8723 struct intel_crtc_state *crtc_state,
7429e9d4 8724 u32 *fp,
9a7c7890 8725 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8726{
de13a2e3 8727 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8728 struct drm_device *dev = crtc->dev;
8729 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8730 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8731 struct drm_connector *connector;
55bb9992
ACO		 8732 struct drm_connector_state *connector_state;
8733 struct intel_encoder *encoder;
de13a2e3 8734 uint32_t dpll;
55bb9992 8735 int factor, num_connectors = 0, i;
09ede541 8736 bool is_lvds = false, is_sdvo = false;
79e53945 8737
da3ced29 8738 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8739 if (connector_state->crtc != crtc_state->base.crtc)
8740 continue;
8741
8742 encoder = to_intel_encoder(connector_state->best_encoder);
8743
8744 switch (encoder->type) {
79e53945
JB		 8745 case INTEL_OUTPUT_LVDS:
8746 is_lvds = true;
8747 break;
8748 case INTEL_OUTPUT_SDVO:
7d57382e 8749 case INTEL_OUTPUT_HDMI:
79e53945 8750 is_sdvo = true;
79e53945 8751 break;
6847d71b
PZ		 8752 default:
8753 break;
79e53945 8754 }
43565a06 8755
c751ce4f 8756 num_connectors++;
79e53945 8757 }
79e53945 8758
c1858123 8759 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8760 factor = 21;
8761 if (is_lvds) {
8762 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8763 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8764 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8765 factor = 25;
190f68c5 8766 } else if (crtc_state->sdvo_tv_clock)
8febb297 8767 factor = 20;
c1858123 8768
190f68c5 8769 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8770 *fp |= FP_CB_TUNE;
2c07245f 8771
9a7c7890
DV		 8772 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8773 *fp2 |= FP_CB_TUNE;
8774
5eddb70b 8775 dpll = 0;
2c07245f 8776
a07d6787
EA		 8777 if (is_lvds)
8778 dpll |= DPLLB_MODE_LVDS;
8779 else
8780 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8781
190f68c5 8782 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8783 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8784
8785 if (is_sdvo)
4a33e48d 8786 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8787 if (crtc_state->has_dp_encoder)
4a33e48d 8788 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8789
a07d6787 8790 /* compute bitmask from p1 value */
190f68c5 8791 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8792 /* also FPA1 */
190f68c5 8793 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8794
190f68c5 8795 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8796 case 5:
8797 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8798 break;
8799 case 7:
8800 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8801 break;
8802 case 10:
8803 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8804 break;
8805 case 14:
8806 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8807 break;
79e53945
JB		 8808 }
8809
b4c09f3b 8810 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8811 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8812 else
8813 dpll |= PLL_REF_INPUT_DREFCLK;
8814
959e16d6 8815 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8816}
8817
190f68c5
ACO		 8818static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8819 struct intel_crtc_state *crtc_state)
de13a2e3 8820{
c7653199 8821 struct drm_device *dev = crtc->base.dev;
de13a2e3 8822 intel_clock_t clock, reduced_clock;
cbbab5bd 8823 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8824 bool ok, has_reduced_clock = false;
8b47047b 8825 bool is_lvds = false;
e2b78267 8826 struct intel_shared_dpll *pll;
de13a2e3 8827
dd3cd74a
ACO		 8828 memset(&crtc_state->dpll_hw_state, 0,
8829 sizeof(crtc_state->dpll_hw_state));
8830
409ee761 8831 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8832
5dc5298b
PZ		 8833 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8834 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8835
190f68c5 8836 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8837 &has_reduced_clock, &reduced_clock);
190f68c5 8838 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8839 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8840 return -EINVAL;
79e53945 8841 }
f47709a9 8842 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8843 if (!crtc_state->clock_set) {
8844 crtc_state->dpll.n = clock.n;
8845 crtc_state->dpll.m1 = clock.m1;
8846 crtc_state->dpll.m2 = clock.m2;
8847 crtc_state->dpll.p1 = clock.p1;
8848 crtc_state->dpll.p2 = clock.p2;
f47709a9 8849 }
79e53945 8850
5dc5298b 8851 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8852 if (crtc_state->has_pch_encoder) {
8853 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8854 if (has_reduced_clock)
7429e9d4 8855 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8856
190f68c5 8857 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8858 &fp, &reduced_clock,
8859 has_reduced_clock ? &fp2 : NULL);
8860
190f68c5
ACO		 8861 crtc_state->dpll_hw_state.dpll = dpll;
8862 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8863 if (has_reduced_clock)
190f68c5 8864 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8865 else
190f68c5 8866 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8867
190f68c5 8868 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8869 if (pll == NULL) {
84f44ce7 8870 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8871 pipe_name(crtc->pipe));
4b645f14
JB		 8872 return -EINVAL;
8873 }
3fb37703 8874 }
79e53945 8875
ab585dea 8876 if (is_lvds && has_reduced_clock)
c7653199 8877 crtc->lowfreq_avail = true;
bcd644e0 8878 else
c7653199 8879 crtc->lowfreq_avail = false;
e2b78267 8880
c8f7a0db 8881 return 0;
79e53945
JB		 8882}
8883
eb14cb74
VS		 8884static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8885 struct intel_link_m_n *m_n)
8886{
8887 struct drm_device *dev = crtc->base.dev;
8888 struct drm_i915_private *dev_priv = dev->dev_private;
8889 enum pipe pipe = crtc->pipe;
8890
8891 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8892 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8893 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8894 & ~TU_SIZE_MASK;
8895 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8896 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8897 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8898}
8899
8900static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8901 enum transcoder transcoder,
b95af8be
VK		 8902 struct intel_link_m_n *m_n,
8903 struct intel_link_m_n *m2_n2)
72419203
DV		 8904{
8905 struct drm_device *dev = crtc->base.dev;
8906 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8907 enum pipe pipe = crtc->pipe;
72419203 8908
eb14cb74
VS		 8909 if (INTEL_INFO(dev)->gen >= 5) {
8910 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8911 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8912 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8913 & ~TU_SIZE_MASK;
8914 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8915 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8916 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8917 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8918 * gen < 8) and if DRRS is supported (to make sure the
8919 * registers are not unnecessarily read).
8920 */
8921 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8922 crtc->config->has_drrs) {
b95af8be
VK		 8923 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8924 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8925 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8926 & ~TU_SIZE_MASK;
8927 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8928 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8929 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8930 }
eb14cb74
VS		 8931 } else {
8932 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8933 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8934 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8935 & ~TU_SIZE_MASK;
8936 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8937 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8938 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8939 }
8940}
8941
8942void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8943 struct intel_crtc_state *pipe_config)
eb14cb74 8944{
681a8504 8945 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8946 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8947 else
8948 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8949 &pipe_config->dp_m_n,
8950 &pipe_config->dp_m2_n2);
eb14cb74 8951}
72419203 8952
eb14cb74 8953static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8954 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8955{
8956 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8957 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8958}
8959
bd2e244f 8960static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8961 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8962{
8963 struct drm_device *dev = crtc->base.dev;
8964 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8965 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8966 uint32_t ps_ctrl = 0;
8967 int id = -1;
8968 int i;
bd2e244f 8969
a1b2278e
CK		 8970 /* find scaler attached to this pipe */
8971 for (i = 0; i < crtc->num_scalers; i++) {
8972 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8973 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8974 id = i;
8975 pipe_config->pch_pfit.enabled = true;
8976 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8977 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8978 break;
8979 }
8980 }
bd2e244f 8981
a1b2278e
CK		 8982 scaler_state->scaler_id = id;
8983 if (id >= 0) {
8984 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8985 } else {
8986 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8987 }
8988}
8989
5724dbd1
DL		 8990static void
8991skylake_get_initial_plane_config(struct intel_crtc *crtc,
8992 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8993{
8994 struct drm_device *dev = crtc->base.dev;
8995 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8996 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8997 int pipe = crtc->pipe;
8998 int fourcc, pixel_format;
6761dd31 8999 unsigned int aligned_height;
bc8d7dff 9000 struct drm_framebuffer *fb;
1b842c89 9001 struct intel_framebuffer *intel_fb;
bc8d7dff 9002
d9806c9f 9003 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9004 if (!intel_fb) {
bc8d7dff
DL		 9005 DRM_DEBUG_KMS("failed to alloc fb\n");
9006 return;
9007 }
9008
1b842c89
DL		 9009 fb = &intel_fb->base;
9010
bc8d7dff 9011 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9012 if (!(val & PLANE_CTL_ENABLE))
9013 goto error;
9014
bc8d7dff
DL		 9015 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9016 fourcc = skl_format_to_fourcc(pixel_format,
9017 val & PLANE_CTL_ORDER_RGBX,
9018 val & PLANE_CTL_ALPHA_MASK);
9019 fb->pixel_format = fourcc;
9020 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9021
40f46283
DL		 9022 tiling = val & PLANE_CTL_TILED_MASK;
9023 switch (tiling) {
9024 case PLANE_CTL_TILED_LINEAR:
9025 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9026 break;
9027 case PLANE_CTL_TILED_X:
9028 plane_config->tiling = I915_TILING_X;
9029 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9030 break;
9031 case PLANE_CTL_TILED_Y:
9032 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9033 break;
9034 case PLANE_CTL_TILED_YF:
9035 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9036 break;
9037 default:
9038 MISSING_CASE(tiling);
9039 goto error;
9040 }
9041
bc8d7dff
DL		 9042 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9043 plane_config->base = base;
9044
9045 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9046
9047 val = I915_READ(PLANE_SIZE(pipe, 0));
9048 fb->height = ((val >> 16) & 0xfff) + 1;
9049 fb->width = ((val >> 0) & 0x1fff) + 1;
9050
9051 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9052 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9053 fb->pixel_format);
bc8d7dff
DL		 9054 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9055
9056 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9057 fb->pixel_format,
9058 fb->modifier[0]);
bc8d7dff 9059
f37b5c2b 9060 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9061
9062 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9063 pipe_name(pipe), fb->width, fb->height,
9064 fb->bits_per_pixel, base, fb->pitches[0],
9065 plane_config->size);
9066
2d14030b 9067 plane_config->fb = intel_fb;
bc8d7dff
DL		 9068 return;
9069
9070error:
9071 kfree(fb);
9072}
9073
2fa2fe9a 9074static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9075 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9076{
9077 struct drm_device *dev = crtc->base.dev;
9078 struct drm_i915_private *dev_priv = dev->dev_private;
9079 uint32_t tmp;
9080
9081 tmp = I915_READ(PF_CTL(crtc->pipe));
9082
9083 if (tmp & PF_ENABLE) {
fd4daa9c 9084 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9085 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9086 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9087
9088 /* We currently do not free assignements of panel fitters on
9089 * ivb/hsw (since we don't use the higher upscaling modes which
9090 * differentiates them) so just WARN about this case for now. */
9091 if (IS_GEN7(dev)) {
9092 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9093 PF_PIPE_SEL_IVB(crtc->pipe));
9094 }
2fa2fe9a 9095 }
79e53945
JB		 9096}
9097
5724dbd1
DL		 9098static void
9099ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9100 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9101{
9102 struct drm_device *dev = crtc->base.dev;
9103 struct drm_i915_private *dev_priv = dev->dev_private;
9104 u32 val, base, offset;
aeee5a49 9105 int pipe = crtc->pipe;
4c6baa59 9106 int fourcc, pixel_format;
6761dd31 9107 unsigned int aligned_height;
b113d5ee 9108 struct drm_framebuffer *fb;
1b842c89 9109 struct intel_framebuffer *intel_fb;
4c6baa59 9110
42a7b088
DL		 9111 val = I915_READ(DSPCNTR(pipe));
9112 if (!(val & DISPLAY_PLANE_ENABLE))
9113 return;
9114
d9806c9f 9115 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9116 if (!intel_fb) {
4c6baa59
JB		 9117 DRM_DEBUG_KMS("failed to alloc fb\n");
9118 return;
9119 }
9120
1b842c89
DL		 9121 fb = &intel_fb->base;
9122
18c5247e
DV		 9123 if (INTEL_INFO(dev)->gen >= 4) {
9124 if (val & DISPPLANE_TILED) {
49af449b 9125 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9126 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9127 }
9128 }
4c6baa59
JB		 9129
9130 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9131 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9132 fb->pixel_format = fourcc;
9133 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9134
aeee5a49 9135 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9136 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9137 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9138 } else {
49af449b 9139 if (plane_config->tiling)
aeee5a49 9140 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9141 else
aeee5a49 9142 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9143 }
9144 plane_config->base = base;
9145
9146 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9147 fb->width = ((val >> 16) & 0xfff) + 1;
9148 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9149
9150 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9151 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9152
b113d5ee 9153 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9154 fb->pixel_format,
9155 fb->modifier[0]);
4c6baa59 9156
f37b5c2b 9157 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9158
2844a921
DL		 9159 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9160 pipe_name(pipe), fb->width, fb->height,
9161 fb->bits_per_pixel, base, fb->pitches[0],
9162 plane_config->size);
b113d5ee 9163
2d14030b 9164 plane_config->fb = intel_fb;
4c6baa59
JB		 9165}
9166
0e8ffe1b 9167static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9168 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9169{
9170 struct drm_device *dev = crtc->base.dev;
9171 struct drm_i915_private *dev_priv = dev->dev_private;
9172 uint32_t tmp;
9173
f458ebbc
DV		 9174 if (!intel_display_power_is_enabled(dev_priv,
9175 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9176 return false;
9177
e143a21c 9178 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9179 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9180
0e8ffe1b
DV		 9181 tmp = I915_READ(PIPECONF(crtc->pipe));
9182 if (!(tmp & PIPECONF_ENABLE))
9183 return false;
9184
42571aef
VS		 9185 switch (tmp & PIPECONF_BPC_MASK) {
9186 case PIPECONF_6BPC:
9187 pipe_config->pipe_bpp = 18;
9188 break;
9189 case PIPECONF_8BPC:
9190 pipe_config->pipe_bpp = 24;
9191 break;
9192 case PIPECONF_10BPC:
9193 pipe_config->pipe_bpp = 30;
9194 break;
9195 case PIPECONF_12BPC:
9196 pipe_config->pipe_bpp = 36;
9197 break;
9198 default:
9199 break;
9200 }
9201
b5a9fa09
DV		 9202 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9203 pipe_config->limited_color_range = true;
9204
ab9412ba 9205 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9206 struct intel_shared_dpll *pll;
9207
88adfff1
DV		 9208 pipe_config->has_pch_encoder = true;
9209
627eb5a3
DV		 9210 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9211 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9212 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9213
9214 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9215
c0d43d62 9216 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9217 pipe_config->shared_dpll =
9218 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9219 } else {
9220 tmp = I915_READ(PCH_DPLL_SEL);
9221 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9222 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9223 else
9224 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9225 }
66e985c0
DV		 9226
9227 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9228
9229 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9230 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9231
9232 tmp = pipe_config->dpll_hw_state.dpll;
9233 pipe_config->pixel_multiplier =
9234 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9235 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9236
9237 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9238 } else {
9239 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9240 }
9241
1bd1bd80
DV		 9242 intel_get_pipe_timings(crtc, pipe_config);
9243
2fa2fe9a
DV		 9244 ironlake_get_pfit_config(crtc, pipe_config);
9245
0e8ffe1b
DV		 9246 return true;
9247}
9248
be256dc7
PZ		 9249static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9250{
9251 struct drm_device *dev = dev_priv->dev;
be256dc7 9252 struct intel_crtc *crtc;
be256dc7 9253
d3fcc808 9254 for_each_intel_crtc(dev, crtc)
e2c719b7 9255 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9256 pipe_name(crtc->pipe));
9257
e2c719b7
RC		 9258 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9259 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9260 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9261 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9262 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9263 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9264 "CPU PWM1 enabled\n");
c5107b87 9265 if (IS_HASWELL(dev))
e2c719b7 9266 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9267 "CPU PWM2 enabled\n");
e2c719b7 9268 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9269 "PCH PWM1 enabled\n");
e2c719b7 9270 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9271 "Utility pin enabled\n");
e2c719b7 9272 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9273
9926ada1
PZ		 9274 /*
9275 * In theory we can still leave IRQs enabled, as long as only the HPD
9276 * interrupts remain enabled. We used to check for that, but since it's
9277 * gen-specific and since we only disable LCPLL after we fully disable
9278 * the interrupts, the check below should be enough.
9279 */
e2c719b7 9280 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9281}
9282
9ccd5aeb
PZ		 9283static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9284{
9285 struct drm_device *dev = dev_priv->dev;
9286
9287 if (IS_HASWELL(dev))
9288 return I915_READ(D_COMP_HSW);
9289 else
9290 return I915_READ(D_COMP_BDW);
9291}
9292
3c4c9b81
PZ		 9293static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9294{
9295 struct drm_device *dev = dev_priv->dev;
9296
9297 if (IS_HASWELL(dev)) {
9298 mutex_lock(&dev_priv->rps.hw_lock);
9299 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9300 val))
f475dadf 9301 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9302 mutex_unlock(&dev_priv->rps.hw_lock);
9303 } else {
9ccd5aeb
PZ		 9304 I915_WRITE(D_COMP_BDW, val);
9305 POSTING_READ(D_COMP_BDW);
3c4c9b81 9306 }
be256dc7
PZ		 9307}
9308
9309/*
9310 * This function implements pieces of two sequences from BSpec:
9311 * - Sequence for display software to disable LCPLL
9312 * - Sequence for display software to allow package C8+
9313 * The steps implemented here are just the steps that actually touch the LCPLL
9314 * register. Callers should take care of disabling all the display engine
9315 * functions, doing the mode unset, fixing interrupts, etc.
9316 */
6ff58d53
PZ		 9317static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9318 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9319{
9320 uint32_t val;
9321
9322 assert_can_disable_lcpll(dev_priv);
9323
9324 val = I915_READ(LCPLL_CTL);
9325
9326 if (switch_to_fclk) {
9327 val |= LCPLL_CD_SOURCE_FCLK;
9328 I915_WRITE(LCPLL_CTL, val);
9329
9330 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9331 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9332 DRM_ERROR("Switching to FCLK failed\n");
9333
9334 val = I915_READ(LCPLL_CTL);
9335 }
9336
9337 val |= LCPLL_PLL_DISABLE;
9338 I915_WRITE(LCPLL_CTL, val);
9339 POSTING_READ(LCPLL_CTL);
9340
9341 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9342 DRM_ERROR("LCPLL still locked\n");
9343
9ccd5aeb 9344 val = hsw_read_dcomp(dev_priv);
be256dc7 9345 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9346 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9347 ndelay(100);
9348
9ccd5aeb
PZ		 9349 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9350 1))
be256dc7
PZ		 9351 DRM_ERROR("D_COMP RCOMP still in progress\n");
9352
9353 if (allow_power_down) {
9354 val = I915_READ(LCPLL_CTL);
9355 val |= LCPLL_POWER_DOWN_ALLOW;
9356 I915_WRITE(LCPLL_CTL, val);
9357 POSTING_READ(LCPLL_CTL);
9358 }
9359}
9360
9361/*
9362 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9363 * source.
9364 */
6ff58d53 9365static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9366{
9367 uint32_t val;
9368
9369 val = I915_READ(LCPLL_CTL);
9370
9371 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9372 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9373 return;
9374
a8a8bd54
PZ		 9375 /*
9376 * Make sure we're not on PC8 state before disabling PC8, otherwise
9377 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9378 */
59bad947 9379 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9380
be256dc7
PZ		 9381 if (val & LCPLL_POWER_DOWN_ALLOW) {
9382 val &= ~LCPLL_POWER_DOWN_ALLOW;
9383 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9384 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9385 }
9386
9ccd5aeb 9387 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9388 val |= D_COMP_COMP_FORCE;
9389 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9390 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9391
9392 val = I915_READ(LCPLL_CTL);
9393 val &= ~LCPLL_PLL_DISABLE;
9394 I915_WRITE(LCPLL_CTL, val);
9395
9396 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9397 DRM_ERROR("LCPLL not locked yet\n");
9398
9399 if (val & LCPLL_CD_SOURCE_FCLK) {
9400 val = I915_READ(LCPLL_CTL);
9401 val &= ~LCPLL_CD_SOURCE_FCLK;
9402 I915_WRITE(LCPLL_CTL, val);
9403
9404 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9405 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9406 DRM_ERROR("Switching back to LCPLL failed\n");
9407 }
215733fa 9408
59bad947 9409 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9410 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9411}
9412
765dab67
PZ		 9413/*
9414 * Package states C8 and deeper are really deep PC states that can only be
9415 * reached when all the devices on the system allow it, so even if the graphics
9416 * device allows PC8+, it doesn't mean the system will actually get to these
9417 * states. Our driver only allows PC8+ when going into runtime PM.
9418 *
9419 * The requirements for PC8+ are that all the outputs are disabled, the power
9420 * well is disabled and most interrupts are disabled, and these are also
9421 * requirements for runtime PM. When these conditions are met, we manually do
9422 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9423 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9424 * hang the machine.
9425 *
9426 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9427 * the state of some registers, so when we come back from PC8+ we need to
9428 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9429 * need to take care of the registers kept by RC6. Notice that this happens even
9430 * if we don't put the device in PCI D3 state (which is what currently happens
9431 * because of the runtime PM support).
9432 *
9433 * For more, read "Display Sequences for Package C8" on the hardware
9434 * documentation.
9435 */
a14cb6fc 9436void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9437{
c67a470b
PZ		 9438 struct drm_device *dev = dev_priv->dev;
9439 uint32_t val;
9440
c67a470b
PZ		 9441 DRM_DEBUG_KMS("Enabling package C8+\n");
9442
c67a470b
PZ		 9443 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9444 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9445 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9446 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9447 }
9448
9449 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9450 hsw_disable_lcpll(dev_priv, true, true);
9451}
9452
a14cb6fc 9453void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9454{
9455 struct drm_device *dev = dev_priv->dev;
9456 uint32_t val;
9457
c67a470b
PZ		 9458 DRM_DEBUG_KMS("Disabling package C8+\n");
9459
9460 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9461 lpt_init_pch_refclk(dev);
9462
9463 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9464 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9465 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9466 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9467 }
9468
9469 intel_prepare_ddi(dev);
c67a470b
PZ		 9470}
9471
27c329ed 9472static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9473{
a821fc46 9474 struct drm_device *dev = old_state->dev;
27c329ed 9475 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9476
27c329ed 9477 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9478}
9479
b432e5cf 9480/* compute the max rate for new configuration */
27c329ed 9481static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9482{
b432e5cf 9483 struct intel_crtc *intel_crtc;
27c329ed 9484 struct intel_crtc_state *crtc_state;
b432e5cf 9485 int max_pixel_rate = 0;
b432e5cf 9486
27c329ed
ML		 9487 for_each_intel_crtc(state->dev, intel_crtc) {
9488 int pixel_rate;
9489
9490 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9491 if (IS_ERR(crtc_state))
9492 return PTR_ERR(crtc_state);
9493
9494 if (!crtc_state->base.enable)
b432e5cf
VS		 9495 continue;
9496
27c329ed 9497 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9498
9499 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9500 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9501 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9502
9503 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9504 }
9505
9506 return max_pixel_rate;
9507}
9508
9509static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9510{
9511 struct drm_i915_private *dev_priv = dev->dev_private;
9512 uint32_t val, data;
9513 int ret;
9514
9515 if (WARN((I915_READ(LCPLL_CTL) &
9516 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9517 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9518 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9519 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9520 "trying to change cdclk frequency with cdclk not enabled\n"))
9521 return;
9522
9523 mutex_lock(&dev_priv->rps.hw_lock);
9524 ret = sandybridge_pcode_write(dev_priv,
9525 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9526 mutex_unlock(&dev_priv->rps.hw_lock);
9527 if (ret) {
9528 DRM_ERROR("failed to inform pcode about cdclk change\n");
9529 return;
9530 }
9531
9532 val = I915_READ(LCPLL_CTL);
9533 val |= LCPLL_CD_SOURCE_FCLK;
9534 I915_WRITE(LCPLL_CTL, val);
9535
9536 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9537 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9538 DRM_ERROR("Switching to FCLK failed\n");
9539
9540 val = I915_READ(LCPLL_CTL);
9541 val &= ~LCPLL_CLK_FREQ_MASK;
9542
9543 switch (cdclk) {
9544 case 450000:
9545 val |= LCPLL_CLK_FREQ_450;
9546 data = 0;
9547 break;
9548 case 540000:
9549 val |= LCPLL_CLK_FREQ_54O_BDW;
9550 data = 1;
9551 break;
9552 case 337500:
9553 val |= LCPLL_CLK_FREQ_337_5_BDW;
9554 data = 2;
9555 break;
9556 case 675000:
9557 val |= LCPLL_CLK_FREQ_675_BDW;
9558 data = 3;
9559 break;
9560 default:
9561 WARN(1, "invalid cdclk frequency\n");
9562 return;
9563 }
9564
9565 I915_WRITE(LCPLL_CTL, val);
9566
9567 val = I915_READ(LCPLL_CTL);
9568 val &= ~LCPLL_CD_SOURCE_FCLK;
9569 I915_WRITE(LCPLL_CTL, val);
9570
9571 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9572 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9573 DRM_ERROR("Switching back to LCPLL failed\n");
9574
9575 mutex_lock(&dev_priv->rps.hw_lock);
9576 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9577 mutex_unlock(&dev_priv->rps.hw_lock);
9578
9579 intel_update_cdclk(dev);
9580
9581 WARN(cdclk != dev_priv->cdclk_freq,
9582 "cdclk requested %d kHz but got %d kHz\n",
9583 cdclk, dev_priv->cdclk_freq);
9584}
9585
27c329ed 9586static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9587{
27c329ed
ML		 9588 struct drm_i915_private *dev_priv = to_i915(state->dev);
9589 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9590 int cdclk;
9591
9592 /*
9593 * FIXME should also account for plane ratio
9594 * once 64bpp pixel formats are supported.
9595 */
27c329ed 9596 if (max_pixclk > 540000)
b432e5cf 9597 cdclk = 675000;
27c329ed 9598 else if (max_pixclk > 450000)
b432e5cf 9599 cdclk = 540000;
27c329ed 9600 else if (max_pixclk > 337500)
b432e5cf
VS		 9601 cdclk = 450000;
9602 else
9603 cdclk = 337500;
9604
9605 /*
9606 * FIXME move the cdclk caclulation to
9607 * compute_config() so we can fail gracegully.
9608 */
9609 if (cdclk > dev_priv->max_cdclk_freq) {
9610 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9611 cdclk, dev_priv->max_cdclk_freq);
9612 cdclk = dev_priv->max_cdclk_freq;
9613 }
9614
27c329ed 9615 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9616
9617 return 0;
9618}
9619
27c329ed 9620static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9621{
27c329ed
ML		 9622 struct drm_device *dev = old_state->dev;
9623 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9624
27c329ed 9625 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9626}
9627
190f68c5
ACO		 9628static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9629 struct intel_crtc_state *crtc_state)
09b4ddf9 9630{
190f68c5 9631 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9632 return -EINVAL;
716c2e55 9633
c7653199 9634 crtc->lowfreq_avail = false;
644cef34 9635
c8f7a0db 9636 return 0;
79e53945
JB		 9637}
9638
3760b59c
S		 9639static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9640 enum port port,
9641 struct intel_crtc_state *pipe_config)
9642{
9643 switch (port) {
9644 case PORT_A:
9645 pipe_config->ddi_pll_sel = SKL_DPLL0;
9646 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9647 break;
9648 case PORT_B:
9649 pipe_config->ddi_pll_sel = SKL_DPLL1;
9650 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9651 break;
9652 case PORT_C:
9653 pipe_config->ddi_pll_sel = SKL_DPLL2;
9654 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9655 break;
9656 default:
9657 DRM_ERROR("Incorrect port type\n");
9658 }
9659}
9660
96b7dfb7
S		 9661static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9662 enum port port,
5cec258b 9663 struct intel_crtc_state *pipe_config)
96b7dfb7 9664{
3148ade7 9665 u32 temp, dpll_ctl1;
96b7dfb7
S		 9666
9667 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9668 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9669
9670 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9671 case SKL_DPLL0:
9672 /*
9673 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9674 * of the shared DPLL framework and thus needs to be read out
9675 * separately
9676 */
9677 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9678 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9679 break;
96b7dfb7
S		 9680 case SKL_DPLL1:
9681 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9682 break;
9683 case SKL_DPLL2:
9684 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9685 break;
9686 case SKL_DPLL3:
9687 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9688 break;
96b7dfb7
S		 9689 }
9690}
9691
7d2c8175
DL		 9692static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9693 enum port port,
5cec258b 9694 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9695{
9696 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9697
9698 switch (pipe_config->ddi_pll_sel) {
9699 case PORT_CLK_SEL_WRPLL1:
9700 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9701 break;
9702 case PORT_CLK_SEL_WRPLL2:
9703 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9704 break;
9705 }
9706}
9707
26804afd 9708static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9709 struct intel_crtc_state *pipe_config)
26804afd
DV		 9710{
9711 struct drm_device *dev = crtc->base.dev;
9712 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9713 struct intel_shared_dpll *pll;
26804afd
DV		 9714 enum port port;
9715 uint32_t tmp;
9716
9717 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9718
9719 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9720
96b7dfb7
S		 9721 if (IS_SKYLAKE(dev))
9722 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9723 else if (IS_BROXTON(dev))
9724 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9725 else
9726 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9727
d452c5b6
DV		 9728 if (pipe_config->shared_dpll >= 0) {
9729 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9730
9731 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9732 &pipe_config->dpll_hw_state));
9733 }
9734
26804afd
DV		 9735 /*
9736 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9737 * DDI E. So just check whether this pipe is wired to DDI E and whether
9738 * the PCH transcoder is on.
9739 */
ca370455
DL		 9740 if (INTEL_INFO(dev)->gen < 9 &&
9741 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9742 pipe_config->has_pch_encoder = true;
9743
9744 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9745 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9746 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9747
9748 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9749 }
9750}
9751
0e8ffe1b 9752static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9753 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9754{
9755 struct drm_device *dev = crtc->base.dev;
9756 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9757 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9758 uint32_t tmp;
9759
f458ebbc 9760 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9761 POWER_DOMAIN_PIPE(crtc->pipe)))
9762 return false;
9763
e143a21c 9764 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9765 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9766
eccb140b
DV		 9767 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9768 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9769 enum pipe trans_edp_pipe;
9770 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9771 default:
9772 WARN(1, "unknown pipe linked to edp transcoder\n");
9773 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9774 case TRANS_DDI_EDP_INPUT_A_ON:
9775 trans_edp_pipe = PIPE_A;
9776 break;
9777 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9778 trans_edp_pipe = PIPE_B;
9779 break;
9780 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9781 trans_edp_pipe = PIPE_C;
9782 break;
9783 }
9784
9785 if (trans_edp_pipe == crtc->pipe)
9786 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9787 }
9788
f458ebbc 9789 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9790 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9791 return false;
9792
eccb140b 9793 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9794 if (!(tmp & PIPECONF_ENABLE))
9795 return false;
9796
26804afd 9797 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9798
1bd1bd80
DV		 9799 intel_get_pipe_timings(crtc, pipe_config);
9800
a1b2278e
CK		 9801 if (INTEL_INFO(dev)->gen >= 9) {
9802 skl_init_scalers(dev, crtc, pipe_config);
9803 }
9804
2fa2fe9a 9805 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9806
9807 if (INTEL_INFO(dev)->gen >= 9) {
9808 pipe_config->scaler_state.scaler_id = -1;
9809 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9810 }
9811
bd2e244f 9812 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9813 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9814 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9815 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9816 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9817 else
9818 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9819 }
88adfff1 9820
e59150dc
JB		 9821 if (IS_HASWELL(dev))
9822 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9823 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9824
ebb69c95
CT		 9825 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9826 pipe_config->pixel_multiplier =
9827 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9828 } else {
9829 pipe_config->pixel_multiplier = 1;
9830 }
6c49f241 9831
0e8ffe1b
DV		 9832 return true;
9833}
9834
560b85bb
CW		 9835static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9836{
9837 struct drm_device *dev = crtc->dev;
9838 struct drm_i915_private *dev_priv = dev->dev_private;
9839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9840 uint32_t cntl = 0, size = 0;
560b85bb 9841
dc41c154 9842 if (base) {
3dd512fb
MR		 9843 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9844 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9845 unsigned int stride = roundup_pow_of_two(width) * 4;
9846
9847 switch (stride) {
9848 default:
9849 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9850 width, stride);
9851 stride = 256;
9852 /* fallthrough */
9853 case 256:
9854 case 512:
9855 case 1024:
9856 case 2048:
9857 break;
4b0e333e
CW		 9858 }
9859
dc41c154
VS		 9860 cntl |= CURSOR_ENABLE |
9861 CURSOR_GAMMA_ENABLE |
9862 CURSOR_FORMAT_ARGB |
9863 CURSOR_STRIDE(stride);
9864
9865 size = (height << 12) | width;
4b0e333e 9866 }
560b85bb 9867
dc41c154
VS		 9868 if (intel_crtc->cursor_cntl != 0 &&
9869 (intel_crtc->cursor_base != base ||
9870 intel_crtc->cursor_size != size ||
9871 intel_crtc->cursor_cntl != cntl)) {
9872 /* On these chipsets we can only modify the base/size/stride
9873 * whilst the cursor is disabled.
9874 */
9875 I915_WRITE(_CURACNTR, 0);
4b0e333e 9876 POSTING_READ(_CURACNTR);
dc41c154 9877 intel_crtc->cursor_cntl = 0;
4b0e333e 9878 }
560b85bb 9879
99d1f387 9880 if (intel_crtc->cursor_base != base) {
9db4a9c7 9881 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9882 intel_crtc->cursor_base = base;
9883 }
4726e0b0 9884
dc41c154
VS		 9885 if (intel_crtc->cursor_size != size) {
9886 I915_WRITE(CURSIZE, size);
9887 intel_crtc->cursor_size = size;
4b0e333e 9888 }
560b85bb 9889
4b0e333e 9890 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9891 I915_WRITE(_CURACNTR, cntl);
9892 POSTING_READ(_CURACNTR);
4b0e333e 9893 intel_crtc->cursor_cntl = cntl;
560b85bb 9894 }
560b85bb
CW		 9895}
9896
560b85bb 9897static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9898{
9899 struct drm_device *dev = crtc->dev;
9900 struct drm_i915_private *dev_priv = dev->dev_private;
9901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9902 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9903 uint32_t cntl;
9904
9905 cntl = 0;
9906 if (base) {
9907 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9908 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9909 case 64:
9910 cntl |= CURSOR_MODE_64_ARGB_AX;
9911 break;
9912 case 128:
9913 cntl |= CURSOR_MODE_128_ARGB_AX;
9914 break;
9915 case 256:
9916 cntl |= CURSOR_MODE_256_ARGB_AX;
9917 break;
9918 default:
3dd512fb 9919 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9920 return;
65a21cd6 9921 }
4b0e333e 9922 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9923
9924 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9925 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9926 }
65a21cd6 9927
8e7d688b 9928 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9929 cntl |= CURSOR_ROTATE_180;
9930
4b0e333e
CW		 9931 if (intel_crtc->cursor_cntl != cntl) {
9932 I915_WRITE(CURCNTR(pipe), cntl);
9933 POSTING_READ(CURCNTR(pipe));
9934 intel_crtc->cursor_cntl = cntl;
65a21cd6 9935 }
4b0e333e 9936
65a21cd6 9937 /* and commit changes on next vblank */
5efb3e28
VS		 9938 I915_WRITE(CURBASE(pipe), base);
9939 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9940
9941 intel_crtc->cursor_base = base;
65a21cd6
JB		 9942}
9943
cda4b7d3 9944/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9945static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9946 bool on)
cda4b7d3
CW		 9947{
9948 struct drm_device *dev = crtc->dev;
9949 struct drm_i915_private *dev_priv = dev->dev_private;
9950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9951 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9952 int x = crtc->cursor_x;
9953 int y = crtc->cursor_y;
d6e4db15 9954 u32 base = 0, pos = 0;
cda4b7d3 9955
d6e4db15 9956 if (on)
cda4b7d3 9957 base = intel_crtc->cursor_addr;
cda4b7d3 9958
6e3c9717 9959 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9960 base = 0;
9961
6e3c9717 9962 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9963 base = 0;
9964
9965 if (x < 0) {
3dd512fb 9966 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9967 base = 0;
9968
9969 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9970 x = -x;
9971 }
9972 pos |= x << CURSOR_X_SHIFT;
9973
9974 if (y < 0) {
3dd512fb 9975 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9976 base = 0;
9977
9978 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9979 y = -y;
9980 }
9981 pos |= y << CURSOR_Y_SHIFT;
9982
4b0e333e 9983 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9984 return;
9985
5efb3e28
VS		 9986 I915_WRITE(CURPOS(pipe), pos);
9987
4398ad45
VS		 9988 /* ILK+ do this automagically */
9989 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9990 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9991 base += (intel_crtc->base.cursor->state->crtc_h *
9992 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9993 }
9994
8ac54669 9995 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9996 i845_update_cursor(crtc, base);
9997 else
9998 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9999}
10000
dc41c154
VS		 10001static bool cursor_size_ok(struct drm_device *dev,
10002 uint32_t width, uint32_t height)
10003{
10004 if (width == 0 || height == 0)
10005 return false;
10006
10007 /*
10008 * 845g/865g are special in that they are only limited by
10009 * the width of their cursors, the height is arbitrary up to
10010 * the precision of the register. Everything else requires
10011 * square cursors, limited to a few power-of-two sizes.
10012 */
10013 if (IS_845G(dev) || IS_I865G(dev)) {
10014 if ((width & 63) != 0)
10015 return false;
10016
10017 if (width > (IS_845G(dev) ? 64 : 512))
10018 return false;
10019
10020 if (height > 1023)
10021 return false;
10022 } else {
10023 switch (width | height) {
10024 case 256:
10025 case 128:
10026 if (IS_GEN2(dev))
10027 return false;
10028 case 64:
10029 break;
10030 default:
10031 return false;
10032 }
10033 }
10034
10035 return true;
10036}
10037
79e53945 10038static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10039 u16 *blue, uint32_t start, uint32_t size)
79e53945 10040{
7203425a 10041 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10043
7203425a 10044 for (i = start; i < end; i++) {
79e53945
JB		 10045 intel_crtc->lut_r[i] = red[i] >> 8;
10046 intel_crtc->lut_g[i] = green[i] >> 8;
10047 intel_crtc->lut_b[i] = blue[i] >> 8;
10048 }
10049
10050 intel_crtc_load_lut(crtc);
10051}
10052
79e53945
JB		 10053/* VESA 640x480x72Hz mode to set on the pipe */
10054static struct drm_display_mode load_detect_mode = {
10055 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10056 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10057};
10058
a8bb6818
DV		 10059struct drm_framebuffer *
10060__intel_framebuffer_create(struct drm_device *dev,
10061 struct drm_mode_fb_cmd2 *mode_cmd,
10062 struct drm_i915_gem_object *obj)
d2dff872
CW		 10063{
10064 struct intel_framebuffer *intel_fb;
10065 int ret;
10066
10067 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10068 if (!intel_fb) {
6ccb81f2 10069 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10070 return ERR_PTR(-ENOMEM);
10071 }
10072
10073 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10074 if (ret)
10075 goto err;
d2dff872
CW		 10076
10077 return &intel_fb->base;
dd4916c5 10078err:
6ccb81f2 10079 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10080 kfree(intel_fb);
10081
10082 return ERR_PTR(ret);
d2dff872
CW		 10083}
10084
b5ea642a 10085static struct drm_framebuffer *
a8bb6818
DV		 10086intel_framebuffer_create(struct drm_device *dev,
10087 struct drm_mode_fb_cmd2 *mode_cmd,
10088 struct drm_i915_gem_object *obj)
10089{
10090 struct drm_framebuffer *fb;
10091 int ret;
10092
10093 ret = i915_mutex_lock_interruptible(dev);
10094 if (ret)
10095 return ERR_PTR(ret);
10096 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10097 mutex_unlock(&dev->struct_mutex);
10098
10099 return fb;
10100}
10101
d2dff872
CW		 10102static u32
10103intel_framebuffer_pitch_for_width(int width, int bpp)
10104{
10105 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10106 return ALIGN(pitch, 64);
10107}
10108
10109static u32
10110intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10111{
10112 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10113 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10114}
10115
10116static struct drm_framebuffer *
10117intel_framebuffer_create_for_mode(struct drm_device *dev,
10118 struct drm_display_mode *mode,
10119 int depth, int bpp)
10120{
10121 struct drm_i915_gem_object *obj;
0fed39bd 10122 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10123
10124 obj = i915_gem_alloc_object(dev,
10125 intel_framebuffer_size_for_mode(mode, bpp));
10126 if (obj == NULL)
10127 return ERR_PTR(-ENOMEM);
10128
10129 mode_cmd.width = mode->hdisplay;
10130 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10131 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10132 bpp);
5ca0c34a 10133 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10134
10135 return intel_framebuffer_create(dev, &mode_cmd, obj);
10136}
10137
10138static struct drm_framebuffer *
10139mode_fits_in_fbdev(struct drm_device *dev,
10140 struct drm_display_mode *mode)
10141{
4520f53a 10142#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10143 struct drm_i915_private *dev_priv = dev->dev_private;
10144 struct drm_i915_gem_object *obj;
10145 struct drm_framebuffer *fb;
10146
4c0e5528 10147 if (!dev_priv->fbdev)
d2dff872
CW		 10148 return NULL;
10149
4c0e5528 10150 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10151 return NULL;
10152
4c0e5528
DV		 10153 obj = dev_priv->fbdev->fb->obj;
10154 BUG_ON(!obj);
10155
8bcd4553 10156 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10157 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10158 fb->bits_per_pixel))
d2dff872
CW		 10159 return NULL;
10160
01f2c773 10161 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10162 return NULL;
10163
10164 return fb;
4520f53a
DV		 10165#else
10166 return NULL;
10167#endif
d2dff872
CW		 10168}
10169
d3a40d1b
ACO		 10170static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10171 struct drm_crtc *crtc,
10172 struct drm_display_mode *mode,
10173 struct drm_framebuffer *fb,
10174 int x, int y)
10175{
10176 struct drm_plane_state *plane_state;
10177 int hdisplay, vdisplay;
10178 int ret;
10179
10180 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10181 if (IS_ERR(plane_state))
10182 return PTR_ERR(plane_state);
10183
10184 if (mode)
10185 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10186 else
10187 hdisplay = vdisplay = 0;
10188
10189 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10190 if (ret)
10191 return ret;
10192 drm_atomic_set_fb_for_plane(plane_state, fb);
10193 plane_state->crtc_x = 0;
10194 plane_state->crtc_y = 0;
10195 plane_state->crtc_w = hdisplay;
10196 plane_state->crtc_h = vdisplay;
10197 plane_state->src_x = x << 16;
10198 plane_state->src_y = y << 16;
10199 plane_state->src_w = hdisplay << 16;
10200 plane_state->src_h = vdisplay << 16;
10201
10202 return 0;
10203}
10204
d2434ab7 10205bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10206 struct drm_display_mode *mode,
51fd371b
RC		 10207 struct intel_load_detect_pipe *old,
10208 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10209{
10210 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10211 struct intel_encoder *intel_encoder =
10212 intel_attached_encoder(connector);
79e53945 10213 struct drm_crtc *possible_crtc;
4ef69c7a 10214 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10215 struct drm_crtc *crtc = NULL;
10216 struct drm_device *dev = encoder->dev;
94352cf9 10217 struct drm_framebuffer *fb;
51fd371b 10218 struct drm_mode_config *config = &dev->mode_config;
83a57153 10219 struct drm_atomic_state *state = NULL;
944b0c76 10220 struct drm_connector_state *connector_state;
4be07317 10221 struct intel_crtc_state *crtc_state;
51fd371b 10222 int ret, i = -1;
79e53945 10223
d2dff872 10224 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10225 connector->base.id, connector->name,
8e329a03 10226 encoder->base.id, encoder->name);
d2dff872 10227
51fd371b
RC		 10228retry:
10229 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10230 if (ret)
10231 goto fail_unlock;
6e9f798d 10232
79e53945
JB		 10233 /*
10234 * Algorithm gets a little messy:
7a5e4805 10235 *
79e53945
JB		 10236 * - if the connector already has an assigned crtc, use it (but make
10237 * sure it's on first)
7a5e4805 10238 *
79e53945
JB		 10239 * - try to find the first unused crtc that can drive this connector,
10240 * and use that if we find one
79e53945
JB		 10241 */
10242
10243 /* See if we already have a CRTC for this connector */
10244 if (encoder->crtc) {
10245 crtc = encoder->crtc;
8261b191 10246
51fd371b 10247 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10248 if (ret)
10249 goto fail_unlock;
10250 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10251 if (ret)
10252 goto fail_unlock;
7b24056b 10253
24218aac 10254 old->dpms_mode = connector->dpms;
8261b191
CW		 10255 old->load_detect_temp = false;
10256
10257 /* Make sure the crtc and connector are running */
24218aac
DV		 10258 if (connector->dpms != DRM_MODE_DPMS_ON)
10259 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10260
7173188d 10261 return true;
79e53945
JB		 10262 }
10263
10264 /* Find an unused one (if possible) */
70e1e0ec 10265 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10266 i++;
10267 if (!(encoder->possible_crtcs & (1 << i)))
10268 continue;
83d65738 10269 if (possible_crtc->state->enable)
a459249c
VS		 10270 continue;
10271 /* This can occur when applying the pipe A quirk on resume. */
10272 if (to_intel_crtc(possible_crtc)->new_enabled)
10273 continue;
10274
10275 crtc = possible_crtc;
10276 break;
79e53945
JB		 10277 }
10278
10279 /*
10280 * If we didn't find an unused CRTC, don't use any.
10281 */
10282 if (!crtc) {
7173188d 10283 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10284 goto fail_unlock;
79e53945
JB		 10285 }
10286
51fd371b
RC		 10287 ret = drm_modeset_lock(&crtc->mutex, ctx);
10288 if (ret)
4d02e2de
DV		 10289 goto fail_unlock;
10290 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10291 if (ret)
51fd371b 10292 goto fail_unlock;
fc303101
DV		 10293 intel_encoder->new_crtc = to_intel_crtc(crtc);
10294 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10295
10296 intel_crtc = to_intel_crtc(crtc);
412b61d8 10297 intel_crtc->new_enabled = true;
24218aac 10298 old->dpms_mode = connector->dpms;
8261b191 10299 old->load_detect_temp = true;
d2dff872 10300 old->release_fb = NULL;
79e53945 10301
83a57153
ACO		 10302 state = drm_atomic_state_alloc(dev);
10303 if (!state)
10304 return false;
10305
10306 state->acquire_ctx = ctx;
10307
944b0c76
ACO		 10308 connector_state = drm_atomic_get_connector_state(state, connector);
10309 if (IS_ERR(connector_state)) {
10310 ret = PTR_ERR(connector_state);
10311 goto fail;
10312 }
10313
10314 connector_state->crtc = crtc;
10315 connector_state->best_encoder = &intel_encoder->base;
10316
4be07317
ACO		 10317 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10318 if (IS_ERR(crtc_state)) {
10319 ret = PTR_ERR(crtc_state);
10320 goto fail;
10321 }
10322
49d6fa21 10323 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10324
6492711d
CW		 10325 if (!mode)
10326 mode = &load_detect_mode;
79e53945 10327
d2dff872
CW		 10328 /* We need a framebuffer large enough to accommodate all accesses
10329 * that the plane may generate whilst we perform load detection.
10330 * We can not rely on the fbcon either being present (we get called
10331 * during its initialisation to detect all boot displays, or it may
10332 * not even exist) or that it is large enough to satisfy the
10333 * requested mode.
10334 */
94352cf9
DV		 10335 fb = mode_fits_in_fbdev(dev, mode);
10336 if (fb == NULL) {
d2dff872 10337 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10338 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10339 old->release_fb = fb;
d2dff872
CW		 10340 } else
10341 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10342 if (IS_ERR(fb)) {
d2dff872 10343 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10344 goto fail;
79e53945 10345 }
79e53945 10346
d3a40d1b
ACO		 10347 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10348 if (ret)
10349 goto fail;
10350
8c7b5ccb
ACO		 10351 drm_mode_copy(&crtc_state->base.mode, mode);
10352
568c634a 10353 if (intel_set_mode(state)) {
6492711d 10354 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10355 if (old->release_fb)
10356 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10357 goto fail;
79e53945 10358 }
9128b040 10359 crtc->primary->crtc = crtc;
7173188d 10360
79e53945 10361 /* let the connector get through one full cycle before testing */
9d0498a2 10362 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10363 return true;
412b61d8
VS		 10364
10365 fail:
83d65738 10366 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10367fail_unlock:
e5d958ef
ACO		 10368 drm_atomic_state_free(state);
10369 state = NULL;
83a57153 10370
51fd371b
RC		 10371 if (ret == -EDEADLK) {
10372 drm_modeset_backoff(ctx);
10373 goto retry;
10374 }
10375
412b61d8 10376 return false;
79e53945
JB		 10377}
10378
d2434ab7 10379void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10380 struct intel_load_detect_pipe *old,
10381 struct drm_modeset_acquire_ctx *ctx)
79e53945 10382{
83a57153 10383 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10384 struct intel_encoder *intel_encoder =
10385 intel_attached_encoder(connector);
4ef69c7a 10386 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10387 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10389 struct drm_atomic_state *state;
944b0c76 10390 struct drm_connector_state *connector_state;
4be07317 10391 struct intel_crtc_state *crtc_state;
d3a40d1b 10392 int ret;
79e53945 10393
d2dff872 10394 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10395 connector->base.id, connector->name,
8e329a03 10396 encoder->base.id, encoder->name);
d2dff872 10397
8261b191 10398 if (old->load_detect_temp) {
83a57153 10399 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10400 if (!state)
10401 goto fail;
83a57153
ACO		 10402
10403 state->acquire_ctx = ctx;
10404
944b0c76
ACO		 10405 connector_state = drm_atomic_get_connector_state(state, connector);
10406 if (IS_ERR(connector_state))
10407 goto fail;
10408
4be07317
ACO		 10409 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10410 if (IS_ERR(crtc_state))
10411 goto fail;
10412
fc303101
DV		 10413 to_intel_connector(connector)->new_encoder = NULL;
10414 intel_encoder->new_crtc = NULL;
412b61d8 10415 intel_crtc->new_enabled = false;
944b0c76
ACO		 10416
10417 connector_state->best_encoder = NULL;
10418 connector_state->crtc = NULL;
10419
49d6fa21 10420 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10421
d3a40d1b
ACO		 10422 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10423 0, 0);
10424 if (ret)
10425 goto fail;
10426
568c634a 10427 ret = intel_set_mode(state);
2bfb4627
ACO		 10428 if (ret)
10429 goto fail;
d2dff872 10430
36206361
DV		 10431 if (old->release_fb) {
10432 drm_framebuffer_unregister_private(old->release_fb);
10433 drm_framebuffer_unreference(old->release_fb);
10434 }
d2dff872 10435
0622a53c 10436 return;
79e53945
JB		 10437 }
10438
c751ce4f 10439 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10440 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10441 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10442
10443 return;
10444fail:
10445 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10446 drm_atomic_state_free(state);
79e53945
JB		 10447}
10448
da4a1efa 10449static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10450 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10451{
10452 struct drm_i915_private *dev_priv = dev->dev_private;
10453 u32 dpll = pipe_config->dpll_hw_state.dpll;
10454
10455 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10456 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10457 else if (HAS_PCH_SPLIT(dev))
10458 return 120000;
10459 else if (!IS_GEN2(dev))
10460 return 96000;
10461 else
10462 return 48000;
10463}
10464
79e53945 10465/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10466static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10467 struct intel_crtc_state *pipe_config)
79e53945 10468{
f1f644dc 10469 struct drm_device *dev = crtc->base.dev;
79e53945 10470 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10471 int pipe = pipe_config->cpu_transcoder;
293623f7 10472 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10473 u32 fp;
10474 intel_clock_t clock;
dccbea3b 10475 int port_clock;
da4a1efa 10476 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10477
10478 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10479 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10480 else
293623f7 10481 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10482
10483 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10484 if (IS_PINEVIEW(dev)) {
10485 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10486 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10487 } else {
10488 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10489 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10490 }
10491
a6c45cf0 10492 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10493 if (IS_PINEVIEW(dev))
10494 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10495 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10496 else
10497 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10498 DPLL_FPA01_P1_POST_DIV_SHIFT);
10499
10500 switch (dpll & DPLL_MODE_MASK) {
10501 case DPLLB_MODE_DAC_SERIAL:
10502 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10503 5 : 10;
10504 break;
10505 case DPLLB_MODE_LVDS:
10506 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10507 7 : 14;
10508 break;
10509 default:
28c97730 10510 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10511 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10512 return;
79e53945
JB		 10513 }
10514
ac58c3f0 10515 if (IS_PINEVIEW(dev))
dccbea3b 10516 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10517 else
dccbea3b 10518 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10519 } else {
0fb58223 10520 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10521 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10522
10523 if (is_lvds) {
10524 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10525 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10526
10527 if (lvds & LVDS_CLKB_POWER_UP)
10528 clock.p2 = 7;
10529 else
10530 clock.p2 = 14;
79e53945
JB		 10531 } else {
10532 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10533 clock.p1 = 2;
10534 else {
10535 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10536 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10537 }
10538 if (dpll & PLL_P2_DIVIDE_BY_4)
10539 clock.p2 = 4;
10540 else
10541 clock.p2 = 2;
79e53945 10542 }
da4a1efa 10543
dccbea3b 10544 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10545 }
10546
18442d08
VS		 10547 /*
10548 * This value includes pixel_multiplier. We will use
241bfc38 10549 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10550 * encoder's get_config() function.
10551 */
dccbea3b 10552 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10553}
10554
6878da05
VS		 10555int intel_dotclock_calculate(int link_freq,
10556 const struct intel_link_m_n *m_n)
f1f644dc 10557{
f1f644dc
JB		 10558 /*
10559 * The calculation for the data clock is:
1041a02f 10560 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10561 * But we want to avoid losing precison if possible, so:
1041a02f 10562 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10563 *
10564 * and the link clock is simpler:
1041a02f 10565 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10566 */
10567
6878da05
VS		 10568 if (!m_n->link_n)
10569 return 0;
f1f644dc 10570
6878da05
VS		 10571 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10572}
f1f644dc 10573
18442d08 10574static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10575 struct intel_crtc_state *pipe_config)
6878da05
VS		 10576{
10577 struct drm_device *dev = crtc->base.dev;
79e53945 10578
18442d08
VS		 10579 /* read out port_clock from the DPLL */
10580 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10581
f1f644dc 10582 /*
18442d08 10583 * This value does not include pixel_multiplier.
241bfc38 10584 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10585 * agree once we know their relationship in the encoder's
10586 * get_config() function.
79e53945 10587 */
2d112de7 10588 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10589 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10590 &pipe_config->fdi_m_n);
79e53945
JB		 10591}
10592
10593/** Returns the currently programmed mode of the given pipe. */
10594struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10595 struct drm_crtc *crtc)
10596{
548f245b 10597 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10599 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10600 struct drm_display_mode *mode;
5cec258b 10601 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10602 int htot = I915_READ(HTOTAL(cpu_transcoder));
10603 int hsync = I915_READ(HSYNC(cpu_transcoder));
10604 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10605 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10606 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10607
10608 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10609 if (!mode)
10610 return NULL;
10611
f1f644dc
JB		 10612 /*
10613 * Construct a pipe_config sufficient for getting the clock info
10614 * back out of crtc_clock_get.
10615 *
10616 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10617 * to use a real value here instead.
10618 */
293623f7 10619 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10620 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10621 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10622 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10623 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10624 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10625
773ae034 10626 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10627 mode->hdisplay = (htot & 0xffff) + 1;
10628 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10629 mode->hsync_start = (hsync & 0xffff) + 1;
10630 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10631 mode->vdisplay = (vtot & 0xffff) + 1;
10632 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10633 mode->vsync_start = (vsync & 0xffff) + 1;
10634 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10635
10636 drm_mode_set_name(mode);
79e53945
JB		 10637
10638 return mode;
10639}
10640
f047e395
CW		 10641void intel_mark_busy(struct drm_device *dev)
10642{
c67a470b
PZ		 10643 struct drm_i915_private *dev_priv = dev->dev_private;
10644
f62a0076
CW		 10645 if (dev_priv->mm.busy)
10646 return;
10647
43694d69 10648 intel_runtime_pm_get(dev_priv);
c67a470b 10649 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10650 if (INTEL_INFO(dev)->gen >= 6)
10651 gen6_rps_busy(dev_priv);
f62a0076 10652 dev_priv->mm.busy = true;
f047e395
CW		 10653}
10654
10655void intel_mark_idle(struct drm_device *dev)
652c393a 10656{
c67a470b 10657 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10658
f62a0076
CW		 10659 if (!dev_priv->mm.busy)
10660 return;
10661
10662 dev_priv->mm.busy = false;
10663
3d13ef2e 10664 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10665 gen6_rps_idle(dev->dev_private);
bb4cdd53 10666
43694d69 10667 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10668}
10669
79e53945
JB		 10670static void intel_crtc_destroy(struct drm_crtc *crtc)
10671{
10672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10673 struct drm_device *dev = crtc->dev;
10674 struct intel_unpin_work *work;
67e77c5a 10675
5e2d7afc 10676 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10677 work = intel_crtc->unpin_work;
10678 intel_crtc->unpin_work = NULL;
5e2d7afc 10679 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10680
10681 if (work) {
10682 cancel_work_sync(&work->work);
10683 kfree(work);
10684 }
79e53945
JB		 10685
10686 drm_crtc_cleanup(crtc);
67e77c5a 10687
79e53945
JB		 10688 kfree(intel_crtc);
10689}
10690
6b95a207
KH		 10691static void intel_unpin_work_fn(struct work_struct *__work)
10692{
10693 struct intel_unpin_work *work =
10694 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10695 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10696 struct drm_device *dev = crtc->base.dev;
10697 struct drm_plane *primary = crtc->base.primary;
6b95a207 10698
b4a98e57 10699 mutex_lock(&dev->struct_mutex);
a9ff8714 10700 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10701 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10702
7ff0ebcc 10703 intel_fbc_update(dev);
f06cc1b9
JH		 10704
10705 if (work->flip_queued_req)
146d84f0 10706 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10707 mutex_unlock(&dev->struct_mutex);
10708
a9ff8714 10709 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10710 drm_framebuffer_unreference(work->old_fb);
f99d7069 10711
a9ff8714
VS		 10712 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10713 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10714
6b95a207
KH		 10715 kfree(work);
10716}
10717
1afe3e9d 10718static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10719 struct drm_crtc *crtc)
6b95a207 10720{
6b95a207
KH		 10721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10722 struct intel_unpin_work *work;
6b95a207
KH		 10723 unsigned long flags;
10724
10725 /* Ignore early vblank irqs */
10726 if (intel_crtc == NULL)
10727 return;
10728
f326038a
DV		 10729 /*
10730 * This is called both by irq handlers and the reset code (to complete
10731 * lost pageflips) so needs the full irqsave spinlocks.
10732 */
6b95a207
KH		 10733 spin_lock_irqsave(&dev->event_lock, flags);
10734 work = intel_crtc->unpin_work;
e7d841ca
CW		 10735
10736 /* Ensure we don't miss a work->pending update ... */
10737 smp_rmb();
10738
10739 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10740 spin_unlock_irqrestore(&dev->event_lock, flags);
10741 return;
10742 }
10743
d6bbafa1 10744 page_flip_completed(intel_crtc);
0af7e4df 10745
6b95a207 10746 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10747}
10748
1afe3e9d
JB		 10749void intel_finish_page_flip(struct drm_device *dev, int pipe)
10750{
fbee40df 10751 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10752 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10753
49b14a5c 10754 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10755}
10756
10757void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10758{
fbee40df 10759 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10760 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10761
49b14a5c 10762 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10763}
10764
75f7f3ec
VS		 10765/* Is 'a' after or equal to 'b'? */
10766static bool g4x_flip_count_after_eq(u32 a, u32 b)
10767{
10768 return !((a - b) & 0x80000000);
10769}
10770
10771static bool page_flip_finished(struct intel_crtc *crtc)
10772{
10773 struct drm_device *dev = crtc->base.dev;
10774 struct drm_i915_private *dev_priv = dev->dev_private;
10775
bdfa7542
VS		 10776 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10777 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10778 return true;
10779
75f7f3ec
VS		 10780 /*
10781 * The relevant registers doen't exist on pre-ctg.
10782 * As the flip done interrupt doesn't trigger for mmio
10783 * flips on gmch platforms, a flip count check isn't
10784 * really needed there. But since ctg has the registers,
10785 * include it in the check anyway.
10786 */
10787 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10788 return true;
10789
10790 /*
10791 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10792 * used the same base address. In that case the mmio flip might
10793 * have completed, but the CS hasn't even executed the flip yet.
10794 *
10795 * A flip count check isn't enough as the CS might have updated
10796 * the base address just after start of vblank, but before we
10797 * managed to process the interrupt. This means we'd complete the
10798 * CS flip too soon.
10799 *
10800 * Combining both checks should get us a good enough result. It may
10801 * still happen that the CS flip has been executed, but has not
10802 * yet actually completed. But in case the base address is the same
10803 * anyway, we don't really care.
10804 */
10805 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10806 crtc->unpin_work->gtt_offset &&
10807 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10808 crtc->unpin_work->flip_count);
10809}
10810
6b95a207
KH		 10811void intel_prepare_page_flip(struct drm_device *dev, int plane)
10812{
fbee40df 10813 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10814 struct intel_crtc *intel_crtc =
10815 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10816 unsigned long flags;
10817
f326038a
DV		 10818
10819 /*
10820 * This is called both by irq handlers and the reset code (to complete
10821 * lost pageflips) so needs the full irqsave spinlocks.
10822 *
10823 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10824 * generate a page-flip completion irq, i.e. every modeset
10825 * is also accompanied by a spurious intel_prepare_page_flip().
10826 */
6b95a207 10827 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10828 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10829 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10830 spin_unlock_irqrestore(&dev->event_lock, flags);
10831}
10832
eba905b2 10833static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10834{
10835 /* Ensure that the work item is consistent when activating it ... */
10836 smp_wmb();
10837 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10838 /* and that it is marked active as soon as the irq could fire. */
10839 smp_wmb();
10840}
10841
8c9f3aaf
JB		 10842static int intel_gen2_queue_flip(struct drm_device *dev,
10843 struct drm_crtc *crtc,
10844 struct drm_framebuffer *fb,
ed8d1975 10845 struct drm_i915_gem_object *obj,
6258fbe2 10846 struct drm_i915_gem_request *req,
ed8d1975 10847 uint32_t flags)
8c9f3aaf 10848{
6258fbe2 10849 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10851 u32 flip_mask;
10852 int ret;
10853
5fb9de1a 10854 ret = intel_ring_begin(req, 6);
8c9f3aaf 10855 if (ret)
4fa62c89 10856 return ret;
8c9f3aaf
JB		 10857
10858 /* Can't queue multiple flips, so wait for the previous
10859 * one to finish before executing the next.
10860 */
10861 if (intel_crtc->plane)
10862 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10863 else
10864 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10865 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10866 intel_ring_emit(ring, MI_NOOP);
10867 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10868 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10869 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10870 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10871 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10872
10873 intel_mark_page_flip_active(intel_crtc);
83d4092b 10874 return 0;
8c9f3aaf
JB		 10875}
10876
10877static int intel_gen3_queue_flip(struct drm_device *dev,
10878 struct drm_crtc *crtc,
10879 struct drm_framebuffer *fb,
ed8d1975 10880 struct drm_i915_gem_object *obj,
6258fbe2 10881 struct drm_i915_gem_request *req,
ed8d1975 10882 uint32_t flags)
8c9f3aaf 10883{
6258fbe2 10884 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10886 u32 flip_mask;
10887 int ret;
10888
5fb9de1a 10889 ret = intel_ring_begin(req, 6);
8c9f3aaf 10890 if (ret)
4fa62c89 10891 return ret;
8c9f3aaf
JB		 10892
10893 if (intel_crtc->plane)
10894 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10895 else
10896 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10897 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10898 intel_ring_emit(ring, MI_NOOP);
10899 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10900 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10901 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10902 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10903 intel_ring_emit(ring, MI_NOOP);
10904
e7d841ca 10905 intel_mark_page_flip_active(intel_crtc);
83d4092b 10906 return 0;
8c9f3aaf
JB		 10907}
10908
10909static int intel_gen4_queue_flip(struct drm_device *dev,
10910 struct drm_crtc *crtc,
10911 struct drm_framebuffer *fb,
ed8d1975 10912 struct drm_i915_gem_object *obj,
6258fbe2 10913 struct drm_i915_gem_request *req,
ed8d1975 10914 uint32_t flags)
8c9f3aaf 10915{
6258fbe2 10916 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10917 struct drm_i915_private *dev_priv = dev->dev_private;
10918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10919 uint32_t pf, pipesrc;
10920 int ret;
10921
5fb9de1a 10922 ret = intel_ring_begin(req, 4);
8c9f3aaf 10923 if (ret)
4fa62c89 10924 return ret;
8c9f3aaf
JB		 10925
10926 /* i965+ uses the linear or tiled offsets from the
10927 * Display Registers (which do not change across a page-flip)
10928 * so we need only reprogram the base address.
10929 */
6d90c952
DV		 10930 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10931 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10932 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10933 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10934 obj->tiling_mode);
8c9f3aaf
JB		 10935
10936 /* XXX Enabling the panel-fitter across page-flip is so far
10937 * untested on non-native modes, so ignore it for now.
10938 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10939 */
10940 pf = 0;
10941 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10942 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10943
10944 intel_mark_page_flip_active(intel_crtc);
83d4092b 10945 return 0;
8c9f3aaf
JB		 10946}
10947
10948static int intel_gen6_queue_flip(struct drm_device *dev,
10949 struct drm_crtc *crtc,
10950 struct drm_framebuffer *fb,
ed8d1975 10951 struct drm_i915_gem_object *obj,
6258fbe2 10952 struct drm_i915_gem_request *req,
ed8d1975 10953 uint32_t flags)
8c9f3aaf 10954{
6258fbe2 10955 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10956 struct drm_i915_private *dev_priv = dev->dev_private;
10957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10958 uint32_t pf, pipesrc;
10959 int ret;
10960
5fb9de1a 10961 ret = intel_ring_begin(req, 4);
8c9f3aaf 10962 if (ret)
4fa62c89 10963 return ret;
8c9f3aaf 10964
6d90c952
DV		 10965 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10966 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10967 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10968 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10969
dc257cf1
DV		 10970 /* Contrary to the suggestions in the documentation,
10971 * "Enable Panel Fitter" does not seem to be required when page
10972 * flipping with a non-native mode, and worse causes a normal
10973 * modeset to fail.
10974 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10975 */
10976 pf = 0;
8c9f3aaf 10977 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10978 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10979
10980 intel_mark_page_flip_active(intel_crtc);
83d4092b 10981 return 0;
8c9f3aaf
JB		 10982}
10983
7c9017e5
JB		 10984static int intel_gen7_queue_flip(struct drm_device *dev,
10985 struct drm_crtc *crtc,
10986 struct drm_framebuffer *fb,
ed8d1975 10987 struct drm_i915_gem_object *obj,
6258fbe2 10988 struct drm_i915_gem_request *req,
ed8d1975 10989 uint32_t flags)
7c9017e5 10990{
6258fbe2 10991 struct intel_engine_cs *ring = req->ring;
7c9017e5 10992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10993 uint32_t plane_bit = 0;
ffe74d75
CW		 10994 int len, ret;
10995
eba905b2 10996 switch (intel_crtc->plane) {
cb05d8de
DV		 10997 case PLANE_A:
10998 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10999 break;
11000 case PLANE_B:
11001 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11002 break;
11003 case PLANE_C:
11004 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11005 break;
11006 default:
11007 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11008 return -ENODEV;
cb05d8de
DV		 11009 }
11010
ffe74d75 11011 len = 4;
f476828a 11012 if (ring->id == RCS) {
ffe74d75 11013 len += 6;
f476828a
DL		 11014 /*
11015 * On Gen 8, SRM is now taking an extra dword to accommodate
11016 * 48bits addresses, and we need a NOOP for the batch size to
11017 * stay even.
11018 */
11019 if (IS_GEN8(dev))
11020 len += 2;
11021 }
ffe74d75 11022
f66fab8e
VS		 11023 /*
11024 * BSpec MI_DISPLAY_FLIP for IVB:
11025 * "The full packet must be contained within the same cache line."
11026 *
11027 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11028 * cacheline, if we ever start emitting more commands before
11029 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11030 * then do the cacheline alignment, and finally emit the
11031 * MI_DISPLAY_FLIP.
11032 */
bba09b12 11033 ret = intel_ring_cacheline_align(req);
f66fab8e 11034 if (ret)
4fa62c89 11035 return ret;
f66fab8e 11036
5fb9de1a 11037 ret = intel_ring_begin(req, len);
7c9017e5 11038 if (ret)
4fa62c89 11039 return ret;
7c9017e5 11040
ffe74d75
CW		 11041 /* Unmask the flip-done completion message. Note that the bspec says that
11042 * we should do this for both the BCS and RCS, and that we must not unmask
11043 * more than one flip event at any time (or ensure that one flip message
11044 * can be sent by waiting for flip-done prior to queueing new flips).
11045 * Experimentation says that BCS works despite DERRMR masking all
11046 * flip-done completion events and that unmasking all planes at once
11047 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11048 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11049 */
11050 if (ring->id == RCS) {
11051 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11052 intel_ring_emit(ring, DERRMR);
11053 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11054 DERRMR_PIPEB_PRI_FLIP_DONE |
11055 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11056 if (IS_GEN8(dev))
11057 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11058 MI_SRM_LRM_GLOBAL_GTT);
11059 else
11060 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11061 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11062 intel_ring_emit(ring, DERRMR);
11063 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11064 if (IS_GEN8(dev)) {
11065 intel_ring_emit(ring, 0);
11066 intel_ring_emit(ring, MI_NOOP);
11067 }
ffe74d75
CW		 11068 }
11069
cb05d8de 11070 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11071 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11072 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11073 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11074
11075 intel_mark_page_flip_active(intel_crtc);
83d4092b 11076 return 0;
7c9017e5
JB		 11077}
11078
84c33a64
SG		 11079static bool use_mmio_flip(struct intel_engine_cs *ring,
11080 struct drm_i915_gem_object *obj)
11081{
11082 /*
11083 * This is not being used for older platforms, because
11084 * non-availability of flip done interrupt forces us to use
11085 * CS flips. Older platforms derive flip done using some clever
11086 * tricks involving the flip_pending status bits and vblank irqs.
11087 * So using MMIO flips there would disrupt this mechanism.
11088 */
11089
8e09bf83
CW		 11090 if (ring == NULL)
11091 return true;
11092
84c33a64
SG		 11093 if (INTEL_INFO(ring->dev)->gen < 5)
11094 return false;
11095
11096 if (i915.use_mmio_flip < 0)
11097 return false;
11098 else if (i915.use_mmio_flip > 0)
11099 return true;
14bf993e
OM		 11100 else if (i915.enable_execlists)
11101 return true;
84c33a64 11102 else
b4716185 11103 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11104}
11105
ff944564
DL		 11106static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11107{
11108 struct drm_device *dev = intel_crtc->base.dev;
11109 struct drm_i915_private *dev_priv = dev->dev_private;
11110 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11111 const enum pipe pipe = intel_crtc->pipe;
11112 u32 ctl, stride;
11113
11114 ctl = I915_READ(PLANE_CTL(pipe, 0));
11115 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11116 switch (fb->modifier[0]) {
11117 case DRM_FORMAT_MOD_NONE:
11118 break;
11119 case I915_FORMAT_MOD_X_TILED:
ff944564 11120 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11121 break;
11122 case I915_FORMAT_MOD_Y_TILED:
11123 ctl |= PLANE_CTL_TILED_Y;
11124 break;
11125 case I915_FORMAT_MOD_Yf_TILED:
11126 ctl |= PLANE_CTL_TILED_YF;
11127 break;
11128 default:
11129 MISSING_CASE(fb->modifier[0]);
11130 }
ff944564
DL		 11131
11132 /*
11133 * The stride is either expressed as a multiple of 64 bytes chunks for
11134 * linear buffers or in number of tiles for tiled buffers.
11135 */
2ebef630
TU		 11136 stride = fb->pitches[0] /
11137 intel_fb_stride_alignment(dev, fb->modifier[0],
11138 fb->pixel_format);
ff944564
DL		 11139
11140 /*
11141 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11142 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11143 */
11144 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11145 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11146
11147 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11148 POSTING_READ(PLANE_SURF(pipe, 0));
11149}
11150
11151static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11152{
11153 struct drm_device *dev = intel_crtc->base.dev;
11154 struct drm_i915_private *dev_priv = dev->dev_private;
11155 struct intel_framebuffer *intel_fb =
11156 to_intel_framebuffer(intel_crtc->base.primary->fb);
11157 struct drm_i915_gem_object *obj = intel_fb->obj;
11158 u32 dspcntr;
11159 u32 reg;
11160
84c33a64
SG		 11161 reg = DSPCNTR(intel_crtc->plane);
11162 dspcntr = I915_READ(reg);
11163
c5d97472
DL		 11164 if (obj->tiling_mode != I915_TILING_NONE)
11165 dspcntr |= DISPPLANE_TILED;
11166 else
11167 dspcntr &= ~DISPPLANE_TILED;
11168
84c33a64
SG		 11169 I915_WRITE(reg, dspcntr);
11170
11171 I915_WRITE(DSPSURF(intel_crtc->plane),
11172 intel_crtc->unpin_work->gtt_offset);
11173 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11174
ff944564
DL		 11175}
11176
11177/*
11178 * XXX: This is the temporary way to update the plane registers until we get
11179 * around to using the usual plane update functions for MMIO flips
11180 */
11181static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11182{
11183 struct drm_device *dev = intel_crtc->base.dev;
11184 bool atomic_update;
11185 u32 start_vbl_count;
11186
11187 intel_mark_page_flip_active(intel_crtc);
11188
11189 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11190
11191 if (INTEL_INFO(dev)->gen >= 9)
11192 skl_do_mmio_flip(intel_crtc);
11193 else
11194 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11195 ilk_do_mmio_flip(intel_crtc);
11196
9362c7c5
ACO		 11197 if (atomic_update)
11198 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11199}
11200
9362c7c5 11201static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11202{
b2cfe0ab
CW		 11203 struct intel_mmio_flip *mmio_flip =
11204 container_of(work, struct intel_mmio_flip, work);
84c33a64 11205
eed29a5b
DV		 11206 if (mmio_flip->req)
11207 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11208 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11209 false, NULL,
11210 &mmio_flip->i915->rps.mmioflips));
84c33a64 11211
b2cfe0ab
CW		 11212 intel_do_mmio_flip(mmio_flip->crtc);
11213
eed29a5b 11214 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11215 kfree(mmio_flip);
84c33a64
SG		 11216}
11217
11218static int intel_queue_mmio_flip(struct drm_device *dev,
11219 struct drm_crtc *crtc,
11220 struct drm_framebuffer *fb,
11221 struct drm_i915_gem_object *obj,
11222 struct intel_engine_cs *ring,
11223 uint32_t flags)
11224{
b2cfe0ab
CW		 11225 struct intel_mmio_flip *mmio_flip;
11226
11227 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11228 if (mmio_flip == NULL)
11229 return -ENOMEM;
84c33a64 11230
bcafc4e3 11231 mmio_flip->i915 = to_i915(dev);
eed29a5b 11232 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11233 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11234
b2cfe0ab
CW		 11235 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11236 schedule_work(&mmio_flip->work);
84c33a64 11237
84c33a64
SG		 11238 return 0;
11239}
11240
8c9f3aaf
JB		 11241static int intel_default_queue_flip(struct drm_device *dev,
11242 struct drm_crtc *crtc,
11243 struct drm_framebuffer *fb,
ed8d1975 11244 struct drm_i915_gem_object *obj,
6258fbe2 11245 struct drm_i915_gem_request *req,
ed8d1975 11246 uint32_t flags)
8c9f3aaf
JB		 11247{
11248 return -ENODEV;
11249}
11250
d6bbafa1
CW		 11251static bool __intel_pageflip_stall_check(struct drm_device *dev,
11252 struct drm_crtc *crtc)
11253{
11254 struct drm_i915_private *dev_priv = dev->dev_private;
11255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11256 struct intel_unpin_work *work = intel_crtc->unpin_work;
11257 u32 addr;
11258
11259 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11260 return true;
11261
11262 if (!work->enable_stall_check)
11263 return false;
11264
11265 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11266 if (work->flip_queued_req &&
11267 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11268 return false;
11269
1e3feefd 11270 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11271 }
11272
1e3feefd 11273 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11274 return false;
11275
11276 /* Potential stall - if we see that the flip has happened,
11277 * assume a missed interrupt. */
11278 if (INTEL_INFO(dev)->gen >= 4)
11279 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11280 else
11281 addr = I915_READ(DSPADDR(intel_crtc->plane));
11282
11283 /* There is a potential issue here with a false positive after a flip
11284 * to the same address. We could address this by checking for a
11285 * non-incrementing frame counter.
11286 */
11287 return addr == work->gtt_offset;
11288}
11289
11290void intel_check_page_flip(struct drm_device *dev, int pipe)
11291{
11292 struct drm_i915_private *dev_priv = dev->dev_private;
11293 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11295 struct intel_unpin_work *work;
f326038a 11296
6c51d46f 11297 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11298
11299 if (crtc == NULL)
11300 return;
11301
f326038a 11302 spin_lock(&dev->event_lock);
6ad790c0
CW		 11303 work = intel_crtc->unpin_work;
11304 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11305 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11306 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11307 page_flip_completed(intel_crtc);
6ad790c0 11308 work = NULL;
d6bbafa1 11309 }
6ad790c0
CW		 11310 if (work != NULL &&
11311 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11312 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11313 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11314}
11315
6b95a207
KH		 11316static int intel_crtc_page_flip(struct drm_crtc *crtc,
11317 struct drm_framebuffer *fb,
ed8d1975
KP		 11318 struct drm_pending_vblank_event *event,
11319 uint32_t page_flip_flags)
6b95a207
KH		 11320{
11321 struct drm_device *dev = crtc->dev;
11322 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11323 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11324 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11326 struct drm_plane *primary = crtc->primary;
a071fa00 11327 enum pipe pipe = intel_crtc->pipe;
6b95a207 11328 struct intel_unpin_work *work;
a4872ba6 11329 struct intel_engine_cs *ring;
cf5d8a46 11330 bool mmio_flip;
91af127f 11331 struct drm_i915_gem_request *request = NULL;
52e68630 11332 int ret;
6b95a207 11333
2ff8fde1
MR		 11334 /*
11335 * drm_mode_page_flip_ioctl() should already catch this, but double
11336 * check to be safe. In the future we may enable pageflipping from
11337 * a disabled primary plane.
11338 */
11339 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11340 return -EBUSY;
11341
e6a595d2 11342 /* Can't change pixel format via MI display flips. */
f4510a27 11343 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11344 return -EINVAL;
11345
11346 /*
11347 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11348 * Note that pitch changes could also affect these register.
11349 */
11350 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11351 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11352 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11353 return -EINVAL;
11354
f900db47
CW		 11355 if (i915_terminally_wedged(&dev_priv->gpu_error))
11356 goto out_hang;
11357
b14c5679 11358 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11359 if (work == NULL)
11360 return -ENOMEM;
11361
6b95a207 11362 work->event = event;
b4a98e57 11363 work->crtc = crtc;
ab8d6675 11364 work->old_fb = old_fb;
6b95a207
KH		 11365 INIT_WORK(&work->work, intel_unpin_work_fn);
11366
87b6b101 11367 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11368 if (ret)
11369 goto free_work;
11370
6b95a207 11371 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11372 spin_lock_irq(&dev->event_lock);
6b95a207 11373 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11374 /* Before declaring the flip queue wedged, check if
11375 * the hardware completed the operation behind our backs.
11376 */
11377 if (__intel_pageflip_stall_check(dev, crtc)) {
11378 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11379 page_flip_completed(intel_crtc);
11380 } else {
11381 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11382 spin_unlock_irq(&dev->event_lock);
468f0b44 11383
d6bbafa1
CW		 11384 drm_crtc_vblank_put(crtc);
11385 kfree(work);
11386 return -EBUSY;
11387 }
6b95a207
KH		 11388 }
11389 intel_crtc->unpin_work = work;
5e2d7afc 11390 spin_unlock_irq(&dev->event_lock);
6b95a207 11391
b4a98e57
CW		 11392 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11393 flush_workqueue(dev_priv->wq);
11394
75dfca80 11395 /* Reference the objects for the scheduled work. */
ab8d6675 11396 drm_framebuffer_reference(work->old_fb);
05394f39 11397 drm_gem_object_reference(&obj->base);
6b95a207 11398
f4510a27 11399 crtc->primary->fb = fb;
afd65eb4 11400 update_state_fb(crtc->primary);
1ed1f968 11401
e1f99ce6 11402 work->pending_flip_obj = obj;
e1f99ce6 11403
89ed88ba
CW		 11404 ret = i915_mutex_lock_interruptible(dev);
11405 if (ret)
11406 goto cleanup;
11407
b4a98e57 11408 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11409 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11410
75f7f3ec 11411 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11412 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11413
4fa62c89
VS		 11414 if (IS_VALLEYVIEW(dev)) {
11415 ring = &dev_priv->ring[BCS];
ab8d6675 11416 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11417 /* vlv: DISPLAY_FLIP fails to change tiling */
11418 ring = NULL;
48bf5b2d 11419 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11420 ring = &dev_priv->ring[BCS];
4fa62c89 11421 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11422 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11423 if (ring == NULL || ring->id != RCS)
11424 ring = &dev_priv->ring[BCS];
11425 } else {
11426 ring = &dev_priv->ring[RCS];
11427 }
11428
cf5d8a46
CW		 11429 mmio_flip = use_mmio_flip(ring, obj);
11430
11431 /* When using CS flips, we want to emit semaphores between rings.
11432 * However, when using mmio flips we will create a task to do the
11433 * synchronisation, so all we want here is to pin the framebuffer
11434 * into the display plane and skip any waits.
11435 */
82bc3b2d 11436 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11437 crtc->primary->state,
91af127f 11438 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11439 if (ret)
11440 goto cleanup_pending;
6b95a207 11441
121920fa
TU		 11442 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11443 + intel_crtc->dspaddr_offset;
4fa62c89 11444
cf5d8a46 11445 if (mmio_flip) {
84c33a64
SG		 11446 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11447 page_flip_flags);
d6bbafa1
CW		 11448 if (ret)
11449 goto cleanup_unpin;
11450
f06cc1b9
JH		 11451 i915_gem_request_assign(&work->flip_queued_req,
11452 obj->last_write_req);
d6bbafa1 11453 } else {
6258fbe2
JH		 11454 if (!request) {
11455 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11456 if (ret)
11457 goto cleanup_unpin;
11458 }
11459
11460 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11461 page_flip_flags);
11462 if (ret)
11463 goto cleanup_unpin;
11464
6258fbe2 11465 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11466 }
11467
91af127f 11468 if (request)
75289874 11469 i915_add_request_no_flush(request);
91af127f 11470
1e3feefd 11471 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11472 work->enable_stall_check = true;
4fa62c89 11473
ab8d6675 11474 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11475 to_intel_plane(primary)->frontbuffer_bit);
a071fa00 11476
7ff0ebcc 11477 intel_fbc_disable(dev);
5abeca4e 11478 mutex_unlock(&dev->struct_mutex);
a9ff8714
VS		 11479 intel_frontbuffer_flip_prepare(dev,
11480 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11481
e5510fac
JB		 11482 trace_i915_flip_request(intel_crtc->plane, obj);
11483
6b95a207 11484 return 0;
96b099fd 11485
4fa62c89 11486cleanup_unpin:
82bc3b2d 11487 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11488cleanup_pending:
91af127f
JH		 11489 if (request)
11490 i915_gem_request_cancel(request);
b4a98e57 11491 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11492 mutex_unlock(&dev->struct_mutex);
11493cleanup:
f4510a27 11494 crtc->primary->fb = old_fb;
afd65eb4 11495 update_state_fb(crtc->primary);
89ed88ba
CW		 11496
11497 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11498 drm_framebuffer_unreference(work->old_fb);
96b099fd 11499
5e2d7afc 11500 spin_lock_irq(&dev->event_lock);
96b099fd 11501 intel_crtc->unpin_work = NULL;
5e2d7afc 11502 spin_unlock_irq(&dev->event_lock);
96b099fd 11503
87b6b101 11504 drm_crtc_vblank_put(crtc);
7317c75e 11505free_work:
96b099fd
CW		 11506 kfree(work);
11507
f900db47 11508 if (ret == -EIO) {
02e0efb5
ML		 11509 struct drm_atomic_state *state;
11510 struct drm_plane_state *plane_state;
11511
f900db47 11512out_hang:
02e0efb5
ML		 11513 state = drm_atomic_state_alloc(dev);
11514 if (!state)
11515 return -ENOMEM;
11516 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11517
11518retry:
11519 plane_state = drm_atomic_get_plane_state(state, primary);
11520 ret = PTR_ERR_OR_ZERO(plane_state);
11521 if (!ret) {
11522 drm_atomic_set_fb_for_plane(plane_state, fb);
11523
11524 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11525 if (!ret)
11526 ret = drm_atomic_commit(state);
11527 }
11528
11529 if (ret == -EDEADLK) {
11530 drm_modeset_backoff(state->acquire_ctx);
11531 drm_atomic_state_clear(state);
11532 goto retry;
11533 }
11534
11535 if (ret)
11536 drm_atomic_state_free(state);
11537
f0d3dad3 11538 if (ret == 0 && event) {
5e2d7afc 11539 spin_lock_irq(&dev->event_lock);
a071fa00 11540 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11541 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11542 }
f900db47 11543 }
96b099fd 11544 return ret;
6b95a207
KH		 11545}
11546
da20eabd
ML		 11547
11548/**
11549 * intel_wm_need_update - Check whether watermarks need updating
11550 * @plane: drm plane
11551 * @state: new plane state
11552 *
11553 * Check current plane state versus the new one to determine whether
11554 * watermarks need to be recalculated.
11555 *
11556 * Returns true or false.
11557 */
11558static bool intel_wm_need_update(struct drm_plane *plane,
11559 struct drm_plane_state *state)
11560{
11561 /* Update watermarks on tiling changes. */
11562 if (!plane->state->fb || !state->fb ||
11563 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11564 plane->state->rotation != state->rotation)
11565 return true;
11566
11567 if (plane->state->crtc_w != state->crtc_w)
11568 return true;
11569
11570 return false;
11571}
11572
11573int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11574 struct drm_plane_state *plane_state)
11575{
11576 struct drm_crtc *crtc = crtc_state->crtc;
11577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11578 struct drm_plane *plane = plane_state->plane;
11579 struct drm_device *dev = crtc->dev;
11580 struct drm_i915_private *dev_priv = dev->dev_private;
11581 struct intel_plane_state *old_plane_state =
11582 to_intel_plane_state(plane->state);
11583 int idx = intel_crtc->base.base.id, ret;
11584 int i = drm_plane_index(plane);
11585 bool mode_changed = needs_modeset(crtc_state);
11586 bool was_crtc_enabled = crtc->state->active;
11587 bool is_crtc_enabled = crtc_state->active;
11588
11589 bool turn_off, turn_on, visible, was_visible;
11590 struct drm_framebuffer *fb = plane_state->fb;
11591
11592 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11593 plane->type != DRM_PLANE_TYPE_CURSOR) {
11594 ret = skl_update_scaler_plane(
11595 to_intel_crtc_state(crtc_state),
11596 to_intel_plane_state(plane_state));
11597 if (ret)
11598 return ret;
11599 }
11600
11601 /*
11602 * Disabling a plane is always okay; we just need to update
11603 * fb tracking in a special way since cleanup_fb() won't
11604 * get called by the plane helpers.
11605 */
11606 if (old_plane_state->base.fb && !fb)
11607 intel_crtc->atomic.disabled_planes |= 1 << i;
11608
da20eabd
ML		 11609 was_visible = old_plane_state->visible;
11610 visible = to_intel_plane_state(plane_state)->visible;
11611
11612 if (!was_crtc_enabled && WARN_ON(was_visible))
11613 was_visible = false;
11614
11615 if (!is_crtc_enabled && WARN_ON(visible))
11616 visible = false;
11617
11618 if (!was_visible && !visible)
11619 return 0;
11620
11621 turn_off = was_visible && (!visible || mode_changed);
11622 turn_on = visible && (!was_visible || mode_changed);
11623
11624 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11625 plane->base.id, fb ? fb->base.id : -1);
11626
11627 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11628 plane->base.id, was_visible, visible,
11629 turn_off, turn_on, mode_changed);
11630
852eb00d 11631 if (turn_on) {
f015c551 11632 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11633 /* must disable cxsr around plane enable/disable */
11634 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11635 intel_crtc->atomic.disable_cxsr = true;
11636 /* to potentially re-enable cxsr */
11637 intel_crtc->atomic.wait_vblank = true;
11638 intel_crtc->atomic.update_wm_post = true;
11639 }
11640 } else if (turn_off) {
f015c551 11641 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11642 /* must disable cxsr around plane enable/disable */
11643 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11644 if (is_crtc_enabled)
11645 intel_crtc->atomic.wait_vblank = true;
11646 intel_crtc->atomic.disable_cxsr = true;
11647 }
11648 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11649 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11650 }
da20eabd 11651
a9ff8714
VS		 11652 if (visible)
11653 intel_crtc->atomic.fb_bits |=
11654 to_intel_plane(plane)->frontbuffer_bit;
11655
da20eabd
ML		 11656 switch (plane->type) {
11657 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11658 intel_crtc->atomic.wait_for_flips = true;
11659 intel_crtc->atomic.pre_disable_primary = turn_off;
11660 intel_crtc->atomic.post_enable_primary = turn_on;
11661
066cf55b
RV		 11662 if (turn_off) {
11663 /*
11664 * FIXME: Actually if we will still have any other
11665 * plane enabled on the pipe we could let IPS enabled
11666 * still, but for now lets consider that when we make
11667 * primary invisible by setting DSPCNTR to 0 on
11668 * update_primary_plane function IPS needs to be
11669 * disable.
11670 */
11671 intel_crtc->atomic.disable_ips = true;
11672
da20eabd 11673 intel_crtc->atomic.disable_fbc = true;
066cf55b 11674 }
da20eabd
ML		 11675
11676 /*
11677 * FBC does not work on some platforms for rotated
11678 * planes, so disable it when rotation is not 0 and
11679 * update it when rotation is set back to 0.
11680 *
11681 * FIXME: This is redundant with the fbc update done in
11682 * the primary plane enable function except that that
11683 * one is done too late. We eventually need to unify
11684 * this.
11685 */
11686
11687 if (visible &&
11688 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11689 dev_priv->fbc.crtc == intel_crtc &&
11690 plane_state->rotation != BIT(DRM_ROTATE_0))
11691 intel_crtc->atomic.disable_fbc = true;
11692
11693 /*
11694 * BDW signals flip done immediately if the plane
11695 * is disabled, even if the plane enable is already
11696 * armed to occur at the next vblank :(
11697 */
11698 if (turn_on && IS_BROADWELL(dev))
11699 intel_crtc->atomic.wait_vblank = true;
11700
11701 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11702 break;
11703 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11704 break;
11705 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11706 if (turn_off && !mode_changed) {
da20eabd
ML		 11707 intel_crtc->atomic.wait_vblank = true;
11708 intel_crtc->atomic.update_sprite_watermarks |=
11709 1 << i;
11710 }
da20eabd
ML		 11711 }
11712 return 0;
11713}
11714
6d3a1ce7
ML		 11715static bool encoders_cloneable(const struct intel_encoder *a,
11716 const struct intel_encoder *b)
11717{
11718 /* masks could be asymmetric, so check both ways */
11719 return a == b || (a->cloneable & (1 << b->type) &&
11720 b->cloneable & (1 << a->type));
11721}
11722
11723static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11724 struct intel_crtc *crtc,
11725 struct intel_encoder *encoder)
11726{
11727 struct intel_encoder *source_encoder;
11728 struct drm_connector *connector;
11729 struct drm_connector_state *connector_state;
11730 int i;
11731
11732 for_each_connector_in_state(state, connector, connector_state, i) {
11733 if (connector_state->crtc != &crtc->base)
11734 continue;
11735
11736 source_encoder =
11737 to_intel_encoder(connector_state->best_encoder);
11738 if (!encoders_cloneable(encoder, source_encoder))
11739 return false;
11740 }
11741
11742 return true;
11743}
11744
11745static bool check_encoder_cloning(struct drm_atomic_state *state,
11746 struct intel_crtc *crtc)
11747{
11748 struct intel_encoder *encoder;
11749 struct drm_connector *connector;
11750 struct drm_connector_state *connector_state;
11751 int i;
11752
11753 for_each_connector_in_state(state, connector, connector_state, i) {
11754 if (connector_state->crtc != &crtc->base)
11755 continue;
11756
11757 encoder = to_intel_encoder(connector_state->best_encoder);
11758 if (!check_single_encoder_cloning(state, crtc, encoder))
11759 return false;
11760 }
11761
11762 return true;
11763}
11764
d032ffa0
ML		 11765static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11766 struct drm_crtc_state *crtc_state)
11767{
11768 struct intel_crtc_state *pipe_config =
11769 to_intel_crtc_state(crtc_state);
11770 struct drm_plane *p;
11771 unsigned visible_mask = 0;
11772
11773 drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11774 struct drm_plane_state *plane_state =
11775 drm_atomic_get_existing_plane_state(crtc_state->state, p);
11776
11777 if (WARN_ON(!plane_state))
11778 continue;
11779
11780 if (!plane_state->fb)
11781 crtc_state->plane_mask &=
11782 ~(1 << drm_plane_index(p));
11783 else if (to_intel_plane_state(plane_state)->visible)
11784 visible_mask |= 1 << drm_plane_index(p);
11785 }
11786
11787 if (!visible_mask)
11788 return;
11789
11790 pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11791}
11792
6d3a1ce7
ML		 11793static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11794 struct drm_crtc_state *crtc_state)
11795{
cf5a15be 11796 struct drm_device *dev = crtc->dev;
ad421372 11797 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11799 struct intel_crtc_state *pipe_config =
11800 to_intel_crtc_state(crtc_state);
6d3a1ce7 11801 struct drm_atomic_state *state = crtc_state->state;
ad421372 11802 int ret, idx = crtc->base.id;
6d3a1ce7
ML		 11803 bool mode_changed = needs_modeset(crtc_state);
11804
11805 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11806 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11807 return -EINVAL;
11808 }
11809
11810 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11811 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11812 idx, crtc->state->active, intel_crtc->active);
11813
d032ffa0
ML		 11814 /* plane mask is fixed up after all initial planes are calculated */
11815 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11816 intel_crtc_check_initial_planes(crtc, crtc_state);
11817
852eb00d
VS		 11818 if (mode_changed && !crtc_state->active)
11819 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11820
ad421372
ML		 11821 if (mode_changed && crtc_state->enable &&
11822 dev_priv->display.crtc_compute_clock &&
11823 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11824 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11825 pipe_config);
11826 if (ret)
11827 return ret;
11828 }
11829
cf5a15be 11830 return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
6d3a1ce7
ML		 11831}
11832
65b38e0d 11833static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11834 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11835 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11836 .atomic_begin = intel_begin_crtc_commit,
11837 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11838 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11839};
11840
9a935856
DV		 11841/**
11842 * intel_modeset_update_staged_output_state
11843 *
11844 * Updates the staged output configuration state, e.g. after we've read out the
11845 * current hw state.
11846 */
11847static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11848{
7668851f 11849 struct intel_crtc *crtc;
9a935856
DV		 11850 struct intel_encoder *encoder;
11851 struct intel_connector *connector;
f6e5b160 11852
3a3371ff 11853 for_each_intel_connector(dev, connector) {
9a935856
DV		 11854 connector->new_encoder =
11855 to_intel_encoder(connector->base.encoder);
11856 }
f6e5b160 11857
b2784e15 11858 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11859 encoder->new_crtc =
11860 to_intel_crtc(encoder->base.crtc);
11861 }
7668851f 11862
d3fcc808 11863 for_each_intel_crtc(dev, crtc) {
83d65738 11864 crtc->new_enabled = crtc->base.state->enable;
7668851f 11865 }
f6e5b160
CW		 11866}
11867
d29b2f9d
ACO		 11868/* Transitional helper to copy current connector/encoder state to
11869 * connector->state. This is needed so that code that is partially
11870 * converted to atomic does the right thing.
11871 */
11872static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11873{
11874 struct intel_connector *connector;
11875
11876 for_each_intel_connector(dev, connector) {
11877 if (connector->base.encoder) {
11878 connector->base.state->best_encoder =
11879 connector->base.encoder;
11880 connector->base.state->crtc =
11881 connector->base.encoder->crtc;
11882 } else {
11883 connector->base.state->best_encoder = NULL;
11884 connector->base.state->crtc = NULL;
11885 }
11886 }
11887}
11888
050f7aeb 11889static void
eba905b2 11890connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11891 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11892{
11893 int bpp = pipe_config->pipe_bpp;
11894
11895 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11896 connector->base.base.id,
c23cc417 11897 connector->base.name);
050f7aeb
DV		 11898
11899 /* Don't use an invalid EDID bpc value */
11900 if (connector->base.display_info.bpc &&
11901 connector->base.display_info.bpc * 3 < bpp) {
11902 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11903 bpp, connector->base.display_info.bpc*3);
11904 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11905 }
11906
11907 /* Clamp bpp to 8 on screens without EDID 1.4 */
11908 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11909 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11910 bpp);
11911 pipe_config->pipe_bpp = 24;
11912 }
11913}
11914
4e53c2e0 11915static int
050f7aeb 11916compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11917 struct intel_crtc_state *pipe_config)
4e53c2e0 11918{
050f7aeb 11919 struct drm_device *dev = crtc->base.dev;
1486017f 11920 struct drm_atomic_state *state;
da3ced29
ACO		 11921 struct drm_connector *connector;
11922 struct drm_connector_state *connector_state;
1486017f 11923 int bpp, i;
4e53c2e0 11924
d328c9d7 11925 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11926 bpp = 10*3;
d328c9d7
DV		 11927 else if (INTEL_INFO(dev)->gen >= 5)
11928 bpp = 12*3;
11929 else
11930 bpp = 8*3;
11931
4e53c2e0 11932
4e53c2e0
DV		 11933 pipe_config->pipe_bpp = bpp;
11934
1486017f
ACO		 11935 state = pipe_config->base.state;
11936
4e53c2e0 11937 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11938 for_each_connector_in_state(state, connector, connector_state, i) {
11939 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11940 continue;
11941
da3ced29
ACO		 11942 connected_sink_compute_bpp(to_intel_connector(connector),
11943 pipe_config);
4e53c2e0
DV		 11944 }
11945
11946 return bpp;
11947}
11948
644db711
DV		 11949static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11950{
11951 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11952 "type: 0x%x flags: 0x%x\n",
1342830c 11953 mode->crtc_clock,
644db711
DV		 11954 mode->crtc_hdisplay, mode->crtc_hsync_start,
11955 mode->crtc_hsync_end, mode->crtc_htotal,
11956 mode->crtc_vdisplay, mode->crtc_vsync_start,
11957 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11958}
11959
c0b03411 11960static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11961 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11962 const char *context)
11963{
6a60cd87
CK		 11964 struct drm_device *dev = crtc->base.dev;
11965 struct drm_plane *plane;
11966 struct intel_plane *intel_plane;
11967 struct intel_plane_state *state;
11968 struct drm_framebuffer *fb;
11969
11970 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11971 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11972
11973 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11974 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11975 pipe_config->pipe_bpp, pipe_config->dither);
11976 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11977 pipe_config->has_pch_encoder,
11978 pipe_config->fdi_lanes,
11979 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11980 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11981 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11982 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11983 pipe_config->has_dp_encoder,
11984 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11985 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11986 pipe_config->dp_m_n.tu);
b95af8be
VK		 11987
11988 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11989 pipe_config->has_dp_encoder,
11990 pipe_config->dp_m2_n2.gmch_m,
11991 pipe_config->dp_m2_n2.gmch_n,
11992 pipe_config->dp_m2_n2.link_m,
11993 pipe_config->dp_m2_n2.link_n,
11994 pipe_config->dp_m2_n2.tu);
11995
55072d19
DV		 11996 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11997 pipe_config->has_audio,
11998 pipe_config->has_infoframe);
11999
c0b03411 12000 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 12001 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 12002 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 12003 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12004 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 12005 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 12006 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12007 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 12008 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12009 crtc->num_scalers,
12010 pipe_config->scaler_state.scaler_users,
12011 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 12012 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12013 pipe_config->gmch_pfit.control,
12014 pipe_config->gmch_pfit.pgm_ratios,
12015 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12016 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12017 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 12018 pipe_config->pch_pfit.size,
12019 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12020 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12021 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12022
415ff0f6 12023 if (IS_BROXTON(dev)) {
05712c15 12024 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 12025 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 12026 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 12027 pipe_config->ddi_pll_sel,
12028 pipe_config->dpll_hw_state.ebb0,
05712c15 12029 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 12030 pipe_config->dpll_hw_state.pll0,
12031 pipe_config->dpll_hw_state.pll1,
12032 pipe_config->dpll_hw_state.pll2,
12033 pipe_config->dpll_hw_state.pll3,
12034 pipe_config->dpll_hw_state.pll6,
12035 pipe_config->dpll_hw_state.pll8,
05712c15 12036 pipe_config->dpll_hw_state.pll9,
c8453338 12037 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 12038 pipe_config->dpll_hw_state.pcsdw12);
12039 } else if (IS_SKYLAKE(dev)) {
12040 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12041 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12042 pipe_config->ddi_pll_sel,
12043 pipe_config->dpll_hw_state.ctrl1,
12044 pipe_config->dpll_hw_state.cfgcr1,
12045 pipe_config->dpll_hw_state.cfgcr2);
12046 } else if (HAS_DDI(dev)) {
12047 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12048 pipe_config->ddi_pll_sel,
12049 pipe_config->dpll_hw_state.wrpll);
12050 } else {
12051 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12052 "fp0: 0x%x, fp1: 0x%x\n",
12053 pipe_config->dpll_hw_state.dpll,
12054 pipe_config->dpll_hw_state.dpll_md,
12055 pipe_config->dpll_hw_state.fp0,
12056 pipe_config->dpll_hw_state.fp1);
12057 }
12058
6a60cd87
CK		 12059 DRM_DEBUG_KMS("planes on this crtc\n");
12060 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12061 intel_plane = to_intel_plane(plane);
12062 if (intel_plane->pipe != crtc->pipe)
12063 continue;
12064
12065 state = to_intel_plane_state(plane->state);
12066 fb = state->base.fb;
12067 if (!fb) {
12068 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12069 "disabled, scaler_id = %d\n",
12070 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12071 plane->base.id, intel_plane->pipe,
12072 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12073 drm_plane_index(plane), state->scaler_id);
12074 continue;
12075 }
12076
12077 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12078 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12079 plane->base.id, intel_plane->pipe,
12080 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12081 drm_plane_index(plane));
12082 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12083 fb->base.id, fb->width, fb->height, fb->pixel_format);
12084 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12085 state->scaler_id,
12086 state->src.x1 >> 16, state->src.y1 >> 16,
12087 drm_rect_width(&state->src) >> 16,
12088 drm_rect_height(&state->src) >> 16,
12089 state->dst.x1, state->dst.y1,
12090 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12091 }
c0b03411
DV		 12092}
12093
5448a00d 12094static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12095{
5448a00d
ACO		 12096 struct drm_device *dev = state->dev;
12097 struct intel_encoder *encoder;
da3ced29 12098 struct drm_connector *connector;
5448a00d 12099 struct drm_connector_state *connector_state;
00f0b378 12100 unsigned int used_ports = 0;
5448a00d 12101 int i;
00f0b378
VS		 12102
12103 /*
12104 * Walk the connector list instead of the encoder
12105 * list to detect the problem on ddi platforms
12106 * where there's just one encoder per digital port.
12107 */
da3ced29 12108 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12109 if (!connector_state->best_encoder)
00f0b378
VS		 12110 continue;
12111
5448a00d
ACO		 12112 encoder = to_intel_encoder(connector_state->best_encoder);
12113
12114 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12115
12116 switch (encoder->type) {
12117 unsigned int port_mask;
12118 case INTEL_OUTPUT_UNKNOWN:
12119 if (WARN_ON(!HAS_DDI(dev)))
12120 break;
12121 case INTEL_OUTPUT_DISPLAYPORT:
12122 case INTEL_OUTPUT_HDMI:
12123 case INTEL_OUTPUT_EDP:
12124 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12125
12126 /* the same port mustn't appear more than once */
12127 if (used_ports & port_mask)
12128 return false;
12129
12130 used_ports |= port_mask;
12131 default:
12132 break;
12133 }
12134 }
12135
12136 return true;
12137}
12138
83a57153
ACO		 12139static void
12140clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12141{
12142 struct drm_crtc_state tmp_state;
663a3640 12143 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12144 struct intel_dpll_hw_state dpll_hw_state;
12145 enum intel_dpll_id shared_dpll;
8504c74c 12146 uint32_t ddi_pll_sel;
83a57153 12147
7546a384
ACO		 12148 /* FIXME: before the switch to atomic started, a new pipe_config was
12149 * kzalloc'd. Code that depends on any field being zero should be
12150 * fixed, so that the crtc_state can be safely duplicated. For now,
12151 * only fields that are know to not cause problems are preserved. */
12152
83a57153 12153 tmp_state = crtc_state->base;
663a3640 12154 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12155 shared_dpll = crtc_state->shared_dpll;
12156 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12157 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12158
83a57153 12159 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12160
83a57153 12161 crtc_state->base = tmp_state;
663a3640 12162 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12163 crtc_state->shared_dpll = shared_dpll;
12164 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12165 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12166}
12167
548ee15b 12168static int
b8cecdf5 12169intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12170 struct intel_crtc_state *pipe_config)
ee7b9f93 12171{
b359283a 12172 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12173 struct intel_encoder *encoder;
da3ced29 12174 struct drm_connector *connector;
0b901879 12175 struct drm_connector_state *connector_state;
d328c9d7 12176 int base_bpp, ret = -EINVAL;
0b901879 12177 int i;
e29c22c0 12178 bool retry = true;
ee7b9f93 12179
83a57153 12180 clear_intel_crtc_state(pipe_config);
7758a113 12181
e143a21c
DV		 12182 pipe_config->cpu_transcoder =
12183 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12184
2960bc9c
ID		 12185 /*
12186 * Sanitize sync polarity flags based on requested ones. If neither
12187 * positive or negative polarity is requested, treat this as meaning
12188 * negative polarity.
12189 */
2d112de7 12190 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12191 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12192 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12193
2d112de7 12194 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12195 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12196 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12197
050f7aeb
DV		 12198 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12199 * plane pixel format and any sink constraints into account. Returns the
12200 * source plane bpp so that dithering can be selected on mismatches
12201 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12202 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12203 pipe_config);
12204 if (base_bpp < 0)
4e53c2e0
DV		 12205 goto fail;
12206
e41a56be
VS		 12207 /*
12208 * Determine the real pipe dimensions. Note that stereo modes can
12209 * increase the actual pipe size due to the frame doubling and
12210 * insertion of additional space for blanks between the frame. This
12211 * is stored in the crtc timings. We use the requested mode to do this
12212 * computation to clearly distinguish it from the adjusted mode, which
12213 * can be changed by the connectors in the below retry loop.
12214 */
2d112de7 12215 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12216 &pipe_config->pipe_src_w,
12217 &pipe_config->pipe_src_h);
e41a56be 12218
e29c22c0 12219encoder_retry:
ef1b460d 12220 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12221 pipe_config->port_clock = 0;
ef1b460d 12222 pipe_config->pixel_multiplier = 1;
ff9a6750 12223
135c81b8 12224 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12225 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12226 CRTC_STEREO_DOUBLE);
135c81b8 12227
7758a113
DV		 12228 /* Pass our mode to the connectors and the CRTC to give them a chance to
12229 * adjust it according to limitations or connector properties, and also
12230 * a chance to reject the mode entirely.
47f1c6c9 12231 */
da3ced29 12232 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12233 if (connector_state->crtc != crtc)
7758a113 12234 continue;
7ae89233 12235
0b901879
ACO		 12236 encoder = to_intel_encoder(connector_state->best_encoder);
12237
efea6e8e
DV		 12238 if (!(encoder->compute_config(encoder, pipe_config))) {
12239 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12240 goto fail;
12241 }
ee7b9f93 12242 }
47f1c6c9 12243
ff9a6750
DV		 12244 /* Set default port clock if not overwritten by the encoder. Needs to be
12245 * done afterwards in case the encoder adjusts the mode. */
12246 if (!pipe_config->port_clock)
2d112de7 12247 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12248 * pipe_config->pixel_multiplier;
ff9a6750 12249
a43f6e0f 12250 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12251 if (ret < 0) {
7758a113
DV		 12252 DRM_DEBUG_KMS("CRTC fixup failed\n");
12253 goto fail;
ee7b9f93 12254 }
e29c22c0
DV		 12255
12256 if (ret == RETRY) {
12257 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12258 ret = -EINVAL;
12259 goto fail;
12260 }
12261
12262 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12263 retry = false;
12264 goto encoder_retry;
12265 }
12266
d328c9d7 12267 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12268 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12269 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12270
cdba954e
ACO		 12271 /* Check if we need to force a modeset */
12272 if (pipe_config->has_audio !=
85a96e7a 12273 to_intel_crtc_state(crtc->state)->has_audio) {
cdba954e 12274 pipe_config->base.mode_changed = true;
85a96e7a
ML		 12275 ret = drm_atomic_add_affected_planes(state, crtc);
12276 }
cdba954e
ACO		 12277
12278 /*
12279 * Note we have an issue here with infoframes: current code
12280 * only updates them on the full mode set path per hw
12281 * requirements. So here we should be checking for any
12282 * required changes and forcing a mode set.
12283 */
7758a113 12284fail:
548ee15b 12285 return ret;
ee7b9f93 12286}
47f1c6c9 12287
ea9d758d 12288static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12289{
ea9d758d 12290 struct drm_encoder *encoder;
f6e5b160 12291 struct drm_device *dev = crtc->dev;
f6e5b160 12292
ea9d758d
DV		 12293 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12294 if (encoder->crtc == crtc)
12295 return true;
12296
12297 return false;
12298}
12299
12300static void
0a9ab303 12301intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12302{
0a9ab303 12303 struct drm_device *dev = state->dev;
ea9d758d 12304 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12305 struct drm_crtc *crtc;
12306 struct drm_crtc_state *crtc_state;
ea9d758d
DV		 12307 struct drm_connector *connector;
12308
de419ab6 12309 intel_shared_dpll_commit(state);
ba41c0de 12310
b2784e15 12311 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12312 if (!intel_encoder->base.crtc)
12313 continue;
12314
69024de8
ML		 12315 crtc = intel_encoder->base.crtc;
12316 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12317 if (!crtc_state || !needs_modeset(crtc->state))
12318 continue;
ea9d758d 12319
69024de8 12320 intel_encoder->connectors_active = false;
ea9d758d
DV		 12321 }
12322
3cb480bc 12323 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
f7217905 12324 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12325
7668851f 12326 /* Double check state. */
0a9ab303
ACO		 12327 for_each_crtc(dev, crtc) {
12328 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12329
12330 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12331
12332 /* Update hwmode for vblank functions */
12333 if (crtc->state->active)
12334 crtc->hwmode = crtc->state->adjusted_mode;
12335 else
12336 crtc->hwmode.crtc_clock = 0;
ea9d758d
DV		 12337 }
12338
12339 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12340 if (!connector->encoder || !connector->encoder->crtc)
12341 continue;
12342
69024de8
ML		 12343 crtc = connector->encoder->crtc;
12344 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12345 if (!crtc_state || !needs_modeset(crtc->state))
12346 continue;
ea9d758d 12347
53d9f4e9 12348 if (crtc->state->active) {
69024de8
ML		 12349 struct drm_property *dpms_property =
12350 dev->mode_config.dpms_property;
68d34720 12351
69024de8
ML		 12352 connector->dpms = DRM_MODE_DPMS_ON;
12353 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12354
69024de8
ML		 12355 intel_encoder = to_intel_encoder(connector->encoder);
12356 intel_encoder->connectors_active = true;
12357 } else
12358 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12359 }
ea9d758d
DV		 12360}
12361
3bd26263 12362static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12363{
3bd26263 12364 int diff;
f1f644dc
JB		 12365
12366 if (clock1 == clock2)
12367 return true;
12368
12369 if (!clock1 || !clock2)
12370 return false;
12371
12372 diff = abs(clock1 - clock2);
12373
12374 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12375 return true;
12376
12377 return false;
12378}
12379
25c5b266
DV		 12380#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12381 list_for_each_entry((intel_crtc), \
12382 &(dev)->mode_config.crtc_list, \
12383 base.head) \
0973f18f 12384 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12385
0e8ffe1b 12386static bool
2fa2fe9a 12387intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12388 struct intel_crtc_state *current_config,
12389 struct intel_crtc_state *pipe_config)
0e8ffe1b 12390{
66e985c0
DV		 12391#define PIPE_CONF_CHECK_X(name) \
12392 if (current_config->name != pipe_config->name) { \
12393 DRM_ERROR("mismatch in " #name " " \
12394 "(expected 0x%08x, found 0x%08x)\n", \
12395 current_config->name, \
12396 pipe_config->name); \
12397 return false; \
12398 }
12399
08a24034
DV		 12400#define PIPE_CONF_CHECK_I(name) \
12401 if (current_config->name != pipe_config->name) { \
12402 DRM_ERROR("mismatch in " #name " " \
12403 "(expected %i, found %i)\n", \
12404 current_config->name, \
12405 pipe_config->name); \
12406 return false; \
88adfff1
DV		 12407 }
12408
b95af8be
VK		 12409/* This is required for BDW+ where there is only one set of registers for
12410 * switching between high and low RR.
12411 * This macro can be used whenever a comparison has to be made between one
12412 * hw state and multiple sw state variables.
12413 */
12414#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12415 if ((current_config->name != pipe_config->name) && \
12416 (current_config->alt_name != pipe_config->name)) { \
12417 DRM_ERROR("mismatch in " #name " " \
12418 "(expected %i or %i, found %i)\n", \
12419 current_config->name, \
12420 current_config->alt_name, \
12421 pipe_config->name); \
12422 return false; \
12423 }
12424
1bd1bd80
DV		 12425#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12426 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12427 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12428 "(expected %i, found %i)\n", \
12429 current_config->name & (mask), \
12430 pipe_config->name & (mask)); \
12431 return false; \
12432 }
12433
5e550656
VS		 12434#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12435 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12436 DRM_ERROR("mismatch in " #name " " \
12437 "(expected %i, found %i)\n", \
12438 current_config->name, \
12439 pipe_config->name); \
12440 return false; \
12441 }
12442
bb760063
DV		 12443#define PIPE_CONF_QUIRK(quirk) \
12444 ((current_config->quirks | pipe_config->quirks) & (quirk))
12445
eccb140b
DV		 12446 PIPE_CONF_CHECK_I(cpu_transcoder);
12447
08a24034
DV		 12448 PIPE_CONF_CHECK_I(has_pch_encoder);
12449 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12450 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12451 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12452 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12453 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12454 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12455
eb14cb74 12456 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12457
12458 if (INTEL_INFO(dev)->gen < 8) {
12459 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12460 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12461 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12462 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12463 PIPE_CONF_CHECK_I(dp_m_n.tu);
12464
12465 if (current_config->has_drrs) {
12466 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12467 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12468 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12469 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12470 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12471 }
12472 } else {
12473 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12474 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12475 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12476 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12477 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12478 }
eb14cb74 12479
2d112de7
ACO		 12480 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12481 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12482 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12483 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12484 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12485 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12486
2d112de7
ACO		 12487 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12488 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12489 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12490 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12491 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12492 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12493
c93f54cf 12494 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12495 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12496 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12497 IS_VALLEYVIEW(dev))
12498 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12499 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12500
9ed109a7
DV		 12501 PIPE_CONF_CHECK_I(has_audio);
12502
2d112de7 12503 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12504 DRM_MODE_FLAG_INTERLACE);
12505
bb760063 12506 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12507 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12508 DRM_MODE_FLAG_PHSYNC);
2d112de7 12509 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12510 DRM_MODE_FLAG_NHSYNC);
2d112de7 12511 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12512 DRM_MODE_FLAG_PVSYNC);
2d112de7 12513 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12514 DRM_MODE_FLAG_NVSYNC);
12515 }
045ac3b5 12516
37327abd
VS		 12517 PIPE_CONF_CHECK_I(pipe_src_w);
12518 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12519
9953599b
DV		 12520 /*
12521 * FIXME: BIOS likes to set up a cloned config with lvds+external
12522 * screen. Since we don't yet re-compute the pipe config when moving
12523 * just the lvds port away to another pipe the sw tracking won't match.
12524 *
12525 * Proper atomic modesets with recomputed global state will fix this.
12526 * Until then just don't check gmch state for inherited modes.
12527 */
12528 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12529 PIPE_CONF_CHECK_I(gmch_pfit.control);
12530 /* pfit ratios are autocomputed by the hw on gen4+ */
12531 if (INTEL_INFO(dev)->gen < 4)
12532 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12533 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12534 }
12535
fd4daa9c
CW		 12536 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12537 if (current_config->pch_pfit.enabled) {
12538 PIPE_CONF_CHECK_I(pch_pfit.pos);
12539 PIPE_CONF_CHECK_I(pch_pfit.size);
12540 }
2fa2fe9a 12541
a1b2278e
CK		 12542 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12543
e59150dc
JB		 12544 /* BDW+ don't expose a synchronous way to read the state */
12545 if (IS_HASWELL(dev))
12546 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12547
282740f7
VS		 12548 PIPE_CONF_CHECK_I(double_wide);
12549
26804afd
DV		 12550 PIPE_CONF_CHECK_X(ddi_pll_sel);
12551
c0d43d62 12552 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12553 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12554 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12555 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12556 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12557 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12558 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12559 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12560 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12561
42571aef
VS		 12562 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12563 PIPE_CONF_CHECK_I(pipe_bpp);
12564
2d112de7 12565 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12566 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12567
66e985c0 12568#undef PIPE_CONF_CHECK_X
08a24034 12569#undef PIPE_CONF_CHECK_I
b95af8be 12570#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12571#undef PIPE_CONF_CHECK_FLAGS
5e550656 12572#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12573#undef PIPE_CONF_QUIRK
88adfff1 12574
0e8ffe1b
DV		 12575 return true;
12576}
12577
08db6652
DL		 12578static void check_wm_state(struct drm_device *dev)
12579{
12580 struct drm_i915_private *dev_priv = dev->dev_private;
12581 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12582 struct intel_crtc *intel_crtc;
12583 int plane;
12584
12585 if (INTEL_INFO(dev)->gen < 9)
12586 return;
12587
12588 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12589 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12590
12591 for_each_intel_crtc(dev, intel_crtc) {
12592 struct skl_ddb_entry *hw_entry, *sw_entry;
12593 const enum pipe pipe = intel_crtc->pipe;
12594
12595 if (!intel_crtc->active)
12596 continue;
12597
12598 /* planes */
dd740780 12599 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12600 hw_entry = &hw_ddb.plane[pipe][plane];
12601 sw_entry = &sw_ddb->plane[pipe][plane];
12602
12603 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12604 continue;
12605
12606 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12607 "(expected (%u,%u), found (%u,%u))\n",
12608 pipe_name(pipe), plane + 1,
12609 sw_entry->start, sw_entry->end,
12610 hw_entry->start, hw_entry->end);
12611 }
12612
12613 /* cursor */
12614 hw_entry = &hw_ddb.cursor[pipe];
12615 sw_entry = &sw_ddb->cursor[pipe];
12616
12617 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12618 continue;
12619
12620 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12621 "(expected (%u,%u), found (%u,%u))\n",
12622 pipe_name(pipe),
12623 sw_entry->start, sw_entry->end,
12624 hw_entry->start, hw_entry->end);
12625 }
12626}
12627
91d1b4bd
DV		 12628static void
12629check_connector_state(struct drm_device *dev)
8af6cf88 12630{
8af6cf88
DV		 12631 struct intel_connector *connector;
12632
3a3371ff 12633 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12634 /* This also checks the encoder/connector hw state with the
12635 * ->get_hw_state callbacks. */
12636 intel_connector_check_state(connector);
12637
e2c719b7 12638 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12639 "connector's staged encoder doesn't match current encoder\n");
12640 }
91d1b4bd
DV		 12641}
12642
12643static void
12644check_encoder_state(struct drm_device *dev)
12645{
12646 struct intel_encoder *encoder;
12647 struct intel_connector *connector;
8af6cf88 12648
b2784e15 12649 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12650 bool enabled = false;
12651 bool active = false;
12652 enum pipe pipe, tracked_pipe;
12653
12654 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12655 encoder->base.base.id,
8e329a03 12656 encoder->base.name);
8af6cf88 12657
e2c719b7 12658 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12659 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12660 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12661 "encoder's active_connectors set, but no crtc\n");
12662
3a3371ff 12663 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12664 if (connector->base.encoder != &encoder->base)
12665 continue;
12666 enabled = true;
12667 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12668 active = true;
12669 }
0e32b39c
DA		 12670 /*
12671 * for MST connectors if we unplug the connector is gone
12672 * away but the encoder is still connected to a crtc
12673 * until a modeset happens in response to the hotplug.
12674 */
12675 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12676 continue;
12677
e2c719b7 12678 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12679 "encoder's enabled state mismatch "
12680 "(expected %i, found %i)\n",
12681 !!encoder->base.crtc, enabled);
e2c719b7 12682 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12683 "active encoder with no crtc\n");
12684
e2c719b7 12685 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12686 "encoder's computed active state doesn't match tracked active state "
12687 "(expected %i, found %i)\n", active, encoder->connectors_active);
12688
12689 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12690 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12691 "encoder's hw state doesn't match sw tracking "
12692 "(expected %i, found %i)\n",
12693 encoder->connectors_active, active);
12694
12695 if (!encoder->base.crtc)
12696 continue;
12697
12698 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12699 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12700 "active encoder's pipe doesn't match"
12701 "(expected %i, found %i)\n",
12702 tracked_pipe, pipe);
12703
12704 }
91d1b4bd
DV		 12705}
12706
12707static void
12708check_crtc_state(struct drm_device *dev)
12709{
fbee40df 12710 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12711 struct intel_crtc *crtc;
12712 struct intel_encoder *encoder;
5cec258b 12713 struct intel_crtc_state pipe_config;
8af6cf88 12714
d3fcc808 12715 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12716 bool enabled = false;
12717 bool active = false;
12718
045ac3b5
JB		 12719 memset(&pipe_config, 0, sizeof(pipe_config));
12720
8af6cf88
DV		 12721 DRM_DEBUG_KMS("[CRTC:%d]\n",
12722 crtc->base.base.id);
12723
83d65738 12724 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12725 "active crtc, but not enabled in sw tracking\n");
12726
b2784e15 12727 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12728 if (encoder->base.crtc != &crtc->base)
12729 continue;
12730 enabled = true;
12731 if (encoder->connectors_active)
12732 active = true;
12733 }
6c49f241 12734
e2c719b7 12735 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12736 "crtc's computed active state doesn't match tracked active state "
12737 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12738 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12739 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12740 "(expected %i, found %i)\n", enabled,
12741 crtc->base.state->enable);
8af6cf88 12742
0e8ffe1b
DV		 12743 active = dev_priv->display.get_pipe_config(crtc,
12744 &pipe_config);
d62cf62a 12745
b6b5d049
VS		 12746 /* hw state is inconsistent with the pipe quirk */
12747 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12748 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12749 active = crtc->active;
12750
b2784e15 12751 for_each_intel_encoder(dev, encoder) {
3eaba51c 12752 enum pipe pipe;
6c49f241
DV		 12753 if (encoder->base.crtc != &crtc->base)
12754 continue;
1d37b689 12755 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12756 encoder->get_config(encoder, &pipe_config);
12757 }
12758
e2c719b7 12759 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12760 "crtc active state doesn't match with hw state "
12761 "(expected %i, found %i)\n", crtc->active, active);
12762
53d9f4e9
ML		 12763 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12764 "transitional active state does not match atomic hw state "
12765 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12766
c0b03411 12767 if (active &&
6e3c9717 12768 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12769 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12770 intel_dump_pipe_config(crtc, &pipe_config,
12771 "[hw state]");
6e3c9717 12772 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12773 "[sw state]");
12774 }
8af6cf88
DV		 12775 }
12776}
12777
91d1b4bd
DV		 12778static void
12779check_shared_dpll_state(struct drm_device *dev)
12780{
fbee40df 12781 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12782 struct intel_crtc *crtc;
12783 struct intel_dpll_hw_state dpll_hw_state;
12784 int i;
5358901f
DV		 12785
12786 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12787 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12788 int enabled_crtcs = 0, active_crtcs = 0;
12789 bool active;
12790
12791 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12792
12793 DRM_DEBUG_KMS("%s\n", pll->name);
12794
12795 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12796
e2c719b7 12797 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12798 "more active pll users than references: %i vs %i\n",
3e369b76 12799 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12800 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12801 "pll in active use but not on in sw tracking\n");
e2c719b7 12802 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12803 "pll in on but not on in use in sw tracking\n");
e2c719b7 12804 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12805 "pll on state mismatch (expected %i, found %i)\n",
12806 pll->on, active);
12807
d3fcc808 12808 for_each_intel_crtc(dev, crtc) {
83d65738 12809 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12810 enabled_crtcs++;
12811 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12812 active_crtcs++;
12813 }
e2c719b7 12814 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12815 "pll active crtcs mismatch (expected %i, found %i)\n",
12816 pll->active, active_crtcs);
e2c719b7 12817 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12818 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12819 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12820
e2c719b7 12821 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12822 sizeof(dpll_hw_state)),
12823 "pll hw state mismatch\n");
5358901f 12824 }
8af6cf88
DV		 12825}
12826
91d1b4bd
DV		 12827void
12828intel_modeset_check_state(struct drm_device *dev)
12829{
08db6652 12830 check_wm_state(dev);
91d1b4bd
DV		 12831 check_connector_state(dev);
12832 check_encoder_state(dev);
12833 check_crtc_state(dev);
12834 check_shared_dpll_state(dev);
12835}
12836
5cec258b 12837void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12838 int dotclock)
12839{
12840 /*
12841 * FDI already provided one idea for the dotclock.
12842 * Yell if the encoder disagrees.
12843 */
2d112de7 12844 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12845 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12846 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12847}
12848
80715b2f
VS		 12849static void update_scanline_offset(struct intel_crtc *crtc)
12850{
12851 struct drm_device *dev = crtc->base.dev;
12852
12853 /*
12854 * The scanline counter increments at the leading edge of hsync.
12855 *
12856 * On most platforms it starts counting from vtotal-1 on the
12857 * first active line. That means the scanline counter value is
12858 * always one less than what we would expect. Ie. just after
12859 * start of vblank, which also occurs at start of hsync (on the
12860 * last active line), the scanline counter will read vblank_start-1.
12861 *
12862 * On gen2 the scanline counter starts counting from 1 instead
12863 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12864 * to keep the value positive), instead of adding one.
12865 *
12866 * On HSW+ the behaviour of the scanline counter depends on the output
12867 * type. For DP ports it behaves like most other platforms, but on HDMI
12868 * there's an extra 1 line difference. So we need to add two instead of
12869 * one to the value.
12870 */
12871 if (IS_GEN2(dev)) {
6e3c9717 12872 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12873 int vtotal;
12874
12875 vtotal = mode->crtc_vtotal;
12876 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12877 vtotal /= 2;
12878
12879 crtc->scanline_offset = vtotal - 1;
12880 } else if (HAS_DDI(dev) &&
409ee761 12881 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12882 crtc->scanline_offset = 2;
12883 } else
12884 crtc->scanline_offset = 1;
12885}
12886
ad421372 12887static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12888{
225da59b 12889 struct drm_device *dev = state->dev;
ed6739ef 12890 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12891 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12892 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12893 struct intel_crtc_state *intel_crtc_state;
12894 struct drm_crtc *crtc;
12895 struct drm_crtc_state *crtc_state;
0a9ab303 12896 int i;
ed6739ef
ACO		 12897
12898 if (!dev_priv->display.crtc_compute_clock)
ad421372 12899 return;
ed6739ef 12900
0a9ab303 12901 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12902 int dpll;
12903
0a9ab303 12904 intel_crtc = to_intel_crtc(crtc);
4978cc93 12905 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12906 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12907
ad421372 12908 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12909 continue;
12910
ad421372 12911 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12912
ad421372
ML		 12913 if (!shared_dpll)
12914 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12915
ad421372
ML		 12916 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12917 }
ed6739ef
ACO		 12918}
12919
99d736a2
ML		 12920/*
12921 * This implements the workaround described in the "notes" section of the mode
12922 * set sequence documentation. When going from no pipes or single pipe to
12923 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12924 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12925 */
12926static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12927{
12928 struct drm_crtc_state *crtc_state;
12929 struct intel_crtc *intel_crtc;
12930 struct drm_crtc *crtc;
12931 struct intel_crtc_state *first_crtc_state = NULL;
12932 struct intel_crtc_state *other_crtc_state = NULL;
12933 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12934 int i;
12935
12936 /* look at all crtc's that are going to be enabled in during modeset */
12937 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12938 intel_crtc = to_intel_crtc(crtc);
12939
12940 if (!crtc_state->active || !needs_modeset(crtc_state))
12941 continue;
12942
12943 if (first_crtc_state) {
12944 other_crtc_state = to_intel_crtc_state(crtc_state);
12945 break;
12946 } else {
12947 first_crtc_state = to_intel_crtc_state(crtc_state);
12948 first_pipe = intel_crtc->pipe;
12949 }
12950 }
12951
12952 /* No workaround needed? */
12953 if (!first_crtc_state)
12954 return 0;
12955
12956 /* w/a possibly needed, check how many crtc's are already enabled. */
12957 for_each_intel_crtc(state->dev, intel_crtc) {
12958 struct intel_crtc_state *pipe_config;
12959
12960 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12961 if (IS_ERR(pipe_config))
12962 return PTR_ERR(pipe_config);
12963
12964 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12965
12966 if (!pipe_config->base.active ||
12967 needs_modeset(&pipe_config->base))
12968 continue;
12969
12970 /* 2 or more enabled crtcs means no need for w/a */
12971 if (enabled_pipe != INVALID_PIPE)
12972 return 0;
12973
12974 enabled_pipe = intel_crtc->pipe;
12975 }
12976
12977 if (enabled_pipe != INVALID_PIPE)
12978 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12979 else if (other_crtc_state)
12980 other_crtc_state->hsw_workaround_pipe = first_pipe;
12981
12982 return 0;
12983}
12984
27c329ed
ML		 12985static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12986{
12987 struct drm_crtc *crtc;
12988 struct drm_crtc_state *crtc_state;
12989 int ret = 0;
12990
12991 /* add all active pipes to the state */
12992 for_each_crtc(state->dev, crtc) {
12993 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12994 if (IS_ERR(crtc_state))
12995 return PTR_ERR(crtc_state);
12996
12997 if (!crtc_state->active || needs_modeset(crtc_state))
12998 continue;
12999
13000 crtc_state->mode_changed = true;
13001
13002 ret = drm_atomic_add_affected_connectors(state, crtc);
13003 if (ret)
13004 break;
13005
13006 ret = drm_atomic_add_affected_planes(state, crtc);
13007 if (ret)
13008 break;
13009 }
13010
13011 return ret;
13012}
13013
13014
054518dd 13015/* Code that should eventually be part of atomic_check() */
c347a676 13016static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 13017{
13018 struct drm_device *dev = state->dev;
27c329ed 13019 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 13020 int ret;
13021
b359283a
ML		 13022 if (!check_digital_port_conflicts(state)) {
13023 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13024 return -EINVAL;
13025 }
13026
054518dd
ACO		 13027 /*
13028 * See if the config requires any additional preparation, e.g.
13029 * to adjust global state with pipes off. We need to do this
13030 * here so we can get the modeset_pipe updated config for the new
13031 * mode set on this crtc. For other crtcs we need to use the
13032 * adjusted_mode bits in the crtc directly.
13033 */
27c329ed
ML		 13034 if (dev_priv->display.modeset_calc_cdclk) {
13035 unsigned int cdclk;
b432e5cf 13036
27c329ed
ML		 13037 ret = dev_priv->display.modeset_calc_cdclk(state);
13038
13039 cdclk = to_intel_atomic_state(state)->cdclk;
13040 if (!ret && cdclk != dev_priv->cdclk_freq)
13041 ret = intel_modeset_all_pipes(state);
13042
13043 if (ret < 0)
054518dd 13044 return ret;
27c329ed
ML		 13045 } else
13046 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13047
ad421372 13048 intel_modeset_clear_plls(state);
054518dd 13049
99d736a2 13050 if (IS_HASWELL(dev))
ad421372 13051 return haswell_mode_set_planes_workaround(state);
99d736a2 13052
ad421372 13053 return 0;
c347a676
ACO		 13054}
13055
13056static int
13057intel_modeset_compute_config(struct drm_atomic_state *state)
13058{
13059 struct drm_crtc *crtc;
13060 struct drm_crtc_state *crtc_state;
13061 int ret, i;
61333b60 13062 bool any_ms = false;
c347a676
ACO		 13063
13064 ret = drm_atomic_helper_check_modeset(state->dev, state);
054518dd
ACO		 13065 if (ret)
13066 return ret;
13067
c347a676 13068 for_each_crtc_in_state(state, crtc, crtc_state, i) {
61333b60
ML		 13069 if (!crtc_state->enable) {
13070 if (needs_modeset(crtc_state))
13071 any_ms = true;
c347a676 13072 continue;
61333b60 13073 }
c347a676 13074
d032ffa0
ML		 13075 if (to_intel_crtc_state(crtc_state)->quirks &
13076 PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13077 ret = drm_atomic_add_affected_planes(state, crtc);
13078 if (ret)
13079 return ret;
13080
13081 /*
13082 * We ought to handle i915.fastboot here.
13083 * If no modeset is required and the primary plane has
13084 * a fb, update the members of crtc_state as needed,
13085 * and run the necessary updates during vblank evasion.
13086 */
13087 }
13088
b359283a
ML		 13089 if (!needs_modeset(crtc_state)) {
13090 ret = drm_atomic_add_affected_connectors(state, crtc);
13091 if (ret)
13092 return ret;
13093 }
13094
13095 ret = intel_modeset_pipe_config(crtc,
13096 to_intel_crtc_state(crtc_state));
c347a676
ACO		 13097 if (ret)
13098 return ret;
13099
61333b60
ML		 13100 if (needs_modeset(crtc_state))
13101 any_ms = true;
13102
c347a676
ACO		 13103 intel_dump_pipe_config(to_intel_crtc(crtc),
13104 to_intel_crtc_state(crtc_state),
13105 "[modeset]");
13106 }
13107
61333b60
ML		 13108 if (any_ms) {
13109 ret = intel_modeset_checks(state);
13110
13111 if (ret)
13112 return ret;
27c329ed
ML		 13113 } else
13114 to_intel_atomic_state(state)->cdclk =
13115 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13116
13117 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13118}
13119
c72d969b 13120static int __intel_set_mode(struct drm_atomic_state *state)
a6778b3c 13121{
c72d969b 13122 struct drm_device *dev = state->dev;
fbee40df 13123 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13124 struct drm_crtc *crtc;
13125 struct drm_crtc_state *crtc_state;
c0c36b94 13126 int ret = 0;
0a9ab303 13127 int i;
61333b60 13128 bool any_ms = false;
a6778b3c 13129
d4afb8cc
ACO		 13130 ret = drm_atomic_helper_prepare_planes(dev, state);
13131 if (ret)
13132 return ret;
13133
1c5e19f8
ML		 13134 drm_atomic_helper_swap_state(dev, state);
13135
0a9ab303 13136 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13138
61333b60
ML		 13139 if (!needs_modeset(crtc->state))
13140 continue;
13141
13142 any_ms = true;
a539205a 13143 intel_pre_plane_update(intel_crtc);
460da916 13144
a539205a
ML		 13145 if (crtc_state->active) {
13146 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13147 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13148 intel_crtc->active = false;
13149 intel_disable_shared_dpll(intel_crtc);
a539205a 13150 }
b8cecdf5 13151 }
7758a113 13152
ea9d758d
DV		 13153 /* Only after disabling all output pipelines that will be changed can we
13154 * update the the output configuration. */
0a9ab303 13155 intel_modeset_update_state(state);
f6e5b160 13156
a821fc46
ACO		 13157 /* The state has been swaped above, so state actually contains the
13158 * old state now. */
61333b60
ML		 13159 if (any_ms)
13160 modeset_update_crtc_power_domains(state);
47fab737 13161
a6778b3c 13162 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13163 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13164 if (needs_modeset(crtc->state) && crtc->state->active) {
13165 update_scanline_offset(to_intel_crtc(crtc));
13166 dev_priv->display.crtc_enable(crtc);
13167 }
80715b2f 13168
a539205a 13169 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
80715b2f 13170 }
a6778b3c 13171
a6778b3c 13172 /* FIXME: add subpixel order */
83a57153 13173
d4afb8cc
ACO		 13174 drm_atomic_helper_cleanup_planes(dev, state);
13175
2bfb4627
ACO		 13176 drm_atomic_state_free(state);
13177
9eb45f22 13178 return 0;
f6e5b160
CW		 13179}
13180
568c634a 13181static int intel_set_mode_checked(struct drm_atomic_state *state)
f30da187 13182{
568c634a 13183 struct drm_device *dev = state->dev;
f30da187
DV		 13184 int ret;
13185
568c634a 13186 ret = __intel_set_mode(state);
f30da187 13187 if (ret == 0)
568c634a 13188 intel_modeset_check_state(dev);
f30da187
DV		 13189
13190 return ret;
13191}
13192
568c634a 13193static int intel_set_mode(struct drm_atomic_state *state)
7f27126e 13194{
568c634a 13195 int ret;
83a57153 13196
568c634a 13197 ret = intel_modeset_compute_config(state);
83a57153 13198 if (ret)
568c634a 13199 return ret;
7f27126e 13200
568c634a 13201 return intel_set_mode_checked(state);
7f27126e
JB		 13202}
13203
c0c36b94
CW		 13204void intel_crtc_restore_mode(struct drm_crtc *crtc)
13205{
83a57153
ACO		 13206 struct drm_device *dev = crtc->dev;
13207 struct drm_atomic_state *state;
13208 struct intel_encoder *encoder;
13209 struct intel_connector *connector;
13210 struct drm_connector_state *connector_state;
4be07317 13211 struct intel_crtc_state *crtc_state;
2bfb4627 13212 int ret;
83a57153
ACO		 13213
13214 state = drm_atomic_state_alloc(dev);
13215 if (!state) {
13216 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13217 crtc->base.id);
13218 return;
13219 }
13220
13221 state->acquire_ctx = dev->mode_config.acquire_ctx;
13222
13223 /* The force restore path in the HW readout code relies on the staged
13224 * config still keeping the user requested config while the actual
13225 * state has been overwritten by the configuration read from HW. We
13226 * need to copy the staged config to the atomic state, otherwise the
13227 * mode set will just reapply the state the HW is already in. */
13228 for_each_intel_encoder(dev, encoder) {
13229 if (&encoder->new_crtc->base != crtc)
13230 continue;
13231
13232 for_each_intel_connector(dev, connector) {
13233 if (connector->new_encoder != encoder)
13234 continue;
13235
13236 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13237 if (IS_ERR(connector_state)) {
13238 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13239 connector->base.base.id,
13240 connector->base.name,
13241 PTR_ERR(connector_state));
13242 continue;
13243 }
13244
13245 connector_state->crtc = crtc;
13246 connector_state->best_encoder = &encoder->base;
13247 }
13248 }
13249
4ed9fb37
ACO		 13250 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13251 if (IS_ERR(crtc_state)) {
13252 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13253 crtc->base.id, PTR_ERR(crtc_state));
13254 drm_atomic_state_free(state);
13255 return;
13256 }
4be07317 13257
4ed9fb37
ACO		 13258 crtc_state->base.active = crtc_state->base.enable =
13259 to_intel_crtc(crtc)->new_enabled;
8c7b5ccb 13260
4ed9fb37 13261 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317 13262
d3a40d1b
ACO		 13263 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13264 crtc->primary->fb, crtc->x, crtc->y);
13265
568c634a 13266 ret = intel_set_mode(state);
2bfb4627
ACO		 13267 if (ret)
13268 drm_atomic_state_free(state);
c0c36b94
CW		 13269}
13270
25c5b266
DV		 13271#undef for_each_intel_crtc_masked
13272
b7885264
ACO		 13273static bool intel_connector_in_mode_set(struct intel_connector *connector,
13274 struct drm_mode_set *set)
13275{
13276 int ro;
13277
13278 for (ro = 0; ro < set->num_connectors; ro++)
13279 if (set->connectors[ro] == &connector->base)
13280 return true;
13281
13282 return false;
13283}
13284
2e431051 13285static int
9a935856
DV		 13286intel_modeset_stage_output_state(struct drm_device *dev,
13287 struct drm_mode_set *set,
944b0c76 13288 struct drm_atomic_state *state)
50f56119 13289{
9a935856 13290 struct intel_connector *connector;
d5432a9d 13291 struct drm_connector *drm_connector;
944b0c76 13292 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13293 struct drm_crtc *crtc;
13294 struct drm_crtc_state *crtc_state;
13295 int i, ret;
50f56119 13296
9abdda74 13297 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13298 * of connectors. For paranoia, double-check this. */
13299 WARN_ON(!set->fb && (set->num_connectors != 0));
13300 WARN_ON(set->fb && (set->num_connectors == 0));
13301
3a3371ff 13302 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13303 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13304
d5432a9d
ACO		 13305 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13306 continue;
13307
13308 connector_state =
13309 drm_atomic_get_connector_state(state, &connector->base);
13310 if (IS_ERR(connector_state))
13311 return PTR_ERR(connector_state);
13312
b7885264
ACO		 13313 if (in_mode_set) {
13314 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13315 connector_state->best_encoder =
13316 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13317 }
13318
d5432a9d 13319 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13320 continue;
13321
9a935856
DV		 13322 /* If we disable the crtc, disable all its connectors. Also, if
13323 * the connector is on the changing crtc but not on the new
13324 * connector list, disable it. */
b7885264 13325 if (!set->fb || !in_mode_set) {
d5432a9d 13326 connector_state->best_encoder = NULL;
9a935856
DV		 13327
13328 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13329 connector->base.base.id,
c23cc417 13330 connector->base.name);
9a935856 13331 }
50f56119 13332 }
9a935856 13333 /* connector->new_encoder is now updated for all connectors. */
50f56119 13334
d5432a9d
ACO		 13335 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13336 connector = to_intel_connector(drm_connector);
13337
13338 if (!connector_state->best_encoder) {
13339 ret = drm_atomic_set_crtc_for_connector(connector_state,
13340 NULL);
13341 if (ret)
13342 return ret;
7668851f 13343
50f56119 13344 continue;
d5432a9d 13345 }
50f56119 13346
d5432a9d
ACO		 13347 if (intel_connector_in_mode_set(connector, set)) {
13348 struct drm_crtc *crtc = connector->base.state->crtc;
13349
13350 /* If this connector was in a previous crtc, add it
13351 * to the state. We might need to disable it. */
13352 if (crtc) {
13353 crtc_state =
13354 drm_atomic_get_crtc_state(state, crtc);
13355 if (IS_ERR(crtc_state))
13356 return PTR_ERR(crtc_state);
13357 }
13358
13359 ret = drm_atomic_set_crtc_for_connector(connector_state,
13360 set->crtc);
13361 if (ret)
13362 return ret;
13363 }
50f56119
DV		 13364
13365 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13366 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13367 connector_state->crtc)) {
5e2b584e 13368 return -EINVAL;
50f56119 13369 }
944b0c76 13370
9a935856
DV		 13371 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13372 connector->base.base.id,
c23cc417 13373 connector->base.name,
d5432a9d 13374 connector_state->crtc->base.id);
944b0c76 13375
d5432a9d
ACO		 13376 if (connector_state->best_encoder != &connector->encoder->base)
13377 connector->encoder =
13378 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13379 }
7668851f 13380
d5432a9d 13381 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13382 bool has_connectors;
13383
d5432a9d
ACO		 13384 ret = drm_atomic_add_affected_connectors(state, crtc);
13385 if (ret)
13386 return ret;
4be07317 13387
49d6fa21
ML		 13388 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13389 if (has_connectors != crtc_state->enable)
13390 crtc_state->enable =
13391 crtc_state->active = has_connectors;
7668851f
VS		 13392 }
13393
8c7b5ccb
ACO		 13394 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13395 set->fb, set->x, set->y);
13396 if (ret)
13397 return ret;
13398
13399 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13400 if (IS_ERR(crtc_state))
13401 return PTR_ERR(crtc_state);
13402
ce52299c
MR		 13403 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13404 if (ret)
13405 return ret;
8c7b5ccb
ACO		 13406
13407 if (set->num_connectors)
13408 crtc_state->active = true;
13409
2e431051
DV		 13410 return 0;
13411}
13412
13413static int intel_crtc_set_config(struct drm_mode_set *set)
13414{
13415 struct drm_device *dev;
83a57153 13416 struct drm_atomic_state *state = NULL;
2e431051 13417 int ret;
2e431051 13418
8d3e375e
DV		 13419 BUG_ON(!set);
13420 BUG_ON(!set->crtc);
13421 BUG_ON(!set->crtc->helper_private);
2e431051 13422
7e53f3a4
DV		 13423 /* Enforce sane interface api - has been abused by the fb helper. */
13424 BUG_ON(!set->mode && set->fb);
13425 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13426
2e431051
DV		 13427 if (set->fb) {
13428 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13429 set->crtc->base.id, set->fb->base.id,
13430 (int)set->num_connectors, set->x, set->y);
13431 } else {
13432 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13433 }
13434
13435 dev = set->crtc->dev;
13436
83a57153 13437 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13438 if (!state)
13439 return -ENOMEM;
83a57153
ACO		 13440
13441 state->acquire_ctx = dev->mode_config.acquire_ctx;
13442
462a425a 13443 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13444 if (ret)
7cbf41d6 13445 goto out;
2e431051 13446
568c634a
ACO		 13447 ret = intel_modeset_compute_config(state);
13448 if (ret)
7cbf41d6 13449 goto out;
50f52756 13450
1f9954d0
JB		 13451 intel_update_pipe_size(to_intel_crtc(set->crtc));
13452
568c634a 13453 ret = intel_set_mode_checked(state);
2d05eae1 13454 if (ret) {
bf67dfeb
DV		 13455 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13456 set->crtc->base.id, ret);
2d05eae1 13457 }
50f56119 13458
7cbf41d6 13459out:
2bfb4627
ACO		 13460 if (ret)
13461 drm_atomic_state_free(state);
50f56119
DV		 13462 return ret;
13463}
f6e5b160
CW		 13464
13465static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13466 .gamma_set = intel_crtc_gamma_set,
50f56119 13467 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13468 .destroy = intel_crtc_destroy,
13469 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13470 .atomic_duplicate_state = intel_crtc_duplicate_state,
13471 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13472};
13473
5358901f
DV		 13474static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13475 struct intel_shared_dpll *pll,
13476 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13477{
5358901f 13478 uint32_t val;
ee7b9f93 13479
f458ebbc 13480 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13481 return false;
13482
5358901f 13483 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13484 hw_state->dpll = val;
13485 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13486 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13487
13488 return val & DPLL_VCO_ENABLE;
13489}
13490
15bdd4cf
DV		 13491static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13492 struct intel_shared_dpll *pll)
13493{
3e369b76
ACO		 13494 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13495 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13496}
13497
e7b903d2
DV		 13498static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13499 struct intel_shared_dpll *pll)
13500{
e7b903d2 13501 /* PCH refclock must be enabled first */
89eff4be 13502 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13503
3e369b76 13504 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13505
13506 /* Wait for the clocks to stabilize. */
13507 POSTING_READ(PCH_DPLL(pll->id));
13508 udelay(150);
13509
13510 /* The pixel multiplier can only be updated once the
13511 * DPLL is enabled and the clocks are stable.
13512 *
13513 * So write it again.
13514 */
3e369b76 13515 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13516 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13517 udelay(200);
13518}
13519
13520static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13521 struct intel_shared_dpll *pll)
13522{
13523 struct drm_device *dev = dev_priv->dev;
13524 struct intel_crtc *crtc;
e7b903d2
DV		 13525
13526 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13527 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13528 if (intel_crtc_to_shared_dpll(crtc) == pll)
13529 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13530 }
13531
15bdd4cf
DV		 13532 I915_WRITE(PCH_DPLL(pll->id), 0);
13533 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13534 udelay(200);
13535}
13536
46edb027
DV		 13537static char *ibx_pch_dpll_names[] = {
13538 "PCH DPLL A",
13539 "PCH DPLL B",
13540};
13541
7c74ade1 13542static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13543{
e7b903d2 13544 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13545 int i;
13546
7c74ade1 13547 dev_priv->num_shared_dpll = 2;
ee7b9f93 13548
e72f9fbf 13549 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13550 dev_priv->shared_dplls[i].id = i;
13551 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13552 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13553 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13554 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13555 dev_priv->shared_dplls[i].get_hw_state =
13556 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13557 }
13558}
13559
7c74ade1
DV		 13560static void intel_shared_dpll_init(struct drm_device *dev)
13561{
e7b903d2 13562 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13563
b6283055
VS		 13564 intel_update_cdclk(dev);
13565
9cd86933
DV		 13566 if (HAS_DDI(dev))
13567 intel_ddi_pll_init(dev);
13568 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13569 ibx_pch_dpll_init(dev);
13570 else
13571 dev_priv->num_shared_dpll = 0;
13572
13573 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13574}
13575
6beb8c23
MR		 13576/**
13577 * intel_prepare_plane_fb - Prepare fb for usage on plane
13578 * @plane: drm plane to prepare for
13579 * @fb: framebuffer to prepare for presentation
13580 *
13581 * Prepares a framebuffer for usage on a display plane. Generally this
13582 * involves pinning the underlying object and updating the frontbuffer tracking
13583 * bits. Some older platforms need special physical address handling for
13584 * cursor planes.
13585 *
13586 * Returns 0 on success, negative error code on failure.
13587 */
13588int
13589intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13590 struct drm_framebuffer *fb,
13591 const struct drm_plane_state *new_state)
465c120c
MR		 13592{
13593 struct drm_device *dev = plane->dev;
6beb8c23 13594 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13595 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13596 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13597 int ret = 0;
465c120c 13598
ea2c67bb 13599 if (!obj)
465c120c
MR		 13600 return 0;
13601
6beb8c23 13602 mutex_lock(&dev->struct_mutex);
465c120c 13603
6beb8c23
MR		 13604 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13605 INTEL_INFO(dev)->cursor_needs_physical) {
13606 int align = IS_I830(dev) ? 16 * 1024 : 256;
13607 ret = i915_gem_object_attach_phys(obj, align);
13608 if (ret)
13609 DRM_DEBUG_KMS("failed to attach phys object\n");
13610 } else {
91af127f 13611 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13612 }
465c120c 13613
6beb8c23 13614 if (ret == 0)
a9ff8714 13615 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13616
4c34574f 13617 mutex_unlock(&dev->struct_mutex);
465c120c 13618
6beb8c23
MR		 13619 return ret;
13620}
13621
38f3ce3a
MR		 13622/**
13623 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13624 * @plane: drm plane to clean up for
13625 * @fb: old framebuffer that was on plane
13626 *
13627 * Cleans up a framebuffer that has just been removed from a plane.
13628 */
13629void
13630intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13631 struct drm_framebuffer *fb,
13632 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13633{
13634 struct drm_device *dev = plane->dev;
13635 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13636
13637 if (WARN_ON(!obj))
13638 return;
13639
13640 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13641 !INTEL_INFO(dev)->cursor_needs_physical) {
13642 mutex_lock(&dev->struct_mutex);
82bc3b2d 13643 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13644 mutex_unlock(&dev->struct_mutex);
13645 }
465c120c
MR		 13646}
13647
6156a456
CK		 13648int
13649skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13650{
13651 int max_scale;
13652 struct drm_device *dev;
13653 struct drm_i915_private *dev_priv;
13654 int crtc_clock, cdclk;
13655
13656 if (!intel_crtc || !crtc_state)
13657 return DRM_PLANE_HELPER_NO_SCALING;
13658
13659 dev = intel_crtc->base.dev;
13660 dev_priv = dev->dev_private;
13661 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13662 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13663
13664 if (!crtc_clock || !cdclk)
13665 return DRM_PLANE_HELPER_NO_SCALING;
13666
13667 /*
13668 * skl max scale is lower of:
13669 * close to 3 but not 3, -1 is for that purpose
13670 * or
13671 * cdclk/crtc_clock
13672 */
13673 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13674
13675 return max_scale;
13676}
13677
465c120c 13678static int
3c692a41 13679intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13680 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13681 struct intel_plane_state *state)
13682{
2b875c22
MR		 13683 struct drm_crtc *crtc = state->base.crtc;
13684 struct drm_framebuffer *fb = state->base.fb;
6156a456 13685 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13686 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13687 bool can_position = false;
465c120c 13688
061e4b8d
ML		 13689 /* use scaler when colorkey is not required */
13690 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13691 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13692 min_scale = 1;
13693 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13694 can_position = true;
6156a456 13695 }
d8106366 13696
061e4b8d
ML		 13697 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13698 &state->dst, &state->clip,
da20eabd
ML		 13699 min_scale, max_scale,
13700 can_position, true,
13701 &state->visible);
14af293f
GP		 13702}
13703
13704static void
13705intel_commit_primary_plane(struct drm_plane *plane,
13706 struct intel_plane_state *state)
13707{
2b875c22
MR		 13708 struct drm_crtc *crtc = state->base.crtc;
13709 struct drm_framebuffer *fb = state->base.fb;
13710 struct drm_device *dev = plane->dev;
14af293f 13711 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13712 struct intel_crtc *intel_crtc;
14af293f
GP		 13713 struct drm_rect *src = &state->src;
13714
ea2c67bb
MR		 13715 crtc = crtc ? crtc : plane->crtc;
13716 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13717
13718 plane->fb = fb;
9dc806fc
MR		 13719 crtc->x = src->x1 >> 16;
13720 crtc->y = src->y1 >> 16;
ccc759dc 13721
a539205a 13722 if (!crtc->state->active)
302d19ac 13723 return;
465c120c 13724
302d19ac
ML		 13725 if (state->visible)
13726 /* FIXME: kill this fastboot hack */
13727 intel_update_pipe_size(intel_crtc);
13728
13729 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13730}
13731
a8ad0d8e
ML		 13732static void
13733intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13734 struct drm_crtc *crtc)
a8ad0d8e
ML		 13735{
13736 struct drm_device *dev = plane->dev;
13737 struct drm_i915_private *dev_priv = dev->dev_private;
13738
a8ad0d8e
ML		 13739 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13740}
13741
32b7eeec 13742static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13743{
32b7eeec 13744 struct drm_device *dev = crtc->dev;
140fd38d 13745 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13747
a539205a
ML		 13748 if (!needs_modeset(crtc->state))
13749 intel_pre_plane_update(intel_crtc);
3c692a41 13750
f015c551 13751 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13752 intel_update_watermarks(crtc);
3c692a41 13753
32b7eeec 13754 intel_runtime_pm_get(dev_priv);
3c692a41 13755
c34c9ee4 13756 /* Perform vblank evasion around commit operation */
a539205a 13757 if (crtc->state->active)
c34c9ee4
MR		 13758 intel_crtc->atomic.evade =
13759 intel_pipe_update_start(intel_crtc,
13760 &intel_crtc->atomic.start_vbl_count);
0583236e
ML		 13761
13762 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13763 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13764}
13765
13766static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13767{
13768 struct drm_device *dev = crtc->dev;
13769 struct drm_i915_private *dev_priv = dev->dev_private;
13770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13771
c34c9ee4
MR		 13772 if (intel_crtc->atomic.evade)
13773 intel_pipe_update_end(intel_crtc,
13774 intel_crtc->atomic.start_vbl_count);
3c692a41 13775
140fd38d 13776 intel_runtime_pm_put(dev_priv);
3c692a41 13777
ac21b225 13778 intel_post_plane_update(intel_crtc);
3c692a41
GP		 13779}
13780
cf4c7c12 13781/**
4a3b8769
MR		 13782 * intel_plane_destroy - destroy a plane
13783 * @plane: plane to destroy
cf4c7c12 13784 *
4a3b8769
MR		 13785 * Common destruction function for all types of planes (primary, cursor,
13786 * sprite).
cf4c7c12 13787 */
4a3b8769 13788void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13789{
13790 struct intel_plane *intel_plane = to_intel_plane(plane);
13791 drm_plane_cleanup(plane);
13792 kfree(intel_plane);
13793}
13794
65a3fea0 13795const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13796 .update_plane = drm_atomic_helper_update_plane,
13797 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13798 .destroy = intel_plane_destroy,
c196e1d6 13799 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13800 .atomic_get_property = intel_plane_atomic_get_property,
13801 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13802 .atomic_duplicate_state = intel_plane_duplicate_state,
13803 .atomic_destroy_state = intel_plane_destroy_state,
13804
465c120c
MR		 13805};
13806
13807static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13808 int pipe)
13809{
13810 struct intel_plane *primary;
8e7d688b 13811 struct intel_plane_state *state;
465c120c
MR		 13812 const uint32_t *intel_primary_formats;
13813 int num_formats;
13814
13815 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13816 if (primary == NULL)
13817 return NULL;
13818
8e7d688b
MR		 13819 state = intel_create_plane_state(&primary->base);
13820 if (!state) {
ea2c67bb
MR		 13821 kfree(primary);
13822 return NULL;
13823 }
8e7d688b 13824 primary->base.state = &state->base;
ea2c67bb 13825
465c120c
MR		 13826 primary->can_scale = false;
13827 primary->max_downscale = 1;
6156a456
CK		 13828 if (INTEL_INFO(dev)->gen >= 9) {
13829 primary->can_scale = true;
af99ceda 13830 state->scaler_id = -1;
6156a456 13831 }
465c120c
MR		 13832 primary->pipe = pipe;
13833 primary->plane = pipe;
a9ff8714 13834 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13835 primary->check_plane = intel_check_primary_plane;
13836 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13837 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13838 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13839 primary->plane = !pipe;
13840
6c0fd451
DL		 13841 if (INTEL_INFO(dev)->gen >= 9) {
13842 intel_primary_formats = skl_primary_formats;
13843 num_formats = ARRAY_SIZE(skl_primary_formats);
13844 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13845 intel_primary_formats = i965_primary_formats;
13846 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13847 } else {
13848 intel_primary_formats = i8xx_primary_formats;
13849 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13850 }
13851
13852 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13853 &intel_plane_funcs,
465c120c
MR		 13854 intel_primary_formats, num_formats,
13855 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13856
3b7a5119
SJ		 13857 if (INTEL_INFO(dev)->gen >= 4)
13858 intel_create_rotation_property(dev, primary);
48404c1e 13859
ea2c67bb
MR		 13860 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13861
465c120c
MR		 13862 return &primary->base;
13863}
13864
3b7a5119
SJ		 13865void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13866{
13867 if (!dev->mode_config.rotation_property) {
13868 unsigned long flags = BIT(DRM_ROTATE_0) |
13869 BIT(DRM_ROTATE_180);
13870
13871 if (INTEL_INFO(dev)->gen >= 9)
13872 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13873
13874 dev->mode_config.rotation_property =
13875 drm_mode_create_rotation_property(dev, flags);
13876 }
13877 if (dev->mode_config.rotation_property)
13878 drm_object_attach_property(&plane->base.base,
13879 dev->mode_config.rotation_property,
13880 plane->base.state->rotation);
13881}
13882
3d7d6510 13883static int
852e787c 13884intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13885 struct intel_crtc_state *crtc_state,
852e787c 13886 struct intel_plane_state *state)
3d7d6510 13887{
061e4b8d 13888 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13889 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13890 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13891 unsigned stride;
13892 int ret;
3d7d6510 13893
061e4b8d
ML		 13894 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13895 &state->dst, &state->clip,
3d7d6510
MR		 13896 DRM_PLANE_HELPER_NO_SCALING,
13897 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13898 true, true, &state->visible);
757f9a3e
GP		 13899 if (ret)
13900 return ret;
13901
757f9a3e
GP		 13902 /* if we want to turn off the cursor ignore width and height */
13903 if (!obj)
da20eabd 13904 return 0;
757f9a3e 13905
757f9a3e 13906 /* Check for which cursor types we support */
061e4b8d 13907 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13908 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13909 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13910 return -EINVAL;
13911 }
13912
ea2c67bb
MR		 13913 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13914 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13915 DRM_DEBUG_KMS("buffer is too small\n");
13916 return -ENOMEM;
13917 }
13918
3a656b54 13919 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13920 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13921 return -EINVAL;
32b7eeec
MR		 13922 }
13923
da20eabd 13924 return 0;
852e787c 13925}
3d7d6510 13926
a8ad0d8e
ML		 13927static void
13928intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13929 struct drm_crtc *crtc)
a8ad0d8e 13930{
a8ad0d8e
ML		 13931 intel_crtc_update_cursor(crtc, false);
13932}
13933
f4a2cf29 13934static void
852e787c
GP		 13935intel_commit_cursor_plane(struct drm_plane *plane,
13936 struct intel_plane_state *state)
13937{
2b875c22 13938 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13939 struct drm_device *dev = plane->dev;
13940 struct intel_crtc *intel_crtc;
2b875c22 13941 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13942 uint32_t addr;
852e787c 13943
ea2c67bb
MR		 13944 crtc = crtc ? crtc : plane->crtc;
13945 intel_crtc = to_intel_crtc(crtc);
13946
2b875c22 13947 plane->fb = state->base.fb;
ea2c67bb
MR		 13948 crtc->cursor_x = state->base.crtc_x;
13949 crtc->cursor_y = state->base.crtc_y;
13950
a912f12f
GP		 13951 if (intel_crtc->cursor_bo == obj)
13952 goto update;
4ed91096 13953
f4a2cf29 13954 if (!obj)
a912f12f 13955 addr = 0;
f4a2cf29 13956 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13957 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13958 else
a912f12f 13959 addr = obj->phys_handle->busaddr;
852e787c 13960
a912f12f
GP		 13961 intel_crtc->cursor_addr = addr;
13962 intel_crtc->cursor_bo = obj;
852e787c 13963
302d19ac 13964update:
a539205a 13965 if (crtc->state->active)
a912f12f 13966 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13967}
13968
3d7d6510
MR		 13969static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13970 int pipe)
13971{
13972 struct intel_plane *cursor;
8e7d688b 13973 struct intel_plane_state *state;
3d7d6510
MR		 13974
13975 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13976 if (cursor == NULL)
13977 return NULL;
13978
8e7d688b
MR		 13979 state = intel_create_plane_state(&cursor->base);
13980 if (!state) {
ea2c67bb
MR		 13981 kfree(cursor);
13982 return NULL;
13983 }
8e7d688b 13984 cursor->base.state = &state->base;
ea2c67bb 13985
3d7d6510
MR		 13986 cursor->can_scale = false;
13987 cursor->max_downscale = 1;
13988 cursor->pipe = pipe;
13989 cursor->plane = pipe;
a9ff8714 13990 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13991 cursor->check_plane = intel_check_cursor_plane;
13992 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13993 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13994
13995 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13996 &intel_plane_funcs,
3d7d6510
MR		 13997 intel_cursor_formats,
13998 ARRAY_SIZE(intel_cursor_formats),
13999 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14000
14001 if (INTEL_INFO(dev)->gen >= 4) {
14002 if (!dev->mode_config.rotation_property)
14003 dev->mode_config.rotation_property =
14004 drm_mode_create_rotation_property(dev,
14005 BIT(DRM_ROTATE_0) |
14006 BIT(DRM_ROTATE_180));
14007 if (dev->mode_config.rotation_property)
14008 drm_object_attach_property(&cursor->base.base,
14009 dev->mode_config.rotation_property,
8e7d688b 14010 state->base.rotation);
4398ad45
VS		 14011 }
14012
af99ceda
CK		 14013 if (INTEL_INFO(dev)->gen >=9)
14014 state->scaler_id = -1;
14015
ea2c67bb
MR		 14016 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14017
3d7d6510
MR		 14018 return &cursor->base;
14019}
14020
549e2bfb
CK		 14021static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14022 struct intel_crtc_state *crtc_state)
14023{
14024 int i;
14025 struct intel_scaler *intel_scaler;
14026 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14027
14028 for (i = 0; i < intel_crtc->num_scalers; i++) {
14029 intel_scaler = &scaler_state->scalers[i];
14030 intel_scaler->in_use = 0;
549e2bfb
CK		 14031 intel_scaler->mode = PS_SCALER_MODE_DYN;
14032 }
14033
14034 scaler_state->scaler_id = -1;
14035}
14036
b358d0a6 14037static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14038{
fbee40df 14039 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14040 struct intel_crtc *intel_crtc;
f5de6e07 14041 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14042 struct drm_plane *primary = NULL;
14043 struct drm_plane *cursor = NULL;
465c120c 14044 int i, ret;
79e53945 14045
955382f3 14046 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14047 if (intel_crtc == NULL)
14048 return;
14049
f5de6e07
ACO		 14050 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14051 if (!crtc_state)
14052 goto fail;
550acefd
ACO		 14053 intel_crtc->config = crtc_state;
14054 intel_crtc->base.state = &crtc_state->base;
07878248 14055 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14056
549e2bfb
CK		 14057 /* initialize shared scalers */
14058 if (INTEL_INFO(dev)->gen >= 9) {
14059 if (pipe == PIPE_C)
14060 intel_crtc->num_scalers = 1;
14061 else
14062 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14063
14064 skl_init_scalers(dev, intel_crtc, crtc_state);
14065 }
14066
465c120c 14067 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14068 if (!primary)
14069 goto fail;
14070
14071 cursor = intel_cursor_plane_create(dev, pipe);
14072 if (!cursor)
14073 goto fail;
14074
465c120c 14075 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14076 cursor, &intel_crtc_funcs);
14077 if (ret)
14078 goto fail;
79e53945
JB		 14079
14080 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14081 for (i = 0; i < 256; i++) {
14082 intel_crtc->lut_r[i] = i;
14083 intel_crtc->lut_g[i] = i;
14084 intel_crtc->lut_b[i] = i;
14085 }
14086
1f1c2e24
VS		 14087 /*
14088 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14089 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14090 */
80824003
JB		 14091 intel_crtc->pipe = pipe;
14092 intel_crtc->plane = pipe;
3a77c4c4 14093 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14094 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14095 intel_crtc->plane = !pipe;
80824003
JB		 14096 }
14097
4b0e333e
CW		 14098 intel_crtc->cursor_base = ~0;
14099 intel_crtc->cursor_cntl = ~0;
dc41c154 14100 intel_crtc->cursor_size = ~0;
8d7849db 14101
852eb00d
VS		 14102 intel_crtc->wm.cxsr_allowed = true;
14103
22fd0fab
JB		 14104 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14105 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14106 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14107 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14108
79e53945 14109 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14110
14111 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14112 return;
14113
14114fail:
14115 if (primary)
14116 drm_plane_cleanup(primary);
14117 if (cursor)
14118 drm_plane_cleanup(cursor);
f5de6e07 14119 kfree(crtc_state);
3d7d6510 14120 kfree(intel_crtc);
79e53945
JB		 14121}
14122
752aa88a
JB		 14123enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14124{
14125 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14126 struct drm_device *dev = connector->base.dev;
752aa88a 14127
51fd371b 14128 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14129
d3babd3f 14130 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14131 return INVALID_PIPE;
14132
14133 return to_intel_crtc(encoder->crtc)->pipe;
14134}
14135
08d7b3d1 14136int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14137 struct drm_file *file)
08d7b3d1 14138{
08d7b3d1 14139 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14140 struct drm_crtc *drmmode_crtc;
c05422d5 14141 struct intel_crtc *crtc;
08d7b3d1 14142
7707e653 14143 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14144
7707e653 14145 if (!drmmode_crtc) {
08d7b3d1 14146 DRM_ERROR("no such CRTC id\n");
3f2c2057 14147 return -ENOENT;
08d7b3d1
CW		 14148 }
14149
7707e653 14150 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14151 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14152
c05422d5 14153 return 0;
08d7b3d1
CW		 14154}
14155
66a9278e 14156static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14157{
66a9278e
DV		 14158 struct drm_device *dev = encoder->base.dev;
14159 struct intel_encoder *source_encoder;
79e53945 14160 int index_mask = 0;
79e53945
JB		 14161 int entry = 0;
14162
b2784e15 14163 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14164 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14165 index_mask |= (1 << entry);
14166
79e53945
JB		 14167 entry++;
14168 }
4ef69c7a 14169
79e53945
JB		 14170 return index_mask;
14171}
14172
4d302442
CW		 14173static bool has_edp_a(struct drm_device *dev)
14174{
14175 struct drm_i915_private *dev_priv = dev->dev_private;
14176
14177 if (!IS_MOBILE(dev))
14178 return false;
14179
14180 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14181 return false;
14182
e3589908 14183 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14184 return false;
14185
14186 return true;
14187}
14188
84b4e042
JB		 14189static bool intel_crt_present(struct drm_device *dev)
14190{
14191 struct drm_i915_private *dev_priv = dev->dev_private;
14192
884497ed
DL		 14193 if (INTEL_INFO(dev)->gen >= 9)
14194 return false;
14195
cf404ce4 14196 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14197 return false;
14198
14199 if (IS_CHERRYVIEW(dev))
14200 return false;
14201
14202 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14203 return false;
14204
14205 return true;
14206}
14207
79e53945
JB		 14208static void intel_setup_outputs(struct drm_device *dev)
14209{
725e30ad 14210 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14211 struct intel_encoder *encoder;
cb0953d7 14212 bool dpd_is_edp = false;
79e53945 14213
c9093354 14214 intel_lvds_init(dev);
79e53945 14215
84b4e042 14216 if (intel_crt_present(dev))
79935fca 14217 intel_crt_init(dev);
cb0953d7 14218
c776eb2e
VK		 14219 if (IS_BROXTON(dev)) {
14220 /*
14221 * FIXME: Broxton doesn't support port detection via the
14222 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14223 * detect the ports.
14224 */
14225 intel_ddi_init(dev, PORT_A);
14226 intel_ddi_init(dev, PORT_B);
14227 intel_ddi_init(dev, PORT_C);
14228 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14229 int found;
14230
de31facd
JB		 14231 /*
14232 * Haswell uses DDI functions to detect digital outputs.
14233 * On SKL pre-D0 the strap isn't connected, so we assume
14234 * it's there.
14235 */
0e72a5b5 14236 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14237 /* WaIgnoreDDIAStrap: skl */
14238 if (found ||
14239 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14240 intel_ddi_init(dev, PORT_A);
14241
14242 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14243 * register */
14244 found = I915_READ(SFUSE_STRAP);
14245
14246 if (found & SFUSE_STRAP_DDIB_DETECTED)
14247 intel_ddi_init(dev, PORT_B);
14248 if (found & SFUSE_STRAP_DDIC_DETECTED)
14249 intel_ddi_init(dev, PORT_C);
14250 if (found & SFUSE_STRAP_DDID_DETECTED)
14251 intel_ddi_init(dev, PORT_D);
14252 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14253 int found;
5d8a7752 14254 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14255
14256 if (has_edp_a(dev))
14257 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14258
dc0fa718 14259 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14260 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14261 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14262 if (!found)
e2debe91 14263 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14264 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14265 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14266 }
14267
dc0fa718 14268 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14269 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14270
dc0fa718 14271 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14272 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14273
5eb08b69 14274 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14275 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14276
270b3042 14277 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14278 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14279 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14280 /*
14281 * The DP_DETECTED bit is the latched state of the DDC
14282 * SDA pin at boot. However since eDP doesn't require DDC
14283 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14284 * eDP ports may have been muxed to an alternate function.
14285 * Thus we can't rely on the DP_DETECTED bit alone to detect
14286 * eDP ports. Consult the VBT as well as DP_DETECTED to
14287 * detect eDP ports.
14288 */
d2182a66
VS		 14289 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14290 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14291 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14292 PORT_B);
e17ac6db
VS		 14293 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14294 intel_dp_is_edp(dev, PORT_B))
14295 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14296
d2182a66
VS		 14297 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14298 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14299 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14300 PORT_C);
e17ac6db
VS		 14301 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14302 intel_dp_is_edp(dev, PORT_C))
14303 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14304
9418c1f1 14305 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14306 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14307 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14308 PORT_D);
e17ac6db
VS		 14309 /* eDP not supported on port D, so don't check VBT */
14310 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14311 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14312 }
14313
3cfca973 14314 intel_dsi_init(dev);
103a196f 14315 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14316 bool found = false;
7d57382e 14317
e2debe91 14318 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14319 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14320 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14321 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14322 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14323 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14324 }
27185ae1 14325
e7281eab 14326 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14327 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14328 }
13520b05
KH		 14329
14330 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14331
e2debe91 14332 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14333 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14334 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14335 }
27185ae1 14336
e2debe91 14337 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14338
b01f2c3a
JB		 14339 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14340 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14341 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14342 }
e7281eab 14343 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14344 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14345 }
27185ae1 14346
b01f2c3a 14347 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14348 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14349 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14350 } else if (IS_GEN2(dev))
79e53945
JB		 14351 intel_dvo_init(dev);
14352
103a196f 14353 if (SUPPORTS_TV(dev))
79e53945
JB		 14354 intel_tv_init(dev);
14355
0bc12bcb 14356 intel_psr_init(dev);
7c8f8a70 14357
b2784e15 14358 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14359 encoder->base.possible_crtcs = encoder->crtc_mask;
14360 encoder->base.possible_clones =
66a9278e 14361 intel_encoder_clones(encoder);
79e53945 14362 }
47356eb6 14363
dde86e2d 14364 intel_init_pch_refclk(dev);
270b3042
DV		 14365
14366 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14367}
14368
14369static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14370{
60a5ca01 14371 struct drm_device *dev = fb->dev;
79e53945 14372 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14373
ef2d633e 14374 drm_framebuffer_cleanup(fb);
60a5ca01 14375 mutex_lock(&dev->struct_mutex);
ef2d633e 14376 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14377 drm_gem_object_unreference(&intel_fb->obj->base);
14378 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14379 kfree(intel_fb);
14380}
14381
14382static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14383 struct drm_file *file,
79e53945
JB		 14384 unsigned int *handle)
14385{
14386 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14387 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14388
05394f39 14389 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14390}
14391
14392static const struct drm_framebuffer_funcs intel_fb_funcs = {
14393 .destroy = intel_user_framebuffer_destroy,
14394 .create_handle = intel_user_framebuffer_create_handle,
14395};
14396
b321803d
DL		 14397static
14398u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14399 uint32_t pixel_format)
14400{
14401 u32 gen = INTEL_INFO(dev)->gen;
14402
14403 if (gen >= 9) {
14404 /* "The stride in bytes must not exceed the of the size of 8K
14405 * pixels and 32K bytes."
14406 */
14407 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14408 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14409 return 32*1024;
14410 } else if (gen >= 4) {
14411 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14412 return 16*1024;
14413 else
14414 return 32*1024;
14415 } else if (gen >= 3) {
14416 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14417 return 8*1024;
14418 else
14419 return 16*1024;
14420 } else {
14421 /* XXX DSPC is limited to 4k tiled */
14422 return 8*1024;
14423 }
14424}
14425
b5ea642a
DV		 14426static int intel_framebuffer_init(struct drm_device *dev,
14427 struct intel_framebuffer *intel_fb,
14428 struct drm_mode_fb_cmd2 *mode_cmd,
14429 struct drm_i915_gem_object *obj)
79e53945 14430{
6761dd31 14431 unsigned int aligned_height;
79e53945 14432 int ret;
b321803d 14433 u32 pitch_limit, stride_alignment;
79e53945 14434
dd4916c5
DV		 14435 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14436
2a80eada
DV		 14437 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14438 /* Enforce that fb modifier and tiling mode match, but only for
14439 * X-tiled. This is needed for FBC. */
14440 if (!!(obj->tiling_mode == I915_TILING_X) !=
14441 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14442 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14443 return -EINVAL;
14444 }
14445 } else {
14446 if (obj->tiling_mode == I915_TILING_X)
14447 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14448 else if (obj->tiling_mode == I915_TILING_Y) {
14449 DRM_DEBUG("No Y tiling for legacy addfb\n");
14450 return -EINVAL;
14451 }
14452 }
14453
9a8f0a12
TU		 14454 /* Passed in modifier sanity checking. */
14455 switch (mode_cmd->modifier[0]) {
14456 case I915_FORMAT_MOD_Y_TILED:
14457 case I915_FORMAT_MOD_Yf_TILED:
14458 if (INTEL_INFO(dev)->gen < 9) {
14459 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14460 mode_cmd->modifier[0]);
14461 return -EINVAL;
14462 }
14463 case DRM_FORMAT_MOD_NONE:
14464 case I915_FORMAT_MOD_X_TILED:
14465 break;
14466 default:
c0f40428
JB		 14467 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14468 mode_cmd->modifier[0]);
57cd6508 14469 return -EINVAL;
c16ed4be 14470 }
57cd6508 14471
b321803d
DL		 14472 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14473 mode_cmd->pixel_format);
14474 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14475 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14476 mode_cmd->pitches[0], stride_alignment);
57cd6508 14477 return -EINVAL;
c16ed4be 14478 }
57cd6508 14479
b321803d
DL		 14480 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14481 mode_cmd->pixel_format);
a35cdaa0 14482 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14483 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14484 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14485 "tiled" : "linear",
a35cdaa0 14486 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14487 return -EINVAL;
c16ed4be 14488 }
5d7bd705 14489
2a80eada 14490 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14491 mode_cmd->pitches[0] != obj->stride) {
14492 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14493 mode_cmd->pitches[0], obj->stride);
5d7bd705 14494 return -EINVAL;
c16ed4be 14495 }
5d7bd705 14496
57779d06 14497 /* Reject formats not supported by any plane early. */
308e5bcb 14498 switch (mode_cmd->pixel_format) {
57779d06 14499 case DRM_FORMAT_C8:
04b3924d
VS		 14500 case DRM_FORMAT_RGB565:
14501 case DRM_FORMAT_XRGB8888:
14502 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14503 break;
14504 case DRM_FORMAT_XRGB1555:
c16ed4be 14505 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14506 DRM_DEBUG("unsupported pixel format: %s\n",
14507 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14508 return -EINVAL;
c16ed4be 14509 }
57779d06 14510 break;
57779d06 14511 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14512 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14513 DRM_DEBUG("unsupported pixel format: %s\n",
14514 drm_get_format_name(mode_cmd->pixel_format));
14515 return -EINVAL;
14516 }
14517 break;
14518 case DRM_FORMAT_XBGR8888:
04b3924d 14519 case DRM_FORMAT_XRGB2101010:
57779d06 14520 case DRM_FORMAT_XBGR2101010:
c16ed4be 14521 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14522 DRM_DEBUG("unsupported pixel format: %s\n",
14523 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14524 return -EINVAL;
c16ed4be 14525 }
b5626747 14526 break;
7531208b
DL		 14527 case DRM_FORMAT_ABGR2101010:
14528 if (!IS_VALLEYVIEW(dev)) {
14529 DRM_DEBUG("unsupported pixel format: %s\n",
14530 drm_get_format_name(mode_cmd->pixel_format));
14531 return -EINVAL;
14532 }
14533 break;
04b3924d
VS		 14534 case DRM_FORMAT_YUYV:
14535 case DRM_FORMAT_UYVY:
14536 case DRM_FORMAT_YVYU:
14537 case DRM_FORMAT_VYUY:
c16ed4be 14538 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14539 DRM_DEBUG("unsupported pixel format: %s\n",
14540 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14541 return -EINVAL;
c16ed4be 14542 }
57cd6508
CW		 14543 break;
14544 default:
4ee62c76
VS		 14545 DRM_DEBUG("unsupported pixel format: %s\n",
14546 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14547 return -EINVAL;
14548 }
14549
90f9a336
VS		 14550 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14551 if (mode_cmd->offsets[0] != 0)
14552 return -EINVAL;
14553
ec2c981e 14554 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14555 mode_cmd->pixel_format,
14556 mode_cmd->modifier[0]);
53155c0a
DV		 14557 /* FIXME drm helper for size checks (especially planar formats)? */
14558 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14559 return -EINVAL;
14560
c7d73f6a
DV		 14561 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14562 intel_fb->obj = obj;
80075d49 14563 intel_fb->obj->framebuffer_references++;
c7d73f6a 14564
79e53945
JB		 14565 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14566 if (ret) {
14567 DRM_ERROR("framebuffer init failed %d\n", ret);
14568 return ret;
14569 }
14570
79e53945
JB		 14571 return 0;
14572}
14573
79e53945
JB		 14574static struct drm_framebuffer *
14575intel_user_framebuffer_create(struct drm_device *dev,
14576 struct drm_file *filp,
308e5bcb 14577 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14578{
05394f39 14579 struct drm_i915_gem_object *obj;
79e53945 14580
308e5bcb
JB		 14581 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14582 mode_cmd->handles[0]));
c8725226 14583 if (&obj->base == NULL)
cce13ff7 14584 return ERR_PTR(-ENOENT);
79e53945 14585
d2dff872 14586 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14587}
14588
4520f53a 14589#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14590static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14591{
14592}
14593#endif
14594
79e53945 14595static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14596 .fb_create = intel_user_framebuffer_create,
0632fef6 14597 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14598 .atomic_check = intel_atomic_check,
14599 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14600 .atomic_state_alloc = intel_atomic_state_alloc,
14601 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14602};
14603
e70236a8
JB		 14604/* Set up chip specific display functions */
14605static void intel_init_display(struct drm_device *dev)
14606{
14607 struct drm_i915_private *dev_priv = dev->dev_private;
14608
ee9300bb
DV		 14609 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14610 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14611 else if (IS_CHERRYVIEW(dev))
14612 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14613 else if (IS_VALLEYVIEW(dev))
14614 dev_priv->display.find_dpll = vlv_find_best_dpll;
14615 else if (IS_PINEVIEW(dev))
14616 dev_priv->display.find_dpll = pnv_find_best_dpll;
14617 else
14618 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14619
bc8d7dff
DL		 14620 if (INTEL_INFO(dev)->gen >= 9) {
14621 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14622 dev_priv->display.get_initial_plane_config =
14623 skylake_get_initial_plane_config;
bc8d7dff
DL		 14624 dev_priv->display.crtc_compute_clock =
14625 haswell_crtc_compute_clock;
14626 dev_priv->display.crtc_enable = haswell_crtc_enable;
14627 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14628 dev_priv->display.update_primary_plane =
14629 skylake_update_primary_plane;
14630 } else if (HAS_DDI(dev)) {
0e8ffe1b 14631 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14632 dev_priv->display.get_initial_plane_config =
14633 ironlake_get_initial_plane_config;
797d0259
ACO		 14634 dev_priv->display.crtc_compute_clock =
14635 haswell_crtc_compute_clock;
4f771f10
PZ		 14636 dev_priv->display.crtc_enable = haswell_crtc_enable;
14637 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14638 dev_priv->display.update_primary_plane =
14639 ironlake_update_primary_plane;
09b4ddf9 14640 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14641 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14642 dev_priv->display.get_initial_plane_config =
14643 ironlake_get_initial_plane_config;
3fb37703
ACO		 14644 dev_priv->display.crtc_compute_clock =
14645 ironlake_crtc_compute_clock;
76e5a89c
DV		 14646 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14647 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14648 dev_priv->display.update_primary_plane =
14649 ironlake_update_primary_plane;
89b667f8
JB		 14650 } else if (IS_VALLEYVIEW(dev)) {
14651 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14652 dev_priv->display.get_initial_plane_config =
14653 i9xx_get_initial_plane_config;
d6dfee7a 14654 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14655 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14656 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14657 dev_priv->display.update_primary_plane =
14658 i9xx_update_primary_plane;
f564048e 14659 } else {
0e8ffe1b 14660 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14661 dev_priv->display.get_initial_plane_config =
14662 i9xx_get_initial_plane_config;
d6dfee7a 14663 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14664 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14665 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14666 dev_priv->display.update_primary_plane =
14667 i9xx_update_primary_plane;
f564048e 14668 }
e70236a8 14669
e70236a8 14670 /* Returns the core display clock speed */
1652d19e
VS		 14671 if (IS_SKYLAKE(dev))
14672 dev_priv->display.get_display_clock_speed =
14673 skylake_get_display_clock_speed;
acd3f3d3
BP		 14674 else if (IS_BROXTON(dev))
14675 dev_priv->display.get_display_clock_speed =
14676 broxton_get_display_clock_speed;
1652d19e
VS		 14677 else if (IS_BROADWELL(dev))
14678 dev_priv->display.get_display_clock_speed =
14679 broadwell_get_display_clock_speed;
14680 else if (IS_HASWELL(dev))
14681 dev_priv->display.get_display_clock_speed =
14682 haswell_get_display_clock_speed;
14683 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14684 dev_priv->display.get_display_clock_speed =
14685 valleyview_get_display_clock_speed;
b37a6434
VS		 14686 else if (IS_GEN5(dev))
14687 dev_priv->display.get_display_clock_speed =
14688 ilk_get_display_clock_speed;
a7c66cd8 14689 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14690 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14691 dev_priv->display.get_display_clock_speed =
14692 i945_get_display_clock_speed;
34edce2f
VS		 14693 else if (IS_GM45(dev))
14694 dev_priv->display.get_display_clock_speed =
14695 gm45_get_display_clock_speed;
14696 else if (IS_CRESTLINE(dev))
14697 dev_priv->display.get_display_clock_speed =
14698 i965gm_get_display_clock_speed;
14699 else if (IS_PINEVIEW(dev))
14700 dev_priv->display.get_display_clock_speed =
14701 pnv_get_display_clock_speed;
14702 else if (IS_G33(dev) || IS_G4X(dev))
14703 dev_priv->display.get_display_clock_speed =
14704 g33_get_display_clock_speed;
e70236a8
JB		 14705 else if (IS_I915G(dev))
14706 dev_priv->display.get_display_clock_speed =
14707 i915_get_display_clock_speed;
257a7ffc 14708 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14709 dev_priv->display.get_display_clock_speed =
14710 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14711 else if (IS_PINEVIEW(dev))
14712 dev_priv->display.get_display_clock_speed =
14713 pnv_get_display_clock_speed;
e70236a8
JB		 14714 else if (IS_I915GM(dev))
14715 dev_priv->display.get_display_clock_speed =
14716 i915gm_get_display_clock_speed;
14717 else if (IS_I865G(dev))
14718 dev_priv->display.get_display_clock_speed =
14719 i865_get_display_clock_speed;
f0f8a9ce 14720 else if (IS_I85X(dev))
e70236a8 14721 dev_priv->display.get_display_clock_speed =
1b1d2716 14722 i85x_get_display_clock_speed;
623e01e5
VS		 14723 else { /* 830 */
14724 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14725 dev_priv->display.get_display_clock_speed =
14726 i830_get_display_clock_speed;
623e01e5 14727 }
e70236a8 14728
7c10a2b5 14729 if (IS_GEN5(dev)) {
3bb11b53 14730 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14731 } else if (IS_GEN6(dev)) {
14732 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14733 } else if (IS_IVYBRIDGE(dev)) {
14734 /* FIXME: detect B0+ stepping and use auto training */
14735 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14736 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14737 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14738 if (IS_BROADWELL(dev)) {
14739 dev_priv->display.modeset_commit_cdclk =
14740 broadwell_modeset_commit_cdclk;
14741 dev_priv->display.modeset_calc_cdclk =
14742 broadwell_modeset_calc_cdclk;
14743 }
30a970c6 14744 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14745 dev_priv->display.modeset_commit_cdclk =
14746 valleyview_modeset_commit_cdclk;
14747 dev_priv->display.modeset_calc_cdclk =
14748 valleyview_modeset_calc_cdclk;
f8437dd1 14749 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14750 dev_priv->display.modeset_commit_cdclk =
14751 broxton_modeset_commit_cdclk;
14752 dev_priv->display.modeset_calc_cdclk =
14753 broxton_modeset_calc_cdclk;
e70236a8 14754 }
8c9f3aaf 14755
8c9f3aaf
JB		 14756 switch (INTEL_INFO(dev)->gen) {
14757 case 2:
14758 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14759 break;
14760
14761 case 3:
14762 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14763 break;
14764
14765 case 4:
14766 case 5:
14767 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14768 break;
14769
14770 case 6:
14771 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14772 break;
7c9017e5 14773 case 7:
4e0bbc31 14774 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14775 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14776 break;
830c81db 14777 case 9:
ba343e02
TU		 14778 /* Drop through - unsupported since execlist only. */
14779 default:
14780 /* Default just returns -ENODEV to indicate unsupported */
14781 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14782 }
7bd688cd
JN		 14783
14784 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14785
14786 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14787}
14788
b690e96c
JB		 14789/*
14790 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14791 * resume, or other times. This quirk makes sure that's the case for
14792 * affected systems.
14793 */
0206e353 14794static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14795{
14796 struct drm_i915_private *dev_priv = dev->dev_private;
14797
14798 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14799 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14800}
14801
b6b5d049
VS		 14802static void quirk_pipeb_force(struct drm_device *dev)
14803{
14804 struct drm_i915_private *dev_priv = dev->dev_private;
14805
14806 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14807 DRM_INFO("applying pipe b force quirk\n");
14808}
14809
435793df
KP		 14810/*
14811 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14812 */
14813static void quirk_ssc_force_disable(struct drm_device *dev)
14814{
14815 struct drm_i915_private *dev_priv = dev->dev_private;
14816 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14817 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14818}
14819
4dca20ef 14820/*
5a15ab5b
CE		 14821 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14822 * brightness value
4dca20ef
CE		 14823 */
14824static void quirk_invert_brightness(struct drm_device *dev)
14825{
14826 struct drm_i915_private *dev_priv = dev->dev_private;
14827 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14828 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14829}
14830
9c72cc6f
SD		 14831/* Some VBT's incorrectly indicate no backlight is present */
14832static void quirk_backlight_present(struct drm_device *dev)
14833{
14834 struct drm_i915_private *dev_priv = dev->dev_private;
14835 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14836 DRM_INFO("applying backlight present quirk\n");
14837}
14838
b690e96c
JB		 14839struct intel_quirk {
14840 int device;
14841 int subsystem_vendor;
14842 int subsystem_device;
14843 void (*hook)(struct drm_device *dev);
14844};
14845
5f85f176
EE		 14846/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14847struct intel_dmi_quirk {
14848 void (*hook)(struct drm_device *dev);
14849 const struct dmi_system_id (*dmi_id_list)[];
14850};
14851
14852static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14853{
14854 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14855 return 1;
14856}
14857
14858static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14859 {
14860 .dmi_id_list = &(const struct dmi_system_id[]) {
14861 {
14862 .callback = intel_dmi_reverse_brightness,
14863 .ident = "NCR Corporation",
14864 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14865 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14866 },
14867 },
14868 { } /* terminating entry */
14869 },
14870 .hook = quirk_invert_brightness,
14871 },
14872};
14873
c43b5634 14874static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14875 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14876 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14877
b690e96c
JB		 14878 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14879 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14880
5f080c0f
VS		 14881 /* 830 needs to leave pipe A & dpll A up */
14882 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14883
b6b5d049
VS		 14884 /* 830 needs to leave pipe B & dpll B up */
14885 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14886
435793df
KP		 14887 /* Lenovo U160 cannot use SSC on LVDS */
14888 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14889
14890 /* Sony Vaio Y cannot use SSC on LVDS */
14891 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14892
be505f64
AH		 14893 /* Acer Aspire 5734Z must invert backlight brightness */
14894 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14895
14896 /* Acer/eMachines G725 */
14897 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14898
14899 /* Acer/eMachines e725 */
14900 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14901
14902 /* Acer/Packard Bell NCL20 */
14903 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14904
14905 /* Acer Aspire 4736Z */
14906 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14907
14908 /* Acer Aspire 5336 */
14909 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14910
14911 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14912 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14913
dfb3d47b
SD		 14914 /* Acer C720 Chromebook (Core i3 4005U) */
14915 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14916
b2a9601c 14917 /* Apple Macbook 2,1 (Core 2 T7400) */
14918 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14919
d4967d8c
SD		 14920 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14921 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14922
14923 /* HP Chromebook 14 (Celeron 2955U) */
14924 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14925
14926 /* Dell Chromebook 11 */
14927 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14928};
14929
14930static void intel_init_quirks(struct drm_device *dev)
14931{
14932 struct pci_dev *d = dev->pdev;
14933 int i;
14934
14935 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14936 struct intel_quirk *q = &intel_quirks[i];
14937
14938 if (d->device == q->device &&
14939 (d->subsystem_vendor == q->subsystem_vendor ||
14940 q->subsystem_vendor == PCI_ANY_ID) &&
14941 (d->subsystem_device == q->subsystem_device ||
14942 q->subsystem_device == PCI_ANY_ID))
14943 q->hook(dev);
14944 }
5f85f176
EE		 14945 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14946 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14947 intel_dmi_quirks[i].hook(dev);
14948 }
b690e96c
JB		 14949}
14950
9cce37f4
JB		 14951/* Disable the VGA plane that we never use */
14952static void i915_disable_vga(struct drm_device *dev)
14953{
14954 struct drm_i915_private *dev_priv = dev->dev_private;
14955 u8 sr1;
766aa1c4 14956 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14957
2b37c616 14958 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14959 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14960 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14961 sr1 = inb(VGA_SR_DATA);
14962 outb(sr1 | 1<<5, VGA_SR_DATA);
14963 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14964 udelay(300);
14965
01f5a626 14966 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14967 POSTING_READ(vga_reg);
14968}
14969
f817586c
DV		 14970void intel_modeset_init_hw(struct drm_device *dev)
14971{
b6283055 14972 intel_update_cdclk(dev);
a8f78b58 14973 intel_prepare_ddi(dev);
f817586c 14974 intel_init_clock_gating(dev);
8090c6b9 14975 intel_enable_gt_powersave(dev);
f817586c
DV		 14976}
14977
79e53945
JB		 14978void intel_modeset_init(struct drm_device *dev)
14979{
652c393a 14980 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14981 int sprite, ret;
8cc87b75 14982 enum pipe pipe;
46f297fb 14983 struct intel_crtc *crtc;
79e53945
JB		 14984
14985 drm_mode_config_init(dev);
14986
14987 dev->mode_config.min_width = 0;
14988 dev->mode_config.min_height = 0;
14989
019d96cb
DA		 14990 dev->mode_config.preferred_depth = 24;
14991 dev->mode_config.prefer_shadow = 1;
14992
25bab385
TU		 14993 dev->mode_config.allow_fb_modifiers = true;
14994
e6ecefaa 14995 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14996
b690e96c
JB		 14997 intel_init_quirks(dev);
14998
1fa61106
ED		 14999 intel_init_pm(dev);
15000
e3c74757
BW		 15001 if (INTEL_INFO(dev)->num_pipes == 0)
15002 return;
15003
e70236a8 15004 intel_init_display(dev);
7c10a2b5 15005 intel_init_audio(dev);
e70236a8 15006
a6c45cf0
CW		 15007 if (IS_GEN2(dev)) {
15008 dev->mode_config.max_width = 2048;
15009 dev->mode_config.max_height = 2048;
15010 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15011 dev->mode_config.max_width = 4096;
15012 dev->mode_config.max_height = 4096;
79e53945 15013 } else {
a6c45cf0
CW		 15014 dev->mode_config.max_width = 8192;
15015 dev->mode_config.max_height = 8192;
79e53945 15016 }
068be561 15017
dc41c154
VS		 15018 if (IS_845G(dev) || IS_I865G(dev)) {
15019 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15020 dev->mode_config.cursor_height = 1023;
15021 } else if (IS_GEN2(dev)) {
068be561
DL		 15022 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15023 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15024 } else {
15025 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15026 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15027 }
15028
5d4545ae 15029 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15030
28c97730 15031 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15032 INTEL_INFO(dev)->num_pipes,
15033 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15034
055e393f 15035 for_each_pipe(dev_priv, pipe) {
8cc87b75 15036 intel_crtc_init(dev, pipe);
3bdcfc0c 15037 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15038 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15039 if (ret)
06da8da2 15040 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15041 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15042 }
79e53945
JB		 15043 }
15044
f42bb70d
JB		 15045 intel_init_dpio(dev);
15046
e72f9fbf 15047 intel_shared_dpll_init(dev);
ee7b9f93 15048
9cce37f4
JB		 15049 /* Just disable it once at startup */
15050 i915_disable_vga(dev);
79e53945 15051 intel_setup_outputs(dev);
11be49eb
CW		 15052
15053 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15054 intel_fbc_disable(dev);
fa9fa083 15055
6e9f798d 15056 drm_modeset_lock_all(dev);
fa9fa083 15057 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15058 drm_modeset_unlock_all(dev);
46f297fb 15059
d3fcc808 15060 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15061 if (!crtc->active)
15062 continue;
15063
46f297fb 15064 /*
46f297fb
JB		 15065 * Note that reserving the BIOS fb up front prevents us
15066 * from stuffing other stolen allocations like the ring
15067 * on top. This prevents some ugliness at boot time, and
15068 * can even allow for smooth boot transitions if the BIOS
15069 * fb is large enough for the active pipe configuration.
15070 */
5724dbd1
DL		 15071 if (dev_priv->display.get_initial_plane_config) {
15072 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15073 &crtc->plane_config);
15074 /*
15075 * If the fb is shared between multiple heads, we'll
15076 * just get the first one.
15077 */
f6936e29 15078 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15079 }
46f297fb 15080 }
2c7111db
CW		 15081}
15082
7fad798e
DV		 15083static void intel_enable_pipe_a(struct drm_device *dev)
15084{
15085 struct intel_connector *connector;
15086 struct drm_connector *crt = NULL;
15087 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15088 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15089
15090 /* We can't just switch on the pipe A, we need to set things up with a
15091 * proper mode and output configuration. As a gross hack, enable pipe A
15092 * by enabling the load detect pipe once. */
3a3371ff 15093 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15094 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15095 crt = &connector->base;
15096 break;
15097 }
15098 }
15099
15100 if (!crt)
15101 return;
15102
208bf9fd 15103 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15104 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15105}
15106
fa555837
DV		 15107static bool
15108intel_check_plane_mapping(struct intel_crtc *crtc)
15109{
7eb552ae
BW		 15110 struct drm_device *dev = crtc->base.dev;
15111 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15112 u32 reg, val;
15113
7eb552ae 15114 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15115 return true;
15116
15117 reg = DSPCNTR(!crtc->plane);
15118 val = I915_READ(reg);
15119
15120 if ((val & DISPLAY_PLANE_ENABLE) &&
15121 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15122 return false;
15123
15124 return true;
15125}
15126
24929352
DV		 15127static void intel_sanitize_crtc(struct intel_crtc *crtc)
15128{
15129 struct drm_device *dev = crtc->base.dev;
15130 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 15131 struct intel_encoder *encoder;
fa555837 15132 u32 reg;
b17d48e2 15133 bool enable;
24929352 15134
24929352 15135 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15136 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15137 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15138
d3eaf884 15139 /* restore vblank interrupts to correct state */
9625604c 15140 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15141 if (crtc->active) {
15142 update_scanline_offset(crtc);
9625604c
DV		 15143 drm_crtc_vblank_on(&crtc->base);
15144 }
d3eaf884 15145
24929352 15146 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15147 * disable the crtc (and hence change the state) if it is wrong. Note
15148 * that gen4+ has a fixed plane -> pipe mapping. */
15149 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15150 bool plane;
15151
24929352
DV		 15152 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15153 crtc->base.base.id);
15154
15155 /* Pipe has the wrong plane attached and the plane is active.
15156 * Temporarily change the plane mapping and disable everything
15157 * ... */
15158 plane = crtc->plane;
b70709a6 15159 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15160 crtc->plane = !plane;
b17d48e2 15161 intel_crtc_disable_noatomic(&crtc->base);
24929352 15162 crtc->plane = plane;
24929352 15163 }
24929352 15164
7fad798e
DV		 15165 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15166 crtc->pipe == PIPE_A && !crtc->active) {
15167 /* BIOS forgot to enable pipe A, this mostly happens after
15168 * resume. Force-enable the pipe to fix this, the update_dpms
15169 * call below we restore the pipe to the right state, but leave
15170 * the required bits on. */
15171 intel_enable_pipe_a(dev);
15172 }
15173
24929352
DV		 15174 /* Adjust the state of the output pipe according to whether we
15175 * have active connectors/encoders. */
b17d48e2
ML		 15176 enable = false;
15177 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15178 enable |= encoder->connectors_active;
24929352 15179
b17d48e2
ML		 15180 if (!enable)
15181 intel_crtc_disable_noatomic(&crtc->base);
24929352 15182
53d9f4e9 15183 if (crtc->active != crtc->base.state->active) {
24929352
DV		 15184
15185 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15186 * functions or because of calls to intel_crtc_disable_noatomic,
15187 * or because the pipe is force-enabled due to the
24929352
DV		 15188 * pipe A quirk. */
15189 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15190 crtc->base.base.id,
83d65738 15191 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15192 crtc->active ? "enabled" : "disabled");
15193
83d65738 15194 crtc->base.state->enable = crtc->active;
49d6fa21 15195 crtc->base.state->active = crtc->active;
24929352
DV		 15196 crtc->base.enabled = crtc->active;
15197
15198 /* Because we only establish the connector -> encoder ->
15199 * crtc links if something is active, this means the
15200 * crtc is now deactivated. Break the links. connector
15201 * -> encoder links are only establish when things are
15202 * actually up, hence no need to break them. */
15203 WARN_ON(crtc->active);
15204
15205 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15206 WARN_ON(encoder->connectors_active);
15207 encoder->base.crtc = NULL;
15208 }
15209 }
c5ab3bc0 15210
a3ed6aad 15211 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15212 /*
15213 * We start out with underrun reporting disabled to avoid races.
15214 * For correct bookkeeping mark this on active crtcs.
15215 *
c5ab3bc0
DV		 15216 * Also on gmch platforms we dont have any hardware bits to
15217 * disable the underrun reporting. Which means we need to start
15218 * out with underrun reporting disabled also on inactive pipes,
15219 * since otherwise we'll complain about the garbage we read when
15220 * e.g. coming up after runtime pm.
15221 *
4cc31489
DV		 15222 * No protection against concurrent access is required - at
15223 * worst a fifo underrun happens which also sets this to false.
15224 */
15225 crtc->cpu_fifo_underrun_disabled = true;
15226 crtc->pch_fifo_underrun_disabled = true;
15227 }
24929352
DV		 15228}
15229
15230static void intel_sanitize_encoder(struct intel_encoder *encoder)
15231{
15232 struct intel_connector *connector;
15233 struct drm_device *dev = encoder->base.dev;
15234
15235 /* We need to check both for a crtc link (meaning that the
15236 * encoder is active and trying to read from a pipe) and the
15237 * pipe itself being active. */
15238 bool has_active_crtc = encoder->base.crtc &&
15239 to_intel_crtc(encoder->base.crtc)->active;
15240
15241 if (encoder->connectors_active && !has_active_crtc) {
15242 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15243 encoder->base.base.id,
8e329a03 15244 encoder->base.name);
24929352
DV		 15245
15246 /* Connector is active, but has no active pipe. This is
15247 * fallout from our resume register restoring. Disable
15248 * the encoder manually again. */
15249 if (encoder->base.crtc) {
15250 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15251 encoder->base.base.id,
8e329a03 15252 encoder->base.name);
24929352 15253 encoder->disable(encoder);
a62d1497
VS		 15254 if (encoder->post_disable)
15255 encoder->post_disable(encoder);
24929352 15256 }
7f1950fb
EE		 15257 encoder->base.crtc = NULL;
15258 encoder->connectors_active = false;
24929352
DV		 15259
15260 /* Inconsistent output/port/pipe state happens presumably due to
15261 * a bug in one of the get_hw_state functions. Or someplace else
15262 * in our code, like the register restore mess on resume. Clamp
15263 * things to off as a safer default. */
3a3371ff 15264 for_each_intel_connector(dev, connector) {
24929352
DV		 15265 if (connector->encoder != encoder)
15266 continue;
7f1950fb
EE		 15267 connector->base.dpms = DRM_MODE_DPMS_OFF;
15268 connector->base.encoder = NULL;
24929352
DV		 15269 }
15270 }
15271 /* Enabled encoders without active connectors will be fixed in
15272 * the crtc fixup. */
15273}
15274
04098753 15275void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15276{
15277 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15278 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15279
04098753
ID		 15280 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15281 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15282 i915_disable_vga(dev);
15283 }
15284}
15285
15286void i915_redisable_vga(struct drm_device *dev)
15287{
15288 struct drm_i915_private *dev_priv = dev->dev_private;
15289
8dc8a27c
PZ		 15290 /* This function can be called both from intel_modeset_setup_hw_state or
15291 * at a very early point in our resume sequence, where the power well
15292 * structures are not yet restored. Since this function is at a very
15293 * paranoid "someone might have enabled VGA while we were not looking"
15294 * level, just check if the power well is enabled instead of trying to
15295 * follow the "don't touch the power well if we don't need it" policy
15296 * the rest of the driver uses. */
f458ebbc 15297 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15298 return;
15299
04098753 15300 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15301}
15302
98ec7739
VS		 15303static bool primary_get_hw_state(struct intel_crtc *crtc)
15304{
15305 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15306
d032ffa0
ML		 15307 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15308}
15309
15310static void readout_plane_state(struct intel_crtc *crtc,
15311 struct intel_crtc_state *crtc_state)
15312{
15313 struct intel_plane *p;
15314 struct drm_plane_state *drm_plane_state;
15315 bool active = crtc_state->base.active;
15316
15317 if (active) {
15318 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15319
15320 /* apply to previous sw state too */
15321 to_intel_crtc_state(crtc->base.state)->quirks |=
15322 PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15323 }
98ec7739 15324
d032ffa0
ML		 15325 for_each_intel_plane(crtc->base.dev, p) {
15326 bool visible = active;
15327
15328 if (crtc->pipe != p->pipe)
15329 continue;
15330
15331 drm_plane_state = p->base.state;
15332 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15333 visible = primary_get_hw_state(crtc);
15334 to_intel_plane_state(drm_plane_state)->visible = visible;
15335 } else {
15336 /*
15337 * unknown state, assume it's off to force a transition
15338 * to on when calculating state changes.
15339 */
15340 to_intel_plane_state(drm_plane_state)->visible = false;
15341 }
15342
15343 if (visible) {
15344 crtc_state->base.plane_mask |=
15345 1 << drm_plane_index(&p->base);
15346 } else if (crtc_state->base.state) {
15347 /* Make this unconditional for atomic hw readout. */
15348 crtc_state->base.plane_mask &=
15349 ~(1 << drm_plane_index(&p->base));
15350 }
15351 }
98ec7739
VS		 15352}
15353
30e984df 15354static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15355{
15356 struct drm_i915_private *dev_priv = dev->dev_private;
15357 enum pipe pipe;
24929352
DV		 15358 struct intel_crtc *crtc;
15359 struct intel_encoder *encoder;
15360 struct intel_connector *connector;
5358901f 15361 int i;
24929352 15362
d3fcc808 15363 for_each_intel_crtc(dev, crtc) {
6e3c9717 15364 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15365 crtc->config->base.crtc = &crtc->base;
3b117c8f 15366
6e3c9717 15367 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15368
0e8ffe1b 15369 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15370 crtc->config);
24929352 15371
83d65738 15372 crtc->base.state->enable = crtc->active;
49d6fa21 15373 crtc->base.state->active = crtc->active;
24929352 15374 crtc->base.enabled = crtc->active;
b8b7fade 15375 crtc->base.hwmode = crtc->config->base.adjusted_mode;
b70709a6 15376
d032ffa0 15377 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15378
15379 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15380 crtc->base.base.id,
15381 crtc->active ? "enabled" : "disabled");
15382 }
15383
5358901f
DV		 15384 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15385 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15386
3e369b76
ACO		 15387 pll->on = pll->get_hw_state(dev_priv, pll,
15388 &pll->config.hw_state);
5358901f 15389 pll->active = 0;
3e369b76 15390 pll->config.crtc_mask = 0;
d3fcc808 15391 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15392 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15393 pll->active++;
3e369b76 15394 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15395 }
5358901f 15396 }
5358901f 15397
1e6f2ddc 15398 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15399 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15400
3e369b76 15401 if (pll->config.crtc_mask)
bd2bb1b9 15402 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15403 }
15404
b2784e15 15405 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15406 pipe = 0;
15407
15408 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15409 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15410 encoder->base.crtc = &crtc->base;
6e3c9717 15411 encoder->get_config(encoder, crtc->config);
24929352
DV		 15412 } else {
15413 encoder->base.crtc = NULL;
15414 }
15415
15416 encoder->connectors_active = false;
6f2bcceb 15417 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15418 encoder->base.base.id,
8e329a03 15419 encoder->base.name,
24929352 15420 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15421 pipe_name(pipe));
24929352
DV		 15422 }
15423
3a3371ff 15424 for_each_intel_connector(dev, connector) {
24929352
DV		 15425 if (connector->get_hw_state(connector)) {
15426 connector->base.dpms = DRM_MODE_DPMS_ON;
15427 connector->encoder->connectors_active = true;
15428 connector->base.encoder = &connector->encoder->base;
15429 } else {
15430 connector->base.dpms = DRM_MODE_DPMS_OFF;
15431 connector->base.encoder = NULL;
15432 }
15433 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15434 connector->base.base.id,
c23cc417 15435 connector->base.name,
24929352
DV		 15436 connector->base.encoder ? "enabled" : "disabled");
15437 }
30e984df
DV		 15438}
15439
15440/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15441 * and i915 state tracking structures. */
15442void intel_modeset_setup_hw_state(struct drm_device *dev,
15443 bool force_restore)
15444{
15445 struct drm_i915_private *dev_priv = dev->dev_private;
15446 enum pipe pipe;
30e984df
DV		 15447 struct intel_crtc *crtc;
15448 struct intel_encoder *encoder;
35c95375 15449 int i;
30e984df
DV		 15450
15451 intel_modeset_readout_hw_state(dev);
24929352 15452
babea61d
JB		 15453 /*
15454 * Now that we have the config, copy it to each CRTC struct
15455 * Note that this could go away if we move to using crtc_config
15456 * checking everywhere.
15457 */
d3fcc808 15458 for_each_intel_crtc(dev, crtc) {
d330a953 15459 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15460 intel_mode_from_pipe_config(&crtc->base.mode,
15461 crtc->config);
babea61d
JB		 15462 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15463 crtc->base.base.id);
15464 drm_mode_debug_printmodeline(&crtc->base.mode);
15465 }
15466 }
15467
24929352 15468 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15469 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15470 intel_sanitize_encoder(encoder);
15471 }
15472
055e393f 15473 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15474 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15475 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15476 intel_dump_pipe_config(crtc, crtc->config,
15477 "[setup_hw_state]");
24929352 15478 }
9a935856 15479
d29b2f9d
ACO		 15480 intel_modeset_update_connector_atomic_state(dev);
15481
35c95375
DV		 15482 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15483 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15484
15485 if (!pll->on || pll->active)
15486 continue;
15487
15488 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15489
15490 pll->disable(dev_priv, pll);
15491 pll->on = false;
15492 }
15493
26e1fe4f 15494 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15495 vlv_wm_get_hw_state(dev);
15496 else if (IS_GEN9(dev))
3078999f
PB		 15497 skl_wm_get_hw_state(dev);
15498 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15499 ilk_wm_get_hw_state(dev);
15500
45e2b5f6 15501 if (force_restore) {
7d0bc1ea
VS		 15502 i915_redisable_vga(dev);
15503
f30da187
DV		 15504 /*
15505 * We need to use raw interfaces for restoring state to avoid
15506 * checking (bogus) intermediate states.
15507 */
055e393f 15508 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15509 struct drm_crtc *crtc =
15510 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15511
83a57153 15512 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15513 }
15514 } else {
15515 intel_modeset_update_staged_output_state(dev);
15516 }
8af6cf88
DV		 15517
15518 intel_modeset_check_state(dev);
2c7111db
CW		 15519}
15520
15521void intel_modeset_gem_init(struct drm_device *dev)
15522{
92122789 15523 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15524 struct drm_crtc *c;
2ff8fde1 15525 struct drm_i915_gem_object *obj;
e0d6149b 15526 int ret;
484b41dd 15527
ae48434c
ID		 15528 mutex_lock(&dev->struct_mutex);
15529 intel_init_gt_powersave(dev);
15530 mutex_unlock(&dev->struct_mutex);
15531
92122789
JB		 15532 /*
15533 * There may be no VBT; and if the BIOS enabled SSC we can
15534 * just keep using it to avoid unnecessary flicker. Whereas if the
15535 * BIOS isn't using it, don't assume it will work even if the VBT
15536 * indicates as much.
15537 */
15538 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15539 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15540 DREF_SSC1_ENABLE);
15541
1833b134 15542 intel_modeset_init_hw(dev);
02e792fb
DV		 15543
15544 intel_setup_overlay(dev);
484b41dd
JB		 15545
15546 /*
15547 * Make sure any fbs we allocated at startup are properly
15548 * pinned & fenced. When we do the allocation it's too early
15549 * for this.
15550 */
70e1e0ec 15551 for_each_crtc(dev, c) {
2ff8fde1
MR		 15552 obj = intel_fb_obj(c->primary->fb);
15553 if (obj == NULL)
484b41dd
JB		 15554 continue;
15555
e0d6149b
TU		 15556 mutex_lock(&dev->struct_mutex);
15557 ret = intel_pin_and_fence_fb_obj(c->primary,
15558 c->primary->fb,
15559 c->primary->state,
91af127f 15560 NULL, NULL);
e0d6149b
TU		 15561 mutex_unlock(&dev->struct_mutex);
15562 if (ret) {
484b41dd
JB		 15563 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15564 to_intel_crtc(c)->pipe);
66e514c1
DA		 15565 drm_framebuffer_unreference(c->primary->fb);
15566 c->primary->fb = NULL;
36750f28 15567 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15568 update_state_fb(c->primary);
36750f28 15569 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15570 }
15571 }
0962c3c9
VS		 15572
15573 intel_backlight_register(dev);
79e53945
JB		 15574}
15575
4932e2c3
ID		 15576void intel_connector_unregister(struct intel_connector *intel_connector)
15577{
15578 struct drm_connector *connector = &intel_connector->base;
15579
15580 intel_panel_destroy_backlight(connector);
34ea3d38 15581 drm_connector_unregister(connector);
4932e2c3
ID		 15582}
15583
79e53945
JB		 15584void intel_modeset_cleanup(struct drm_device *dev)
15585{
652c393a 15586 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15587 struct drm_connector *connector;
652c393a 15588
2eb5252e
ID		 15589 intel_disable_gt_powersave(dev);
15590
0962c3c9
VS		 15591 intel_backlight_unregister(dev);
15592
fd0c0642
DV		 15593 /*
15594 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15595 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15596 * experience fancy races otherwise.
15597 */
2aeb7d3a 15598 intel_irq_uninstall(dev_priv);
eb21b92b 15599
fd0c0642
DV		 15600 /*
15601 * Due to the hpd irq storm handling the hotplug work can re-arm the
15602 * poll handlers. Hence disable polling after hpd handling is shut down.
15603 */
f87ea761 15604 drm_kms_helper_poll_fini(dev);
fd0c0642 15605
723bfd70
JB		 15606 intel_unregister_dsm_handler();
15607
b5e4b84d 15608 mutex_lock(&dev->struct_mutex);
7ff0ebcc 15609 intel_fbc_disable(dev);
69341a5e
KH		 15610 mutex_unlock(&dev->struct_mutex);
15611
1630fe75
CW		 15612 /* flush any delayed tasks or pending work */
15613 flush_scheduled_work();
15614
db31af1d
JN		 15615 /* destroy the backlight and sysfs files before encoders/connectors */
15616 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15617 struct intel_connector *intel_connector;
15618
15619 intel_connector = to_intel_connector(connector);
15620 intel_connector->unregister(intel_connector);
db31af1d 15621 }
d9255d57 15622
79e53945 15623 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15624
15625 intel_cleanup_overlay(dev);
ae48434c
ID		 15626
15627 mutex_lock(&dev->struct_mutex);
15628 intel_cleanup_gt_powersave(dev);
15629 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15630}
15631
f1c79df3
ZW		 15632/*
15633 * Return which encoder is currently attached for connector.
15634 */
df0e9248 15635struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15636{
df0e9248
CW		 15637 return &intel_attached_encoder(connector)->base;
15638}
f1c79df3 15639
df0e9248
CW		 15640void intel_connector_attach_encoder(struct intel_connector *connector,
15641 struct intel_encoder *encoder)
15642{
15643 connector->encoder = encoder;
15644 drm_mode_connector_attach_encoder(&connector->base,
15645 &encoder->base);
79e53945 15646}
28d52043
DA		 15647
15648/*
15649 * set vga decode state - true == enable VGA decode
15650 */
15651int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15652{
15653 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15654 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15655 u16 gmch_ctrl;
15656
75fa041d
CW		 15657 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15658 DRM_ERROR("failed to read control word\n");
15659 return -EIO;
15660 }
15661
c0cc8a55
CW		 15662 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15663 return 0;
15664
28d52043
DA		 15665 if (state)
15666 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15667 else
15668 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15669
15670 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15671 DRM_ERROR("failed to write control word\n");
15672 return -EIO;
15673 }
15674
28d52043
DA		 15675 return 0;
15676}
c4a1d9e4 15677
c4a1d9e4 15678struct intel_display_error_state {
ff57f1b0
PZ		 15679
15680 u32 power_well_driver;
15681
63b66e5b
CW		 15682 int num_transcoders;
15683
c4a1d9e4
CW		 15684 struct intel_cursor_error_state {
15685 u32 control;
15686 u32 position;
15687 u32 base;
15688 u32 size;
52331309 15689 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15690
15691 struct intel_pipe_error_state {
ddf9c536 15692 bool power_domain_on;
c4a1d9e4 15693 u32 source;
f301b1e1 15694 u32 stat;
52331309 15695 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15696
15697 struct intel_plane_error_state {
15698 u32 control;
15699 u32 stride;
15700 u32 size;
15701 u32 pos;
15702 u32 addr;
15703 u32 surface;
15704 u32 tile_offset;
52331309 15705 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15706
15707 struct intel_transcoder_error_state {
ddf9c536 15708 bool power_domain_on;
63b66e5b
CW		 15709 enum transcoder cpu_transcoder;
15710
15711 u32 conf;
15712
15713 u32 htotal;
15714 u32 hblank;
15715 u32 hsync;
15716 u32 vtotal;
15717 u32 vblank;
15718 u32 vsync;
15719 } transcoder[4];
c4a1d9e4
CW		 15720};
15721
15722struct intel_display_error_state *
15723intel_display_capture_error_state(struct drm_device *dev)
15724{
fbee40df 15725 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15726 struct intel_display_error_state *error;
63b66e5b
CW		 15727 int transcoders[] = {
15728 TRANSCODER_A,
15729 TRANSCODER_B,
15730 TRANSCODER_C,
15731 TRANSCODER_EDP,
15732 };
c4a1d9e4
CW		 15733 int i;
15734
63b66e5b
CW		 15735 if (INTEL_INFO(dev)->num_pipes == 0)
15736 return NULL;
15737
9d1cb914 15738 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15739 if (error == NULL)
15740 return NULL;
15741
190be112 15742 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15743 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15744
055e393f 15745 for_each_pipe(dev_priv, i) {
ddf9c536 15746 error->pipe[i].power_domain_on =
f458ebbc
DV		 15747 __intel_display_power_is_enabled(dev_priv,
15748 POWER_DOMAIN_PIPE(i));
ddf9c536 15749 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15750 continue;
15751
5efb3e28
VS		 15752 error->cursor[i].control = I915_READ(CURCNTR(i));
15753 error->cursor[i].position = I915_READ(CURPOS(i));
15754 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15755
15756 error->plane[i].control = I915_READ(DSPCNTR(i));
15757 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15758 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15759 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15760 error->plane[i].pos = I915_READ(DSPPOS(i));
15761 }
ca291363
PZ		 15762 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15763 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15764 if (INTEL_INFO(dev)->gen >= 4) {
15765 error->plane[i].surface = I915_READ(DSPSURF(i));
15766 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15767 }
15768
c4a1d9e4 15769 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15770
3abfce77 15771 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15772 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15773 }
15774
15775 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15776 if (HAS_DDI(dev_priv->dev))
15777 error->num_transcoders++; /* Account for eDP. */
15778
15779 for (i = 0; i < error->num_transcoders; i++) {
15780 enum transcoder cpu_transcoder = transcoders[i];
15781
ddf9c536 15782 error->transcoder[i].power_domain_on =
f458ebbc 15783 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15784 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15785 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15786 continue;
15787
63b66e5b
CW		 15788 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15789
15790 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15791 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15792 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15793 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15794 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15795 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15796 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15797 }
15798
15799 return error;
15800}
15801
edc3d884
MK		 15802#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15803
c4a1d9e4 15804void
edc3d884 15805intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15806 struct drm_device *dev,
15807 struct intel_display_error_state *error)
15808{
055e393f 15809 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15810 int i;
15811
63b66e5b
CW		 15812 if (!error)
15813 return;
15814
edc3d884 15815 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15816 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15817 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15818 error->power_well_driver);
055e393f 15819 for_each_pipe(dev_priv, i) {
edc3d884 15820 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15821 err_printf(m, " Power: %s\n",
15822 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15823 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15824 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15825
15826 err_printf(m, "Plane [%d]:\n", i);
15827 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15828 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15829 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15830 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15831 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15832 }
4b71a570 15833 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15834 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15835 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15836 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15837 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15838 }
15839
edc3d884
MK		 15840 err_printf(m, "Cursor [%d]:\n", i);
15841 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15842 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15843 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15844 }
63b66e5b
CW		 15845
15846 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15847 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15848 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15849 err_printf(m, " Power: %s\n",
15850 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15851 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15852 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15853 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15854 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15855 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15856 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15857 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15858 }
c4a1d9e4 15859}
e2fcdaa9
VS		 15860
15861void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15862{
15863 struct intel_crtc *crtc;
15864
15865 for_each_intel_crtc(dev, crtc) {
15866 struct intel_unpin_work *work;
e2fcdaa9 15867
5e2d7afc 15868 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15869
15870 work = crtc->unpin_work;
15871
15872 if (work && work->event &&
15873 work->event->base.file_priv == file) {
15874 kfree(work->event);
15875 work->event = NULL;
15876 }
15877
5e2d7afc 15878 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15879 }
15880}
Linux kernel - Deliverables
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