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drm/i915: rename intel_{en, dis}able_transcoder
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
DV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
DV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
DV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
DV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
DV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
DV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
DV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a 1581/**
b6b4e185 1582 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
b6b4e185 1589static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
b8a4f404
PZ		 1673static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
040484af
JB		 1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
59c859d6
ED		 1692 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694 return;
1695 }
040484af
JB		 1696 reg = TRANSCONF(pipe);
1697 val = I915_READ(reg);
5f7f726d 1698 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1699
1700 if (HAS_PCH_IBX(dev_priv->dev)) {
1701 /*
1702 * make the BPC in transcoder be consistent with
1703 * that in pipeconf reg.
1704 */
1705 val &= ~PIPE_BPC_MASK;
5f7f726d 1706 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1707 }
5f7f726d
PZ		 1708
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1711 if (HAS_PCH_IBX(dev_priv->dev) &&
1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1714 else
1715 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1716 else
1717 val |= TRANS_PROGRESSIVE;
1718
040484af
JB		 1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722}
1723
b8a4f404
PZ		 1724static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1725 enum pipe pipe)
040484af
JB		 1726{
1727 int reg;
1728 u32 val;
1729
1730 /* FDI relies on the transcoder */
1731 assert_fdi_tx_disabled(dev_priv, pipe);
1732 assert_fdi_rx_disabled(dev_priv, pipe);
1733
291906f1
JB		 1734 /* Ports must be off as well */
1735 assert_pch_ports_disabled(dev_priv, pipe);
1736
040484af
JB		 1737 reg = TRANSCONF(pipe);
1738 val = I915_READ(reg);
1739 val &= ~TRANS_ENABLE;
1740 I915_WRITE(reg, val);
1741 /* wait for PCH transcoder off, transcoder state */
1742 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1743 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1744}
1745
b24e7179 1746/**
309cfea8 1747 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to enable
040484af 1750 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1751 *
1752 * Enable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe is actually running (i.e. first vblank) before
1758 * returning.
1759 */
040484af
JB		 1760static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761 bool pch_port)
b24e7179 1762{
702e7a56
PZ		 1763 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 pipe);
b24e7179
JB		 1765 int reg;
1766 u32 val;
1767
1768 /*
1769 * A pipe without a PLL won't actually be able to drive bits from
1770 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1771 * need the check.
1772 */
1773 if (!HAS_PCH_SPLIT(dev_priv->dev))
1774 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1775 else {
1776 if (pch_port) {
1777 /* if driving the PCH, we need FDI enabled */
1778 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780 }
1781 /* FIXME: assert CPU port conditions for SNB+ */
1782 }
b24e7179 1783
702e7a56 1784 reg = PIPECONF(cpu_transcoder);
b24e7179 1785 val = I915_READ(reg);
00d70b15
CW		 1786 if (val & PIPECONF_ENABLE)
1787 return;
1788
1789 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1790 intel_wait_for_vblank(dev_priv->dev, pipe);
1791}
1792
1793/**
309cfea8 1794 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1797 *
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800 *
1801 * @pipe should be %PIPE_A or %PIPE_B.
1802 *
1803 * Will wait until the pipe has shut down before returning.
1804 */
1805static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807{
702e7a56
PZ		 1808 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809 pipe);
b24e7179
JB		 1810 int reg;
1811 u32 val;
1812
1813 /*
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1816 */
1817 assert_planes_disabled(dev_priv, pipe);
1818
1819 /* Don't disable pipe A or pipe A PLLs if needed */
1820 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821 return;
1822
702e7a56 1823 reg = PIPECONF(cpu_transcoder);
b24e7179 1824 val = I915_READ(reg);
00d70b15
CW		 1825 if ((val & PIPECONF_ENABLE) == 0)
1826 return;
1827
1828 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1829 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830}
1831
d74362c9
KP		 1832/*
1833 * Plane regs are double buffered, going from enabled->disabled needs a
1834 * trigger in order to latch. The display address reg provides this.
1835 */
6f1d69b0 1836void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1837 enum plane plane)
1838{
14f86147
DL		 1839 if (dev_priv->info->gen >= 4)
1840 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841 else
1842 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1843}
1844
b24e7179
JB		 1845/**
1846 * intel_enable_plane - enable a display plane on a given pipe
1847 * @dev_priv: i915 private structure
1848 * @plane: plane to enable
1849 * @pipe: pipe being fed
1850 *
1851 * Enable @plane on @pipe, making sure that @pipe is running first.
1852 */
1853static void intel_enable_plane(struct drm_i915_private *dev_priv,
1854 enum plane plane, enum pipe pipe)
1855{
1856 int reg;
1857 u32 val;
1858
1859 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1860 assert_pipe_enabled(dev_priv, pipe);
1861
1862 reg = DSPCNTR(plane);
1863 val = I915_READ(reg);
00d70b15
CW		 1864 if (val & DISPLAY_PLANE_ENABLE)
1865 return;
1866
1867 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1868 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1869 intel_wait_for_vblank(dev_priv->dev, pipe);
1870}
1871
b24e7179
JB		 1872/**
1873 * intel_disable_plane - disable a display plane
1874 * @dev_priv: i915 private structure
1875 * @plane: plane to disable
1876 * @pipe: pipe consuming the data
1877 *
1878 * Disable @plane; should be an independent operation.
1879 */
1880static void intel_disable_plane(struct drm_i915_private *dev_priv,
1881 enum plane plane, enum pipe pipe)
1882{
1883 int reg;
1884 u32 val;
1885
1886 reg = DSPCNTR(plane);
1887 val = I915_READ(reg);
00d70b15
CW		 1888 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1889 return;
1890
1891 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1892 intel_flush_display_plane(dev_priv, plane);
1893 intel_wait_for_vblank(dev_priv->dev, pipe);
1894}
1895
127bd2ac 1896int
48b956c5 1897intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1898 struct drm_i915_gem_object *obj,
919926ae 1899 struct intel_ring_buffer *pipelined)
6b95a207 1900{
ce453d81 1901 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1902 u32 alignment;
1903 int ret;
1904
05394f39 1905 switch (obj->tiling_mode) {
6b95a207 1906 case I915_TILING_NONE:
534843da
CW		 1907 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1908 alignment = 128 * 1024;
a6c45cf0 1909 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1910 alignment = 4 * 1024;
1911 else
1912 alignment = 64 * 1024;
6b95a207
KH		 1913 break;
1914 case I915_TILING_X:
1915 /* pin() will align the object as required by fence */
1916 alignment = 0;
1917 break;
1918 case I915_TILING_Y:
1919 /* FIXME: Is this true? */
1920 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1921 return -EINVAL;
1922 default:
1923 BUG();
1924 }
1925
ce453d81 1926 dev_priv->mm.interruptible = false;
2da3b9b9 1927 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1928 if (ret)
ce453d81 1929 goto err_interruptible;
6b95a207
KH		 1930
1931 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1932 * fence, whereas 965+ only requires a fence if using
1933 * framebuffer compression. For simplicity, we always install
1934 * a fence as the cost is not that onerous.
1935 */
06d98131 1936 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1937 if (ret)
1938 goto err_unpin;
1690e1eb 1939
9a5a53b3 1940 i915_gem_object_pin_fence(obj);
6b95a207 1941
ce453d81 1942 dev_priv->mm.interruptible = true;
6b95a207 1943 return 0;
48b956c5
CW		 1944
1945err_unpin:
1946 i915_gem_object_unpin(obj);
ce453d81
CW		 1947err_interruptible:
1948 dev_priv->mm.interruptible = true;
48b956c5 1949 return ret;
6b95a207
KH		 1950}
1951
1690e1eb
CW		 1952void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1953{
1954 i915_gem_object_unpin_fence(obj);
1955 i915_gem_object_unpin(obj);
1956}
1957
c2c75131
DV		 1958/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1959 * is assumed to be a power-of-two. */
5a35e99e
DL		 1960unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1961 unsigned int bpp,
1962 unsigned int pitch)
c2c75131
DV		 1963{
1964 int tile_rows, tiles;
1965
1966 tile_rows = *y / 8;
1967 *y %= 8;
1968 tiles = *x / (512/bpp);
1969 *x %= 512/bpp;
1970
1971 return tile_rows * pitch * 8 + tiles * 4096;
1972}
1973
17638cd6
JB		 1974static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1975 int x, int y)
81255565
JB		 1976{
1977 struct drm_device *dev = crtc->dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980 struct intel_framebuffer *intel_fb;
05394f39 1981 struct drm_i915_gem_object *obj;
81255565 1982 int plane = intel_crtc->plane;
e506a0c6 1983 unsigned long linear_offset;
81255565 1984 u32 dspcntr;
5eddb70b 1985 u32 reg;
81255565
JB		 1986
1987 switch (plane) {
1988 case 0:
1989 case 1:
1990 break;
1991 default:
1992 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1993 return -EINVAL;
1994 }
1995
1996 intel_fb = to_intel_framebuffer(fb);
1997 obj = intel_fb->obj;
81255565 1998
5eddb70b
CW		 1999 reg = DSPCNTR(plane);
2000 dspcntr = I915_READ(reg);
81255565
JB		 2001 /* Mask out pixel format bits in case we change it */
2002 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2003 switch (fb->pixel_format) {
2004 case DRM_FORMAT_C8:
81255565
JB		 2005 dspcntr |= DISPPLANE_8BPP;
2006 break;
57779d06
VS		 2007 case DRM_FORMAT_XRGB1555:
2008 case DRM_FORMAT_ARGB1555:
2009 dspcntr |= DISPPLANE_BGRX555;
81255565 2010 break;
57779d06
VS		 2011 case DRM_FORMAT_RGB565:
2012 dspcntr |= DISPPLANE_BGRX565;
2013 break;
2014 case DRM_FORMAT_XRGB8888:
2015 case DRM_FORMAT_ARGB8888:
2016 dspcntr |= DISPPLANE_BGRX888;
2017 break;
2018 case DRM_FORMAT_XBGR8888:
2019 case DRM_FORMAT_ABGR8888:
2020 dspcntr |= DISPPLANE_RGBX888;
2021 break;
2022 case DRM_FORMAT_XRGB2101010:
2023 case DRM_FORMAT_ARGB2101010:
2024 dspcntr |= DISPPLANE_BGRX101010;
2025 break;
2026 case DRM_FORMAT_XBGR2101010:
2027 case DRM_FORMAT_ABGR2101010:
2028 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2029 break;
2030 default:
57779d06 2031 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2032 return -EINVAL;
2033 }
57779d06 2034
a6c45cf0 2035 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2036 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2037 dspcntr |= DISPPLANE_TILED;
2038 else
2039 dspcntr &= ~DISPPLANE_TILED;
2040 }
2041
5eddb70b 2042 I915_WRITE(reg, dspcntr);
81255565 2043
e506a0c6 2044 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2045
c2c75131
DV		 2046 if (INTEL_INFO(dev)->gen >= 4) {
2047 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2048 intel_gen4_compute_offset_xtiled(&x, &y,
2049 fb->bits_per_pixel / 8,
2050 fb->pitches[0]);
c2c75131
DV		 2051 linear_offset -= intel_crtc->dspaddr_offset;
2052 } else {
e506a0c6 2053 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2054 }
e506a0c6
DV		 2055
2056 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2057 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2058 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2059 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2060 I915_MODIFY_DISPBASE(DSPSURF(plane),
2061 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2062 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2063 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2064 } else
e506a0c6 2065 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2066 POSTING_READ(reg);
81255565 2067
17638cd6
JB		 2068 return 0;
2069}
2070
2071static int ironlake_update_plane(struct drm_crtc *crtc,
2072 struct drm_framebuffer *fb, int x, int y)
2073{
2074 struct drm_device *dev = crtc->dev;
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077 struct intel_framebuffer *intel_fb;
2078 struct drm_i915_gem_object *obj;
2079 int plane = intel_crtc->plane;
e506a0c6 2080 unsigned long linear_offset;
17638cd6
JB		 2081 u32 dspcntr;
2082 u32 reg;
2083
2084 switch (plane) {
2085 case 0:
2086 case 1:
27f8227b 2087 case 2:
17638cd6
JB		 2088 break;
2089 default:
2090 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2091 return -EINVAL;
2092 }
2093
2094 intel_fb = to_intel_framebuffer(fb);
2095 obj = intel_fb->obj;
2096
2097 reg = DSPCNTR(plane);
2098 dspcntr = I915_READ(reg);
2099 /* Mask out pixel format bits in case we change it */
2100 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2101 switch (fb->pixel_format) {
2102 case DRM_FORMAT_C8:
17638cd6
JB		 2103 dspcntr |= DISPPLANE_8BPP;
2104 break;
57779d06
VS		 2105 case DRM_FORMAT_RGB565:
2106 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2107 break;
57779d06
VS		 2108 case DRM_FORMAT_XRGB8888:
2109 case DRM_FORMAT_ARGB8888:
2110 dspcntr |= DISPPLANE_BGRX888;
2111 break;
2112 case DRM_FORMAT_XBGR8888:
2113 case DRM_FORMAT_ABGR8888:
2114 dspcntr |= DISPPLANE_RGBX888;
2115 break;
2116 case DRM_FORMAT_XRGB2101010:
2117 case DRM_FORMAT_ARGB2101010:
2118 dspcntr |= DISPPLANE_BGRX101010;
2119 break;
2120 case DRM_FORMAT_XBGR2101010:
2121 case DRM_FORMAT_ABGR2101010:
2122 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2123 break;
2124 default:
57779d06 2125 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2126 return -EINVAL;
2127 }
2128
2129 if (obj->tiling_mode != I915_TILING_NONE)
2130 dspcntr |= DISPPLANE_TILED;
2131 else
2132 dspcntr &= ~DISPPLANE_TILED;
2133
2134 /* must disable */
2135 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2136
2137 I915_WRITE(reg, dspcntr);
2138
e506a0c6 2139 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2140 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2141 intel_gen4_compute_offset_xtiled(&x, &y,
2142 fb->bits_per_pixel / 8,
2143 fb->pitches[0]);
c2c75131 2144 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2145
e506a0c6
DV		 2146 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2147 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2148 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2149 I915_MODIFY_DISPBASE(DSPSURF(plane),
2150 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2151 if (IS_HASWELL(dev)) {
2152 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2153 } else {
2154 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2155 I915_WRITE(DSPLINOFF(plane), linear_offset);
2156 }
17638cd6
JB		 2157 POSTING_READ(reg);
2158
2159 return 0;
2160}
2161
2162/* Assume fb object is pinned & idle & fenced and just update base pointers */
2163static int
2164intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2165 int x, int y, enum mode_set_atomic state)
2166{
2167 struct drm_device *dev = crtc->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2169
6b8e6ed0
CW		 2170 if (dev_priv->display.disable_fbc)
2171 dev_priv->display.disable_fbc(dev);
3dec0095 2172 intel_increase_pllclock(crtc);
81255565 2173
6b8e6ed0 2174 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2175}
2176
14667a4b
CW		 2177static int
2178intel_finish_fb(struct drm_framebuffer *old_fb)
2179{
2180 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2181 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2182 bool was_interruptible = dev_priv->mm.interruptible;
2183 int ret;
2184
2185 wait_event(dev_priv->pending_flip_queue,
2186 atomic_read(&dev_priv->mm.wedged) ||
2187 atomic_read(&obj->pending_flip) == 0);
2188
2189 /* Big Hammer, we also need to ensure that any pending
2190 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2191 * current scanout is retired before unpinning the old
2192 * framebuffer.
2193 *
2194 * This should only fail upon a hung GPU, in which case we
2195 * can safely continue.
2196 */
2197 dev_priv->mm.interruptible = false;
2198 ret = i915_gem_object_finish_gpu(obj);
2199 dev_priv->mm.interruptible = was_interruptible;
2200
2201 return ret;
2202}
2203
198598d0
VS		 2204static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2205{
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_master_private *master_priv;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209
2210 if (!dev->primary->master)
2211 return;
2212
2213 master_priv = dev->primary->master->driver_priv;
2214 if (!master_priv->sarea_priv)
2215 return;
2216
2217 switch (intel_crtc->pipe) {
2218 case 0:
2219 master_priv->sarea_priv->pipeA_x = x;
2220 master_priv->sarea_priv->pipeA_y = y;
2221 break;
2222 case 1:
2223 master_priv->sarea_priv->pipeB_x = x;
2224 master_priv->sarea_priv->pipeB_y = y;
2225 break;
2226 default:
2227 break;
2228 }
2229}
2230
5c3b82e2 2231static int
3c4fdcfb 2232intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2233 struct drm_framebuffer *fb)
79e53945
JB		 2234{
2235 struct drm_device *dev = crtc->dev;
6b8e6ed0 2236 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2238 struct drm_framebuffer *old_fb;
5c3b82e2 2239 int ret;
79e53945
JB		 2240
2241 /* no fb bound */
94352cf9 2242 if (!fb) {
a5071c2f 2243 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2244 return 0;
2245 }
2246
5826eca5
ED		 2247 if(intel_crtc->plane > dev_priv->num_pipe) {
2248 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2249 intel_crtc->plane,
2250 dev_priv->num_pipe);
5c3b82e2 2251 return -EINVAL;
79e53945
JB		 2252 }
2253
5c3b82e2 2254 mutex_lock(&dev->struct_mutex);
265db958 2255 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2256 to_intel_framebuffer(fb)->obj,
919926ae 2257 NULL);
5c3b82e2
CW		 2258 if (ret != 0) {
2259 mutex_unlock(&dev->struct_mutex);
a5071c2f 2260 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2261 return ret;
2262 }
79e53945 2263
94352cf9
DV		 2264 if (crtc->fb)
2265 intel_finish_fb(crtc->fb);
265db958 2266
94352cf9 2267 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2268 if (ret) {
94352cf9 2269 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2270 mutex_unlock(&dev->struct_mutex);
a5071c2f 2271 DRM_ERROR("failed to update base address\n");
4e6cfefc 2272 return ret;
79e53945 2273 }
3c4fdcfb 2274
94352cf9
DV		 2275 old_fb = crtc->fb;
2276 crtc->fb = fb;
6c4c86f5
DV		 2277 crtc->x = x;
2278 crtc->y = y;
94352cf9 2279
b7f1de28
CW		 2280 if (old_fb) {
2281 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2282 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2283 }
652c393a 2284
6b8e6ed0 2285 intel_update_fbc(dev);
5c3b82e2 2286 mutex_unlock(&dev->struct_mutex);
79e53945 2287
198598d0 2288 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2289
2290 return 0;
79e53945
JB		 2291}
2292
5eddb70b 2293static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2294{
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 u32 dpa_ctl;
2298
28c97730 2299 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2300 dpa_ctl = I915_READ(DP_A);
2301 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2302
2303 if (clock < 200000) {
2304 u32 temp;
2305 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2306 /* workaround for 160Mhz:
2307 1) program 0x4600c bits 15:0 = 0x8124
2308 2) program 0x46010 bit 0 = 1
2309 3) program 0x46034 bit 24 = 1
2310 4) program 0x64000 bit 14 = 1
2311 */
2312 temp = I915_READ(0x4600c);
2313 temp &= 0xffff0000;
2314 I915_WRITE(0x4600c, temp | 0x8124);
2315
2316 temp = I915_READ(0x46010);
2317 I915_WRITE(0x46010, temp | 1);
2318
2319 temp = I915_READ(0x46034);
2320 I915_WRITE(0x46034, temp | (1 << 24));
2321 } else {
2322 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2323 }
2324 I915_WRITE(DP_A, dpa_ctl);
2325
5eddb70b 2326 POSTING_READ(DP_A);
32f9d658
ZW		 2327 udelay(500);
2328}
2329
5e84e1a4
ZW		 2330static void intel_fdi_normal_train(struct drm_crtc *crtc)
2331{
2332 struct drm_device *dev = crtc->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2335 int pipe = intel_crtc->pipe;
2336 u32 reg, temp;
2337
2338 /* enable normal train */
2339 reg = FDI_TX_CTL(pipe);
2340 temp = I915_READ(reg);
61e499bf 2341 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2342 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2343 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2344 } else {
2345 temp &= ~FDI_LINK_TRAIN_NONE;
2346 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2347 }
5e84e1a4
ZW		 2348 I915_WRITE(reg, temp);
2349
2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
2352 if (HAS_PCH_CPT(dev)) {
2353 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2354 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2355 } else {
2356 temp &= ~FDI_LINK_TRAIN_NONE;
2357 temp |= FDI_LINK_TRAIN_NONE;
2358 }
2359 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2360
2361 /* wait one idle pattern time */
2362 POSTING_READ(reg);
2363 udelay(1000);
357555c0
JB		 2364
2365 /* IVB wants error correction enabled */
2366 if (IS_IVYBRIDGE(dev))
2367 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2368 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2369}
2370
291427f5
JB		 2371static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2372{
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 u32 flags = I915_READ(SOUTH_CHICKEN1);
2375
2376 flags |= FDI_PHASE_SYNC_OVR(pipe);
2377 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2378 flags |= FDI_PHASE_SYNC_EN(pipe);
2379 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2380 POSTING_READ(SOUTH_CHICKEN1);
2381}
2382
01a415fd
DV		 2383static void ivb_modeset_global_resources(struct drm_device *dev)
2384{
2385 struct drm_i915_private *dev_priv = dev->dev_private;
2386 struct intel_crtc *pipe_B_crtc =
2387 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2388 struct intel_crtc *pipe_C_crtc =
2389 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2390 uint32_t temp;
2391
2392 /* When everything is off disable fdi C so that we could enable fdi B
2393 * with all lanes. XXX: This misses the case where a pipe is not using
2394 * any pch resources and so doesn't need any fdi lanes. */
2395 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2396 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2397 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2398
2399 temp = I915_READ(SOUTH_CHICKEN1);
2400 temp &= ~FDI_BC_BIFURCATION_SELECT;
2401 DRM_DEBUG_KMS("disabling fdi C rx\n");
2402 I915_WRITE(SOUTH_CHICKEN1, temp);
2403 }
2404}
2405
8db9d77b
ZW		 2406/* The FDI link training functions for ILK/Ibexpeak. */
2407static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2408{
2409 struct drm_device *dev = crtc->dev;
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412 int pipe = intel_crtc->pipe;
0fc932b8 2413 int plane = intel_crtc->plane;
5eddb70b 2414 u32 reg, temp, tries;
8db9d77b 2415
0fc932b8
JB		 2416 /* FDI needs bits from pipe & plane first */
2417 assert_pipe_enabled(dev_priv, pipe);
2418 assert_plane_enabled(dev_priv, plane);
2419
e1a44743
AJ		 2420 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2421 for train result */
5eddb70b
CW		 2422 reg = FDI_RX_IMR(pipe);
2423 temp = I915_READ(reg);
e1a44743
AJ		 2424 temp &= ~FDI_RX_SYMBOL_LOCK;
2425 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2426 I915_WRITE(reg, temp);
2427 I915_READ(reg);
e1a44743
AJ		 2428 udelay(150);
2429
8db9d77b 2430 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2431 reg = FDI_TX_CTL(pipe);
2432 temp = I915_READ(reg);
77ffb597
AJ		 2433 temp &= ~(7 << 19);
2434 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2435 temp &= ~FDI_LINK_TRAIN_NONE;
2436 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2437 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2438
5eddb70b
CW		 2439 reg = FDI_RX_CTL(pipe);
2440 temp = I915_READ(reg);
8db9d77b
ZW		 2441 temp &= ~FDI_LINK_TRAIN_NONE;
2442 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2443 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2444
2445 POSTING_READ(reg);
8db9d77b
ZW		 2446 udelay(150);
2447
5b2adf89 2448 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2449 if (HAS_PCH_IBX(dev)) {
2450 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2451 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2452 FDI_RX_PHASE_SYNC_POINTER_EN);
2453 }
5b2adf89 2454
5eddb70b 2455 reg = FDI_RX_IIR(pipe);
e1a44743 2456 for (tries = 0; tries < 5; tries++) {
5eddb70b 2457 temp = I915_READ(reg);
8db9d77b
ZW		 2458 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2459
2460 if ((temp & FDI_RX_BIT_LOCK)) {
2461 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2462 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2463 break;
2464 }
8db9d77b 2465 }
e1a44743 2466 if (tries == 5)
5eddb70b 2467 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2468
2469 /* Train 2 */
5eddb70b
CW		 2470 reg = FDI_TX_CTL(pipe);
2471 temp = I915_READ(reg);
8db9d77b
ZW		 2472 temp &= ~FDI_LINK_TRAIN_NONE;
2473 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2474 I915_WRITE(reg, temp);
8db9d77b 2475
5eddb70b
CW		 2476 reg = FDI_RX_CTL(pipe);
2477 temp = I915_READ(reg);
8db9d77b
ZW		 2478 temp &= ~FDI_LINK_TRAIN_NONE;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2480 I915_WRITE(reg, temp);
8db9d77b 2481
5eddb70b
CW		 2482 POSTING_READ(reg);
2483 udelay(150);
8db9d77b 2484
5eddb70b 2485 reg = FDI_RX_IIR(pipe);
e1a44743 2486 for (tries = 0; tries < 5; tries++) {
5eddb70b 2487 temp = I915_READ(reg);
8db9d77b
ZW		 2488 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2489
2490 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2491 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2492 DRM_DEBUG_KMS("FDI train 2 done.\n");
2493 break;
2494 }
8db9d77b 2495 }
e1a44743 2496 if (tries == 5)
5eddb70b 2497 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2498
2499 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2500
8db9d77b
ZW		 2501}
2502
0206e353 2503static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2504 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2505 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2506 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2507 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2508};
2509
2510/* The FDI link training functions for SNB/Cougarpoint. */
2511static void gen6_fdi_link_train(struct drm_crtc *crtc)
2512{
2513 struct drm_device *dev = crtc->dev;
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516 int pipe = intel_crtc->pipe;
fa37d39e 2517 u32 reg, temp, i, retry;
8db9d77b 2518
e1a44743
AJ		 2519 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2520 for train result */
5eddb70b
CW		 2521 reg = FDI_RX_IMR(pipe);
2522 temp = I915_READ(reg);
e1a44743
AJ		 2523 temp &= ~FDI_RX_SYMBOL_LOCK;
2524 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2525 I915_WRITE(reg, temp);
2526
2527 POSTING_READ(reg);
e1a44743
AJ		 2528 udelay(150);
2529
8db9d77b 2530 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2531 reg = FDI_TX_CTL(pipe);
2532 temp = I915_READ(reg);
77ffb597
AJ		 2533 temp &= ~(7 << 19);
2534 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1;
2537 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538 /* SNB-B */
2539 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2540 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2541
d74cf324
DV		 2542 I915_WRITE(FDI_RX_MISC(pipe),
2543 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2544
5eddb70b
CW		 2545 reg = FDI_RX_CTL(pipe);
2546 temp = I915_READ(reg);
8db9d77b
ZW		 2547 if (HAS_PCH_CPT(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2550 } else {
2551 temp &= ~FDI_LINK_TRAIN_NONE;
2552 temp |= FDI_LINK_TRAIN_PATTERN_1;
2553 }
5eddb70b
CW		 2554 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556 POSTING_READ(reg);
8db9d77b
ZW		 2557 udelay(150);
2558
291427f5
JB		 2559 if (HAS_PCH_CPT(dev))
2560 cpt_phase_pointer_enable(dev, pipe);
2561
0206e353 2562 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2563 reg = FDI_TX_CTL(pipe);
2564 temp = I915_READ(reg);
8db9d77b
ZW		 2565 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
8db9d77b
ZW		 2570 udelay(500);
2571
fa37d39e
SP		 2572 for (retry = 0; retry < 5; retry++) {
2573 reg = FDI_RX_IIR(pipe);
2574 temp = I915_READ(reg);
2575 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2576 if (temp & FDI_RX_BIT_LOCK) {
2577 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2578 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579 break;
2580 }
2581 udelay(50);
8db9d77b 2582 }
fa37d39e
SP		 2583 if (retry < 5)
2584 break;
8db9d77b
ZW		 2585 }
2586 if (i == 4)
5eddb70b 2587 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2588
2589 /* Train 2 */
5eddb70b
CW		 2590 reg = FDI_TX_CTL(pipe);
2591 temp = I915_READ(reg);
8db9d77b
ZW		 2592 temp &= ~FDI_LINK_TRAIN_NONE;
2593 temp |= FDI_LINK_TRAIN_PATTERN_2;
2594 if (IS_GEN6(dev)) {
2595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596 /* SNB-B */
2597 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2598 }
5eddb70b 2599 I915_WRITE(reg, temp);
8db9d77b 2600
5eddb70b
CW		 2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
8db9d77b
ZW		 2603 if (HAS_PCH_CPT(dev)) {
2604 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2605 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2606 } else {
2607 temp &= ~FDI_LINK_TRAIN_NONE;
2608 temp |= FDI_LINK_TRAIN_PATTERN_2;
2609 }
5eddb70b
CW		 2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
8db9d77b
ZW		 2613 udelay(150);
2614
0206e353 2615 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
8db9d77b
ZW		 2618 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2620 I915_WRITE(reg, temp);
2621
2622 POSTING_READ(reg);
8db9d77b
ZW		 2623 udelay(500);
2624
fa37d39e
SP		 2625 for (retry = 0; retry < 5; retry++) {
2626 reg = FDI_RX_IIR(pipe);
2627 temp = I915_READ(reg);
2628 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629 if (temp & FDI_RX_SYMBOL_LOCK) {
2630 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2631 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632 break;
2633 }
2634 udelay(50);
8db9d77b 2635 }
fa37d39e
SP		 2636 if (retry < 5)
2637 break;
8db9d77b
ZW		 2638 }
2639 if (i == 4)
5eddb70b 2640 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2641
2642 DRM_DEBUG_KMS("FDI train done.\n");
2643}
2644
357555c0
JB		 2645/* Manual link training for Ivy Bridge A0 parts */
2646static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2647{
2648 struct drm_device *dev = crtc->dev;
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651 int pipe = intel_crtc->pipe;
2652 u32 reg, temp, i;
2653
2654 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2655 for train result */
2656 reg = FDI_RX_IMR(pipe);
2657 temp = I915_READ(reg);
2658 temp &= ~FDI_RX_SYMBOL_LOCK;
2659 temp &= ~FDI_RX_BIT_LOCK;
2660 I915_WRITE(reg, temp);
2661
2662 POSTING_READ(reg);
2663 udelay(150);
2664
01a415fd
DV		 2665 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2666 I915_READ(FDI_RX_IIR(pipe)));
2667
357555c0
JB		 2668 /* enable CPU FDI TX and PCH FDI RX */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~(7 << 19);
2672 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2673 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2674 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2677 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2678 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2679
d74cf324
DV		 2680 I915_WRITE(FDI_RX_MISC(pipe),
2681 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2682
357555c0
JB		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_AUTO;
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2688 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2689 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2690
2691 POSTING_READ(reg);
2692 udelay(150);
2693
291427f5
JB		 2694 if (HAS_PCH_CPT(dev))
2695 cpt_phase_pointer_enable(dev, pipe);
2696
0206e353 2697 for (i = 0; i < 4; i++) {
357555c0
JB		 2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
2700 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701 temp |= snb_b_fdi_train_param[i];
2702 I915_WRITE(reg, temp);
2703
2704 POSTING_READ(reg);
2705 udelay(500);
2706
2707 reg = FDI_RX_IIR(pipe);
2708 temp = I915_READ(reg);
2709 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2710
2711 if (temp & FDI_RX_BIT_LOCK ||
2712 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2713 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2714 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2715 break;
2716 }
2717 }
2718 if (i == 4)
2719 DRM_ERROR("FDI train 1 fail!\n");
2720
2721 /* Train 2 */
2722 reg = FDI_TX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2725 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2726 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2727 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2728 I915_WRITE(reg, temp);
2729
2730 reg = FDI_RX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2733 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2734 I915_WRITE(reg, temp);
2735
2736 POSTING_READ(reg);
2737 udelay(150);
2738
0206e353 2739 for (i = 0; i < 4; i++) {
357555c0
JB		 2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743 temp |= snb_b_fdi_train_param[i];
2744 I915_WRITE(reg, temp);
2745
2746 POSTING_READ(reg);
2747 udelay(500);
2748
2749 reg = FDI_RX_IIR(pipe);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753 if (temp & FDI_RX_SYMBOL_LOCK) {
2754 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2755 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2756 break;
2757 }
2758 }
2759 if (i == 4)
2760 DRM_ERROR("FDI train 2 fail!\n");
2761
2762 DRM_DEBUG_KMS("FDI train done.\n");
2763}
2764
88cefb6c 2765static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2766{
88cefb6c 2767 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2768 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2769 int pipe = intel_crtc->pipe;
5eddb70b 2770 u32 reg, temp;
79e53945 2771
c64e311e 2772
c98e9dcf 2773 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2774 reg = FDI_RX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2777 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2778 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2779 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2780
2781 POSTING_READ(reg);
c98e9dcf
JB		 2782 udelay(200);
2783
2784 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2785 temp = I915_READ(reg);
2786 I915_WRITE(reg, temp | FDI_PCDCLK);
2787
2788 POSTING_READ(reg);
c98e9dcf
JB		 2789 udelay(200);
2790
bf507ef7
ED		 2791 /* On Haswell, the PLL configuration for ports and pipes is handled
2792 * separately, as part of DDI setup */
2793 if (!IS_HASWELL(dev)) {
2794 /* Enable CPU FDI TX PLL, always on for Ironlake */
2795 reg = FDI_TX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2798 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2799
bf507ef7
ED		 2800 POSTING_READ(reg);
2801 udelay(100);
2802 }
6be4a607 2803 }
0e23b99d
JB		 2804}
2805
88cefb6c
DV		 2806static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2807{
2808 struct drm_device *dev = intel_crtc->base.dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 int pipe = intel_crtc->pipe;
2811 u32 reg, temp;
2812
2813 /* Switch from PCDclk to Rawclk */
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2817
2818 /* Disable CPU FDI TX PLL */
2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2822
2823 POSTING_READ(reg);
2824 udelay(100);
2825
2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2829
2830 /* Wait for the clocks to turn off. */
2831 POSTING_READ(reg);
2832 udelay(100);
2833}
2834
291427f5
JB		 2835static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2836{
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 u32 flags = I915_READ(SOUTH_CHICKEN1);
2839
2840 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2841 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2842 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2843 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2844 POSTING_READ(SOUTH_CHICKEN1);
2845}
0fc932b8
JB		 2846static void ironlake_fdi_disable(struct drm_crtc *crtc)
2847{
2848 struct drm_device *dev = crtc->dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2851 int pipe = intel_crtc->pipe;
2852 u32 reg, temp;
2853
2854 /* disable CPU FDI tx and PCH FDI rx */
2855 reg = FDI_TX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2858 POSTING_READ(reg);
2859
2860 reg = FDI_RX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 temp &= ~(0x7 << 16);
2863 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2864 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2865
2866 POSTING_READ(reg);
2867 udelay(100);
2868
2869 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2870 if (HAS_PCH_IBX(dev)) {
2871 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2872 I915_WRITE(FDI_RX_CHICKEN(pipe),
2873 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2874 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2875 } else if (HAS_PCH_CPT(dev)) {
2876 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2877 }
0fc932b8
JB		 2878
2879 /* still set train pattern 1 */
2880 reg = FDI_TX_CTL(pipe);
2881 temp = I915_READ(reg);
2882 temp &= ~FDI_LINK_TRAIN_NONE;
2883 temp |= FDI_LINK_TRAIN_PATTERN_1;
2884 I915_WRITE(reg, temp);
2885
2886 reg = FDI_RX_CTL(pipe);
2887 temp = I915_READ(reg);
2888 if (HAS_PCH_CPT(dev)) {
2889 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2890 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2891 } else {
2892 temp &= ~FDI_LINK_TRAIN_NONE;
2893 temp |= FDI_LINK_TRAIN_PATTERN_1;
2894 }
2895 /* BPC in FDI rx is consistent with that in PIPECONF */
2896 temp &= ~(0x07 << 16);
2897 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2898 I915_WRITE(reg, temp);
2899
2900 POSTING_READ(reg);
2901 udelay(100);
2902}
2903
5bb61643
CW		 2904static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2905{
2906 struct drm_device *dev = crtc->dev;
2907 struct drm_i915_private *dev_priv = dev->dev_private;
2908 unsigned long flags;
2909 bool pending;
2910
2911 if (atomic_read(&dev_priv->mm.wedged))
2912 return false;
2913
2914 spin_lock_irqsave(&dev->event_lock, flags);
2915 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2916 spin_unlock_irqrestore(&dev->event_lock, flags);
2917
2918 return pending;
2919}
2920
e6c3a2a6
CW		 2921static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2922{
0f91128d 2923 struct drm_device *dev = crtc->dev;
5bb61643 2924 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2925
2926 if (crtc->fb == NULL)
2927 return;
2928
5bb61643
CW		 2929 wait_event(dev_priv->pending_flip_queue,
2930 !intel_crtc_has_pending_flip(crtc));
2931
0f91128d
CW		 2932 mutex_lock(&dev->struct_mutex);
2933 intel_finish_fb(crtc->fb);
2934 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2935}
2936
fc316cbe 2937static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2938{
2939 struct drm_device *dev = crtc->dev;
228d3e36 2940 struct intel_encoder *intel_encoder;
040484af
JB		 2941
2942 /*
2943 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2944 * must be driven by its own crtc; no sharing is possible.
2945 */
228d3e36 2946 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2947 switch (intel_encoder->type) {
040484af 2948 case INTEL_OUTPUT_EDP:
228d3e36 2949 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2950 return false;
2951 continue;
2952 }
2953 }
2954
2955 return true;
2956}
2957
fc316cbe
PZ		 2958static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2959{
2960 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2961}
2962
e615efe4
ED		 2963/* Program iCLKIP clock to the desired frequency */
2964static void lpt_program_iclkip(struct drm_crtc *crtc)
2965{
2966 struct drm_device *dev = crtc->dev;
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2969 u32 temp;
2970
2971 /* It is necessary to ungate the pixclk gate prior to programming
2972 * the divisors, and gate it back when it is done.
2973 */
2974 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2975
2976 /* Disable SSCCTL */
2977 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2978 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2979 SBI_SSCCTL_DISABLE);
2980
2981 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2982 if (crtc->mode.clock == 20000) {
2983 auxdiv = 1;
2984 divsel = 0x41;
2985 phaseinc = 0x20;
2986 } else {
2987 /* The iCLK virtual clock root frequency is in MHz,
2988 * but the crtc->mode.clock in in KHz. To get the divisors,
2989 * it is necessary to divide one by another, so we
2990 * convert the virtual clock precision to KHz here for higher
2991 * precision.
2992 */
2993 u32 iclk_virtual_root_freq = 172800 * 1000;
2994 u32 iclk_pi_range = 64;
2995 u32 desired_divisor, msb_divisor_value, pi_value;
2996
2997 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2998 msb_divisor_value = desired_divisor / iclk_pi_range;
2999 pi_value = desired_divisor % iclk_pi_range;
3000
3001 auxdiv = 0;
3002 divsel = msb_divisor_value - 2;
3003 phaseinc = pi_value;
3004 }
3005
3006 /* This should not happen with any sane values */
3007 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3008 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3009 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3010 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3011
3012 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3013 crtc->mode.clock,
3014 auxdiv,
3015 divsel,
3016 phasedir,
3017 phaseinc);
3018
3019 /* Program SSCDIVINTPHASE6 */
3020 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3021 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3022 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3023 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3024 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3025 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3026 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3027
3028 intel_sbi_write(dev_priv,
3029 SBI_SSCDIVINTPHASE6,
3030 temp);
3031
3032 /* Program SSCAUXDIV */
3033 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3034 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3035 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3036 intel_sbi_write(dev_priv,
3037 SBI_SSCAUXDIV6,
3038 temp);
3039
3040
3041 /* Enable modulator and associated divider */
3042 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3043 temp &= ~SBI_SSCCTL_DISABLE;
3044 intel_sbi_write(dev_priv,
3045 SBI_SSCCTL6,
3046 temp);
3047
3048 /* Wait for initialization time */
3049 udelay(24);
3050
3051 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3052}
3053
f67a559d
JB		 3054/*
3055 * Enable PCH resources required for PCH ports:
3056 * - PCH PLLs
3057 * - FDI training & RX/TX
3058 * - update transcoder timings
3059 * - DP transcoding bits
3060 * - transcoder
3061 */
3062static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3063{
3064 struct drm_device *dev = crtc->dev;
3065 struct drm_i915_private *dev_priv = dev->dev_private;
3066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067 int pipe = intel_crtc->pipe;
ee7b9f93 3068 u32 reg, temp;
2c07245f 3069
e7e164db
CW		 3070 assert_transcoder_disabled(dev_priv, pipe);
3071
cd986abb
DV		 3072 /* Write the TU size bits before fdi link training, so that error
3073 * detection works. */
3074 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3075 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3076
c98e9dcf 3077 /* For PCH output, training FDI link */
674cf967 3078 dev_priv->display.fdi_link_train(crtc);
2c07245f 3079
572deb37
DV		 3080 /* XXX: pch pll's can be enabled any time before we enable the PCH
3081 * transcoder, and we actually should do this to not upset any PCH
3082 * transcoder that already use the clock when we share it.
3083 *
3084 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3085 * unconditionally resets the pll - we need that to have the right LVDS
3086 * enable sequence. */
b6b4e185 3087 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3088
303b81e0 3089 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3090 u32 sel;
4b645f14 3091
c98e9dcf 3092 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3093 switch (pipe) {
3094 default:
3095 case 0:
3096 temp |= TRANSA_DPLL_ENABLE;
3097 sel = TRANSA_DPLLB_SEL;
3098 break;
3099 case 1:
3100 temp |= TRANSB_DPLL_ENABLE;
3101 sel = TRANSB_DPLLB_SEL;
3102 break;
3103 case 2:
3104 temp |= TRANSC_DPLL_ENABLE;
3105 sel = TRANSC_DPLLB_SEL;
3106 break;
d64311ab 3107 }
ee7b9f93
JB		 3108 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3109 temp |= sel;
3110 else
3111 temp &= ~sel;
c98e9dcf 3112 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3113 }
5eddb70b 3114
d9b6cb56
JB		 3115 /* set transcoder timing, panel must allow it */
3116 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3117 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3118 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3119 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3120
5eddb70b
CW		 3121 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3122 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3123 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3124 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3125
303b81e0 3126 intel_fdi_normal_train(crtc);
5e84e1a4 3127
c98e9dcf
JB		 3128 /* For PCH DP, enable TRANS_DP_CTL */
3129 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3130 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3131 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3132 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3133 reg = TRANS_DP_CTL(pipe);
3134 temp = I915_READ(reg);
3135 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3136 TRANS_DP_SYNC_MASK |
3137 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3138 temp |= (TRANS_DP_OUTPUT_ENABLE |
3139 TRANS_DP_ENH_FRAMING);
9325c9f0 3140 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3141
3142 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3143 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3144 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3145 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3146
3147 switch (intel_trans_dp_port_sel(crtc)) {
3148 case PCH_DP_B:
5eddb70b 3149 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3150 break;
3151 case PCH_DP_C:
5eddb70b 3152 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3153 break;
3154 case PCH_DP_D:
5eddb70b 3155 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3156 break;
3157 default:
e95d41e1 3158 BUG();
32f9d658 3159 }
2c07245f 3160
5eddb70b 3161 I915_WRITE(reg, temp);
6be4a607 3162 }
b52eb4dc 3163
b8a4f404 3164 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3165}
3166
1507e5bd
PZ		 3167static void lpt_pch_enable(struct drm_crtc *crtc)
3168{
3169 struct drm_device *dev = crtc->dev;
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172 int pipe = intel_crtc->pipe;
daed2dbb 3173 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3174
daed2dbb 3175 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd
PZ		 3176
3177 /* Write the TU size bits before fdi link training, so that error
3178 * detection works. */
3179 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3180 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3181
3182 /* For PCH output, training FDI link */
3183 dev_priv->display.fdi_link_train(crtc);
3184
8c52b5e8 3185 lpt_program_iclkip(crtc);
1507e5bd 3186
0540e488 3187 /* Set transcoder timing. */
daed2dbb
PZ		 3188 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3189 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3190 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3191
daed2dbb
PZ		 3192 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3193 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3194 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3195 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3196
b8a4f404 3197 ironlake_enable_pch_transcoder(dev_priv, intel_crtc->pipe);
1507e5bd
PZ		 3198}
3199
ee7b9f93
JB		 3200static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3201{
3202 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3203
3204 if (pll == NULL)
3205 return;
3206
3207 if (pll->refcount == 0) {
3208 WARN(1, "bad PCH PLL refcount\n");
3209 return;
3210 }
3211
3212 --pll->refcount;
3213 intel_crtc->pch_pll = NULL;
3214}
3215
3216static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3217{
3218 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3219 struct intel_pch_pll *pll;
3220 int i;
3221
3222 pll = intel_crtc->pch_pll;
3223 if (pll) {
3224 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3225 intel_crtc->base.base.id, pll->pll_reg);
3226 goto prepare;
3227 }
3228
98b6bd99
DV		 3229 if (HAS_PCH_IBX(dev_priv->dev)) {
3230 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3231 i = intel_crtc->pipe;
3232 pll = &dev_priv->pch_plls[i];
3233
3234 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3235 intel_crtc->base.base.id, pll->pll_reg);
3236
3237 goto found;
3238 }
3239
ee7b9f93
JB		 3240 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3241 pll = &dev_priv->pch_plls[i];
3242
3243 /* Only want to check enabled timings first */
3244 if (pll->refcount == 0)
3245 continue;
3246
3247 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3248 fp == I915_READ(pll->fp0_reg)) {
3249 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3250 intel_crtc->base.base.id,
3251 pll->pll_reg, pll->refcount, pll->active);
3252
3253 goto found;
3254 }
3255 }
3256
3257 /* Ok no matching timings, maybe there's a free one? */
3258 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3259 pll = &dev_priv->pch_plls[i];
3260 if (pll->refcount == 0) {
3261 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3262 intel_crtc->base.base.id, pll->pll_reg);
3263 goto found;
3264 }
3265 }
3266
3267 return NULL;
3268
3269found:
3270 intel_crtc->pch_pll = pll;
3271 pll->refcount++;
3272 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3273prepare: /* separate function? */
3274 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3275
e04c7350
CW		 3276 /* Wait for the clocks to stabilize before rewriting the regs */
3277 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3278 POSTING_READ(pll->pll_reg);
3279 udelay(150);
e04c7350
CW		 3280
3281 I915_WRITE(pll->fp0_reg, fp);
3282 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3283 pll->on = false;
3284 return pll;
3285}
3286
d4270e57
JB		 3287void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3288{
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3291 u32 temp;
3292
3293 temp = I915_READ(dslreg);
3294 udelay(500);
3295 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3296 /* Without this, mode sets may fail silently on FDI */
3297 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3298 udelay(250);
3299 I915_WRITE(tc2reg, 0);
3300 if (wait_for(I915_READ(dslreg) != temp, 5))
3301 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3302 }
3303}
3304
f67a559d
JB		 3305static void ironlake_crtc_enable(struct drm_crtc *crtc)
3306{
3307 struct drm_device *dev = crtc->dev;
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3310 struct intel_encoder *encoder;
f67a559d
JB		 3311 int pipe = intel_crtc->pipe;
3312 int plane = intel_crtc->plane;
3313 u32 temp;
3314 bool is_pch_port;
3315
08a48469
DV		 3316 WARN_ON(!crtc->enabled);
3317
f67a559d
JB		 3318 if (intel_crtc->active)
3319 return;
3320
3321 intel_crtc->active = true;
3322 intel_update_watermarks(dev);
3323
3324 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3325 temp = I915_READ(PCH_LVDS);
3326 if ((temp & LVDS_PORT_EN) == 0)
3327 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3328 }
3329
fc316cbe 3330 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3331
46b6f814 3332 if (is_pch_port) {
fff367c7
DV		 3333 /* Note: FDI PLL enabling _must_ be done before we enable the
3334 * cpu pipes, hence this is separate from all the other fdi/pch
3335 * enabling. */
88cefb6c 3336 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3337 } else {
3338 assert_fdi_tx_disabled(dev_priv, pipe);
3339 assert_fdi_rx_disabled(dev_priv, pipe);
3340 }
f67a559d 3341
bf49ec8c
DV		 3342 for_each_encoder_on_crtc(dev, crtc, encoder)
3343 if (encoder->pre_enable)
3344 encoder->pre_enable(encoder);
3345
f67a559d
JB		 3346 /* Enable panel fitting for LVDS */
3347 if (dev_priv->pch_pf_size &&
3348 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3349 /* Force use of hard-coded filter coefficients
3350 * as some pre-programmed values are broken,
3351 * e.g. x201.
3352 */
9db4a9c7
JB		 3353 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3354 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3355 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3356 }
3357
9c54c0dd
JB		 3358 /*
3359 * On ILK+ LUT must be loaded before the pipe is running but with
3360 * clocks enabled
3361 */
3362 intel_crtc_load_lut(crtc);
3363
f67a559d
JB		 3364 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3365 intel_enable_plane(dev_priv, plane, pipe);
3366
3367 if (is_pch_port)
3368 ironlake_pch_enable(crtc);
c98e9dcf 3369
d1ebd816 3370 mutex_lock(&dev->struct_mutex);
bed4a673 3371 intel_update_fbc(dev);
d1ebd816
BW		 3372 mutex_unlock(&dev->struct_mutex);
3373
6b383a7f 3374 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3375
fa5c73b1
DV		 3376 for_each_encoder_on_crtc(dev, crtc, encoder)
3377 encoder->enable(encoder);
61b77ddd
DV		 3378
3379 if (HAS_PCH_CPT(dev))
3380 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3381
3382 /*
3383 * There seems to be a race in PCH platform hw (at least on some
3384 * outputs) where an enabled pipe still completes any pageflip right
3385 * away (as if the pipe is off) instead of waiting for vblank. As soon
3386 * as the first vblank happend, everything works as expected. Hence just
3387 * wait for one vblank before returning to avoid strange things
3388 * happening.
3389 */
3390 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3391}
3392
4f771f10
PZ		 3393static void haswell_crtc_enable(struct drm_crtc *crtc)
3394{
3395 struct drm_device *dev = crtc->dev;
3396 struct drm_i915_private *dev_priv = dev->dev_private;
3397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3398 struct intel_encoder *encoder;
3399 int pipe = intel_crtc->pipe;
3400 int plane = intel_crtc->plane;
4f771f10
PZ		 3401 bool is_pch_port;
3402
3403 WARN_ON(!crtc->enabled);
3404
3405 if (intel_crtc->active)
3406 return;
3407
3408 intel_crtc->active = true;
3409 intel_update_watermarks(dev);
3410
fc316cbe 3411 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3412
83616634 3413 if (is_pch_port)
4f771f10 3414 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3415
3416 for_each_encoder_on_crtc(dev, crtc, encoder)
3417 if (encoder->pre_enable)
3418 encoder->pre_enable(encoder);
3419
1f544388 3420 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3421
1f544388
PZ		 3422 /* Enable panel fitting for eDP */
3423 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3424 /* Force use of hard-coded filter coefficients
3425 * as some pre-programmed values are broken,
3426 * e.g. x201.
3427 */
3428 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3429 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3430 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3431 }
3432
3433 /*
3434 * On ILK+ LUT must be loaded before the pipe is running but with
3435 * clocks enabled
3436 */
3437 intel_crtc_load_lut(crtc);
3438
1f544388
PZ		 3439 intel_ddi_set_pipe_settings(crtc);
3440 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3441
3442 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3443 intel_enable_plane(dev_priv, plane, pipe);
3444
3445 if (is_pch_port)
1507e5bd 3446 lpt_pch_enable(crtc);
4f771f10
PZ		 3447
3448 mutex_lock(&dev->struct_mutex);
3449 intel_update_fbc(dev);
3450 mutex_unlock(&dev->struct_mutex);
3451
3452 intel_crtc_update_cursor(crtc, true);
3453
3454 for_each_encoder_on_crtc(dev, crtc, encoder)
3455 encoder->enable(encoder);
3456
4f771f10
PZ		 3457 /*
3458 * There seems to be a race in PCH platform hw (at least on some
3459 * outputs) where an enabled pipe still completes any pageflip right
3460 * away (as if the pipe is off) instead of waiting for vblank. As soon
3461 * as the first vblank happend, everything works as expected. Hence just
3462 * wait for one vblank before returning to avoid strange things
3463 * happening.
3464 */
3465 intel_wait_for_vblank(dev, intel_crtc->pipe);
3466}
3467
6be4a607
JB		 3468static void ironlake_crtc_disable(struct drm_crtc *crtc)
3469{
3470 struct drm_device *dev = crtc->dev;
3471 struct drm_i915_private *dev_priv = dev->dev_private;
3472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3473 struct intel_encoder *encoder;
6be4a607
JB		 3474 int pipe = intel_crtc->pipe;
3475 int plane = intel_crtc->plane;
5eddb70b 3476 u32 reg, temp;
b52eb4dc 3477
ef9c3aee 3478
f7abfe8b
CW		 3479 if (!intel_crtc->active)
3480 return;
3481
ea9d758d
DV		 3482 for_each_encoder_on_crtc(dev, crtc, encoder)
3483 encoder->disable(encoder);
3484
e6c3a2a6 3485 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3486 drm_vblank_off(dev, pipe);
6b383a7f 3487 intel_crtc_update_cursor(crtc, false);
5eddb70b 3488
b24e7179 3489 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3490
973d04f9
CW		 3491 if (dev_priv->cfb_plane == plane)
3492 intel_disable_fbc(dev);
2c07245f 3493
b24e7179 3494 intel_disable_pipe(dev_priv, pipe);
32f9d658 3495
6be4a607 3496 /* Disable PF */
9db4a9c7
JB		 3497 I915_WRITE(PF_CTL(pipe), 0);
3498 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3499
bf49ec8c
DV		 3500 for_each_encoder_on_crtc(dev, crtc, encoder)
3501 if (encoder->post_disable)
3502 encoder->post_disable(encoder);
3503
0fc932b8 3504 ironlake_fdi_disable(crtc);
2c07245f 3505
b8a4f404 3506 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3507
6be4a607
JB		 3508 if (HAS_PCH_CPT(dev)) {
3509 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3510 reg = TRANS_DP_CTL(pipe);
3511 temp = I915_READ(reg);
3512 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3513 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3514 I915_WRITE(reg, temp);
6be4a607
JB		 3515
3516 /* disable DPLL_SEL */
3517 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3518 switch (pipe) {
3519 case 0:
d64311ab 3520 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3521 break;
3522 case 1:
6be4a607 3523 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3524 break;
3525 case 2:
4b645f14 3526 /* C shares PLL A or B */
d64311ab 3527 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3528 break;
3529 default:
3530 BUG(); /* wtf */
3531 }
6be4a607 3532 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3533 }
e3421a18 3534
6be4a607 3535 /* disable PCH DPLL */
ee7b9f93 3536 intel_disable_pch_pll(intel_crtc);
8db9d77b 3537
88cefb6c 3538 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3539
f7abfe8b 3540 intel_crtc->active = false;
6b383a7f 3541 intel_update_watermarks(dev);
d1ebd816
BW		 3542
3543 mutex_lock(&dev->struct_mutex);
6b383a7f 3544 intel_update_fbc(dev);
d1ebd816 3545 mutex_unlock(&dev->struct_mutex);
6be4a607 3546}
1b3c7a47 3547
4f771f10
PZ		 3548static void haswell_crtc_disable(struct drm_crtc *crtc)
3549{
3550 struct drm_device *dev = crtc->dev;
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553 struct intel_encoder *encoder;
3554 int pipe = intel_crtc->pipe;
3555 int plane = intel_crtc->plane;
ad80a810 3556 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3557 bool is_pch_port;
4f771f10
PZ		 3558
3559 if (!intel_crtc->active)
3560 return;
3561
83616634
PZ		 3562 is_pch_port = haswell_crtc_driving_pch(crtc);
3563
4f771f10
PZ		 3564 for_each_encoder_on_crtc(dev, crtc, encoder)
3565 encoder->disable(encoder);
3566
3567 intel_crtc_wait_for_pending_flips(crtc);
3568 drm_vblank_off(dev, pipe);
3569 intel_crtc_update_cursor(crtc, false);
3570
3571 intel_disable_plane(dev_priv, plane, pipe);
3572
3573 if (dev_priv->cfb_plane == plane)
3574 intel_disable_fbc(dev);
3575
3576 intel_disable_pipe(dev_priv, pipe);
3577
ad80a810 3578 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3579
3580 /* Disable PF */
3581 I915_WRITE(PF_CTL(pipe), 0);
3582 I915_WRITE(PF_WIN_SZ(pipe), 0);
3583
1f544388 3584 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3585
3586 for_each_encoder_on_crtc(dev, crtc, encoder)
3587 if (encoder->post_disable)
3588 encoder->post_disable(encoder);
3589
83616634
PZ		 3590 if (is_pch_port) {
3591 ironlake_fdi_disable(crtc);
b8a4f404 3592 ironlake_disable_pch_transcoder(dev_priv, pipe);
83616634
PZ		 3593 intel_disable_pch_pll(intel_crtc);
3594 ironlake_fdi_pll_disable(intel_crtc);
3595 }
4f771f10
PZ		 3596
3597 intel_crtc->active = false;
3598 intel_update_watermarks(dev);
3599
3600 mutex_lock(&dev->struct_mutex);
3601 intel_update_fbc(dev);
3602 mutex_unlock(&dev->struct_mutex);
3603}
3604
ee7b9f93
JB		 3605static void ironlake_crtc_off(struct drm_crtc *crtc)
3606{
3607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3608 intel_put_pch_pll(intel_crtc);
3609}
3610
6441ab5f
PZ		 3611static void haswell_crtc_off(struct drm_crtc *crtc)
3612{
a5c961d1
PZ		 3613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614
3615 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3616 * start using it. */
3617 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3618
6441ab5f
PZ		 3619 intel_ddi_put_crtc_pll(crtc);
3620}
3621
02e792fb
DV		 3622static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3623{
02e792fb 3624 if (!enable && intel_crtc->overlay) {
23f09ce3 3625 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3626 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3627
23f09ce3 3628 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3629 dev_priv->mm.interruptible = false;
3630 (void) intel_overlay_switch_off(intel_crtc->overlay);
3631 dev_priv->mm.interruptible = true;
23f09ce3 3632 mutex_unlock(&dev->struct_mutex);
02e792fb 3633 }
02e792fb 3634
5dcdbcb0
CW		 3635 /* Let userspace switch the overlay on again. In most cases userspace
3636 * has to recompute where to put it anyway.
3637 */
02e792fb
DV		 3638}
3639
0b8765c6 3640static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3641{
3642 struct drm_device *dev = crtc->dev;
79e53945
JB		 3643 struct drm_i915_private *dev_priv = dev->dev_private;
3644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3645 struct intel_encoder *encoder;
79e53945 3646 int pipe = intel_crtc->pipe;
80824003 3647 int plane = intel_crtc->plane;
79e53945 3648
08a48469
DV		 3649 WARN_ON(!crtc->enabled);
3650
f7abfe8b
CW		 3651 if (intel_crtc->active)
3652 return;
3653
3654 intel_crtc->active = true;
6b383a7f
CW		 3655 intel_update_watermarks(dev);
3656
63d7bbe9 3657 intel_enable_pll(dev_priv, pipe);
040484af 3658 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3659 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3660
0b8765c6 3661 intel_crtc_load_lut(crtc);
bed4a673 3662 intel_update_fbc(dev);
79e53945 3663
0b8765c6
JB		 3664 /* Give the overlay scaler a chance to enable if it's on this pipe */
3665 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3666 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3667
fa5c73b1
DV		 3668 for_each_encoder_on_crtc(dev, crtc, encoder)
3669 encoder->enable(encoder);
0b8765c6 3670}
79e53945 3671
0b8765c6
JB		 3672static void i9xx_crtc_disable(struct drm_crtc *crtc)
3673{
3674 struct drm_device *dev = crtc->dev;
3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3677 struct intel_encoder *encoder;
0b8765c6
JB		 3678 int pipe = intel_crtc->pipe;
3679 int plane = intel_crtc->plane;
b690e96c 3680
ef9c3aee 3681
f7abfe8b
CW		 3682 if (!intel_crtc->active)
3683 return;
3684
ea9d758d
DV		 3685 for_each_encoder_on_crtc(dev, crtc, encoder)
3686 encoder->disable(encoder);
3687
0b8765c6 3688 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3689 intel_crtc_wait_for_pending_flips(crtc);
3690 drm_vblank_off(dev, pipe);
0b8765c6 3691 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3692 intel_crtc_update_cursor(crtc, false);
0b8765c6 3693
973d04f9
CW		 3694 if (dev_priv->cfb_plane == plane)
3695 intel_disable_fbc(dev);
79e53945 3696
b24e7179 3697 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3698 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3699 intel_disable_pll(dev_priv, pipe);
0b8765c6 3700
f7abfe8b 3701 intel_crtc->active = false;
6b383a7f
CW		 3702 intel_update_fbc(dev);
3703 intel_update_watermarks(dev);
0b8765c6
JB		 3704}
3705
ee7b9f93
JB		 3706static void i9xx_crtc_off(struct drm_crtc *crtc)
3707{
3708}
3709
976f8a20
DV		 3710static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3711 bool enabled)
2c07245f
ZW		 3712{
3713 struct drm_device *dev = crtc->dev;
3714 struct drm_i915_master_private *master_priv;
3715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3716 int pipe = intel_crtc->pipe;
79e53945
JB		 3717
3718 if (!dev->primary->master)
3719 return;
3720
3721 master_priv = dev->primary->master->driver_priv;
3722 if (!master_priv->sarea_priv)
3723 return;
3724
79e53945
JB		 3725 switch (pipe) {
3726 case 0:
3727 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3728 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3729 break;
3730 case 1:
3731 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3732 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3733 break;
3734 default:
9db4a9c7 3735 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3736 break;
3737 }
79e53945
JB		 3738}
3739
976f8a20
DV		 3740/**
3741 * Sets the power management mode of the pipe and plane.
3742 */
3743void intel_crtc_update_dpms(struct drm_crtc *crtc)
3744{
3745 struct drm_device *dev = crtc->dev;
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747 struct intel_encoder *intel_encoder;
3748 bool enable = false;
3749
3750 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3751 enable |= intel_encoder->connectors_active;
3752
3753 if (enable)
3754 dev_priv->display.crtc_enable(crtc);
3755 else
3756 dev_priv->display.crtc_disable(crtc);
3757
3758 intel_crtc_update_sarea(crtc, enable);
3759}
3760
3761static void intel_crtc_noop(struct drm_crtc *crtc)
3762{
3763}
3764
cdd59983
CW		 3765static void intel_crtc_disable(struct drm_crtc *crtc)
3766{
cdd59983 3767 struct drm_device *dev = crtc->dev;
976f8a20 3768 struct drm_connector *connector;
ee7b9f93 3769 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3770
976f8a20
DV		 3771 /* crtc should still be enabled when we disable it. */
3772 WARN_ON(!crtc->enabled);
3773
3774 dev_priv->display.crtc_disable(crtc);
3775 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3776 dev_priv->display.off(crtc);
3777
931872fc
CW		 3778 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3779 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3780
3781 if (crtc->fb) {
3782 mutex_lock(&dev->struct_mutex);
1690e1eb 3783 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3784 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3785 crtc->fb = NULL;
3786 }
3787
3788 /* Update computed state. */
3789 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3790 if (!connector->encoder || !connector->encoder->crtc)
3791 continue;
3792
3793 if (connector->encoder->crtc != crtc)
3794 continue;
3795
3796 connector->dpms = DRM_MODE_DPMS_OFF;
3797 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3798 }
3799}
3800
a261b246 3801void intel_modeset_disable(struct drm_device *dev)
79e53945 3802{
a261b246
DV		 3803 struct drm_crtc *crtc;
3804
3805 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3806 if (crtc->enabled)
3807 intel_crtc_disable(crtc);
3808 }
79e53945
JB		 3809}
3810
1f703855 3811void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3812{
7e7d76c3
JB		 3813}
3814
ea5b213a 3815void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3816{
4ef69c7a 3817 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3818
ea5b213a
CW		 3819 drm_encoder_cleanup(encoder);
3820 kfree(intel_encoder);
7e7d76c3
JB		 3821}
3822
5ab432ef
DV		 3823/* Simple dpms helper for encodres with just one connector, no cloning and only
3824 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3825 * state of the entire output pipe. */
3826void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3827{
5ab432ef
DV		 3828 if (mode == DRM_MODE_DPMS_ON) {
3829 encoder->connectors_active = true;
3830
b2cabb0e 3831 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3832 } else {
3833 encoder->connectors_active = false;
3834
b2cabb0e 3835 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3836 }
79e53945
JB		 3837}
3838
0a91ca29
DV		 3839/* Cross check the actual hw state with our own modeset state tracking (and it's
3840 * internal consistency). */
b980514c 3841static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3842{
0a91ca29
DV		 3843 if (connector->get_hw_state(connector)) {
3844 struct intel_encoder *encoder = connector->encoder;
3845 struct drm_crtc *crtc;
3846 bool encoder_enabled;
3847 enum pipe pipe;
3848
3849 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3850 connector->base.base.id,
3851 drm_get_connector_name(&connector->base));
3852
3853 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3854 "wrong connector dpms state\n");
3855 WARN(connector->base.encoder != &encoder->base,
3856 "active connector not linked to encoder\n");
3857 WARN(!encoder->connectors_active,
3858 "encoder->connectors_active not set\n");
3859
3860 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3861 WARN(!encoder_enabled, "encoder not enabled\n");
3862 if (WARN_ON(!encoder->base.crtc))
3863 return;
3864
3865 crtc = encoder->base.crtc;
3866
3867 WARN(!crtc->enabled, "crtc not enabled\n");
3868 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3869 WARN(pipe != to_intel_crtc(crtc)->pipe,
3870 "encoder active on the wrong pipe\n");
3871 }
79e53945
JB		 3872}
3873
5ab432ef
DV		 3874/* Even simpler default implementation, if there's really no special case to
3875 * consider. */
3876void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3877{
5ab432ef 3878 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3879
5ab432ef
DV		 3880 /* All the simple cases only support two dpms states. */
3881 if (mode != DRM_MODE_DPMS_ON)
3882 mode = DRM_MODE_DPMS_OFF;
d4270e57 3883
5ab432ef
DV		 3884 if (mode == connector->dpms)
3885 return;
3886
3887 connector->dpms = mode;
3888
3889 /* Only need to change hw state when actually enabled */
3890 if (encoder->base.crtc)
3891 intel_encoder_dpms(encoder, mode);
3892 else
8af6cf88 3893 WARN_ON(encoder->connectors_active != false);
0a91ca29 3894
b980514c 3895 intel_modeset_check_state(connector->dev);
79e53945
JB		 3896}
3897
f0947c37
DV		 3898/* Simple connector->get_hw_state implementation for encoders that support only
3899 * one connector and no cloning and hence the encoder state determines the state
3900 * of the connector. */
3901bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3902{
24929352 3903 enum pipe pipe = 0;
f0947c37 3904 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3905
f0947c37 3906 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3907}
3908
79e53945 3909static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3910 const struct drm_display_mode *mode,
79e53945
JB		 3911 struct drm_display_mode *adjusted_mode)
3912{
2c07245f 3913 struct drm_device *dev = crtc->dev;
89749350 3914
bad720ff 3915 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3916 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3917 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3918 return false;
2c07245f 3919 }
89749350 3920
f9bef081
DV		 3921 /* All interlaced capable intel hw wants timings in frames. Note though
3922 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3923 * timings, so we need to be careful not to clobber these.*/
3924 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3925 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3926
44f46b42
CW		 3927 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3928 * with a hsync front porch of 0.
3929 */
3930 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3931 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3932 return false;
3933
79e53945
JB		 3934 return true;
3935}
3936
25eb05fc
JB		 3937static int valleyview_get_display_clock_speed(struct drm_device *dev)
3938{
3939 return 400000; /* FIXME */
3940}
3941
e70236a8
JB		 3942static int i945_get_display_clock_speed(struct drm_device *dev)
3943{
3944 return 400000;
3945}
79e53945 3946
e70236a8 3947static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3948{
e70236a8
JB		 3949 return 333000;
3950}
79e53945 3951
e70236a8
JB		 3952static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3953{
3954 return 200000;
3955}
79e53945 3956
e70236a8
JB		 3957static int i915gm_get_display_clock_speed(struct drm_device *dev)
3958{
3959 u16 gcfgc = 0;
79e53945 3960
e70236a8
JB		 3961 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3962
3963 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3964 return 133000;
3965 else {
3966 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3967 case GC_DISPLAY_CLOCK_333_MHZ:
3968 return 333000;
3969 default:
3970 case GC_DISPLAY_CLOCK_190_200_MHZ:
3971 return 190000;
79e53945 3972 }
e70236a8
JB		 3973 }
3974}
3975
3976static int i865_get_display_clock_speed(struct drm_device *dev)
3977{
3978 return 266000;
3979}
3980
3981static int i855_get_display_clock_speed(struct drm_device *dev)
3982{
3983 u16 hpllcc = 0;
3984 /* Assume that the hardware is in the high speed state. This
3985 * should be the default.
3986 */
3987 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3988 case GC_CLOCK_133_200:
3989 case GC_CLOCK_100_200:
3990 return 200000;
3991 case GC_CLOCK_166_250:
3992 return 250000;
3993 case GC_CLOCK_100_133:
79e53945 3994 return 133000;
e70236a8 3995 }
79e53945 3996
e70236a8
JB		 3997 /* Shouldn't happen */
3998 return 0;
3999}
79e53945 4000
e70236a8
JB		 4001static int i830_get_display_clock_speed(struct drm_device *dev)
4002{
4003 return 133000;
79e53945
JB		 4004}
4005
2c07245f
ZW		 4006struct fdi_m_n {
4007 u32 tu;
4008 u32 gmch_m;
4009 u32 gmch_n;
4010 u32 link_m;
4011 u32 link_n;
4012};
4013
4014static void
4015fdi_reduce_ratio(u32 *num, u32 *den)
4016{
4017 while (*num > 0xffffff || *den > 0xffffff) {
4018 *num >>= 1;
4019 *den >>= 1;
4020 }
4021}
4022
2c07245f 4023static void
f2b115e6
AJ		 4024ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4025 int link_clock, struct fdi_m_n *m_n)
2c07245f 4026{
2c07245f
ZW		 4027 m_n->tu = 64; /* default size */
4028
22ed1113
CW		 4029 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4030 m_n->gmch_m = bits_per_pixel * pixel_clock;
4031 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4032 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4033
22ed1113
CW		 4034 m_n->link_m = pixel_clock;
4035 m_n->link_n = link_clock;
2c07245f
ZW		 4036 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4037}
4038
a7615030
CW		 4039static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4040{
72bbe58c
KP		 4041 if (i915_panel_use_ssc >= 0)
4042 return i915_panel_use_ssc != 0;
4043 return dev_priv->lvds_use_ssc
435793df 4044 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4045}
4046
5a354204
JB		 4047/**
4048 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4049 * @crtc: CRTC structure
3b5c78a3 4050 * @mode: requested mode
5a354204
JB		 4051 *
4052 * A pipe may be connected to one or more outputs. Based on the depth of the
4053 * attached framebuffer, choose a good color depth to use on the pipe.
4054 *
4055 * If possible, match the pipe depth to the fb depth. In some cases, this
4056 * isn't ideal, because the connected output supports a lesser or restricted
4057 * set of depths. Resolve that here:
4058 * LVDS typically supports only 6bpc, so clamp down in that case
4059 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4060 * Displays may support a restricted set as well, check EDID and clamp as
4061 * appropriate.
3b5c78a3 4062 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4063 *
4064 * RETURNS:
4065 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4066 * true if they don't match).
4067 */
4068static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4069 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4070 unsigned int *pipe_bpp,
4071 struct drm_display_mode *mode)
5a354204
JB		 4072{
4073 struct drm_device *dev = crtc->dev;
4074 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4075 struct drm_connector *connector;
6c2b7c12 4076 struct intel_encoder *intel_encoder;
5a354204
JB		 4077 unsigned int display_bpc = UINT_MAX, bpc;
4078
4079 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4080 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4081
4082 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4083 unsigned int lvds_bpc;
4084
4085 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4086 LVDS_A3_POWER_UP)
4087 lvds_bpc = 8;
4088 else
4089 lvds_bpc = 6;
4090
4091 if (lvds_bpc < display_bpc) {
82820490 4092 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4093 display_bpc = lvds_bpc;
4094 }
4095 continue;
4096 }
4097
5a354204
JB		 4098 /* Not one of the known troublemakers, check the EDID */
4099 list_for_each_entry(connector, &dev->mode_config.connector_list,
4100 head) {
6c2b7c12 4101 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4102 continue;
4103
62ac41a6
JB		 4104 /* Don't use an invalid EDID bpc value */
4105 if (connector->display_info.bpc &&
4106 connector->display_info.bpc < display_bpc) {
82820490 4107 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4108 display_bpc = connector->display_info.bpc;
4109 }
4110 }
4111
4112 /*
4113 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4114 * through, clamp it down. (Note: >12bpc will be caught below.)
4115 */
4116 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4117 if (display_bpc > 8 && display_bpc < 12) {
82820490 4118 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4119 display_bpc = 12;
4120 } else {
82820490 4121 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4122 display_bpc = 8;
4123 }
4124 }
4125 }
4126
3b5c78a3
AJ		 4127 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4128 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4129 display_bpc = 6;
4130 }
4131
5a354204
JB		 4132 /*
4133 * We could just drive the pipe at the highest bpc all the time and
4134 * enable dithering as needed, but that costs bandwidth. So choose
4135 * the minimum value that expresses the full color range of the fb but
4136 * also stays within the max display bpc discovered above.
4137 */
4138
94352cf9 4139 switch (fb->depth) {
5a354204
JB		 4140 case 8:
4141 bpc = 8; /* since we go through a colormap */
4142 break;
4143 case 15:
4144 case 16:
4145 bpc = 6; /* min is 18bpp */
4146 break;
4147 case 24:
578393cd 4148 bpc = 8;
5a354204
JB		 4149 break;
4150 case 30:
578393cd 4151 bpc = 10;
5a354204
JB		 4152 break;
4153 case 48:
578393cd 4154 bpc = 12;
5a354204
JB		 4155 break;
4156 default:
4157 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4158 bpc = min((unsigned int)8, display_bpc);
4159 break;
4160 }
4161
578393cd
KP		 4162 display_bpc = min(display_bpc, bpc);
4163
82820490
AJ		 4164 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4165 bpc, display_bpc);
5a354204 4166
578393cd 4167 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4168
4169 return display_bpc != bpc;
4170}
4171
a0c4da24
JB		 4172static int vlv_get_refclk(struct drm_crtc *crtc)
4173{
4174 struct drm_device *dev = crtc->dev;
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176 int refclk = 27000; /* for DP & HDMI */
4177
4178 return 100000; /* only one validated so far */
4179
4180 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4181 refclk = 96000;
4182 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4183 if (intel_panel_use_ssc(dev_priv))
4184 refclk = 100000;
4185 else
4186 refclk = 96000;
4187 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4188 refclk = 100000;
4189 }
4190
4191 return refclk;
4192}
4193
c65d77d8
JB		 4194static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4195{
4196 struct drm_device *dev = crtc->dev;
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4198 int refclk;
4199
a0c4da24
JB		 4200 if (IS_VALLEYVIEW(dev)) {
4201 refclk = vlv_get_refclk(crtc);
4202 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4203 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4204 refclk = dev_priv->lvds_ssc_freq * 1000;
4205 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4206 refclk / 1000);
4207 } else if (!IS_GEN2(dev)) {
4208 refclk = 96000;
4209 } else {
4210 refclk = 48000;
4211 }
4212
4213 return refclk;
4214}
4215
4216static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4217 intel_clock_t *clock)
4218{
4219 /* SDVO TV has fixed PLL values depend on its clock range,
4220 this mirrors vbios setting. */
4221 if (adjusted_mode->clock >= 100000
4222 && adjusted_mode->clock < 140500) {
4223 clock->p1 = 2;
4224 clock->p2 = 10;
4225 clock->n = 3;
4226 clock->m1 = 16;
4227 clock->m2 = 8;
4228 } else if (adjusted_mode->clock >= 140500
4229 && adjusted_mode->clock <= 200000) {
4230 clock->p1 = 1;
4231 clock->p2 = 10;
4232 clock->n = 6;
4233 clock->m1 = 12;
4234 clock->m2 = 8;
4235 }
4236}
4237
a7516a05
JB		 4238static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4239 intel_clock_t *clock,
4240 intel_clock_t *reduced_clock)
4241{
4242 struct drm_device *dev = crtc->dev;
4243 struct drm_i915_private *dev_priv = dev->dev_private;
4244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4245 int pipe = intel_crtc->pipe;
4246 u32 fp, fp2 = 0;
4247
4248 if (IS_PINEVIEW(dev)) {
4249 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4250 if (reduced_clock)
4251 fp2 = (1 << reduced_clock->n) << 16 |
4252 reduced_clock->m1 << 8 | reduced_clock->m2;
4253 } else {
4254 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4255 if (reduced_clock)
4256 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4257 reduced_clock->m2;
4258 }
4259
4260 I915_WRITE(FP0(pipe), fp);
4261
4262 intel_crtc->lowfreq_avail = false;
4263 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4264 reduced_clock && i915_powersave) {
4265 I915_WRITE(FP1(pipe), fp2);
4266 intel_crtc->lowfreq_avail = true;
4267 } else {
4268 I915_WRITE(FP1(pipe), fp);
4269 }
4270}
4271
93e537a1
DV		 4272static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4273 struct drm_display_mode *adjusted_mode)
4274{
4275 struct drm_device *dev = crtc->dev;
4276 struct drm_i915_private *dev_priv = dev->dev_private;
4277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4278 int pipe = intel_crtc->pipe;
284d5df5 4279 u32 temp;
93e537a1
DV		 4280
4281 temp = I915_READ(LVDS);
4282 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4283 if (pipe == 1) {
4284 temp |= LVDS_PIPEB_SELECT;
4285 } else {
4286 temp &= ~LVDS_PIPEB_SELECT;
4287 }
4288 /* set the corresponsding LVDS_BORDER bit */
4289 temp |= dev_priv->lvds_border_bits;
4290 /* Set the B0-B3 data pairs corresponding to whether we're going to
4291 * set the DPLLs for dual-channel mode or not.
4292 */
4293 if (clock->p2 == 7)
4294 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4295 else
4296 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4297
4298 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4299 * appropriately here, but we need to look more thoroughly into how
4300 * panels behave in the two modes.
4301 */
4302 /* set the dithering flag on LVDS as needed */
4303 if (INTEL_INFO(dev)->gen >= 4) {
4304 if (dev_priv->lvds_dither)
4305 temp |= LVDS_ENABLE_DITHER;
4306 else
4307 temp &= ~LVDS_ENABLE_DITHER;
4308 }
284d5df5 4309 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4310 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4311 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4312 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4313 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4314 I915_WRITE(LVDS, temp);
4315}
4316
a0c4da24
JB		 4317static void vlv_update_pll(struct drm_crtc *crtc,
4318 struct drm_display_mode *mode,
4319 struct drm_display_mode *adjusted_mode,
4320 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4321 int num_connectors)
a0c4da24
JB		 4322{
4323 struct drm_device *dev = crtc->dev;
4324 struct drm_i915_private *dev_priv = dev->dev_private;
4325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4326 int pipe = intel_crtc->pipe;
4327 u32 dpll, mdiv, pdiv;
4328 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4329 bool is_sdvo;
4330 u32 temp;
4331
4332 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4333 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4334
2a8f64ca
VP		 4335 dpll = DPLL_VGA_MODE_DIS;
4336 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4337 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4338 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4339
4340 I915_WRITE(DPLL(pipe), dpll);
4341 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4342
4343 bestn = clock->n;
4344 bestm1 = clock->m1;
4345 bestm2 = clock->m2;
4346 bestp1 = clock->p1;
4347 bestp2 = clock->p2;
4348
2a8f64ca
VP		 4349 /*
4350 * In Valleyview PLL and program lane counter registers are exposed
4351 * through DPIO interface
4352 */
a0c4da24
JB		 4353 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4354 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4355 mdiv |= ((bestn << DPIO_N_SHIFT));
4356 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4357 mdiv |= (1 << DPIO_K_SHIFT);
4358 mdiv |= DPIO_ENABLE_CALIBRATION;
4359 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4360
4361 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4362
2a8f64ca 4363 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4364 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4365 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4366 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4367 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4368
2a8f64ca 4369 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4370
4371 dpll |= DPLL_VCO_ENABLE;
4372 I915_WRITE(DPLL(pipe), dpll);
4373 POSTING_READ(DPLL(pipe));
4374 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4375 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4376
2a8f64ca
VP		 4377 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4378
4379 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4380 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4381
4382 I915_WRITE(DPLL(pipe), dpll);
4383
4384 /* Wait for the clocks to stabilize. */
4385 POSTING_READ(DPLL(pipe));
4386 udelay(150);
a0c4da24 4387
2a8f64ca
VP		 4388 temp = 0;
4389 if (is_sdvo) {
4390 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4391 if (temp > 1)
4392 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4393 else
4394 temp = 0;
a0c4da24 4395 }
2a8f64ca
VP		 4396 I915_WRITE(DPLL_MD(pipe), temp);
4397 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4398
2a8f64ca
VP		 4399 /* Now program lane control registers */
4400 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4401 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4402 {
4403 temp = 0x1000C4;
4404 if(pipe == 1)
4405 temp |= (1 << 21);
4406 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4407 }
4408 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4409 {
4410 temp = 0x1000C4;
4411 if(pipe == 1)
4412 temp |= (1 << 21);
4413 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4414 }
a0c4da24
JB		 4415}
4416
eb1cbe48
DV		 4417static void i9xx_update_pll(struct drm_crtc *crtc,
4418 struct drm_display_mode *mode,
4419 struct drm_display_mode *adjusted_mode,
4420 intel_clock_t *clock, intel_clock_t *reduced_clock,
4421 int num_connectors)
4422{
4423 struct drm_device *dev = crtc->dev;
4424 struct drm_i915_private *dev_priv = dev->dev_private;
4425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4426 int pipe = intel_crtc->pipe;
4427 u32 dpll;
4428 bool is_sdvo;
4429
2a8f64ca
VP		 4430 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4431
eb1cbe48
DV		 4432 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4433 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4434
4435 dpll = DPLL_VGA_MODE_DIS;
4436
4437 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4438 dpll |= DPLLB_MODE_LVDS;
4439 else
4440 dpll |= DPLLB_MODE_DAC_SERIAL;
4441 if (is_sdvo) {
4442 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4443 if (pixel_multiplier > 1) {
4444 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4445 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4446 }
4447 dpll |= DPLL_DVO_HIGH_SPEED;
4448 }
4449 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4450 dpll |= DPLL_DVO_HIGH_SPEED;
4451
4452 /* compute bitmask from p1 value */
4453 if (IS_PINEVIEW(dev))
4454 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4455 else {
4456 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4457 if (IS_G4X(dev) && reduced_clock)
4458 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4459 }
4460 switch (clock->p2) {
4461 case 5:
4462 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4463 break;
4464 case 7:
4465 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4466 break;
4467 case 10:
4468 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4469 break;
4470 case 14:
4471 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4472 break;
4473 }
4474 if (INTEL_INFO(dev)->gen >= 4)
4475 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4476
4477 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4478 dpll |= PLL_REF_INPUT_TVCLKINBC;
4479 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4480 /* XXX: just matching BIOS for now */
4481 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4482 dpll |= 3;
4483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4484 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4485 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4486 else
4487 dpll |= PLL_REF_INPUT_DREFCLK;
4488
4489 dpll |= DPLL_VCO_ENABLE;
4490 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4491 POSTING_READ(DPLL(pipe));
4492 udelay(150);
4493
4494 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4495 * This is an exception to the general rule that mode_set doesn't turn
4496 * things on.
4497 */
4498 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4499 intel_update_lvds(crtc, clock, adjusted_mode);
4500
4501 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4502 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4503
4504 I915_WRITE(DPLL(pipe), dpll);
4505
4506 /* Wait for the clocks to stabilize. */
4507 POSTING_READ(DPLL(pipe));
4508 udelay(150);
4509
4510 if (INTEL_INFO(dev)->gen >= 4) {
4511 u32 temp = 0;
4512 if (is_sdvo) {
4513 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4514 if (temp > 1)
4515 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4516 else
4517 temp = 0;
4518 }
4519 I915_WRITE(DPLL_MD(pipe), temp);
4520 } else {
4521 /* The pixel multiplier can only be updated once the
4522 * DPLL is enabled and the clocks are stable.
4523 *
4524 * So write it again.
4525 */
4526 I915_WRITE(DPLL(pipe), dpll);
4527 }
4528}
4529
4530static void i8xx_update_pll(struct drm_crtc *crtc,
4531 struct drm_display_mode *adjusted_mode,
2a8f64ca 4532 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4533 int num_connectors)
4534{
4535 struct drm_device *dev = crtc->dev;
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538 int pipe = intel_crtc->pipe;
4539 u32 dpll;
4540
2a8f64ca
VP		 4541 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4542
eb1cbe48
DV		 4543 dpll = DPLL_VGA_MODE_DIS;
4544
4545 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4546 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4547 } else {
4548 if (clock->p1 == 2)
4549 dpll |= PLL_P1_DIVIDE_BY_TWO;
4550 else
4551 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4552 if (clock->p2 == 4)
4553 dpll |= PLL_P2_DIVIDE_BY_4;
4554 }
4555
4556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4557 /* XXX: just matching BIOS for now */
4558 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4559 dpll |= 3;
4560 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4561 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4562 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4563 else
4564 dpll |= PLL_REF_INPUT_DREFCLK;
4565
4566 dpll |= DPLL_VCO_ENABLE;
4567 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4568 POSTING_READ(DPLL(pipe));
4569 udelay(150);
4570
eb1cbe48
DV		 4571 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4572 * This is an exception to the general rule that mode_set doesn't turn
4573 * things on.
4574 */
4575 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4576 intel_update_lvds(crtc, clock, adjusted_mode);
4577
5b5896e4
DV		 4578 I915_WRITE(DPLL(pipe), dpll);
4579
4580 /* Wait for the clocks to stabilize. */
4581 POSTING_READ(DPLL(pipe));
4582 udelay(150);
4583
eb1cbe48
DV		 4584 /* The pixel multiplier can only be updated once the
4585 * DPLL is enabled and the clocks are stable.
4586 *
4587 * So write it again.
4588 */
4589 I915_WRITE(DPLL(pipe), dpll);
4590}
4591
b0e77b9c
PZ		 4592static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4593 struct drm_display_mode *mode,
4594 struct drm_display_mode *adjusted_mode)
4595{
4596 struct drm_device *dev = intel_crtc->base.dev;
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4599 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4600 uint32_t vsyncshift;
4601
4602 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4603 /* the chip adds 2 halflines automatically */
4604 adjusted_mode->crtc_vtotal -= 1;
4605 adjusted_mode->crtc_vblank_end -= 1;
4606 vsyncshift = adjusted_mode->crtc_hsync_start
4607 - adjusted_mode->crtc_htotal / 2;
4608 } else {
4609 vsyncshift = 0;
4610 }
4611
4612 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4613 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4614
fe2b8f9d 4615 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4616 (adjusted_mode->crtc_hdisplay - 1) |
4617 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4618 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4619 (adjusted_mode->crtc_hblank_start - 1) |
4620 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4621 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4622 (adjusted_mode->crtc_hsync_start - 1) |
4623 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4624
fe2b8f9d 4625 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4626 (adjusted_mode->crtc_vdisplay - 1) |
4627 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4628 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4629 (adjusted_mode->crtc_vblank_start - 1) |
4630 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4631 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4632 (adjusted_mode->crtc_vsync_start - 1) |
4633 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4634
b5e508d4
PZ		 4635 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4636 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4637 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4638 * bits. */
4639 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4640 (pipe == PIPE_B || pipe == PIPE_C))
4641 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4642
b0e77b9c
PZ		 4643 /* pipesrc controls the size that is scaled from, which should
4644 * always be the user's requested size.
4645 */
4646 I915_WRITE(PIPESRC(pipe),
4647 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4648}
4649
f564048e
EA		 4650static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4651 struct drm_display_mode *mode,
4652 struct drm_display_mode *adjusted_mode,
4653 int x, int y,
94352cf9 4654 struct drm_framebuffer *fb)
79e53945
JB		 4655{
4656 struct drm_device *dev = crtc->dev;
4657 struct drm_i915_private *dev_priv = dev->dev_private;
4658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4659 int pipe = intel_crtc->pipe;
80824003 4660 int plane = intel_crtc->plane;
c751ce4f 4661 int refclk, num_connectors = 0;
652c393a 4662 intel_clock_t clock, reduced_clock;
b0e77b9c 4663 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4664 bool ok, has_reduced_clock = false, is_sdvo = false;
4665 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4666 struct intel_encoder *encoder;
d4906093 4667 const intel_limit_t *limit;
5c3b82e2 4668 int ret;
79e53945 4669
6c2b7c12 4670 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4671 switch (encoder->type) {
79e53945
JB		 4672 case INTEL_OUTPUT_LVDS:
4673 is_lvds = true;
4674 break;
4675 case INTEL_OUTPUT_SDVO:
7d57382e 4676 case INTEL_OUTPUT_HDMI:
79e53945 4677 is_sdvo = true;
5eddb70b 4678 if (encoder->needs_tv_clock)
e2f0ba97 4679 is_tv = true;
79e53945 4680 break;
79e53945
JB		 4681 case INTEL_OUTPUT_TVOUT:
4682 is_tv = true;
4683 break;
a4fc5ed6
KP		 4684 case INTEL_OUTPUT_DISPLAYPORT:
4685 is_dp = true;
4686 break;
79e53945 4687 }
43565a06 4688
c751ce4f 4689 num_connectors++;
79e53945
JB		 4690 }
4691
c65d77d8 4692 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4693
d4906093
ML		 4694 /*
4695 * Returns a set of divisors for the desired target clock with the given
4696 * refclk, or FALSE. The returned values represent the clock equation:
4697 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4698 */
1b894b59 4699 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4700 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4701 &clock);
79e53945
JB		 4702 if (!ok) {
4703 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4704 return -EINVAL;
79e53945
JB		 4705 }
4706
cda4b7d3 4707 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4708 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4709
ddc9003c 4710 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4711 /*
4712 * Ensure we match the reduced clock's P to the target clock.
4713 * If the clocks don't match, we can't switch the display clock
4714 * by using the FP0/FP1. In such case we will disable the LVDS
4715 * downclock feature.
4716 */
ddc9003c 4717 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4718 dev_priv->lvds_downclock,
4719 refclk,
cec2f356 4720 &clock,
5eddb70b 4721 &reduced_clock);
7026d4ac
ZW		 4722 }
4723
c65d77d8
JB		 4724 if (is_sdvo && is_tv)
4725 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4726
eb1cbe48 4727 if (IS_GEN2(dev))
2a8f64ca
VP		 4728 i8xx_update_pll(crtc, adjusted_mode, &clock,
4729 has_reduced_clock ? &reduced_clock : NULL,
4730 num_connectors);
a0c4da24 4731 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4732 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4733 has_reduced_clock ? &reduced_clock : NULL,
4734 num_connectors);
79e53945 4735 else
eb1cbe48
DV		 4736 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4737 has_reduced_clock ? &reduced_clock : NULL,
4738 num_connectors);
79e53945
JB		 4739
4740 /* setup pipeconf */
5eddb70b 4741 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4742
4743 /* Set up the display plane register */
4744 dspcntr = DISPPLANE_GAMMA_ENABLE;
4745
929c77fb
EA		 4746 if (pipe == 0)
4747 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4748 else
4749 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4750
a6c45cf0 4751 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4752 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4753 * core speed.
4754 *
4755 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4756 * pipe == 0 check?
4757 */
e70236a8
JB		 4758 if (mode->clock >
4759 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4760 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4761 else
5eddb70b 4762 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4763 }
4764
3b5c78a3
AJ		 4765 /* default to 8bpc */
4766 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4767 if (is_dp) {
0c96c65b 4768 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4769 pipeconf |= PIPECONF_BPP_6 |
4770 PIPECONF_DITHER_EN |
4771 PIPECONF_DITHER_TYPE_SP;
4772 }
4773 }
4774
19c03924
GB		 4775 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4776 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4777 pipeconf |= PIPECONF_BPP_6 |
4778 PIPECONF_ENABLE |
4779 I965_PIPECONF_ACTIVE;
4780 }
4781 }
4782
28c97730 4783 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4784 drm_mode_debug_printmodeline(mode);
4785
a7516a05
JB		 4786 if (HAS_PIPE_CXSR(dev)) {
4787 if (intel_crtc->lowfreq_avail) {
28c97730 4788 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4789 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4790 } else {
28c97730 4791 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4792 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4793 }
4794 }
4795
617cf884 4796 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4797 if (!IS_GEN2(dev) &&
b0e77b9c 4798 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4799 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4800 else
617cf884 4801 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4802
b0e77b9c 4803 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4804
4805 /* pipesrc and dspsize control the size that is scaled from,
4806 * which should always be the user's requested size.
79e53945 4807 */
929c77fb
EA		 4808 I915_WRITE(DSPSIZE(plane),
4809 ((mode->vdisplay - 1) << 16) |
4810 (mode->hdisplay - 1));
4811 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4812
f564048e
EA		 4813 I915_WRITE(PIPECONF(pipe), pipeconf);
4814 POSTING_READ(PIPECONF(pipe));
929c77fb 4815 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4816
4817 intel_wait_for_vblank(dev, pipe);
4818
f564048e
EA		 4819 I915_WRITE(DSPCNTR(plane), dspcntr);
4820 POSTING_READ(DSPCNTR(plane));
4821
94352cf9 4822 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4823
4824 intel_update_watermarks(dev);
4825
f564048e
EA		 4826 return ret;
4827}
4828
9fb526db
KP		 4829/*
4830 * Initialize reference clocks when the driver loads
4831 */
4832void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4833{
4834 struct drm_i915_private *dev_priv = dev->dev_private;
4835 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4836 struct intel_encoder *encoder;
13d83a67
JB		 4837 u32 temp;
4838 bool has_lvds = false;
199e5d79
KP		 4839 bool has_cpu_edp = false;
4840 bool has_pch_edp = false;
4841 bool has_panel = false;
99eb6a01
KP		 4842 bool has_ck505 = false;
4843 bool can_ssc = false;
13d83a67
JB		 4844
4845 /* We need to take the global config into account */
199e5d79
KP		 4846 list_for_each_entry(encoder, &mode_config->encoder_list,
4847 base.head) {
4848 switch (encoder->type) {
4849 case INTEL_OUTPUT_LVDS:
4850 has_panel = true;
4851 has_lvds = true;
4852 break;
4853 case INTEL_OUTPUT_EDP:
4854 has_panel = true;
4855 if (intel_encoder_is_pch_edp(&encoder->base))
4856 has_pch_edp = true;
4857 else
4858 has_cpu_edp = true;
4859 break;
13d83a67
JB		 4860 }
4861 }
4862
99eb6a01
KP		 4863 if (HAS_PCH_IBX(dev)) {
4864 has_ck505 = dev_priv->display_clock_mode;
4865 can_ssc = has_ck505;
4866 } else {
4867 has_ck505 = false;
4868 can_ssc = true;
4869 }
4870
4871 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4872 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4873 has_ck505);
13d83a67
JB		 4874
4875 /* Ironlake: try to setup display ref clock before DPLL
4876 * enabling. This is only under driver's control after
4877 * PCH B stepping, previous chipset stepping should be
4878 * ignoring this setting.
4879 */
4880 temp = I915_READ(PCH_DREF_CONTROL);
4881 /* Always enable nonspread source */
4882 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4883
99eb6a01
KP		 4884 if (has_ck505)
4885 temp |= DREF_NONSPREAD_CK505_ENABLE;
4886 else
4887 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4888
199e5d79
KP		 4889 if (has_panel) {
4890 temp &= ~DREF_SSC_SOURCE_MASK;
4891 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4892
199e5d79 4893 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4894 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4895 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4896 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4897 } else
4898 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4899
4900 /* Get SSC going before enabling the outputs */
4901 I915_WRITE(PCH_DREF_CONTROL, temp);
4902 POSTING_READ(PCH_DREF_CONTROL);
4903 udelay(200);
4904
13d83a67
JB		 4905 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4906
4907 /* Enable CPU source on CPU attached eDP */
199e5d79 4908 if (has_cpu_edp) {
99eb6a01 4909 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4910 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4911 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4912 }
13d83a67
JB		 4913 else
4914 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4915 } else
4916 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4917
4918 I915_WRITE(PCH_DREF_CONTROL, temp);
4919 POSTING_READ(PCH_DREF_CONTROL);
4920 udelay(200);
4921 } else {
4922 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4923
4924 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4925
4926 /* Turn off CPU output */
4927 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4928
4929 I915_WRITE(PCH_DREF_CONTROL, temp);
4930 POSTING_READ(PCH_DREF_CONTROL);
4931 udelay(200);
4932
4933 /* Turn off the SSC source */
4934 temp &= ~DREF_SSC_SOURCE_MASK;
4935 temp |= DREF_SSC_SOURCE_DISABLE;
4936
4937 /* Turn off SSC1 */
4938 temp &= ~ DREF_SSC1_ENABLE;
4939
13d83a67
JB		 4940 I915_WRITE(PCH_DREF_CONTROL, temp);
4941 POSTING_READ(PCH_DREF_CONTROL);
4942 udelay(200);
4943 }
4944}
4945
d9d444cb
JB		 4946static int ironlake_get_refclk(struct drm_crtc *crtc)
4947{
4948 struct drm_device *dev = crtc->dev;
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 struct intel_encoder *encoder;
d9d444cb
JB		 4951 struct intel_encoder *edp_encoder = NULL;
4952 int num_connectors = 0;
4953 bool is_lvds = false;
4954
6c2b7c12 4955 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4956 switch (encoder->type) {
4957 case INTEL_OUTPUT_LVDS:
4958 is_lvds = true;
4959 break;
4960 case INTEL_OUTPUT_EDP:
4961 edp_encoder = encoder;
4962 break;
4963 }
4964 num_connectors++;
4965 }
4966
4967 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4968 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4969 dev_priv->lvds_ssc_freq);
4970 return dev_priv->lvds_ssc_freq * 1000;
4971 }
4972
4973 return 120000;
4974}
4975
c8203565
PZ		 4976static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4977 struct drm_display_mode *adjusted_mode,
4978 bool dither)
4979{
4980 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4982 int pipe = intel_crtc->pipe;
4983 uint32_t val;
4984
4985 val = I915_READ(PIPECONF(pipe));
4986
4987 val &= ~PIPE_BPC_MASK;
4988 switch (intel_crtc->bpp) {
4989 case 18:
4990 val |= PIPE_6BPC;
4991 break;
4992 case 24:
4993 val |= PIPE_8BPC;
4994 break;
4995 case 30:
4996 val |= PIPE_10BPC;
4997 break;
4998 case 36:
4999 val |= PIPE_12BPC;
5000 break;
5001 default:
cc769b62
PZ		 5002 /* Case prevented by intel_choose_pipe_bpp_dither. */
5003 BUG();
c8203565
PZ		 5004 }
5005
5006 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5007 if (dither)
5008 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5009
5010 val &= ~PIPECONF_INTERLACE_MASK;
5011 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5012 val |= PIPECONF_INTERLACED_ILK;
5013 else
5014 val |= PIPECONF_PROGRESSIVE;
5015
5016 I915_WRITE(PIPECONF(pipe), val);
5017 POSTING_READ(PIPECONF(pipe));
5018}
5019
ee2b0b38
PZ		 5020static void haswell_set_pipeconf(struct drm_crtc *crtc,
5021 struct drm_display_mode *adjusted_mode,
5022 bool dither)
5023{
5024 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5026 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5027 uint32_t val;
5028
702e7a56 5029 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5030
5031 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5032 if (dither)
5033 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5034
5035 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5036 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5037 val |= PIPECONF_INTERLACED_ILK;
5038 else
5039 val |= PIPECONF_PROGRESSIVE;
5040
702e7a56
PZ		 5041 I915_WRITE(PIPECONF(cpu_transcoder), val);
5042 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5043}
5044
6591c6e4
PZ		 5045static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5046 struct drm_display_mode *adjusted_mode,
5047 intel_clock_t *clock,
5048 bool *has_reduced_clock,
5049 intel_clock_t *reduced_clock)
5050{
5051 struct drm_device *dev = crtc->dev;
5052 struct drm_i915_private *dev_priv = dev->dev_private;
5053 struct intel_encoder *intel_encoder;
5054 int refclk;
5055 const intel_limit_t *limit;
5056 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5057
5058 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5059 switch (intel_encoder->type) {
5060 case INTEL_OUTPUT_LVDS:
5061 is_lvds = true;
5062 break;
5063 case INTEL_OUTPUT_SDVO:
5064 case INTEL_OUTPUT_HDMI:
5065 is_sdvo = true;
5066 if (intel_encoder->needs_tv_clock)
5067 is_tv = true;
5068 break;
5069 case INTEL_OUTPUT_TVOUT:
5070 is_tv = true;
5071 break;
5072 }
5073 }
5074
5075 refclk = ironlake_get_refclk(crtc);
5076
5077 /*
5078 * Returns a set of divisors for the desired target clock with the given
5079 * refclk, or FALSE. The returned values represent the clock equation:
5080 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5081 */
5082 limit = intel_limit(crtc, refclk);
5083 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5084 clock);
5085 if (!ret)
5086 return false;
5087
5088 if (is_lvds && dev_priv->lvds_downclock_avail) {
5089 /*
5090 * Ensure we match the reduced clock's P to the target clock.
5091 * If the clocks don't match, we can't switch the display clock
5092 * by using the FP0/FP1. In such case we will disable the LVDS
5093 * downclock feature.
5094 */
5095 *has_reduced_clock = limit->find_pll(limit, crtc,
5096 dev_priv->lvds_downclock,
5097 refclk,
5098 clock,
5099 reduced_clock);
5100 }
5101
5102 if (is_sdvo && is_tv)
5103 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5104
5105 return true;
5106}
5107
01a415fd
DV		 5108static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5109{
5110 struct drm_i915_private *dev_priv = dev->dev_private;
5111 uint32_t temp;
5112
5113 temp = I915_READ(SOUTH_CHICKEN1);
5114 if (temp & FDI_BC_BIFURCATION_SELECT)
5115 return;
5116
5117 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5118 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5119
5120 temp |= FDI_BC_BIFURCATION_SELECT;
5121 DRM_DEBUG_KMS("enabling fdi C rx\n");
5122 I915_WRITE(SOUTH_CHICKEN1, temp);
5123 POSTING_READ(SOUTH_CHICKEN1);
5124}
5125
5126static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5127{
5128 struct drm_device *dev = intel_crtc->base.dev;
5129 struct drm_i915_private *dev_priv = dev->dev_private;
5130 struct intel_crtc *pipe_B_crtc =
5131 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5132
5133 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5134 intel_crtc->pipe, intel_crtc->fdi_lanes);
5135 if (intel_crtc->fdi_lanes > 4) {
5136 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5137 intel_crtc->pipe, intel_crtc->fdi_lanes);
5138 /* Clamp lanes to avoid programming the hw with bogus values. */
5139 intel_crtc->fdi_lanes = 4;
5140
5141 return false;
5142 }
5143
5144 if (dev_priv->num_pipe == 2)
5145 return true;
5146
5147 switch (intel_crtc->pipe) {
5148 case PIPE_A:
5149 return true;
5150 case PIPE_B:
5151 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5152 intel_crtc->fdi_lanes > 2) {
5153 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5154 intel_crtc->pipe, intel_crtc->fdi_lanes);
5155 /* Clamp lanes to avoid programming the hw with bogus values. */
5156 intel_crtc->fdi_lanes = 2;
5157
5158 return false;
5159 }
5160
5161 if (intel_crtc->fdi_lanes > 2)
5162 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5163 else
5164 cpt_enable_fdi_bc_bifurcation(dev);
5165
5166 return true;
5167 case PIPE_C:
5168 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5169 if (intel_crtc->fdi_lanes > 2) {
5170 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5171 intel_crtc->pipe, intel_crtc->fdi_lanes);
5172 /* Clamp lanes to avoid programming the hw with bogus values. */
5173 intel_crtc->fdi_lanes = 2;
5174
5175 return false;
5176 }
5177 } else {
5178 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5179 return false;
5180 }
5181
5182 cpt_enable_fdi_bc_bifurcation(dev);
5183
5184 return true;
5185 default:
5186 BUG();
5187 }
5188}
5189
f48d8f23
PZ		 5190static void ironlake_set_m_n(struct drm_crtc *crtc,
5191 struct drm_display_mode *mode,
5192 struct drm_display_mode *adjusted_mode)
5193{
5194 struct drm_device *dev = crtc->dev;
5195 struct drm_i915_private *dev_priv = dev->dev_private;
5196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5197 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5198 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5199 struct fdi_m_n m_n = {0};
5200 int target_clock, pixel_multiplier, lane, link_bw;
5201 bool is_dp = false, is_cpu_edp = false;
5202
5203 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5204 switch (intel_encoder->type) {
5205 case INTEL_OUTPUT_DISPLAYPORT:
5206 is_dp = true;
5207 break;
5208 case INTEL_OUTPUT_EDP:
5209 is_dp = true;
5210 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5211 is_cpu_edp = true;
5212 edp_encoder = intel_encoder;
5213 break;
5214 }
5215 }
5216
5217 /* FDI link */
5218 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5219 lane = 0;
5220 /* CPU eDP doesn't require FDI link, so just set DP M/N
5221 according to current link config */
5222 if (is_cpu_edp) {
5223 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5224 } else {
5225 /* FDI is a binary signal running at ~2.7GHz, encoding
5226 * each output octet as 10 bits. The actual frequency
5227 * is stored as a divider into a 100MHz clock, and the
5228 * mode pixel clock is stored in units of 1KHz.
5229 * Hence the bw of each lane in terms of the mode signal
5230 * is:
5231 */
5232 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5233 }
5234
5235 /* [e]DP over FDI requires target mode clock instead of link clock. */
5236 if (edp_encoder)
5237 target_clock = intel_edp_target_clock(edp_encoder, mode);
5238 else if (is_dp)
5239 target_clock = mode->clock;
5240 else
5241 target_clock = adjusted_mode->clock;
5242
5243 if (!lane) {
5244 /*
5245 * Account for spread spectrum to avoid
5246 * oversubscribing the link. Max center spread
5247 * is 2.5%; use 5% for safety's sake.
5248 */
5249 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5250 lane = bps / (link_bw * 8) + 1;
5251 }
5252
5253 intel_crtc->fdi_lanes = lane;
5254
5255 if (pixel_multiplier > 1)
5256 link_bw *= pixel_multiplier;
5257 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5258 &m_n);
5259
afe2fcf5
PZ		 5260 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5261 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5262 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5263 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5264}
5265
de13a2e3
PZ		 5266static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5267 struct drm_display_mode *adjusted_mode,
5268 intel_clock_t *clock, u32 fp)
79e53945 5269{
de13a2e3 5270 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5271 struct drm_device *dev = crtc->dev;
5272 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5273 struct intel_encoder *intel_encoder;
5274 uint32_t dpll;
5275 int factor, pixel_multiplier, num_connectors = 0;
5276 bool is_lvds = false, is_sdvo = false, is_tv = false;
5277 bool is_dp = false, is_cpu_edp = false;
79e53945 5278
de13a2e3
PZ		 5279 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5280 switch (intel_encoder->type) {
79e53945
JB		 5281 case INTEL_OUTPUT_LVDS:
5282 is_lvds = true;
5283 break;
5284 case INTEL_OUTPUT_SDVO:
7d57382e 5285 case INTEL_OUTPUT_HDMI:
79e53945 5286 is_sdvo = true;
de13a2e3 5287 if (intel_encoder->needs_tv_clock)
e2f0ba97 5288 is_tv = true;
79e53945 5289 break;
79e53945
JB		 5290 case INTEL_OUTPUT_TVOUT:
5291 is_tv = true;
5292 break;
a4fc5ed6
KP		 5293 case INTEL_OUTPUT_DISPLAYPORT:
5294 is_dp = true;
5295 break;
32f9d658 5296 case INTEL_OUTPUT_EDP:
e3aef172 5297 is_dp = true;
de13a2e3 5298 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5299 is_cpu_edp = true;
32f9d658 5300 break;
79e53945 5301 }
43565a06 5302
c751ce4f 5303 num_connectors++;
79e53945
JB		 5304 }
5305
c1858123 5306 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5307 factor = 21;
5308 if (is_lvds) {
5309 if ((intel_panel_use_ssc(dev_priv) &&
5310 dev_priv->lvds_ssc_freq == 100) ||
5311 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5312 factor = 25;
5313 } else if (is_sdvo && is_tv)
5314 factor = 20;
c1858123 5315
de13a2e3 5316 if (clock->m < factor * clock->n)
8febb297 5317 fp |= FP_CB_TUNE;
2c07245f 5318
5eddb70b 5319 dpll = 0;
2c07245f 5320
a07d6787
EA		 5321 if (is_lvds)
5322 dpll |= DPLLB_MODE_LVDS;
5323 else
5324 dpll |= DPLLB_MODE_DAC_SERIAL;
5325 if (is_sdvo) {
de13a2e3 5326 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5327 if (pixel_multiplier > 1) {
5328 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5329 }
a07d6787
EA		 5330 dpll |= DPLL_DVO_HIGH_SPEED;
5331 }
e3aef172 5332 if (is_dp && !is_cpu_edp)
a07d6787 5333 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5334
a07d6787 5335 /* compute bitmask from p1 value */
de13a2e3 5336 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5337 /* also FPA1 */
de13a2e3 5338 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5339
de13a2e3 5340 switch (clock->p2) {
a07d6787
EA		 5341 case 5:
5342 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5343 break;
5344 case 7:
5345 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5346 break;
5347 case 10:
5348 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5349 break;
5350 case 14:
5351 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5352 break;
79e53945
JB		 5353 }
5354
43565a06
KH		 5355 if (is_sdvo && is_tv)
5356 dpll |= PLL_REF_INPUT_TVCLKINBC;
5357 else if (is_tv)
79e53945 5358 /* XXX: just matching BIOS for now */
43565a06 5359 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5360 dpll |= 3;
a7615030 5361 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5362 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5363 else
5364 dpll |= PLL_REF_INPUT_DREFCLK;
5365
de13a2e3
PZ		 5366 return dpll;
5367}
5368
5369static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5370 struct drm_display_mode *mode,
5371 struct drm_display_mode *adjusted_mode,
5372 int x, int y,
5373 struct drm_framebuffer *fb)
5374{
5375 struct drm_device *dev = crtc->dev;
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5378 int pipe = intel_crtc->pipe;
5379 int plane = intel_crtc->plane;
5380 int num_connectors = 0;
5381 intel_clock_t clock, reduced_clock;
5382 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5383 bool ok, has_reduced_clock = false;
5384 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5385 struct intel_encoder *encoder;
5386 u32 temp;
5387 int ret;
01a415fd 5388 bool dither, fdi_config_ok;
de13a2e3
PZ		 5389
5390 for_each_encoder_on_crtc(dev, crtc, encoder) {
5391 switch (encoder->type) {
5392 case INTEL_OUTPUT_LVDS:
5393 is_lvds = true;
5394 break;
de13a2e3
PZ		 5395 case INTEL_OUTPUT_DISPLAYPORT:
5396 is_dp = true;
5397 break;
5398 case INTEL_OUTPUT_EDP:
5399 is_dp = true;
e2f12b07 5400 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5401 is_cpu_edp = true;
5402 break;
5403 }
5404
5405 num_connectors++;
5406 }
5407
5dc5298b
PZ		 5408 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5409 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5410
de13a2e3
PZ		 5411 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5412 &has_reduced_clock, &reduced_clock);
5413 if (!ok) {
5414 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5415 return -EINVAL;
5416 }
5417
5418 /* Ensure that the cursor is valid for the new mode before changing... */
5419 intel_crtc_update_cursor(crtc, true);
5420
5421 /* determine panel color depth */
c8241969
JN		 5422 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5423 adjusted_mode);
de13a2e3
PZ		 5424 if (is_lvds && dev_priv->lvds_dither)
5425 dither = true;
5426
5427 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5428 if (has_reduced_clock)
5429 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5430 reduced_clock.m2;
5431
5432 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5433
f7cb34d4 5434 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5435 drm_mode_debug_printmodeline(mode);
5436
5dc5298b
PZ		 5437 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5438 if (!is_cpu_edp) {
ee7b9f93 5439 struct intel_pch_pll *pll;
4b645f14 5440
ee7b9f93
JB		 5441 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5442 if (pll == NULL) {
5443 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5444 pipe);
4b645f14
JB		 5445 return -EINVAL;
5446 }
ee7b9f93
JB		 5447 } else
5448 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5449
5450 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5451 * This is an exception to the general rule that mode_set doesn't turn
5452 * things on.
5453 */
5454 if (is_lvds) {
fae14981 5455 temp = I915_READ(PCH_LVDS);
5eddb70b 5456 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5457 if (HAS_PCH_CPT(dev)) {
5458 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5459 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5460 } else {
5461 if (pipe == 1)
5462 temp |= LVDS_PIPEB_SELECT;
5463 else
5464 temp &= ~LVDS_PIPEB_SELECT;
5465 }
4b645f14 5466
a3e17eb8 5467 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5468 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5469 /* Set the B0-B3 data pairs corresponding to whether we're going to
5470 * set the DPLLs for dual-channel mode or not.
5471 */
5472 if (clock.p2 == 7)
5eddb70b 5473 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5474 else
5eddb70b 5475 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5476
5477 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5478 * appropriately here, but we need to look more thoroughly into how
5479 * panels behave in the two modes.
5480 */
284d5df5 5481 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5482 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5483 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5484 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5485 temp |= LVDS_VSYNC_POLARITY;
fae14981 5486 I915_WRITE(PCH_LVDS, temp);
79e53945 5487 }
434ed097 5488
e3aef172 5489 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5490 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5491 } else {
8db9d77b 5492 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5493 I915_WRITE(TRANSDATA_M1(pipe), 0);
5494 I915_WRITE(TRANSDATA_N1(pipe), 0);
5495 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5496 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5497 }
79e53945 5498
ee7b9f93
JB		 5499 if (intel_crtc->pch_pll) {
5500 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5501
32f9d658 5502 /* Wait for the clocks to stabilize. */
ee7b9f93 5503 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5504 udelay(150);
5505
8febb297
EA		 5506 /* The pixel multiplier can only be updated once the
5507 * DPLL is enabled and the clocks are stable.
5508 *
5509 * So write it again.
5510 */
ee7b9f93 5511 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5512 }
79e53945 5513
5eddb70b 5514 intel_crtc->lowfreq_avail = false;
ee7b9f93 5515 if (intel_crtc->pch_pll) {
4b645f14 5516 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5517 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5518 intel_crtc->lowfreq_avail = true;
4b645f14 5519 } else {
ee7b9f93 5520 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5521 }
5522 }
5523
b0e77b9c 5524 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5525
01a415fd
DV		 5526 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5527 * ironlake_check_fdi_lanes. */
f48d8f23 5528 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5529
01a415fd
DV		 5530 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5531
e3aef172 5532 if (is_cpu_edp)
8febb297 5533 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5534
c8203565 5535 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5536
9d0498a2 5537 intel_wait_for_vblank(dev, pipe);
79e53945 5538
a1f9e77e
PZ		 5539 /* Set up the display plane register */
5540 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5541 POSTING_READ(DSPCNTR(plane));
79e53945 5542
94352cf9 5543 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5544
5545 intel_update_watermarks(dev);
5546
1f8eeabf
ED		 5547 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5548
01a415fd 5549 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5550}
5551
09b4ddf9
PZ		 5552static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5553 struct drm_display_mode *mode,
5554 struct drm_display_mode *adjusted_mode,
5555 int x, int y,
5556 struct drm_framebuffer *fb)
5557{
5558 struct drm_device *dev = crtc->dev;
5559 struct drm_i915_private *dev_priv = dev->dev_private;
5560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5561 int pipe = intel_crtc->pipe;
5562 int plane = intel_crtc->plane;
5563 int num_connectors = 0;
5564 intel_clock_t clock, reduced_clock;
5dc5298b 5565 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5566 bool ok, has_reduced_clock = false;
5567 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5568 struct intel_encoder *encoder;
5569 u32 temp;
5570 int ret;
5571 bool dither;
5572
5573 for_each_encoder_on_crtc(dev, crtc, encoder) {
5574 switch (encoder->type) {
5575 case INTEL_OUTPUT_LVDS:
5576 is_lvds = true;
5577 break;
5578 case INTEL_OUTPUT_DISPLAYPORT:
5579 is_dp = true;
5580 break;
5581 case INTEL_OUTPUT_EDP:
5582 is_dp = true;
5583 if (!intel_encoder_is_pch_edp(&encoder->base))
5584 is_cpu_edp = true;
5585 break;
5586 }
5587
5588 num_connectors++;
5589 }
5590
a5c961d1
PZ		 5591 if (is_cpu_edp)
5592 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5593 else
5594 intel_crtc->cpu_transcoder = pipe;
5595
5dc5298b
PZ		 5596 /* We are not sure yet this won't happen. */
5597 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5598 INTEL_PCH_TYPE(dev));
5599
5600 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5601 num_connectors, pipe_name(pipe));
5602
702e7a56 5603 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5604 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5605
5606 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5607
6441ab5f
PZ		 5608 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5609 return -EINVAL;
5610
5dc5298b
PZ		 5611 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5612 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5613 &has_reduced_clock,
5614 &reduced_clock);
5615 if (!ok) {
5616 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5617 return -EINVAL;
5618 }
09b4ddf9
PZ		 5619 }
5620
5621 /* Ensure that the cursor is valid for the new mode before changing... */
5622 intel_crtc_update_cursor(crtc, true);
5623
5624 /* determine panel color depth */
c8241969
JN		 5625 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5626 adjusted_mode);
09b4ddf9
PZ		 5627 if (is_lvds && dev_priv->lvds_dither)
5628 dither = true;
5629
09b4ddf9
PZ		 5630 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5631 drm_mode_debug_printmodeline(mode);
5632
5dc5298b
PZ		 5633 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5634 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5635 if (has_reduced_clock)
5636 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5637 reduced_clock.m2;
5638
5639 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5640 fp);
5641
5642 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5643 * own on pre-Haswell/LPT generation */
5644 if (!is_cpu_edp) {
5645 struct intel_pch_pll *pll;
5646
5647 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5648 if (pll == NULL) {
5649 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5650 pipe);
5651 return -EINVAL;
5652 }
5653 } else
5654 intel_put_pch_pll(intel_crtc);
09b4ddf9 5655
5dc5298b
PZ		 5656 /* The LVDS pin pair needs to be on before the DPLLs are
5657 * enabled. This is an exception to the general rule that
5658 * mode_set doesn't turn things on.
5659 */
5660 if (is_lvds) {
5661 temp = I915_READ(PCH_LVDS);
5662 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5663 if (HAS_PCH_CPT(dev)) {
5664 temp &= ~PORT_TRANS_SEL_MASK;
5665 temp |= PORT_TRANS_SEL_CPT(pipe);
5666 } else {
5667 if (pipe == 1)
5668 temp |= LVDS_PIPEB_SELECT;
5669 else
5670 temp &= ~LVDS_PIPEB_SELECT;
5671 }
09b4ddf9 5672
5dc5298b
PZ		 5673 /* set the corresponsding LVDS_BORDER bit */
5674 temp |= dev_priv->lvds_border_bits;
5675 /* Set the B0-B3 data pairs corresponding to whether
5676 * we're going to set the DPLLs for dual-channel mode or
5677 * not.
5678 */
5679 if (clock.p2 == 7)
5680 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5681 else
5dc5298b
PZ		 5682 temp &= ~(LVDS_B0B3_POWER_UP |
5683 LVDS_CLKB_POWER_UP);
5684
5685 /* It would be nice to set 24 vs 18-bit mode
5686 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5687 * look more thoroughly into how panels behave in the
5688 * two modes.
5689 */
5690 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5691 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5692 temp |= LVDS_HSYNC_POLARITY;
5693 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5694 temp |= LVDS_VSYNC_POLARITY;
5695 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5696 }
09b4ddf9
PZ		 5697 }
5698
5699 if (is_dp && !is_cpu_edp) {
5700 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5701 } else {
5dc5298b
PZ		 5702 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5703 /* For non-DP output, clear any trans DP clock recovery
5704 * setting.*/
5705 I915_WRITE(TRANSDATA_M1(pipe), 0);
5706 I915_WRITE(TRANSDATA_N1(pipe), 0);
5707 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5708 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5709 }
09b4ddf9
PZ		 5710 }
5711
5712 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5713 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5714 if (intel_crtc->pch_pll) {
5715 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5716
5717 /* Wait for the clocks to stabilize. */
5718 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5719 udelay(150);
5720
5721 /* The pixel multiplier can only be updated once the
5722 * DPLL is enabled and the clocks are stable.
5723 *
5724 * So write it again.
5725 */
5726 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5727 }
5728
5729 if (intel_crtc->pch_pll) {
5730 if (is_lvds && has_reduced_clock && i915_powersave) {
5731 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5732 intel_crtc->lowfreq_avail = true;
5733 } else {
5734 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5735 }
09b4ddf9
PZ		 5736 }
5737 }
5738
5739 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5740
1eb8dfec
PZ		 5741 if (!is_dp || is_cpu_edp)
5742 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5743
5dc5298b
PZ		 5744 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5745 if (is_cpu_edp)
5746 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5747
ee2b0b38 5748 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5749
09b4ddf9
PZ		 5750 /* Set up the display plane register */
5751 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5752 POSTING_READ(DSPCNTR(plane));
5753
5754 ret = intel_pipe_set_base(crtc, x, y, fb);
5755
5756 intel_update_watermarks(dev);
5757
5758 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5759
5760 return ret;
5761}
5762
f564048e
EA		 5763static int intel_crtc_mode_set(struct drm_crtc *crtc,
5764 struct drm_display_mode *mode,
5765 struct drm_display_mode *adjusted_mode,
5766 int x, int y,
94352cf9 5767 struct drm_framebuffer *fb)
f564048e
EA		 5768{
5769 struct drm_device *dev = crtc->dev;
5770 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5771 struct drm_encoder_helper_funcs *encoder_funcs;
5772 struct intel_encoder *encoder;
0b701d27
EA		 5773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5774 int pipe = intel_crtc->pipe;
f564048e
EA		 5775 int ret;
5776
0b701d27 5777 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5778
f564048e 5779 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5780 x, y, fb);
79e53945 5781 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5782
9256aa19
DV		 5783 if (ret != 0)
5784 return ret;
5785
5786 for_each_encoder_on_crtc(dev, crtc, encoder) {
5787 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5788 encoder->base.base.id,
5789 drm_get_encoder_name(&encoder->base),
5790 mode->base.id, mode->name);
5791 encoder_funcs = encoder->base.helper_private;
5792 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5793 }
5794
5795 return 0;
79e53945
JB		 5796}
5797
3a9627f4
WF		 5798static bool intel_eld_uptodate(struct drm_connector *connector,
5799 int reg_eldv, uint32_t bits_eldv,
5800 int reg_elda, uint32_t bits_elda,
5801 int reg_edid)
5802{
5803 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5804 uint8_t *eld = connector->eld;
5805 uint32_t i;
5806
5807 i = I915_READ(reg_eldv);
5808 i &= bits_eldv;
5809
5810 if (!eld[0])
5811 return !i;
5812
5813 if (!i)
5814 return false;
5815
5816 i = I915_READ(reg_elda);
5817 i &= ~bits_elda;
5818 I915_WRITE(reg_elda, i);
5819
5820 for (i = 0; i < eld[2]; i++)
5821 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5822 return false;
5823
5824 return true;
5825}
5826
e0dac65e
WF		 5827static void g4x_write_eld(struct drm_connector *connector,
5828 struct drm_crtc *crtc)
5829{
5830 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5831 uint8_t *eld = connector->eld;
5832 uint32_t eldv;
5833 uint32_t len;
5834 uint32_t i;
5835
5836 i = I915_READ(G4X_AUD_VID_DID);
5837
5838 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5839 eldv = G4X_ELDV_DEVCL_DEVBLC;
5840 else
5841 eldv = G4X_ELDV_DEVCTG;
5842
3a9627f4
WF		 5843 if (intel_eld_uptodate(connector,
5844 G4X_AUD_CNTL_ST, eldv,
5845 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5846 G4X_HDMIW_HDMIEDID))
5847 return;
5848
e0dac65e
WF		 5849 i = I915_READ(G4X_AUD_CNTL_ST);
5850 i &= ~(eldv | G4X_ELD_ADDR);
5851 len = (i >> 9) & 0x1f; /* ELD buffer size */
5852 I915_WRITE(G4X_AUD_CNTL_ST, i);
5853
5854 if (!eld[0])
5855 return;
5856
5857 len = min_t(uint8_t, eld[2], len);
5858 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5859 for (i = 0; i < len; i++)
5860 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5861
5862 i = I915_READ(G4X_AUD_CNTL_ST);
5863 i |= eldv;
5864 I915_WRITE(G4X_AUD_CNTL_ST, i);
5865}
5866
83358c85
WX		 5867static void haswell_write_eld(struct drm_connector *connector,
5868 struct drm_crtc *crtc)
5869{
5870 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5871 uint8_t *eld = connector->eld;
5872 struct drm_device *dev = crtc->dev;
5873 uint32_t eldv;
5874 uint32_t i;
5875 int len;
5876 int pipe = to_intel_crtc(crtc)->pipe;
5877 int tmp;
5878
5879 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5880 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5881 int aud_config = HSW_AUD_CFG(pipe);
5882 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5883
5884
5885 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5886
5887 /* Audio output enable */
5888 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5889 tmp = I915_READ(aud_cntrl_st2);
5890 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5891 I915_WRITE(aud_cntrl_st2, tmp);
5892
5893 /* Wait for 1 vertical blank */
5894 intel_wait_for_vblank(dev, pipe);
5895
5896 /* Set ELD valid state */
5897 tmp = I915_READ(aud_cntrl_st2);
5898 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5899 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5900 I915_WRITE(aud_cntrl_st2, tmp);
5901 tmp = I915_READ(aud_cntrl_st2);
5902 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5903
5904 /* Enable HDMI mode */
5905 tmp = I915_READ(aud_config);
5906 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5907 /* clear N_programing_enable and N_value_index */
5908 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5909 I915_WRITE(aud_config, tmp);
5910
5911 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5912
5913 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5914
5915 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5916 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5917 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5918 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5919 } else
5920 I915_WRITE(aud_config, 0);
5921
5922 if (intel_eld_uptodate(connector,
5923 aud_cntrl_st2, eldv,
5924 aud_cntl_st, IBX_ELD_ADDRESS,
5925 hdmiw_hdmiedid))
5926 return;
5927
5928 i = I915_READ(aud_cntrl_st2);
5929 i &= ~eldv;
5930 I915_WRITE(aud_cntrl_st2, i);
5931
5932 if (!eld[0])
5933 return;
5934
5935 i = I915_READ(aud_cntl_st);
5936 i &= ~IBX_ELD_ADDRESS;
5937 I915_WRITE(aud_cntl_st, i);
5938 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5939 DRM_DEBUG_DRIVER("port num:%d\n", i);
5940
5941 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5942 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5943 for (i = 0; i < len; i++)
5944 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5945
5946 i = I915_READ(aud_cntrl_st2);
5947 i |= eldv;
5948 I915_WRITE(aud_cntrl_st2, i);
5949
5950}
5951
e0dac65e
WF		 5952static void ironlake_write_eld(struct drm_connector *connector,
5953 struct drm_crtc *crtc)
5954{
5955 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5956 uint8_t *eld = connector->eld;
5957 uint32_t eldv;
5958 uint32_t i;
5959 int len;
5960 int hdmiw_hdmiedid;
b6daa025 5961 int aud_config;
e0dac65e
WF		 5962 int aud_cntl_st;
5963 int aud_cntrl_st2;
9b138a83 5964 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5965
b3f33cbf 5966 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5967 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5968 aud_config = IBX_AUD_CFG(pipe);
5969 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5970 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5971 } else {
9b138a83
WX		 5972 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5973 aud_config = CPT_AUD_CFG(pipe);
5974 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5975 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5976 }
5977
9b138a83 5978 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5979
5980 i = I915_READ(aud_cntl_st);
9b138a83 5981 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5982 if (!i) {
5983 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5984 /* operate blindly on all ports */
1202b4c6
WF		 5985 eldv = IBX_ELD_VALIDB;
5986 eldv |= IBX_ELD_VALIDB << 4;
5987 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5988 } else {
5989 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5990 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5991 }
5992
3a9627f4
WF		 5993 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5994 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5995 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5996 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5997 } else
5998 I915_WRITE(aud_config, 0);
e0dac65e 5999
3a9627f4
WF		 6000 if (intel_eld_uptodate(connector,
6001 aud_cntrl_st2, eldv,
6002 aud_cntl_st, IBX_ELD_ADDRESS,
6003 hdmiw_hdmiedid))
6004 return;
6005
e0dac65e
WF		 6006 i = I915_READ(aud_cntrl_st2);
6007 i &= ~eldv;
6008 I915_WRITE(aud_cntrl_st2, i);
6009
6010 if (!eld[0])
6011 return;
6012
e0dac65e 6013 i = I915_READ(aud_cntl_st);
1202b4c6 6014 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6015 I915_WRITE(aud_cntl_st, i);
6016
6017 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6018 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6019 for (i = 0; i < len; i++)
6020 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6021
6022 i = I915_READ(aud_cntrl_st2);
6023 i |= eldv;
6024 I915_WRITE(aud_cntrl_st2, i);
6025}
6026
6027void intel_write_eld(struct drm_encoder *encoder,
6028 struct drm_display_mode *mode)
6029{
6030 struct drm_crtc *crtc = encoder->crtc;
6031 struct drm_connector *connector;
6032 struct drm_device *dev = encoder->dev;
6033 struct drm_i915_private *dev_priv = dev->dev_private;
6034
6035 connector = drm_select_eld(encoder, mode);
6036 if (!connector)
6037 return;
6038
6039 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6040 connector->base.id,
6041 drm_get_connector_name(connector),
6042 connector->encoder->base.id,
6043 drm_get_encoder_name(connector->encoder));
6044
6045 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6046
6047 if (dev_priv->display.write_eld)
6048 dev_priv->display.write_eld(connector, crtc);
6049}
6050
79e53945
JB		 6051/** Loads the palette/gamma unit for the CRTC with the prepared values */
6052void intel_crtc_load_lut(struct drm_crtc *crtc)
6053{
6054 struct drm_device *dev = crtc->dev;
6055 struct drm_i915_private *dev_priv = dev->dev_private;
6056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6057 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6058 int i;
6059
6060 /* The clocks have to be on to load the palette. */
aed3f09d 6061 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6062 return;
6063
f2b115e6 6064 /* use legacy palette for Ironlake */
bad720ff 6065 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6066 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6067
79e53945
JB		 6068 for (i = 0; i < 256; i++) {
6069 I915_WRITE(palreg + 4 * i,
6070 (intel_crtc->lut_r[i] << 16) |
6071 (intel_crtc->lut_g[i] << 8) |
6072 intel_crtc->lut_b[i]);
6073 }
6074}
6075
560b85bb
CW		 6076static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6077{
6078 struct drm_device *dev = crtc->dev;
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6081 bool visible = base != 0;
6082 u32 cntl;
6083
6084 if (intel_crtc->cursor_visible == visible)
6085 return;
6086
9db4a9c7 6087 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6088 if (visible) {
6089 /* On these chipsets we can only modify the base whilst
6090 * the cursor is disabled.
6091 */
9db4a9c7 6092 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6093
6094 cntl &= ~(CURSOR_FORMAT_MASK);
6095 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6096 cntl |= CURSOR_ENABLE |
6097 CURSOR_GAMMA_ENABLE |
6098 CURSOR_FORMAT_ARGB;
6099 } else
6100 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6101 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6102
6103 intel_crtc->cursor_visible = visible;
6104}
6105
6106static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6107{
6108 struct drm_device *dev = crtc->dev;
6109 struct drm_i915_private *dev_priv = dev->dev_private;
6110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6111 int pipe = intel_crtc->pipe;
6112 bool visible = base != 0;
6113
6114 if (intel_crtc->cursor_visible != visible) {
548f245b 6115 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6116 if (base) {
6117 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6118 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6119 cntl |= pipe << 28; /* Connect to correct pipe */
6120 } else {
6121 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6122 cntl |= CURSOR_MODE_DISABLE;
6123 }
9db4a9c7 6124 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6125
6126 intel_crtc->cursor_visible = visible;
6127 }
6128 /* and commit changes on next vblank */
9db4a9c7 6129 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6130}
6131
65a21cd6
JB		 6132static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6133{
6134 struct drm_device *dev = crtc->dev;
6135 struct drm_i915_private *dev_priv = dev->dev_private;
6136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6137 int pipe = intel_crtc->pipe;
6138 bool visible = base != 0;
6139
6140 if (intel_crtc->cursor_visible != visible) {
6141 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6142 if (base) {
6143 cntl &= ~CURSOR_MODE;
6144 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6145 } else {
6146 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6147 cntl |= CURSOR_MODE_DISABLE;
6148 }
6149 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6150
6151 intel_crtc->cursor_visible = visible;
6152 }
6153 /* and commit changes on next vblank */
6154 I915_WRITE(CURBASE_IVB(pipe), base);
6155}
6156
cda4b7d3 6157/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6158static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6159 bool on)
cda4b7d3
CW		 6160{
6161 struct drm_device *dev = crtc->dev;
6162 struct drm_i915_private *dev_priv = dev->dev_private;
6163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6164 int pipe = intel_crtc->pipe;
6165 int x = intel_crtc->cursor_x;
6166 int y = intel_crtc->cursor_y;
560b85bb 6167 u32 base, pos;
cda4b7d3
CW		 6168 bool visible;
6169
6170 pos = 0;
6171
6b383a7f 6172 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6173 base = intel_crtc->cursor_addr;
6174 if (x > (int) crtc->fb->width)
6175 base = 0;
6176
6177 if (y > (int) crtc->fb->height)
6178 base = 0;
6179 } else
6180 base = 0;
6181
6182 if (x < 0) {
6183 if (x + intel_crtc->cursor_width < 0)
6184 base = 0;
6185
6186 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6187 x = -x;
6188 }
6189 pos |= x << CURSOR_X_SHIFT;
6190
6191 if (y < 0) {
6192 if (y + intel_crtc->cursor_height < 0)
6193 base = 0;
6194
6195 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6196 y = -y;
6197 }
6198 pos |= y << CURSOR_Y_SHIFT;
6199
6200 visible = base != 0;
560b85bb 6201 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6202 return;
6203
0cd83aa9 6204 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6205 I915_WRITE(CURPOS_IVB(pipe), pos);
6206 ivb_update_cursor(crtc, base);
6207 } else {
6208 I915_WRITE(CURPOS(pipe), pos);
6209 if (IS_845G(dev) || IS_I865G(dev))
6210 i845_update_cursor(crtc, base);
6211 else
6212 i9xx_update_cursor(crtc, base);
6213 }
cda4b7d3
CW		 6214}
6215
79e53945 6216static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6217 struct drm_file *file,
79e53945
JB		 6218 uint32_t handle,
6219 uint32_t width, uint32_t height)
6220{
6221 struct drm_device *dev = crtc->dev;
6222 struct drm_i915_private *dev_priv = dev->dev_private;
6223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6224 struct drm_i915_gem_object *obj;
cda4b7d3 6225 uint32_t addr;
3f8bc370 6226 int ret;
79e53945 6227
79e53945
JB		 6228 /* if we want to turn off the cursor ignore width and height */
6229 if (!handle) {
28c97730 6230 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6231 addr = 0;
05394f39 6232 obj = NULL;
5004417d 6233 mutex_lock(&dev->struct_mutex);
3f8bc370 6234 goto finish;
79e53945
JB		 6235 }
6236
6237 /* Currently we only support 64x64 cursors */
6238 if (width != 64 || height != 64) {
6239 DRM_ERROR("we currently only support 64x64 cursors\n");
6240 return -EINVAL;
6241 }
6242
05394f39 6243 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6244 if (&obj->base == NULL)
79e53945
JB		 6245 return -ENOENT;
6246
05394f39 6247 if (obj->base.size < width * height * 4) {
79e53945 6248 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6249 ret = -ENOMEM;
6250 goto fail;
79e53945
JB		 6251 }
6252
71acb5eb 6253 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6254 mutex_lock(&dev->struct_mutex);
b295d1b6 6255 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6256 if (obj->tiling_mode) {
6257 DRM_ERROR("cursor cannot be tiled\n");
6258 ret = -EINVAL;
6259 goto fail_locked;
6260 }
6261
2da3b9b9 6262 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6263 if (ret) {
6264 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6265 goto fail_locked;
e7b526bb
CW		 6266 }
6267
d9e86c0e
CW		 6268 ret = i915_gem_object_put_fence(obj);
6269 if (ret) {
2da3b9b9 6270 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6271 goto fail_unpin;
6272 }
6273
05394f39 6274 addr = obj->gtt_offset;
71acb5eb 6275 } else {
6eeefaf3 6276 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6277 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6278 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6279 align);
71acb5eb
DA		 6280 if (ret) {
6281 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6282 goto fail_locked;
71acb5eb 6283 }
05394f39 6284 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6285 }
6286
a6c45cf0 6287 if (IS_GEN2(dev))
14b60391
JB		 6288 I915_WRITE(CURSIZE, (height << 12) | width);
6289
3f8bc370 6290 finish:
3f8bc370 6291 if (intel_crtc->cursor_bo) {
b295d1b6 6292 if (dev_priv->info->cursor_needs_physical) {
05394f39 6293 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6294 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6295 } else
6296 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6297 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6298 }
80824003 6299
7f9872e0 6300 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6301
6302 intel_crtc->cursor_addr = addr;
05394f39 6303 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6304 intel_crtc->cursor_width = width;
6305 intel_crtc->cursor_height = height;
6306
6b383a7f 6307 intel_crtc_update_cursor(crtc, true);
3f8bc370 6308
79e53945 6309 return 0;
e7b526bb 6310fail_unpin:
05394f39 6311 i915_gem_object_unpin(obj);
7f9872e0 6312fail_locked:
34b8686e 6313 mutex_unlock(&dev->struct_mutex);
bc9025bd 6314fail:
05394f39 6315 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6316 return ret;
79e53945
JB		 6317}
6318
6319static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6320{
79e53945 6321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6322
cda4b7d3
CW		 6323 intel_crtc->cursor_x = x;
6324 intel_crtc->cursor_y = y;
652c393a 6325
6b383a7f 6326 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6327
6328 return 0;
6329}
6330
6331/** Sets the color ramps on behalf of RandR */
6332void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6333 u16 blue, int regno)
6334{
6335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6336
6337 intel_crtc->lut_r[regno] = red >> 8;
6338 intel_crtc->lut_g[regno] = green >> 8;
6339 intel_crtc->lut_b[regno] = blue >> 8;
6340}
6341
b8c00ac5
DA		 6342void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6343 u16 *blue, int regno)
6344{
6345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6346
6347 *red = intel_crtc->lut_r[regno] << 8;
6348 *green = intel_crtc->lut_g[regno] << 8;
6349 *blue = intel_crtc->lut_b[regno] << 8;
6350}
6351
79e53945 6352static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6353 u16 *blue, uint32_t start, uint32_t size)
79e53945 6354{
7203425a 6355 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6357
7203425a 6358 for (i = start; i < end; i++) {
79e53945
JB		 6359 intel_crtc->lut_r[i] = red[i] >> 8;
6360 intel_crtc->lut_g[i] = green[i] >> 8;
6361 intel_crtc->lut_b[i] = blue[i] >> 8;
6362 }
6363
6364 intel_crtc_load_lut(crtc);
6365}
6366
6367/**
6368 * Get a pipe with a simple mode set on it for doing load-based monitor
6369 * detection.
6370 *
6371 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6372 * its requirements. The pipe will be connected to no other encoders.
79e53945 6373 *
c751ce4f 6374 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6375 * configured for it. In the future, it could choose to temporarily disable
6376 * some outputs to free up a pipe for its use.
6377 *
6378 * \return crtc, or NULL if no pipes are available.
6379 */
6380
6381/* VESA 640x480x72Hz mode to set on the pipe */
6382static struct drm_display_mode load_detect_mode = {
6383 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6384 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6385};
6386
d2dff872
CW		 6387static struct drm_framebuffer *
6388intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6389 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6390 struct drm_i915_gem_object *obj)
6391{
6392 struct intel_framebuffer *intel_fb;
6393 int ret;
6394
6395 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6396 if (!intel_fb) {
6397 drm_gem_object_unreference_unlocked(&obj->base);
6398 return ERR_PTR(-ENOMEM);
6399 }
6400
6401 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6402 if (ret) {
6403 drm_gem_object_unreference_unlocked(&obj->base);
6404 kfree(intel_fb);
6405 return ERR_PTR(ret);
6406 }
6407
6408 return &intel_fb->base;
6409}
6410
6411static u32
6412intel_framebuffer_pitch_for_width(int width, int bpp)
6413{
6414 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6415 return ALIGN(pitch, 64);
6416}
6417
6418static u32
6419intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6420{
6421 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6422 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6423}
6424
6425static struct drm_framebuffer *
6426intel_framebuffer_create_for_mode(struct drm_device *dev,
6427 struct drm_display_mode *mode,
6428 int depth, int bpp)
6429{
6430 struct drm_i915_gem_object *obj;
308e5bcb 6431 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6432
6433 obj = i915_gem_alloc_object(dev,
6434 intel_framebuffer_size_for_mode(mode, bpp));
6435 if (obj == NULL)
6436 return ERR_PTR(-ENOMEM);
6437
6438 mode_cmd.width = mode->hdisplay;
6439 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6440 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6441 bpp);
5ca0c34a 6442 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6443
6444 return intel_framebuffer_create(dev, &mode_cmd, obj);
6445}
6446
6447static struct drm_framebuffer *
6448mode_fits_in_fbdev(struct drm_device *dev,
6449 struct drm_display_mode *mode)
6450{
6451 struct drm_i915_private *dev_priv = dev->dev_private;
6452 struct drm_i915_gem_object *obj;
6453 struct drm_framebuffer *fb;
6454
6455 if (dev_priv->fbdev == NULL)
6456 return NULL;
6457
6458 obj = dev_priv->fbdev->ifb.obj;
6459 if (obj == NULL)
6460 return NULL;
6461
6462 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6463 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6464 fb->bits_per_pixel))
d2dff872
CW		 6465 return NULL;
6466
01f2c773 6467 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6468 return NULL;
6469
6470 return fb;
6471}
6472
d2434ab7 6473bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6474 struct drm_display_mode *mode,
8261b191 6475 struct intel_load_detect_pipe *old)
79e53945
JB		 6476{
6477 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6478 struct intel_encoder *intel_encoder =
6479 intel_attached_encoder(connector);
79e53945 6480 struct drm_crtc *possible_crtc;
4ef69c7a 6481 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6482 struct drm_crtc *crtc = NULL;
6483 struct drm_device *dev = encoder->dev;
94352cf9 6484 struct drm_framebuffer *fb;
79e53945
JB		 6485 int i = -1;
6486
d2dff872
CW		 6487 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6488 connector->base.id, drm_get_connector_name(connector),
6489 encoder->base.id, drm_get_encoder_name(encoder));
6490
79e53945
JB		 6491 /*
6492 * Algorithm gets a little messy:
7a5e4805 6493 *
79e53945
JB		 6494 * - if the connector already has an assigned crtc, use it (but make
6495 * sure it's on first)
7a5e4805 6496 *
79e53945
JB		 6497 * - try to find the first unused crtc that can drive this connector,
6498 * and use that if we find one
79e53945
JB		 6499 */
6500
6501 /* See if we already have a CRTC for this connector */
6502 if (encoder->crtc) {
6503 crtc = encoder->crtc;
8261b191 6504
24218aac 6505 old->dpms_mode = connector->dpms;
8261b191
CW		 6506 old->load_detect_temp = false;
6507
6508 /* Make sure the crtc and connector are running */
24218aac
DV		 6509 if (connector->dpms != DRM_MODE_DPMS_ON)
6510 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6511
7173188d 6512 return true;
79e53945
JB		 6513 }
6514
6515 /* Find an unused one (if possible) */
6516 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6517 i++;
6518 if (!(encoder->possible_crtcs & (1 << i)))
6519 continue;
6520 if (!possible_crtc->enabled) {
6521 crtc = possible_crtc;
6522 break;
6523 }
79e53945
JB		 6524 }
6525
6526 /*
6527 * If we didn't find an unused CRTC, don't use any.
6528 */
6529 if (!crtc) {
7173188d
CW		 6530 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6531 return false;
79e53945
JB		 6532 }
6533
fc303101
DV		 6534 intel_encoder->new_crtc = to_intel_crtc(crtc);
6535 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6536
6537 intel_crtc = to_intel_crtc(crtc);
24218aac 6538 old->dpms_mode = connector->dpms;
8261b191 6539 old->load_detect_temp = true;
d2dff872 6540 old->release_fb = NULL;
79e53945 6541
6492711d
CW		 6542 if (!mode)
6543 mode = &load_detect_mode;
79e53945 6544
d2dff872
CW		 6545 /* We need a framebuffer large enough to accommodate all accesses
6546 * that the plane may generate whilst we perform load detection.
6547 * We can not rely on the fbcon either being present (we get called
6548 * during its initialisation to detect all boot displays, or it may
6549 * not even exist) or that it is large enough to satisfy the
6550 * requested mode.
6551 */
94352cf9
DV		 6552 fb = mode_fits_in_fbdev(dev, mode);
6553 if (fb == NULL) {
d2dff872 6554 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6555 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6556 old->release_fb = fb;
d2dff872
CW		 6557 } else
6558 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6559 if (IS_ERR(fb)) {
d2dff872 6560 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6561 goto fail;
79e53945 6562 }
79e53945 6563
94352cf9 6564 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6565 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6566 if (old->release_fb)
6567 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6568 goto fail;
79e53945 6569 }
7173188d 6570
79e53945 6571 /* let the connector get through one full cycle before testing */
9d0498a2 6572 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6573
7173188d 6574 return true;
24218aac
DV		 6575fail:
6576 connector->encoder = NULL;
6577 encoder->crtc = NULL;
24218aac 6578 return false;
79e53945
JB		 6579}
6580
d2434ab7 6581void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6582 struct intel_load_detect_pipe *old)
79e53945 6583{
d2434ab7
DV		 6584 struct intel_encoder *intel_encoder =
6585 intel_attached_encoder(connector);
4ef69c7a 6586 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6587
d2dff872
CW		 6588 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6589 connector->base.id, drm_get_connector_name(connector),
6590 encoder->base.id, drm_get_encoder_name(encoder));
6591
8261b191 6592 if (old->load_detect_temp) {
fc303101
DV		 6593 struct drm_crtc *crtc = encoder->crtc;
6594
6595 to_intel_connector(connector)->new_encoder = NULL;
6596 intel_encoder->new_crtc = NULL;
6597 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6598
6599 if (old->release_fb)
6600 old->release_fb->funcs->destroy(old->release_fb);
6601
0622a53c 6602 return;
79e53945
JB		 6603 }
6604
c751ce4f 6605 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6606 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6607 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6608}
6609
6610/* Returns the clock of the currently programmed mode of the given pipe. */
6611static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6612{
6613 struct drm_i915_private *dev_priv = dev->dev_private;
6614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6615 int pipe = intel_crtc->pipe;
548f245b 6616 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6617 u32 fp;
6618 intel_clock_t clock;
6619
6620 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6621 fp = I915_READ(FP0(pipe));
79e53945 6622 else
39adb7a5 6623 fp = I915_READ(FP1(pipe));
79e53945
JB		 6624
6625 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6626 if (IS_PINEVIEW(dev)) {
6627 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6628 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6629 } else {
6630 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6631 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6632 }
6633
a6c45cf0 6634 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6635 if (IS_PINEVIEW(dev))
6636 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6637 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6638 else
6639 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6640 DPLL_FPA01_P1_POST_DIV_SHIFT);
6641
6642 switch (dpll & DPLL_MODE_MASK) {
6643 case DPLLB_MODE_DAC_SERIAL:
6644 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6645 5 : 10;
6646 break;
6647 case DPLLB_MODE_LVDS:
6648 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6649 7 : 14;
6650 break;
6651 default:
28c97730 6652 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6653 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6654 return 0;
6655 }
6656
6657 /* XXX: Handle the 100Mhz refclk */
2177832f 6658 intel_clock(dev, 96000, &clock);
79e53945
JB		 6659 } else {
6660 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6661
6662 if (is_lvds) {
6663 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6664 DPLL_FPA01_P1_POST_DIV_SHIFT);
6665 clock.p2 = 14;
6666
6667 if ((dpll & PLL_REF_INPUT_MASK) ==
6668 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6669 /* XXX: might not be 66MHz */
2177832f 6670 intel_clock(dev, 66000, &clock);
79e53945 6671 } else
2177832f 6672 intel_clock(dev, 48000, &clock);
79e53945
JB		 6673 } else {
6674 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6675 clock.p1 = 2;
6676 else {
6677 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6678 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6679 }
6680 if (dpll & PLL_P2_DIVIDE_BY_4)
6681 clock.p2 = 4;
6682 else
6683 clock.p2 = 2;
6684
2177832f 6685 intel_clock(dev, 48000, &clock);
79e53945
JB		 6686 }
6687 }
6688
6689 /* XXX: It would be nice to validate the clocks, but we can't reuse
6690 * i830PllIsValid() because it relies on the xf86_config connector
6691 * configuration being accurate, which it isn't necessarily.
6692 */
6693
6694 return clock.dot;
6695}
6696
6697/** Returns the currently programmed mode of the given pipe. */
6698struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6699 struct drm_crtc *crtc)
6700{
548f245b 6701 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6703 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6704 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6705 int htot = I915_READ(HTOTAL(cpu_transcoder));
6706 int hsync = I915_READ(HSYNC(cpu_transcoder));
6707 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6708 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6709
6710 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6711 if (!mode)
6712 return NULL;
6713
6714 mode->clock = intel_crtc_clock_get(dev, crtc);
6715 mode->hdisplay = (htot & 0xffff) + 1;
6716 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6717 mode->hsync_start = (hsync & 0xffff) + 1;
6718 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6719 mode->vdisplay = (vtot & 0xffff) + 1;
6720 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6721 mode->vsync_start = (vsync & 0xffff) + 1;
6722 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6723
6724 drm_mode_set_name(mode);
79e53945
JB		 6725
6726 return mode;
6727}
6728
3dec0095 6729static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6730{
6731 struct drm_device *dev = crtc->dev;
6732 drm_i915_private_t *dev_priv = dev->dev_private;
6733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6734 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6735 int dpll_reg = DPLL(pipe);
6736 int dpll;
652c393a 6737
bad720ff 6738 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6739 return;
6740
6741 if (!dev_priv->lvds_downclock_avail)
6742 return;
6743
dbdc6479 6744 dpll = I915_READ(dpll_reg);
652c393a 6745 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6746 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6747
8ac5a6d5 6748 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6749
6750 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6751 I915_WRITE(dpll_reg, dpll);
9d0498a2 6752 intel_wait_for_vblank(dev, pipe);
dbdc6479 6753
652c393a
JB		 6754 dpll = I915_READ(dpll_reg);
6755 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6756 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6757 }
652c393a
JB		 6758}
6759
6760static void intel_decrease_pllclock(struct drm_crtc *crtc)
6761{
6762 struct drm_device *dev = crtc->dev;
6763 drm_i915_private_t *dev_priv = dev->dev_private;
6764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6765
bad720ff 6766 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6767 return;
6768
6769 if (!dev_priv->lvds_downclock_avail)
6770 return;
6771
6772 /*
6773 * Since this is called by a timer, we should never get here in
6774 * the manual case.
6775 */
6776 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6777 int pipe = intel_crtc->pipe;
6778 int dpll_reg = DPLL(pipe);
6779 int dpll;
f6e5b160 6780
44d98a61 6781 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6782
8ac5a6d5 6783 assert_panel_unlocked(dev_priv, pipe);
652c393a 6784
dc257cf1 6785 dpll = I915_READ(dpll_reg);
652c393a
JB		 6786 dpll |= DISPLAY_RATE_SELECT_FPA1;
6787 I915_WRITE(dpll_reg, dpll);
9d0498a2 6788 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6789 dpll = I915_READ(dpll_reg);
6790 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6791 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6792 }
6793
6794}
6795
f047e395
CW		 6796void intel_mark_busy(struct drm_device *dev)
6797{
f047e395
CW		 6798 i915_update_gfx_val(dev->dev_private);
6799}
6800
6801void intel_mark_idle(struct drm_device *dev)
652c393a 6802{
f047e395
CW		 6803}
6804
6805void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6806{
6807 struct drm_device *dev = obj->base.dev;
652c393a 6808 struct drm_crtc *crtc;
652c393a
JB		 6809
6810 if (!i915_powersave)
6811 return;
6812
652c393a 6813 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6814 if (!crtc->fb)
6815 continue;
6816
f047e395
CW		 6817 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6818 intel_increase_pllclock(crtc);
652c393a 6819 }
652c393a
JB		 6820}
6821
f047e395 6822void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6823{
f047e395
CW		 6824 struct drm_device *dev = obj->base.dev;
6825 struct drm_crtc *crtc;
652c393a 6826
f047e395 6827 if (!i915_powersave)
acb87dfb
CW		 6828 return;
6829
652c393a
JB		 6830 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6831 if (!crtc->fb)
6832 continue;
6833
f047e395
CW		 6834 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6835 intel_decrease_pllclock(crtc);
652c393a
JB		 6836 }
6837}
6838
79e53945
JB		 6839static void intel_crtc_destroy(struct drm_crtc *crtc)
6840{
6841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6842 struct drm_device *dev = crtc->dev;
6843 struct intel_unpin_work *work;
6844 unsigned long flags;
6845
6846 spin_lock_irqsave(&dev->event_lock, flags);
6847 work = intel_crtc->unpin_work;
6848 intel_crtc->unpin_work = NULL;
6849 spin_unlock_irqrestore(&dev->event_lock, flags);
6850
6851 if (work) {
6852 cancel_work_sync(&work->work);
6853 kfree(work);
6854 }
79e53945
JB		 6855
6856 drm_crtc_cleanup(crtc);
67e77c5a 6857
79e53945
JB		 6858 kfree(intel_crtc);
6859}
6860
6b95a207
KH		 6861static void intel_unpin_work_fn(struct work_struct *__work)
6862{
6863 struct intel_unpin_work *work =
6864 container_of(__work, struct intel_unpin_work, work);
6865
6866 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6867 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6868 drm_gem_object_unreference(&work->pending_flip_obj->base);
6869 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6870
7782de3b 6871 intel_update_fbc(work->dev);
6b95a207
KH		 6872 mutex_unlock(&work->dev->struct_mutex);
6873 kfree(work);
6874}
6875
1afe3e9d 6876static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6877 struct drm_crtc *crtc)
6b95a207
KH		 6878{
6879 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6881 struct intel_unpin_work *work;
05394f39 6882 struct drm_i915_gem_object *obj;
6b95a207 6883 struct drm_pending_vblank_event *e;
95cb1b02 6884 struct timeval tvbl;
6b95a207
KH		 6885 unsigned long flags;
6886
6887 /* Ignore early vblank irqs */
6888 if (intel_crtc == NULL)
6889 return;
6890
6891 spin_lock_irqsave(&dev->event_lock, flags);
6892 work = intel_crtc->unpin_work;
6893 if (work == NULL || !work->pending) {
6894 spin_unlock_irqrestore(&dev->event_lock, flags);
6895 return;
6896 }
6897
6898 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6899
6900 if (work->event) {
6901 e = work->event;
49b14a5c 6902 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6903
49b14a5c
MK		 6904 e->event.tv_sec = tvbl.tv_sec;
6905 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6906
6b95a207
KH		 6907 list_add_tail(&e->base.link,
6908 &e->base.file_priv->event_list);
6909 wake_up_interruptible(&e->base.file_priv->event_wait);
6910 }
6911
0af7e4df
MK		 6912 drm_vblank_put(dev, intel_crtc->pipe);
6913
6b95a207
KH		 6914 spin_unlock_irqrestore(&dev->event_lock, flags);
6915
05394f39 6916 obj = work->old_fb_obj;
d9e86c0e 6917
e59f2bac 6918 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6919 &obj->pending_flip.counter);
d9e86c0e 6920
5bb61643 6921 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6922 schedule_work(&work->work);
e5510fac
JB		 6923
6924 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6925}
6926
1afe3e9d
JB		 6927void intel_finish_page_flip(struct drm_device *dev, int pipe)
6928{
6929 drm_i915_private_t *dev_priv = dev->dev_private;
6930 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6931
49b14a5c 6932 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6933}
6934
6935void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6936{
6937 drm_i915_private_t *dev_priv = dev->dev_private;
6938 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6939
49b14a5c 6940 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6941}
6942
6b95a207
KH		 6943void intel_prepare_page_flip(struct drm_device *dev, int plane)
6944{
6945 drm_i915_private_t *dev_priv = dev->dev_private;
6946 struct intel_crtc *intel_crtc =
6947 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6948 unsigned long flags;
6949
6950 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6951 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6952 if ((++intel_crtc->unpin_work->pending) > 1)
6953 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6954 } else {
6955 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6956 }
6b95a207
KH		 6957 spin_unlock_irqrestore(&dev->event_lock, flags);
6958}
6959
8c9f3aaf
JB		 6960static int intel_gen2_queue_flip(struct drm_device *dev,
6961 struct drm_crtc *crtc,
6962 struct drm_framebuffer *fb,
6963 struct drm_i915_gem_object *obj)
6964{
6965 struct drm_i915_private *dev_priv = dev->dev_private;
6966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6967 u32 flip_mask;
6d90c952 6968 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6969 int ret;
6970
6d90c952 6971 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6972 if (ret)
83d4092b 6973 goto err;
8c9f3aaf 6974
6d90c952 6975 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6976 if (ret)
83d4092b 6977 goto err_unpin;
8c9f3aaf
JB		 6978
6979 /* Can't queue multiple flips, so wait for the previous
6980 * one to finish before executing the next.
6981 */
6982 if (intel_crtc->plane)
6983 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6984 else
6985 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6986 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6987 intel_ring_emit(ring, MI_NOOP);
6988 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6989 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6990 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6991 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6992 intel_ring_emit(ring, 0); /* aux display base address, unused */
6993 intel_ring_advance(ring);
83d4092b
CW		 6994 return 0;
6995
6996err_unpin:
6997 intel_unpin_fb_obj(obj);
6998err:
8c9f3aaf
JB		 6999 return ret;
7000}
7001
7002static int intel_gen3_queue_flip(struct drm_device *dev,
7003 struct drm_crtc *crtc,
7004 struct drm_framebuffer *fb,
7005 struct drm_i915_gem_object *obj)
7006{
7007 struct drm_i915_private *dev_priv = dev->dev_private;
7008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7009 u32 flip_mask;
6d90c952 7010 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7011 int ret;
7012
6d90c952 7013 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7014 if (ret)
83d4092b 7015 goto err;
8c9f3aaf 7016
6d90c952 7017 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7018 if (ret)
83d4092b 7019 goto err_unpin;
8c9f3aaf
JB		 7020
7021 if (intel_crtc->plane)
7022 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7023 else
7024 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7025 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7026 intel_ring_emit(ring, MI_NOOP);
7027 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7028 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7029 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7030 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7031 intel_ring_emit(ring, MI_NOOP);
7032
7033 intel_ring_advance(ring);
83d4092b
CW		 7034 return 0;
7035
7036err_unpin:
7037 intel_unpin_fb_obj(obj);
7038err:
8c9f3aaf
JB		 7039 return ret;
7040}
7041
7042static int intel_gen4_queue_flip(struct drm_device *dev,
7043 struct drm_crtc *crtc,
7044 struct drm_framebuffer *fb,
7045 struct drm_i915_gem_object *obj)
7046{
7047 struct drm_i915_private *dev_priv = dev->dev_private;
7048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7049 uint32_t pf, pipesrc;
6d90c952 7050 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7051 int ret;
7052
6d90c952 7053 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7054 if (ret)
83d4092b 7055 goto err;
8c9f3aaf 7056
6d90c952 7057 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7058 if (ret)
83d4092b 7059 goto err_unpin;
8c9f3aaf
JB		 7060
7061 /* i965+ uses the linear or tiled offsets from the
7062 * Display Registers (which do not change across a page-flip)
7063 * so we need only reprogram the base address.
7064 */
6d90c952
DV		 7065 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7066 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7067 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7068 intel_ring_emit(ring,
7069 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7070 obj->tiling_mode);
8c9f3aaf
JB		 7071
7072 /* XXX Enabling the panel-fitter across page-flip is so far
7073 * untested on non-native modes, so ignore it for now.
7074 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7075 */
7076 pf = 0;
7077 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7078 intel_ring_emit(ring, pf | pipesrc);
7079 intel_ring_advance(ring);
83d4092b
CW		 7080 return 0;
7081
7082err_unpin:
7083 intel_unpin_fb_obj(obj);
7084err:
8c9f3aaf
JB		 7085 return ret;
7086}
7087
7088static int intel_gen6_queue_flip(struct drm_device *dev,
7089 struct drm_crtc *crtc,
7090 struct drm_framebuffer *fb,
7091 struct drm_i915_gem_object *obj)
7092{
7093 struct drm_i915_private *dev_priv = dev->dev_private;
7094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7095 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7096 uint32_t pf, pipesrc;
7097 int ret;
7098
6d90c952 7099 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7100 if (ret)
83d4092b 7101 goto err;
8c9f3aaf 7102
6d90c952 7103 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7104 if (ret)
83d4092b 7105 goto err_unpin;
8c9f3aaf 7106
6d90c952
DV		 7107 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7108 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7109 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7110 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7111
dc257cf1
DV		 7112 /* Contrary to the suggestions in the documentation,
7113 * "Enable Panel Fitter" does not seem to be required when page
7114 * flipping with a non-native mode, and worse causes a normal
7115 * modeset to fail.
7116 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7117 */
7118 pf = 0;
8c9f3aaf 7119 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7120 intel_ring_emit(ring, pf | pipesrc);
7121 intel_ring_advance(ring);
83d4092b
CW		 7122 return 0;
7123
7124err_unpin:
7125 intel_unpin_fb_obj(obj);
7126err:
8c9f3aaf
JB		 7127 return ret;
7128}
7129
7c9017e5
JB		 7130/*
7131 * On gen7 we currently use the blit ring because (in early silicon at least)
7132 * the render ring doesn't give us interrpts for page flip completion, which
7133 * means clients will hang after the first flip is queued. Fortunately the
7134 * blit ring generates interrupts properly, so use it instead.
7135 */
7136static int intel_gen7_queue_flip(struct drm_device *dev,
7137 struct drm_crtc *crtc,
7138 struct drm_framebuffer *fb,
7139 struct drm_i915_gem_object *obj)
7140{
7141 struct drm_i915_private *dev_priv = dev->dev_private;
7142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7143 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7144 uint32_t plane_bit = 0;
7c9017e5
JB		 7145 int ret;
7146
7147 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7148 if (ret)
83d4092b 7149 goto err;
7c9017e5 7150
cb05d8de
DV		 7151 switch(intel_crtc->plane) {
7152 case PLANE_A:
7153 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7154 break;
7155 case PLANE_B:
7156 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7157 break;
7158 case PLANE_C:
7159 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7160 break;
7161 default:
7162 WARN_ONCE(1, "unknown plane in flip command\n");
7163 ret = -ENODEV;
ab3951eb 7164 goto err_unpin;
cb05d8de
DV		 7165 }
7166
7c9017e5
JB		 7167 ret = intel_ring_begin(ring, 4);
7168 if (ret)
83d4092b 7169 goto err_unpin;
7c9017e5 7170
cb05d8de 7171 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7172 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7173 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7174 intel_ring_emit(ring, (MI_NOOP));
7175 intel_ring_advance(ring);
83d4092b
CW		 7176 return 0;
7177
7178err_unpin:
7179 intel_unpin_fb_obj(obj);
7180err:
7c9017e5
JB		 7181 return ret;
7182}
7183
8c9f3aaf
JB		 7184static int intel_default_queue_flip(struct drm_device *dev,
7185 struct drm_crtc *crtc,
7186 struct drm_framebuffer *fb,
7187 struct drm_i915_gem_object *obj)
7188{
7189 return -ENODEV;
7190}
7191
6b95a207
KH		 7192static int intel_crtc_page_flip(struct drm_crtc *crtc,
7193 struct drm_framebuffer *fb,
7194 struct drm_pending_vblank_event *event)
7195{
7196 struct drm_device *dev = crtc->dev;
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198 struct intel_framebuffer *intel_fb;
05394f39 7199 struct drm_i915_gem_object *obj;
6b95a207
KH		 7200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7201 struct intel_unpin_work *work;
8c9f3aaf 7202 unsigned long flags;
52e68630 7203 int ret;
6b95a207 7204
e6a595d2
VS		 7205 /* Can't change pixel format via MI display flips. */
7206 if (fb->pixel_format != crtc->fb->pixel_format)
7207 return -EINVAL;
7208
7209 /*
7210 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7211 * Note that pitch changes could also affect these register.
7212 */
7213 if (INTEL_INFO(dev)->gen > 3 &&
7214 (fb->offsets[0] != crtc->fb->offsets[0] ||
7215 fb->pitches[0] != crtc->fb->pitches[0]))
7216 return -EINVAL;
7217
6b95a207
KH		 7218 work = kzalloc(sizeof *work, GFP_KERNEL);
7219 if (work == NULL)
7220 return -ENOMEM;
7221
6b95a207
KH		 7222 work->event = event;
7223 work->dev = crtc->dev;
7224 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7225 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7226 INIT_WORK(&work->work, intel_unpin_work_fn);
7227
7317c75e
JB		 7228 ret = drm_vblank_get(dev, intel_crtc->pipe);
7229 if (ret)
7230 goto free_work;
7231
6b95a207
KH		 7232 /* We borrow the event spin lock for protecting unpin_work */
7233 spin_lock_irqsave(&dev->event_lock, flags);
7234 if (intel_crtc->unpin_work) {
7235 spin_unlock_irqrestore(&dev->event_lock, flags);
7236 kfree(work);
7317c75e 7237 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7238
7239 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7240 return -EBUSY;
7241 }
7242 intel_crtc->unpin_work = work;
7243 spin_unlock_irqrestore(&dev->event_lock, flags);
7244
7245 intel_fb = to_intel_framebuffer(fb);
7246 obj = intel_fb->obj;
7247
79158103
CW		 7248 ret = i915_mutex_lock_interruptible(dev);
7249 if (ret)
7250 goto cleanup;
6b95a207 7251
75dfca80 7252 /* Reference the objects for the scheduled work. */
05394f39
CW		 7253 drm_gem_object_reference(&work->old_fb_obj->base);
7254 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7255
7256 crtc->fb = fb;
96b099fd 7257
e1f99ce6 7258 work->pending_flip_obj = obj;
e1f99ce6 7259
4e5359cd
SF		 7260 work->enable_stall_check = true;
7261
e1f99ce6
CW		 7262 /* Block clients from rendering to the new back buffer until
7263 * the flip occurs and the object is no longer visible.
7264 */
05394f39 7265 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7266
8c9f3aaf
JB		 7267 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7268 if (ret)
7269 goto cleanup_pending;
6b95a207 7270
7782de3b 7271 intel_disable_fbc(dev);
f047e395 7272 intel_mark_fb_busy(obj);
6b95a207
KH		 7273 mutex_unlock(&dev->struct_mutex);
7274
e5510fac
JB		 7275 trace_i915_flip_request(intel_crtc->plane, obj);
7276
6b95a207 7277 return 0;
96b099fd 7278
8c9f3aaf
JB		 7279cleanup_pending:
7280 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7281 drm_gem_object_unreference(&work->old_fb_obj->base);
7282 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7283 mutex_unlock(&dev->struct_mutex);
7284
79158103 7285cleanup:
96b099fd
CW		 7286 spin_lock_irqsave(&dev->event_lock, flags);
7287 intel_crtc->unpin_work = NULL;
7288 spin_unlock_irqrestore(&dev->event_lock, flags);
7289
7317c75e
JB		 7290 drm_vblank_put(dev, intel_crtc->pipe);
7291free_work:
96b099fd
CW		 7292 kfree(work);
7293
7294 return ret;
6b95a207
KH		 7295}
7296
f6e5b160 7297static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7298 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7299 .load_lut = intel_crtc_load_lut,
976f8a20 7300 .disable = intel_crtc_noop,
f6e5b160
CW		 7301};
7302
6ed0f796 7303bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7304{
6ed0f796
DV		 7305 struct intel_encoder *other_encoder;
7306 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7307
6ed0f796
DV		 7308 if (WARN_ON(!crtc))
7309 return false;
7310
7311 list_for_each_entry(other_encoder,
7312 &crtc->dev->mode_config.encoder_list,
7313 base.head) {
7314
7315 if (&other_encoder->new_crtc->base != crtc ||
7316 encoder == other_encoder)
7317 continue;
7318 else
7319 return true;
f47166d2
CW		 7320 }
7321
6ed0f796
DV		 7322 return false;
7323}
47f1c6c9 7324
50f56119
DV		 7325static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7326 struct drm_crtc *crtc)
7327{
7328 struct drm_device *dev;
7329 struct drm_crtc *tmp;
7330 int crtc_mask = 1;
47f1c6c9 7331
50f56119 7332 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7333
50f56119 7334 dev = crtc->dev;
47f1c6c9 7335
50f56119
DV		 7336 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7337 if (tmp == crtc)
7338 break;
7339 crtc_mask <<= 1;
7340 }
47f1c6c9 7341
50f56119
DV		 7342 if (encoder->possible_crtcs & crtc_mask)
7343 return true;
7344 return false;
47f1c6c9 7345}
79e53945 7346
9a935856
DV		 7347/**
7348 * intel_modeset_update_staged_output_state
7349 *
7350 * Updates the staged output configuration state, e.g. after we've read out the
7351 * current hw state.
7352 */
7353static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7354{
9a935856
DV		 7355 struct intel_encoder *encoder;
7356 struct intel_connector *connector;
f6e5b160 7357
9a935856
DV		 7358 list_for_each_entry(connector, &dev->mode_config.connector_list,
7359 base.head) {
7360 connector->new_encoder =
7361 to_intel_encoder(connector->base.encoder);
7362 }
f6e5b160 7363
9a935856
DV		 7364 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7365 base.head) {
7366 encoder->new_crtc =
7367 to_intel_crtc(encoder->base.crtc);
7368 }
f6e5b160
CW		 7369}
7370
9a935856
DV		 7371/**
7372 * intel_modeset_commit_output_state
7373 *
7374 * This function copies the stage display pipe configuration to the real one.
7375 */
7376static void intel_modeset_commit_output_state(struct drm_device *dev)
7377{
7378 struct intel_encoder *encoder;
7379 struct intel_connector *connector;
f6e5b160 7380
9a935856
DV		 7381 list_for_each_entry(connector, &dev->mode_config.connector_list,
7382 base.head) {
7383 connector->base.encoder = &connector->new_encoder->base;
7384 }
f6e5b160 7385
9a935856
DV		 7386 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7387 base.head) {
7388 encoder->base.crtc = &encoder->new_crtc->base;
7389 }
7390}
7391
7758a113
DV		 7392static struct drm_display_mode *
7393intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7394 struct drm_display_mode *mode)
ee7b9f93 7395{
7758a113
DV		 7396 struct drm_device *dev = crtc->dev;
7397 struct drm_display_mode *adjusted_mode;
7398 struct drm_encoder_helper_funcs *encoder_funcs;
7399 struct intel_encoder *encoder;
ee7b9f93 7400
7758a113
DV		 7401 adjusted_mode = drm_mode_duplicate(dev, mode);
7402 if (!adjusted_mode)
7403 return ERR_PTR(-ENOMEM);
7404
7405 /* Pass our mode to the connectors and the CRTC to give them a chance to
7406 * adjust it according to limitations or connector properties, and also
7407 * a chance to reject the mode entirely.
7408 */
7409 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7410 base.head) {
7411
7412 if (&encoder->new_crtc->base != crtc)
7413 continue;
7414 encoder_funcs = encoder->base.helper_private;
7415 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7416 adjusted_mode))) {
7417 DRM_DEBUG_KMS("Encoder fixup failed\n");
7418 goto fail;
7419 }
ee7b9f93
JB		 7420 }
7421
7758a113
DV		 7422 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7423 DRM_DEBUG_KMS("CRTC fixup failed\n");
7424 goto fail;
ee7b9f93 7425 }
7758a113
DV		 7426 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7427
7428 return adjusted_mode;
7429fail:
7430 drm_mode_destroy(dev, adjusted_mode);
7431 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7432}
7433
e2e1ed41
DV		 7434/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7435 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7436static void
7437intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7438 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7439{
7440 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7441 struct drm_device *dev = crtc->dev;
7442 struct intel_encoder *encoder;
7443 struct intel_connector *connector;
7444 struct drm_crtc *tmp_crtc;
79e53945 7445
e2e1ed41 7446 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7447
e2e1ed41
DV		 7448 /* Check which crtcs have changed outputs connected to them, these need
7449 * to be part of the prepare_pipes mask. We don't (yet) support global
7450 * modeset across multiple crtcs, so modeset_pipes will only have one
7451 * bit set at most. */
7452 list_for_each_entry(connector, &dev->mode_config.connector_list,
7453 base.head) {
7454 if (connector->base.encoder == &connector->new_encoder->base)
7455 continue;
79e53945 7456
e2e1ed41
DV		 7457 if (connector->base.encoder) {
7458 tmp_crtc = connector->base.encoder->crtc;
7459
7460 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7461 }
7462
7463 if (connector->new_encoder)
7464 *prepare_pipes |=
7465 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7466 }
7467
e2e1ed41
DV		 7468 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7469 base.head) {
7470 if (encoder->base.crtc == &encoder->new_crtc->base)
7471 continue;
7472
7473 if (encoder->base.crtc) {
7474 tmp_crtc = encoder->base.crtc;
7475
7476 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7477 }
7478
7479 if (encoder->new_crtc)
7480 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7481 }
7482
e2e1ed41
DV		 7483 /* Check for any pipes that will be fully disabled ... */
7484 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7485 base.head) {
7486 bool used = false;
22fd0fab 7487
e2e1ed41
DV		 7488 /* Don't try to disable disabled crtcs. */
7489 if (!intel_crtc->base.enabled)
7490 continue;
7e7d76c3 7491
e2e1ed41
DV		 7492 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7493 base.head) {
7494 if (encoder->new_crtc == intel_crtc)
7495 used = true;
7496 }
7497
7498 if (!used)
7499 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7500 }
7501
e2e1ed41
DV		 7502
7503 /* set_mode is also used to update properties on life display pipes. */
7504 intel_crtc = to_intel_crtc(crtc);
7505 if (crtc->enabled)
7506 *prepare_pipes |= 1 << intel_crtc->pipe;
7507
7508 /* We only support modeset on one single crtc, hence we need to do that
7509 * only for the passed in crtc iff we change anything else than just
7510 * disable crtcs.
7511 *
7512 * This is actually not true, to be fully compatible with the old crtc
7513 * helper we automatically disable _any_ output (i.e. doesn't need to be
7514 * connected to the crtc we're modesetting on) if it's disconnected.
7515 * Which is a rather nutty api (since changed the output configuration
7516 * without userspace's explicit request can lead to confusion), but
7517 * alas. Hence we currently need to modeset on all pipes we prepare. */
7518 if (*prepare_pipes)
7519 *modeset_pipes = *prepare_pipes;
7520
7521 /* ... and mask these out. */
7522 *modeset_pipes &= ~(*disable_pipes);
7523 *prepare_pipes &= ~(*disable_pipes);
7524}
7525
ea9d758d
DV		 7526static bool intel_crtc_in_use(struct drm_crtc *crtc)
7527{
7528 struct drm_encoder *encoder;
7529 struct drm_device *dev = crtc->dev;
7530
7531 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7532 if (encoder->crtc == crtc)
7533 return true;
7534
7535 return false;
7536}
7537
7538static void
7539intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7540{
7541 struct intel_encoder *intel_encoder;
7542 struct intel_crtc *intel_crtc;
7543 struct drm_connector *connector;
7544
7545 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7546 base.head) {
7547 if (!intel_encoder->base.crtc)
7548 continue;
7549
7550 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7551
7552 if (prepare_pipes & (1 << intel_crtc->pipe))
7553 intel_encoder->connectors_active = false;
7554 }
7555
7556 intel_modeset_commit_output_state(dev);
7557
7558 /* Update computed state. */
7559 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7560 base.head) {
7561 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7562 }
7563
7564 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7565 if (!connector->encoder || !connector->encoder->crtc)
7566 continue;
7567
7568 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7569
7570 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7571 struct drm_property *dpms_property =
7572 dev->mode_config.dpms_property;
7573
ea9d758d 7574 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7575 drm_connector_property_set_value(connector,
7576 dpms_property,
7577 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7578
7579 intel_encoder = to_intel_encoder(connector->encoder);
7580 intel_encoder->connectors_active = true;
7581 }
7582 }
7583
7584}
7585
25c5b266
DV		 7586#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7587 list_for_each_entry((intel_crtc), \
7588 &(dev)->mode_config.crtc_list, \
7589 base.head) \
7590 if (mask & (1 <<(intel_crtc)->pipe)) \
7591
b980514c 7592void
8af6cf88
DV		 7593intel_modeset_check_state(struct drm_device *dev)
7594{
7595 struct intel_crtc *crtc;
7596 struct intel_encoder *encoder;
7597 struct intel_connector *connector;
7598
7599 list_for_each_entry(connector, &dev->mode_config.connector_list,
7600 base.head) {
7601 /* This also checks the encoder/connector hw state with the
7602 * ->get_hw_state callbacks. */
7603 intel_connector_check_state(connector);
7604
7605 WARN(&connector->new_encoder->base != connector->base.encoder,
7606 "connector's staged encoder doesn't match current encoder\n");
7607 }
7608
7609 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7610 base.head) {
7611 bool enabled = false;
7612 bool active = false;
7613 enum pipe pipe, tracked_pipe;
7614
7615 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7616 encoder->base.base.id,
7617 drm_get_encoder_name(&encoder->base));
7618
7619 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7620 "encoder's stage crtc doesn't match current crtc\n");
7621 WARN(encoder->connectors_active && !encoder->base.crtc,
7622 "encoder's active_connectors set, but no crtc\n");
7623
7624 list_for_each_entry(connector, &dev->mode_config.connector_list,
7625 base.head) {
7626 if (connector->base.encoder != &encoder->base)
7627 continue;
7628 enabled = true;
7629 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7630 active = true;
7631 }
7632 WARN(!!encoder->base.crtc != enabled,
7633 "encoder's enabled state mismatch "
7634 "(expected %i, found %i)\n",
7635 !!encoder->base.crtc, enabled);
7636 WARN(active && !encoder->base.crtc,
7637 "active encoder with no crtc\n");
7638
7639 WARN(encoder->connectors_active != active,
7640 "encoder's computed active state doesn't match tracked active state "
7641 "(expected %i, found %i)\n", active, encoder->connectors_active);
7642
7643 active = encoder->get_hw_state(encoder, &pipe);
7644 WARN(active != encoder->connectors_active,
7645 "encoder's hw state doesn't match sw tracking "
7646 "(expected %i, found %i)\n",
7647 encoder->connectors_active, active);
7648
7649 if (!encoder->base.crtc)
7650 continue;
7651
7652 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7653 WARN(active && pipe != tracked_pipe,
7654 "active encoder's pipe doesn't match"
7655 "(expected %i, found %i)\n",
7656 tracked_pipe, pipe);
7657
7658 }
7659
7660 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7661 base.head) {
7662 bool enabled = false;
7663 bool active = false;
7664
7665 DRM_DEBUG_KMS("[CRTC:%d]\n",
7666 crtc->base.base.id);
7667
7668 WARN(crtc->active && !crtc->base.enabled,
7669 "active crtc, but not enabled in sw tracking\n");
7670
7671 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7672 base.head) {
7673 if (encoder->base.crtc != &crtc->base)
7674 continue;
7675 enabled = true;
7676 if (encoder->connectors_active)
7677 active = true;
7678 }
7679 WARN(active != crtc->active,
7680 "crtc's computed active state doesn't match tracked active state "
7681 "(expected %i, found %i)\n", active, crtc->active);
7682 WARN(enabled != crtc->base.enabled,
7683 "crtc's computed enabled state doesn't match tracked enabled state "
7684 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7685
7686 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7687 }
7688}
7689
a6778b3c
DV		 7690bool intel_set_mode(struct drm_crtc *crtc,
7691 struct drm_display_mode *mode,
94352cf9 7692 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7693{
7694 struct drm_device *dev = crtc->dev;
dbf2b54e 7695 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7696 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7697 struct intel_crtc *intel_crtc;
7698 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7699 bool ret = true;
7700
e2e1ed41 7701 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7702 &prepare_pipes, &disable_pipes);
7703
7704 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7705 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7706
976f8a20
DV		 7707 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7708 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7709
a6778b3c
DV		 7710 saved_hwmode = crtc->hwmode;
7711 saved_mode = crtc->mode;
a6778b3c 7712
25c5b266
DV		 7713 /* Hack: Because we don't (yet) support global modeset on multiple
7714 * crtcs, we don't keep track of the new mode for more than one crtc.
7715 * Hence simply check whether any bit is set in modeset_pipes in all the
7716 * pieces of code that are not yet converted to deal with mutliple crtcs
7717 * changing their mode at the same time. */
7718 adjusted_mode = NULL;
7719 if (modeset_pipes) {
7720 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7721 if (IS_ERR(adjusted_mode)) {
7722 return false;
7723 }
25c5b266 7724 }
a6778b3c 7725
ea9d758d
DV		 7726 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7727 if (intel_crtc->base.enabled)
7728 dev_priv->display.crtc_disable(&intel_crtc->base);
7729 }
a6778b3c 7730
6c4c86f5
DV		 7731 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7732 * to set it here already despite that we pass it down the callchain.
7733 */
7734 if (modeset_pipes)
25c5b266 7735 crtc->mode = *mode;
7758a113 7736
ea9d758d
DV		 7737 /* Only after disabling all output pipelines that will be changed can we
7738 * update the the output configuration. */
7739 intel_modeset_update_state(dev, prepare_pipes);
7740
47fab737
DV		 7741 if (dev_priv->display.modeset_global_resources)
7742 dev_priv->display.modeset_global_resources(dev);
7743
a6778b3c
DV		 7744 /* Set up the DPLL and any encoders state that needs to adjust or depend
7745 * on the DPLL.
7746 */
25c5b266
DV		 7747 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7748 ret = !intel_crtc_mode_set(&intel_crtc->base,
7749 mode, adjusted_mode,
7750 x, y, fb);
7751 if (!ret)
7752 goto done;
a6778b3c
DV		 7753 }
7754
7755 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7756 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7757 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7758
25c5b266
DV		 7759 if (modeset_pipes) {
7760 /* Store real post-adjustment hardware mode. */
7761 crtc->hwmode = *adjusted_mode;
a6778b3c 7762
25c5b266
DV		 7763 /* Calculate and store various constants which
7764 * are later needed by vblank and swap-completion
7765 * timestamping. They are derived from true hwmode.
7766 */
7767 drm_calc_timestamping_constants(crtc);
7768 }
a6778b3c
DV		 7769
7770 /* FIXME: add subpixel order */
7771done:
7772 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7773 if (!ret && crtc->enabled) {
a6778b3c
DV		 7774 crtc->hwmode = saved_hwmode;
7775 crtc->mode = saved_mode;
8af6cf88
DV		 7776 } else {
7777 intel_modeset_check_state(dev);
a6778b3c
DV		 7778 }
7779
7780 return ret;
7781}
7782
25c5b266
DV		 7783#undef for_each_intel_crtc_masked
7784
d9e55608
DV		 7785static void intel_set_config_free(struct intel_set_config *config)
7786{
7787 if (!config)
7788 return;
7789
1aa4b628
DV		 7790 kfree(config->save_connector_encoders);
7791 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7792 kfree(config);
7793}
7794
85f9eb71
DV		 7795static int intel_set_config_save_state(struct drm_device *dev,
7796 struct intel_set_config *config)
7797{
85f9eb71
DV		 7798 struct drm_encoder *encoder;
7799 struct drm_connector *connector;
7800 int count;
7801
1aa4b628
DV		 7802 config->save_encoder_crtcs =
7803 kcalloc(dev->mode_config.num_encoder,
7804 sizeof(struct drm_crtc *), GFP_KERNEL);
7805 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7806 return -ENOMEM;
7807
1aa4b628
DV		 7808 config->save_connector_encoders =
7809 kcalloc(dev->mode_config.num_connector,
7810 sizeof(struct drm_encoder *), GFP_KERNEL);
7811 if (!config->save_connector_encoders)
85f9eb71
DV		 7812 return -ENOMEM;
7813
7814 /* Copy data. Note that driver private data is not affected.
7815 * Should anything bad happen only the expected state is
7816 * restored, not the drivers personal bookkeeping.
7817 */
85f9eb71
DV		 7818 count = 0;
7819 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7820 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7821 }
7822
7823 count = 0;
7824 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7825 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7826 }
7827
7828 return 0;
7829}
7830
7831static void intel_set_config_restore_state(struct drm_device *dev,
7832 struct intel_set_config *config)
7833{
9a935856
DV		 7834 struct intel_encoder *encoder;
7835 struct intel_connector *connector;
85f9eb71
DV		 7836 int count;
7837
85f9eb71 7838 count = 0;
9a935856
DV		 7839 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7840 encoder->new_crtc =
7841 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7842 }
7843
7844 count = 0;
9a935856
DV		 7845 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7846 connector->new_encoder =
7847 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7848 }
7849}
7850
5e2b584e
DV		 7851static void
7852intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7853 struct intel_set_config *config)
7854{
7855
7856 /* We should be able to check here if the fb has the same properties
7857 * and then just flip_or_move it */
7858 if (set->crtc->fb != set->fb) {
7859 /* If we have no fb then treat it as a full mode set */
7860 if (set->crtc->fb == NULL) {
7861 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7862 config->mode_changed = true;
7863 } else if (set->fb == NULL) {
7864 config->mode_changed = true;
7865 } else if (set->fb->depth != set->crtc->fb->depth) {
7866 config->mode_changed = true;
7867 } else if (set->fb->bits_per_pixel !=
7868 set->crtc->fb->bits_per_pixel) {
7869 config->mode_changed = true;
7870 } else
7871 config->fb_changed = true;
7872 }
7873
835c5873 7874 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7875 config->fb_changed = true;
7876
7877 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7878 DRM_DEBUG_KMS("modes are different, full mode set\n");
7879 drm_mode_debug_printmodeline(&set->crtc->mode);
7880 drm_mode_debug_printmodeline(set->mode);
7881 config->mode_changed = true;
7882 }
7883}
7884
2e431051 7885static int
9a935856
DV		 7886intel_modeset_stage_output_state(struct drm_device *dev,
7887 struct drm_mode_set *set,
7888 struct intel_set_config *config)
50f56119 7889{
85f9eb71 7890 struct drm_crtc *new_crtc;
9a935856
DV		 7891 struct intel_connector *connector;
7892 struct intel_encoder *encoder;
2e431051 7893 int count, ro;
50f56119 7894
9a935856
DV		 7895 /* The upper layers ensure that we either disabl a crtc or have a list
7896 * of connectors. For paranoia, double-check this. */
7897 WARN_ON(!set->fb && (set->num_connectors != 0));
7898 WARN_ON(set->fb && (set->num_connectors == 0));
7899
50f56119 7900 count = 0;
9a935856
DV		 7901 list_for_each_entry(connector, &dev->mode_config.connector_list,
7902 base.head) {
7903 /* Otherwise traverse passed in connector list and get encoders
7904 * for them. */
50f56119 7905 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7906 if (set->connectors[ro] == &connector->base) {
7907 connector->new_encoder = connector->encoder;
50f56119
DV		 7908 break;
7909 }
7910 }
7911
9a935856
DV		 7912 /* If we disable the crtc, disable all its connectors. Also, if
7913 * the connector is on the changing crtc but not on the new
7914 * connector list, disable it. */
7915 if ((!set->fb || ro == set->num_connectors) &&
7916 connector->base.encoder &&
7917 connector->base.encoder->crtc == set->crtc) {
7918 connector->new_encoder = NULL;
7919
7920 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7921 connector->base.base.id,
7922 drm_get_connector_name(&connector->base));
7923 }
7924
7925
7926 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7927 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7928 config->mode_changed = true;
50f56119 7929 }
9a935856
DV		 7930
7931 /* Disable all disconnected encoders. */
7932 if (connector->base.status == connector_status_disconnected)
7933 connector->new_encoder = NULL;
50f56119 7934 }
9a935856 7935 /* connector->new_encoder is now updated for all connectors. */
50f56119 7936
9a935856 7937 /* Update crtc of enabled connectors. */
50f56119 7938 count = 0;
9a935856
DV		 7939 list_for_each_entry(connector, &dev->mode_config.connector_list,
7940 base.head) {
7941 if (!connector->new_encoder)
50f56119
DV		 7942 continue;
7943
9a935856 7944 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7945
7946 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7947 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7948 new_crtc = set->crtc;
7949 }
7950
7951 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7952 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7953 new_crtc)) {
5e2b584e 7954 return -EINVAL;
50f56119 7955 }
9a935856
DV		 7956 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7957
7958 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7959 connector->base.base.id,
7960 drm_get_connector_name(&connector->base),
7961 new_crtc->base.id);
7962 }
7963
7964 /* Check for any encoders that needs to be disabled. */
7965 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7966 base.head) {
7967 list_for_each_entry(connector,
7968 &dev->mode_config.connector_list,
7969 base.head) {
7970 if (connector->new_encoder == encoder) {
7971 WARN_ON(!connector->new_encoder->new_crtc);
7972
7973 goto next_encoder;
7974 }
7975 }
7976 encoder->new_crtc = NULL;
7977next_encoder:
7978 /* Only now check for crtc changes so we don't miss encoders
7979 * that will be disabled. */
7980 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7981 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7982 config->mode_changed = true;
50f56119
DV		 7983 }
7984 }
9a935856 7985 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7986
2e431051
DV		 7987 return 0;
7988}
7989
7990static int intel_crtc_set_config(struct drm_mode_set *set)
7991{
7992 struct drm_device *dev;
2e431051
DV		 7993 struct drm_mode_set save_set;
7994 struct intel_set_config *config;
7995 int ret;
2e431051 7996
8d3e375e
DV		 7997 BUG_ON(!set);
7998 BUG_ON(!set->crtc);
7999 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8000
8001 if (!set->mode)
8002 set->fb = NULL;
8003
431e50f7
DV		 8004 /* The fb helper likes to play gross jokes with ->mode_set_config.
8005 * Unfortunately the crtc helper doesn't do much at all for this case,
8006 * so we have to cope with this madness until the fb helper is fixed up. */
8007 if (set->fb && set->num_connectors == 0)
8008 return 0;
8009
2e431051
DV		 8010 if (set->fb) {
8011 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8012 set->crtc->base.id, set->fb->base.id,
8013 (int)set->num_connectors, set->x, set->y);
8014 } else {
8015 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8016 }
8017
8018 dev = set->crtc->dev;
8019
8020 ret = -ENOMEM;
8021 config = kzalloc(sizeof(*config), GFP_KERNEL);
8022 if (!config)
8023 goto out_config;
8024
8025 ret = intel_set_config_save_state(dev, config);
8026 if (ret)
8027 goto out_config;
8028
8029 save_set.crtc = set->crtc;
8030 save_set.mode = &set->crtc->mode;
8031 save_set.x = set->crtc->x;
8032 save_set.y = set->crtc->y;
8033 save_set.fb = set->crtc->fb;
8034
8035 /* Compute whether we need a full modeset, only an fb base update or no
8036 * change at all. In the future we might also check whether only the
8037 * mode changed, e.g. for LVDS where we only change the panel fitter in
8038 * such cases. */
8039 intel_set_config_compute_mode_changes(set, config);
8040
9a935856 8041 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8042 if (ret)
8043 goto fail;
8044
5e2b584e 8045 if (config->mode_changed) {
87f1faa6 8046 if (set->mode) {
50f56119
DV		 8047 DRM_DEBUG_KMS("attempting to set mode from"
8048 " userspace\n");
8049 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8050 }
8051
8052 if (!intel_set_mode(set->crtc, set->mode,
8053 set->x, set->y, set->fb)) {
8054 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8055 set->crtc->base.id);
8056 ret = -EINVAL;
8057 goto fail;
8058 }
5e2b584e 8059 } else if (config->fb_changed) {
4f660f49 8060 ret = intel_pipe_set_base(set->crtc,
94352cf9 8061 set->x, set->y, set->fb);
50f56119
DV		 8062 }
8063
d9e55608
DV		 8064 intel_set_config_free(config);
8065
50f56119
DV		 8066 return 0;
8067
8068fail:
85f9eb71 8069 intel_set_config_restore_state(dev, config);
50f56119
DV		 8070
8071 /* Try to restore the config */
5e2b584e 8072 if (config->mode_changed &&
a6778b3c
DV		 8073 !intel_set_mode(save_set.crtc, save_set.mode,
8074 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8075 DRM_ERROR("failed to restore config after modeset failure\n");
8076
d9e55608
DV		 8077out_config:
8078 intel_set_config_free(config);
50f56119
DV		 8079 return ret;
8080}
8081
f6e5b160 8082static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8083 .cursor_set = intel_crtc_cursor_set,
8084 .cursor_move = intel_crtc_cursor_move,
8085 .gamma_set = intel_crtc_gamma_set,
50f56119 8086 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8087 .destroy = intel_crtc_destroy,
8088 .page_flip = intel_crtc_page_flip,
8089};
8090
79f689aa
PZ		 8091static void intel_cpu_pll_init(struct drm_device *dev)
8092{
8093 if (IS_HASWELL(dev))
8094 intel_ddi_pll_init(dev);
8095}
8096
ee7b9f93
JB		 8097static void intel_pch_pll_init(struct drm_device *dev)
8098{
8099 drm_i915_private_t *dev_priv = dev->dev_private;
8100 int i;
8101
8102 if (dev_priv->num_pch_pll == 0) {
8103 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8104 return;
8105 }
8106
8107 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8108 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8109 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8110 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8111 }
8112}
8113
b358d0a6 8114static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8115{
22fd0fab 8116 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8117 struct intel_crtc *intel_crtc;
8118 int i;
8119
8120 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8121 if (intel_crtc == NULL)
8122 return;
8123
8124 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8125
8126 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8127 for (i = 0; i < 256; i++) {
8128 intel_crtc->lut_r[i] = i;
8129 intel_crtc->lut_g[i] = i;
8130 intel_crtc->lut_b[i] = i;
8131 }
8132
80824003
JB		 8133 /* Swap pipes & planes for FBC on pre-965 */
8134 intel_crtc->pipe = pipe;
8135 intel_crtc->plane = pipe;
a5c961d1 8136 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8137 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8138 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8139 intel_crtc->plane = !pipe;
80824003
JB		 8140 }
8141
22fd0fab
JB		 8142 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8143 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8144 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8145 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8146
5a354204 8147 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8148
79e53945 8149 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8150}
8151
08d7b3d1 8152int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8153 struct drm_file *file)
08d7b3d1 8154{
08d7b3d1 8155 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8156 struct drm_mode_object *drmmode_obj;
8157 struct intel_crtc *crtc;
08d7b3d1 8158
1cff8f6b
DV		 8159 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8160 return -ENODEV;
08d7b3d1 8161
c05422d5
DV		 8162 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8163 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8164
c05422d5 8165 if (!drmmode_obj) {
08d7b3d1
CW		 8166 DRM_ERROR("no such CRTC id\n");
8167 return -EINVAL;
8168 }
8169
c05422d5
DV		 8170 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8171 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8172
c05422d5 8173 return 0;
08d7b3d1
CW		 8174}
8175
66a9278e 8176static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8177{
66a9278e
DV		 8178 struct drm_device *dev = encoder->base.dev;
8179 struct intel_encoder *source_encoder;
79e53945 8180 int index_mask = 0;
79e53945
JB		 8181 int entry = 0;
8182
66a9278e
DV		 8183 list_for_each_entry(source_encoder,
8184 &dev->mode_config.encoder_list, base.head) {
8185
8186 if (encoder == source_encoder)
79e53945 8187 index_mask |= (1 << entry);
66a9278e
DV		 8188
8189 /* Intel hw has only one MUX where enocoders could be cloned. */
8190 if (encoder->cloneable && source_encoder->cloneable)
8191 index_mask |= (1 << entry);
8192
79e53945
JB		 8193 entry++;
8194 }
4ef69c7a 8195
79e53945
JB		 8196 return index_mask;
8197}
8198
4d302442
CW		 8199static bool has_edp_a(struct drm_device *dev)
8200{
8201 struct drm_i915_private *dev_priv = dev->dev_private;
8202
8203 if (!IS_MOBILE(dev))
8204 return false;
8205
8206 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8207 return false;
8208
8209 if (IS_GEN5(dev) &&
8210 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8211 return false;
8212
8213 return true;
8214}
8215
79e53945
JB		 8216static void intel_setup_outputs(struct drm_device *dev)
8217{
725e30ad 8218 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8219 struct intel_encoder *encoder;
cb0953d7 8220 bool dpd_is_edp = false;
f3cfcba6 8221 bool has_lvds;
79e53945 8222
f3cfcba6 8223 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8224 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8225 /* disable the panel fitter on everything but LVDS */
8226 I915_WRITE(PFIT_CONTROL, 0);
8227 }
79e53945 8228
bad720ff 8229 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8230 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8231
4d302442 8232 if (has_edp_a(dev))
ab9d7c30 8233 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 8234
cb0953d7 8235 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8236 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 8237 }
8238
8239 intel_crt_init(dev);
8240
0e72a5b5
ED		 8241 if (IS_HASWELL(dev)) {
8242 int found;
8243
8244 /* Haswell uses DDI functions to detect digital outputs */
8245 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8246 /* DDI A only supports eDP */
8247 if (found)
8248 intel_ddi_init(dev, PORT_A);
8249
8250 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8251 * register */
8252 found = I915_READ(SFUSE_STRAP);
8253
8254 if (found & SFUSE_STRAP_DDIB_DETECTED)
8255 intel_ddi_init(dev, PORT_B);
8256 if (found & SFUSE_STRAP_DDIC_DETECTED)
8257 intel_ddi_init(dev, PORT_C);
8258 if (found & SFUSE_STRAP_DDID_DETECTED)
8259 intel_ddi_init(dev, PORT_D);
8260 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 8261 int found;
8262
30ad48b7 8263 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8264 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8265 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8266 if (!found)
08d644ad 8267 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8268 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8269 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8270 }
8271
8272 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8273 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8274
b708a1d5 8275 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8276 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8277
5eb08b69 8278 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8279 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8280
cb0953d7 8281 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8282 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8283 } else if (IS_VALLEYVIEW(dev)) {
8284 int found;
8285
19c03924
GB		 8286 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8287 if (I915_READ(DP_C) & DP_DETECTED)
8288 intel_dp_init(dev, DP_C, PORT_C);
8289
4a87d65d
JB		 8290 if (I915_READ(SDVOB) & PORT_DETECTED) {
8291 /* SDVOB multiplex with HDMIB */
8292 found = intel_sdvo_init(dev, SDVOB, true);
8293 if (!found)
08d644ad 8294 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8295 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8296 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8297 }
8298
8299 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8300 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8301
103a196f 8302 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8303 bool found = false;
7d57382e 8304
725e30ad 8305 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8306 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8307 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8308 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8309 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8310 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8311 }
27185ae1 8312
b01f2c3a
JB		 8313 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8314 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8315 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8316 }
725e30ad 8317 }
13520b05
KH		 8318
8319 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8320
b01f2c3a
JB		 8321 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8322 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8323 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8324 }
27185ae1
ML		 8325
8326 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8327
b01f2c3a
JB		 8328 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8329 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8330 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8331 }
8332 if (SUPPORTS_INTEGRATED_DP(dev)) {
8333 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8334 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8335 }
725e30ad 8336 }
27185ae1 8337
b01f2c3a
JB		 8338 if (SUPPORTS_INTEGRATED_DP(dev) &&
8339 (I915_READ(DP_D) & DP_DETECTED)) {
8340 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8341 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8342 }
bad720ff 8343 } else if (IS_GEN2(dev))
79e53945
JB		 8344 intel_dvo_init(dev);
8345
103a196f 8346 if (SUPPORTS_TV(dev))
79e53945
JB		 8347 intel_tv_init(dev);
8348
4ef69c7a
CW		 8349 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8350 encoder->base.possible_crtcs = encoder->crtc_mask;
8351 encoder->base.possible_clones =
66a9278e 8352 intel_encoder_clones(encoder);
79e53945 8353 }
47356eb6 8354
40579abe 8355 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8356 ironlake_init_pch_refclk(dev);
79e53945
JB		 8357}
8358
8359static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8360{
8361 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8362
8363 drm_framebuffer_cleanup(fb);
05394f39 8364 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8365
8366 kfree(intel_fb);
8367}
8368
8369static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8370 struct drm_file *file,
79e53945
JB		 8371 unsigned int *handle)
8372{
8373 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8374 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8375
05394f39 8376 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8377}
8378
8379static const struct drm_framebuffer_funcs intel_fb_funcs = {
8380 .destroy = intel_user_framebuffer_destroy,
8381 .create_handle = intel_user_framebuffer_create_handle,
8382};
8383
38651674
DA		 8384int intel_framebuffer_init(struct drm_device *dev,
8385 struct intel_framebuffer *intel_fb,
308e5bcb 8386 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8387 struct drm_i915_gem_object *obj)
79e53945 8388{
79e53945
JB		 8389 int ret;
8390
05394f39 8391 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8392 return -EINVAL;
8393
308e5bcb 8394 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8395 return -EINVAL;
8396
5d7bd705
VS		 8397 /* FIXME <= Gen4 stride limits are bit unclear */
8398 if (mode_cmd->pitches[0] > 32768)
8399 return -EINVAL;
8400
8401 if (obj->tiling_mode != I915_TILING_NONE &&
8402 mode_cmd->pitches[0] != obj->stride)
8403 return -EINVAL;
8404
57779d06 8405 /* Reject formats not supported by any plane early. */
308e5bcb 8406 switch (mode_cmd->pixel_format) {
57779d06 8407 case DRM_FORMAT_C8:
04b3924d
VS		 8408 case DRM_FORMAT_RGB565:
8409 case DRM_FORMAT_XRGB8888:
8410 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8411 break;
8412 case DRM_FORMAT_XRGB1555:
8413 case DRM_FORMAT_ARGB1555:
8414 if (INTEL_INFO(dev)->gen > 3)
8415 return -EINVAL;
8416 break;
8417 case DRM_FORMAT_XBGR8888:
8418 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8419 case DRM_FORMAT_XRGB2101010:
8420 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8421 case DRM_FORMAT_XBGR2101010:
8422 case DRM_FORMAT_ABGR2101010:
8423 if (INTEL_INFO(dev)->gen < 4)
8424 return -EINVAL;
b5626747 8425 break;
04b3924d
VS		 8426 case DRM_FORMAT_YUYV:
8427 case DRM_FORMAT_UYVY:
8428 case DRM_FORMAT_YVYU:
8429 case DRM_FORMAT_VYUY:
57779d06
VS		 8430 if (INTEL_INFO(dev)->gen < 6)
8431 return -EINVAL;
57cd6508
CW		 8432 break;
8433 default:
57779d06 8434 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8435 return -EINVAL;
8436 }
8437
90f9a336
VS		 8438 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8439 if (mode_cmd->offsets[0] != 0)
8440 return -EINVAL;
8441
79e53945
JB		 8442 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8443 if (ret) {
8444 DRM_ERROR("framebuffer init failed %d\n", ret);
8445 return ret;
8446 }
8447
8448 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8449 intel_fb->obj = obj;
79e53945
JB		 8450 return 0;
8451}
8452
79e53945
JB		 8453static struct drm_framebuffer *
8454intel_user_framebuffer_create(struct drm_device *dev,
8455 struct drm_file *filp,
308e5bcb 8456 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8457{
05394f39 8458 struct drm_i915_gem_object *obj;
79e53945 8459
308e5bcb
JB		 8460 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8461 mode_cmd->handles[0]));
c8725226 8462 if (&obj->base == NULL)
cce13ff7 8463 return ERR_PTR(-ENOENT);
79e53945 8464
d2dff872 8465 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8466}
8467
79e53945 8468static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8469 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8470 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8471};
8472
e70236a8
JB		 8473/* Set up chip specific display functions */
8474static void intel_init_display(struct drm_device *dev)
8475{
8476 struct drm_i915_private *dev_priv = dev->dev_private;
8477
8478 /* We always want a DPMS function */
09b4ddf9
PZ		 8479 if (IS_HASWELL(dev)) {
8480 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8481 dev_priv->display.crtc_enable = haswell_crtc_enable;
8482 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8483 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8484 dev_priv->display.update_plane = ironlake_update_plane;
8485 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8486 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8487 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8488 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8489 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8490 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8491 } else {
f564048e 8492 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8493 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8494 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8495 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8496 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8497 }
e70236a8 8498
e70236a8 8499 /* Returns the core display clock speed */
25eb05fc
JB		 8500 if (IS_VALLEYVIEW(dev))
8501 dev_priv->display.get_display_clock_speed =
8502 valleyview_get_display_clock_speed;
8503 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8504 dev_priv->display.get_display_clock_speed =
8505 i945_get_display_clock_speed;
8506 else if (IS_I915G(dev))
8507 dev_priv->display.get_display_clock_speed =
8508 i915_get_display_clock_speed;
f2b115e6 8509 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8510 dev_priv->display.get_display_clock_speed =
8511 i9xx_misc_get_display_clock_speed;
8512 else if (IS_I915GM(dev))
8513 dev_priv->display.get_display_clock_speed =
8514 i915gm_get_display_clock_speed;
8515 else if (IS_I865G(dev))
8516 dev_priv->display.get_display_clock_speed =
8517 i865_get_display_clock_speed;
f0f8a9ce 8518 else if (IS_I85X(dev))
e70236a8
JB		 8519 dev_priv->display.get_display_clock_speed =
8520 i855_get_display_clock_speed;
8521 else /* 852, 830 */
8522 dev_priv->display.get_display_clock_speed =
8523 i830_get_display_clock_speed;
8524
7f8a8569 8525 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8526 if (IS_GEN5(dev)) {
674cf967 8527 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8528 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8529 } else if (IS_GEN6(dev)) {
674cf967 8530 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8531 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8532 } else if (IS_IVYBRIDGE(dev)) {
8533 /* FIXME: detect B0+ stepping and use auto training */
8534 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8535 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8536 dev_priv->display.modeset_global_resources =
8537 ivb_modeset_global_resources;
c82e4d26
ED		 8538 } else if (IS_HASWELL(dev)) {
8539 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8540 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8541 } else
8542 dev_priv->display.update_wm = NULL;
6067aaea 8543 } else if (IS_G4X(dev)) {
e0dac65e 8544 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8545 }
8c9f3aaf
JB		 8546
8547 /* Default just returns -ENODEV to indicate unsupported */
8548 dev_priv->display.queue_flip = intel_default_queue_flip;
8549
8550 switch (INTEL_INFO(dev)->gen) {
8551 case 2:
8552 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8553 break;
8554
8555 case 3:
8556 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8557 break;
8558
8559 case 4:
8560 case 5:
8561 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8562 break;
8563
8564 case 6:
8565 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8566 break;
7c9017e5
JB		 8567 case 7:
8568 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8569 break;
8c9f3aaf 8570 }
e70236a8
JB		 8571}
8572
b690e96c
JB		 8573/*
8574 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8575 * resume, or other times. This quirk makes sure that's the case for
8576 * affected systems.
8577 */
0206e353 8578static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8579{
8580 struct drm_i915_private *dev_priv = dev->dev_private;
8581
8582 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8583 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8584}
8585
435793df
KP		 8586/*
8587 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8588 */
8589static void quirk_ssc_force_disable(struct drm_device *dev)
8590{
8591 struct drm_i915_private *dev_priv = dev->dev_private;
8592 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8593 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8594}
8595
4dca20ef 8596/*
5a15ab5b
CE		 8597 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8598 * brightness value
4dca20ef
CE		 8599 */
8600static void quirk_invert_brightness(struct drm_device *dev)
8601{
8602 struct drm_i915_private *dev_priv = dev->dev_private;
8603 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8604 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8605}
8606
b690e96c
JB		 8607struct intel_quirk {
8608 int device;
8609 int subsystem_vendor;
8610 int subsystem_device;
8611 void (*hook)(struct drm_device *dev);
8612};
8613
c43b5634 8614static struct intel_quirk intel_quirks[] = {
b690e96c 8615 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8616 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8617
b690e96c
JB		 8618 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8619 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8620
b690e96c
JB		 8621 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8622 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8623
ccd0d36e 8624 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8625 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8626 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8627
8628 /* Lenovo U160 cannot use SSC on LVDS */
8629 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8630
8631 /* Sony Vaio Y cannot use SSC on LVDS */
8632 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8633
8634 /* Acer Aspire 5734Z must invert backlight brightness */
8635 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8636};
8637
8638static void intel_init_quirks(struct drm_device *dev)
8639{
8640 struct pci_dev *d = dev->pdev;
8641 int i;
8642
8643 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8644 struct intel_quirk *q = &intel_quirks[i];
8645
8646 if (d->device == q->device &&
8647 (d->subsystem_vendor == q->subsystem_vendor ||
8648 q->subsystem_vendor == PCI_ANY_ID) &&
8649 (d->subsystem_device == q->subsystem_device ||
8650 q->subsystem_device == PCI_ANY_ID))
8651 q->hook(dev);
8652 }
8653}
8654
9cce37f4
JB		 8655/* Disable the VGA plane that we never use */
8656static void i915_disable_vga(struct drm_device *dev)
8657{
8658 struct drm_i915_private *dev_priv = dev->dev_private;
8659 u8 sr1;
8660 u32 vga_reg;
8661
8662 if (HAS_PCH_SPLIT(dev))
8663 vga_reg = CPU_VGACNTRL;
8664 else
8665 vga_reg = VGACNTRL;
8666
8667 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8668 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8669 sr1 = inb(VGA_SR_DATA);
8670 outb(sr1 | 1<<5, VGA_SR_DATA);
8671 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8672 udelay(300);
8673
8674 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8675 POSTING_READ(vga_reg);
8676}
8677
f817586c
DV		 8678void intel_modeset_init_hw(struct drm_device *dev)
8679{
0232e927
ED		 8680 /* We attempt to init the necessary power wells early in the initialization
8681 * time, so the subsystems that expect power to be enabled can work.
8682 */
8683 intel_init_power_wells(dev);
8684
a8f78b58
ED		 8685 intel_prepare_ddi(dev);
8686
f817586c
DV		 8687 intel_init_clock_gating(dev);
8688
79f5b2c7 8689 mutex_lock(&dev->struct_mutex);
8090c6b9 8690 intel_enable_gt_powersave(dev);
79f5b2c7 8691 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8692}
8693
79e53945
JB		 8694void intel_modeset_init(struct drm_device *dev)
8695{
652c393a 8696 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8697 int i, ret;
79e53945
JB		 8698
8699 drm_mode_config_init(dev);
8700
8701 dev->mode_config.min_width = 0;
8702 dev->mode_config.min_height = 0;
8703
019d96cb
DA		 8704 dev->mode_config.preferred_depth = 24;
8705 dev->mode_config.prefer_shadow = 1;
8706
e6ecefaa 8707 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8708
b690e96c
JB		 8709 intel_init_quirks(dev);
8710
1fa61106
ED		 8711 intel_init_pm(dev);
8712
e70236a8
JB		 8713 intel_init_display(dev);
8714
a6c45cf0
CW		 8715 if (IS_GEN2(dev)) {
8716 dev->mode_config.max_width = 2048;
8717 dev->mode_config.max_height = 2048;
8718 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8719 dev->mode_config.max_width = 4096;
8720 dev->mode_config.max_height = 4096;
79e53945 8721 } else {
a6c45cf0
CW		 8722 dev->mode_config.max_width = 8192;
8723 dev->mode_config.max_height = 8192;
79e53945 8724 }
dd2757f8 8725 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8726
28c97730 8727 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8728 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8729
a3524f1b 8730 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8731 intel_crtc_init(dev, i);
00c2064b
JB		 8732 ret = intel_plane_init(dev, i);
8733 if (ret)
8734 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8735 }
8736
79f689aa 8737 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8738 intel_pch_pll_init(dev);
8739
9cce37f4
JB		 8740 /* Just disable it once at startup */
8741 i915_disable_vga(dev);
79e53945 8742 intel_setup_outputs(dev);
2c7111db
CW		 8743}
8744
24929352
DV		 8745static void
8746intel_connector_break_all_links(struct intel_connector *connector)
8747{
8748 connector->base.dpms = DRM_MODE_DPMS_OFF;
8749 connector->base.encoder = NULL;
8750 connector->encoder->connectors_active = false;
8751 connector->encoder->base.crtc = NULL;
8752}
8753
7fad798e
DV		 8754static void intel_enable_pipe_a(struct drm_device *dev)
8755{
8756 struct intel_connector *connector;
8757 struct drm_connector *crt = NULL;
8758 struct intel_load_detect_pipe load_detect_temp;
8759
8760 /* We can't just switch on the pipe A, we need to set things up with a
8761 * proper mode and output configuration. As a gross hack, enable pipe A
8762 * by enabling the load detect pipe once. */
8763 list_for_each_entry(connector,
8764 &dev->mode_config.connector_list,
8765 base.head) {
8766 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8767 crt = &connector->base;
8768 break;
8769 }
8770 }
8771
8772 if (!crt)
8773 return;
8774
8775 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8776 intel_release_load_detect_pipe(crt, &load_detect_temp);
8777
8778
8779}
8780
fa555837
DV		 8781static bool
8782intel_check_plane_mapping(struct intel_crtc *crtc)
8783{
8784 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8785 u32 reg, val;
8786
8787 if (dev_priv->num_pipe == 1)
8788 return true;
8789
8790 reg = DSPCNTR(!crtc->plane);
8791 val = I915_READ(reg);
8792
8793 if ((val & DISPLAY_PLANE_ENABLE) &&
8794 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8795 return false;
8796
8797 return true;
8798}
8799
24929352
DV		 8800static void intel_sanitize_crtc(struct intel_crtc *crtc)
8801{
8802 struct drm_device *dev = crtc->base.dev;
8803 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8804 u32 reg;
24929352 8805
24929352 8806 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8807 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8808 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8809
8810 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8811 * disable the crtc (and hence change the state) if it is wrong. Note
8812 * that gen4+ has a fixed plane -> pipe mapping. */
8813 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8814 struct intel_connector *connector;
8815 bool plane;
8816
24929352
DV		 8817 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8818 crtc->base.base.id);
8819
8820 /* Pipe has the wrong plane attached and the plane is active.
8821 * Temporarily change the plane mapping and disable everything
8822 * ... */
8823 plane = crtc->plane;
8824 crtc->plane = !plane;
8825 dev_priv->display.crtc_disable(&crtc->base);
8826 crtc->plane = plane;
8827
8828 /* ... and break all links. */
8829 list_for_each_entry(connector, &dev->mode_config.connector_list,
8830 base.head) {
8831 if (connector->encoder->base.crtc != &crtc->base)
8832 continue;
8833
8834 intel_connector_break_all_links(connector);
8835 }
8836
8837 WARN_ON(crtc->active);
8838 crtc->base.enabled = false;
8839 }
24929352 8840
7fad798e
DV		 8841 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8842 crtc->pipe == PIPE_A && !crtc->active) {
8843 /* BIOS forgot to enable pipe A, this mostly happens after
8844 * resume. Force-enable the pipe to fix this, the update_dpms
8845 * call below we restore the pipe to the right state, but leave
8846 * the required bits on. */
8847 intel_enable_pipe_a(dev);
8848 }
8849
24929352
DV		 8850 /* Adjust the state of the output pipe according to whether we
8851 * have active connectors/encoders. */
8852 intel_crtc_update_dpms(&crtc->base);
8853
8854 if (crtc->active != crtc->base.enabled) {
8855 struct intel_encoder *encoder;
8856
8857 /* This can happen either due to bugs in the get_hw_state
8858 * functions or because the pipe is force-enabled due to the
8859 * pipe A quirk. */
8860 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8861 crtc->base.base.id,
8862 crtc->base.enabled ? "enabled" : "disabled",
8863 crtc->active ? "enabled" : "disabled");
8864
8865 crtc->base.enabled = crtc->active;
8866
8867 /* Because we only establish the connector -> encoder ->
8868 * crtc links if something is active, this means the
8869 * crtc is now deactivated. Break the links. connector
8870 * -> encoder links are only establish when things are
8871 * actually up, hence no need to break them. */
8872 WARN_ON(crtc->active);
8873
8874 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8875 WARN_ON(encoder->connectors_active);
8876 encoder->base.crtc = NULL;
8877 }
8878 }
8879}
8880
8881static void intel_sanitize_encoder(struct intel_encoder *encoder)
8882{
8883 struct intel_connector *connector;
8884 struct drm_device *dev = encoder->base.dev;
8885
8886 /* We need to check both for a crtc link (meaning that the
8887 * encoder is active and trying to read from a pipe) and the
8888 * pipe itself being active. */
8889 bool has_active_crtc = encoder->base.crtc &&
8890 to_intel_crtc(encoder->base.crtc)->active;
8891
8892 if (encoder->connectors_active && !has_active_crtc) {
8893 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8894 encoder->base.base.id,
8895 drm_get_encoder_name(&encoder->base));
8896
8897 /* Connector is active, but has no active pipe. This is
8898 * fallout from our resume register restoring. Disable
8899 * the encoder manually again. */
8900 if (encoder->base.crtc) {
8901 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8902 encoder->base.base.id,
8903 drm_get_encoder_name(&encoder->base));
8904 encoder->disable(encoder);
8905 }
8906
8907 /* Inconsistent output/port/pipe state happens presumably due to
8908 * a bug in one of the get_hw_state functions. Or someplace else
8909 * in our code, like the register restore mess on resume. Clamp
8910 * things to off as a safer default. */
8911 list_for_each_entry(connector,
8912 &dev->mode_config.connector_list,
8913 base.head) {
8914 if (connector->encoder != encoder)
8915 continue;
8916
8917 intel_connector_break_all_links(connector);
8918 }
8919 }
8920 /* Enabled encoders without active connectors will be fixed in
8921 * the crtc fixup. */
8922}
8923
8924/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8925 * and i915 state tracking structures. */
8926void intel_modeset_setup_hw_state(struct drm_device *dev)
8927{
8928 struct drm_i915_private *dev_priv = dev->dev_private;
8929 enum pipe pipe;
8930 u32 tmp;
8931 struct intel_crtc *crtc;
8932 struct intel_encoder *encoder;
8933 struct intel_connector *connector;
8934
e28d54cb
PZ		 8935 if (IS_HASWELL(dev)) {
8936 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8937
8938 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8939 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8940 case TRANS_DDI_EDP_INPUT_A_ON:
8941 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8942 pipe = PIPE_A;
8943 break;
8944 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8945 pipe = PIPE_B;
8946 break;
8947 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8948 pipe = PIPE_C;
8949 break;
8950 }
8951
8952 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8953 crtc->cpu_transcoder = TRANSCODER_EDP;
8954
8955 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8956 pipe_name(pipe));
8957 }
8958 }
8959
24929352
DV		 8960 for_each_pipe(pipe) {
8961 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8962
702e7a56 8963 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8964 if (tmp & PIPECONF_ENABLE)
8965 crtc->active = true;
8966 else
8967 crtc->active = false;
8968
8969 crtc->base.enabled = crtc->active;
8970
8971 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8972 crtc->base.base.id,
8973 crtc->active ? "enabled" : "disabled");
8974 }
8975
6441ab5f
PZ		 8976 if (IS_HASWELL(dev))
8977 intel_ddi_setup_hw_pll_state(dev);
8978
24929352
DV		 8979 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8980 base.head) {
8981 pipe = 0;
8982
8983 if (encoder->get_hw_state(encoder, &pipe)) {
8984 encoder->base.crtc =
8985 dev_priv->pipe_to_crtc_mapping[pipe];
8986 } else {
8987 encoder->base.crtc = NULL;
8988 }
8989
8990 encoder->connectors_active = false;
8991 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8992 encoder->base.base.id,
8993 drm_get_encoder_name(&encoder->base),
8994 encoder->base.crtc ? "enabled" : "disabled",
8995 pipe);
8996 }
8997
8998 list_for_each_entry(connector, &dev->mode_config.connector_list,
8999 base.head) {
9000 if (connector->get_hw_state(connector)) {
9001 connector->base.dpms = DRM_MODE_DPMS_ON;
9002 connector->encoder->connectors_active = true;
9003 connector->base.encoder = &connector->encoder->base;
9004 } else {
9005 connector->base.dpms = DRM_MODE_DPMS_OFF;
9006 connector->base.encoder = NULL;
9007 }
9008 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9009 connector->base.base.id,
9010 drm_get_connector_name(&connector->base),
9011 connector->base.encoder ? "enabled" : "disabled");
9012 }
9013
9014 /* HW state is read out, now we need to sanitize this mess. */
9015 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9016 base.head) {
9017 intel_sanitize_encoder(encoder);
9018 }
9019
9020 for_each_pipe(pipe) {
9021 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9022 intel_sanitize_crtc(crtc);
9023 }
9a935856
DV		 9024
9025 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 9026
9027 intel_modeset_check_state(dev);
2e938892
DV		 9028
9029 drm_mode_config_reset(dev);
24929352
DV		 9030}
9031
2c7111db
CW		 9032void intel_modeset_gem_init(struct drm_device *dev)
9033{
1833b134 9034 intel_modeset_init_hw(dev);
02e792fb
DV		 9035
9036 intel_setup_overlay(dev);
24929352
DV		 9037
9038 intel_modeset_setup_hw_state(dev);
79e53945
JB		 9039}
9040
9041void intel_modeset_cleanup(struct drm_device *dev)
9042{
652c393a
JB		 9043 struct drm_i915_private *dev_priv = dev->dev_private;
9044 struct drm_crtc *crtc;
9045 struct intel_crtc *intel_crtc;
9046
f87ea761 9047 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9048 mutex_lock(&dev->struct_mutex);
9049
723bfd70
JB		 9050 intel_unregister_dsm_handler();
9051
9052
652c393a
JB		 9053 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9054 /* Skip inactive CRTCs */
9055 if (!crtc->fb)
9056 continue;
9057
9058 intel_crtc = to_intel_crtc(crtc);
3dec0095 9059 intel_increase_pllclock(crtc);
652c393a
JB		 9060 }
9061
973d04f9 9062 intel_disable_fbc(dev);
e70236a8 9063
8090c6b9 9064 intel_disable_gt_powersave(dev);
0cdab21f 9065
930ebb46
DV		 9066 ironlake_teardown_rc6(dev);
9067
57f350b6
JB		 9068 if (IS_VALLEYVIEW(dev))
9069 vlv_init_dpio(dev);
9070
69341a5e
KH		 9071 mutex_unlock(&dev->struct_mutex);
9072
6c0d9350
DV		 9073 /* Disable the irq before mode object teardown, for the irq might
9074 * enqueue unpin/hotplug work. */
9075 drm_irq_uninstall(dev);
9076 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9077 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9078
1630fe75
CW		 9079 /* flush any delayed tasks or pending work */
9080 flush_scheduled_work();
9081
79e53945
JB		 9082 drm_mode_config_cleanup(dev);
9083}
9084
f1c79df3
ZW		 9085/*
9086 * Return which encoder is currently attached for connector.
9087 */
df0e9248 9088struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9089{
df0e9248
CW		 9090 return &intel_attached_encoder(connector)->base;
9091}
f1c79df3 9092
df0e9248
CW		 9093void intel_connector_attach_encoder(struct intel_connector *connector,
9094 struct intel_encoder *encoder)
9095{
9096 connector->encoder = encoder;
9097 drm_mode_connector_attach_encoder(&connector->base,
9098 &encoder->base);
79e53945 9099}
28d52043
DA		 9100
9101/*
9102 * set vga decode state - true == enable VGA decode
9103 */
9104int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9105{
9106 struct drm_i915_private *dev_priv = dev->dev_private;
9107 u16 gmch_ctrl;
9108
9109 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9110 if (state)
9111 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9112 else
9113 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9114 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9115 return 0;
9116}
c4a1d9e4
CW		 9117
9118#ifdef CONFIG_DEBUG_FS
9119#include <linux/seq_file.h>
9120
9121struct intel_display_error_state {
9122 struct intel_cursor_error_state {
9123 u32 control;
9124 u32 position;
9125 u32 base;
9126 u32 size;
52331309 9127 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9128
9129 struct intel_pipe_error_state {
9130 u32 conf;
9131 u32 source;
9132
9133 u32 htotal;
9134 u32 hblank;
9135 u32 hsync;
9136 u32 vtotal;
9137 u32 vblank;
9138 u32 vsync;
52331309 9139 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9140
9141 struct intel_plane_error_state {
9142 u32 control;
9143 u32 stride;
9144 u32 size;
9145 u32 pos;
9146 u32 addr;
9147 u32 surface;
9148 u32 tile_offset;
52331309 9149 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9150};
9151
9152struct intel_display_error_state *
9153intel_display_capture_error_state(struct drm_device *dev)
9154{
0206e353 9155 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9156 struct intel_display_error_state *error;
702e7a56 9157 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9158 int i;
9159
9160 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9161 if (error == NULL)
9162 return NULL;
9163
52331309 9164 for_each_pipe(i) {
702e7a56
PZ		 9165 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9166
c4a1d9e4
CW		 9167 error->cursor[i].control = I915_READ(CURCNTR(i));
9168 error->cursor[i].position = I915_READ(CURPOS(i));
9169 error->cursor[i].base = I915_READ(CURBASE(i));
9170
9171 error->plane[i].control = I915_READ(DSPCNTR(i));
9172 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9173 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9174 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9175 error->plane[i].addr = I915_READ(DSPADDR(i));
9176 if (INTEL_INFO(dev)->gen >= 4) {
9177 error->plane[i].surface = I915_READ(DSPSURF(i));
9178 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9179 }
9180
702e7a56 9181 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9182 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9183 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9184 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9185 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9186 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9187 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9188 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9189 }
9190
9191 return error;
9192}
9193
9194void
9195intel_display_print_error_state(struct seq_file *m,
9196 struct drm_device *dev,
9197 struct intel_display_error_state *error)
9198{
52331309 9199 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9200 int i;
9201
52331309
DL		 9202 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9203 for_each_pipe(i) {
c4a1d9e4
CW		 9204 seq_printf(m, "Pipe [%d]:\n", i);
9205 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9206 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9207 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9208 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9209 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9210 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9211 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9212 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9213
9214 seq_printf(m, "Plane [%d]:\n", i);
9215 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9216 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9217 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9218 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9219 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9220 if (INTEL_INFO(dev)->gen >= 4) {
9221 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9222 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9223 }
9224
9225 seq_printf(m, "Cursor [%d]:\n", i);
9226 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9227 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9228 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9229 }
9230}
9231#endif
Linux kernel - Deliverables
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