projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Keep GMCH DPLL VGA mode always disabled
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
568c634a 89static int intel_set_mode(struct drm_atomic_state *state);
eb1bfe80
JB		 90static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
5b18e57c
DV		 94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
29407aab 99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 102static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
d288f65f 104static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 105 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 106static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 108static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
e7457a9a 112
0e32b39c
DA		 113static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114{
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119}
120
79e53945 121typedef struct {
0206e353 122 int min, max;
79e53945
JB		 123} intel_range_t;
124
125typedef struct {
0206e353
AJ		 126 int dot_limit;
127 int p2_slow, p2_fast;
79e53945
JB		 128} intel_p2_t;
129
d4906093
ML		 130typedef struct intel_limit intel_limit_t;
131struct intel_limit {
0206e353
AJ		 132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
d4906093 134};
79e53945 135
d2acd215
DV		 136int
137intel_pch_rawclk(struct drm_device *dev)
138{
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144}
145
021357ac
CW		 146static inline u32 /* units of 100MHz */
147intel_fdi_link_freq(struct drm_device *dev)
148{
8b99e68c
CW		 149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
021357ac
CW		 154}
155
5d536e28 156static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 157 .dot = { .min = 25000, .max = 350000 },
9c333719 158 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 159 .n = { .min = 2, .max = 16 },
0206e353
AJ		 160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 167};
168
5d536e28
DV		 169static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
9c333719 171 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 172 .n = { .min = 2, .max = 16 },
5d536e28
DV		 173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180};
181
e4b36699 182static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 183 .dot = { .min = 25000, .max = 350000 },
9c333719 184 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 185 .n = { .min = 2, .max = 16 },
0206e353
AJ		 186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
e4b36699 193};
273e27ca 194
e4b36699 195static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 219};
220
273e27ca 221
e4b36699 222static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
044c7c41 234 },
e4b36699
KP		 235};
236
237static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 248};
249
250static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
044c7c41 261 },
e4b36699
KP		 262};
263
264static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
044c7c41 275 },
e4b36699
KP		 276};
277
f2b115e6 278static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 281 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
273e27ca 284 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 291};
292
f2b115e6 293static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 304};
305
273e27ca
EA		 306/* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
b91ad0ec 311static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 322};
323
b91ad0ec 324static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 335};
336
337static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 348};
349
273e27ca 350/* LVDS 100mhz refclk limits. */
b91ad0ec 351static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
0206e353 359 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 362};
363
364static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
0206e353 372 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 375};
376
dc730512 377static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 385 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 386 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
b99ab663 389 .p1 = { .min = 2, .max = 3 },
5fdc9c49 390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 391};
392
ef9348c8
CML		 393static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 401 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407};
408
5ab7b0b7
ID		 409static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
e6292556 412 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419};
420
cdba954e
ACO		 421static bool
422needs_modeset(struct drm_crtc_state *state)
423{
424 return state->mode_changed || state->active_changed;
425}
426
e0638cdf
PZ		 427/**
428 * Returns whether any output on the specified pipe is of the specified type
429 */
4093561b 430bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 431{
409ee761 432 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 433 struct intel_encoder *encoder;
434
409ee761 435 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 436 if (encoder->type == type)
437 return true;
438
439 return false;
440}
441
d0737e1d
ACO		 442/**
443 * Returns whether any output on the specified pipe will have the specified
444 * type after a staged modeset is complete, i.e., the same as
445 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
446 * encoder->crtc.
447 */
a93e255f
ACO		 448static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
449 int type)
d0737e1d 450{
a93e255f 451 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 452 struct drm_connector *connector;
a93e255f 453 struct drm_connector_state *connector_state;
d0737e1d 454 struct intel_encoder *encoder;
a93e255f
ACO		 455 int i, num_connectors = 0;
456
da3ced29 457 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 458 if (connector_state->crtc != crtc_state->base.crtc)
459 continue;
460
461 num_connectors++;
d0737e1d 462
a93e255f
ACO		 463 encoder = to_intel_encoder(connector_state->best_encoder);
464 if (encoder->type == type)
d0737e1d 465 return true;
a93e255f
ACO		 466 }
467
468 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 469
470 return false;
471}
472
a93e255f
ACO		 473static const intel_limit_t *
474intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 475{
a93e255f 476 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 477 const intel_limit_t *limit;
b91ad0ec 478
a93e255f 479 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 480 if (intel_is_dual_link_lvds(dev)) {
1b894b59 481 if (refclk == 100000)
b91ad0ec
ZW		 482 limit = &intel_limits_ironlake_dual_lvds_100m;
483 else
484 limit = &intel_limits_ironlake_dual_lvds;
485 } else {
1b894b59 486 if (refclk == 100000)
b91ad0ec
ZW		 487 limit = &intel_limits_ironlake_single_lvds_100m;
488 else
489 limit = &intel_limits_ironlake_single_lvds;
490 }
c6bb3538 491 } else
b91ad0ec 492 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 493
494 return limit;
495}
496
a93e255f
ACO		 497static const intel_limit_t *
498intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 499{
a93e255f 500 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 501 const intel_limit_t *limit;
502
a93e255f 503 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 504 if (intel_is_dual_link_lvds(dev))
e4b36699 505 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 506 else
e4b36699 507 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 508 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
509 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 510 limit = &intel_limits_g4x_hdmi;
a93e255f 511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 512 limit = &intel_limits_g4x_sdvo;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
a93e255f
ACO		 519static const intel_limit_t *
520intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 521{
a93e255f 522 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 523 const intel_limit_t *limit;
524
5ab7b0b7
ID		 525 if (IS_BROXTON(dev))
526 limit = &intel_limits_bxt;
527 else if (HAS_PCH_SPLIT(dev))
a93e255f 528 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 529 else if (IS_G4X(dev)) {
a93e255f 530 limit = intel_g4x_limit(crtc_state);
f2b115e6 531 } else if (IS_PINEVIEW(dev)) {
a93e255f 532 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 533 limit = &intel_limits_pineview_lvds;
2177832f 534 else
f2b115e6 535 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 536 } else if (IS_CHERRYVIEW(dev)) {
537 limit = &intel_limits_chv;
a0c4da24 538 } else if (IS_VALLEYVIEW(dev)) {
dc730512 539 limit = &intel_limits_vlv;
a6c45cf0 540 } else if (!IS_GEN2(dev)) {
a93e255f 541 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945 545 } else {
a93e255f 546 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
a93e255f 548 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 549 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 550 else
551 limit = &intel_limits_i8xx_dac;
79e53945
JB		 552 }
553 return limit;
554}
555
dccbea3b
ID		 556/*
557 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
558 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
559 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
560 * The helpers' return value is the rate of the clock that is fed to the
561 * display engine's pipe which can be the above fast dot clock rate or a
562 * divided-down version of it.
563 */
f2b115e6 564/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 565static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 566{
2177832f
SL		 567 clock->m = clock->m2 + 2;
568 clock->p = clock->p1 * clock->p2;
ed5ca77e 569 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 570 return 0;
fb03ac01
VS		 571 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
572 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 573
574 return clock->dot;
2177832f
SL		 575}
576
7429e9d4
DV		 577static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
578{
579 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
580}
581
dccbea3b 582static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 583{
7429e9d4 584 clock->m = i9xx_dpll_compute_m(clock);
79e53945 585 clock->p = clock->p1 * clock->p2;
ed5ca77e 586 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 587 return 0;
fb03ac01
VS		 588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 590
591 return clock->dot;
79e53945
JB		 592}
593
dccbea3b 594static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 595{
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 599 return 0;
589eca67
ID		 600 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
601 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 602
603 return clock->dot / 5;
589eca67
ID		 604}
605
dccbea3b 606int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 607{
608 clock->m = clock->m1 * clock->m2;
609 clock->p = clock->p1 * clock->p2;
610 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 611 return 0;
ef9348c8
CML		 612 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
613 clock->n << 22);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 615
616 return clock->dot / 5;
ef9348c8
CML		 617}
618
7c04d1d9 619#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 620/**
621 * Returns whether the given set of divisors are valid for a given refclk with
622 * the given connectors.
623 */
624
1b894b59
CW		 625static bool intel_PLL_is_valid(struct drm_device *dev,
626 const intel_limit_t *limit,
627 const intel_clock_t *clock)
79e53945 628{
f01b7962
VS		 629 if (clock->n < limit->n.min || limit->n.max < clock->n)
630 INTELPllInvalid("n out of range\n");
79e53945 631 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 632 INTELPllInvalid("p1 out of range\n");
79e53945 633 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 634 INTELPllInvalid("m2 out of range\n");
79e53945 635 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 636 INTELPllInvalid("m1 out of range\n");
f01b7962 637
5ab7b0b7 638 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 639 if (clock->m1 <= clock->m2)
640 INTELPllInvalid("m1 <= m2\n");
641
5ab7b0b7 642 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 643 if (clock->p < limit->p.min || limit->p.max < clock->p)
644 INTELPllInvalid("p out of range\n");
645 if (clock->m < limit->m.min || limit->m.max < clock->m)
646 INTELPllInvalid("m out of range\n");
647 }
648
79e53945 649 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 650 INTELPllInvalid("vco out of range\n");
79e53945
JB		 651 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
652 * connector, etc., rather than just a single range.
653 */
654 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 655 INTELPllInvalid("dot out of range\n");
79e53945
JB		 656
657 return true;
658}
659
3b1429d9
VS		 660static int
661i9xx_select_p2_div(const intel_limit_t *limit,
662 const struct intel_crtc_state *crtc_state,
663 int target)
79e53945 664{
3b1429d9 665 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 666
a93e255f 667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 668 /*
a210b028
DV		 669 * For LVDS just rely on its current settings for dual-channel.
670 * We haven't figured out how to reliably set up different
671 * single/dual channel state, if we even can.
79e53945 672 */
1974cad0 673 if (intel_is_dual_link_lvds(dev))
3b1429d9 674 return limit->p2.p2_fast;
79e53945 675 else
3b1429d9 676 return limit->p2.p2_slow;
79e53945
JB		 677 } else {
678 if (target < limit->p2.dot_limit)
3b1429d9 679 return limit->p2.p2_slow;
79e53945 680 else
3b1429d9 681 return limit->p2.p2_fast;
79e53945 682 }
3b1429d9
VS		 683}
684
685static bool
686i9xx_find_best_dpll(const intel_limit_t *limit,
687 struct intel_crtc_state *crtc_state,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
690{
691 struct drm_device *dev = crtc_state->base.crtc->dev;
692 intel_clock_t clock;
693 int err = target;
79e53945 694
0206e353 695 memset(best_clock, 0, sizeof(*best_clock));
79e53945 696
3b1429d9
VS		 697 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
698
42158660
ZY		 699 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
700 clock.m1++) {
701 for (clock.m2 = limit->m2.min;
702 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 703 if (clock.m2 >= clock.m1)
42158660
ZY		 704 break;
705 for (clock.n = limit->n.min;
706 clock.n <= limit->n.max; clock.n++) {
707 for (clock.p1 = limit->p1.min;
708 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 709 int this_err;
710
dccbea3b 711 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
714 continue;
715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
718
719 this_err = abs(clock.dot - target);
720 if (this_err < err) {
721 *best_clock = clock;
722 err = this_err;
723 }
724 }
725 }
726 }
727 }
728
729 return (err != target);
730}
731
732static bool
a93e255f
ACO		 733pnv_find_best_dpll(const intel_limit_t *limit,
734 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
79e53945 737{
3b1429d9 738 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 739 intel_clock_t clock;
79e53945
JB		 740 int err = target;
741
0206e353 742 memset(best_clock, 0, sizeof(*best_clock));
79e53945 743
3b1429d9
VS		 744 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745
42158660
ZY		 746 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
747 clock.m1++) {
748 for (clock.m2 = limit->m2.min;
749 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 750 for (clock.n = limit->n.min;
751 clock.n <= limit->n.max; clock.n++) {
752 for (clock.p1 = limit->p1.min;
753 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 754 int this_err;
755
dccbea3b 756 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
79e53945 759 continue;
cec2f356
SP		 760 if (match_clock &&
761 clock.p != match_clock->p)
762 continue;
79e53945
JB		 763
764 this_err = abs(clock.dot - target);
765 if (this_err < err) {
766 *best_clock = clock;
767 err = this_err;
768 }
769 }
770 }
771 }
772 }
773
774 return (err != target);
775}
776
d4906093 777static bool
a93e255f
ACO		 778g4x_find_best_dpll(const intel_limit_t *limit,
779 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
d4906093 782{
3b1429d9 783 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 784 intel_clock_t clock;
785 int max_n;
3b1429d9 786 bool found = false;
6ba770dc
AJ		 787 /* approximately equals target * 0.00585 */
788 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 789
790 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 791
792 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
793
d4906093 794 max_n = limit->n.max;
f77f13e2 795 /* based on hardware requirement, prefer smaller n to precision */
d4906093 796 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 797 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 798 for (clock.m1 = limit->m1.max;
799 clock.m1 >= limit->m1.min; clock.m1--) {
800 for (clock.m2 = limit->m2.max;
801 clock.m2 >= limit->m2.min; clock.m2--) {
802 for (clock.p1 = limit->p1.max;
803 clock.p1 >= limit->p1.min; clock.p1--) {
804 int this_err;
805
dccbea3b 806 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 807 if (!intel_PLL_is_valid(dev, limit,
808 &clock))
d4906093 809 continue;
1b894b59
CW		 810
811 this_err = abs(clock.dot - target);
d4906093
ML		 812 if (this_err < err_most) {
813 *best_clock = clock;
814 err_most = this_err;
815 max_n = clock.n;
816 found = true;
817 }
818 }
819 }
820 }
821 }
2c07245f
ZW		 822 return found;
823}
824
d5dd62bd
ID		 825/*
826 * Check if the calculated PLL configuration is more optimal compared to the
827 * best configuration and error found so far. Return the calculated error.
828 */
829static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
830 const intel_clock_t *calculated_clock,
831 const intel_clock_t *best_clock,
832 unsigned int best_error_ppm,
833 unsigned int *error_ppm)
834{
9ca3ba01
ID		 835 /*
836 * For CHV ignore the error and consider only the P value.
837 * Prefer a bigger P value based on HW requirements.
838 */
839 if (IS_CHERRYVIEW(dev)) {
840 *error_ppm = 0;
841
842 return calculated_clock->p > best_clock->p;
843 }
844
24be4e46
ID		 845 if (WARN_ON_ONCE(!target_freq))
846 return false;
847
d5dd62bd
ID		 848 *error_ppm = div_u64(1000000ULL *
849 abs(target_freq - calculated_clock->dot),
850 target_freq);
851 /*
852 * Prefer a better P value over a better (smaller) error if the error
853 * is small. Ensure this preference for future configurations too by
854 * setting the error to 0.
855 */
856 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
857 *error_ppm = 0;
858
859 return true;
860 }
861
862 return *error_ppm + 10 < best_error_ppm;
863}
864
a0c4da24 865static bool
a93e255f
ACO		 866vlv_find_best_dpll(const intel_limit_t *limit,
867 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 868 int target, int refclk, intel_clock_t *match_clock,
869 intel_clock_t *best_clock)
a0c4da24 870{
a93e255f 871 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 872 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 873 intel_clock_t clock;
69e4f900 874 unsigned int bestppm = 1000000;
27e639bf
VS		 875 /* min update 19.2 MHz */
876 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 877 bool found = false;
a0c4da24 878
6b4bf1c4
VS		 879 target *= 5; /* fast clock */
880
881 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 882
883 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 884 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 885 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 886 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 887 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 888 clock.p = clock.p1 * clock.p2;
a0c4da24 889 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 890 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 891 unsigned int ppm;
69e4f900 892
6b4bf1c4
VS		 893 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
894 refclk * clock.m1);
895
dccbea3b 896 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 897
f01b7962
VS		 898 if (!intel_PLL_is_valid(dev, limit,
899 &clock))
43b0ac53
VS		 900 continue;
901
d5dd62bd
ID		 902 if (!vlv_PLL_is_optimal(dev, target,
903 &clock,
904 best_clock,
905 bestppm, &ppm))
906 continue;
6b4bf1c4 907
d5dd62bd
ID		 908 *best_clock = clock;
909 bestppm = ppm;
910 found = true;
a0c4da24
JB		 911 }
912 }
913 }
914 }
a0c4da24 915
49e497ef 916 return found;
a0c4da24 917}
a4fc5ed6 918
ef9348c8 919static bool
a93e255f
ACO		 920chv_find_best_dpll(const intel_limit_t *limit,
921 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 922 int target, int refclk, intel_clock_t *match_clock,
923 intel_clock_t *best_clock)
924{
a93e255f 925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 926 struct drm_device *dev = crtc->base.dev;
9ca3ba01 927 unsigned int best_error_ppm;
ef9348c8
CML		 928 intel_clock_t clock;
929 uint64_t m2;
930 int found = false;
931
932 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 933 best_error_ppm = 1000000;
ef9348c8
CML		 934
935 /*
936 * Based on hardware doc, the n always set to 1, and m1 always
937 * set to 2. If requires to support 200Mhz refclk, we need to
938 * revisit this because n may not 1 anymore.
939 */
940 clock.n = 1, clock.m1 = 2;
941 target *= 5; /* fast clock */
942
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
944 for (clock.p2 = limit->p2.p2_fast;
945 clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 947 unsigned int error_ppm;
ef9348c8
CML		 948
949 clock.p = clock.p1 * clock.p2;
950
951 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
952 clock.n) << 22, refclk * clock.m1);
953
954 if (m2 > INT_MAX/clock.m1)
955 continue;
956
957 clock.m2 = m2;
958
dccbea3b 959 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 960
961 if (!intel_PLL_is_valid(dev, limit, &clock))
962 continue;
963
9ca3ba01
ID		 964 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
965 best_error_ppm, &error_ppm))
966 continue;
967
968 *best_clock = clock;
969 best_error_ppm = error_ppm;
970 found = true;
ef9348c8
CML		 971 }
972 }
973
974 return found;
975}
976
5ab7b0b7
ID		 977bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
978 intel_clock_t *best_clock)
979{
980 int refclk = i9xx_get_refclk(crtc_state, 0);
981
982 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
983 target_clock, refclk, NULL, best_clock);
984}
985
20ddf665
VS		 986bool intel_crtc_active(struct drm_crtc *crtc)
987{
988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
989
990 /* Be paranoid as we can arrive here with only partial
991 * state retrieved from the hardware during setup.
992 *
241bfc38 993 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 994 * as Haswell has gained clock readout/fastboot support.
995 *
66e514c1 996 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 997 * properly reconstruct framebuffers.
c3d1f436
MR		 998 *
999 * FIXME: The intel_crtc->active here should be switched to
1000 * crtc->state->active once we have proper CRTC states wired up
1001 * for atomic.
20ddf665 1002 */
c3d1f436 1003 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1004 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1005}
1006
a5c961d1
PZ		 1007enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1008 enum pipe pipe)
1009{
1010 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1012
6e3c9717 1013 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1014}
1015
fbf49ea2
VS		 1016static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1017{
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 reg = PIPEDSL(pipe);
1020 u32 line1, line2;
1021 u32 line_mask;
1022
1023 if (IS_GEN2(dev))
1024 line_mask = DSL_LINEMASK_GEN2;
1025 else
1026 line_mask = DSL_LINEMASK_GEN3;
1027
1028 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1029 msleep(5);
fbf49ea2
VS		 1030 line2 = I915_READ(reg) & line_mask;
1031
1032 return line1 == line2;
1033}
1034
ab7ad7f6
KP		 1035/*
1036 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1037 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1038 *
1039 * After disabling a pipe, we can't wait for vblank in the usual way,
1040 * spinning on the vblank interrupt status bit, since we won't actually
1041 * see an interrupt when the pipe is disabled.
1042 *
ab7ad7f6
KP		 1043 * On Gen4 and above:
1044 * wait for the pipe register state bit to turn off
1045 *
1046 * Otherwise:
1047 * wait for the display line value to settle (it usually
1048 * ends up stopping at the start of the next frame).
58e10eb9 1049 *
9d0498a2 1050 */
575f7ab7 1051static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1052{
575f7ab7 1053 struct drm_device *dev = crtc->base.dev;
9d0498a2 1054 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1055 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1056 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1057
1058 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1059 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1060
1061 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1062 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1063 100))
284637d9 1064 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1065 } else {
ab7ad7f6 1066 /* Wait for the display line to settle */
fbf49ea2 1067 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1068 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1069 }
79e53945
JB		 1070}
1071
b0ea7d37
DL		 1072/*
1073 * ibx_digital_port_connected - is the specified port connected?
1074 * @dev_priv: i915 private structure
1075 * @port: the port to test
1076 *
1077 * Returns true if @port is connected, false otherwise.
1078 */
1079bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1080 struct intel_digital_port *port)
1081{
1082 u32 bit;
1083
c36346e3 1084 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1085 switch (port->port) {
c36346e3
DL		 1086 case PORT_B:
1087 bit = SDE_PORTB_HOTPLUG;
1088 break;
1089 case PORT_C:
1090 bit = SDE_PORTC_HOTPLUG;
1091 break;
1092 case PORT_D:
1093 bit = SDE_PORTD_HOTPLUG;
1094 break;
1095 default:
1096 return true;
1097 }
1098 } else {
eba905b2 1099 switch (port->port) {
c36346e3
DL		 1100 case PORT_B:
1101 bit = SDE_PORTB_HOTPLUG_CPT;
1102 break;
1103 case PORT_C:
1104 bit = SDE_PORTC_HOTPLUG_CPT;
1105 break;
1106 case PORT_D:
1107 bit = SDE_PORTD_HOTPLUG_CPT;
1108 break;
1109 default:
1110 return true;
1111 }
b0ea7d37
DL		 1112 }
1113
1114 return I915_READ(SDEISR) & bit;
1115}
1116
b24e7179
JB		 1117static const char *state_string(bool enabled)
1118{
1119 return enabled ? "on" : "off";
1120}
1121
1122/* Only for pre-ILK configs */
55607e8a
DV		 1123void assert_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
b24e7179
JB		 1125{
1126 int reg;
1127 u32 val;
1128 bool cur_state;
1129
1130 reg = DPLL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1133 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1134 "PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136}
b24e7179 1137
23538ef1
JN		 1138/* XXX: the dsi pll is shared between MIPI DSI ports */
1139static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1140{
1141 u32 val;
1142 bool cur_state;
1143
a580516d 1144 mutex_lock(&dev_priv->sb_lock);
23538ef1 1145 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1146 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1147
1148 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1149 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1150 "DSI PLL state assertion failure (expected %s, current %s)\n",
1151 state_string(state), state_string(cur_state));
1152}
1153#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1154#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1155
55607e8a 1156struct intel_shared_dpll *
e2b78267
DV		 1157intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1158{
1159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1160
6e3c9717 1161 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1162 return NULL;
1163
6e3c9717 1164 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1165}
1166
040484af 1167/* For ILK+ */
55607e8a
DV		 1168void assert_shared_dpll(struct drm_i915_private *dev_priv,
1169 struct intel_shared_dpll *pll,
1170 bool state)
040484af 1171{
040484af 1172 bool cur_state;
5358901f 1173 struct intel_dpll_hw_state hw_state;
040484af 1174
92b27b08 1175 if (WARN (!pll,
46edb027 1176 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1177 return;
ee7b9f93 1178
5358901f 1179 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1180 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1181 "%s assertion failure (expected %s, current %s)\n",
1182 pll->name, state_string(state), state_string(cur_state));
040484af 1183}
040484af
JB		 1184
1185static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187{
1188 int reg;
1189 u32 val;
1190 bool cur_state;
ad80a810
PZ		 1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192 pipe);
040484af 1193
affa9354
PZ		 1194 if (HAS_DDI(dev_priv->dev)) {
1195 /* DDI does not have a specific FDI_TX register */
ad80a810 1196 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1197 val = I915_READ(reg);
ad80a810 1198 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1199 } else {
1200 reg = FDI_TX_CTL(pipe);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & FDI_TX_ENABLE);
1203 }
e2c719b7 1204 I915_STATE_WARN(cur_state != state,
040484af
JB		 1205 "FDI TX state assertion failure (expected %s, current %s)\n",
1206 state_string(state), state_string(cur_state));
1207}
1208#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1209#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1210
1211static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1212 enum pipe pipe, bool state)
1213{
1214 int reg;
1215 u32 val;
1216 bool cur_state;
1217
d63fa0dc
PZ		 1218 reg = FDI_RX_CTL(pipe);
1219 val = I915_READ(reg);
1220 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1221 I915_STATE_WARN(cur_state != state,
040484af
JB		 1222 "FDI RX state assertion failure (expected %s, current %s)\n",
1223 state_string(state), state_string(cur_state));
1224}
1225#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1226#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1227
1228static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230{
1231 int reg;
1232 u32 val;
1233
1234 /* ILK FDI PLL is always enabled */
3d13ef2e 1235 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1236 return;
1237
bf507ef7 1238 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1239 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1240 return;
1241
040484af
JB		 1242 reg = FDI_TX_CTL(pipe);
1243 val = I915_READ(reg);
e2c719b7 1244 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1245}
1246
55607e8a
DV		 1247void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1248 enum pipe pipe, bool state)
040484af
JB		 1249{
1250 int reg;
1251 u32 val;
55607e8a 1252 bool cur_state;
040484af
JB		 1253
1254 reg = FDI_RX_CTL(pipe);
1255 val = I915_READ(reg);
55607e8a 1256 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1257 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1258 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1259 state_string(state), state_string(cur_state));
040484af
JB		 1260}
1261
b680c37a
DV		 1262void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
ea0760cf 1264{
bedd4dba
JN		 1265 struct drm_device *dev = dev_priv->dev;
1266 int pp_reg;
ea0760cf
JB		 1267 u32 val;
1268 enum pipe panel_pipe = PIPE_A;
0de3b485 1269 bool locked = true;
ea0760cf 1270
bedd4dba
JN		 1271 if (WARN_ON(HAS_DDI(dev)))
1272 return;
1273
1274 if (HAS_PCH_SPLIT(dev)) {
1275 u32 port_sel;
1276
ea0760cf 1277 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1278 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1279
1280 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1281 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1282 panel_pipe = PIPE_B;
1283 /* XXX: else fix for eDP */
1284 } else if (IS_VALLEYVIEW(dev)) {
1285 /* presumably write lock depends on pipe, not port select */
1286 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1287 panel_pipe = pipe;
ea0760cf
JB		 1288 } else {
1289 pp_reg = PP_CONTROL;
bedd4dba
JN		 1290 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1291 panel_pipe = PIPE_B;
ea0760cf
JB		 1292 }
1293
1294 val = I915_READ(pp_reg);
1295 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1296 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1297 locked = false;
1298
e2c719b7 1299 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1300 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1301 pipe_name(pipe));
ea0760cf
JB		 1302}
1303
93ce0ba6
JN		 1304static void assert_cursor(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, bool state)
1306{
1307 struct drm_device *dev = dev_priv->dev;
1308 bool cur_state;
1309
d9d82081 1310 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1311 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1312 else
5efb3e28 1313 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1314
e2c719b7 1315 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1316 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe), state_string(state), state_string(cur_state));
1318}
1319#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1320#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1321
b840d907
JB		 1322void assert_pipe(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
b24e7179
JB		 1324{
1325 int reg;
1326 u32 val;
63d7bbe9 1327 bool cur_state;
702e7a56
PZ		 1328 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1329 pipe);
b24e7179 1330
b6b5d049
VS		 1331 /* if we need the pipe quirk it must be always on */
1332 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1333 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1334 state = true;
1335
f458ebbc 1336 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1337 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1338 cur_state = false;
1339 } else {
1340 reg = PIPECONF(cpu_transcoder);
1341 val = I915_READ(reg);
1342 cur_state = !!(val & PIPECONF_ENABLE);
1343 }
1344
e2c719b7 1345 I915_STATE_WARN(cur_state != state,
63d7bbe9 1346 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1347 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1348}
1349
931872fc
CW		 1350static void assert_plane(struct drm_i915_private *dev_priv,
1351 enum plane plane, bool state)
b24e7179
JB		 1352{
1353 int reg;
1354 u32 val;
931872fc 1355 bool cur_state;
b24e7179
JB		 1356
1357 reg = DSPCNTR(plane);
1358 val = I915_READ(reg);
931872fc 1359 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1360 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1361 "plane %c assertion failure (expected %s, current %s)\n",
1362 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1363}
1364
931872fc
CW		 1365#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1366#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1367
b24e7179
JB		 1368static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370{
653e1026 1371 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1372 int reg, i;
1373 u32 val;
1374 int cur_pipe;
1375
653e1026
VS		 1376 /* Primary planes are fixed to pipes on gen4+ */
1377 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1378 reg = DSPCNTR(pipe);
1379 val = I915_READ(reg);
e2c719b7 1380 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1381 "plane %c assertion failure, should be disabled but not\n",
1382 plane_name(pipe));
19ec1358 1383 return;
28c05794 1384 }
19ec1358 1385
b24e7179 1386 /* Need to check both planes against the pipe */
055e393f 1387 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1388 reg = DSPCNTR(i);
1389 val = I915_READ(reg);
1390 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1391 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1392 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1393 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1394 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1395 }
1396}
1397
19332d7a
JB		 1398static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe)
1400{
20674eef 1401 struct drm_device *dev = dev_priv->dev;
1fe47785 1402 int reg, sprite;
19332d7a
JB		 1403 u32 val;
1404
7feb8b88 1405 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1406 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1407 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1408 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1409 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1410 sprite, pipe_name(pipe));
1411 }
1412 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1413 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1414 reg = SPCNTR(pipe, sprite);
20674eef 1415 val = I915_READ(reg);
e2c719b7 1416 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1418 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1419 }
1420 } else if (INTEL_INFO(dev)->gen >= 7) {
1421 reg = SPRCTL(pipe);
19332d7a 1422 val = I915_READ(reg);
e2c719b7 1423 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1425 plane_name(pipe), pipe_name(pipe));
1426 } else if (INTEL_INFO(dev)->gen >= 5) {
1427 reg = DVSCNTR(pipe);
19332d7a 1428 val = I915_READ(reg);
e2c719b7 1429 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1431 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1432 }
1433}
1434
08c71e5e
VS		 1435static void assert_vblank_disabled(struct drm_crtc *crtc)
1436{
e2c719b7 1437 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1438 drm_crtc_vblank_put(crtc);
1439}
1440
89eff4be 1441static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1442{
1443 u32 val;
1444 bool enabled;
1445
e2c719b7 1446 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1447
92f2584a
JB		 1448 val = I915_READ(PCH_DREF_CONTROL);
1449 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1450 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1451 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1452}
1453
ab9412ba
DV		 1454static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1455 enum pipe pipe)
92f2584a
JB		 1456{
1457 int reg;
1458 u32 val;
1459 bool enabled;
1460
ab9412ba 1461 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1462 val = I915_READ(reg);
1463 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1464 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1465 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1466 pipe_name(pipe));
92f2584a
JB		 1467}
1468
4e634389
KP		 1469static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1471{
1472 if ((val & DP_PORT_EN) == 0)
1473 return false;
1474
1475 if (HAS_PCH_CPT(dev_priv->dev)) {
1476 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1477 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1478 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1479 return false;
44f37d1f
CML		 1480 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1481 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1482 return false;
f0575e92
KP		 1483 } else {
1484 if ((val & DP_PIPE_MASK) != (pipe << 30))
1485 return false;
1486 }
1487 return true;
1488}
1489
1519b995
KP		 1490static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1491 enum pipe pipe, u32 val)
1492{
dc0fa718 1493 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1494 return false;
1495
1496 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1497 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1498 return false;
44f37d1f
CML		 1499 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1500 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1501 return false;
1519b995 1502 } else {
dc0fa718 1503 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1504 return false;
1505 }
1506 return true;
1507}
1508
1509static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511{
1512 if ((val & LVDS_PORT_EN) == 0)
1513 return false;
1514
1515 if (HAS_PCH_CPT(dev_priv->dev)) {
1516 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1517 return false;
1518 } else {
1519 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1520 return false;
1521 }
1522 return true;
1523}
1524
1525static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1526 enum pipe pipe, u32 val)
1527{
1528 if ((val & ADPA_DAC_ENABLE) == 0)
1529 return false;
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
1531 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1532 return false;
1533 } else {
1534 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1535 return false;
1536 }
1537 return true;
1538}
1539
291906f1 1540static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1541 enum pipe pipe, int reg, u32 port_sel)
291906f1 1542{
47a05eca 1543 u32 val = I915_READ(reg);
e2c719b7 1544 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1545 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1546 reg, pipe_name(pipe));
de9a35ab 1547
e2c719b7 1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1549 && (val & DP_PIPEB_SELECT),
de9a35ab 1550 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1551}
1552
1553static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1554 enum pipe pipe, int reg)
1555{
47a05eca 1556 u32 val = I915_READ(reg);
e2c719b7 1557 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1558 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1559 reg, pipe_name(pipe));
de9a35ab 1560
e2c719b7 1561 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1562 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1563 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1564}
1565
1566static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
1568{
1569 int reg;
1570 u32 val;
291906f1 1571
f0575e92
KP		 1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1575
1576 reg = PCH_ADPA;
1577 val = I915_READ(reg);
e2c719b7 1578 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1579 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1580 pipe_name(pipe));
291906f1
JB		 1581
1582 reg = PCH_LVDS;
1583 val = I915_READ(reg);
e2c719b7 1584 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1585 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1586 pipe_name(pipe));
291906f1 1587
e2debe91
PZ		 1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1591}
1592
40e9cf64
JB		 1593static void intel_init_dpio(struct drm_device *dev)
1594{
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597 if (!IS_VALLEYVIEW(dev))
1598 return;
1599
a09caddd
CML		 1600 /*
1601 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1602 * CHV x1 PHY (DP/HDMI D)
1603 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1604 */
1605 if (IS_CHERRYVIEW(dev)) {
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1607 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1608 } else {
1609 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1610 }
5382f5f3
JB		 1611}
1612
d288f65f 1613static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1614 const struct intel_crtc_state *pipe_config)
87442f73 1615{
426115cf
DV		 1616 struct drm_device *dev = crtc->base.dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 int reg = DPLL(crtc->pipe);
d288f65f 1619 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1620
426115cf 1621 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1622
1623 /* No really, not for ILK+ */
1624 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1625
1626 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1627 if (IS_MOBILE(dev_priv->dev))
426115cf 1628 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1629
426115cf
DV		 1630 I915_WRITE(reg, dpll);
1631 POSTING_READ(reg);
1632 udelay(150);
1633
1634 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1636
d288f65f 1637 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1638 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1639
1640 /* We do this three times for luck */
426115cf 1641 I915_WRITE(reg, dpll);
87442f73
DV		 1642 POSTING_READ(reg);
1643 udelay(150); /* wait for warmup */
426115cf 1644 I915_WRITE(reg, dpll);
87442f73
DV		 1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
426115cf 1647 I915_WRITE(reg, dpll);
87442f73
DV		 1648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
1650}
1651
d288f65f 1652static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1653 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1654{
1655 struct drm_device *dev = crtc->base.dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 int pipe = crtc->pipe;
1658 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1659 u32 tmp;
1660
1661 assert_pipe_disabled(dev_priv, crtc->pipe);
1662
1663 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1664
a580516d 1665 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1666
1667 /* Enable back the 10bit clock to display controller */
1668 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1669 tmp |= DPIO_DCLKP_EN;
1670 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1671
54433e91
VS		 1672 mutex_unlock(&dev_priv->sb_lock);
1673
9d556c99
CML		 1674 /*
1675 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1676 */
1677 udelay(1);
1678
1679 /* Enable PLL */
d288f65f 1680 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1681
1682 /* Check PLL is locked */
a11b0703 1683 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1684 DRM_ERROR("PLL %d failed to lock\n", pipe);
1685
a11b0703 1686 /* not sure when this should be written */
d288f65f 1687 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1688 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1689}
1690
1c4e0274
VS		 1691static int intel_num_dvo_pipes(struct drm_device *dev)
1692{
1693 struct intel_crtc *crtc;
1694 int count = 0;
1695
1696 for_each_intel_crtc(dev, crtc)
3538b9df 1697 count += crtc->base.state->active &&
409ee761 1698 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1699
1700 return count;
1701}
1702
66e3d5c0 1703static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1704{
66e3d5c0
DV		 1705 struct drm_device *dev = crtc->base.dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 int reg = DPLL(crtc->pipe);
6e3c9717 1708 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1709
66e3d5c0 1710 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1711
63d7bbe9 1712 /* No really, not for ILK+ */
3d13ef2e 1713 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1714
1715 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1716 if (IS_MOBILE(dev) && !IS_I830(dev))
1717 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1718
1c4e0274
VS		 1719 /* Enable DVO 2x clock on both PLLs if necessary */
1720 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1721 /*
1722 * It appears to be important that we don't enable this
1723 * for the current pipe before otherwise configuring the
1724 * PLL. No idea how this should be handled if multiple
1725 * DVO outputs are enabled simultaneosly.
1726 */
1727 dpll |= DPLL_DVO_2X_MODE;
1728 I915_WRITE(DPLL(!crtc->pipe),
1729 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1730 }
66e3d5c0
DV		 1731
1732 /* Wait for the clocks to stabilize. */
1733 POSTING_READ(reg);
1734 udelay(150);
1735
1736 if (INTEL_INFO(dev)->gen >= 4) {
1737 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1738 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1739 } else {
1740 /* The pixel multiplier can only be updated once the
1741 * DPLL is enabled and the clocks are stable.
1742 *
1743 * So write it again.
1744 */
1745 I915_WRITE(reg, dpll);
1746 }
63d7bbe9
JB		 1747
1748 /* We do this three times for luck */
66e3d5c0 1749 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1750 POSTING_READ(reg);
1751 udelay(150); /* wait for warmup */
66e3d5c0 1752 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1753 POSTING_READ(reg);
1754 udelay(150); /* wait for warmup */
66e3d5c0 1755 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1756 POSTING_READ(reg);
1757 udelay(150); /* wait for warmup */
1758}
1759
1760/**
50b44a44 1761 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1762 * @dev_priv: i915 private structure
1763 * @pipe: pipe PLL to disable
1764 *
1765 * Disable the PLL for @pipe, making sure the pipe is off first.
1766 *
1767 * Note! This is for pre-ILK only.
1768 */
1c4e0274 1769static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1770{
1c4e0274
VS		 1771 struct drm_device *dev = crtc->base.dev;
1772 struct drm_i915_private *dev_priv = dev->dev_private;
1773 enum pipe pipe = crtc->pipe;
1774
1775 /* Disable DVO 2x clock on both PLLs if necessary */
1776 if (IS_I830(dev) &&
409ee761 1777 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1778 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1779 I915_WRITE(DPLL(PIPE_B),
1780 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1781 I915_WRITE(DPLL(PIPE_A),
1782 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1783 }
1784
b6b5d049
VS		 1785 /* Don't disable pipe or pipe PLLs if needed */
1786 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1787 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1788 return;
1789
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
1792
b8afb911 1793 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1794 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1795}
1796
f6071166
JB		 1797static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1798{
b8afb911 1799 u32 val;
f6071166
JB		 1800
1801 /* Make sure the pipe isn't still relying on us */
1802 assert_pipe_disabled(dev_priv, pipe);
1803
e5cbfbfb
ID		 1804 /*
1805 * Leave integrated clock source and reference clock enabled for pipe B.
1806 * The latter is needed for VGA hotplug / manual detection.
1807 */
b8afb911 1808 val = DPLL_VGA_MODE_DIS;
f6071166 1809 if (pipe == PIPE_B)
e5cbfbfb 1810 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1811 I915_WRITE(DPLL(pipe), val);
1812 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1813
1814}
1815
1816static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1817{
d752048d 1818 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1819 u32 val;
1820
a11b0703
VS		 1821 /* Make sure the pipe isn't still relying on us */
1822 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1823
a11b0703 1824 /* Set PLL en = 0 */
b8afb911
VS		 1825 val = DPLL_SSC_REF_CLOCK_CHV |
1826 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1827 if (pipe != PIPE_A)
1828 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1829 I915_WRITE(DPLL(pipe), val);
1830 POSTING_READ(DPLL(pipe));
d752048d 1831
a580516d 1832 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1833
1834 /* Disable 10bit clock to display controller */
1835 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1836 val &= ~DPIO_DCLKP_EN;
1837 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1838
61407f6d
VS		 1839 /* disable left/right clock distribution */
1840 if (pipe != PIPE_B) {
1841 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1842 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1843 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1844 } else {
1845 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1846 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1847 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1848 }
1849
a580516d 1850 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1851}
1852
e4607fcf 1853void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1854 struct intel_digital_port *dport,
1855 unsigned int expected_mask)
89b667f8
JB		 1856{
1857 u32 port_mask;
00fc31b7 1858 int dpll_reg;
89b667f8 1859
e4607fcf
CML		 1860 switch (dport->port) {
1861 case PORT_B:
89b667f8 1862 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1863 dpll_reg = DPLL(0);
e4607fcf
CML		 1864 break;
1865 case PORT_C:
89b667f8 1866 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1867 dpll_reg = DPLL(0);
9b6de0a1 1868 expected_mask <<= 4;
00fc31b7
CML		 1869 break;
1870 case PORT_D:
1871 port_mask = DPLL_PORTD_READY_MASK;
1872 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1873 break;
1874 default:
1875 BUG();
1876 }
89b667f8 1877
9b6de0a1
VS		 1878 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1879 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1880 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1881}
1882
b14b1055
DV		 1883static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1884{
1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
be19f0ff
CW		 1889 if (WARN_ON(pll == NULL))
1890 return;
1891
3e369b76 1892 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1893 if (pll->active == 0) {
1894 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1895 WARN_ON(pll->on);
1896 assert_shared_dpll_disabled(dev_priv, pll);
1897
1898 pll->mode_set(dev_priv, pll);
1899 }
1900}
1901
92f2584a 1902/**
85b3894f 1903 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1904 * @dev_priv: i915 private structure
1905 * @pipe: pipe PLL to enable
1906 *
1907 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1908 * drives the transcoder clock.
1909 */
85b3894f 1910static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1911{
3d13ef2e
DL		 1912 struct drm_device *dev = crtc->base.dev;
1913 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1914 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1915
87a875bb 1916 if (WARN_ON(pll == NULL))
48da64a8
CW		 1917 return;
1918
3e369b76 1919 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1920 return;
ee7b9f93 1921
74dd6928 1922 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1923 pll->name, pll->active, pll->on,
e2b78267 1924 crtc->base.base.id);
92f2584a 1925
cdbd2316
DV		 1926 if (pll->active++) {
1927 WARN_ON(!pll->on);
e9d6944e 1928 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1929 return;
1930 }
f4a091c7 1931 WARN_ON(pll->on);
ee7b9f93 1932
bd2bb1b9
PZ		 1933 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1934
46edb027 1935 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1936 pll->enable(dev_priv, pll);
ee7b9f93 1937 pll->on = true;
92f2584a
JB		 1938}
1939
f6daaec2 1940static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1941{
3d13ef2e
DL		 1942 struct drm_device *dev = crtc->base.dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1944 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1945
92f2584a 1946 /* PCH only available on ILK+ */
3d13ef2e 1947 BUG_ON(INTEL_INFO(dev)->gen < 5);
eddfcbcd
ML		 1948 if (pll == NULL)
1949 return;
92f2584a 1950
eddfcbcd 1951 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1952 return;
7a419866 1953
46edb027
DV		 1954 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1955 pll->name, pll->active, pll->on,
e2b78267 1956 crtc->base.base.id);
7a419866 1957
48da64a8 1958 if (WARN_ON(pll->active == 0)) {
e9d6944e 1959 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1960 return;
1961 }
1962
e9d6944e 1963 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1964 WARN_ON(!pll->on);
cdbd2316 1965 if (--pll->active)
7a419866 1966 return;
ee7b9f93 1967
46edb027 1968 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1969 pll->disable(dev_priv, pll);
ee7b9f93 1970 pll->on = false;
bd2bb1b9
PZ		 1971
1972 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1973}
1974
b8a4f404
PZ		 1975static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1976 enum pipe pipe)
040484af 1977{
23670b32 1978 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1979 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1981 uint32_t reg, val, pipeconf_val;
040484af
JB		 1982
1983 /* PCH only available on ILK+ */
55522f37 1984 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1985
1986 /* Make sure PCH DPLL is enabled */
e72f9fbf 1987 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1988 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1989
1990 /* FDI must be feeding us bits for PCH ports */
1991 assert_fdi_tx_enabled(dev_priv, pipe);
1992 assert_fdi_rx_enabled(dev_priv, pipe);
1993
23670b32
DV		 1994 if (HAS_PCH_CPT(dev)) {
1995 /* Workaround: Set the timing override bit before enabling the
1996 * pch transcoder. */
1997 reg = TRANS_CHICKEN2(pipe);
1998 val = I915_READ(reg);
1999 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2000 I915_WRITE(reg, val);
59c859d6 2001 }
23670b32 2002
ab9412ba 2003 reg = PCH_TRANSCONF(pipe);
040484af 2004 val = I915_READ(reg);
5f7f726d 2005 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2006
2007 if (HAS_PCH_IBX(dev_priv->dev)) {
2008 /*
c5de7c6f
VS		 2009 * Make the BPC in transcoder be consistent with
2010 * that in pipeconf reg. For HDMI we must use 8bpc
2011 * here for both 8bpc and 12bpc.
e9bcff5c 2012 */
dfd07d72 2013 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2014 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2015 val |= PIPECONF_8BPC;
2016 else
2017 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2018 }
5f7f726d
PZ		 2019
2020 val &= ~TRANS_INTERLACE_MASK;
2021 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2022 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2023 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2024 val |= TRANS_LEGACY_INTERLACED_ILK;
2025 else
2026 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2027 else
2028 val |= TRANS_PROGRESSIVE;
2029
040484af
JB		 2030 I915_WRITE(reg, val | TRANS_ENABLE);
2031 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2032 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2033}
2034
8fb033d7 2035static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2036 enum transcoder cpu_transcoder)
040484af 2037{
8fb033d7 2038 u32 val, pipeconf_val;
8fb033d7
PZ		 2039
2040 /* PCH only available on ILK+ */
55522f37 2041 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2042
8fb033d7 2043 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2044 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2045 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2046
223a6fdf
PZ		 2047 /* Workaround: set timing override bit. */
2048 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2049 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2050 I915_WRITE(_TRANSA_CHICKEN2, val);
2051
25f3ef11 2052 val = TRANS_ENABLE;
937bb610 2053 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2054
9a76b1c6
PZ		 2055 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2056 PIPECONF_INTERLACED_ILK)
a35f2679 2057 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2058 else
2059 val |= TRANS_PROGRESSIVE;
2060
ab9412ba
DV		 2061 I915_WRITE(LPT_TRANSCONF, val);
2062 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2063 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2064}
2065
b8a4f404
PZ		 2066static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2067 enum pipe pipe)
040484af 2068{
23670b32
DV		 2069 struct drm_device *dev = dev_priv->dev;
2070 uint32_t reg, val;
040484af
JB		 2071
2072 /* FDI relies on the transcoder */
2073 assert_fdi_tx_disabled(dev_priv, pipe);
2074 assert_fdi_rx_disabled(dev_priv, pipe);
2075
291906f1
JB		 2076 /* Ports must be off as well */
2077 assert_pch_ports_disabled(dev_priv, pipe);
2078
ab9412ba 2079 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2080 val = I915_READ(reg);
2081 val &= ~TRANS_ENABLE;
2082 I915_WRITE(reg, val);
2083 /* wait for PCH transcoder off, transcoder state */
2084 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2085 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2086
2087 if (!HAS_PCH_IBX(dev)) {
2088 /* Workaround: Clear the timing override chicken bit again. */
2089 reg = TRANS_CHICKEN2(pipe);
2090 val = I915_READ(reg);
2091 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2092 I915_WRITE(reg, val);
2093 }
040484af
JB		 2094}
2095
ab4d966c 2096static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2097{
8fb033d7
PZ		 2098 u32 val;
2099
ab9412ba 2100 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2101 val &= ~TRANS_ENABLE;
ab9412ba 2102 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2103 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2104 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2105 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2106
2107 /* Workaround: clear timing override bit. */
2108 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2109 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2110 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2111}
2112
b24e7179 2113/**
309cfea8 2114 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2115 * @crtc: crtc responsible for the pipe
b24e7179 2116 *
0372264a 2117 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2118 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2119 */
e1fdc473 2120static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2121{
0372264a
PZ		 2122 struct drm_device *dev = crtc->base.dev;
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2124 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2126 pipe);
1a240d4d 2127 enum pipe pch_transcoder;
b24e7179
JB		 2128 int reg;
2129 u32 val;
2130
9e2ee2dd
VS		 2131 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2132
58c6eaa2 2133 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2134 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2135 assert_sprites_disabled(dev_priv, pipe);
2136
681e5811 2137 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2138 pch_transcoder = TRANSCODER_A;
2139 else
2140 pch_transcoder = pipe;
2141
b24e7179
JB		 2142 /*
2143 * A pipe without a PLL won't actually be able to drive bits from
2144 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2145 * need the check.
2146 */
50360403 2147 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2148 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2149 assert_dsi_pll_enabled(dev_priv);
2150 else
2151 assert_pll_enabled(dev_priv, pipe);
040484af 2152 else {
6e3c9717 2153 if (crtc->config->has_pch_encoder) {
040484af 2154 /* if driving the PCH, we need FDI enabled */
cc391bbb 2155 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2156 assert_fdi_tx_pll_enabled(dev_priv,
2157 (enum pipe) cpu_transcoder);
040484af
JB		 2158 }
2159 /* FIXME: assert CPU port conditions for SNB+ */
2160 }
b24e7179 2161
702e7a56 2162 reg = PIPECONF(cpu_transcoder);
b24e7179 2163 val = I915_READ(reg);
7ad25d48 2164 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2165 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2166 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2167 return;
7ad25d48 2168 }
00d70b15
CW		 2169
2170 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2171 POSTING_READ(reg);
b24e7179
JB		 2172}
2173
2174/**
309cfea8 2175 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2176 * @crtc: crtc whose pipes is to be disabled
b24e7179 2177 *
575f7ab7
VS		 2178 * Disable the pipe of @crtc, making sure that various hardware
2179 * specific requirements are met, if applicable, e.g. plane
2180 * disabled, panel fitter off, etc.
b24e7179
JB		 2181 *
2182 * Will wait until the pipe has shut down before returning.
2183 */
575f7ab7 2184static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2185{
575f7ab7 2186 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2187 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2188 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2189 int reg;
2190 u32 val;
2191
9e2ee2dd
VS		 2192 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2193
b24e7179
JB		 2194 /*
2195 * Make sure planes won't keep trying to pump pixels to us,
2196 * or we might hang the display.
2197 */
2198 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2199 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2200 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2201
702e7a56 2202 reg = PIPECONF(cpu_transcoder);
b24e7179 2203 val = I915_READ(reg);
00d70b15
CW		 2204 if ((val & PIPECONF_ENABLE) == 0)
2205 return;
2206
67adc644
VS		 2207 /*
2208 * Double wide has implications for planes
2209 * so best keep it disabled when not needed.
2210 */
6e3c9717 2211 if (crtc->config->double_wide)
67adc644
VS		 2212 val &= ~PIPECONF_DOUBLE_WIDE;
2213
2214 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2215 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2216 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2217 val &= ~PIPECONF_ENABLE;
2218
2219 I915_WRITE(reg, val);
2220 if ((val & PIPECONF_ENABLE) == 0)
2221 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2222}
2223
693db184
CW		 2224static bool need_vtd_wa(struct drm_device *dev)
2225{
2226#ifdef CONFIG_INTEL_IOMMU
2227 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2228 return true;
2229#endif
2230 return false;
2231}
2232
50470bb0 2233unsigned int
6761dd31
TU		 2234intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2235 uint64_t fb_format_modifier)
a57ce0b2 2236{
6761dd31
TU		 2237 unsigned int tile_height;
2238 uint32_t pixel_bytes;
a57ce0b2 2239
b5d0e9bf
DL		 2240 switch (fb_format_modifier) {
2241 case DRM_FORMAT_MOD_NONE:
2242 tile_height = 1;
2243 break;
2244 case I915_FORMAT_MOD_X_TILED:
2245 tile_height = IS_GEN2(dev) ? 16 : 8;
2246 break;
2247 case I915_FORMAT_MOD_Y_TILED:
2248 tile_height = 32;
2249 break;
2250 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2251 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2252 switch (pixel_bytes) {
b5d0e9bf 2253 default:
6761dd31 2254 case 1:
b5d0e9bf
DL		 2255 tile_height = 64;
2256 break;
6761dd31
TU		 2257 case 2:
2258 case 4:
b5d0e9bf
DL		 2259 tile_height = 32;
2260 break;
6761dd31 2261 case 8:
b5d0e9bf
DL		 2262 tile_height = 16;
2263 break;
6761dd31 2264 case 16:
b5d0e9bf
DL		 2265 WARN_ONCE(1,
2266 "128-bit pixels are not supported for display!");
2267 tile_height = 16;
2268 break;
2269 }
2270 break;
2271 default:
2272 MISSING_CASE(fb_format_modifier);
2273 tile_height = 1;
2274 break;
2275 }
091df6cb 2276
6761dd31
TU		 2277 return tile_height;
2278}
2279
2280unsigned int
2281intel_fb_align_height(struct drm_device *dev, unsigned int height,
2282 uint32_t pixel_format, uint64_t fb_format_modifier)
2283{
2284 return ALIGN(height, intel_tile_height(dev, pixel_format,
2285 fb_format_modifier));
a57ce0b2
JB		 2286}
2287
f64b98cd
TU		 2288static int
2289intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2290 const struct drm_plane_state *plane_state)
2291{
50470bb0 2292 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2293 unsigned int tile_height, tile_pitch;
50470bb0 2294
f64b98cd
TU		 2295 *view = i915_ggtt_view_normal;
2296
50470bb0
TU		 2297 if (!plane_state)
2298 return 0;
2299
121920fa 2300 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2301 return 0;
2302
9abc4648 2303 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2304
2305 info->height = fb->height;
2306 info->pixel_format = fb->pixel_format;
2307 info->pitch = fb->pitches[0];
2308 info->fb_modifier = fb->modifier[0];
2309
84fe03f7
TU		 2310 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2311 fb->modifier[0]);
2312 tile_pitch = PAGE_SIZE / tile_height;
2313 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2314 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2315 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2316
f64b98cd
TU		 2317 return 0;
2318}
2319
4e9a86b6
VS		 2320static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2321{
2322 if (INTEL_INFO(dev_priv)->gen >= 9)
2323 return 256 * 1024;
985b8bb4
VS		 2324 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2325 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2326 return 128 * 1024;
2327 else if (INTEL_INFO(dev_priv)->gen >= 4)
2328 return 4 * 1024;
2329 else
44c5905e 2330 return 0;
4e9a86b6
VS		 2331}
2332
127bd2ac 2333int
850c4cdc
TU		 2334intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2335 struct drm_framebuffer *fb,
82bc3b2d 2336 const struct drm_plane_state *plane_state,
91af127f
JH		 2337 struct intel_engine_cs *pipelined,
2338 struct drm_i915_gem_request **pipelined_request)
6b95a207 2339{
850c4cdc 2340 struct drm_device *dev = fb->dev;
ce453d81 2341 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2342 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2343 struct i915_ggtt_view view;
6b95a207
KH		 2344 u32 alignment;
2345 int ret;
2346
ebcdd39e
MR		 2347 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2348
7b911adc
TU		 2349 switch (fb->modifier[0]) {
2350 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2351 alignment = intel_linear_alignment(dev_priv);
6b95a207 2352 break;
7b911adc 2353 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2354 if (INTEL_INFO(dev)->gen >= 9)
2355 alignment = 256 * 1024;
2356 else {
2357 /* pin() will align the object as required by fence */
2358 alignment = 0;
2359 }
6b95a207 2360 break;
7b911adc 2361 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2362 case I915_FORMAT_MOD_Yf_TILED:
2363 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2364 "Y tiling bo slipped through, driver bug!\n"))
2365 return -EINVAL;
2366 alignment = 1 * 1024 * 1024;
2367 break;
6b95a207 2368 default:
7b911adc
TU		 2369 MISSING_CASE(fb->modifier[0]);
2370 return -EINVAL;
6b95a207
KH		 2371 }
2372
f64b98cd
TU		 2373 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2374 if (ret)
2375 return ret;
2376
693db184
CW		 2377 /* Note that the w/a also requires 64 PTE of padding following the
2378 * bo. We currently fill all unused PTE with the shadow page and so
2379 * we should always have valid PTE following the scanout preventing
2380 * the VT-d warning.
2381 */
2382 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2383 alignment = 256 * 1024;
2384
d6dd6843
PZ		 2385 /*
2386 * Global gtt pte registers are special registers which actually forward
2387 * writes to a chunk of system memory. Which means that there is no risk
2388 * that the register values disappear as soon as we call
2389 * intel_runtime_pm_put(), so it is correct to wrap only the
2390 * pin/unpin/fence and not more.
2391 */
2392 intel_runtime_pm_get(dev_priv);
2393
ce453d81 2394 dev_priv->mm.interruptible = false;
e6617330 2395 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2396 pipelined_request, &view);
48b956c5 2397 if (ret)
ce453d81 2398 goto err_interruptible;
6b95a207
KH		 2399
2400 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2401 * fence, whereas 965+ only requires a fence if using
2402 * framebuffer compression. For simplicity, we always install
2403 * a fence as the cost is not that onerous.
2404 */
06d98131 2405 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2406 if (ret)
2407 goto err_unpin;
1690e1eb 2408
9a5a53b3 2409 i915_gem_object_pin_fence(obj);
6b95a207 2410
ce453d81 2411 dev_priv->mm.interruptible = true;
d6dd6843 2412 intel_runtime_pm_put(dev_priv);
6b95a207 2413 return 0;
48b956c5
CW		 2414
2415err_unpin:
f64b98cd 2416 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2417err_interruptible:
2418 dev_priv->mm.interruptible = true;
d6dd6843 2419 intel_runtime_pm_put(dev_priv);
48b956c5 2420 return ret;
6b95a207
KH		 2421}
2422
82bc3b2d
TU		 2423static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2424 const struct drm_plane_state *plane_state)
1690e1eb 2425{
82bc3b2d 2426 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2427 struct i915_ggtt_view view;
2428 int ret;
82bc3b2d 2429
ebcdd39e
MR		 2430 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2431
f64b98cd
TU		 2432 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2433 WARN_ONCE(ret, "Couldn't get view from plane state!");
2434
1690e1eb 2435 i915_gem_object_unpin_fence(obj);
f64b98cd 2436 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2437}
2438
c2c75131
DV		 2439/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2440 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2441unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2442 int *x, int *y,
bc752862
CW		 2443 unsigned int tiling_mode,
2444 unsigned int cpp,
2445 unsigned int pitch)
c2c75131 2446{
bc752862
CW		 2447 if (tiling_mode != I915_TILING_NONE) {
2448 unsigned int tile_rows, tiles;
c2c75131 2449
bc752862
CW		 2450 tile_rows = *y / 8;
2451 *y %= 8;
c2c75131 2452
bc752862
CW		 2453 tiles = *x / (512/cpp);
2454 *x %= 512/cpp;
2455
2456 return tile_rows * pitch * 8 + tiles * 4096;
2457 } else {
4e9a86b6 2458 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2459 unsigned int offset;
2460
2461 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2462 *y = (offset & alignment) / pitch;
2463 *x = ((offset & alignment) - *y * pitch) / cpp;
2464 return offset & ~alignment;
bc752862 2465 }
c2c75131
DV		 2466}
2467
b35d63fa 2468static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2469{
2470 switch (format) {
2471 case DISPPLANE_8BPP:
2472 return DRM_FORMAT_C8;
2473 case DISPPLANE_BGRX555:
2474 return DRM_FORMAT_XRGB1555;
2475 case DISPPLANE_BGRX565:
2476 return DRM_FORMAT_RGB565;
2477 default:
2478 case DISPPLANE_BGRX888:
2479 return DRM_FORMAT_XRGB8888;
2480 case DISPPLANE_RGBX888:
2481 return DRM_FORMAT_XBGR8888;
2482 case DISPPLANE_BGRX101010:
2483 return DRM_FORMAT_XRGB2101010;
2484 case DISPPLANE_RGBX101010:
2485 return DRM_FORMAT_XBGR2101010;
2486 }
2487}
2488
bc8d7dff
DL		 2489static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2490{
2491 switch (format) {
2492 case PLANE_CTL_FORMAT_RGB_565:
2493 return DRM_FORMAT_RGB565;
2494 default:
2495 case PLANE_CTL_FORMAT_XRGB_8888:
2496 if (rgb_order) {
2497 if (alpha)
2498 return DRM_FORMAT_ABGR8888;
2499 else
2500 return DRM_FORMAT_XBGR8888;
2501 } else {
2502 if (alpha)
2503 return DRM_FORMAT_ARGB8888;
2504 else
2505 return DRM_FORMAT_XRGB8888;
2506 }
2507 case PLANE_CTL_FORMAT_XRGB_2101010:
2508 if (rgb_order)
2509 return DRM_FORMAT_XBGR2101010;
2510 else
2511 return DRM_FORMAT_XRGB2101010;
2512 }
2513}
2514
5724dbd1 2515static bool
f6936e29
DV		 2516intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2517 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2518{
2519 struct drm_device *dev = crtc->base.dev;
2520 struct drm_i915_gem_object *obj = NULL;
2521 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2522 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2523 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2524 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2525 PAGE_SIZE);
2526
2527 size_aligned -= base_aligned;
46f297fb 2528
ff2652ea
CW		 2529 if (plane_config->size == 0)
2530 return false;
2531
f37b5c2b
DV		 2532 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2533 base_aligned,
2534 base_aligned,
2535 size_aligned);
46f297fb 2536 if (!obj)
484b41dd 2537 return false;
46f297fb 2538
49af449b
DL		 2539 obj->tiling_mode = plane_config->tiling;
2540 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2541 obj->stride = fb->pitches[0];
46f297fb 2542
6bf129df
DL		 2543 mode_cmd.pixel_format = fb->pixel_format;
2544 mode_cmd.width = fb->width;
2545 mode_cmd.height = fb->height;
2546 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2547 mode_cmd.modifier[0] = fb->modifier[0];
2548 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2549
2550 mutex_lock(&dev->struct_mutex);
6bf129df 2551 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2552 &mode_cmd, obj)) {
46f297fb
JB		 2553 DRM_DEBUG_KMS("intel fb init failed\n");
2554 goto out_unref_obj;
2555 }
46f297fb 2556 mutex_unlock(&dev->struct_mutex);
484b41dd 2557
f6936e29 2558 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2559 return true;
46f297fb
JB		 2560
2561out_unref_obj:
2562 drm_gem_object_unreference(&obj->base);
2563 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2564 return false;
2565}
2566
afd65eb4
MR		 2567/* Update plane->state->fb to match plane->fb after driver-internal updates */
2568static void
2569update_state_fb(struct drm_plane *plane)
2570{
2571 if (plane->fb == plane->state->fb)
2572 return;
2573
2574 if (plane->state->fb)
2575 drm_framebuffer_unreference(plane->state->fb);
2576 plane->state->fb = plane->fb;
2577 if (plane->state->fb)
2578 drm_framebuffer_reference(plane->state->fb);
2579}
2580
5724dbd1 2581static void
f6936e29
DV		 2582intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2583 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2584{
2585 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2586 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2587 struct drm_crtc *c;
2588 struct intel_crtc *i;
2ff8fde1 2589 struct drm_i915_gem_object *obj;
88595ac9
DV		 2590 struct drm_plane *primary = intel_crtc->base.primary;
2591 struct drm_framebuffer *fb;
484b41dd 2592
2d14030b 2593 if (!plane_config->fb)
484b41dd
JB		 2594 return;
2595
f6936e29 2596 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2597 fb = &plane_config->fb->base;
2598 goto valid_fb;
f55548b5 2599 }
484b41dd 2600
2d14030b 2601 kfree(plane_config->fb);
484b41dd
JB		 2602
2603 /*
2604 * Failed to alloc the obj, check to see if we should share
2605 * an fb with another CRTC instead
2606 */
70e1e0ec 2607 for_each_crtc(dev, c) {
484b41dd
JB		 2608 i = to_intel_crtc(c);
2609
2610 if (c == &intel_crtc->base)
2611 continue;
2612
2ff8fde1
MR		 2613 if (!i->active)
2614 continue;
2615
88595ac9
DV		 2616 fb = c->primary->fb;
2617 if (!fb)
484b41dd
JB		 2618 continue;
2619
88595ac9 2620 obj = intel_fb_obj(fb);
2ff8fde1 2621 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2622 drm_framebuffer_reference(fb);
2623 goto valid_fb;
484b41dd
JB		 2624 }
2625 }
88595ac9
DV		 2626
2627 return;
2628
2629valid_fb:
2630 obj = intel_fb_obj(fb);
2631 if (obj->tiling_mode != I915_TILING_NONE)
2632 dev_priv->preserve_bios_swizzle = true;
2633
2634 primary->fb = fb;
36750f28 2635 primary->crtc = primary->state->crtc = &intel_crtc->base;
88595ac9 2636 update_state_fb(primary);
36750f28 2637 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2638 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2639}
2640
29b9bde6
DV		 2641static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2642 struct drm_framebuffer *fb,
2643 int x, int y)
81255565
JB		 2644{
2645 struct drm_device *dev = crtc->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2648 struct drm_plane *primary = crtc->primary;
2649 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2650 struct drm_i915_gem_object *obj;
81255565 2651 int plane = intel_crtc->plane;
e506a0c6 2652 unsigned long linear_offset;
81255565 2653 u32 dspcntr;
f45651ba 2654 u32 reg = DSPCNTR(plane);
48404c1e 2655 int pixel_size;
f45651ba 2656
b70709a6 2657 if (!visible || !fb) {
fdd508a6
VS		 2658 I915_WRITE(reg, 0);
2659 if (INTEL_INFO(dev)->gen >= 4)
2660 I915_WRITE(DSPSURF(plane), 0);
2661 else
2662 I915_WRITE(DSPADDR(plane), 0);
2663 POSTING_READ(reg);
2664 return;
2665 }
2666
c9ba6fad
VS		 2667 obj = intel_fb_obj(fb);
2668 if (WARN_ON(obj == NULL))
2669 return;
2670
2671 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2672
f45651ba
VS		 2673 dspcntr = DISPPLANE_GAMMA_ENABLE;
2674
fdd508a6 2675 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2676
2677 if (INTEL_INFO(dev)->gen < 4) {
2678 if (intel_crtc->pipe == PIPE_B)
2679 dspcntr |= DISPPLANE_SEL_PIPE_B;
2680
2681 /* pipesrc and dspsize control the size that is scaled from,
2682 * which should always be the user's requested size.
2683 */
2684 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2685 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2686 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2687 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2688 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2689 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2690 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2691 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2692 I915_WRITE(PRIMPOS(plane), 0);
2693 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2694 }
81255565 2695
57779d06
VS		 2696 switch (fb->pixel_format) {
2697 case DRM_FORMAT_C8:
81255565
JB		 2698 dspcntr |= DISPPLANE_8BPP;
2699 break;
57779d06 2700 case DRM_FORMAT_XRGB1555:
57779d06 2701 dspcntr |= DISPPLANE_BGRX555;
81255565 2702 break;
57779d06
VS		 2703 case DRM_FORMAT_RGB565:
2704 dspcntr |= DISPPLANE_BGRX565;
2705 break;
2706 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2707 dspcntr |= DISPPLANE_BGRX888;
2708 break;
2709 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2710 dspcntr |= DISPPLANE_RGBX888;
2711 break;
2712 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2713 dspcntr |= DISPPLANE_BGRX101010;
2714 break;
2715 case DRM_FORMAT_XBGR2101010:
57779d06 2716 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2717 break;
2718 default:
baba133a 2719 BUG();
81255565 2720 }
57779d06 2721
f45651ba
VS		 2722 if (INTEL_INFO(dev)->gen >= 4 &&
2723 obj->tiling_mode != I915_TILING_NONE)
2724 dspcntr |= DISPPLANE_TILED;
81255565 2725
de1aa629
VS		 2726 if (IS_G4X(dev))
2727 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2728
b9897127 2729 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2730
c2c75131
DV		 2731 if (INTEL_INFO(dev)->gen >= 4) {
2732 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2733 intel_gen4_compute_page_offset(dev_priv,
2734 &x, &y, obj->tiling_mode,
b9897127 2735 pixel_size,
bc752862 2736 fb->pitches[0]);
c2c75131
DV		 2737 linear_offset -= intel_crtc->dspaddr_offset;
2738 } else {
e506a0c6 2739 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2740 }
e506a0c6 2741
8e7d688b 2742 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2743 dspcntr |= DISPPLANE_ROTATE_180;
2744
6e3c9717
ACO		 2745 x += (intel_crtc->config->pipe_src_w - 1);
2746 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2747
2748 /* Finding the last pixel of the last line of the display
2749 data and adding to linear_offset*/
2750 linear_offset +=
6e3c9717
ACO		 2751 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2752 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2753 }
2754
2755 I915_WRITE(reg, dspcntr);
2756
01f2c773 2757 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2758 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2759 I915_WRITE(DSPSURF(plane),
2760 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2761 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2762 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2763 } else
f343c5f6 2764 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2765 POSTING_READ(reg);
17638cd6
JB		 2766}
2767
29b9bde6
DV		 2768static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2769 struct drm_framebuffer *fb,
2770 int x, int y)
17638cd6
JB		 2771{
2772 struct drm_device *dev = crtc->dev;
2773 struct drm_i915_private *dev_priv = dev->dev_private;
2774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2775 struct drm_plane *primary = crtc->primary;
2776 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2777 struct drm_i915_gem_object *obj;
17638cd6 2778 int plane = intel_crtc->plane;
e506a0c6 2779 unsigned long linear_offset;
17638cd6 2780 u32 dspcntr;
f45651ba 2781 u32 reg = DSPCNTR(plane);
48404c1e 2782 int pixel_size;
f45651ba 2783
b70709a6 2784 if (!visible || !fb) {
fdd508a6
VS		 2785 I915_WRITE(reg, 0);
2786 I915_WRITE(DSPSURF(plane), 0);
2787 POSTING_READ(reg);
2788 return;
2789 }
2790
c9ba6fad
VS		 2791 obj = intel_fb_obj(fb);
2792 if (WARN_ON(obj == NULL))
2793 return;
2794
2795 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2796
f45651ba
VS		 2797 dspcntr = DISPPLANE_GAMMA_ENABLE;
2798
fdd508a6 2799 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2800
2801 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2802 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2803
57779d06
VS		 2804 switch (fb->pixel_format) {
2805 case DRM_FORMAT_C8:
17638cd6
JB		 2806 dspcntr |= DISPPLANE_8BPP;
2807 break;
57779d06
VS		 2808 case DRM_FORMAT_RGB565:
2809 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2810 break;
57779d06 2811 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2812 dspcntr |= DISPPLANE_BGRX888;
2813 break;
2814 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2815 dspcntr |= DISPPLANE_RGBX888;
2816 break;
2817 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2818 dspcntr |= DISPPLANE_BGRX101010;
2819 break;
2820 case DRM_FORMAT_XBGR2101010:
57779d06 2821 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2822 break;
2823 default:
baba133a 2824 BUG();
17638cd6
JB		 2825 }
2826
2827 if (obj->tiling_mode != I915_TILING_NONE)
2828 dspcntr |= DISPPLANE_TILED;
17638cd6 2829
f45651ba 2830 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2831 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2832
b9897127 2833 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2834 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2835 intel_gen4_compute_page_offset(dev_priv,
2836 &x, &y, obj->tiling_mode,
b9897127 2837 pixel_size,
bc752862 2838 fb->pitches[0]);
c2c75131 2839 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2840 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2841 dspcntr |= DISPPLANE_ROTATE_180;
2842
2843 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2844 x += (intel_crtc->config->pipe_src_w - 1);
2845 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2846
2847 /* Finding the last pixel of the last line of the display
2848 data and adding to linear_offset*/
2849 linear_offset +=
6e3c9717
ACO		 2850 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2851 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2852 }
2853 }
2854
2855 I915_WRITE(reg, dspcntr);
17638cd6 2856
01f2c773 2857 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2858 I915_WRITE(DSPSURF(plane),
2859 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2860 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2861 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2862 } else {
2863 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2864 I915_WRITE(DSPLINOFF(plane), linear_offset);
2865 }
17638cd6 2866 POSTING_READ(reg);
17638cd6
JB		 2867}
2868
b321803d
DL		 2869u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2870 uint32_t pixel_format)
2871{
2872 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2873
2874 /*
2875 * The stride is either expressed as a multiple of 64 bytes
2876 * chunks for linear buffers or in number of tiles for tiled
2877 * buffers.
2878 */
2879 switch (fb_modifier) {
2880 case DRM_FORMAT_MOD_NONE:
2881 return 64;
2882 case I915_FORMAT_MOD_X_TILED:
2883 if (INTEL_INFO(dev)->gen == 2)
2884 return 128;
2885 return 512;
2886 case I915_FORMAT_MOD_Y_TILED:
2887 /* No need to check for old gens and Y tiling since this is
2888 * about the display engine and those will be blocked before
2889 * we get here.
2890 */
2891 return 128;
2892 case I915_FORMAT_MOD_Yf_TILED:
2893 if (bits_per_pixel == 8)
2894 return 64;
2895 else
2896 return 128;
2897 default:
2898 MISSING_CASE(fb_modifier);
2899 return 64;
2900 }
2901}
2902
121920fa
TU		 2903unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2904 struct drm_i915_gem_object *obj)
2905{
9abc4648 2906 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2907
2908 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2909 view = &i915_ggtt_view_rotated;
121920fa
TU		 2910
2911 return i915_gem_obj_ggtt_offset_view(obj, view);
2912}
2913
a1b2278e
CK		 2914/*
2915 * This function detaches (aka. unbinds) unused scalers in hardware
2916 */
0583236e 2917static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e
CK		 2918{
2919 struct drm_device *dev;
2920 struct drm_i915_private *dev_priv;
2921 struct intel_crtc_scaler_state *scaler_state;
2922 int i;
2923
a1b2278e
CK		 2924 dev = intel_crtc->base.dev;
2925 dev_priv = dev->dev_private;
2926 scaler_state = &intel_crtc->config->scaler_state;
2927
2928 /* loop through and disable scalers that aren't in use */
2929 for (i = 0; i < intel_crtc->num_scalers; i++) {
2930 if (!scaler_state->scalers[i].in_use) {
2931 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2932 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2933 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2934 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2935 intel_crtc->base.base.id, intel_crtc->pipe, i);
2936 }
2937 }
2938}
2939
6156a456 2940u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2941{
6156a456 2942 switch (pixel_format) {
d161cf7a 2943 case DRM_FORMAT_C8:
c34ce3d1 2944 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2945 case DRM_FORMAT_RGB565:
c34ce3d1 2946 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2947 case DRM_FORMAT_XBGR8888:
c34ce3d1 2948 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2949 case DRM_FORMAT_XRGB8888:
c34ce3d1 2950 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2951 /*
2952 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2953 * to be already pre-multiplied. We need to add a knob (or a different
2954 * DRM_FORMAT) for user-space to configure that.
2955 */
f75fb42a 2956 case DRM_FORMAT_ABGR8888:
c34ce3d1 2957 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2958 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2959 case DRM_FORMAT_ARGB8888:
c34ce3d1 2960 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2961 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2962 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2963 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2964 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2965 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2966 case DRM_FORMAT_YUYV:
c34ce3d1 2967 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2968 case DRM_FORMAT_YVYU:
c34ce3d1 2969 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2970 case DRM_FORMAT_UYVY:
c34ce3d1 2971 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2972 case DRM_FORMAT_VYUY:
c34ce3d1 2973 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2974 default:
4249eeef 2975 MISSING_CASE(pixel_format);
70d21f0e 2976 }
8cfcba41 2977
c34ce3d1 2978 return 0;
6156a456 2979}
70d21f0e 2980
6156a456
CK		 2981u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2982{
6156a456 2983 switch (fb_modifier) {
30af77c4 2984 case DRM_FORMAT_MOD_NONE:
70d21f0e 2985 break;
30af77c4 2986 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2987 return PLANE_CTL_TILED_X;
b321803d 2988 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2989 return PLANE_CTL_TILED_Y;
b321803d 2990 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2991 return PLANE_CTL_TILED_YF;
70d21f0e 2992 default:
6156a456 2993 MISSING_CASE(fb_modifier);
70d21f0e 2994 }
8cfcba41 2995
c34ce3d1 2996 return 0;
6156a456 2997}
70d21f0e 2998
6156a456
CK		 2999u32 skl_plane_ctl_rotation(unsigned int rotation)
3000{
3b7a5119 3001 switch (rotation) {
6156a456
CK		 3002 case BIT(DRM_ROTATE_0):
3003 break;
1e8df167
SJ		 3004 /*
3005 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3006 * while i915 HW rotation is clockwise, thats why this swapping.
3007 */
3b7a5119 3008 case BIT(DRM_ROTATE_90):
1e8df167 3009 return PLANE_CTL_ROTATE_270;
3b7a5119 3010 case BIT(DRM_ROTATE_180):
c34ce3d1 3011 return PLANE_CTL_ROTATE_180;
3b7a5119 3012 case BIT(DRM_ROTATE_270):
1e8df167 3013 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3014 default:
3015 MISSING_CASE(rotation);
3016 }
3017
c34ce3d1 3018 return 0;
6156a456
CK		 3019}
3020
3021static void skylake_update_primary_plane(struct drm_crtc *crtc,
3022 struct drm_framebuffer *fb,
3023 int x, int y)
3024{
3025 struct drm_device *dev = crtc->dev;
3026 struct drm_i915_private *dev_priv = dev->dev_private;
3027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3028 struct drm_plane *plane = crtc->primary;
3029 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3030 struct drm_i915_gem_object *obj;
3031 int pipe = intel_crtc->pipe;
3032 u32 plane_ctl, stride_div, stride;
3033 u32 tile_height, plane_offset, plane_size;
3034 unsigned int rotation;
3035 int x_offset, y_offset;
3036 unsigned long surf_addr;
6156a456
CK		 3037 struct intel_crtc_state *crtc_state = intel_crtc->config;
3038 struct intel_plane_state *plane_state;
3039 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3040 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3041 int scaler_id = -1;
3042
6156a456
CK		 3043 plane_state = to_intel_plane_state(plane->state);
3044
b70709a6 3045 if (!visible || !fb) {
6156a456
CK		 3046 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3047 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3048 POSTING_READ(PLANE_CTL(pipe, 0));
3049 return;
3b7a5119 3050 }
70d21f0e 3051
6156a456
CK		 3052 plane_ctl = PLANE_CTL_ENABLE |
3053 PLANE_CTL_PIPE_GAMMA_ENABLE |
3054 PLANE_CTL_PIPE_CSC_ENABLE;
3055
3056 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3057 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3058 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3059
3060 rotation = plane->state->rotation;
3061 plane_ctl |= skl_plane_ctl_rotation(rotation);
3062
b321803d
DL		 3063 obj = intel_fb_obj(fb);
3064 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3065 fb->pixel_format);
3b7a5119
SJ		 3066 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3067
6156a456
CK		 3068 /*
3069 * FIXME: intel_plane_state->src, dst aren't set when transitional
3070 * update_plane helpers are called from legacy paths.
3071 * Once full atomic crtc is available, below check can be avoided.
3072 */
3073 if (drm_rect_width(&plane_state->src)) {
3074 scaler_id = plane_state->scaler_id;
3075 src_x = plane_state->src.x1 >> 16;
3076 src_y = plane_state->src.y1 >> 16;
3077 src_w = drm_rect_width(&plane_state->src) >> 16;
3078 src_h = drm_rect_height(&plane_state->src) >> 16;
3079 dst_x = plane_state->dst.x1;
3080 dst_y = plane_state->dst.y1;
3081 dst_w = drm_rect_width(&plane_state->dst);
3082 dst_h = drm_rect_height(&plane_state->dst);
3083
3084 WARN_ON(x != src_x || y != src_y);
3085 } else {
3086 src_w = intel_crtc->config->pipe_src_w;
3087 src_h = intel_crtc->config->pipe_src_h;
3088 }
3089
3b7a5119
SJ		 3090 if (intel_rotation_90_or_270(rotation)) {
3091 /* stride = Surface height in tiles */
2614f17d 3092 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3093 fb->modifier[0]);
3094 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3095 x_offset = stride * tile_height - y - src_h;
3b7a5119 3096 y_offset = x;
6156a456 3097 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3098 } else {
3099 stride = fb->pitches[0] / stride_div;
3100 x_offset = x;
3101 y_offset = y;
6156a456 3102 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3103 }
3104 plane_offset = y_offset << 16 | x_offset;
b321803d 3105
70d21f0e 3106 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3107 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3108 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3109 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3110
3111 if (scaler_id >= 0) {
3112 uint32_t ps_ctrl = 0;
3113
3114 WARN_ON(!dst_w || !dst_h);
3115 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3116 crtc_state->scaler_state.scalers[scaler_id].mode;
3117 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3118 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3119 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3120 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3121 I915_WRITE(PLANE_POS(pipe, 0), 0);
3122 } else {
3123 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3124 }
3125
121920fa 3126 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3127
3128 POSTING_READ(PLANE_SURF(pipe, 0));
3129}
3130
17638cd6
JB		 3131/* Assume fb object is pinned & idle & fenced and just update base pointers */
3132static int
3133intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3134 int x, int y, enum mode_set_atomic state)
3135{
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3138
ff2a3117 3139 if (dev_priv->fbc.disable_fbc)
7733b49b 3140 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3141
29b9bde6
DV		 3142 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3143
3144 return 0;
81255565
JB		 3145}
3146
7514747d 3147static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3148{
96a02917
VS		 3149 struct drm_crtc *crtc;
3150
70e1e0ec 3151 for_each_crtc(dev, crtc) {
96a02917
VS		 3152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3153 enum plane plane = intel_crtc->plane;
3154
3155 intel_prepare_page_flip(dev, plane);
3156 intel_finish_page_flip_plane(dev, plane);
3157 }
7514747d
VS		 3158}
3159
3160static void intel_update_primary_planes(struct drm_device *dev)
3161{
3162 struct drm_i915_private *dev_priv = dev->dev_private;
3163 struct drm_crtc *crtc;
96a02917 3164
70e1e0ec 3165 for_each_crtc(dev, crtc) {
96a02917
VS		 3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167
51fd371b 3168 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3169 /*
3170 * FIXME: Once we have proper support for primary planes (and
3171 * disabling them without disabling the entire crtc) allow again
66e514c1 3172 * a NULL crtc->primary->fb.
947fdaad 3173 */
f4510a27 3174 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3175 dev_priv->display.update_primary_plane(crtc,
66e514c1 3176 crtc->primary->fb,
262ca2b0
MR		 3177 crtc->x,
3178 crtc->y);
51fd371b 3179 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3180 }
3181}
3182
7514747d
VS		 3183void intel_prepare_reset(struct drm_device *dev)
3184{
3185 /* no reset support for gen2 */
3186 if (IS_GEN2(dev))
3187 return;
3188
3189 /* reset doesn't touch the display */
3190 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3191 return;
3192
3193 drm_modeset_lock_all(dev);
f98ce92f
VS		 3194 /*
3195 * Disabling the crtcs gracefully seems nicer. Also the
3196 * g33 docs say we should at least disable all the planes.
3197 */
6b72d486 3198 intel_display_suspend(dev);
7514747d
VS		 3199}
3200
3201void intel_finish_reset(struct drm_device *dev)
3202{
3203 struct drm_i915_private *dev_priv = to_i915(dev);
3204
3205 /*
3206 * Flips in the rings will be nuked by the reset,
3207 * so complete all pending flips so that user space
3208 * will get its events and not get stuck.
3209 */
3210 intel_complete_page_flips(dev);
3211
3212 /* no reset support for gen2 */
3213 if (IS_GEN2(dev))
3214 return;
3215
3216 /* reset doesn't touch the display */
3217 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3218 /*
3219 * Flips in the rings have been nuked by the reset,
3220 * so update the base address of all primary
3221 * planes to the the last fb to make sure we're
3222 * showing the correct fb after a reset.
3223 */
3224 intel_update_primary_planes(dev);
3225 return;
3226 }
3227
3228 /*
3229 * The display has been reset as well,
3230 * so need a full re-initialization.
3231 */
3232 intel_runtime_pm_disable_interrupts(dev_priv);
3233 intel_runtime_pm_enable_interrupts(dev_priv);
3234
3235 intel_modeset_init_hw(dev);
3236
3237 spin_lock_irq(&dev_priv->irq_lock);
3238 if (dev_priv->display.hpd_irq_setup)
3239 dev_priv->display.hpd_irq_setup(dev);
3240 spin_unlock_irq(&dev_priv->irq_lock);
3241
3242 intel_modeset_setup_hw_state(dev, true);
3243
3244 intel_hpd_init(dev_priv);
3245
3246 drm_modeset_unlock_all(dev);
3247}
3248
2e2f351d 3249static void
14667a4b
CW		 3250intel_finish_fb(struct drm_framebuffer *old_fb)
3251{
2ff8fde1 3252 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3253 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3254 bool was_interruptible = dev_priv->mm.interruptible;
3255 int ret;
3256
14667a4b
CW		 3257 /* Big Hammer, we also need to ensure that any pending
3258 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3259 * current scanout is retired before unpinning the old
2e2f351d
CW		 3260 * framebuffer. Note that we rely on userspace rendering
3261 * into the buffer attached to the pipe they are waiting
3262 * on. If not, userspace generates a GPU hang with IPEHR
3263 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3264 *
3265 * This should only fail upon a hung GPU, in which case we
3266 * can safely continue.
3267 */
3268 dev_priv->mm.interruptible = false;
2e2f351d 3269 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3270 dev_priv->mm.interruptible = was_interruptible;
3271
2e2f351d 3272 WARN_ON(ret);
14667a4b
CW		 3273}
3274
7d5e3799
CW		 3275static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3276{
3277 struct drm_device *dev = crtc->dev;
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3280 bool pending;
3281
3282 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3283 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3284 return false;
3285
5e2d7afc 3286 spin_lock_irq(&dev->event_lock);
7d5e3799 3287 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3288 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3289
3290 return pending;
3291}
3292
e30e8f75
GP		 3293static void intel_update_pipe_size(struct intel_crtc *crtc)
3294{
3295 struct drm_device *dev = crtc->base.dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 const struct drm_display_mode *adjusted_mode;
3298
3299 if (!i915.fastboot)
3300 return;
3301
3302 /*
3303 * Update pipe size and adjust fitter if needed: the reason for this is
3304 * that in compute_mode_changes we check the native mode (not the pfit
3305 * mode) to see if we can flip rather than do a full mode set. In the
3306 * fastboot case, we'll flip, but if we don't update the pipesrc and
3307 * pfit state, we'll end up with a big fb scanned out into the wrong
3308 * sized surface.
3309 *
3310 * To fix this properly, we need to hoist the checks up into
3311 * compute_mode_changes (or above), check the actual pfit state and
3312 * whether the platform allows pfit disable with pipe active, and only
3313 * then update the pipesrc and pfit state, even on the flip path.
3314 */
3315
6e3c9717 3316 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3317
3318 I915_WRITE(PIPESRC(crtc->pipe),
3319 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3320 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3321 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3322 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3323 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3324 I915_WRITE(PF_CTL(crtc->pipe), 0);
3325 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3326 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3327 }
6e3c9717
ACO		 3328 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3329 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3330}
3331
5e84e1a4
ZW		 3332static void intel_fdi_normal_train(struct drm_crtc *crtc)
3333{
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 int pipe = intel_crtc->pipe;
3338 u32 reg, temp;
3339
3340 /* enable normal train */
3341 reg = FDI_TX_CTL(pipe);
3342 temp = I915_READ(reg);
61e499bf 3343 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3344 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3345 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3346 } else {
3347 temp &= ~FDI_LINK_TRAIN_NONE;
3348 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3349 }
5e84e1a4
ZW		 3350 I915_WRITE(reg, temp);
3351
3352 reg = FDI_RX_CTL(pipe);
3353 temp = I915_READ(reg);
3354 if (HAS_PCH_CPT(dev)) {
3355 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3357 } else {
3358 temp &= ~FDI_LINK_TRAIN_NONE;
3359 temp |= FDI_LINK_TRAIN_NONE;
3360 }
3361 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3362
3363 /* wait one idle pattern time */
3364 POSTING_READ(reg);
3365 udelay(1000);
357555c0
JB		 3366
3367 /* IVB wants error correction enabled */
3368 if (IS_IVYBRIDGE(dev))
3369 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3370 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3371}
3372
8db9d77b
ZW		 3373/* The FDI link training functions for ILK/Ibexpeak. */
3374static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3375{
3376 struct drm_device *dev = crtc->dev;
3377 struct drm_i915_private *dev_priv = dev->dev_private;
3378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3379 int pipe = intel_crtc->pipe;
5eddb70b 3380 u32 reg, temp, tries;
8db9d77b 3381
1c8562f6 3382 /* FDI needs bits from pipe first */
0fc932b8 3383 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3384
e1a44743
AJ		 3385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3386 for train result */
5eddb70b
CW		 3387 reg = FDI_RX_IMR(pipe);
3388 temp = I915_READ(reg);
e1a44743
AJ		 3389 temp &= ~FDI_RX_SYMBOL_LOCK;
3390 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3391 I915_WRITE(reg, temp);
3392 I915_READ(reg);
e1a44743
AJ		 3393 udelay(150);
3394
8db9d77b 3395 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3396 reg = FDI_TX_CTL(pipe);
3397 temp = I915_READ(reg);
627eb5a3 3398 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3399 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3400 temp &= ~FDI_LINK_TRAIN_NONE;
3401 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3402 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3403
5eddb70b
CW		 3404 reg = FDI_RX_CTL(pipe);
3405 temp = I915_READ(reg);
8db9d77b
ZW		 3406 temp &= ~FDI_LINK_TRAIN_NONE;
3407 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3408 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3409
3410 POSTING_READ(reg);
8db9d77b
ZW		 3411 udelay(150);
3412
5b2adf89 3413 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3414 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3415 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3416 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3417
5eddb70b 3418 reg = FDI_RX_IIR(pipe);
e1a44743 3419 for (tries = 0; tries < 5; tries++) {
5eddb70b 3420 temp = I915_READ(reg);
8db9d77b
ZW		 3421 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3422
3423 if ((temp & FDI_RX_BIT_LOCK)) {
3424 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3425 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3426 break;
3427 }
8db9d77b 3428 }
e1a44743 3429 if (tries == 5)
5eddb70b 3430 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3431
3432 /* Train 2 */
5eddb70b
CW		 3433 reg = FDI_TX_CTL(pipe);
3434 temp = I915_READ(reg);
8db9d77b
ZW		 3435 temp &= ~FDI_LINK_TRAIN_NONE;
3436 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3437 I915_WRITE(reg, temp);
8db9d77b 3438
5eddb70b
CW		 3439 reg = FDI_RX_CTL(pipe);
3440 temp = I915_READ(reg);
8db9d77b
ZW		 3441 temp &= ~FDI_LINK_TRAIN_NONE;
3442 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3443 I915_WRITE(reg, temp);
8db9d77b 3444
5eddb70b
CW		 3445 POSTING_READ(reg);
3446 udelay(150);
8db9d77b 3447
5eddb70b 3448 reg = FDI_RX_IIR(pipe);
e1a44743 3449 for (tries = 0; tries < 5; tries++) {
5eddb70b 3450 temp = I915_READ(reg);
8db9d77b
ZW		 3451 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3452
3453 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3454 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3455 DRM_DEBUG_KMS("FDI train 2 done.\n");
3456 break;
3457 }
8db9d77b 3458 }
e1a44743 3459 if (tries == 5)
5eddb70b 3460 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3461
3462 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3463
8db9d77b
ZW		 3464}
3465
0206e353 3466static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3467 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3468 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3469 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3470 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3471};
3472
3473/* The FDI link training functions for SNB/Cougarpoint. */
3474static void gen6_fdi_link_train(struct drm_crtc *crtc)
3475{
3476 struct drm_device *dev = crtc->dev;
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479 int pipe = intel_crtc->pipe;
fa37d39e 3480 u32 reg, temp, i, retry;
8db9d77b 3481
e1a44743
AJ		 3482 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3483 for train result */
5eddb70b
CW		 3484 reg = FDI_RX_IMR(pipe);
3485 temp = I915_READ(reg);
e1a44743
AJ		 3486 temp &= ~FDI_RX_SYMBOL_LOCK;
3487 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3488 I915_WRITE(reg, temp);
3489
3490 POSTING_READ(reg);
e1a44743
AJ		 3491 udelay(150);
3492
8db9d77b 3493 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3494 reg = FDI_TX_CTL(pipe);
3495 temp = I915_READ(reg);
627eb5a3 3496 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3497 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3498 temp &= ~FDI_LINK_TRAIN_NONE;
3499 temp |= FDI_LINK_TRAIN_PATTERN_1;
3500 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3501 /* SNB-B */
3502 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3503 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3504
d74cf324
DV		 3505 I915_WRITE(FDI_RX_MISC(pipe),
3506 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3507
5eddb70b
CW		 3508 reg = FDI_RX_CTL(pipe);
3509 temp = I915_READ(reg);
8db9d77b
ZW		 3510 if (HAS_PCH_CPT(dev)) {
3511 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3512 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3513 } else {
3514 temp &= ~FDI_LINK_TRAIN_NONE;
3515 temp |= FDI_LINK_TRAIN_PATTERN_1;
3516 }
5eddb70b
CW		 3517 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3518
3519 POSTING_READ(reg);
8db9d77b
ZW		 3520 udelay(150);
3521
0206e353 3522 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3523 reg = FDI_TX_CTL(pipe);
3524 temp = I915_READ(reg);
8db9d77b
ZW		 3525 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3526 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3527 I915_WRITE(reg, temp);
3528
3529 POSTING_READ(reg);
8db9d77b
ZW		 3530 udelay(500);
3531
fa37d39e
SP		 3532 for (retry = 0; retry < 5; retry++) {
3533 reg = FDI_RX_IIR(pipe);
3534 temp = I915_READ(reg);
3535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3536 if (temp & FDI_RX_BIT_LOCK) {
3537 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3538 DRM_DEBUG_KMS("FDI train 1 done.\n");
3539 break;
3540 }
3541 udelay(50);
8db9d77b 3542 }
fa37d39e
SP		 3543 if (retry < 5)
3544 break;
8db9d77b
ZW		 3545 }
3546 if (i == 4)
5eddb70b 3547 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3548
3549 /* Train 2 */
5eddb70b
CW		 3550 reg = FDI_TX_CTL(pipe);
3551 temp = I915_READ(reg);
8db9d77b
ZW		 3552 temp &= ~FDI_LINK_TRAIN_NONE;
3553 temp |= FDI_LINK_TRAIN_PATTERN_2;
3554 if (IS_GEN6(dev)) {
3555 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3556 /* SNB-B */
3557 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3558 }
5eddb70b 3559 I915_WRITE(reg, temp);
8db9d77b 3560
5eddb70b
CW		 3561 reg = FDI_RX_CTL(pipe);
3562 temp = I915_READ(reg);
8db9d77b
ZW		 3563 if (HAS_PCH_CPT(dev)) {
3564 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3565 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3566 } else {
3567 temp &= ~FDI_LINK_TRAIN_NONE;
3568 temp |= FDI_LINK_TRAIN_PATTERN_2;
3569 }
5eddb70b
CW		 3570 I915_WRITE(reg, temp);
3571
3572 POSTING_READ(reg);
8db9d77b
ZW		 3573 udelay(150);
3574
0206e353 3575 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3576 reg = FDI_TX_CTL(pipe);
3577 temp = I915_READ(reg);
8db9d77b
ZW		 3578 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3579 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3580 I915_WRITE(reg, temp);
3581
3582 POSTING_READ(reg);
8db9d77b
ZW		 3583 udelay(500);
3584
fa37d39e
SP		 3585 for (retry = 0; retry < 5; retry++) {
3586 reg = FDI_RX_IIR(pipe);
3587 temp = I915_READ(reg);
3588 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3589 if (temp & FDI_RX_SYMBOL_LOCK) {
3590 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3591 DRM_DEBUG_KMS("FDI train 2 done.\n");
3592 break;
3593 }
3594 udelay(50);
8db9d77b 3595 }
fa37d39e
SP		 3596 if (retry < 5)
3597 break;
8db9d77b
ZW		 3598 }
3599 if (i == 4)
5eddb70b 3600 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3601
3602 DRM_DEBUG_KMS("FDI train done.\n");
3603}
3604
357555c0
JB		 3605/* Manual link training for Ivy Bridge A0 parts */
3606static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3607{
3608 struct drm_device *dev = crtc->dev;
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3611 int pipe = intel_crtc->pipe;
139ccd3f 3612 u32 reg, temp, i, j;
357555c0
JB		 3613
3614 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3615 for train result */
3616 reg = FDI_RX_IMR(pipe);
3617 temp = I915_READ(reg);
3618 temp &= ~FDI_RX_SYMBOL_LOCK;
3619 temp &= ~FDI_RX_BIT_LOCK;
3620 I915_WRITE(reg, temp);
3621
3622 POSTING_READ(reg);
3623 udelay(150);
3624
01a415fd
DV		 3625 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3626 I915_READ(FDI_RX_IIR(pipe)));
3627
139ccd3f
JB		 3628 /* Try each vswing and preemphasis setting twice before moving on */
3629 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3630 /* disable first in case we need to retry */
3631 reg = FDI_TX_CTL(pipe);
3632 temp = I915_READ(reg);
3633 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3634 temp &= ~FDI_TX_ENABLE;
3635 I915_WRITE(reg, temp);
357555c0 3636
139ccd3f
JB		 3637 reg = FDI_RX_CTL(pipe);
3638 temp = I915_READ(reg);
3639 temp &= ~FDI_LINK_TRAIN_AUTO;
3640 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3641 temp &= ~FDI_RX_ENABLE;
3642 I915_WRITE(reg, temp);
357555c0 3643
139ccd3f 3644 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3645 reg = FDI_TX_CTL(pipe);
3646 temp = I915_READ(reg);
139ccd3f 3647 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3649 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3650 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3651 temp |= snb_b_fdi_train_param[j/2];
3652 temp |= FDI_COMPOSITE_SYNC;
3653 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3654
139ccd3f
JB		 3655 I915_WRITE(FDI_RX_MISC(pipe),
3656 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3657
139ccd3f 3658 reg = FDI_RX_CTL(pipe);
357555c0 3659 temp = I915_READ(reg);
139ccd3f
JB		 3660 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3661 temp |= FDI_COMPOSITE_SYNC;
3662 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3663
139ccd3f
JB		 3664 POSTING_READ(reg);
3665 udelay(1); /* should be 0.5us */
357555c0 3666
139ccd3f
JB		 3667 for (i = 0; i < 4; i++) {
3668 reg = FDI_RX_IIR(pipe);
3669 temp = I915_READ(reg);
3670 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3671
139ccd3f
JB		 3672 if (temp & FDI_RX_BIT_LOCK ||
3673 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3674 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3675 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3676 i);
3677 break;
3678 }
3679 udelay(1); /* should be 0.5us */
3680 }
3681 if (i == 4) {
3682 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3683 continue;
3684 }
357555c0 3685
139ccd3f 3686 /* Train 2 */
357555c0
JB		 3687 reg = FDI_TX_CTL(pipe);
3688 temp = I915_READ(reg);
139ccd3f
JB		 3689 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3690 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3691 I915_WRITE(reg, temp);
3692
3693 reg = FDI_RX_CTL(pipe);
3694 temp = I915_READ(reg);
3695 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3696 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3697 I915_WRITE(reg, temp);
3698
3699 POSTING_READ(reg);
139ccd3f 3700 udelay(2); /* should be 1.5us */
357555c0 3701
139ccd3f
JB		 3702 for (i = 0; i < 4; i++) {
3703 reg = FDI_RX_IIR(pipe);
3704 temp = I915_READ(reg);
3705 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3706
139ccd3f
JB		 3707 if (temp & FDI_RX_SYMBOL_LOCK ||
3708 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3709 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3710 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3711 i);
3712 goto train_done;
3713 }
3714 udelay(2); /* should be 1.5us */
357555c0 3715 }
139ccd3f
JB		 3716 if (i == 4)
3717 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3718 }
357555c0 3719
139ccd3f 3720train_done:
357555c0
JB		 3721 DRM_DEBUG_KMS("FDI train done.\n");
3722}
3723
88cefb6c 3724static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3725{
88cefb6c 3726 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3727 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3728 int pipe = intel_crtc->pipe;
5eddb70b 3729 u32 reg, temp;
79e53945 3730
c64e311e 3731
c98e9dcf 3732 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3733 reg = FDI_RX_CTL(pipe);
3734 temp = I915_READ(reg);
627eb5a3 3735 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3736 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3737 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3738 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3739
3740 POSTING_READ(reg);
c98e9dcf
JB		 3741 udelay(200);
3742
3743 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3744 temp = I915_READ(reg);
3745 I915_WRITE(reg, temp | FDI_PCDCLK);
3746
3747 POSTING_READ(reg);
c98e9dcf
JB		 3748 udelay(200);
3749
20749730
PZ		 3750 /* Enable CPU FDI TX PLL, always on for Ironlake */
3751 reg = FDI_TX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3754 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3755
20749730
PZ		 3756 POSTING_READ(reg);
3757 udelay(100);
6be4a607 3758 }
0e23b99d
JB		 3759}
3760
88cefb6c
DV		 3761static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3762{
3763 struct drm_device *dev = intel_crtc->base.dev;
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 int pipe = intel_crtc->pipe;
3766 u32 reg, temp;
3767
3768 /* Switch from PCDclk to Rawclk */
3769 reg = FDI_RX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3772
3773 /* Disable CPU FDI TX PLL */
3774 reg = FDI_TX_CTL(pipe);
3775 temp = I915_READ(reg);
3776 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3777
3778 POSTING_READ(reg);
3779 udelay(100);
3780
3781 reg = FDI_RX_CTL(pipe);
3782 temp = I915_READ(reg);
3783 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3784
3785 /* Wait for the clocks to turn off. */
3786 POSTING_READ(reg);
3787 udelay(100);
3788}
3789
0fc932b8
JB		 3790static void ironlake_fdi_disable(struct drm_crtc *crtc)
3791{
3792 struct drm_device *dev = crtc->dev;
3793 struct drm_i915_private *dev_priv = dev->dev_private;
3794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3795 int pipe = intel_crtc->pipe;
3796 u32 reg, temp;
3797
3798 /* disable CPU FDI tx and PCH FDI rx */
3799 reg = FDI_TX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3802 POSTING_READ(reg);
3803
3804 reg = FDI_RX_CTL(pipe);
3805 temp = I915_READ(reg);
3806 temp &= ~(0x7 << 16);
dfd07d72 3807 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3808 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812
3813 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3814 if (HAS_PCH_IBX(dev))
6f06ce18 3815 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3816
3817 /* still set train pattern 1 */
3818 reg = FDI_TX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 temp &= ~FDI_LINK_TRAIN_NONE;
3821 temp |= FDI_LINK_TRAIN_PATTERN_1;
3822 I915_WRITE(reg, temp);
3823
3824 reg = FDI_RX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 if (HAS_PCH_CPT(dev)) {
3827 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3828 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3829 } else {
3830 temp &= ~FDI_LINK_TRAIN_NONE;
3831 temp |= FDI_LINK_TRAIN_PATTERN_1;
3832 }
3833 /* BPC in FDI rx is consistent with that in PIPECONF */
3834 temp &= ~(0x07 << 16);
dfd07d72 3835 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3836 I915_WRITE(reg, temp);
3837
3838 POSTING_READ(reg);
3839 udelay(100);
3840}
3841
5dce5b93
CW		 3842bool intel_has_pending_fb_unpin(struct drm_device *dev)
3843{
3844 struct intel_crtc *crtc;
3845
3846 /* Note that we don't need to be called with mode_config.lock here
3847 * as our list of CRTC objects is static for the lifetime of the
3848 * device and so cannot disappear as we iterate. Similarly, we can
3849 * happily treat the predicates as racy, atomic checks as userspace
3850 * cannot claim and pin a new fb without at least acquring the
3851 * struct_mutex and so serialising with us.
3852 */
d3fcc808 3853 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3854 if (atomic_read(&crtc->unpin_work_count) == 0)
3855 continue;
3856
3857 if (crtc->unpin_work)
3858 intel_wait_for_vblank(dev, crtc->pipe);
3859
3860 return true;
3861 }
3862
3863 return false;
3864}
3865
d6bbafa1
CW		 3866static void page_flip_completed(struct intel_crtc *intel_crtc)
3867{
3868 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3869 struct intel_unpin_work *work = intel_crtc->unpin_work;
3870
3871 /* ensure that the unpin work is consistent wrt ->pending. */
3872 smp_rmb();
3873 intel_crtc->unpin_work = NULL;
3874
3875 if (work->event)
3876 drm_send_vblank_event(intel_crtc->base.dev,
3877 intel_crtc->pipe,
3878 work->event);
3879
3880 drm_crtc_vblank_put(&intel_crtc->base);
3881
3882 wake_up_all(&dev_priv->pending_flip_queue);
3883 queue_work(dev_priv->wq, &work->work);
3884
3885 trace_i915_flip_complete(intel_crtc->plane,
3886 work->pending_flip_obj);
3887}
3888
46a55d30 3889void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3890{
0f91128d 3891 struct drm_device *dev = crtc->dev;
5bb61643 3892 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3893
2c10d571 3894 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3895 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3896 !intel_crtc_has_pending_flip(crtc),
3897 60*HZ) == 0)) {
3898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3899
5e2d7afc 3900 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3901 if (intel_crtc->unpin_work) {
3902 WARN_ONCE(1, "Removing stuck page flip\n");
3903 page_flip_completed(intel_crtc);
3904 }
5e2d7afc 3905 spin_unlock_irq(&dev->event_lock);
9c787942 3906 }
5bb61643 3907
975d568a
CW		 3908 if (crtc->primary->fb) {
3909 mutex_lock(&dev->struct_mutex);
3910 intel_finish_fb(crtc->primary->fb);
3911 mutex_unlock(&dev->struct_mutex);
3912 }
e6c3a2a6
CW		 3913}
3914
e615efe4
ED		 3915/* Program iCLKIP clock to the desired frequency */
3916static void lpt_program_iclkip(struct drm_crtc *crtc)
3917{
3918 struct drm_device *dev = crtc->dev;
3919 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3920 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3921 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3922 u32 temp;
3923
a580516d 3924 mutex_lock(&dev_priv->sb_lock);
09153000 3925
e615efe4
ED		 3926 /* It is necessary to ungate the pixclk gate prior to programming
3927 * the divisors, and gate it back when it is done.
3928 */
3929 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3930
3931 /* Disable SSCCTL */
3932 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3933 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3934 SBI_SSCCTL_DISABLE,
3935 SBI_ICLK);
e615efe4
ED		 3936
3937 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3938 if (clock == 20000) {
e615efe4
ED		 3939 auxdiv = 1;
3940 divsel = 0x41;
3941 phaseinc = 0x20;
3942 } else {
3943 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3944 * but the adjusted_mode->crtc_clock in in KHz. To get the
3945 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3946 * convert the virtual clock precision to KHz here for higher
3947 * precision.
3948 */
3949 u32 iclk_virtual_root_freq = 172800 * 1000;
3950 u32 iclk_pi_range = 64;
3951 u32 desired_divisor, msb_divisor_value, pi_value;
3952
12d7ceed 3953 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3954 msb_divisor_value = desired_divisor / iclk_pi_range;
3955 pi_value = desired_divisor % iclk_pi_range;
3956
3957 auxdiv = 0;
3958 divsel = msb_divisor_value - 2;
3959 phaseinc = pi_value;
3960 }
3961
3962 /* This should not happen with any sane values */
3963 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3964 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3965 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3966 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3967
3968 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3969 clock,
e615efe4
ED		 3970 auxdiv,
3971 divsel,
3972 phasedir,
3973 phaseinc);
3974
3975 /* Program SSCDIVINTPHASE6 */
988d6ee8 3976 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3977 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3978 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3979 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3980 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3981 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3982 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3983 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3984
3985 /* Program SSCAUXDIV */
988d6ee8 3986 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3987 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3988 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3989 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3990
3991 /* Enable modulator and associated divider */
988d6ee8 3992 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3993 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3994 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3995
3996 /* Wait for initialization time */
3997 udelay(24);
3998
3999 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4000
a580516d 4001 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4002}
4003
275f01b2
DV		 4004static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4005 enum pipe pch_transcoder)
4006{
4007 struct drm_device *dev = crtc->base.dev;
4008 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4009 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4010
4011 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4012 I915_READ(HTOTAL(cpu_transcoder)));
4013 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4014 I915_READ(HBLANK(cpu_transcoder)));
4015 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4016 I915_READ(HSYNC(cpu_transcoder)));
4017
4018 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4019 I915_READ(VTOTAL(cpu_transcoder)));
4020 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4021 I915_READ(VBLANK(cpu_transcoder)));
4022 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4023 I915_READ(VSYNC(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4025 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4026}
4027
003632d9 4028static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4029{
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 uint32_t temp;
4032
4033 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4034 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4035 return;
4036
4037 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4038 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4039
003632d9
ACO		 4040 temp &= ~FDI_BC_BIFURCATION_SELECT;
4041 if (enable)
4042 temp |= FDI_BC_BIFURCATION_SELECT;
4043
4044 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4045 I915_WRITE(SOUTH_CHICKEN1, temp);
4046 POSTING_READ(SOUTH_CHICKEN1);
4047}
4048
4049static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4050{
4051 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4052
4053 switch (intel_crtc->pipe) {
4054 case PIPE_A:
4055 break;
4056 case PIPE_B:
6e3c9717 4057 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4058 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4059 else
003632d9 4060 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4061
4062 break;
4063 case PIPE_C:
003632d9 4064 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4065
4066 break;
4067 default:
4068 BUG();
4069 }
4070}
4071
f67a559d
JB		 4072/*
4073 * Enable PCH resources required for PCH ports:
4074 * - PCH PLLs
4075 * - FDI training & RX/TX
4076 * - update transcoder timings
4077 * - DP transcoding bits
4078 * - transcoder
4079 */
4080static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4081{
4082 struct drm_device *dev = crtc->dev;
4083 struct drm_i915_private *dev_priv = dev->dev_private;
4084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4085 int pipe = intel_crtc->pipe;
ee7b9f93 4086 u32 reg, temp;
2c07245f 4087
ab9412ba 4088 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4089
1fbc0d78
DV		 4090 if (IS_IVYBRIDGE(dev))
4091 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4092
cd986abb
DV		 4093 /* Write the TU size bits before fdi link training, so that error
4094 * detection works. */
4095 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4096 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4097
c98e9dcf 4098 /* For PCH output, training FDI link */
674cf967 4099 dev_priv->display.fdi_link_train(crtc);
2c07245f 4100
3ad8a208
DV		 4101 /* We need to program the right clock selection before writing the pixel
4102 * mutliplier into the DPLL. */
303b81e0 4103 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4104 u32 sel;
4b645f14 4105
c98e9dcf 4106 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4107 temp |= TRANS_DPLL_ENABLE(pipe);
4108 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4109 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4110 temp |= sel;
4111 else
4112 temp &= ~sel;
c98e9dcf 4113 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4114 }
5eddb70b 4115
3ad8a208
DV		 4116 /* XXX: pch pll's can be enabled any time before we enable the PCH
4117 * transcoder, and we actually should do this to not upset any PCH
4118 * transcoder that already use the clock when we share it.
4119 *
4120 * Note that enable_shared_dpll tries to do the right thing, but
4121 * get_shared_dpll unconditionally resets the pll - we need that to have
4122 * the right LVDS enable sequence. */
85b3894f 4123 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4124
d9b6cb56
JB		 4125 /* set transcoder timing, panel must allow it */
4126 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4127 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4128
303b81e0 4129 intel_fdi_normal_train(crtc);
5e84e1a4 4130
c98e9dcf 4131 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4132 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4133 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4134 reg = TRANS_DP_CTL(pipe);
4135 temp = I915_READ(reg);
4136 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4137 TRANS_DP_SYNC_MASK |
4138 TRANS_DP_BPC_MASK);
e3ef4479 4139 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4140 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4141
4142 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4143 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4144 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4145 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4146
4147 switch (intel_trans_dp_port_sel(crtc)) {
4148 case PCH_DP_B:
5eddb70b 4149 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4150 break;
4151 case PCH_DP_C:
5eddb70b 4152 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4153 break;
4154 case PCH_DP_D:
5eddb70b 4155 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4156 break;
4157 default:
e95d41e1 4158 BUG();
32f9d658 4159 }
2c07245f 4160
5eddb70b 4161 I915_WRITE(reg, temp);
6be4a607 4162 }
b52eb4dc 4163
b8a4f404 4164 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4165}
4166
1507e5bd
PZ		 4167static void lpt_pch_enable(struct drm_crtc *crtc)
4168{
4169 struct drm_device *dev = crtc->dev;
4170 struct drm_i915_private *dev_priv = dev->dev_private;
4171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4172 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4173
ab9412ba 4174 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4175
8c52b5e8 4176 lpt_program_iclkip(crtc);
1507e5bd 4177
0540e488 4178 /* Set transcoder timing. */
275f01b2 4179 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4180
937bb610 4181 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4182}
4183
190f68c5
ACO		 4184struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4185 struct intel_crtc_state *crtc_state)
ee7b9f93 4186{
e2b78267 4187 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4188 struct intel_shared_dpll *pll;
de419ab6 4189 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4190 enum intel_dpll_id i;
ee7b9f93 4191
de419ab6
ML		 4192 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4193
98b6bd99
DV		 4194 if (HAS_PCH_IBX(dev_priv->dev)) {
4195 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4196 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4197 pll = &dev_priv->shared_dplls[i];
98b6bd99 4198
46edb027
DV		 4199 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4200 crtc->base.base.id, pll->name);
98b6bd99 4201
de419ab6 4202 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4203
98b6bd99
DV		 4204 goto found;
4205 }
4206
bcddf610
S		 4207 if (IS_BROXTON(dev_priv->dev)) {
4208 /* PLL is attached to port in bxt */
4209 struct intel_encoder *encoder;
4210 struct intel_digital_port *intel_dig_port;
4211
4212 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4213 if (WARN_ON(!encoder))
4214 return NULL;
4215
4216 intel_dig_port = enc_to_dig_port(&encoder->base);
4217 /* 1:1 mapping between ports and PLLs */
4218 i = (enum intel_dpll_id)intel_dig_port->port;
4219 pll = &dev_priv->shared_dplls[i];
4220 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4221 crtc->base.base.id, pll->name);
de419ab6 4222 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4223
4224 goto found;
4225 }
4226
e72f9fbf
DV		 4227 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4228 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4229
4230 /* Only want to check enabled timings first */
de419ab6 4231 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4232 continue;
4233
190f68c5 4234 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4235 &shared_dpll[i].hw_state,
4236 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4237 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4238 crtc->base.base.id, pll->name,
de419ab6 4239 shared_dpll[i].crtc_mask,
8bd31e67 4240 pll->active);
ee7b9f93
JB		 4241 goto found;
4242 }
4243 }
4244
4245 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4246 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4247 pll = &dev_priv->shared_dplls[i];
de419ab6 4248 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4249 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4250 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4251 goto found;
4252 }
4253 }
4254
4255 return NULL;
4256
4257found:
de419ab6
ML		 4258 if (shared_dpll[i].crtc_mask == 0)
4259 shared_dpll[i].hw_state =
4260 crtc_state->dpll_hw_state;
f2a69f44 4261
190f68c5 4262 crtc_state->shared_dpll = i;
46edb027
DV		 4263 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4264 pipe_name(crtc->pipe));
ee7b9f93 4265
de419ab6 4266 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4267
ee7b9f93
JB		 4268 return pll;
4269}
4270
de419ab6 4271static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4272{
de419ab6
ML		 4273 struct drm_i915_private *dev_priv = to_i915(state->dev);
4274 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4275 struct intel_shared_dpll *pll;
4276 enum intel_dpll_id i;
4277
de419ab6
ML		 4278 if (!to_intel_atomic_state(state)->dpll_set)
4279 return;
8bd31e67 4280
de419ab6 4281 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
de419ab6 4284 pll->config = shared_dpll[i];
8bd31e67
ACO		 4285 }
4286}
4287
a1520318 4288static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4289{
4290 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4291 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4292 u32 temp;
4293
4294 temp = I915_READ(dslreg);
4295 udelay(500);
4296 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4297 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4298 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4299 }
4300}
4301
86adf9d7
ML		 4302static int
4303skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4304 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4305 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4306{
86adf9d7
ML		 4307 struct intel_crtc_scaler_state *scaler_state =
4308 &crtc_state->scaler_state;
4309 struct intel_crtc *intel_crtc =
4310 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4311 int need_scaling;
6156a456
CK		 4312
4313 need_scaling = intel_rotation_90_or_270(rotation) ?
4314 (src_h != dst_w || src_w != dst_h):
4315 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4316
4317 /*
4318 * if plane is being disabled or scaler is no more required or force detach
4319 * - free scaler binded to this plane/crtc
4320 * - in order to do this, update crtc->scaler_usage
4321 *
4322 * Here scaler state in crtc_state is set free so that
4323 * scaler can be assigned to other user. Actual register
4324 * update to free the scaler is done in plane/panel-fit programming.
4325 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4326 */
86adf9d7 4327 if (force_detach || !need_scaling) {
a1b2278e 4328 if (*scaler_id >= 0) {
86adf9d7 4329 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4330 scaler_state->scalers[*scaler_id].in_use = 0;
4331
86adf9d7
ML		 4332 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4333 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4334 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4335 scaler_state->scaler_users);
4336 *scaler_id = -1;
4337 }
4338 return 0;
4339 }
4340
4341 /* range checks */
4342 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4343 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4344
4345 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4346 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4347 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4348 "size is out of scaler range\n",
86adf9d7 4349 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4350 return -EINVAL;
4351 }
4352
86adf9d7
ML		 4353 /* mark this plane as a scaler user in crtc_state */
4354 scaler_state->scaler_users |= (1 << scaler_user);
4355 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4356 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4357 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4358 scaler_state->scaler_users);
4359
4360 return 0;
4361}
4362
4363/**
4364 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4365 *
4366 * @state: crtc's scaler state
4367 * @force_detach: whether to forcibly disable scaler
4368 *
4369 * Return
4370 * 0 - scaler_usage updated successfully
4371 * error - requested scaling cannot be supported or other error condition
4372 */
4373int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4374{
4375 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4376 struct drm_display_mode *adjusted_mode =
4377 &state->base.adjusted_mode;
4378
4379 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4380 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4381
4382 return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4383 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4384 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4385 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4386}
4387
4388/**
4389 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4390 *
4391 * @state: crtc's scaler state
86adf9d7
ML		 4392 * @plane_state: atomic plane state to update
4393 *
4394 * Return
4395 * 0 - scaler_usage updated successfully
4396 * error - requested scaling cannot be supported or other error condition
4397 */
da20eabd
ML		 4398static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4399 struct intel_plane_state *plane_state)
86adf9d7
ML		 4400{
4401
4402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4403 struct intel_plane *intel_plane =
4404 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4405 struct drm_framebuffer *fb = plane_state->base.fb;
4406 int ret;
4407
4408 bool force_detach = !fb || !plane_state->visible;
4409
4410 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4411 intel_plane->base.base.id, intel_crtc->pipe,
4412 drm_plane_index(&intel_plane->base));
4413
4414 ret = skl_update_scaler(crtc_state, force_detach,
4415 drm_plane_index(&intel_plane->base),
4416 &plane_state->scaler_id,
4417 plane_state->base.rotation,
4418 drm_rect_width(&plane_state->src) >> 16,
4419 drm_rect_height(&plane_state->src) >> 16,
4420 drm_rect_width(&plane_state->dst),
4421 drm_rect_height(&plane_state->dst));
4422
4423 if (ret || plane_state->scaler_id < 0)
4424 return ret;
4425
a1b2278e 4426 /* check colorkey */
818ed961 4427 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4428 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4429 intel_plane->base.base.id);
a1b2278e
CK		 4430 return -EINVAL;
4431 }
4432
4433 /* Check src format */
86adf9d7
ML		 4434 switch (fb->pixel_format) {
4435 case DRM_FORMAT_RGB565:
4436 case DRM_FORMAT_XBGR8888:
4437 case DRM_FORMAT_XRGB8888:
4438 case DRM_FORMAT_ABGR8888:
4439 case DRM_FORMAT_ARGB8888:
4440 case DRM_FORMAT_XRGB2101010:
4441 case DRM_FORMAT_XBGR2101010:
4442 case DRM_FORMAT_YUYV:
4443 case DRM_FORMAT_YVYU:
4444 case DRM_FORMAT_UYVY:
4445 case DRM_FORMAT_VYUY:
4446 break;
4447 default:
4448 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4449 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4450 return -EINVAL;
a1b2278e
CK		 4451 }
4452
a1b2278e
CK		 4453 return 0;
4454}
4455
4456static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4457{
4458 struct drm_device *dev = crtc->base.dev;
4459 struct drm_i915_private *dev_priv = dev->dev_private;
4460 int pipe = crtc->pipe;
a1b2278e
CK		 4461 struct intel_crtc_scaler_state *scaler_state =
4462 &crtc->config->scaler_state;
4463
4464 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4465
4466 /* To update pfit, first update scaler state */
86adf9d7 4467 skl_update_scaler_crtc(crtc->config, !enable);
a1b2278e
CK		 4468 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4469 skl_detach_scalers(crtc);
4470 if (!enable)
4471 return;
bd2e244f 4472
6e3c9717 4473 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4474 int id;
4475
4476 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4477 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4478 return;
4479 }
4480
4481 id = scaler_state->scaler_id;
4482 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4483 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4484 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4485 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4486
4487 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4488 }
4489}
4490
b074cec8
JB		 4491static void ironlake_pfit_enable(struct intel_crtc *crtc)
4492{
4493 struct drm_device *dev = crtc->base.dev;
4494 struct drm_i915_private *dev_priv = dev->dev_private;
4495 int pipe = crtc->pipe;
4496
6e3c9717 4497 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4498 /* Force use of hard-coded filter coefficients
4499 * as some pre-programmed values are broken,
4500 * e.g. x201.
4501 */
4502 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4503 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4504 PF_PIPE_SEL_IVB(pipe));
4505 else
4506 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4507 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4508 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4509 }
4510}
4511
20bc8673 4512void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4513{
cea165c3
VS		 4514 struct drm_device *dev = crtc->base.dev;
4515 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4516
6e3c9717 4517 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4518 return;
4519
cea165c3
VS		 4520 /* We can only enable IPS after we enable a plane and wait for a vblank */
4521 intel_wait_for_vblank(dev, crtc->pipe);
4522
d77e4531 4523 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4524 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4525 mutex_lock(&dev_priv->rps.hw_lock);
4526 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4527 mutex_unlock(&dev_priv->rps.hw_lock);
4528 /* Quoting Art Runyan: "its not safe to expect any particular
4529 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4530 * mailbox." Moreover, the mailbox may return a bogus state,
4531 * so we need to just enable it and continue on.
2a114cc1
BW		 4532 */
4533 } else {
4534 I915_WRITE(IPS_CTL, IPS_ENABLE);
4535 /* The bit only becomes 1 in the next vblank, so this wait here
4536 * is essentially intel_wait_for_vblank. If we don't have this
4537 * and don't wait for vblanks until the end of crtc_enable, then
4538 * the HW state readout code will complain that the expected
4539 * IPS_CTL value is not the one we read. */
4540 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4541 DRM_ERROR("Timed out waiting for IPS enable\n");
4542 }
d77e4531
PZ		 4543}
4544
20bc8673 4545void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4546{
4547 struct drm_device *dev = crtc->base.dev;
4548 struct drm_i915_private *dev_priv = dev->dev_private;
4549
6e3c9717 4550 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4551 return;
4552
4553 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4554 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4555 mutex_lock(&dev_priv->rps.hw_lock);
4556 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4557 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4558 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4559 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4560 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4561 } else {
2a114cc1 4562 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4563 POSTING_READ(IPS_CTL);
4564 }
d77e4531
PZ		 4565
4566 /* We need to wait for a vblank before we can disable the plane. */
4567 intel_wait_for_vblank(dev, crtc->pipe);
4568}
4569
4570/** Loads the palette/gamma unit for the CRTC with the prepared values */
4571static void intel_crtc_load_lut(struct drm_crtc *crtc)
4572{
4573 struct drm_device *dev = crtc->dev;
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4576 enum pipe pipe = intel_crtc->pipe;
4577 int palreg = PALETTE(pipe);
4578 int i;
4579 bool reenable_ips = false;
4580
4581 /* The clocks have to be on to load the palette. */
53d9f4e9 4582 if (!crtc->state->active)
d77e4531
PZ		 4583 return;
4584
50360403 4585 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4586 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4587 assert_dsi_pll_enabled(dev_priv);
4588 else
4589 assert_pll_enabled(dev_priv, pipe);
4590 }
4591
4592 /* use legacy palette for Ironlake */
7a1db49a 4593 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4594 palreg = LGC_PALETTE(pipe);
4595
4596 /* Workaround : Do not read or write the pipe palette/gamma data while
4597 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4598 */
6e3c9717 4599 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4600 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4601 GAMMA_MODE_MODE_SPLIT)) {
4602 hsw_disable_ips(intel_crtc);
4603 reenable_ips = true;
4604 }
4605
4606 for (i = 0; i < 256; i++) {
4607 I915_WRITE(palreg + 4 * i,
4608 (intel_crtc->lut_r[i] << 16) |
4609 (intel_crtc->lut_g[i] << 8) |
4610 intel_crtc->lut_b[i]);
4611 }
4612
4613 if (reenable_ips)
4614 hsw_enable_ips(intel_crtc);
4615}
4616
7cac945f 4617static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4618{
7cac945f 4619 if (intel_crtc->overlay) {
d3eedb1a
VS		 4620 struct drm_device *dev = intel_crtc->base.dev;
4621 struct drm_i915_private *dev_priv = dev->dev_private;
4622
4623 mutex_lock(&dev->struct_mutex);
4624 dev_priv->mm.interruptible = false;
4625 (void) intel_overlay_switch_off(intel_crtc->overlay);
4626 dev_priv->mm.interruptible = true;
4627 mutex_unlock(&dev->struct_mutex);
4628 }
4629
4630 /* Let userspace switch the overlay on again. In most cases userspace
4631 * has to recompute where to put it anyway.
4632 */
4633}
4634
87d4300a
ML		 4635/**
4636 * intel_post_enable_primary - Perform operations after enabling primary plane
4637 * @crtc: the CRTC whose primary plane was just enabled
4638 *
4639 * Performs potentially sleeping operations that must be done after the primary
4640 * plane is enabled, such as updating FBC and IPS. Note that this may be
4641 * called due to an explicit primary plane update, or due to an implicit
4642 * re-enable that is caused when a sprite plane is updated to no longer
4643 * completely hide the primary plane.
4644 */
4645static void
4646intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4647{
4648 struct drm_device *dev = crtc->dev;
87d4300a 4649 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4651 int pipe = intel_crtc->pipe;
a5c4d7bc 4652
87d4300a
ML		 4653 /*
4654 * BDW signals flip done immediately if the plane
4655 * is disabled, even if the plane enable is already
4656 * armed to occur at the next vblank :(
4657 */
4658 if (IS_BROADWELL(dev))
4659 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4660
87d4300a
ML		 4661 /*
4662 * FIXME IPS should be fine as long as one plane is
4663 * enabled, but in practice it seems to have problems
4664 * when going from primary only to sprite only and vice
4665 * versa.
4666 */
a5c4d7bc
VS		 4667 hsw_enable_ips(intel_crtc);
4668
f99d7069 4669 /*
87d4300a
ML		 4670 * Gen2 reports pipe underruns whenever all planes are disabled.
4671 * So don't enable underrun reporting before at least some planes
4672 * are enabled.
4673 * FIXME: Need to fix the logic to work when we turn off all planes
4674 * but leave the pipe running.
f99d7069 4675 */
87d4300a
ML		 4676 if (IS_GEN2(dev))
4677 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4678
4679 /* Underruns don't raise interrupts, so check manually. */
4680 if (HAS_GMCH_DISPLAY(dev))
4681 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4682}
4683
87d4300a
ML		 4684/**
4685 * intel_pre_disable_primary - Perform operations before disabling primary plane
4686 * @crtc: the CRTC whose primary plane is to be disabled
4687 *
4688 * Performs potentially sleeping operations that must be done before the
4689 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4690 * be called due to an explicit primary plane update, or due to an implicit
4691 * disable that is caused when a sprite plane completely hides the primary
4692 * plane.
4693 */
4694static void
4695intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4696{
4697 struct drm_device *dev = crtc->dev;
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4700 int pipe = intel_crtc->pipe;
a5c4d7bc 4701
87d4300a
ML		 4702 /*
4703 * Gen2 reports pipe underruns whenever all planes are disabled.
4704 * So diasble underrun reporting before all the planes get disabled.
4705 * FIXME: Need to fix the logic to work when we turn off all planes
4706 * but leave the pipe running.
4707 */
4708 if (IS_GEN2(dev))
4709 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4710
87d4300a
ML		 4711 /*
4712 * Vblank time updates from the shadow to live plane control register
4713 * are blocked if the memory self-refresh mode is active at that
4714 * moment. So to make sure the plane gets truly disabled, disable
4715 * first the self-refresh mode. The self-refresh enable bit in turn
4716 * will be checked/applied by the HW only at the next frame start
4717 * event which is after the vblank start event, so we need to have a
4718 * wait-for-vblank between disabling the plane and the pipe.
4719 */
262cd2e1 4720 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4721 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4722 dev_priv->wm.vlv.cxsr = false;
4723 intel_wait_for_vblank(dev, pipe);
4724 }
87d4300a 4725
87d4300a
ML		 4726 /*
4727 * FIXME IPS should be fine as long as one plane is
4728 * enabled, but in practice it seems to have problems
4729 * when going from primary only to sprite only and vice
4730 * versa.
4731 */
a5c4d7bc 4732 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4733}
4734
ac21b225
ML		 4735static void intel_post_plane_update(struct intel_crtc *crtc)
4736{
4737 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4738 struct drm_device *dev = crtc->base.dev;
7733b49b 4739 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4740 struct drm_plane *plane;
4741
4742 if (atomic->wait_vblank)
4743 intel_wait_for_vblank(dev, crtc->pipe);
4744
4745 intel_frontbuffer_flip(dev, atomic->fb_bits);
4746
852eb00d
VS		 4747 if (atomic->disable_cxsr)
4748 crtc->wm.cxsr_allowed = true;
4749
f015c551
VS		 4750 if (crtc->atomic.update_wm_post)
4751 intel_update_watermarks(&crtc->base);
4752
c80ac854 4753 if (atomic->update_fbc)
7733b49b 4754 intel_fbc_update(dev_priv);
ac21b225
ML		 4755
4756 if (atomic->post_enable_primary)
4757 intel_post_enable_primary(&crtc->base);
4758
4759 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4760 intel_update_sprite_watermarks(plane, &crtc->base,
4761 0, 0, 0, false, false);
4762
4763 memset(atomic, 0, sizeof(*atomic));
4764}
4765
4766static void intel_pre_plane_update(struct intel_crtc *crtc)
4767{
4768 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4769 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4770 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4771 struct drm_plane *p;
4772
4773 /* Track fb's for any planes being disabled */
ac21b225
ML		 4774 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4775 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4776
4777 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4778 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4779 plane->frontbuffer_bit);
ac21b225
ML		 4780 mutex_unlock(&dev->struct_mutex);
4781 }
4782
4783 if (atomic->wait_for_flips)
4784 intel_crtc_wait_for_pending_flips(&crtc->base);
4785
c80ac854 4786 if (atomic->disable_fbc)
25ad93fd 4787 intel_fbc_disable_crtc(crtc);
ac21b225 4788
066cf55b
RV		 4789 if (crtc->atomic.disable_ips)
4790 hsw_disable_ips(crtc);
4791
ac21b225
ML		 4792 if (atomic->pre_disable_primary)
4793 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4794
4795 if (atomic->disable_cxsr) {
4796 crtc->wm.cxsr_allowed = false;
4797 intel_set_memory_cxsr(dev_priv, false);
4798 }
ac21b225
ML		 4799}
4800
d032ffa0 4801static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4802{
4803 struct drm_device *dev = crtc->dev;
4804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4805 struct drm_plane *p;
87d4300a
ML		 4806 int pipe = intel_crtc->pipe;
4807
7cac945f 4808 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4809
d032ffa0
ML		 4810 drm_for_each_plane_mask(p, dev, plane_mask)
4811 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4812
f99d7069
DV		 4813 /*
4814 * FIXME: Once we grow proper nuclear flip support out of this we need
4815 * to compute the mask of flip planes precisely. For the time being
4816 * consider this a flip to a NULL plane.
4817 */
4818 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4819}
4820
f67a559d
JB		 4821static void ironlake_crtc_enable(struct drm_crtc *crtc)
4822{
4823 struct drm_device *dev = crtc->dev;
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4826 struct intel_encoder *encoder;
f67a559d 4827 int pipe = intel_crtc->pipe;
f67a559d 4828
53d9f4e9 4829 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4830 return;
4831
6e3c9717 4832 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4833 intel_prepare_shared_dpll(intel_crtc);
4834
6e3c9717 4835 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4836 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4837
4838 intel_set_pipe_timings(intel_crtc);
4839
6e3c9717 4840 if (intel_crtc->config->has_pch_encoder) {
29407aab 4841 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4842 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4843 }
4844
4845 ironlake_set_pipeconf(crtc);
4846
f67a559d 4847 intel_crtc->active = true;
8664281b 4848
a72e4c9f
DV		 4849 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4850 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4851
f6736a1a 4852 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4853 if (encoder->pre_enable)
4854 encoder->pre_enable(encoder);
f67a559d 4855
6e3c9717 4856 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4857 /* Note: FDI PLL enabling _must_ be done before we enable the
4858 * cpu pipes, hence this is separate from all the other fdi/pch
4859 * enabling. */
88cefb6c 4860 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4861 } else {
4862 assert_fdi_tx_disabled(dev_priv, pipe);
4863 assert_fdi_rx_disabled(dev_priv, pipe);
4864 }
f67a559d 4865
b074cec8 4866 ironlake_pfit_enable(intel_crtc);
f67a559d 4867
9c54c0dd
JB		 4868 /*
4869 * On ILK+ LUT must be loaded before the pipe is running but with
4870 * clocks enabled
4871 */
4872 intel_crtc_load_lut(crtc);
4873
f37fcc2a 4874 intel_update_watermarks(crtc);
e1fdc473 4875 intel_enable_pipe(intel_crtc);
f67a559d 4876
6e3c9717 4877 if (intel_crtc->config->has_pch_encoder)
f67a559d 4878 ironlake_pch_enable(crtc);
c98e9dcf 4879
f9b61ff6
DV		 4880 assert_vblank_disabled(crtc);
4881 drm_crtc_vblank_on(crtc);
4882
fa5c73b1
DV		 4883 for_each_encoder_on_crtc(dev, crtc, encoder)
4884 encoder->enable(encoder);
61b77ddd
DV		 4885
4886 if (HAS_PCH_CPT(dev))
a1520318 4887 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4888}
4889
42db64ef
PZ		 4890/* IPS only exists on ULT machines and is tied to pipe A. */
4891static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4892{
f5adf94e 4893 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4894}
4895
4f771f10
PZ		 4896static void haswell_crtc_enable(struct drm_crtc *crtc)
4897{
4898 struct drm_device *dev = crtc->dev;
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4901 struct intel_encoder *encoder;
99d736a2
ML		 4902 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4903 struct intel_crtc_state *pipe_config =
4904 to_intel_crtc_state(crtc->state);
4f771f10 4905
53d9f4e9 4906 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4907 return;
4908
df8ad70c
DV		 4909 if (intel_crtc_to_shared_dpll(intel_crtc))
4910 intel_enable_shared_dpll(intel_crtc);
4911
6e3c9717 4912 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4913 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4914
4915 intel_set_pipe_timings(intel_crtc);
4916
6e3c9717
ACO		 4917 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4918 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4919 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4920 }
4921
6e3c9717 4922 if (intel_crtc->config->has_pch_encoder) {
229fca97 4923 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4924 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4925 }
4926
4927 haswell_set_pipeconf(crtc);
4928
4929 intel_set_pipe_csc(crtc);
4930
4f771f10 4931 intel_crtc->active = true;
8664281b 4932
a72e4c9f 4933 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4934 for_each_encoder_on_crtc(dev, crtc, encoder)
4935 if (encoder->pre_enable)
4936 encoder->pre_enable(encoder);
4937
6e3c9717 4938 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4939 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4940 true);
4fe9467d
ID		 4941 dev_priv->display.fdi_link_train(crtc);
4942 }
4943
1f544388 4944 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4945
ff6d9f55 4946 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4947 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4948 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4949 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4950 else
4951 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4952
4953 /*
4954 * On ILK+ LUT must be loaded before the pipe is running but with
4955 * clocks enabled
4956 */
4957 intel_crtc_load_lut(crtc);
4958
1f544388 4959 intel_ddi_set_pipe_settings(crtc);
8228c251 4960 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4961
f37fcc2a 4962 intel_update_watermarks(crtc);
e1fdc473 4963 intel_enable_pipe(intel_crtc);
42db64ef 4964
6e3c9717 4965 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4966 lpt_pch_enable(crtc);
4f771f10 4967
6e3c9717 4968 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4969 intel_ddi_set_vc_payload_alloc(crtc, true);
4970
f9b61ff6
DV		 4971 assert_vblank_disabled(crtc);
4972 drm_crtc_vblank_on(crtc);
4973
8807e55b 4974 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4975 encoder->enable(encoder);
8807e55b
JN		 4976 intel_opregion_notify_encoder(encoder, true);
4977 }
4f771f10 4978
e4916946
PZ		 4979 /* If we change the relative order between pipe/planes enabling, we need
4980 * to change the workaround. */
99d736a2
ML		 4981 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4982 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4983 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4984 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4985 }
4f771f10
PZ		 4986}
4987
3f8dce3a
DV		 4988static void ironlake_pfit_disable(struct intel_crtc *crtc)
4989{
4990 struct drm_device *dev = crtc->base.dev;
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 int pipe = crtc->pipe;
4993
4994 /* To avoid upsetting the power well on haswell only disable the pfit if
4995 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4996 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4997 I915_WRITE(PF_CTL(pipe), 0);
4998 I915_WRITE(PF_WIN_POS(pipe), 0);
4999 I915_WRITE(PF_WIN_SZ(pipe), 0);
5000 }
5001}
5002
6be4a607
JB		 5003static void ironlake_crtc_disable(struct drm_crtc *crtc)
5004{
5005 struct drm_device *dev = crtc->dev;
5006 struct drm_i915_private *dev_priv = dev->dev_private;
5007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5008 struct intel_encoder *encoder;
6be4a607 5009 int pipe = intel_crtc->pipe;
5eddb70b 5010 u32 reg, temp;
b52eb4dc 5011
ea9d758d
DV		 5012 for_each_encoder_on_crtc(dev, crtc, encoder)
5013 encoder->disable(encoder);
5014
f9b61ff6
DV		 5015 drm_crtc_vblank_off(crtc);
5016 assert_vblank_disabled(crtc);
5017
6e3c9717 5018 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5019 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5020
575f7ab7 5021 intel_disable_pipe(intel_crtc);
32f9d658 5022
3f8dce3a 5023 ironlake_pfit_disable(intel_crtc);
2c07245f 5024
5a74f70a
VS		 5025 if (intel_crtc->config->has_pch_encoder)
5026 ironlake_fdi_disable(crtc);
5027
bf49ec8c
DV		 5028 for_each_encoder_on_crtc(dev, crtc, encoder)
5029 if (encoder->post_disable)
5030 encoder->post_disable(encoder);
2c07245f 5031
6e3c9717 5032 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5033 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5034
d925c59a
DV		 5035 if (HAS_PCH_CPT(dev)) {
5036 /* disable TRANS_DP_CTL */
5037 reg = TRANS_DP_CTL(pipe);
5038 temp = I915_READ(reg);
5039 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5040 TRANS_DP_PORT_SEL_MASK);
5041 temp |= TRANS_DP_PORT_SEL_NONE;
5042 I915_WRITE(reg, temp);
5043
5044 /* disable DPLL_SEL */
5045 temp = I915_READ(PCH_DPLL_SEL);
11887397 5046 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5047 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5048 }
e3421a18 5049
d925c59a
DV		 5050 ironlake_fdi_pll_disable(intel_crtc);
5051 }
6be4a607 5052}
1b3c7a47 5053
4f771f10 5054static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5055{
4f771f10
PZ		 5056 struct drm_device *dev = crtc->dev;
5057 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5059 struct intel_encoder *encoder;
6e3c9717 5060 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5061
8807e55b
JN		 5062 for_each_encoder_on_crtc(dev, crtc, encoder) {
5063 intel_opregion_notify_encoder(encoder, false);
4f771f10 5064 encoder->disable(encoder);
8807e55b 5065 }
4f771f10 5066
f9b61ff6
DV		 5067 drm_crtc_vblank_off(crtc);
5068 assert_vblank_disabled(crtc);
5069
6e3c9717 5070 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5071 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5072 false);
575f7ab7 5073 intel_disable_pipe(intel_crtc);
4f771f10 5074
6e3c9717 5075 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5076 intel_ddi_set_vc_payload_alloc(crtc, false);
5077
ad80a810 5078 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5079
ff6d9f55 5080 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5081 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5082 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5083 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5084 else
5085 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5086
1f544388 5087 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5088
6e3c9717 5089 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5090 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5091 intel_ddi_fdi_disable(crtc);
83616634 5092 }
4f771f10 5093
97b040aa
ID		 5094 for_each_encoder_on_crtc(dev, crtc, encoder)
5095 if (encoder->post_disable)
5096 encoder->post_disable(encoder);
4f771f10
PZ		 5097}
5098
2dd24552
JB		 5099static void i9xx_pfit_enable(struct intel_crtc *crtc)
5100{
5101 struct drm_device *dev = crtc->base.dev;
5102 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5103 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5104
681a8504 5105 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5106 return;
5107
2dd24552 5108 /*
c0b03411
DV		 5109 * The panel fitter should only be adjusted whilst the pipe is disabled,
5110 * according to register description and PRM.
2dd24552 5111 */
c0b03411
DV		 5112 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5113 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5114
b074cec8
JB		 5115 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5116 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5117
5118 /* Border color in case we don't scale up to the full screen. Black by
5119 * default, change to something else for debugging. */
5120 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5121}
5122
d05410f9
DA		 5123static enum intel_display_power_domain port_to_power_domain(enum port port)
5124{
5125 switch (port) {
5126 case PORT_A:
5127 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5128 case PORT_B:
5129 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5130 case PORT_C:
5131 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5132 case PORT_D:
5133 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5134 default:
5135 WARN_ON_ONCE(1);
5136 return POWER_DOMAIN_PORT_OTHER;
5137 }
5138}
5139
77d22dca
ID		 5140#define for_each_power_domain(domain, mask) \
5141 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5142 if ((1 << (domain)) & (mask))
5143
319be8ae
ID		 5144enum intel_display_power_domain
5145intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5146{
5147 struct drm_device *dev = intel_encoder->base.dev;
5148 struct intel_digital_port *intel_dig_port;
5149
5150 switch (intel_encoder->type) {
5151 case INTEL_OUTPUT_UNKNOWN:
5152 /* Only DDI platforms should ever use this output type */
5153 WARN_ON_ONCE(!HAS_DDI(dev));
5154 case INTEL_OUTPUT_DISPLAYPORT:
5155 case INTEL_OUTPUT_HDMI:
5156 case INTEL_OUTPUT_EDP:
5157 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5158 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5159 case INTEL_OUTPUT_DP_MST:
5160 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5161 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5162 case INTEL_OUTPUT_ANALOG:
5163 return POWER_DOMAIN_PORT_CRT;
5164 case INTEL_OUTPUT_DSI:
5165 return POWER_DOMAIN_PORT_DSI;
5166 default:
5167 return POWER_DOMAIN_PORT_OTHER;
5168 }
5169}
5170
5171static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5172{
319be8ae
ID		 5173 struct drm_device *dev = crtc->dev;
5174 struct intel_encoder *intel_encoder;
5175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5176 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5177 unsigned long mask;
5178 enum transcoder transcoder;
5179
5180 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5181
5182 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5183 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5184 if (intel_crtc->config->pch_pfit.enabled ||
5185 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5186 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5187
319be8ae
ID		 5188 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5189 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5190
77d22dca
ID		 5191 return mask;
5192}
5193
679dacd4 5194static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5195{
679dacd4 5196 struct drm_device *dev = state->dev;
77d22dca
ID		 5197 struct drm_i915_private *dev_priv = dev->dev_private;
5198 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5199 struct intel_crtc *crtc;
5200
5201 /*
5202 * First get all needed power domains, then put all unneeded, to avoid
5203 * any unnecessary toggling of the power wells.
5204 */
d3fcc808 5205 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5206 enum intel_display_power_domain domain;
5207
83d65738 5208 if (!crtc->base.state->enable)
77d22dca
ID		 5209 continue;
5210
319be8ae 5211 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5212
5213 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5214 intel_display_power_get(dev_priv, domain);
5215 }
5216
27c329ed
ML		 5217 if (dev_priv->display.modeset_commit_cdclk) {
5218 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5219
5220 if (cdclk != dev_priv->cdclk_freq &&
5221 !WARN_ON(!state->allow_modeset))
5222 dev_priv->display.modeset_commit_cdclk(state);
5223 }
50f6e502 5224
d3fcc808 5225 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5226 enum intel_display_power_domain domain;
5227
5228 for_each_power_domain(domain, crtc->enabled_power_domains)
5229 intel_display_power_put(dev_priv, domain);
5230
5231 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5232 }
5233
5234 intel_display_set_init_power(dev_priv, false);
5235}
5236
560a7ae4
DL		 5237static void intel_update_max_cdclk(struct drm_device *dev)
5238{
5239 struct drm_i915_private *dev_priv = dev->dev_private;
5240
5241 if (IS_SKYLAKE(dev)) {
5242 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5243
5244 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5245 dev_priv->max_cdclk_freq = 675000;
5246 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5247 dev_priv->max_cdclk_freq = 540000;
5248 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5249 dev_priv->max_cdclk_freq = 450000;
5250 else
5251 dev_priv->max_cdclk_freq = 337500;
5252 } else if (IS_BROADWELL(dev)) {
5253 /*
5254 * FIXME with extra cooling we can allow
5255 * 540 MHz for ULX and 675 Mhz for ULT.
5256 * How can we know if extra cooling is
5257 * available? PCI ID, VTB, something else?
5258 */
5259 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5260 dev_priv->max_cdclk_freq = 450000;
5261 else if (IS_BDW_ULX(dev))
5262 dev_priv->max_cdclk_freq = 450000;
5263 else if (IS_BDW_ULT(dev))
5264 dev_priv->max_cdclk_freq = 540000;
5265 else
5266 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5267 } else if (IS_CHERRYVIEW(dev)) {
5268 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5269 } else if (IS_VALLEYVIEW(dev)) {
5270 dev_priv->max_cdclk_freq = 400000;
5271 } else {
5272 /* otherwise assume cdclk is fixed */
5273 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5274 }
5275
5276 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5277 dev_priv->max_cdclk_freq);
5278}
5279
5280static void intel_update_cdclk(struct drm_device *dev)
5281{
5282 struct drm_i915_private *dev_priv = dev->dev_private;
5283
5284 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5285 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5286 dev_priv->cdclk_freq);
5287
5288 /*
5289 * Program the gmbus_freq based on the cdclk frequency.
5290 * BSpec erroneously claims we should aim for 4MHz, but
5291 * in fact 1MHz is the correct frequency.
5292 */
5293 if (IS_VALLEYVIEW(dev)) {
5294 /*
5295 * Program the gmbus_freq based on the cdclk frequency.
5296 * BSpec erroneously claims we should aim for 4MHz, but
5297 * in fact 1MHz is the correct frequency.
5298 */
5299 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5300 }
5301
5302 if (dev_priv->max_cdclk_freq == 0)
5303 intel_update_max_cdclk(dev);
5304}
5305
70d0c574 5306static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5307{
5308 struct drm_i915_private *dev_priv = dev->dev_private;
5309 uint32_t divider;
5310 uint32_t ratio;
5311 uint32_t current_freq;
5312 int ret;
5313
5314 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5315 switch (frequency) {
5316 case 144000:
5317 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5318 ratio = BXT_DE_PLL_RATIO(60);
5319 break;
5320 case 288000:
5321 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5322 ratio = BXT_DE_PLL_RATIO(60);
5323 break;
5324 case 384000:
5325 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5326 ratio = BXT_DE_PLL_RATIO(60);
5327 break;
5328 case 576000:
5329 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5330 ratio = BXT_DE_PLL_RATIO(60);
5331 break;
5332 case 624000:
5333 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5334 ratio = BXT_DE_PLL_RATIO(65);
5335 break;
5336 case 19200:
5337 /*
5338 * Bypass frequency with DE PLL disabled. Init ratio, divider
5339 * to suppress GCC warning.
5340 */
5341 ratio = 0;
5342 divider = 0;
5343 break;
5344 default:
5345 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5346
5347 return;
5348 }
5349
5350 mutex_lock(&dev_priv->rps.hw_lock);
5351 /* Inform power controller of upcoming frequency change */
5352 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5353 0x80000000);
5354 mutex_unlock(&dev_priv->rps.hw_lock);
5355
5356 if (ret) {
5357 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5358 ret, frequency);
5359 return;
5360 }
5361
5362 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5363 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5364 current_freq = current_freq * 500 + 1000;
5365
5366 /*
5367 * DE PLL has to be disabled when
5368 * - setting to 19.2MHz (bypass, PLL isn't used)
5369 * - before setting to 624MHz (PLL needs toggling)
5370 * - before setting to any frequency from 624MHz (PLL needs toggling)
5371 */
5372 if (frequency == 19200 || frequency == 624000 ||
5373 current_freq == 624000) {
5374 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5375 /* Timeout 200us */
5376 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5377 1))
5378 DRM_ERROR("timout waiting for DE PLL unlock\n");
5379 }
5380
5381 if (frequency != 19200) {
5382 uint32_t val;
5383
5384 val = I915_READ(BXT_DE_PLL_CTL);
5385 val &= ~BXT_DE_PLL_RATIO_MASK;
5386 val |= ratio;
5387 I915_WRITE(BXT_DE_PLL_CTL, val);
5388
5389 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5390 /* Timeout 200us */
5391 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5392 DRM_ERROR("timeout waiting for DE PLL lock\n");
5393
5394 val = I915_READ(CDCLK_CTL);
5395 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5396 val |= divider;
5397 /*
5398 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5399 * enable otherwise.
5400 */
5401 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5402 if (frequency >= 500000)
5403 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5404
5405 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5406 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5407 val |= (frequency - 1000) / 500;
5408 I915_WRITE(CDCLK_CTL, val);
5409 }
5410
5411 mutex_lock(&dev_priv->rps.hw_lock);
5412 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5413 DIV_ROUND_UP(frequency, 25000));
5414 mutex_unlock(&dev_priv->rps.hw_lock);
5415
5416 if (ret) {
5417 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5418 ret, frequency);
5419 return;
5420 }
5421
a47871bd 5422 intel_update_cdclk(dev);
f8437dd1
VK		 5423}
5424
5425void broxton_init_cdclk(struct drm_device *dev)
5426{
5427 struct drm_i915_private *dev_priv = dev->dev_private;
5428 uint32_t val;
5429
5430 /*
5431 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5432 * or else the reset will hang because there is no PCH to respond.
5433 * Move the handshake programming to initialization sequence.
5434 * Previously was left up to BIOS.
5435 */
5436 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5437 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5438 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5439
5440 /* Enable PG1 for cdclk */
5441 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5442
5443 /* check if cd clock is enabled */
5444 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5445 DRM_DEBUG_KMS("Display already initialized\n");
5446 return;
5447 }
5448
5449 /*
5450 * FIXME:
5451 * - The initial CDCLK needs to be read from VBT.
5452 * Need to make this change after VBT has changes for BXT.
5453 * - check if setting the max (or any) cdclk freq is really necessary
5454 * here, it belongs to modeset time
5455 */
5456 broxton_set_cdclk(dev, 624000);
5457
5458 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5459 POSTING_READ(DBUF_CTL);
5460
f8437dd1
VK		 5461 udelay(10);
5462
5463 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5464 DRM_ERROR("DBuf power enable timeout!\n");
5465}
5466
5467void broxton_uninit_cdclk(struct drm_device *dev)
5468{
5469 struct drm_i915_private *dev_priv = dev->dev_private;
5470
5471 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5472 POSTING_READ(DBUF_CTL);
5473
f8437dd1
VK		 5474 udelay(10);
5475
5476 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5477 DRM_ERROR("DBuf power disable timeout!\n");
5478
5479 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5480 broxton_set_cdclk(dev, 19200);
5481
5482 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5483}
5484
5d96d8af
DL		 5485static const struct skl_cdclk_entry {
5486 unsigned int freq;
5487 unsigned int vco;
5488} skl_cdclk_frequencies[] = {
5489 { .freq = 308570, .vco = 8640 },
5490 { .freq = 337500, .vco = 8100 },
5491 { .freq = 432000, .vco = 8640 },
5492 { .freq = 450000, .vco = 8100 },
5493 { .freq = 540000, .vco = 8100 },
5494 { .freq = 617140, .vco = 8640 },
5495 { .freq = 675000, .vco = 8100 },
5496};
5497
5498static unsigned int skl_cdclk_decimal(unsigned int freq)
5499{
5500 return (freq - 1000) / 500;
5501}
5502
5503static unsigned int skl_cdclk_get_vco(unsigned int freq)
5504{
5505 unsigned int i;
5506
5507 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5508 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5509
5510 if (e->freq == freq)
5511 return e->vco;
5512 }
5513
5514 return 8100;
5515}
5516
5517static void
5518skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5519{
5520 unsigned int min_freq;
5521 u32 val;
5522
5523 /* select the minimum CDCLK before enabling DPLL 0 */
5524 val = I915_READ(CDCLK_CTL);
5525 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5526 val |= CDCLK_FREQ_337_308;
5527
5528 if (required_vco == 8640)
5529 min_freq = 308570;
5530 else
5531 min_freq = 337500;
5532
5533 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5534
5535 I915_WRITE(CDCLK_CTL, val);
5536 POSTING_READ(CDCLK_CTL);
5537
5538 /*
5539 * We always enable DPLL0 with the lowest link rate possible, but still
5540 * taking into account the VCO required to operate the eDP panel at the
5541 * desired frequency. The usual DP link rates operate with a VCO of
5542 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5543 * The modeset code is responsible for the selection of the exact link
5544 * rate later on, with the constraint of choosing a frequency that
5545 * works with required_vco.
5546 */
5547 val = I915_READ(DPLL_CTRL1);
5548
5549 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5550 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5551 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5552 if (required_vco == 8640)
5553 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5554 SKL_DPLL0);
5555 else
5556 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5557 SKL_DPLL0);
5558
5559 I915_WRITE(DPLL_CTRL1, val);
5560 POSTING_READ(DPLL_CTRL1);
5561
5562 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5563
5564 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5565 DRM_ERROR("DPLL0 not locked\n");
5566}
5567
5568static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5569{
5570 int ret;
5571 u32 val;
5572
5573 /* inform PCU we want to change CDCLK */
5574 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5575 mutex_lock(&dev_priv->rps.hw_lock);
5576 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5577 mutex_unlock(&dev_priv->rps.hw_lock);
5578
5579 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5580}
5581
5582static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5583{
5584 unsigned int i;
5585
5586 for (i = 0; i < 15; i++) {
5587 if (skl_cdclk_pcu_ready(dev_priv))
5588 return true;
5589 udelay(10);
5590 }
5591
5592 return false;
5593}
5594
5595static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5596{
560a7ae4 5597 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5598 u32 freq_select, pcu_ack;
5599
5600 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5601
5602 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5603 DRM_ERROR("failed to inform PCU about cdclk change\n");
5604 return;
5605 }
5606
5607 /* set CDCLK_CTL */
5608 switch(freq) {
5609 case 450000:
5610 case 432000:
5611 freq_select = CDCLK_FREQ_450_432;
5612 pcu_ack = 1;
5613 break;
5614 case 540000:
5615 freq_select = CDCLK_FREQ_540;
5616 pcu_ack = 2;
5617 break;
5618 case 308570:
5619 case 337500:
5620 default:
5621 freq_select = CDCLK_FREQ_337_308;
5622 pcu_ack = 0;
5623 break;
5624 case 617140:
5625 case 675000:
5626 freq_select = CDCLK_FREQ_675_617;
5627 pcu_ack = 3;
5628 break;
5629 }
5630
5631 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5632 POSTING_READ(CDCLK_CTL);
5633
5634 /* inform PCU of the change */
5635 mutex_lock(&dev_priv->rps.hw_lock);
5636 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5637 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5638
5639 intel_update_cdclk(dev);
5d96d8af
DL		 5640}
5641
5642void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5643{
5644 /* disable DBUF power */
5645 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5646 POSTING_READ(DBUF_CTL);
5647
5648 udelay(10);
5649
5650 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5651 DRM_ERROR("DBuf power disable timeout\n");
5652
5653 /* disable DPLL0 */
5654 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5655 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5656 DRM_ERROR("Couldn't disable DPLL0\n");
5657
5658 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5659}
5660
5661void skl_init_cdclk(struct drm_i915_private *dev_priv)
5662{
5663 u32 val;
5664 unsigned int required_vco;
5665
5666 /* enable PCH reset handshake */
5667 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5668 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5669
5670 /* enable PG1 and Misc I/O */
5671 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5672
5673 /* DPLL0 already enabed !? */
5674 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5675 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5676 return;
5677 }
5678
5679 /* enable DPLL0 */
5680 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5681 skl_dpll0_enable(dev_priv, required_vco);
5682
5683 /* set CDCLK to the frequency the BIOS chose */
5684 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5685
5686 /* enable DBUF power */
5687 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5688 POSTING_READ(DBUF_CTL);
5689
5690 udelay(10);
5691
5692 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5693 DRM_ERROR("DBuf power enable timeout\n");
5694}
5695
dfcab17e 5696/* returns HPLL frequency in kHz */
f8bf63fd 5697static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5698{
586f49dc 5699 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5700
586f49dc 5701 /* Obtain SKU information */
a580516d 5702 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5703 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5704 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5705 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5706
dfcab17e 5707 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5708}
5709
5710/* Adjust CDclk dividers to allow high res or save power if possible */
5711static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5712{
5713 struct drm_i915_private *dev_priv = dev->dev_private;
5714 u32 val, cmd;
5715
164dfd28
VK		 5716 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5717 != dev_priv->cdclk_freq);
d60c4473 5718
dfcab17e 5719 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5720 cmd = 2;
dfcab17e 5721 else if (cdclk == 266667)
30a970c6
JB		 5722 cmd = 1;
5723 else
5724 cmd = 0;
5725
5726 mutex_lock(&dev_priv->rps.hw_lock);
5727 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5728 val &= ~DSPFREQGUAR_MASK;
5729 val |= (cmd << DSPFREQGUAR_SHIFT);
5730 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5731 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5732 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5733 50)) {
5734 DRM_ERROR("timed out waiting for CDclk change\n");
5735 }
5736 mutex_unlock(&dev_priv->rps.hw_lock);
5737
54433e91
VS		 5738 mutex_lock(&dev_priv->sb_lock);
5739
dfcab17e 5740 if (cdclk == 400000) {
6bcda4f0 5741 u32 divider;
30a970c6 5742
6bcda4f0 5743 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5744
30a970c6
JB		 5745 /* adjust cdclk divider */
5746 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5747 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5748 val |= divider;
5749 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5750
5751 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5752 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5753 50))
5754 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5755 }
5756
30a970c6
JB		 5757 /* adjust self-refresh exit latency value */
5758 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5759 val &= ~0x7f;
5760
5761 /*
5762 * For high bandwidth configs, we set a higher latency in the bunit
5763 * so that the core display fetch happens in time to avoid underruns.
5764 */
dfcab17e 5765 if (cdclk == 400000)
30a970c6
JB		 5766 val |= 4500 / 250; /* 4.5 usec */
5767 else
5768 val |= 3000 / 250; /* 3.0 usec */
5769 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5770
a580516d 5771 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5772
b6283055 5773 intel_update_cdclk(dev);
30a970c6
JB		 5774}
5775
383c5a6a
VS		 5776static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5777{
5778 struct drm_i915_private *dev_priv = dev->dev_private;
5779 u32 val, cmd;
5780
164dfd28
VK		 5781 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5782 != dev_priv->cdclk_freq);
383c5a6a
VS		 5783
5784 switch (cdclk) {
383c5a6a
VS		 5785 case 333333:
5786 case 320000:
383c5a6a 5787 case 266667:
383c5a6a 5788 case 200000:
383c5a6a
VS		 5789 break;
5790 default:
5f77eeb0 5791 MISSING_CASE(cdclk);
383c5a6a
VS		 5792 return;
5793 }
5794
9d0d3fda
VS		 5795 /*
5796 * Specs are full of misinformation, but testing on actual
5797 * hardware has shown that we just need to write the desired
5798 * CCK divider into the Punit register.
5799 */
5800 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5801
383c5a6a
VS		 5802 mutex_lock(&dev_priv->rps.hw_lock);
5803 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5804 val &= ~DSPFREQGUAR_MASK_CHV;
5805 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5806 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5807 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5808 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5809 50)) {
5810 DRM_ERROR("timed out waiting for CDclk change\n");
5811 }
5812 mutex_unlock(&dev_priv->rps.hw_lock);
5813
b6283055 5814 intel_update_cdclk(dev);
383c5a6a
VS		 5815}
5816
30a970c6
JB		 5817static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5818 int max_pixclk)
5819{
6bcda4f0 5820 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5821 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5822
30a970c6
JB		 5823 /*
5824 * Really only a few cases to deal with, as only 4 CDclks are supported:
5825 * 200MHz
5826 * 267MHz
29dc7ef3 5827 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5828 * 400MHz (VLV only)
5829 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5830 * of the lower bin and adjust if needed.
e37c67a1
VS		 5831 *
5832 * We seem to get an unstable or solid color picture at 200MHz.
5833 * Not sure what's wrong. For now use 200MHz only when all pipes
5834 * are off.
30a970c6 5835 */
6cca3195
VS		 5836 if (!IS_CHERRYVIEW(dev_priv) &&
5837 max_pixclk > freq_320*limit/100)
dfcab17e 5838 return 400000;
6cca3195 5839 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5840 return freq_320;
e37c67a1 5841 else if (max_pixclk > 0)
dfcab17e 5842 return 266667;
e37c67a1
VS		 5843 else
5844 return 200000;
30a970c6
JB		 5845}
5846
f8437dd1
VK		 5847static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5848 int max_pixclk)
5849{
5850 /*
5851 * FIXME:
5852 * - remove the guardband, it's not needed on BXT
5853 * - set 19.2MHz bypass frequency if there are no active pipes
5854 */
5855 if (max_pixclk > 576000*9/10)
5856 return 624000;
5857 else if (max_pixclk > 384000*9/10)
5858 return 576000;
5859 else if (max_pixclk > 288000*9/10)
5860 return 384000;
5861 else if (max_pixclk > 144000*9/10)
5862 return 288000;
5863 else
5864 return 144000;
5865}
5866
a821fc46
ACO		 5867/* Compute the max pixel clock for new configuration. Uses atomic state if
5868 * that's non-NULL, look at current state otherwise. */
5869static int intel_mode_max_pixclk(struct drm_device *dev,
5870 struct drm_atomic_state *state)
30a970c6 5871{
30a970c6 5872 struct intel_crtc *intel_crtc;
304603f4 5873 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5874 int max_pixclk = 0;
5875
d3fcc808 5876 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5877 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5878 if (IS_ERR(crtc_state))
5879 return PTR_ERR(crtc_state);
5880
5881 if (!crtc_state->base.enable)
5882 continue;
5883
5884 max_pixclk = max(max_pixclk,
5885 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5886 }
5887
5888 return max_pixclk;
5889}
5890
27c329ed 5891static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5892{
27c329ed
ML		 5893 struct drm_device *dev = state->dev;
5894 struct drm_i915_private *dev_priv = dev->dev_private;
5895 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5896
304603f4
ACO		 5897 if (max_pixclk < 0)
5898 return max_pixclk;
30a970c6 5899
27c329ed
ML		 5900 to_intel_atomic_state(state)->cdclk =
5901 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5902
27c329ed
ML		 5903 return 0;
5904}
304603f4 5905
27c329ed
ML		 5906static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5907{
5908 struct drm_device *dev = state->dev;
5909 struct drm_i915_private *dev_priv = dev->dev_private;
5910 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5911
27c329ed
ML		 5912 if (max_pixclk < 0)
5913 return max_pixclk;
85a96e7a 5914
27c329ed
ML		 5915 to_intel_atomic_state(state)->cdclk =
5916 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5917
27c329ed 5918 return 0;
30a970c6
JB		 5919}
5920
1e69cd74
VS		 5921static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5922{
5923 unsigned int credits, default_credits;
5924
5925 if (IS_CHERRYVIEW(dev_priv))
5926 default_credits = PFI_CREDIT(12);
5927 else
5928 default_credits = PFI_CREDIT(8);
5929
164dfd28 5930 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5931 /* CHV suggested value is 31 or 63 */
5932 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5933 credits = PFI_CREDIT_63;
1e69cd74
VS		 5934 else
5935 credits = PFI_CREDIT(15);
5936 } else {
5937 credits = default_credits;
5938 }
5939
5940 /*
5941 * WA - write default credits before re-programming
5942 * FIXME: should we also set the resend bit here?
5943 */
5944 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5945 default_credits);
5946
5947 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5948 credits | PFI_CREDIT_RESEND);
5949
5950 /*
5951 * FIXME is this guaranteed to clear
5952 * immediately or should we poll for it?
5953 */
5954 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5955}
5956
27c329ed 5957static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5958{
a821fc46 5959 struct drm_device *dev = old_state->dev;
27c329ed 5960 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5961 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5962
27c329ed
ML		 5963 /*
5964 * FIXME: We can end up here with all power domains off, yet
5965 * with a CDCLK frequency other than the minimum. To account
5966 * for this take the PIPE-A power domain, which covers the HW
5967 * blocks needed for the following programming. This can be
5968 * removed once it's guaranteed that we get here either with
5969 * the minimum CDCLK set, or the required power domains
5970 * enabled.
5971 */
5972 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5973
27c329ed
ML		 5974 if (IS_CHERRYVIEW(dev))
5975 cherryview_set_cdclk(dev, req_cdclk);
5976 else
5977 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5978
27c329ed 5979 vlv_program_pfi_credits(dev_priv);
1e69cd74 5980
27c329ed 5981 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 5982}
5983
89b667f8
JB		 5984static void valleyview_crtc_enable(struct drm_crtc *crtc)
5985{
5986 struct drm_device *dev = crtc->dev;
a72e4c9f 5987 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5989 struct intel_encoder *encoder;
5990 int pipe = intel_crtc->pipe;
23538ef1 5991 bool is_dsi;
89b667f8 5992
53d9f4e9 5993 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 5994 return;
5995
409ee761 5996 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5997
1ae0d137
VS		 5998 if (!is_dsi) {
5999 if (IS_CHERRYVIEW(dev))
6e3c9717 6000 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6001 else
6e3c9717 6002 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6003 }
5b18e57c 6004
6e3c9717 6005 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6006 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6007
6008 intel_set_pipe_timings(intel_crtc);
6009
c14b0485
VS		 6010 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012
6013 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6014 I915_WRITE(CHV_CANVAS(pipe), 0);
6015 }
6016
5b18e57c
DV		 6017 i9xx_set_pipeconf(intel_crtc);
6018
89b667f8 6019 intel_crtc->active = true;
89b667f8 6020
a72e4c9f 6021 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6022
89b667f8
JB		 6023 for_each_encoder_on_crtc(dev, crtc, encoder)
6024 if (encoder->pre_pll_enable)
6025 encoder->pre_pll_enable(encoder);
6026
9d556c99
CML		 6027 if (!is_dsi) {
6028 if (IS_CHERRYVIEW(dev))
6e3c9717 6029 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6030 else
6e3c9717 6031 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6032 }
89b667f8
JB		 6033
6034 for_each_encoder_on_crtc(dev, crtc, encoder)
6035 if (encoder->pre_enable)
6036 encoder->pre_enable(encoder);
6037
2dd24552
JB		 6038 i9xx_pfit_enable(intel_crtc);
6039
63cbb074
VS		 6040 intel_crtc_load_lut(crtc);
6041
e1fdc473 6042 intel_enable_pipe(intel_crtc);
be6a6f8e 6043
4b3a9526
VS		 6044 assert_vblank_disabled(crtc);
6045 drm_crtc_vblank_on(crtc);
6046
f9b61ff6
DV		 6047 for_each_encoder_on_crtc(dev, crtc, encoder)
6048 encoder->enable(encoder);
89b667f8
JB		 6049}
6050
f13c2ef3
DV		 6051static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6052{
6053 struct drm_device *dev = crtc->base.dev;
6054 struct drm_i915_private *dev_priv = dev->dev_private;
6055
6e3c9717
ACO		 6056 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6057 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6058}
6059
0b8765c6 6060static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6061{
6062 struct drm_device *dev = crtc->dev;
a72e4c9f 6063 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6065 struct intel_encoder *encoder;
79e53945 6066 int pipe = intel_crtc->pipe;
79e53945 6067
53d9f4e9 6068 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6069 return;
6070
f13c2ef3
DV		 6071 i9xx_set_pll_dividers(intel_crtc);
6072
6e3c9717 6073 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6074 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6075
6076 intel_set_pipe_timings(intel_crtc);
6077
5b18e57c
DV		 6078 i9xx_set_pipeconf(intel_crtc);
6079
f7abfe8b 6080 intel_crtc->active = true;
6b383a7f 6081
4a3436e8 6082 if (!IS_GEN2(dev))
a72e4c9f 6083 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6084
9d6d9f19
MK		 6085 for_each_encoder_on_crtc(dev, crtc, encoder)
6086 if (encoder->pre_enable)
6087 encoder->pre_enable(encoder);
6088
f6736a1a
DV		 6089 i9xx_enable_pll(intel_crtc);
6090
2dd24552
JB		 6091 i9xx_pfit_enable(intel_crtc);
6092
63cbb074
VS		 6093 intel_crtc_load_lut(crtc);
6094
f37fcc2a 6095 intel_update_watermarks(crtc);
e1fdc473 6096 intel_enable_pipe(intel_crtc);
be6a6f8e 6097
4b3a9526
VS		 6098 assert_vblank_disabled(crtc);
6099 drm_crtc_vblank_on(crtc);
6100
f9b61ff6
DV		 6101 for_each_encoder_on_crtc(dev, crtc, encoder)
6102 encoder->enable(encoder);
0b8765c6 6103}
79e53945 6104
87476d63
DV		 6105static void i9xx_pfit_disable(struct intel_crtc *crtc)
6106{
6107 struct drm_device *dev = crtc->base.dev;
6108 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6109
6e3c9717 6110 if (!crtc->config->gmch_pfit.control)
328d8e82 6111 return;
87476d63 6112
328d8e82 6113 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6114
328d8e82
DV		 6115 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6116 I915_READ(PFIT_CONTROL));
6117 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6118}
6119
0b8765c6
JB		 6120static void i9xx_crtc_disable(struct drm_crtc *crtc)
6121{
6122 struct drm_device *dev = crtc->dev;
6123 struct drm_i915_private *dev_priv = dev->dev_private;
6124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6125 struct intel_encoder *encoder;
0b8765c6 6126 int pipe = intel_crtc->pipe;
ef9c3aee 6127
6304cd91
VS		 6128 /*
6129 * On gen2 planes are double buffered but the pipe isn't, so we must
6130 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6131 * We also need to wait on all gmch platforms because of the
6132 * self-refresh mode constraint explained above.
6304cd91 6133 */
564ed191 6134 intel_wait_for_vblank(dev, pipe);
6304cd91 6135
4b3a9526
VS		 6136 for_each_encoder_on_crtc(dev, crtc, encoder)
6137 encoder->disable(encoder);
6138
f9b61ff6
DV		 6139 drm_crtc_vblank_off(crtc);
6140 assert_vblank_disabled(crtc);
6141
575f7ab7 6142 intel_disable_pipe(intel_crtc);
24a1f16d 6143
87476d63 6144 i9xx_pfit_disable(intel_crtc);
24a1f16d 6145
89b667f8
JB		 6146 for_each_encoder_on_crtc(dev, crtc, encoder)
6147 if (encoder->post_disable)
6148 encoder->post_disable(encoder);
6149
409ee761 6150 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6151 if (IS_CHERRYVIEW(dev))
6152 chv_disable_pll(dev_priv, pipe);
6153 else if (IS_VALLEYVIEW(dev))
6154 vlv_disable_pll(dev_priv, pipe);
6155 else
1c4e0274 6156 i9xx_disable_pll(intel_crtc);
076ed3b2 6157 }
0b8765c6 6158
4a3436e8 6159 if (!IS_GEN2(dev))
a72e4c9f 6160 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6161}
6162
b17d48e2
ML		 6163static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6164{
6165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6166 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6167 enum intel_display_power_domain domain;
6168 unsigned long domains;
6169
6170 if (!intel_crtc->active)
6171 return;
6172
a539205a
ML		 6173 if (to_intel_plane_state(crtc->primary->state)->visible) {
6174 intel_crtc_wait_for_pending_flips(crtc);
6175 intel_pre_disable_primary(crtc);
6176 }
6177
d032ffa0 6178 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2
ML		 6179 dev_priv->display.crtc_disable(crtc);
6180
6181 domains = intel_crtc->enabled_power_domains;
6182 for_each_power_domain(domain, domains)
6183 intel_display_power_put(dev_priv, domain);
6184 intel_crtc->enabled_power_domains = 0;
6185}
6186
6b72d486
ML		 6187/*
6188 * turn all crtc's off, but do not adjust state
6189 * This has to be paired with a call to intel_modeset_setup_hw_state.
6190 */
9716c691 6191void intel_display_suspend(struct drm_device *dev)
ee7b9f93 6192{
6b72d486
ML		 6193 struct drm_crtc *crtc;
6194
b17d48e2
ML		 6195 for_each_crtc(dev, crtc)
6196 intel_crtc_disable_noatomic(crtc);
ee7b9f93
JB		 6197}
6198
b04c5bd6 6199/* Master function to enable/disable CRTC and corresponding power wells */
5da76e94 6200int intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6201{
6202 struct drm_device *dev = crtc->dev;
5da76e94
ML		 6203 struct drm_mode_config *config = &dev->mode_config;
6204 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
0e572fe7 6205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5da76e94
ML		 6206 struct intel_crtc_state *pipe_config;
6207 struct drm_atomic_state *state;
6208 int ret;
976f8a20 6209
1b509259 6210 if (enable == intel_crtc->active)
5da76e94 6211 return 0;
0e572fe7 6212
1b509259 6213 if (enable && !crtc->state->enable)
5da76e94 6214 return 0;
1b509259 6215
5da76e94
ML		 6216 /* this function should be called with drm_modeset_lock_all for now */
6217 if (WARN_ON(!ctx))
6218 return -EIO;
6219 lockdep_assert_held(&ctx->ww_ctx);
1b509259 6220
5da76e94
ML		 6221 state = drm_atomic_state_alloc(dev);
6222 if (WARN_ON(!state))
6223 return -ENOMEM;
1b509259 6224
5da76e94
ML		 6225 state->acquire_ctx = ctx;
6226 state->allow_modeset = true;
6227
6228 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6229 if (IS_ERR(pipe_config)) {
6230 ret = PTR_ERR(pipe_config);
6231 goto err;
0e572fe7 6232 }
5da76e94
ML		 6233 pipe_config->base.active = enable;
6234
6235 ret = intel_set_mode(state);
6236 if (!ret)
6237 return ret;
6238
6239err:
6240 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6241 drm_atomic_state_free(state);
6242 return ret;
b04c5bd6
BF		 6243}
6244
6245/**
6246 * Sets the power management mode of the pipe and plane.
6247 */
6248void intel_crtc_update_dpms(struct drm_crtc *crtc)
6249{
6250 struct drm_device *dev = crtc->dev;
6251 struct intel_encoder *intel_encoder;
6252 bool enable = false;
6253
6254 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6255 enable |= intel_encoder->connectors_active;
6256
6257 intel_crtc_control(crtc, enable);
cdd59983
CW		 6258}
6259
ea5b213a 6260void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6261{
4ef69c7a 6262 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6263
ea5b213a
CW		 6264 drm_encoder_cleanup(encoder);
6265 kfree(intel_encoder);
7e7d76c3
JB		 6266}
6267
9237329d 6268/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6269 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6270 * state of the entire output pipe. */
9237329d 6271static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6272{
5ab432ef
DV		 6273 if (mode == DRM_MODE_DPMS_ON) {
6274 encoder->connectors_active = true;
6275
b2cabb0e 6276 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6277 } else {
6278 encoder->connectors_active = false;
6279
b2cabb0e 6280 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6281 }
79e53945
JB		 6282}
6283
0a91ca29
DV		 6284/* Cross check the actual hw state with our own modeset state tracking (and it's
6285 * internal consistency). */
b980514c 6286static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6287{
0a91ca29
DV		 6288 if (connector->get_hw_state(connector)) {
6289 struct intel_encoder *encoder = connector->encoder;
6290 struct drm_crtc *crtc;
6291 bool encoder_enabled;
6292 enum pipe pipe;
6293
6294 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6295 connector->base.base.id,
c23cc417 6296 connector->base.name);
0a91ca29 6297
0e32b39c
DA		 6298 /* there is no real hw state for MST connectors */
6299 if (connector->mst_port)
6300 return;
6301
e2c719b7 6302 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6303 "wrong connector dpms state\n");
e2c719b7 6304 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6305 "active connector not linked to encoder\n");
0a91ca29 6306
36cd7444 6307 if (encoder) {
e2c719b7 6308 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6309 "encoder->connectors_active not set\n");
6310
6311 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6312 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6313 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6314 return;
0a91ca29 6315
36cd7444 6316 crtc = encoder->base.crtc;
0a91ca29 6317
83d65738
MR		 6318 I915_STATE_WARN(!crtc->state->enable,
6319 "crtc not enabled\n");
e2c719b7
RC		 6320 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6321 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6322 "encoder active on the wrong pipe\n");
6323 }
0a91ca29 6324 }
79e53945
JB		 6325}
6326
08d9bc92
ACO		 6327int intel_connector_init(struct intel_connector *connector)
6328{
6329 struct drm_connector_state *connector_state;
6330
6331 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6332 if (!connector_state)
6333 return -ENOMEM;
6334
6335 connector->base.state = connector_state;
6336 return 0;
6337}
6338
6339struct intel_connector *intel_connector_alloc(void)
6340{
6341 struct intel_connector *connector;
6342
6343 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6344 if (!connector)
6345 return NULL;
6346
6347 if (intel_connector_init(connector) < 0) {
6348 kfree(connector);
6349 return NULL;
6350 }
6351
6352 return connector;
6353}
6354
5ab432ef
DV		 6355/* Even simpler default implementation, if there's really no special case to
6356 * consider. */
6357void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6358{
5ab432ef
DV		 6359 /* All the simple cases only support two dpms states. */
6360 if (mode != DRM_MODE_DPMS_ON)
6361 mode = DRM_MODE_DPMS_OFF;
d4270e57 6362
5ab432ef
DV		 6363 if (mode == connector->dpms)
6364 return;
6365
6366 connector->dpms = mode;
6367
6368 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6369 if (connector->encoder)
6370 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6371
b980514c 6372 intel_modeset_check_state(connector->dev);
79e53945
JB		 6373}
6374
f0947c37
DV		 6375/* Simple connector->get_hw_state implementation for encoders that support only
6376 * one connector and no cloning and hence the encoder state determines the state
6377 * of the connector. */
6378bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6379{
24929352 6380 enum pipe pipe = 0;
f0947c37 6381 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6382
f0947c37 6383 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6384}
6385
6d293983 6386static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6387{
6d293983
ACO		 6388 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6389 return crtc_state->fdi_lanes;
d272ddfa
VS		 6390
6391 return 0;
6392}
6393
6d293983 6394static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6395 struct intel_crtc_state *pipe_config)
1857e1da 6396{
6d293983
ACO		 6397 struct drm_atomic_state *state = pipe_config->base.state;
6398 struct intel_crtc *other_crtc;
6399 struct intel_crtc_state *other_crtc_state;
6400
1857e1da
DV		 6401 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6402 pipe_name(pipe), pipe_config->fdi_lanes);
6403 if (pipe_config->fdi_lanes > 4) {
6404 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6405 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6406 return -EINVAL;
1857e1da
DV		 6407 }
6408
bafb6553 6409 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6410 if (pipe_config->fdi_lanes > 2) {
6411 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6412 pipe_config->fdi_lanes);
6d293983 6413 return -EINVAL;
1857e1da 6414 } else {
6d293983 6415 return 0;
1857e1da
DV		 6416 }
6417 }
6418
6419 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6420 return 0;
1857e1da
DV		 6421
6422 /* Ivybridge 3 pipe is really complicated */
6423 switch (pipe) {
6424 case PIPE_A:
6d293983 6425 return 0;
1857e1da 6426 case PIPE_B:
6d293983
ACO		 6427 if (pipe_config->fdi_lanes <= 2)
6428 return 0;
6429
6430 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6431 other_crtc_state =
6432 intel_atomic_get_crtc_state(state, other_crtc);
6433 if (IS_ERR(other_crtc_state))
6434 return PTR_ERR(other_crtc_state);
6435
6436 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6437 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6438 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6439 return -EINVAL;
1857e1da 6440 }
6d293983 6441 return 0;
1857e1da 6442 case PIPE_C:
251cc67c
VS		 6443 if (pipe_config->fdi_lanes > 2) {
6444 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6445 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6446 return -EINVAL;
251cc67c 6447 }
6d293983
ACO		 6448
6449 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6450 other_crtc_state =
6451 intel_atomic_get_crtc_state(state, other_crtc);
6452 if (IS_ERR(other_crtc_state))
6453 return PTR_ERR(other_crtc_state);
6454
6455 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6456 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6457 return -EINVAL;
1857e1da 6458 }
6d293983 6459 return 0;
1857e1da
DV		 6460 default:
6461 BUG();
6462 }
6463}
6464
e29c22c0
DV		 6465#define RETRY 1
6466static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6467 struct intel_crtc_state *pipe_config)
877d48d5 6468{
1857e1da 6469 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6470 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6471 int lane, link_bw, fdi_dotclock, ret;
6472 bool needs_recompute = false;
877d48d5 6473
e29c22c0 6474retry:
877d48d5
DV		 6475 /* FDI is a binary signal running at ~2.7GHz, encoding
6476 * each output octet as 10 bits. The actual frequency
6477 * is stored as a divider into a 100MHz clock, and the
6478 * mode pixel clock is stored in units of 1KHz.
6479 * Hence the bw of each lane in terms of the mode signal
6480 * is:
6481 */
6482 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6483
241bfc38 6484 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6485
2bd89a07 6486 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6487 pipe_config->pipe_bpp);
6488
6489 pipe_config->fdi_lanes = lane;
6490
2bd89a07 6491 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6492 link_bw, &pipe_config->fdi_m_n);
1857e1da 6493
6d293983
ACO		 6494 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6495 intel_crtc->pipe, pipe_config);
6496 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6497 pipe_config->pipe_bpp -= 2*3;
6498 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6499 pipe_config->pipe_bpp);
6500 needs_recompute = true;
6501 pipe_config->bw_constrained = true;
6502
6503 goto retry;
6504 }
6505
6506 if (needs_recompute)
6507 return RETRY;
6508
6d293983 6509 return ret;
877d48d5
DV		 6510}
6511
8cfb3407
VS		 6512static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6513 struct intel_crtc_state *pipe_config)
6514{
6515 if (pipe_config->pipe_bpp > 24)
6516 return false;
6517
6518 /* HSW can handle pixel rate up to cdclk? */
6519 if (IS_HASWELL(dev_priv->dev))
6520 return true;
6521
6522 /*
b432e5cf
VS		 6523 * We compare against max which means we must take
6524 * the increased cdclk requirement into account when
6525 * calculating the new cdclk.
6526 *
6527 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6528 */
6529 return ilk_pipe_pixel_rate(pipe_config) <=
6530 dev_priv->max_cdclk_freq * 95 / 100;
6531}
6532
42db64ef 6533static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6534 struct intel_crtc_state *pipe_config)
42db64ef 6535{
8cfb3407
VS		 6536 struct drm_device *dev = crtc->base.dev;
6537 struct drm_i915_private *dev_priv = dev->dev_private;
6538
d330a953 6539 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6540 hsw_crtc_supports_ips(crtc) &&
6541 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6542}
6543
a43f6e0f 6544static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6545 struct intel_crtc_state *pipe_config)
79e53945 6546{
a43f6e0f 6547 struct drm_device *dev = crtc->base.dev;
8bd31e67 6548 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6549 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6550
ad3a4479 6551 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6552 if (INTEL_INFO(dev)->gen < 4) {
44913155 6553 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6554
6555 /*
6556 * Enable pixel doubling when the dot clock
6557 * is > 90% of the (display) core speed.
6558 *
b397c96b
VS		 6559 * GDG double wide on either pipe,
6560 * otherwise pipe A only.
cf532bb2 6561 */
b397c96b 6562 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6563 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6564 clock_limit *= 2;
cf532bb2 6565 pipe_config->double_wide = true;
ad3a4479
VS		 6566 }
6567
241bfc38 6568 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6569 return -EINVAL;
2c07245f 6570 }
89749350 6571
1d1d0e27
VS		 6572 /*
6573 * Pipe horizontal size must be even in:
6574 * - DVO ganged mode
6575 * - LVDS dual channel mode
6576 * - Double wide pipe
6577 */
a93e255f 6578 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6579 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6580 pipe_config->pipe_src_w &= ~1;
6581
8693a824
DL		 6582 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6583 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6584 */
6585 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6586 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6587 return -EINVAL;
44f46b42 6588
f5adf94e 6589 if (HAS_IPS(dev))
a43f6e0f
DV		 6590 hsw_compute_ips_config(crtc, pipe_config);
6591
877d48d5 6592 if (pipe_config->has_pch_encoder)
a43f6e0f 6593 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6594
cf5a15be 6595 return 0;
79e53945
JB		 6596}
6597
1652d19e
VS		 6598static int skylake_get_display_clock_speed(struct drm_device *dev)
6599{
6600 struct drm_i915_private *dev_priv = to_i915(dev);
6601 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6602 uint32_t cdctl = I915_READ(CDCLK_CTL);
6603 uint32_t linkrate;
6604
414355a7 6605 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6606 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6607
6608 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6609 return 540000;
6610
6611 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6612 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6613
71cd8423
DL		 6614 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6615 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6616 /* vco 8640 */
6617 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6618 case CDCLK_FREQ_450_432:
6619 return 432000;
6620 case CDCLK_FREQ_337_308:
6621 return 308570;
6622 case CDCLK_FREQ_675_617:
6623 return 617140;
6624 default:
6625 WARN(1, "Unknown cd freq selection\n");
6626 }
6627 } else {
6628 /* vco 8100 */
6629 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6630 case CDCLK_FREQ_450_432:
6631 return 450000;
6632 case CDCLK_FREQ_337_308:
6633 return 337500;
6634 case CDCLK_FREQ_675_617:
6635 return 675000;
6636 default:
6637 WARN(1, "Unknown cd freq selection\n");
6638 }
6639 }
6640
6641 /* error case, do as if DPLL0 isn't enabled */
6642 return 24000;
6643}
6644
acd3f3d3
BP		 6645static int broxton_get_display_clock_speed(struct drm_device *dev)
6646{
6647 struct drm_i915_private *dev_priv = to_i915(dev);
6648 uint32_t cdctl = I915_READ(CDCLK_CTL);
6649 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6650 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6651 int cdclk;
6652
6653 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6654 return 19200;
6655
6656 cdclk = 19200 * pll_ratio / 2;
6657
6658 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6659 case BXT_CDCLK_CD2X_DIV_SEL_1:
6660 return cdclk; /* 576MHz or 624MHz */
6661 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6662 return cdclk * 2 / 3; /* 384MHz */
6663 case BXT_CDCLK_CD2X_DIV_SEL_2:
6664 return cdclk / 2; /* 288MHz */
6665 case BXT_CDCLK_CD2X_DIV_SEL_4:
6666 return cdclk / 4; /* 144MHz */
6667 }
6668
6669 /* error case, do as if DE PLL isn't enabled */
6670 return 19200;
6671}
6672
1652d19e
VS		 6673static int broadwell_get_display_clock_speed(struct drm_device *dev)
6674{
6675 struct drm_i915_private *dev_priv = dev->dev_private;
6676 uint32_t lcpll = I915_READ(LCPLL_CTL);
6677 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6678
6679 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6680 return 800000;
6681 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6682 return 450000;
6683 else if (freq == LCPLL_CLK_FREQ_450)
6684 return 450000;
6685 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6686 return 540000;
6687 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6688 return 337500;
6689 else
6690 return 675000;
6691}
6692
6693static int haswell_get_display_clock_speed(struct drm_device *dev)
6694{
6695 struct drm_i915_private *dev_priv = dev->dev_private;
6696 uint32_t lcpll = I915_READ(LCPLL_CTL);
6697 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6698
6699 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6700 return 800000;
6701 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6702 return 450000;
6703 else if (freq == LCPLL_CLK_FREQ_450)
6704 return 450000;
6705 else if (IS_HSW_ULT(dev))
6706 return 337500;
6707 else
6708 return 540000;
79e53945
JB		 6709}
6710
25eb05fc
JB		 6711static int valleyview_get_display_clock_speed(struct drm_device *dev)
6712{
d197b7d3 6713 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6714 u32 val;
6715 int divider;
6716
6bcda4f0
VS		 6717 if (dev_priv->hpll_freq == 0)
6718 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6719
a580516d 6720 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6721 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6722 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6723
6724 divider = val & DISPLAY_FREQUENCY_VALUES;
6725
7d007f40
VS		 6726 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6727 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6728 "cdclk change in progress\n");
6729
6bcda4f0 6730 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6731}
6732
b37a6434
VS		 6733static int ilk_get_display_clock_speed(struct drm_device *dev)
6734{
6735 return 450000;
6736}
6737
e70236a8
JB		 6738static int i945_get_display_clock_speed(struct drm_device *dev)
6739{
6740 return 400000;
6741}
79e53945 6742
e70236a8 6743static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6744{
e907f170 6745 return 333333;
e70236a8 6746}
79e53945 6747
e70236a8
JB		 6748static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6749{
6750 return 200000;
6751}
79e53945 6752
257a7ffc
DV		 6753static int pnv_get_display_clock_speed(struct drm_device *dev)
6754{
6755 u16 gcfgc = 0;
6756
6757 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6758
6759 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6760 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6761 return 266667;
257a7ffc 6762 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6763 return 333333;
257a7ffc 6764 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6765 return 444444;
257a7ffc
DV		 6766 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6767 return 200000;
6768 default:
6769 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6770 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6771 return 133333;
257a7ffc 6772 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6773 return 166667;
257a7ffc
DV		 6774 }
6775}
6776
e70236a8
JB		 6777static int i915gm_get_display_clock_speed(struct drm_device *dev)
6778{
6779 u16 gcfgc = 0;
79e53945 6780
e70236a8
JB		 6781 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6782
6783 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6784 return 133333;
e70236a8
JB		 6785 else {
6786 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6787 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6788 return 333333;
e70236a8
JB		 6789 default:
6790 case GC_DISPLAY_CLOCK_190_200_MHZ:
6791 return 190000;
79e53945 6792 }
e70236a8
JB		 6793 }
6794}
6795
6796static int i865_get_display_clock_speed(struct drm_device *dev)
6797{
e907f170 6798 return 266667;
e70236a8
JB		 6799}
6800
1b1d2716 6801static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6802{
6803 u16 hpllcc = 0;
1b1d2716 6804
65cd2b3f
VS		 6805 /*
6806 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6807 * encoding is different :(
6808 * FIXME is this the right way to detect 852GM/852GMV?
6809 */
6810 if (dev->pdev->revision == 0x1)
6811 return 133333;
6812
1b1d2716
VS		 6813 pci_bus_read_config_word(dev->pdev->bus,
6814 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6815
e70236a8
JB		 6816 /* Assume that the hardware is in the high speed state. This
6817 * should be the default.
6818 */
6819 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6820 case GC_CLOCK_133_200:
1b1d2716 6821 case GC_CLOCK_133_200_2:
e70236a8
JB		 6822 case GC_CLOCK_100_200:
6823 return 200000;
6824 case GC_CLOCK_166_250:
6825 return 250000;
6826 case GC_CLOCK_100_133:
e907f170 6827 return 133333;
1b1d2716
VS		 6828 case GC_CLOCK_133_266:
6829 case GC_CLOCK_133_266_2:
6830 case GC_CLOCK_166_266:
6831 return 266667;
e70236a8 6832 }
79e53945 6833
e70236a8
JB		 6834 /* Shouldn't happen */
6835 return 0;
6836}
79e53945 6837
e70236a8
JB		 6838static int i830_get_display_clock_speed(struct drm_device *dev)
6839{
e907f170 6840 return 133333;
79e53945
JB		 6841}
6842
34edce2f
VS		 6843static unsigned int intel_hpll_vco(struct drm_device *dev)
6844{
6845 struct drm_i915_private *dev_priv = dev->dev_private;
6846 static const unsigned int blb_vco[8] = {
6847 [0] = 3200000,
6848 [1] = 4000000,
6849 [2] = 5333333,
6850 [3] = 4800000,
6851 [4] = 6400000,
6852 };
6853 static const unsigned int pnv_vco[8] = {
6854 [0] = 3200000,
6855 [1] = 4000000,
6856 [2] = 5333333,
6857 [3] = 4800000,
6858 [4] = 2666667,
6859 };
6860 static const unsigned int cl_vco[8] = {
6861 [0] = 3200000,
6862 [1] = 4000000,
6863 [2] = 5333333,
6864 [3] = 6400000,
6865 [4] = 3333333,
6866 [5] = 3566667,
6867 [6] = 4266667,
6868 };
6869 static const unsigned int elk_vco[8] = {
6870 [0] = 3200000,
6871 [1] = 4000000,
6872 [2] = 5333333,
6873 [3] = 4800000,
6874 };
6875 static const unsigned int ctg_vco[8] = {
6876 [0] = 3200000,
6877 [1] = 4000000,
6878 [2] = 5333333,
6879 [3] = 6400000,
6880 [4] = 2666667,
6881 [5] = 4266667,
6882 };
6883 const unsigned int *vco_table;
6884 unsigned int vco;
6885 uint8_t tmp = 0;
6886
6887 /* FIXME other chipsets? */
6888 if (IS_GM45(dev))
6889 vco_table = ctg_vco;
6890 else if (IS_G4X(dev))
6891 vco_table = elk_vco;
6892 else if (IS_CRESTLINE(dev))
6893 vco_table = cl_vco;
6894 else if (IS_PINEVIEW(dev))
6895 vco_table = pnv_vco;
6896 else if (IS_G33(dev))
6897 vco_table = blb_vco;
6898 else
6899 return 0;
6900
6901 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6902
6903 vco = vco_table[tmp & 0x7];
6904 if (vco == 0)
6905 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6906 else
6907 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6908
6909 return vco;
6910}
6911
6912static int gm45_get_display_clock_speed(struct drm_device *dev)
6913{
6914 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6915 uint16_t tmp = 0;
6916
6917 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6918
6919 cdclk_sel = (tmp >> 12) & 0x1;
6920
6921 switch (vco) {
6922 case 2666667:
6923 case 4000000:
6924 case 5333333:
6925 return cdclk_sel ? 333333 : 222222;
6926 case 3200000:
6927 return cdclk_sel ? 320000 : 228571;
6928 default:
6929 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6930 return 222222;
6931 }
6932}
6933
6934static int i965gm_get_display_clock_speed(struct drm_device *dev)
6935{
6936 static const uint8_t div_3200[] = { 16, 10, 8 };
6937 static const uint8_t div_4000[] = { 20, 12, 10 };
6938 static const uint8_t div_5333[] = { 24, 16, 14 };
6939 const uint8_t *div_table;
6940 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6941 uint16_t tmp = 0;
6942
6943 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6944
6945 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6946
6947 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6948 goto fail;
6949
6950 switch (vco) {
6951 case 3200000:
6952 div_table = div_3200;
6953 break;
6954 case 4000000:
6955 div_table = div_4000;
6956 break;
6957 case 5333333:
6958 div_table = div_5333;
6959 break;
6960 default:
6961 goto fail;
6962 }
6963
6964 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6965
caf4e252 6966fail:
34edce2f
VS		 6967 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6968 return 200000;
6969}
6970
6971static int g33_get_display_clock_speed(struct drm_device *dev)
6972{
6973 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6974 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6975 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6976 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6977 const uint8_t *div_table;
6978 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6979 uint16_t tmp = 0;
6980
6981 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6982
6983 cdclk_sel = (tmp >> 4) & 0x7;
6984
6985 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6986 goto fail;
6987
6988 switch (vco) {
6989 case 3200000:
6990 div_table = div_3200;
6991 break;
6992 case 4000000:
6993 div_table = div_4000;
6994 break;
6995 case 4800000:
6996 div_table = div_4800;
6997 break;
6998 case 5333333:
6999 div_table = div_5333;
7000 break;
7001 default:
7002 goto fail;
7003 }
7004
7005 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7006
caf4e252 7007fail:
34edce2f
VS		 7008 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7009 return 190476;
7010}
7011
2c07245f 7012static void
a65851af 7013intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7014{
a65851af
VS		 7015 while (*num > DATA_LINK_M_N_MASK ||
7016 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7017 *num >>= 1;
7018 *den >>= 1;
7019 }
7020}
7021
a65851af
VS		 7022static void compute_m_n(unsigned int m, unsigned int n,
7023 uint32_t *ret_m, uint32_t *ret_n)
7024{
7025 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7026 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7027 intel_reduce_m_n_ratio(ret_m, ret_n);
7028}
7029
e69d0bc1
DV		 7030void
7031intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7032 int pixel_clock, int link_clock,
7033 struct intel_link_m_n *m_n)
2c07245f 7034{
e69d0bc1 7035 m_n->tu = 64;
a65851af
VS		 7036
7037 compute_m_n(bits_per_pixel * pixel_clock,
7038 link_clock * nlanes * 8,
7039 &m_n->gmch_m, &m_n->gmch_n);
7040
7041 compute_m_n(pixel_clock, link_clock,
7042 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7043}
7044
a7615030
CW		 7045static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7046{
d330a953
JN		 7047 if (i915.panel_use_ssc >= 0)
7048 return i915.panel_use_ssc != 0;
41aa3448 7049 return dev_priv->vbt.lvds_use_ssc
435793df 7050 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7051}
7052
a93e255f
ACO		 7053static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7054 int num_connectors)
c65d77d8 7055{
a93e255f 7056 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7057 struct drm_i915_private *dev_priv = dev->dev_private;
7058 int refclk;
7059
a93e255f
ACO		 7060 WARN_ON(!crtc_state->base.state);
7061
5ab7b0b7 7062 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7063 refclk = 100000;
a93e255f 7064 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7065 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7066 refclk = dev_priv->vbt.lvds_ssc_freq;
7067 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7068 } else if (!IS_GEN2(dev)) {
7069 refclk = 96000;
7070 } else {
7071 refclk = 48000;
7072 }
7073
7074 return refclk;
7075}
7076
7429e9d4 7077static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7078{
7df00d7a 7079 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7080}
f47709a9 7081
7429e9d4
DV		 7082static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7083{
7084 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7085}
7086
f47709a9 7087static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7088 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7089 intel_clock_t *reduced_clock)
7090{
f47709a9 7091 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7092 u32 fp, fp2 = 0;
7093
7094 if (IS_PINEVIEW(dev)) {
190f68c5 7095 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7096 if (reduced_clock)
7429e9d4 7097 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7098 } else {
190f68c5 7099 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7100 if (reduced_clock)
7429e9d4 7101 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7102 }
7103
190f68c5 7104 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7105
f47709a9 7106 crtc->lowfreq_avail = false;
a93e255f 7107 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7108 reduced_clock) {
190f68c5 7109 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7110 crtc->lowfreq_avail = true;
a7516a05 7111 } else {
190f68c5 7112 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7113 }
7114}
7115
5e69f97f
CML		 7116static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7117 pipe)
89b667f8
JB		 7118{
7119 u32 reg_val;
7120
7121 /*
7122 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7123 * and set it to a reasonable value instead.
7124 */
ab3c759a 7125 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7126 reg_val &= 0xffffff00;
7127 reg_val |= 0x00000030;
ab3c759a 7128 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7129
ab3c759a 7130 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7131 reg_val &= 0x8cffffff;
7132 reg_val = 0x8c000000;
ab3c759a 7133 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7134
ab3c759a 7135 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7136 reg_val &= 0xffffff00;
ab3c759a 7137 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7138
ab3c759a 7139 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7140 reg_val &= 0x00ffffff;
7141 reg_val |= 0xb0000000;
ab3c759a 7142 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7143}
7144
b551842d
DV		 7145static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7146 struct intel_link_m_n *m_n)
7147{
7148 struct drm_device *dev = crtc->base.dev;
7149 struct drm_i915_private *dev_priv = dev->dev_private;
7150 int pipe = crtc->pipe;
7151
e3b95f1e
DV		 7152 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7153 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7154 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7155 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7156}
7157
7158static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7159 struct intel_link_m_n *m_n,
7160 struct intel_link_m_n *m2_n2)
b551842d
DV		 7161{
7162 struct drm_device *dev = crtc->base.dev;
7163 struct drm_i915_private *dev_priv = dev->dev_private;
7164 int pipe = crtc->pipe;
6e3c9717 7165 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7166
7167 if (INTEL_INFO(dev)->gen >= 5) {
7168 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7169 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7170 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7171 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7172 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7173 * for gen < 8) and if DRRS is supported (to make sure the
7174 * registers are not unnecessarily accessed).
7175 */
44395bfe 7176 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7177 crtc->config->has_drrs) {
f769cd24
VK		 7178 I915_WRITE(PIPE_DATA_M2(transcoder),
7179 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7180 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7181 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7182 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7183 }
b551842d 7184 } else {
e3b95f1e
DV		 7185 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7186 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7187 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7188 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7189 }
7190}
7191
fe3cd48d 7192void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7193{
fe3cd48d
R		 7194 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7195
7196 if (m_n == M1_N1) {
7197 dp_m_n = &crtc->config->dp_m_n;
7198 dp_m2_n2 = &crtc->config->dp_m2_n2;
7199 } else if (m_n == M2_N2) {
7200
7201 /*
7202 * M2_N2 registers are not supported. Hence m2_n2 divider value
7203 * needs to be programmed into M1_N1.
7204 */
7205 dp_m_n = &crtc->config->dp_m2_n2;
7206 } else {
7207 DRM_ERROR("Unsupported divider value\n");
7208 return;
7209 }
7210
6e3c9717
ACO		 7211 if (crtc->config->has_pch_encoder)
7212 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7213 else
fe3cd48d 7214 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7215}
7216
251ac862
DV		 7217static void vlv_compute_dpll(struct intel_crtc *crtc,
7218 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7219{
7220 u32 dpll, dpll_md;
7221
7222 /*
7223 * Enable DPIO clock input. We should never disable the reference
7224 * clock for pipe B, since VGA hotplug / manual detection depends
7225 * on it.
7226 */
7227 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7228 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7229 /* We should never disable this, set it here for state tracking */
7230 if (crtc->pipe == PIPE_B)
7231 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7232 dpll |= DPLL_VCO_ENABLE;
d288f65f 7233 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7234
d288f65f 7235 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7236 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7237 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7238}
7239
d288f65f 7240static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7241 const struct intel_crtc_state *pipe_config)
a0c4da24 7242{
f47709a9 7243 struct drm_device *dev = crtc->base.dev;
a0c4da24 7244 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7245 int pipe = crtc->pipe;
bdd4b6a6 7246 u32 mdiv;
a0c4da24 7247 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7248 u32 coreclk, reg_val;
a0c4da24 7249
a580516d 7250 mutex_lock(&dev_priv->sb_lock);
09153000 7251
d288f65f
VS		 7252 bestn = pipe_config->dpll.n;
7253 bestm1 = pipe_config->dpll.m1;
7254 bestm2 = pipe_config->dpll.m2;
7255 bestp1 = pipe_config->dpll.p1;
7256 bestp2 = pipe_config->dpll.p2;
a0c4da24 7257
89b667f8
JB		 7258 /* See eDP HDMI DPIO driver vbios notes doc */
7259
7260 /* PLL B needs special handling */
bdd4b6a6 7261 if (pipe == PIPE_B)
5e69f97f 7262 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7263
7264 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7265 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7266
7267 /* Disable target IRef on PLL */
ab3c759a 7268 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7269 reg_val &= 0x00ffffff;
ab3c759a 7270 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7271
7272 /* Disable fast lock */
ab3c759a 7273 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7274
7275 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7276 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7277 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7278 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7279 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7280
7281 /*
7282 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7283 * but we don't support that).
7284 * Note: don't use the DAC post divider as it seems unstable.
7285 */
7286 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7288
a0c4da24 7289 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7290 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7291
89b667f8 7292 /* Set HBR and RBR LPF coefficients */
d288f65f 7293 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7294 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7295 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7296 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7297 0x009f0003);
89b667f8 7298 else
ab3c759a 7299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7300 0x00d0000f);
7301
681a8504 7302 if (pipe_config->has_dp_encoder) {
89b667f8 7303 /* Use SSC source */
bdd4b6a6 7304 if (pipe == PIPE_A)
ab3c759a 7305 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7306 0x0df40000);
7307 else
ab3c759a 7308 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7309 0x0df70000);
7310 } else { /* HDMI or VGA */
7311 /* Use bend source */
bdd4b6a6 7312 if (pipe == PIPE_A)
ab3c759a 7313 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7314 0x0df70000);
7315 else
ab3c759a 7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7317 0x0df40000);
7318 }
a0c4da24 7319
ab3c759a 7320 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7321 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7322 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7323 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7324 coreclk |= 0x01000000;
ab3c759a 7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7326
ab3c759a 7327 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7328 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7329}
7330
251ac862
DV		 7331static void chv_compute_dpll(struct intel_crtc *crtc,
7332 struct intel_crtc_state *pipe_config)
1ae0d137 7333{
d288f65f 7334 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7335 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7336 DPLL_VCO_ENABLE;
7337 if (crtc->pipe != PIPE_A)
d288f65f 7338 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7339
d288f65f
VS		 7340 pipe_config->dpll_hw_state.dpll_md =
7341 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7342}
7343
d288f65f 7344static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7345 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7346{
7347 struct drm_device *dev = crtc->base.dev;
7348 struct drm_i915_private *dev_priv = dev->dev_private;
7349 int pipe = crtc->pipe;
7350 int dpll_reg = DPLL(crtc->pipe);
7351 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7352 u32 loopfilter, tribuf_calcntr;
9d556c99 7353 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7354 u32 dpio_val;
9cbe40c1 7355 int vco;
9d556c99 7356
d288f65f
VS		 7357 bestn = pipe_config->dpll.n;
7358 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7359 bestm1 = pipe_config->dpll.m1;
7360 bestm2 = pipe_config->dpll.m2 >> 22;
7361 bestp1 = pipe_config->dpll.p1;
7362 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7363 vco = pipe_config->dpll.vco;
a945ce7e 7364 dpio_val = 0;
9cbe40c1 7365 loopfilter = 0;
9d556c99
CML		 7366
7367 /*
7368 * Enable Refclk and SSC
7369 */
a11b0703 7370 I915_WRITE(dpll_reg,
d288f65f 7371 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7372
a580516d 7373 mutex_lock(&dev_priv->sb_lock);
9d556c99 7374
9d556c99
CML		 7375 /* p1 and p2 divider */
7376 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7377 5 << DPIO_CHV_S1_DIV_SHIFT |
7378 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7379 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7380 1 << DPIO_CHV_K_DIV_SHIFT);
7381
7382 /* Feedback post-divider - m2 */
7383 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7384
7385 /* Feedback refclk divider - n and m1 */
7386 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7387 DPIO_CHV_M1_DIV_BY_2 |
7388 1 << DPIO_CHV_N_DIV_SHIFT);
7389
7390 /* M2 fraction division */
a945ce7e
VP		 7391 if (bestm2_frac)
7392 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7393
7394 /* M2 fraction division enable */
a945ce7e
VP		 7395 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7396 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7397 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7398 if (bestm2_frac)
7399 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7400 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7401
de3a0fde
VP		 7402 /* Program digital lock detect threshold */
7403 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7404 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7405 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7406 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7407 if (!bestm2_frac)
7408 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7409 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7410
9d556c99 7411 /* Loop filter */
9cbe40c1
VP		 7412 if (vco == 5400000) {
7413 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7414 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7415 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7416 tribuf_calcntr = 0x9;
7417 } else if (vco <= 6200000) {
7418 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7419 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7420 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7421 tribuf_calcntr = 0x9;
7422 } else if (vco <= 6480000) {
7423 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7424 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7425 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7426 tribuf_calcntr = 0x8;
7427 } else {
7428 /* Not supported. Apply the same limits as in the max case */
7429 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7430 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7431 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7432 tribuf_calcntr = 0;
7433 }
9d556c99
CML		 7434 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7435
968040b2 7436 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7437 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7438 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7439 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7440
9d556c99
CML		 7441 /* AFC Recal */
7442 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7443 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7444 DPIO_AFC_RECAL);
7445
a580516d 7446 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7447}
7448
d288f65f
VS		 7449/**
7450 * vlv_force_pll_on - forcibly enable just the PLL
7451 * @dev_priv: i915 private structure
7452 * @pipe: pipe PLL to enable
7453 * @dpll: PLL configuration
7454 *
7455 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7456 * in cases where we need the PLL enabled even when @pipe is not going to
7457 * be enabled.
7458 */
7459void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7460 const struct dpll *dpll)
7461{
7462 struct intel_crtc *crtc =
7463 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7464 struct intel_crtc_state pipe_config = {
a93e255f 7465 .base.crtc = &crtc->base,
d288f65f
VS		 7466 .pixel_multiplier = 1,
7467 .dpll = *dpll,
7468 };
7469
7470 if (IS_CHERRYVIEW(dev)) {
251ac862 7471 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7472 chv_prepare_pll(crtc, &pipe_config);
7473 chv_enable_pll(crtc, &pipe_config);
7474 } else {
251ac862 7475 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7476 vlv_prepare_pll(crtc, &pipe_config);
7477 vlv_enable_pll(crtc, &pipe_config);
7478 }
7479}
7480
7481/**
7482 * vlv_force_pll_off - forcibly disable just the PLL
7483 * @dev_priv: i915 private structure
7484 * @pipe: pipe PLL to disable
7485 *
7486 * Disable the PLL for @pipe. To be used in cases where we need
7487 * the PLL enabled even when @pipe is not going to be enabled.
7488 */
7489void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7490{
7491 if (IS_CHERRYVIEW(dev))
7492 chv_disable_pll(to_i915(dev), pipe);
7493 else
7494 vlv_disable_pll(to_i915(dev), pipe);
7495}
7496
251ac862
DV		 7497static void i9xx_compute_dpll(struct intel_crtc *crtc,
7498 struct intel_crtc_state *crtc_state,
7499 intel_clock_t *reduced_clock,
7500 int num_connectors)
eb1cbe48 7501{
f47709a9 7502 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7503 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7504 u32 dpll;
7505 bool is_sdvo;
190f68c5 7506 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7507
190f68c5 7508 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7509
a93e255f
ACO		 7510 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7511 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7512
7513 dpll = DPLL_VGA_MODE_DIS;
7514
a93e255f 7515 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7516 dpll |= DPLLB_MODE_LVDS;
7517 else
7518 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7519
ef1b460d 7520 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7521 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7522 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7523 }
198a037f
DV		 7524
7525 if (is_sdvo)
4a33e48d 7526 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7527
190f68c5 7528 if (crtc_state->has_dp_encoder)
4a33e48d 7529 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7530
7531 /* compute bitmask from p1 value */
7532 if (IS_PINEVIEW(dev))
7533 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7534 else {
7535 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7536 if (IS_G4X(dev) && reduced_clock)
7537 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7538 }
7539 switch (clock->p2) {
7540 case 5:
7541 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7542 break;
7543 case 7:
7544 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7545 break;
7546 case 10:
7547 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7548 break;
7549 case 14:
7550 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7551 break;
7552 }
7553 if (INTEL_INFO(dev)->gen >= 4)
7554 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7555
190f68c5 7556 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7557 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7558 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7559 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7560 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7561 else
7562 dpll |= PLL_REF_INPUT_DREFCLK;
7563
7564 dpll |= DPLL_VCO_ENABLE;
190f68c5 7565 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7566
eb1cbe48 7567 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7568 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7569 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7570 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7571 }
7572}
7573
251ac862
DV		 7574static void i8xx_compute_dpll(struct intel_crtc *crtc,
7575 struct intel_crtc_state *crtc_state,
7576 intel_clock_t *reduced_clock,
7577 int num_connectors)
eb1cbe48 7578{
f47709a9 7579 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7580 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7581 u32 dpll;
190f68c5 7582 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7583
190f68c5 7584 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7585
eb1cbe48
DV		 7586 dpll = DPLL_VGA_MODE_DIS;
7587
a93e255f 7588 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7589 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7590 } else {
7591 if (clock->p1 == 2)
7592 dpll |= PLL_P1_DIVIDE_BY_TWO;
7593 else
7594 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7595 if (clock->p2 == 4)
7596 dpll |= PLL_P2_DIVIDE_BY_4;
7597 }
7598
a93e255f 7599 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7600 dpll |= DPLL_DVO_2X_MODE;
7601
a93e255f 7602 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7603 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7604 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7605 else
7606 dpll |= PLL_REF_INPUT_DREFCLK;
7607
7608 dpll |= DPLL_VCO_ENABLE;
190f68c5 7609 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7610}
7611
8a654f3b 7612static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7613{
7614 struct drm_device *dev = intel_crtc->base.dev;
7615 struct drm_i915_private *dev_priv = dev->dev_private;
7616 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7617 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7618 struct drm_display_mode *adjusted_mode =
6e3c9717 7619 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7620 uint32_t crtc_vtotal, crtc_vblank_end;
7621 int vsyncshift = 0;
4d8a62ea
DV		 7622
7623 /* We need to be careful not to changed the adjusted mode, for otherwise
7624 * the hw state checker will get angry at the mismatch. */
7625 crtc_vtotal = adjusted_mode->crtc_vtotal;
7626 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7627
609aeaca 7628 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7629 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7630 crtc_vtotal -= 1;
7631 crtc_vblank_end -= 1;
609aeaca 7632
409ee761 7633 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7634 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7635 else
7636 vsyncshift = adjusted_mode->crtc_hsync_start -
7637 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7638 if (vsyncshift < 0)
7639 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7640 }
7641
7642 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7643 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7644
fe2b8f9d 7645 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7646 (adjusted_mode->crtc_hdisplay - 1) |
7647 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7648 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7649 (adjusted_mode->crtc_hblank_start - 1) |
7650 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7651 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7652 (adjusted_mode->crtc_hsync_start - 1) |
7653 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7654
fe2b8f9d 7655 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7656 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7657 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7658 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7659 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7660 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7661 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7662 (adjusted_mode->crtc_vsync_start - 1) |
7663 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7664
b5e508d4
PZ		 7665 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7666 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7667 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7668 * bits. */
7669 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7670 (pipe == PIPE_B || pipe == PIPE_C))
7671 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7672
b0e77b9c
PZ		 7673 /* pipesrc controls the size that is scaled from, which should
7674 * always be the user's requested size.
7675 */
7676 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7677 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7678 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7679}
7680
1bd1bd80 7681static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7682 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7683{
7684 struct drm_device *dev = crtc->base.dev;
7685 struct drm_i915_private *dev_priv = dev->dev_private;
7686 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7687 uint32_t tmp;
7688
7689 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7690 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7691 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7692 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7693 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7694 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7695 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7696 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7697 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7698
7699 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7700 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7701 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7702 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7703 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7704 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7705 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7706 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7707 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7708
7709 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7710 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7711 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7712 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7713 }
7714
7715 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7716 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7717 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7718
2d112de7
ACO		 7719 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7720 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7721}
7722
f6a83288 7723void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7724 struct intel_crtc_state *pipe_config)
babea61d 7725{
2d112de7
ACO		 7726 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7727 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7728 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7729 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7730
2d112de7
ACO		 7731 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7732 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7733 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7734 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7735
2d112de7 7736 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7737
2d112de7
ACO		 7738 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7739 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7740}
7741
84b046f3
DV		 7742static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7743{
7744 struct drm_device *dev = intel_crtc->base.dev;
7745 struct drm_i915_private *dev_priv = dev->dev_private;
7746 uint32_t pipeconf;
7747
9f11a9e4 7748 pipeconf = 0;
84b046f3 7749
b6b5d049
VS		 7750 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7751 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7752 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7753
6e3c9717 7754 if (intel_crtc->config->double_wide)
cf532bb2 7755 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7756
ff9ce46e
DV		 7757 /* only g4x and later have fancy bpc/dither controls */
7758 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7759 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7760 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7761 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7762 PIPECONF_DITHER_TYPE_SP;
84b046f3 7763
6e3c9717 7764 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7765 case 18:
7766 pipeconf |= PIPECONF_6BPC;
7767 break;
7768 case 24:
7769 pipeconf |= PIPECONF_8BPC;
7770 break;
7771 case 30:
7772 pipeconf |= PIPECONF_10BPC;
7773 break;
7774 default:
7775 /* Case prevented by intel_choose_pipe_bpp_dither. */
7776 BUG();
84b046f3
DV		 7777 }
7778 }
7779
7780 if (HAS_PIPE_CXSR(dev)) {
7781 if (intel_crtc->lowfreq_avail) {
7782 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7783 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7784 } else {
7785 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7786 }
7787 }
7788
6e3c9717 7789 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7790 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7791 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7792 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7793 else
7794 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7795 } else
84b046f3
DV		 7796 pipeconf |= PIPECONF_PROGRESSIVE;
7797
6e3c9717 7798 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7799 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7800
84b046f3
DV		 7801 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7802 POSTING_READ(PIPECONF(intel_crtc->pipe));
7803}
7804
190f68c5
ACO		 7805static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7806 struct intel_crtc_state *crtc_state)
79e53945 7807{
c7653199 7808 struct drm_device *dev = crtc->base.dev;
79e53945 7809 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7810 int refclk, num_connectors = 0;
c329a4ec
DV		 7811 intel_clock_t clock;
7812 bool ok;
7813 bool is_dsi = false;
5eddb70b 7814 struct intel_encoder *encoder;
d4906093 7815 const intel_limit_t *limit;
55bb9992 7816 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7817 struct drm_connector *connector;
55bb9992
ACO		 7818 struct drm_connector_state *connector_state;
7819 int i;
79e53945 7820
dd3cd74a
ACO		 7821 memset(&crtc_state->dpll_hw_state, 0,
7822 sizeof(crtc_state->dpll_hw_state));
7823
da3ced29 7824 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7825 if (connector_state->crtc != &crtc->base)
7826 continue;
7827
7828 encoder = to_intel_encoder(connector_state->best_encoder);
7829
5eddb70b 7830 switch (encoder->type) {
e9fd1c02
JN		 7831 case INTEL_OUTPUT_DSI:
7832 is_dsi = true;
7833 break;
6847d71b
PZ		 7834 default:
7835 break;
79e53945 7836 }
43565a06 7837
c751ce4f 7838 num_connectors++;
79e53945
JB		 7839 }
7840
f2335330 7841 if (is_dsi)
5b18e57c 7842 return 0;
f2335330 7843
190f68c5 7844 if (!crtc_state->clock_set) {
a93e255f 7845 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7846
e9fd1c02
JN		 7847 /*
7848 * Returns a set of divisors for the desired target clock with
7849 * the given refclk, or FALSE. The returned values represent
7850 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7851 * 2) / p1 / p2.
7852 */
a93e255f
ACO		 7853 limit = intel_limit(crtc_state, refclk);
7854 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7855 crtc_state->port_clock,
e9fd1c02 7856 refclk, NULL, &clock);
f2335330 7857 if (!ok) {
e9fd1c02
JN		 7858 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7859 return -EINVAL;
7860 }
79e53945 7861
f2335330 7862 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7863 crtc_state->dpll.n = clock.n;
7864 crtc_state->dpll.m1 = clock.m1;
7865 crtc_state->dpll.m2 = clock.m2;
7866 crtc_state->dpll.p1 = clock.p1;
7867 crtc_state->dpll.p2 = clock.p2;
f47709a9 7868 }
7026d4ac 7869
e9fd1c02 7870 if (IS_GEN2(dev)) {
c329a4ec 7871 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7872 num_connectors);
9d556c99 7873 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7874 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7875 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7876 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7877 } else {
c329a4ec 7878 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7879 num_connectors);
e9fd1c02 7880 }
79e53945 7881
c8f7a0db 7882 return 0;
f564048e
EA		 7883}
7884
2fa2fe9a 7885static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7886 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7887{
7888 struct drm_device *dev = crtc->base.dev;
7889 struct drm_i915_private *dev_priv = dev->dev_private;
7890 uint32_t tmp;
7891
dc9e7dec
VS		 7892 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7893 return;
7894
2fa2fe9a 7895 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7896 if (!(tmp & PFIT_ENABLE))
7897 return;
2fa2fe9a 7898
06922821 7899 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7900 if (INTEL_INFO(dev)->gen < 4) {
7901 if (crtc->pipe != PIPE_B)
7902 return;
2fa2fe9a
DV		 7903 } else {
7904 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7905 return;
7906 }
7907
06922821 7908 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7909 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7910 if (INTEL_INFO(dev)->gen < 5)
7911 pipe_config->gmch_pfit.lvds_border_bits =
7912 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7913}
7914
acbec814 7915static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7916 struct intel_crtc_state *pipe_config)
acbec814
JB		 7917{
7918 struct drm_device *dev = crtc->base.dev;
7919 struct drm_i915_private *dev_priv = dev->dev_private;
7920 int pipe = pipe_config->cpu_transcoder;
7921 intel_clock_t clock;
7922 u32 mdiv;
662c6ecb 7923 int refclk = 100000;
acbec814 7924
f573de5a
SK		 7925 /* In case of MIPI DPLL will not even be used */
7926 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7927 return;
7928
a580516d 7929 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7930 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7931 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7932
7933 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7934 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7935 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7936 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7937 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7938
dccbea3b 7939 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7940}
7941
5724dbd1
DL		 7942static void
7943i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7944 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7945{
7946 struct drm_device *dev = crtc->base.dev;
7947 struct drm_i915_private *dev_priv = dev->dev_private;
7948 u32 val, base, offset;
7949 int pipe = crtc->pipe, plane = crtc->plane;
7950 int fourcc, pixel_format;
6761dd31 7951 unsigned int aligned_height;
b113d5ee 7952 struct drm_framebuffer *fb;
1b842c89 7953 struct intel_framebuffer *intel_fb;
1ad292b5 7954
42a7b088
DL		 7955 val = I915_READ(DSPCNTR(plane));
7956 if (!(val & DISPLAY_PLANE_ENABLE))
7957 return;
7958
d9806c9f 7959 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7960 if (!intel_fb) {
1ad292b5
JB		 7961 DRM_DEBUG_KMS("failed to alloc fb\n");
7962 return;
7963 }
7964
1b842c89
DL		 7965 fb = &intel_fb->base;
7966
18c5247e
DV		 7967 if (INTEL_INFO(dev)->gen >= 4) {
7968 if (val & DISPPLANE_TILED) {
49af449b 7969 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7970 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7971 }
7972 }
1ad292b5
JB		 7973
7974 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7975 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7976 fb->pixel_format = fourcc;
7977 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7978
7979 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7980 if (plane_config->tiling)
1ad292b5
JB		 7981 offset = I915_READ(DSPTILEOFF(plane));
7982 else
7983 offset = I915_READ(DSPLINOFF(plane));
7984 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7985 } else {
7986 base = I915_READ(DSPADDR(plane));
7987 }
7988 plane_config->base = base;
7989
7990 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7991 fb->width = ((val >> 16) & 0xfff) + 1;
7992 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7993
7994 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7995 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7996
b113d5ee 7997 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7998 fb->pixel_format,
7999 fb->modifier[0]);
1ad292b5 8000
f37b5c2b 8001 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8002
2844a921
DL		 8003 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8004 pipe_name(pipe), plane, fb->width, fb->height,
8005 fb->bits_per_pixel, base, fb->pitches[0],
8006 plane_config->size);
1ad292b5 8007
2d14030b 8008 plane_config->fb = intel_fb;
1ad292b5
JB		 8009}
8010
70b23a98 8011static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8012 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8013{
8014 struct drm_device *dev = crtc->base.dev;
8015 struct drm_i915_private *dev_priv = dev->dev_private;
8016 int pipe = pipe_config->cpu_transcoder;
8017 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8018 intel_clock_t clock;
8019 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8020 int refclk = 100000;
8021
a580516d 8022 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8023 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8024 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8025 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8026 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8027 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8028
8029 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8030 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8031 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8032 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8033 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8034
dccbea3b 8035 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8036}
8037
0e8ffe1b 8038static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8039 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8040{
8041 struct drm_device *dev = crtc->base.dev;
8042 struct drm_i915_private *dev_priv = dev->dev_private;
8043 uint32_t tmp;
8044
f458ebbc
DV		 8045 if (!intel_display_power_is_enabled(dev_priv,
8046 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8047 return false;
8048
e143a21c 8049 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8050 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8051
0e8ffe1b
DV		 8052 tmp = I915_READ(PIPECONF(crtc->pipe));
8053 if (!(tmp & PIPECONF_ENABLE))
8054 return false;
8055
42571aef
VS		 8056 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8057 switch (tmp & PIPECONF_BPC_MASK) {
8058 case PIPECONF_6BPC:
8059 pipe_config->pipe_bpp = 18;
8060 break;
8061 case PIPECONF_8BPC:
8062 pipe_config->pipe_bpp = 24;
8063 break;
8064 case PIPECONF_10BPC:
8065 pipe_config->pipe_bpp = 30;
8066 break;
8067 default:
8068 break;
8069 }
8070 }
8071
b5a9fa09
DV		 8072 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8073 pipe_config->limited_color_range = true;
8074
282740f7
VS		 8075 if (INTEL_INFO(dev)->gen < 4)
8076 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8077
1bd1bd80
DV		 8078 intel_get_pipe_timings(crtc, pipe_config);
8079
2fa2fe9a
DV		 8080 i9xx_get_pfit_config(crtc, pipe_config);
8081
6c49f241
DV		 8082 if (INTEL_INFO(dev)->gen >= 4) {
8083 tmp = I915_READ(DPLL_MD(crtc->pipe));
8084 pipe_config->pixel_multiplier =
8085 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8086 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8087 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8088 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8089 tmp = I915_READ(DPLL(crtc->pipe));
8090 pipe_config->pixel_multiplier =
8091 ((tmp & SDVO_MULTIPLIER_MASK)
8092 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8093 } else {
8094 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8095 * port and will be fixed up in the encoder->get_config
8096 * function. */
8097 pipe_config->pixel_multiplier = 1;
8098 }
8bcc2795
DV		 8099 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8100 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8101 /*
8102 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8103 * on 830. Filter it out here so that we don't
8104 * report errors due to that.
8105 */
8106 if (IS_I830(dev))
8107 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8108
8bcc2795
DV		 8109 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8110 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8111 } else {
8112 /* Mask out read-only status bits. */
8113 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8114 DPLL_PORTC_READY_MASK |
8115 DPLL_PORTB_READY_MASK);
8bcc2795 8116 }
6c49f241 8117
70b23a98
VS		 8118 if (IS_CHERRYVIEW(dev))
8119 chv_crtc_clock_get(crtc, pipe_config);
8120 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8121 vlv_crtc_clock_get(crtc, pipe_config);
8122 else
8123 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8124
0e8ffe1b
DV		 8125 return true;
8126}
8127
dde86e2d 8128static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8129{
8130 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8131 struct intel_encoder *encoder;
74cfd7ac 8132 u32 val, final;
13d83a67 8133 bool has_lvds = false;
199e5d79 8134 bool has_cpu_edp = false;
199e5d79 8135 bool has_panel = false;
99eb6a01
KP		 8136 bool has_ck505 = false;
8137 bool can_ssc = false;
13d83a67
JB		 8138
8139 /* We need to take the global config into account */
b2784e15 8140 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8141 switch (encoder->type) {
8142 case INTEL_OUTPUT_LVDS:
8143 has_panel = true;
8144 has_lvds = true;
8145 break;
8146 case INTEL_OUTPUT_EDP:
8147 has_panel = true;
2de6905f 8148 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8149 has_cpu_edp = true;
8150 break;
6847d71b
PZ		 8151 default:
8152 break;
13d83a67
JB		 8153 }
8154 }
8155
99eb6a01 8156 if (HAS_PCH_IBX(dev)) {
41aa3448 8157 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8158 can_ssc = has_ck505;
8159 } else {
8160 has_ck505 = false;
8161 can_ssc = true;
8162 }
8163
2de6905f
ID		 8164 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8165 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8166
8167 /* Ironlake: try to setup display ref clock before DPLL
8168 * enabling. This is only under driver's control after
8169 * PCH B stepping, previous chipset stepping should be
8170 * ignoring this setting.
8171 */
74cfd7ac
CW		 8172 val = I915_READ(PCH_DREF_CONTROL);
8173
8174 /* As we must carefully and slowly disable/enable each source in turn,
8175 * compute the final state we want first and check if we need to
8176 * make any changes at all.
8177 */
8178 final = val;
8179 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8180 if (has_ck505)
8181 final |= DREF_NONSPREAD_CK505_ENABLE;
8182 else
8183 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8184
8185 final &= ~DREF_SSC_SOURCE_MASK;
8186 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8187 final &= ~DREF_SSC1_ENABLE;
8188
8189 if (has_panel) {
8190 final |= DREF_SSC_SOURCE_ENABLE;
8191
8192 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8193 final |= DREF_SSC1_ENABLE;
8194
8195 if (has_cpu_edp) {
8196 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8197 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8198 else
8199 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8200 } else
8201 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8202 } else {
8203 final |= DREF_SSC_SOURCE_DISABLE;
8204 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8205 }
8206
8207 if (final == val)
8208 return;
8209
13d83a67 8210 /* Always enable nonspread source */
74cfd7ac 8211 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8212
99eb6a01 8213 if (has_ck505)
74cfd7ac 8214 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8215 else
74cfd7ac 8216 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8217
199e5d79 8218 if (has_panel) {
74cfd7ac
CW		 8219 val &= ~DREF_SSC_SOURCE_MASK;
8220 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8221
199e5d79 8222 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8223 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8224 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8225 val |= DREF_SSC1_ENABLE;
e77166b5 8226 } else
74cfd7ac 8227 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8228
8229 /* Get SSC going before enabling the outputs */
74cfd7ac 8230 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8231 POSTING_READ(PCH_DREF_CONTROL);
8232 udelay(200);
8233
74cfd7ac 8234 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8235
8236 /* Enable CPU source on CPU attached eDP */
199e5d79 8237 if (has_cpu_edp) {
99eb6a01 8238 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8239 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8240 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8241 } else
74cfd7ac 8242 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8243 } else
74cfd7ac 8244 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8245
74cfd7ac 8246 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8247 POSTING_READ(PCH_DREF_CONTROL);
8248 udelay(200);
8249 } else {
8250 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8251
74cfd7ac 8252 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8253
8254 /* Turn off CPU output */
74cfd7ac 8255 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8256
74cfd7ac 8257 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8258 POSTING_READ(PCH_DREF_CONTROL);
8259 udelay(200);
8260
8261 /* Turn off the SSC source */
74cfd7ac
CW		 8262 val &= ~DREF_SSC_SOURCE_MASK;
8263 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8264
8265 /* Turn off SSC1 */
74cfd7ac 8266 val &= ~DREF_SSC1_ENABLE;
199e5d79 8267
74cfd7ac 8268 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8269 POSTING_READ(PCH_DREF_CONTROL);
8270 udelay(200);
8271 }
74cfd7ac
CW		 8272
8273 BUG_ON(val != final);
13d83a67
JB		 8274}
8275
f31f2d55 8276static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8277{
f31f2d55 8278 uint32_t tmp;
dde86e2d 8279
0ff066a9
PZ		 8280 tmp = I915_READ(SOUTH_CHICKEN2);
8281 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8282 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8283
0ff066a9
PZ		 8284 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8285 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8286 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8287
0ff066a9
PZ		 8288 tmp = I915_READ(SOUTH_CHICKEN2);
8289 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8290 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8291
0ff066a9
PZ		 8292 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8293 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8294 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8295}
8296
8297/* WaMPhyProgramming:hsw */
8298static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8299{
8300 uint32_t tmp;
dde86e2d
PZ		 8301
8302 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8303 tmp &= ~(0xFF << 24);
8304 tmp |= (0x12 << 24);
8305 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8306
dde86e2d
PZ		 8307 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8308 tmp |= (1 << 11);
8309 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8310
8311 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8312 tmp |= (1 << 11);
8313 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8314
dde86e2d
PZ		 8315 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8316 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8317 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8318
8319 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8320 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8321 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8322
0ff066a9
PZ		 8323 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8324 tmp &= ~(7 << 13);
8325 tmp |= (5 << 13);
8326 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8327
0ff066a9
PZ		 8328 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8329 tmp &= ~(7 << 13);
8330 tmp |= (5 << 13);
8331 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8332
8333 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8334 tmp &= ~0xFF;
8335 tmp |= 0x1C;
8336 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8337
8338 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8339 tmp &= ~0xFF;
8340 tmp |= 0x1C;
8341 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8342
8343 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8344 tmp &= ~(0xFF << 16);
8345 tmp |= (0x1C << 16);
8346 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8347
8348 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8349 tmp &= ~(0xFF << 16);
8350 tmp |= (0x1C << 16);
8351 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8352
0ff066a9
PZ		 8353 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8354 tmp |= (1 << 27);
8355 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8356
0ff066a9
PZ		 8357 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8358 tmp |= (1 << 27);
8359 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8360
0ff066a9
PZ		 8361 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8362 tmp &= ~(0xF << 28);
8363 tmp |= (4 << 28);
8364 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8365
0ff066a9
PZ		 8366 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8367 tmp &= ~(0xF << 28);
8368 tmp |= (4 << 28);
8369 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8370}
8371
2fa86a1f
PZ		 8372/* Implements 3 different sequences from BSpec chapter "Display iCLK
8373 * Programming" based on the parameters passed:
8374 * - Sequence to enable CLKOUT_DP
8375 * - Sequence to enable CLKOUT_DP without spread
8376 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8377 */
8378static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8379 bool with_fdi)
f31f2d55
PZ		 8380{
8381 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8382 uint32_t reg, tmp;
8383
8384 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8385 with_spread = true;
8386 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8387 with_fdi, "LP PCH doesn't have FDI\n"))
8388 with_fdi = false;
f31f2d55 8389
a580516d 8390 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8391
8392 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8393 tmp &= ~SBI_SSCCTL_DISABLE;
8394 tmp |= SBI_SSCCTL_PATHALT;
8395 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8396
8397 udelay(24);
8398
2fa86a1f
PZ		 8399 if (with_spread) {
8400 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8401 tmp &= ~SBI_SSCCTL_PATHALT;
8402 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8403
2fa86a1f
PZ		 8404 if (with_fdi) {
8405 lpt_reset_fdi_mphy(dev_priv);
8406 lpt_program_fdi_mphy(dev_priv);
8407 }
8408 }
dde86e2d 8409
2fa86a1f
PZ		 8410 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8411 SBI_GEN0 : SBI_DBUFF0;
8412 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8413 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8414 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8415
a580516d 8416 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8417}
8418
47701c3b
PZ		 8419/* Sequence to disable CLKOUT_DP */
8420static void lpt_disable_clkout_dp(struct drm_device *dev)
8421{
8422 struct drm_i915_private *dev_priv = dev->dev_private;
8423 uint32_t reg, tmp;
8424
a580516d 8425 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8426
8427 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8428 SBI_GEN0 : SBI_DBUFF0;
8429 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8430 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8431 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8432
8433 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8434 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8435 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8436 tmp |= SBI_SSCCTL_PATHALT;
8437 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8438 udelay(32);
8439 }
8440 tmp |= SBI_SSCCTL_DISABLE;
8441 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8442 }
8443
a580516d 8444 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8445}
8446
bf8fa3d3
PZ		 8447static void lpt_init_pch_refclk(struct drm_device *dev)
8448{
bf8fa3d3
PZ		 8449 struct intel_encoder *encoder;
8450 bool has_vga = false;
8451
b2784e15 8452 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8453 switch (encoder->type) {
8454 case INTEL_OUTPUT_ANALOG:
8455 has_vga = true;
8456 break;
6847d71b
PZ		 8457 default:
8458 break;
bf8fa3d3
PZ		 8459 }
8460 }
8461
47701c3b
PZ		 8462 if (has_vga)
8463 lpt_enable_clkout_dp(dev, true, true);
8464 else
8465 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8466}
8467
dde86e2d
PZ		 8468/*
8469 * Initialize reference clocks when the driver loads
8470 */
8471void intel_init_pch_refclk(struct drm_device *dev)
8472{
8473 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8474 ironlake_init_pch_refclk(dev);
8475 else if (HAS_PCH_LPT(dev))
8476 lpt_init_pch_refclk(dev);
8477}
8478
55bb9992 8479static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8480{
55bb9992 8481 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8482 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8483 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8484 struct drm_connector *connector;
55bb9992 8485 struct drm_connector_state *connector_state;
d9d444cb 8486 struct intel_encoder *encoder;
55bb9992 8487 int num_connectors = 0, i;
d9d444cb
JB		 8488 bool is_lvds = false;
8489
da3ced29 8490 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8491 if (connector_state->crtc != crtc_state->base.crtc)
8492 continue;
8493
8494 encoder = to_intel_encoder(connector_state->best_encoder);
8495
d9d444cb
JB		 8496 switch (encoder->type) {
8497 case INTEL_OUTPUT_LVDS:
8498 is_lvds = true;
8499 break;
6847d71b
PZ		 8500 default:
8501 break;
d9d444cb
JB		 8502 }
8503 num_connectors++;
8504 }
8505
8506 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8507 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8508 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8509 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8510 }
8511
8512 return 120000;
8513}
8514
6ff93609 8515static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8516{
c8203565 8517 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8519 int pipe = intel_crtc->pipe;
c8203565
PZ		 8520 uint32_t val;
8521
78114071 8522 val = 0;
c8203565 8523
6e3c9717 8524 switch (intel_crtc->config->pipe_bpp) {
c8203565 8525 case 18:
dfd07d72 8526 val |= PIPECONF_6BPC;
c8203565
PZ		 8527 break;
8528 case 24:
dfd07d72 8529 val |= PIPECONF_8BPC;
c8203565
PZ		 8530 break;
8531 case 30:
dfd07d72 8532 val |= PIPECONF_10BPC;
c8203565
PZ		 8533 break;
8534 case 36:
dfd07d72 8535 val |= PIPECONF_12BPC;
c8203565
PZ		 8536 break;
8537 default:
cc769b62
PZ		 8538 /* Case prevented by intel_choose_pipe_bpp_dither. */
8539 BUG();
c8203565
PZ		 8540 }
8541
6e3c9717 8542 if (intel_crtc->config->dither)
c8203565
PZ		 8543 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8544
6e3c9717 8545 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8546 val |= PIPECONF_INTERLACED_ILK;
8547 else
8548 val |= PIPECONF_PROGRESSIVE;
8549
6e3c9717 8550 if (intel_crtc->config->limited_color_range)
3685a8f3 8551 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8552
c8203565
PZ		 8553 I915_WRITE(PIPECONF(pipe), val);
8554 POSTING_READ(PIPECONF(pipe));
8555}
8556
86d3efce
VS		 8557/*
8558 * Set up the pipe CSC unit.
8559 *
8560 * Currently only full range RGB to limited range RGB conversion
8561 * is supported, but eventually this should handle various
8562 * RGB<->YCbCr scenarios as well.
8563 */
50f3b016 8564static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8565{
8566 struct drm_device *dev = crtc->dev;
8567 struct drm_i915_private *dev_priv = dev->dev_private;
8568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8569 int pipe = intel_crtc->pipe;
8570 uint16_t coeff = 0x7800; /* 1.0 */
8571
8572 /*
8573 * TODO: Check what kind of values actually come out of the pipe
8574 * with these coeff/postoff values and adjust to get the best
8575 * accuracy. Perhaps we even need to take the bpc value into
8576 * consideration.
8577 */
8578
6e3c9717 8579 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8580 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8581
8582 /*
8583 * GY/GU and RY/RU should be the other way around according
8584 * to BSpec, but reality doesn't agree. Just set them up in
8585 * a way that results in the correct picture.
8586 */
8587 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8588 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8589
8590 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8591 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8592
8593 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8594 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8595
8596 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8597 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8598 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8599
8600 if (INTEL_INFO(dev)->gen > 6) {
8601 uint16_t postoff = 0;
8602
6e3c9717 8603 if (intel_crtc->config->limited_color_range)
32cf0cb0 8604 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8605
8606 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8607 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8608 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8609
8610 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8611 } else {
8612 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8613
6e3c9717 8614 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8615 mode |= CSC_BLACK_SCREEN_OFFSET;
8616
8617 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8618 }
8619}
8620
6ff93609 8621static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8622{
756f85cf
PZ		 8623 struct drm_device *dev = crtc->dev;
8624 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8626 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8627 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8628 uint32_t val;
8629
3eff4faa 8630 val = 0;
ee2b0b38 8631
6e3c9717 8632 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8633 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8634
6e3c9717 8635 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8636 val |= PIPECONF_INTERLACED_ILK;
8637 else
8638 val |= PIPECONF_PROGRESSIVE;
8639
702e7a56
PZ		 8640 I915_WRITE(PIPECONF(cpu_transcoder), val);
8641 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8642
8643 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8644 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8645
3cdf122c 8646 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8647 val = 0;
8648
6e3c9717 8649 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8650 case 18:
8651 val |= PIPEMISC_DITHER_6_BPC;
8652 break;
8653 case 24:
8654 val |= PIPEMISC_DITHER_8_BPC;
8655 break;
8656 case 30:
8657 val |= PIPEMISC_DITHER_10_BPC;
8658 break;
8659 case 36:
8660 val |= PIPEMISC_DITHER_12_BPC;
8661 break;
8662 default:
8663 /* Case prevented by pipe_config_set_bpp. */
8664 BUG();
8665 }
8666
6e3c9717 8667 if (intel_crtc->config->dither)
756f85cf
PZ		 8668 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8669
8670 I915_WRITE(PIPEMISC(pipe), val);
8671 }
ee2b0b38
PZ		 8672}
8673
6591c6e4 8674static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8675 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8676 intel_clock_t *clock,
8677 bool *has_reduced_clock,
8678 intel_clock_t *reduced_clock)
8679{
8680 struct drm_device *dev = crtc->dev;
8681 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8682 int refclk;
d4906093 8683 const intel_limit_t *limit;
c329a4ec 8684 bool ret;
79e53945 8685
55bb9992 8686 refclk = ironlake_get_refclk(crtc_state);
79e53945 8687
d4906093
ML		 8688 /*
8689 * Returns a set of divisors for the desired target clock with the given
8690 * refclk, or FALSE. The returned values represent the clock equation:
8691 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8692 */
a93e255f
ACO		 8693 limit = intel_limit(crtc_state, refclk);
8694 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8695 crtc_state->port_clock,
ee9300bb 8696 refclk, NULL, clock);
6591c6e4
PZ		 8697 if (!ret)
8698 return false;
cda4b7d3 8699
6591c6e4
PZ		 8700 return true;
8701}
8702
d4b1931c
PZ		 8703int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8704{
8705 /*
8706 * Account for spread spectrum to avoid
8707 * oversubscribing the link. Max center spread
8708 * is 2.5%; use 5% for safety's sake.
8709 */
8710 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8711 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8712}
8713
7429e9d4 8714static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8715{
7429e9d4 8716 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8717}
8718
de13a2e3 8719static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8720 struct intel_crtc_state *crtc_state,
7429e9d4 8721 u32 *fp,
9a7c7890 8722 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8723{
de13a2e3 8724 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8725 struct drm_device *dev = crtc->dev;
8726 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8727 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8728 struct drm_connector *connector;
55bb9992
ACO		 8729 struct drm_connector_state *connector_state;
8730 struct intel_encoder *encoder;
de13a2e3 8731 uint32_t dpll;
55bb9992 8732 int factor, num_connectors = 0, i;
09ede541 8733 bool is_lvds = false, is_sdvo = false;
79e53945 8734
da3ced29 8735 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8736 if (connector_state->crtc != crtc_state->base.crtc)
8737 continue;
8738
8739 encoder = to_intel_encoder(connector_state->best_encoder);
8740
8741 switch (encoder->type) {
79e53945
JB		 8742 case INTEL_OUTPUT_LVDS:
8743 is_lvds = true;
8744 break;
8745 case INTEL_OUTPUT_SDVO:
7d57382e 8746 case INTEL_OUTPUT_HDMI:
79e53945 8747 is_sdvo = true;
79e53945 8748 break;
6847d71b
PZ		 8749 default:
8750 break;
79e53945 8751 }
43565a06 8752
c751ce4f 8753 num_connectors++;
79e53945 8754 }
79e53945 8755
c1858123 8756 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8757 factor = 21;
8758 if (is_lvds) {
8759 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8760 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8761 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8762 factor = 25;
190f68c5 8763 } else if (crtc_state->sdvo_tv_clock)
8febb297 8764 factor = 20;
c1858123 8765
190f68c5 8766 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8767 *fp |= FP_CB_TUNE;
2c07245f 8768
9a7c7890
DV		 8769 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8770 *fp2 |= FP_CB_TUNE;
8771
5eddb70b 8772 dpll = 0;
2c07245f 8773
a07d6787
EA		 8774 if (is_lvds)
8775 dpll |= DPLLB_MODE_LVDS;
8776 else
8777 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8778
190f68c5 8779 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8780 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8781
8782 if (is_sdvo)
4a33e48d 8783 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8784 if (crtc_state->has_dp_encoder)
4a33e48d 8785 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8786
a07d6787 8787 /* compute bitmask from p1 value */
190f68c5 8788 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8789 /* also FPA1 */
190f68c5 8790 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8791
190f68c5 8792 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8793 case 5:
8794 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8795 break;
8796 case 7:
8797 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8798 break;
8799 case 10:
8800 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8801 break;
8802 case 14:
8803 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8804 break;
79e53945
JB		 8805 }
8806
b4c09f3b 8807 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8808 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8809 else
8810 dpll |= PLL_REF_INPUT_DREFCLK;
8811
959e16d6 8812 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8813}
8814
190f68c5
ACO		 8815static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8816 struct intel_crtc_state *crtc_state)
de13a2e3 8817{
c7653199 8818 struct drm_device *dev = crtc->base.dev;
de13a2e3 8819 intel_clock_t clock, reduced_clock;
cbbab5bd 8820 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8821 bool ok, has_reduced_clock = false;
8b47047b 8822 bool is_lvds = false;
e2b78267 8823 struct intel_shared_dpll *pll;
de13a2e3 8824
dd3cd74a
ACO		 8825 memset(&crtc_state->dpll_hw_state, 0,
8826 sizeof(crtc_state->dpll_hw_state));
8827
409ee761 8828 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8829
5dc5298b
PZ		 8830 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8831 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8832
190f68c5 8833 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8834 &has_reduced_clock, &reduced_clock);
190f68c5 8835 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8836 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8837 return -EINVAL;
79e53945 8838 }
f47709a9 8839 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8840 if (!crtc_state->clock_set) {
8841 crtc_state->dpll.n = clock.n;
8842 crtc_state->dpll.m1 = clock.m1;
8843 crtc_state->dpll.m2 = clock.m2;
8844 crtc_state->dpll.p1 = clock.p1;
8845 crtc_state->dpll.p2 = clock.p2;
f47709a9 8846 }
79e53945 8847
5dc5298b 8848 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8849 if (crtc_state->has_pch_encoder) {
8850 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8851 if (has_reduced_clock)
7429e9d4 8852 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8853
190f68c5 8854 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8855 &fp, &reduced_clock,
8856 has_reduced_clock ? &fp2 : NULL);
8857
190f68c5
ACO		 8858 crtc_state->dpll_hw_state.dpll = dpll;
8859 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8860 if (has_reduced_clock)
190f68c5 8861 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8862 else
190f68c5 8863 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8864
190f68c5 8865 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8866 if (pll == NULL) {
84f44ce7 8867 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8868 pipe_name(crtc->pipe));
4b645f14
JB		 8869 return -EINVAL;
8870 }
3fb37703 8871 }
79e53945 8872
ab585dea 8873 if (is_lvds && has_reduced_clock)
c7653199 8874 crtc->lowfreq_avail = true;
bcd644e0 8875 else
c7653199 8876 crtc->lowfreq_avail = false;
e2b78267 8877
c8f7a0db 8878 return 0;
79e53945
JB		 8879}
8880
eb14cb74
VS		 8881static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8882 struct intel_link_m_n *m_n)
8883{
8884 struct drm_device *dev = crtc->base.dev;
8885 struct drm_i915_private *dev_priv = dev->dev_private;
8886 enum pipe pipe = crtc->pipe;
8887
8888 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8889 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8890 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8891 & ~TU_SIZE_MASK;
8892 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8893 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8894 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8895}
8896
8897static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8898 enum transcoder transcoder,
b95af8be
VK		 8899 struct intel_link_m_n *m_n,
8900 struct intel_link_m_n *m2_n2)
72419203
DV		 8901{
8902 struct drm_device *dev = crtc->base.dev;
8903 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8904 enum pipe pipe = crtc->pipe;
72419203 8905
eb14cb74
VS		 8906 if (INTEL_INFO(dev)->gen >= 5) {
8907 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8908 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8909 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8910 & ~TU_SIZE_MASK;
8911 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8912 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8913 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8914 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8915 * gen < 8) and if DRRS is supported (to make sure the
8916 * registers are not unnecessarily read).
8917 */
8918 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8919 crtc->config->has_drrs) {
b95af8be
VK		 8920 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8921 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8922 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8923 & ~TU_SIZE_MASK;
8924 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8925 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8926 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8927 }
eb14cb74
VS		 8928 } else {
8929 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8930 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8931 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8932 & ~TU_SIZE_MASK;
8933 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8934 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8935 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8936 }
8937}
8938
8939void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8940 struct intel_crtc_state *pipe_config)
eb14cb74 8941{
681a8504 8942 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8943 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8944 else
8945 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8946 &pipe_config->dp_m_n,
8947 &pipe_config->dp_m2_n2);
eb14cb74 8948}
72419203 8949
eb14cb74 8950static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8951 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8952{
8953 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8954 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8955}
8956
bd2e244f 8957static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8958 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8959{
8960 struct drm_device *dev = crtc->base.dev;
8961 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8962 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8963 uint32_t ps_ctrl = 0;
8964 int id = -1;
8965 int i;
bd2e244f 8966
a1b2278e
CK		 8967 /* find scaler attached to this pipe */
8968 for (i = 0; i < crtc->num_scalers; i++) {
8969 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8970 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8971 id = i;
8972 pipe_config->pch_pfit.enabled = true;
8973 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8974 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8975 break;
8976 }
8977 }
bd2e244f 8978
a1b2278e
CK		 8979 scaler_state->scaler_id = id;
8980 if (id >= 0) {
8981 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8982 } else {
8983 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8984 }
8985}
8986
5724dbd1
DL		 8987static void
8988skylake_get_initial_plane_config(struct intel_crtc *crtc,
8989 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8990{
8991 struct drm_device *dev = crtc->base.dev;
8992 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8993 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8994 int pipe = crtc->pipe;
8995 int fourcc, pixel_format;
6761dd31 8996 unsigned int aligned_height;
bc8d7dff 8997 struct drm_framebuffer *fb;
1b842c89 8998 struct intel_framebuffer *intel_fb;
bc8d7dff 8999
d9806c9f 9000 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9001 if (!intel_fb) {
bc8d7dff
DL		 9002 DRM_DEBUG_KMS("failed to alloc fb\n");
9003 return;
9004 }
9005
1b842c89
DL		 9006 fb = &intel_fb->base;
9007
bc8d7dff 9008 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9009 if (!(val & PLANE_CTL_ENABLE))
9010 goto error;
9011
bc8d7dff
DL		 9012 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9013 fourcc = skl_format_to_fourcc(pixel_format,
9014 val & PLANE_CTL_ORDER_RGBX,
9015 val & PLANE_CTL_ALPHA_MASK);
9016 fb->pixel_format = fourcc;
9017 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9018
40f46283
DL		 9019 tiling = val & PLANE_CTL_TILED_MASK;
9020 switch (tiling) {
9021 case PLANE_CTL_TILED_LINEAR:
9022 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9023 break;
9024 case PLANE_CTL_TILED_X:
9025 plane_config->tiling = I915_TILING_X;
9026 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9027 break;
9028 case PLANE_CTL_TILED_Y:
9029 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9030 break;
9031 case PLANE_CTL_TILED_YF:
9032 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9033 break;
9034 default:
9035 MISSING_CASE(tiling);
9036 goto error;
9037 }
9038
bc8d7dff
DL		 9039 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9040 plane_config->base = base;
9041
9042 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9043
9044 val = I915_READ(PLANE_SIZE(pipe, 0));
9045 fb->height = ((val >> 16) & 0xfff) + 1;
9046 fb->width = ((val >> 0) & 0x1fff) + 1;
9047
9048 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9049 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9050 fb->pixel_format);
bc8d7dff
DL		 9051 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9052
9053 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9054 fb->pixel_format,
9055 fb->modifier[0]);
bc8d7dff 9056
f37b5c2b 9057 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9058
9059 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9060 pipe_name(pipe), fb->width, fb->height,
9061 fb->bits_per_pixel, base, fb->pitches[0],
9062 plane_config->size);
9063
2d14030b 9064 plane_config->fb = intel_fb;
bc8d7dff
DL		 9065 return;
9066
9067error:
9068 kfree(fb);
9069}
9070
2fa2fe9a 9071static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9072 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9073{
9074 struct drm_device *dev = crtc->base.dev;
9075 struct drm_i915_private *dev_priv = dev->dev_private;
9076 uint32_t tmp;
9077
9078 tmp = I915_READ(PF_CTL(crtc->pipe));
9079
9080 if (tmp & PF_ENABLE) {
fd4daa9c 9081 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9082 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9083 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9084
9085 /* We currently do not free assignements of panel fitters on
9086 * ivb/hsw (since we don't use the higher upscaling modes which
9087 * differentiates them) so just WARN about this case for now. */
9088 if (IS_GEN7(dev)) {
9089 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9090 PF_PIPE_SEL_IVB(crtc->pipe));
9091 }
2fa2fe9a 9092 }
79e53945
JB		 9093}
9094
5724dbd1
DL		 9095static void
9096ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9097 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9098{
9099 struct drm_device *dev = crtc->base.dev;
9100 struct drm_i915_private *dev_priv = dev->dev_private;
9101 u32 val, base, offset;
aeee5a49 9102 int pipe = crtc->pipe;
4c6baa59 9103 int fourcc, pixel_format;
6761dd31 9104 unsigned int aligned_height;
b113d5ee 9105 struct drm_framebuffer *fb;
1b842c89 9106 struct intel_framebuffer *intel_fb;
4c6baa59 9107
42a7b088
DL		 9108 val = I915_READ(DSPCNTR(pipe));
9109 if (!(val & DISPLAY_PLANE_ENABLE))
9110 return;
9111
d9806c9f 9112 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9113 if (!intel_fb) {
4c6baa59
JB		 9114 DRM_DEBUG_KMS("failed to alloc fb\n");
9115 return;
9116 }
9117
1b842c89
DL		 9118 fb = &intel_fb->base;
9119
18c5247e
DV		 9120 if (INTEL_INFO(dev)->gen >= 4) {
9121 if (val & DISPPLANE_TILED) {
49af449b 9122 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9123 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9124 }
9125 }
4c6baa59
JB		 9126
9127 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9128 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9129 fb->pixel_format = fourcc;
9130 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9131
aeee5a49 9132 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9133 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9134 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9135 } else {
49af449b 9136 if (plane_config->tiling)
aeee5a49 9137 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9138 else
aeee5a49 9139 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9140 }
9141 plane_config->base = base;
9142
9143 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9144 fb->width = ((val >> 16) & 0xfff) + 1;
9145 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9146
9147 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9148 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9149
b113d5ee 9150 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9151 fb->pixel_format,
9152 fb->modifier[0]);
4c6baa59 9153
f37b5c2b 9154 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9155
2844a921
DL		 9156 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9157 pipe_name(pipe), fb->width, fb->height,
9158 fb->bits_per_pixel, base, fb->pitches[0],
9159 plane_config->size);
b113d5ee 9160
2d14030b 9161 plane_config->fb = intel_fb;
4c6baa59
JB		 9162}
9163
0e8ffe1b 9164static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9165 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9166{
9167 struct drm_device *dev = crtc->base.dev;
9168 struct drm_i915_private *dev_priv = dev->dev_private;
9169 uint32_t tmp;
9170
f458ebbc
DV		 9171 if (!intel_display_power_is_enabled(dev_priv,
9172 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9173 return false;
9174
e143a21c 9175 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9176 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9177
0e8ffe1b
DV		 9178 tmp = I915_READ(PIPECONF(crtc->pipe));
9179 if (!(tmp & PIPECONF_ENABLE))
9180 return false;
9181
42571aef
VS		 9182 switch (tmp & PIPECONF_BPC_MASK) {
9183 case PIPECONF_6BPC:
9184 pipe_config->pipe_bpp = 18;
9185 break;
9186 case PIPECONF_8BPC:
9187 pipe_config->pipe_bpp = 24;
9188 break;
9189 case PIPECONF_10BPC:
9190 pipe_config->pipe_bpp = 30;
9191 break;
9192 case PIPECONF_12BPC:
9193 pipe_config->pipe_bpp = 36;
9194 break;
9195 default:
9196 break;
9197 }
9198
b5a9fa09
DV		 9199 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9200 pipe_config->limited_color_range = true;
9201
ab9412ba 9202 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9203 struct intel_shared_dpll *pll;
9204
88adfff1
DV		 9205 pipe_config->has_pch_encoder = true;
9206
627eb5a3
DV		 9207 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9208 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9209 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9210
9211 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9212
c0d43d62 9213 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9214 pipe_config->shared_dpll =
9215 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9216 } else {
9217 tmp = I915_READ(PCH_DPLL_SEL);
9218 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9219 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9220 else
9221 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9222 }
66e985c0
DV		 9223
9224 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9225
9226 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9227 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9228
9229 tmp = pipe_config->dpll_hw_state.dpll;
9230 pipe_config->pixel_multiplier =
9231 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9232 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9233
9234 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9235 } else {
9236 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9237 }
9238
1bd1bd80
DV		 9239 intel_get_pipe_timings(crtc, pipe_config);
9240
2fa2fe9a
DV		 9241 ironlake_get_pfit_config(crtc, pipe_config);
9242
0e8ffe1b
DV		 9243 return true;
9244}
9245
be256dc7
PZ		 9246static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9247{
9248 struct drm_device *dev = dev_priv->dev;
be256dc7 9249 struct intel_crtc *crtc;
be256dc7 9250
d3fcc808 9251 for_each_intel_crtc(dev, crtc)
e2c719b7 9252 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9253 pipe_name(crtc->pipe));
9254
e2c719b7
RC		 9255 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9256 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9257 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9258 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9259 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9260 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9261 "CPU PWM1 enabled\n");
c5107b87 9262 if (IS_HASWELL(dev))
e2c719b7 9263 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9264 "CPU PWM2 enabled\n");
e2c719b7 9265 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9266 "PCH PWM1 enabled\n");
e2c719b7 9267 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9268 "Utility pin enabled\n");
e2c719b7 9269 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9270
9926ada1
PZ		 9271 /*
9272 * In theory we can still leave IRQs enabled, as long as only the HPD
9273 * interrupts remain enabled. We used to check for that, but since it's
9274 * gen-specific and since we only disable LCPLL after we fully disable
9275 * the interrupts, the check below should be enough.
9276 */
e2c719b7 9277 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9278}
9279
9ccd5aeb
PZ		 9280static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9281{
9282 struct drm_device *dev = dev_priv->dev;
9283
9284 if (IS_HASWELL(dev))
9285 return I915_READ(D_COMP_HSW);
9286 else
9287 return I915_READ(D_COMP_BDW);
9288}
9289
3c4c9b81
PZ		 9290static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9291{
9292 struct drm_device *dev = dev_priv->dev;
9293
9294 if (IS_HASWELL(dev)) {
9295 mutex_lock(&dev_priv->rps.hw_lock);
9296 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9297 val))
f475dadf 9298 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9299 mutex_unlock(&dev_priv->rps.hw_lock);
9300 } else {
9ccd5aeb
PZ		 9301 I915_WRITE(D_COMP_BDW, val);
9302 POSTING_READ(D_COMP_BDW);
3c4c9b81 9303 }
be256dc7
PZ		 9304}
9305
9306/*
9307 * This function implements pieces of two sequences from BSpec:
9308 * - Sequence for display software to disable LCPLL
9309 * - Sequence for display software to allow package C8+
9310 * The steps implemented here are just the steps that actually touch the LCPLL
9311 * register. Callers should take care of disabling all the display engine
9312 * functions, doing the mode unset, fixing interrupts, etc.
9313 */
6ff58d53
PZ		 9314static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9315 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9316{
9317 uint32_t val;
9318
9319 assert_can_disable_lcpll(dev_priv);
9320
9321 val = I915_READ(LCPLL_CTL);
9322
9323 if (switch_to_fclk) {
9324 val |= LCPLL_CD_SOURCE_FCLK;
9325 I915_WRITE(LCPLL_CTL, val);
9326
9327 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9328 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9329 DRM_ERROR("Switching to FCLK failed\n");
9330
9331 val = I915_READ(LCPLL_CTL);
9332 }
9333
9334 val |= LCPLL_PLL_DISABLE;
9335 I915_WRITE(LCPLL_CTL, val);
9336 POSTING_READ(LCPLL_CTL);
9337
9338 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9339 DRM_ERROR("LCPLL still locked\n");
9340
9ccd5aeb 9341 val = hsw_read_dcomp(dev_priv);
be256dc7 9342 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9343 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9344 ndelay(100);
9345
9ccd5aeb
PZ		 9346 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9347 1))
be256dc7
PZ		 9348 DRM_ERROR("D_COMP RCOMP still in progress\n");
9349
9350 if (allow_power_down) {
9351 val = I915_READ(LCPLL_CTL);
9352 val |= LCPLL_POWER_DOWN_ALLOW;
9353 I915_WRITE(LCPLL_CTL, val);
9354 POSTING_READ(LCPLL_CTL);
9355 }
9356}
9357
9358/*
9359 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9360 * source.
9361 */
6ff58d53 9362static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9363{
9364 uint32_t val;
9365
9366 val = I915_READ(LCPLL_CTL);
9367
9368 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9369 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9370 return;
9371
a8a8bd54
PZ		 9372 /*
9373 * Make sure we're not on PC8 state before disabling PC8, otherwise
9374 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9375 */
59bad947 9376 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9377
be256dc7
PZ		 9378 if (val & LCPLL_POWER_DOWN_ALLOW) {
9379 val &= ~LCPLL_POWER_DOWN_ALLOW;
9380 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9381 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9382 }
9383
9ccd5aeb 9384 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9385 val |= D_COMP_COMP_FORCE;
9386 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9387 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9388
9389 val = I915_READ(LCPLL_CTL);
9390 val &= ~LCPLL_PLL_DISABLE;
9391 I915_WRITE(LCPLL_CTL, val);
9392
9393 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9394 DRM_ERROR("LCPLL not locked yet\n");
9395
9396 if (val & LCPLL_CD_SOURCE_FCLK) {
9397 val = I915_READ(LCPLL_CTL);
9398 val &= ~LCPLL_CD_SOURCE_FCLK;
9399 I915_WRITE(LCPLL_CTL, val);
9400
9401 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9402 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9403 DRM_ERROR("Switching back to LCPLL failed\n");
9404 }
215733fa 9405
59bad947 9406 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9407 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9408}
9409
765dab67
PZ		 9410/*
9411 * Package states C8 and deeper are really deep PC states that can only be
9412 * reached when all the devices on the system allow it, so even if the graphics
9413 * device allows PC8+, it doesn't mean the system will actually get to these
9414 * states. Our driver only allows PC8+ when going into runtime PM.
9415 *
9416 * The requirements for PC8+ are that all the outputs are disabled, the power
9417 * well is disabled and most interrupts are disabled, and these are also
9418 * requirements for runtime PM. When these conditions are met, we manually do
9419 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9420 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9421 * hang the machine.
9422 *
9423 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9424 * the state of some registers, so when we come back from PC8+ we need to
9425 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9426 * need to take care of the registers kept by RC6. Notice that this happens even
9427 * if we don't put the device in PCI D3 state (which is what currently happens
9428 * because of the runtime PM support).
9429 *
9430 * For more, read "Display Sequences for Package C8" on the hardware
9431 * documentation.
9432 */
a14cb6fc 9433void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9434{
c67a470b
PZ		 9435 struct drm_device *dev = dev_priv->dev;
9436 uint32_t val;
9437
c67a470b
PZ		 9438 DRM_DEBUG_KMS("Enabling package C8+\n");
9439
c67a470b
PZ		 9440 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9441 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9442 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9443 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9444 }
9445
9446 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9447 hsw_disable_lcpll(dev_priv, true, true);
9448}
9449
a14cb6fc 9450void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9451{
9452 struct drm_device *dev = dev_priv->dev;
9453 uint32_t val;
9454
c67a470b
PZ		 9455 DRM_DEBUG_KMS("Disabling package C8+\n");
9456
9457 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9458 lpt_init_pch_refclk(dev);
9459
9460 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9461 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9462 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9463 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9464 }
9465
9466 intel_prepare_ddi(dev);
c67a470b
PZ		 9467}
9468
27c329ed 9469static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9470{
a821fc46 9471 struct drm_device *dev = old_state->dev;
27c329ed 9472 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9473
27c329ed 9474 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9475}
9476
b432e5cf 9477/* compute the max rate for new configuration */
27c329ed 9478static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9479{
b432e5cf 9480 struct intel_crtc *intel_crtc;
27c329ed 9481 struct intel_crtc_state *crtc_state;
b432e5cf 9482 int max_pixel_rate = 0;
b432e5cf 9483
27c329ed
ML		 9484 for_each_intel_crtc(state->dev, intel_crtc) {
9485 int pixel_rate;
9486
9487 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9488 if (IS_ERR(crtc_state))
9489 return PTR_ERR(crtc_state);
9490
9491 if (!crtc_state->base.enable)
b432e5cf
VS		 9492 continue;
9493
27c329ed 9494 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9495
9496 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9497 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9498 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9499
9500 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9501 }
9502
9503 return max_pixel_rate;
9504}
9505
9506static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9507{
9508 struct drm_i915_private *dev_priv = dev->dev_private;
9509 uint32_t val, data;
9510 int ret;
9511
9512 if (WARN((I915_READ(LCPLL_CTL) &
9513 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9514 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9515 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9516 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9517 "trying to change cdclk frequency with cdclk not enabled\n"))
9518 return;
9519
9520 mutex_lock(&dev_priv->rps.hw_lock);
9521 ret = sandybridge_pcode_write(dev_priv,
9522 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9523 mutex_unlock(&dev_priv->rps.hw_lock);
9524 if (ret) {
9525 DRM_ERROR("failed to inform pcode about cdclk change\n");
9526 return;
9527 }
9528
9529 val = I915_READ(LCPLL_CTL);
9530 val |= LCPLL_CD_SOURCE_FCLK;
9531 I915_WRITE(LCPLL_CTL, val);
9532
9533 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9534 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9535 DRM_ERROR("Switching to FCLK failed\n");
9536
9537 val = I915_READ(LCPLL_CTL);
9538 val &= ~LCPLL_CLK_FREQ_MASK;
9539
9540 switch (cdclk) {
9541 case 450000:
9542 val |= LCPLL_CLK_FREQ_450;
9543 data = 0;
9544 break;
9545 case 540000:
9546 val |= LCPLL_CLK_FREQ_54O_BDW;
9547 data = 1;
9548 break;
9549 case 337500:
9550 val |= LCPLL_CLK_FREQ_337_5_BDW;
9551 data = 2;
9552 break;
9553 case 675000:
9554 val |= LCPLL_CLK_FREQ_675_BDW;
9555 data = 3;
9556 break;
9557 default:
9558 WARN(1, "invalid cdclk frequency\n");
9559 return;
9560 }
9561
9562 I915_WRITE(LCPLL_CTL, val);
9563
9564 val = I915_READ(LCPLL_CTL);
9565 val &= ~LCPLL_CD_SOURCE_FCLK;
9566 I915_WRITE(LCPLL_CTL, val);
9567
9568 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9569 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9570 DRM_ERROR("Switching back to LCPLL failed\n");
9571
9572 mutex_lock(&dev_priv->rps.hw_lock);
9573 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9574 mutex_unlock(&dev_priv->rps.hw_lock);
9575
9576 intel_update_cdclk(dev);
9577
9578 WARN(cdclk != dev_priv->cdclk_freq,
9579 "cdclk requested %d kHz but got %d kHz\n",
9580 cdclk, dev_priv->cdclk_freq);
9581}
9582
27c329ed 9583static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9584{
27c329ed
ML		 9585 struct drm_i915_private *dev_priv = to_i915(state->dev);
9586 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9587 int cdclk;
9588
9589 /*
9590 * FIXME should also account for plane ratio
9591 * once 64bpp pixel formats are supported.
9592 */
27c329ed 9593 if (max_pixclk > 540000)
b432e5cf 9594 cdclk = 675000;
27c329ed 9595 else if (max_pixclk > 450000)
b432e5cf 9596 cdclk = 540000;
27c329ed 9597 else if (max_pixclk > 337500)
b432e5cf
VS		 9598 cdclk = 450000;
9599 else
9600 cdclk = 337500;
9601
9602 /*
9603 * FIXME move the cdclk caclulation to
9604 * compute_config() so we can fail gracegully.
9605 */
9606 if (cdclk > dev_priv->max_cdclk_freq) {
9607 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9608 cdclk, dev_priv->max_cdclk_freq);
9609 cdclk = dev_priv->max_cdclk_freq;
9610 }
9611
27c329ed 9612 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9613
9614 return 0;
9615}
9616
27c329ed 9617static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9618{
27c329ed
ML		 9619 struct drm_device *dev = old_state->dev;
9620 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9621
27c329ed 9622 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9623}
9624
190f68c5
ACO		 9625static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9626 struct intel_crtc_state *crtc_state)
09b4ddf9 9627{
190f68c5 9628 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9629 return -EINVAL;
716c2e55 9630
c7653199 9631 crtc->lowfreq_avail = false;
644cef34 9632
c8f7a0db 9633 return 0;
79e53945
JB		 9634}
9635
3760b59c
S		 9636static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9637 enum port port,
9638 struct intel_crtc_state *pipe_config)
9639{
9640 switch (port) {
9641 case PORT_A:
9642 pipe_config->ddi_pll_sel = SKL_DPLL0;
9643 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9644 break;
9645 case PORT_B:
9646 pipe_config->ddi_pll_sel = SKL_DPLL1;
9647 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9648 break;
9649 case PORT_C:
9650 pipe_config->ddi_pll_sel = SKL_DPLL2;
9651 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9652 break;
9653 default:
9654 DRM_ERROR("Incorrect port type\n");
9655 }
9656}
9657
96b7dfb7
S		 9658static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9659 enum port port,
5cec258b 9660 struct intel_crtc_state *pipe_config)
96b7dfb7 9661{
3148ade7 9662 u32 temp, dpll_ctl1;
96b7dfb7
S		 9663
9664 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9665 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9666
9667 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9668 case SKL_DPLL0:
9669 /*
9670 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9671 * of the shared DPLL framework and thus needs to be read out
9672 * separately
9673 */
9674 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9675 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9676 break;
96b7dfb7
S		 9677 case SKL_DPLL1:
9678 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9679 break;
9680 case SKL_DPLL2:
9681 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9682 break;
9683 case SKL_DPLL3:
9684 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9685 break;
96b7dfb7
S		 9686 }
9687}
9688
7d2c8175
DL		 9689static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9690 enum port port,
5cec258b 9691 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9692{
9693 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9694
9695 switch (pipe_config->ddi_pll_sel) {
9696 case PORT_CLK_SEL_WRPLL1:
9697 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9698 break;
9699 case PORT_CLK_SEL_WRPLL2:
9700 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9701 break;
9702 }
9703}
9704
26804afd 9705static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9706 struct intel_crtc_state *pipe_config)
26804afd
DV		 9707{
9708 struct drm_device *dev = crtc->base.dev;
9709 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9710 struct intel_shared_dpll *pll;
26804afd
DV		 9711 enum port port;
9712 uint32_t tmp;
9713
9714 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9715
9716 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9717
96b7dfb7
S		 9718 if (IS_SKYLAKE(dev))
9719 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9720 else if (IS_BROXTON(dev))
9721 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9722 else
9723 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9724
d452c5b6
DV		 9725 if (pipe_config->shared_dpll >= 0) {
9726 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9727
9728 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9729 &pipe_config->dpll_hw_state));
9730 }
9731
26804afd
DV		 9732 /*
9733 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9734 * DDI E. So just check whether this pipe is wired to DDI E and whether
9735 * the PCH transcoder is on.
9736 */
ca370455
DL		 9737 if (INTEL_INFO(dev)->gen < 9 &&
9738 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9739 pipe_config->has_pch_encoder = true;
9740
9741 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9742 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9743 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9744
9745 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9746 }
9747}
9748
0e8ffe1b 9749static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9750 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9751{
9752 struct drm_device *dev = crtc->base.dev;
9753 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9754 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9755 uint32_t tmp;
9756
f458ebbc 9757 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9758 POWER_DOMAIN_PIPE(crtc->pipe)))
9759 return false;
9760
e143a21c 9761 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9762 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9763
eccb140b
DV		 9764 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9765 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9766 enum pipe trans_edp_pipe;
9767 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9768 default:
9769 WARN(1, "unknown pipe linked to edp transcoder\n");
9770 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9771 case TRANS_DDI_EDP_INPUT_A_ON:
9772 trans_edp_pipe = PIPE_A;
9773 break;
9774 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9775 trans_edp_pipe = PIPE_B;
9776 break;
9777 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9778 trans_edp_pipe = PIPE_C;
9779 break;
9780 }
9781
9782 if (trans_edp_pipe == crtc->pipe)
9783 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9784 }
9785
f458ebbc 9786 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9787 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9788 return false;
9789
eccb140b 9790 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9791 if (!(tmp & PIPECONF_ENABLE))
9792 return false;
9793
26804afd 9794 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9795
1bd1bd80
DV		 9796 intel_get_pipe_timings(crtc, pipe_config);
9797
a1b2278e
CK		 9798 if (INTEL_INFO(dev)->gen >= 9) {
9799 skl_init_scalers(dev, crtc, pipe_config);
9800 }
9801
2fa2fe9a 9802 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9803
9804 if (INTEL_INFO(dev)->gen >= 9) {
9805 pipe_config->scaler_state.scaler_id = -1;
9806 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9807 }
9808
bd2e244f 9809 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9810 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9811 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9812 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9813 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9814 else
9815 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9816 }
88adfff1 9817
e59150dc
JB		 9818 if (IS_HASWELL(dev))
9819 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9820 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9821
ebb69c95
CT		 9822 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9823 pipe_config->pixel_multiplier =
9824 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9825 } else {
9826 pipe_config->pixel_multiplier = 1;
9827 }
6c49f241 9828
0e8ffe1b
DV		 9829 return true;
9830}
9831
560b85bb
CW		 9832static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9833{
9834 struct drm_device *dev = crtc->dev;
9835 struct drm_i915_private *dev_priv = dev->dev_private;
9836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9837 uint32_t cntl = 0, size = 0;
560b85bb 9838
dc41c154 9839 if (base) {
3dd512fb
MR		 9840 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9841 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9842 unsigned int stride = roundup_pow_of_two(width) * 4;
9843
9844 switch (stride) {
9845 default:
9846 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9847 width, stride);
9848 stride = 256;
9849 /* fallthrough */
9850 case 256:
9851 case 512:
9852 case 1024:
9853 case 2048:
9854 break;
4b0e333e
CW		 9855 }
9856
dc41c154
VS		 9857 cntl |= CURSOR_ENABLE |
9858 CURSOR_GAMMA_ENABLE |
9859 CURSOR_FORMAT_ARGB |
9860 CURSOR_STRIDE(stride);
9861
9862 size = (height << 12) | width;
4b0e333e 9863 }
560b85bb 9864
dc41c154
VS		 9865 if (intel_crtc->cursor_cntl != 0 &&
9866 (intel_crtc->cursor_base != base ||
9867 intel_crtc->cursor_size != size ||
9868 intel_crtc->cursor_cntl != cntl)) {
9869 /* On these chipsets we can only modify the base/size/stride
9870 * whilst the cursor is disabled.
9871 */
9872 I915_WRITE(_CURACNTR, 0);
4b0e333e 9873 POSTING_READ(_CURACNTR);
dc41c154 9874 intel_crtc->cursor_cntl = 0;
4b0e333e 9875 }
560b85bb 9876
99d1f387 9877 if (intel_crtc->cursor_base != base) {
9db4a9c7 9878 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9879 intel_crtc->cursor_base = base;
9880 }
4726e0b0 9881
dc41c154
VS		 9882 if (intel_crtc->cursor_size != size) {
9883 I915_WRITE(CURSIZE, size);
9884 intel_crtc->cursor_size = size;
4b0e333e 9885 }
560b85bb 9886
4b0e333e 9887 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9888 I915_WRITE(_CURACNTR, cntl);
9889 POSTING_READ(_CURACNTR);
4b0e333e 9890 intel_crtc->cursor_cntl = cntl;
560b85bb 9891 }
560b85bb
CW		 9892}
9893
560b85bb 9894static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9895{
9896 struct drm_device *dev = crtc->dev;
9897 struct drm_i915_private *dev_priv = dev->dev_private;
9898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9899 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9900 uint32_t cntl;
9901
9902 cntl = 0;
9903 if (base) {
9904 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9905 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9906 case 64:
9907 cntl |= CURSOR_MODE_64_ARGB_AX;
9908 break;
9909 case 128:
9910 cntl |= CURSOR_MODE_128_ARGB_AX;
9911 break;
9912 case 256:
9913 cntl |= CURSOR_MODE_256_ARGB_AX;
9914 break;
9915 default:
3dd512fb 9916 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9917 return;
65a21cd6 9918 }
4b0e333e 9919 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9920
9921 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9922 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9923 }
65a21cd6 9924
8e7d688b 9925 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9926 cntl |= CURSOR_ROTATE_180;
9927
4b0e333e
CW		 9928 if (intel_crtc->cursor_cntl != cntl) {
9929 I915_WRITE(CURCNTR(pipe), cntl);
9930 POSTING_READ(CURCNTR(pipe));
9931 intel_crtc->cursor_cntl = cntl;
65a21cd6 9932 }
4b0e333e 9933
65a21cd6 9934 /* and commit changes on next vblank */
5efb3e28
VS		 9935 I915_WRITE(CURBASE(pipe), base);
9936 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9937
9938 intel_crtc->cursor_base = base;
65a21cd6
JB		 9939}
9940
cda4b7d3 9941/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9942static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9943 bool on)
cda4b7d3
CW		 9944{
9945 struct drm_device *dev = crtc->dev;
9946 struct drm_i915_private *dev_priv = dev->dev_private;
9947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9948 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9949 int x = crtc->cursor_x;
9950 int y = crtc->cursor_y;
d6e4db15 9951 u32 base = 0, pos = 0;
cda4b7d3 9952
d6e4db15 9953 if (on)
cda4b7d3 9954 base = intel_crtc->cursor_addr;
cda4b7d3 9955
6e3c9717 9956 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9957 base = 0;
9958
6e3c9717 9959 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9960 base = 0;
9961
9962 if (x < 0) {
3dd512fb 9963 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9964 base = 0;
9965
9966 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9967 x = -x;
9968 }
9969 pos |= x << CURSOR_X_SHIFT;
9970
9971 if (y < 0) {
3dd512fb 9972 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9973 base = 0;
9974
9975 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9976 y = -y;
9977 }
9978 pos |= y << CURSOR_Y_SHIFT;
9979
4b0e333e 9980 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9981 return;
9982
5efb3e28
VS		 9983 I915_WRITE(CURPOS(pipe), pos);
9984
4398ad45
VS		 9985 /* ILK+ do this automagically */
9986 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9987 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9988 base += (intel_crtc->base.cursor->state->crtc_h *
9989 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9990 }
9991
8ac54669 9992 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9993 i845_update_cursor(crtc, base);
9994 else
9995 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9996}
9997
dc41c154
VS		 9998static bool cursor_size_ok(struct drm_device *dev,
9999 uint32_t width, uint32_t height)
10000{
10001 if (width == 0 || height == 0)
10002 return false;
10003
10004 /*
10005 * 845g/865g are special in that they are only limited by
10006 * the width of their cursors, the height is arbitrary up to
10007 * the precision of the register. Everything else requires
10008 * square cursors, limited to a few power-of-two sizes.
10009 */
10010 if (IS_845G(dev) || IS_I865G(dev)) {
10011 if ((width & 63) != 0)
10012 return false;
10013
10014 if (width > (IS_845G(dev) ? 64 : 512))
10015 return false;
10016
10017 if (height > 1023)
10018 return false;
10019 } else {
10020 switch (width | height) {
10021 case 256:
10022 case 128:
10023 if (IS_GEN2(dev))
10024 return false;
10025 case 64:
10026 break;
10027 default:
10028 return false;
10029 }
10030 }
10031
10032 return true;
10033}
10034
79e53945 10035static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10036 u16 *blue, uint32_t start, uint32_t size)
79e53945 10037{
7203425a 10038 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10040
7203425a 10041 for (i = start; i < end; i++) {
79e53945
JB		 10042 intel_crtc->lut_r[i] = red[i] >> 8;
10043 intel_crtc->lut_g[i] = green[i] >> 8;
10044 intel_crtc->lut_b[i] = blue[i] >> 8;
10045 }
10046
10047 intel_crtc_load_lut(crtc);
10048}
10049
79e53945
JB		 10050/* VESA 640x480x72Hz mode to set on the pipe */
10051static struct drm_display_mode load_detect_mode = {
10052 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10053 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10054};
10055
a8bb6818
DV		 10056struct drm_framebuffer *
10057__intel_framebuffer_create(struct drm_device *dev,
10058 struct drm_mode_fb_cmd2 *mode_cmd,
10059 struct drm_i915_gem_object *obj)
d2dff872
CW		 10060{
10061 struct intel_framebuffer *intel_fb;
10062 int ret;
10063
10064 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10065 if (!intel_fb) {
6ccb81f2 10066 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10067 return ERR_PTR(-ENOMEM);
10068 }
10069
10070 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10071 if (ret)
10072 goto err;
d2dff872
CW		 10073
10074 return &intel_fb->base;
dd4916c5 10075err:
6ccb81f2 10076 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10077 kfree(intel_fb);
10078
10079 return ERR_PTR(ret);
d2dff872
CW		 10080}
10081
b5ea642a 10082static struct drm_framebuffer *
a8bb6818
DV		 10083intel_framebuffer_create(struct drm_device *dev,
10084 struct drm_mode_fb_cmd2 *mode_cmd,
10085 struct drm_i915_gem_object *obj)
10086{
10087 struct drm_framebuffer *fb;
10088 int ret;
10089
10090 ret = i915_mutex_lock_interruptible(dev);
10091 if (ret)
10092 return ERR_PTR(ret);
10093 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10094 mutex_unlock(&dev->struct_mutex);
10095
10096 return fb;
10097}
10098
d2dff872
CW		 10099static u32
10100intel_framebuffer_pitch_for_width(int width, int bpp)
10101{
10102 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10103 return ALIGN(pitch, 64);
10104}
10105
10106static u32
10107intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10108{
10109 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10110 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10111}
10112
10113static struct drm_framebuffer *
10114intel_framebuffer_create_for_mode(struct drm_device *dev,
10115 struct drm_display_mode *mode,
10116 int depth, int bpp)
10117{
10118 struct drm_i915_gem_object *obj;
0fed39bd 10119 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10120
10121 obj = i915_gem_alloc_object(dev,
10122 intel_framebuffer_size_for_mode(mode, bpp));
10123 if (obj == NULL)
10124 return ERR_PTR(-ENOMEM);
10125
10126 mode_cmd.width = mode->hdisplay;
10127 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10128 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10129 bpp);
5ca0c34a 10130 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10131
10132 return intel_framebuffer_create(dev, &mode_cmd, obj);
10133}
10134
10135static struct drm_framebuffer *
10136mode_fits_in_fbdev(struct drm_device *dev,
10137 struct drm_display_mode *mode)
10138{
4520f53a 10139#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10140 struct drm_i915_private *dev_priv = dev->dev_private;
10141 struct drm_i915_gem_object *obj;
10142 struct drm_framebuffer *fb;
10143
4c0e5528 10144 if (!dev_priv->fbdev)
d2dff872
CW		 10145 return NULL;
10146
4c0e5528 10147 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10148 return NULL;
10149
4c0e5528
DV		 10150 obj = dev_priv->fbdev->fb->obj;
10151 BUG_ON(!obj);
10152
8bcd4553 10153 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10154 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10155 fb->bits_per_pixel))
d2dff872
CW		 10156 return NULL;
10157
01f2c773 10158 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10159 return NULL;
10160
10161 return fb;
4520f53a
DV		 10162#else
10163 return NULL;
10164#endif
d2dff872
CW		 10165}
10166
d3a40d1b
ACO		 10167static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10168 struct drm_crtc *crtc,
10169 struct drm_display_mode *mode,
10170 struct drm_framebuffer *fb,
10171 int x, int y)
10172{
10173 struct drm_plane_state *plane_state;
10174 int hdisplay, vdisplay;
10175 int ret;
10176
10177 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10178 if (IS_ERR(plane_state))
10179 return PTR_ERR(plane_state);
10180
10181 if (mode)
10182 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10183 else
10184 hdisplay = vdisplay = 0;
10185
10186 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10187 if (ret)
10188 return ret;
10189 drm_atomic_set_fb_for_plane(plane_state, fb);
10190 plane_state->crtc_x = 0;
10191 plane_state->crtc_y = 0;
10192 plane_state->crtc_w = hdisplay;
10193 plane_state->crtc_h = vdisplay;
10194 plane_state->src_x = x << 16;
10195 plane_state->src_y = y << 16;
10196 plane_state->src_w = hdisplay << 16;
10197 plane_state->src_h = vdisplay << 16;
10198
10199 return 0;
10200}
10201
d2434ab7 10202bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10203 struct drm_display_mode *mode,
51fd371b
RC		 10204 struct intel_load_detect_pipe *old,
10205 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10206{
10207 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10208 struct intel_encoder *intel_encoder =
10209 intel_attached_encoder(connector);
79e53945 10210 struct drm_crtc *possible_crtc;
4ef69c7a 10211 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10212 struct drm_crtc *crtc = NULL;
10213 struct drm_device *dev = encoder->dev;
94352cf9 10214 struct drm_framebuffer *fb;
51fd371b 10215 struct drm_mode_config *config = &dev->mode_config;
83a57153 10216 struct drm_atomic_state *state = NULL;
944b0c76 10217 struct drm_connector_state *connector_state;
4be07317 10218 struct intel_crtc_state *crtc_state;
51fd371b 10219 int ret, i = -1;
79e53945 10220
d2dff872 10221 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10222 connector->base.id, connector->name,
8e329a03 10223 encoder->base.id, encoder->name);
d2dff872 10224
51fd371b
RC		 10225retry:
10226 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10227 if (ret)
10228 goto fail_unlock;
6e9f798d 10229
79e53945
JB		 10230 /*
10231 * Algorithm gets a little messy:
7a5e4805 10232 *
79e53945
JB		 10233 * - if the connector already has an assigned crtc, use it (but make
10234 * sure it's on first)
7a5e4805 10235 *
79e53945
JB		 10236 * - try to find the first unused crtc that can drive this connector,
10237 * and use that if we find one
79e53945
JB		 10238 */
10239
10240 /* See if we already have a CRTC for this connector */
10241 if (encoder->crtc) {
10242 crtc = encoder->crtc;
8261b191 10243
51fd371b 10244 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10245 if (ret)
10246 goto fail_unlock;
10247 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10248 if (ret)
10249 goto fail_unlock;
7b24056b 10250
24218aac 10251 old->dpms_mode = connector->dpms;
8261b191
CW		 10252 old->load_detect_temp = false;
10253
10254 /* Make sure the crtc and connector are running */
24218aac
DV		 10255 if (connector->dpms != DRM_MODE_DPMS_ON)
10256 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10257
7173188d 10258 return true;
79e53945
JB		 10259 }
10260
10261 /* Find an unused one (if possible) */
70e1e0ec 10262 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10263 i++;
10264 if (!(encoder->possible_crtcs & (1 << i)))
10265 continue;
83d65738 10266 if (possible_crtc->state->enable)
a459249c
VS		 10267 continue;
10268 /* This can occur when applying the pipe A quirk on resume. */
10269 if (to_intel_crtc(possible_crtc)->new_enabled)
10270 continue;
10271
10272 crtc = possible_crtc;
10273 break;
79e53945
JB		 10274 }
10275
10276 /*
10277 * If we didn't find an unused CRTC, don't use any.
10278 */
10279 if (!crtc) {
7173188d 10280 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10281 goto fail_unlock;
79e53945
JB		 10282 }
10283
51fd371b
RC		 10284 ret = drm_modeset_lock(&crtc->mutex, ctx);
10285 if (ret)
4d02e2de
DV		 10286 goto fail_unlock;
10287 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10288 if (ret)
51fd371b 10289 goto fail_unlock;
fc303101
DV		 10290 intel_encoder->new_crtc = to_intel_crtc(crtc);
10291 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10292
10293 intel_crtc = to_intel_crtc(crtc);
412b61d8 10294 intel_crtc->new_enabled = true;
24218aac 10295 old->dpms_mode = connector->dpms;
8261b191 10296 old->load_detect_temp = true;
d2dff872 10297 old->release_fb = NULL;
79e53945 10298
83a57153
ACO		 10299 state = drm_atomic_state_alloc(dev);
10300 if (!state)
10301 return false;
10302
10303 state->acquire_ctx = ctx;
10304
944b0c76
ACO		 10305 connector_state = drm_atomic_get_connector_state(state, connector);
10306 if (IS_ERR(connector_state)) {
10307 ret = PTR_ERR(connector_state);
10308 goto fail;
10309 }
10310
10311 connector_state->crtc = crtc;
10312 connector_state->best_encoder = &intel_encoder->base;
10313
4be07317
ACO		 10314 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10315 if (IS_ERR(crtc_state)) {
10316 ret = PTR_ERR(crtc_state);
10317 goto fail;
10318 }
10319
49d6fa21 10320 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10321
6492711d
CW		 10322 if (!mode)
10323 mode = &load_detect_mode;
79e53945 10324
d2dff872
CW		 10325 /* We need a framebuffer large enough to accommodate all accesses
10326 * that the plane may generate whilst we perform load detection.
10327 * We can not rely on the fbcon either being present (we get called
10328 * during its initialisation to detect all boot displays, or it may
10329 * not even exist) or that it is large enough to satisfy the
10330 * requested mode.
10331 */
94352cf9
DV		 10332 fb = mode_fits_in_fbdev(dev, mode);
10333 if (fb == NULL) {
d2dff872 10334 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10335 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10336 old->release_fb = fb;
d2dff872
CW		 10337 } else
10338 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10339 if (IS_ERR(fb)) {
d2dff872 10340 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10341 goto fail;
79e53945 10342 }
79e53945 10343
d3a40d1b
ACO		 10344 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10345 if (ret)
10346 goto fail;
10347
8c7b5ccb
ACO		 10348 drm_mode_copy(&crtc_state->base.mode, mode);
10349
568c634a 10350 if (intel_set_mode(state)) {
6492711d 10351 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10352 if (old->release_fb)
10353 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10354 goto fail;
79e53945 10355 }
9128b040 10356 crtc->primary->crtc = crtc;
7173188d 10357
79e53945 10358 /* let the connector get through one full cycle before testing */
9d0498a2 10359 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10360 return true;
412b61d8
VS		 10361
10362 fail:
83d65738 10363 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10364fail_unlock:
e5d958ef
ACO		 10365 drm_atomic_state_free(state);
10366 state = NULL;
83a57153 10367
51fd371b
RC		 10368 if (ret == -EDEADLK) {
10369 drm_modeset_backoff(ctx);
10370 goto retry;
10371 }
10372
412b61d8 10373 return false;
79e53945
JB		 10374}
10375
d2434ab7 10376void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10377 struct intel_load_detect_pipe *old,
10378 struct drm_modeset_acquire_ctx *ctx)
79e53945 10379{
83a57153 10380 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10381 struct intel_encoder *intel_encoder =
10382 intel_attached_encoder(connector);
4ef69c7a 10383 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10384 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10386 struct drm_atomic_state *state;
944b0c76 10387 struct drm_connector_state *connector_state;
4be07317 10388 struct intel_crtc_state *crtc_state;
d3a40d1b 10389 int ret;
79e53945 10390
d2dff872 10391 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10392 connector->base.id, connector->name,
8e329a03 10393 encoder->base.id, encoder->name);
d2dff872 10394
8261b191 10395 if (old->load_detect_temp) {
83a57153 10396 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10397 if (!state)
10398 goto fail;
83a57153
ACO		 10399
10400 state->acquire_ctx = ctx;
10401
944b0c76
ACO		 10402 connector_state = drm_atomic_get_connector_state(state, connector);
10403 if (IS_ERR(connector_state))
10404 goto fail;
10405
4be07317
ACO		 10406 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10407 if (IS_ERR(crtc_state))
10408 goto fail;
10409
fc303101
DV		 10410 to_intel_connector(connector)->new_encoder = NULL;
10411 intel_encoder->new_crtc = NULL;
412b61d8 10412 intel_crtc->new_enabled = false;
944b0c76
ACO		 10413
10414 connector_state->best_encoder = NULL;
10415 connector_state->crtc = NULL;
10416
49d6fa21 10417 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10418
d3a40d1b
ACO		 10419 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10420 0, 0);
10421 if (ret)
10422 goto fail;
10423
568c634a 10424 ret = intel_set_mode(state);
2bfb4627
ACO		 10425 if (ret)
10426 goto fail;
d2dff872 10427
36206361
DV		 10428 if (old->release_fb) {
10429 drm_framebuffer_unregister_private(old->release_fb);
10430 drm_framebuffer_unreference(old->release_fb);
10431 }
d2dff872 10432
0622a53c 10433 return;
79e53945
JB		 10434 }
10435
c751ce4f 10436 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10437 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10438 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10439
10440 return;
10441fail:
10442 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10443 drm_atomic_state_free(state);
79e53945
JB		 10444}
10445
da4a1efa 10446static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10447 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10448{
10449 struct drm_i915_private *dev_priv = dev->dev_private;
10450 u32 dpll = pipe_config->dpll_hw_state.dpll;
10451
10452 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10453 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10454 else if (HAS_PCH_SPLIT(dev))
10455 return 120000;
10456 else if (!IS_GEN2(dev))
10457 return 96000;
10458 else
10459 return 48000;
10460}
10461
79e53945 10462/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10463static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10464 struct intel_crtc_state *pipe_config)
79e53945 10465{
f1f644dc 10466 struct drm_device *dev = crtc->base.dev;
79e53945 10467 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10468 int pipe = pipe_config->cpu_transcoder;
293623f7 10469 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10470 u32 fp;
10471 intel_clock_t clock;
dccbea3b 10472 int port_clock;
da4a1efa 10473 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10474
10475 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10476 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10477 else
293623f7 10478 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10479
10480 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10481 if (IS_PINEVIEW(dev)) {
10482 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10483 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10484 } else {
10485 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10486 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10487 }
10488
a6c45cf0 10489 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10490 if (IS_PINEVIEW(dev))
10491 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10492 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10493 else
10494 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10495 DPLL_FPA01_P1_POST_DIV_SHIFT);
10496
10497 switch (dpll & DPLL_MODE_MASK) {
10498 case DPLLB_MODE_DAC_SERIAL:
10499 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10500 5 : 10;
10501 break;
10502 case DPLLB_MODE_LVDS:
10503 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10504 7 : 14;
10505 break;
10506 default:
28c97730 10507 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10508 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10509 return;
79e53945
JB		 10510 }
10511
ac58c3f0 10512 if (IS_PINEVIEW(dev))
dccbea3b 10513 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10514 else
dccbea3b 10515 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10516 } else {
0fb58223 10517 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10518 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10519
10520 if (is_lvds) {
10521 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10522 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10523
10524 if (lvds & LVDS_CLKB_POWER_UP)
10525 clock.p2 = 7;
10526 else
10527 clock.p2 = 14;
79e53945
JB		 10528 } else {
10529 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10530 clock.p1 = 2;
10531 else {
10532 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10533 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10534 }
10535 if (dpll & PLL_P2_DIVIDE_BY_4)
10536 clock.p2 = 4;
10537 else
10538 clock.p2 = 2;
79e53945 10539 }
da4a1efa 10540
dccbea3b 10541 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10542 }
10543
18442d08
VS		 10544 /*
10545 * This value includes pixel_multiplier. We will use
241bfc38 10546 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10547 * encoder's get_config() function.
10548 */
dccbea3b 10549 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10550}
10551
6878da05
VS		 10552int intel_dotclock_calculate(int link_freq,
10553 const struct intel_link_m_n *m_n)
f1f644dc 10554{
f1f644dc
JB		 10555 /*
10556 * The calculation for the data clock is:
1041a02f 10557 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10558 * But we want to avoid losing precison if possible, so:
1041a02f 10559 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10560 *
10561 * and the link clock is simpler:
1041a02f 10562 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10563 */
10564
6878da05
VS		 10565 if (!m_n->link_n)
10566 return 0;
f1f644dc 10567
6878da05
VS		 10568 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10569}
f1f644dc 10570
18442d08 10571static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10572 struct intel_crtc_state *pipe_config)
6878da05
VS		 10573{
10574 struct drm_device *dev = crtc->base.dev;
79e53945 10575
18442d08
VS		 10576 /* read out port_clock from the DPLL */
10577 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10578
f1f644dc 10579 /*
18442d08 10580 * This value does not include pixel_multiplier.
241bfc38 10581 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10582 * agree once we know their relationship in the encoder's
10583 * get_config() function.
79e53945 10584 */
2d112de7 10585 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10586 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10587 &pipe_config->fdi_m_n);
79e53945
JB		 10588}
10589
10590/** Returns the currently programmed mode of the given pipe. */
10591struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10592 struct drm_crtc *crtc)
10593{
548f245b 10594 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10596 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10597 struct drm_display_mode *mode;
5cec258b 10598 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10599 int htot = I915_READ(HTOTAL(cpu_transcoder));
10600 int hsync = I915_READ(HSYNC(cpu_transcoder));
10601 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10602 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10603 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10604
10605 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10606 if (!mode)
10607 return NULL;
10608
f1f644dc
JB		 10609 /*
10610 * Construct a pipe_config sufficient for getting the clock info
10611 * back out of crtc_clock_get.
10612 *
10613 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10614 * to use a real value here instead.
10615 */
293623f7 10616 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10617 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10618 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10619 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10620 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10621 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10622
773ae034 10623 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10624 mode->hdisplay = (htot & 0xffff) + 1;
10625 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10626 mode->hsync_start = (hsync & 0xffff) + 1;
10627 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10628 mode->vdisplay = (vtot & 0xffff) + 1;
10629 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10630 mode->vsync_start = (vsync & 0xffff) + 1;
10631 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10632
10633 drm_mode_set_name(mode);
79e53945
JB		 10634
10635 return mode;
10636}
10637
f047e395
CW		 10638void intel_mark_busy(struct drm_device *dev)
10639{
c67a470b
PZ		 10640 struct drm_i915_private *dev_priv = dev->dev_private;
10641
f62a0076
CW		 10642 if (dev_priv->mm.busy)
10643 return;
10644
43694d69 10645 intel_runtime_pm_get(dev_priv);
c67a470b 10646 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10647 if (INTEL_INFO(dev)->gen >= 6)
10648 gen6_rps_busy(dev_priv);
f62a0076 10649 dev_priv->mm.busy = true;
f047e395
CW		 10650}
10651
10652void intel_mark_idle(struct drm_device *dev)
652c393a 10653{
c67a470b 10654 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10655
f62a0076
CW		 10656 if (!dev_priv->mm.busy)
10657 return;
10658
10659 dev_priv->mm.busy = false;
10660
3d13ef2e 10661 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10662 gen6_rps_idle(dev->dev_private);
bb4cdd53 10663
43694d69 10664 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10665}
10666
79e53945
JB		 10667static void intel_crtc_destroy(struct drm_crtc *crtc)
10668{
10669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10670 struct drm_device *dev = crtc->dev;
10671 struct intel_unpin_work *work;
67e77c5a 10672
5e2d7afc 10673 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10674 work = intel_crtc->unpin_work;
10675 intel_crtc->unpin_work = NULL;
5e2d7afc 10676 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10677
10678 if (work) {
10679 cancel_work_sync(&work->work);
10680 kfree(work);
10681 }
79e53945
JB		 10682
10683 drm_crtc_cleanup(crtc);
67e77c5a 10684
79e53945
JB		 10685 kfree(intel_crtc);
10686}
10687
6b95a207
KH		 10688static void intel_unpin_work_fn(struct work_struct *__work)
10689{
10690 struct intel_unpin_work *work =
10691 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10692 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10693 struct drm_device *dev = crtc->base.dev;
7733b49b 10694 struct drm_i915_private *dev_priv = dev->dev_private;
a9ff8714 10695 struct drm_plane *primary = crtc->base.primary;
6b95a207 10696
b4a98e57 10697 mutex_lock(&dev->struct_mutex);
a9ff8714 10698 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10699 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10700
7733b49b 10701 intel_fbc_update(dev_priv);
f06cc1b9
JH		 10702
10703 if (work->flip_queued_req)
146d84f0 10704 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10705 mutex_unlock(&dev->struct_mutex);
10706
a9ff8714 10707 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10708 drm_framebuffer_unreference(work->old_fb);
f99d7069 10709
a9ff8714
VS		 10710 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10711 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10712
6b95a207
KH		 10713 kfree(work);
10714}
10715
1afe3e9d 10716static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10717 struct drm_crtc *crtc)
6b95a207 10718{
6b95a207
KH		 10719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10720 struct intel_unpin_work *work;
6b95a207
KH		 10721 unsigned long flags;
10722
10723 /* Ignore early vblank irqs */
10724 if (intel_crtc == NULL)
10725 return;
10726
f326038a
DV		 10727 /*
10728 * This is called both by irq handlers and the reset code (to complete
10729 * lost pageflips) so needs the full irqsave spinlocks.
10730 */
6b95a207
KH		 10731 spin_lock_irqsave(&dev->event_lock, flags);
10732 work = intel_crtc->unpin_work;
e7d841ca
CW		 10733
10734 /* Ensure we don't miss a work->pending update ... */
10735 smp_rmb();
10736
10737 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10738 spin_unlock_irqrestore(&dev->event_lock, flags);
10739 return;
10740 }
10741
d6bbafa1 10742 page_flip_completed(intel_crtc);
0af7e4df 10743
6b95a207 10744 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10745}
10746
1afe3e9d
JB		 10747void intel_finish_page_flip(struct drm_device *dev, int pipe)
10748{
fbee40df 10749 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10750 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10751
49b14a5c 10752 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10753}
10754
10755void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10756{
fbee40df 10757 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10758 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10759
49b14a5c 10760 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10761}
10762
75f7f3ec
VS		 10763/* Is 'a' after or equal to 'b'? */
10764static bool g4x_flip_count_after_eq(u32 a, u32 b)
10765{
10766 return !((a - b) & 0x80000000);
10767}
10768
10769static bool page_flip_finished(struct intel_crtc *crtc)
10770{
10771 struct drm_device *dev = crtc->base.dev;
10772 struct drm_i915_private *dev_priv = dev->dev_private;
10773
bdfa7542
VS		 10774 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10775 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10776 return true;
10777
75f7f3ec
VS		 10778 /*
10779 * The relevant registers doen't exist on pre-ctg.
10780 * As the flip done interrupt doesn't trigger for mmio
10781 * flips on gmch platforms, a flip count check isn't
10782 * really needed there. But since ctg has the registers,
10783 * include it in the check anyway.
10784 */
10785 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10786 return true;
10787
10788 /*
10789 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10790 * used the same base address. In that case the mmio flip might
10791 * have completed, but the CS hasn't even executed the flip yet.
10792 *
10793 * A flip count check isn't enough as the CS might have updated
10794 * the base address just after start of vblank, but before we
10795 * managed to process the interrupt. This means we'd complete the
10796 * CS flip too soon.
10797 *
10798 * Combining both checks should get us a good enough result. It may
10799 * still happen that the CS flip has been executed, but has not
10800 * yet actually completed. But in case the base address is the same
10801 * anyway, we don't really care.
10802 */
10803 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10804 crtc->unpin_work->gtt_offset &&
10805 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10806 crtc->unpin_work->flip_count);
10807}
10808
6b95a207
KH		 10809void intel_prepare_page_flip(struct drm_device *dev, int plane)
10810{
fbee40df 10811 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10812 struct intel_crtc *intel_crtc =
10813 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10814 unsigned long flags;
10815
f326038a
DV		 10816
10817 /*
10818 * This is called both by irq handlers and the reset code (to complete
10819 * lost pageflips) so needs the full irqsave spinlocks.
10820 *
10821 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10822 * generate a page-flip completion irq, i.e. every modeset
10823 * is also accompanied by a spurious intel_prepare_page_flip().
10824 */
6b95a207 10825 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10826 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10827 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10828 spin_unlock_irqrestore(&dev->event_lock, flags);
10829}
10830
eba905b2 10831static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10832{
10833 /* Ensure that the work item is consistent when activating it ... */
10834 smp_wmb();
10835 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10836 /* and that it is marked active as soon as the irq could fire. */
10837 smp_wmb();
10838}
10839
8c9f3aaf
JB		 10840static int intel_gen2_queue_flip(struct drm_device *dev,
10841 struct drm_crtc *crtc,
10842 struct drm_framebuffer *fb,
ed8d1975 10843 struct drm_i915_gem_object *obj,
6258fbe2 10844 struct drm_i915_gem_request *req,
ed8d1975 10845 uint32_t flags)
8c9f3aaf 10846{
6258fbe2 10847 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10849 u32 flip_mask;
10850 int ret;
10851
5fb9de1a 10852 ret = intel_ring_begin(req, 6);
8c9f3aaf 10853 if (ret)
4fa62c89 10854 return ret;
8c9f3aaf
JB		 10855
10856 /* Can't queue multiple flips, so wait for the previous
10857 * one to finish before executing the next.
10858 */
10859 if (intel_crtc->plane)
10860 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10861 else
10862 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10863 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10864 intel_ring_emit(ring, MI_NOOP);
10865 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10866 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10867 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10868 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10869 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10870
10871 intel_mark_page_flip_active(intel_crtc);
83d4092b 10872 return 0;
8c9f3aaf
JB		 10873}
10874
10875static int intel_gen3_queue_flip(struct drm_device *dev,
10876 struct drm_crtc *crtc,
10877 struct drm_framebuffer *fb,
ed8d1975 10878 struct drm_i915_gem_object *obj,
6258fbe2 10879 struct drm_i915_gem_request *req,
ed8d1975 10880 uint32_t flags)
8c9f3aaf 10881{
6258fbe2 10882 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10884 u32 flip_mask;
10885 int ret;
10886
5fb9de1a 10887 ret = intel_ring_begin(req, 6);
8c9f3aaf 10888 if (ret)
4fa62c89 10889 return ret;
8c9f3aaf
JB		 10890
10891 if (intel_crtc->plane)
10892 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10893 else
10894 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10895 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10896 intel_ring_emit(ring, MI_NOOP);
10897 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10898 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10899 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10900 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10901 intel_ring_emit(ring, MI_NOOP);
10902
e7d841ca 10903 intel_mark_page_flip_active(intel_crtc);
83d4092b 10904 return 0;
8c9f3aaf
JB		 10905}
10906
10907static int intel_gen4_queue_flip(struct drm_device *dev,
10908 struct drm_crtc *crtc,
10909 struct drm_framebuffer *fb,
ed8d1975 10910 struct drm_i915_gem_object *obj,
6258fbe2 10911 struct drm_i915_gem_request *req,
ed8d1975 10912 uint32_t flags)
8c9f3aaf 10913{
6258fbe2 10914 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10915 struct drm_i915_private *dev_priv = dev->dev_private;
10916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10917 uint32_t pf, pipesrc;
10918 int ret;
10919
5fb9de1a 10920 ret = intel_ring_begin(req, 4);
8c9f3aaf 10921 if (ret)
4fa62c89 10922 return ret;
8c9f3aaf
JB		 10923
10924 /* i965+ uses the linear or tiled offsets from the
10925 * Display Registers (which do not change across a page-flip)
10926 * so we need only reprogram the base address.
10927 */
6d90c952
DV		 10928 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10929 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10930 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10931 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10932 obj->tiling_mode);
8c9f3aaf
JB		 10933
10934 /* XXX Enabling the panel-fitter across page-flip is so far
10935 * untested on non-native modes, so ignore it for now.
10936 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10937 */
10938 pf = 0;
10939 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10940 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10941
10942 intel_mark_page_flip_active(intel_crtc);
83d4092b 10943 return 0;
8c9f3aaf
JB		 10944}
10945
10946static int intel_gen6_queue_flip(struct drm_device *dev,
10947 struct drm_crtc *crtc,
10948 struct drm_framebuffer *fb,
ed8d1975 10949 struct drm_i915_gem_object *obj,
6258fbe2 10950 struct drm_i915_gem_request *req,
ed8d1975 10951 uint32_t flags)
8c9f3aaf 10952{
6258fbe2 10953 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10954 struct drm_i915_private *dev_priv = dev->dev_private;
10955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10956 uint32_t pf, pipesrc;
10957 int ret;
10958
5fb9de1a 10959 ret = intel_ring_begin(req, 4);
8c9f3aaf 10960 if (ret)
4fa62c89 10961 return ret;
8c9f3aaf 10962
6d90c952
DV		 10963 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10964 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10965 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10966 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10967
dc257cf1
DV		 10968 /* Contrary to the suggestions in the documentation,
10969 * "Enable Panel Fitter" does not seem to be required when page
10970 * flipping with a non-native mode, and worse causes a normal
10971 * modeset to fail.
10972 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10973 */
10974 pf = 0;
8c9f3aaf 10975 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10976 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10977
10978 intel_mark_page_flip_active(intel_crtc);
83d4092b 10979 return 0;
8c9f3aaf
JB		 10980}
10981
7c9017e5
JB		 10982static int intel_gen7_queue_flip(struct drm_device *dev,
10983 struct drm_crtc *crtc,
10984 struct drm_framebuffer *fb,
ed8d1975 10985 struct drm_i915_gem_object *obj,
6258fbe2 10986 struct drm_i915_gem_request *req,
ed8d1975 10987 uint32_t flags)
7c9017e5 10988{
6258fbe2 10989 struct intel_engine_cs *ring = req->ring;
7c9017e5 10990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10991 uint32_t plane_bit = 0;
ffe74d75
CW		 10992 int len, ret;
10993
eba905b2 10994 switch (intel_crtc->plane) {
cb05d8de
DV		 10995 case PLANE_A:
10996 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10997 break;
10998 case PLANE_B:
10999 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11000 break;
11001 case PLANE_C:
11002 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11003 break;
11004 default:
11005 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11006 return -ENODEV;
cb05d8de
DV		 11007 }
11008
ffe74d75 11009 len = 4;
f476828a 11010 if (ring->id == RCS) {
ffe74d75 11011 len += 6;
f476828a
DL		 11012 /*
11013 * On Gen 8, SRM is now taking an extra dword to accommodate
11014 * 48bits addresses, and we need a NOOP for the batch size to
11015 * stay even.
11016 */
11017 if (IS_GEN8(dev))
11018 len += 2;
11019 }
ffe74d75 11020
f66fab8e
VS		 11021 /*
11022 * BSpec MI_DISPLAY_FLIP for IVB:
11023 * "The full packet must be contained within the same cache line."
11024 *
11025 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11026 * cacheline, if we ever start emitting more commands before
11027 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11028 * then do the cacheline alignment, and finally emit the
11029 * MI_DISPLAY_FLIP.
11030 */
bba09b12 11031 ret = intel_ring_cacheline_align(req);
f66fab8e 11032 if (ret)
4fa62c89 11033 return ret;
f66fab8e 11034
5fb9de1a 11035 ret = intel_ring_begin(req, len);
7c9017e5 11036 if (ret)
4fa62c89 11037 return ret;
7c9017e5 11038
ffe74d75
CW		 11039 /* Unmask the flip-done completion message. Note that the bspec says that
11040 * we should do this for both the BCS and RCS, and that we must not unmask
11041 * more than one flip event at any time (or ensure that one flip message
11042 * can be sent by waiting for flip-done prior to queueing new flips).
11043 * Experimentation says that BCS works despite DERRMR masking all
11044 * flip-done completion events and that unmasking all planes at once
11045 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11046 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11047 */
11048 if (ring->id == RCS) {
11049 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11050 intel_ring_emit(ring, DERRMR);
11051 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11052 DERRMR_PIPEB_PRI_FLIP_DONE |
11053 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11054 if (IS_GEN8(dev))
11055 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11056 MI_SRM_LRM_GLOBAL_GTT);
11057 else
11058 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11059 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11060 intel_ring_emit(ring, DERRMR);
11061 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11062 if (IS_GEN8(dev)) {
11063 intel_ring_emit(ring, 0);
11064 intel_ring_emit(ring, MI_NOOP);
11065 }
ffe74d75
CW		 11066 }
11067
cb05d8de 11068 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11069 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11070 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11071 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11072
11073 intel_mark_page_flip_active(intel_crtc);
83d4092b 11074 return 0;
7c9017e5
JB		 11075}
11076
84c33a64
SG		 11077static bool use_mmio_flip(struct intel_engine_cs *ring,
11078 struct drm_i915_gem_object *obj)
11079{
11080 /*
11081 * This is not being used for older platforms, because
11082 * non-availability of flip done interrupt forces us to use
11083 * CS flips. Older platforms derive flip done using some clever
11084 * tricks involving the flip_pending status bits and vblank irqs.
11085 * So using MMIO flips there would disrupt this mechanism.
11086 */
11087
8e09bf83
CW		 11088 if (ring == NULL)
11089 return true;
11090
84c33a64
SG		 11091 if (INTEL_INFO(ring->dev)->gen < 5)
11092 return false;
11093
11094 if (i915.use_mmio_flip < 0)
11095 return false;
11096 else if (i915.use_mmio_flip > 0)
11097 return true;
14bf993e
OM		 11098 else if (i915.enable_execlists)
11099 return true;
84c33a64 11100 else
b4716185 11101 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11102}
11103
ff944564
DL		 11104static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11105{
11106 struct drm_device *dev = intel_crtc->base.dev;
11107 struct drm_i915_private *dev_priv = dev->dev_private;
11108 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11109 const enum pipe pipe = intel_crtc->pipe;
11110 u32 ctl, stride;
11111
11112 ctl = I915_READ(PLANE_CTL(pipe, 0));
11113 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11114 switch (fb->modifier[0]) {
11115 case DRM_FORMAT_MOD_NONE:
11116 break;
11117 case I915_FORMAT_MOD_X_TILED:
ff944564 11118 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11119 break;
11120 case I915_FORMAT_MOD_Y_TILED:
11121 ctl |= PLANE_CTL_TILED_Y;
11122 break;
11123 case I915_FORMAT_MOD_Yf_TILED:
11124 ctl |= PLANE_CTL_TILED_YF;
11125 break;
11126 default:
11127 MISSING_CASE(fb->modifier[0]);
11128 }
ff944564
DL		 11129
11130 /*
11131 * The stride is either expressed as a multiple of 64 bytes chunks for
11132 * linear buffers or in number of tiles for tiled buffers.
11133 */
2ebef630
TU		 11134 stride = fb->pitches[0] /
11135 intel_fb_stride_alignment(dev, fb->modifier[0],
11136 fb->pixel_format);
ff944564
DL		 11137
11138 /*
11139 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11140 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11141 */
11142 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11143 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11144
11145 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11146 POSTING_READ(PLANE_SURF(pipe, 0));
11147}
11148
11149static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11150{
11151 struct drm_device *dev = intel_crtc->base.dev;
11152 struct drm_i915_private *dev_priv = dev->dev_private;
11153 struct intel_framebuffer *intel_fb =
11154 to_intel_framebuffer(intel_crtc->base.primary->fb);
11155 struct drm_i915_gem_object *obj = intel_fb->obj;
11156 u32 dspcntr;
11157 u32 reg;
11158
84c33a64
SG		 11159 reg = DSPCNTR(intel_crtc->plane);
11160 dspcntr = I915_READ(reg);
11161
c5d97472
DL		 11162 if (obj->tiling_mode != I915_TILING_NONE)
11163 dspcntr |= DISPPLANE_TILED;
11164 else
11165 dspcntr &= ~DISPPLANE_TILED;
11166
84c33a64
SG		 11167 I915_WRITE(reg, dspcntr);
11168
11169 I915_WRITE(DSPSURF(intel_crtc->plane),
11170 intel_crtc->unpin_work->gtt_offset);
11171 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11172
ff944564
DL		 11173}
11174
11175/*
11176 * XXX: This is the temporary way to update the plane registers until we get
11177 * around to using the usual plane update functions for MMIO flips
11178 */
11179static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11180{
11181 struct drm_device *dev = intel_crtc->base.dev;
11182 bool atomic_update;
11183 u32 start_vbl_count;
11184
11185 intel_mark_page_flip_active(intel_crtc);
11186
11187 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11188
11189 if (INTEL_INFO(dev)->gen >= 9)
11190 skl_do_mmio_flip(intel_crtc);
11191 else
11192 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11193 ilk_do_mmio_flip(intel_crtc);
11194
9362c7c5
ACO		 11195 if (atomic_update)
11196 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11197}
11198
9362c7c5 11199static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11200{
b2cfe0ab
CW		 11201 struct intel_mmio_flip *mmio_flip =
11202 container_of(work, struct intel_mmio_flip, work);
84c33a64 11203
eed29a5b
DV		 11204 if (mmio_flip->req)
11205 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11206 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11207 false, NULL,
11208 &mmio_flip->i915->rps.mmioflips));
84c33a64 11209
b2cfe0ab
CW		 11210 intel_do_mmio_flip(mmio_flip->crtc);
11211
eed29a5b 11212 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11213 kfree(mmio_flip);
84c33a64
SG		 11214}
11215
11216static int intel_queue_mmio_flip(struct drm_device *dev,
11217 struct drm_crtc *crtc,
11218 struct drm_framebuffer *fb,
11219 struct drm_i915_gem_object *obj,
11220 struct intel_engine_cs *ring,
11221 uint32_t flags)
11222{
b2cfe0ab
CW		 11223 struct intel_mmio_flip *mmio_flip;
11224
11225 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11226 if (mmio_flip == NULL)
11227 return -ENOMEM;
84c33a64 11228
bcafc4e3 11229 mmio_flip->i915 = to_i915(dev);
eed29a5b 11230 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11231 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11232
b2cfe0ab
CW		 11233 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11234 schedule_work(&mmio_flip->work);
84c33a64 11235
84c33a64
SG		 11236 return 0;
11237}
11238
8c9f3aaf
JB		 11239static int intel_default_queue_flip(struct drm_device *dev,
11240 struct drm_crtc *crtc,
11241 struct drm_framebuffer *fb,
ed8d1975 11242 struct drm_i915_gem_object *obj,
6258fbe2 11243 struct drm_i915_gem_request *req,
ed8d1975 11244 uint32_t flags)
8c9f3aaf
JB		 11245{
11246 return -ENODEV;
11247}
11248
d6bbafa1
CW		 11249static bool __intel_pageflip_stall_check(struct drm_device *dev,
11250 struct drm_crtc *crtc)
11251{
11252 struct drm_i915_private *dev_priv = dev->dev_private;
11253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11254 struct intel_unpin_work *work = intel_crtc->unpin_work;
11255 u32 addr;
11256
11257 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11258 return true;
11259
11260 if (!work->enable_stall_check)
11261 return false;
11262
11263 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11264 if (work->flip_queued_req &&
11265 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11266 return false;
11267
1e3feefd 11268 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11269 }
11270
1e3feefd 11271 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11272 return false;
11273
11274 /* Potential stall - if we see that the flip has happened,
11275 * assume a missed interrupt. */
11276 if (INTEL_INFO(dev)->gen >= 4)
11277 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11278 else
11279 addr = I915_READ(DSPADDR(intel_crtc->plane));
11280
11281 /* There is a potential issue here with a false positive after a flip
11282 * to the same address. We could address this by checking for a
11283 * non-incrementing frame counter.
11284 */
11285 return addr == work->gtt_offset;
11286}
11287
11288void intel_check_page_flip(struct drm_device *dev, int pipe)
11289{
11290 struct drm_i915_private *dev_priv = dev->dev_private;
11291 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11293 struct intel_unpin_work *work;
f326038a 11294
6c51d46f 11295 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11296
11297 if (crtc == NULL)
11298 return;
11299
f326038a 11300 spin_lock(&dev->event_lock);
6ad790c0
CW		 11301 work = intel_crtc->unpin_work;
11302 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11303 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11304 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11305 page_flip_completed(intel_crtc);
6ad790c0 11306 work = NULL;
d6bbafa1 11307 }
6ad790c0
CW		 11308 if (work != NULL &&
11309 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11310 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11311 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11312}
11313
6b95a207
KH		 11314static int intel_crtc_page_flip(struct drm_crtc *crtc,
11315 struct drm_framebuffer *fb,
ed8d1975
KP		 11316 struct drm_pending_vblank_event *event,
11317 uint32_t page_flip_flags)
6b95a207
KH		 11318{
11319 struct drm_device *dev = crtc->dev;
11320 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11321 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11322 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11324 struct drm_plane *primary = crtc->primary;
a071fa00 11325 enum pipe pipe = intel_crtc->pipe;
6b95a207 11326 struct intel_unpin_work *work;
a4872ba6 11327 struct intel_engine_cs *ring;
cf5d8a46 11328 bool mmio_flip;
91af127f 11329 struct drm_i915_gem_request *request = NULL;
52e68630 11330 int ret;
6b95a207 11331
2ff8fde1
MR		 11332 /*
11333 * drm_mode_page_flip_ioctl() should already catch this, but double
11334 * check to be safe. In the future we may enable pageflipping from
11335 * a disabled primary plane.
11336 */
11337 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11338 return -EBUSY;
11339
e6a595d2 11340 /* Can't change pixel format via MI display flips. */
f4510a27 11341 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11342 return -EINVAL;
11343
11344 /*
11345 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11346 * Note that pitch changes could also affect these register.
11347 */
11348 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11349 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11350 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11351 return -EINVAL;
11352
f900db47
CW		 11353 if (i915_terminally_wedged(&dev_priv->gpu_error))
11354 goto out_hang;
11355
b14c5679 11356 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11357 if (work == NULL)
11358 return -ENOMEM;
11359
6b95a207 11360 work->event = event;
b4a98e57 11361 work->crtc = crtc;
ab8d6675 11362 work->old_fb = old_fb;
6b95a207
KH		 11363 INIT_WORK(&work->work, intel_unpin_work_fn);
11364
87b6b101 11365 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11366 if (ret)
11367 goto free_work;
11368
6b95a207 11369 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11370 spin_lock_irq(&dev->event_lock);
6b95a207 11371 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11372 /* Before declaring the flip queue wedged, check if
11373 * the hardware completed the operation behind our backs.
11374 */
11375 if (__intel_pageflip_stall_check(dev, crtc)) {
11376 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11377 page_flip_completed(intel_crtc);
11378 } else {
11379 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11380 spin_unlock_irq(&dev->event_lock);
468f0b44 11381
d6bbafa1
CW		 11382 drm_crtc_vblank_put(crtc);
11383 kfree(work);
11384 return -EBUSY;
11385 }
6b95a207
KH		 11386 }
11387 intel_crtc->unpin_work = work;
5e2d7afc 11388 spin_unlock_irq(&dev->event_lock);
6b95a207 11389
b4a98e57
CW		 11390 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11391 flush_workqueue(dev_priv->wq);
11392
75dfca80 11393 /* Reference the objects for the scheduled work. */
ab8d6675 11394 drm_framebuffer_reference(work->old_fb);
05394f39 11395 drm_gem_object_reference(&obj->base);
6b95a207 11396
f4510a27 11397 crtc->primary->fb = fb;
afd65eb4 11398 update_state_fb(crtc->primary);
1ed1f968 11399
e1f99ce6 11400 work->pending_flip_obj = obj;
e1f99ce6 11401
89ed88ba
CW		 11402 ret = i915_mutex_lock_interruptible(dev);
11403 if (ret)
11404 goto cleanup;
11405
b4a98e57 11406 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11407 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11408
75f7f3ec 11409 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11410 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11411
4fa62c89
VS		 11412 if (IS_VALLEYVIEW(dev)) {
11413 ring = &dev_priv->ring[BCS];
ab8d6675 11414 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11415 /* vlv: DISPLAY_FLIP fails to change tiling */
11416 ring = NULL;
48bf5b2d 11417 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11418 ring = &dev_priv->ring[BCS];
4fa62c89 11419 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11420 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11421 if (ring == NULL || ring->id != RCS)
11422 ring = &dev_priv->ring[BCS];
11423 } else {
11424 ring = &dev_priv->ring[RCS];
11425 }
11426
cf5d8a46
CW		 11427 mmio_flip = use_mmio_flip(ring, obj);
11428
11429 /* When using CS flips, we want to emit semaphores between rings.
11430 * However, when using mmio flips we will create a task to do the
11431 * synchronisation, so all we want here is to pin the framebuffer
11432 * into the display plane and skip any waits.
11433 */
82bc3b2d 11434 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11435 crtc->primary->state,
91af127f 11436 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11437 if (ret)
11438 goto cleanup_pending;
6b95a207 11439
121920fa
TU		 11440 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11441 + intel_crtc->dspaddr_offset;
4fa62c89 11442
cf5d8a46 11443 if (mmio_flip) {
84c33a64
SG		 11444 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11445 page_flip_flags);
d6bbafa1
CW		 11446 if (ret)
11447 goto cleanup_unpin;
11448
f06cc1b9
JH		 11449 i915_gem_request_assign(&work->flip_queued_req,
11450 obj->last_write_req);
d6bbafa1 11451 } else {
6258fbe2
JH		 11452 if (!request) {
11453 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11454 if (ret)
11455 goto cleanup_unpin;
11456 }
11457
11458 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11459 page_flip_flags);
11460 if (ret)
11461 goto cleanup_unpin;
11462
6258fbe2 11463 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11464 }
11465
91af127f 11466 if (request)
75289874 11467 i915_add_request_no_flush(request);
91af127f 11468
1e3feefd 11469 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11470 work->enable_stall_check = true;
4fa62c89 11471
ab8d6675 11472 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11473 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11474 mutex_unlock(&dev->struct_mutex);
a071fa00 11475
7733b49b 11476 intel_fbc_disable(dev_priv);
a9ff8714
VS		 11477 intel_frontbuffer_flip_prepare(dev,
11478 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11479
e5510fac
JB		 11480 trace_i915_flip_request(intel_crtc->plane, obj);
11481
6b95a207 11482 return 0;
96b099fd 11483
4fa62c89 11484cleanup_unpin:
82bc3b2d 11485 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11486cleanup_pending:
91af127f
JH		 11487 if (request)
11488 i915_gem_request_cancel(request);
b4a98e57 11489 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11490 mutex_unlock(&dev->struct_mutex);
11491cleanup:
f4510a27 11492 crtc->primary->fb = old_fb;
afd65eb4 11493 update_state_fb(crtc->primary);
89ed88ba
CW		 11494
11495 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11496 drm_framebuffer_unreference(work->old_fb);
96b099fd 11497
5e2d7afc 11498 spin_lock_irq(&dev->event_lock);
96b099fd 11499 intel_crtc->unpin_work = NULL;
5e2d7afc 11500 spin_unlock_irq(&dev->event_lock);
96b099fd 11501
87b6b101 11502 drm_crtc_vblank_put(crtc);
7317c75e 11503free_work:
96b099fd
CW		 11504 kfree(work);
11505
f900db47 11506 if (ret == -EIO) {
02e0efb5
ML		 11507 struct drm_atomic_state *state;
11508 struct drm_plane_state *plane_state;
11509
f900db47 11510out_hang:
02e0efb5
ML		 11511 state = drm_atomic_state_alloc(dev);
11512 if (!state)
11513 return -ENOMEM;
11514 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11515
11516retry:
11517 plane_state = drm_atomic_get_plane_state(state, primary);
11518 ret = PTR_ERR_OR_ZERO(plane_state);
11519 if (!ret) {
11520 drm_atomic_set_fb_for_plane(plane_state, fb);
11521
11522 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11523 if (!ret)
11524 ret = drm_atomic_commit(state);
11525 }
11526
11527 if (ret == -EDEADLK) {
11528 drm_modeset_backoff(state->acquire_ctx);
11529 drm_atomic_state_clear(state);
11530 goto retry;
11531 }
11532
11533 if (ret)
11534 drm_atomic_state_free(state);
11535
f0d3dad3 11536 if (ret == 0 && event) {
5e2d7afc 11537 spin_lock_irq(&dev->event_lock);
a071fa00 11538 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11539 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11540 }
f900db47 11541 }
96b099fd 11542 return ret;
6b95a207
KH		 11543}
11544
da20eabd
ML		 11545
11546/**
11547 * intel_wm_need_update - Check whether watermarks need updating
11548 * @plane: drm plane
11549 * @state: new plane state
11550 *
11551 * Check current plane state versus the new one to determine whether
11552 * watermarks need to be recalculated.
11553 *
11554 * Returns true or false.
11555 */
11556static bool intel_wm_need_update(struct drm_plane *plane,
11557 struct drm_plane_state *state)
11558{
11559 /* Update watermarks on tiling changes. */
11560 if (!plane->state->fb || !state->fb ||
11561 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11562 plane->state->rotation != state->rotation)
11563 return true;
11564
11565 if (plane->state->crtc_w != state->crtc_w)
11566 return true;
11567
11568 return false;
11569}
11570
11571int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11572 struct drm_plane_state *plane_state)
11573{
11574 struct drm_crtc *crtc = crtc_state->crtc;
11575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11576 struct drm_plane *plane = plane_state->plane;
11577 struct drm_device *dev = crtc->dev;
11578 struct drm_i915_private *dev_priv = dev->dev_private;
11579 struct intel_plane_state *old_plane_state =
11580 to_intel_plane_state(plane->state);
11581 int idx = intel_crtc->base.base.id, ret;
11582 int i = drm_plane_index(plane);
11583 bool mode_changed = needs_modeset(crtc_state);
11584 bool was_crtc_enabled = crtc->state->active;
11585 bool is_crtc_enabled = crtc_state->active;
11586
11587 bool turn_off, turn_on, visible, was_visible;
11588 struct drm_framebuffer *fb = plane_state->fb;
11589
11590 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11591 plane->type != DRM_PLANE_TYPE_CURSOR) {
11592 ret = skl_update_scaler_plane(
11593 to_intel_crtc_state(crtc_state),
11594 to_intel_plane_state(plane_state));
11595 if (ret)
11596 return ret;
11597 }
11598
11599 /*
11600 * Disabling a plane is always okay; we just need to update
11601 * fb tracking in a special way since cleanup_fb() won't
11602 * get called by the plane helpers.
11603 */
11604 if (old_plane_state->base.fb && !fb)
11605 intel_crtc->atomic.disabled_planes |= 1 << i;
11606
da20eabd
ML		 11607 was_visible = old_plane_state->visible;
11608 visible = to_intel_plane_state(plane_state)->visible;
11609
11610 if (!was_crtc_enabled && WARN_ON(was_visible))
11611 was_visible = false;
11612
11613 if (!is_crtc_enabled && WARN_ON(visible))
11614 visible = false;
11615
11616 if (!was_visible && !visible)
11617 return 0;
11618
11619 turn_off = was_visible && (!visible || mode_changed);
11620 turn_on = visible && (!was_visible || mode_changed);
11621
11622 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11623 plane->base.id, fb ? fb->base.id : -1);
11624
11625 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11626 plane->base.id, was_visible, visible,
11627 turn_off, turn_on, mode_changed);
11628
852eb00d 11629 if (turn_on) {
f015c551 11630 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11631 /* must disable cxsr around plane enable/disable */
11632 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11633 intel_crtc->atomic.disable_cxsr = true;
11634 /* to potentially re-enable cxsr */
11635 intel_crtc->atomic.wait_vblank = true;
11636 intel_crtc->atomic.update_wm_post = true;
11637 }
11638 } else if (turn_off) {
f015c551 11639 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11640 /* must disable cxsr around plane enable/disable */
11641 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11642 if (is_crtc_enabled)
11643 intel_crtc->atomic.wait_vblank = true;
11644 intel_crtc->atomic.disable_cxsr = true;
11645 }
11646 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11647 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11648 }
da20eabd 11649
a9ff8714
VS		 11650 if (visible)
11651 intel_crtc->atomic.fb_bits |=
11652 to_intel_plane(plane)->frontbuffer_bit;
11653
da20eabd
ML		 11654 switch (plane->type) {
11655 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11656 intel_crtc->atomic.wait_for_flips = true;
11657 intel_crtc->atomic.pre_disable_primary = turn_off;
11658 intel_crtc->atomic.post_enable_primary = turn_on;
11659
066cf55b
RV		 11660 if (turn_off) {
11661 /*
11662 * FIXME: Actually if we will still have any other
11663 * plane enabled on the pipe we could let IPS enabled
11664 * still, but for now lets consider that when we make
11665 * primary invisible by setting DSPCNTR to 0 on
11666 * update_primary_plane function IPS needs to be
11667 * disable.
11668 */
11669 intel_crtc->atomic.disable_ips = true;
11670
da20eabd 11671 intel_crtc->atomic.disable_fbc = true;
066cf55b 11672 }
da20eabd
ML		 11673
11674 /*
11675 * FBC does not work on some platforms for rotated
11676 * planes, so disable it when rotation is not 0 and
11677 * update it when rotation is set back to 0.
11678 *
11679 * FIXME: This is redundant with the fbc update done in
11680 * the primary plane enable function except that that
11681 * one is done too late. We eventually need to unify
11682 * this.
11683 */
11684
11685 if (visible &&
11686 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11687 dev_priv->fbc.crtc == intel_crtc &&
11688 plane_state->rotation != BIT(DRM_ROTATE_0))
11689 intel_crtc->atomic.disable_fbc = true;
11690
11691 /*
11692 * BDW signals flip done immediately if the plane
11693 * is disabled, even if the plane enable is already
11694 * armed to occur at the next vblank :(
11695 */
11696 if (turn_on && IS_BROADWELL(dev))
11697 intel_crtc->atomic.wait_vblank = true;
11698
11699 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11700 break;
11701 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11702 break;
11703 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11704 if (turn_off && !mode_changed) {
da20eabd
ML		 11705 intel_crtc->atomic.wait_vblank = true;
11706 intel_crtc->atomic.update_sprite_watermarks |=
11707 1 << i;
11708 }
da20eabd
ML		 11709 }
11710 return 0;
11711}
11712
6d3a1ce7
ML		 11713static bool encoders_cloneable(const struct intel_encoder *a,
11714 const struct intel_encoder *b)
11715{
11716 /* masks could be asymmetric, so check both ways */
11717 return a == b || (a->cloneable & (1 << b->type) &&
11718 b->cloneable & (1 << a->type));
11719}
11720
11721static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11722 struct intel_crtc *crtc,
11723 struct intel_encoder *encoder)
11724{
11725 struct intel_encoder *source_encoder;
11726 struct drm_connector *connector;
11727 struct drm_connector_state *connector_state;
11728 int i;
11729
11730 for_each_connector_in_state(state, connector, connector_state, i) {
11731 if (connector_state->crtc != &crtc->base)
11732 continue;
11733
11734 source_encoder =
11735 to_intel_encoder(connector_state->best_encoder);
11736 if (!encoders_cloneable(encoder, source_encoder))
11737 return false;
11738 }
11739
11740 return true;
11741}
11742
11743static bool check_encoder_cloning(struct drm_atomic_state *state,
11744 struct intel_crtc *crtc)
11745{
11746 struct intel_encoder *encoder;
11747 struct drm_connector *connector;
11748 struct drm_connector_state *connector_state;
11749 int i;
11750
11751 for_each_connector_in_state(state, connector, connector_state, i) {
11752 if (connector_state->crtc != &crtc->base)
11753 continue;
11754
11755 encoder = to_intel_encoder(connector_state->best_encoder);
11756 if (!check_single_encoder_cloning(state, crtc, encoder))
11757 return false;
11758 }
11759
11760 return true;
11761}
11762
d032ffa0
ML		 11763static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11764 struct drm_crtc_state *crtc_state)
11765{
11766 struct intel_crtc_state *pipe_config =
11767 to_intel_crtc_state(crtc_state);
11768 struct drm_plane *p;
11769 unsigned visible_mask = 0;
11770
11771 drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11772 struct drm_plane_state *plane_state =
11773 drm_atomic_get_existing_plane_state(crtc_state->state, p);
11774
11775 if (WARN_ON(!plane_state))
11776 continue;
11777
11778 if (!plane_state->fb)
11779 crtc_state->plane_mask &=
11780 ~(1 << drm_plane_index(p));
11781 else if (to_intel_plane_state(plane_state)->visible)
11782 visible_mask |= 1 << drm_plane_index(p);
11783 }
11784
11785 if (!visible_mask)
11786 return;
11787
11788 pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11789}
11790
6d3a1ce7
ML		 11791static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11792 struct drm_crtc_state *crtc_state)
11793{
cf5a15be 11794 struct drm_device *dev = crtc->dev;
ad421372 11795 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11797 struct intel_crtc_state *pipe_config =
11798 to_intel_crtc_state(crtc_state);
6d3a1ce7 11799 struct drm_atomic_state *state = crtc_state->state;
ad421372 11800 int ret, idx = crtc->base.id;
6d3a1ce7
ML		 11801 bool mode_changed = needs_modeset(crtc_state);
11802
11803 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11804 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11805 return -EINVAL;
11806 }
11807
11808 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11809 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11810 idx, crtc->state->active, intel_crtc->active);
11811
d032ffa0
ML		 11812 /* plane mask is fixed up after all initial planes are calculated */
11813 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11814 intel_crtc_check_initial_planes(crtc, crtc_state);
11815
852eb00d
VS		 11816 if (mode_changed && !crtc_state->active)
11817 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11818
ad421372
ML		 11819 if (mode_changed && crtc_state->enable &&
11820 dev_priv->display.crtc_compute_clock &&
11821 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11822 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11823 pipe_config);
11824 if (ret)
11825 return ret;
11826 }
11827
cf5a15be 11828 return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
6d3a1ce7
ML		 11829}
11830
65b38e0d 11831static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11832 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11833 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11834 .atomic_begin = intel_begin_crtc_commit,
11835 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11836 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11837};
11838
9a935856
DV		 11839/**
11840 * intel_modeset_update_staged_output_state
11841 *
11842 * Updates the staged output configuration state, e.g. after we've read out the
11843 * current hw state.
11844 */
11845static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11846{
7668851f 11847 struct intel_crtc *crtc;
9a935856
DV		 11848 struct intel_encoder *encoder;
11849 struct intel_connector *connector;
f6e5b160 11850
3a3371ff 11851 for_each_intel_connector(dev, connector) {
9a935856
DV		 11852 connector->new_encoder =
11853 to_intel_encoder(connector->base.encoder);
11854 }
f6e5b160 11855
b2784e15 11856 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11857 encoder->new_crtc =
11858 to_intel_crtc(encoder->base.crtc);
11859 }
7668851f 11860
d3fcc808 11861 for_each_intel_crtc(dev, crtc) {
83d65738 11862 crtc->new_enabled = crtc->base.state->enable;
7668851f 11863 }
f6e5b160
CW		 11864}
11865
d29b2f9d
ACO		 11866/* Transitional helper to copy current connector/encoder state to
11867 * connector->state. This is needed so that code that is partially
11868 * converted to atomic does the right thing.
11869 */
11870static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11871{
11872 struct intel_connector *connector;
11873
11874 for_each_intel_connector(dev, connector) {
11875 if (connector->base.encoder) {
11876 connector->base.state->best_encoder =
11877 connector->base.encoder;
11878 connector->base.state->crtc =
11879 connector->base.encoder->crtc;
11880 } else {
11881 connector->base.state->best_encoder = NULL;
11882 connector->base.state->crtc = NULL;
11883 }
11884 }
11885}
11886
050f7aeb 11887static void
eba905b2 11888connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11889 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11890{
11891 int bpp = pipe_config->pipe_bpp;
11892
11893 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11894 connector->base.base.id,
c23cc417 11895 connector->base.name);
050f7aeb
DV		 11896
11897 /* Don't use an invalid EDID bpc value */
11898 if (connector->base.display_info.bpc &&
11899 connector->base.display_info.bpc * 3 < bpp) {
11900 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11901 bpp, connector->base.display_info.bpc*3);
11902 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11903 }
11904
11905 /* Clamp bpp to 8 on screens without EDID 1.4 */
11906 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11907 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11908 bpp);
11909 pipe_config->pipe_bpp = 24;
11910 }
11911}
11912
4e53c2e0 11913static int
050f7aeb 11914compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11915 struct intel_crtc_state *pipe_config)
4e53c2e0 11916{
050f7aeb 11917 struct drm_device *dev = crtc->base.dev;
1486017f 11918 struct drm_atomic_state *state;
da3ced29
ACO		 11919 struct drm_connector *connector;
11920 struct drm_connector_state *connector_state;
1486017f 11921 int bpp, i;
4e53c2e0 11922
d328c9d7 11923 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11924 bpp = 10*3;
d328c9d7
DV		 11925 else if (INTEL_INFO(dev)->gen >= 5)
11926 bpp = 12*3;
11927 else
11928 bpp = 8*3;
11929
4e53c2e0 11930
4e53c2e0
DV		 11931 pipe_config->pipe_bpp = bpp;
11932
1486017f
ACO		 11933 state = pipe_config->base.state;
11934
4e53c2e0 11935 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11936 for_each_connector_in_state(state, connector, connector_state, i) {
11937 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11938 continue;
11939
da3ced29
ACO		 11940 connected_sink_compute_bpp(to_intel_connector(connector),
11941 pipe_config);
4e53c2e0
DV		 11942 }
11943
11944 return bpp;
11945}
11946
644db711
DV		 11947static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11948{
11949 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11950 "type: 0x%x flags: 0x%x\n",
1342830c 11951 mode->crtc_clock,
644db711
DV		 11952 mode->crtc_hdisplay, mode->crtc_hsync_start,
11953 mode->crtc_hsync_end, mode->crtc_htotal,
11954 mode->crtc_vdisplay, mode->crtc_vsync_start,
11955 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11956}
11957
c0b03411 11958static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11959 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11960 const char *context)
11961{
6a60cd87
CK		 11962 struct drm_device *dev = crtc->base.dev;
11963 struct drm_plane *plane;
11964 struct intel_plane *intel_plane;
11965 struct intel_plane_state *state;
11966 struct drm_framebuffer *fb;
11967
11968 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11969 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11970
11971 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11972 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11973 pipe_config->pipe_bpp, pipe_config->dither);
11974 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11975 pipe_config->has_pch_encoder,
11976 pipe_config->fdi_lanes,
11977 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11978 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11979 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11980 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11981 pipe_config->has_dp_encoder,
11982 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11983 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11984 pipe_config->dp_m_n.tu);
b95af8be
VK		 11985
11986 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11987 pipe_config->has_dp_encoder,
11988 pipe_config->dp_m2_n2.gmch_m,
11989 pipe_config->dp_m2_n2.gmch_n,
11990 pipe_config->dp_m2_n2.link_m,
11991 pipe_config->dp_m2_n2.link_n,
11992 pipe_config->dp_m2_n2.tu);
11993
55072d19
DV		 11994 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11995 pipe_config->has_audio,
11996 pipe_config->has_infoframe);
11997
c0b03411 11998 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11999 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 12000 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 12001 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12002 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 12003 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 12004 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12005 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 12006 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12007 crtc->num_scalers,
12008 pipe_config->scaler_state.scaler_users,
12009 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 12010 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12011 pipe_config->gmch_pfit.control,
12012 pipe_config->gmch_pfit.pgm_ratios,
12013 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12014 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12015 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 12016 pipe_config->pch_pfit.size,
12017 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12018 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12019 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12020
415ff0f6 12021 if (IS_BROXTON(dev)) {
05712c15 12022 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 12023 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 12024 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 12025 pipe_config->ddi_pll_sel,
12026 pipe_config->dpll_hw_state.ebb0,
05712c15 12027 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 12028 pipe_config->dpll_hw_state.pll0,
12029 pipe_config->dpll_hw_state.pll1,
12030 pipe_config->dpll_hw_state.pll2,
12031 pipe_config->dpll_hw_state.pll3,
12032 pipe_config->dpll_hw_state.pll6,
12033 pipe_config->dpll_hw_state.pll8,
05712c15 12034 pipe_config->dpll_hw_state.pll9,
c8453338 12035 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 12036 pipe_config->dpll_hw_state.pcsdw12);
12037 } else if (IS_SKYLAKE(dev)) {
12038 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12039 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12040 pipe_config->ddi_pll_sel,
12041 pipe_config->dpll_hw_state.ctrl1,
12042 pipe_config->dpll_hw_state.cfgcr1,
12043 pipe_config->dpll_hw_state.cfgcr2);
12044 } else if (HAS_DDI(dev)) {
12045 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12046 pipe_config->ddi_pll_sel,
12047 pipe_config->dpll_hw_state.wrpll);
12048 } else {
12049 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12050 "fp0: 0x%x, fp1: 0x%x\n",
12051 pipe_config->dpll_hw_state.dpll,
12052 pipe_config->dpll_hw_state.dpll_md,
12053 pipe_config->dpll_hw_state.fp0,
12054 pipe_config->dpll_hw_state.fp1);
12055 }
12056
6a60cd87
CK		 12057 DRM_DEBUG_KMS("planes on this crtc\n");
12058 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12059 intel_plane = to_intel_plane(plane);
12060 if (intel_plane->pipe != crtc->pipe)
12061 continue;
12062
12063 state = to_intel_plane_state(plane->state);
12064 fb = state->base.fb;
12065 if (!fb) {
12066 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12067 "disabled, scaler_id = %d\n",
12068 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12069 plane->base.id, intel_plane->pipe,
12070 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12071 drm_plane_index(plane), state->scaler_id);
12072 continue;
12073 }
12074
12075 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12076 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12077 plane->base.id, intel_plane->pipe,
12078 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12079 drm_plane_index(plane));
12080 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12081 fb->base.id, fb->width, fb->height, fb->pixel_format);
12082 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12083 state->scaler_id,
12084 state->src.x1 >> 16, state->src.y1 >> 16,
12085 drm_rect_width(&state->src) >> 16,
12086 drm_rect_height(&state->src) >> 16,
12087 state->dst.x1, state->dst.y1,
12088 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12089 }
c0b03411
DV		 12090}
12091
5448a00d 12092static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12093{
5448a00d
ACO		 12094 struct drm_device *dev = state->dev;
12095 struct intel_encoder *encoder;
da3ced29 12096 struct drm_connector *connector;
5448a00d 12097 struct drm_connector_state *connector_state;
00f0b378 12098 unsigned int used_ports = 0;
5448a00d 12099 int i;
00f0b378
VS		 12100
12101 /*
12102 * Walk the connector list instead of the encoder
12103 * list to detect the problem on ddi platforms
12104 * where there's just one encoder per digital port.
12105 */
da3ced29 12106 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12107 if (!connector_state->best_encoder)
00f0b378
VS		 12108 continue;
12109
5448a00d
ACO		 12110 encoder = to_intel_encoder(connector_state->best_encoder);
12111
12112 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12113
12114 switch (encoder->type) {
12115 unsigned int port_mask;
12116 case INTEL_OUTPUT_UNKNOWN:
12117 if (WARN_ON(!HAS_DDI(dev)))
12118 break;
12119 case INTEL_OUTPUT_DISPLAYPORT:
12120 case INTEL_OUTPUT_HDMI:
12121 case INTEL_OUTPUT_EDP:
12122 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12123
12124 /* the same port mustn't appear more than once */
12125 if (used_ports & port_mask)
12126 return false;
12127
12128 used_ports |= port_mask;
12129 default:
12130 break;
12131 }
12132 }
12133
12134 return true;
12135}
12136
83a57153
ACO		 12137static void
12138clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12139{
12140 struct drm_crtc_state tmp_state;
663a3640 12141 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12142 struct intel_dpll_hw_state dpll_hw_state;
12143 enum intel_dpll_id shared_dpll;
8504c74c 12144 uint32_t ddi_pll_sel;
83a57153 12145
7546a384
ACO		 12146 /* FIXME: before the switch to atomic started, a new pipe_config was
12147 * kzalloc'd. Code that depends on any field being zero should be
12148 * fixed, so that the crtc_state can be safely duplicated. For now,
12149 * only fields that are know to not cause problems are preserved. */
12150
83a57153 12151 tmp_state = crtc_state->base;
663a3640 12152 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12153 shared_dpll = crtc_state->shared_dpll;
12154 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12155 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12156
83a57153 12157 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12158
83a57153 12159 crtc_state->base = tmp_state;
663a3640 12160 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12161 crtc_state->shared_dpll = shared_dpll;
12162 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12163 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12164}
12165
548ee15b 12166static int
b8cecdf5 12167intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12168 struct intel_crtc_state *pipe_config)
ee7b9f93 12169{
b359283a 12170 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12171 struct intel_encoder *encoder;
da3ced29 12172 struct drm_connector *connector;
0b901879 12173 struct drm_connector_state *connector_state;
d328c9d7 12174 int base_bpp, ret = -EINVAL;
0b901879 12175 int i;
e29c22c0 12176 bool retry = true;
ee7b9f93 12177
83a57153 12178 clear_intel_crtc_state(pipe_config);
7758a113 12179
e143a21c
DV		 12180 pipe_config->cpu_transcoder =
12181 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12182
2960bc9c
ID		 12183 /*
12184 * Sanitize sync polarity flags based on requested ones. If neither
12185 * positive or negative polarity is requested, treat this as meaning
12186 * negative polarity.
12187 */
2d112de7 12188 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12189 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12190 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12191
2d112de7 12192 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12193 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12194 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12195
050f7aeb
DV		 12196 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12197 * plane pixel format and any sink constraints into account. Returns the
12198 * source plane bpp so that dithering can be selected on mismatches
12199 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12200 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12201 pipe_config);
12202 if (base_bpp < 0)
4e53c2e0
DV		 12203 goto fail;
12204
e41a56be
VS		 12205 /*
12206 * Determine the real pipe dimensions. Note that stereo modes can
12207 * increase the actual pipe size due to the frame doubling and
12208 * insertion of additional space for blanks between the frame. This
12209 * is stored in the crtc timings. We use the requested mode to do this
12210 * computation to clearly distinguish it from the adjusted mode, which
12211 * can be changed by the connectors in the below retry loop.
12212 */
2d112de7 12213 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12214 &pipe_config->pipe_src_w,
12215 &pipe_config->pipe_src_h);
e41a56be 12216
e29c22c0 12217encoder_retry:
ef1b460d 12218 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12219 pipe_config->port_clock = 0;
ef1b460d 12220 pipe_config->pixel_multiplier = 1;
ff9a6750 12221
135c81b8 12222 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12223 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12224 CRTC_STEREO_DOUBLE);
135c81b8 12225
7758a113
DV		 12226 /* Pass our mode to the connectors and the CRTC to give them a chance to
12227 * adjust it according to limitations or connector properties, and also
12228 * a chance to reject the mode entirely.
47f1c6c9 12229 */
da3ced29 12230 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12231 if (connector_state->crtc != crtc)
7758a113 12232 continue;
7ae89233 12233
0b901879
ACO		 12234 encoder = to_intel_encoder(connector_state->best_encoder);
12235
efea6e8e
DV		 12236 if (!(encoder->compute_config(encoder, pipe_config))) {
12237 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12238 goto fail;
12239 }
ee7b9f93 12240 }
47f1c6c9 12241
ff9a6750
DV		 12242 /* Set default port clock if not overwritten by the encoder. Needs to be
12243 * done afterwards in case the encoder adjusts the mode. */
12244 if (!pipe_config->port_clock)
2d112de7 12245 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12246 * pipe_config->pixel_multiplier;
ff9a6750 12247
a43f6e0f 12248 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12249 if (ret < 0) {
7758a113
DV		 12250 DRM_DEBUG_KMS("CRTC fixup failed\n");
12251 goto fail;
ee7b9f93 12252 }
e29c22c0
DV		 12253
12254 if (ret == RETRY) {
12255 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12256 ret = -EINVAL;
12257 goto fail;
12258 }
12259
12260 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12261 retry = false;
12262 goto encoder_retry;
12263 }
12264
d328c9d7 12265 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12266 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12267 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12268
cdba954e
ACO		 12269 /* Check if we need to force a modeset */
12270 if (pipe_config->has_audio !=
85a96e7a 12271 to_intel_crtc_state(crtc->state)->has_audio) {
cdba954e 12272 pipe_config->base.mode_changed = true;
85a96e7a
ML		 12273 ret = drm_atomic_add_affected_planes(state, crtc);
12274 }
cdba954e
ACO		 12275
12276 /*
12277 * Note we have an issue here with infoframes: current code
12278 * only updates them on the full mode set path per hw
12279 * requirements. So here we should be checking for any
12280 * required changes and forcing a mode set.
12281 */
7758a113 12282fail:
548ee15b 12283 return ret;
ee7b9f93 12284}
47f1c6c9 12285
ea9d758d 12286static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12287{
ea9d758d 12288 struct drm_encoder *encoder;
f6e5b160 12289 struct drm_device *dev = crtc->dev;
f6e5b160 12290
ea9d758d
DV		 12291 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12292 if (encoder->crtc == crtc)
12293 return true;
12294
12295 return false;
12296}
12297
12298static void
0a9ab303 12299intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12300{
0a9ab303 12301 struct drm_device *dev = state->dev;
ea9d758d 12302 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12303 struct drm_crtc *crtc;
12304 struct drm_crtc_state *crtc_state;
ea9d758d
DV		 12305 struct drm_connector *connector;
12306
de419ab6 12307 intel_shared_dpll_commit(state);
ba41c0de 12308
b2784e15 12309 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12310 if (!intel_encoder->base.crtc)
12311 continue;
12312
69024de8
ML		 12313 crtc = intel_encoder->base.crtc;
12314 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12315 if (!crtc_state || !needs_modeset(crtc->state))
12316 continue;
ea9d758d 12317
69024de8 12318 intel_encoder->connectors_active = false;
ea9d758d
DV		 12319 }
12320
3cb480bc 12321 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
f7217905 12322 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12323
7668851f 12324 /* Double check state. */
0a9ab303
ACO		 12325 for_each_crtc(dev, crtc) {
12326 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12327
12328 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12329
12330 /* Update hwmode for vblank functions */
12331 if (crtc->state->active)
12332 crtc->hwmode = crtc->state->adjusted_mode;
12333 else
12334 crtc->hwmode.crtc_clock = 0;
ea9d758d
DV		 12335 }
12336
12337 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12338 if (!connector->encoder || !connector->encoder->crtc)
12339 continue;
12340
69024de8
ML		 12341 crtc = connector->encoder->crtc;
12342 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12343 if (!crtc_state || !needs_modeset(crtc->state))
12344 continue;
ea9d758d 12345
53d9f4e9 12346 if (crtc->state->active) {
69024de8
ML		 12347 struct drm_property *dpms_property =
12348 dev->mode_config.dpms_property;
68d34720 12349
69024de8
ML		 12350 connector->dpms = DRM_MODE_DPMS_ON;
12351 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12352
69024de8
ML		 12353 intel_encoder = to_intel_encoder(connector->encoder);
12354 intel_encoder->connectors_active = true;
12355 } else
12356 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12357 }
ea9d758d
DV		 12358}
12359
3bd26263 12360static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12361{
3bd26263 12362 int diff;
f1f644dc
JB		 12363
12364 if (clock1 == clock2)
12365 return true;
12366
12367 if (!clock1 || !clock2)
12368 return false;
12369
12370 diff = abs(clock1 - clock2);
12371
12372 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12373 return true;
12374
12375 return false;
12376}
12377
25c5b266
DV		 12378#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12379 list_for_each_entry((intel_crtc), \
12380 &(dev)->mode_config.crtc_list, \
12381 base.head) \
0973f18f 12382 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12383
0e8ffe1b 12384static bool
2fa2fe9a 12385intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12386 struct intel_crtc_state *current_config,
12387 struct intel_crtc_state *pipe_config)
0e8ffe1b 12388{
66e985c0
DV		 12389#define PIPE_CONF_CHECK_X(name) \
12390 if (current_config->name != pipe_config->name) { \
12391 DRM_ERROR("mismatch in " #name " " \
12392 "(expected 0x%08x, found 0x%08x)\n", \
12393 current_config->name, \
12394 pipe_config->name); \
12395 return false; \
12396 }
12397
08a24034
DV		 12398#define PIPE_CONF_CHECK_I(name) \
12399 if (current_config->name != pipe_config->name) { \
12400 DRM_ERROR("mismatch in " #name " " \
12401 "(expected %i, found %i)\n", \
12402 current_config->name, \
12403 pipe_config->name); \
12404 return false; \
88adfff1
DV		 12405 }
12406
b95af8be
VK		 12407/* This is required for BDW+ where there is only one set of registers for
12408 * switching between high and low RR.
12409 * This macro can be used whenever a comparison has to be made between one
12410 * hw state and multiple sw state variables.
12411 */
12412#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12413 if ((current_config->name != pipe_config->name) && \
12414 (current_config->alt_name != pipe_config->name)) { \
12415 DRM_ERROR("mismatch in " #name " " \
12416 "(expected %i or %i, found %i)\n", \
12417 current_config->name, \
12418 current_config->alt_name, \
12419 pipe_config->name); \
12420 return false; \
12421 }
12422
1bd1bd80
DV		 12423#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12424 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12425 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12426 "(expected %i, found %i)\n", \
12427 current_config->name & (mask), \
12428 pipe_config->name & (mask)); \
12429 return false; \
12430 }
12431
5e550656
VS		 12432#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12433 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12434 DRM_ERROR("mismatch in " #name " " \
12435 "(expected %i, found %i)\n", \
12436 current_config->name, \
12437 pipe_config->name); \
12438 return false; \
12439 }
12440
bb760063
DV		 12441#define PIPE_CONF_QUIRK(quirk) \
12442 ((current_config->quirks | pipe_config->quirks) & (quirk))
12443
eccb140b
DV		 12444 PIPE_CONF_CHECK_I(cpu_transcoder);
12445
08a24034
DV		 12446 PIPE_CONF_CHECK_I(has_pch_encoder);
12447 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12448 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12449 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12450 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12451 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12452 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12453
eb14cb74 12454 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12455
12456 if (INTEL_INFO(dev)->gen < 8) {
12457 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12458 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12459 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12460 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12461 PIPE_CONF_CHECK_I(dp_m_n.tu);
12462
12463 if (current_config->has_drrs) {
12464 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12465 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12466 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12467 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12468 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12469 }
12470 } else {
12471 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12472 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12473 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12474 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12475 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12476 }
eb14cb74 12477
2d112de7
ACO		 12478 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12479 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12480 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12481 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12482 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12483 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12484
2d112de7
ACO		 12485 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12486 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12487 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12488 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12489 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12490 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12491
c93f54cf 12492 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12493 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12494 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12495 IS_VALLEYVIEW(dev))
12496 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12497 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12498
9ed109a7
DV		 12499 PIPE_CONF_CHECK_I(has_audio);
12500
2d112de7 12501 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12502 DRM_MODE_FLAG_INTERLACE);
12503
bb760063 12504 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12505 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12506 DRM_MODE_FLAG_PHSYNC);
2d112de7 12507 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12508 DRM_MODE_FLAG_NHSYNC);
2d112de7 12509 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12510 DRM_MODE_FLAG_PVSYNC);
2d112de7 12511 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12512 DRM_MODE_FLAG_NVSYNC);
12513 }
045ac3b5 12514
37327abd
VS		 12515 PIPE_CONF_CHECK_I(pipe_src_w);
12516 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12517
9953599b
DV		 12518 /*
12519 * FIXME: BIOS likes to set up a cloned config with lvds+external
12520 * screen. Since we don't yet re-compute the pipe config when moving
12521 * just the lvds port away to another pipe the sw tracking won't match.
12522 *
12523 * Proper atomic modesets with recomputed global state will fix this.
12524 * Until then just don't check gmch state for inherited modes.
12525 */
12526 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12527 PIPE_CONF_CHECK_I(gmch_pfit.control);
12528 /* pfit ratios are autocomputed by the hw on gen4+ */
12529 if (INTEL_INFO(dev)->gen < 4)
12530 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12531 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12532 }
12533
fd4daa9c
CW		 12534 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12535 if (current_config->pch_pfit.enabled) {
12536 PIPE_CONF_CHECK_I(pch_pfit.pos);
12537 PIPE_CONF_CHECK_I(pch_pfit.size);
12538 }
2fa2fe9a 12539
a1b2278e
CK		 12540 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12541
e59150dc
JB		 12542 /* BDW+ don't expose a synchronous way to read the state */
12543 if (IS_HASWELL(dev))
12544 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12545
282740f7
VS		 12546 PIPE_CONF_CHECK_I(double_wide);
12547
26804afd
DV		 12548 PIPE_CONF_CHECK_X(ddi_pll_sel);
12549
c0d43d62 12550 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12551 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12552 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12553 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12554 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12555 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12556 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12557 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12558 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12559
42571aef
VS		 12560 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12561 PIPE_CONF_CHECK_I(pipe_bpp);
12562
2d112de7 12563 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12564 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12565
66e985c0 12566#undef PIPE_CONF_CHECK_X
08a24034 12567#undef PIPE_CONF_CHECK_I
b95af8be 12568#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12569#undef PIPE_CONF_CHECK_FLAGS
5e550656 12570#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12571#undef PIPE_CONF_QUIRK
88adfff1 12572
0e8ffe1b
DV		 12573 return true;
12574}
12575
08db6652
DL		 12576static void check_wm_state(struct drm_device *dev)
12577{
12578 struct drm_i915_private *dev_priv = dev->dev_private;
12579 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12580 struct intel_crtc *intel_crtc;
12581 int plane;
12582
12583 if (INTEL_INFO(dev)->gen < 9)
12584 return;
12585
12586 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12587 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12588
12589 for_each_intel_crtc(dev, intel_crtc) {
12590 struct skl_ddb_entry *hw_entry, *sw_entry;
12591 const enum pipe pipe = intel_crtc->pipe;
12592
12593 if (!intel_crtc->active)
12594 continue;
12595
12596 /* planes */
dd740780 12597 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12598 hw_entry = &hw_ddb.plane[pipe][plane];
12599 sw_entry = &sw_ddb->plane[pipe][plane];
12600
12601 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12602 continue;
12603
12604 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12605 "(expected (%u,%u), found (%u,%u))\n",
12606 pipe_name(pipe), plane + 1,
12607 sw_entry->start, sw_entry->end,
12608 hw_entry->start, hw_entry->end);
12609 }
12610
12611 /* cursor */
12612 hw_entry = &hw_ddb.cursor[pipe];
12613 sw_entry = &sw_ddb->cursor[pipe];
12614
12615 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12616 continue;
12617
12618 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12619 "(expected (%u,%u), found (%u,%u))\n",
12620 pipe_name(pipe),
12621 sw_entry->start, sw_entry->end,
12622 hw_entry->start, hw_entry->end);
12623 }
12624}
12625
91d1b4bd
DV		 12626static void
12627check_connector_state(struct drm_device *dev)
8af6cf88 12628{
8af6cf88
DV		 12629 struct intel_connector *connector;
12630
3a3371ff 12631 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12632 /* This also checks the encoder/connector hw state with the
12633 * ->get_hw_state callbacks. */
12634 intel_connector_check_state(connector);
12635
e2c719b7 12636 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12637 "connector's staged encoder doesn't match current encoder\n");
12638 }
91d1b4bd
DV		 12639}
12640
12641static void
12642check_encoder_state(struct drm_device *dev)
12643{
12644 struct intel_encoder *encoder;
12645 struct intel_connector *connector;
8af6cf88 12646
b2784e15 12647 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12648 bool enabled = false;
12649 bool active = false;
12650 enum pipe pipe, tracked_pipe;
12651
12652 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12653 encoder->base.base.id,
8e329a03 12654 encoder->base.name);
8af6cf88 12655
e2c719b7 12656 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12657 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12658 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12659 "encoder's active_connectors set, but no crtc\n");
12660
3a3371ff 12661 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12662 if (connector->base.encoder != &encoder->base)
12663 continue;
12664 enabled = true;
12665 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12666 active = true;
12667 }
0e32b39c
DA		 12668 /*
12669 * for MST connectors if we unplug the connector is gone
12670 * away but the encoder is still connected to a crtc
12671 * until a modeset happens in response to the hotplug.
12672 */
12673 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12674 continue;
12675
e2c719b7 12676 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12677 "encoder's enabled state mismatch "
12678 "(expected %i, found %i)\n",
12679 !!encoder->base.crtc, enabled);
e2c719b7 12680 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12681 "active encoder with no crtc\n");
12682
e2c719b7 12683 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12684 "encoder's computed active state doesn't match tracked active state "
12685 "(expected %i, found %i)\n", active, encoder->connectors_active);
12686
12687 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12688 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12689 "encoder's hw state doesn't match sw tracking "
12690 "(expected %i, found %i)\n",
12691 encoder->connectors_active, active);
12692
12693 if (!encoder->base.crtc)
12694 continue;
12695
12696 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12697 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12698 "active encoder's pipe doesn't match"
12699 "(expected %i, found %i)\n",
12700 tracked_pipe, pipe);
12701
12702 }
91d1b4bd
DV		 12703}
12704
12705static void
12706check_crtc_state(struct drm_device *dev)
12707{
fbee40df 12708 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12709 struct intel_crtc *crtc;
12710 struct intel_encoder *encoder;
5cec258b 12711 struct intel_crtc_state pipe_config;
8af6cf88 12712
d3fcc808 12713 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12714 bool enabled = false;
12715 bool active = false;
12716
045ac3b5
JB		 12717 memset(&pipe_config, 0, sizeof(pipe_config));
12718
8af6cf88
DV		 12719 DRM_DEBUG_KMS("[CRTC:%d]\n",
12720 crtc->base.base.id);
12721
83d65738 12722 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12723 "active crtc, but not enabled in sw tracking\n");
12724
b2784e15 12725 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12726 if (encoder->base.crtc != &crtc->base)
12727 continue;
12728 enabled = true;
12729 if (encoder->connectors_active)
12730 active = true;
12731 }
6c49f241 12732
e2c719b7 12733 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12734 "crtc's computed active state doesn't match tracked active state "
12735 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12736 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12737 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12738 "(expected %i, found %i)\n", enabled,
12739 crtc->base.state->enable);
8af6cf88 12740
0e8ffe1b
DV		 12741 active = dev_priv->display.get_pipe_config(crtc,
12742 &pipe_config);
d62cf62a 12743
b6b5d049
VS		 12744 /* hw state is inconsistent with the pipe quirk */
12745 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12746 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12747 active = crtc->active;
12748
b2784e15 12749 for_each_intel_encoder(dev, encoder) {
3eaba51c 12750 enum pipe pipe;
6c49f241
DV		 12751 if (encoder->base.crtc != &crtc->base)
12752 continue;
1d37b689 12753 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12754 encoder->get_config(encoder, &pipe_config);
12755 }
12756
e2c719b7 12757 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12758 "crtc active state doesn't match with hw state "
12759 "(expected %i, found %i)\n", crtc->active, active);
12760
53d9f4e9
ML		 12761 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12762 "transitional active state does not match atomic hw state "
12763 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12764
c0b03411 12765 if (active &&
6e3c9717 12766 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12767 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12768 intel_dump_pipe_config(crtc, &pipe_config,
12769 "[hw state]");
6e3c9717 12770 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12771 "[sw state]");
12772 }
8af6cf88
DV		 12773 }
12774}
12775
91d1b4bd
DV		 12776static void
12777check_shared_dpll_state(struct drm_device *dev)
12778{
fbee40df 12779 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12780 struct intel_crtc *crtc;
12781 struct intel_dpll_hw_state dpll_hw_state;
12782 int i;
5358901f
DV		 12783
12784 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12785 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12786 int enabled_crtcs = 0, active_crtcs = 0;
12787 bool active;
12788
12789 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12790
12791 DRM_DEBUG_KMS("%s\n", pll->name);
12792
12793 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12794
e2c719b7 12795 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12796 "more active pll users than references: %i vs %i\n",
3e369b76 12797 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12798 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12799 "pll in active use but not on in sw tracking\n");
e2c719b7 12800 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12801 "pll in on but not on in use in sw tracking\n");
e2c719b7 12802 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12803 "pll on state mismatch (expected %i, found %i)\n",
12804 pll->on, active);
12805
d3fcc808 12806 for_each_intel_crtc(dev, crtc) {
83d65738 12807 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12808 enabled_crtcs++;
12809 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12810 active_crtcs++;
12811 }
e2c719b7 12812 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12813 "pll active crtcs mismatch (expected %i, found %i)\n",
12814 pll->active, active_crtcs);
e2c719b7 12815 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12816 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12817 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12818
e2c719b7 12819 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12820 sizeof(dpll_hw_state)),
12821 "pll hw state mismatch\n");
5358901f 12822 }
8af6cf88
DV		 12823}
12824
91d1b4bd
DV		 12825void
12826intel_modeset_check_state(struct drm_device *dev)
12827{
08db6652 12828 check_wm_state(dev);
91d1b4bd
DV		 12829 check_connector_state(dev);
12830 check_encoder_state(dev);
12831 check_crtc_state(dev);
12832 check_shared_dpll_state(dev);
12833}
12834
5cec258b 12835void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12836 int dotclock)
12837{
12838 /*
12839 * FDI already provided one idea for the dotclock.
12840 * Yell if the encoder disagrees.
12841 */
2d112de7 12842 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12843 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12844 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12845}
12846
80715b2f
VS		 12847static void update_scanline_offset(struct intel_crtc *crtc)
12848{
12849 struct drm_device *dev = crtc->base.dev;
12850
12851 /*
12852 * The scanline counter increments at the leading edge of hsync.
12853 *
12854 * On most platforms it starts counting from vtotal-1 on the
12855 * first active line. That means the scanline counter value is
12856 * always one less than what we would expect. Ie. just after
12857 * start of vblank, which also occurs at start of hsync (on the
12858 * last active line), the scanline counter will read vblank_start-1.
12859 *
12860 * On gen2 the scanline counter starts counting from 1 instead
12861 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12862 * to keep the value positive), instead of adding one.
12863 *
12864 * On HSW+ the behaviour of the scanline counter depends on the output
12865 * type. For DP ports it behaves like most other platforms, but on HDMI
12866 * there's an extra 1 line difference. So we need to add two instead of
12867 * one to the value.
12868 */
12869 if (IS_GEN2(dev)) {
6e3c9717 12870 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12871 int vtotal;
12872
12873 vtotal = mode->crtc_vtotal;
12874 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12875 vtotal /= 2;
12876
12877 crtc->scanline_offset = vtotal - 1;
12878 } else if (HAS_DDI(dev) &&
409ee761 12879 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12880 crtc->scanline_offset = 2;
12881 } else
12882 crtc->scanline_offset = 1;
12883}
12884
ad421372 12885static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12886{
225da59b 12887 struct drm_device *dev = state->dev;
ed6739ef 12888 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12889 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12890 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12891 struct intel_crtc_state *intel_crtc_state;
12892 struct drm_crtc *crtc;
12893 struct drm_crtc_state *crtc_state;
0a9ab303 12894 int i;
ed6739ef
ACO		 12895
12896 if (!dev_priv->display.crtc_compute_clock)
ad421372 12897 return;
ed6739ef 12898
0a9ab303 12899 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12900 int dpll;
12901
0a9ab303 12902 intel_crtc = to_intel_crtc(crtc);
4978cc93 12903 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12904 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12905
ad421372 12906 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12907 continue;
12908
ad421372 12909 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12910
ad421372
ML		 12911 if (!shared_dpll)
12912 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12913
ad421372
ML		 12914 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12915 }
ed6739ef
ACO		 12916}
12917
99d736a2
ML		 12918/*
12919 * This implements the workaround described in the "notes" section of the mode
12920 * set sequence documentation. When going from no pipes or single pipe to
12921 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12922 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12923 */
12924static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12925{
12926 struct drm_crtc_state *crtc_state;
12927 struct intel_crtc *intel_crtc;
12928 struct drm_crtc *crtc;
12929 struct intel_crtc_state *first_crtc_state = NULL;
12930 struct intel_crtc_state *other_crtc_state = NULL;
12931 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12932 int i;
12933
12934 /* look at all crtc's that are going to be enabled in during modeset */
12935 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12936 intel_crtc = to_intel_crtc(crtc);
12937
12938 if (!crtc_state->active || !needs_modeset(crtc_state))
12939 continue;
12940
12941 if (first_crtc_state) {
12942 other_crtc_state = to_intel_crtc_state(crtc_state);
12943 break;
12944 } else {
12945 first_crtc_state = to_intel_crtc_state(crtc_state);
12946 first_pipe = intel_crtc->pipe;
12947 }
12948 }
12949
12950 /* No workaround needed? */
12951 if (!first_crtc_state)
12952 return 0;
12953
12954 /* w/a possibly needed, check how many crtc's are already enabled. */
12955 for_each_intel_crtc(state->dev, intel_crtc) {
12956 struct intel_crtc_state *pipe_config;
12957
12958 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12959 if (IS_ERR(pipe_config))
12960 return PTR_ERR(pipe_config);
12961
12962 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12963
12964 if (!pipe_config->base.active ||
12965 needs_modeset(&pipe_config->base))
12966 continue;
12967
12968 /* 2 or more enabled crtcs means no need for w/a */
12969 if (enabled_pipe != INVALID_PIPE)
12970 return 0;
12971
12972 enabled_pipe = intel_crtc->pipe;
12973 }
12974
12975 if (enabled_pipe != INVALID_PIPE)
12976 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12977 else if (other_crtc_state)
12978 other_crtc_state->hsw_workaround_pipe = first_pipe;
12979
12980 return 0;
12981}
12982
27c329ed
ML		 12983static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12984{
12985 struct drm_crtc *crtc;
12986 struct drm_crtc_state *crtc_state;
12987 int ret = 0;
12988
12989 /* add all active pipes to the state */
12990 for_each_crtc(state->dev, crtc) {
12991 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12992 if (IS_ERR(crtc_state))
12993 return PTR_ERR(crtc_state);
12994
12995 if (!crtc_state->active || needs_modeset(crtc_state))
12996 continue;
12997
12998 crtc_state->mode_changed = true;
12999
13000 ret = drm_atomic_add_affected_connectors(state, crtc);
13001 if (ret)
13002 break;
13003
13004 ret = drm_atomic_add_affected_planes(state, crtc);
13005 if (ret)
13006 break;
13007 }
13008
13009 return ret;
13010}
13011
13012
054518dd 13013/* Code that should eventually be part of atomic_check() */
c347a676 13014static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 13015{
13016 struct drm_device *dev = state->dev;
27c329ed 13017 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 13018 int ret;
13019
b359283a
ML		 13020 if (!check_digital_port_conflicts(state)) {
13021 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13022 return -EINVAL;
13023 }
13024
054518dd
ACO		 13025 /*
13026 * See if the config requires any additional preparation, e.g.
13027 * to adjust global state with pipes off. We need to do this
13028 * here so we can get the modeset_pipe updated config for the new
13029 * mode set on this crtc. For other crtcs we need to use the
13030 * adjusted_mode bits in the crtc directly.
13031 */
27c329ed
ML		 13032 if (dev_priv->display.modeset_calc_cdclk) {
13033 unsigned int cdclk;
b432e5cf 13034
27c329ed
ML		 13035 ret = dev_priv->display.modeset_calc_cdclk(state);
13036
13037 cdclk = to_intel_atomic_state(state)->cdclk;
13038 if (!ret && cdclk != dev_priv->cdclk_freq)
13039 ret = intel_modeset_all_pipes(state);
13040
13041 if (ret < 0)
054518dd 13042 return ret;
27c329ed
ML		 13043 } else
13044 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13045
ad421372 13046 intel_modeset_clear_plls(state);
054518dd 13047
99d736a2 13048 if (IS_HASWELL(dev))
ad421372 13049 return haswell_mode_set_planes_workaround(state);
99d736a2 13050
ad421372 13051 return 0;
c347a676
ACO		 13052}
13053
13054static int
13055intel_modeset_compute_config(struct drm_atomic_state *state)
13056{
13057 struct drm_crtc *crtc;
13058 struct drm_crtc_state *crtc_state;
13059 int ret, i;
61333b60 13060 bool any_ms = false;
c347a676
ACO		 13061
13062 ret = drm_atomic_helper_check_modeset(state->dev, state);
054518dd
ACO		 13063 if (ret)
13064 return ret;
13065
c347a676 13066 for_each_crtc_in_state(state, crtc, crtc_state, i) {
61333b60
ML		 13067 if (!crtc_state->enable) {
13068 if (needs_modeset(crtc_state))
13069 any_ms = true;
c347a676 13070 continue;
61333b60 13071 }
c347a676 13072
d032ffa0
ML		 13073 if (to_intel_crtc_state(crtc_state)->quirks &
13074 PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13075 ret = drm_atomic_add_affected_planes(state, crtc);
13076 if (ret)
13077 return ret;
13078
13079 /*
13080 * We ought to handle i915.fastboot here.
13081 * If no modeset is required and the primary plane has
13082 * a fb, update the members of crtc_state as needed,
13083 * and run the necessary updates during vblank evasion.
13084 */
13085 }
13086
b359283a
ML		 13087 if (!needs_modeset(crtc_state)) {
13088 ret = drm_atomic_add_affected_connectors(state, crtc);
13089 if (ret)
13090 return ret;
13091 }
13092
13093 ret = intel_modeset_pipe_config(crtc,
13094 to_intel_crtc_state(crtc_state));
c347a676
ACO		 13095 if (ret)
13096 return ret;
13097
61333b60
ML		 13098 if (needs_modeset(crtc_state))
13099 any_ms = true;
13100
c347a676
ACO		 13101 intel_dump_pipe_config(to_intel_crtc(crtc),
13102 to_intel_crtc_state(crtc_state),
13103 "[modeset]");
13104 }
13105
61333b60
ML		 13106 if (any_ms) {
13107 ret = intel_modeset_checks(state);
13108
13109 if (ret)
13110 return ret;
27c329ed
ML		 13111 } else
13112 to_intel_atomic_state(state)->cdclk =
13113 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13114
13115 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13116}
13117
c72d969b 13118static int __intel_set_mode(struct drm_atomic_state *state)
a6778b3c 13119{
c72d969b 13120 struct drm_device *dev = state->dev;
fbee40df 13121 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13122 struct drm_crtc *crtc;
13123 struct drm_crtc_state *crtc_state;
c0c36b94 13124 int ret = 0;
0a9ab303 13125 int i;
61333b60 13126 bool any_ms = false;
a6778b3c 13127
d4afb8cc
ACO		 13128 ret = drm_atomic_helper_prepare_planes(dev, state);
13129 if (ret)
13130 return ret;
13131
1c5e19f8
ML		 13132 drm_atomic_helper_swap_state(dev, state);
13133
0a9ab303 13134 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13136
61333b60
ML		 13137 if (!needs_modeset(crtc->state))
13138 continue;
13139
13140 any_ms = true;
a539205a 13141 intel_pre_plane_update(intel_crtc);
460da916 13142
a539205a
ML		 13143 if (crtc_state->active) {
13144 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13145 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13146 intel_crtc->active = false;
13147 intel_disable_shared_dpll(intel_crtc);
a539205a 13148 }
b8cecdf5 13149 }
7758a113 13150
ea9d758d
DV		 13151 /* Only after disabling all output pipelines that will be changed can we
13152 * update the the output configuration. */
0a9ab303 13153 intel_modeset_update_state(state);
f6e5b160 13154
a821fc46
ACO		 13155 /* The state has been swaped above, so state actually contains the
13156 * old state now. */
61333b60
ML		 13157 if (any_ms)
13158 modeset_update_crtc_power_domains(state);
47fab737 13159
a6778b3c 13160 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13161 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13162 if (needs_modeset(crtc->state) && crtc->state->active) {
13163 update_scanline_offset(to_intel_crtc(crtc));
13164 dev_priv->display.crtc_enable(crtc);
13165 }
80715b2f 13166
a539205a 13167 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
80715b2f 13168 }
a6778b3c 13169
a6778b3c 13170 /* FIXME: add subpixel order */
83a57153 13171
d4afb8cc
ACO		 13172 drm_atomic_helper_cleanup_planes(dev, state);
13173
2bfb4627
ACO		 13174 drm_atomic_state_free(state);
13175
9eb45f22 13176 return 0;
f6e5b160
CW		 13177}
13178
568c634a 13179static int intel_set_mode_checked(struct drm_atomic_state *state)
f30da187 13180{
568c634a 13181 struct drm_device *dev = state->dev;
f30da187
DV		 13182 int ret;
13183
568c634a 13184 ret = __intel_set_mode(state);
f30da187 13185 if (ret == 0)
568c634a 13186 intel_modeset_check_state(dev);
f30da187
DV		 13187
13188 return ret;
13189}
13190
568c634a 13191static int intel_set_mode(struct drm_atomic_state *state)
7f27126e 13192{
568c634a 13193 int ret;
83a57153 13194
568c634a 13195 ret = intel_modeset_compute_config(state);
83a57153 13196 if (ret)
568c634a 13197 return ret;
7f27126e 13198
568c634a 13199 return intel_set_mode_checked(state);
7f27126e
JB		 13200}
13201
c0c36b94
CW		 13202void intel_crtc_restore_mode(struct drm_crtc *crtc)
13203{
83a57153
ACO		 13204 struct drm_device *dev = crtc->dev;
13205 struct drm_atomic_state *state;
13206 struct intel_encoder *encoder;
13207 struct intel_connector *connector;
13208 struct drm_connector_state *connector_state;
4be07317 13209 struct intel_crtc_state *crtc_state;
2bfb4627 13210 int ret;
83a57153
ACO		 13211
13212 state = drm_atomic_state_alloc(dev);
13213 if (!state) {
13214 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13215 crtc->base.id);
13216 return;
13217 }
13218
13219 state->acquire_ctx = dev->mode_config.acquire_ctx;
13220
13221 /* The force restore path in the HW readout code relies on the staged
13222 * config still keeping the user requested config while the actual
13223 * state has been overwritten by the configuration read from HW. We
13224 * need to copy the staged config to the atomic state, otherwise the
13225 * mode set will just reapply the state the HW is already in. */
13226 for_each_intel_encoder(dev, encoder) {
13227 if (&encoder->new_crtc->base != crtc)
13228 continue;
13229
13230 for_each_intel_connector(dev, connector) {
13231 if (connector->new_encoder != encoder)
13232 continue;
13233
13234 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13235 if (IS_ERR(connector_state)) {
13236 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13237 connector->base.base.id,
13238 connector->base.name,
13239 PTR_ERR(connector_state));
13240 continue;
13241 }
13242
13243 connector_state->crtc = crtc;
13244 connector_state->best_encoder = &encoder->base;
13245 }
13246 }
13247
4ed9fb37
ACO		 13248 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13249 if (IS_ERR(crtc_state)) {
13250 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13251 crtc->base.id, PTR_ERR(crtc_state));
13252 drm_atomic_state_free(state);
13253 return;
13254 }
4be07317 13255
4ed9fb37
ACO		 13256 crtc_state->base.active = crtc_state->base.enable =
13257 to_intel_crtc(crtc)->new_enabled;
8c7b5ccb 13258
4ed9fb37 13259 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317 13260
d3a40d1b
ACO		 13261 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13262 crtc->primary->fb, crtc->x, crtc->y);
13263
568c634a 13264 ret = intel_set_mode(state);
2bfb4627
ACO		 13265 if (ret)
13266 drm_atomic_state_free(state);
c0c36b94
CW		 13267}
13268
25c5b266
DV		 13269#undef for_each_intel_crtc_masked
13270
b7885264
ACO		 13271static bool intel_connector_in_mode_set(struct intel_connector *connector,
13272 struct drm_mode_set *set)
13273{
13274 int ro;
13275
13276 for (ro = 0; ro < set->num_connectors; ro++)
13277 if (set->connectors[ro] == &connector->base)
13278 return true;
13279
13280 return false;
13281}
13282
2e431051 13283static int
9a935856
DV		 13284intel_modeset_stage_output_state(struct drm_device *dev,
13285 struct drm_mode_set *set,
944b0c76 13286 struct drm_atomic_state *state)
50f56119 13287{
9a935856 13288 struct intel_connector *connector;
d5432a9d 13289 struct drm_connector *drm_connector;
944b0c76 13290 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13291 struct drm_crtc *crtc;
13292 struct drm_crtc_state *crtc_state;
13293 int i, ret;
50f56119 13294
9abdda74 13295 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13296 * of connectors. For paranoia, double-check this. */
13297 WARN_ON(!set->fb && (set->num_connectors != 0));
13298 WARN_ON(set->fb && (set->num_connectors == 0));
13299
3a3371ff 13300 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13301 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13302
d5432a9d
ACO		 13303 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13304 continue;
13305
13306 connector_state =
13307 drm_atomic_get_connector_state(state, &connector->base);
13308 if (IS_ERR(connector_state))
13309 return PTR_ERR(connector_state);
13310
b7885264
ACO		 13311 if (in_mode_set) {
13312 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13313 connector_state->best_encoder =
13314 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13315 }
13316
d5432a9d 13317 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13318 continue;
13319
9a935856
DV		 13320 /* If we disable the crtc, disable all its connectors. Also, if
13321 * the connector is on the changing crtc but not on the new
13322 * connector list, disable it. */
b7885264 13323 if (!set->fb || !in_mode_set) {
d5432a9d 13324 connector_state->best_encoder = NULL;
9a935856
DV		 13325
13326 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13327 connector->base.base.id,
c23cc417 13328 connector->base.name);
9a935856 13329 }
50f56119 13330 }
9a935856 13331 /* connector->new_encoder is now updated for all connectors. */
50f56119 13332
d5432a9d
ACO		 13333 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13334 connector = to_intel_connector(drm_connector);
13335
13336 if (!connector_state->best_encoder) {
13337 ret = drm_atomic_set_crtc_for_connector(connector_state,
13338 NULL);
13339 if (ret)
13340 return ret;
7668851f 13341
50f56119 13342 continue;
d5432a9d 13343 }
50f56119 13344
d5432a9d
ACO		 13345 if (intel_connector_in_mode_set(connector, set)) {
13346 struct drm_crtc *crtc = connector->base.state->crtc;
13347
13348 /* If this connector was in a previous crtc, add it
13349 * to the state. We might need to disable it. */
13350 if (crtc) {
13351 crtc_state =
13352 drm_atomic_get_crtc_state(state, crtc);
13353 if (IS_ERR(crtc_state))
13354 return PTR_ERR(crtc_state);
13355 }
13356
13357 ret = drm_atomic_set_crtc_for_connector(connector_state,
13358 set->crtc);
13359 if (ret)
13360 return ret;
13361 }
50f56119
DV		 13362
13363 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13364 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13365 connector_state->crtc)) {
5e2b584e 13366 return -EINVAL;
50f56119 13367 }
944b0c76 13368
9a935856
DV		 13369 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13370 connector->base.base.id,
c23cc417 13371 connector->base.name,
d5432a9d 13372 connector_state->crtc->base.id);
944b0c76 13373
d5432a9d
ACO		 13374 if (connector_state->best_encoder != &connector->encoder->base)
13375 connector->encoder =
13376 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13377 }
7668851f 13378
d5432a9d 13379 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13380 bool has_connectors;
13381
d5432a9d
ACO		 13382 ret = drm_atomic_add_affected_connectors(state, crtc);
13383 if (ret)
13384 return ret;
4be07317 13385
49d6fa21
ML		 13386 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13387 if (has_connectors != crtc_state->enable)
13388 crtc_state->enable =
13389 crtc_state->active = has_connectors;
7668851f
VS		 13390 }
13391
8c7b5ccb
ACO		 13392 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13393 set->fb, set->x, set->y);
13394 if (ret)
13395 return ret;
13396
13397 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13398 if (IS_ERR(crtc_state))
13399 return PTR_ERR(crtc_state);
13400
ce52299c
MR		 13401 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13402 if (ret)
13403 return ret;
8c7b5ccb
ACO		 13404
13405 if (set->num_connectors)
13406 crtc_state->active = true;
13407
2e431051
DV		 13408 return 0;
13409}
13410
13411static int intel_crtc_set_config(struct drm_mode_set *set)
13412{
13413 struct drm_device *dev;
83a57153 13414 struct drm_atomic_state *state = NULL;
2e431051 13415 int ret;
2e431051 13416
8d3e375e
DV		 13417 BUG_ON(!set);
13418 BUG_ON(!set->crtc);
13419 BUG_ON(!set->crtc->helper_private);
2e431051 13420
7e53f3a4
DV		 13421 /* Enforce sane interface api - has been abused by the fb helper. */
13422 BUG_ON(!set->mode && set->fb);
13423 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13424
2e431051
DV		 13425 if (set->fb) {
13426 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13427 set->crtc->base.id, set->fb->base.id,
13428 (int)set->num_connectors, set->x, set->y);
13429 } else {
13430 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13431 }
13432
13433 dev = set->crtc->dev;
13434
83a57153 13435 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13436 if (!state)
13437 return -ENOMEM;
83a57153
ACO		 13438
13439 state->acquire_ctx = dev->mode_config.acquire_ctx;
13440
462a425a 13441 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13442 if (ret)
7cbf41d6 13443 goto out;
2e431051 13444
568c634a
ACO		 13445 ret = intel_modeset_compute_config(state);
13446 if (ret)
7cbf41d6 13447 goto out;
50f52756 13448
1f9954d0
JB		 13449 intel_update_pipe_size(to_intel_crtc(set->crtc));
13450
568c634a 13451 ret = intel_set_mode_checked(state);
2d05eae1 13452 if (ret) {
bf67dfeb
DV		 13453 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13454 set->crtc->base.id, ret);
2d05eae1 13455 }
50f56119 13456
7cbf41d6 13457out:
2bfb4627
ACO		 13458 if (ret)
13459 drm_atomic_state_free(state);
50f56119
DV		 13460 return ret;
13461}
f6e5b160
CW		 13462
13463static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13464 .gamma_set = intel_crtc_gamma_set,
50f56119 13465 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13466 .destroy = intel_crtc_destroy,
13467 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13468 .atomic_duplicate_state = intel_crtc_duplicate_state,
13469 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13470};
13471
5358901f
DV		 13472static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13473 struct intel_shared_dpll *pll,
13474 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13475{
5358901f 13476 uint32_t val;
ee7b9f93 13477
f458ebbc 13478 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13479 return false;
13480
5358901f 13481 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13482 hw_state->dpll = val;
13483 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13484 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13485
13486 return val & DPLL_VCO_ENABLE;
13487}
13488
15bdd4cf
DV		 13489static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13490 struct intel_shared_dpll *pll)
13491{
3e369b76
ACO		 13492 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13493 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13494}
13495
e7b903d2
DV		 13496static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13497 struct intel_shared_dpll *pll)
13498{
e7b903d2 13499 /* PCH refclock must be enabled first */
89eff4be 13500 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13501
3e369b76 13502 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13503
13504 /* Wait for the clocks to stabilize. */
13505 POSTING_READ(PCH_DPLL(pll->id));
13506 udelay(150);
13507
13508 /* The pixel multiplier can only be updated once the
13509 * DPLL is enabled and the clocks are stable.
13510 *
13511 * So write it again.
13512 */
3e369b76 13513 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13514 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13515 udelay(200);
13516}
13517
13518static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13519 struct intel_shared_dpll *pll)
13520{
13521 struct drm_device *dev = dev_priv->dev;
13522 struct intel_crtc *crtc;
e7b903d2
DV		 13523
13524 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13525 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13526 if (intel_crtc_to_shared_dpll(crtc) == pll)
13527 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13528 }
13529
15bdd4cf
DV		 13530 I915_WRITE(PCH_DPLL(pll->id), 0);
13531 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13532 udelay(200);
13533}
13534
46edb027
DV		 13535static char *ibx_pch_dpll_names[] = {
13536 "PCH DPLL A",
13537 "PCH DPLL B",
13538};
13539
7c74ade1 13540static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13541{
e7b903d2 13542 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13543 int i;
13544
7c74ade1 13545 dev_priv->num_shared_dpll = 2;
ee7b9f93 13546
e72f9fbf 13547 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13548 dev_priv->shared_dplls[i].id = i;
13549 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13550 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13551 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13552 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13553 dev_priv->shared_dplls[i].get_hw_state =
13554 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13555 }
13556}
13557
7c74ade1
DV		 13558static void intel_shared_dpll_init(struct drm_device *dev)
13559{
e7b903d2 13560 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13561
b6283055
VS		 13562 intel_update_cdclk(dev);
13563
9cd86933
DV		 13564 if (HAS_DDI(dev))
13565 intel_ddi_pll_init(dev);
13566 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13567 ibx_pch_dpll_init(dev);
13568 else
13569 dev_priv->num_shared_dpll = 0;
13570
13571 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13572}
13573
6beb8c23
MR		 13574/**
13575 * intel_prepare_plane_fb - Prepare fb for usage on plane
13576 * @plane: drm plane to prepare for
13577 * @fb: framebuffer to prepare for presentation
13578 *
13579 * Prepares a framebuffer for usage on a display plane. Generally this
13580 * involves pinning the underlying object and updating the frontbuffer tracking
13581 * bits. Some older platforms need special physical address handling for
13582 * cursor planes.
13583 *
13584 * Returns 0 on success, negative error code on failure.
13585 */
13586int
13587intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13588 struct drm_framebuffer *fb,
13589 const struct drm_plane_state *new_state)
465c120c
MR		 13590{
13591 struct drm_device *dev = plane->dev;
6beb8c23 13592 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13593 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13594 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13595 int ret = 0;
465c120c 13596
ea2c67bb 13597 if (!obj)
465c120c
MR		 13598 return 0;
13599
6beb8c23 13600 mutex_lock(&dev->struct_mutex);
465c120c 13601
6beb8c23
MR		 13602 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13603 INTEL_INFO(dev)->cursor_needs_physical) {
13604 int align = IS_I830(dev) ? 16 * 1024 : 256;
13605 ret = i915_gem_object_attach_phys(obj, align);
13606 if (ret)
13607 DRM_DEBUG_KMS("failed to attach phys object\n");
13608 } else {
91af127f 13609 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13610 }
465c120c 13611
6beb8c23 13612 if (ret == 0)
a9ff8714 13613 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13614
4c34574f 13615 mutex_unlock(&dev->struct_mutex);
465c120c 13616
6beb8c23
MR		 13617 return ret;
13618}
13619
38f3ce3a
MR		 13620/**
13621 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13622 * @plane: drm plane to clean up for
13623 * @fb: old framebuffer that was on plane
13624 *
13625 * Cleans up a framebuffer that has just been removed from a plane.
13626 */
13627void
13628intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13629 struct drm_framebuffer *fb,
13630 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13631{
13632 struct drm_device *dev = plane->dev;
13633 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13634
13635 if (WARN_ON(!obj))
13636 return;
13637
13638 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13639 !INTEL_INFO(dev)->cursor_needs_physical) {
13640 mutex_lock(&dev->struct_mutex);
82bc3b2d 13641 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13642 mutex_unlock(&dev->struct_mutex);
13643 }
465c120c
MR		 13644}
13645
6156a456
CK		 13646int
13647skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13648{
13649 int max_scale;
13650 struct drm_device *dev;
13651 struct drm_i915_private *dev_priv;
13652 int crtc_clock, cdclk;
13653
13654 if (!intel_crtc || !crtc_state)
13655 return DRM_PLANE_HELPER_NO_SCALING;
13656
13657 dev = intel_crtc->base.dev;
13658 dev_priv = dev->dev_private;
13659 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13660 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13661
13662 if (!crtc_clock || !cdclk)
13663 return DRM_PLANE_HELPER_NO_SCALING;
13664
13665 /*
13666 * skl max scale is lower of:
13667 * close to 3 but not 3, -1 is for that purpose
13668 * or
13669 * cdclk/crtc_clock
13670 */
13671 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13672
13673 return max_scale;
13674}
13675
465c120c 13676static int
3c692a41 13677intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13678 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13679 struct intel_plane_state *state)
13680{
2b875c22
MR		 13681 struct drm_crtc *crtc = state->base.crtc;
13682 struct drm_framebuffer *fb = state->base.fb;
6156a456 13683 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13684 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13685 bool can_position = false;
465c120c 13686
061e4b8d
ML		 13687 /* use scaler when colorkey is not required */
13688 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13689 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13690 min_scale = 1;
13691 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13692 can_position = true;
6156a456 13693 }
d8106366 13694
061e4b8d
ML		 13695 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13696 &state->dst, &state->clip,
da20eabd
ML		 13697 min_scale, max_scale,
13698 can_position, true,
13699 &state->visible);
14af293f
GP		 13700}
13701
13702static void
13703intel_commit_primary_plane(struct drm_plane *plane,
13704 struct intel_plane_state *state)
13705{
2b875c22
MR		 13706 struct drm_crtc *crtc = state->base.crtc;
13707 struct drm_framebuffer *fb = state->base.fb;
13708 struct drm_device *dev = plane->dev;
14af293f 13709 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13710 struct intel_crtc *intel_crtc;
14af293f
GP		 13711 struct drm_rect *src = &state->src;
13712
ea2c67bb
MR		 13713 crtc = crtc ? crtc : plane->crtc;
13714 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13715
13716 plane->fb = fb;
9dc806fc
MR		 13717 crtc->x = src->x1 >> 16;
13718 crtc->y = src->y1 >> 16;
ccc759dc 13719
a539205a 13720 if (!crtc->state->active)
302d19ac 13721 return;
465c120c 13722
302d19ac
ML		 13723 if (state->visible)
13724 /* FIXME: kill this fastboot hack */
13725 intel_update_pipe_size(intel_crtc);
13726
13727 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13728}
13729
a8ad0d8e
ML		 13730static void
13731intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13732 struct drm_crtc *crtc)
a8ad0d8e
ML		 13733{
13734 struct drm_device *dev = plane->dev;
13735 struct drm_i915_private *dev_priv = dev->dev_private;
13736
a8ad0d8e
ML		 13737 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13738}
13739
32b7eeec 13740static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13741{
32b7eeec 13742 struct drm_device *dev = crtc->dev;
140fd38d 13743 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13745
a539205a
ML		 13746 if (!needs_modeset(crtc->state))
13747 intel_pre_plane_update(intel_crtc);
3c692a41 13748
f015c551 13749 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13750 intel_update_watermarks(crtc);
3c692a41 13751
32b7eeec 13752 intel_runtime_pm_get(dev_priv);
3c692a41 13753
c34c9ee4 13754 /* Perform vblank evasion around commit operation */
a539205a 13755 if (crtc->state->active)
c34c9ee4
MR		 13756 intel_crtc->atomic.evade =
13757 intel_pipe_update_start(intel_crtc,
13758 &intel_crtc->atomic.start_vbl_count);
0583236e
ML		 13759
13760 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13761 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13762}
13763
13764static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13765{
13766 struct drm_device *dev = crtc->dev;
13767 struct drm_i915_private *dev_priv = dev->dev_private;
13768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13769
c34c9ee4
MR		 13770 if (intel_crtc->atomic.evade)
13771 intel_pipe_update_end(intel_crtc,
13772 intel_crtc->atomic.start_vbl_count);
3c692a41 13773
140fd38d 13774 intel_runtime_pm_put(dev_priv);
3c692a41 13775
ac21b225 13776 intel_post_plane_update(intel_crtc);
3c692a41
GP		 13777}
13778
cf4c7c12 13779/**
4a3b8769
MR		 13780 * intel_plane_destroy - destroy a plane
13781 * @plane: plane to destroy
cf4c7c12 13782 *
4a3b8769
MR		 13783 * Common destruction function for all types of planes (primary, cursor,
13784 * sprite).
cf4c7c12 13785 */
4a3b8769 13786void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13787{
13788 struct intel_plane *intel_plane = to_intel_plane(plane);
13789 drm_plane_cleanup(plane);
13790 kfree(intel_plane);
13791}
13792
65a3fea0 13793const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13794 .update_plane = drm_atomic_helper_update_plane,
13795 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13796 .destroy = intel_plane_destroy,
c196e1d6 13797 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13798 .atomic_get_property = intel_plane_atomic_get_property,
13799 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13800 .atomic_duplicate_state = intel_plane_duplicate_state,
13801 .atomic_destroy_state = intel_plane_destroy_state,
13802
465c120c
MR		 13803};
13804
13805static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13806 int pipe)
13807{
13808 struct intel_plane *primary;
8e7d688b 13809 struct intel_plane_state *state;
465c120c
MR		 13810 const uint32_t *intel_primary_formats;
13811 int num_formats;
13812
13813 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13814 if (primary == NULL)
13815 return NULL;
13816
8e7d688b
MR		 13817 state = intel_create_plane_state(&primary->base);
13818 if (!state) {
ea2c67bb
MR		 13819 kfree(primary);
13820 return NULL;
13821 }
8e7d688b 13822 primary->base.state = &state->base;
ea2c67bb 13823
465c120c
MR		 13824 primary->can_scale = false;
13825 primary->max_downscale = 1;
6156a456
CK		 13826 if (INTEL_INFO(dev)->gen >= 9) {
13827 primary->can_scale = true;
af99ceda 13828 state->scaler_id = -1;
6156a456 13829 }
465c120c
MR		 13830 primary->pipe = pipe;
13831 primary->plane = pipe;
a9ff8714 13832 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13833 primary->check_plane = intel_check_primary_plane;
13834 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13835 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13836 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13837 primary->plane = !pipe;
13838
6c0fd451
DL		 13839 if (INTEL_INFO(dev)->gen >= 9) {
13840 intel_primary_formats = skl_primary_formats;
13841 num_formats = ARRAY_SIZE(skl_primary_formats);
13842 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13843 intel_primary_formats = i965_primary_formats;
13844 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13845 } else {
13846 intel_primary_formats = i8xx_primary_formats;
13847 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13848 }
13849
13850 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13851 &intel_plane_funcs,
465c120c
MR		 13852 intel_primary_formats, num_formats,
13853 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13854
3b7a5119
SJ		 13855 if (INTEL_INFO(dev)->gen >= 4)
13856 intel_create_rotation_property(dev, primary);
48404c1e 13857
ea2c67bb
MR		 13858 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13859
465c120c
MR		 13860 return &primary->base;
13861}
13862
3b7a5119
SJ		 13863void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13864{
13865 if (!dev->mode_config.rotation_property) {
13866 unsigned long flags = BIT(DRM_ROTATE_0) |
13867 BIT(DRM_ROTATE_180);
13868
13869 if (INTEL_INFO(dev)->gen >= 9)
13870 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13871
13872 dev->mode_config.rotation_property =
13873 drm_mode_create_rotation_property(dev, flags);
13874 }
13875 if (dev->mode_config.rotation_property)
13876 drm_object_attach_property(&plane->base.base,
13877 dev->mode_config.rotation_property,
13878 plane->base.state->rotation);
13879}
13880
3d7d6510 13881static int
852e787c 13882intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13883 struct intel_crtc_state *crtc_state,
852e787c 13884 struct intel_plane_state *state)
3d7d6510 13885{
061e4b8d 13886 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13887 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13888 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13889 unsigned stride;
13890 int ret;
3d7d6510 13891
061e4b8d
ML		 13892 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13893 &state->dst, &state->clip,
3d7d6510
MR		 13894 DRM_PLANE_HELPER_NO_SCALING,
13895 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13896 true, true, &state->visible);
757f9a3e
GP		 13897 if (ret)
13898 return ret;
13899
757f9a3e
GP		 13900 /* if we want to turn off the cursor ignore width and height */
13901 if (!obj)
da20eabd 13902 return 0;
757f9a3e 13903
757f9a3e 13904 /* Check for which cursor types we support */
061e4b8d 13905 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13906 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13907 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13908 return -EINVAL;
13909 }
13910
ea2c67bb
MR		 13911 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13912 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13913 DRM_DEBUG_KMS("buffer is too small\n");
13914 return -ENOMEM;
13915 }
13916
3a656b54 13917 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13918 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13919 return -EINVAL;
32b7eeec
MR		 13920 }
13921
da20eabd 13922 return 0;
852e787c 13923}
3d7d6510 13924
a8ad0d8e
ML		 13925static void
13926intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13927 struct drm_crtc *crtc)
a8ad0d8e 13928{
a8ad0d8e
ML		 13929 intel_crtc_update_cursor(crtc, false);
13930}
13931
f4a2cf29 13932static void
852e787c
GP		 13933intel_commit_cursor_plane(struct drm_plane *plane,
13934 struct intel_plane_state *state)
13935{
2b875c22 13936 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13937 struct drm_device *dev = plane->dev;
13938 struct intel_crtc *intel_crtc;
2b875c22 13939 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13940 uint32_t addr;
852e787c 13941
ea2c67bb
MR		 13942 crtc = crtc ? crtc : plane->crtc;
13943 intel_crtc = to_intel_crtc(crtc);
13944
2b875c22 13945 plane->fb = state->base.fb;
ea2c67bb
MR		 13946 crtc->cursor_x = state->base.crtc_x;
13947 crtc->cursor_y = state->base.crtc_y;
13948
a912f12f
GP		 13949 if (intel_crtc->cursor_bo == obj)
13950 goto update;
4ed91096 13951
f4a2cf29 13952 if (!obj)
a912f12f 13953 addr = 0;
f4a2cf29 13954 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13955 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13956 else
a912f12f 13957 addr = obj->phys_handle->busaddr;
852e787c 13958
a912f12f
GP		 13959 intel_crtc->cursor_addr = addr;
13960 intel_crtc->cursor_bo = obj;
852e787c 13961
302d19ac 13962update:
a539205a 13963 if (crtc->state->active)
a912f12f 13964 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13965}
13966
3d7d6510
MR		 13967static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13968 int pipe)
13969{
13970 struct intel_plane *cursor;
8e7d688b 13971 struct intel_plane_state *state;
3d7d6510
MR		 13972
13973 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13974 if (cursor == NULL)
13975 return NULL;
13976
8e7d688b
MR		 13977 state = intel_create_plane_state(&cursor->base);
13978 if (!state) {
ea2c67bb
MR		 13979 kfree(cursor);
13980 return NULL;
13981 }
8e7d688b 13982 cursor->base.state = &state->base;
ea2c67bb 13983
3d7d6510
MR		 13984 cursor->can_scale = false;
13985 cursor->max_downscale = 1;
13986 cursor->pipe = pipe;
13987 cursor->plane = pipe;
a9ff8714 13988 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13989 cursor->check_plane = intel_check_cursor_plane;
13990 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13991 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13992
13993 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13994 &intel_plane_funcs,
3d7d6510
MR		 13995 intel_cursor_formats,
13996 ARRAY_SIZE(intel_cursor_formats),
13997 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13998
13999 if (INTEL_INFO(dev)->gen >= 4) {
14000 if (!dev->mode_config.rotation_property)
14001 dev->mode_config.rotation_property =
14002 drm_mode_create_rotation_property(dev,
14003 BIT(DRM_ROTATE_0) |
14004 BIT(DRM_ROTATE_180));
14005 if (dev->mode_config.rotation_property)
14006 drm_object_attach_property(&cursor->base.base,
14007 dev->mode_config.rotation_property,
8e7d688b 14008 state->base.rotation);
4398ad45
VS		 14009 }
14010
af99ceda
CK		 14011 if (INTEL_INFO(dev)->gen >=9)
14012 state->scaler_id = -1;
14013
ea2c67bb
MR		 14014 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14015
3d7d6510
MR		 14016 return &cursor->base;
14017}
14018
549e2bfb
CK		 14019static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14020 struct intel_crtc_state *crtc_state)
14021{
14022 int i;
14023 struct intel_scaler *intel_scaler;
14024 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14025
14026 for (i = 0; i < intel_crtc->num_scalers; i++) {
14027 intel_scaler = &scaler_state->scalers[i];
14028 intel_scaler->in_use = 0;
549e2bfb
CK		 14029 intel_scaler->mode = PS_SCALER_MODE_DYN;
14030 }
14031
14032 scaler_state->scaler_id = -1;
14033}
14034
b358d0a6 14035static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14036{
fbee40df 14037 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14038 struct intel_crtc *intel_crtc;
f5de6e07 14039 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14040 struct drm_plane *primary = NULL;
14041 struct drm_plane *cursor = NULL;
465c120c 14042 int i, ret;
79e53945 14043
955382f3 14044 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14045 if (intel_crtc == NULL)
14046 return;
14047
f5de6e07
ACO		 14048 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14049 if (!crtc_state)
14050 goto fail;
550acefd
ACO		 14051 intel_crtc->config = crtc_state;
14052 intel_crtc->base.state = &crtc_state->base;
07878248 14053 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14054
549e2bfb
CK		 14055 /* initialize shared scalers */
14056 if (INTEL_INFO(dev)->gen >= 9) {
14057 if (pipe == PIPE_C)
14058 intel_crtc->num_scalers = 1;
14059 else
14060 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14061
14062 skl_init_scalers(dev, intel_crtc, crtc_state);
14063 }
14064
465c120c 14065 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14066 if (!primary)
14067 goto fail;
14068
14069 cursor = intel_cursor_plane_create(dev, pipe);
14070 if (!cursor)
14071 goto fail;
14072
465c120c 14073 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14074 cursor, &intel_crtc_funcs);
14075 if (ret)
14076 goto fail;
79e53945
JB		 14077
14078 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14079 for (i = 0; i < 256; i++) {
14080 intel_crtc->lut_r[i] = i;
14081 intel_crtc->lut_g[i] = i;
14082 intel_crtc->lut_b[i] = i;
14083 }
14084
1f1c2e24
VS		 14085 /*
14086 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14087 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14088 */
80824003
JB		 14089 intel_crtc->pipe = pipe;
14090 intel_crtc->plane = pipe;
3a77c4c4 14091 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14092 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14093 intel_crtc->plane = !pipe;
80824003
JB		 14094 }
14095
4b0e333e
CW		 14096 intel_crtc->cursor_base = ~0;
14097 intel_crtc->cursor_cntl = ~0;
dc41c154 14098 intel_crtc->cursor_size = ~0;
8d7849db 14099
852eb00d
VS		 14100 intel_crtc->wm.cxsr_allowed = true;
14101
22fd0fab
JB		 14102 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14103 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14104 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14105 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14106
79e53945 14107 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14108
14109 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14110 return;
14111
14112fail:
14113 if (primary)
14114 drm_plane_cleanup(primary);
14115 if (cursor)
14116 drm_plane_cleanup(cursor);
f5de6e07 14117 kfree(crtc_state);
3d7d6510 14118 kfree(intel_crtc);
79e53945
JB		 14119}
14120
752aa88a
JB		 14121enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14122{
14123 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14124 struct drm_device *dev = connector->base.dev;
752aa88a 14125
51fd371b 14126 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14127
d3babd3f 14128 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14129 return INVALID_PIPE;
14130
14131 return to_intel_crtc(encoder->crtc)->pipe;
14132}
14133
08d7b3d1 14134int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14135 struct drm_file *file)
08d7b3d1 14136{
08d7b3d1 14137 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14138 struct drm_crtc *drmmode_crtc;
c05422d5 14139 struct intel_crtc *crtc;
08d7b3d1 14140
7707e653 14141 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14142
7707e653 14143 if (!drmmode_crtc) {
08d7b3d1 14144 DRM_ERROR("no such CRTC id\n");
3f2c2057 14145 return -ENOENT;
08d7b3d1
CW		 14146 }
14147
7707e653 14148 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14149 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14150
c05422d5 14151 return 0;
08d7b3d1
CW		 14152}
14153
66a9278e 14154static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14155{
66a9278e
DV		 14156 struct drm_device *dev = encoder->base.dev;
14157 struct intel_encoder *source_encoder;
79e53945 14158 int index_mask = 0;
79e53945
JB		 14159 int entry = 0;
14160
b2784e15 14161 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14162 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14163 index_mask |= (1 << entry);
14164
79e53945
JB		 14165 entry++;
14166 }
4ef69c7a 14167
79e53945
JB		 14168 return index_mask;
14169}
14170
4d302442
CW		 14171static bool has_edp_a(struct drm_device *dev)
14172{
14173 struct drm_i915_private *dev_priv = dev->dev_private;
14174
14175 if (!IS_MOBILE(dev))
14176 return false;
14177
14178 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14179 return false;
14180
e3589908 14181 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14182 return false;
14183
14184 return true;
14185}
14186
84b4e042
JB		 14187static bool intel_crt_present(struct drm_device *dev)
14188{
14189 struct drm_i915_private *dev_priv = dev->dev_private;
14190
884497ed
DL		 14191 if (INTEL_INFO(dev)->gen >= 9)
14192 return false;
14193
cf404ce4 14194 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14195 return false;
14196
14197 if (IS_CHERRYVIEW(dev))
14198 return false;
14199
14200 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14201 return false;
14202
14203 return true;
14204}
14205
79e53945
JB		 14206static void intel_setup_outputs(struct drm_device *dev)
14207{
725e30ad 14208 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14209 struct intel_encoder *encoder;
cb0953d7 14210 bool dpd_is_edp = false;
79e53945 14211
c9093354 14212 intel_lvds_init(dev);
79e53945 14213
84b4e042 14214 if (intel_crt_present(dev))
79935fca 14215 intel_crt_init(dev);
cb0953d7 14216
c776eb2e
VK		 14217 if (IS_BROXTON(dev)) {
14218 /*
14219 * FIXME: Broxton doesn't support port detection via the
14220 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14221 * detect the ports.
14222 */
14223 intel_ddi_init(dev, PORT_A);
14224 intel_ddi_init(dev, PORT_B);
14225 intel_ddi_init(dev, PORT_C);
14226 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14227 int found;
14228
de31facd
JB		 14229 /*
14230 * Haswell uses DDI functions to detect digital outputs.
14231 * On SKL pre-D0 the strap isn't connected, so we assume
14232 * it's there.
14233 */
0e72a5b5 14234 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14235 /* WaIgnoreDDIAStrap: skl */
14236 if (found ||
14237 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14238 intel_ddi_init(dev, PORT_A);
14239
14240 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14241 * register */
14242 found = I915_READ(SFUSE_STRAP);
14243
14244 if (found & SFUSE_STRAP_DDIB_DETECTED)
14245 intel_ddi_init(dev, PORT_B);
14246 if (found & SFUSE_STRAP_DDIC_DETECTED)
14247 intel_ddi_init(dev, PORT_C);
14248 if (found & SFUSE_STRAP_DDID_DETECTED)
14249 intel_ddi_init(dev, PORT_D);
14250 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14251 int found;
5d8a7752 14252 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14253
14254 if (has_edp_a(dev))
14255 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14256
dc0fa718 14257 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14258 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14259 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14260 if (!found)
e2debe91 14261 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14262 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14263 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14264 }
14265
dc0fa718 14266 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14267 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14268
dc0fa718 14269 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14270 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14271
5eb08b69 14272 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14273 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14274
270b3042 14275 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14276 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14277 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14278 /*
14279 * The DP_DETECTED bit is the latched state of the DDC
14280 * SDA pin at boot. However since eDP doesn't require DDC
14281 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14282 * eDP ports may have been muxed to an alternate function.
14283 * Thus we can't rely on the DP_DETECTED bit alone to detect
14284 * eDP ports. Consult the VBT as well as DP_DETECTED to
14285 * detect eDP ports.
14286 */
d2182a66
VS		 14287 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14288 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14289 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14290 PORT_B);
e17ac6db
VS		 14291 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14292 intel_dp_is_edp(dev, PORT_B))
14293 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14294
d2182a66
VS		 14295 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14296 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14297 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14298 PORT_C);
e17ac6db
VS		 14299 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14300 intel_dp_is_edp(dev, PORT_C))
14301 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14302
9418c1f1 14303 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14304 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14305 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14306 PORT_D);
e17ac6db
VS		 14307 /* eDP not supported on port D, so don't check VBT */
14308 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14309 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14310 }
14311
3cfca973 14312 intel_dsi_init(dev);
09da55dc 14313 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14314 bool found = false;
7d57382e 14315
e2debe91 14316 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14317 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14318 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14319 if (!found && IS_G4X(dev)) {
b01f2c3a 14320 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14321 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14322 }
27185ae1 14323
3fec3d2f 14324 if (!found && IS_G4X(dev))
ab9d7c30 14325 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14326 }
13520b05
KH		 14327
14328 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14329
e2debe91 14330 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14331 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14332 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14333 }
27185ae1 14334
e2debe91 14335 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14336
3fec3d2f 14337 if (IS_G4X(dev)) {
b01f2c3a 14338 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14339 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14340 }
3fec3d2f 14341 if (IS_G4X(dev))
ab9d7c30 14342 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14343 }
27185ae1 14344
3fec3d2f 14345 if (IS_G4X(dev) &&
e7281eab 14346 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14347 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14348 } else if (IS_GEN2(dev))
79e53945
JB		 14349 intel_dvo_init(dev);
14350
103a196f 14351 if (SUPPORTS_TV(dev))
79e53945
JB		 14352 intel_tv_init(dev);
14353
0bc12bcb 14354 intel_psr_init(dev);
7c8f8a70 14355
b2784e15 14356 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14357 encoder->base.possible_crtcs = encoder->crtc_mask;
14358 encoder->base.possible_clones =
66a9278e 14359 intel_encoder_clones(encoder);
79e53945 14360 }
47356eb6 14361
dde86e2d 14362 intel_init_pch_refclk(dev);
270b3042
DV		 14363
14364 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14365}
14366
14367static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14368{
60a5ca01 14369 struct drm_device *dev = fb->dev;
79e53945 14370 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14371
ef2d633e 14372 drm_framebuffer_cleanup(fb);
60a5ca01 14373 mutex_lock(&dev->struct_mutex);
ef2d633e 14374 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14375 drm_gem_object_unreference(&intel_fb->obj->base);
14376 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14377 kfree(intel_fb);
14378}
14379
14380static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14381 struct drm_file *file,
79e53945
JB		 14382 unsigned int *handle)
14383{
14384 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14385 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14386
05394f39 14387 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14388}
14389
86c98588
RV		 14390static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14391 struct drm_file *file,
14392 unsigned flags, unsigned color,
14393 struct drm_clip_rect *clips,
14394 unsigned num_clips)
14395{
14396 struct drm_device *dev = fb->dev;
14397 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14398 struct drm_i915_gem_object *obj = intel_fb->obj;
14399
14400 mutex_lock(&dev->struct_mutex);
14401 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
14402 mutex_unlock(&dev->struct_mutex);
14403
14404 return 0;
14405}
14406
79e53945
JB		 14407static const struct drm_framebuffer_funcs intel_fb_funcs = {
14408 .destroy = intel_user_framebuffer_destroy,
14409 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14410 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14411};
14412
b321803d
DL		 14413static
14414u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14415 uint32_t pixel_format)
14416{
14417 u32 gen = INTEL_INFO(dev)->gen;
14418
14419 if (gen >= 9) {
14420 /* "The stride in bytes must not exceed the of the size of 8K
14421 * pixels and 32K bytes."
14422 */
14423 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14424 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14425 return 32*1024;
14426 } else if (gen >= 4) {
14427 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14428 return 16*1024;
14429 else
14430 return 32*1024;
14431 } else if (gen >= 3) {
14432 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14433 return 8*1024;
14434 else
14435 return 16*1024;
14436 } else {
14437 /* XXX DSPC is limited to 4k tiled */
14438 return 8*1024;
14439 }
14440}
14441
b5ea642a
DV		 14442static int intel_framebuffer_init(struct drm_device *dev,
14443 struct intel_framebuffer *intel_fb,
14444 struct drm_mode_fb_cmd2 *mode_cmd,
14445 struct drm_i915_gem_object *obj)
79e53945 14446{
6761dd31 14447 unsigned int aligned_height;
79e53945 14448 int ret;
b321803d 14449 u32 pitch_limit, stride_alignment;
79e53945 14450
dd4916c5
DV		 14451 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14452
2a80eada
DV		 14453 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14454 /* Enforce that fb modifier and tiling mode match, but only for
14455 * X-tiled. This is needed for FBC. */
14456 if (!!(obj->tiling_mode == I915_TILING_X) !=
14457 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14458 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14459 return -EINVAL;
14460 }
14461 } else {
14462 if (obj->tiling_mode == I915_TILING_X)
14463 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14464 else if (obj->tiling_mode == I915_TILING_Y) {
14465 DRM_DEBUG("No Y tiling for legacy addfb\n");
14466 return -EINVAL;
14467 }
14468 }
14469
9a8f0a12
TU		 14470 /* Passed in modifier sanity checking. */
14471 switch (mode_cmd->modifier[0]) {
14472 case I915_FORMAT_MOD_Y_TILED:
14473 case I915_FORMAT_MOD_Yf_TILED:
14474 if (INTEL_INFO(dev)->gen < 9) {
14475 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14476 mode_cmd->modifier[0]);
14477 return -EINVAL;
14478 }
14479 case DRM_FORMAT_MOD_NONE:
14480 case I915_FORMAT_MOD_X_TILED:
14481 break;
14482 default:
c0f40428
JB		 14483 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14484 mode_cmd->modifier[0]);
57cd6508 14485 return -EINVAL;
c16ed4be 14486 }
57cd6508 14487
b321803d
DL		 14488 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14489 mode_cmd->pixel_format);
14490 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14491 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14492 mode_cmd->pitches[0], stride_alignment);
57cd6508 14493 return -EINVAL;
c16ed4be 14494 }
57cd6508 14495
b321803d
DL		 14496 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14497 mode_cmd->pixel_format);
a35cdaa0 14498 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14499 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14500 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14501 "tiled" : "linear",
a35cdaa0 14502 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14503 return -EINVAL;
c16ed4be 14504 }
5d7bd705 14505
2a80eada 14506 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14507 mode_cmd->pitches[0] != obj->stride) {
14508 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14509 mode_cmd->pitches[0], obj->stride);
5d7bd705 14510 return -EINVAL;
c16ed4be 14511 }
5d7bd705 14512
57779d06 14513 /* Reject formats not supported by any plane early. */
308e5bcb 14514 switch (mode_cmd->pixel_format) {
57779d06 14515 case DRM_FORMAT_C8:
04b3924d
VS		 14516 case DRM_FORMAT_RGB565:
14517 case DRM_FORMAT_XRGB8888:
14518 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14519 break;
14520 case DRM_FORMAT_XRGB1555:
c16ed4be 14521 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14522 DRM_DEBUG("unsupported pixel format: %s\n",
14523 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14524 return -EINVAL;
c16ed4be 14525 }
57779d06 14526 break;
57779d06 14527 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14528 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14529 DRM_DEBUG("unsupported pixel format: %s\n",
14530 drm_get_format_name(mode_cmd->pixel_format));
14531 return -EINVAL;
14532 }
14533 break;
14534 case DRM_FORMAT_XBGR8888:
04b3924d 14535 case DRM_FORMAT_XRGB2101010:
57779d06 14536 case DRM_FORMAT_XBGR2101010:
c16ed4be 14537 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14538 DRM_DEBUG("unsupported pixel format: %s\n",
14539 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14540 return -EINVAL;
c16ed4be 14541 }
b5626747 14542 break;
7531208b
DL		 14543 case DRM_FORMAT_ABGR2101010:
14544 if (!IS_VALLEYVIEW(dev)) {
14545 DRM_DEBUG("unsupported pixel format: %s\n",
14546 drm_get_format_name(mode_cmd->pixel_format));
14547 return -EINVAL;
14548 }
14549 break;
04b3924d
VS		 14550 case DRM_FORMAT_YUYV:
14551 case DRM_FORMAT_UYVY:
14552 case DRM_FORMAT_YVYU:
14553 case DRM_FORMAT_VYUY:
c16ed4be 14554 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14555 DRM_DEBUG("unsupported pixel format: %s\n",
14556 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14557 return -EINVAL;
c16ed4be 14558 }
57cd6508
CW		 14559 break;
14560 default:
4ee62c76
VS		 14561 DRM_DEBUG("unsupported pixel format: %s\n",
14562 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14563 return -EINVAL;
14564 }
14565
90f9a336
VS		 14566 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14567 if (mode_cmd->offsets[0] != 0)
14568 return -EINVAL;
14569
ec2c981e 14570 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14571 mode_cmd->pixel_format,
14572 mode_cmd->modifier[0]);
53155c0a
DV		 14573 /* FIXME drm helper for size checks (especially planar formats)? */
14574 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14575 return -EINVAL;
14576
c7d73f6a
DV		 14577 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14578 intel_fb->obj = obj;
80075d49 14579 intel_fb->obj->framebuffer_references++;
c7d73f6a 14580
79e53945
JB		 14581 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14582 if (ret) {
14583 DRM_ERROR("framebuffer init failed %d\n", ret);
14584 return ret;
14585 }
14586
79e53945
JB		 14587 return 0;
14588}
14589
79e53945
JB		 14590static struct drm_framebuffer *
14591intel_user_framebuffer_create(struct drm_device *dev,
14592 struct drm_file *filp,
308e5bcb 14593 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14594{
05394f39 14595 struct drm_i915_gem_object *obj;
79e53945 14596
308e5bcb
JB		 14597 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14598 mode_cmd->handles[0]));
c8725226 14599 if (&obj->base == NULL)
cce13ff7 14600 return ERR_PTR(-ENOENT);
79e53945 14601
d2dff872 14602 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14603}
14604
4520f53a 14605#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14606static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14607{
14608}
14609#endif
14610
79e53945 14611static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14612 .fb_create = intel_user_framebuffer_create,
0632fef6 14613 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14614 .atomic_check = intel_atomic_check,
14615 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14616 .atomic_state_alloc = intel_atomic_state_alloc,
14617 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14618};
14619
e70236a8
JB		 14620/* Set up chip specific display functions */
14621static void intel_init_display(struct drm_device *dev)
14622{
14623 struct drm_i915_private *dev_priv = dev->dev_private;
14624
ee9300bb
DV		 14625 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14626 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14627 else if (IS_CHERRYVIEW(dev))
14628 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14629 else if (IS_VALLEYVIEW(dev))
14630 dev_priv->display.find_dpll = vlv_find_best_dpll;
14631 else if (IS_PINEVIEW(dev))
14632 dev_priv->display.find_dpll = pnv_find_best_dpll;
14633 else
14634 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14635
bc8d7dff
DL		 14636 if (INTEL_INFO(dev)->gen >= 9) {
14637 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14638 dev_priv->display.get_initial_plane_config =
14639 skylake_get_initial_plane_config;
bc8d7dff
DL		 14640 dev_priv->display.crtc_compute_clock =
14641 haswell_crtc_compute_clock;
14642 dev_priv->display.crtc_enable = haswell_crtc_enable;
14643 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14644 dev_priv->display.update_primary_plane =
14645 skylake_update_primary_plane;
14646 } else if (HAS_DDI(dev)) {
0e8ffe1b 14647 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14648 dev_priv->display.get_initial_plane_config =
14649 ironlake_get_initial_plane_config;
797d0259
ACO		 14650 dev_priv->display.crtc_compute_clock =
14651 haswell_crtc_compute_clock;
4f771f10
PZ		 14652 dev_priv->display.crtc_enable = haswell_crtc_enable;
14653 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14654 dev_priv->display.update_primary_plane =
14655 ironlake_update_primary_plane;
09b4ddf9 14656 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14657 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14658 dev_priv->display.get_initial_plane_config =
14659 ironlake_get_initial_plane_config;
3fb37703
ACO		 14660 dev_priv->display.crtc_compute_clock =
14661 ironlake_crtc_compute_clock;
76e5a89c
DV		 14662 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14663 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14664 dev_priv->display.update_primary_plane =
14665 ironlake_update_primary_plane;
89b667f8
JB		 14666 } else if (IS_VALLEYVIEW(dev)) {
14667 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14668 dev_priv->display.get_initial_plane_config =
14669 i9xx_get_initial_plane_config;
d6dfee7a 14670 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14671 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14672 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14673 dev_priv->display.update_primary_plane =
14674 i9xx_update_primary_plane;
f564048e 14675 } else {
0e8ffe1b 14676 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14677 dev_priv->display.get_initial_plane_config =
14678 i9xx_get_initial_plane_config;
d6dfee7a 14679 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14680 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14681 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14682 dev_priv->display.update_primary_plane =
14683 i9xx_update_primary_plane;
f564048e 14684 }
e70236a8 14685
e70236a8 14686 /* Returns the core display clock speed */
1652d19e
VS		 14687 if (IS_SKYLAKE(dev))
14688 dev_priv->display.get_display_clock_speed =
14689 skylake_get_display_clock_speed;
acd3f3d3
BP		 14690 else if (IS_BROXTON(dev))
14691 dev_priv->display.get_display_clock_speed =
14692 broxton_get_display_clock_speed;
1652d19e
VS		 14693 else if (IS_BROADWELL(dev))
14694 dev_priv->display.get_display_clock_speed =
14695 broadwell_get_display_clock_speed;
14696 else if (IS_HASWELL(dev))
14697 dev_priv->display.get_display_clock_speed =
14698 haswell_get_display_clock_speed;
14699 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14700 dev_priv->display.get_display_clock_speed =
14701 valleyview_get_display_clock_speed;
b37a6434
VS		 14702 else if (IS_GEN5(dev))
14703 dev_priv->display.get_display_clock_speed =
14704 ilk_get_display_clock_speed;
a7c66cd8 14705 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14706 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14707 dev_priv->display.get_display_clock_speed =
14708 i945_get_display_clock_speed;
34edce2f
VS		 14709 else if (IS_GM45(dev))
14710 dev_priv->display.get_display_clock_speed =
14711 gm45_get_display_clock_speed;
14712 else if (IS_CRESTLINE(dev))
14713 dev_priv->display.get_display_clock_speed =
14714 i965gm_get_display_clock_speed;
14715 else if (IS_PINEVIEW(dev))
14716 dev_priv->display.get_display_clock_speed =
14717 pnv_get_display_clock_speed;
14718 else if (IS_G33(dev) || IS_G4X(dev))
14719 dev_priv->display.get_display_clock_speed =
14720 g33_get_display_clock_speed;
e70236a8
JB		 14721 else if (IS_I915G(dev))
14722 dev_priv->display.get_display_clock_speed =
14723 i915_get_display_clock_speed;
257a7ffc 14724 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14725 dev_priv->display.get_display_clock_speed =
14726 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14727 else if (IS_PINEVIEW(dev))
14728 dev_priv->display.get_display_clock_speed =
14729 pnv_get_display_clock_speed;
e70236a8
JB		 14730 else if (IS_I915GM(dev))
14731 dev_priv->display.get_display_clock_speed =
14732 i915gm_get_display_clock_speed;
14733 else if (IS_I865G(dev))
14734 dev_priv->display.get_display_clock_speed =
14735 i865_get_display_clock_speed;
f0f8a9ce 14736 else if (IS_I85X(dev))
e70236a8 14737 dev_priv->display.get_display_clock_speed =
1b1d2716 14738 i85x_get_display_clock_speed;
623e01e5
VS		 14739 else { /* 830 */
14740 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14741 dev_priv->display.get_display_clock_speed =
14742 i830_get_display_clock_speed;
623e01e5 14743 }
e70236a8 14744
7c10a2b5 14745 if (IS_GEN5(dev)) {
3bb11b53 14746 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14747 } else if (IS_GEN6(dev)) {
14748 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14749 } else if (IS_IVYBRIDGE(dev)) {
14750 /* FIXME: detect B0+ stepping and use auto training */
14751 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14752 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14753 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14754 if (IS_BROADWELL(dev)) {
14755 dev_priv->display.modeset_commit_cdclk =
14756 broadwell_modeset_commit_cdclk;
14757 dev_priv->display.modeset_calc_cdclk =
14758 broadwell_modeset_calc_cdclk;
14759 }
30a970c6 14760 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14761 dev_priv->display.modeset_commit_cdclk =
14762 valleyview_modeset_commit_cdclk;
14763 dev_priv->display.modeset_calc_cdclk =
14764 valleyview_modeset_calc_cdclk;
f8437dd1 14765 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14766 dev_priv->display.modeset_commit_cdclk =
14767 broxton_modeset_commit_cdclk;
14768 dev_priv->display.modeset_calc_cdclk =
14769 broxton_modeset_calc_cdclk;
e70236a8 14770 }
8c9f3aaf 14771
8c9f3aaf
JB		 14772 switch (INTEL_INFO(dev)->gen) {
14773 case 2:
14774 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14775 break;
14776
14777 case 3:
14778 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14779 break;
14780
14781 case 4:
14782 case 5:
14783 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14784 break;
14785
14786 case 6:
14787 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14788 break;
7c9017e5 14789 case 7:
4e0bbc31 14790 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14791 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14792 break;
830c81db 14793 case 9:
ba343e02
TU		 14794 /* Drop through - unsupported since execlist only. */
14795 default:
14796 /* Default just returns -ENODEV to indicate unsupported */
14797 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14798 }
7bd688cd
JN		 14799
14800 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14801
14802 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14803}
14804
b690e96c
JB		 14805/*
14806 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14807 * resume, or other times. This quirk makes sure that's the case for
14808 * affected systems.
14809 */
0206e353 14810static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14811{
14812 struct drm_i915_private *dev_priv = dev->dev_private;
14813
14814 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14815 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14816}
14817
b6b5d049
VS		 14818static void quirk_pipeb_force(struct drm_device *dev)
14819{
14820 struct drm_i915_private *dev_priv = dev->dev_private;
14821
14822 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14823 DRM_INFO("applying pipe b force quirk\n");
14824}
14825
435793df
KP		 14826/*
14827 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14828 */
14829static void quirk_ssc_force_disable(struct drm_device *dev)
14830{
14831 struct drm_i915_private *dev_priv = dev->dev_private;
14832 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14833 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14834}
14835
4dca20ef 14836/*
5a15ab5b
CE		 14837 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14838 * brightness value
4dca20ef
CE		 14839 */
14840static void quirk_invert_brightness(struct drm_device *dev)
14841{
14842 struct drm_i915_private *dev_priv = dev->dev_private;
14843 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14844 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14845}
14846
9c72cc6f
SD		 14847/* Some VBT's incorrectly indicate no backlight is present */
14848static void quirk_backlight_present(struct drm_device *dev)
14849{
14850 struct drm_i915_private *dev_priv = dev->dev_private;
14851 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14852 DRM_INFO("applying backlight present quirk\n");
14853}
14854
b690e96c
JB		 14855struct intel_quirk {
14856 int device;
14857 int subsystem_vendor;
14858 int subsystem_device;
14859 void (*hook)(struct drm_device *dev);
14860};
14861
5f85f176
EE		 14862/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14863struct intel_dmi_quirk {
14864 void (*hook)(struct drm_device *dev);
14865 const struct dmi_system_id (*dmi_id_list)[];
14866};
14867
14868static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14869{
14870 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14871 return 1;
14872}
14873
14874static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14875 {
14876 .dmi_id_list = &(const struct dmi_system_id[]) {
14877 {
14878 .callback = intel_dmi_reverse_brightness,
14879 .ident = "NCR Corporation",
14880 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14881 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14882 },
14883 },
14884 { } /* terminating entry */
14885 },
14886 .hook = quirk_invert_brightness,
14887 },
14888};
14889
c43b5634 14890static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14891 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14892 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14893
b690e96c
JB		 14894 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14895 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14896
5f080c0f
VS		 14897 /* 830 needs to leave pipe A & dpll A up */
14898 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14899
b6b5d049
VS		 14900 /* 830 needs to leave pipe B & dpll B up */
14901 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14902
435793df
KP		 14903 /* Lenovo U160 cannot use SSC on LVDS */
14904 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14905
14906 /* Sony Vaio Y cannot use SSC on LVDS */
14907 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14908
be505f64
AH		 14909 /* Acer Aspire 5734Z must invert backlight brightness */
14910 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14911
14912 /* Acer/eMachines G725 */
14913 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14914
14915 /* Acer/eMachines e725 */
14916 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14917
14918 /* Acer/Packard Bell NCL20 */
14919 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14920
14921 /* Acer Aspire 4736Z */
14922 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14923
14924 /* Acer Aspire 5336 */
14925 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14926
14927 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14928 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14929
dfb3d47b
SD		 14930 /* Acer C720 Chromebook (Core i3 4005U) */
14931 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14932
b2a9601c 14933 /* Apple Macbook 2,1 (Core 2 T7400) */
14934 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14935
d4967d8c
SD		 14936 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14937 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14938
14939 /* HP Chromebook 14 (Celeron 2955U) */
14940 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14941
14942 /* Dell Chromebook 11 */
14943 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14944};
14945
14946static void intel_init_quirks(struct drm_device *dev)
14947{
14948 struct pci_dev *d = dev->pdev;
14949 int i;
14950
14951 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14952 struct intel_quirk *q = &intel_quirks[i];
14953
14954 if (d->device == q->device &&
14955 (d->subsystem_vendor == q->subsystem_vendor ||
14956 q->subsystem_vendor == PCI_ANY_ID) &&
14957 (d->subsystem_device == q->subsystem_device ||
14958 q->subsystem_device == PCI_ANY_ID))
14959 q->hook(dev);
14960 }
5f85f176
EE		 14961 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14962 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14963 intel_dmi_quirks[i].hook(dev);
14964 }
b690e96c
JB		 14965}
14966
9cce37f4
JB		 14967/* Disable the VGA plane that we never use */
14968static void i915_disable_vga(struct drm_device *dev)
14969{
14970 struct drm_i915_private *dev_priv = dev->dev_private;
14971 u8 sr1;
766aa1c4 14972 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14973
2b37c616 14974 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14975 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14976 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14977 sr1 = inb(VGA_SR_DATA);
14978 outb(sr1 | 1<<5, VGA_SR_DATA);
14979 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14980 udelay(300);
14981
01f5a626 14982 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14983 POSTING_READ(vga_reg);
14984}
14985
f817586c
DV		 14986void intel_modeset_init_hw(struct drm_device *dev)
14987{
b6283055 14988 intel_update_cdclk(dev);
a8f78b58 14989 intel_prepare_ddi(dev);
f817586c 14990 intel_init_clock_gating(dev);
8090c6b9 14991 intel_enable_gt_powersave(dev);
f817586c
DV		 14992}
14993
79e53945
JB		 14994void intel_modeset_init(struct drm_device *dev)
14995{
652c393a 14996 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14997 int sprite, ret;
8cc87b75 14998 enum pipe pipe;
46f297fb 14999 struct intel_crtc *crtc;
79e53945
JB		 15000
15001 drm_mode_config_init(dev);
15002
15003 dev->mode_config.min_width = 0;
15004 dev->mode_config.min_height = 0;
15005
019d96cb
DA		 15006 dev->mode_config.preferred_depth = 24;
15007 dev->mode_config.prefer_shadow = 1;
15008
25bab385
TU		 15009 dev->mode_config.allow_fb_modifiers = true;
15010
e6ecefaa 15011 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15012
b690e96c
JB		 15013 intel_init_quirks(dev);
15014
1fa61106
ED		 15015 intel_init_pm(dev);
15016
e3c74757
BW		 15017 if (INTEL_INFO(dev)->num_pipes == 0)
15018 return;
15019
e70236a8 15020 intel_init_display(dev);
7c10a2b5 15021 intel_init_audio(dev);
e70236a8 15022
a6c45cf0
CW		 15023 if (IS_GEN2(dev)) {
15024 dev->mode_config.max_width = 2048;
15025 dev->mode_config.max_height = 2048;
15026 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15027 dev->mode_config.max_width = 4096;
15028 dev->mode_config.max_height = 4096;
79e53945 15029 } else {
a6c45cf0
CW		 15030 dev->mode_config.max_width = 8192;
15031 dev->mode_config.max_height = 8192;
79e53945 15032 }
068be561 15033
dc41c154
VS		 15034 if (IS_845G(dev) || IS_I865G(dev)) {
15035 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15036 dev->mode_config.cursor_height = 1023;
15037 } else if (IS_GEN2(dev)) {
068be561
DL		 15038 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15039 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15040 } else {
15041 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15042 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15043 }
15044
5d4545ae 15045 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15046
28c97730 15047 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15048 INTEL_INFO(dev)->num_pipes,
15049 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15050
055e393f 15051 for_each_pipe(dev_priv, pipe) {
8cc87b75 15052 intel_crtc_init(dev, pipe);
3bdcfc0c 15053 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15054 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15055 if (ret)
06da8da2 15056 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15057 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15058 }
79e53945
JB		 15059 }
15060
f42bb70d
JB		 15061 intel_init_dpio(dev);
15062
e72f9fbf 15063 intel_shared_dpll_init(dev);
ee7b9f93 15064
9cce37f4
JB		 15065 /* Just disable it once at startup */
15066 i915_disable_vga(dev);
79e53945 15067 intel_setup_outputs(dev);
11be49eb
CW		 15068
15069 /* Just in case the BIOS is doing something questionable. */
7733b49b 15070 intel_fbc_disable(dev_priv);
fa9fa083 15071
6e9f798d 15072 drm_modeset_lock_all(dev);
fa9fa083 15073 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15074 drm_modeset_unlock_all(dev);
46f297fb 15075
d3fcc808 15076 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15077 if (!crtc->active)
15078 continue;
15079
46f297fb 15080 /*
46f297fb
JB		 15081 * Note that reserving the BIOS fb up front prevents us
15082 * from stuffing other stolen allocations like the ring
15083 * on top. This prevents some ugliness at boot time, and
15084 * can even allow for smooth boot transitions if the BIOS
15085 * fb is large enough for the active pipe configuration.
15086 */
5724dbd1
DL		 15087 if (dev_priv->display.get_initial_plane_config) {
15088 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15089 &crtc->plane_config);
15090 /*
15091 * If the fb is shared between multiple heads, we'll
15092 * just get the first one.
15093 */
f6936e29 15094 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15095 }
46f297fb 15096 }
2c7111db
CW		 15097}
15098
7fad798e
DV		 15099static void intel_enable_pipe_a(struct drm_device *dev)
15100{
15101 struct intel_connector *connector;
15102 struct drm_connector *crt = NULL;
15103 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15104 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15105
15106 /* We can't just switch on the pipe A, we need to set things up with a
15107 * proper mode and output configuration. As a gross hack, enable pipe A
15108 * by enabling the load detect pipe once. */
3a3371ff 15109 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15110 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15111 crt = &connector->base;
15112 break;
15113 }
15114 }
15115
15116 if (!crt)
15117 return;
15118
208bf9fd 15119 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15120 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15121}
15122
fa555837
DV		 15123static bool
15124intel_check_plane_mapping(struct intel_crtc *crtc)
15125{
7eb552ae
BW		 15126 struct drm_device *dev = crtc->base.dev;
15127 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15128 u32 reg, val;
15129
7eb552ae 15130 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15131 return true;
15132
15133 reg = DSPCNTR(!crtc->plane);
15134 val = I915_READ(reg);
15135
15136 if ((val & DISPLAY_PLANE_ENABLE) &&
15137 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15138 return false;
15139
15140 return true;
15141}
15142
24929352
DV		 15143static void intel_sanitize_crtc(struct intel_crtc *crtc)
15144{
15145 struct drm_device *dev = crtc->base.dev;
15146 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 15147 struct intel_encoder *encoder;
fa555837 15148 u32 reg;
b17d48e2 15149 bool enable;
24929352 15150
24929352 15151 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15152 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15153 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15154
d3eaf884 15155 /* restore vblank interrupts to correct state */
9625604c 15156 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15157 if (crtc->active) {
15158 update_scanline_offset(crtc);
9625604c
DV		 15159 drm_crtc_vblank_on(&crtc->base);
15160 }
d3eaf884 15161
24929352 15162 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15163 * disable the crtc (and hence change the state) if it is wrong. Note
15164 * that gen4+ has a fixed plane -> pipe mapping. */
15165 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15166 bool plane;
15167
24929352
DV		 15168 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15169 crtc->base.base.id);
15170
15171 /* Pipe has the wrong plane attached and the plane is active.
15172 * Temporarily change the plane mapping and disable everything
15173 * ... */
15174 plane = crtc->plane;
b70709a6 15175 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15176 crtc->plane = !plane;
b17d48e2 15177 intel_crtc_disable_noatomic(&crtc->base);
24929352 15178 crtc->plane = plane;
24929352 15179 }
24929352 15180
7fad798e
DV		 15181 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15182 crtc->pipe == PIPE_A && !crtc->active) {
15183 /* BIOS forgot to enable pipe A, this mostly happens after
15184 * resume. Force-enable the pipe to fix this, the update_dpms
15185 * call below we restore the pipe to the right state, but leave
15186 * the required bits on. */
15187 intel_enable_pipe_a(dev);
15188 }
15189
24929352
DV		 15190 /* Adjust the state of the output pipe according to whether we
15191 * have active connectors/encoders. */
b17d48e2
ML		 15192 enable = false;
15193 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15194 enable |= encoder->connectors_active;
24929352 15195
b17d48e2
ML		 15196 if (!enable)
15197 intel_crtc_disable_noatomic(&crtc->base);
24929352 15198
53d9f4e9 15199 if (crtc->active != crtc->base.state->active) {
24929352
DV		 15200
15201 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15202 * functions or because of calls to intel_crtc_disable_noatomic,
15203 * or because the pipe is force-enabled due to the
24929352
DV		 15204 * pipe A quirk. */
15205 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15206 crtc->base.base.id,
83d65738 15207 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15208 crtc->active ? "enabled" : "disabled");
15209
83d65738 15210 crtc->base.state->enable = crtc->active;
49d6fa21 15211 crtc->base.state->active = crtc->active;
24929352
DV		 15212 crtc->base.enabled = crtc->active;
15213
15214 /* Because we only establish the connector -> encoder ->
15215 * crtc links if something is active, this means the
15216 * crtc is now deactivated. Break the links. connector
15217 * -> encoder links are only establish when things are
15218 * actually up, hence no need to break them. */
15219 WARN_ON(crtc->active);
15220
15221 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15222 WARN_ON(encoder->connectors_active);
15223 encoder->base.crtc = NULL;
15224 }
15225 }
c5ab3bc0 15226
a3ed6aad 15227 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15228 /*
15229 * We start out with underrun reporting disabled to avoid races.
15230 * For correct bookkeeping mark this on active crtcs.
15231 *
c5ab3bc0
DV		 15232 * Also on gmch platforms we dont have any hardware bits to
15233 * disable the underrun reporting. Which means we need to start
15234 * out with underrun reporting disabled also on inactive pipes,
15235 * since otherwise we'll complain about the garbage we read when
15236 * e.g. coming up after runtime pm.
15237 *
4cc31489
DV		 15238 * No protection against concurrent access is required - at
15239 * worst a fifo underrun happens which also sets this to false.
15240 */
15241 crtc->cpu_fifo_underrun_disabled = true;
15242 crtc->pch_fifo_underrun_disabled = true;
15243 }
24929352
DV		 15244}
15245
15246static void intel_sanitize_encoder(struct intel_encoder *encoder)
15247{
15248 struct intel_connector *connector;
15249 struct drm_device *dev = encoder->base.dev;
15250
15251 /* We need to check both for a crtc link (meaning that the
15252 * encoder is active and trying to read from a pipe) and the
15253 * pipe itself being active. */
15254 bool has_active_crtc = encoder->base.crtc &&
15255 to_intel_crtc(encoder->base.crtc)->active;
15256
15257 if (encoder->connectors_active && !has_active_crtc) {
15258 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15259 encoder->base.base.id,
8e329a03 15260 encoder->base.name);
24929352
DV		 15261
15262 /* Connector is active, but has no active pipe. This is
15263 * fallout from our resume register restoring. Disable
15264 * the encoder manually again. */
15265 if (encoder->base.crtc) {
15266 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15267 encoder->base.base.id,
8e329a03 15268 encoder->base.name);
24929352 15269 encoder->disable(encoder);
a62d1497
VS		 15270 if (encoder->post_disable)
15271 encoder->post_disable(encoder);
24929352 15272 }
7f1950fb
EE		 15273 encoder->base.crtc = NULL;
15274 encoder->connectors_active = false;
24929352
DV		 15275
15276 /* Inconsistent output/port/pipe state happens presumably due to
15277 * a bug in one of the get_hw_state functions. Or someplace else
15278 * in our code, like the register restore mess on resume. Clamp
15279 * things to off as a safer default. */
3a3371ff 15280 for_each_intel_connector(dev, connector) {
24929352
DV		 15281 if (connector->encoder != encoder)
15282 continue;
7f1950fb
EE		 15283 connector->base.dpms = DRM_MODE_DPMS_OFF;
15284 connector->base.encoder = NULL;
24929352
DV		 15285 }
15286 }
15287 /* Enabled encoders without active connectors will be fixed in
15288 * the crtc fixup. */
15289}
15290
04098753 15291void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15292{
15293 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15294 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15295
04098753
ID		 15296 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15297 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15298 i915_disable_vga(dev);
15299 }
15300}
15301
15302void i915_redisable_vga(struct drm_device *dev)
15303{
15304 struct drm_i915_private *dev_priv = dev->dev_private;
15305
8dc8a27c
PZ		 15306 /* This function can be called both from intel_modeset_setup_hw_state or
15307 * at a very early point in our resume sequence, where the power well
15308 * structures are not yet restored. Since this function is at a very
15309 * paranoid "someone might have enabled VGA while we were not looking"
15310 * level, just check if the power well is enabled instead of trying to
15311 * follow the "don't touch the power well if we don't need it" policy
15312 * the rest of the driver uses. */
f458ebbc 15313 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15314 return;
15315
04098753 15316 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15317}
15318
98ec7739
VS		 15319static bool primary_get_hw_state(struct intel_crtc *crtc)
15320{
15321 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15322
d032ffa0
ML		 15323 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15324}
15325
15326static void readout_plane_state(struct intel_crtc *crtc,
15327 struct intel_crtc_state *crtc_state)
15328{
15329 struct intel_plane *p;
15330 struct drm_plane_state *drm_plane_state;
15331 bool active = crtc_state->base.active;
15332
15333 if (active) {
15334 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15335
15336 /* apply to previous sw state too */
15337 to_intel_crtc_state(crtc->base.state)->quirks |=
15338 PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15339 }
98ec7739 15340
d032ffa0
ML		 15341 for_each_intel_plane(crtc->base.dev, p) {
15342 bool visible = active;
15343
15344 if (crtc->pipe != p->pipe)
15345 continue;
15346
15347 drm_plane_state = p->base.state;
15348 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15349 visible = primary_get_hw_state(crtc);
15350 to_intel_plane_state(drm_plane_state)->visible = visible;
15351 } else {
15352 /*
15353 * unknown state, assume it's off to force a transition
15354 * to on when calculating state changes.
15355 */
15356 to_intel_plane_state(drm_plane_state)->visible = false;
15357 }
15358
15359 if (visible) {
15360 crtc_state->base.plane_mask |=
15361 1 << drm_plane_index(&p->base);
15362 } else if (crtc_state->base.state) {
15363 /* Make this unconditional for atomic hw readout. */
15364 crtc_state->base.plane_mask &=
15365 ~(1 << drm_plane_index(&p->base));
15366 }
15367 }
98ec7739
VS		 15368}
15369
30e984df 15370static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15371{
15372 struct drm_i915_private *dev_priv = dev->dev_private;
15373 enum pipe pipe;
24929352
DV		 15374 struct intel_crtc *crtc;
15375 struct intel_encoder *encoder;
15376 struct intel_connector *connector;
5358901f 15377 int i;
24929352 15378
d3fcc808 15379 for_each_intel_crtc(dev, crtc) {
6e3c9717 15380 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15381 crtc->config->base.crtc = &crtc->base;
3b117c8f 15382
6e3c9717 15383 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15384
0e8ffe1b 15385 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15386 crtc->config);
24929352 15387
83d65738 15388 crtc->base.state->enable = crtc->active;
49d6fa21 15389 crtc->base.state->active = crtc->active;
24929352 15390 crtc->base.enabled = crtc->active;
b8b7fade 15391 crtc->base.hwmode = crtc->config->base.adjusted_mode;
b70709a6 15392
d032ffa0 15393 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15394
15395 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15396 crtc->base.base.id,
15397 crtc->active ? "enabled" : "disabled");
15398 }
15399
5358901f
DV		 15400 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15401 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15402
3e369b76
ACO		 15403 pll->on = pll->get_hw_state(dev_priv, pll,
15404 &pll->config.hw_state);
5358901f 15405 pll->active = 0;
3e369b76 15406 pll->config.crtc_mask = 0;
d3fcc808 15407 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15408 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15409 pll->active++;
3e369b76 15410 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15411 }
5358901f 15412 }
5358901f 15413
1e6f2ddc 15414 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15415 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15416
3e369b76 15417 if (pll->config.crtc_mask)
bd2bb1b9 15418 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15419 }
15420
b2784e15 15421 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15422 pipe = 0;
15423
15424 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15425 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15426 encoder->base.crtc = &crtc->base;
6e3c9717 15427 encoder->get_config(encoder, crtc->config);
24929352
DV		 15428 } else {
15429 encoder->base.crtc = NULL;
15430 }
15431
15432 encoder->connectors_active = false;
6f2bcceb 15433 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15434 encoder->base.base.id,
8e329a03 15435 encoder->base.name,
24929352 15436 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15437 pipe_name(pipe));
24929352
DV		 15438 }
15439
3a3371ff 15440 for_each_intel_connector(dev, connector) {
24929352
DV		 15441 if (connector->get_hw_state(connector)) {
15442 connector->base.dpms = DRM_MODE_DPMS_ON;
15443 connector->encoder->connectors_active = true;
15444 connector->base.encoder = &connector->encoder->base;
15445 } else {
15446 connector->base.dpms = DRM_MODE_DPMS_OFF;
15447 connector->base.encoder = NULL;
15448 }
15449 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15450 connector->base.base.id,
c23cc417 15451 connector->base.name,
24929352
DV		 15452 connector->base.encoder ? "enabled" : "disabled");
15453 }
30e984df
DV		 15454}
15455
15456/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15457 * and i915 state tracking structures. */
15458void intel_modeset_setup_hw_state(struct drm_device *dev,
15459 bool force_restore)
15460{
15461 struct drm_i915_private *dev_priv = dev->dev_private;
15462 enum pipe pipe;
30e984df
DV		 15463 struct intel_crtc *crtc;
15464 struct intel_encoder *encoder;
35c95375 15465 int i;
30e984df
DV		 15466
15467 intel_modeset_readout_hw_state(dev);
24929352 15468
babea61d
JB		 15469 /*
15470 * Now that we have the config, copy it to each CRTC struct
15471 * Note that this could go away if we move to using crtc_config
15472 * checking everywhere.
15473 */
d3fcc808 15474 for_each_intel_crtc(dev, crtc) {
d330a953 15475 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15476 intel_mode_from_pipe_config(&crtc->base.mode,
15477 crtc->config);
babea61d
JB		 15478 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15479 crtc->base.base.id);
15480 drm_mode_debug_printmodeline(&crtc->base.mode);
15481 }
15482 }
15483
24929352 15484 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15485 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15486 intel_sanitize_encoder(encoder);
15487 }
15488
055e393f 15489 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15490 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15491 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15492 intel_dump_pipe_config(crtc, crtc->config,
15493 "[setup_hw_state]");
24929352 15494 }
9a935856 15495
d29b2f9d
ACO		 15496 intel_modeset_update_connector_atomic_state(dev);
15497
35c95375
DV		 15498 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15499 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15500
15501 if (!pll->on || pll->active)
15502 continue;
15503
15504 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15505
15506 pll->disable(dev_priv, pll);
15507 pll->on = false;
15508 }
15509
26e1fe4f 15510 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15511 vlv_wm_get_hw_state(dev);
15512 else if (IS_GEN9(dev))
3078999f
PB		 15513 skl_wm_get_hw_state(dev);
15514 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15515 ilk_wm_get_hw_state(dev);
15516
45e2b5f6 15517 if (force_restore) {
7d0bc1ea
VS		 15518 i915_redisable_vga(dev);
15519
f30da187
DV		 15520 /*
15521 * We need to use raw interfaces for restoring state to avoid
15522 * checking (bogus) intermediate states.
15523 */
055e393f 15524 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15525 struct drm_crtc *crtc =
15526 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15527
83a57153 15528 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15529 }
15530 } else {
15531 intel_modeset_update_staged_output_state(dev);
15532 }
8af6cf88
DV		 15533
15534 intel_modeset_check_state(dev);
2c7111db
CW		 15535}
15536
15537void intel_modeset_gem_init(struct drm_device *dev)
15538{
92122789 15539 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15540 struct drm_crtc *c;
2ff8fde1 15541 struct drm_i915_gem_object *obj;
e0d6149b 15542 int ret;
484b41dd 15543
ae48434c
ID		 15544 mutex_lock(&dev->struct_mutex);
15545 intel_init_gt_powersave(dev);
15546 mutex_unlock(&dev->struct_mutex);
15547
92122789
JB		 15548 /*
15549 * There may be no VBT; and if the BIOS enabled SSC we can
15550 * just keep using it to avoid unnecessary flicker. Whereas if the
15551 * BIOS isn't using it, don't assume it will work even if the VBT
15552 * indicates as much.
15553 */
15554 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15555 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15556 DREF_SSC1_ENABLE);
15557
1833b134 15558 intel_modeset_init_hw(dev);
02e792fb
DV		 15559
15560 intel_setup_overlay(dev);
484b41dd
JB		 15561
15562 /*
15563 * Make sure any fbs we allocated at startup are properly
15564 * pinned & fenced. When we do the allocation it's too early
15565 * for this.
15566 */
70e1e0ec 15567 for_each_crtc(dev, c) {
2ff8fde1
MR		 15568 obj = intel_fb_obj(c->primary->fb);
15569 if (obj == NULL)
484b41dd
JB		 15570 continue;
15571
e0d6149b
TU		 15572 mutex_lock(&dev->struct_mutex);
15573 ret = intel_pin_and_fence_fb_obj(c->primary,
15574 c->primary->fb,
15575 c->primary->state,
91af127f 15576 NULL, NULL);
e0d6149b
TU		 15577 mutex_unlock(&dev->struct_mutex);
15578 if (ret) {
484b41dd
JB		 15579 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15580 to_intel_crtc(c)->pipe);
66e514c1
DA		 15581 drm_framebuffer_unreference(c->primary->fb);
15582 c->primary->fb = NULL;
36750f28 15583 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15584 update_state_fb(c->primary);
36750f28 15585 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15586 }
15587 }
0962c3c9
VS		 15588
15589 intel_backlight_register(dev);
79e53945
JB		 15590}
15591
4932e2c3
ID		 15592void intel_connector_unregister(struct intel_connector *intel_connector)
15593{
15594 struct drm_connector *connector = &intel_connector->base;
15595
15596 intel_panel_destroy_backlight(connector);
34ea3d38 15597 drm_connector_unregister(connector);
4932e2c3
ID		 15598}
15599
79e53945
JB		 15600void intel_modeset_cleanup(struct drm_device *dev)
15601{
652c393a 15602 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15603 struct drm_connector *connector;
652c393a 15604
2eb5252e
ID		 15605 intel_disable_gt_powersave(dev);
15606
0962c3c9
VS		 15607 intel_backlight_unregister(dev);
15608
fd0c0642
DV		 15609 /*
15610 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15611 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15612 * experience fancy races otherwise.
15613 */
2aeb7d3a 15614 intel_irq_uninstall(dev_priv);
eb21b92b 15615
fd0c0642
DV		 15616 /*
15617 * Due to the hpd irq storm handling the hotplug work can re-arm the
15618 * poll handlers. Hence disable polling after hpd handling is shut down.
15619 */
f87ea761 15620 drm_kms_helper_poll_fini(dev);
fd0c0642 15621
723bfd70
JB		 15622 intel_unregister_dsm_handler();
15623
7733b49b 15624 intel_fbc_disable(dev_priv);
69341a5e 15625
1630fe75
CW		 15626 /* flush any delayed tasks or pending work */
15627 flush_scheduled_work();
15628
db31af1d
JN		 15629 /* destroy the backlight and sysfs files before encoders/connectors */
15630 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15631 struct intel_connector *intel_connector;
15632
15633 intel_connector = to_intel_connector(connector);
15634 intel_connector->unregister(intel_connector);
db31af1d 15635 }
d9255d57 15636
79e53945 15637 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15638
15639 intel_cleanup_overlay(dev);
ae48434c
ID		 15640
15641 mutex_lock(&dev->struct_mutex);
15642 intel_cleanup_gt_powersave(dev);
15643 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15644}
15645
f1c79df3
ZW		 15646/*
15647 * Return which encoder is currently attached for connector.
15648 */
df0e9248 15649struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15650{
df0e9248
CW		 15651 return &intel_attached_encoder(connector)->base;
15652}
f1c79df3 15653
df0e9248
CW		 15654void intel_connector_attach_encoder(struct intel_connector *connector,
15655 struct intel_encoder *encoder)
15656{
15657 connector->encoder = encoder;
15658 drm_mode_connector_attach_encoder(&connector->base,
15659 &encoder->base);
79e53945 15660}
28d52043
DA		 15661
15662/*
15663 * set vga decode state - true == enable VGA decode
15664 */
15665int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15666{
15667 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15668 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15669 u16 gmch_ctrl;
15670
75fa041d
CW		 15671 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15672 DRM_ERROR("failed to read control word\n");
15673 return -EIO;
15674 }
15675
c0cc8a55
CW		 15676 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15677 return 0;
15678
28d52043
DA		 15679 if (state)
15680 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15681 else
15682 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15683
15684 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15685 DRM_ERROR("failed to write control word\n");
15686 return -EIO;
15687 }
15688
28d52043
DA		 15689 return 0;
15690}
c4a1d9e4 15691
c4a1d9e4 15692struct intel_display_error_state {
ff57f1b0
PZ		 15693
15694 u32 power_well_driver;
15695
63b66e5b
CW		 15696 int num_transcoders;
15697
c4a1d9e4
CW		 15698 struct intel_cursor_error_state {
15699 u32 control;
15700 u32 position;
15701 u32 base;
15702 u32 size;
52331309 15703 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15704
15705 struct intel_pipe_error_state {
ddf9c536 15706 bool power_domain_on;
c4a1d9e4 15707 u32 source;
f301b1e1 15708 u32 stat;
52331309 15709 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15710
15711 struct intel_plane_error_state {
15712 u32 control;
15713 u32 stride;
15714 u32 size;
15715 u32 pos;
15716 u32 addr;
15717 u32 surface;
15718 u32 tile_offset;
52331309 15719 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15720
15721 struct intel_transcoder_error_state {
ddf9c536 15722 bool power_domain_on;
63b66e5b
CW		 15723 enum transcoder cpu_transcoder;
15724
15725 u32 conf;
15726
15727 u32 htotal;
15728 u32 hblank;
15729 u32 hsync;
15730 u32 vtotal;
15731 u32 vblank;
15732 u32 vsync;
15733 } transcoder[4];
c4a1d9e4
CW		 15734};
15735
15736struct intel_display_error_state *
15737intel_display_capture_error_state(struct drm_device *dev)
15738{
fbee40df 15739 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15740 struct intel_display_error_state *error;
63b66e5b
CW		 15741 int transcoders[] = {
15742 TRANSCODER_A,
15743 TRANSCODER_B,
15744 TRANSCODER_C,
15745 TRANSCODER_EDP,
15746 };
c4a1d9e4
CW		 15747 int i;
15748
63b66e5b
CW		 15749 if (INTEL_INFO(dev)->num_pipes == 0)
15750 return NULL;
15751
9d1cb914 15752 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15753 if (error == NULL)
15754 return NULL;
15755
190be112 15756 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15757 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15758
055e393f 15759 for_each_pipe(dev_priv, i) {
ddf9c536 15760 error->pipe[i].power_domain_on =
f458ebbc
DV		 15761 __intel_display_power_is_enabled(dev_priv,
15762 POWER_DOMAIN_PIPE(i));
ddf9c536 15763 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15764 continue;
15765
5efb3e28
VS		 15766 error->cursor[i].control = I915_READ(CURCNTR(i));
15767 error->cursor[i].position = I915_READ(CURPOS(i));
15768 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15769
15770 error->plane[i].control = I915_READ(DSPCNTR(i));
15771 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15772 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15773 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15774 error->plane[i].pos = I915_READ(DSPPOS(i));
15775 }
ca291363
PZ		 15776 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15777 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15778 if (INTEL_INFO(dev)->gen >= 4) {
15779 error->plane[i].surface = I915_READ(DSPSURF(i));
15780 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15781 }
15782
c4a1d9e4 15783 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15784
3abfce77 15785 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15786 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15787 }
15788
15789 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15790 if (HAS_DDI(dev_priv->dev))
15791 error->num_transcoders++; /* Account for eDP. */
15792
15793 for (i = 0; i < error->num_transcoders; i++) {
15794 enum transcoder cpu_transcoder = transcoders[i];
15795
ddf9c536 15796 error->transcoder[i].power_domain_on =
f458ebbc 15797 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15798 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15799 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15800 continue;
15801
63b66e5b
CW		 15802 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15803
15804 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15805 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15806 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15807 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15808 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15809 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15810 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15811 }
15812
15813 return error;
15814}
15815
edc3d884
MK		 15816#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15817
c4a1d9e4 15818void
edc3d884 15819intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15820 struct drm_device *dev,
15821 struct intel_display_error_state *error)
15822{
055e393f 15823 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15824 int i;
15825
63b66e5b
CW		 15826 if (!error)
15827 return;
15828
edc3d884 15829 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15830 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15831 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15832 error->power_well_driver);
055e393f 15833 for_each_pipe(dev_priv, i) {
edc3d884 15834 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15835 err_printf(m, " Power: %s\n",
15836 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15837 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15838 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15839
15840 err_printf(m, "Plane [%d]:\n", i);
15841 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15842 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15843 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15844 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15845 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15846 }
4b71a570 15847 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15848 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15849 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15850 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15851 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15852 }
15853
edc3d884
MK		 15854 err_printf(m, "Cursor [%d]:\n", i);
15855 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15856 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15857 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15858 }
63b66e5b
CW		 15859
15860 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15861 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15862 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15863 err_printf(m, " Power: %s\n",
15864 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15865 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15866 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15867 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15868 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15869 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15870 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15871 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15872 }
c4a1d9e4 15873}
e2fcdaa9
VS		 15874
15875void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15876{
15877 struct intel_crtc *crtc;
15878
15879 for_each_intel_crtc(dev, crtc) {
15880 struct intel_unpin_work *work;
e2fcdaa9 15881
5e2d7afc 15882 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15883
15884 work = crtc->unpin_work;
15885
15886 if (work && work->event &&
15887 work->event->base.file_priv == file) {
15888 kfree(work->event);
15889 work->event = NULL;
15890 }
15891
5e2d7afc 15892 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15893 }
15894}
Linux kernel - Deliverables
This page took 3.03603 seconds and 5 git commands to generate.