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drm/i915: Update missing properties in find_initial_plane_obj
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
568c634a 89static int intel_set_mode(struct drm_atomic_state *state);
eb1bfe80
JB		 90static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
5b18e57c
DV		 94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
29407aab 99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 102static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
d288f65f 104static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 105 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 106static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 108static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
e7457a9a 112
0e32b39c
DA		 113static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114{
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119}
120
79e53945 121typedef struct {
0206e353 122 int min, max;
79e53945
JB		 123} intel_range_t;
124
125typedef struct {
0206e353
AJ		 126 int dot_limit;
127 int p2_slow, p2_fast;
79e53945
JB		 128} intel_p2_t;
129
d4906093
ML		 130typedef struct intel_limit intel_limit_t;
131struct intel_limit {
0206e353
AJ		 132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
d4906093 134};
79e53945 135
d2acd215
DV		 136int
137intel_pch_rawclk(struct drm_device *dev)
138{
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144}
145
021357ac
CW		 146static inline u32 /* units of 100MHz */
147intel_fdi_link_freq(struct drm_device *dev)
148{
8b99e68c
CW		 149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
021357ac
CW		 154}
155
5d536e28 156static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 157 .dot = { .min = 25000, .max = 350000 },
9c333719 158 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 159 .n = { .min = 2, .max = 16 },
0206e353
AJ		 160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 167};
168
5d536e28
DV		 169static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
9c333719 171 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 172 .n = { .min = 2, .max = 16 },
5d536e28
DV		 173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180};
181
e4b36699 182static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 183 .dot = { .min = 25000, .max = 350000 },
9c333719 184 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 185 .n = { .min = 2, .max = 16 },
0206e353
AJ		 186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
e4b36699 193};
273e27ca 194
e4b36699 195static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 219};
220
273e27ca 221
e4b36699 222static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
044c7c41 234 },
e4b36699
KP		 235};
236
237static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 248};
249
250static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
044c7c41 261 },
e4b36699
KP		 262};
263
264static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
044c7c41 275 },
e4b36699
KP		 276};
277
f2b115e6 278static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 281 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
273e27ca 284 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 291};
292
f2b115e6 293static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 304};
305
273e27ca
EA		 306/* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
b91ad0ec 311static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 322};
323
b91ad0ec 324static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 335};
336
337static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 348};
349
273e27ca 350/* LVDS 100mhz refclk limits. */
b91ad0ec 351static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
0206e353 359 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 362};
363
364static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
0206e353 372 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 375};
376
dc730512 377static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 385 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 386 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
b99ab663 389 .p1 = { .min = 2, .max = 3 },
5fdc9c49 390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 391};
392
ef9348c8
CML		 393static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 401 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407};
408
5ab7b0b7
ID		 409static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
e6292556 412 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419};
420
cdba954e
ACO		 421static bool
422needs_modeset(struct drm_crtc_state *state)
423{
424 return state->mode_changed || state->active_changed;
425}
426
e0638cdf
PZ		 427/**
428 * Returns whether any output on the specified pipe is of the specified type
429 */
4093561b 430bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 431{
409ee761 432 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 433 struct intel_encoder *encoder;
434
409ee761 435 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 436 if (encoder->type == type)
437 return true;
438
439 return false;
440}
441
d0737e1d
ACO		 442/**
443 * Returns whether any output on the specified pipe will have the specified
444 * type after a staged modeset is complete, i.e., the same as
445 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
446 * encoder->crtc.
447 */
a93e255f
ACO		 448static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
449 int type)
d0737e1d 450{
a93e255f 451 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 452 struct drm_connector *connector;
a93e255f 453 struct drm_connector_state *connector_state;
d0737e1d 454 struct intel_encoder *encoder;
a93e255f
ACO		 455 int i, num_connectors = 0;
456
da3ced29 457 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 458 if (connector_state->crtc != crtc_state->base.crtc)
459 continue;
460
461 num_connectors++;
d0737e1d 462
a93e255f
ACO		 463 encoder = to_intel_encoder(connector_state->best_encoder);
464 if (encoder->type == type)
d0737e1d 465 return true;
a93e255f
ACO		 466 }
467
468 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 469
470 return false;
471}
472
a93e255f
ACO		 473static const intel_limit_t *
474intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 475{
a93e255f 476 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 477 const intel_limit_t *limit;
b91ad0ec 478
a93e255f 479 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 480 if (intel_is_dual_link_lvds(dev)) {
1b894b59 481 if (refclk == 100000)
b91ad0ec
ZW		 482 limit = &intel_limits_ironlake_dual_lvds_100m;
483 else
484 limit = &intel_limits_ironlake_dual_lvds;
485 } else {
1b894b59 486 if (refclk == 100000)
b91ad0ec
ZW		 487 limit = &intel_limits_ironlake_single_lvds_100m;
488 else
489 limit = &intel_limits_ironlake_single_lvds;
490 }
c6bb3538 491 } else
b91ad0ec 492 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 493
494 return limit;
495}
496
a93e255f
ACO		 497static const intel_limit_t *
498intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 499{
a93e255f 500 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 501 const intel_limit_t *limit;
502
a93e255f 503 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 504 if (intel_is_dual_link_lvds(dev))
e4b36699 505 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 506 else
e4b36699 507 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 508 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
509 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 510 limit = &intel_limits_g4x_hdmi;
a93e255f 511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 512 limit = &intel_limits_g4x_sdvo;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
a93e255f
ACO		 519static const intel_limit_t *
520intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 521{
a93e255f 522 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 523 const intel_limit_t *limit;
524
5ab7b0b7
ID		 525 if (IS_BROXTON(dev))
526 limit = &intel_limits_bxt;
527 else if (HAS_PCH_SPLIT(dev))
a93e255f 528 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 529 else if (IS_G4X(dev)) {
a93e255f 530 limit = intel_g4x_limit(crtc_state);
f2b115e6 531 } else if (IS_PINEVIEW(dev)) {
a93e255f 532 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 533 limit = &intel_limits_pineview_lvds;
2177832f 534 else
f2b115e6 535 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 536 } else if (IS_CHERRYVIEW(dev)) {
537 limit = &intel_limits_chv;
a0c4da24 538 } else if (IS_VALLEYVIEW(dev)) {
dc730512 539 limit = &intel_limits_vlv;
a6c45cf0 540 } else if (!IS_GEN2(dev)) {
a93e255f 541 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945 545 } else {
a93e255f 546 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
a93e255f 548 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 549 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 550 else
551 limit = &intel_limits_i8xx_dac;
79e53945
JB		 552 }
553 return limit;
554}
555
dccbea3b
ID		 556/*
557 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
558 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
559 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
560 * The helpers' return value is the rate of the clock that is fed to the
561 * display engine's pipe which can be the above fast dot clock rate or a
562 * divided-down version of it.
563 */
f2b115e6 564/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 565static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 566{
2177832f
SL		 567 clock->m = clock->m2 + 2;
568 clock->p = clock->p1 * clock->p2;
ed5ca77e 569 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 570 return 0;
fb03ac01
VS		 571 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
572 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 573
574 return clock->dot;
2177832f
SL		 575}
576
7429e9d4
DV		 577static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
578{
579 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
580}
581
dccbea3b 582static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 583{
7429e9d4 584 clock->m = i9xx_dpll_compute_m(clock);
79e53945 585 clock->p = clock->p1 * clock->p2;
ed5ca77e 586 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 587 return 0;
fb03ac01
VS		 588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 590
591 return clock->dot;
79e53945
JB		 592}
593
dccbea3b 594static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 595{
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 599 return 0;
589eca67
ID		 600 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
601 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 602
603 return clock->dot / 5;
589eca67
ID		 604}
605
dccbea3b 606int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 607{
608 clock->m = clock->m1 * clock->m2;
609 clock->p = clock->p1 * clock->p2;
610 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 611 return 0;
ef9348c8
CML		 612 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
613 clock->n << 22);
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 615
616 return clock->dot / 5;
ef9348c8
CML		 617}
618
7c04d1d9 619#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 620/**
621 * Returns whether the given set of divisors are valid for a given refclk with
622 * the given connectors.
623 */
624
1b894b59
CW		 625static bool intel_PLL_is_valid(struct drm_device *dev,
626 const intel_limit_t *limit,
627 const intel_clock_t *clock)
79e53945 628{
f01b7962
VS		 629 if (clock->n < limit->n.min || limit->n.max < clock->n)
630 INTELPllInvalid("n out of range\n");
79e53945 631 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 632 INTELPllInvalid("p1 out of range\n");
79e53945 633 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 634 INTELPllInvalid("m2 out of range\n");
79e53945 635 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 636 INTELPllInvalid("m1 out of range\n");
f01b7962 637
5ab7b0b7 638 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 639 if (clock->m1 <= clock->m2)
640 INTELPllInvalid("m1 <= m2\n");
641
5ab7b0b7 642 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 643 if (clock->p < limit->p.min || limit->p.max < clock->p)
644 INTELPllInvalid("p out of range\n");
645 if (clock->m < limit->m.min || limit->m.max < clock->m)
646 INTELPllInvalid("m out of range\n");
647 }
648
79e53945 649 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 650 INTELPllInvalid("vco out of range\n");
79e53945
JB		 651 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
652 * connector, etc., rather than just a single range.
653 */
654 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 655 INTELPllInvalid("dot out of range\n");
79e53945
JB		 656
657 return true;
658}
659
3b1429d9
VS		 660static int
661i9xx_select_p2_div(const intel_limit_t *limit,
662 const struct intel_crtc_state *crtc_state,
663 int target)
79e53945 664{
3b1429d9 665 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 666
a93e255f 667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 668 /*
a210b028
DV		 669 * For LVDS just rely on its current settings for dual-channel.
670 * We haven't figured out how to reliably set up different
671 * single/dual channel state, if we even can.
79e53945 672 */
1974cad0 673 if (intel_is_dual_link_lvds(dev))
3b1429d9 674 return limit->p2.p2_fast;
79e53945 675 else
3b1429d9 676 return limit->p2.p2_slow;
79e53945
JB		 677 } else {
678 if (target < limit->p2.dot_limit)
3b1429d9 679 return limit->p2.p2_slow;
79e53945 680 else
3b1429d9 681 return limit->p2.p2_fast;
79e53945 682 }
3b1429d9
VS		 683}
684
685static bool
686i9xx_find_best_dpll(const intel_limit_t *limit,
687 struct intel_crtc_state *crtc_state,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
690{
691 struct drm_device *dev = crtc_state->base.crtc->dev;
692 intel_clock_t clock;
693 int err = target;
79e53945 694
0206e353 695 memset(best_clock, 0, sizeof(*best_clock));
79e53945 696
3b1429d9
VS		 697 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
698
42158660
ZY		 699 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
700 clock.m1++) {
701 for (clock.m2 = limit->m2.min;
702 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 703 if (clock.m2 >= clock.m1)
42158660
ZY		 704 break;
705 for (clock.n = limit->n.min;
706 clock.n <= limit->n.max; clock.n++) {
707 for (clock.p1 = limit->p1.min;
708 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 709 int this_err;
710
dccbea3b 711 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
714 continue;
715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
718
719 this_err = abs(clock.dot - target);
720 if (this_err < err) {
721 *best_clock = clock;
722 err = this_err;
723 }
724 }
725 }
726 }
727 }
728
729 return (err != target);
730}
731
732static bool
a93e255f
ACO		 733pnv_find_best_dpll(const intel_limit_t *limit,
734 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
79e53945 737{
3b1429d9 738 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 739 intel_clock_t clock;
79e53945
JB		 740 int err = target;
741
0206e353 742 memset(best_clock, 0, sizeof(*best_clock));
79e53945 743
3b1429d9
VS		 744 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745
42158660
ZY		 746 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
747 clock.m1++) {
748 for (clock.m2 = limit->m2.min;
749 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 750 for (clock.n = limit->n.min;
751 clock.n <= limit->n.max; clock.n++) {
752 for (clock.p1 = limit->p1.min;
753 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 754 int this_err;
755
dccbea3b 756 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
79e53945 759 continue;
cec2f356
SP		 760 if (match_clock &&
761 clock.p != match_clock->p)
762 continue;
79e53945
JB		 763
764 this_err = abs(clock.dot - target);
765 if (this_err < err) {
766 *best_clock = clock;
767 err = this_err;
768 }
769 }
770 }
771 }
772 }
773
774 return (err != target);
775}
776
d4906093 777static bool
a93e255f
ACO		 778g4x_find_best_dpll(const intel_limit_t *limit,
779 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
d4906093 782{
3b1429d9 783 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 784 intel_clock_t clock;
785 int max_n;
3b1429d9 786 bool found = false;
6ba770dc
AJ		 787 /* approximately equals target * 0.00585 */
788 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 789
790 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 791
792 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
793
d4906093 794 max_n = limit->n.max;
f77f13e2 795 /* based on hardware requirement, prefer smaller n to precision */
d4906093 796 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 797 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 798 for (clock.m1 = limit->m1.max;
799 clock.m1 >= limit->m1.min; clock.m1--) {
800 for (clock.m2 = limit->m2.max;
801 clock.m2 >= limit->m2.min; clock.m2--) {
802 for (clock.p1 = limit->p1.max;
803 clock.p1 >= limit->p1.min; clock.p1--) {
804 int this_err;
805
dccbea3b 806 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 807 if (!intel_PLL_is_valid(dev, limit,
808 &clock))
d4906093 809 continue;
1b894b59
CW		 810
811 this_err = abs(clock.dot - target);
d4906093
ML		 812 if (this_err < err_most) {
813 *best_clock = clock;
814 err_most = this_err;
815 max_n = clock.n;
816 found = true;
817 }
818 }
819 }
820 }
821 }
2c07245f
ZW		 822 return found;
823}
824
d5dd62bd
ID		 825/*
826 * Check if the calculated PLL configuration is more optimal compared to the
827 * best configuration and error found so far. Return the calculated error.
828 */
829static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
830 const intel_clock_t *calculated_clock,
831 const intel_clock_t *best_clock,
832 unsigned int best_error_ppm,
833 unsigned int *error_ppm)
834{
9ca3ba01
ID		 835 /*
836 * For CHV ignore the error and consider only the P value.
837 * Prefer a bigger P value based on HW requirements.
838 */
839 if (IS_CHERRYVIEW(dev)) {
840 *error_ppm = 0;
841
842 return calculated_clock->p > best_clock->p;
843 }
844
24be4e46
ID		 845 if (WARN_ON_ONCE(!target_freq))
846 return false;
847
d5dd62bd
ID		 848 *error_ppm = div_u64(1000000ULL *
849 abs(target_freq - calculated_clock->dot),
850 target_freq);
851 /*
852 * Prefer a better P value over a better (smaller) error if the error
853 * is small. Ensure this preference for future configurations too by
854 * setting the error to 0.
855 */
856 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
857 *error_ppm = 0;
858
859 return true;
860 }
861
862 return *error_ppm + 10 < best_error_ppm;
863}
864
a0c4da24 865static bool
a93e255f
ACO		 866vlv_find_best_dpll(const intel_limit_t *limit,
867 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 868 int target, int refclk, intel_clock_t *match_clock,
869 intel_clock_t *best_clock)
a0c4da24 870{
a93e255f 871 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 872 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 873 intel_clock_t clock;
69e4f900 874 unsigned int bestppm = 1000000;
27e639bf
VS		 875 /* min update 19.2 MHz */
876 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 877 bool found = false;
a0c4da24 878
6b4bf1c4
VS		 879 target *= 5; /* fast clock */
880
881 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 882
883 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 884 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 885 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 886 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 887 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 888 clock.p = clock.p1 * clock.p2;
a0c4da24 889 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 890 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 891 unsigned int ppm;
69e4f900 892
6b4bf1c4
VS		 893 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
894 refclk * clock.m1);
895
dccbea3b 896 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 897
f01b7962
VS		 898 if (!intel_PLL_is_valid(dev, limit,
899 &clock))
43b0ac53
VS		 900 continue;
901
d5dd62bd
ID		 902 if (!vlv_PLL_is_optimal(dev, target,
903 &clock,
904 best_clock,
905 bestppm, &ppm))
906 continue;
6b4bf1c4 907
d5dd62bd
ID		 908 *best_clock = clock;
909 bestppm = ppm;
910 found = true;
a0c4da24
JB		 911 }
912 }
913 }
914 }
a0c4da24 915
49e497ef 916 return found;
a0c4da24 917}
a4fc5ed6 918
ef9348c8 919static bool
a93e255f
ACO		 920chv_find_best_dpll(const intel_limit_t *limit,
921 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 922 int target, int refclk, intel_clock_t *match_clock,
923 intel_clock_t *best_clock)
924{
a93e255f 925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 926 struct drm_device *dev = crtc->base.dev;
9ca3ba01 927 unsigned int best_error_ppm;
ef9348c8
CML		 928 intel_clock_t clock;
929 uint64_t m2;
930 int found = false;
931
932 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 933 best_error_ppm = 1000000;
ef9348c8
CML		 934
935 /*
936 * Based on hardware doc, the n always set to 1, and m1 always
937 * set to 2. If requires to support 200Mhz refclk, we need to
938 * revisit this because n may not 1 anymore.
939 */
940 clock.n = 1, clock.m1 = 2;
941 target *= 5; /* fast clock */
942
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
944 for (clock.p2 = limit->p2.p2_fast;
945 clock.p2 >= limit->p2.p2_slow;
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 947 unsigned int error_ppm;
ef9348c8
CML		 948
949 clock.p = clock.p1 * clock.p2;
950
951 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
952 clock.n) << 22, refclk * clock.m1);
953
954 if (m2 > INT_MAX/clock.m1)
955 continue;
956
957 clock.m2 = m2;
958
dccbea3b 959 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 960
961 if (!intel_PLL_is_valid(dev, limit, &clock))
962 continue;
963
9ca3ba01
ID		 964 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
965 best_error_ppm, &error_ppm))
966 continue;
967
968 *best_clock = clock;
969 best_error_ppm = error_ppm;
970 found = true;
ef9348c8
CML		 971 }
972 }
973
974 return found;
975}
976
5ab7b0b7
ID		 977bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
978 intel_clock_t *best_clock)
979{
980 int refclk = i9xx_get_refclk(crtc_state, 0);
981
982 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
983 target_clock, refclk, NULL, best_clock);
984}
985
20ddf665
VS		 986bool intel_crtc_active(struct drm_crtc *crtc)
987{
988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
989
990 /* Be paranoid as we can arrive here with only partial
991 * state retrieved from the hardware during setup.
992 *
241bfc38 993 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 994 * as Haswell has gained clock readout/fastboot support.
995 *
66e514c1 996 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 997 * properly reconstruct framebuffers.
c3d1f436
MR		 998 *
999 * FIXME: The intel_crtc->active here should be switched to
1000 * crtc->state->active once we have proper CRTC states wired up
1001 * for atomic.
20ddf665 1002 */
c3d1f436 1003 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1004 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1005}
1006
a5c961d1
PZ		 1007enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1008 enum pipe pipe)
1009{
1010 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1012
6e3c9717 1013 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1014}
1015
fbf49ea2
VS		 1016static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1017{
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 reg = PIPEDSL(pipe);
1020 u32 line1, line2;
1021 u32 line_mask;
1022
1023 if (IS_GEN2(dev))
1024 line_mask = DSL_LINEMASK_GEN2;
1025 else
1026 line_mask = DSL_LINEMASK_GEN3;
1027
1028 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1029 msleep(5);
fbf49ea2
VS		 1030 line2 = I915_READ(reg) & line_mask;
1031
1032 return line1 == line2;
1033}
1034
ab7ad7f6
KP		 1035/*
1036 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1037 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1038 *
1039 * After disabling a pipe, we can't wait for vblank in the usual way,
1040 * spinning on the vblank interrupt status bit, since we won't actually
1041 * see an interrupt when the pipe is disabled.
1042 *
ab7ad7f6
KP		 1043 * On Gen4 and above:
1044 * wait for the pipe register state bit to turn off
1045 *
1046 * Otherwise:
1047 * wait for the display line value to settle (it usually
1048 * ends up stopping at the start of the next frame).
58e10eb9 1049 *
9d0498a2 1050 */
575f7ab7 1051static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1052{
575f7ab7 1053 struct drm_device *dev = crtc->base.dev;
9d0498a2 1054 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1055 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1056 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1057
1058 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1059 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1060
1061 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1062 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1063 100))
284637d9 1064 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1065 } else {
ab7ad7f6 1066 /* Wait for the display line to settle */
fbf49ea2 1067 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1068 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1069 }
79e53945
JB		 1070}
1071
b0ea7d37
DL		 1072/*
1073 * ibx_digital_port_connected - is the specified port connected?
1074 * @dev_priv: i915 private structure
1075 * @port: the port to test
1076 *
1077 * Returns true if @port is connected, false otherwise.
1078 */
1079bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1080 struct intel_digital_port *port)
1081{
1082 u32 bit;
1083
c36346e3 1084 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1085 switch (port->port) {
c36346e3
DL		 1086 case PORT_B:
1087 bit = SDE_PORTB_HOTPLUG;
1088 break;
1089 case PORT_C:
1090 bit = SDE_PORTC_HOTPLUG;
1091 break;
1092 case PORT_D:
1093 bit = SDE_PORTD_HOTPLUG;
1094 break;
1095 default:
1096 return true;
1097 }
1098 } else {
eba905b2 1099 switch (port->port) {
c36346e3
DL		 1100 case PORT_B:
1101 bit = SDE_PORTB_HOTPLUG_CPT;
1102 break;
1103 case PORT_C:
1104 bit = SDE_PORTC_HOTPLUG_CPT;
1105 break;
1106 case PORT_D:
1107 bit = SDE_PORTD_HOTPLUG_CPT;
1108 break;
1109 default:
1110 return true;
1111 }
b0ea7d37
DL		 1112 }
1113
1114 return I915_READ(SDEISR) & bit;
1115}
1116
b24e7179
JB		 1117static const char *state_string(bool enabled)
1118{
1119 return enabled ? "on" : "off";
1120}
1121
1122/* Only for pre-ILK configs */
55607e8a
DV		 1123void assert_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
b24e7179
JB		 1125{
1126 int reg;
1127 u32 val;
1128 bool cur_state;
1129
1130 reg = DPLL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1133 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1134 "PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136}
b24e7179 1137
23538ef1
JN		 1138/* XXX: the dsi pll is shared between MIPI DSI ports */
1139static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1140{
1141 u32 val;
1142 bool cur_state;
1143
a580516d 1144 mutex_lock(&dev_priv->sb_lock);
23538ef1 1145 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1146 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1147
1148 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1149 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1150 "DSI PLL state assertion failure (expected %s, current %s)\n",
1151 state_string(state), state_string(cur_state));
1152}
1153#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1154#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1155
55607e8a 1156struct intel_shared_dpll *
e2b78267
DV		 1157intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1158{
1159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1160
6e3c9717 1161 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1162 return NULL;
1163
6e3c9717 1164 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1165}
1166
040484af 1167/* For ILK+ */
55607e8a
DV		 1168void assert_shared_dpll(struct drm_i915_private *dev_priv,
1169 struct intel_shared_dpll *pll,
1170 bool state)
040484af 1171{
040484af 1172 bool cur_state;
5358901f 1173 struct intel_dpll_hw_state hw_state;
040484af 1174
92b27b08 1175 if (WARN (!pll,
46edb027 1176 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1177 return;
ee7b9f93 1178
5358901f 1179 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1180 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1181 "%s assertion failure (expected %s, current %s)\n",
1182 pll->name, state_string(state), state_string(cur_state));
040484af 1183}
040484af
JB		 1184
1185static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187{
1188 int reg;
1189 u32 val;
1190 bool cur_state;
ad80a810
PZ		 1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192 pipe);
040484af 1193
affa9354
PZ		 1194 if (HAS_DDI(dev_priv->dev)) {
1195 /* DDI does not have a specific FDI_TX register */
ad80a810 1196 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1197 val = I915_READ(reg);
ad80a810 1198 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1199 } else {
1200 reg = FDI_TX_CTL(pipe);
1201 val = I915_READ(reg);
1202 cur_state = !!(val & FDI_TX_ENABLE);
1203 }
e2c719b7 1204 I915_STATE_WARN(cur_state != state,
040484af
JB		 1205 "FDI TX state assertion failure (expected %s, current %s)\n",
1206 state_string(state), state_string(cur_state));
1207}
1208#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1209#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1210
1211static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1212 enum pipe pipe, bool state)
1213{
1214 int reg;
1215 u32 val;
1216 bool cur_state;
1217
d63fa0dc
PZ		 1218 reg = FDI_RX_CTL(pipe);
1219 val = I915_READ(reg);
1220 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1221 I915_STATE_WARN(cur_state != state,
040484af
JB		 1222 "FDI RX state assertion failure (expected %s, current %s)\n",
1223 state_string(state), state_string(cur_state));
1224}
1225#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1226#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1227
1228static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230{
1231 int reg;
1232 u32 val;
1233
1234 /* ILK FDI PLL is always enabled */
3d13ef2e 1235 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1236 return;
1237
bf507ef7 1238 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1239 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1240 return;
1241
040484af
JB		 1242 reg = FDI_TX_CTL(pipe);
1243 val = I915_READ(reg);
e2c719b7 1244 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1245}
1246
55607e8a
DV		 1247void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1248 enum pipe pipe, bool state)
040484af
JB		 1249{
1250 int reg;
1251 u32 val;
55607e8a 1252 bool cur_state;
040484af
JB		 1253
1254 reg = FDI_RX_CTL(pipe);
1255 val = I915_READ(reg);
55607e8a 1256 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1257 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1258 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1259 state_string(state), state_string(cur_state));
040484af
JB		 1260}
1261
b680c37a
DV		 1262void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
ea0760cf 1264{
bedd4dba
JN		 1265 struct drm_device *dev = dev_priv->dev;
1266 int pp_reg;
ea0760cf
JB		 1267 u32 val;
1268 enum pipe panel_pipe = PIPE_A;
0de3b485 1269 bool locked = true;
ea0760cf 1270
bedd4dba
JN		 1271 if (WARN_ON(HAS_DDI(dev)))
1272 return;
1273
1274 if (HAS_PCH_SPLIT(dev)) {
1275 u32 port_sel;
1276
ea0760cf 1277 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1278 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1279
1280 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1281 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1282 panel_pipe = PIPE_B;
1283 /* XXX: else fix for eDP */
1284 } else if (IS_VALLEYVIEW(dev)) {
1285 /* presumably write lock depends on pipe, not port select */
1286 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1287 panel_pipe = pipe;
ea0760cf
JB		 1288 } else {
1289 pp_reg = PP_CONTROL;
bedd4dba
JN		 1290 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1291 panel_pipe = PIPE_B;
ea0760cf
JB		 1292 }
1293
1294 val = I915_READ(pp_reg);
1295 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1296 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1297 locked = false;
1298
e2c719b7 1299 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1300 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1301 pipe_name(pipe));
ea0760cf
JB		 1302}
1303
93ce0ba6
JN		 1304static void assert_cursor(struct drm_i915_private *dev_priv,
1305 enum pipe pipe, bool state)
1306{
1307 struct drm_device *dev = dev_priv->dev;
1308 bool cur_state;
1309
d9d82081 1310 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1311 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1312 else
5efb3e28 1313 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1314
e2c719b7 1315 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1316 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe), state_string(state), state_string(cur_state));
1318}
1319#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1320#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1321
b840d907
JB		 1322void assert_pipe(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
b24e7179
JB		 1324{
1325 int reg;
1326 u32 val;
63d7bbe9 1327 bool cur_state;
702e7a56
PZ		 1328 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1329 pipe);
b24e7179 1330
b6b5d049
VS		 1331 /* if we need the pipe quirk it must be always on */
1332 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1333 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1334 state = true;
1335
f458ebbc 1336 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1337 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1338 cur_state = false;
1339 } else {
1340 reg = PIPECONF(cpu_transcoder);
1341 val = I915_READ(reg);
1342 cur_state = !!(val & PIPECONF_ENABLE);
1343 }
1344
e2c719b7 1345 I915_STATE_WARN(cur_state != state,
63d7bbe9 1346 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1347 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1348}
1349
931872fc
CW		 1350static void assert_plane(struct drm_i915_private *dev_priv,
1351 enum plane plane, bool state)
b24e7179
JB		 1352{
1353 int reg;
1354 u32 val;
931872fc 1355 bool cur_state;
b24e7179
JB		 1356
1357 reg = DSPCNTR(plane);
1358 val = I915_READ(reg);
931872fc 1359 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1360 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1361 "plane %c assertion failure (expected %s, current %s)\n",
1362 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1363}
1364
931872fc
CW		 1365#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1366#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1367
b24e7179
JB		 1368static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370{
653e1026 1371 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1372 int reg, i;
1373 u32 val;
1374 int cur_pipe;
1375
653e1026
VS		 1376 /* Primary planes are fixed to pipes on gen4+ */
1377 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1378 reg = DSPCNTR(pipe);
1379 val = I915_READ(reg);
e2c719b7 1380 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1381 "plane %c assertion failure, should be disabled but not\n",
1382 plane_name(pipe));
19ec1358 1383 return;
28c05794 1384 }
19ec1358 1385
b24e7179 1386 /* Need to check both planes against the pipe */
055e393f 1387 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1388 reg = DSPCNTR(i);
1389 val = I915_READ(reg);
1390 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1391 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1392 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1393 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1394 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1395 }
1396}
1397
19332d7a
JB		 1398static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe)
1400{
20674eef 1401 struct drm_device *dev = dev_priv->dev;
1fe47785 1402 int reg, sprite;
19332d7a
JB		 1403 u32 val;
1404
7feb8b88 1405 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1406 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1407 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1408 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1409 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1410 sprite, pipe_name(pipe));
1411 }
1412 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1413 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1414 reg = SPCNTR(pipe, sprite);
20674eef 1415 val = I915_READ(reg);
e2c719b7 1416 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1418 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1419 }
1420 } else if (INTEL_INFO(dev)->gen >= 7) {
1421 reg = SPRCTL(pipe);
19332d7a 1422 val = I915_READ(reg);
e2c719b7 1423 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1425 plane_name(pipe), pipe_name(pipe));
1426 } else if (INTEL_INFO(dev)->gen >= 5) {
1427 reg = DVSCNTR(pipe);
19332d7a 1428 val = I915_READ(reg);
e2c719b7 1429 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1431 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1432 }
1433}
1434
08c71e5e
VS		 1435static void assert_vblank_disabled(struct drm_crtc *crtc)
1436{
e2c719b7 1437 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1438 drm_crtc_vblank_put(crtc);
1439}
1440
89eff4be 1441static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1442{
1443 u32 val;
1444 bool enabled;
1445
e2c719b7 1446 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1447
92f2584a
JB		 1448 val = I915_READ(PCH_DREF_CONTROL);
1449 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1450 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1451 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1452}
1453
ab9412ba
DV		 1454static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1455 enum pipe pipe)
92f2584a
JB		 1456{
1457 int reg;
1458 u32 val;
1459 bool enabled;
1460
ab9412ba 1461 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1462 val = I915_READ(reg);
1463 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1464 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1465 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1466 pipe_name(pipe));
92f2584a
JB		 1467}
1468
4e634389
KP		 1469static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1470 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1471{
1472 if ((val & DP_PORT_EN) == 0)
1473 return false;
1474
1475 if (HAS_PCH_CPT(dev_priv->dev)) {
1476 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1477 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1478 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1479 return false;
44f37d1f
CML		 1480 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1481 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1482 return false;
f0575e92
KP		 1483 } else {
1484 if ((val & DP_PIPE_MASK) != (pipe << 30))
1485 return false;
1486 }
1487 return true;
1488}
1489
1519b995
KP		 1490static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1491 enum pipe pipe, u32 val)
1492{
dc0fa718 1493 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1494 return false;
1495
1496 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1497 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1498 return false;
44f37d1f
CML		 1499 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1500 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1501 return false;
1519b995 1502 } else {
dc0fa718 1503 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1504 return false;
1505 }
1506 return true;
1507}
1508
1509static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511{
1512 if ((val & LVDS_PORT_EN) == 0)
1513 return false;
1514
1515 if (HAS_PCH_CPT(dev_priv->dev)) {
1516 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1517 return false;
1518 } else {
1519 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1520 return false;
1521 }
1522 return true;
1523}
1524
1525static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1526 enum pipe pipe, u32 val)
1527{
1528 if ((val & ADPA_DAC_ENABLE) == 0)
1529 return false;
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
1531 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1532 return false;
1533 } else {
1534 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1535 return false;
1536 }
1537 return true;
1538}
1539
291906f1 1540static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1541 enum pipe pipe, int reg, u32 port_sel)
291906f1 1542{
47a05eca 1543 u32 val = I915_READ(reg);
e2c719b7 1544 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1545 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1546 reg, pipe_name(pipe));
de9a35ab 1547
e2c719b7 1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1549 && (val & DP_PIPEB_SELECT),
de9a35ab 1550 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1551}
1552
1553static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1554 enum pipe pipe, int reg)
1555{
47a05eca 1556 u32 val = I915_READ(reg);
e2c719b7 1557 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1558 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1559 reg, pipe_name(pipe));
de9a35ab 1560
e2c719b7 1561 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1562 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1563 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1564}
1565
1566static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
1568{
1569 int reg;
1570 u32 val;
291906f1 1571
f0575e92
KP		 1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1575
1576 reg = PCH_ADPA;
1577 val = I915_READ(reg);
e2c719b7 1578 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1579 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1580 pipe_name(pipe));
291906f1
JB		 1581
1582 reg = PCH_LVDS;
1583 val = I915_READ(reg);
e2c719b7 1584 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1585 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1586 pipe_name(pipe));
291906f1 1587
e2debe91
PZ		 1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1591}
1592
40e9cf64
JB		 1593static void intel_init_dpio(struct drm_device *dev)
1594{
1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597 if (!IS_VALLEYVIEW(dev))
1598 return;
1599
a09caddd
CML		 1600 /*
1601 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1602 * CHV x1 PHY (DP/HDMI D)
1603 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1604 */
1605 if (IS_CHERRYVIEW(dev)) {
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1607 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1608 } else {
1609 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1610 }
5382f5f3
JB		 1611}
1612
d288f65f 1613static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1614 const struct intel_crtc_state *pipe_config)
87442f73 1615{
426115cf
DV		 1616 struct drm_device *dev = crtc->base.dev;
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 int reg = DPLL(crtc->pipe);
d288f65f 1619 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1620
426115cf 1621 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1622
1623 /* No really, not for ILK+ */
1624 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1625
1626 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1627 if (IS_MOBILE(dev_priv->dev))
426115cf 1628 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1629
426115cf
DV		 1630 I915_WRITE(reg, dpll);
1631 POSTING_READ(reg);
1632 udelay(150);
1633
1634 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1635 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1636
d288f65f 1637 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1638 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1639
1640 /* We do this three times for luck */
426115cf 1641 I915_WRITE(reg, dpll);
87442f73
DV		 1642 POSTING_READ(reg);
1643 udelay(150); /* wait for warmup */
426115cf 1644 I915_WRITE(reg, dpll);
87442f73
DV		 1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
426115cf 1647 I915_WRITE(reg, dpll);
87442f73
DV		 1648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
1650}
1651
d288f65f 1652static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1653 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1654{
1655 struct drm_device *dev = crtc->base.dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 int pipe = crtc->pipe;
1658 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1659 u32 tmp;
1660
1661 assert_pipe_disabled(dev_priv, crtc->pipe);
1662
1663 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1664
a580516d 1665 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1666
1667 /* Enable back the 10bit clock to display controller */
1668 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1669 tmp |= DPIO_DCLKP_EN;
1670 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1671
54433e91
VS		 1672 mutex_unlock(&dev_priv->sb_lock);
1673
9d556c99
CML		 1674 /*
1675 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1676 */
1677 udelay(1);
1678
1679 /* Enable PLL */
d288f65f 1680 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1681
1682 /* Check PLL is locked */
a11b0703 1683 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1684 DRM_ERROR("PLL %d failed to lock\n", pipe);
1685
a11b0703 1686 /* not sure when this should be written */
d288f65f 1687 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1688 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1689}
1690
1c4e0274
VS		 1691static int intel_num_dvo_pipes(struct drm_device *dev)
1692{
1693 struct intel_crtc *crtc;
1694 int count = 0;
1695
1696 for_each_intel_crtc(dev, crtc)
3538b9df 1697 count += crtc->base.state->active &&
409ee761 1698 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1699
1700 return count;
1701}
1702
66e3d5c0 1703static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1704{
66e3d5c0
DV		 1705 struct drm_device *dev = crtc->base.dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 int reg = DPLL(crtc->pipe);
6e3c9717 1708 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1709
66e3d5c0 1710 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1711
63d7bbe9 1712 /* No really, not for ILK+ */
3d13ef2e 1713 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1714
1715 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1716 if (IS_MOBILE(dev) && !IS_I830(dev))
1717 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1718
1c4e0274
VS		 1719 /* Enable DVO 2x clock on both PLLs if necessary */
1720 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1721 /*
1722 * It appears to be important that we don't enable this
1723 * for the current pipe before otherwise configuring the
1724 * PLL. No idea how this should be handled if multiple
1725 * DVO outputs are enabled simultaneosly.
1726 */
1727 dpll |= DPLL_DVO_2X_MODE;
1728 I915_WRITE(DPLL(!crtc->pipe),
1729 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1730 }
66e3d5c0
DV		 1731
1732 /* Wait for the clocks to stabilize. */
1733 POSTING_READ(reg);
1734 udelay(150);
1735
1736 if (INTEL_INFO(dev)->gen >= 4) {
1737 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1738 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1739 } else {
1740 /* The pixel multiplier can only be updated once the
1741 * DPLL is enabled and the clocks are stable.
1742 *
1743 * So write it again.
1744 */
1745 I915_WRITE(reg, dpll);
1746 }
63d7bbe9
JB		 1747
1748 /* We do this three times for luck */
66e3d5c0 1749 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1750 POSTING_READ(reg);
1751 udelay(150); /* wait for warmup */
66e3d5c0 1752 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1753 POSTING_READ(reg);
1754 udelay(150); /* wait for warmup */
66e3d5c0 1755 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1756 POSTING_READ(reg);
1757 udelay(150); /* wait for warmup */
1758}
1759
1760/**
50b44a44 1761 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1762 * @dev_priv: i915 private structure
1763 * @pipe: pipe PLL to disable
1764 *
1765 * Disable the PLL for @pipe, making sure the pipe is off first.
1766 *
1767 * Note! This is for pre-ILK only.
1768 */
1c4e0274 1769static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1770{
1c4e0274
VS		 1771 struct drm_device *dev = crtc->base.dev;
1772 struct drm_i915_private *dev_priv = dev->dev_private;
1773 enum pipe pipe = crtc->pipe;
1774
1775 /* Disable DVO 2x clock on both PLLs if necessary */
1776 if (IS_I830(dev) &&
409ee761 1777 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1778 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1779 I915_WRITE(DPLL(PIPE_B),
1780 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1781 I915_WRITE(DPLL(PIPE_A),
1782 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1783 }
1784
b6b5d049
VS		 1785 /* Don't disable pipe or pipe PLLs if needed */
1786 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1787 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1788 return;
1789
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
1792
b8afb911 1793 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1794 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1795}
1796
f6071166
JB		 1797static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1798{
b8afb911 1799 u32 val;
f6071166
JB		 1800
1801 /* Make sure the pipe isn't still relying on us */
1802 assert_pipe_disabled(dev_priv, pipe);
1803
e5cbfbfb
ID		 1804 /*
1805 * Leave integrated clock source and reference clock enabled for pipe B.
1806 * The latter is needed for VGA hotplug / manual detection.
1807 */
b8afb911 1808 val = DPLL_VGA_MODE_DIS;
f6071166 1809 if (pipe == PIPE_B)
60bfe44f 1810 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1811 I915_WRITE(DPLL(pipe), val);
1812 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1813
1814}
1815
1816static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1817{
d752048d 1818 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1819 u32 val;
1820
a11b0703
VS		 1821 /* Make sure the pipe isn't still relying on us */
1822 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1823
a11b0703 1824 /* Set PLL en = 0 */
60bfe44f
VS		 1825 val = DPLL_SSC_REF_CLK_CHV |
1826 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1827 if (pipe != PIPE_A)
1828 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1829 I915_WRITE(DPLL(pipe), val);
1830 POSTING_READ(DPLL(pipe));
d752048d 1831
a580516d 1832 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1833
1834 /* Disable 10bit clock to display controller */
1835 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1836 val &= ~DPIO_DCLKP_EN;
1837 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1838
61407f6d
VS		 1839 /* disable left/right clock distribution */
1840 if (pipe != PIPE_B) {
1841 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1842 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1843 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1844 } else {
1845 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1846 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1847 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1848 }
1849
a580516d 1850 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1851}
1852
e4607fcf 1853void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1854 struct intel_digital_port *dport,
1855 unsigned int expected_mask)
89b667f8
JB		 1856{
1857 u32 port_mask;
00fc31b7 1858 int dpll_reg;
89b667f8 1859
e4607fcf
CML		 1860 switch (dport->port) {
1861 case PORT_B:
89b667f8 1862 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1863 dpll_reg = DPLL(0);
e4607fcf
CML		 1864 break;
1865 case PORT_C:
89b667f8 1866 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1867 dpll_reg = DPLL(0);
9b6de0a1 1868 expected_mask <<= 4;
00fc31b7
CML		 1869 break;
1870 case PORT_D:
1871 port_mask = DPLL_PORTD_READY_MASK;
1872 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1873 break;
1874 default:
1875 BUG();
1876 }
89b667f8 1877
9b6de0a1
VS		 1878 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1879 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1880 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1881}
1882
b14b1055
DV		 1883static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1884{
1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
be19f0ff
CW		 1889 if (WARN_ON(pll == NULL))
1890 return;
1891
3e369b76 1892 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1893 if (pll->active == 0) {
1894 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1895 WARN_ON(pll->on);
1896 assert_shared_dpll_disabled(dev_priv, pll);
1897
1898 pll->mode_set(dev_priv, pll);
1899 }
1900}
1901
92f2584a 1902/**
85b3894f 1903 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1904 * @dev_priv: i915 private structure
1905 * @pipe: pipe PLL to enable
1906 *
1907 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1908 * drives the transcoder clock.
1909 */
85b3894f 1910static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1911{
3d13ef2e
DL		 1912 struct drm_device *dev = crtc->base.dev;
1913 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1914 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1915
87a875bb 1916 if (WARN_ON(pll == NULL))
48da64a8
CW		 1917 return;
1918
3e369b76 1919 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1920 return;
ee7b9f93 1921
74dd6928 1922 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1923 pll->name, pll->active, pll->on,
e2b78267 1924 crtc->base.base.id);
92f2584a 1925
cdbd2316
DV		 1926 if (pll->active++) {
1927 WARN_ON(!pll->on);
e9d6944e 1928 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1929 return;
1930 }
f4a091c7 1931 WARN_ON(pll->on);
ee7b9f93 1932
bd2bb1b9
PZ		 1933 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1934
46edb027 1935 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1936 pll->enable(dev_priv, pll);
ee7b9f93 1937 pll->on = true;
92f2584a
JB		 1938}
1939
f6daaec2 1940static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1941{
3d13ef2e
DL		 1942 struct drm_device *dev = crtc->base.dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1944 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1945
92f2584a 1946 /* PCH only available on ILK+ */
3d13ef2e 1947 BUG_ON(INTEL_INFO(dev)->gen < 5);
eddfcbcd
ML		 1948 if (pll == NULL)
1949 return;
92f2584a 1950
eddfcbcd 1951 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1952 return;
7a419866 1953
46edb027
DV		 1954 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1955 pll->name, pll->active, pll->on,
e2b78267 1956 crtc->base.base.id);
7a419866 1957
48da64a8 1958 if (WARN_ON(pll->active == 0)) {
e9d6944e 1959 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1960 return;
1961 }
1962
e9d6944e 1963 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1964 WARN_ON(!pll->on);
cdbd2316 1965 if (--pll->active)
7a419866 1966 return;
ee7b9f93 1967
46edb027 1968 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1969 pll->disable(dev_priv, pll);
ee7b9f93 1970 pll->on = false;
bd2bb1b9
PZ		 1971
1972 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1973}
1974
b8a4f404
PZ		 1975static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1976 enum pipe pipe)
040484af 1977{
23670b32 1978 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1979 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1981 uint32_t reg, val, pipeconf_val;
040484af
JB		 1982
1983 /* PCH only available on ILK+ */
55522f37 1984 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1985
1986 /* Make sure PCH DPLL is enabled */
e72f9fbf 1987 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1988 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1989
1990 /* FDI must be feeding us bits for PCH ports */
1991 assert_fdi_tx_enabled(dev_priv, pipe);
1992 assert_fdi_rx_enabled(dev_priv, pipe);
1993
23670b32
DV		 1994 if (HAS_PCH_CPT(dev)) {
1995 /* Workaround: Set the timing override bit before enabling the
1996 * pch transcoder. */
1997 reg = TRANS_CHICKEN2(pipe);
1998 val = I915_READ(reg);
1999 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2000 I915_WRITE(reg, val);
59c859d6 2001 }
23670b32 2002
ab9412ba 2003 reg = PCH_TRANSCONF(pipe);
040484af 2004 val = I915_READ(reg);
5f7f726d 2005 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2006
2007 if (HAS_PCH_IBX(dev_priv->dev)) {
2008 /*
c5de7c6f
VS		 2009 * Make the BPC in transcoder be consistent with
2010 * that in pipeconf reg. For HDMI we must use 8bpc
2011 * here for both 8bpc and 12bpc.
e9bcff5c 2012 */
dfd07d72 2013 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2014 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2015 val |= PIPECONF_8BPC;
2016 else
2017 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2018 }
5f7f726d
PZ		 2019
2020 val &= ~TRANS_INTERLACE_MASK;
2021 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2022 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2023 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2024 val |= TRANS_LEGACY_INTERLACED_ILK;
2025 else
2026 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2027 else
2028 val |= TRANS_PROGRESSIVE;
2029
040484af
JB		 2030 I915_WRITE(reg, val | TRANS_ENABLE);
2031 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2032 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2033}
2034
8fb033d7 2035static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2036 enum transcoder cpu_transcoder)
040484af 2037{
8fb033d7 2038 u32 val, pipeconf_val;
8fb033d7
PZ		 2039
2040 /* PCH only available on ILK+ */
55522f37 2041 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2042
8fb033d7 2043 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2044 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2045 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2046
223a6fdf
PZ		 2047 /* Workaround: set timing override bit. */
2048 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2049 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2050 I915_WRITE(_TRANSA_CHICKEN2, val);
2051
25f3ef11 2052 val = TRANS_ENABLE;
937bb610 2053 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2054
9a76b1c6
PZ		 2055 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2056 PIPECONF_INTERLACED_ILK)
a35f2679 2057 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2058 else
2059 val |= TRANS_PROGRESSIVE;
2060
ab9412ba
DV		 2061 I915_WRITE(LPT_TRANSCONF, val);
2062 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2063 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2064}
2065
b8a4f404
PZ		 2066static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2067 enum pipe pipe)
040484af 2068{
23670b32
DV		 2069 struct drm_device *dev = dev_priv->dev;
2070 uint32_t reg, val;
040484af
JB		 2071
2072 /* FDI relies on the transcoder */
2073 assert_fdi_tx_disabled(dev_priv, pipe);
2074 assert_fdi_rx_disabled(dev_priv, pipe);
2075
291906f1
JB		 2076 /* Ports must be off as well */
2077 assert_pch_ports_disabled(dev_priv, pipe);
2078
ab9412ba 2079 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2080 val = I915_READ(reg);
2081 val &= ~TRANS_ENABLE;
2082 I915_WRITE(reg, val);
2083 /* wait for PCH transcoder off, transcoder state */
2084 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2085 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2086
2087 if (!HAS_PCH_IBX(dev)) {
2088 /* Workaround: Clear the timing override chicken bit again. */
2089 reg = TRANS_CHICKEN2(pipe);
2090 val = I915_READ(reg);
2091 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2092 I915_WRITE(reg, val);
2093 }
040484af
JB		 2094}
2095
ab4d966c 2096static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2097{
8fb033d7
PZ		 2098 u32 val;
2099
ab9412ba 2100 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2101 val &= ~TRANS_ENABLE;
ab9412ba 2102 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2103 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2104 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2105 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2106
2107 /* Workaround: clear timing override bit. */
2108 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2109 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2110 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2111}
2112
b24e7179 2113/**
309cfea8 2114 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2115 * @crtc: crtc responsible for the pipe
b24e7179 2116 *
0372264a 2117 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2118 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2119 */
e1fdc473 2120static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2121{
0372264a
PZ		 2122 struct drm_device *dev = crtc->base.dev;
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2124 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2126 pipe);
1a240d4d 2127 enum pipe pch_transcoder;
b24e7179
JB		 2128 int reg;
2129 u32 val;
2130
9e2ee2dd
VS		 2131 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2132
58c6eaa2 2133 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2134 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2135 assert_sprites_disabled(dev_priv, pipe);
2136
681e5811 2137 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2138 pch_transcoder = TRANSCODER_A;
2139 else
2140 pch_transcoder = pipe;
2141
b24e7179
JB		 2142 /*
2143 * A pipe without a PLL won't actually be able to drive bits from
2144 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2145 * need the check.
2146 */
50360403 2147 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2148 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2149 assert_dsi_pll_enabled(dev_priv);
2150 else
2151 assert_pll_enabled(dev_priv, pipe);
040484af 2152 else {
6e3c9717 2153 if (crtc->config->has_pch_encoder) {
040484af 2154 /* if driving the PCH, we need FDI enabled */
cc391bbb 2155 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2156 assert_fdi_tx_pll_enabled(dev_priv,
2157 (enum pipe) cpu_transcoder);
040484af
JB		 2158 }
2159 /* FIXME: assert CPU port conditions for SNB+ */
2160 }
b24e7179 2161
702e7a56 2162 reg = PIPECONF(cpu_transcoder);
b24e7179 2163 val = I915_READ(reg);
7ad25d48 2164 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2165 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2166 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2167 return;
7ad25d48 2168 }
00d70b15
CW		 2169
2170 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2171 POSTING_READ(reg);
b24e7179
JB		 2172}
2173
2174/**
309cfea8 2175 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2176 * @crtc: crtc whose pipes is to be disabled
b24e7179 2177 *
575f7ab7
VS		 2178 * Disable the pipe of @crtc, making sure that various hardware
2179 * specific requirements are met, if applicable, e.g. plane
2180 * disabled, panel fitter off, etc.
b24e7179
JB		 2181 *
2182 * Will wait until the pipe has shut down before returning.
2183 */
575f7ab7 2184static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2185{
575f7ab7 2186 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2187 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2188 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2189 int reg;
2190 u32 val;
2191
9e2ee2dd
VS		 2192 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2193
b24e7179
JB		 2194 /*
2195 * Make sure planes won't keep trying to pump pixels to us,
2196 * or we might hang the display.
2197 */
2198 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2199 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2200 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2201
702e7a56 2202 reg = PIPECONF(cpu_transcoder);
b24e7179 2203 val = I915_READ(reg);
00d70b15
CW		 2204 if ((val & PIPECONF_ENABLE) == 0)
2205 return;
2206
67adc644
VS		 2207 /*
2208 * Double wide has implications for planes
2209 * so best keep it disabled when not needed.
2210 */
6e3c9717 2211 if (crtc->config->double_wide)
67adc644
VS		 2212 val &= ~PIPECONF_DOUBLE_WIDE;
2213
2214 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2215 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2216 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2217 val &= ~PIPECONF_ENABLE;
2218
2219 I915_WRITE(reg, val);
2220 if ((val & PIPECONF_ENABLE) == 0)
2221 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2222}
2223
693db184
CW		 2224static bool need_vtd_wa(struct drm_device *dev)
2225{
2226#ifdef CONFIG_INTEL_IOMMU
2227 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2228 return true;
2229#endif
2230 return false;
2231}
2232
50470bb0 2233unsigned int
6761dd31
TU		 2234intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2235 uint64_t fb_format_modifier)
a57ce0b2 2236{
6761dd31
TU		 2237 unsigned int tile_height;
2238 uint32_t pixel_bytes;
a57ce0b2 2239
b5d0e9bf
DL		 2240 switch (fb_format_modifier) {
2241 case DRM_FORMAT_MOD_NONE:
2242 tile_height = 1;
2243 break;
2244 case I915_FORMAT_MOD_X_TILED:
2245 tile_height = IS_GEN2(dev) ? 16 : 8;
2246 break;
2247 case I915_FORMAT_MOD_Y_TILED:
2248 tile_height = 32;
2249 break;
2250 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2251 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2252 switch (pixel_bytes) {
b5d0e9bf 2253 default:
6761dd31 2254 case 1:
b5d0e9bf
DL		 2255 tile_height = 64;
2256 break;
6761dd31
TU		 2257 case 2:
2258 case 4:
b5d0e9bf
DL		 2259 tile_height = 32;
2260 break;
6761dd31 2261 case 8:
b5d0e9bf
DL		 2262 tile_height = 16;
2263 break;
6761dd31 2264 case 16:
b5d0e9bf
DL		 2265 WARN_ONCE(1,
2266 "128-bit pixels are not supported for display!");
2267 tile_height = 16;
2268 break;
2269 }
2270 break;
2271 default:
2272 MISSING_CASE(fb_format_modifier);
2273 tile_height = 1;
2274 break;
2275 }
091df6cb 2276
6761dd31
TU		 2277 return tile_height;
2278}
2279
2280unsigned int
2281intel_fb_align_height(struct drm_device *dev, unsigned int height,
2282 uint32_t pixel_format, uint64_t fb_format_modifier)
2283{
2284 return ALIGN(height, intel_tile_height(dev, pixel_format,
2285 fb_format_modifier));
a57ce0b2
JB		 2286}
2287
f64b98cd
TU		 2288static int
2289intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2290 const struct drm_plane_state *plane_state)
2291{
50470bb0 2292 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2293 unsigned int tile_height, tile_pitch;
50470bb0 2294
f64b98cd
TU		 2295 *view = i915_ggtt_view_normal;
2296
50470bb0
TU		 2297 if (!plane_state)
2298 return 0;
2299
121920fa 2300 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2301 return 0;
2302
9abc4648 2303 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2304
2305 info->height = fb->height;
2306 info->pixel_format = fb->pixel_format;
2307 info->pitch = fb->pitches[0];
2308 info->fb_modifier = fb->modifier[0];
2309
84fe03f7
TU		 2310 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2311 fb->modifier[0]);
2312 tile_pitch = PAGE_SIZE / tile_height;
2313 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2314 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2315 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2316
f64b98cd
TU		 2317 return 0;
2318}
2319
4e9a86b6
VS		 2320static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2321{
2322 if (INTEL_INFO(dev_priv)->gen >= 9)
2323 return 256 * 1024;
985b8bb4
VS		 2324 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2325 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2326 return 128 * 1024;
2327 else if (INTEL_INFO(dev_priv)->gen >= 4)
2328 return 4 * 1024;
2329 else
44c5905e 2330 return 0;
4e9a86b6
VS		 2331}
2332
127bd2ac 2333int
850c4cdc
TU		 2334intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2335 struct drm_framebuffer *fb,
82bc3b2d 2336 const struct drm_plane_state *plane_state,
91af127f
JH		 2337 struct intel_engine_cs *pipelined,
2338 struct drm_i915_gem_request **pipelined_request)
6b95a207 2339{
850c4cdc 2340 struct drm_device *dev = fb->dev;
ce453d81 2341 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2342 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2343 struct i915_ggtt_view view;
6b95a207
KH		 2344 u32 alignment;
2345 int ret;
2346
ebcdd39e
MR		 2347 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2348
7b911adc
TU		 2349 switch (fb->modifier[0]) {
2350 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2351 alignment = intel_linear_alignment(dev_priv);
6b95a207 2352 break;
7b911adc 2353 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2354 if (INTEL_INFO(dev)->gen >= 9)
2355 alignment = 256 * 1024;
2356 else {
2357 /* pin() will align the object as required by fence */
2358 alignment = 0;
2359 }
6b95a207 2360 break;
7b911adc 2361 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2362 case I915_FORMAT_MOD_Yf_TILED:
2363 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2364 "Y tiling bo slipped through, driver bug!\n"))
2365 return -EINVAL;
2366 alignment = 1 * 1024 * 1024;
2367 break;
6b95a207 2368 default:
7b911adc
TU		 2369 MISSING_CASE(fb->modifier[0]);
2370 return -EINVAL;
6b95a207
KH		 2371 }
2372
f64b98cd
TU		 2373 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2374 if (ret)
2375 return ret;
2376
693db184
CW		 2377 /* Note that the w/a also requires 64 PTE of padding following the
2378 * bo. We currently fill all unused PTE with the shadow page and so
2379 * we should always have valid PTE following the scanout preventing
2380 * the VT-d warning.
2381 */
2382 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2383 alignment = 256 * 1024;
2384
d6dd6843
PZ		 2385 /*
2386 * Global gtt pte registers are special registers which actually forward
2387 * writes to a chunk of system memory. Which means that there is no risk
2388 * that the register values disappear as soon as we call
2389 * intel_runtime_pm_put(), so it is correct to wrap only the
2390 * pin/unpin/fence and not more.
2391 */
2392 intel_runtime_pm_get(dev_priv);
2393
ce453d81 2394 dev_priv->mm.interruptible = false;
e6617330 2395 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2396 pipelined_request, &view);
48b956c5 2397 if (ret)
ce453d81 2398 goto err_interruptible;
6b95a207
KH		 2399
2400 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2401 * fence, whereas 965+ only requires a fence if using
2402 * framebuffer compression. For simplicity, we always install
2403 * a fence as the cost is not that onerous.
2404 */
06d98131 2405 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2406 if (ret)
2407 goto err_unpin;
1690e1eb 2408
9a5a53b3 2409 i915_gem_object_pin_fence(obj);
6b95a207 2410
ce453d81 2411 dev_priv->mm.interruptible = true;
d6dd6843 2412 intel_runtime_pm_put(dev_priv);
6b95a207 2413 return 0;
48b956c5
CW		 2414
2415err_unpin:
f64b98cd 2416 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2417err_interruptible:
2418 dev_priv->mm.interruptible = true;
d6dd6843 2419 intel_runtime_pm_put(dev_priv);
48b956c5 2420 return ret;
6b95a207
KH		 2421}
2422
82bc3b2d
TU		 2423static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2424 const struct drm_plane_state *plane_state)
1690e1eb 2425{
82bc3b2d 2426 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2427 struct i915_ggtt_view view;
2428 int ret;
82bc3b2d 2429
ebcdd39e
MR		 2430 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2431
f64b98cd
TU		 2432 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2433 WARN_ONCE(ret, "Couldn't get view from plane state!");
2434
1690e1eb 2435 i915_gem_object_unpin_fence(obj);
f64b98cd 2436 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2437}
2438
c2c75131
DV		 2439/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2440 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2441unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2442 int *x, int *y,
bc752862
CW		 2443 unsigned int tiling_mode,
2444 unsigned int cpp,
2445 unsigned int pitch)
c2c75131 2446{
bc752862
CW		 2447 if (tiling_mode != I915_TILING_NONE) {
2448 unsigned int tile_rows, tiles;
c2c75131 2449
bc752862
CW		 2450 tile_rows = *y / 8;
2451 *y %= 8;
c2c75131 2452
bc752862
CW		 2453 tiles = *x / (512/cpp);
2454 *x %= 512/cpp;
2455
2456 return tile_rows * pitch * 8 + tiles * 4096;
2457 } else {
4e9a86b6 2458 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2459 unsigned int offset;
2460
2461 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2462 *y = (offset & alignment) / pitch;
2463 *x = ((offset & alignment) - *y * pitch) / cpp;
2464 return offset & ~alignment;
bc752862 2465 }
c2c75131
DV		 2466}
2467
b35d63fa 2468static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2469{
2470 switch (format) {
2471 case DISPPLANE_8BPP:
2472 return DRM_FORMAT_C8;
2473 case DISPPLANE_BGRX555:
2474 return DRM_FORMAT_XRGB1555;
2475 case DISPPLANE_BGRX565:
2476 return DRM_FORMAT_RGB565;
2477 default:
2478 case DISPPLANE_BGRX888:
2479 return DRM_FORMAT_XRGB8888;
2480 case DISPPLANE_RGBX888:
2481 return DRM_FORMAT_XBGR8888;
2482 case DISPPLANE_BGRX101010:
2483 return DRM_FORMAT_XRGB2101010;
2484 case DISPPLANE_RGBX101010:
2485 return DRM_FORMAT_XBGR2101010;
2486 }
2487}
2488
bc8d7dff
DL		 2489static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2490{
2491 switch (format) {
2492 case PLANE_CTL_FORMAT_RGB_565:
2493 return DRM_FORMAT_RGB565;
2494 default:
2495 case PLANE_CTL_FORMAT_XRGB_8888:
2496 if (rgb_order) {
2497 if (alpha)
2498 return DRM_FORMAT_ABGR8888;
2499 else
2500 return DRM_FORMAT_XBGR8888;
2501 } else {
2502 if (alpha)
2503 return DRM_FORMAT_ARGB8888;
2504 else
2505 return DRM_FORMAT_XRGB8888;
2506 }
2507 case PLANE_CTL_FORMAT_XRGB_2101010:
2508 if (rgb_order)
2509 return DRM_FORMAT_XBGR2101010;
2510 else
2511 return DRM_FORMAT_XRGB2101010;
2512 }
2513}
2514
5724dbd1 2515static bool
f6936e29
DV		 2516intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2517 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2518{
2519 struct drm_device *dev = crtc->base.dev;
2520 struct drm_i915_gem_object *obj = NULL;
2521 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2522 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2523 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2524 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2525 PAGE_SIZE);
2526
2527 size_aligned -= base_aligned;
46f297fb 2528
ff2652ea
CW		 2529 if (plane_config->size == 0)
2530 return false;
2531
f37b5c2b
DV		 2532 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2533 base_aligned,
2534 base_aligned,
2535 size_aligned);
46f297fb 2536 if (!obj)
484b41dd 2537 return false;
46f297fb 2538
49af449b
DL		 2539 obj->tiling_mode = plane_config->tiling;
2540 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2541 obj->stride = fb->pitches[0];
46f297fb 2542
6bf129df
DL		 2543 mode_cmd.pixel_format = fb->pixel_format;
2544 mode_cmd.width = fb->width;
2545 mode_cmd.height = fb->height;
2546 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2547 mode_cmd.modifier[0] = fb->modifier[0];
2548 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2549
2550 mutex_lock(&dev->struct_mutex);
6bf129df 2551 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2552 &mode_cmd, obj)) {
46f297fb
JB		 2553 DRM_DEBUG_KMS("intel fb init failed\n");
2554 goto out_unref_obj;
2555 }
46f297fb 2556 mutex_unlock(&dev->struct_mutex);
484b41dd 2557
f6936e29 2558 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2559 return true;
46f297fb
JB		 2560
2561out_unref_obj:
2562 drm_gem_object_unreference(&obj->base);
2563 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2564 return false;
2565}
2566
afd65eb4
MR		 2567/* Update plane->state->fb to match plane->fb after driver-internal updates */
2568static void
2569update_state_fb(struct drm_plane *plane)
2570{
2571 if (plane->fb == plane->state->fb)
2572 return;
2573
2574 if (plane->state->fb)
2575 drm_framebuffer_unreference(plane->state->fb);
2576 plane->state->fb = plane->fb;
2577 if (plane->state->fb)
2578 drm_framebuffer_reference(plane->state->fb);
2579}
2580
5724dbd1 2581static void
f6936e29
DV		 2582intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2583 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2584{
2585 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2586 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2587 struct drm_crtc *c;
2588 struct intel_crtc *i;
2ff8fde1 2589 struct drm_i915_gem_object *obj;
88595ac9 2590 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2591 struct drm_plane_state *plane_state = primary->state;
88595ac9 2592 struct drm_framebuffer *fb;
484b41dd 2593
2d14030b 2594 if (!plane_config->fb)
484b41dd
JB		 2595 return;
2596
f6936e29 2597 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2598 fb = &plane_config->fb->base;
2599 goto valid_fb;
f55548b5 2600 }
484b41dd 2601
2d14030b 2602 kfree(plane_config->fb);
484b41dd
JB		 2603
2604 /*
2605 * Failed to alloc the obj, check to see if we should share
2606 * an fb with another CRTC instead
2607 */
70e1e0ec 2608 for_each_crtc(dev, c) {
484b41dd
JB		 2609 i = to_intel_crtc(c);
2610
2611 if (c == &intel_crtc->base)
2612 continue;
2613
2ff8fde1
MR		 2614 if (!i->active)
2615 continue;
2616
88595ac9
DV		 2617 fb = c->primary->fb;
2618 if (!fb)
484b41dd
JB		 2619 continue;
2620
88595ac9 2621 obj = intel_fb_obj(fb);
2ff8fde1 2622 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2623 drm_framebuffer_reference(fb);
2624 goto valid_fb;
484b41dd
JB		 2625 }
2626 }
88595ac9
DV		 2627
2628 return;
2629
2630valid_fb:
be5651f2
ML		 2631 plane_state->src_x = plane_state->src_y = 0;
2632 plane_state->src_w = fb->width << 16;
2633 plane_state->src_h = fb->height << 16;
2634
2635 plane_state->crtc_x = plane_state->src_y = 0;
2636 plane_state->crtc_w = fb->width;
2637 plane_state->crtc_h = fb->height;
2638
88595ac9
DV		 2639 obj = intel_fb_obj(fb);
2640 if (obj->tiling_mode != I915_TILING_NONE)
2641 dev_priv->preserve_bios_swizzle = true;
2642
be5651f2
ML		 2643 drm_framebuffer_reference(fb);
2644 primary->fb = primary->state->fb = fb;
36750f28 2645 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2646 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2647 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2648}
2649
29b9bde6
DV		 2650static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2651 struct drm_framebuffer *fb,
2652 int x, int y)
81255565
JB		 2653{
2654 struct drm_device *dev = crtc->dev;
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2657 struct drm_plane *primary = crtc->primary;
2658 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2659 struct drm_i915_gem_object *obj;
81255565 2660 int plane = intel_crtc->plane;
e506a0c6 2661 unsigned long linear_offset;
81255565 2662 u32 dspcntr;
f45651ba 2663 u32 reg = DSPCNTR(plane);
48404c1e 2664 int pixel_size;
f45651ba 2665
b70709a6 2666 if (!visible || !fb) {
fdd508a6
VS		 2667 I915_WRITE(reg, 0);
2668 if (INTEL_INFO(dev)->gen >= 4)
2669 I915_WRITE(DSPSURF(plane), 0);
2670 else
2671 I915_WRITE(DSPADDR(plane), 0);
2672 POSTING_READ(reg);
2673 return;
2674 }
2675
c9ba6fad
VS		 2676 obj = intel_fb_obj(fb);
2677 if (WARN_ON(obj == NULL))
2678 return;
2679
2680 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2681
f45651ba
VS		 2682 dspcntr = DISPPLANE_GAMMA_ENABLE;
2683
fdd508a6 2684 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2685
2686 if (INTEL_INFO(dev)->gen < 4) {
2687 if (intel_crtc->pipe == PIPE_B)
2688 dspcntr |= DISPPLANE_SEL_PIPE_B;
2689
2690 /* pipesrc and dspsize control the size that is scaled from,
2691 * which should always be the user's requested size.
2692 */
2693 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2694 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2695 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2696 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2697 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2698 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2699 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2700 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2701 I915_WRITE(PRIMPOS(plane), 0);
2702 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2703 }
81255565 2704
57779d06
VS		 2705 switch (fb->pixel_format) {
2706 case DRM_FORMAT_C8:
81255565
JB		 2707 dspcntr |= DISPPLANE_8BPP;
2708 break;
57779d06 2709 case DRM_FORMAT_XRGB1555:
57779d06 2710 dspcntr |= DISPPLANE_BGRX555;
81255565 2711 break;
57779d06
VS		 2712 case DRM_FORMAT_RGB565:
2713 dspcntr |= DISPPLANE_BGRX565;
2714 break;
2715 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2716 dspcntr |= DISPPLANE_BGRX888;
2717 break;
2718 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2719 dspcntr |= DISPPLANE_RGBX888;
2720 break;
2721 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2722 dspcntr |= DISPPLANE_BGRX101010;
2723 break;
2724 case DRM_FORMAT_XBGR2101010:
57779d06 2725 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2726 break;
2727 default:
baba133a 2728 BUG();
81255565 2729 }
57779d06 2730
f45651ba
VS		 2731 if (INTEL_INFO(dev)->gen >= 4 &&
2732 obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
81255565 2734
de1aa629
VS		 2735 if (IS_G4X(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
b9897127 2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2739
c2c75131
DV		 2740 if (INTEL_INFO(dev)->gen >= 4) {
2741 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2742 intel_gen4_compute_page_offset(dev_priv,
2743 &x, &y, obj->tiling_mode,
b9897127 2744 pixel_size,
bc752862 2745 fb->pitches[0]);
c2c75131
DV		 2746 linear_offset -= intel_crtc->dspaddr_offset;
2747 } else {
e506a0c6 2748 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2749 }
e506a0c6 2750
8e7d688b 2751 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2752 dspcntr |= DISPPLANE_ROTATE_180;
2753
6e3c9717
ACO		 2754 x += (intel_crtc->config->pipe_src_w - 1);
2755 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2756
2757 /* Finding the last pixel of the last line of the display
2758 data and adding to linear_offset*/
2759 linear_offset +=
6e3c9717
ACO		 2760 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2761 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2762 }
2763
2764 I915_WRITE(reg, dspcntr);
2765
01f2c773 2766 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2767 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2768 I915_WRITE(DSPSURF(plane),
2769 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2770 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2771 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2772 } else
f343c5f6 2773 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2774 POSTING_READ(reg);
17638cd6
JB		 2775}
2776
29b9bde6
DV		 2777static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2778 struct drm_framebuffer *fb,
2779 int x, int y)
17638cd6
JB		 2780{
2781 struct drm_device *dev = crtc->dev;
2782 struct drm_i915_private *dev_priv = dev->dev_private;
2783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2784 struct drm_plane *primary = crtc->primary;
2785 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2786 struct drm_i915_gem_object *obj;
17638cd6 2787 int plane = intel_crtc->plane;
e506a0c6 2788 unsigned long linear_offset;
17638cd6 2789 u32 dspcntr;
f45651ba 2790 u32 reg = DSPCNTR(plane);
48404c1e 2791 int pixel_size;
f45651ba 2792
b70709a6 2793 if (!visible || !fb) {
fdd508a6
VS		 2794 I915_WRITE(reg, 0);
2795 I915_WRITE(DSPSURF(plane), 0);
2796 POSTING_READ(reg);
2797 return;
2798 }
2799
c9ba6fad
VS		 2800 obj = intel_fb_obj(fb);
2801 if (WARN_ON(obj == NULL))
2802 return;
2803
2804 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2805
f45651ba
VS		 2806 dspcntr = DISPPLANE_GAMMA_ENABLE;
2807
fdd508a6 2808 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2809
2810 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2811 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2812
57779d06
VS		 2813 switch (fb->pixel_format) {
2814 case DRM_FORMAT_C8:
17638cd6
JB		 2815 dspcntr |= DISPPLANE_8BPP;
2816 break;
57779d06
VS		 2817 case DRM_FORMAT_RGB565:
2818 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2819 break;
57779d06 2820 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2821 dspcntr |= DISPPLANE_BGRX888;
2822 break;
2823 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2824 dspcntr |= DISPPLANE_RGBX888;
2825 break;
2826 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2827 dspcntr |= DISPPLANE_BGRX101010;
2828 break;
2829 case DRM_FORMAT_XBGR2101010:
57779d06 2830 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2831 break;
2832 default:
baba133a 2833 BUG();
17638cd6
JB		 2834 }
2835
2836 if (obj->tiling_mode != I915_TILING_NONE)
2837 dspcntr |= DISPPLANE_TILED;
17638cd6 2838
f45651ba 2839 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2840 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2841
b9897127 2842 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2843 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2844 intel_gen4_compute_page_offset(dev_priv,
2845 &x, &y, obj->tiling_mode,
b9897127 2846 pixel_size,
bc752862 2847 fb->pitches[0]);
c2c75131 2848 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2849 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2850 dspcntr |= DISPPLANE_ROTATE_180;
2851
2852 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2853 x += (intel_crtc->config->pipe_src_w - 1);
2854 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2855
2856 /* Finding the last pixel of the last line of the display
2857 data and adding to linear_offset*/
2858 linear_offset +=
6e3c9717
ACO		 2859 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2860 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2861 }
2862 }
2863
2864 I915_WRITE(reg, dspcntr);
17638cd6 2865
01f2c773 2866 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2867 I915_WRITE(DSPSURF(plane),
2868 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2869 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2870 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2871 } else {
2872 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2873 I915_WRITE(DSPLINOFF(plane), linear_offset);
2874 }
17638cd6 2875 POSTING_READ(reg);
17638cd6
JB		 2876}
2877
b321803d
DL		 2878u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2879 uint32_t pixel_format)
2880{
2881 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2882
2883 /*
2884 * The stride is either expressed as a multiple of 64 bytes
2885 * chunks for linear buffers or in number of tiles for tiled
2886 * buffers.
2887 */
2888 switch (fb_modifier) {
2889 case DRM_FORMAT_MOD_NONE:
2890 return 64;
2891 case I915_FORMAT_MOD_X_TILED:
2892 if (INTEL_INFO(dev)->gen == 2)
2893 return 128;
2894 return 512;
2895 case I915_FORMAT_MOD_Y_TILED:
2896 /* No need to check for old gens and Y tiling since this is
2897 * about the display engine and those will be blocked before
2898 * we get here.
2899 */
2900 return 128;
2901 case I915_FORMAT_MOD_Yf_TILED:
2902 if (bits_per_pixel == 8)
2903 return 64;
2904 else
2905 return 128;
2906 default:
2907 MISSING_CASE(fb_modifier);
2908 return 64;
2909 }
2910}
2911
121920fa
TU		 2912unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2913 struct drm_i915_gem_object *obj)
2914{
9abc4648 2915 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2916
2917 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2918 view = &i915_ggtt_view_rotated;
121920fa
TU		 2919
2920 return i915_gem_obj_ggtt_offset_view(obj, view);
2921}
2922
e435d6e5
ML		 2923static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2924{
2925 struct drm_device *dev = intel_crtc->base.dev;
2926 struct drm_i915_private *dev_priv = dev->dev_private;
2927
2928 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2929 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2930 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2931 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2932 intel_crtc->base.base.id, intel_crtc->pipe, id);
2933}
2934
a1b2278e
CK		 2935/*
2936 * This function detaches (aka. unbinds) unused scalers in hardware
2937 */
0583236e 2938static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2939{
a1b2278e
CK		 2940 struct intel_crtc_scaler_state *scaler_state;
2941 int i;
2942
a1b2278e
CK		 2943 scaler_state = &intel_crtc->config->scaler_state;
2944
2945 /* loop through and disable scalers that aren't in use */
2946 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2947 if (!scaler_state->scalers[i].in_use)
2948 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2949 }
2950}
2951
6156a456 2952u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2953{
6156a456 2954 switch (pixel_format) {
d161cf7a 2955 case DRM_FORMAT_C8:
c34ce3d1 2956 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2957 case DRM_FORMAT_RGB565:
c34ce3d1 2958 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2959 case DRM_FORMAT_XBGR8888:
c34ce3d1 2960 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2961 case DRM_FORMAT_XRGB8888:
c34ce3d1 2962 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2963 /*
2964 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2965 * to be already pre-multiplied. We need to add a knob (or a different
2966 * DRM_FORMAT) for user-space to configure that.
2967 */
f75fb42a 2968 case DRM_FORMAT_ABGR8888:
c34ce3d1 2969 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2970 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2971 case DRM_FORMAT_ARGB8888:
c34ce3d1 2972 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2973 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2974 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2975 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2976 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2977 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2978 case DRM_FORMAT_YUYV:
c34ce3d1 2979 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2980 case DRM_FORMAT_YVYU:
c34ce3d1 2981 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2982 case DRM_FORMAT_UYVY:
c34ce3d1 2983 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2984 case DRM_FORMAT_VYUY:
c34ce3d1 2985 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2986 default:
4249eeef 2987 MISSING_CASE(pixel_format);
70d21f0e 2988 }
8cfcba41 2989
c34ce3d1 2990 return 0;
6156a456 2991}
70d21f0e 2992
6156a456
CK		 2993u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2994{
6156a456 2995 switch (fb_modifier) {
30af77c4 2996 case DRM_FORMAT_MOD_NONE:
70d21f0e 2997 break;
30af77c4 2998 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2999 return PLANE_CTL_TILED_X;
b321803d 3000 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3001 return PLANE_CTL_TILED_Y;
b321803d 3002 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3003 return PLANE_CTL_TILED_YF;
70d21f0e 3004 default:
6156a456 3005 MISSING_CASE(fb_modifier);
70d21f0e 3006 }
8cfcba41 3007
c34ce3d1 3008 return 0;
6156a456 3009}
70d21f0e 3010
6156a456
CK		 3011u32 skl_plane_ctl_rotation(unsigned int rotation)
3012{
3b7a5119 3013 switch (rotation) {
6156a456
CK		 3014 case BIT(DRM_ROTATE_0):
3015 break;
1e8df167
SJ		 3016 /*
3017 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3018 * while i915 HW rotation is clockwise, thats why this swapping.
3019 */
3b7a5119 3020 case BIT(DRM_ROTATE_90):
1e8df167 3021 return PLANE_CTL_ROTATE_270;
3b7a5119 3022 case BIT(DRM_ROTATE_180):
c34ce3d1 3023 return PLANE_CTL_ROTATE_180;
3b7a5119 3024 case BIT(DRM_ROTATE_270):
1e8df167 3025 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3026 default:
3027 MISSING_CASE(rotation);
3028 }
3029
c34ce3d1 3030 return 0;
6156a456
CK		 3031}
3032
3033static void skylake_update_primary_plane(struct drm_crtc *crtc,
3034 struct drm_framebuffer *fb,
3035 int x, int y)
3036{
3037 struct drm_device *dev = crtc->dev;
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3040 struct drm_plane *plane = crtc->primary;
3041 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3042 struct drm_i915_gem_object *obj;
3043 int pipe = intel_crtc->pipe;
3044 u32 plane_ctl, stride_div, stride;
3045 u32 tile_height, plane_offset, plane_size;
3046 unsigned int rotation;
3047 int x_offset, y_offset;
3048 unsigned long surf_addr;
6156a456
CK		 3049 struct intel_crtc_state *crtc_state = intel_crtc->config;
3050 struct intel_plane_state *plane_state;
3051 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3052 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3053 int scaler_id = -1;
3054
6156a456
CK		 3055 plane_state = to_intel_plane_state(plane->state);
3056
b70709a6 3057 if (!visible || !fb) {
6156a456
CK		 3058 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3059 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3060 POSTING_READ(PLANE_CTL(pipe, 0));
3061 return;
3b7a5119 3062 }
70d21f0e 3063
6156a456
CK		 3064 plane_ctl = PLANE_CTL_ENABLE |
3065 PLANE_CTL_PIPE_GAMMA_ENABLE |
3066 PLANE_CTL_PIPE_CSC_ENABLE;
3067
3068 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3069 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3070 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3071
3072 rotation = plane->state->rotation;
3073 plane_ctl |= skl_plane_ctl_rotation(rotation);
3074
b321803d
DL		 3075 obj = intel_fb_obj(fb);
3076 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3077 fb->pixel_format);
3b7a5119
SJ		 3078 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3079
6156a456
CK		 3080 /*
3081 * FIXME: intel_plane_state->src, dst aren't set when transitional
3082 * update_plane helpers are called from legacy paths.
3083 * Once full atomic crtc is available, below check can be avoided.
3084 */
3085 if (drm_rect_width(&plane_state->src)) {
3086 scaler_id = plane_state->scaler_id;
3087 src_x = plane_state->src.x1 >> 16;
3088 src_y = plane_state->src.y1 >> 16;
3089 src_w = drm_rect_width(&plane_state->src) >> 16;
3090 src_h = drm_rect_height(&plane_state->src) >> 16;
3091 dst_x = plane_state->dst.x1;
3092 dst_y = plane_state->dst.y1;
3093 dst_w = drm_rect_width(&plane_state->dst);
3094 dst_h = drm_rect_height(&plane_state->dst);
3095
3096 WARN_ON(x != src_x || y != src_y);
3097 } else {
3098 src_w = intel_crtc->config->pipe_src_w;
3099 src_h = intel_crtc->config->pipe_src_h;
3100 }
3101
3b7a5119
SJ		 3102 if (intel_rotation_90_or_270(rotation)) {
3103 /* stride = Surface height in tiles */
2614f17d 3104 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3105 fb->modifier[0]);
3106 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3107 x_offset = stride * tile_height - y - src_h;
3b7a5119 3108 y_offset = x;
6156a456 3109 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3110 } else {
3111 stride = fb->pitches[0] / stride_div;
3112 x_offset = x;
3113 y_offset = y;
6156a456 3114 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3115 }
3116 plane_offset = y_offset << 16 | x_offset;
b321803d 3117
70d21f0e 3118 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3119 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3120 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3121 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3122
3123 if (scaler_id >= 0) {
3124 uint32_t ps_ctrl = 0;
3125
3126 WARN_ON(!dst_w || !dst_h);
3127 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3128 crtc_state->scaler_state.scalers[scaler_id].mode;
3129 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3130 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3131 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3132 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3133 I915_WRITE(PLANE_POS(pipe, 0), 0);
3134 } else {
3135 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3136 }
3137
121920fa 3138 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3139
3140 POSTING_READ(PLANE_SURF(pipe, 0));
3141}
3142
17638cd6
JB		 3143/* Assume fb object is pinned & idle & fenced and just update base pointers */
3144static int
3145intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3146 int x, int y, enum mode_set_atomic state)
3147{
3148 struct drm_device *dev = crtc->dev;
3149 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3150
ff2a3117 3151 if (dev_priv->fbc.disable_fbc)
7733b49b 3152 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3153
29b9bde6
DV		 3154 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3155
3156 return 0;
81255565
JB		 3157}
3158
7514747d 3159static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3160{
96a02917
VS		 3161 struct drm_crtc *crtc;
3162
70e1e0ec 3163 for_each_crtc(dev, crtc) {
96a02917
VS		 3164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3165 enum plane plane = intel_crtc->plane;
3166
3167 intel_prepare_page_flip(dev, plane);
3168 intel_finish_page_flip_plane(dev, plane);
3169 }
7514747d
VS		 3170}
3171
3172static void intel_update_primary_planes(struct drm_device *dev)
3173{
3174 struct drm_i915_private *dev_priv = dev->dev_private;
3175 struct drm_crtc *crtc;
96a02917 3176
70e1e0ec 3177 for_each_crtc(dev, crtc) {
96a02917
VS		 3178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3179
51fd371b 3180 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3181 /*
3182 * FIXME: Once we have proper support for primary planes (and
3183 * disabling them without disabling the entire crtc) allow again
66e514c1 3184 * a NULL crtc->primary->fb.
947fdaad 3185 */
f4510a27 3186 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3187 dev_priv->display.update_primary_plane(crtc,
66e514c1 3188 crtc->primary->fb,
262ca2b0
MR		 3189 crtc->x,
3190 crtc->y);
51fd371b 3191 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3192 }
3193}
3194
7514747d
VS		 3195void intel_prepare_reset(struct drm_device *dev)
3196{
3197 /* no reset support for gen2 */
3198 if (IS_GEN2(dev))
3199 return;
3200
3201 /* reset doesn't touch the display */
3202 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3203 return;
3204
3205 drm_modeset_lock_all(dev);
f98ce92f
VS		 3206 /*
3207 * Disabling the crtcs gracefully seems nicer. Also the
3208 * g33 docs say we should at least disable all the planes.
3209 */
6b72d486 3210 intel_display_suspend(dev);
7514747d
VS		 3211}
3212
3213void intel_finish_reset(struct drm_device *dev)
3214{
3215 struct drm_i915_private *dev_priv = to_i915(dev);
3216
3217 /*
3218 * Flips in the rings will be nuked by the reset,
3219 * so complete all pending flips so that user space
3220 * will get its events and not get stuck.
3221 */
3222 intel_complete_page_flips(dev);
3223
3224 /* no reset support for gen2 */
3225 if (IS_GEN2(dev))
3226 return;
3227
3228 /* reset doesn't touch the display */
3229 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3230 /*
3231 * Flips in the rings have been nuked by the reset,
3232 * so update the base address of all primary
3233 * planes to the the last fb to make sure we're
3234 * showing the correct fb after a reset.
3235 */
3236 intel_update_primary_planes(dev);
3237 return;
3238 }
3239
3240 /*
3241 * The display has been reset as well,
3242 * so need a full re-initialization.
3243 */
3244 intel_runtime_pm_disable_interrupts(dev_priv);
3245 intel_runtime_pm_enable_interrupts(dev_priv);
3246
3247 intel_modeset_init_hw(dev);
3248
3249 spin_lock_irq(&dev_priv->irq_lock);
3250 if (dev_priv->display.hpd_irq_setup)
3251 dev_priv->display.hpd_irq_setup(dev);
3252 spin_unlock_irq(&dev_priv->irq_lock);
3253
3254 intel_modeset_setup_hw_state(dev, true);
3255
3256 intel_hpd_init(dev_priv);
3257
3258 drm_modeset_unlock_all(dev);
3259}
3260
2e2f351d 3261static void
14667a4b
CW		 3262intel_finish_fb(struct drm_framebuffer *old_fb)
3263{
2ff8fde1 3264 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3265 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3266 bool was_interruptible = dev_priv->mm.interruptible;
3267 int ret;
3268
14667a4b
CW		 3269 /* Big Hammer, we also need to ensure that any pending
3270 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3271 * current scanout is retired before unpinning the old
2e2f351d
CW		 3272 * framebuffer. Note that we rely on userspace rendering
3273 * into the buffer attached to the pipe they are waiting
3274 * on. If not, userspace generates a GPU hang with IPEHR
3275 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3276 *
3277 * This should only fail upon a hung GPU, in which case we
3278 * can safely continue.
3279 */
3280 dev_priv->mm.interruptible = false;
2e2f351d 3281 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3282 dev_priv->mm.interruptible = was_interruptible;
3283
2e2f351d 3284 WARN_ON(ret);
14667a4b
CW		 3285}
3286
7d5e3799
CW		 3287static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3288{
3289 struct drm_device *dev = crtc->dev;
3290 struct drm_i915_private *dev_priv = dev->dev_private;
3291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3292 bool pending;
3293
3294 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3295 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3296 return false;
3297
5e2d7afc 3298 spin_lock_irq(&dev->event_lock);
7d5e3799 3299 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3300 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3301
3302 return pending;
3303}
3304
e30e8f75
GP		 3305static void intel_update_pipe_size(struct intel_crtc *crtc)
3306{
3307 struct drm_device *dev = crtc->base.dev;
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 const struct drm_display_mode *adjusted_mode;
3310
3311 if (!i915.fastboot)
3312 return;
3313
3314 /*
3315 * Update pipe size and adjust fitter if needed: the reason for this is
3316 * that in compute_mode_changes we check the native mode (not the pfit
3317 * mode) to see if we can flip rather than do a full mode set. In the
3318 * fastboot case, we'll flip, but if we don't update the pipesrc and
3319 * pfit state, we'll end up with a big fb scanned out into the wrong
3320 * sized surface.
3321 *
3322 * To fix this properly, we need to hoist the checks up into
3323 * compute_mode_changes (or above), check the actual pfit state and
3324 * whether the platform allows pfit disable with pipe active, and only
3325 * then update the pipesrc and pfit state, even on the flip path.
3326 */
3327
6e3c9717 3328 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3329
3330 I915_WRITE(PIPESRC(crtc->pipe),
3331 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3332 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3333 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3334 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3335 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3336 I915_WRITE(PF_CTL(crtc->pipe), 0);
3337 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3338 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3339 }
6e3c9717
ACO		 3340 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3341 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3342}
3343
5e84e1a4
ZW		 3344static void intel_fdi_normal_train(struct drm_crtc *crtc)
3345{
3346 struct drm_device *dev = crtc->dev;
3347 struct drm_i915_private *dev_priv = dev->dev_private;
3348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3349 int pipe = intel_crtc->pipe;
3350 u32 reg, temp;
3351
3352 /* enable normal train */
3353 reg = FDI_TX_CTL(pipe);
3354 temp = I915_READ(reg);
61e499bf 3355 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3356 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3357 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3358 } else {
3359 temp &= ~FDI_LINK_TRAIN_NONE;
3360 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3361 }
5e84e1a4
ZW		 3362 I915_WRITE(reg, temp);
3363
3364 reg = FDI_RX_CTL(pipe);
3365 temp = I915_READ(reg);
3366 if (HAS_PCH_CPT(dev)) {
3367 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3368 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3369 } else {
3370 temp &= ~FDI_LINK_TRAIN_NONE;
3371 temp |= FDI_LINK_TRAIN_NONE;
3372 }
3373 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3374
3375 /* wait one idle pattern time */
3376 POSTING_READ(reg);
3377 udelay(1000);
357555c0
JB		 3378
3379 /* IVB wants error correction enabled */
3380 if (IS_IVYBRIDGE(dev))
3381 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3382 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3383}
3384
8db9d77b
ZW		 3385/* The FDI link training functions for ILK/Ibexpeak. */
3386static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3387{
3388 struct drm_device *dev = crtc->dev;
3389 struct drm_i915_private *dev_priv = dev->dev_private;
3390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3391 int pipe = intel_crtc->pipe;
5eddb70b 3392 u32 reg, temp, tries;
8db9d77b 3393
1c8562f6 3394 /* FDI needs bits from pipe first */
0fc932b8 3395 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3396
e1a44743
AJ		 3397 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3398 for train result */
5eddb70b
CW		 3399 reg = FDI_RX_IMR(pipe);
3400 temp = I915_READ(reg);
e1a44743
AJ		 3401 temp &= ~FDI_RX_SYMBOL_LOCK;
3402 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3403 I915_WRITE(reg, temp);
3404 I915_READ(reg);
e1a44743
AJ		 3405 udelay(150);
3406
8db9d77b 3407 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3408 reg = FDI_TX_CTL(pipe);
3409 temp = I915_READ(reg);
627eb5a3 3410 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3411 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3412 temp &= ~FDI_LINK_TRAIN_NONE;
3413 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3414 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3415
5eddb70b
CW		 3416 reg = FDI_RX_CTL(pipe);
3417 temp = I915_READ(reg);
8db9d77b
ZW		 3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3420 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3421
3422 POSTING_READ(reg);
8db9d77b
ZW		 3423 udelay(150);
3424
5b2adf89 3425 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3426 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3427 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3428 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3429
5eddb70b 3430 reg = FDI_RX_IIR(pipe);
e1a44743 3431 for (tries = 0; tries < 5; tries++) {
5eddb70b 3432 temp = I915_READ(reg);
8db9d77b
ZW		 3433 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3434
3435 if ((temp & FDI_RX_BIT_LOCK)) {
3436 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3437 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3438 break;
3439 }
8db9d77b 3440 }
e1a44743 3441 if (tries == 5)
5eddb70b 3442 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3443
3444 /* Train 2 */
5eddb70b
CW		 3445 reg = FDI_TX_CTL(pipe);
3446 temp = I915_READ(reg);
8db9d77b
ZW		 3447 temp &= ~FDI_LINK_TRAIN_NONE;
3448 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3449 I915_WRITE(reg, temp);
8db9d77b 3450
5eddb70b
CW		 3451 reg = FDI_RX_CTL(pipe);
3452 temp = I915_READ(reg);
8db9d77b
ZW		 3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3455 I915_WRITE(reg, temp);
8db9d77b 3456
5eddb70b
CW		 3457 POSTING_READ(reg);
3458 udelay(150);
8db9d77b 3459
5eddb70b 3460 reg = FDI_RX_IIR(pipe);
e1a44743 3461 for (tries = 0; tries < 5; tries++) {
5eddb70b 3462 temp = I915_READ(reg);
8db9d77b
ZW		 3463 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3464
3465 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3466 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3467 DRM_DEBUG_KMS("FDI train 2 done.\n");
3468 break;
3469 }
8db9d77b 3470 }
e1a44743 3471 if (tries == 5)
5eddb70b 3472 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3473
3474 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3475
8db9d77b
ZW		 3476}
3477
0206e353 3478static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3479 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3480 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3481 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3482 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3483};
3484
3485/* The FDI link training functions for SNB/Cougarpoint. */
3486static void gen6_fdi_link_train(struct drm_crtc *crtc)
3487{
3488 struct drm_device *dev = crtc->dev;
3489 struct drm_i915_private *dev_priv = dev->dev_private;
3490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3491 int pipe = intel_crtc->pipe;
fa37d39e 3492 u32 reg, temp, i, retry;
8db9d77b 3493
e1a44743
AJ		 3494 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3495 for train result */
5eddb70b
CW		 3496 reg = FDI_RX_IMR(pipe);
3497 temp = I915_READ(reg);
e1a44743
AJ		 3498 temp &= ~FDI_RX_SYMBOL_LOCK;
3499 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3500 I915_WRITE(reg, temp);
3501
3502 POSTING_READ(reg);
e1a44743
AJ		 3503 udelay(150);
3504
8db9d77b 3505 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3506 reg = FDI_TX_CTL(pipe);
3507 temp = I915_READ(reg);
627eb5a3 3508 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3509 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3510 temp &= ~FDI_LINK_TRAIN_NONE;
3511 temp |= FDI_LINK_TRAIN_PATTERN_1;
3512 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3513 /* SNB-B */
3514 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3515 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3516
d74cf324
DV		 3517 I915_WRITE(FDI_RX_MISC(pipe),
3518 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3519
5eddb70b
CW		 3520 reg = FDI_RX_CTL(pipe);
3521 temp = I915_READ(reg);
8db9d77b
ZW		 3522 if (HAS_PCH_CPT(dev)) {
3523 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3524 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3525 } else {
3526 temp &= ~FDI_LINK_TRAIN_NONE;
3527 temp |= FDI_LINK_TRAIN_PATTERN_1;
3528 }
5eddb70b
CW		 3529 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3530
3531 POSTING_READ(reg);
8db9d77b
ZW		 3532 udelay(150);
3533
0206e353 3534 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3535 reg = FDI_TX_CTL(pipe);
3536 temp = I915_READ(reg);
8db9d77b
ZW		 3537 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3538 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3539 I915_WRITE(reg, temp);
3540
3541 POSTING_READ(reg);
8db9d77b
ZW		 3542 udelay(500);
3543
fa37d39e
SP		 3544 for (retry = 0; retry < 5; retry++) {
3545 reg = FDI_RX_IIR(pipe);
3546 temp = I915_READ(reg);
3547 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3548 if (temp & FDI_RX_BIT_LOCK) {
3549 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3550 DRM_DEBUG_KMS("FDI train 1 done.\n");
3551 break;
3552 }
3553 udelay(50);
8db9d77b 3554 }
fa37d39e
SP		 3555 if (retry < 5)
3556 break;
8db9d77b
ZW		 3557 }
3558 if (i == 4)
5eddb70b 3559 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3560
3561 /* Train 2 */
5eddb70b
CW		 3562 reg = FDI_TX_CTL(pipe);
3563 temp = I915_READ(reg);
8db9d77b
ZW		 3564 temp &= ~FDI_LINK_TRAIN_NONE;
3565 temp |= FDI_LINK_TRAIN_PATTERN_2;
3566 if (IS_GEN6(dev)) {
3567 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3568 /* SNB-B */
3569 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3570 }
5eddb70b 3571 I915_WRITE(reg, temp);
8db9d77b 3572
5eddb70b
CW		 3573 reg = FDI_RX_CTL(pipe);
3574 temp = I915_READ(reg);
8db9d77b
ZW		 3575 if (HAS_PCH_CPT(dev)) {
3576 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3577 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3578 } else {
3579 temp &= ~FDI_LINK_TRAIN_NONE;
3580 temp |= FDI_LINK_TRAIN_PATTERN_2;
3581 }
5eddb70b
CW		 3582 I915_WRITE(reg, temp);
3583
3584 POSTING_READ(reg);
8db9d77b
ZW		 3585 udelay(150);
3586
0206e353 3587 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3588 reg = FDI_TX_CTL(pipe);
3589 temp = I915_READ(reg);
8db9d77b
ZW		 3590 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3591 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3592 I915_WRITE(reg, temp);
3593
3594 POSTING_READ(reg);
8db9d77b
ZW		 3595 udelay(500);
3596
fa37d39e
SP		 3597 for (retry = 0; retry < 5; retry++) {
3598 reg = FDI_RX_IIR(pipe);
3599 temp = I915_READ(reg);
3600 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3601 if (temp & FDI_RX_SYMBOL_LOCK) {
3602 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3603 DRM_DEBUG_KMS("FDI train 2 done.\n");
3604 break;
3605 }
3606 udelay(50);
8db9d77b 3607 }
fa37d39e
SP		 3608 if (retry < 5)
3609 break;
8db9d77b
ZW		 3610 }
3611 if (i == 4)
5eddb70b 3612 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3613
3614 DRM_DEBUG_KMS("FDI train done.\n");
3615}
3616
357555c0
JB		 3617/* Manual link training for Ivy Bridge A0 parts */
3618static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3619{
3620 struct drm_device *dev = crtc->dev;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3623 int pipe = intel_crtc->pipe;
139ccd3f 3624 u32 reg, temp, i, j;
357555c0
JB		 3625
3626 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3627 for train result */
3628 reg = FDI_RX_IMR(pipe);
3629 temp = I915_READ(reg);
3630 temp &= ~FDI_RX_SYMBOL_LOCK;
3631 temp &= ~FDI_RX_BIT_LOCK;
3632 I915_WRITE(reg, temp);
3633
3634 POSTING_READ(reg);
3635 udelay(150);
3636
01a415fd
DV		 3637 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3638 I915_READ(FDI_RX_IIR(pipe)));
3639
139ccd3f
JB		 3640 /* Try each vswing and preemphasis setting twice before moving on */
3641 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3642 /* disable first in case we need to retry */
3643 reg = FDI_TX_CTL(pipe);
3644 temp = I915_READ(reg);
3645 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3646 temp &= ~FDI_TX_ENABLE;
3647 I915_WRITE(reg, temp);
357555c0 3648
139ccd3f
JB		 3649 reg = FDI_RX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~FDI_LINK_TRAIN_AUTO;
3652 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3653 temp &= ~FDI_RX_ENABLE;
3654 I915_WRITE(reg, temp);
357555c0 3655
139ccd3f 3656 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3657 reg = FDI_TX_CTL(pipe);
3658 temp = I915_READ(reg);
139ccd3f 3659 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3660 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3661 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3662 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3663 temp |= snb_b_fdi_train_param[j/2];
3664 temp |= FDI_COMPOSITE_SYNC;
3665 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3666
139ccd3f
JB		 3667 I915_WRITE(FDI_RX_MISC(pipe),
3668 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3669
139ccd3f 3670 reg = FDI_RX_CTL(pipe);
357555c0 3671 temp = I915_READ(reg);
139ccd3f
JB		 3672 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3673 temp |= FDI_COMPOSITE_SYNC;
3674 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3675
139ccd3f
JB		 3676 POSTING_READ(reg);
3677 udelay(1); /* should be 0.5us */
357555c0 3678
139ccd3f
JB		 3679 for (i = 0; i < 4; i++) {
3680 reg = FDI_RX_IIR(pipe);
3681 temp = I915_READ(reg);
3682 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3683
139ccd3f
JB		 3684 if (temp & FDI_RX_BIT_LOCK ||
3685 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3686 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3687 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3688 i);
3689 break;
3690 }
3691 udelay(1); /* should be 0.5us */
3692 }
3693 if (i == 4) {
3694 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3695 continue;
3696 }
357555c0 3697
139ccd3f 3698 /* Train 2 */
357555c0
JB		 3699 reg = FDI_TX_CTL(pipe);
3700 temp = I915_READ(reg);
139ccd3f
JB		 3701 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3702 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3703 I915_WRITE(reg, temp);
3704
3705 reg = FDI_RX_CTL(pipe);
3706 temp = I915_READ(reg);
3707 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3708 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3709 I915_WRITE(reg, temp);
3710
3711 POSTING_READ(reg);
139ccd3f 3712 udelay(2); /* should be 1.5us */
357555c0 3713
139ccd3f
JB		 3714 for (i = 0; i < 4; i++) {
3715 reg = FDI_RX_IIR(pipe);
3716 temp = I915_READ(reg);
3717 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3718
139ccd3f
JB		 3719 if (temp & FDI_RX_SYMBOL_LOCK ||
3720 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3721 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3722 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3723 i);
3724 goto train_done;
3725 }
3726 udelay(2); /* should be 1.5us */
357555c0 3727 }
139ccd3f
JB		 3728 if (i == 4)
3729 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3730 }
357555c0 3731
139ccd3f 3732train_done:
357555c0
JB		 3733 DRM_DEBUG_KMS("FDI train done.\n");
3734}
3735
88cefb6c 3736static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3737{
88cefb6c 3738 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3739 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3740 int pipe = intel_crtc->pipe;
5eddb70b 3741 u32 reg, temp;
79e53945 3742
c64e311e 3743
c98e9dcf 3744 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3745 reg = FDI_RX_CTL(pipe);
3746 temp = I915_READ(reg);
627eb5a3 3747 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3748 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3749 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3750 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3751
3752 POSTING_READ(reg);
c98e9dcf
JB		 3753 udelay(200);
3754
3755 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3756 temp = I915_READ(reg);
3757 I915_WRITE(reg, temp | FDI_PCDCLK);
3758
3759 POSTING_READ(reg);
c98e9dcf
JB		 3760 udelay(200);
3761
20749730
PZ		 3762 /* Enable CPU FDI TX PLL, always on for Ironlake */
3763 reg = FDI_TX_CTL(pipe);
3764 temp = I915_READ(reg);
3765 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3766 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3767
20749730
PZ		 3768 POSTING_READ(reg);
3769 udelay(100);
6be4a607 3770 }
0e23b99d
JB		 3771}
3772
88cefb6c
DV		 3773static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3774{
3775 struct drm_device *dev = intel_crtc->base.dev;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 int pipe = intel_crtc->pipe;
3778 u32 reg, temp;
3779
3780 /* Switch from PCDclk to Rawclk */
3781 reg = FDI_RX_CTL(pipe);
3782 temp = I915_READ(reg);
3783 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3784
3785 /* Disable CPU FDI TX PLL */
3786 reg = FDI_TX_CTL(pipe);
3787 temp = I915_READ(reg);
3788 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3789
3790 POSTING_READ(reg);
3791 udelay(100);
3792
3793 reg = FDI_RX_CTL(pipe);
3794 temp = I915_READ(reg);
3795 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3796
3797 /* Wait for the clocks to turn off. */
3798 POSTING_READ(reg);
3799 udelay(100);
3800}
3801
0fc932b8
JB		 3802static void ironlake_fdi_disable(struct drm_crtc *crtc)
3803{
3804 struct drm_device *dev = crtc->dev;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3807 int pipe = intel_crtc->pipe;
3808 u32 reg, temp;
3809
3810 /* disable CPU FDI tx and PCH FDI rx */
3811 reg = FDI_TX_CTL(pipe);
3812 temp = I915_READ(reg);
3813 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3814 POSTING_READ(reg);
3815
3816 reg = FDI_RX_CTL(pipe);
3817 temp = I915_READ(reg);
3818 temp &= ~(0x7 << 16);
dfd07d72 3819 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3820 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3821
3822 POSTING_READ(reg);
3823 udelay(100);
3824
3825 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3826 if (HAS_PCH_IBX(dev))
6f06ce18 3827 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3828
3829 /* still set train pattern 1 */
3830 reg = FDI_TX_CTL(pipe);
3831 temp = I915_READ(reg);
3832 temp &= ~FDI_LINK_TRAIN_NONE;
3833 temp |= FDI_LINK_TRAIN_PATTERN_1;
3834 I915_WRITE(reg, temp);
3835
3836 reg = FDI_RX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 if (HAS_PCH_CPT(dev)) {
3839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3841 } else {
3842 temp &= ~FDI_LINK_TRAIN_NONE;
3843 temp |= FDI_LINK_TRAIN_PATTERN_1;
3844 }
3845 /* BPC in FDI rx is consistent with that in PIPECONF */
3846 temp &= ~(0x07 << 16);
dfd07d72 3847 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3848 I915_WRITE(reg, temp);
3849
3850 POSTING_READ(reg);
3851 udelay(100);
3852}
3853
5dce5b93
CW		 3854bool intel_has_pending_fb_unpin(struct drm_device *dev)
3855{
3856 struct intel_crtc *crtc;
3857
3858 /* Note that we don't need to be called with mode_config.lock here
3859 * as our list of CRTC objects is static for the lifetime of the
3860 * device and so cannot disappear as we iterate. Similarly, we can
3861 * happily treat the predicates as racy, atomic checks as userspace
3862 * cannot claim and pin a new fb without at least acquring the
3863 * struct_mutex and so serialising with us.
3864 */
d3fcc808 3865 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3866 if (atomic_read(&crtc->unpin_work_count) == 0)
3867 continue;
3868
3869 if (crtc->unpin_work)
3870 intel_wait_for_vblank(dev, crtc->pipe);
3871
3872 return true;
3873 }
3874
3875 return false;
3876}
3877
d6bbafa1
CW		 3878static void page_flip_completed(struct intel_crtc *intel_crtc)
3879{
3880 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3881 struct intel_unpin_work *work = intel_crtc->unpin_work;
3882
3883 /* ensure that the unpin work is consistent wrt ->pending. */
3884 smp_rmb();
3885 intel_crtc->unpin_work = NULL;
3886
3887 if (work->event)
3888 drm_send_vblank_event(intel_crtc->base.dev,
3889 intel_crtc->pipe,
3890 work->event);
3891
3892 drm_crtc_vblank_put(&intel_crtc->base);
3893
3894 wake_up_all(&dev_priv->pending_flip_queue);
3895 queue_work(dev_priv->wq, &work->work);
3896
3897 trace_i915_flip_complete(intel_crtc->plane,
3898 work->pending_flip_obj);
3899}
3900
46a55d30 3901void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3902{
0f91128d 3903 struct drm_device *dev = crtc->dev;
5bb61643 3904 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3905
2c10d571 3906 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3907 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3908 !intel_crtc_has_pending_flip(crtc),
3909 60*HZ) == 0)) {
3910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3911
5e2d7afc 3912 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3913 if (intel_crtc->unpin_work) {
3914 WARN_ONCE(1, "Removing stuck page flip\n");
3915 page_flip_completed(intel_crtc);
3916 }
5e2d7afc 3917 spin_unlock_irq(&dev->event_lock);
9c787942 3918 }
5bb61643 3919
975d568a
CW		 3920 if (crtc->primary->fb) {
3921 mutex_lock(&dev->struct_mutex);
3922 intel_finish_fb(crtc->primary->fb);
3923 mutex_unlock(&dev->struct_mutex);
3924 }
e6c3a2a6
CW		 3925}
3926
e615efe4
ED		 3927/* Program iCLKIP clock to the desired frequency */
3928static void lpt_program_iclkip(struct drm_crtc *crtc)
3929{
3930 struct drm_device *dev = crtc->dev;
3931 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3932 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3933 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3934 u32 temp;
3935
a580516d 3936 mutex_lock(&dev_priv->sb_lock);
09153000 3937
e615efe4
ED		 3938 /* It is necessary to ungate the pixclk gate prior to programming
3939 * the divisors, and gate it back when it is done.
3940 */
3941 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3942
3943 /* Disable SSCCTL */
3944 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3945 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3946 SBI_SSCCTL_DISABLE,
3947 SBI_ICLK);
e615efe4
ED		 3948
3949 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3950 if (clock == 20000) {
e615efe4
ED		 3951 auxdiv = 1;
3952 divsel = 0x41;
3953 phaseinc = 0x20;
3954 } else {
3955 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3956 * but the adjusted_mode->crtc_clock in in KHz. To get the
3957 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3958 * convert the virtual clock precision to KHz here for higher
3959 * precision.
3960 */
3961 u32 iclk_virtual_root_freq = 172800 * 1000;
3962 u32 iclk_pi_range = 64;
3963 u32 desired_divisor, msb_divisor_value, pi_value;
3964
12d7ceed 3965 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3966 msb_divisor_value = desired_divisor / iclk_pi_range;
3967 pi_value = desired_divisor % iclk_pi_range;
3968
3969 auxdiv = 0;
3970 divsel = msb_divisor_value - 2;
3971 phaseinc = pi_value;
3972 }
3973
3974 /* This should not happen with any sane values */
3975 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3976 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3977 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3978 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3979
3980 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3981 clock,
e615efe4
ED		 3982 auxdiv,
3983 divsel,
3984 phasedir,
3985 phaseinc);
3986
3987 /* Program SSCDIVINTPHASE6 */
988d6ee8 3988 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3989 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3990 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3991 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3992 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3993 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3994 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3995 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3996
3997 /* Program SSCAUXDIV */
988d6ee8 3998 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3999 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4000 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4001 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4002
4003 /* Enable modulator and associated divider */
988d6ee8 4004 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4005 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4006 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4007
4008 /* Wait for initialization time */
4009 udelay(24);
4010
4011 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4012
a580516d 4013 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4014}
4015
275f01b2
DV		 4016static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4017 enum pipe pch_transcoder)
4018{
4019 struct drm_device *dev = crtc->base.dev;
4020 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4021 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4022
4023 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4024 I915_READ(HTOTAL(cpu_transcoder)));
4025 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4026 I915_READ(HBLANK(cpu_transcoder)));
4027 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4028 I915_READ(HSYNC(cpu_transcoder)));
4029
4030 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4031 I915_READ(VTOTAL(cpu_transcoder)));
4032 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4033 I915_READ(VBLANK(cpu_transcoder)));
4034 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4035 I915_READ(VSYNC(cpu_transcoder)));
4036 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4037 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4038}
4039
003632d9 4040static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4041{
4042 struct drm_i915_private *dev_priv = dev->dev_private;
4043 uint32_t temp;
4044
4045 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4046 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4047 return;
4048
4049 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4050 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4051
003632d9
ACO		 4052 temp &= ~FDI_BC_BIFURCATION_SELECT;
4053 if (enable)
4054 temp |= FDI_BC_BIFURCATION_SELECT;
4055
4056 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4057 I915_WRITE(SOUTH_CHICKEN1, temp);
4058 POSTING_READ(SOUTH_CHICKEN1);
4059}
4060
4061static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4062{
4063 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4064
4065 switch (intel_crtc->pipe) {
4066 case PIPE_A:
4067 break;
4068 case PIPE_B:
6e3c9717 4069 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4070 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4071 else
003632d9 4072 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4073
4074 break;
4075 case PIPE_C:
003632d9 4076 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4077
4078 break;
4079 default:
4080 BUG();
4081 }
4082}
4083
f67a559d
JB		 4084/*
4085 * Enable PCH resources required for PCH ports:
4086 * - PCH PLLs
4087 * - FDI training & RX/TX
4088 * - update transcoder timings
4089 * - DP transcoding bits
4090 * - transcoder
4091 */
4092static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4093{
4094 struct drm_device *dev = crtc->dev;
4095 struct drm_i915_private *dev_priv = dev->dev_private;
4096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4097 int pipe = intel_crtc->pipe;
ee7b9f93 4098 u32 reg, temp;
2c07245f 4099
ab9412ba 4100 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4101
1fbc0d78
DV		 4102 if (IS_IVYBRIDGE(dev))
4103 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4104
cd986abb
DV		 4105 /* Write the TU size bits before fdi link training, so that error
4106 * detection works. */
4107 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4108 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4109
c98e9dcf 4110 /* For PCH output, training FDI link */
674cf967 4111 dev_priv->display.fdi_link_train(crtc);
2c07245f 4112
3ad8a208
DV		 4113 /* We need to program the right clock selection before writing the pixel
4114 * mutliplier into the DPLL. */
303b81e0 4115 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4116 u32 sel;
4b645f14 4117
c98e9dcf 4118 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4119 temp |= TRANS_DPLL_ENABLE(pipe);
4120 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4121 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4122 temp |= sel;
4123 else
4124 temp &= ~sel;
c98e9dcf 4125 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4126 }
5eddb70b 4127
3ad8a208
DV		 4128 /* XXX: pch pll's can be enabled any time before we enable the PCH
4129 * transcoder, and we actually should do this to not upset any PCH
4130 * transcoder that already use the clock when we share it.
4131 *
4132 * Note that enable_shared_dpll tries to do the right thing, but
4133 * get_shared_dpll unconditionally resets the pll - we need that to have
4134 * the right LVDS enable sequence. */
85b3894f 4135 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4136
d9b6cb56
JB		 4137 /* set transcoder timing, panel must allow it */
4138 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4139 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4140
303b81e0 4141 intel_fdi_normal_train(crtc);
5e84e1a4 4142
c98e9dcf 4143 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4144 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4145 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4146 reg = TRANS_DP_CTL(pipe);
4147 temp = I915_READ(reg);
4148 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4149 TRANS_DP_SYNC_MASK |
4150 TRANS_DP_BPC_MASK);
e3ef4479 4151 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4152 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4153
4154 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4155 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4156 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4157 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4158
4159 switch (intel_trans_dp_port_sel(crtc)) {
4160 case PCH_DP_B:
5eddb70b 4161 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4162 break;
4163 case PCH_DP_C:
5eddb70b 4164 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4165 break;
4166 case PCH_DP_D:
5eddb70b 4167 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4168 break;
4169 default:
e95d41e1 4170 BUG();
32f9d658 4171 }
2c07245f 4172
5eddb70b 4173 I915_WRITE(reg, temp);
6be4a607 4174 }
b52eb4dc 4175
b8a4f404 4176 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4177}
4178
1507e5bd
PZ		 4179static void lpt_pch_enable(struct drm_crtc *crtc)
4180{
4181 struct drm_device *dev = crtc->dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4184 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4185
ab9412ba 4186 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4187
8c52b5e8 4188 lpt_program_iclkip(crtc);
1507e5bd 4189
0540e488 4190 /* Set transcoder timing. */
275f01b2 4191 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4192
937bb610 4193 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4194}
4195
190f68c5
ACO		 4196struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4197 struct intel_crtc_state *crtc_state)
ee7b9f93 4198{
e2b78267 4199 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4200 struct intel_shared_dpll *pll;
de419ab6 4201 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4202 enum intel_dpll_id i;
ee7b9f93 4203
de419ab6
ML		 4204 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4205
98b6bd99
DV		 4206 if (HAS_PCH_IBX(dev_priv->dev)) {
4207 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4208 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4209 pll = &dev_priv->shared_dplls[i];
98b6bd99 4210
46edb027
DV		 4211 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4212 crtc->base.base.id, pll->name);
98b6bd99 4213
de419ab6 4214 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4215
98b6bd99
DV		 4216 goto found;
4217 }
4218
bcddf610
S		 4219 if (IS_BROXTON(dev_priv->dev)) {
4220 /* PLL is attached to port in bxt */
4221 struct intel_encoder *encoder;
4222 struct intel_digital_port *intel_dig_port;
4223
4224 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4225 if (WARN_ON(!encoder))
4226 return NULL;
4227
4228 intel_dig_port = enc_to_dig_port(&encoder->base);
4229 /* 1:1 mapping between ports and PLLs */
4230 i = (enum intel_dpll_id)intel_dig_port->port;
4231 pll = &dev_priv->shared_dplls[i];
4232 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4233 crtc->base.base.id, pll->name);
de419ab6 4234 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4235
4236 goto found;
4237 }
4238
e72f9fbf
DV		 4239 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4240 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4241
4242 /* Only want to check enabled timings first */
de419ab6 4243 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4244 continue;
4245
190f68c5 4246 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4247 &shared_dpll[i].hw_state,
4248 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4249 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4250 crtc->base.base.id, pll->name,
de419ab6 4251 shared_dpll[i].crtc_mask,
8bd31e67 4252 pll->active);
ee7b9f93
JB		 4253 goto found;
4254 }
4255 }
4256
4257 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4258 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4259 pll = &dev_priv->shared_dplls[i];
de419ab6 4260 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4261 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4262 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4263 goto found;
4264 }
4265 }
4266
4267 return NULL;
4268
4269found:
de419ab6
ML		 4270 if (shared_dpll[i].crtc_mask == 0)
4271 shared_dpll[i].hw_state =
4272 crtc_state->dpll_hw_state;
f2a69f44 4273
190f68c5 4274 crtc_state->shared_dpll = i;
46edb027
DV		 4275 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4276 pipe_name(crtc->pipe));
ee7b9f93 4277
de419ab6 4278 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4279
ee7b9f93
JB		 4280 return pll;
4281}
4282
de419ab6 4283static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4284{
de419ab6
ML		 4285 struct drm_i915_private *dev_priv = to_i915(state->dev);
4286 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4287 struct intel_shared_dpll *pll;
4288 enum intel_dpll_id i;
4289
de419ab6
ML		 4290 if (!to_intel_atomic_state(state)->dpll_set)
4291 return;
8bd31e67 4292
de419ab6 4293 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4294 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4295 pll = &dev_priv->shared_dplls[i];
de419ab6 4296 pll->config = shared_dpll[i];
8bd31e67
ACO		 4297 }
4298}
4299
a1520318 4300static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4301{
4302 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4303 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4304 u32 temp;
4305
4306 temp = I915_READ(dslreg);
4307 udelay(500);
4308 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4309 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4310 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4311 }
4312}
4313
86adf9d7
ML		 4314static int
4315skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4316 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4317 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4318{
86adf9d7
ML		 4319 struct intel_crtc_scaler_state *scaler_state =
4320 &crtc_state->scaler_state;
4321 struct intel_crtc *intel_crtc =
4322 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4323 int need_scaling;
6156a456
CK		 4324
4325 need_scaling = intel_rotation_90_or_270(rotation) ?
4326 (src_h != dst_w || src_w != dst_h):
4327 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4328
4329 /*
4330 * if plane is being disabled or scaler is no more required or force detach
4331 * - free scaler binded to this plane/crtc
4332 * - in order to do this, update crtc->scaler_usage
4333 *
4334 * Here scaler state in crtc_state is set free so that
4335 * scaler can be assigned to other user. Actual register
4336 * update to free the scaler is done in plane/panel-fit programming.
4337 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4338 */
86adf9d7 4339 if (force_detach || !need_scaling) {
a1b2278e 4340 if (*scaler_id >= 0) {
86adf9d7 4341 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4342 scaler_state->scalers[*scaler_id].in_use = 0;
4343
86adf9d7
ML		 4344 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4345 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4346 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4347 scaler_state->scaler_users);
4348 *scaler_id = -1;
4349 }
4350 return 0;
4351 }
4352
4353 /* range checks */
4354 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4355 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4356
4357 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4358 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4359 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4360 "size is out of scaler range\n",
86adf9d7 4361 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4362 return -EINVAL;
4363 }
4364
86adf9d7
ML		 4365 /* mark this plane as a scaler user in crtc_state */
4366 scaler_state->scaler_users |= (1 << scaler_user);
4367 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4368 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4369 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4370 scaler_state->scaler_users);
4371
4372 return 0;
4373}
4374
4375/**
4376 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4377 *
4378 * @state: crtc's scaler state
86adf9d7
ML		 4379 *
4380 * Return
4381 * 0 - scaler_usage updated successfully
4382 * error - requested scaling cannot be supported or other error condition
4383 */
e435d6e5 4384int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4385{
4386 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4387 struct drm_display_mode *adjusted_mode =
4388 &state->base.adjusted_mode;
4389
4390 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4391 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4392
e435d6e5 4393 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4394 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4395 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4396 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4397}
4398
4399/**
4400 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4401 *
4402 * @state: crtc's scaler state
86adf9d7
ML		 4403 * @plane_state: atomic plane state to update
4404 *
4405 * Return
4406 * 0 - scaler_usage updated successfully
4407 * error - requested scaling cannot be supported or other error condition
4408 */
da20eabd
ML		 4409static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4410 struct intel_plane_state *plane_state)
86adf9d7
ML		 4411{
4412
4413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4414 struct intel_plane *intel_plane =
4415 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4416 struct drm_framebuffer *fb = plane_state->base.fb;
4417 int ret;
4418
4419 bool force_detach = !fb || !plane_state->visible;
4420
4421 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4422 intel_plane->base.base.id, intel_crtc->pipe,
4423 drm_plane_index(&intel_plane->base));
4424
4425 ret = skl_update_scaler(crtc_state, force_detach,
4426 drm_plane_index(&intel_plane->base),
4427 &plane_state->scaler_id,
4428 plane_state->base.rotation,
4429 drm_rect_width(&plane_state->src) >> 16,
4430 drm_rect_height(&plane_state->src) >> 16,
4431 drm_rect_width(&plane_state->dst),
4432 drm_rect_height(&plane_state->dst));
4433
4434 if (ret || plane_state->scaler_id < 0)
4435 return ret;
4436
a1b2278e 4437 /* check colorkey */
818ed961 4438 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4439 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4440 intel_plane->base.base.id);
a1b2278e
CK		 4441 return -EINVAL;
4442 }
4443
4444 /* Check src format */
86adf9d7
ML		 4445 switch (fb->pixel_format) {
4446 case DRM_FORMAT_RGB565:
4447 case DRM_FORMAT_XBGR8888:
4448 case DRM_FORMAT_XRGB8888:
4449 case DRM_FORMAT_ABGR8888:
4450 case DRM_FORMAT_ARGB8888:
4451 case DRM_FORMAT_XRGB2101010:
4452 case DRM_FORMAT_XBGR2101010:
4453 case DRM_FORMAT_YUYV:
4454 case DRM_FORMAT_YVYU:
4455 case DRM_FORMAT_UYVY:
4456 case DRM_FORMAT_VYUY:
4457 break;
4458 default:
4459 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4460 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4461 return -EINVAL;
a1b2278e
CK		 4462 }
4463
a1b2278e
CK		 4464 return 0;
4465}
4466
e435d6e5
ML		 4467static void skylake_scaler_disable(struct intel_crtc *crtc)
4468{
4469 int i;
4470
4471 for (i = 0; i < crtc->num_scalers; i++)
4472 skl_detach_scaler(crtc, i);
4473}
4474
4475static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4476{
4477 struct drm_device *dev = crtc->base.dev;
4478 struct drm_i915_private *dev_priv = dev->dev_private;
4479 int pipe = crtc->pipe;
a1b2278e
CK		 4480 struct intel_crtc_scaler_state *scaler_state =
4481 &crtc->config->scaler_state;
4482
4483 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4484
6e3c9717 4485 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4486 int id;
4487
4488 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4489 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4490 return;
4491 }
4492
4493 id = scaler_state->scaler_id;
4494 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4495 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4496 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4497 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4498
4499 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4500 }
4501}
4502
b074cec8
JB		 4503static void ironlake_pfit_enable(struct intel_crtc *crtc)
4504{
4505 struct drm_device *dev = crtc->base.dev;
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4507 int pipe = crtc->pipe;
4508
6e3c9717 4509 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4510 /* Force use of hard-coded filter coefficients
4511 * as some pre-programmed values are broken,
4512 * e.g. x201.
4513 */
4514 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4515 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4516 PF_PIPE_SEL_IVB(pipe));
4517 else
4518 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4519 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4520 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4521 }
4522}
4523
20bc8673 4524void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4525{
cea165c3
VS		 4526 struct drm_device *dev = crtc->base.dev;
4527 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4528
6e3c9717 4529 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4530 return;
4531
cea165c3
VS		 4532 /* We can only enable IPS after we enable a plane and wait for a vblank */
4533 intel_wait_for_vblank(dev, crtc->pipe);
4534
d77e4531 4535 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4536 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4537 mutex_lock(&dev_priv->rps.hw_lock);
4538 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4539 mutex_unlock(&dev_priv->rps.hw_lock);
4540 /* Quoting Art Runyan: "its not safe to expect any particular
4541 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4542 * mailbox." Moreover, the mailbox may return a bogus state,
4543 * so we need to just enable it and continue on.
2a114cc1
BW		 4544 */
4545 } else {
4546 I915_WRITE(IPS_CTL, IPS_ENABLE);
4547 /* The bit only becomes 1 in the next vblank, so this wait here
4548 * is essentially intel_wait_for_vblank. If we don't have this
4549 * and don't wait for vblanks until the end of crtc_enable, then
4550 * the HW state readout code will complain that the expected
4551 * IPS_CTL value is not the one we read. */
4552 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4553 DRM_ERROR("Timed out waiting for IPS enable\n");
4554 }
d77e4531
PZ		 4555}
4556
20bc8673 4557void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4558{
4559 struct drm_device *dev = crtc->base.dev;
4560 struct drm_i915_private *dev_priv = dev->dev_private;
4561
6e3c9717 4562 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4563 return;
4564
4565 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4566 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4567 mutex_lock(&dev_priv->rps.hw_lock);
4568 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4569 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4570 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4571 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4572 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4573 } else {
2a114cc1 4574 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4575 POSTING_READ(IPS_CTL);
4576 }
d77e4531
PZ		 4577
4578 /* We need to wait for a vblank before we can disable the plane. */
4579 intel_wait_for_vblank(dev, crtc->pipe);
4580}
4581
4582/** Loads the palette/gamma unit for the CRTC with the prepared values */
4583static void intel_crtc_load_lut(struct drm_crtc *crtc)
4584{
4585 struct drm_device *dev = crtc->dev;
4586 struct drm_i915_private *dev_priv = dev->dev_private;
4587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4588 enum pipe pipe = intel_crtc->pipe;
4589 int palreg = PALETTE(pipe);
4590 int i;
4591 bool reenable_ips = false;
4592
4593 /* The clocks have to be on to load the palette. */
53d9f4e9 4594 if (!crtc->state->active)
d77e4531
PZ		 4595 return;
4596
50360403 4597 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4598 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4599 assert_dsi_pll_enabled(dev_priv);
4600 else
4601 assert_pll_enabled(dev_priv, pipe);
4602 }
4603
4604 /* use legacy palette for Ironlake */
7a1db49a 4605 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4606 palreg = LGC_PALETTE(pipe);
4607
4608 /* Workaround : Do not read or write the pipe palette/gamma data while
4609 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4610 */
6e3c9717 4611 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4612 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4613 GAMMA_MODE_MODE_SPLIT)) {
4614 hsw_disable_ips(intel_crtc);
4615 reenable_ips = true;
4616 }
4617
4618 for (i = 0; i < 256; i++) {
4619 I915_WRITE(palreg + 4 * i,
4620 (intel_crtc->lut_r[i] << 16) |
4621 (intel_crtc->lut_g[i] << 8) |
4622 intel_crtc->lut_b[i]);
4623 }
4624
4625 if (reenable_ips)
4626 hsw_enable_ips(intel_crtc);
4627}
4628
7cac945f 4629static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4630{
7cac945f 4631 if (intel_crtc->overlay) {
d3eedb1a
VS		 4632 struct drm_device *dev = intel_crtc->base.dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634
4635 mutex_lock(&dev->struct_mutex);
4636 dev_priv->mm.interruptible = false;
4637 (void) intel_overlay_switch_off(intel_crtc->overlay);
4638 dev_priv->mm.interruptible = true;
4639 mutex_unlock(&dev->struct_mutex);
4640 }
4641
4642 /* Let userspace switch the overlay on again. In most cases userspace
4643 * has to recompute where to put it anyway.
4644 */
4645}
4646
87d4300a
ML		 4647/**
4648 * intel_post_enable_primary - Perform operations after enabling primary plane
4649 * @crtc: the CRTC whose primary plane was just enabled
4650 *
4651 * Performs potentially sleeping operations that must be done after the primary
4652 * plane is enabled, such as updating FBC and IPS. Note that this may be
4653 * called due to an explicit primary plane update, or due to an implicit
4654 * re-enable that is caused when a sprite plane is updated to no longer
4655 * completely hide the primary plane.
4656 */
4657static void
4658intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4659{
4660 struct drm_device *dev = crtc->dev;
87d4300a 4661 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4663 int pipe = intel_crtc->pipe;
a5c4d7bc 4664
87d4300a
ML		 4665 /*
4666 * BDW signals flip done immediately if the plane
4667 * is disabled, even if the plane enable is already
4668 * armed to occur at the next vblank :(
4669 */
4670 if (IS_BROADWELL(dev))
4671 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4672
87d4300a
ML		 4673 /*
4674 * FIXME IPS should be fine as long as one plane is
4675 * enabled, but in practice it seems to have problems
4676 * when going from primary only to sprite only and vice
4677 * versa.
4678 */
a5c4d7bc
VS		 4679 hsw_enable_ips(intel_crtc);
4680
f99d7069 4681 /*
87d4300a
ML		 4682 * Gen2 reports pipe underruns whenever all planes are disabled.
4683 * So don't enable underrun reporting before at least some planes
4684 * are enabled.
4685 * FIXME: Need to fix the logic to work when we turn off all planes
4686 * but leave the pipe running.
f99d7069 4687 */
87d4300a
ML		 4688 if (IS_GEN2(dev))
4689 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4690
4691 /* Underruns don't raise interrupts, so check manually. */
4692 if (HAS_GMCH_DISPLAY(dev))
4693 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4694}
4695
87d4300a
ML		 4696/**
4697 * intel_pre_disable_primary - Perform operations before disabling primary plane
4698 * @crtc: the CRTC whose primary plane is to be disabled
4699 *
4700 * Performs potentially sleeping operations that must be done before the
4701 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4702 * be called due to an explicit primary plane update, or due to an implicit
4703 * disable that is caused when a sprite plane completely hides the primary
4704 * plane.
4705 */
4706static void
4707intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4708{
4709 struct drm_device *dev = crtc->dev;
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4712 int pipe = intel_crtc->pipe;
a5c4d7bc 4713
87d4300a
ML		 4714 /*
4715 * Gen2 reports pipe underruns whenever all planes are disabled.
4716 * So diasble underrun reporting before all the planes get disabled.
4717 * FIXME: Need to fix the logic to work when we turn off all planes
4718 * but leave the pipe running.
4719 */
4720 if (IS_GEN2(dev))
4721 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4722
87d4300a
ML		 4723 /*
4724 * Vblank time updates from the shadow to live plane control register
4725 * are blocked if the memory self-refresh mode is active at that
4726 * moment. So to make sure the plane gets truly disabled, disable
4727 * first the self-refresh mode. The self-refresh enable bit in turn
4728 * will be checked/applied by the HW only at the next frame start
4729 * event which is after the vblank start event, so we need to have a
4730 * wait-for-vblank between disabling the plane and the pipe.
4731 */
262cd2e1 4732 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4733 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4734 dev_priv->wm.vlv.cxsr = false;
4735 intel_wait_for_vblank(dev, pipe);
4736 }
87d4300a 4737
87d4300a
ML		 4738 /*
4739 * FIXME IPS should be fine as long as one plane is
4740 * enabled, but in practice it seems to have problems
4741 * when going from primary only to sprite only and vice
4742 * versa.
4743 */
a5c4d7bc 4744 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4745}
4746
ac21b225
ML		 4747static void intel_post_plane_update(struct intel_crtc *crtc)
4748{
4749 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4750 struct drm_device *dev = crtc->base.dev;
7733b49b 4751 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4752 struct drm_plane *plane;
4753
4754 if (atomic->wait_vblank)
4755 intel_wait_for_vblank(dev, crtc->pipe);
4756
4757 intel_frontbuffer_flip(dev, atomic->fb_bits);
4758
852eb00d
VS		 4759 if (atomic->disable_cxsr)
4760 crtc->wm.cxsr_allowed = true;
4761
f015c551
VS		 4762 if (crtc->atomic.update_wm_post)
4763 intel_update_watermarks(&crtc->base);
4764
c80ac854 4765 if (atomic->update_fbc)
7733b49b 4766 intel_fbc_update(dev_priv);
ac21b225
ML		 4767
4768 if (atomic->post_enable_primary)
4769 intel_post_enable_primary(&crtc->base);
4770
4771 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4772 intel_update_sprite_watermarks(plane, &crtc->base,
4773 0, 0, 0, false, false);
4774
4775 memset(atomic, 0, sizeof(*atomic));
4776}
4777
4778static void intel_pre_plane_update(struct intel_crtc *crtc)
4779{
4780 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4781 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4782 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4783 struct drm_plane *p;
4784
4785 /* Track fb's for any planes being disabled */
ac21b225
ML		 4786 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4787 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4788
4789 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4790 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4791 plane->frontbuffer_bit);
ac21b225
ML		 4792 mutex_unlock(&dev->struct_mutex);
4793 }
4794
4795 if (atomic->wait_for_flips)
4796 intel_crtc_wait_for_pending_flips(&crtc->base);
4797
c80ac854 4798 if (atomic->disable_fbc)
25ad93fd 4799 intel_fbc_disable_crtc(crtc);
ac21b225 4800
066cf55b
RV		 4801 if (crtc->atomic.disable_ips)
4802 hsw_disable_ips(crtc);
4803
ac21b225
ML		 4804 if (atomic->pre_disable_primary)
4805 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4806
4807 if (atomic->disable_cxsr) {
4808 crtc->wm.cxsr_allowed = false;
4809 intel_set_memory_cxsr(dev_priv, false);
4810 }
ac21b225
ML		 4811}
4812
d032ffa0 4813static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4814{
4815 struct drm_device *dev = crtc->dev;
4816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4817 struct drm_plane *p;
87d4300a
ML		 4818 int pipe = intel_crtc->pipe;
4819
7cac945f 4820 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4821
d032ffa0
ML		 4822 drm_for_each_plane_mask(p, dev, plane_mask)
4823 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4824
f99d7069
DV		 4825 /*
4826 * FIXME: Once we grow proper nuclear flip support out of this we need
4827 * to compute the mask of flip planes precisely. For the time being
4828 * consider this a flip to a NULL plane.
4829 */
4830 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4831}
4832
f67a559d
JB		 4833static void ironlake_crtc_enable(struct drm_crtc *crtc)
4834{
4835 struct drm_device *dev = crtc->dev;
4836 struct drm_i915_private *dev_priv = dev->dev_private;
4837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4838 struct intel_encoder *encoder;
f67a559d 4839 int pipe = intel_crtc->pipe;
f67a559d 4840
53d9f4e9 4841 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4842 return;
4843
6e3c9717 4844 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4845 intel_prepare_shared_dpll(intel_crtc);
4846
6e3c9717 4847 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4848 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4849
4850 intel_set_pipe_timings(intel_crtc);
4851
6e3c9717 4852 if (intel_crtc->config->has_pch_encoder) {
29407aab 4853 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4854 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4855 }
4856
4857 ironlake_set_pipeconf(crtc);
4858
f67a559d 4859 intel_crtc->active = true;
8664281b 4860
a72e4c9f
DV		 4861 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4862 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4863
f6736a1a 4864 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4865 if (encoder->pre_enable)
4866 encoder->pre_enable(encoder);
f67a559d 4867
6e3c9717 4868 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4869 /* Note: FDI PLL enabling _must_ be done before we enable the
4870 * cpu pipes, hence this is separate from all the other fdi/pch
4871 * enabling. */
88cefb6c 4872 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4873 } else {
4874 assert_fdi_tx_disabled(dev_priv, pipe);
4875 assert_fdi_rx_disabled(dev_priv, pipe);
4876 }
f67a559d 4877
b074cec8 4878 ironlake_pfit_enable(intel_crtc);
f67a559d 4879
9c54c0dd
JB		 4880 /*
4881 * On ILK+ LUT must be loaded before the pipe is running but with
4882 * clocks enabled
4883 */
4884 intel_crtc_load_lut(crtc);
4885
f37fcc2a 4886 intel_update_watermarks(crtc);
e1fdc473 4887 intel_enable_pipe(intel_crtc);
f67a559d 4888
6e3c9717 4889 if (intel_crtc->config->has_pch_encoder)
f67a559d 4890 ironlake_pch_enable(crtc);
c98e9dcf 4891
f9b61ff6
DV		 4892 assert_vblank_disabled(crtc);
4893 drm_crtc_vblank_on(crtc);
4894
fa5c73b1
DV		 4895 for_each_encoder_on_crtc(dev, crtc, encoder)
4896 encoder->enable(encoder);
61b77ddd
DV		 4897
4898 if (HAS_PCH_CPT(dev))
a1520318 4899 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4900}
4901
42db64ef
PZ		 4902/* IPS only exists on ULT machines and is tied to pipe A. */
4903static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4904{
f5adf94e 4905 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4906}
4907
4f771f10
PZ		 4908static void haswell_crtc_enable(struct drm_crtc *crtc)
4909{
4910 struct drm_device *dev = crtc->dev;
4911 struct drm_i915_private *dev_priv = dev->dev_private;
4912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4913 struct intel_encoder *encoder;
99d736a2
ML		 4914 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4915 struct intel_crtc_state *pipe_config =
4916 to_intel_crtc_state(crtc->state);
4f771f10 4917
53d9f4e9 4918 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4919 return;
4920
df8ad70c
DV		 4921 if (intel_crtc_to_shared_dpll(intel_crtc))
4922 intel_enable_shared_dpll(intel_crtc);
4923
6e3c9717 4924 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4925 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4926
4927 intel_set_pipe_timings(intel_crtc);
4928
6e3c9717
ACO		 4929 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4930 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4931 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4932 }
4933
6e3c9717 4934 if (intel_crtc->config->has_pch_encoder) {
229fca97 4935 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4936 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4937 }
4938
4939 haswell_set_pipeconf(crtc);
4940
4941 intel_set_pipe_csc(crtc);
4942
4f771f10 4943 intel_crtc->active = true;
8664281b 4944
a72e4c9f 4945 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4946 for_each_encoder_on_crtc(dev, crtc, encoder)
4947 if (encoder->pre_enable)
4948 encoder->pre_enable(encoder);
4949
6e3c9717 4950 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4951 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4952 true);
4fe9467d
ID		 4953 dev_priv->display.fdi_link_train(crtc);
4954 }
4955
1f544388 4956 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4957
ff6d9f55 4958 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 4959 skylake_pfit_enable(intel_crtc);
ff6d9f55 4960 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4961 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4962 else
4963 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4964
4965 /*
4966 * On ILK+ LUT must be loaded before the pipe is running but with
4967 * clocks enabled
4968 */
4969 intel_crtc_load_lut(crtc);
4970
1f544388 4971 intel_ddi_set_pipe_settings(crtc);
8228c251 4972 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4973
f37fcc2a 4974 intel_update_watermarks(crtc);
e1fdc473 4975 intel_enable_pipe(intel_crtc);
42db64ef 4976
6e3c9717 4977 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4978 lpt_pch_enable(crtc);
4f771f10 4979
6e3c9717 4980 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4981 intel_ddi_set_vc_payload_alloc(crtc, true);
4982
f9b61ff6
DV		 4983 assert_vblank_disabled(crtc);
4984 drm_crtc_vblank_on(crtc);
4985
8807e55b 4986 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4987 encoder->enable(encoder);
8807e55b
JN		 4988 intel_opregion_notify_encoder(encoder, true);
4989 }
4f771f10 4990
e4916946
PZ		 4991 /* If we change the relative order between pipe/planes enabling, we need
4992 * to change the workaround. */
99d736a2
ML		 4993 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4994 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4995 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4996 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4997 }
4f771f10
PZ		 4998}
4999
3f8dce3a
DV		 5000static void ironlake_pfit_disable(struct intel_crtc *crtc)
5001{
5002 struct drm_device *dev = crtc->base.dev;
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004 int pipe = crtc->pipe;
5005
5006 /* To avoid upsetting the power well on haswell only disable the pfit if
5007 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5008 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5009 I915_WRITE(PF_CTL(pipe), 0);
5010 I915_WRITE(PF_WIN_POS(pipe), 0);
5011 I915_WRITE(PF_WIN_SZ(pipe), 0);
5012 }
5013}
5014
6be4a607
JB		 5015static void ironlake_crtc_disable(struct drm_crtc *crtc)
5016{
5017 struct drm_device *dev = crtc->dev;
5018 struct drm_i915_private *dev_priv = dev->dev_private;
5019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5020 struct intel_encoder *encoder;
6be4a607 5021 int pipe = intel_crtc->pipe;
5eddb70b 5022 u32 reg, temp;
b52eb4dc 5023
ea9d758d
DV		 5024 for_each_encoder_on_crtc(dev, crtc, encoder)
5025 encoder->disable(encoder);
5026
f9b61ff6
DV		 5027 drm_crtc_vblank_off(crtc);
5028 assert_vblank_disabled(crtc);
5029
6e3c9717 5030 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5031 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5032
575f7ab7 5033 intel_disable_pipe(intel_crtc);
32f9d658 5034
3f8dce3a 5035 ironlake_pfit_disable(intel_crtc);
2c07245f 5036
5a74f70a
VS		 5037 if (intel_crtc->config->has_pch_encoder)
5038 ironlake_fdi_disable(crtc);
5039
bf49ec8c
DV		 5040 for_each_encoder_on_crtc(dev, crtc, encoder)
5041 if (encoder->post_disable)
5042 encoder->post_disable(encoder);
2c07245f 5043
6e3c9717 5044 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5045 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5046
d925c59a
DV		 5047 if (HAS_PCH_CPT(dev)) {
5048 /* disable TRANS_DP_CTL */
5049 reg = TRANS_DP_CTL(pipe);
5050 temp = I915_READ(reg);
5051 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5052 TRANS_DP_PORT_SEL_MASK);
5053 temp |= TRANS_DP_PORT_SEL_NONE;
5054 I915_WRITE(reg, temp);
5055
5056 /* disable DPLL_SEL */
5057 temp = I915_READ(PCH_DPLL_SEL);
11887397 5058 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5059 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5060 }
e3421a18 5061
d925c59a
DV		 5062 ironlake_fdi_pll_disable(intel_crtc);
5063 }
e4ca0612
PJ		 5064
5065 intel_crtc->active = false;
5066 intel_update_watermarks(crtc);
6be4a607 5067}
1b3c7a47 5068
4f771f10 5069static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5070{
4f771f10
PZ		 5071 struct drm_device *dev = crtc->dev;
5072 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5074 struct intel_encoder *encoder;
6e3c9717 5075 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5076
8807e55b
JN		 5077 for_each_encoder_on_crtc(dev, crtc, encoder) {
5078 intel_opregion_notify_encoder(encoder, false);
4f771f10 5079 encoder->disable(encoder);
8807e55b 5080 }
4f771f10 5081
f9b61ff6
DV		 5082 drm_crtc_vblank_off(crtc);
5083 assert_vblank_disabled(crtc);
5084
6e3c9717 5085 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5086 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5087 false);
575f7ab7 5088 intel_disable_pipe(intel_crtc);
4f771f10 5089
6e3c9717 5090 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5091 intel_ddi_set_vc_payload_alloc(crtc, false);
5092
ad80a810 5093 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5094
ff6d9f55 5095 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 5096 skylake_scaler_disable(intel_crtc);
ff6d9f55 5097 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5098 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5099 else
5100 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5101
1f544388 5102 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5103
6e3c9717 5104 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5105 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5106 intel_ddi_fdi_disable(crtc);
83616634 5107 }
4f771f10 5108
97b040aa
ID		 5109 for_each_encoder_on_crtc(dev, crtc, encoder)
5110 if (encoder->post_disable)
5111 encoder->post_disable(encoder);
e4ca0612
PJ		 5112
5113 intel_crtc->active = false;
5114 intel_update_watermarks(crtc);
4f771f10
PZ		 5115}
5116
2dd24552
JB		 5117static void i9xx_pfit_enable(struct intel_crtc *crtc)
5118{
5119 struct drm_device *dev = crtc->base.dev;
5120 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5121 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5122
681a8504 5123 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5124 return;
5125
2dd24552 5126 /*
c0b03411
DV		 5127 * The panel fitter should only be adjusted whilst the pipe is disabled,
5128 * according to register description and PRM.
2dd24552 5129 */
c0b03411
DV		 5130 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5131 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5132
b074cec8
JB		 5133 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5134 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5135
5136 /* Border color in case we don't scale up to the full screen. Black by
5137 * default, change to something else for debugging. */
5138 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5139}
5140
d05410f9
DA		 5141static enum intel_display_power_domain port_to_power_domain(enum port port)
5142{
5143 switch (port) {
5144 case PORT_A:
5145 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5146 case PORT_B:
5147 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5148 case PORT_C:
5149 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5150 case PORT_D:
5151 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5152 default:
5153 WARN_ON_ONCE(1);
5154 return POWER_DOMAIN_PORT_OTHER;
5155 }
5156}
5157
77d22dca
ID		 5158#define for_each_power_domain(domain, mask) \
5159 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5160 if ((1 << (domain)) & (mask))
5161
319be8ae
ID		 5162enum intel_display_power_domain
5163intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5164{
5165 struct drm_device *dev = intel_encoder->base.dev;
5166 struct intel_digital_port *intel_dig_port;
5167
5168 switch (intel_encoder->type) {
5169 case INTEL_OUTPUT_UNKNOWN:
5170 /* Only DDI platforms should ever use this output type */
5171 WARN_ON_ONCE(!HAS_DDI(dev));
5172 case INTEL_OUTPUT_DISPLAYPORT:
5173 case INTEL_OUTPUT_HDMI:
5174 case INTEL_OUTPUT_EDP:
5175 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5176 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5177 case INTEL_OUTPUT_DP_MST:
5178 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5179 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5180 case INTEL_OUTPUT_ANALOG:
5181 return POWER_DOMAIN_PORT_CRT;
5182 case INTEL_OUTPUT_DSI:
5183 return POWER_DOMAIN_PORT_DSI;
5184 default:
5185 return POWER_DOMAIN_PORT_OTHER;
5186 }
5187}
5188
5189static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5190{
319be8ae
ID		 5191 struct drm_device *dev = crtc->dev;
5192 struct intel_encoder *intel_encoder;
5193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5194 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5195 unsigned long mask;
5196 enum transcoder transcoder;
5197
5198 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5199
5200 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5201 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5202 if (intel_crtc->config->pch_pfit.enabled ||
5203 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5204 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5205
319be8ae
ID		 5206 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5207 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5208
77d22dca
ID		 5209 return mask;
5210}
5211
679dacd4 5212static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5213{
679dacd4 5214 struct drm_device *dev = state->dev;
77d22dca
ID		 5215 struct drm_i915_private *dev_priv = dev->dev_private;
5216 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5217 struct intel_crtc *crtc;
5218
5219 /*
5220 * First get all needed power domains, then put all unneeded, to avoid
5221 * any unnecessary toggling of the power wells.
5222 */
d3fcc808 5223 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5224 enum intel_display_power_domain domain;
5225
83d65738 5226 if (!crtc->base.state->enable)
77d22dca
ID		 5227 continue;
5228
319be8ae 5229 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5230
5231 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5232 intel_display_power_get(dev_priv, domain);
5233 }
5234
27c329ed
ML		 5235 if (dev_priv->display.modeset_commit_cdclk) {
5236 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5237
5238 if (cdclk != dev_priv->cdclk_freq &&
5239 !WARN_ON(!state->allow_modeset))
5240 dev_priv->display.modeset_commit_cdclk(state);
5241 }
50f6e502 5242
d3fcc808 5243 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5244 enum intel_display_power_domain domain;
5245
5246 for_each_power_domain(domain, crtc->enabled_power_domains)
5247 intel_display_power_put(dev_priv, domain);
5248
5249 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5250 }
5251
5252 intel_display_set_init_power(dev_priv, false);
5253}
5254
560a7ae4
DL		 5255static void intel_update_max_cdclk(struct drm_device *dev)
5256{
5257 struct drm_i915_private *dev_priv = dev->dev_private;
5258
5259 if (IS_SKYLAKE(dev)) {
5260 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5261
5262 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5263 dev_priv->max_cdclk_freq = 675000;
5264 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5265 dev_priv->max_cdclk_freq = 540000;
5266 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5267 dev_priv->max_cdclk_freq = 450000;
5268 else
5269 dev_priv->max_cdclk_freq = 337500;
5270 } else if (IS_BROADWELL(dev)) {
5271 /*
5272 * FIXME with extra cooling we can allow
5273 * 540 MHz for ULX and 675 Mhz for ULT.
5274 * How can we know if extra cooling is
5275 * available? PCI ID, VTB, something else?
5276 */
5277 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5278 dev_priv->max_cdclk_freq = 450000;
5279 else if (IS_BDW_ULX(dev))
5280 dev_priv->max_cdclk_freq = 450000;
5281 else if (IS_BDW_ULT(dev))
5282 dev_priv->max_cdclk_freq = 540000;
5283 else
5284 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5285 } else if (IS_CHERRYVIEW(dev)) {
5286 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5287 } else if (IS_VALLEYVIEW(dev)) {
5288 dev_priv->max_cdclk_freq = 400000;
5289 } else {
5290 /* otherwise assume cdclk is fixed */
5291 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5292 }
5293
5294 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5295 dev_priv->max_cdclk_freq);
5296}
5297
5298static void intel_update_cdclk(struct drm_device *dev)
5299{
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301
5302 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5303 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5304 dev_priv->cdclk_freq);
5305
5306 /*
5307 * Program the gmbus_freq based on the cdclk frequency.
5308 * BSpec erroneously claims we should aim for 4MHz, but
5309 * in fact 1MHz is the correct frequency.
5310 */
5311 if (IS_VALLEYVIEW(dev)) {
5312 /*
5313 * Program the gmbus_freq based on the cdclk frequency.
5314 * BSpec erroneously claims we should aim for 4MHz, but
5315 * in fact 1MHz is the correct frequency.
5316 */
5317 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5318 }
5319
5320 if (dev_priv->max_cdclk_freq == 0)
5321 intel_update_max_cdclk(dev);
5322}
5323
70d0c574 5324static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5325{
5326 struct drm_i915_private *dev_priv = dev->dev_private;
5327 uint32_t divider;
5328 uint32_t ratio;
5329 uint32_t current_freq;
5330 int ret;
5331
5332 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5333 switch (frequency) {
5334 case 144000:
5335 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5336 ratio = BXT_DE_PLL_RATIO(60);
5337 break;
5338 case 288000:
5339 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5340 ratio = BXT_DE_PLL_RATIO(60);
5341 break;
5342 case 384000:
5343 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5344 ratio = BXT_DE_PLL_RATIO(60);
5345 break;
5346 case 576000:
5347 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5348 ratio = BXT_DE_PLL_RATIO(60);
5349 break;
5350 case 624000:
5351 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5352 ratio = BXT_DE_PLL_RATIO(65);
5353 break;
5354 case 19200:
5355 /*
5356 * Bypass frequency with DE PLL disabled. Init ratio, divider
5357 * to suppress GCC warning.
5358 */
5359 ratio = 0;
5360 divider = 0;
5361 break;
5362 default:
5363 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5364
5365 return;
5366 }
5367
5368 mutex_lock(&dev_priv->rps.hw_lock);
5369 /* Inform power controller of upcoming frequency change */
5370 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5371 0x80000000);
5372 mutex_unlock(&dev_priv->rps.hw_lock);
5373
5374 if (ret) {
5375 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5376 ret, frequency);
5377 return;
5378 }
5379
5380 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5381 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5382 current_freq = current_freq * 500 + 1000;
5383
5384 /*
5385 * DE PLL has to be disabled when
5386 * - setting to 19.2MHz (bypass, PLL isn't used)
5387 * - before setting to 624MHz (PLL needs toggling)
5388 * - before setting to any frequency from 624MHz (PLL needs toggling)
5389 */
5390 if (frequency == 19200 || frequency == 624000 ||
5391 current_freq == 624000) {
5392 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5393 /* Timeout 200us */
5394 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5395 1))
5396 DRM_ERROR("timout waiting for DE PLL unlock\n");
5397 }
5398
5399 if (frequency != 19200) {
5400 uint32_t val;
5401
5402 val = I915_READ(BXT_DE_PLL_CTL);
5403 val &= ~BXT_DE_PLL_RATIO_MASK;
5404 val |= ratio;
5405 I915_WRITE(BXT_DE_PLL_CTL, val);
5406
5407 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5408 /* Timeout 200us */
5409 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5410 DRM_ERROR("timeout waiting for DE PLL lock\n");
5411
5412 val = I915_READ(CDCLK_CTL);
5413 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5414 val |= divider;
5415 /*
5416 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5417 * enable otherwise.
5418 */
5419 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5420 if (frequency >= 500000)
5421 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5422
5423 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5424 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5425 val |= (frequency - 1000) / 500;
5426 I915_WRITE(CDCLK_CTL, val);
5427 }
5428
5429 mutex_lock(&dev_priv->rps.hw_lock);
5430 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5431 DIV_ROUND_UP(frequency, 25000));
5432 mutex_unlock(&dev_priv->rps.hw_lock);
5433
5434 if (ret) {
5435 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5436 ret, frequency);
5437 return;
5438 }
5439
a47871bd 5440 intel_update_cdclk(dev);
f8437dd1
VK		 5441}
5442
5443void broxton_init_cdclk(struct drm_device *dev)
5444{
5445 struct drm_i915_private *dev_priv = dev->dev_private;
5446 uint32_t val;
5447
5448 /*
5449 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5450 * or else the reset will hang because there is no PCH to respond.
5451 * Move the handshake programming to initialization sequence.
5452 * Previously was left up to BIOS.
5453 */
5454 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5455 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5456 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5457
5458 /* Enable PG1 for cdclk */
5459 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5460
5461 /* check if cd clock is enabled */
5462 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5463 DRM_DEBUG_KMS("Display already initialized\n");
5464 return;
5465 }
5466
5467 /*
5468 * FIXME:
5469 * - The initial CDCLK needs to be read from VBT.
5470 * Need to make this change after VBT has changes for BXT.
5471 * - check if setting the max (or any) cdclk freq is really necessary
5472 * here, it belongs to modeset time
5473 */
5474 broxton_set_cdclk(dev, 624000);
5475
5476 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5477 POSTING_READ(DBUF_CTL);
5478
f8437dd1
VK		 5479 udelay(10);
5480
5481 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5482 DRM_ERROR("DBuf power enable timeout!\n");
5483}
5484
5485void broxton_uninit_cdclk(struct drm_device *dev)
5486{
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5488
5489 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5490 POSTING_READ(DBUF_CTL);
5491
f8437dd1
VK		 5492 udelay(10);
5493
5494 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5495 DRM_ERROR("DBuf power disable timeout!\n");
5496
5497 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5498 broxton_set_cdclk(dev, 19200);
5499
5500 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5501}
5502
5d96d8af
DL		 5503static const struct skl_cdclk_entry {
5504 unsigned int freq;
5505 unsigned int vco;
5506} skl_cdclk_frequencies[] = {
5507 { .freq = 308570, .vco = 8640 },
5508 { .freq = 337500, .vco = 8100 },
5509 { .freq = 432000, .vco = 8640 },
5510 { .freq = 450000, .vco = 8100 },
5511 { .freq = 540000, .vco = 8100 },
5512 { .freq = 617140, .vco = 8640 },
5513 { .freq = 675000, .vco = 8100 },
5514};
5515
5516static unsigned int skl_cdclk_decimal(unsigned int freq)
5517{
5518 return (freq - 1000) / 500;
5519}
5520
5521static unsigned int skl_cdclk_get_vco(unsigned int freq)
5522{
5523 unsigned int i;
5524
5525 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5526 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5527
5528 if (e->freq == freq)
5529 return e->vco;
5530 }
5531
5532 return 8100;
5533}
5534
5535static void
5536skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5537{
5538 unsigned int min_freq;
5539 u32 val;
5540
5541 /* select the minimum CDCLK before enabling DPLL 0 */
5542 val = I915_READ(CDCLK_CTL);
5543 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5544 val |= CDCLK_FREQ_337_308;
5545
5546 if (required_vco == 8640)
5547 min_freq = 308570;
5548 else
5549 min_freq = 337500;
5550
5551 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5552
5553 I915_WRITE(CDCLK_CTL, val);
5554 POSTING_READ(CDCLK_CTL);
5555
5556 /*
5557 * We always enable DPLL0 with the lowest link rate possible, but still
5558 * taking into account the VCO required to operate the eDP panel at the
5559 * desired frequency. The usual DP link rates operate with a VCO of
5560 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5561 * The modeset code is responsible for the selection of the exact link
5562 * rate later on, with the constraint of choosing a frequency that
5563 * works with required_vco.
5564 */
5565 val = I915_READ(DPLL_CTRL1);
5566
5567 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5568 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5569 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5570 if (required_vco == 8640)
5571 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5572 SKL_DPLL0);
5573 else
5574 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5575 SKL_DPLL0);
5576
5577 I915_WRITE(DPLL_CTRL1, val);
5578 POSTING_READ(DPLL_CTRL1);
5579
5580 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5581
5582 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5583 DRM_ERROR("DPLL0 not locked\n");
5584}
5585
5586static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5587{
5588 int ret;
5589 u32 val;
5590
5591 /* inform PCU we want to change CDCLK */
5592 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5593 mutex_lock(&dev_priv->rps.hw_lock);
5594 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5595 mutex_unlock(&dev_priv->rps.hw_lock);
5596
5597 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5598}
5599
5600static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5601{
5602 unsigned int i;
5603
5604 for (i = 0; i < 15; i++) {
5605 if (skl_cdclk_pcu_ready(dev_priv))
5606 return true;
5607 udelay(10);
5608 }
5609
5610 return false;
5611}
5612
5613static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5614{
560a7ae4 5615 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5616 u32 freq_select, pcu_ack;
5617
5618 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5619
5620 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5621 DRM_ERROR("failed to inform PCU about cdclk change\n");
5622 return;
5623 }
5624
5625 /* set CDCLK_CTL */
5626 switch(freq) {
5627 case 450000:
5628 case 432000:
5629 freq_select = CDCLK_FREQ_450_432;
5630 pcu_ack = 1;
5631 break;
5632 case 540000:
5633 freq_select = CDCLK_FREQ_540;
5634 pcu_ack = 2;
5635 break;
5636 case 308570:
5637 case 337500:
5638 default:
5639 freq_select = CDCLK_FREQ_337_308;
5640 pcu_ack = 0;
5641 break;
5642 case 617140:
5643 case 675000:
5644 freq_select = CDCLK_FREQ_675_617;
5645 pcu_ack = 3;
5646 break;
5647 }
5648
5649 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5650 POSTING_READ(CDCLK_CTL);
5651
5652 /* inform PCU of the change */
5653 mutex_lock(&dev_priv->rps.hw_lock);
5654 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5655 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5656
5657 intel_update_cdclk(dev);
5d96d8af
DL		 5658}
5659
5660void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5661{
5662 /* disable DBUF power */
5663 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5664 POSTING_READ(DBUF_CTL);
5665
5666 udelay(10);
5667
5668 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5669 DRM_ERROR("DBuf power disable timeout\n");
5670
5671 /* disable DPLL0 */
5672 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5673 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5674 DRM_ERROR("Couldn't disable DPLL0\n");
5675
5676 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5677}
5678
5679void skl_init_cdclk(struct drm_i915_private *dev_priv)
5680{
5681 u32 val;
5682 unsigned int required_vco;
5683
5684 /* enable PCH reset handshake */
5685 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5686 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5687
5688 /* enable PG1 and Misc I/O */
5689 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5690
5691 /* DPLL0 already enabed !? */
5692 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5693 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5694 return;
5695 }
5696
5697 /* enable DPLL0 */
5698 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5699 skl_dpll0_enable(dev_priv, required_vco);
5700
5701 /* set CDCLK to the frequency the BIOS chose */
5702 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5703
5704 /* enable DBUF power */
5705 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5706 POSTING_READ(DBUF_CTL);
5707
5708 udelay(10);
5709
5710 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5711 DRM_ERROR("DBuf power enable timeout\n");
5712}
5713
dfcab17e 5714/* returns HPLL frequency in kHz */
f8bf63fd 5715static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5716{
586f49dc 5717 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5718
586f49dc 5719 /* Obtain SKU information */
a580516d 5720 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5721 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5722 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5723 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5724
dfcab17e 5725 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5726}
5727
5728/* Adjust CDclk dividers to allow high res or save power if possible */
5729static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5730{
5731 struct drm_i915_private *dev_priv = dev->dev_private;
5732 u32 val, cmd;
5733
164dfd28
VK		 5734 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5735 != dev_priv->cdclk_freq);
d60c4473 5736
dfcab17e 5737 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5738 cmd = 2;
dfcab17e 5739 else if (cdclk == 266667)
30a970c6
JB		 5740 cmd = 1;
5741 else
5742 cmd = 0;
5743
5744 mutex_lock(&dev_priv->rps.hw_lock);
5745 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5746 val &= ~DSPFREQGUAR_MASK;
5747 val |= (cmd << DSPFREQGUAR_SHIFT);
5748 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5749 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5750 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5751 50)) {
5752 DRM_ERROR("timed out waiting for CDclk change\n");
5753 }
5754 mutex_unlock(&dev_priv->rps.hw_lock);
5755
54433e91
VS		 5756 mutex_lock(&dev_priv->sb_lock);
5757
dfcab17e 5758 if (cdclk == 400000) {
6bcda4f0 5759 u32 divider;
30a970c6 5760
6bcda4f0 5761 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5762
30a970c6
JB		 5763 /* adjust cdclk divider */
5764 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5765 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5766 val |= divider;
5767 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5768
5769 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5770 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5771 50))
5772 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5773 }
5774
30a970c6
JB		 5775 /* adjust self-refresh exit latency value */
5776 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5777 val &= ~0x7f;
5778
5779 /*
5780 * For high bandwidth configs, we set a higher latency in the bunit
5781 * so that the core display fetch happens in time to avoid underruns.
5782 */
dfcab17e 5783 if (cdclk == 400000)
30a970c6
JB		 5784 val |= 4500 / 250; /* 4.5 usec */
5785 else
5786 val |= 3000 / 250; /* 3.0 usec */
5787 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5788
a580516d 5789 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5790
b6283055 5791 intel_update_cdclk(dev);
30a970c6
JB		 5792}
5793
383c5a6a
VS		 5794static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5795{
5796 struct drm_i915_private *dev_priv = dev->dev_private;
5797 u32 val, cmd;
5798
164dfd28
VK		 5799 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5800 != dev_priv->cdclk_freq);
383c5a6a
VS		 5801
5802 switch (cdclk) {
383c5a6a
VS		 5803 case 333333:
5804 case 320000:
383c5a6a 5805 case 266667:
383c5a6a 5806 case 200000:
383c5a6a
VS		 5807 break;
5808 default:
5f77eeb0 5809 MISSING_CASE(cdclk);
383c5a6a
VS		 5810 return;
5811 }
5812
9d0d3fda
VS		 5813 /*
5814 * Specs are full of misinformation, but testing on actual
5815 * hardware has shown that we just need to write the desired
5816 * CCK divider into the Punit register.
5817 */
5818 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5819
383c5a6a
VS		 5820 mutex_lock(&dev_priv->rps.hw_lock);
5821 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5822 val &= ~DSPFREQGUAR_MASK_CHV;
5823 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5824 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5825 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5826 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5827 50)) {
5828 DRM_ERROR("timed out waiting for CDclk change\n");
5829 }
5830 mutex_unlock(&dev_priv->rps.hw_lock);
5831
b6283055 5832 intel_update_cdclk(dev);
383c5a6a
VS		 5833}
5834
30a970c6
JB		 5835static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5836 int max_pixclk)
5837{
6bcda4f0 5838 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5839 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5840
30a970c6
JB		 5841 /*
5842 * Really only a few cases to deal with, as only 4 CDclks are supported:
5843 * 200MHz
5844 * 267MHz
29dc7ef3 5845 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5846 * 400MHz (VLV only)
5847 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5848 * of the lower bin and adjust if needed.
e37c67a1
VS		 5849 *
5850 * We seem to get an unstable or solid color picture at 200MHz.
5851 * Not sure what's wrong. For now use 200MHz only when all pipes
5852 * are off.
30a970c6 5853 */
6cca3195
VS		 5854 if (!IS_CHERRYVIEW(dev_priv) &&
5855 max_pixclk > freq_320*limit/100)
dfcab17e 5856 return 400000;
6cca3195 5857 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5858 return freq_320;
e37c67a1 5859 else if (max_pixclk > 0)
dfcab17e 5860 return 266667;
e37c67a1
VS		 5861 else
5862 return 200000;
30a970c6
JB		 5863}
5864
f8437dd1
VK		 5865static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5866 int max_pixclk)
5867{
5868 /*
5869 * FIXME:
5870 * - remove the guardband, it's not needed on BXT
5871 * - set 19.2MHz bypass frequency if there are no active pipes
5872 */
5873 if (max_pixclk > 576000*9/10)
5874 return 624000;
5875 else if (max_pixclk > 384000*9/10)
5876 return 576000;
5877 else if (max_pixclk > 288000*9/10)
5878 return 384000;
5879 else if (max_pixclk > 144000*9/10)
5880 return 288000;
5881 else
5882 return 144000;
5883}
5884
a821fc46
ACO		 5885/* Compute the max pixel clock for new configuration. Uses atomic state if
5886 * that's non-NULL, look at current state otherwise. */
5887static int intel_mode_max_pixclk(struct drm_device *dev,
5888 struct drm_atomic_state *state)
30a970c6 5889{
30a970c6 5890 struct intel_crtc *intel_crtc;
304603f4 5891 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5892 int max_pixclk = 0;
5893
d3fcc808 5894 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5895 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5896 if (IS_ERR(crtc_state))
5897 return PTR_ERR(crtc_state);
5898
5899 if (!crtc_state->base.enable)
5900 continue;
5901
5902 max_pixclk = max(max_pixclk,
5903 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5904 }
5905
5906 return max_pixclk;
5907}
5908
27c329ed 5909static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5910{
27c329ed
ML		 5911 struct drm_device *dev = state->dev;
5912 struct drm_i915_private *dev_priv = dev->dev_private;
5913 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5914
304603f4
ACO		 5915 if (max_pixclk < 0)
5916 return max_pixclk;
30a970c6 5917
27c329ed
ML		 5918 to_intel_atomic_state(state)->cdclk =
5919 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5920
27c329ed
ML		 5921 return 0;
5922}
304603f4 5923
27c329ed
ML		 5924static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5925{
5926 struct drm_device *dev = state->dev;
5927 struct drm_i915_private *dev_priv = dev->dev_private;
5928 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5929
27c329ed
ML		 5930 if (max_pixclk < 0)
5931 return max_pixclk;
85a96e7a 5932
27c329ed
ML		 5933 to_intel_atomic_state(state)->cdclk =
5934 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5935
27c329ed 5936 return 0;
30a970c6
JB		 5937}
5938
1e69cd74
VS		 5939static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5940{
5941 unsigned int credits, default_credits;
5942
5943 if (IS_CHERRYVIEW(dev_priv))
5944 default_credits = PFI_CREDIT(12);
5945 else
5946 default_credits = PFI_CREDIT(8);
5947
164dfd28 5948 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5949 /* CHV suggested value is 31 or 63 */
5950 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5951 credits = PFI_CREDIT_63;
1e69cd74
VS		 5952 else
5953 credits = PFI_CREDIT(15);
5954 } else {
5955 credits = default_credits;
5956 }
5957
5958 /*
5959 * WA - write default credits before re-programming
5960 * FIXME: should we also set the resend bit here?
5961 */
5962 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5963 default_credits);
5964
5965 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5966 credits | PFI_CREDIT_RESEND);
5967
5968 /*
5969 * FIXME is this guaranteed to clear
5970 * immediately or should we poll for it?
5971 */
5972 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5973}
5974
27c329ed 5975static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5976{
a821fc46 5977 struct drm_device *dev = old_state->dev;
27c329ed 5978 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5979 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5980
27c329ed
ML		 5981 /*
5982 * FIXME: We can end up here with all power domains off, yet
5983 * with a CDCLK frequency other than the minimum. To account
5984 * for this take the PIPE-A power domain, which covers the HW
5985 * blocks needed for the following programming. This can be
5986 * removed once it's guaranteed that we get here either with
5987 * the minimum CDCLK set, or the required power domains
5988 * enabled.
5989 */
5990 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5991
27c329ed
ML		 5992 if (IS_CHERRYVIEW(dev))
5993 cherryview_set_cdclk(dev, req_cdclk);
5994 else
5995 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5996
27c329ed 5997 vlv_program_pfi_credits(dev_priv);
1e69cd74 5998
27c329ed 5999 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6000}
6001
89b667f8
JB		 6002static void valleyview_crtc_enable(struct drm_crtc *crtc)
6003{
6004 struct drm_device *dev = crtc->dev;
a72e4c9f 6005 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6007 struct intel_encoder *encoder;
6008 int pipe = intel_crtc->pipe;
23538ef1 6009 bool is_dsi;
89b667f8 6010
53d9f4e9 6011 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6012 return;
6013
409ee761 6014 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6015
1ae0d137
VS		 6016 if (!is_dsi) {
6017 if (IS_CHERRYVIEW(dev))
6e3c9717 6018 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6019 else
6e3c9717 6020 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6021 }
5b18e57c 6022
6e3c9717 6023 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6024 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6025
6026 intel_set_pipe_timings(intel_crtc);
6027
c14b0485
VS		 6028 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6029 struct drm_i915_private *dev_priv = dev->dev_private;
6030
6031 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6032 I915_WRITE(CHV_CANVAS(pipe), 0);
6033 }
6034
5b18e57c
DV		 6035 i9xx_set_pipeconf(intel_crtc);
6036
89b667f8 6037 intel_crtc->active = true;
89b667f8 6038
a72e4c9f 6039 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6040
89b667f8
JB		 6041 for_each_encoder_on_crtc(dev, crtc, encoder)
6042 if (encoder->pre_pll_enable)
6043 encoder->pre_pll_enable(encoder);
6044
9d556c99
CML		 6045 if (!is_dsi) {
6046 if (IS_CHERRYVIEW(dev))
6e3c9717 6047 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6048 else
6e3c9717 6049 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6050 }
89b667f8
JB		 6051
6052 for_each_encoder_on_crtc(dev, crtc, encoder)
6053 if (encoder->pre_enable)
6054 encoder->pre_enable(encoder);
6055
2dd24552
JB		 6056 i9xx_pfit_enable(intel_crtc);
6057
63cbb074
VS		 6058 intel_crtc_load_lut(crtc);
6059
e1fdc473 6060 intel_enable_pipe(intel_crtc);
be6a6f8e 6061
4b3a9526
VS		 6062 assert_vblank_disabled(crtc);
6063 drm_crtc_vblank_on(crtc);
6064
f9b61ff6
DV		 6065 for_each_encoder_on_crtc(dev, crtc, encoder)
6066 encoder->enable(encoder);
89b667f8
JB		 6067}
6068
f13c2ef3
DV		 6069static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6070{
6071 struct drm_device *dev = crtc->base.dev;
6072 struct drm_i915_private *dev_priv = dev->dev_private;
6073
6e3c9717
ACO		 6074 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6075 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6076}
6077
0b8765c6 6078static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6079{
6080 struct drm_device *dev = crtc->dev;
a72e4c9f 6081 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6083 struct intel_encoder *encoder;
79e53945 6084 int pipe = intel_crtc->pipe;
79e53945 6085
53d9f4e9 6086 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6087 return;
6088
f13c2ef3
DV		 6089 i9xx_set_pll_dividers(intel_crtc);
6090
6e3c9717 6091 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6092 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6093
6094 intel_set_pipe_timings(intel_crtc);
6095
5b18e57c
DV		 6096 i9xx_set_pipeconf(intel_crtc);
6097
f7abfe8b 6098 intel_crtc->active = true;
6b383a7f 6099
4a3436e8 6100 if (!IS_GEN2(dev))
a72e4c9f 6101 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6102
9d6d9f19
MK		 6103 for_each_encoder_on_crtc(dev, crtc, encoder)
6104 if (encoder->pre_enable)
6105 encoder->pre_enable(encoder);
6106
f6736a1a
DV		 6107 i9xx_enable_pll(intel_crtc);
6108
2dd24552
JB		 6109 i9xx_pfit_enable(intel_crtc);
6110
63cbb074
VS		 6111 intel_crtc_load_lut(crtc);
6112
f37fcc2a 6113 intel_update_watermarks(crtc);
e1fdc473 6114 intel_enable_pipe(intel_crtc);
be6a6f8e 6115
4b3a9526
VS		 6116 assert_vblank_disabled(crtc);
6117 drm_crtc_vblank_on(crtc);
6118
f9b61ff6
DV		 6119 for_each_encoder_on_crtc(dev, crtc, encoder)
6120 encoder->enable(encoder);
0b8765c6 6121}
79e53945 6122
87476d63
DV		 6123static void i9xx_pfit_disable(struct intel_crtc *crtc)
6124{
6125 struct drm_device *dev = crtc->base.dev;
6126 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6127
6e3c9717 6128 if (!crtc->config->gmch_pfit.control)
328d8e82 6129 return;
87476d63 6130
328d8e82 6131 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6132
328d8e82
DV		 6133 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6134 I915_READ(PFIT_CONTROL));
6135 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6136}
6137
0b8765c6
JB		 6138static void i9xx_crtc_disable(struct drm_crtc *crtc)
6139{
6140 struct drm_device *dev = crtc->dev;
6141 struct drm_i915_private *dev_priv = dev->dev_private;
6142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6143 struct intel_encoder *encoder;
0b8765c6 6144 int pipe = intel_crtc->pipe;
ef9c3aee 6145
6304cd91
VS		 6146 /*
6147 * On gen2 planes are double buffered but the pipe isn't, so we must
6148 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6149 * We also need to wait on all gmch platforms because of the
6150 * self-refresh mode constraint explained above.
6304cd91 6151 */
564ed191 6152 intel_wait_for_vblank(dev, pipe);
6304cd91 6153
4b3a9526
VS		 6154 for_each_encoder_on_crtc(dev, crtc, encoder)
6155 encoder->disable(encoder);
6156
f9b61ff6
DV		 6157 drm_crtc_vblank_off(crtc);
6158 assert_vblank_disabled(crtc);
6159
575f7ab7 6160 intel_disable_pipe(intel_crtc);
24a1f16d 6161
87476d63 6162 i9xx_pfit_disable(intel_crtc);
24a1f16d 6163
89b667f8
JB		 6164 for_each_encoder_on_crtc(dev, crtc, encoder)
6165 if (encoder->post_disable)
6166 encoder->post_disable(encoder);
6167
409ee761 6168 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6169 if (IS_CHERRYVIEW(dev))
6170 chv_disable_pll(dev_priv, pipe);
6171 else if (IS_VALLEYVIEW(dev))
6172 vlv_disable_pll(dev_priv, pipe);
6173 else
1c4e0274 6174 i9xx_disable_pll(intel_crtc);
076ed3b2 6175 }
0b8765c6 6176
4a3436e8 6177 if (!IS_GEN2(dev))
a72e4c9f 6178 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ		 6179
6180 intel_crtc->active = false;
6181 intel_update_watermarks(crtc);
0b8765c6
JB		 6182}
6183
b17d48e2
ML		 6184static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6185{
6186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6187 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6188 enum intel_display_power_domain domain;
6189 unsigned long domains;
6190
6191 if (!intel_crtc->active)
6192 return;
6193
a539205a
ML		 6194 if (to_intel_plane_state(crtc->primary->state)->visible) {
6195 intel_crtc_wait_for_pending_flips(crtc);
6196 intel_pre_disable_primary(crtc);
6197 }
6198
d032ffa0 6199 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2
ML		 6200 dev_priv->display.crtc_disable(crtc);
6201
6202 domains = intel_crtc->enabled_power_domains;
6203 for_each_power_domain(domain, domains)
6204 intel_display_power_put(dev_priv, domain);
6205 intel_crtc->enabled_power_domains = 0;
6206}
6207
6b72d486
ML		 6208/*
6209 * turn all crtc's off, but do not adjust state
6210 * This has to be paired with a call to intel_modeset_setup_hw_state.
6211 */
9716c691 6212void intel_display_suspend(struct drm_device *dev)
ee7b9f93 6213{
6b72d486
ML		 6214 struct drm_crtc *crtc;
6215
b17d48e2
ML		 6216 for_each_crtc(dev, crtc)
6217 intel_crtc_disable_noatomic(crtc);
ee7b9f93
JB		 6218}
6219
b04c5bd6 6220/* Master function to enable/disable CRTC and corresponding power wells */
5da76e94 6221int intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6222{
6223 struct drm_device *dev = crtc->dev;
5da76e94
ML		 6224 struct drm_mode_config *config = &dev->mode_config;
6225 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
0e572fe7 6226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5da76e94
ML		 6227 struct intel_crtc_state *pipe_config;
6228 struct drm_atomic_state *state;
6229 int ret;
976f8a20 6230
1b509259 6231 if (enable == intel_crtc->active)
5da76e94 6232 return 0;
0e572fe7 6233
1b509259 6234 if (enable && !crtc->state->enable)
5da76e94 6235 return 0;
1b509259 6236
5da76e94
ML		 6237 /* this function should be called with drm_modeset_lock_all for now */
6238 if (WARN_ON(!ctx))
6239 return -EIO;
6240 lockdep_assert_held(&ctx->ww_ctx);
1b509259 6241
5da76e94
ML		 6242 state = drm_atomic_state_alloc(dev);
6243 if (WARN_ON(!state))
6244 return -ENOMEM;
1b509259 6245
5da76e94
ML		 6246 state->acquire_ctx = ctx;
6247 state->allow_modeset = true;
6248
6249 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6250 if (IS_ERR(pipe_config)) {
6251 ret = PTR_ERR(pipe_config);
6252 goto err;
0e572fe7 6253 }
5da76e94
ML		 6254 pipe_config->base.active = enable;
6255
6256 ret = intel_set_mode(state);
6257 if (!ret)
6258 return ret;
6259
6260err:
6261 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6262 drm_atomic_state_free(state);
6263 return ret;
b04c5bd6
BF		 6264}
6265
6266/**
6267 * Sets the power management mode of the pipe and plane.
6268 */
6269void intel_crtc_update_dpms(struct drm_crtc *crtc)
6270{
6271 struct drm_device *dev = crtc->dev;
6272 struct intel_encoder *intel_encoder;
6273 bool enable = false;
6274
6275 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6276 enable |= intel_encoder->connectors_active;
6277
6278 intel_crtc_control(crtc, enable);
cdd59983
CW		 6279}
6280
ea5b213a 6281void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6282{
4ef69c7a 6283 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6284
ea5b213a
CW		 6285 drm_encoder_cleanup(encoder);
6286 kfree(intel_encoder);
7e7d76c3
JB		 6287}
6288
9237329d 6289/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6290 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6291 * state of the entire output pipe. */
9237329d 6292static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6293{
5ab432ef
DV		 6294 if (mode == DRM_MODE_DPMS_ON) {
6295 encoder->connectors_active = true;
6296
b2cabb0e 6297 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6298 } else {
6299 encoder->connectors_active = false;
6300
b2cabb0e 6301 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6302 }
79e53945
JB		 6303}
6304
0a91ca29
DV		 6305/* Cross check the actual hw state with our own modeset state tracking (and it's
6306 * internal consistency). */
b980514c 6307static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6308{
0a91ca29
DV		 6309 if (connector->get_hw_state(connector)) {
6310 struct intel_encoder *encoder = connector->encoder;
6311 struct drm_crtc *crtc;
6312 bool encoder_enabled;
6313 enum pipe pipe;
6314
6315 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6316 connector->base.base.id,
c23cc417 6317 connector->base.name);
0a91ca29 6318
0e32b39c
DA		 6319 /* there is no real hw state for MST connectors */
6320 if (connector->mst_port)
6321 return;
6322
e2c719b7 6323 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6324 "wrong connector dpms state\n");
e2c719b7 6325 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6326 "active connector not linked to encoder\n");
0a91ca29 6327
36cd7444 6328 if (encoder) {
e2c719b7 6329 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6330 "encoder->connectors_active not set\n");
6331
6332 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6333 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6334 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6335 return;
0a91ca29 6336
36cd7444 6337 crtc = encoder->base.crtc;
0a91ca29 6338
83d65738
MR		 6339 I915_STATE_WARN(!crtc->state->enable,
6340 "crtc not enabled\n");
e2c719b7
RC		 6341 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6342 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6343 "encoder active on the wrong pipe\n");
6344 }
0a91ca29 6345 }
79e53945
JB		 6346}
6347
08d9bc92
ACO		 6348int intel_connector_init(struct intel_connector *connector)
6349{
6350 struct drm_connector_state *connector_state;
6351
6352 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6353 if (!connector_state)
6354 return -ENOMEM;
6355
6356 connector->base.state = connector_state;
6357 return 0;
6358}
6359
6360struct intel_connector *intel_connector_alloc(void)
6361{
6362 struct intel_connector *connector;
6363
6364 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6365 if (!connector)
6366 return NULL;
6367
6368 if (intel_connector_init(connector) < 0) {
6369 kfree(connector);
6370 return NULL;
6371 }
6372
6373 return connector;
6374}
6375
5ab432ef
DV		 6376/* Even simpler default implementation, if there's really no special case to
6377 * consider. */
6378void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6379{
5ab432ef
DV		 6380 /* All the simple cases only support two dpms states. */
6381 if (mode != DRM_MODE_DPMS_ON)
6382 mode = DRM_MODE_DPMS_OFF;
d4270e57 6383
5ab432ef
DV		 6384 if (mode == connector->dpms)
6385 return;
6386
6387 connector->dpms = mode;
6388
6389 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6390 if (connector->encoder)
6391 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6392
b980514c 6393 intel_modeset_check_state(connector->dev);
79e53945
JB		 6394}
6395
f0947c37
DV		 6396/* Simple connector->get_hw_state implementation for encoders that support only
6397 * one connector and no cloning and hence the encoder state determines the state
6398 * of the connector. */
6399bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6400{
24929352 6401 enum pipe pipe = 0;
f0947c37 6402 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6403
f0947c37 6404 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6405}
6406
6d293983 6407static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6408{
6d293983
ACO		 6409 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6410 return crtc_state->fdi_lanes;
d272ddfa
VS		 6411
6412 return 0;
6413}
6414
6d293983 6415static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6416 struct intel_crtc_state *pipe_config)
1857e1da 6417{
6d293983
ACO		 6418 struct drm_atomic_state *state = pipe_config->base.state;
6419 struct intel_crtc *other_crtc;
6420 struct intel_crtc_state *other_crtc_state;
6421
1857e1da
DV		 6422 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6423 pipe_name(pipe), pipe_config->fdi_lanes);
6424 if (pipe_config->fdi_lanes > 4) {
6425 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6426 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6427 return -EINVAL;
1857e1da
DV		 6428 }
6429
bafb6553 6430 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6431 if (pipe_config->fdi_lanes > 2) {
6432 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6433 pipe_config->fdi_lanes);
6d293983 6434 return -EINVAL;
1857e1da 6435 } else {
6d293983 6436 return 0;
1857e1da
DV		 6437 }
6438 }
6439
6440 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6441 return 0;
1857e1da
DV		 6442
6443 /* Ivybridge 3 pipe is really complicated */
6444 switch (pipe) {
6445 case PIPE_A:
6d293983 6446 return 0;
1857e1da 6447 case PIPE_B:
6d293983
ACO		 6448 if (pipe_config->fdi_lanes <= 2)
6449 return 0;
6450
6451 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6452 other_crtc_state =
6453 intel_atomic_get_crtc_state(state, other_crtc);
6454 if (IS_ERR(other_crtc_state))
6455 return PTR_ERR(other_crtc_state);
6456
6457 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6458 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6459 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6460 return -EINVAL;
1857e1da 6461 }
6d293983 6462 return 0;
1857e1da 6463 case PIPE_C:
251cc67c
VS		 6464 if (pipe_config->fdi_lanes > 2) {
6465 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6466 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6467 return -EINVAL;
251cc67c 6468 }
6d293983
ACO		 6469
6470 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6471 other_crtc_state =
6472 intel_atomic_get_crtc_state(state, other_crtc);
6473 if (IS_ERR(other_crtc_state))
6474 return PTR_ERR(other_crtc_state);
6475
6476 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6477 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6478 return -EINVAL;
1857e1da 6479 }
6d293983 6480 return 0;
1857e1da
DV		 6481 default:
6482 BUG();
6483 }
6484}
6485
e29c22c0
DV		 6486#define RETRY 1
6487static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6488 struct intel_crtc_state *pipe_config)
877d48d5 6489{
1857e1da 6490 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6491 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6492 int lane, link_bw, fdi_dotclock, ret;
6493 bool needs_recompute = false;
877d48d5 6494
e29c22c0 6495retry:
877d48d5
DV		 6496 /* FDI is a binary signal running at ~2.7GHz, encoding
6497 * each output octet as 10 bits. The actual frequency
6498 * is stored as a divider into a 100MHz clock, and the
6499 * mode pixel clock is stored in units of 1KHz.
6500 * Hence the bw of each lane in terms of the mode signal
6501 * is:
6502 */
6503 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6504
241bfc38 6505 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6506
2bd89a07 6507 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6508 pipe_config->pipe_bpp);
6509
6510 pipe_config->fdi_lanes = lane;
6511
2bd89a07 6512 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6513 link_bw, &pipe_config->fdi_m_n);
1857e1da 6514
6d293983
ACO		 6515 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6516 intel_crtc->pipe, pipe_config);
6517 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6518 pipe_config->pipe_bpp -= 2*3;
6519 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6520 pipe_config->pipe_bpp);
6521 needs_recompute = true;
6522 pipe_config->bw_constrained = true;
6523
6524 goto retry;
6525 }
6526
6527 if (needs_recompute)
6528 return RETRY;
6529
6d293983 6530 return ret;
877d48d5
DV		 6531}
6532
8cfb3407
VS		 6533static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6534 struct intel_crtc_state *pipe_config)
6535{
6536 if (pipe_config->pipe_bpp > 24)
6537 return false;
6538
6539 /* HSW can handle pixel rate up to cdclk? */
6540 if (IS_HASWELL(dev_priv->dev))
6541 return true;
6542
6543 /*
b432e5cf
VS		 6544 * We compare against max which means we must take
6545 * the increased cdclk requirement into account when
6546 * calculating the new cdclk.
6547 *
6548 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6549 */
6550 return ilk_pipe_pixel_rate(pipe_config) <=
6551 dev_priv->max_cdclk_freq * 95 / 100;
6552}
6553
42db64ef 6554static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6555 struct intel_crtc_state *pipe_config)
42db64ef 6556{
8cfb3407
VS		 6557 struct drm_device *dev = crtc->base.dev;
6558 struct drm_i915_private *dev_priv = dev->dev_private;
6559
d330a953 6560 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6561 hsw_crtc_supports_ips(crtc) &&
6562 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6563}
6564
a43f6e0f 6565static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6566 struct intel_crtc_state *pipe_config)
79e53945 6567{
a43f6e0f 6568 struct drm_device *dev = crtc->base.dev;
8bd31e67 6569 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6570 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6571
ad3a4479 6572 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6573 if (INTEL_INFO(dev)->gen < 4) {
44913155 6574 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6575
6576 /*
6577 * Enable pixel doubling when the dot clock
6578 * is > 90% of the (display) core speed.
6579 *
b397c96b
VS		 6580 * GDG double wide on either pipe,
6581 * otherwise pipe A only.
cf532bb2 6582 */
b397c96b 6583 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6584 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6585 clock_limit *= 2;
cf532bb2 6586 pipe_config->double_wide = true;
ad3a4479
VS		 6587 }
6588
241bfc38 6589 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6590 return -EINVAL;
2c07245f 6591 }
89749350 6592
1d1d0e27
VS		 6593 /*
6594 * Pipe horizontal size must be even in:
6595 * - DVO ganged mode
6596 * - LVDS dual channel mode
6597 * - Double wide pipe
6598 */
a93e255f 6599 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6600 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6601 pipe_config->pipe_src_w &= ~1;
6602
8693a824
DL		 6603 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6604 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6605 */
6606 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6607 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6608 return -EINVAL;
44f46b42 6609
f5adf94e 6610 if (HAS_IPS(dev))
a43f6e0f
DV		 6611 hsw_compute_ips_config(crtc, pipe_config);
6612
877d48d5 6613 if (pipe_config->has_pch_encoder)
a43f6e0f 6614 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6615
cf5a15be 6616 return 0;
79e53945
JB		 6617}
6618
1652d19e
VS		 6619static int skylake_get_display_clock_speed(struct drm_device *dev)
6620{
6621 struct drm_i915_private *dev_priv = to_i915(dev);
6622 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6623 uint32_t cdctl = I915_READ(CDCLK_CTL);
6624 uint32_t linkrate;
6625
414355a7 6626 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6627 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6628
6629 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6630 return 540000;
6631
6632 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6633 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6634
71cd8423
DL		 6635 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6636 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6637 /* vco 8640 */
6638 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6639 case CDCLK_FREQ_450_432:
6640 return 432000;
6641 case CDCLK_FREQ_337_308:
6642 return 308570;
6643 case CDCLK_FREQ_675_617:
6644 return 617140;
6645 default:
6646 WARN(1, "Unknown cd freq selection\n");
6647 }
6648 } else {
6649 /* vco 8100 */
6650 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6651 case CDCLK_FREQ_450_432:
6652 return 450000;
6653 case CDCLK_FREQ_337_308:
6654 return 337500;
6655 case CDCLK_FREQ_675_617:
6656 return 675000;
6657 default:
6658 WARN(1, "Unknown cd freq selection\n");
6659 }
6660 }
6661
6662 /* error case, do as if DPLL0 isn't enabled */
6663 return 24000;
6664}
6665
acd3f3d3
BP		 6666static int broxton_get_display_clock_speed(struct drm_device *dev)
6667{
6668 struct drm_i915_private *dev_priv = to_i915(dev);
6669 uint32_t cdctl = I915_READ(CDCLK_CTL);
6670 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6671 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6672 int cdclk;
6673
6674 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6675 return 19200;
6676
6677 cdclk = 19200 * pll_ratio / 2;
6678
6679 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6680 case BXT_CDCLK_CD2X_DIV_SEL_1:
6681 return cdclk; /* 576MHz or 624MHz */
6682 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6683 return cdclk * 2 / 3; /* 384MHz */
6684 case BXT_CDCLK_CD2X_DIV_SEL_2:
6685 return cdclk / 2; /* 288MHz */
6686 case BXT_CDCLK_CD2X_DIV_SEL_4:
6687 return cdclk / 4; /* 144MHz */
6688 }
6689
6690 /* error case, do as if DE PLL isn't enabled */
6691 return 19200;
6692}
6693
1652d19e
VS		 6694static int broadwell_get_display_clock_speed(struct drm_device *dev)
6695{
6696 struct drm_i915_private *dev_priv = dev->dev_private;
6697 uint32_t lcpll = I915_READ(LCPLL_CTL);
6698 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6699
6700 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6701 return 800000;
6702 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6703 return 450000;
6704 else if (freq == LCPLL_CLK_FREQ_450)
6705 return 450000;
6706 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6707 return 540000;
6708 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6709 return 337500;
6710 else
6711 return 675000;
6712}
6713
6714static int haswell_get_display_clock_speed(struct drm_device *dev)
6715{
6716 struct drm_i915_private *dev_priv = dev->dev_private;
6717 uint32_t lcpll = I915_READ(LCPLL_CTL);
6718 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6719
6720 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6721 return 800000;
6722 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6723 return 450000;
6724 else if (freq == LCPLL_CLK_FREQ_450)
6725 return 450000;
6726 else if (IS_HSW_ULT(dev))
6727 return 337500;
6728 else
6729 return 540000;
79e53945
JB		 6730}
6731
25eb05fc
JB		 6732static int valleyview_get_display_clock_speed(struct drm_device *dev)
6733{
d197b7d3 6734 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6735 u32 val;
6736 int divider;
6737
6bcda4f0
VS		 6738 if (dev_priv->hpll_freq == 0)
6739 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6740
a580516d 6741 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6742 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6743 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6744
6745 divider = val & DISPLAY_FREQUENCY_VALUES;
6746
7d007f40
VS		 6747 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6748 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6749 "cdclk change in progress\n");
6750
6bcda4f0 6751 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6752}
6753
b37a6434
VS		 6754static int ilk_get_display_clock_speed(struct drm_device *dev)
6755{
6756 return 450000;
6757}
6758
e70236a8
JB		 6759static int i945_get_display_clock_speed(struct drm_device *dev)
6760{
6761 return 400000;
6762}
79e53945 6763
e70236a8 6764static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6765{
e907f170 6766 return 333333;
e70236a8 6767}
79e53945 6768
e70236a8
JB		 6769static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6770{
6771 return 200000;
6772}
79e53945 6773
257a7ffc
DV		 6774static int pnv_get_display_clock_speed(struct drm_device *dev)
6775{
6776 u16 gcfgc = 0;
6777
6778 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6779
6780 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6781 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6782 return 266667;
257a7ffc 6783 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6784 return 333333;
257a7ffc 6785 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6786 return 444444;
257a7ffc
DV		 6787 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6788 return 200000;
6789 default:
6790 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6791 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6792 return 133333;
257a7ffc 6793 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6794 return 166667;
257a7ffc
DV		 6795 }
6796}
6797
e70236a8
JB		 6798static int i915gm_get_display_clock_speed(struct drm_device *dev)
6799{
6800 u16 gcfgc = 0;
79e53945 6801
e70236a8
JB		 6802 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6803
6804 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6805 return 133333;
e70236a8
JB		 6806 else {
6807 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6808 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6809 return 333333;
e70236a8
JB		 6810 default:
6811 case GC_DISPLAY_CLOCK_190_200_MHZ:
6812 return 190000;
79e53945 6813 }
e70236a8
JB		 6814 }
6815}
6816
6817static int i865_get_display_clock_speed(struct drm_device *dev)
6818{
e907f170 6819 return 266667;
e70236a8
JB		 6820}
6821
1b1d2716 6822static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6823{
6824 u16 hpllcc = 0;
1b1d2716 6825
65cd2b3f
VS		 6826 /*
6827 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6828 * encoding is different :(
6829 * FIXME is this the right way to detect 852GM/852GMV?
6830 */
6831 if (dev->pdev->revision == 0x1)
6832 return 133333;
6833
1b1d2716
VS		 6834 pci_bus_read_config_word(dev->pdev->bus,
6835 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6836
e70236a8
JB		 6837 /* Assume that the hardware is in the high speed state. This
6838 * should be the default.
6839 */
6840 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6841 case GC_CLOCK_133_200:
1b1d2716 6842 case GC_CLOCK_133_200_2:
e70236a8
JB		 6843 case GC_CLOCK_100_200:
6844 return 200000;
6845 case GC_CLOCK_166_250:
6846 return 250000;
6847 case GC_CLOCK_100_133:
e907f170 6848 return 133333;
1b1d2716
VS		 6849 case GC_CLOCK_133_266:
6850 case GC_CLOCK_133_266_2:
6851 case GC_CLOCK_166_266:
6852 return 266667;
e70236a8 6853 }
79e53945 6854
e70236a8
JB		 6855 /* Shouldn't happen */
6856 return 0;
6857}
79e53945 6858
e70236a8
JB		 6859static int i830_get_display_clock_speed(struct drm_device *dev)
6860{
e907f170 6861 return 133333;
79e53945
JB		 6862}
6863
34edce2f
VS		 6864static unsigned int intel_hpll_vco(struct drm_device *dev)
6865{
6866 struct drm_i915_private *dev_priv = dev->dev_private;
6867 static const unsigned int blb_vco[8] = {
6868 [0] = 3200000,
6869 [1] = 4000000,
6870 [2] = 5333333,
6871 [3] = 4800000,
6872 [4] = 6400000,
6873 };
6874 static const unsigned int pnv_vco[8] = {
6875 [0] = 3200000,
6876 [1] = 4000000,
6877 [2] = 5333333,
6878 [3] = 4800000,
6879 [4] = 2666667,
6880 };
6881 static const unsigned int cl_vco[8] = {
6882 [0] = 3200000,
6883 [1] = 4000000,
6884 [2] = 5333333,
6885 [3] = 6400000,
6886 [4] = 3333333,
6887 [5] = 3566667,
6888 [6] = 4266667,
6889 };
6890 static const unsigned int elk_vco[8] = {
6891 [0] = 3200000,
6892 [1] = 4000000,
6893 [2] = 5333333,
6894 [3] = 4800000,
6895 };
6896 static const unsigned int ctg_vco[8] = {
6897 [0] = 3200000,
6898 [1] = 4000000,
6899 [2] = 5333333,
6900 [3] = 6400000,
6901 [4] = 2666667,
6902 [5] = 4266667,
6903 };
6904 const unsigned int *vco_table;
6905 unsigned int vco;
6906 uint8_t tmp = 0;
6907
6908 /* FIXME other chipsets? */
6909 if (IS_GM45(dev))
6910 vco_table = ctg_vco;
6911 else if (IS_G4X(dev))
6912 vco_table = elk_vco;
6913 else if (IS_CRESTLINE(dev))
6914 vco_table = cl_vco;
6915 else if (IS_PINEVIEW(dev))
6916 vco_table = pnv_vco;
6917 else if (IS_G33(dev))
6918 vco_table = blb_vco;
6919 else
6920 return 0;
6921
6922 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6923
6924 vco = vco_table[tmp & 0x7];
6925 if (vco == 0)
6926 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6927 else
6928 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6929
6930 return vco;
6931}
6932
6933static int gm45_get_display_clock_speed(struct drm_device *dev)
6934{
6935 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6936 uint16_t tmp = 0;
6937
6938 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6939
6940 cdclk_sel = (tmp >> 12) & 0x1;
6941
6942 switch (vco) {
6943 case 2666667:
6944 case 4000000:
6945 case 5333333:
6946 return cdclk_sel ? 333333 : 222222;
6947 case 3200000:
6948 return cdclk_sel ? 320000 : 228571;
6949 default:
6950 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6951 return 222222;
6952 }
6953}
6954
6955static int i965gm_get_display_clock_speed(struct drm_device *dev)
6956{
6957 static const uint8_t div_3200[] = { 16, 10, 8 };
6958 static const uint8_t div_4000[] = { 20, 12, 10 };
6959 static const uint8_t div_5333[] = { 24, 16, 14 };
6960 const uint8_t *div_table;
6961 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6962 uint16_t tmp = 0;
6963
6964 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6965
6966 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6967
6968 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6969 goto fail;
6970
6971 switch (vco) {
6972 case 3200000:
6973 div_table = div_3200;
6974 break;
6975 case 4000000:
6976 div_table = div_4000;
6977 break;
6978 case 5333333:
6979 div_table = div_5333;
6980 break;
6981 default:
6982 goto fail;
6983 }
6984
6985 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6986
caf4e252 6987fail:
34edce2f
VS		 6988 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6989 return 200000;
6990}
6991
6992static int g33_get_display_clock_speed(struct drm_device *dev)
6993{
6994 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6995 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6996 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6997 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6998 const uint8_t *div_table;
6999 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7000 uint16_t tmp = 0;
7001
7002 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7003
7004 cdclk_sel = (tmp >> 4) & 0x7;
7005
7006 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7007 goto fail;
7008
7009 switch (vco) {
7010 case 3200000:
7011 div_table = div_3200;
7012 break;
7013 case 4000000:
7014 div_table = div_4000;
7015 break;
7016 case 4800000:
7017 div_table = div_4800;
7018 break;
7019 case 5333333:
7020 div_table = div_5333;
7021 break;
7022 default:
7023 goto fail;
7024 }
7025
7026 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7027
caf4e252 7028fail:
34edce2f
VS		 7029 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7030 return 190476;
7031}
7032
2c07245f 7033static void
a65851af 7034intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7035{
a65851af
VS		 7036 while (*num > DATA_LINK_M_N_MASK ||
7037 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7038 *num >>= 1;
7039 *den >>= 1;
7040 }
7041}
7042
a65851af
VS		 7043static void compute_m_n(unsigned int m, unsigned int n,
7044 uint32_t *ret_m, uint32_t *ret_n)
7045{
7046 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7047 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7048 intel_reduce_m_n_ratio(ret_m, ret_n);
7049}
7050
e69d0bc1
DV		 7051void
7052intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7053 int pixel_clock, int link_clock,
7054 struct intel_link_m_n *m_n)
2c07245f 7055{
e69d0bc1 7056 m_n->tu = 64;
a65851af
VS		 7057
7058 compute_m_n(bits_per_pixel * pixel_clock,
7059 link_clock * nlanes * 8,
7060 &m_n->gmch_m, &m_n->gmch_n);
7061
7062 compute_m_n(pixel_clock, link_clock,
7063 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7064}
7065
a7615030
CW		 7066static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7067{
d330a953
JN		 7068 if (i915.panel_use_ssc >= 0)
7069 return i915.panel_use_ssc != 0;
41aa3448 7070 return dev_priv->vbt.lvds_use_ssc
435793df 7071 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7072}
7073
a93e255f
ACO		 7074static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7075 int num_connectors)
c65d77d8 7076{
a93e255f 7077 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7078 struct drm_i915_private *dev_priv = dev->dev_private;
7079 int refclk;
7080
a93e255f
ACO		 7081 WARN_ON(!crtc_state->base.state);
7082
5ab7b0b7 7083 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7084 refclk = 100000;
a93e255f 7085 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7086 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7087 refclk = dev_priv->vbt.lvds_ssc_freq;
7088 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7089 } else if (!IS_GEN2(dev)) {
7090 refclk = 96000;
7091 } else {
7092 refclk = 48000;
7093 }
7094
7095 return refclk;
7096}
7097
7429e9d4 7098static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7099{
7df00d7a 7100 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7101}
f47709a9 7102
7429e9d4
DV		 7103static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7104{
7105 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7106}
7107
f47709a9 7108static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7109 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7110 intel_clock_t *reduced_clock)
7111{
f47709a9 7112 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7113 u32 fp, fp2 = 0;
7114
7115 if (IS_PINEVIEW(dev)) {
190f68c5 7116 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7117 if (reduced_clock)
7429e9d4 7118 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7119 } else {
190f68c5 7120 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7121 if (reduced_clock)
7429e9d4 7122 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7123 }
7124
190f68c5 7125 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7126
f47709a9 7127 crtc->lowfreq_avail = false;
a93e255f 7128 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7129 reduced_clock) {
190f68c5 7130 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7131 crtc->lowfreq_avail = true;
a7516a05 7132 } else {
190f68c5 7133 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7134 }
7135}
7136
5e69f97f
CML		 7137static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7138 pipe)
89b667f8
JB		 7139{
7140 u32 reg_val;
7141
7142 /*
7143 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7144 * and set it to a reasonable value instead.
7145 */
ab3c759a 7146 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7147 reg_val &= 0xffffff00;
7148 reg_val |= 0x00000030;
ab3c759a 7149 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7150
ab3c759a 7151 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7152 reg_val &= 0x8cffffff;
7153 reg_val = 0x8c000000;
ab3c759a 7154 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7155
ab3c759a 7156 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7157 reg_val &= 0xffffff00;
ab3c759a 7158 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7159
ab3c759a 7160 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7161 reg_val &= 0x00ffffff;
7162 reg_val |= 0xb0000000;
ab3c759a 7163 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7164}
7165
b551842d
DV		 7166static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7167 struct intel_link_m_n *m_n)
7168{
7169 struct drm_device *dev = crtc->base.dev;
7170 struct drm_i915_private *dev_priv = dev->dev_private;
7171 int pipe = crtc->pipe;
7172
e3b95f1e
DV		 7173 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7174 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7175 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7176 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7177}
7178
7179static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7180 struct intel_link_m_n *m_n,
7181 struct intel_link_m_n *m2_n2)
b551842d
DV		 7182{
7183 struct drm_device *dev = crtc->base.dev;
7184 struct drm_i915_private *dev_priv = dev->dev_private;
7185 int pipe = crtc->pipe;
6e3c9717 7186 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7187
7188 if (INTEL_INFO(dev)->gen >= 5) {
7189 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7190 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7191 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7192 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7193 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7194 * for gen < 8) and if DRRS is supported (to make sure the
7195 * registers are not unnecessarily accessed).
7196 */
44395bfe 7197 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7198 crtc->config->has_drrs) {
f769cd24
VK		 7199 I915_WRITE(PIPE_DATA_M2(transcoder),
7200 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7201 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7202 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7203 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7204 }
b551842d 7205 } else {
e3b95f1e
DV		 7206 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7207 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7208 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7209 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7210 }
7211}
7212
fe3cd48d 7213void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7214{
fe3cd48d
R		 7215 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7216
7217 if (m_n == M1_N1) {
7218 dp_m_n = &crtc->config->dp_m_n;
7219 dp_m2_n2 = &crtc->config->dp_m2_n2;
7220 } else if (m_n == M2_N2) {
7221
7222 /*
7223 * M2_N2 registers are not supported. Hence m2_n2 divider value
7224 * needs to be programmed into M1_N1.
7225 */
7226 dp_m_n = &crtc->config->dp_m2_n2;
7227 } else {
7228 DRM_ERROR("Unsupported divider value\n");
7229 return;
7230 }
7231
6e3c9717
ACO		 7232 if (crtc->config->has_pch_encoder)
7233 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7234 else
fe3cd48d 7235 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7236}
7237
251ac862
DV		 7238static void vlv_compute_dpll(struct intel_crtc *crtc,
7239 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7240{
7241 u32 dpll, dpll_md;
7242
7243 /*
7244 * Enable DPIO clock input. We should never disable the reference
7245 * clock for pipe B, since VGA hotplug / manual detection depends
7246 * on it.
7247 */
60bfe44f
VS		 7248 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7249 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7250 /* We should never disable this, set it here for state tracking */
7251 if (crtc->pipe == PIPE_B)
7252 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7253 dpll |= DPLL_VCO_ENABLE;
d288f65f 7254 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7255
d288f65f 7256 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7257 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7258 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7259}
7260
d288f65f 7261static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7262 const struct intel_crtc_state *pipe_config)
a0c4da24 7263{
f47709a9 7264 struct drm_device *dev = crtc->base.dev;
a0c4da24 7265 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7266 int pipe = crtc->pipe;
bdd4b6a6 7267 u32 mdiv;
a0c4da24 7268 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7269 u32 coreclk, reg_val;
a0c4da24 7270
a580516d 7271 mutex_lock(&dev_priv->sb_lock);
09153000 7272
d288f65f
VS		 7273 bestn = pipe_config->dpll.n;
7274 bestm1 = pipe_config->dpll.m1;
7275 bestm2 = pipe_config->dpll.m2;
7276 bestp1 = pipe_config->dpll.p1;
7277 bestp2 = pipe_config->dpll.p2;
a0c4da24 7278
89b667f8
JB		 7279 /* See eDP HDMI DPIO driver vbios notes doc */
7280
7281 /* PLL B needs special handling */
bdd4b6a6 7282 if (pipe == PIPE_B)
5e69f97f 7283 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7284
7285 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7286 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7287
7288 /* Disable target IRef on PLL */
ab3c759a 7289 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7290 reg_val &= 0x00ffffff;
ab3c759a 7291 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7292
7293 /* Disable fast lock */
ab3c759a 7294 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7295
7296 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7297 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7298 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7299 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7300 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7301
7302 /*
7303 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7304 * but we don't support that).
7305 * Note: don't use the DAC post divider as it seems unstable.
7306 */
7307 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7308 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7309
a0c4da24 7310 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7311 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7312
89b667f8 7313 /* Set HBR and RBR LPF coefficients */
d288f65f 7314 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7315 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7316 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7317 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7318 0x009f0003);
89b667f8 7319 else
ab3c759a 7320 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7321 0x00d0000f);
7322
681a8504 7323 if (pipe_config->has_dp_encoder) {
89b667f8 7324 /* Use SSC source */
bdd4b6a6 7325 if (pipe == PIPE_A)
ab3c759a 7326 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7327 0x0df40000);
7328 else
ab3c759a 7329 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7330 0x0df70000);
7331 } else { /* HDMI or VGA */
7332 /* Use bend source */
bdd4b6a6 7333 if (pipe == PIPE_A)
ab3c759a 7334 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7335 0x0df70000);
7336 else
ab3c759a 7337 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7338 0x0df40000);
7339 }
a0c4da24 7340
ab3c759a 7341 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7342 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7343 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7344 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7345 coreclk |= 0x01000000;
ab3c759a 7346 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7347
ab3c759a 7348 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7349 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7350}
7351
251ac862
DV		 7352static void chv_compute_dpll(struct intel_crtc *crtc,
7353 struct intel_crtc_state *pipe_config)
1ae0d137 7354{
60bfe44f
VS		 7355 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7356 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7357 DPLL_VCO_ENABLE;
7358 if (crtc->pipe != PIPE_A)
d288f65f 7359 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7360
d288f65f
VS		 7361 pipe_config->dpll_hw_state.dpll_md =
7362 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7363}
7364
d288f65f 7365static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7366 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7367{
7368 struct drm_device *dev = crtc->base.dev;
7369 struct drm_i915_private *dev_priv = dev->dev_private;
7370 int pipe = crtc->pipe;
7371 int dpll_reg = DPLL(crtc->pipe);
7372 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7373 u32 loopfilter, tribuf_calcntr;
9d556c99 7374 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7375 u32 dpio_val;
9cbe40c1 7376 int vco;
9d556c99 7377
d288f65f
VS		 7378 bestn = pipe_config->dpll.n;
7379 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7380 bestm1 = pipe_config->dpll.m1;
7381 bestm2 = pipe_config->dpll.m2 >> 22;
7382 bestp1 = pipe_config->dpll.p1;
7383 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7384 vco = pipe_config->dpll.vco;
a945ce7e 7385 dpio_val = 0;
9cbe40c1 7386 loopfilter = 0;
9d556c99
CML		 7387
7388 /*
7389 * Enable Refclk and SSC
7390 */
a11b0703 7391 I915_WRITE(dpll_reg,
d288f65f 7392 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7393
a580516d 7394 mutex_lock(&dev_priv->sb_lock);
9d556c99 7395
9d556c99
CML		 7396 /* p1 and p2 divider */
7397 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7398 5 << DPIO_CHV_S1_DIV_SHIFT |
7399 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7400 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7401 1 << DPIO_CHV_K_DIV_SHIFT);
7402
7403 /* Feedback post-divider - m2 */
7404 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7405
7406 /* Feedback refclk divider - n and m1 */
7407 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7408 DPIO_CHV_M1_DIV_BY_2 |
7409 1 << DPIO_CHV_N_DIV_SHIFT);
7410
7411 /* M2 fraction division */
a945ce7e
VP		 7412 if (bestm2_frac)
7413 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7414
7415 /* M2 fraction division enable */
a945ce7e
VP		 7416 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7417 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7418 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7419 if (bestm2_frac)
7420 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7421 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7422
de3a0fde
VP		 7423 /* Program digital lock detect threshold */
7424 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7425 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7426 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7427 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7428 if (!bestm2_frac)
7429 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7430 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7431
9d556c99 7432 /* Loop filter */
9cbe40c1
VP		 7433 if (vco == 5400000) {
7434 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7435 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7436 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7437 tribuf_calcntr = 0x9;
7438 } else if (vco <= 6200000) {
7439 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7440 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7441 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7442 tribuf_calcntr = 0x9;
7443 } else if (vco <= 6480000) {
7444 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7445 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7446 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7447 tribuf_calcntr = 0x8;
7448 } else {
7449 /* Not supported. Apply the same limits as in the max case */
7450 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7451 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7452 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7453 tribuf_calcntr = 0;
7454 }
9d556c99
CML		 7455 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7456
968040b2 7457 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7458 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7459 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7460 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7461
9d556c99
CML		 7462 /* AFC Recal */
7463 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7464 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7465 DPIO_AFC_RECAL);
7466
a580516d 7467 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7468}
7469
d288f65f
VS		 7470/**
7471 * vlv_force_pll_on - forcibly enable just the PLL
7472 * @dev_priv: i915 private structure
7473 * @pipe: pipe PLL to enable
7474 * @dpll: PLL configuration
7475 *
7476 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7477 * in cases where we need the PLL enabled even when @pipe is not going to
7478 * be enabled.
7479 */
7480void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7481 const struct dpll *dpll)
7482{
7483 struct intel_crtc *crtc =
7484 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7485 struct intel_crtc_state pipe_config = {
a93e255f 7486 .base.crtc = &crtc->base,
d288f65f
VS		 7487 .pixel_multiplier = 1,
7488 .dpll = *dpll,
7489 };
7490
7491 if (IS_CHERRYVIEW(dev)) {
251ac862 7492 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7493 chv_prepare_pll(crtc, &pipe_config);
7494 chv_enable_pll(crtc, &pipe_config);
7495 } else {
251ac862 7496 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7497 vlv_prepare_pll(crtc, &pipe_config);
7498 vlv_enable_pll(crtc, &pipe_config);
7499 }
7500}
7501
7502/**
7503 * vlv_force_pll_off - forcibly disable just the PLL
7504 * @dev_priv: i915 private structure
7505 * @pipe: pipe PLL to disable
7506 *
7507 * Disable the PLL for @pipe. To be used in cases where we need
7508 * the PLL enabled even when @pipe is not going to be enabled.
7509 */
7510void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7511{
7512 if (IS_CHERRYVIEW(dev))
7513 chv_disable_pll(to_i915(dev), pipe);
7514 else
7515 vlv_disable_pll(to_i915(dev), pipe);
7516}
7517
251ac862
DV		 7518static void i9xx_compute_dpll(struct intel_crtc *crtc,
7519 struct intel_crtc_state *crtc_state,
7520 intel_clock_t *reduced_clock,
7521 int num_connectors)
eb1cbe48 7522{
f47709a9 7523 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7524 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7525 u32 dpll;
7526 bool is_sdvo;
190f68c5 7527 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7528
190f68c5 7529 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7530
a93e255f
ACO		 7531 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7532 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7533
7534 dpll = DPLL_VGA_MODE_DIS;
7535
a93e255f 7536 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7537 dpll |= DPLLB_MODE_LVDS;
7538 else
7539 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7540
ef1b460d 7541 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7542 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7543 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7544 }
198a037f
DV		 7545
7546 if (is_sdvo)
4a33e48d 7547 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7548
190f68c5 7549 if (crtc_state->has_dp_encoder)
4a33e48d 7550 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7551
7552 /* compute bitmask from p1 value */
7553 if (IS_PINEVIEW(dev))
7554 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7555 else {
7556 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7557 if (IS_G4X(dev) && reduced_clock)
7558 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7559 }
7560 switch (clock->p2) {
7561 case 5:
7562 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7563 break;
7564 case 7:
7565 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7566 break;
7567 case 10:
7568 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7569 break;
7570 case 14:
7571 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7572 break;
7573 }
7574 if (INTEL_INFO(dev)->gen >= 4)
7575 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7576
190f68c5 7577 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7578 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7579 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7580 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7581 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7582 else
7583 dpll |= PLL_REF_INPUT_DREFCLK;
7584
7585 dpll |= DPLL_VCO_ENABLE;
190f68c5 7586 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7587
eb1cbe48 7588 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7589 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7590 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7591 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7592 }
7593}
7594
251ac862
DV		 7595static void i8xx_compute_dpll(struct intel_crtc *crtc,
7596 struct intel_crtc_state *crtc_state,
7597 intel_clock_t *reduced_clock,
7598 int num_connectors)
eb1cbe48 7599{
f47709a9 7600 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7601 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7602 u32 dpll;
190f68c5 7603 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7604
190f68c5 7605 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7606
eb1cbe48
DV		 7607 dpll = DPLL_VGA_MODE_DIS;
7608
a93e255f 7609 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7610 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7611 } else {
7612 if (clock->p1 == 2)
7613 dpll |= PLL_P1_DIVIDE_BY_TWO;
7614 else
7615 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7616 if (clock->p2 == 4)
7617 dpll |= PLL_P2_DIVIDE_BY_4;
7618 }
7619
a93e255f 7620 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7621 dpll |= DPLL_DVO_2X_MODE;
7622
a93e255f 7623 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7624 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7625 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7626 else
7627 dpll |= PLL_REF_INPUT_DREFCLK;
7628
7629 dpll |= DPLL_VCO_ENABLE;
190f68c5 7630 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7631}
7632
8a654f3b 7633static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7634{
7635 struct drm_device *dev = intel_crtc->base.dev;
7636 struct drm_i915_private *dev_priv = dev->dev_private;
7637 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7638 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7639 struct drm_display_mode *adjusted_mode =
6e3c9717 7640 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7641 uint32_t crtc_vtotal, crtc_vblank_end;
7642 int vsyncshift = 0;
4d8a62ea
DV		 7643
7644 /* We need to be careful not to changed the adjusted mode, for otherwise
7645 * the hw state checker will get angry at the mismatch. */
7646 crtc_vtotal = adjusted_mode->crtc_vtotal;
7647 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7648
609aeaca 7649 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7650 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7651 crtc_vtotal -= 1;
7652 crtc_vblank_end -= 1;
609aeaca 7653
409ee761 7654 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7655 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7656 else
7657 vsyncshift = adjusted_mode->crtc_hsync_start -
7658 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7659 if (vsyncshift < 0)
7660 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7661 }
7662
7663 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7664 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7665
fe2b8f9d 7666 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7667 (adjusted_mode->crtc_hdisplay - 1) |
7668 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7669 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7670 (adjusted_mode->crtc_hblank_start - 1) |
7671 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7672 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7673 (adjusted_mode->crtc_hsync_start - 1) |
7674 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7675
fe2b8f9d 7676 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7677 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7678 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7679 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7680 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7681 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7682 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7683 (adjusted_mode->crtc_vsync_start - 1) |
7684 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7685
b5e508d4
PZ		 7686 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7687 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7688 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7689 * bits. */
7690 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7691 (pipe == PIPE_B || pipe == PIPE_C))
7692 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7693
b0e77b9c
PZ		 7694 /* pipesrc controls the size that is scaled from, which should
7695 * always be the user's requested size.
7696 */
7697 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7698 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7699 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7700}
7701
1bd1bd80 7702static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7703 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7704{
7705 struct drm_device *dev = crtc->base.dev;
7706 struct drm_i915_private *dev_priv = dev->dev_private;
7707 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7708 uint32_t tmp;
7709
7710 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7711 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7712 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7713 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7714 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7715 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7716 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7717 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7718 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7719
7720 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7721 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7722 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7723 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7724 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7725 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7726 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7727 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7728 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7729
7730 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7731 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7732 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7733 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7734 }
7735
7736 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7737 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7738 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7739
2d112de7
ACO		 7740 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7741 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7742}
7743
f6a83288 7744void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7745 struct intel_crtc_state *pipe_config)
babea61d 7746{
2d112de7
ACO		 7747 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7748 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7749 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7750 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7751
2d112de7
ACO		 7752 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7753 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7754 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7755 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7756
2d112de7 7757 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7758
2d112de7
ACO		 7759 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7760 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7761}
7762
84b046f3
DV		 7763static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7764{
7765 struct drm_device *dev = intel_crtc->base.dev;
7766 struct drm_i915_private *dev_priv = dev->dev_private;
7767 uint32_t pipeconf;
7768
9f11a9e4 7769 pipeconf = 0;
84b046f3 7770
b6b5d049
VS		 7771 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7772 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7773 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7774
6e3c9717 7775 if (intel_crtc->config->double_wide)
cf532bb2 7776 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7777
ff9ce46e
DV		 7778 /* only g4x and later have fancy bpc/dither controls */
7779 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7780 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7781 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7782 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7783 PIPECONF_DITHER_TYPE_SP;
84b046f3 7784
6e3c9717 7785 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7786 case 18:
7787 pipeconf |= PIPECONF_6BPC;
7788 break;
7789 case 24:
7790 pipeconf |= PIPECONF_8BPC;
7791 break;
7792 case 30:
7793 pipeconf |= PIPECONF_10BPC;
7794 break;
7795 default:
7796 /* Case prevented by intel_choose_pipe_bpp_dither. */
7797 BUG();
84b046f3
DV		 7798 }
7799 }
7800
7801 if (HAS_PIPE_CXSR(dev)) {
7802 if (intel_crtc->lowfreq_avail) {
7803 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7804 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7805 } else {
7806 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7807 }
7808 }
7809
6e3c9717 7810 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7811 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7812 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7813 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7814 else
7815 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7816 } else
84b046f3
DV		 7817 pipeconf |= PIPECONF_PROGRESSIVE;
7818
6e3c9717 7819 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7820 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7821
84b046f3
DV		 7822 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7823 POSTING_READ(PIPECONF(intel_crtc->pipe));
7824}
7825
190f68c5
ACO		 7826static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7827 struct intel_crtc_state *crtc_state)
79e53945 7828{
c7653199 7829 struct drm_device *dev = crtc->base.dev;
79e53945 7830 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7831 int refclk, num_connectors = 0;
c329a4ec
DV		 7832 intel_clock_t clock;
7833 bool ok;
7834 bool is_dsi = false;
5eddb70b 7835 struct intel_encoder *encoder;
d4906093 7836 const intel_limit_t *limit;
55bb9992 7837 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7838 struct drm_connector *connector;
55bb9992
ACO		 7839 struct drm_connector_state *connector_state;
7840 int i;
79e53945 7841
dd3cd74a
ACO		 7842 memset(&crtc_state->dpll_hw_state, 0,
7843 sizeof(crtc_state->dpll_hw_state));
7844
da3ced29 7845 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7846 if (connector_state->crtc != &crtc->base)
7847 continue;
7848
7849 encoder = to_intel_encoder(connector_state->best_encoder);
7850
5eddb70b 7851 switch (encoder->type) {
e9fd1c02
JN		 7852 case INTEL_OUTPUT_DSI:
7853 is_dsi = true;
7854 break;
6847d71b
PZ		 7855 default:
7856 break;
79e53945 7857 }
43565a06 7858
c751ce4f 7859 num_connectors++;
79e53945
JB		 7860 }
7861
f2335330 7862 if (is_dsi)
5b18e57c 7863 return 0;
f2335330 7864
190f68c5 7865 if (!crtc_state->clock_set) {
a93e255f 7866 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7867
e9fd1c02
JN		 7868 /*
7869 * Returns a set of divisors for the desired target clock with
7870 * the given refclk, or FALSE. The returned values represent
7871 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7872 * 2) / p1 / p2.
7873 */
a93e255f
ACO		 7874 limit = intel_limit(crtc_state, refclk);
7875 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7876 crtc_state->port_clock,
e9fd1c02 7877 refclk, NULL, &clock);
f2335330 7878 if (!ok) {
e9fd1c02
JN		 7879 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7880 return -EINVAL;
7881 }
79e53945 7882
f2335330 7883 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7884 crtc_state->dpll.n = clock.n;
7885 crtc_state->dpll.m1 = clock.m1;
7886 crtc_state->dpll.m2 = clock.m2;
7887 crtc_state->dpll.p1 = clock.p1;
7888 crtc_state->dpll.p2 = clock.p2;
f47709a9 7889 }
7026d4ac 7890
e9fd1c02 7891 if (IS_GEN2(dev)) {
c329a4ec 7892 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7893 num_connectors);
9d556c99 7894 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7895 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7896 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7897 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7898 } else {
c329a4ec 7899 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7900 num_connectors);
e9fd1c02 7901 }
79e53945 7902
c8f7a0db 7903 return 0;
f564048e
EA		 7904}
7905
2fa2fe9a 7906static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7907 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7908{
7909 struct drm_device *dev = crtc->base.dev;
7910 struct drm_i915_private *dev_priv = dev->dev_private;
7911 uint32_t tmp;
7912
dc9e7dec
VS		 7913 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7914 return;
7915
2fa2fe9a 7916 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7917 if (!(tmp & PFIT_ENABLE))
7918 return;
2fa2fe9a 7919
06922821 7920 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7921 if (INTEL_INFO(dev)->gen < 4) {
7922 if (crtc->pipe != PIPE_B)
7923 return;
2fa2fe9a
DV		 7924 } else {
7925 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7926 return;
7927 }
7928
06922821 7929 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7930 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7931 if (INTEL_INFO(dev)->gen < 5)
7932 pipe_config->gmch_pfit.lvds_border_bits =
7933 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7934}
7935
acbec814 7936static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7937 struct intel_crtc_state *pipe_config)
acbec814
JB		 7938{
7939 struct drm_device *dev = crtc->base.dev;
7940 struct drm_i915_private *dev_priv = dev->dev_private;
7941 int pipe = pipe_config->cpu_transcoder;
7942 intel_clock_t clock;
7943 u32 mdiv;
662c6ecb 7944 int refclk = 100000;
acbec814 7945
f573de5a
SK		 7946 /* In case of MIPI DPLL will not even be used */
7947 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7948 return;
7949
a580516d 7950 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7951 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7952 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7953
7954 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7955 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7956 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7957 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7958 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7959
dccbea3b 7960 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7961}
7962
5724dbd1
DL		 7963static void
7964i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7965 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7966{
7967 struct drm_device *dev = crtc->base.dev;
7968 struct drm_i915_private *dev_priv = dev->dev_private;
7969 u32 val, base, offset;
7970 int pipe = crtc->pipe, plane = crtc->plane;
7971 int fourcc, pixel_format;
6761dd31 7972 unsigned int aligned_height;
b113d5ee 7973 struct drm_framebuffer *fb;
1b842c89 7974 struct intel_framebuffer *intel_fb;
1ad292b5 7975
42a7b088
DL		 7976 val = I915_READ(DSPCNTR(plane));
7977 if (!(val & DISPLAY_PLANE_ENABLE))
7978 return;
7979
d9806c9f 7980 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7981 if (!intel_fb) {
1ad292b5
JB		 7982 DRM_DEBUG_KMS("failed to alloc fb\n");
7983 return;
7984 }
7985
1b842c89
DL		 7986 fb = &intel_fb->base;
7987
18c5247e
DV		 7988 if (INTEL_INFO(dev)->gen >= 4) {
7989 if (val & DISPPLANE_TILED) {
49af449b 7990 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7991 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7992 }
7993 }
1ad292b5
JB		 7994
7995 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7996 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7997 fb->pixel_format = fourcc;
7998 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7999
8000 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8001 if (plane_config->tiling)
1ad292b5
JB		 8002 offset = I915_READ(DSPTILEOFF(plane));
8003 else
8004 offset = I915_READ(DSPLINOFF(plane));
8005 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8006 } else {
8007 base = I915_READ(DSPADDR(plane));
8008 }
8009 plane_config->base = base;
8010
8011 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8012 fb->width = ((val >> 16) & 0xfff) + 1;
8013 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8014
8015 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8016 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8017
b113d5ee 8018 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8019 fb->pixel_format,
8020 fb->modifier[0]);
1ad292b5 8021
f37b5c2b 8022 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8023
2844a921
DL		 8024 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8025 pipe_name(pipe), plane, fb->width, fb->height,
8026 fb->bits_per_pixel, base, fb->pitches[0],
8027 plane_config->size);
1ad292b5 8028
2d14030b 8029 plane_config->fb = intel_fb;
1ad292b5
JB		 8030}
8031
70b23a98 8032static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8033 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8034{
8035 struct drm_device *dev = crtc->base.dev;
8036 struct drm_i915_private *dev_priv = dev->dev_private;
8037 int pipe = pipe_config->cpu_transcoder;
8038 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8039 intel_clock_t clock;
8040 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8041 int refclk = 100000;
8042
a580516d 8043 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8044 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8045 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8046 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8047 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8048 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8049
8050 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8051 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8052 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8053 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8054 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8055
dccbea3b 8056 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8057}
8058
0e8ffe1b 8059static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8060 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8061{
8062 struct drm_device *dev = crtc->base.dev;
8063 struct drm_i915_private *dev_priv = dev->dev_private;
8064 uint32_t tmp;
8065
f458ebbc
DV		 8066 if (!intel_display_power_is_enabled(dev_priv,
8067 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8068 return false;
8069
e143a21c 8070 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8071 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8072
0e8ffe1b
DV		 8073 tmp = I915_READ(PIPECONF(crtc->pipe));
8074 if (!(tmp & PIPECONF_ENABLE))
8075 return false;
8076
42571aef
VS		 8077 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8078 switch (tmp & PIPECONF_BPC_MASK) {
8079 case PIPECONF_6BPC:
8080 pipe_config->pipe_bpp = 18;
8081 break;
8082 case PIPECONF_8BPC:
8083 pipe_config->pipe_bpp = 24;
8084 break;
8085 case PIPECONF_10BPC:
8086 pipe_config->pipe_bpp = 30;
8087 break;
8088 default:
8089 break;
8090 }
8091 }
8092
b5a9fa09
DV		 8093 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8094 pipe_config->limited_color_range = true;
8095
282740f7
VS		 8096 if (INTEL_INFO(dev)->gen < 4)
8097 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8098
1bd1bd80
DV		 8099 intel_get_pipe_timings(crtc, pipe_config);
8100
2fa2fe9a
DV		 8101 i9xx_get_pfit_config(crtc, pipe_config);
8102
6c49f241
DV		 8103 if (INTEL_INFO(dev)->gen >= 4) {
8104 tmp = I915_READ(DPLL_MD(crtc->pipe));
8105 pipe_config->pixel_multiplier =
8106 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8107 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8108 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8109 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8110 tmp = I915_READ(DPLL(crtc->pipe));
8111 pipe_config->pixel_multiplier =
8112 ((tmp & SDVO_MULTIPLIER_MASK)
8113 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8114 } else {
8115 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8116 * port and will be fixed up in the encoder->get_config
8117 * function. */
8118 pipe_config->pixel_multiplier = 1;
8119 }
8bcc2795
DV		 8120 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8121 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8122 /*
8123 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8124 * on 830. Filter it out here so that we don't
8125 * report errors due to that.
8126 */
8127 if (IS_I830(dev))
8128 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8129
8bcc2795
DV		 8130 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8131 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8132 } else {
8133 /* Mask out read-only status bits. */
8134 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8135 DPLL_PORTC_READY_MASK |
8136 DPLL_PORTB_READY_MASK);
8bcc2795 8137 }
6c49f241 8138
70b23a98
VS		 8139 if (IS_CHERRYVIEW(dev))
8140 chv_crtc_clock_get(crtc, pipe_config);
8141 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8142 vlv_crtc_clock_get(crtc, pipe_config);
8143 else
8144 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8145
0e8ffe1b
DV		 8146 return true;
8147}
8148
dde86e2d 8149static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8150{
8151 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8152 struct intel_encoder *encoder;
74cfd7ac 8153 u32 val, final;
13d83a67 8154 bool has_lvds = false;
199e5d79 8155 bool has_cpu_edp = false;
199e5d79 8156 bool has_panel = false;
99eb6a01
KP		 8157 bool has_ck505 = false;
8158 bool can_ssc = false;
13d83a67
JB		 8159
8160 /* We need to take the global config into account */
b2784e15 8161 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8162 switch (encoder->type) {
8163 case INTEL_OUTPUT_LVDS:
8164 has_panel = true;
8165 has_lvds = true;
8166 break;
8167 case INTEL_OUTPUT_EDP:
8168 has_panel = true;
2de6905f 8169 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8170 has_cpu_edp = true;
8171 break;
6847d71b
PZ		 8172 default:
8173 break;
13d83a67
JB		 8174 }
8175 }
8176
99eb6a01 8177 if (HAS_PCH_IBX(dev)) {
41aa3448 8178 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8179 can_ssc = has_ck505;
8180 } else {
8181 has_ck505 = false;
8182 can_ssc = true;
8183 }
8184
2de6905f
ID		 8185 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8186 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8187
8188 /* Ironlake: try to setup display ref clock before DPLL
8189 * enabling. This is only under driver's control after
8190 * PCH B stepping, previous chipset stepping should be
8191 * ignoring this setting.
8192 */
74cfd7ac
CW		 8193 val = I915_READ(PCH_DREF_CONTROL);
8194
8195 /* As we must carefully and slowly disable/enable each source in turn,
8196 * compute the final state we want first and check if we need to
8197 * make any changes at all.
8198 */
8199 final = val;
8200 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8201 if (has_ck505)
8202 final |= DREF_NONSPREAD_CK505_ENABLE;
8203 else
8204 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8205
8206 final &= ~DREF_SSC_SOURCE_MASK;
8207 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8208 final &= ~DREF_SSC1_ENABLE;
8209
8210 if (has_panel) {
8211 final |= DREF_SSC_SOURCE_ENABLE;
8212
8213 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8214 final |= DREF_SSC1_ENABLE;
8215
8216 if (has_cpu_edp) {
8217 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8218 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8219 else
8220 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8221 } else
8222 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8223 } else {
8224 final |= DREF_SSC_SOURCE_DISABLE;
8225 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8226 }
8227
8228 if (final == val)
8229 return;
8230
13d83a67 8231 /* Always enable nonspread source */
74cfd7ac 8232 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8233
99eb6a01 8234 if (has_ck505)
74cfd7ac 8235 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8236 else
74cfd7ac 8237 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8238
199e5d79 8239 if (has_panel) {
74cfd7ac
CW		 8240 val &= ~DREF_SSC_SOURCE_MASK;
8241 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8242
199e5d79 8243 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8244 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8245 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8246 val |= DREF_SSC1_ENABLE;
e77166b5 8247 } else
74cfd7ac 8248 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8249
8250 /* Get SSC going before enabling the outputs */
74cfd7ac 8251 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8252 POSTING_READ(PCH_DREF_CONTROL);
8253 udelay(200);
8254
74cfd7ac 8255 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8256
8257 /* Enable CPU source on CPU attached eDP */
199e5d79 8258 if (has_cpu_edp) {
99eb6a01 8259 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8260 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8261 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8262 } else
74cfd7ac 8263 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8264 } else
74cfd7ac 8265 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8266
74cfd7ac 8267 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8268 POSTING_READ(PCH_DREF_CONTROL);
8269 udelay(200);
8270 } else {
8271 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8272
74cfd7ac 8273 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8274
8275 /* Turn off CPU output */
74cfd7ac 8276 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8277
74cfd7ac 8278 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8279 POSTING_READ(PCH_DREF_CONTROL);
8280 udelay(200);
8281
8282 /* Turn off the SSC source */
74cfd7ac
CW		 8283 val &= ~DREF_SSC_SOURCE_MASK;
8284 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8285
8286 /* Turn off SSC1 */
74cfd7ac 8287 val &= ~DREF_SSC1_ENABLE;
199e5d79 8288
74cfd7ac 8289 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8290 POSTING_READ(PCH_DREF_CONTROL);
8291 udelay(200);
8292 }
74cfd7ac
CW		 8293
8294 BUG_ON(val != final);
13d83a67
JB		 8295}
8296
f31f2d55 8297static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8298{
f31f2d55 8299 uint32_t tmp;
dde86e2d 8300
0ff066a9
PZ		 8301 tmp = I915_READ(SOUTH_CHICKEN2);
8302 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8303 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8304
0ff066a9
PZ		 8305 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8306 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8307 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8308
0ff066a9
PZ		 8309 tmp = I915_READ(SOUTH_CHICKEN2);
8310 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8311 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8312
0ff066a9
PZ		 8313 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8314 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8315 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8316}
8317
8318/* WaMPhyProgramming:hsw */
8319static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8320{
8321 uint32_t tmp;
dde86e2d
PZ		 8322
8323 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8324 tmp &= ~(0xFF << 24);
8325 tmp |= (0x12 << 24);
8326 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8327
dde86e2d
PZ		 8328 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8329 tmp |= (1 << 11);
8330 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8331
8332 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8333 tmp |= (1 << 11);
8334 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8335
dde86e2d
PZ		 8336 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8337 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8338 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8339
8340 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8341 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8342 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8343
0ff066a9
PZ		 8344 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8345 tmp &= ~(7 << 13);
8346 tmp |= (5 << 13);
8347 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8348
0ff066a9
PZ		 8349 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8350 tmp &= ~(7 << 13);
8351 tmp |= (5 << 13);
8352 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8353
8354 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8355 tmp &= ~0xFF;
8356 tmp |= 0x1C;
8357 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8358
8359 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8360 tmp &= ~0xFF;
8361 tmp |= 0x1C;
8362 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8363
8364 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8365 tmp &= ~(0xFF << 16);
8366 tmp |= (0x1C << 16);
8367 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8368
8369 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8370 tmp &= ~(0xFF << 16);
8371 tmp |= (0x1C << 16);
8372 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8373
0ff066a9
PZ		 8374 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8375 tmp |= (1 << 27);
8376 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8377
0ff066a9
PZ		 8378 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8379 tmp |= (1 << 27);
8380 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8381
0ff066a9
PZ		 8382 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8383 tmp &= ~(0xF << 28);
8384 tmp |= (4 << 28);
8385 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8386
0ff066a9
PZ		 8387 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8388 tmp &= ~(0xF << 28);
8389 tmp |= (4 << 28);
8390 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8391}
8392
2fa86a1f
PZ		 8393/* Implements 3 different sequences from BSpec chapter "Display iCLK
8394 * Programming" based on the parameters passed:
8395 * - Sequence to enable CLKOUT_DP
8396 * - Sequence to enable CLKOUT_DP without spread
8397 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8398 */
8399static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8400 bool with_fdi)
f31f2d55
PZ		 8401{
8402 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8403 uint32_t reg, tmp;
8404
8405 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8406 with_spread = true;
8407 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8408 with_fdi, "LP PCH doesn't have FDI\n"))
8409 with_fdi = false;
f31f2d55 8410
a580516d 8411 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8412
8413 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8414 tmp &= ~SBI_SSCCTL_DISABLE;
8415 tmp |= SBI_SSCCTL_PATHALT;
8416 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8417
8418 udelay(24);
8419
2fa86a1f
PZ		 8420 if (with_spread) {
8421 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8422 tmp &= ~SBI_SSCCTL_PATHALT;
8423 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8424
2fa86a1f
PZ		 8425 if (with_fdi) {
8426 lpt_reset_fdi_mphy(dev_priv);
8427 lpt_program_fdi_mphy(dev_priv);
8428 }
8429 }
dde86e2d 8430
2fa86a1f
PZ		 8431 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8432 SBI_GEN0 : SBI_DBUFF0;
8433 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8434 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8435 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8436
a580516d 8437 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8438}
8439
47701c3b
PZ		 8440/* Sequence to disable CLKOUT_DP */
8441static void lpt_disable_clkout_dp(struct drm_device *dev)
8442{
8443 struct drm_i915_private *dev_priv = dev->dev_private;
8444 uint32_t reg, tmp;
8445
a580516d 8446 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8447
8448 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8449 SBI_GEN0 : SBI_DBUFF0;
8450 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8451 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8452 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8453
8454 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8455 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8456 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8457 tmp |= SBI_SSCCTL_PATHALT;
8458 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8459 udelay(32);
8460 }
8461 tmp |= SBI_SSCCTL_DISABLE;
8462 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8463 }
8464
a580516d 8465 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8466}
8467
bf8fa3d3
PZ		 8468static void lpt_init_pch_refclk(struct drm_device *dev)
8469{
bf8fa3d3
PZ		 8470 struct intel_encoder *encoder;
8471 bool has_vga = false;
8472
b2784e15 8473 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8474 switch (encoder->type) {
8475 case INTEL_OUTPUT_ANALOG:
8476 has_vga = true;
8477 break;
6847d71b
PZ		 8478 default:
8479 break;
bf8fa3d3
PZ		 8480 }
8481 }
8482
47701c3b
PZ		 8483 if (has_vga)
8484 lpt_enable_clkout_dp(dev, true, true);
8485 else
8486 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8487}
8488
dde86e2d
PZ		 8489/*
8490 * Initialize reference clocks when the driver loads
8491 */
8492void intel_init_pch_refclk(struct drm_device *dev)
8493{
8494 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8495 ironlake_init_pch_refclk(dev);
8496 else if (HAS_PCH_LPT(dev))
8497 lpt_init_pch_refclk(dev);
8498}
8499
55bb9992 8500static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8501{
55bb9992 8502 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8503 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8504 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8505 struct drm_connector *connector;
55bb9992 8506 struct drm_connector_state *connector_state;
d9d444cb 8507 struct intel_encoder *encoder;
55bb9992 8508 int num_connectors = 0, i;
d9d444cb
JB		 8509 bool is_lvds = false;
8510
da3ced29 8511 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8512 if (connector_state->crtc != crtc_state->base.crtc)
8513 continue;
8514
8515 encoder = to_intel_encoder(connector_state->best_encoder);
8516
d9d444cb
JB		 8517 switch (encoder->type) {
8518 case INTEL_OUTPUT_LVDS:
8519 is_lvds = true;
8520 break;
6847d71b
PZ		 8521 default:
8522 break;
d9d444cb
JB		 8523 }
8524 num_connectors++;
8525 }
8526
8527 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8528 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8529 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8530 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8531 }
8532
8533 return 120000;
8534}
8535
6ff93609 8536static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8537{
c8203565 8538 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8540 int pipe = intel_crtc->pipe;
c8203565
PZ		 8541 uint32_t val;
8542
78114071 8543 val = 0;
c8203565 8544
6e3c9717 8545 switch (intel_crtc->config->pipe_bpp) {
c8203565 8546 case 18:
dfd07d72 8547 val |= PIPECONF_6BPC;
c8203565
PZ		 8548 break;
8549 case 24:
dfd07d72 8550 val |= PIPECONF_8BPC;
c8203565
PZ		 8551 break;
8552 case 30:
dfd07d72 8553 val |= PIPECONF_10BPC;
c8203565
PZ		 8554 break;
8555 case 36:
dfd07d72 8556 val |= PIPECONF_12BPC;
c8203565
PZ		 8557 break;
8558 default:
cc769b62
PZ		 8559 /* Case prevented by intel_choose_pipe_bpp_dither. */
8560 BUG();
c8203565
PZ		 8561 }
8562
6e3c9717 8563 if (intel_crtc->config->dither)
c8203565
PZ		 8564 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8565
6e3c9717 8566 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8567 val |= PIPECONF_INTERLACED_ILK;
8568 else
8569 val |= PIPECONF_PROGRESSIVE;
8570
6e3c9717 8571 if (intel_crtc->config->limited_color_range)
3685a8f3 8572 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8573
c8203565
PZ		 8574 I915_WRITE(PIPECONF(pipe), val);
8575 POSTING_READ(PIPECONF(pipe));
8576}
8577
86d3efce
VS		 8578/*
8579 * Set up the pipe CSC unit.
8580 *
8581 * Currently only full range RGB to limited range RGB conversion
8582 * is supported, but eventually this should handle various
8583 * RGB<->YCbCr scenarios as well.
8584 */
50f3b016 8585static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8586{
8587 struct drm_device *dev = crtc->dev;
8588 struct drm_i915_private *dev_priv = dev->dev_private;
8589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8590 int pipe = intel_crtc->pipe;
8591 uint16_t coeff = 0x7800; /* 1.0 */
8592
8593 /*
8594 * TODO: Check what kind of values actually come out of the pipe
8595 * with these coeff/postoff values and adjust to get the best
8596 * accuracy. Perhaps we even need to take the bpc value into
8597 * consideration.
8598 */
8599
6e3c9717 8600 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8601 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8602
8603 /*
8604 * GY/GU and RY/RU should be the other way around according
8605 * to BSpec, but reality doesn't agree. Just set them up in
8606 * a way that results in the correct picture.
8607 */
8608 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8609 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8610
8611 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8612 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8613
8614 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8615 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8616
8617 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8618 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8619 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8620
8621 if (INTEL_INFO(dev)->gen > 6) {
8622 uint16_t postoff = 0;
8623
6e3c9717 8624 if (intel_crtc->config->limited_color_range)
32cf0cb0 8625 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8626
8627 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8628 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8629 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8630
8631 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8632 } else {
8633 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8634
6e3c9717 8635 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8636 mode |= CSC_BLACK_SCREEN_OFFSET;
8637
8638 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8639 }
8640}
8641
6ff93609 8642static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8643{
756f85cf
PZ		 8644 struct drm_device *dev = crtc->dev;
8645 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8647 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8648 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8649 uint32_t val;
8650
3eff4faa 8651 val = 0;
ee2b0b38 8652
6e3c9717 8653 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8654 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8655
6e3c9717 8656 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8657 val |= PIPECONF_INTERLACED_ILK;
8658 else
8659 val |= PIPECONF_PROGRESSIVE;
8660
702e7a56
PZ		 8661 I915_WRITE(PIPECONF(cpu_transcoder), val);
8662 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8663
8664 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8665 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8666
3cdf122c 8667 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8668 val = 0;
8669
6e3c9717 8670 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8671 case 18:
8672 val |= PIPEMISC_DITHER_6_BPC;
8673 break;
8674 case 24:
8675 val |= PIPEMISC_DITHER_8_BPC;
8676 break;
8677 case 30:
8678 val |= PIPEMISC_DITHER_10_BPC;
8679 break;
8680 case 36:
8681 val |= PIPEMISC_DITHER_12_BPC;
8682 break;
8683 default:
8684 /* Case prevented by pipe_config_set_bpp. */
8685 BUG();
8686 }
8687
6e3c9717 8688 if (intel_crtc->config->dither)
756f85cf
PZ		 8689 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8690
8691 I915_WRITE(PIPEMISC(pipe), val);
8692 }
ee2b0b38
PZ		 8693}
8694
6591c6e4 8695static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8696 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8697 intel_clock_t *clock,
8698 bool *has_reduced_clock,
8699 intel_clock_t *reduced_clock)
8700{
8701 struct drm_device *dev = crtc->dev;
8702 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8703 int refclk;
d4906093 8704 const intel_limit_t *limit;
c329a4ec 8705 bool ret;
79e53945 8706
55bb9992 8707 refclk = ironlake_get_refclk(crtc_state);
79e53945 8708
d4906093
ML		 8709 /*
8710 * Returns a set of divisors for the desired target clock with the given
8711 * refclk, or FALSE. The returned values represent the clock equation:
8712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8713 */
a93e255f
ACO		 8714 limit = intel_limit(crtc_state, refclk);
8715 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8716 crtc_state->port_clock,
ee9300bb 8717 refclk, NULL, clock);
6591c6e4
PZ		 8718 if (!ret)
8719 return false;
cda4b7d3 8720
6591c6e4
PZ		 8721 return true;
8722}
8723
d4b1931c
PZ		 8724int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8725{
8726 /*
8727 * Account for spread spectrum to avoid
8728 * oversubscribing the link. Max center spread
8729 * is 2.5%; use 5% for safety's sake.
8730 */
8731 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8732 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8733}
8734
7429e9d4 8735static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8736{
7429e9d4 8737 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8738}
8739
de13a2e3 8740static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8741 struct intel_crtc_state *crtc_state,
7429e9d4 8742 u32 *fp,
9a7c7890 8743 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8744{
de13a2e3 8745 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8746 struct drm_device *dev = crtc->dev;
8747 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8748 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8749 struct drm_connector *connector;
55bb9992
ACO		 8750 struct drm_connector_state *connector_state;
8751 struct intel_encoder *encoder;
de13a2e3 8752 uint32_t dpll;
55bb9992 8753 int factor, num_connectors = 0, i;
09ede541 8754 bool is_lvds = false, is_sdvo = false;
79e53945 8755
da3ced29 8756 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8757 if (connector_state->crtc != crtc_state->base.crtc)
8758 continue;
8759
8760 encoder = to_intel_encoder(connector_state->best_encoder);
8761
8762 switch (encoder->type) {
79e53945
JB		 8763 case INTEL_OUTPUT_LVDS:
8764 is_lvds = true;
8765 break;
8766 case INTEL_OUTPUT_SDVO:
7d57382e 8767 case INTEL_OUTPUT_HDMI:
79e53945 8768 is_sdvo = true;
79e53945 8769 break;
6847d71b
PZ		 8770 default:
8771 break;
79e53945 8772 }
43565a06 8773
c751ce4f 8774 num_connectors++;
79e53945 8775 }
79e53945 8776
c1858123 8777 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8778 factor = 21;
8779 if (is_lvds) {
8780 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8781 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8782 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8783 factor = 25;
190f68c5 8784 } else if (crtc_state->sdvo_tv_clock)
8febb297 8785 factor = 20;
c1858123 8786
190f68c5 8787 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8788 *fp |= FP_CB_TUNE;
2c07245f 8789
9a7c7890
DV		 8790 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8791 *fp2 |= FP_CB_TUNE;
8792
5eddb70b 8793 dpll = 0;
2c07245f 8794
a07d6787
EA		 8795 if (is_lvds)
8796 dpll |= DPLLB_MODE_LVDS;
8797 else
8798 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8799
190f68c5 8800 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8801 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8802
8803 if (is_sdvo)
4a33e48d 8804 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8805 if (crtc_state->has_dp_encoder)
4a33e48d 8806 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8807
a07d6787 8808 /* compute bitmask from p1 value */
190f68c5 8809 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8810 /* also FPA1 */
190f68c5 8811 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8812
190f68c5 8813 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8814 case 5:
8815 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8816 break;
8817 case 7:
8818 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8819 break;
8820 case 10:
8821 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8822 break;
8823 case 14:
8824 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8825 break;
79e53945
JB		 8826 }
8827
b4c09f3b 8828 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8829 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8830 else
8831 dpll |= PLL_REF_INPUT_DREFCLK;
8832
959e16d6 8833 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8834}
8835
190f68c5
ACO		 8836static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8837 struct intel_crtc_state *crtc_state)
de13a2e3 8838{
c7653199 8839 struct drm_device *dev = crtc->base.dev;
de13a2e3 8840 intel_clock_t clock, reduced_clock;
cbbab5bd 8841 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8842 bool ok, has_reduced_clock = false;
8b47047b 8843 bool is_lvds = false;
e2b78267 8844 struct intel_shared_dpll *pll;
de13a2e3 8845
dd3cd74a
ACO		 8846 memset(&crtc_state->dpll_hw_state, 0,
8847 sizeof(crtc_state->dpll_hw_state));
8848
409ee761 8849 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8850
5dc5298b
PZ		 8851 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8852 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8853
190f68c5 8854 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8855 &has_reduced_clock, &reduced_clock);
190f68c5 8856 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8857 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8858 return -EINVAL;
79e53945 8859 }
f47709a9 8860 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8861 if (!crtc_state->clock_set) {
8862 crtc_state->dpll.n = clock.n;
8863 crtc_state->dpll.m1 = clock.m1;
8864 crtc_state->dpll.m2 = clock.m2;
8865 crtc_state->dpll.p1 = clock.p1;
8866 crtc_state->dpll.p2 = clock.p2;
f47709a9 8867 }
79e53945 8868
5dc5298b 8869 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8870 if (crtc_state->has_pch_encoder) {
8871 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8872 if (has_reduced_clock)
7429e9d4 8873 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8874
190f68c5 8875 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8876 &fp, &reduced_clock,
8877 has_reduced_clock ? &fp2 : NULL);
8878
190f68c5
ACO		 8879 crtc_state->dpll_hw_state.dpll = dpll;
8880 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8881 if (has_reduced_clock)
190f68c5 8882 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8883 else
190f68c5 8884 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8885
190f68c5 8886 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8887 if (pll == NULL) {
84f44ce7 8888 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8889 pipe_name(crtc->pipe));
4b645f14
JB		 8890 return -EINVAL;
8891 }
3fb37703 8892 }
79e53945 8893
ab585dea 8894 if (is_lvds && has_reduced_clock)
c7653199 8895 crtc->lowfreq_avail = true;
bcd644e0 8896 else
c7653199 8897 crtc->lowfreq_avail = false;
e2b78267 8898
c8f7a0db 8899 return 0;
79e53945
JB		 8900}
8901
eb14cb74
VS		 8902static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8903 struct intel_link_m_n *m_n)
8904{
8905 struct drm_device *dev = crtc->base.dev;
8906 struct drm_i915_private *dev_priv = dev->dev_private;
8907 enum pipe pipe = crtc->pipe;
8908
8909 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8910 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8911 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8912 & ~TU_SIZE_MASK;
8913 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8914 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8915 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8916}
8917
8918static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8919 enum transcoder transcoder,
b95af8be
VK		 8920 struct intel_link_m_n *m_n,
8921 struct intel_link_m_n *m2_n2)
72419203
DV		 8922{
8923 struct drm_device *dev = crtc->base.dev;
8924 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8925 enum pipe pipe = crtc->pipe;
72419203 8926
eb14cb74
VS		 8927 if (INTEL_INFO(dev)->gen >= 5) {
8928 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8929 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8930 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8931 & ~TU_SIZE_MASK;
8932 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8933 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8934 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8935 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8936 * gen < 8) and if DRRS is supported (to make sure the
8937 * registers are not unnecessarily read).
8938 */
8939 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8940 crtc->config->has_drrs) {
b95af8be
VK		 8941 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8942 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8943 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8944 & ~TU_SIZE_MASK;
8945 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8946 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8947 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8948 }
eb14cb74
VS		 8949 } else {
8950 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8951 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8952 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8953 & ~TU_SIZE_MASK;
8954 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8955 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8956 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8957 }
8958}
8959
8960void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8961 struct intel_crtc_state *pipe_config)
eb14cb74 8962{
681a8504 8963 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8964 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8965 else
8966 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8967 &pipe_config->dp_m_n,
8968 &pipe_config->dp_m2_n2);
eb14cb74 8969}
72419203 8970
eb14cb74 8971static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8972 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8973{
8974 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8975 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8976}
8977
bd2e244f 8978static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8979 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8980{
8981 struct drm_device *dev = crtc->base.dev;
8982 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8983 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8984 uint32_t ps_ctrl = 0;
8985 int id = -1;
8986 int i;
bd2e244f 8987
a1b2278e
CK		 8988 /* find scaler attached to this pipe */
8989 for (i = 0; i < crtc->num_scalers; i++) {
8990 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8991 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8992 id = i;
8993 pipe_config->pch_pfit.enabled = true;
8994 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8995 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8996 break;
8997 }
8998 }
bd2e244f 8999
a1b2278e
CK		 9000 scaler_state->scaler_id = id;
9001 if (id >= 0) {
9002 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9003 } else {
9004 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9005 }
9006}
9007
5724dbd1
DL		 9008static void
9009skylake_get_initial_plane_config(struct intel_crtc *crtc,
9010 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9011{
9012 struct drm_device *dev = crtc->base.dev;
9013 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9014 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9015 int pipe = crtc->pipe;
9016 int fourcc, pixel_format;
6761dd31 9017 unsigned int aligned_height;
bc8d7dff 9018 struct drm_framebuffer *fb;
1b842c89 9019 struct intel_framebuffer *intel_fb;
bc8d7dff 9020
d9806c9f 9021 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9022 if (!intel_fb) {
bc8d7dff
DL		 9023 DRM_DEBUG_KMS("failed to alloc fb\n");
9024 return;
9025 }
9026
1b842c89
DL		 9027 fb = &intel_fb->base;
9028
bc8d7dff 9029 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9030 if (!(val & PLANE_CTL_ENABLE))
9031 goto error;
9032
bc8d7dff
DL		 9033 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9034 fourcc = skl_format_to_fourcc(pixel_format,
9035 val & PLANE_CTL_ORDER_RGBX,
9036 val & PLANE_CTL_ALPHA_MASK);
9037 fb->pixel_format = fourcc;
9038 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9039
40f46283
DL		 9040 tiling = val & PLANE_CTL_TILED_MASK;
9041 switch (tiling) {
9042 case PLANE_CTL_TILED_LINEAR:
9043 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9044 break;
9045 case PLANE_CTL_TILED_X:
9046 plane_config->tiling = I915_TILING_X;
9047 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9048 break;
9049 case PLANE_CTL_TILED_Y:
9050 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9051 break;
9052 case PLANE_CTL_TILED_YF:
9053 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9054 break;
9055 default:
9056 MISSING_CASE(tiling);
9057 goto error;
9058 }
9059
bc8d7dff
DL		 9060 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9061 plane_config->base = base;
9062
9063 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9064
9065 val = I915_READ(PLANE_SIZE(pipe, 0));
9066 fb->height = ((val >> 16) & 0xfff) + 1;
9067 fb->width = ((val >> 0) & 0x1fff) + 1;
9068
9069 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9070 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9071 fb->pixel_format);
bc8d7dff
DL		 9072 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9073
9074 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9075 fb->pixel_format,
9076 fb->modifier[0]);
bc8d7dff 9077
f37b5c2b 9078 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9079
9080 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9081 pipe_name(pipe), fb->width, fb->height,
9082 fb->bits_per_pixel, base, fb->pitches[0],
9083 plane_config->size);
9084
2d14030b 9085 plane_config->fb = intel_fb;
bc8d7dff
DL		 9086 return;
9087
9088error:
9089 kfree(fb);
9090}
9091
2fa2fe9a 9092static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9093 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9094{
9095 struct drm_device *dev = crtc->base.dev;
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097 uint32_t tmp;
9098
9099 tmp = I915_READ(PF_CTL(crtc->pipe));
9100
9101 if (tmp & PF_ENABLE) {
fd4daa9c 9102 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9103 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9104 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9105
9106 /* We currently do not free assignements of panel fitters on
9107 * ivb/hsw (since we don't use the higher upscaling modes which
9108 * differentiates them) so just WARN about this case for now. */
9109 if (IS_GEN7(dev)) {
9110 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9111 PF_PIPE_SEL_IVB(crtc->pipe));
9112 }
2fa2fe9a 9113 }
79e53945
JB		 9114}
9115
5724dbd1
DL		 9116static void
9117ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9118 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9119{
9120 struct drm_device *dev = crtc->base.dev;
9121 struct drm_i915_private *dev_priv = dev->dev_private;
9122 u32 val, base, offset;
aeee5a49 9123 int pipe = crtc->pipe;
4c6baa59 9124 int fourcc, pixel_format;
6761dd31 9125 unsigned int aligned_height;
b113d5ee 9126 struct drm_framebuffer *fb;
1b842c89 9127 struct intel_framebuffer *intel_fb;
4c6baa59 9128
42a7b088
DL		 9129 val = I915_READ(DSPCNTR(pipe));
9130 if (!(val & DISPLAY_PLANE_ENABLE))
9131 return;
9132
d9806c9f 9133 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9134 if (!intel_fb) {
4c6baa59
JB		 9135 DRM_DEBUG_KMS("failed to alloc fb\n");
9136 return;
9137 }
9138
1b842c89
DL		 9139 fb = &intel_fb->base;
9140
18c5247e
DV		 9141 if (INTEL_INFO(dev)->gen >= 4) {
9142 if (val & DISPPLANE_TILED) {
49af449b 9143 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9144 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9145 }
9146 }
4c6baa59
JB		 9147
9148 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9149 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9150 fb->pixel_format = fourcc;
9151 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9152
aeee5a49 9153 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9154 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9155 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9156 } else {
49af449b 9157 if (plane_config->tiling)
aeee5a49 9158 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9159 else
aeee5a49 9160 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9161 }
9162 plane_config->base = base;
9163
9164 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9165 fb->width = ((val >> 16) & 0xfff) + 1;
9166 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9167
9168 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9169 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9170
b113d5ee 9171 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9172 fb->pixel_format,
9173 fb->modifier[0]);
4c6baa59 9174
f37b5c2b 9175 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9176
2844a921
DL		 9177 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9178 pipe_name(pipe), fb->width, fb->height,
9179 fb->bits_per_pixel, base, fb->pitches[0],
9180 plane_config->size);
b113d5ee 9181
2d14030b 9182 plane_config->fb = intel_fb;
4c6baa59
JB		 9183}
9184
0e8ffe1b 9185static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9186 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9187{
9188 struct drm_device *dev = crtc->base.dev;
9189 struct drm_i915_private *dev_priv = dev->dev_private;
9190 uint32_t tmp;
9191
f458ebbc
DV		 9192 if (!intel_display_power_is_enabled(dev_priv,
9193 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9194 return false;
9195
e143a21c 9196 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9197 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9198
0e8ffe1b
DV		 9199 tmp = I915_READ(PIPECONF(crtc->pipe));
9200 if (!(tmp & PIPECONF_ENABLE))
9201 return false;
9202
42571aef
VS		 9203 switch (tmp & PIPECONF_BPC_MASK) {
9204 case PIPECONF_6BPC:
9205 pipe_config->pipe_bpp = 18;
9206 break;
9207 case PIPECONF_8BPC:
9208 pipe_config->pipe_bpp = 24;
9209 break;
9210 case PIPECONF_10BPC:
9211 pipe_config->pipe_bpp = 30;
9212 break;
9213 case PIPECONF_12BPC:
9214 pipe_config->pipe_bpp = 36;
9215 break;
9216 default:
9217 break;
9218 }
9219
b5a9fa09
DV		 9220 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9221 pipe_config->limited_color_range = true;
9222
ab9412ba 9223 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9224 struct intel_shared_dpll *pll;
9225
88adfff1
DV		 9226 pipe_config->has_pch_encoder = true;
9227
627eb5a3
DV		 9228 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9229 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9230 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9231
9232 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9233
c0d43d62 9234 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9235 pipe_config->shared_dpll =
9236 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9237 } else {
9238 tmp = I915_READ(PCH_DPLL_SEL);
9239 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9240 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9241 else
9242 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9243 }
66e985c0
DV		 9244
9245 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9246
9247 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9248 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9249
9250 tmp = pipe_config->dpll_hw_state.dpll;
9251 pipe_config->pixel_multiplier =
9252 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9253 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9254
9255 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9256 } else {
9257 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9258 }
9259
1bd1bd80
DV		 9260 intel_get_pipe_timings(crtc, pipe_config);
9261
2fa2fe9a
DV		 9262 ironlake_get_pfit_config(crtc, pipe_config);
9263
0e8ffe1b
DV		 9264 return true;
9265}
9266
be256dc7
PZ		 9267static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9268{
9269 struct drm_device *dev = dev_priv->dev;
be256dc7 9270 struct intel_crtc *crtc;
be256dc7 9271
d3fcc808 9272 for_each_intel_crtc(dev, crtc)
e2c719b7 9273 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9274 pipe_name(crtc->pipe));
9275
e2c719b7
RC		 9276 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9277 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9278 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9279 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9280 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9281 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9282 "CPU PWM1 enabled\n");
c5107b87 9283 if (IS_HASWELL(dev))
e2c719b7 9284 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9285 "CPU PWM2 enabled\n");
e2c719b7 9286 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9287 "PCH PWM1 enabled\n");
e2c719b7 9288 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9289 "Utility pin enabled\n");
e2c719b7 9290 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9291
9926ada1
PZ		 9292 /*
9293 * In theory we can still leave IRQs enabled, as long as only the HPD
9294 * interrupts remain enabled. We used to check for that, but since it's
9295 * gen-specific and since we only disable LCPLL after we fully disable
9296 * the interrupts, the check below should be enough.
9297 */
e2c719b7 9298 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9299}
9300
9ccd5aeb
PZ		 9301static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9302{
9303 struct drm_device *dev = dev_priv->dev;
9304
9305 if (IS_HASWELL(dev))
9306 return I915_READ(D_COMP_HSW);
9307 else
9308 return I915_READ(D_COMP_BDW);
9309}
9310
3c4c9b81
PZ		 9311static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9312{
9313 struct drm_device *dev = dev_priv->dev;
9314
9315 if (IS_HASWELL(dev)) {
9316 mutex_lock(&dev_priv->rps.hw_lock);
9317 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9318 val))
f475dadf 9319 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9320 mutex_unlock(&dev_priv->rps.hw_lock);
9321 } else {
9ccd5aeb
PZ		 9322 I915_WRITE(D_COMP_BDW, val);
9323 POSTING_READ(D_COMP_BDW);
3c4c9b81 9324 }
be256dc7
PZ		 9325}
9326
9327/*
9328 * This function implements pieces of two sequences from BSpec:
9329 * - Sequence for display software to disable LCPLL
9330 * - Sequence for display software to allow package C8+
9331 * The steps implemented here are just the steps that actually touch the LCPLL
9332 * register. Callers should take care of disabling all the display engine
9333 * functions, doing the mode unset, fixing interrupts, etc.
9334 */
6ff58d53
PZ		 9335static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9336 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9337{
9338 uint32_t val;
9339
9340 assert_can_disable_lcpll(dev_priv);
9341
9342 val = I915_READ(LCPLL_CTL);
9343
9344 if (switch_to_fclk) {
9345 val |= LCPLL_CD_SOURCE_FCLK;
9346 I915_WRITE(LCPLL_CTL, val);
9347
9348 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9349 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9350 DRM_ERROR("Switching to FCLK failed\n");
9351
9352 val = I915_READ(LCPLL_CTL);
9353 }
9354
9355 val |= LCPLL_PLL_DISABLE;
9356 I915_WRITE(LCPLL_CTL, val);
9357 POSTING_READ(LCPLL_CTL);
9358
9359 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9360 DRM_ERROR("LCPLL still locked\n");
9361
9ccd5aeb 9362 val = hsw_read_dcomp(dev_priv);
be256dc7 9363 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9364 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9365 ndelay(100);
9366
9ccd5aeb
PZ		 9367 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9368 1))
be256dc7
PZ		 9369 DRM_ERROR("D_COMP RCOMP still in progress\n");
9370
9371 if (allow_power_down) {
9372 val = I915_READ(LCPLL_CTL);
9373 val |= LCPLL_POWER_DOWN_ALLOW;
9374 I915_WRITE(LCPLL_CTL, val);
9375 POSTING_READ(LCPLL_CTL);
9376 }
9377}
9378
9379/*
9380 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9381 * source.
9382 */
6ff58d53 9383static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9384{
9385 uint32_t val;
9386
9387 val = I915_READ(LCPLL_CTL);
9388
9389 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9390 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9391 return;
9392
a8a8bd54
PZ		 9393 /*
9394 * Make sure we're not on PC8 state before disabling PC8, otherwise
9395 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9396 */
59bad947 9397 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9398
be256dc7
PZ		 9399 if (val & LCPLL_POWER_DOWN_ALLOW) {
9400 val &= ~LCPLL_POWER_DOWN_ALLOW;
9401 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9402 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9403 }
9404
9ccd5aeb 9405 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9406 val |= D_COMP_COMP_FORCE;
9407 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9408 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9409
9410 val = I915_READ(LCPLL_CTL);
9411 val &= ~LCPLL_PLL_DISABLE;
9412 I915_WRITE(LCPLL_CTL, val);
9413
9414 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9415 DRM_ERROR("LCPLL not locked yet\n");
9416
9417 if (val & LCPLL_CD_SOURCE_FCLK) {
9418 val = I915_READ(LCPLL_CTL);
9419 val &= ~LCPLL_CD_SOURCE_FCLK;
9420 I915_WRITE(LCPLL_CTL, val);
9421
9422 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9423 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9424 DRM_ERROR("Switching back to LCPLL failed\n");
9425 }
215733fa 9426
59bad947 9427 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9428 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9429}
9430
765dab67
PZ		 9431/*
9432 * Package states C8 and deeper are really deep PC states that can only be
9433 * reached when all the devices on the system allow it, so even if the graphics
9434 * device allows PC8+, it doesn't mean the system will actually get to these
9435 * states. Our driver only allows PC8+ when going into runtime PM.
9436 *
9437 * The requirements for PC8+ are that all the outputs are disabled, the power
9438 * well is disabled and most interrupts are disabled, and these are also
9439 * requirements for runtime PM. When these conditions are met, we manually do
9440 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9441 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9442 * hang the machine.
9443 *
9444 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9445 * the state of some registers, so when we come back from PC8+ we need to
9446 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9447 * need to take care of the registers kept by RC6. Notice that this happens even
9448 * if we don't put the device in PCI D3 state (which is what currently happens
9449 * because of the runtime PM support).
9450 *
9451 * For more, read "Display Sequences for Package C8" on the hardware
9452 * documentation.
9453 */
a14cb6fc 9454void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9455{
c67a470b
PZ		 9456 struct drm_device *dev = dev_priv->dev;
9457 uint32_t val;
9458
c67a470b
PZ		 9459 DRM_DEBUG_KMS("Enabling package C8+\n");
9460
c67a470b
PZ		 9461 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9462 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9463 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9464 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9465 }
9466
9467 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9468 hsw_disable_lcpll(dev_priv, true, true);
9469}
9470
a14cb6fc 9471void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9472{
9473 struct drm_device *dev = dev_priv->dev;
9474 uint32_t val;
9475
c67a470b
PZ		 9476 DRM_DEBUG_KMS("Disabling package C8+\n");
9477
9478 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9479 lpt_init_pch_refclk(dev);
9480
9481 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9482 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9483 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9484 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9485 }
9486
9487 intel_prepare_ddi(dev);
c67a470b
PZ		 9488}
9489
27c329ed 9490static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9491{
a821fc46 9492 struct drm_device *dev = old_state->dev;
27c329ed 9493 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9494
27c329ed 9495 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9496}
9497
b432e5cf 9498/* compute the max rate for new configuration */
27c329ed 9499static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9500{
b432e5cf 9501 struct intel_crtc *intel_crtc;
27c329ed 9502 struct intel_crtc_state *crtc_state;
b432e5cf 9503 int max_pixel_rate = 0;
b432e5cf 9504
27c329ed
ML		 9505 for_each_intel_crtc(state->dev, intel_crtc) {
9506 int pixel_rate;
9507
9508 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9509 if (IS_ERR(crtc_state))
9510 return PTR_ERR(crtc_state);
9511
9512 if (!crtc_state->base.enable)
b432e5cf
VS		 9513 continue;
9514
27c329ed 9515 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9516
9517 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9518 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9519 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9520
9521 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9522 }
9523
9524 return max_pixel_rate;
9525}
9526
9527static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9528{
9529 struct drm_i915_private *dev_priv = dev->dev_private;
9530 uint32_t val, data;
9531 int ret;
9532
9533 if (WARN((I915_READ(LCPLL_CTL) &
9534 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9535 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9536 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9537 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9538 "trying to change cdclk frequency with cdclk not enabled\n"))
9539 return;
9540
9541 mutex_lock(&dev_priv->rps.hw_lock);
9542 ret = sandybridge_pcode_write(dev_priv,
9543 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9544 mutex_unlock(&dev_priv->rps.hw_lock);
9545 if (ret) {
9546 DRM_ERROR("failed to inform pcode about cdclk change\n");
9547 return;
9548 }
9549
9550 val = I915_READ(LCPLL_CTL);
9551 val |= LCPLL_CD_SOURCE_FCLK;
9552 I915_WRITE(LCPLL_CTL, val);
9553
9554 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9555 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9556 DRM_ERROR("Switching to FCLK failed\n");
9557
9558 val = I915_READ(LCPLL_CTL);
9559 val &= ~LCPLL_CLK_FREQ_MASK;
9560
9561 switch (cdclk) {
9562 case 450000:
9563 val |= LCPLL_CLK_FREQ_450;
9564 data = 0;
9565 break;
9566 case 540000:
9567 val |= LCPLL_CLK_FREQ_54O_BDW;
9568 data = 1;
9569 break;
9570 case 337500:
9571 val |= LCPLL_CLK_FREQ_337_5_BDW;
9572 data = 2;
9573 break;
9574 case 675000:
9575 val |= LCPLL_CLK_FREQ_675_BDW;
9576 data = 3;
9577 break;
9578 default:
9579 WARN(1, "invalid cdclk frequency\n");
9580 return;
9581 }
9582
9583 I915_WRITE(LCPLL_CTL, val);
9584
9585 val = I915_READ(LCPLL_CTL);
9586 val &= ~LCPLL_CD_SOURCE_FCLK;
9587 I915_WRITE(LCPLL_CTL, val);
9588
9589 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9590 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9591 DRM_ERROR("Switching back to LCPLL failed\n");
9592
9593 mutex_lock(&dev_priv->rps.hw_lock);
9594 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9595 mutex_unlock(&dev_priv->rps.hw_lock);
9596
9597 intel_update_cdclk(dev);
9598
9599 WARN(cdclk != dev_priv->cdclk_freq,
9600 "cdclk requested %d kHz but got %d kHz\n",
9601 cdclk, dev_priv->cdclk_freq);
9602}
9603
27c329ed 9604static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9605{
27c329ed
ML		 9606 struct drm_i915_private *dev_priv = to_i915(state->dev);
9607 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9608 int cdclk;
9609
9610 /*
9611 * FIXME should also account for plane ratio
9612 * once 64bpp pixel formats are supported.
9613 */
27c329ed 9614 if (max_pixclk > 540000)
b432e5cf 9615 cdclk = 675000;
27c329ed 9616 else if (max_pixclk > 450000)
b432e5cf 9617 cdclk = 540000;
27c329ed 9618 else if (max_pixclk > 337500)
b432e5cf
VS		 9619 cdclk = 450000;
9620 else
9621 cdclk = 337500;
9622
9623 /*
9624 * FIXME move the cdclk caclulation to
9625 * compute_config() so we can fail gracegully.
9626 */
9627 if (cdclk > dev_priv->max_cdclk_freq) {
9628 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9629 cdclk, dev_priv->max_cdclk_freq);
9630 cdclk = dev_priv->max_cdclk_freq;
9631 }
9632
27c329ed 9633 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9634
9635 return 0;
9636}
9637
27c329ed 9638static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9639{
27c329ed
ML		 9640 struct drm_device *dev = old_state->dev;
9641 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9642
27c329ed 9643 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9644}
9645
190f68c5
ACO		 9646static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9647 struct intel_crtc_state *crtc_state)
09b4ddf9 9648{
190f68c5 9649 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9650 return -EINVAL;
716c2e55 9651
c7653199 9652 crtc->lowfreq_avail = false;
644cef34 9653
c8f7a0db 9654 return 0;
79e53945
JB		 9655}
9656
3760b59c
S		 9657static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9658 enum port port,
9659 struct intel_crtc_state *pipe_config)
9660{
9661 switch (port) {
9662 case PORT_A:
9663 pipe_config->ddi_pll_sel = SKL_DPLL0;
9664 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9665 break;
9666 case PORT_B:
9667 pipe_config->ddi_pll_sel = SKL_DPLL1;
9668 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9669 break;
9670 case PORT_C:
9671 pipe_config->ddi_pll_sel = SKL_DPLL2;
9672 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9673 break;
9674 default:
9675 DRM_ERROR("Incorrect port type\n");
9676 }
9677}
9678
96b7dfb7
S		 9679static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9680 enum port port,
5cec258b 9681 struct intel_crtc_state *pipe_config)
96b7dfb7 9682{
3148ade7 9683 u32 temp, dpll_ctl1;
96b7dfb7
S		 9684
9685 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9686 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9687
9688 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9689 case SKL_DPLL0:
9690 /*
9691 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9692 * of the shared DPLL framework and thus needs to be read out
9693 * separately
9694 */
9695 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9696 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9697 break;
96b7dfb7
S		 9698 case SKL_DPLL1:
9699 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9700 break;
9701 case SKL_DPLL2:
9702 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9703 break;
9704 case SKL_DPLL3:
9705 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9706 break;
96b7dfb7
S		 9707 }
9708}
9709
7d2c8175
DL		 9710static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9711 enum port port,
5cec258b 9712 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9713{
9714 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9715
9716 switch (pipe_config->ddi_pll_sel) {
9717 case PORT_CLK_SEL_WRPLL1:
9718 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9719 break;
9720 case PORT_CLK_SEL_WRPLL2:
9721 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9722 break;
9723 }
9724}
9725
26804afd 9726static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9727 struct intel_crtc_state *pipe_config)
26804afd
DV		 9728{
9729 struct drm_device *dev = crtc->base.dev;
9730 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9731 struct intel_shared_dpll *pll;
26804afd
DV		 9732 enum port port;
9733 uint32_t tmp;
9734
9735 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9736
9737 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9738
96b7dfb7
S		 9739 if (IS_SKYLAKE(dev))
9740 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9741 else if (IS_BROXTON(dev))
9742 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9743 else
9744 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9745
d452c5b6
DV		 9746 if (pipe_config->shared_dpll >= 0) {
9747 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9748
9749 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9750 &pipe_config->dpll_hw_state));
9751 }
9752
26804afd
DV		 9753 /*
9754 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9755 * DDI E. So just check whether this pipe is wired to DDI E and whether
9756 * the PCH transcoder is on.
9757 */
ca370455
DL		 9758 if (INTEL_INFO(dev)->gen < 9 &&
9759 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9760 pipe_config->has_pch_encoder = true;
9761
9762 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9763 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9764 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9765
9766 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9767 }
9768}
9769
0e8ffe1b 9770static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9771 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9772{
9773 struct drm_device *dev = crtc->base.dev;
9774 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9775 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9776 uint32_t tmp;
9777
f458ebbc 9778 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9779 POWER_DOMAIN_PIPE(crtc->pipe)))
9780 return false;
9781
e143a21c 9782 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9783 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9784
eccb140b
DV		 9785 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9786 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9787 enum pipe trans_edp_pipe;
9788 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9789 default:
9790 WARN(1, "unknown pipe linked to edp transcoder\n");
9791 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9792 case TRANS_DDI_EDP_INPUT_A_ON:
9793 trans_edp_pipe = PIPE_A;
9794 break;
9795 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9796 trans_edp_pipe = PIPE_B;
9797 break;
9798 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9799 trans_edp_pipe = PIPE_C;
9800 break;
9801 }
9802
9803 if (trans_edp_pipe == crtc->pipe)
9804 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9805 }
9806
f458ebbc 9807 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9808 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9809 return false;
9810
eccb140b 9811 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9812 if (!(tmp & PIPECONF_ENABLE))
9813 return false;
9814
26804afd 9815 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9816
1bd1bd80
DV		 9817 intel_get_pipe_timings(crtc, pipe_config);
9818
a1b2278e
CK		 9819 if (INTEL_INFO(dev)->gen >= 9) {
9820 skl_init_scalers(dev, crtc, pipe_config);
9821 }
9822
2fa2fe9a 9823 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9824
9825 if (INTEL_INFO(dev)->gen >= 9) {
9826 pipe_config->scaler_state.scaler_id = -1;
9827 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9828 }
9829
bd2e244f 9830 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9831 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9832 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9833 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9834 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9835 else
9836 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9837 }
88adfff1 9838
e59150dc
JB		 9839 if (IS_HASWELL(dev))
9840 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9841 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9842
ebb69c95
CT		 9843 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9844 pipe_config->pixel_multiplier =
9845 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9846 } else {
9847 pipe_config->pixel_multiplier = 1;
9848 }
6c49f241 9849
0e8ffe1b
DV		 9850 return true;
9851}
9852
560b85bb
CW		 9853static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9854{
9855 struct drm_device *dev = crtc->dev;
9856 struct drm_i915_private *dev_priv = dev->dev_private;
9857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9858 uint32_t cntl = 0, size = 0;
560b85bb 9859
dc41c154 9860 if (base) {
3dd512fb
MR		 9861 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9862 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9863 unsigned int stride = roundup_pow_of_two(width) * 4;
9864
9865 switch (stride) {
9866 default:
9867 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9868 width, stride);
9869 stride = 256;
9870 /* fallthrough */
9871 case 256:
9872 case 512:
9873 case 1024:
9874 case 2048:
9875 break;
4b0e333e
CW		 9876 }
9877
dc41c154
VS		 9878 cntl |= CURSOR_ENABLE |
9879 CURSOR_GAMMA_ENABLE |
9880 CURSOR_FORMAT_ARGB |
9881 CURSOR_STRIDE(stride);
9882
9883 size = (height << 12) | width;
4b0e333e 9884 }
560b85bb 9885
dc41c154
VS		 9886 if (intel_crtc->cursor_cntl != 0 &&
9887 (intel_crtc->cursor_base != base ||
9888 intel_crtc->cursor_size != size ||
9889 intel_crtc->cursor_cntl != cntl)) {
9890 /* On these chipsets we can only modify the base/size/stride
9891 * whilst the cursor is disabled.
9892 */
9893 I915_WRITE(_CURACNTR, 0);
4b0e333e 9894 POSTING_READ(_CURACNTR);
dc41c154 9895 intel_crtc->cursor_cntl = 0;
4b0e333e 9896 }
560b85bb 9897
99d1f387 9898 if (intel_crtc->cursor_base != base) {
9db4a9c7 9899 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9900 intel_crtc->cursor_base = base;
9901 }
4726e0b0 9902
dc41c154
VS		 9903 if (intel_crtc->cursor_size != size) {
9904 I915_WRITE(CURSIZE, size);
9905 intel_crtc->cursor_size = size;
4b0e333e 9906 }
560b85bb 9907
4b0e333e 9908 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9909 I915_WRITE(_CURACNTR, cntl);
9910 POSTING_READ(_CURACNTR);
4b0e333e 9911 intel_crtc->cursor_cntl = cntl;
560b85bb 9912 }
560b85bb
CW		 9913}
9914
560b85bb 9915static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9916{
9917 struct drm_device *dev = crtc->dev;
9918 struct drm_i915_private *dev_priv = dev->dev_private;
9919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9920 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9921 uint32_t cntl;
9922
9923 cntl = 0;
9924 if (base) {
9925 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9926 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9927 case 64:
9928 cntl |= CURSOR_MODE_64_ARGB_AX;
9929 break;
9930 case 128:
9931 cntl |= CURSOR_MODE_128_ARGB_AX;
9932 break;
9933 case 256:
9934 cntl |= CURSOR_MODE_256_ARGB_AX;
9935 break;
9936 default:
3dd512fb 9937 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9938 return;
65a21cd6 9939 }
4b0e333e 9940 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9941
9942 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9943 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9944 }
65a21cd6 9945
8e7d688b 9946 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9947 cntl |= CURSOR_ROTATE_180;
9948
4b0e333e
CW		 9949 if (intel_crtc->cursor_cntl != cntl) {
9950 I915_WRITE(CURCNTR(pipe), cntl);
9951 POSTING_READ(CURCNTR(pipe));
9952 intel_crtc->cursor_cntl = cntl;
65a21cd6 9953 }
4b0e333e 9954
65a21cd6 9955 /* and commit changes on next vblank */
5efb3e28
VS		 9956 I915_WRITE(CURBASE(pipe), base);
9957 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9958
9959 intel_crtc->cursor_base = base;
65a21cd6
JB		 9960}
9961
cda4b7d3 9962/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9963static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9964 bool on)
cda4b7d3
CW		 9965{
9966 struct drm_device *dev = crtc->dev;
9967 struct drm_i915_private *dev_priv = dev->dev_private;
9968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9969 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9970 int x = crtc->cursor_x;
9971 int y = crtc->cursor_y;
d6e4db15 9972 u32 base = 0, pos = 0;
cda4b7d3 9973
d6e4db15 9974 if (on)
cda4b7d3 9975 base = intel_crtc->cursor_addr;
cda4b7d3 9976
6e3c9717 9977 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9978 base = 0;
9979
6e3c9717 9980 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9981 base = 0;
9982
9983 if (x < 0) {
3dd512fb 9984 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9985 base = 0;
9986
9987 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9988 x = -x;
9989 }
9990 pos |= x << CURSOR_X_SHIFT;
9991
9992 if (y < 0) {
3dd512fb 9993 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9994 base = 0;
9995
9996 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9997 y = -y;
9998 }
9999 pos |= y << CURSOR_Y_SHIFT;
10000
4b0e333e 10001 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10002 return;
10003
5efb3e28
VS		 10004 I915_WRITE(CURPOS(pipe), pos);
10005
4398ad45
VS		 10006 /* ILK+ do this automagically */
10007 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10008 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 10009 base += (intel_crtc->base.cursor->state->crtc_h *
10010 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 10011 }
10012
8ac54669 10013 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10014 i845_update_cursor(crtc, base);
10015 else
10016 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10017}
10018
dc41c154
VS		 10019static bool cursor_size_ok(struct drm_device *dev,
10020 uint32_t width, uint32_t height)
10021{
10022 if (width == 0 || height == 0)
10023 return false;
10024
10025 /*
10026 * 845g/865g are special in that they are only limited by
10027 * the width of their cursors, the height is arbitrary up to
10028 * the precision of the register. Everything else requires
10029 * square cursors, limited to a few power-of-two sizes.
10030 */
10031 if (IS_845G(dev) || IS_I865G(dev)) {
10032 if ((width & 63) != 0)
10033 return false;
10034
10035 if (width > (IS_845G(dev) ? 64 : 512))
10036 return false;
10037
10038 if (height > 1023)
10039 return false;
10040 } else {
10041 switch (width | height) {
10042 case 256:
10043 case 128:
10044 if (IS_GEN2(dev))
10045 return false;
10046 case 64:
10047 break;
10048 default:
10049 return false;
10050 }
10051 }
10052
10053 return true;
10054}
10055
79e53945 10056static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10057 u16 *blue, uint32_t start, uint32_t size)
79e53945 10058{
7203425a 10059 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10061
7203425a 10062 for (i = start; i < end; i++) {
79e53945
JB		 10063 intel_crtc->lut_r[i] = red[i] >> 8;
10064 intel_crtc->lut_g[i] = green[i] >> 8;
10065 intel_crtc->lut_b[i] = blue[i] >> 8;
10066 }
10067
10068 intel_crtc_load_lut(crtc);
10069}
10070
79e53945
JB		 10071/* VESA 640x480x72Hz mode to set on the pipe */
10072static struct drm_display_mode load_detect_mode = {
10073 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10074 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10075};
10076
a8bb6818
DV		 10077struct drm_framebuffer *
10078__intel_framebuffer_create(struct drm_device *dev,
10079 struct drm_mode_fb_cmd2 *mode_cmd,
10080 struct drm_i915_gem_object *obj)
d2dff872
CW		 10081{
10082 struct intel_framebuffer *intel_fb;
10083 int ret;
10084
10085 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10086 if (!intel_fb) {
6ccb81f2 10087 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10088 return ERR_PTR(-ENOMEM);
10089 }
10090
10091 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10092 if (ret)
10093 goto err;
d2dff872
CW		 10094
10095 return &intel_fb->base;
dd4916c5 10096err:
6ccb81f2 10097 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10098 kfree(intel_fb);
10099
10100 return ERR_PTR(ret);
d2dff872
CW		 10101}
10102
b5ea642a 10103static struct drm_framebuffer *
a8bb6818
DV		 10104intel_framebuffer_create(struct drm_device *dev,
10105 struct drm_mode_fb_cmd2 *mode_cmd,
10106 struct drm_i915_gem_object *obj)
10107{
10108 struct drm_framebuffer *fb;
10109 int ret;
10110
10111 ret = i915_mutex_lock_interruptible(dev);
10112 if (ret)
10113 return ERR_PTR(ret);
10114 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10115 mutex_unlock(&dev->struct_mutex);
10116
10117 return fb;
10118}
10119
d2dff872
CW		 10120static u32
10121intel_framebuffer_pitch_for_width(int width, int bpp)
10122{
10123 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10124 return ALIGN(pitch, 64);
10125}
10126
10127static u32
10128intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10129{
10130 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10131 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10132}
10133
10134static struct drm_framebuffer *
10135intel_framebuffer_create_for_mode(struct drm_device *dev,
10136 struct drm_display_mode *mode,
10137 int depth, int bpp)
10138{
10139 struct drm_i915_gem_object *obj;
0fed39bd 10140 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10141
10142 obj = i915_gem_alloc_object(dev,
10143 intel_framebuffer_size_for_mode(mode, bpp));
10144 if (obj == NULL)
10145 return ERR_PTR(-ENOMEM);
10146
10147 mode_cmd.width = mode->hdisplay;
10148 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10149 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10150 bpp);
5ca0c34a 10151 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10152
10153 return intel_framebuffer_create(dev, &mode_cmd, obj);
10154}
10155
10156static struct drm_framebuffer *
10157mode_fits_in_fbdev(struct drm_device *dev,
10158 struct drm_display_mode *mode)
10159{
4520f53a 10160#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10161 struct drm_i915_private *dev_priv = dev->dev_private;
10162 struct drm_i915_gem_object *obj;
10163 struct drm_framebuffer *fb;
10164
4c0e5528 10165 if (!dev_priv->fbdev)
d2dff872
CW		 10166 return NULL;
10167
4c0e5528 10168 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10169 return NULL;
10170
4c0e5528
DV		 10171 obj = dev_priv->fbdev->fb->obj;
10172 BUG_ON(!obj);
10173
8bcd4553 10174 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10175 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10176 fb->bits_per_pixel))
d2dff872
CW		 10177 return NULL;
10178
01f2c773 10179 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10180 return NULL;
10181
10182 return fb;
4520f53a
DV		 10183#else
10184 return NULL;
10185#endif
d2dff872
CW		 10186}
10187
d3a40d1b
ACO		 10188static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10189 struct drm_crtc *crtc,
10190 struct drm_display_mode *mode,
10191 struct drm_framebuffer *fb,
10192 int x, int y)
10193{
10194 struct drm_plane_state *plane_state;
10195 int hdisplay, vdisplay;
10196 int ret;
10197
10198 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10199 if (IS_ERR(plane_state))
10200 return PTR_ERR(plane_state);
10201
10202 if (mode)
10203 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10204 else
10205 hdisplay = vdisplay = 0;
10206
10207 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10208 if (ret)
10209 return ret;
10210 drm_atomic_set_fb_for_plane(plane_state, fb);
10211 plane_state->crtc_x = 0;
10212 plane_state->crtc_y = 0;
10213 plane_state->crtc_w = hdisplay;
10214 plane_state->crtc_h = vdisplay;
10215 plane_state->src_x = x << 16;
10216 plane_state->src_y = y << 16;
10217 plane_state->src_w = hdisplay << 16;
10218 plane_state->src_h = vdisplay << 16;
10219
10220 return 0;
10221}
10222
d2434ab7 10223bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10224 struct drm_display_mode *mode,
51fd371b
RC		 10225 struct intel_load_detect_pipe *old,
10226 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10227{
10228 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10229 struct intel_encoder *intel_encoder =
10230 intel_attached_encoder(connector);
79e53945 10231 struct drm_crtc *possible_crtc;
4ef69c7a 10232 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10233 struct drm_crtc *crtc = NULL;
10234 struct drm_device *dev = encoder->dev;
94352cf9 10235 struct drm_framebuffer *fb;
51fd371b 10236 struct drm_mode_config *config = &dev->mode_config;
83a57153 10237 struct drm_atomic_state *state = NULL;
944b0c76 10238 struct drm_connector_state *connector_state;
4be07317 10239 struct intel_crtc_state *crtc_state;
51fd371b 10240 int ret, i = -1;
79e53945 10241
d2dff872 10242 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10243 connector->base.id, connector->name,
8e329a03 10244 encoder->base.id, encoder->name);
d2dff872 10245
51fd371b
RC		 10246retry:
10247 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10248 if (ret)
10249 goto fail_unlock;
6e9f798d 10250
79e53945
JB		 10251 /*
10252 * Algorithm gets a little messy:
7a5e4805 10253 *
79e53945
JB		 10254 * - if the connector already has an assigned crtc, use it (but make
10255 * sure it's on first)
7a5e4805 10256 *
79e53945
JB		 10257 * - try to find the first unused crtc that can drive this connector,
10258 * and use that if we find one
79e53945
JB		 10259 */
10260
10261 /* See if we already have a CRTC for this connector */
10262 if (encoder->crtc) {
10263 crtc = encoder->crtc;
8261b191 10264
51fd371b 10265 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10266 if (ret)
10267 goto fail_unlock;
10268 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10269 if (ret)
10270 goto fail_unlock;
7b24056b 10271
24218aac 10272 old->dpms_mode = connector->dpms;
8261b191
CW		 10273 old->load_detect_temp = false;
10274
10275 /* Make sure the crtc and connector are running */
24218aac
DV		 10276 if (connector->dpms != DRM_MODE_DPMS_ON)
10277 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10278
7173188d 10279 return true;
79e53945
JB		 10280 }
10281
10282 /* Find an unused one (if possible) */
70e1e0ec 10283 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10284 i++;
10285 if (!(encoder->possible_crtcs & (1 << i)))
10286 continue;
83d65738 10287 if (possible_crtc->state->enable)
a459249c
VS		 10288 continue;
10289 /* This can occur when applying the pipe A quirk on resume. */
10290 if (to_intel_crtc(possible_crtc)->new_enabled)
10291 continue;
10292
10293 crtc = possible_crtc;
10294 break;
79e53945
JB		 10295 }
10296
10297 /*
10298 * If we didn't find an unused CRTC, don't use any.
10299 */
10300 if (!crtc) {
7173188d 10301 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10302 goto fail_unlock;
79e53945
JB		 10303 }
10304
51fd371b
RC		 10305 ret = drm_modeset_lock(&crtc->mutex, ctx);
10306 if (ret)
4d02e2de
DV		 10307 goto fail_unlock;
10308 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10309 if (ret)
51fd371b 10310 goto fail_unlock;
fc303101
DV		 10311 intel_encoder->new_crtc = to_intel_crtc(crtc);
10312 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10313
10314 intel_crtc = to_intel_crtc(crtc);
412b61d8 10315 intel_crtc->new_enabled = true;
24218aac 10316 old->dpms_mode = connector->dpms;
8261b191 10317 old->load_detect_temp = true;
d2dff872 10318 old->release_fb = NULL;
79e53945 10319
83a57153
ACO		 10320 state = drm_atomic_state_alloc(dev);
10321 if (!state)
10322 return false;
10323
10324 state->acquire_ctx = ctx;
10325
944b0c76
ACO		 10326 connector_state = drm_atomic_get_connector_state(state, connector);
10327 if (IS_ERR(connector_state)) {
10328 ret = PTR_ERR(connector_state);
10329 goto fail;
10330 }
10331
10332 connector_state->crtc = crtc;
10333 connector_state->best_encoder = &intel_encoder->base;
10334
4be07317
ACO		 10335 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10336 if (IS_ERR(crtc_state)) {
10337 ret = PTR_ERR(crtc_state);
10338 goto fail;
10339 }
10340
49d6fa21 10341 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10342
6492711d
CW		 10343 if (!mode)
10344 mode = &load_detect_mode;
79e53945 10345
d2dff872
CW		 10346 /* We need a framebuffer large enough to accommodate all accesses
10347 * that the plane may generate whilst we perform load detection.
10348 * We can not rely on the fbcon either being present (we get called
10349 * during its initialisation to detect all boot displays, or it may
10350 * not even exist) or that it is large enough to satisfy the
10351 * requested mode.
10352 */
94352cf9
DV		 10353 fb = mode_fits_in_fbdev(dev, mode);
10354 if (fb == NULL) {
d2dff872 10355 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10356 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10357 old->release_fb = fb;
d2dff872
CW		 10358 } else
10359 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10360 if (IS_ERR(fb)) {
d2dff872 10361 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10362 goto fail;
79e53945 10363 }
79e53945 10364
d3a40d1b
ACO		 10365 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10366 if (ret)
10367 goto fail;
10368
8c7b5ccb
ACO		 10369 drm_mode_copy(&crtc_state->base.mode, mode);
10370
568c634a 10371 if (intel_set_mode(state)) {
6492711d 10372 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10373 if (old->release_fb)
10374 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10375 goto fail;
79e53945 10376 }
9128b040 10377 crtc->primary->crtc = crtc;
7173188d 10378
79e53945 10379 /* let the connector get through one full cycle before testing */
9d0498a2 10380 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10381 return true;
412b61d8
VS		 10382
10383 fail:
83d65738 10384 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10385fail_unlock:
e5d958ef
ACO		 10386 drm_atomic_state_free(state);
10387 state = NULL;
83a57153 10388
51fd371b
RC		 10389 if (ret == -EDEADLK) {
10390 drm_modeset_backoff(ctx);
10391 goto retry;
10392 }
10393
412b61d8 10394 return false;
79e53945
JB		 10395}
10396
d2434ab7 10397void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10398 struct intel_load_detect_pipe *old,
10399 struct drm_modeset_acquire_ctx *ctx)
79e53945 10400{
83a57153 10401 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10402 struct intel_encoder *intel_encoder =
10403 intel_attached_encoder(connector);
4ef69c7a 10404 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10405 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10407 struct drm_atomic_state *state;
944b0c76 10408 struct drm_connector_state *connector_state;
4be07317 10409 struct intel_crtc_state *crtc_state;
d3a40d1b 10410 int ret;
79e53945 10411
d2dff872 10412 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10413 connector->base.id, connector->name,
8e329a03 10414 encoder->base.id, encoder->name);
d2dff872 10415
8261b191 10416 if (old->load_detect_temp) {
83a57153 10417 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10418 if (!state)
10419 goto fail;
83a57153
ACO		 10420
10421 state->acquire_ctx = ctx;
10422
944b0c76
ACO		 10423 connector_state = drm_atomic_get_connector_state(state, connector);
10424 if (IS_ERR(connector_state))
10425 goto fail;
10426
4be07317
ACO		 10427 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10428 if (IS_ERR(crtc_state))
10429 goto fail;
10430
fc303101
DV		 10431 to_intel_connector(connector)->new_encoder = NULL;
10432 intel_encoder->new_crtc = NULL;
412b61d8 10433 intel_crtc->new_enabled = false;
944b0c76
ACO		 10434
10435 connector_state->best_encoder = NULL;
10436 connector_state->crtc = NULL;
10437
49d6fa21 10438 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10439
d3a40d1b
ACO		 10440 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10441 0, 0);
10442 if (ret)
10443 goto fail;
10444
568c634a 10445 ret = intel_set_mode(state);
2bfb4627
ACO		 10446 if (ret)
10447 goto fail;
d2dff872 10448
36206361
DV		 10449 if (old->release_fb) {
10450 drm_framebuffer_unregister_private(old->release_fb);
10451 drm_framebuffer_unreference(old->release_fb);
10452 }
d2dff872 10453
0622a53c 10454 return;
79e53945
JB		 10455 }
10456
c751ce4f 10457 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10458 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10459 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10460
10461 return;
10462fail:
10463 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10464 drm_atomic_state_free(state);
79e53945
JB		 10465}
10466
da4a1efa 10467static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10468 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10469{
10470 struct drm_i915_private *dev_priv = dev->dev_private;
10471 u32 dpll = pipe_config->dpll_hw_state.dpll;
10472
10473 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10474 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10475 else if (HAS_PCH_SPLIT(dev))
10476 return 120000;
10477 else if (!IS_GEN2(dev))
10478 return 96000;
10479 else
10480 return 48000;
10481}
10482
79e53945 10483/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10484static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10485 struct intel_crtc_state *pipe_config)
79e53945 10486{
f1f644dc 10487 struct drm_device *dev = crtc->base.dev;
79e53945 10488 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10489 int pipe = pipe_config->cpu_transcoder;
293623f7 10490 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10491 u32 fp;
10492 intel_clock_t clock;
dccbea3b 10493 int port_clock;
da4a1efa 10494 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10495
10496 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10497 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10498 else
293623f7 10499 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10500
10501 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10502 if (IS_PINEVIEW(dev)) {
10503 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10504 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10505 } else {
10506 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10507 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10508 }
10509
a6c45cf0 10510 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10511 if (IS_PINEVIEW(dev))
10512 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10513 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10514 else
10515 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10516 DPLL_FPA01_P1_POST_DIV_SHIFT);
10517
10518 switch (dpll & DPLL_MODE_MASK) {
10519 case DPLLB_MODE_DAC_SERIAL:
10520 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10521 5 : 10;
10522 break;
10523 case DPLLB_MODE_LVDS:
10524 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10525 7 : 14;
10526 break;
10527 default:
28c97730 10528 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10529 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10530 return;
79e53945
JB		 10531 }
10532
ac58c3f0 10533 if (IS_PINEVIEW(dev))
dccbea3b 10534 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10535 else
dccbea3b 10536 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10537 } else {
0fb58223 10538 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10539 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10540
10541 if (is_lvds) {
10542 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10543 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10544
10545 if (lvds & LVDS_CLKB_POWER_UP)
10546 clock.p2 = 7;
10547 else
10548 clock.p2 = 14;
79e53945
JB		 10549 } else {
10550 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10551 clock.p1 = 2;
10552 else {
10553 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10554 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10555 }
10556 if (dpll & PLL_P2_DIVIDE_BY_4)
10557 clock.p2 = 4;
10558 else
10559 clock.p2 = 2;
79e53945 10560 }
da4a1efa 10561
dccbea3b 10562 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10563 }
10564
18442d08
VS		 10565 /*
10566 * This value includes pixel_multiplier. We will use
241bfc38 10567 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10568 * encoder's get_config() function.
10569 */
dccbea3b 10570 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10571}
10572
6878da05
VS		 10573int intel_dotclock_calculate(int link_freq,
10574 const struct intel_link_m_n *m_n)
f1f644dc 10575{
f1f644dc
JB		 10576 /*
10577 * The calculation for the data clock is:
1041a02f 10578 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10579 * But we want to avoid losing precison if possible, so:
1041a02f 10580 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10581 *
10582 * and the link clock is simpler:
1041a02f 10583 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10584 */
10585
6878da05
VS		 10586 if (!m_n->link_n)
10587 return 0;
f1f644dc 10588
6878da05
VS		 10589 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10590}
f1f644dc 10591
18442d08 10592static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10593 struct intel_crtc_state *pipe_config)
6878da05
VS		 10594{
10595 struct drm_device *dev = crtc->base.dev;
79e53945 10596
18442d08
VS		 10597 /* read out port_clock from the DPLL */
10598 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10599
f1f644dc 10600 /*
18442d08 10601 * This value does not include pixel_multiplier.
241bfc38 10602 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10603 * agree once we know their relationship in the encoder's
10604 * get_config() function.
79e53945 10605 */
2d112de7 10606 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10607 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10608 &pipe_config->fdi_m_n);
79e53945
JB		 10609}
10610
10611/** Returns the currently programmed mode of the given pipe. */
10612struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10613 struct drm_crtc *crtc)
10614{
548f245b 10615 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10617 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10618 struct drm_display_mode *mode;
5cec258b 10619 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10620 int htot = I915_READ(HTOTAL(cpu_transcoder));
10621 int hsync = I915_READ(HSYNC(cpu_transcoder));
10622 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10623 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10624 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10625
10626 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10627 if (!mode)
10628 return NULL;
10629
f1f644dc
JB		 10630 /*
10631 * Construct a pipe_config sufficient for getting the clock info
10632 * back out of crtc_clock_get.
10633 *
10634 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10635 * to use a real value here instead.
10636 */
293623f7 10637 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10638 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10639 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10640 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10641 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10642 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10643
773ae034 10644 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10645 mode->hdisplay = (htot & 0xffff) + 1;
10646 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10647 mode->hsync_start = (hsync & 0xffff) + 1;
10648 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10649 mode->vdisplay = (vtot & 0xffff) + 1;
10650 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10651 mode->vsync_start = (vsync & 0xffff) + 1;
10652 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10653
10654 drm_mode_set_name(mode);
79e53945
JB		 10655
10656 return mode;
10657}
10658
f047e395
CW		 10659void intel_mark_busy(struct drm_device *dev)
10660{
c67a470b
PZ		 10661 struct drm_i915_private *dev_priv = dev->dev_private;
10662
f62a0076
CW		 10663 if (dev_priv->mm.busy)
10664 return;
10665
43694d69 10666 intel_runtime_pm_get(dev_priv);
c67a470b 10667 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10668 if (INTEL_INFO(dev)->gen >= 6)
10669 gen6_rps_busy(dev_priv);
f62a0076 10670 dev_priv->mm.busy = true;
f047e395
CW		 10671}
10672
10673void intel_mark_idle(struct drm_device *dev)
652c393a 10674{
c67a470b 10675 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10676
f62a0076
CW		 10677 if (!dev_priv->mm.busy)
10678 return;
10679
10680 dev_priv->mm.busy = false;
10681
3d13ef2e 10682 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10683 gen6_rps_idle(dev->dev_private);
bb4cdd53 10684
43694d69 10685 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10686}
10687
79e53945
JB		 10688static void intel_crtc_destroy(struct drm_crtc *crtc)
10689{
10690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10691 struct drm_device *dev = crtc->dev;
10692 struct intel_unpin_work *work;
67e77c5a 10693
5e2d7afc 10694 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10695 work = intel_crtc->unpin_work;
10696 intel_crtc->unpin_work = NULL;
5e2d7afc 10697 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10698
10699 if (work) {
10700 cancel_work_sync(&work->work);
10701 kfree(work);
10702 }
79e53945
JB		 10703
10704 drm_crtc_cleanup(crtc);
67e77c5a 10705
79e53945
JB		 10706 kfree(intel_crtc);
10707}
10708
6b95a207
KH		 10709static void intel_unpin_work_fn(struct work_struct *__work)
10710{
10711 struct intel_unpin_work *work =
10712 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10713 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10714 struct drm_device *dev = crtc->base.dev;
7733b49b 10715 struct drm_i915_private *dev_priv = dev->dev_private;
a9ff8714 10716 struct drm_plane *primary = crtc->base.primary;
6b95a207 10717
b4a98e57 10718 mutex_lock(&dev->struct_mutex);
a9ff8714 10719 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10720 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10721
7733b49b 10722 intel_fbc_update(dev_priv);
f06cc1b9
JH		 10723
10724 if (work->flip_queued_req)
146d84f0 10725 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10726 mutex_unlock(&dev->struct_mutex);
10727
a9ff8714 10728 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10729 drm_framebuffer_unreference(work->old_fb);
f99d7069 10730
a9ff8714
VS		 10731 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10732 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10733
6b95a207
KH		 10734 kfree(work);
10735}
10736
1afe3e9d 10737static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10738 struct drm_crtc *crtc)
6b95a207 10739{
6b95a207
KH		 10740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10741 struct intel_unpin_work *work;
6b95a207
KH		 10742 unsigned long flags;
10743
10744 /* Ignore early vblank irqs */
10745 if (intel_crtc == NULL)
10746 return;
10747
f326038a
DV		 10748 /*
10749 * This is called both by irq handlers and the reset code (to complete
10750 * lost pageflips) so needs the full irqsave spinlocks.
10751 */
6b95a207
KH		 10752 spin_lock_irqsave(&dev->event_lock, flags);
10753 work = intel_crtc->unpin_work;
e7d841ca
CW		 10754
10755 /* Ensure we don't miss a work->pending update ... */
10756 smp_rmb();
10757
10758 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10759 spin_unlock_irqrestore(&dev->event_lock, flags);
10760 return;
10761 }
10762
d6bbafa1 10763 page_flip_completed(intel_crtc);
0af7e4df 10764
6b95a207 10765 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10766}
10767
1afe3e9d
JB		 10768void intel_finish_page_flip(struct drm_device *dev, int pipe)
10769{
fbee40df 10770 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10771 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10772
49b14a5c 10773 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10774}
10775
10776void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10777{
fbee40df 10778 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10779 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10780
49b14a5c 10781 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10782}
10783
75f7f3ec
VS		 10784/* Is 'a' after or equal to 'b'? */
10785static bool g4x_flip_count_after_eq(u32 a, u32 b)
10786{
10787 return !((a - b) & 0x80000000);
10788}
10789
10790static bool page_flip_finished(struct intel_crtc *crtc)
10791{
10792 struct drm_device *dev = crtc->base.dev;
10793 struct drm_i915_private *dev_priv = dev->dev_private;
10794
bdfa7542
VS		 10795 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10796 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10797 return true;
10798
75f7f3ec
VS		 10799 /*
10800 * The relevant registers doen't exist on pre-ctg.
10801 * As the flip done interrupt doesn't trigger for mmio
10802 * flips on gmch platforms, a flip count check isn't
10803 * really needed there. But since ctg has the registers,
10804 * include it in the check anyway.
10805 */
10806 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10807 return true;
10808
10809 /*
10810 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10811 * used the same base address. In that case the mmio flip might
10812 * have completed, but the CS hasn't even executed the flip yet.
10813 *
10814 * A flip count check isn't enough as the CS might have updated
10815 * the base address just after start of vblank, but before we
10816 * managed to process the interrupt. This means we'd complete the
10817 * CS flip too soon.
10818 *
10819 * Combining both checks should get us a good enough result. It may
10820 * still happen that the CS flip has been executed, but has not
10821 * yet actually completed. But in case the base address is the same
10822 * anyway, we don't really care.
10823 */
10824 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10825 crtc->unpin_work->gtt_offset &&
10826 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10827 crtc->unpin_work->flip_count);
10828}
10829
6b95a207
KH		 10830void intel_prepare_page_flip(struct drm_device *dev, int plane)
10831{
fbee40df 10832 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10833 struct intel_crtc *intel_crtc =
10834 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10835 unsigned long flags;
10836
f326038a
DV		 10837
10838 /*
10839 * This is called both by irq handlers and the reset code (to complete
10840 * lost pageflips) so needs the full irqsave spinlocks.
10841 *
10842 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10843 * generate a page-flip completion irq, i.e. every modeset
10844 * is also accompanied by a spurious intel_prepare_page_flip().
10845 */
6b95a207 10846 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10847 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10848 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10849 spin_unlock_irqrestore(&dev->event_lock, flags);
10850}
10851
eba905b2 10852static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10853{
10854 /* Ensure that the work item is consistent when activating it ... */
10855 smp_wmb();
10856 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10857 /* and that it is marked active as soon as the irq could fire. */
10858 smp_wmb();
10859}
10860
8c9f3aaf
JB		 10861static int intel_gen2_queue_flip(struct drm_device *dev,
10862 struct drm_crtc *crtc,
10863 struct drm_framebuffer *fb,
ed8d1975 10864 struct drm_i915_gem_object *obj,
6258fbe2 10865 struct drm_i915_gem_request *req,
ed8d1975 10866 uint32_t flags)
8c9f3aaf 10867{
6258fbe2 10868 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10870 u32 flip_mask;
10871 int ret;
10872
5fb9de1a 10873 ret = intel_ring_begin(req, 6);
8c9f3aaf 10874 if (ret)
4fa62c89 10875 return ret;
8c9f3aaf
JB		 10876
10877 /* Can't queue multiple flips, so wait for the previous
10878 * one to finish before executing the next.
10879 */
10880 if (intel_crtc->plane)
10881 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10882 else
10883 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10884 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10885 intel_ring_emit(ring, MI_NOOP);
10886 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10887 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10888 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10889 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10890 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10891
10892 intel_mark_page_flip_active(intel_crtc);
83d4092b 10893 return 0;
8c9f3aaf
JB		 10894}
10895
10896static int intel_gen3_queue_flip(struct drm_device *dev,
10897 struct drm_crtc *crtc,
10898 struct drm_framebuffer *fb,
ed8d1975 10899 struct drm_i915_gem_object *obj,
6258fbe2 10900 struct drm_i915_gem_request *req,
ed8d1975 10901 uint32_t flags)
8c9f3aaf 10902{
6258fbe2 10903 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10905 u32 flip_mask;
10906 int ret;
10907
5fb9de1a 10908 ret = intel_ring_begin(req, 6);
8c9f3aaf 10909 if (ret)
4fa62c89 10910 return ret;
8c9f3aaf
JB		 10911
10912 if (intel_crtc->plane)
10913 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10914 else
10915 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10916 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10917 intel_ring_emit(ring, MI_NOOP);
10918 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10919 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10920 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10921 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10922 intel_ring_emit(ring, MI_NOOP);
10923
e7d841ca 10924 intel_mark_page_flip_active(intel_crtc);
83d4092b 10925 return 0;
8c9f3aaf
JB		 10926}
10927
10928static int intel_gen4_queue_flip(struct drm_device *dev,
10929 struct drm_crtc *crtc,
10930 struct drm_framebuffer *fb,
ed8d1975 10931 struct drm_i915_gem_object *obj,
6258fbe2 10932 struct drm_i915_gem_request *req,
ed8d1975 10933 uint32_t flags)
8c9f3aaf 10934{
6258fbe2 10935 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10936 struct drm_i915_private *dev_priv = dev->dev_private;
10937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10938 uint32_t pf, pipesrc;
10939 int ret;
10940
5fb9de1a 10941 ret = intel_ring_begin(req, 4);
8c9f3aaf 10942 if (ret)
4fa62c89 10943 return ret;
8c9f3aaf
JB		 10944
10945 /* i965+ uses the linear or tiled offsets from the
10946 * Display Registers (which do not change across a page-flip)
10947 * so we need only reprogram the base address.
10948 */
6d90c952
DV		 10949 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10950 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10951 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10952 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10953 obj->tiling_mode);
8c9f3aaf
JB		 10954
10955 /* XXX Enabling the panel-fitter across page-flip is so far
10956 * untested on non-native modes, so ignore it for now.
10957 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10958 */
10959 pf = 0;
10960 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10961 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10962
10963 intel_mark_page_flip_active(intel_crtc);
83d4092b 10964 return 0;
8c9f3aaf
JB		 10965}
10966
10967static int intel_gen6_queue_flip(struct drm_device *dev,
10968 struct drm_crtc *crtc,
10969 struct drm_framebuffer *fb,
ed8d1975 10970 struct drm_i915_gem_object *obj,
6258fbe2 10971 struct drm_i915_gem_request *req,
ed8d1975 10972 uint32_t flags)
8c9f3aaf 10973{
6258fbe2 10974 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10975 struct drm_i915_private *dev_priv = dev->dev_private;
10976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10977 uint32_t pf, pipesrc;
10978 int ret;
10979
5fb9de1a 10980 ret = intel_ring_begin(req, 4);
8c9f3aaf 10981 if (ret)
4fa62c89 10982 return ret;
8c9f3aaf 10983
6d90c952
DV		 10984 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10985 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10986 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10987 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10988
dc257cf1
DV		 10989 /* Contrary to the suggestions in the documentation,
10990 * "Enable Panel Fitter" does not seem to be required when page
10991 * flipping with a non-native mode, and worse causes a normal
10992 * modeset to fail.
10993 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10994 */
10995 pf = 0;
8c9f3aaf 10996 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10997 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10998
10999 intel_mark_page_flip_active(intel_crtc);
83d4092b 11000 return 0;
8c9f3aaf
JB		 11001}
11002
7c9017e5
JB		 11003static int intel_gen7_queue_flip(struct drm_device *dev,
11004 struct drm_crtc *crtc,
11005 struct drm_framebuffer *fb,
ed8d1975 11006 struct drm_i915_gem_object *obj,
6258fbe2 11007 struct drm_i915_gem_request *req,
ed8d1975 11008 uint32_t flags)
7c9017e5 11009{
6258fbe2 11010 struct intel_engine_cs *ring = req->ring;
7c9017e5 11011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11012 uint32_t plane_bit = 0;
ffe74d75
CW		 11013 int len, ret;
11014
eba905b2 11015 switch (intel_crtc->plane) {
cb05d8de
DV		 11016 case PLANE_A:
11017 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11018 break;
11019 case PLANE_B:
11020 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11021 break;
11022 case PLANE_C:
11023 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11024 break;
11025 default:
11026 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11027 return -ENODEV;
cb05d8de
DV		 11028 }
11029
ffe74d75 11030 len = 4;
f476828a 11031 if (ring->id == RCS) {
ffe74d75 11032 len += 6;
f476828a
DL		 11033 /*
11034 * On Gen 8, SRM is now taking an extra dword to accommodate
11035 * 48bits addresses, and we need a NOOP for the batch size to
11036 * stay even.
11037 */
11038 if (IS_GEN8(dev))
11039 len += 2;
11040 }
ffe74d75 11041
f66fab8e
VS		 11042 /*
11043 * BSpec MI_DISPLAY_FLIP for IVB:
11044 * "The full packet must be contained within the same cache line."
11045 *
11046 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11047 * cacheline, if we ever start emitting more commands before
11048 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11049 * then do the cacheline alignment, and finally emit the
11050 * MI_DISPLAY_FLIP.
11051 */
bba09b12 11052 ret = intel_ring_cacheline_align(req);
f66fab8e 11053 if (ret)
4fa62c89 11054 return ret;
f66fab8e 11055
5fb9de1a 11056 ret = intel_ring_begin(req, len);
7c9017e5 11057 if (ret)
4fa62c89 11058 return ret;
7c9017e5 11059
ffe74d75
CW		 11060 /* Unmask the flip-done completion message. Note that the bspec says that
11061 * we should do this for both the BCS and RCS, and that we must not unmask
11062 * more than one flip event at any time (or ensure that one flip message
11063 * can be sent by waiting for flip-done prior to queueing new flips).
11064 * Experimentation says that BCS works despite DERRMR masking all
11065 * flip-done completion events and that unmasking all planes at once
11066 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11067 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11068 */
11069 if (ring->id == RCS) {
11070 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11071 intel_ring_emit(ring, DERRMR);
11072 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11073 DERRMR_PIPEB_PRI_FLIP_DONE |
11074 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11075 if (IS_GEN8(dev))
11076 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11077 MI_SRM_LRM_GLOBAL_GTT);
11078 else
11079 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11080 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11081 intel_ring_emit(ring, DERRMR);
11082 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11083 if (IS_GEN8(dev)) {
11084 intel_ring_emit(ring, 0);
11085 intel_ring_emit(ring, MI_NOOP);
11086 }
ffe74d75
CW		 11087 }
11088
cb05d8de 11089 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11090 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11091 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11092 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11093
11094 intel_mark_page_flip_active(intel_crtc);
83d4092b 11095 return 0;
7c9017e5
JB		 11096}
11097
84c33a64
SG		 11098static bool use_mmio_flip(struct intel_engine_cs *ring,
11099 struct drm_i915_gem_object *obj)
11100{
11101 /*
11102 * This is not being used for older platforms, because
11103 * non-availability of flip done interrupt forces us to use
11104 * CS flips. Older platforms derive flip done using some clever
11105 * tricks involving the flip_pending status bits and vblank irqs.
11106 * So using MMIO flips there would disrupt this mechanism.
11107 */
11108
8e09bf83
CW		 11109 if (ring == NULL)
11110 return true;
11111
84c33a64
SG		 11112 if (INTEL_INFO(ring->dev)->gen < 5)
11113 return false;
11114
11115 if (i915.use_mmio_flip < 0)
11116 return false;
11117 else if (i915.use_mmio_flip > 0)
11118 return true;
14bf993e
OM		 11119 else if (i915.enable_execlists)
11120 return true;
84c33a64 11121 else
b4716185 11122 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11123}
11124
ff944564
DL		 11125static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11126{
11127 struct drm_device *dev = intel_crtc->base.dev;
11128 struct drm_i915_private *dev_priv = dev->dev_private;
11129 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11130 const enum pipe pipe = intel_crtc->pipe;
11131 u32 ctl, stride;
11132
11133 ctl = I915_READ(PLANE_CTL(pipe, 0));
11134 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11135 switch (fb->modifier[0]) {
11136 case DRM_FORMAT_MOD_NONE:
11137 break;
11138 case I915_FORMAT_MOD_X_TILED:
ff944564 11139 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11140 break;
11141 case I915_FORMAT_MOD_Y_TILED:
11142 ctl |= PLANE_CTL_TILED_Y;
11143 break;
11144 case I915_FORMAT_MOD_Yf_TILED:
11145 ctl |= PLANE_CTL_TILED_YF;
11146 break;
11147 default:
11148 MISSING_CASE(fb->modifier[0]);
11149 }
ff944564
DL		 11150
11151 /*
11152 * The stride is either expressed as a multiple of 64 bytes chunks for
11153 * linear buffers or in number of tiles for tiled buffers.
11154 */
2ebef630
TU		 11155 stride = fb->pitches[0] /
11156 intel_fb_stride_alignment(dev, fb->modifier[0],
11157 fb->pixel_format);
ff944564
DL		 11158
11159 /*
11160 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11161 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11162 */
11163 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11164 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11165
11166 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11167 POSTING_READ(PLANE_SURF(pipe, 0));
11168}
11169
11170static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11171{
11172 struct drm_device *dev = intel_crtc->base.dev;
11173 struct drm_i915_private *dev_priv = dev->dev_private;
11174 struct intel_framebuffer *intel_fb =
11175 to_intel_framebuffer(intel_crtc->base.primary->fb);
11176 struct drm_i915_gem_object *obj = intel_fb->obj;
11177 u32 dspcntr;
11178 u32 reg;
11179
84c33a64
SG		 11180 reg = DSPCNTR(intel_crtc->plane);
11181 dspcntr = I915_READ(reg);
11182
c5d97472
DL		 11183 if (obj->tiling_mode != I915_TILING_NONE)
11184 dspcntr |= DISPPLANE_TILED;
11185 else
11186 dspcntr &= ~DISPPLANE_TILED;
11187
84c33a64
SG		 11188 I915_WRITE(reg, dspcntr);
11189
11190 I915_WRITE(DSPSURF(intel_crtc->plane),
11191 intel_crtc->unpin_work->gtt_offset);
11192 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11193
ff944564
DL		 11194}
11195
11196/*
11197 * XXX: This is the temporary way to update the plane registers until we get
11198 * around to using the usual plane update functions for MMIO flips
11199 */
11200static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11201{
11202 struct drm_device *dev = intel_crtc->base.dev;
11203 bool atomic_update;
11204 u32 start_vbl_count;
11205
11206 intel_mark_page_flip_active(intel_crtc);
11207
11208 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11209
11210 if (INTEL_INFO(dev)->gen >= 9)
11211 skl_do_mmio_flip(intel_crtc);
11212 else
11213 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11214 ilk_do_mmio_flip(intel_crtc);
11215
9362c7c5
ACO		 11216 if (atomic_update)
11217 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11218}
11219
9362c7c5 11220static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11221{
b2cfe0ab
CW		 11222 struct intel_mmio_flip *mmio_flip =
11223 container_of(work, struct intel_mmio_flip, work);
84c33a64 11224
eed29a5b
DV		 11225 if (mmio_flip->req)
11226 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11227 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11228 false, NULL,
11229 &mmio_flip->i915->rps.mmioflips));
84c33a64 11230
b2cfe0ab
CW		 11231 intel_do_mmio_flip(mmio_flip->crtc);
11232
eed29a5b 11233 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11234 kfree(mmio_flip);
84c33a64
SG		 11235}
11236
11237static int intel_queue_mmio_flip(struct drm_device *dev,
11238 struct drm_crtc *crtc,
11239 struct drm_framebuffer *fb,
11240 struct drm_i915_gem_object *obj,
11241 struct intel_engine_cs *ring,
11242 uint32_t flags)
11243{
b2cfe0ab
CW		 11244 struct intel_mmio_flip *mmio_flip;
11245
11246 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11247 if (mmio_flip == NULL)
11248 return -ENOMEM;
84c33a64 11249
bcafc4e3 11250 mmio_flip->i915 = to_i915(dev);
eed29a5b 11251 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11252 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11253
b2cfe0ab
CW		 11254 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11255 schedule_work(&mmio_flip->work);
84c33a64 11256
84c33a64
SG		 11257 return 0;
11258}
11259
8c9f3aaf
JB		 11260static int intel_default_queue_flip(struct drm_device *dev,
11261 struct drm_crtc *crtc,
11262 struct drm_framebuffer *fb,
ed8d1975 11263 struct drm_i915_gem_object *obj,
6258fbe2 11264 struct drm_i915_gem_request *req,
ed8d1975 11265 uint32_t flags)
8c9f3aaf
JB		 11266{
11267 return -ENODEV;
11268}
11269
d6bbafa1
CW		 11270static bool __intel_pageflip_stall_check(struct drm_device *dev,
11271 struct drm_crtc *crtc)
11272{
11273 struct drm_i915_private *dev_priv = dev->dev_private;
11274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11275 struct intel_unpin_work *work = intel_crtc->unpin_work;
11276 u32 addr;
11277
11278 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11279 return true;
11280
11281 if (!work->enable_stall_check)
11282 return false;
11283
11284 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11285 if (work->flip_queued_req &&
11286 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11287 return false;
11288
1e3feefd 11289 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11290 }
11291
1e3feefd 11292 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11293 return false;
11294
11295 /* Potential stall - if we see that the flip has happened,
11296 * assume a missed interrupt. */
11297 if (INTEL_INFO(dev)->gen >= 4)
11298 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11299 else
11300 addr = I915_READ(DSPADDR(intel_crtc->plane));
11301
11302 /* There is a potential issue here with a false positive after a flip
11303 * to the same address. We could address this by checking for a
11304 * non-incrementing frame counter.
11305 */
11306 return addr == work->gtt_offset;
11307}
11308
11309void intel_check_page_flip(struct drm_device *dev, int pipe)
11310{
11311 struct drm_i915_private *dev_priv = dev->dev_private;
11312 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11314 struct intel_unpin_work *work;
f326038a 11315
6c51d46f 11316 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11317
11318 if (crtc == NULL)
11319 return;
11320
f326038a 11321 spin_lock(&dev->event_lock);
6ad790c0
CW		 11322 work = intel_crtc->unpin_work;
11323 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11324 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11325 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11326 page_flip_completed(intel_crtc);
6ad790c0 11327 work = NULL;
d6bbafa1 11328 }
6ad790c0
CW		 11329 if (work != NULL &&
11330 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11331 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11332 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11333}
11334
6b95a207
KH		 11335static int intel_crtc_page_flip(struct drm_crtc *crtc,
11336 struct drm_framebuffer *fb,
ed8d1975
KP		 11337 struct drm_pending_vblank_event *event,
11338 uint32_t page_flip_flags)
6b95a207
KH		 11339{
11340 struct drm_device *dev = crtc->dev;
11341 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11342 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11343 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11345 struct drm_plane *primary = crtc->primary;
a071fa00 11346 enum pipe pipe = intel_crtc->pipe;
6b95a207 11347 struct intel_unpin_work *work;
a4872ba6 11348 struct intel_engine_cs *ring;
cf5d8a46 11349 bool mmio_flip;
91af127f 11350 struct drm_i915_gem_request *request = NULL;
52e68630 11351 int ret;
6b95a207 11352
2ff8fde1
MR		 11353 /*
11354 * drm_mode_page_flip_ioctl() should already catch this, but double
11355 * check to be safe. In the future we may enable pageflipping from
11356 * a disabled primary plane.
11357 */
11358 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11359 return -EBUSY;
11360
e6a595d2 11361 /* Can't change pixel format via MI display flips. */
f4510a27 11362 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11363 return -EINVAL;
11364
11365 /*
11366 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11367 * Note that pitch changes could also affect these register.
11368 */
11369 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11370 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11371 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11372 return -EINVAL;
11373
f900db47
CW		 11374 if (i915_terminally_wedged(&dev_priv->gpu_error))
11375 goto out_hang;
11376
b14c5679 11377 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11378 if (work == NULL)
11379 return -ENOMEM;
11380
6b95a207 11381 work->event = event;
b4a98e57 11382 work->crtc = crtc;
ab8d6675 11383 work->old_fb = old_fb;
6b95a207
KH		 11384 INIT_WORK(&work->work, intel_unpin_work_fn);
11385
87b6b101 11386 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11387 if (ret)
11388 goto free_work;
11389
6b95a207 11390 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11391 spin_lock_irq(&dev->event_lock);
6b95a207 11392 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11393 /* Before declaring the flip queue wedged, check if
11394 * the hardware completed the operation behind our backs.
11395 */
11396 if (__intel_pageflip_stall_check(dev, crtc)) {
11397 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11398 page_flip_completed(intel_crtc);
11399 } else {
11400 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11401 spin_unlock_irq(&dev->event_lock);
468f0b44 11402
d6bbafa1
CW		 11403 drm_crtc_vblank_put(crtc);
11404 kfree(work);
11405 return -EBUSY;
11406 }
6b95a207
KH		 11407 }
11408 intel_crtc->unpin_work = work;
5e2d7afc 11409 spin_unlock_irq(&dev->event_lock);
6b95a207 11410
b4a98e57
CW		 11411 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11412 flush_workqueue(dev_priv->wq);
11413
75dfca80 11414 /* Reference the objects for the scheduled work. */
ab8d6675 11415 drm_framebuffer_reference(work->old_fb);
05394f39 11416 drm_gem_object_reference(&obj->base);
6b95a207 11417
f4510a27 11418 crtc->primary->fb = fb;
afd65eb4 11419 update_state_fb(crtc->primary);
1ed1f968 11420
e1f99ce6 11421 work->pending_flip_obj = obj;
e1f99ce6 11422
89ed88ba
CW		 11423 ret = i915_mutex_lock_interruptible(dev);
11424 if (ret)
11425 goto cleanup;
11426
b4a98e57 11427 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11428 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11429
75f7f3ec 11430 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11431 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11432
4fa62c89
VS		 11433 if (IS_VALLEYVIEW(dev)) {
11434 ring = &dev_priv->ring[BCS];
ab8d6675 11435 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11436 /* vlv: DISPLAY_FLIP fails to change tiling */
11437 ring = NULL;
48bf5b2d 11438 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11439 ring = &dev_priv->ring[BCS];
4fa62c89 11440 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11441 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11442 if (ring == NULL || ring->id != RCS)
11443 ring = &dev_priv->ring[BCS];
11444 } else {
11445 ring = &dev_priv->ring[RCS];
11446 }
11447
cf5d8a46
CW		 11448 mmio_flip = use_mmio_flip(ring, obj);
11449
11450 /* When using CS flips, we want to emit semaphores between rings.
11451 * However, when using mmio flips we will create a task to do the
11452 * synchronisation, so all we want here is to pin the framebuffer
11453 * into the display plane and skip any waits.
11454 */
82bc3b2d 11455 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11456 crtc->primary->state,
91af127f 11457 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11458 if (ret)
11459 goto cleanup_pending;
6b95a207 11460
121920fa
TU		 11461 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11462 + intel_crtc->dspaddr_offset;
4fa62c89 11463
cf5d8a46 11464 if (mmio_flip) {
84c33a64
SG		 11465 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11466 page_flip_flags);
d6bbafa1
CW		 11467 if (ret)
11468 goto cleanup_unpin;
11469
f06cc1b9
JH		 11470 i915_gem_request_assign(&work->flip_queued_req,
11471 obj->last_write_req);
d6bbafa1 11472 } else {
6258fbe2
JH		 11473 if (!request) {
11474 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11475 if (ret)
11476 goto cleanup_unpin;
11477 }
11478
11479 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11480 page_flip_flags);
11481 if (ret)
11482 goto cleanup_unpin;
11483
6258fbe2 11484 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11485 }
11486
91af127f 11487 if (request)
75289874 11488 i915_add_request_no_flush(request);
91af127f 11489
1e3feefd 11490 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11491 work->enable_stall_check = true;
4fa62c89 11492
ab8d6675 11493 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11494 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11495 mutex_unlock(&dev->struct_mutex);
a071fa00 11496
7733b49b 11497 intel_fbc_disable(dev_priv);
a9ff8714
VS		 11498 intel_frontbuffer_flip_prepare(dev,
11499 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11500
e5510fac
JB		 11501 trace_i915_flip_request(intel_crtc->plane, obj);
11502
6b95a207 11503 return 0;
96b099fd 11504
4fa62c89 11505cleanup_unpin:
82bc3b2d 11506 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11507cleanup_pending:
91af127f
JH		 11508 if (request)
11509 i915_gem_request_cancel(request);
b4a98e57 11510 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11511 mutex_unlock(&dev->struct_mutex);
11512cleanup:
f4510a27 11513 crtc->primary->fb = old_fb;
afd65eb4 11514 update_state_fb(crtc->primary);
89ed88ba
CW		 11515
11516 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11517 drm_framebuffer_unreference(work->old_fb);
96b099fd 11518
5e2d7afc 11519 spin_lock_irq(&dev->event_lock);
96b099fd 11520 intel_crtc->unpin_work = NULL;
5e2d7afc 11521 spin_unlock_irq(&dev->event_lock);
96b099fd 11522
87b6b101 11523 drm_crtc_vblank_put(crtc);
7317c75e 11524free_work:
96b099fd
CW		 11525 kfree(work);
11526
f900db47 11527 if (ret == -EIO) {
02e0efb5
ML		 11528 struct drm_atomic_state *state;
11529 struct drm_plane_state *plane_state;
11530
f900db47 11531out_hang:
02e0efb5
ML		 11532 state = drm_atomic_state_alloc(dev);
11533 if (!state)
11534 return -ENOMEM;
11535 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11536
11537retry:
11538 plane_state = drm_atomic_get_plane_state(state, primary);
11539 ret = PTR_ERR_OR_ZERO(plane_state);
11540 if (!ret) {
11541 drm_atomic_set_fb_for_plane(plane_state, fb);
11542
11543 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11544 if (!ret)
11545 ret = drm_atomic_commit(state);
11546 }
11547
11548 if (ret == -EDEADLK) {
11549 drm_modeset_backoff(state->acquire_ctx);
11550 drm_atomic_state_clear(state);
11551 goto retry;
11552 }
11553
11554 if (ret)
11555 drm_atomic_state_free(state);
11556
f0d3dad3 11557 if (ret == 0 && event) {
5e2d7afc 11558 spin_lock_irq(&dev->event_lock);
a071fa00 11559 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11560 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11561 }
f900db47 11562 }
96b099fd 11563 return ret;
6b95a207
KH		 11564}
11565
da20eabd
ML		 11566
11567/**
11568 * intel_wm_need_update - Check whether watermarks need updating
11569 * @plane: drm plane
11570 * @state: new plane state
11571 *
11572 * Check current plane state versus the new one to determine whether
11573 * watermarks need to be recalculated.
11574 *
11575 * Returns true or false.
11576 */
11577static bool intel_wm_need_update(struct drm_plane *plane,
11578 struct drm_plane_state *state)
11579{
11580 /* Update watermarks on tiling changes. */
11581 if (!plane->state->fb || !state->fb ||
11582 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11583 plane->state->rotation != state->rotation)
11584 return true;
11585
11586 if (plane->state->crtc_w != state->crtc_w)
11587 return true;
11588
11589 return false;
11590}
11591
11592int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11593 struct drm_plane_state *plane_state)
11594{
11595 struct drm_crtc *crtc = crtc_state->crtc;
11596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11597 struct drm_plane *plane = plane_state->plane;
11598 struct drm_device *dev = crtc->dev;
11599 struct drm_i915_private *dev_priv = dev->dev_private;
11600 struct intel_plane_state *old_plane_state =
11601 to_intel_plane_state(plane->state);
11602 int idx = intel_crtc->base.base.id, ret;
11603 int i = drm_plane_index(plane);
11604 bool mode_changed = needs_modeset(crtc_state);
11605 bool was_crtc_enabled = crtc->state->active;
11606 bool is_crtc_enabled = crtc_state->active;
11607
11608 bool turn_off, turn_on, visible, was_visible;
11609 struct drm_framebuffer *fb = plane_state->fb;
11610
11611 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11612 plane->type != DRM_PLANE_TYPE_CURSOR) {
11613 ret = skl_update_scaler_plane(
11614 to_intel_crtc_state(crtc_state),
11615 to_intel_plane_state(plane_state));
11616 if (ret)
11617 return ret;
11618 }
11619
11620 /*
11621 * Disabling a plane is always okay; we just need to update
11622 * fb tracking in a special way since cleanup_fb() won't
11623 * get called by the plane helpers.
11624 */
11625 if (old_plane_state->base.fb && !fb)
11626 intel_crtc->atomic.disabled_planes |= 1 << i;
11627
da20eabd
ML		 11628 was_visible = old_plane_state->visible;
11629 visible = to_intel_plane_state(plane_state)->visible;
11630
11631 if (!was_crtc_enabled && WARN_ON(was_visible))
11632 was_visible = false;
11633
11634 if (!is_crtc_enabled && WARN_ON(visible))
11635 visible = false;
11636
11637 if (!was_visible && !visible)
11638 return 0;
11639
11640 turn_off = was_visible && (!visible || mode_changed);
11641 turn_on = visible && (!was_visible || mode_changed);
11642
11643 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11644 plane->base.id, fb ? fb->base.id : -1);
11645
11646 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11647 plane->base.id, was_visible, visible,
11648 turn_off, turn_on, mode_changed);
11649
852eb00d 11650 if (turn_on) {
f015c551 11651 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11652 /* must disable cxsr around plane enable/disable */
11653 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11654 intel_crtc->atomic.disable_cxsr = true;
11655 /* to potentially re-enable cxsr */
11656 intel_crtc->atomic.wait_vblank = true;
11657 intel_crtc->atomic.update_wm_post = true;
11658 }
11659 } else if (turn_off) {
f015c551 11660 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11661 /* must disable cxsr around plane enable/disable */
11662 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11663 if (is_crtc_enabled)
11664 intel_crtc->atomic.wait_vblank = true;
11665 intel_crtc->atomic.disable_cxsr = true;
11666 }
11667 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11668 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11669 }
da20eabd 11670
a9ff8714
VS		 11671 if (visible)
11672 intel_crtc->atomic.fb_bits |=
11673 to_intel_plane(plane)->frontbuffer_bit;
11674
da20eabd
ML		 11675 switch (plane->type) {
11676 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11677 intel_crtc->atomic.wait_for_flips = true;
11678 intel_crtc->atomic.pre_disable_primary = turn_off;
11679 intel_crtc->atomic.post_enable_primary = turn_on;
11680
066cf55b
RV		 11681 if (turn_off) {
11682 /*
11683 * FIXME: Actually if we will still have any other
11684 * plane enabled on the pipe we could let IPS enabled
11685 * still, but for now lets consider that when we make
11686 * primary invisible by setting DSPCNTR to 0 on
11687 * update_primary_plane function IPS needs to be
11688 * disable.
11689 */
11690 intel_crtc->atomic.disable_ips = true;
11691
da20eabd 11692 intel_crtc->atomic.disable_fbc = true;
066cf55b 11693 }
da20eabd
ML		 11694
11695 /*
11696 * FBC does not work on some platforms for rotated
11697 * planes, so disable it when rotation is not 0 and
11698 * update it when rotation is set back to 0.
11699 *
11700 * FIXME: This is redundant with the fbc update done in
11701 * the primary plane enable function except that that
11702 * one is done too late. We eventually need to unify
11703 * this.
11704 */
11705
11706 if (visible &&
11707 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11708 dev_priv->fbc.crtc == intel_crtc &&
11709 plane_state->rotation != BIT(DRM_ROTATE_0))
11710 intel_crtc->atomic.disable_fbc = true;
11711
11712 /*
11713 * BDW signals flip done immediately if the plane
11714 * is disabled, even if the plane enable is already
11715 * armed to occur at the next vblank :(
11716 */
11717 if (turn_on && IS_BROADWELL(dev))
11718 intel_crtc->atomic.wait_vblank = true;
11719
11720 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11721 break;
11722 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11723 break;
11724 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11725 if (turn_off && !mode_changed) {
da20eabd
ML		 11726 intel_crtc->atomic.wait_vblank = true;
11727 intel_crtc->atomic.update_sprite_watermarks |=
11728 1 << i;
11729 }
da20eabd
ML		 11730 }
11731 return 0;
11732}
11733
6d3a1ce7
ML		 11734static bool encoders_cloneable(const struct intel_encoder *a,
11735 const struct intel_encoder *b)
11736{
11737 /* masks could be asymmetric, so check both ways */
11738 return a == b || (a->cloneable & (1 << b->type) &&
11739 b->cloneable & (1 << a->type));
11740}
11741
11742static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11743 struct intel_crtc *crtc,
11744 struct intel_encoder *encoder)
11745{
11746 struct intel_encoder *source_encoder;
11747 struct drm_connector *connector;
11748 struct drm_connector_state *connector_state;
11749 int i;
11750
11751 for_each_connector_in_state(state, connector, connector_state, i) {
11752 if (connector_state->crtc != &crtc->base)
11753 continue;
11754
11755 source_encoder =
11756 to_intel_encoder(connector_state->best_encoder);
11757 if (!encoders_cloneable(encoder, source_encoder))
11758 return false;
11759 }
11760
11761 return true;
11762}
11763
11764static bool check_encoder_cloning(struct drm_atomic_state *state,
11765 struct intel_crtc *crtc)
11766{
11767 struct intel_encoder *encoder;
11768 struct drm_connector *connector;
11769 struct drm_connector_state *connector_state;
11770 int i;
11771
11772 for_each_connector_in_state(state, connector, connector_state, i) {
11773 if (connector_state->crtc != &crtc->base)
11774 continue;
11775
11776 encoder = to_intel_encoder(connector_state->best_encoder);
11777 if (!check_single_encoder_cloning(state, crtc, encoder))
11778 return false;
11779 }
11780
11781 return true;
11782}
11783
d032ffa0
ML		 11784static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11785 struct drm_crtc_state *crtc_state)
11786{
11787 struct intel_crtc_state *pipe_config =
11788 to_intel_crtc_state(crtc_state);
11789 struct drm_plane *p;
11790 unsigned visible_mask = 0;
11791
11792 drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11793 struct drm_plane_state *plane_state =
11794 drm_atomic_get_existing_plane_state(crtc_state->state, p);
11795
11796 if (WARN_ON(!plane_state))
11797 continue;
11798
11799 if (!plane_state->fb)
11800 crtc_state->plane_mask &=
11801 ~(1 << drm_plane_index(p));
11802 else if (to_intel_plane_state(plane_state)->visible)
11803 visible_mask |= 1 << drm_plane_index(p);
11804 }
11805
11806 if (!visible_mask)
11807 return;
11808
11809 pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11810}
11811
6d3a1ce7
ML		 11812static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11813 struct drm_crtc_state *crtc_state)
11814{
cf5a15be 11815 struct drm_device *dev = crtc->dev;
ad421372 11816 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11818 struct intel_crtc_state *pipe_config =
11819 to_intel_crtc_state(crtc_state);
6d3a1ce7 11820 struct drm_atomic_state *state = crtc_state->state;
ad421372 11821 int ret, idx = crtc->base.id;
6d3a1ce7
ML		 11822 bool mode_changed = needs_modeset(crtc_state);
11823
11824 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11825 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11826 return -EINVAL;
11827 }
11828
11829 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11830 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11831 idx, crtc->state->active, intel_crtc->active);
11832
d032ffa0
ML		 11833 /* plane mask is fixed up after all initial planes are calculated */
11834 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11835 intel_crtc_check_initial_planes(crtc, crtc_state);
11836
852eb00d
VS		 11837 if (mode_changed && !crtc_state->active)
11838 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11839
ad421372
ML		 11840 if (mode_changed && crtc_state->enable &&
11841 dev_priv->display.crtc_compute_clock &&
11842 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11843 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11844 pipe_config);
11845 if (ret)
11846 return ret;
11847 }
11848
e435d6e5
ML		 11849 ret = 0;
11850 if (INTEL_INFO(dev)->gen >= 9) {
11851 if (mode_changed)
11852 ret = skl_update_scaler_crtc(pipe_config);
11853
11854 if (!ret)
11855 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11856 pipe_config);
11857 }
11858
11859 return ret;
6d3a1ce7
ML		 11860}
11861
65b38e0d 11862static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11863 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11864 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11865 .atomic_begin = intel_begin_crtc_commit,
11866 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11867 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11868};
11869
9a935856
DV		 11870/**
11871 * intel_modeset_update_staged_output_state
11872 *
11873 * Updates the staged output configuration state, e.g. after we've read out the
11874 * current hw state.
11875 */
11876static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11877{
7668851f 11878 struct intel_crtc *crtc;
9a935856
DV		 11879 struct intel_encoder *encoder;
11880 struct intel_connector *connector;
f6e5b160 11881
3a3371ff 11882 for_each_intel_connector(dev, connector) {
9a935856
DV		 11883 connector->new_encoder =
11884 to_intel_encoder(connector->base.encoder);
11885 }
f6e5b160 11886
b2784e15 11887 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11888 encoder->new_crtc =
11889 to_intel_crtc(encoder->base.crtc);
11890 }
7668851f 11891
d3fcc808 11892 for_each_intel_crtc(dev, crtc) {
83d65738 11893 crtc->new_enabled = crtc->base.state->enable;
7668851f 11894 }
f6e5b160
CW		 11895}
11896
d29b2f9d
ACO		 11897/* Transitional helper to copy current connector/encoder state to
11898 * connector->state. This is needed so that code that is partially
11899 * converted to atomic does the right thing.
11900 */
11901static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11902{
11903 struct intel_connector *connector;
11904
11905 for_each_intel_connector(dev, connector) {
11906 if (connector->base.encoder) {
11907 connector->base.state->best_encoder =
11908 connector->base.encoder;
11909 connector->base.state->crtc =
11910 connector->base.encoder->crtc;
11911 } else {
11912 connector->base.state->best_encoder = NULL;
11913 connector->base.state->crtc = NULL;
11914 }
11915 }
11916}
11917
050f7aeb 11918static void
eba905b2 11919connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11920 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11921{
11922 int bpp = pipe_config->pipe_bpp;
11923
11924 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11925 connector->base.base.id,
c23cc417 11926 connector->base.name);
050f7aeb
DV		 11927
11928 /* Don't use an invalid EDID bpc value */
11929 if (connector->base.display_info.bpc &&
11930 connector->base.display_info.bpc * 3 < bpp) {
11931 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11932 bpp, connector->base.display_info.bpc*3);
11933 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11934 }
11935
11936 /* Clamp bpp to 8 on screens without EDID 1.4 */
11937 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11938 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11939 bpp);
11940 pipe_config->pipe_bpp = 24;
11941 }
11942}
11943
4e53c2e0 11944static int
050f7aeb 11945compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11946 struct intel_crtc_state *pipe_config)
4e53c2e0 11947{
050f7aeb 11948 struct drm_device *dev = crtc->base.dev;
1486017f 11949 struct drm_atomic_state *state;
da3ced29
ACO		 11950 struct drm_connector *connector;
11951 struct drm_connector_state *connector_state;
1486017f 11952 int bpp, i;
4e53c2e0 11953
d328c9d7 11954 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11955 bpp = 10*3;
d328c9d7
DV		 11956 else if (INTEL_INFO(dev)->gen >= 5)
11957 bpp = 12*3;
11958 else
11959 bpp = 8*3;
11960
4e53c2e0 11961
4e53c2e0
DV		 11962 pipe_config->pipe_bpp = bpp;
11963
1486017f
ACO		 11964 state = pipe_config->base.state;
11965
4e53c2e0 11966 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11967 for_each_connector_in_state(state, connector, connector_state, i) {
11968 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11969 continue;
11970
da3ced29
ACO		 11971 connected_sink_compute_bpp(to_intel_connector(connector),
11972 pipe_config);
4e53c2e0
DV		 11973 }
11974
11975 return bpp;
11976}
11977
644db711
DV		 11978static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11979{
11980 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11981 "type: 0x%x flags: 0x%x\n",
1342830c 11982 mode->crtc_clock,
644db711
DV		 11983 mode->crtc_hdisplay, mode->crtc_hsync_start,
11984 mode->crtc_hsync_end, mode->crtc_htotal,
11985 mode->crtc_vdisplay, mode->crtc_vsync_start,
11986 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11987}
11988
c0b03411 11989static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11990 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11991 const char *context)
11992{
6a60cd87
CK		 11993 struct drm_device *dev = crtc->base.dev;
11994 struct drm_plane *plane;
11995 struct intel_plane *intel_plane;
11996 struct intel_plane_state *state;
11997 struct drm_framebuffer *fb;
11998
11999 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12000 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 12001
12002 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12003 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12004 pipe_config->pipe_bpp, pipe_config->dither);
12005 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12006 pipe_config->has_pch_encoder,
12007 pipe_config->fdi_lanes,
12008 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12009 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12010 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 12011 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12012 pipe_config->has_dp_encoder,
12013 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12014 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12015 pipe_config->dp_m_n.tu);
b95af8be
VK		 12016
12017 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12018 pipe_config->has_dp_encoder,
12019 pipe_config->dp_m2_n2.gmch_m,
12020 pipe_config->dp_m2_n2.gmch_n,
12021 pipe_config->dp_m2_n2.link_m,
12022 pipe_config->dp_m2_n2.link_n,
12023 pipe_config->dp_m2_n2.tu);
12024
55072d19
DV		 12025 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12026 pipe_config->has_audio,
12027 pipe_config->has_infoframe);
12028
c0b03411 12029 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 12030 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 12031 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 12032 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12033 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 12034 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 12035 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12036 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 12037 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12038 crtc->num_scalers,
12039 pipe_config->scaler_state.scaler_users,
12040 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 12041 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12042 pipe_config->gmch_pfit.control,
12043 pipe_config->gmch_pfit.pgm_ratios,
12044 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12045 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12046 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 12047 pipe_config->pch_pfit.size,
12048 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12049 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12050 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12051
415ff0f6 12052 if (IS_BROXTON(dev)) {
05712c15 12053 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 12054 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 12055 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 12056 pipe_config->ddi_pll_sel,
12057 pipe_config->dpll_hw_state.ebb0,
05712c15 12058 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 12059 pipe_config->dpll_hw_state.pll0,
12060 pipe_config->dpll_hw_state.pll1,
12061 pipe_config->dpll_hw_state.pll2,
12062 pipe_config->dpll_hw_state.pll3,
12063 pipe_config->dpll_hw_state.pll6,
12064 pipe_config->dpll_hw_state.pll8,
05712c15 12065 pipe_config->dpll_hw_state.pll9,
c8453338 12066 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 12067 pipe_config->dpll_hw_state.pcsdw12);
12068 } else if (IS_SKYLAKE(dev)) {
12069 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12070 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12071 pipe_config->ddi_pll_sel,
12072 pipe_config->dpll_hw_state.ctrl1,
12073 pipe_config->dpll_hw_state.cfgcr1,
12074 pipe_config->dpll_hw_state.cfgcr2);
12075 } else if (HAS_DDI(dev)) {
12076 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12077 pipe_config->ddi_pll_sel,
12078 pipe_config->dpll_hw_state.wrpll);
12079 } else {
12080 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12081 "fp0: 0x%x, fp1: 0x%x\n",
12082 pipe_config->dpll_hw_state.dpll,
12083 pipe_config->dpll_hw_state.dpll_md,
12084 pipe_config->dpll_hw_state.fp0,
12085 pipe_config->dpll_hw_state.fp1);
12086 }
12087
6a60cd87
CK		 12088 DRM_DEBUG_KMS("planes on this crtc\n");
12089 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12090 intel_plane = to_intel_plane(plane);
12091 if (intel_plane->pipe != crtc->pipe)
12092 continue;
12093
12094 state = to_intel_plane_state(plane->state);
12095 fb = state->base.fb;
12096 if (!fb) {
12097 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12098 "disabled, scaler_id = %d\n",
12099 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12100 plane->base.id, intel_plane->pipe,
12101 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12102 drm_plane_index(plane), state->scaler_id);
12103 continue;
12104 }
12105
12106 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12107 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12108 plane->base.id, intel_plane->pipe,
12109 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12110 drm_plane_index(plane));
12111 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12112 fb->base.id, fb->width, fb->height, fb->pixel_format);
12113 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12114 state->scaler_id,
12115 state->src.x1 >> 16, state->src.y1 >> 16,
12116 drm_rect_width(&state->src) >> 16,
12117 drm_rect_height(&state->src) >> 16,
12118 state->dst.x1, state->dst.y1,
12119 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12120 }
c0b03411
DV		 12121}
12122
5448a00d 12123static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12124{
5448a00d
ACO		 12125 struct drm_device *dev = state->dev;
12126 struct intel_encoder *encoder;
da3ced29 12127 struct drm_connector *connector;
5448a00d 12128 struct drm_connector_state *connector_state;
00f0b378 12129 unsigned int used_ports = 0;
5448a00d 12130 int i;
00f0b378
VS		 12131
12132 /*
12133 * Walk the connector list instead of the encoder
12134 * list to detect the problem on ddi platforms
12135 * where there's just one encoder per digital port.
12136 */
da3ced29 12137 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12138 if (!connector_state->best_encoder)
00f0b378
VS		 12139 continue;
12140
5448a00d
ACO		 12141 encoder = to_intel_encoder(connector_state->best_encoder);
12142
12143 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12144
12145 switch (encoder->type) {
12146 unsigned int port_mask;
12147 case INTEL_OUTPUT_UNKNOWN:
12148 if (WARN_ON(!HAS_DDI(dev)))
12149 break;
12150 case INTEL_OUTPUT_DISPLAYPORT:
12151 case INTEL_OUTPUT_HDMI:
12152 case INTEL_OUTPUT_EDP:
12153 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12154
12155 /* the same port mustn't appear more than once */
12156 if (used_ports & port_mask)
12157 return false;
12158
12159 used_ports |= port_mask;
12160 default:
12161 break;
12162 }
12163 }
12164
12165 return true;
12166}
12167
83a57153
ACO		 12168static void
12169clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12170{
12171 struct drm_crtc_state tmp_state;
663a3640 12172 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12173 struct intel_dpll_hw_state dpll_hw_state;
12174 enum intel_dpll_id shared_dpll;
8504c74c 12175 uint32_t ddi_pll_sel;
83a57153 12176
7546a384
ACO		 12177 /* FIXME: before the switch to atomic started, a new pipe_config was
12178 * kzalloc'd. Code that depends on any field being zero should be
12179 * fixed, so that the crtc_state can be safely duplicated. For now,
12180 * only fields that are know to not cause problems are preserved. */
12181
83a57153 12182 tmp_state = crtc_state->base;
663a3640 12183 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12184 shared_dpll = crtc_state->shared_dpll;
12185 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12186 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12187
83a57153 12188 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12189
83a57153 12190 crtc_state->base = tmp_state;
663a3640 12191 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12192 crtc_state->shared_dpll = shared_dpll;
12193 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12194 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12195}
12196
548ee15b 12197static int
b8cecdf5 12198intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12199 struct intel_crtc_state *pipe_config)
ee7b9f93 12200{
b359283a 12201 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12202 struct intel_encoder *encoder;
da3ced29 12203 struct drm_connector *connector;
0b901879 12204 struct drm_connector_state *connector_state;
d328c9d7 12205 int base_bpp, ret = -EINVAL;
0b901879 12206 int i;
e29c22c0 12207 bool retry = true;
ee7b9f93 12208
83a57153 12209 clear_intel_crtc_state(pipe_config);
7758a113 12210
e143a21c
DV		 12211 pipe_config->cpu_transcoder =
12212 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12213
2960bc9c
ID		 12214 /*
12215 * Sanitize sync polarity flags based on requested ones. If neither
12216 * positive or negative polarity is requested, treat this as meaning
12217 * negative polarity.
12218 */
2d112de7 12219 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12220 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12221 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12222
2d112de7 12223 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12224 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12225 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12226
050f7aeb
DV		 12227 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12228 * plane pixel format and any sink constraints into account. Returns the
12229 * source plane bpp so that dithering can be selected on mismatches
12230 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12231 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12232 pipe_config);
12233 if (base_bpp < 0)
4e53c2e0
DV		 12234 goto fail;
12235
e41a56be
VS		 12236 /*
12237 * Determine the real pipe dimensions. Note that stereo modes can
12238 * increase the actual pipe size due to the frame doubling and
12239 * insertion of additional space for blanks between the frame. This
12240 * is stored in the crtc timings. We use the requested mode to do this
12241 * computation to clearly distinguish it from the adjusted mode, which
12242 * can be changed by the connectors in the below retry loop.
12243 */
2d112de7 12244 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12245 &pipe_config->pipe_src_w,
12246 &pipe_config->pipe_src_h);
e41a56be 12247
e29c22c0 12248encoder_retry:
ef1b460d 12249 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12250 pipe_config->port_clock = 0;
ef1b460d 12251 pipe_config->pixel_multiplier = 1;
ff9a6750 12252
135c81b8 12253 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12254 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12255 CRTC_STEREO_DOUBLE);
135c81b8 12256
7758a113
DV		 12257 /* Pass our mode to the connectors and the CRTC to give them a chance to
12258 * adjust it according to limitations or connector properties, and also
12259 * a chance to reject the mode entirely.
47f1c6c9 12260 */
da3ced29 12261 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12262 if (connector_state->crtc != crtc)
7758a113 12263 continue;
7ae89233 12264
0b901879
ACO		 12265 encoder = to_intel_encoder(connector_state->best_encoder);
12266
efea6e8e
DV		 12267 if (!(encoder->compute_config(encoder, pipe_config))) {
12268 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12269 goto fail;
12270 }
ee7b9f93 12271 }
47f1c6c9 12272
ff9a6750
DV		 12273 /* Set default port clock if not overwritten by the encoder. Needs to be
12274 * done afterwards in case the encoder adjusts the mode. */
12275 if (!pipe_config->port_clock)
2d112de7 12276 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12277 * pipe_config->pixel_multiplier;
ff9a6750 12278
a43f6e0f 12279 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12280 if (ret < 0) {
7758a113
DV		 12281 DRM_DEBUG_KMS("CRTC fixup failed\n");
12282 goto fail;
ee7b9f93 12283 }
e29c22c0
DV		 12284
12285 if (ret == RETRY) {
12286 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12287 ret = -EINVAL;
12288 goto fail;
12289 }
12290
12291 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12292 retry = false;
12293 goto encoder_retry;
12294 }
12295
d328c9d7 12296 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12297 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12298 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12299
7758a113 12300fail:
548ee15b 12301 return ret;
ee7b9f93 12302}
47f1c6c9 12303
ea9d758d 12304static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12305{
ea9d758d 12306 struct drm_encoder *encoder;
f6e5b160 12307 struct drm_device *dev = crtc->dev;
f6e5b160 12308
ea9d758d
DV		 12309 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12310 if (encoder->crtc == crtc)
12311 return true;
12312
12313 return false;
12314}
12315
12316static void
0a9ab303 12317intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12318{
0a9ab303 12319 struct drm_device *dev = state->dev;
ea9d758d 12320 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12321 struct drm_crtc *crtc;
12322 struct drm_crtc_state *crtc_state;
ea9d758d 12323 struct drm_connector *connector;
8a75d157 12324 int i;
ea9d758d 12325
de419ab6 12326 intel_shared_dpll_commit(state);
ba41c0de 12327
b2784e15 12328 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12329 if (!intel_encoder->base.crtc)
12330 continue;
12331
69024de8
ML		 12332 crtc = intel_encoder->base.crtc;
12333 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12334 if (!crtc_state || !needs_modeset(crtc->state))
12335 continue;
ea9d758d 12336
69024de8 12337 intel_encoder->connectors_active = false;
ea9d758d
DV		 12338 }
12339
3cb480bc 12340 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
f7217905 12341 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12342
7668851f 12343 /* Double check state. */
8a75d157 12344 for_each_crtc_in_state(state, crtc, crtc_state, i) {
0a9ab303 12345 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12346
12347 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12348
12349 /* Update hwmode for vblank functions */
12350 if (crtc->state->active)
12351 crtc->hwmode = crtc->state->adjusted_mode;
12352 else
12353 crtc->hwmode.crtc_clock = 0;
ea9d758d
DV		 12354 }
12355
12356 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12357 if (!connector->encoder || !connector->encoder->crtc)
12358 continue;
12359
69024de8
ML		 12360 crtc = connector->encoder->crtc;
12361 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12362 if (!crtc_state || !needs_modeset(crtc->state))
12363 continue;
ea9d758d 12364
53d9f4e9 12365 if (crtc->state->active) {
69024de8
ML		 12366 struct drm_property *dpms_property =
12367 dev->mode_config.dpms_property;
68d34720 12368
69024de8
ML		 12369 connector->dpms = DRM_MODE_DPMS_ON;
12370 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12371
69024de8
ML		 12372 intel_encoder = to_intel_encoder(connector->encoder);
12373 intel_encoder->connectors_active = true;
12374 } else
12375 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12376 }
ea9d758d
DV		 12377}
12378
3bd26263 12379static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12380{
3bd26263 12381 int diff;
f1f644dc
JB		 12382
12383 if (clock1 == clock2)
12384 return true;
12385
12386 if (!clock1 || !clock2)
12387 return false;
12388
12389 diff = abs(clock1 - clock2);
12390
12391 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12392 return true;
12393
12394 return false;
12395}
12396
25c5b266
DV		 12397#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12398 list_for_each_entry((intel_crtc), \
12399 &(dev)->mode_config.crtc_list, \
12400 base.head) \
0973f18f 12401 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12402
cfb23ed6
ML		 12403
12404static bool
12405intel_compare_m_n(unsigned int m, unsigned int n,
12406 unsigned int m2, unsigned int n2,
12407 bool exact)
12408{
12409 if (m == m2 && n == n2)
12410 return true;
12411
12412 if (exact || !m || !n || !m2 || !n2)
12413 return false;
12414
12415 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12416
12417 if (m > m2) {
12418 while (m > m2) {
12419 m2 <<= 1;
12420 n2 <<= 1;
12421 }
12422 } else if (m < m2) {
12423 while (m < m2) {
12424 m <<= 1;
12425 n <<= 1;
12426 }
12427 }
12428
12429 return m == m2 && n == n2;
12430}
12431
12432static bool
12433intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12434 struct intel_link_m_n *m2_n2,
12435 bool adjust)
12436{
12437 if (m_n->tu == m2_n2->tu &&
12438 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12439 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12440 intel_compare_m_n(m_n->link_m, m_n->link_n,
12441 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12442 if (adjust)
12443 *m2_n2 = *m_n;
12444
12445 return true;
12446 }
12447
12448 return false;
12449}
12450
0e8ffe1b 12451static bool
2fa2fe9a 12452intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12453 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12454 struct intel_crtc_state *pipe_config,
12455 bool adjust)
0e8ffe1b 12456{
cfb23ed6
ML		 12457 bool ret = true;
12458
12459#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12460 do { \
12461 if (!adjust) \
12462 DRM_ERROR(fmt, ##__VA_ARGS__); \
12463 else \
12464 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12465 } while (0)
12466
66e985c0
DV		 12467#define PIPE_CONF_CHECK_X(name) \
12468 if (current_config->name != pipe_config->name) { \
cfb23ed6 12469 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12470 "(expected 0x%08x, found 0x%08x)\n", \
12471 current_config->name, \
12472 pipe_config->name); \
cfb23ed6 12473 ret = false; \
66e985c0
DV		 12474 }
12475
08a24034
DV		 12476#define PIPE_CONF_CHECK_I(name) \
12477 if (current_config->name != pipe_config->name) { \
cfb23ed6 12478 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12479 "(expected %i, found %i)\n", \
12480 current_config->name, \
12481 pipe_config->name); \
cfb23ed6
ML		 12482 ret = false; \
12483 }
12484
12485#define PIPE_CONF_CHECK_M_N(name) \
12486 if (!intel_compare_link_m_n(&current_config->name, \
12487 &pipe_config->name,\
12488 adjust)) { \
12489 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12490 "(expected tu %i gmch %i/%i link %i/%i, " \
12491 "found tu %i, gmch %i/%i link %i/%i)\n", \
12492 current_config->name.tu, \
12493 current_config->name.gmch_m, \
12494 current_config->name.gmch_n, \
12495 current_config->name.link_m, \
12496 current_config->name.link_n, \
12497 pipe_config->name.tu, \
12498 pipe_config->name.gmch_m, \
12499 pipe_config->name.gmch_n, \
12500 pipe_config->name.link_m, \
12501 pipe_config->name.link_n); \
12502 ret = false; \
12503 }
12504
12505#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12506 if (!intel_compare_link_m_n(&current_config->name, \
12507 &pipe_config->name, adjust) && \
12508 !intel_compare_link_m_n(&current_config->alt_name, \
12509 &pipe_config->name, adjust)) { \
12510 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12511 "(expected tu %i gmch %i/%i link %i/%i, " \
12512 "or tu %i gmch %i/%i link %i/%i, " \
12513 "found tu %i, gmch %i/%i link %i/%i)\n", \
12514 current_config->name.tu, \
12515 current_config->name.gmch_m, \
12516 current_config->name.gmch_n, \
12517 current_config->name.link_m, \
12518 current_config->name.link_n, \
12519 current_config->alt_name.tu, \
12520 current_config->alt_name.gmch_m, \
12521 current_config->alt_name.gmch_n, \
12522 current_config->alt_name.link_m, \
12523 current_config->alt_name.link_n, \
12524 pipe_config->name.tu, \
12525 pipe_config->name.gmch_m, \
12526 pipe_config->name.gmch_n, \
12527 pipe_config->name.link_m, \
12528 pipe_config->name.link_n); \
12529 ret = false; \
88adfff1
DV		 12530 }
12531
b95af8be
VK		 12532/* This is required for BDW+ where there is only one set of registers for
12533 * switching between high and low RR.
12534 * This macro can be used whenever a comparison has to be made between one
12535 * hw state and multiple sw state variables.
12536 */
12537#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12538 if ((current_config->name != pipe_config->name) && \
12539 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12540 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12541 "(expected %i or %i, found %i)\n", \
12542 current_config->name, \
12543 current_config->alt_name, \
12544 pipe_config->name); \
cfb23ed6 12545 ret = false; \
b95af8be
VK		 12546 }
12547
1bd1bd80
DV		 12548#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12549 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12550 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12551 "(expected %i, found %i)\n", \
12552 current_config->name & (mask), \
12553 pipe_config->name & (mask)); \
cfb23ed6 12554 ret = false; \
1bd1bd80
DV		 12555 }
12556
5e550656
VS		 12557#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12558 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12559 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12560 "(expected %i, found %i)\n", \
12561 current_config->name, \
12562 pipe_config->name); \
cfb23ed6 12563 ret = false; \
5e550656
VS		 12564 }
12565
bb760063
DV		 12566#define PIPE_CONF_QUIRK(quirk) \
12567 ((current_config->quirks | pipe_config->quirks) & (quirk))
12568
eccb140b
DV		 12569 PIPE_CONF_CHECK_I(cpu_transcoder);
12570
08a24034
DV		 12571 PIPE_CONF_CHECK_I(has_pch_encoder);
12572 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12573 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12574
eb14cb74 12575 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12576
12577 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12578 PIPE_CONF_CHECK_M_N(dp_m_n);
12579
12580 PIPE_CONF_CHECK_I(has_drrs);
12581 if (current_config->has_drrs)
12582 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12583 } else
12584 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12585
2d112de7
ACO		 12586 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12587 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12588 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12589 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12590 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12591 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12592
2d112de7
ACO		 12593 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12594 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12595 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12596 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12597 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12598 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12599
c93f54cf 12600 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12601 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12602 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12603 IS_VALLEYVIEW(dev))
12604 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12605 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12606
9ed109a7
DV		 12607 PIPE_CONF_CHECK_I(has_audio);
12608
2d112de7 12609 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12610 DRM_MODE_FLAG_INTERLACE);
12611
bb760063 12612 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12613 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12614 DRM_MODE_FLAG_PHSYNC);
2d112de7 12615 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12616 DRM_MODE_FLAG_NHSYNC);
2d112de7 12617 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12618 DRM_MODE_FLAG_PVSYNC);
2d112de7 12619 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12620 DRM_MODE_FLAG_NVSYNC);
12621 }
045ac3b5 12622
37327abd
VS		 12623 PIPE_CONF_CHECK_I(pipe_src_w);
12624 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12625
9953599b
DV		 12626 /*
12627 * FIXME: BIOS likes to set up a cloned config with lvds+external
12628 * screen. Since we don't yet re-compute the pipe config when moving
12629 * just the lvds port away to another pipe the sw tracking won't match.
12630 *
12631 * Proper atomic modesets with recomputed global state will fix this.
12632 * Until then just don't check gmch state for inherited modes.
12633 */
12634 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12635 PIPE_CONF_CHECK_I(gmch_pfit.control);
12636 /* pfit ratios are autocomputed by the hw on gen4+ */
12637 if (INTEL_INFO(dev)->gen < 4)
12638 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12639 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12640 }
12641
fd4daa9c
CW		 12642 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12643 if (current_config->pch_pfit.enabled) {
12644 PIPE_CONF_CHECK_I(pch_pfit.pos);
12645 PIPE_CONF_CHECK_I(pch_pfit.size);
12646 }
2fa2fe9a 12647
a1b2278e
CK		 12648 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12649
e59150dc
JB		 12650 /* BDW+ don't expose a synchronous way to read the state */
12651 if (IS_HASWELL(dev))
12652 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12653
282740f7
VS		 12654 PIPE_CONF_CHECK_I(double_wide);
12655
26804afd
DV		 12656 PIPE_CONF_CHECK_X(ddi_pll_sel);
12657
c0d43d62 12658 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12659 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12660 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12661 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12662 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12663 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12664 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12665 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12666 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12667
42571aef
VS		 12668 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12669 PIPE_CONF_CHECK_I(pipe_bpp);
12670
2d112de7 12671 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12672 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12673
66e985c0 12674#undef PIPE_CONF_CHECK_X
08a24034 12675#undef PIPE_CONF_CHECK_I
b95af8be 12676#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12677#undef PIPE_CONF_CHECK_FLAGS
5e550656 12678#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12679#undef PIPE_CONF_QUIRK
cfb23ed6 12680#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12681
cfb23ed6 12682 return ret;
0e8ffe1b
DV		 12683}
12684
08db6652
DL		 12685static void check_wm_state(struct drm_device *dev)
12686{
12687 struct drm_i915_private *dev_priv = dev->dev_private;
12688 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12689 struct intel_crtc *intel_crtc;
12690 int plane;
12691
12692 if (INTEL_INFO(dev)->gen < 9)
12693 return;
12694
12695 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12696 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12697
12698 for_each_intel_crtc(dev, intel_crtc) {
12699 struct skl_ddb_entry *hw_entry, *sw_entry;
12700 const enum pipe pipe = intel_crtc->pipe;
12701
12702 if (!intel_crtc->active)
12703 continue;
12704
12705 /* planes */
dd740780 12706 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12707 hw_entry = &hw_ddb.plane[pipe][plane];
12708 sw_entry = &sw_ddb->plane[pipe][plane];
12709
12710 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12711 continue;
12712
12713 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12714 "(expected (%u,%u), found (%u,%u))\n",
12715 pipe_name(pipe), plane + 1,
12716 sw_entry->start, sw_entry->end,
12717 hw_entry->start, hw_entry->end);
12718 }
12719
12720 /* cursor */
12721 hw_entry = &hw_ddb.cursor[pipe];
12722 sw_entry = &sw_ddb->cursor[pipe];
12723
12724 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12725 continue;
12726
12727 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12728 "(expected (%u,%u), found (%u,%u))\n",
12729 pipe_name(pipe),
12730 sw_entry->start, sw_entry->end,
12731 hw_entry->start, hw_entry->end);
12732 }
12733}
12734
91d1b4bd
DV		 12735static void
12736check_connector_state(struct drm_device *dev)
8af6cf88 12737{
8af6cf88
DV		 12738 struct intel_connector *connector;
12739
3a3371ff 12740 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12741 /* This also checks the encoder/connector hw state with the
12742 * ->get_hw_state callbacks. */
12743 intel_connector_check_state(connector);
12744
e2c719b7 12745 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12746 "connector's staged encoder doesn't match current encoder\n");
12747 }
91d1b4bd
DV		 12748}
12749
12750static void
12751check_encoder_state(struct drm_device *dev)
12752{
12753 struct intel_encoder *encoder;
12754 struct intel_connector *connector;
8af6cf88 12755
b2784e15 12756 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12757 bool enabled = false;
12758 bool active = false;
12759 enum pipe pipe, tracked_pipe;
12760
12761 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12762 encoder->base.base.id,
8e329a03 12763 encoder->base.name);
8af6cf88 12764
e2c719b7 12765 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12766 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12767 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12768 "encoder's active_connectors set, but no crtc\n");
12769
3a3371ff 12770 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12771 if (connector->base.encoder != &encoder->base)
12772 continue;
12773 enabled = true;
12774 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12775 active = true;
12776 }
0e32b39c
DA		 12777 /*
12778 * for MST connectors if we unplug the connector is gone
12779 * away but the encoder is still connected to a crtc
12780 * until a modeset happens in response to the hotplug.
12781 */
12782 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12783 continue;
12784
e2c719b7 12785 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12786 "encoder's enabled state mismatch "
12787 "(expected %i, found %i)\n",
12788 !!encoder->base.crtc, enabled);
e2c719b7 12789 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12790 "active encoder with no crtc\n");
12791
e2c719b7 12792 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12793 "encoder's computed active state doesn't match tracked active state "
12794 "(expected %i, found %i)\n", active, encoder->connectors_active);
12795
12796 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12797 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12798 "encoder's hw state doesn't match sw tracking "
12799 "(expected %i, found %i)\n",
12800 encoder->connectors_active, active);
12801
12802 if (!encoder->base.crtc)
12803 continue;
12804
12805 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12806 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12807 "active encoder's pipe doesn't match"
12808 "(expected %i, found %i)\n",
12809 tracked_pipe, pipe);
12810
12811 }
91d1b4bd
DV		 12812}
12813
12814static void
12815check_crtc_state(struct drm_device *dev)
12816{
fbee40df 12817 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12818 struct intel_crtc *crtc;
12819 struct intel_encoder *encoder;
5cec258b 12820 struct intel_crtc_state pipe_config;
8af6cf88 12821
d3fcc808 12822 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12823 bool enabled = false;
12824 bool active = false;
12825
045ac3b5
JB		 12826 memset(&pipe_config, 0, sizeof(pipe_config));
12827
8af6cf88
DV		 12828 DRM_DEBUG_KMS("[CRTC:%d]\n",
12829 crtc->base.base.id);
12830
83d65738 12831 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12832 "active crtc, but not enabled in sw tracking\n");
12833
b2784e15 12834 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12835 if (encoder->base.crtc != &crtc->base)
12836 continue;
12837 enabled = true;
12838 if (encoder->connectors_active)
12839 active = true;
12840 }
6c49f241 12841
e2c719b7 12842 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12843 "crtc's computed active state doesn't match tracked active state "
12844 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12845 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12846 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12847 "(expected %i, found %i)\n", enabled,
12848 crtc->base.state->enable);
8af6cf88 12849
0e8ffe1b
DV		 12850 active = dev_priv->display.get_pipe_config(crtc,
12851 &pipe_config);
d62cf62a 12852
b6b5d049
VS		 12853 /* hw state is inconsistent with the pipe quirk */
12854 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12855 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12856 active = crtc->active;
12857
b2784e15 12858 for_each_intel_encoder(dev, encoder) {
3eaba51c 12859 enum pipe pipe;
6c49f241
DV		 12860 if (encoder->base.crtc != &crtc->base)
12861 continue;
1d37b689 12862 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12863 encoder->get_config(encoder, &pipe_config);
12864 }
12865
e2c719b7 12866 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12867 "crtc active state doesn't match with hw state "
12868 "(expected %i, found %i)\n", crtc->active, active);
12869
53d9f4e9
ML		 12870 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12871 "transitional active state does not match atomic hw state "
12872 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12873
cfb23ed6
ML		 12874 if (!active)
12875 continue;
12876
12877 if (!intel_pipe_config_compare(dev, crtc->config,
12878 &pipe_config, false)) {
e2c719b7 12879 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12880 intel_dump_pipe_config(crtc, &pipe_config,
12881 "[hw state]");
6e3c9717 12882 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12883 "[sw state]");
12884 }
8af6cf88
DV		 12885 }
12886}
12887
91d1b4bd
DV		 12888static void
12889check_shared_dpll_state(struct drm_device *dev)
12890{
fbee40df 12891 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12892 struct intel_crtc *crtc;
12893 struct intel_dpll_hw_state dpll_hw_state;
12894 int i;
5358901f
DV		 12895
12896 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12897 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12898 int enabled_crtcs = 0, active_crtcs = 0;
12899 bool active;
12900
12901 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12902
12903 DRM_DEBUG_KMS("%s\n", pll->name);
12904
12905 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12906
e2c719b7 12907 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12908 "more active pll users than references: %i vs %i\n",
3e369b76 12909 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12910 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12911 "pll in active use but not on in sw tracking\n");
e2c719b7 12912 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12913 "pll in on but not on in use in sw tracking\n");
e2c719b7 12914 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12915 "pll on state mismatch (expected %i, found %i)\n",
12916 pll->on, active);
12917
d3fcc808 12918 for_each_intel_crtc(dev, crtc) {
83d65738 12919 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12920 enabled_crtcs++;
12921 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12922 active_crtcs++;
12923 }
e2c719b7 12924 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12925 "pll active crtcs mismatch (expected %i, found %i)\n",
12926 pll->active, active_crtcs);
e2c719b7 12927 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12928 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12929 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12930
e2c719b7 12931 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12932 sizeof(dpll_hw_state)),
12933 "pll hw state mismatch\n");
5358901f 12934 }
8af6cf88
DV		 12935}
12936
91d1b4bd
DV		 12937void
12938intel_modeset_check_state(struct drm_device *dev)
12939{
08db6652 12940 check_wm_state(dev);
91d1b4bd
DV		 12941 check_connector_state(dev);
12942 check_encoder_state(dev);
12943 check_crtc_state(dev);
12944 check_shared_dpll_state(dev);
12945}
12946
5cec258b 12947void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12948 int dotclock)
12949{
12950 /*
12951 * FDI already provided one idea for the dotclock.
12952 * Yell if the encoder disagrees.
12953 */
2d112de7 12954 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12955 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12956 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12957}
12958
80715b2f
VS		 12959static void update_scanline_offset(struct intel_crtc *crtc)
12960{
12961 struct drm_device *dev = crtc->base.dev;
12962
12963 /*
12964 * The scanline counter increments at the leading edge of hsync.
12965 *
12966 * On most platforms it starts counting from vtotal-1 on the
12967 * first active line. That means the scanline counter value is
12968 * always one less than what we would expect. Ie. just after
12969 * start of vblank, which also occurs at start of hsync (on the
12970 * last active line), the scanline counter will read vblank_start-1.
12971 *
12972 * On gen2 the scanline counter starts counting from 1 instead
12973 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12974 * to keep the value positive), instead of adding one.
12975 *
12976 * On HSW+ the behaviour of the scanline counter depends on the output
12977 * type. For DP ports it behaves like most other platforms, but on HDMI
12978 * there's an extra 1 line difference. So we need to add two instead of
12979 * one to the value.
12980 */
12981 if (IS_GEN2(dev)) {
6e3c9717 12982 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12983 int vtotal;
12984
12985 vtotal = mode->crtc_vtotal;
12986 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12987 vtotal /= 2;
12988
12989 crtc->scanline_offset = vtotal - 1;
12990 } else if (HAS_DDI(dev) &&
409ee761 12991 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12992 crtc->scanline_offset = 2;
12993 } else
12994 crtc->scanline_offset = 1;
12995}
12996
ad421372 12997static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12998{
225da59b 12999 struct drm_device *dev = state->dev;
ed6739ef 13000 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 13001 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 13002 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 13003 struct intel_crtc_state *intel_crtc_state;
13004 struct drm_crtc *crtc;
13005 struct drm_crtc_state *crtc_state;
0a9ab303 13006 int i;
ed6739ef
ACO		 13007
13008 if (!dev_priv->display.crtc_compute_clock)
ad421372 13009 return;
ed6739ef 13010
0a9ab303 13011 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 13012 int dpll;
13013
0a9ab303 13014 intel_crtc = to_intel_crtc(crtc);
4978cc93 13015 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 13016 dpll = intel_crtc_state->shared_dpll;
0a9ab303 13017
ad421372 13018 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 13019 continue;
13020
ad421372 13021 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 13022
ad421372
ML		 13023 if (!shared_dpll)
13024 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 13025
ad421372
ML		 13026 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13027 }
ed6739ef
ACO		 13028}
13029
99d736a2
ML		 13030/*
13031 * This implements the workaround described in the "notes" section of the mode
13032 * set sequence documentation. When going from no pipes or single pipe to
13033 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13034 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13035 */
13036static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13037{
13038 struct drm_crtc_state *crtc_state;
13039 struct intel_crtc *intel_crtc;
13040 struct drm_crtc *crtc;
13041 struct intel_crtc_state *first_crtc_state = NULL;
13042 struct intel_crtc_state *other_crtc_state = NULL;
13043 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13044 int i;
13045
13046 /* look at all crtc's that are going to be enabled in during modeset */
13047 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13048 intel_crtc = to_intel_crtc(crtc);
13049
13050 if (!crtc_state->active || !needs_modeset(crtc_state))
13051 continue;
13052
13053 if (first_crtc_state) {
13054 other_crtc_state = to_intel_crtc_state(crtc_state);
13055 break;
13056 } else {
13057 first_crtc_state = to_intel_crtc_state(crtc_state);
13058 first_pipe = intel_crtc->pipe;
13059 }
13060 }
13061
13062 /* No workaround needed? */
13063 if (!first_crtc_state)
13064 return 0;
13065
13066 /* w/a possibly needed, check how many crtc's are already enabled. */
13067 for_each_intel_crtc(state->dev, intel_crtc) {
13068 struct intel_crtc_state *pipe_config;
13069
13070 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13071 if (IS_ERR(pipe_config))
13072 return PTR_ERR(pipe_config);
13073
13074 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13075
13076 if (!pipe_config->base.active ||
13077 needs_modeset(&pipe_config->base))
13078 continue;
13079
13080 /* 2 or more enabled crtcs means no need for w/a */
13081 if (enabled_pipe != INVALID_PIPE)
13082 return 0;
13083
13084 enabled_pipe = intel_crtc->pipe;
13085 }
13086
13087 if (enabled_pipe != INVALID_PIPE)
13088 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13089 else if (other_crtc_state)
13090 other_crtc_state->hsw_workaround_pipe = first_pipe;
13091
13092 return 0;
13093}
13094
27c329ed
ML		 13095static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13096{
13097 struct drm_crtc *crtc;
13098 struct drm_crtc_state *crtc_state;
13099 int ret = 0;
13100
13101 /* add all active pipes to the state */
13102 for_each_crtc(state->dev, crtc) {
13103 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13104 if (IS_ERR(crtc_state))
13105 return PTR_ERR(crtc_state);
13106
13107 if (!crtc_state->active || needs_modeset(crtc_state))
13108 continue;
13109
13110 crtc_state->mode_changed = true;
13111
13112 ret = drm_atomic_add_affected_connectors(state, crtc);
13113 if (ret)
13114 break;
13115
13116 ret = drm_atomic_add_affected_planes(state, crtc);
13117 if (ret)
13118 break;
13119 }
13120
13121 return ret;
13122}
13123
13124
054518dd 13125/* Code that should eventually be part of atomic_check() */
c347a676 13126static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 13127{
13128 struct drm_device *dev = state->dev;
27c329ed 13129 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 13130 int ret;
13131
b359283a
ML		 13132 if (!check_digital_port_conflicts(state)) {
13133 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13134 return -EINVAL;
13135 }
13136
054518dd
ACO		 13137 /*
13138 * See if the config requires any additional preparation, e.g.
13139 * to adjust global state with pipes off. We need to do this
13140 * here so we can get the modeset_pipe updated config for the new
13141 * mode set on this crtc. For other crtcs we need to use the
13142 * adjusted_mode bits in the crtc directly.
13143 */
27c329ed
ML		 13144 if (dev_priv->display.modeset_calc_cdclk) {
13145 unsigned int cdclk;
b432e5cf 13146
27c329ed
ML		 13147 ret = dev_priv->display.modeset_calc_cdclk(state);
13148
13149 cdclk = to_intel_atomic_state(state)->cdclk;
13150 if (!ret && cdclk != dev_priv->cdclk_freq)
13151 ret = intel_modeset_all_pipes(state);
13152
13153 if (ret < 0)
054518dd 13154 return ret;
27c329ed
ML		 13155 } else
13156 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13157
ad421372 13158 intel_modeset_clear_plls(state);
054518dd 13159
99d736a2 13160 if (IS_HASWELL(dev))
ad421372 13161 return haswell_mode_set_planes_workaround(state);
99d736a2 13162
ad421372 13163 return 0;
c347a676
ACO		 13164}
13165
13166static int
13167intel_modeset_compute_config(struct drm_atomic_state *state)
13168{
13169 struct drm_crtc *crtc;
13170 struct drm_crtc_state *crtc_state;
13171 int ret, i;
61333b60 13172 bool any_ms = false;
c347a676
ACO		 13173
13174 ret = drm_atomic_helper_check_modeset(state->dev, state);
054518dd
ACO		 13175 if (ret)
13176 return ret;
13177
c347a676 13178 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 13179 struct intel_crtc_state *pipe_config =
13180 to_intel_crtc_state(crtc_state);
13181 bool modeset, recalc;
13182
61333b60
ML		 13183 if (!crtc_state->enable) {
13184 if (needs_modeset(crtc_state))
13185 any_ms = true;
c347a676 13186 continue;
61333b60 13187 }
c347a676 13188
cfb23ed6 13189 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
d032ffa0
ML		 13190 ret = drm_atomic_add_affected_planes(state, crtc);
13191 if (ret)
13192 return ret;
13193
13194 /*
13195 * We ought to handle i915.fastboot here.
13196 * If no modeset is required and the primary plane has
13197 * a fb, update the members of crtc_state as needed,
13198 * and run the necessary updates during vblank evasion.
13199 */
13200 }
13201
cfb23ed6
ML		 13202 modeset = needs_modeset(crtc_state);
13203 recalc = pipe_config->quirks & PIPE_CONFIG_QUIRK_INHERITED_MODE;
13204
13205 if (!modeset && !recalc)
13206 continue;
13207
13208 if (recalc) {
b359283a
ML		 13209 ret = drm_atomic_add_affected_connectors(state, crtc);
13210 if (ret)
13211 return ret;
13212 }
13213
cfb23ed6 13214 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13215 if (ret)
13216 return ret;
13217
cfb23ed6
ML		 13218 if (recalc && !intel_pipe_config_compare(state->dev,
13219 to_intel_crtc_state(crtc->state),
13220 pipe_config, true)) {
13221 modeset = crtc_state->mode_changed = true;
13222
13223 ret = drm_atomic_add_affected_planes(state, crtc);
13224 if (ret)
13225 return ret;
13226 }
61333b60 13227
cfb23ed6 13228 any_ms = modeset;
c347a676 13229 intel_dump_pipe_config(to_intel_crtc(crtc),
cfb23ed6
ML		 13230 pipe_config,
13231 modeset ? "[modeset]" : "[fastboot]");
c347a676
ACO		 13232 }
13233
61333b60
ML		 13234 if (any_ms) {
13235 ret = intel_modeset_checks(state);
13236
13237 if (ret)
13238 return ret;
27c329ed
ML		 13239 } else
13240 to_intel_atomic_state(state)->cdclk =
13241 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13242
13243 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13244}
13245
c72d969b 13246static int __intel_set_mode(struct drm_atomic_state *state)
a6778b3c 13247{
c72d969b 13248 struct drm_device *dev = state->dev;
fbee40df 13249 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13250 struct drm_crtc *crtc;
13251 struct drm_crtc_state *crtc_state;
c0c36b94 13252 int ret = 0;
0a9ab303 13253 int i;
61333b60 13254 bool any_ms = false;
a6778b3c 13255
d4afb8cc
ACO		 13256 ret = drm_atomic_helper_prepare_planes(dev, state);
13257 if (ret)
13258 return ret;
13259
1c5e19f8
ML		 13260 drm_atomic_helper_swap_state(dev, state);
13261
0a9ab303 13262 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13264
61333b60
ML		 13265 if (!needs_modeset(crtc->state))
13266 continue;
13267
13268 any_ms = true;
a539205a 13269 intel_pre_plane_update(intel_crtc);
460da916 13270
a539205a
ML		 13271 if (crtc_state->active) {
13272 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13273 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13274 intel_crtc->active = false;
13275 intel_disable_shared_dpll(intel_crtc);
a539205a 13276 }
b8cecdf5 13277 }
7758a113 13278
ea9d758d
DV		 13279 /* Only after disabling all output pipelines that will be changed can we
13280 * update the the output configuration. */
0a9ab303 13281 intel_modeset_update_state(state);
f6e5b160 13282
a821fc46
ACO		 13283 /* The state has been swaped above, so state actually contains the
13284 * old state now. */
61333b60
ML		 13285 if (any_ms)
13286 modeset_update_crtc_power_domains(state);
47fab737 13287
a6778b3c 13288 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13289 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13290 if (needs_modeset(crtc->state) && crtc->state->active) {
13291 update_scanline_offset(to_intel_crtc(crtc));
13292 dev_priv->display.crtc_enable(crtc);
13293 }
80715b2f 13294
a539205a 13295 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
80715b2f 13296 }
a6778b3c 13297
a6778b3c 13298 /* FIXME: add subpixel order */
83a57153 13299
d4afb8cc
ACO		 13300 drm_atomic_helper_cleanup_planes(dev, state);
13301
2bfb4627
ACO		 13302 drm_atomic_state_free(state);
13303
9eb45f22 13304 return 0;
f6e5b160
CW		 13305}
13306
568c634a 13307static int intel_set_mode_checked(struct drm_atomic_state *state)
f30da187 13308{
568c634a 13309 struct drm_device *dev = state->dev;
f30da187
DV		 13310 int ret;
13311
568c634a 13312 ret = __intel_set_mode(state);
f30da187 13313 if (ret == 0)
568c634a 13314 intel_modeset_check_state(dev);
f30da187
DV		 13315
13316 return ret;
13317}
13318
568c634a 13319static int intel_set_mode(struct drm_atomic_state *state)
7f27126e 13320{
568c634a 13321 int ret;
83a57153 13322
568c634a 13323 ret = intel_modeset_compute_config(state);
83a57153 13324 if (ret)
568c634a 13325 return ret;
7f27126e 13326
568c634a 13327 return intel_set_mode_checked(state);
7f27126e
JB		 13328}
13329
c0c36b94
CW		 13330void intel_crtc_restore_mode(struct drm_crtc *crtc)
13331{
83a57153
ACO		 13332 struct drm_device *dev = crtc->dev;
13333 struct drm_atomic_state *state;
13334 struct intel_encoder *encoder;
13335 struct intel_connector *connector;
13336 struct drm_connector_state *connector_state;
4be07317 13337 struct intel_crtc_state *crtc_state;
2bfb4627 13338 int ret;
83a57153
ACO		 13339
13340 state = drm_atomic_state_alloc(dev);
13341 if (!state) {
13342 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13343 crtc->base.id);
13344 return;
13345 }
13346
13347 state->acquire_ctx = dev->mode_config.acquire_ctx;
13348
13349 /* The force restore path in the HW readout code relies on the staged
13350 * config still keeping the user requested config while the actual
13351 * state has been overwritten by the configuration read from HW. We
13352 * need to copy the staged config to the atomic state, otherwise the
13353 * mode set will just reapply the state the HW is already in. */
13354 for_each_intel_encoder(dev, encoder) {
13355 if (&encoder->new_crtc->base != crtc)
13356 continue;
13357
13358 for_each_intel_connector(dev, connector) {
13359 if (connector->new_encoder != encoder)
13360 continue;
13361
13362 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13363 if (IS_ERR(connector_state)) {
13364 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13365 connector->base.base.id,
13366 connector->base.name,
13367 PTR_ERR(connector_state));
13368 continue;
13369 }
13370
13371 connector_state->crtc = crtc;
13372 connector_state->best_encoder = &encoder->base;
13373 }
13374 }
13375
4ed9fb37
ACO		 13376 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13377 if (IS_ERR(crtc_state)) {
13378 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13379 crtc->base.id, PTR_ERR(crtc_state));
13380 drm_atomic_state_free(state);
13381 return;
13382 }
4be07317 13383
4ed9fb37
ACO		 13384 crtc_state->base.active = crtc_state->base.enable =
13385 to_intel_crtc(crtc)->new_enabled;
8c7b5ccb 13386
4ed9fb37 13387 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317 13388
d3a40d1b
ACO		 13389 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13390 crtc->primary->fb, crtc->x, crtc->y);
13391
568c634a 13392 ret = intel_set_mode(state);
2bfb4627
ACO		 13393 if (ret)
13394 drm_atomic_state_free(state);
c0c36b94
CW		 13395}
13396
25c5b266
DV		 13397#undef for_each_intel_crtc_masked
13398
b7885264
ACO		 13399static bool intel_connector_in_mode_set(struct intel_connector *connector,
13400 struct drm_mode_set *set)
13401{
13402 int ro;
13403
13404 for (ro = 0; ro < set->num_connectors; ro++)
13405 if (set->connectors[ro] == &connector->base)
13406 return true;
13407
13408 return false;
13409}
13410
2e431051 13411static int
9a935856
DV		 13412intel_modeset_stage_output_state(struct drm_device *dev,
13413 struct drm_mode_set *set,
944b0c76 13414 struct drm_atomic_state *state)
50f56119 13415{
9a935856 13416 struct intel_connector *connector;
d5432a9d 13417 struct drm_connector *drm_connector;
944b0c76 13418 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13419 struct drm_crtc *crtc;
13420 struct drm_crtc_state *crtc_state;
13421 int i, ret;
50f56119 13422
9abdda74 13423 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13424 * of connectors. For paranoia, double-check this. */
13425 WARN_ON(!set->fb && (set->num_connectors != 0));
13426 WARN_ON(set->fb && (set->num_connectors == 0));
13427
3a3371ff 13428 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13429 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13430
d5432a9d
ACO		 13431 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13432 continue;
13433
13434 connector_state =
13435 drm_atomic_get_connector_state(state, &connector->base);
13436 if (IS_ERR(connector_state))
13437 return PTR_ERR(connector_state);
13438
b7885264
ACO		 13439 if (in_mode_set) {
13440 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13441 connector_state->best_encoder =
13442 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13443 }
13444
d5432a9d 13445 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13446 continue;
13447
9a935856
DV		 13448 /* If we disable the crtc, disable all its connectors. Also, if
13449 * the connector is on the changing crtc but not on the new
13450 * connector list, disable it. */
b7885264 13451 if (!set->fb || !in_mode_set) {
d5432a9d 13452 connector_state->best_encoder = NULL;
9a935856
DV		 13453
13454 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13455 connector->base.base.id,
c23cc417 13456 connector->base.name);
9a935856 13457 }
50f56119 13458 }
9a935856 13459 /* connector->new_encoder is now updated for all connectors. */
50f56119 13460
d5432a9d
ACO		 13461 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13462 connector = to_intel_connector(drm_connector);
13463
13464 if (!connector_state->best_encoder) {
13465 ret = drm_atomic_set_crtc_for_connector(connector_state,
13466 NULL);
13467 if (ret)
13468 return ret;
7668851f 13469
50f56119 13470 continue;
d5432a9d 13471 }
50f56119 13472
d5432a9d
ACO		 13473 if (intel_connector_in_mode_set(connector, set)) {
13474 struct drm_crtc *crtc = connector->base.state->crtc;
13475
13476 /* If this connector was in a previous crtc, add it
13477 * to the state. We might need to disable it. */
13478 if (crtc) {
13479 crtc_state =
13480 drm_atomic_get_crtc_state(state, crtc);
13481 if (IS_ERR(crtc_state))
13482 return PTR_ERR(crtc_state);
13483 }
13484
13485 ret = drm_atomic_set_crtc_for_connector(connector_state,
13486 set->crtc);
13487 if (ret)
13488 return ret;
13489 }
50f56119
DV		 13490
13491 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13492 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13493 connector_state->crtc)) {
5e2b584e 13494 return -EINVAL;
50f56119 13495 }
944b0c76 13496
9a935856
DV		 13497 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13498 connector->base.base.id,
c23cc417 13499 connector->base.name,
d5432a9d 13500 connector_state->crtc->base.id);
944b0c76 13501
d5432a9d
ACO		 13502 if (connector_state->best_encoder != &connector->encoder->base)
13503 connector->encoder =
13504 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13505 }
7668851f 13506
d5432a9d 13507 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13508 bool has_connectors;
13509
d5432a9d
ACO		 13510 ret = drm_atomic_add_affected_connectors(state, crtc);
13511 if (ret)
13512 return ret;
4be07317 13513
49d6fa21
ML		 13514 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13515 if (has_connectors != crtc_state->enable)
13516 crtc_state->enable =
13517 crtc_state->active = has_connectors;
7668851f
VS		 13518 }
13519
8c7b5ccb
ACO		 13520 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13521 set->fb, set->x, set->y);
13522 if (ret)
13523 return ret;
13524
13525 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13526 if (IS_ERR(crtc_state))
13527 return PTR_ERR(crtc_state);
13528
ce52299c
MR		 13529 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13530 if (ret)
13531 return ret;
8c7b5ccb
ACO		 13532
13533 if (set->num_connectors)
13534 crtc_state->active = true;
13535
2e431051
DV		 13536 return 0;
13537}
13538
13539static int intel_crtc_set_config(struct drm_mode_set *set)
13540{
13541 struct drm_device *dev;
83a57153 13542 struct drm_atomic_state *state = NULL;
2e431051 13543 int ret;
2e431051 13544
8d3e375e
DV		 13545 BUG_ON(!set);
13546 BUG_ON(!set->crtc);
13547 BUG_ON(!set->crtc->helper_private);
2e431051 13548
7e53f3a4
DV		 13549 /* Enforce sane interface api - has been abused by the fb helper. */
13550 BUG_ON(!set->mode && set->fb);
13551 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13552
2e431051
DV		 13553 if (set->fb) {
13554 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13555 set->crtc->base.id, set->fb->base.id,
13556 (int)set->num_connectors, set->x, set->y);
13557 } else {
13558 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13559 }
13560
13561 dev = set->crtc->dev;
13562
83a57153 13563 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13564 if (!state)
13565 return -ENOMEM;
83a57153
ACO		 13566
13567 state->acquire_ctx = dev->mode_config.acquire_ctx;
13568
462a425a 13569 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13570 if (ret)
7cbf41d6 13571 goto out;
2e431051 13572
568c634a
ACO		 13573 ret = intel_modeset_compute_config(state);
13574 if (ret)
7cbf41d6 13575 goto out;
50f52756 13576
1f9954d0
JB		 13577 intel_update_pipe_size(to_intel_crtc(set->crtc));
13578
568c634a 13579 ret = intel_set_mode_checked(state);
2d05eae1 13580 if (ret) {
bf67dfeb
DV		 13581 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13582 set->crtc->base.id, ret);
2d05eae1 13583 }
50f56119 13584
7cbf41d6 13585out:
2bfb4627
ACO		 13586 if (ret)
13587 drm_atomic_state_free(state);
50f56119
DV		 13588 return ret;
13589}
f6e5b160
CW		 13590
13591static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13592 .gamma_set = intel_crtc_gamma_set,
50f56119 13593 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13594 .destroy = intel_crtc_destroy,
13595 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13596 .atomic_duplicate_state = intel_crtc_duplicate_state,
13597 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13598};
13599
5358901f
DV		 13600static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13601 struct intel_shared_dpll *pll,
13602 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13603{
5358901f 13604 uint32_t val;
ee7b9f93 13605
f458ebbc 13606 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13607 return false;
13608
5358901f 13609 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13610 hw_state->dpll = val;
13611 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13612 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13613
13614 return val & DPLL_VCO_ENABLE;
13615}
13616
15bdd4cf
DV		 13617static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13618 struct intel_shared_dpll *pll)
13619{
3e369b76
ACO		 13620 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13621 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13622}
13623
e7b903d2
DV		 13624static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13625 struct intel_shared_dpll *pll)
13626{
e7b903d2 13627 /* PCH refclock must be enabled first */
89eff4be 13628 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13629
3e369b76 13630 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13631
13632 /* Wait for the clocks to stabilize. */
13633 POSTING_READ(PCH_DPLL(pll->id));
13634 udelay(150);
13635
13636 /* The pixel multiplier can only be updated once the
13637 * DPLL is enabled and the clocks are stable.
13638 *
13639 * So write it again.
13640 */
3e369b76 13641 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13642 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13643 udelay(200);
13644}
13645
13646static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13647 struct intel_shared_dpll *pll)
13648{
13649 struct drm_device *dev = dev_priv->dev;
13650 struct intel_crtc *crtc;
e7b903d2
DV		 13651
13652 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13653 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13654 if (intel_crtc_to_shared_dpll(crtc) == pll)
13655 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13656 }
13657
15bdd4cf
DV		 13658 I915_WRITE(PCH_DPLL(pll->id), 0);
13659 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13660 udelay(200);
13661}
13662
46edb027
DV		 13663static char *ibx_pch_dpll_names[] = {
13664 "PCH DPLL A",
13665 "PCH DPLL B",
13666};
13667
7c74ade1 13668static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13669{
e7b903d2 13670 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13671 int i;
13672
7c74ade1 13673 dev_priv->num_shared_dpll = 2;
ee7b9f93 13674
e72f9fbf 13675 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13676 dev_priv->shared_dplls[i].id = i;
13677 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13678 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13679 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13680 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13681 dev_priv->shared_dplls[i].get_hw_state =
13682 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13683 }
13684}
13685
7c74ade1
DV		 13686static void intel_shared_dpll_init(struct drm_device *dev)
13687{
e7b903d2 13688 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13689
b6283055
VS		 13690 intel_update_cdclk(dev);
13691
9cd86933
DV		 13692 if (HAS_DDI(dev))
13693 intel_ddi_pll_init(dev);
13694 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13695 ibx_pch_dpll_init(dev);
13696 else
13697 dev_priv->num_shared_dpll = 0;
13698
13699 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13700}
13701
6beb8c23
MR		 13702/**
13703 * intel_prepare_plane_fb - Prepare fb for usage on plane
13704 * @plane: drm plane to prepare for
13705 * @fb: framebuffer to prepare for presentation
13706 *
13707 * Prepares a framebuffer for usage on a display plane. Generally this
13708 * involves pinning the underlying object and updating the frontbuffer tracking
13709 * bits. Some older platforms need special physical address handling for
13710 * cursor planes.
13711 *
13712 * Returns 0 on success, negative error code on failure.
13713 */
13714int
13715intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13716 struct drm_framebuffer *fb,
13717 const struct drm_plane_state *new_state)
465c120c
MR		 13718{
13719 struct drm_device *dev = plane->dev;
6beb8c23 13720 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13721 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13722 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13723 int ret = 0;
465c120c 13724
ea2c67bb 13725 if (!obj)
465c120c
MR		 13726 return 0;
13727
6beb8c23 13728 mutex_lock(&dev->struct_mutex);
465c120c 13729
6beb8c23
MR		 13730 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13731 INTEL_INFO(dev)->cursor_needs_physical) {
13732 int align = IS_I830(dev) ? 16 * 1024 : 256;
13733 ret = i915_gem_object_attach_phys(obj, align);
13734 if (ret)
13735 DRM_DEBUG_KMS("failed to attach phys object\n");
13736 } else {
91af127f 13737 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13738 }
465c120c 13739
6beb8c23 13740 if (ret == 0)
a9ff8714 13741 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13742
4c34574f 13743 mutex_unlock(&dev->struct_mutex);
465c120c 13744
6beb8c23
MR		 13745 return ret;
13746}
13747
38f3ce3a
MR		 13748/**
13749 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13750 * @plane: drm plane to clean up for
13751 * @fb: old framebuffer that was on plane
13752 *
13753 * Cleans up a framebuffer that has just been removed from a plane.
13754 */
13755void
13756intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13757 struct drm_framebuffer *fb,
13758 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13759{
13760 struct drm_device *dev = plane->dev;
13761 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13762
13763 if (WARN_ON(!obj))
13764 return;
13765
13766 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13767 !INTEL_INFO(dev)->cursor_needs_physical) {
13768 mutex_lock(&dev->struct_mutex);
82bc3b2d 13769 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13770 mutex_unlock(&dev->struct_mutex);
13771 }
465c120c
MR		 13772}
13773
6156a456
CK		 13774int
13775skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13776{
13777 int max_scale;
13778 struct drm_device *dev;
13779 struct drm_i915_private *dev_priv;
13780 int crtc_clock, cdclk;
13781
13782 if (!intel_crtc || !crtc_state)
13783 return DRM_PLANE_HELPER_NO_SCALING;
13784
13785 dev = intel_crtc->base.dev;
13786 dev_priv = dev->dev_private;
13787 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13788 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13789
13790 if (!crtc_clock || !cdclk)
13791 return DRM_PLANE_HELPER_NO_SCALING;
13792
13793 /*
13794 * skl max scale is lower of:
13795 * close to 3 but not 3, -1 is for that purpose
13796 * or
13797 * cdclk/crtc_clock
13798 */
13799 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13800
13801 return max_scale;
13802}
13803
465c120c 13804static int
3c692a41 13805intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13806 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13807 struct intel_plane_state *state)
13808{
2b875c22
MR		 13809 struct drm_crtc *crtc = state->base.crtc;
13810 struct drm_framebuffer *fb = state->base.fb;
6156a456 13811 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13812 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13813 bool can_position = false;
465c120c 13814
061e4b8d
ML		 13815 /* use scaler when colorkey is not required */
13816 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13817 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13818 min_scale = 1;
13819 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13820 can_position = true;
6156a456 13821 }
d8106366 13822
061e4b8d
ML		 13823 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13824 &state->dst, &state->clip,
da20eabd
ML		 13825 min_scale, max_scale,
13826 can_position, true,
13827 &state->visible);
14af293f
GP		 13828}
13829
13830static void
13831intel_commit_primary_plane(struct drm_plane *plane,
13832 struct intel_plane_state *state)
13833{
2b875c22
MR		 13834 struct drm_crtc *crtc = state->base.crtc;
13835 struct drm_framebuffer *fb = state->base.fb;
13836 struct drm_device *dev = plane->dev;
14af293f 13837 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13838 struct intel_crtc *intel_crtc;
14af293f
GP		 13839 struct drm_rect *src = &state->src;
13840
ea2c67bb
MR		 13841 crtc = crtc ? crtc : plane->crtc;
13842 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13843
13844 plane->fb = fb;
9dc806fc
MR		 13845 crtc->x = src->x1 >> 16;
13846 crtc->y = src->y1 >> 16;
ccc759dc 13847
a539205a 13848 if (!crtc->state->active)
302d19ac 13849 return;
465c120c 13850
302d19ac
ML		 13851 if (state->visible)
13852 /* FIXME: kill this fastboot hack */
13853 intel_update_pipe_size(intel_crtc);
13854
13855 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13856}
13857
a8ad0d8e
ML		 13858static void
13859intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13860 struct drm_crtc *crtc)
a8ad0d8e
ML		 13861{
13862 struct drm_device *dev = plane->dev;
13863 struct drm_i915_private *dev_priv = dev->dev_private;
13864
a8ad0d8e
ML		 13865 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13866}
13867
32b7eeec 13868static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13869{
32b7eeec 13870 struct drm_device *dev = crtc->dev;
140fd38d 13871 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13873
a539205a
ML		 13874 if (!needs_modeset(crtc->state))
13875 intel_pre_plane_update(intel_crtc);
3c692a41 13876
f015c551 13877 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13878 intel_update_watermarks(crtc);
3c692a41 13879
32b7eeec 13880 intel_runtime_pm_get(dev_priv);
3c692a41 13881
c34c9ee4 13882 /* Perform vblank evasion around commit operation */
a539205a 13883 if (crtc->state->active)
c34c9ee4
MR		 13884 intel_crtc->atomic.evade =
13885 intel_pipe_update_start(intel_crtc,
13886 &intel_crtc->atomic.start_vbl_count);
0583236e
ML		 13887
13888 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13889 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13890}
13891
13892static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13893{
13894 struct drm_device *dev = crtc->dev;
13895 struct drm_i915_private *dev_priv = dev->dev_private;
13896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13897
c34c9ee4
MR		 13898 if (intel_crtc->atomic.evade)
13899 intel_pipe_update_end(intel_crtc,
13900 intel_crtc->atomic.start_vbl_count);
3c692a41 13901
140fd38d 13902 intel_runtime_pm_put(dev_priv);
3c692a41 13903
ac21b225 13904 intel_post_plane_update(intel_crtc);
3c692a41
GP		 13905}
13906
cf4c7c12 13907/**
4a3b8769
MR		 13908 * intel_plane_destroy - destroy a plane
13909 * @plane: plane to destroy
cf4c7c12 13910 *
4a3b8769
MR		 13911 * Common destruction function for all types of planes (primary, cursor,
13912 * sprite).
cf4c7c12 13913 */
4a3b8769 13914void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13915{
13916 struct intel_plane *intel_plane = to_intel_plane(plane);
13917 drm_plane_cleanup(plane);
13918 kfree(intel_plane);
13919}
13920
65a3fea0 13921const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13922 .update_plane = drm_atomic_helper_update_plane,
13923 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13924 .destroy = intel_plane_destroy,
c196e1d6 13925 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13926 .atomic_get_property = intel_plane_atomic_get_property,
13927 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13928 .atomic_duplicate_state = intel_plane_duplicate_state,
13929 .atomic_destroy_state = intel_plane_destroy_state,
13930
465c120c
MR		 13931};
13932
13933static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13934 int pipe)
13935{
13936 struct intel_plane *primary;
8e7d688b 13937 struct intel_plane_state *state;
465c120c
MR		 13938 const uint32_t *intel_primary_formats;
13939 int num_formats;
13940
13941 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13942 if (primary == NULL)
13943 return NULL;
13944
8e7d688b
MR		 13945 state = intel_create_plane_state(&primary->base);
13946 if (!state) {
ea2c67bb
MR		 13947 kfree(primary);
13948 return NULL;
13949 }
8e7d688b 13950 primary->base.state = &state->base;
ea2c67bb 13951
465c120c
MR		 13952 primary->can_scale = false;
13953 primary->max_downscale = 1;
6156a456
CK		 13954 if (INTEL_INFO(dev)->gen >= 9) {
13955 primary->can_scale = true;
af99ceda 13956 state->scaler_id = -1;
6156a456 13957 }
465c120c
MR		 13958 primary->pipe = pipe;
13959 primary->plane = pipe;
a9ff8714 13960 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13961 primary->check_plane = intel_check_primary_plane;
13962 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13963 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13964 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13965 primary->plane = !pipe;
13966
6c0fd451
DL		 13967 if (INTEL_INFO(dev)->gen >= 9) {
13968 intel_primary_formats = skl_primary_formats;
13969 num_formats = ARRAY_SIZE(skl_primary_formats);
13970 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13971 intel_primary_formats = i965_primary_formats;
13972 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13973 } else {
13974 intel_primary_formats = i8xx_primary_formats;
13975 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13976 }
13977
13978 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13979 &intel_plane_funcs,
465c120c
MR		 13980 intel_primary_formats, num_formats,
13981 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13982
3b7a5119
SJ		 13983 if (INTEL_INFO(dev)->gen >= 4)
13984 intel_create_rotation_property(dev, primary);
48404c1e 13985
ea2c67bb
MR		 13986 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13987
465c120c
MR		 13988 return &primary->base;
13989}
13990
3b7a5119
SJ		 13991void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13992{
13993 if (!dev->mode_config.rotation_property) {
13994 unsigned long flags = BIT(DRM_ROTATE_0) |
13995 BIT(DRM_ROTATE_180);
13996
13997 if (INTEL_INFO(dev)->gen >= 9)
13998 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13999
14000 dev->mode_config.rotation_property =
14001 drm_mode_create_rotation_property(dev, flags);
14002 }
14003 if (dev->mode_config.rotation_property)
14004 drm_object_attach_property(&plane->base.base,
14005 dev->mode_config.rotation_property,
14006 plane->base.state->rotation);
14007}
14008
3d7d6510 14009static int
852e787c 14010intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 14011 struct intel_crtc_state *crtc_state,
852e787c 14012 struct intel_plane_state *state)
3d7d6510 14013{
061e4b8d 14014 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 14015 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 14016 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 14017 unsigned stride;
14018 int ret;
3d7d6510 14019
061e4b8d
ML		 14020 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14021 &state->dst, &state->clip,
3d7d6510
MR		 14022 DRM_PLANE_HELPER_NO_SCALING,
14023 DRM_PLANE_HELPER_NO_SCALING,
852e787c 14024 true, true, &state->visible);
757f9a3e
GP		 14025 if (ret)
14026 return ret;
14027
757f9a3e
GP		 14028 /* if we want to turn off the cursor ignore width and height */
14029 if (!obj)
da20eabd 14030 return 0;
757f9a3e 14031
757f9a3e 14032 /* Check for which cursor types we support */
061e4b8d 14033 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 14034 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14035 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 14036 return -EINVAL;
14037 }
14038
ea2c67bb
MR		 14039 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14040 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 14041 DRM_DEBUG_KMS("buffer is too small\n");
14042 return -ENOMEM;
14043 }
14044
3a656b54 14045 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 14046 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 14047 return -EINVAL;
32b7eeec
MR		 14048 }
14049
da20eabd 14050 return 0;
852e787c 14051}
3d7d6510 14052
a8ad0d8e
ML		 14053static void
14054intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 14055 struct drm_crtc *crtc)
a8ad0d8e 14056{
a8ad0d8e
ML		 14057 intel_crtc_update_cursor(crtc, false);
14058}
14059
f4a2cf29 14060static void
852e787c
GP		 14061intel_commit_cursor_plane(struct drm_plane *plane,
14062 struct intel_plane_state *state)
14063{
2b875c22 14064 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 14065 struct drm_device *dev = plane->dev;
14066 struct intel_crtc *intel_crtc;
2b875c22 14067 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 14068 uint32_t addr;
852e787c 14069
ea2c67bb
MR		 14070 crtc = crtc ? crtc : plane->crtc;
14071 intel_crtc = to_intel_crtc(crtc);
14072
2b875c22 14073 plane->fb = state->base.fb;
ea2c67bb
MR		 14074 crtc->cursor_x = state->base.crtc_x;
14075 crtc->cursor_y = state->base.crtc_y;
14076
a912f12f
GP		 14077 if (intel_crtc->cursor_bo == obj)
14078 goto update;
4ed91096 14079
f4a2cf29 14080 if (!obj)
a912f12f 14081 addr = 0;
f4a2cf29 14082 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 14083 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 14084 else
a912f12f 14085 addr = obj->phys_handle->busaddr;
852e787c 14086
a912f12f
GP		 14087 intel_crtc->cursor_addr = addr;
14088 intel_crtc->cursor_bo = obj;
852e787c 14089
302d19ac 14090update:
a539205a 14091 if (crtc->state->active)
a912f12f 14092 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 14093}
14094
3d7d6510
MR		 14095static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14096 int pipe)
14097{
14098 struct intel_plane *cursor;
8e7d688b 14099 struct intel_plane_state *state;
3d7d6510
MR		 14100
14101 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14102 if (cursor == NULL)
14103 return NULL;
14104
8e7d688b
MR		 14105 state = intel_create_plane_state(&cursor->base);
14106 if (!state) {
ea2c67bb
MR		 14107 kfree(cursor);
14108 return NULL;
14109 }
8e7d688b 14110 cursor->base.state = &state->base;
ea2c67bb 14111
3d7d6510
MR		 14112 cursor->can_scale = false;
14113 cursor->max_downscale = 1;
14114 cursor->pipe = pipe;
14115 cursor->plane = pipe;
a9ff8714 14116 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 14117 cursor->check_plane = intel_check_cursor_plane;
14118 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 14119 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 14120
14121 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14122 &intel_plane_funcs,
3d7d6510
MR		 14123 intel_cursor_formats,
14124 ARRAY_SIZE(intel_cursor_formats),
14125 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14126
14127 if (INTEL_INFO(dev)->gen >= 4) {
14128 if (!dev->mode_config.rotation_property)
14129 dev->mode_config.rotation_property =
14130 drm_mode_create_rotation_property(dev,
14131 BIT(DRM_ROTATE_0) |
14132 BIT(DRM_ROTATE_180));
14133 if (dev->mode_config.rotation_property)
14134 drm_object_attach_property(&cursor->base.base,
14135 dev->mode_config.rotation_property,
8e7d688b 14136 state->base.rotation);
4398ad45
VS		 14137 }
14138
af99ceda
CK		 14139 if (INTEL_INFO(dev)->gen >=9)
14140 state->scaler_id = -1;
14141
ea2c67bb
MR		 14142 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14143
3d7d6510
MR		 14144 return &cursor->base;
14145}
14146
549e2bfb
CK		 14147static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14148 struct intel_crtc_state *crtc_state)
14149{
14150 int i;
14151 struct intel_scaler *intel_scaler;
14152 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14153
14154 for (i = 0; i < intel_crtc->num_scalers; i++) {
14155 intel_scaler = &scaler_state->scalers[i];
14156 intel_scaler->in_use = 0;
549e2bfb
CK		 14157 intel_scaler->mode = PS_SCALER_MODE_DYN;
14158 }
14159
14160 scaler_state->scaler_id = -1;
14161}
14162
b358d0a6 14163static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14164{
fbee40df 14165 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14166 struct intel_crtc *intel_crtc;
f5de6e07 14167 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14168 struct drm_plane *primary = NULL;
14169 struct drm_plane *cursor = NULL;
465c120c 14170 int i, ret;
79e53945 14171
955382f3 14172 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14173 if (intel_crtc == NULL)
14174 return;
14175
f5de6e07
ACO		 14176 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14177 if (!crtc_state)
14178 goto fail;
550acefd
ACO		 14179 intel_crtc->config = crtc_state;
14180 intel_crtc->base.state = &crtc_state->base;
07878248 14181 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14182
549e2bfb
CK		 14183 /* initialize shared scalers */
14184 if (INTEL_INFO(dev)->gen >= 9) {
14185 if (pipe == PIPE_C)
14186 intel_crtc->num_scalers = 1;
14187 else
14188 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14189
14190 skl_init_scalers(dev, intel_crtc, crtc_state);
14191 }
14192
465c120c 14193 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14194 if (!primary)
14195 goto fail;
14196
14197 cursor = intel_cursor_plane_create(dev, pipe);
14198 if (!cursor)
14199 goto fail;
14200
465c120c 14201 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14202 cursor, &intel_crtc_funcs);
14203 if (ret)
14204 goto fail;
79e53945
JB		 14205
14206 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14207 for (i = 0; i < 256; i++) {
14208 intel_crtc->lut_r[i] = i;
14209 intel_crtc->lut_g[i] = i;
14210 intel_crtc->lut_b[i] = i;
14211 }
14212
1f1c2e24
VS		 14213 /*
14214 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14215 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14216 */
80824003
JB		 14217 intel_crtc->pipe = pipe;
14218 intel_crtc->plane = pipe;
3a77c4c4 14219 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14220 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14221 intel_crtc->plane = !pipe;
80824003
JB		 14222 }
14223
4b0e333e
CW		 14224 intel_crtc->cursor_base = ~0;
14225 intel_crtc->cursor_cntl = ~0;
dc41c154 14226 intel_crtc->cursor_size = ~0;
8d7849db 14227
852eb00d
VS		 14228 intel_crtc->wm.cxsr_allowed = true;
14229
22fd0fab
JB		 14230 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14231 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14232 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14233 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14234
79e53945 14235 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14236
14237 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14238 return;
14239
14240fail:
14241 if (primary)
14242 drm_plane_cleanup(primary);
14243 if (cursor)
14244 drm_plane_cleanup(cursor);
f5de6e07 14245 kfree(crtc_state);
3d7d6510 14246 kfree(intel_crtc);
79e53945
JB		 14247}
14248
752aa88a
JB		 14249enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14250{
14251 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14252 struct drm_device *dev = connector->base.dev;
752aa88a 14253
51fd371b 14254 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14255
d3babd3f 14256 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14257 return INVALID_PIPE;
14258
14259 return to_intel_crtc(encoder->crtc)->pipe;
14260}
14261
08d7b3d1 14262int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14263 struct drm_file *file)
08d7b3d1 14264{
08d7b3d1 14265 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14266 struct drm_crtc *drmmode_crtc;
c05422d5 14267 struct intel_crtc *crtc;
08d7b3d1 14268
7707e653 14269 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14270
7707e653 14271 if (!drmmode_crtc) {
08d7b3d1 14272 DRM_ERROR("no such CRTC id\n");
3f2c2057 14273 return -ENOENT;
08d7b3d1
CW		 14274 }
14275
7707e653 14276 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14277 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14278
c05422d5 14279 return 0;
08d7b3d1
CW		 14280}
14281
66a9278e 14282static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14283{
66a9278e
DV		 14284 struct drm_device *dev = encoder->base.dev;
14285 struct intel_encoder *source_encoder;
79e53945 14286 int index_mask = 0;
79e53945
JB		 14287 int entry = 0;
14288
b2784e15 14289 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14290 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14291 index_mask |= (1 << entry);
14292
79e53945
JB		 14293 entry++;
14294 }
4ef69c7a 14295
79e53945
JB		 14296 return index_mask;
14297}
14298
4d302442
CW		 14299static bool has_edp_a(struct drm_device *dev)
14300{
14301 struct drm_i915_private *dev_priv = dev->dev_private;
14302
14303 if (!IS_MOBILE(dev))
14304 return false;
14305
14306 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14307 return false;
14308
e3589908 14309 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14310 return false;
14311
14312 return true;
14313}
14314
84b4e042
JB		 14315static bool intel_crt_present(struct drm_device *dev)
14316{
14317 struct drm_i915_private *dev_priv = dev->dev_private;
14318
884497ed
DL		 14319 if (INTEL_INFO(dev)->gen >= 9)
14320 return false;
14321
cf404ce4 14322 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14323 return false;
14324
14325 if (IS_CHERRYVIEW(dev))
14326 return false;
14327
14328 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14329 return false;
14330
14331 return true;
14332}
14333
79e53945
JB		 14334static void intel_setup_outputs(struct drm_device *dev)
14335{
725e30ad 14336 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14337 struct intel_encoder *encoder;
cb0953d7 14338 bool dpd_is_edp = false;
79e53945 14339
c9093354 14340 intel_lvds_init(dev);
79e53945 14341
84b4e042 14342 if (intel_crt_present(dev))
79935fca 14343 intel_crt_init(dev);
cb0953d7 14344
c776eb2e
VK		 14345 if (IS_BROXTON(dev)) {
14346 /*
14347 * FIXME: Broxton doesn't support port detection via the
14348 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14349 * detect the ports.
14350 */
14351 intel_ddi_init(dev, PORT_A);
14352 intel_ddi_init(dev, PORT_B);
14353 intel_ddi_init(dev, PORT_C);
14354 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14355 int found;
14356
de31facd
JB		 14357 /*
14358 * Haswell uses DDI functions to detect digital outputs.
14359 * On SKL pre-D0 the strap isn't connected, so we assume
14360 * it's there.
14361 */
0e72a5b5 14362 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14363 /* WaIgnoreDDIAStrap: skl */
14364 if (found ||
14365 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14366 intel_ddi_init(dev, PORT_A);
14367
14368 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14369 * register */
14370 found = I915_READ(SFUSE_STRAP);
14371
14372 if (found & SFUSE_STRAP_DDIB_DETECTED)
14373 intel_ddi_init(dev, PORT_B);
14374 if (found & SFUSE_STRAP_DDIC_DETECTED)
14375 intel_ddi_init(dev, PORT_C);
14376 if (found & SFUSE_STRAP_DDID_DETECTED)
14377 intel_ddi_init(dev, PORT_D);
14378 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14379 int found;
5d8a7752 14380 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14381
14382 if (has_edp_a(dev))
14383 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14384
dc0fa718 14385 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14386 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14387 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14388 if (!found)
e2debe91 14389 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14390 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14391 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14392 }
14393
dc0fa718 14394 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14395 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14396
dc0fa718 14397 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14398 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14399
5eb08b69 14400 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14401 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14402
270b3042 14403 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14404 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14405 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14406 /*
14407 * The DP_DETECTED bit is the latched state of the DDC
14408 * SDA pin at boot. However since eDP doesn't require DDC
14409 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14410 * eDP ports may have been muxed to an alternate function.
14411 * Thus we can't rely on the DP_DETECTED bit alone to detect
14412 * eDP ports. Consult the VBT as well as DP_DETECTED to
14413 * detect eDP ports.
14414 */
d2182a66
VS		 14415 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14416 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14417 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14418 PORT_B);
e17ac6db
VS		 14419 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14420 intel_dp_is_edp(dev, PORT_B))
14421 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14422
d2182a66
VS		 14423 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14424 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14425 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14426 PORT_C);
e17ac6db
VS		 14427 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14428 intel_dp_is_edp(dev, PORT_C))
14429 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14430
9418c1f1 14431 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14432 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14433 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14434 PORT_D);
e17ac6db
VS		 14435 /* eDP not supported on port D, so don't check VBT */
14436 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14437 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14438 }
14439
3cfca973 14440 intel_dsi_init(dev);
09da55dc 14441 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14442 bool found = false;
7d57382e 14443
e2debe91 14444 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14445 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14446 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14447 if (!found && IS_G4X(dev)) {
b01f2c3a 14448 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14449 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14450 }
27185ae1 14451
3fec3d2f 14452 if (!found && IS_G4X(dev))
ab9d7c30 14453 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14454 }
13520b05
KH		 14455
14456 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14457
e2debe91 14458 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14459 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14460 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14461 }
27185ae1 14462
e2debe91 14463 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14464
3fec3d2f 14465 if (IS_G4X(dev)) {
b01f2c3a 14466 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14467 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14468 }
3fec3d2f 14469 if (IS_G4X(dev))
ab9d7c30 14470 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14471 }
27185ae1 14472
3fec3d2f 14473 if (IS_G4X(dev) &&
e7281eab 14474 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14475 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14476 } else if (IS_GEN2(dev))
79e53945
JB		 14477 intel_dvo_init(dev);
14478
103a196f 14479 if (SUPPORTS_TV(dev))
79e53945
JB		 14480 intel_tv_init(dev);
14481
0bc12bcb 14482 intel_psr_init(dev);
7c8f8a70 14483
b2784e15 14484 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14485 encoder->base.possible_crtcs = encoder->crtc_mask;
14486 encoder->base.possible_clones =
66a9278e 14487 intel_encoder_clones(encoder);
79e53945 14488 }
47356eb6 14489
dde86e2d 14490 intel_init_pch_refclk(dev);
270b3042
DV		 14491
14492 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14493}
14494
14495static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14496{
60a5ca01 14497 struct drm_device *dev = fb->dev;
79e53945 14498 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14499
ef2d633e 14500 drm_framebuffer_cleanup(fb);
60a5ca01 14501 mutex_lock(&dev->struct_mutex);
ef2d633e 14502 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14503 drm_gem_object_unreference(&intel_fb->obj->base);
14504 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14505 kfree(intel_fb);
14506}
14507
14508static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14509 struct drm_file *file,
79e53945
JB		 14510 unsigned int *handle)
14511{
14512 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14513 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14514
05394f39 14515 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14516}
14517
86c98588
RV		 14518static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14519 struct drm_file *file,
14520 unsigned flags, unsigned color,
14521 struct drm_clip_rect *clips,
14522 unsigned num_clips)
14523{
14524 struct drm_device *dev = fb->dev;
14525 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14526 struct drm_i915_gem_object *obj = intel_fb->obj;
14527
14528 mutex_lock(&dev->struct_mutex);
14529 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
14530 mutex_unlock(&dev->struct_mutex);
14531
14532 return 0;
14533}
14534
79e53945
JB		 14535static const struct drm_framebuffer_funcs intel_fb_funcs = {
14536 .destroy = intel_user_framebuffer_destroy,
14537 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14538 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14539};
14540
b321803d
DL		 14541static
14542u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14543 uint32_t pixel_format)
14544{
14545 u32 gen = INTEL_INFO(dev)->gen;
14546
14547 if (gen >= 9) {
14548 /* "The stride in bytes must not exceed the of the size of 8K
14549 * pixels and 32K bytes."
14550 */
14551 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14552 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14553 return 32*1024;
14554 } else if (gen >= 4) {
14555 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14556 return 16*1024;
14557 else
14558 return 32*1024;
14559 } else if (gen >= 3) {
14560 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14561 return 8*1024;
14562 else
14563 return 16*1024;
14564 } else {
14565 /* XXX DSPC is limited to 4k tiled */
14566 return 8*1024;
14567 }
14568}
14569
b5ea642a
DV		 14570static int intel_framebuffer_init(struct drm_device *dev,
14571 struct intel_framebuffer *intel_fb,
14572 struct drm_mode_fb_cmd2 *mode_cmd,
14573 struct drm_i915_gem_object *obj)
79e53945 14574{
6761dd31 14575 unsigned int aligned_height;
79e53945 14576 int ret;
b321803d 14577 u32 pitch_limit, stride_alignment;
79e53945 14578
dd4916c5
DV		 14579 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14580
2a80eada
DV		 14581 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14582 /* Enforce that fb modifier and tiling mode match, but only for
14583 * X-tiled. This is needed for FBC. */
14584 if (!!(obj->tiling_mode == I915_TILING_X) !=
14585 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14586 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14587 return -EINVAL;
14588 }
14589 } else {
14590 if (obj->tiling_mode == I915_TILING_X)
14591 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14592 else if (obj->tiling_mode == I915_TILING_Y) {
14593 DRM_DEBUG("No Y tiling for legacy addfb\n");
14594 return -EINVAL;
14595 }
14596 }
14597
9a8f0a12
TU		 14598 /* Passed in modifier sanity checking. */
14599 switch (mode_cmd->modifier[0]) {
14600 case I915_FORMAT_MOD_Y_TILED:
14601 case I915_FORMAT_MOD_Yf_TILED:
14602 if (INTEL_INFO(dev)->gen < 9) {
14603 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14604 mode_cmd->modifier[0]);
14605 return -EINVAL;
14606 }
14607 case DRM_FORMAT_MOD_NONE:
14608 case I915_FORMAT_MOD_X_TILED:
14609 break;
14610 default:
c0f40428
JB		 14611 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14612 mode_cmd->modifier[0]);
57cd6508 14613 return -EINVAL;
c16ed4be 14614 }
57cd6508 14615
b321803d
DL		 14616 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14617 mode_cmd->pixel_format);
14618 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14619 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14620 mode_cmd->pitches[0], stride_alignment);
57cd6508 14621 return -EINVAL;
c16ed4be 14622 }
57cd6508 14623
b321803d
DL		 14624 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14625 mode_cmd->pixel_format);
a35cdaa0 14626 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14627 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14628 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14629 "tiled" : "linear",
a35cdaa0 14630 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14631 return -EINVAL;
c16ed4be 14632 }
5d7bd705 14633
2a80eada 14634 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14635 mode_cmd->pitches[0] != obj->stride) {
14636 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14637 mode_cmd->pitches[0], obj->stride);
5d7bd705 14638 return -EINVAL;
c16ed4be 14639 }
5d7bd705 14640
57779d06 14641 /* Reject formats not supported by any plane early. */
308e5bcb 14642 switch (mode_cmd->pixel_format) {
57779d06 14643 case DRM_FORMAT_C8:
04b3924d
VS		 14644 case DRM_FORMAT_RGB565:
14645 case DRM_FORMAT_XRGB8888:
14646 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14647 break;
14648 case DRM_FORMAT_XRGB1555:
c16ed4be 14649 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14650 DRM_DEBUG("unsupported pixel format: %s\n",
14651 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14652 return -EINVAL;
c16ed4be 14653 }
57779d06 14654 break;
57779d06 14655 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14656 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14657 DRM_DEBUG("unsupported pixel format: %s\n",
14658 drm_get_format_name(mode_cmd->pixel_format));
14659 return -EINVAL;
14660 }
14661 break;
14662 case DRM_FORMAT_XBGR8888:
04b3924d 14663 case DRM_FORMAT_XRGB2101010:
57779d06 14664 case DRM_FORMAT_XBGR2101010:
c16ed4be 14665 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14666 DRM_DEBUG("unsupported pixel format: %s\n",
14667 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14668 return -EINVAL;
c16ed4be 14669 }
b5626747 14670 break;
7531208b
DL		 14671 case DRM_FORMAT_ABGR2101010:
14672 if (!IS_VALLEYVIEW(dev)) {
14673 DRM_DEBUG("unsupported pixel format: %s\n",
14674 drm_get_format_name(mode_cmd->pixel_format));
14675 return -EINVAL;
14676 }
14677 break;
04b3924d
VS		 14678 case DRM_FORMAT_YUYV:
14679 case DRM_FORMAT_UYVY:
14680 case DRM_FORMAT_YVYU:
14681 case DRM_FORMAT_VYUY:
c16ed4be 14682 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14683 DRM_DEBUG("unsupported pixel format: %s\n",
14684 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14685 return -EINVAL;
c16ed4be 14686 }
57cd6508
CW		 14687 break;
14688 default:
4ee62c76
VS		 14689 DRM_DEBUG("unsupported pixel format: %s\n",
14690 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14691 return -EINVAL;
14692 }
14693
90f9a336
VS		 14694 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14695 if (mode_cmd->offsets[0] != 0)
14696 return -EINVAL;
14697
ec2c981e 14698 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14699 mode_cmd->pixel_format,
14700 mode_cmd->modifier[0]);
53155c0a
DV		 14701 /* FIXME drm helper for size checks (especially planar formats)? */
14702 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14703 return -EINVAL;
14704
c7d73f6a
DV		 14705 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14706 intel_fb->obj = obj;
80075d49 14707 intel_fb->obj->framebuffer_references++;
c7d73f6a 14708
79e53945
JB		 14709 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14710 if (ret) {
14711 DRM_ERROR("framebuffer init failed %d\n", ret);
14712 return ret;
14713 }
14714
79e53945
JB		 14715 return 0;
14716}
14717
79e53945
JB		 14718static struct drm_framebuffer *
14719intel_user_framebuffer_create(struct drm_device *dev,
14720 struct drm_file *filp,
308e5bcb 14721 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14722{
05394f39 14723 struct drm_i915_gem_object *obj;
79e53945 14724
308e5bcb
JB		 14725 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14726 mode_cmd->handles[0]));
c8725226 14727 if (&obj->base == NULL)
cce13ff7 14728 return ERR_PTR(-ENOENT);
79e53945 14729
d2dff872 14730 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14731}
14732
4520f53a 14733#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14734static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14735{
14736}
14737#endif
14738
79e53945 14739static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14740 .fb_create = intel_user_framebuffer_create,
0632fef6 14741 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14742 .atomic_check = intel_atomic_check,
14743 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14744 .atomic_state_alloc = intel_atomic_state_alloc,
14745 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14746};
14747
e70236a8
JB		 14748/* Set up chip specific display functions */
14749static void intel_init_display(struct drm_device *dev)
14750{
14751 struct drm_i915_private *dev_priv = dev->dev_private;
14752
ee9300bb
DV		 14753 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14754 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14755 else if (IS_CHERRYVIEW(dev))
14756 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14757 else if (IS_VALLEYVIEW(dev))
14758 dev_priv->display.find_dpll = vlv_find_best_dpll;
14759 else if (IS_PINEVIEW(dev))
14760 dev_priv->display.find_dpll = pnv_find_best_dpll;
14761 else
14762 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14763
bc8d7dff
DL		 14764 if (INTEL_INFO(dev)->gen >= 9) {
14765 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14766 dev_priv->display.get_initial_plane_config =
14767 skylake_get_initial_plane_config;
bc8d7dff
DL		 14768 dev_priv->display.crtc_compute_clock =
14769 haswell_crtc_compute_clock;
14770 dev_priv->display.crtc_enable = haswell_crtc_enable;
14771 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14772 dev_priv->display.update_primary_plane =
14773 skylake_update_primary_plane;
14774 } else if (HAS_DDI(dev)) {
0e8ffe1b 14775 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14776 dev_priv->display.get_initial_plane_config =
14777 ironlake_get_initial_plane_config;
797d0259
ACO		 14778 dev_priv->display.crtc_compute_clock =
14779 haswell_crtc_compute_clock;
4f771f10
PZ		 14780 dev_priv->display.crtc_enable = haswell_crtc_enable;
14781 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14782 dev_priv->display.update_primary_plane =
14783 ironlake_update_primary_plane;
09b4ddf9 14784 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14785 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14786 dev_priv->display.get_initial_plane_config =
14787 ironlake_get_initial_plane_config;
3fb37703
ACO		 14788 dev_priv->display.crtc_compute_clock =
14789 ironlake_crtc_compute_clock;
76e5a89c
DV		 14790 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14791 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14792 dev_priv->display.update_primary_plane =
14793 ironlake_update_primary_plane;
89b667f8
JB		 14794 } else if (IS_VALLEYVIEW(dev)) {
14795 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14796 dev_priv->display.get_initial_plane_config =
14797 i9xx_get_initial_plane_config;
d6dfee7a 14798 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14799 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14800 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14801 dev_priv->display.update_primary_plane =
14802 i9xx_update_primary_plane;
f564048e 14803 } else {
0e8ffe1b 14804 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14805 dev_priv->display.get_initial_plane_config =
14806 i9xx_get_initial_plane_config;
d6dfee7a 14807 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14808 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14809 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14810 dev_priv->display.update_primary_plane =
14811 i9xx_update_primary_plane;
f564048e 14812 }
e70236a8 14813
e70236a8 14814 /* Returns the core display clock speed */
1652d19e
VS		 14815 if (IS_SKYLAKE(dev))
14816 dev_priv->display.get_display_clock_speed =
14817 skylake_get_display_clock_speed;
acd3f3d3
BP		 14818 else if (IS_BROXTON(dev))
14819 dev_priv->display.get_display_clock_speed =
14820 broxton_get_display_clock_speed;
1652d19e
VS		 14821 else if (IS_BROADWELL(dev))
14822 dev_priv->display.get_display_clock_speed =
14823 broadwell_get_display_clock_speed;
14824 else if (IS_HASWELL(dev))
14825 dev_priv->display.get_display_clock_speed =
14826 haswell_get_display_clock_speed;
14827 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14828 dev_priv->display.get_display_clock_speed =
14829 valleyview_get_display_clock_speed;
b37a6434
VS		 14830 else if (IS_GEN5(dev))
14831 dev_priv->display.get_display_clock_speed =
14832 ilk_get_display_clock_speed;
a7c66cd8 14833 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14834 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14835 dev_priv->display.get_display_clock_speed =
14836 i945_get_display_clock_speed;
34edce2f
VS		 14837 else if (IS_GM45(dev))
14838 dev_priv->display.get_display_clock_speed =
14839 gm45_get_display_clock_speed;
14840 else if (IS_CRESTLINE(dev))
14841 dev_priv->display.get_display_clock_speed =
14842 i965gm_get_display_clock_speed;
14843 else if (IS_PINEVIEW(dev))
14844 dev_priv->display.get_display_clock_speed =
14845 pnv_get_display_clock_speed;
14846 else if (IS_G33(dev) || IS_G4X(dev))
14847 dev_priv->display.get_display_clock_speed =
14848 g33_get_display_clock_speed;
e70236a8
JB		 14849 else if (IS_I915G(dev))
14850 dev_priv->display.get_display_clock_speed =
14851 i915_get_display_clock_speed;
257a7ffc 14852 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14853 dev_priv->display.get_display_clock_speed =
14854 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14855 else if (IS_PINEVIEW(dev))
14856 dev_priv->display.get_display_clock_speed =
14857 pnv_get_display_clock_speed;
e70236a8
JB		 14858 else if (IS_I915GM(dev))
14859 dev_priv->display.get_display_clock_speed =
14860 i915gm_get_display_clock_speed;
14861 else if (IS_I865G(dev))
14862 dev_priv->display.get_display_clock_speed =
14863 i865_get_display_clock_speed;
f0f8a9ce 14864 else if (IS_I85X(dev))
e70236a8 14865 dev_priv->display.get_display_clock_speed =
1b1d2716 14866 i85x_get_display_clock_speed;
623e01e5
VS		 14867 else { /* 830 */
14868 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14869 dev_priv->display.get_display_clock_speed =
14870 i830_get_display_clock_speed;
623e01e5 14871 }
e70236a8 14872
7c10a2b5 14873 if (IS_GEN5(dev)) {
3bb11b53 14874 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14875 } else if (IS_GEN6(dev)) {
14876 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14877 } else if (IS_IVYBRIDGE(dev)) {
14878 /* FIXME: detect B0+ stepping and use auto training */
14879 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14880 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14881 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14882 if (IS_BROADWELL(dev)) {
14883 dev_priv->display.modeset_commit_cdclk =
14884 broadwell_modeset_commit_cdclk;
14885 dev_priv->display.modeset_calc_cdclk =
14886 broadwell_modeset_calc_cdclk;
14887 }
30a970c6 14888 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14889 dev_priv->display.modeset_commit_cdclk =
14890 valleyview_modeset_commit_cdclk;
14891 dev_priv->display.modeset_calc_cdclk =
14892 valleyview_modeset_calc_cdclk;
f8437dd1 14893 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14894 dev_priv->display.modeset_commit_cdclk =
14895 broxton_modeset_commit_cdclk;
14896 dev_priv->display.modeset_calc_cdclk =
14897 broxton_modeset_calc_cdclk;
e70236a8 14898 }
8c9f3aaf 14899
8c9f3aaf
JB		 14900 switch (INTEL_INFO(dev)->gen) {
14901 case 2:
14902 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14903 break;
14904
14905 case 3:
14906 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14907 break;
14908
14909 case 4:
14910 case 5:
14911 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14912 break;
14913
14914 case 6:
14915 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14916 break;
7c9017e5 14917 case 7:
4e0bbc31 14918 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14919 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14920 break;
830c81db 14921 case 9:
ba343e02
TU		 14922 /* Drop through - unsupported since execlist only. */
14923 default:
14924 /* Default just returns -ENODEV to indicate unsupported */
14925 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14926 }
7bd688cd
JN		 14927
14928 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14929
14930 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14931}
14932
b690e96c
JB		 14933/*
14934 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14935 * resume, or other times. This quirk makes sure that's the case for
14936 * affected systems.
14937 */
0206e353 14938static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14939{
14940 struct drm_i915_private *dev_priv = dev->dev_private;
14941
14942 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14943 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14944}
14945
b6b5d049
VS		 14946static void quirk_pipeb_force(struct drm_device *dev)
14947{
14948 struct drm_i915_private *dev_priv = dev->dev_private;
14949
14950 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14951 DRM_INFO("applying pipe b force quirk\n");
14952}
14953
435793df
KP		 14954/*
14955 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14956 */
14957static void quirk_ssc_force_disable(struct drm_device *dev)
14958{
14959 struct drm_i915_private *dev_priv = dev->dev_private;
14960 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14961 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14962}
14963
4dca20ef 14964/*
5a15ab5b
CE		 14965 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14966 * brightness value
4dca20ef
CE		 14967 */
14968static void quirk_invert_brightness(struct drm_device *dev)
14969{
14970 struct drm_i915_private *dev_priv = dev->dev_private;
14971 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14972 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14973}
14974
9c72cc6f
SD		 14975/* Some VBT's incorrectly indicate no backlight is present */
14976static void quirk_backlight_present(struct drm_device *dev)
14977{
14978 struct drm_i915_private *dev_priv = dev->dev_private;
14979 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14980 DRM_INFO("applying backlight present quirk\n");
14981}
14982
b690e96c
JB		 14983struct intel_quirk {
14984 int device;
14985 int subsystem_vendor;
14986 int subsystem_device;
14987 void (*hook)(struct drm_device *dev);
14988};
14989
5f85f176
EE		 14990/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14991struct intel_dmi_quirk {
14992 void (*hook)(struct drm_device *dev);
14993 const struct dmi_system_id (*dmi_id_list)[];
14994};
14995
14996static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14997{
14998 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14999 return 1;
15000}
15001
15002static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15003 {
15004 .dmi_id_list = &(const struct dmi_system_id[]) {
15005 {
15006 .callback = intel_dmi_reverse_brightness,
15007 .ident = "NCR Corporation",
15008 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15009 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15010 },
15011 },
15012 { } /* terminating entry */
15013 },
15014 .hook = quirk_invert_brightness,
15015 },
15016};
15017
c43b5634 15018static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 15019 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15020 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15021
b690e96c
JB		 15022 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15023 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15024
5f080c0f
VS		 15025 /* 830 needs to leave pipe A & dpll A up */
15026 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15027
b6b5d049
VS		 15028 /* 830 needs to leave pipe B & dpll B up */
15029 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15030
435793df
KP		 15031 /* Lenovo U160 cannot use SSC on LVDS */
15032 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 15033
15034 /* Sony Vaio Y cannot use SSC on LVDS */
15035 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 15036
be505f64
AH		 15037 /* Acer Aspire 5734Z must invert backlight brightness */
15038 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15039
15040 /* Acer/eMachines G725 */
15041 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15042
15043 /* Acer/eMachines e725 */
15044 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15045
15046 /* Acer/Packard Bell NCL20 */
15047 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15048
15049 /* Acer Aspire 4736Z */
15050 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 15051
15052 /* Acer Aspire 5336 */
15053 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 15054
15055 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15056 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 15057
dfb3d47b
SD		 15058 /* Acer C720 Chromebook (Core i3 4005U) */
15059 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15060
b2a9601c 15061 /* Apple Macbook 2,1 (Core 2 T7400) */
15062 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15063
d4967d8c
SD		 15064 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15065 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 15066
15067 /* HP Chromebook 14 (Celeron 2955U) */
15068 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 15069
15070 /* Dell Chromebook 11 */
15071 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 15072};
15073
15074static void intel_init_quirks(struct drm_device *dev)
15075{
15076 struct pci_dev *d = dev->pdev;
15077 int i;
15078
15079 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15080 struct intel_quirk *q = &intel_quirks[i];
15081
15082 if (d->device == q->device &&
15083 (d->subsystem_vendor == q->subsystem_vendor ||
15084 q->subsystem_vendor == PCI_ANY_ID) &&
15085 (d->subsystem_device == q->subsystem_device ||
15086 q->subsystem_device == PCI_ANY_ID))
15087 q->hook(dev);
15088 }
5f85f176
EE		 15089 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15090 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15091 intel_dmi_quirks[i].hook(dev);
15092 }
b690e96c
JB		 15093}
15094
9cce37f4
JB		 15095/* Disable the VGA plane that we never use */
15096static void i915_disable_vga(struct drm_device *dev)
15097{
15098 struct drm_i915_private *dev_priv = dev->dev_private;
15099 u8 sr1;
766aa1c4 15100 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 15101
2b37c616 15102 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 15103 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 15104 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 15105 sr1 = inb(VGA_SR_DATA);
15106 outb(sr1 | 1<<5, VGA_SR_DATA);
15107 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15108 udelay(300);
15109
01f5a626 15110 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 15111 POSTING_READ(vga_reg);
15112}
15113
f817586c
DV		 15114void intel_modeset_init_hw(struct drm_device *dev)
15115{
b6283055 15116 intel_update_cdclk(dev);
a8f78b58 15117 intel_prepare_ddi(dev);
f817586c 15118 intel_init_clock_gating(dev);
8090c6b9 15119 intel_enable_gt_powersave(dev);
f817586c
DV		 15120}
15121
79e53945
JB		 15122void intel_modeset_init(struct drm_device *dev)
15123{
652c393a 15124 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 15125 int sprite, ret;
8cc87b75 15126 enum pipe pipe;
46f297fb 15127 struct intel_crtc *crtc;
79e53945
JB		 15128
15129 drm_mode_config_init(dev);
15130
15131 dev->mode_config.min_width = 0;
15132 dev->mode_config.min_height = 0;
15133
019d96cb
DA		 15134 dev->mode_config.preferred_depth = 24;
15135 dev->mode_config.prefer_shadow = 1;
15136
25bab385
TU		 15137 dev->mode_config.allow_fb_modifiers = true;
15138
e6ecefaa 15139 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15140
b690e96c
JB		 15141 intel_init_quirks(dev);
15142
1fa61106
ED		 15143 intel_init_pm(dev);
15144
e3c74757
BW		 15145 if (INTEL_INFO(dev)->num_pipes == 0)
15146 return;
15147
e70236a8 15148 intel_init_display(dev);
7c10a2b5 15149 intel_init_audio(dev);
e70236a8 15150
a6c45cf0
CW		 15151 if (IS_GEN2(dev)) {
15152 dev->mode_config.max_width = 2048;
15153 dev->mode_config.max_height = 2048;
15154 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15155 dev->mode_config.max_width = 4096;
15156 dev->mode_config.max_height = 4096;
79e53945 15157 } else {
a6c45cf0
CW		 15158 dev->mode_config.max_width = 8192;
15159 dev->mode_config.max_height = 8192;
79e53945 15160 }
068be561 15161
dc41c154
VS		 15162 if (IS_845G(dev) || IS_I865G(dev)) {
15163 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15164 dev->mode_config.cursor_height = 1023;
15165 } else if (IS_GEN2(dev)) {
068be561
DL		 15166 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15167 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15168 } else {
15169 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15170 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15171 }
15172
5d4545ae 15173 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15174
28c97730 15175 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15176 INTEL_INFO(dev)->num_pipes,
15177 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15178
055e393f 15179 for_each_pipe(dev_priv, pipe) {
8cc87b75 15180 intel_crtc_init(dev, pipe);
3bdcfc0c 15181 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15182 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15183 if (ret)
06da8da2 15184 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15185 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15186 }
79e53945
JB		 15187 }
15188
f42bb70d
JB		 15189 intel_init_dpio(dev);
15190
e72f9fbf 15191 intel_shared_dpll_init(dev);
ee7b9f93 15192
9cce37f4
JB		 15193 /* Just disable it once at startup */
15194 i915_disable_vga(dev);
79e53945 15195 intel_setup_outputs(dev);
11be49eb
CW		 15196
15197 /* Just in case the BIOS is doing something questionable. */
7733b49b 15198 intel_fbc_disable(dev_priv);
fa9fa083 15199
6e9f798d 15200 drm_modeset_lock_all(dev);
fa9fa083 15201 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15202 drm_modeset_unlock_all(dev);
46f297fb 15203
d3fcc808 15204 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15205 if (!crtc->active)
15206 continue;
15207
46f297fb 15208 /*
46f297fb
JB		 15209 * Note that reserving the BIOS fb up front prevents us
15210 * from stuffing other stolen allocations like the ring
15211 * on top. This prevents some ugliness at boot time, and
15212 * can even allow for smooth boot transitions if the BIOS
15213 * fb is large enough for the active pipe configuration.
15214 */
5724dbd1
DL		 15215 if (dev_priv->display.get_initial_plane_config) {
15216 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15217 &crtc->plane_config);
15218 /*
15219 * If the fb is shared between multiple heads, we'll
15220 * just get the first one.
15221 */
f6936e29 15222 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15223 }
46f297fb 15224 }
2c7111db
CW		 15225}
15226
7fad798e
DV		 15227static void intel_enable_pipe_a(struct drm_device *dev)
15228{
15229 struct intel_connector *connector;
15230 struct drm_connector *crt = NULL;
15231 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15232 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15233
15234 /* We can't just switch on the pipe A, we need to set things up with a
15235 * proper mode and output configuration. As a gross hack, enable pipe A
15236 * by enabling the load detect pipe once. */
3a3371ff 15237 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15238 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15239 crt = &connector->base;
15240 break;
15241 }
15242 }
15243
15244 if (!crt)
15245 return;
15246
208bf9fd 15247 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15248 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15249}
15250
fa555837
DV		 15251static bool
15252intel_check_plane_mapping(struct intel_crtc *crtc)
15253{
7eb552ae
BW		 15254 struct drm_device *dev = crtc->base.dev;
15255 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15256 u32 reg, val;
15257
7eb552ae 15258 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15259 return true;
15260
15261 reg = DSPCNTR(!crtc->plane);
15262 val = I915_READ(reg);
15263
15264 if ((val & DISPLAY_PLANE_ENABLE) &&
15265 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15266 return false;
15267
15268 return true;
15269}
15270
24929352
DV		 15271static void intel_sanitize_crtc(struct intel_crtc *crtc)
15272{
15273 struct drm_device *dev = crtc->base.dev;
15274 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 15275 struct intel_encoder *encoder;
fa555837 15276 u32 reg;
b17d48e2 15277 bool enable;
24929352 15278
24929352 15279 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15280 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15281 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15282
d3eaf884 15283 /* restore vblank interrupts to correct state */
9625604c 15284 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15285 if (crtc->active) {
15286 update_scanline_offset(crtc);
9625604c
DV		 15287 drm_crtc_vblank_on(&crtc->base);
15288 }
d3eaf884 15289
24929352 15290 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15291 * disable the crtc (and hence change the state) if it is wrong. Note
15292 * that gen4+ has a fixed plane -> pipe mapping. */
15293 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15294 bool plane;
15295
24929352
DV		 15296 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15297 crtc->base.base.id);
15298
15299 /* Pipe has the wrong plane attached and the plane is active.
15300 * Temporarily change the plane mapping and disable everything
15301 * ... */
15302 plane = crtc->plane;
b70709a6 15303 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15304 crtc->plane = !plane;
b17d48e2 15305 intel_crtc_disable_noatomic(&crtc->base);
24929352 15306 crtc->plane = plane;
24929352 15307 }
24929352 15308
7fad798e
DV		 15309 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15310 crtc->pipe == PIPE_A && !crtc->active) {
15311 /* BIOS forgot to enable pipe A, this mostly happens after
15312 * resume. Force-enable the pipe to fix this, the update_dpms
15313 * call below we restore the pipe to the right state, but leave
15314 * the required bits on. */
15315 intel_enable_pipe_a(dev);
15316 }
15317
24929352
DV		 15318 /* Adjust the state of the output pipe according to whether we
15319 * have active connectors/encoders. */
b17d48e2
ML		 15320 enable = false;
15321 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15322 enable |= encoder->connectors_active;
24929352 15323
b17d48e2
ML		 15324 if (!enable)
15325 intel_crtc_disable_noatomic(&crtc->base);
24929352 15326
53d9f4e9 15327 if (crtc->active != crtc->base.state->active) {
24929352
DV		 15328
15329 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15330 * functions or because of calls to intel_crtc_disable_noatomic,
15331 * or because the pipe is force-enabled due to the
24929352
DV		 15332 * pipe A quirk. */
15333 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15334 crtc->base.base.id,
83d65738 15335 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15336 crtc->active ? "enabled" : "disabled");
15337
83d65738 15338 crtc->base.state->enable = crtc->active;
49d6fa21 15339 crtc->base.state->active = crtc->active;
24929352
DV		 15340 crtc->base.enabled = crtc->active;
15341
15342 /* Because we only establish the connector -> encoder ->
15343 * crtc links if something is active, this means the
15344 * crtc is now deactivated. Break the links. connector
15345 * -> encoder links are only establish when things are
15346 * actually up, hence no need to break them. */
15347 WARN_ON(crtc->active);
15348
15349 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15350 WARN_ON(encoder->connectors_active);
15351 encoder->base.crtc = NULL;
15352 }
15353 }
c5ab3bc0 15354
a3ed6aad 15355 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15356 /*
15357 * We start out with underrun reporting disabled to avoid races.
15358 * For correct bookkeeping mark this on active crtcs.
15359 *
c5ab3bc0
DV		 15360 * Also on gmch platforms we dont have any hardware bits to
15361 * disable the underrun reporting. Which means we need to start
15362 * out with underrun reporting disabled also on inactive pipes,
15363 * since otherwise we'll complain about the garbage we read when
15364 * e.g. coming up after runtime pm.
15365 *
4cc31489
DV		 15366 * No protection against concurrent access is required - at
15367 * worst a fifo underrun happens which also sets this to false.
15368 */
15369 crtc->cpu_fifo_underrun_disabled = true;
15370 crtc->pch_fifo_underrun_disabled = true;
15371 }
24929352
DV		 15372}
15373
15374static void intel_sanitize_encoder(struct intel_encoder *encoder)
15375{
15376 struct intel_connector *connector;
15377 struct drm_device *dev = encoder->base.dev;
15378
15379 /* We need to check both for a crtc link (meaning that the
15380 * encoder is active and trying to read from a pipe) and the
15381 * pipe itself being active. */
15382 bool has_active_crtc = encoder->base.crtc &&
15383 to_intel_crtc(encoder->base.crtc)->active;
15384
15385 if (encoder->connectors_active && !has_active_crtc) {
15386 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15387 encoder->base.base.id,
8e329a03 15388 encoder->base.name);
24929352
DV		 15389
15390 /* Connector is active, but has no active pipe. This is
15391 * fallout from our resume register restoring. Disable
15392 * the encoder manually again. */
15393 if (encoder->base.crtc) {
15394 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15395 encoder->base.base.id,
8e329a03 15396 encoder->base.name);
24929352 15397 encoder->disable(encoder);
a62d1497
VS		 15398 if (encoder->post_disable)
15399 encoder->post_disable(encoder);
24929352 15400 }
7f1950fb
EE		 15401 encoder->base.crtc = NULL;
15402 encoder->connectors_active = false;
24929352
DV		 15403
15404 /* Inconsistent output/port/pipe state happens presumably due to
15405 * a bug in one of the get_hw_state functions. Or someplace else
15406 * in our code, like the register restore mess on resume. Clamp
15407 * things to off as a safer default. */
3a3371ff 15408 for_each_intel_connector(dev, connector) {
24929352
DV		 15409 if (connector->encoder != encoder)
15410 continue;
7f1950fb
EE		 15411 connector->base.dpms = DRM_MODE_DPMS_OFF;
15412 connector->base.encoder = NULL;
24929352
DV		 15413 }
15414 }
15415 /* Enabled encoders without active connectors will be fixed in
15416 * the crtc fixup. */
15417}
15418
04098753 15419void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15420{
15421 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15422 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15423
04098753
ID		 15424 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15425 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15426 i915_disable_vga(dev);
15427 }
15428}
15429
15430void i915_redisable_vga(struct drm_device *dev)
15431{
15432 struct drm_i915_private *dev_priv = dev->dev_private;
15433
8dc8a27c
PZ		 15434 /* This function can be called both from intel_modeset_setup_hw_state or
15435 * at a very early point in our resume sequence, where the power well
15436 * structures are not yet restored. Since this function is at a very
15437 * paranoid "someone might have enabled VGA while we were not looking"
15438 * level, just check if the power well is enabled instead of trying to
15439 * follow the "don't touch the power well if we don't need it" policy
15440 * the rest of the driver uses. */
f458ebbc 15441 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15442 return;
15443
04098753 15444 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15445}
15446
98ec7739
VS		 15447static bool primary_get_hw_state(struct intel_crtc *crtc)
15448{
15449 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15450
d032ffa0
ML		 15451 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15452}
15453
15454static void readout_plane_state(struct intel_crtc *crtc,
15455 struct intel_crtc_state *crtc_state)
15456{
15457 struct intel_plane *p;
15458 struct drm_plane_state *drm_plane_state;
15459 bool active = crtc_state->base.active;
15460
15461 if (active) {
15462 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15463
15464 /* apply to previous sw state too */
15465 to_intel_crtc_state(crtc->base.state)->quirks |=
15466 PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15467 }
98ec7739 15468
d032ffa0
ML		 15469 for_each_intel_plane(crtc->base.dev, p) {
15470 bool visible = active;
15471
15472 if (crtc->pipe != p->pipe)
15473 continue;
15474
15475 drm_plane_state = p->base.state;
e435d6e5
ML		 15476
15477 /* Plane scaler state is not touched here. The first atomic
15478 * commit will restore all plane scalers to its old state.
15479 */
15480
d032ffa0
ML		 15481 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15482 visible = primary_get_hw_state(crtc);
15483 to_intel_plane_state(drm_plane_state)->visible = visible;
15484 } else {
15485 /*
15486 * unknown state, assume it's off to force a transition
15487 * to on when calculating state changes.
15488 */
15489 to_intel_plane_state(drm_plane_state)->visible = false;
15490 }
15491
15492 if (visible) {
15493 crtc_state->base.plane_mask |=
15494 1 << drm_plane_index(&p->base);
15495 } else if (crtc_state->base.state) {
15496 /* Make this unconditional for atomic hw readout. */
15497 crtc_state->base.plane_mask &=
15498 ~(1 << drm_plane_index(&p->base));
15499 }
15500 }
98ec7739
VS		 15501}
15502
30e984df 15503static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15504{
15505 struct drm_i915_private *dev_priv = dev->dev_private;
15506 enum pipe pipe;
24929352
DV		 15507 struct intel_crtc *crtc;
15508 struct intel_encoder *encoder;
15509 struct intel_connector *connector;
5358901f 15510 int i;
24929352 15511
d3fcc808 15512 for_each_intel_crtc(dev, crtc) {
6e3c9717 15513 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15514 crtc->config->base.crtc = &crtc->base;
3b117c8f 15515
6e3c9717 15516 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15517
0e8ffe1b 15518 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15519 crtc->config);
24929352 15520
83d65738 15521 crtc->base.state->enable = crtc->active;
49d6fa21 15522 crtc->base.state->active = crtc->active;
24929352 15523 crtc->base.enabled = crtc->active;
b8b7fade 15524 crtc->base.hwmode = crtc->config->base.adjusted_mode;
b70709a6 15525
d032ffa0 15526 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15527
15528 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15529 crtc->base.base.id,
15530 crtc->active ? "enabled" : "disabled");
15531 }
15532
5358901f
DV		 15533 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15534 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15535
3e369b76
ACO		 15536 pll->on = pll->get_hw_state(dev_priv, pll,
15537 &pll->config.hw_state);
5358901f 15538 pll->active = 0;
3e369b76 15539 pll->config.crtc_mask = 0;
d3fcc808 15540 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15541 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15542 pll->active++;
3e369b76 15543 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15544 }
5358901f 15545 }
5358901f 15546
1e6f2ddc 15547 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15548 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15549
3e369b76 15550 if (pll->config.crtc_mask)
bd2bb1b9 15551 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15552 }
15553
b2784e15 15554 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15555 pipe = 0;
15556
15557 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15558 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15559 encoder->base.crtc = &crtc->base;
6e3c9717 15560 encoder->get_config(encoder, crtc->config);
24929352
DV		 15561 } else {
15562 encoder->base.crtc = NULL;
15563 }
15564
15565 encoder->connectors_active = false;
6f2bcceb 15566 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15567 encoder->base.base.id,
8e329a03 15568 encoder->base.name,
24929352 15569 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15570 pipe_name(pipe));
24929352
DV		 15571 }
15572
3a3371ff 15573 for_each_intel_connector(dev, connector) {
24929352
DV		 15574 if (connector->get_hw_state(connector)) {
15575 connector->base.dpms = DRM_MODE_DPMS_ON;
15576 connector->encoder->connectors_active = true;
15577 connector->base.encoder = &connector->encoder->base;
15578 } else {
15579 connector->base.dpms = DRM_MODE_DPMS_OFF;
15580 connector->base.encoder = NULL;
15581 }
15582 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15583 connector->base.base.id,
c23cc417 15584 connector->base.name,
24929352
DV		 15585 connector->base.encoder ? "enabled" : "disabled");
15586 }
30e984df
DV		 15587}
15588
15589/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15590 * and i915 state tracking structures. */
15591void intel_modeset_setup_hw_state(struct drm_device *dev,
15592 bool force_restore)
15593{
15594 struct drm_i915_private *dev_priv = dev->dev_private;
15595 enum pipe pipe;
30e984df
DV		 15596 struct intel_crtc *crtc;
15597 struct intel_encoder *encoder;
35c95375 15598 int i;
30e984df
DV		 15599
15600 intel_modeset_readout_hw_state(dev);
24929352 15601
babea61d
JB		 15602 /*
15603 * Now that we have the config, copy it to each CRTC struct
15604 * Note that this could go away if we move to using crtc_config
15605 * checking everywhere.
15606 */
d3fcc808 15607 for_each_intel_crtc(dev, crtc) {
d330a953 15608 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15609 intel_mode_from_pipe_config(&crtc->base.mode,
15610 crtc->config);
babea61d
JB		 15611 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15612 crtc->base.base.id);
15613 drm_mode_debug_printmodeline(&crtc->base.mode);
15614 }
15615 }
15616
24929352 15617 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15618 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15619 intel_sanitize_encoder(encoder);
15620 }
15621
055e393f 15622 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15623 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15624 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15625 intel_dump_pipe_config(crtc, crtc->config,
15626 "[setup_hw_state]");
24929352 15627 }
9a935856 15628
d29b2f9d
ACO		 15629 intel_modeset_update_connector_atomic_state(dev);
15630
35c95375
DV		 15631 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15632 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15633
15634 if (!pll->on || pll->active)
15635 continue;
15636
15637 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15638
15639 pll->disable(dev_priv, pll);
15640 pll->on = false;
15641 }
15642
26e1fe4f 15643 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15644 vlv_wm_get_hw_state(dev);
15645 else if (IS_GEN9(dev))
3078999f
PB		 15646 skl_wm_get_hw_state(dev);
15647 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15648 ilk_wm_get_hw_state(dev);
15649
45e2b5f6 15650 if (force_restore) {
7d0bc1ea
VS		 15651 i915_redisable_vga(dev);
15652
f30da187
DV		 15653 /*
15654 * We need to use raw interfaces for restoring state to avoid
15655 * checking (bogus) intermediate states.
15656 */
055e393f 15657 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15658 struct drm_crtc *crtc =
15659 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15660
83a57153 15661 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15662 }
15663 } else {
15664 intel_modeset_update_staged_output_state(dev);
15665 }
8af6cf88
DV		 15666
15667 intel_modeset_check_state(dev);
2c7111db
CW		 15668}
15669
15670void intel_modeset_gem_init(struct drm_device *dev)
15671{
92122789 15672 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15673 struct drm_crtc *c;
2ff8fde1 15674 struct drm_i915_gem_object *obj;
e0d6149b 15675 int ret;
484b41dd 15676
ae48434c
ID		 15677 mutex_lock(&dev->struct_mutex);
15678 intel_init_gt_powersave(dev);
15679 mutex_unlock(&dev->struct_mutex);
15680
92122789
JB		 15681 /*
15682 * There may be no VBT; and if the BIOS enabled SSC we can
15683 * just keep using it to avoid unnecessary flicker. Whereas if the
15684 * BIOS isn't using it, don't assume it will work even if the VBT
15685 * indicates as much.
15686 */
15687 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15688 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15689 DREF_SSC1_ENABLE);
15690
1833b134 15691 intel_modeset_init_hw(dev);
02e792fb
DV		 15692
15693 intel_setup_overlay(dev);
484b41dd
JB		 15694
15695 /*
15696 * Make sure any fbs we allocated at startup are properly
15697 * pinned & fenced. When we do the allocation it's too early
15698 * for this.
15699 */
70e1e0ec 15700 for_each_crtc(dev, c) {
2ff8fde1
MR		 15701 obj = intel_fb_obj(c->primary->fb);
15702 if (obj == NULL)
484b41dd
JB		 15703 continue;
15704
e0d6149b
TU		 15705 mutex_lock(&dev->struct_mutex);
15706 ret = intel_pin_and_fence_fb_obj(c->primary,
15707 c->primary->fb,
15708 c->primary->state,
91af127f 15709 NULL, NULL);
e0d6149b
TU		 15710 mutex_unlock(&dev->struct_mutex);
15711 if (ret) {
484b41dd
JB		 15712 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15713 to_intel_crtc(c)->pipe);
66e514c1
DA		 15714 drm_framebuffer_unreference(c->primary->fb);
15715 c->primary->fb = NULL;
36750f28 15716 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15717 update_state_fb(c->primary);
36750f28 15718 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15719 }
15720 }
0962c3c9
VS		 15721
15722 intel_backlight_register(dev);
79e53945
JB		 15723}
15724
4932e2c3
ID		 15725void intel_connector_unregister(struct intel_connector *intel_connector)
15726{
15727 struct drm_connector *connector = &intel_connector->base;
15728
15729 intel_panel_destroy_backlight(connector);
34ea3d38 15730 drm_connector_unregister(connector);
4932e2c3
ID		 15731}
15732
79e53945
JB		 15733void intel_modeset_cleanup(struct drm_device *dev)
15734{
652c393a 15735 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15736 struct drm_connector *connector;
652c393a 15737
2eb5252e
ID		 15738 intel_disable_gt_powersave(dev);
15739
0962c3c9
VS		 15740 intel_backlight_unregister(dev);
15741
fd0c0642
DV		 15742 /*
15743 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15744 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15745 * experience fancy races otherwise.
15746 */
2aeb7d3a 15747 intel_irq_uninstall(dev_priv);
eb21b92b 15748
fd0c0642
DV		 15749 /*
15750 * Due to the hpd irq storm handling the hotplug work can re-arm the
15751 * poll handlers. Hence disable polling after hpd handling is shut down.
15752 */
f87ea761 15753 drm_kms_helper_poll_fini(dev);
fd0c0642 15754
723bfd70
JB		 15755 intel_unregister_dsm_handler();
15756
7733b49b 15757 intel_fbc_disable(dev_priv);
69341a5e 15758
1630fe75
CW		 15759 /* flush any delayed tasks or pending work */
15760 flush_scheduled_work();
15761
db31af1d
JN		 15762 /* destroy the backlight and sysfs files before encoders/connectors */
15763 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15764 struct intel_connector *intel_connector;
15765
15766 intel_connector = to_intel_connector(connector);
15767 intel_connector->unregister(intel_connector);
db31af1d 15768 }
d9255d57 15769
79e53945 15770 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15771
15772 intel_cleanup_overlay(dev);
ae48434c
ID		 15773
15774 mutex_lock(&dev->struct_mutex);
15775 intel_cleanup_gt_powersave(dev);
15776 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15777}
15778
f1c79df3
ZW		 15779/*
15780 * Return which encoder is currently attached for connector.
15781 */
df0e9248 15782struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15783{
df0e9248
CW		 15784 return &intel_attached_encoder(connector)->base;
15785}
f1c79df3 15786
df0e9248
CW		 15787void intel_connector_attach_encoder(struct intel_connector *connector,
15788 struct intel_encoder *encoder)
15789{
15790 connector->encoder = encoder;
15791 drm_mode_connector_attach_encoder(&connector->base,
15792 &encoder->base);
79e53945 15793}
28d52043
DA		 15794
15795/*
15796 * set vga decode state - true == enable VGA decode
15797 */
15798int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15799{
15800 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15801 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15802 u16 gmch_ctrl;
15803
75fa041d
CW		 15804 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15805 DRM_ERROR("failed to read control word\n");
15806 return -EIO;
15807 }
15808
c0cc8a55
CW		 15809 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15810 return 0;
15811
28d52043
DA		 15812 if (state)
15813 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15814 else
15815 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15816
15817 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15818 DRM_ERROR("failed to write control word\n");
15819 return -EIO;
15820 }
15821
28d52043
DA		 15822 return 0;
15823}
c4a1d9e4 15824
c4a1d9e4 15825struct intel_display_error_state {
ff57f1b0
PZ		 15826
15827 u32 power_well_driver;
15828
63b66e5b
CW		 15829 int num_transcoders;
15830
c4a1d9e4
CW		 15831 struct intel_cursor_error_state {
15832 u32 control;
15833 u32 position;
15834 u32 base;
15835 u32 size;
52331309 15836 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15837
15838 struct intel_pipe_error_state {
ddf9c536 15839 bool power_domain_on;
c4a1d9e4 15840 u32 source;
f301b1e1 15841 u32 stat;
52331309 15842 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15843
15844 struct intel_plane_error_state {
15845 u32 control;
15846 u32 stride;
15847 u32 size;
15848 u32 pos;
15849 u32 addr;
15850 u32 surface;
15851 u32 tile_offset;
52331309 15852 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15853
15854 struct intel_transcoder_error_state {
ddf9c536 15855 bool power_domain_on;
63b66e5b
CW		 15856 enum transcoder cpu_transcoder;
15857
15858 u32 conf;
15859
15860 u32 htotal;
15861 u32 hblank;
15862 u32 hsync;
15863 u32 vtotal;
15864 u32 vblank;
15865 u32 vsync;
15866 } transcoder[4];
c4a1d9e4
CW		 15867};
15868
15869struct intel_display_error_state *
15870intel_display_capture_error_state(struct drm_device *dev)
15871{
fbee40df 15872 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15873 struct intel_display_error_state *error;
63b66e5b
CW		 15874 int transcoders[] = {
15875 TRANSCODER_A,
15876 TRANSCODER_B,
15877 TRANSCODER_C,
15878 TRANSCODER_EDP,
15879 };
c4a1d9e4
CW		 15880 int i;
15881
63b66e5b
CW		 15882 if (INTEL_INFO(dev)->num_pipes == 0)
15883 return NULL;
15884
9d1cb914 15885 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15886 if (error == NULL)
15887 return NULL;
15888
190be112 15889 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15890 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15891
055e393f 15892 for_each_pipe(dev_priv, i) {
ddf9c536 15893 error->pipe[i].power_domain_on =
f458ebbc
DV		 15894 __intel_display_power_is_enabled(dev_priv,
15895 POWER_DOMAIN_PIPE(i));
ddf9c536 15896 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15897 continue;
15898
5efb3e28
VS		 15899 error->cursor[i].control = I915_READ(CURCNTR(i));
15900 error->cursor[i].position = I915_READ(CURPOS(i));
15901 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15902
15903 error->plane[i].control = I915_READ(DSPCNTR(i));
15904 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15905 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15906 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15907 error->plane[i].pos = I915_READ(DSPPOS(i));
15908 }
ca291363
PZ		 15909 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15910 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15911 if (INTEL_INFO(dev)->gen >= 4) {
15912 error->plane[i].surface = I915_READ(DSPSURF(i));
15913 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15914 }
15915
c4a1d9e4 15916 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15917
3abfce77 15918 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15919 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15920 }
15921
15922 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15923 if (HAS_DDI(dev_priv->dev))
15924 error->num_transcoders++; /* Account for eDP. */
15925
15926 for (i = 0; i < error->num_transcoders; i++) {
15927 enum transcoder cpu_transcoder = transcoders[i];
15928
ddf9c536 15929 error->transcoder[i].power_domain_on =
f458ebbc 15930 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15931 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15932 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15933 continue;
15934
63b66e5b
CW		 15935 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15936
15937 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15938 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15939 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15940 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15941 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15942 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15943 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15944 }
15945
15946 return error;
15947}
15948
edc3d884
MK		 15949#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15950
c4a1d9e4 15951void
edc3d884 15952intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15953 struct drm_device *dev,
15954 struct intel_display_error_state *error)
15955{
055e393f 15956 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15957 int i;
15958
63b66e5b
CW		 15959 if (!error)
15960 return;
15961
edc3d884 15962 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15963 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15964 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15965 error->power_well_driver);
055e393f 15966 for_each_pipe(dev_priv, i) {
edc3d884 15967 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15968 err_printf(m, " Power: %s\n",
15969 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15970 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15971 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15972
15973 err_printf(m, "Plane [%d]:\n", i);
15974 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15975 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15976 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15977 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15978 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15979 }
4b71a570 15980 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15981 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15982 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15983 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15984 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15985 }
15986
edc3d884
MK		 15987 err_printf(m, "Cursor [%d]:\n", i);
15988 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15989 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15990 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15991 }
63b66e5b
CW		 15992
15993 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15994 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15995 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15996 err_printf(m, " Power: %s\n",
15997 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15998 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15999 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16000 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16001 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16002 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16003 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16004 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16005 }
c4a1d9e4 16006}
e2fcdaa9
VS		 16007
16008void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16009{
16010 struct intel_crtc *crtc;
16011
16012 for_each_intel_crtc(dev, crtc) {
16013 struct intel_unpin_work *work;
e2fcdaa9 16014
5e2d7afc 16015 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 16016
16017 work = crtc->unpin_work;
16018
16019 if (work && work->event &&
16020 work->event->base.file_priv == file) {
16021 kfree(work->event);
16022 work->event = NULL;
16023 }
16024
5e2d7afc 16025 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 16026 }
16027}
Linux kernel - Deliverables
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