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drm/i915: distinguish between error messages in DIDL initialization
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
040484af
JB		 912/* For ILK+ */
913static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 914 struct intel_pch_pll *pll,
915 struct intel_crtc *crtc,
916 bool state)
040484af 917{
040484af
JB		 918 u32 val;
919 bool cur_state;
920
9d82aa17
ED		 921 if (HAS_PCH_LPT(dev_priv->dev)) {
922 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
923 return;
924 }
925
92b27b08
CW		 926 if (WARN (!pll,
927 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 928 return;
ee7b9f93 929
92b27b08
CW		 930 val = I915_READ(pll->pll_reg);
931 cur_state = !!(val & DPLL_VCO_ENABLE);
932 WARN(cur_state != state,
933 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
934 pll->pll_reg, state_string(state), state_string(cur_state), val);
935
936 /* Make sure the selected PLL is correctly attached to the transcoder */
937 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 938 u32 pch_dpll;
939
940 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 941 cur_state = pll->pll_reg == _PCH_DPLL_B;
942 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 943 "PLL[%d] not attached to this transcoder %c: %08x\n",
944 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 945 cur_state = !!(val >> (4*crtc->pipe + 3));
946 WARN(cur_state != state,
4bb6f1f3 947 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 948 pll->pll_reg == _PCH_DPLL_B,
949 state_string(state),
4bb6f1f3 950 pipe_name(crtc->pipe),
92b27b08
CW		 951 val);
952 }
d3ccbe86 953 }
040484af 954}
92b27b08
CW		 955#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
956#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 957
958static void assert_fdi_tx(struct drm_i915_private *dev_priv,
959 enum pipe pipe, bool state)
960{
961 int reg;
962 u32 val;
963 bool cur_state;
ad80a810
PZ		 964 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
965 pipe);
040484af 966
affa9354
PZ		 967 if (HAS_DDI(dev_priv->dev)) {
968 /* DDI does not have a specific FDI_TX register */
ad80a810 969 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 970 val = I915_READ(reg);
ad80a810 971 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 972 } else {
973 reg = FDI_TX_CTL(pipe);
974 val = I915_READ(reg);
975 cur_state = !!(val & FDI_TX_ENABLE);
976 }
040484af
JB		 977 WARN(cur_state != state,
978 "FDI TX state assertion failure (expected %s, current %s)\n",
979 state_string(state), state_string(cur_state));
980}
981#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
982#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
983
984static void assert_fdi_rx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
990
d63fa0dc
PZ		 991 reg = FDI_RX_CTL(pipe);
992 val = I915_READ(reg);
993 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 994 WARN(cur_state != state,
995 "FDI RX state assertion failure (expected %s, current %s)\n",
996 state_string(state), state_string(cur_state));
997}
998#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
999#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
1006
1007 /* ILK FDI PLL is always enabled */
1008 if (dev_priv->info->gen == 5)
1009 return;
1010
bf507ef7 1011 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1012 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1013 return;
1014
040484af
JB		 1015 reg = FDI_TX_CTL(pipe);
1016 val = I915_READ(reg);
1017 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018}
1019
1020static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 reg = FDI_RX_CTL(pipe);
1027 val = I915_READ(reg);
1028 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029}
1030
ea0760cf
JB		 1031static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032 enum pipe pipe)
1033{
1034 int pp_reg, lvds_reg;
1035 u32 val;
1036 enum pipe panel_pipe = PIPE_A;
0de3b485 1037 bool locked = true;
ea0760cf
JB		 1038
1039 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040 pp_reg = PCH_PP_CONTROL;
1041 lvds_reg = PCH_LVDS;
1042 } else {
1043 pp_reg = PP_CONTROL;
1044 lvds_reg = LVDS;
1045 }
1046
1047 val = I915_READ(pp_reg);
1048 if (!(val & PANEL_POWER_ON) ||
1049 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050 locked = false;
1051
1052 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053 panel_pipe = PIPE_B;
1054
1055 WARN(panel_pipe == pipe && locked,
1056 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1057 pipe_name(pipe));
ea0760cf
JB		 1058}
1059
b840d907
JB		 1060void assert_pipe(struct drm_i915_private *dev_priv,
1061 enum pipe pipe, bool state)
b24e7179
JB		 1062{
1063 int reg;
1064 u32 val;
63d7bbe9 1065 bool cur_state;
702e7a56
PZ		 1066 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067 pipe);
b24e7179 1068
8e636784
DV		 1069 /* if we need the pipe A quirk it must be always on */
1070 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071 state = true;
1072
b97186f0
PZ		 1073 if (!intel_display_power_enabled(dev_priv->dev,
1074 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1075 cur_state = false;
1076 } else {
1077 reg = PIPECONF(cpu_transcoder);
1078 val = I915_READ(reg);
1079 cur_state = !!(val & PIPECONF_ENABLE);
1080 }
1081
63d7bbe9
JB		 1082 WARN(cur_state != state,
1083 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1084 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1085}
1086
931872fc
CW		 1087static void assert_plane(struct drm_i915_private *dev_priv,
1088 enum plane plane, bool state)
b24e7179
JB		 1089{
1090 int reg;
1091 u32 val;
931872fc 1092 bool cur_state;
b24e7179
JB		 1093
1094 reg = DSPCNTR(plane);
1095 val = I915_READ(reg);
931872fc
CW		 1096 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097 WARN(cur_state != state,
1098 "plane %c assertion failure (expected %s, current %s)\n",
1099 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1100}
1101
931872fc
CW		 1102#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
b24e7179
JB		 1105static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106 enum pipe pipe)
1107{
1108 int reg, i;
1109 u32 val;
1110 int cur_pipe;
1111
19ec1358 1112 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1113 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1114 reg = DSPCNTR(pipe);
1115 val = I915_READ(reg);
1116 WARN((val & DISPLAY_PLANE_ENABLE),
1117 "plane %c assertion failure, should be disabled but not\n",
1118 plane_name(pipe));
19ec1358 1119 return;
28c05794 1120 }
19ec1358 1121
b24e7179
JB		 1122 /* Need to check both planes against the pipe */
1123 for (i = 0; i < 2; i++) {
1124 reg = DSPCNTR(i);
1125 val = I915_READ(reg);
1126 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1127 DISPPLANE_SEL_PIPE_SHIFT;
1128 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1129 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1130 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1131 }
1132}
1133
19332d7a
JB		 1134static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1135 enum pipe pipe)
1136{
1137 int reg, i;
1138 u32 val;
1139
1140 if (!IS_VALLEYVIEW(dev_priv->dev))
1141 return;
1142
1143 /* Need to check both planes against the pipe */
1144 for (i = 0; i < dev_priv->num_plane; i++) {
1145 reg = SPCNTR(pipe, i);
1146 val = I915_READ(reg);
1147 WARN((val & SP_ENABLE),
06da8da2
VS		 1148 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1149 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1150 }
1151}
1152
92f2584a
JB		 1153static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1154{
1155 u32 val;
1156 bool enabled;
1157
9d82aa17
ED		 1158 if (HAS_PCH_LPT(dev_priv->dev)) {
1159 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1160 return;
1161 }
1162
92f2584a
JB		 1163 val = I915_READ(PCH_DREF_CONTROL);
1164 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1165 DREF_SUPERSPREAD_SOURCE_MASK));
1166 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1167}
1168
ab9412ba
DV		 1169static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
92f2584a
JB		 1171{
1172 int reg;
1173 u32 val;
1174 bool enabled;
1175
ab9412ba 1176 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1177 val = I915_READ(reg);
1178 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1179 WARN(enabled,
1180 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1181 pipe_name(pipe));
92f2584a
JB		 1182}
1183
4e634389
KP		 1184static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1186{
1187 if ((val & DP_PORT_EN) == 0)
1188 return false;
1189
1190 if (HAS_PCH_CPT(dev_priv->dev)) {
1191 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1192 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1193 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1194 return false;
1195 } else {
1196 if ((val & DP_PIPE_MASK) != (pipe << 30))
1197 return false;
1198 }
1199 return true;
1200}
1201
1519b995
KP		 1202static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1203 enum pipe pipe, u32 val)
1204{
dc0fa718 1205 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1206 return false;
1207
1208 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1209 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1210 return false;
1211 } else {
dc0fa718 1212 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1213 return false;
1214 }
1215 return true;
1216}
1217
1218static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, u32 val)
1220{
1221 if ((val & LVDS_PORT_EN) == 0)
1222 return false;
1223
1224 if (HAS_PCH_CPT(dev_priv->dev)) {
1225 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1226 return false;
1227 } else {
1228 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1229 return false;
1230 }
1231 return true;
1232}
1233
1234static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, u32 val)
1236{
1237 if ((val & ADPA_DAC_ENABLE) == 0)
1238 return false;
1239 if (HAS_PCH_CPT(dev_priv->dev)) {
1240 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1241 return false;
1242 } else {
1243 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1244 return false;
1245 }
1246 return true;
1247}
1248
291906f1 1249static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1250 enum pipe pipe, int reg, u32 port_sel)
291906f1 1251{
47a05eca 1252 u32 val = I915_READ(reg);
4e634389 1253 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1254 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1255 reg, pipe_name(pipe));
de9a35ab 1256
75c5da27
DV		 1257 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1258 && (val & DP_PIPEB_SELECT),
de9a35ab 1259 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1260}
1261
1262static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe, int reg)
1264{
47a05eca 1265 u32 val = I915_READ(reg);
b70ad586 1266 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1267 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1268 reg, pipe_name(pipe));
de9a35ab 1269
dc0fa718 1270 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1271 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1272 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1273}
1274
1275static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1276 enum pipe pipe)
1277{
1278 int reg;
1279 u32 val;
291906f1 1280
f0575e92
KP		 1281 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1282 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1284
1285 reg = PCH_ADPA;
1286 val = I915_READ(reg);
b70ad586 1287 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1288 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1289 pipe_name(pipe));
291906f1
JB		 1290
1291 reg = PCH_LVDS;
1292 val = I915_READ(reg);
b70ad586 1293 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1294 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1295 pipe_name(pipe));
291906f1 1296
e2debe91
PZ		 1297 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1298 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1300}
1301
63d7bbe9
JB		 1302/**
1303 * intel_enable_pll - enable a PLL
1304 * @dev_priv: i915 private structure
1305 * @pipe: pipe PLL to enable
1306 *
1307 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1308 * make sure the PLL reg is writable first though, since the panel write
1309 * protect mechanism may be enabled.
1310 *
1311 * Note! This is for pre-ILK only.
7434a255
TR		 1312 *
1313 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1314 */
1315static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1316{
1317 int reg;
1318 u32 val;
1319
58c6eaa2
DV		 1320 assert_pipe_disabled(dev_priv, pipe);
1321
63d7bbe9 1322 /* No really, not for ILK+ */
a0c4da24 1323 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1324
1325 /* PLL is protected by panel, make sure we can write it */
1326 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1327 assert_panel_unlocked(dev_priv, pipe);
1328
1329 reg = DPLL(pipe);
1330 val = I915_READ(reg);
1331 val |= DPLL_VCO_ENABLE;
1332
1333 /* We do this three times for luck */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337 I915_WRITE(reg, val);
1338 POSTING_READ(reg);
1339 udelay(150); /* wait for warmup */
1340 I915_WRITE(reg, val);
1341 POSTING_READ(reg);
1342 udelay(150); /* wait for warmup */
1343}
1344
1345/**
1346 * intel_disable_pll - disable a PLL
1347 * @dev_priv: i915 private structure
1348 * @pipe: pipe PLL to disable
1349 *
1350 * Disable the PLL for @pipe, making sure the pipe is off first.
1351 *
1352 * Note! This is for pre-ILK only.
1353 */
1354static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1355{
1356 int reg;
1357 u32 val;
1358
1359 /* Don't disable pipe A or pipe A PLLs if needed */
1360 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1361 return;
1362
1363 /* Make sure the pipe isn't still relying on us */
1364 assert_pipe_disabled(dev_priv, pipe);
1365
1366 reg = DPLL(pipe);
1367 val = I915_READ(reg);
1368 val &= ~DPLL_VCO_ENABLE;
1369 I915_WRITE(reg, val);
1370 POSTING_READ(reg);
1371}
1372
89b667f8
JB		 1373void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1374{
1375 u32 port_mask;
1376
1377 if (!port)
1378 port_mask = DPLL_PORTB_READY_MASK;
1379 else
1380 port_mask = DPLL_PORTC_READY_MASK;
1381
1382 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1383 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1384 'B' + port, I915_READ(DPLL(0)));
1385}
1386
92f2584a 1387/**
b6b4e185 1388 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1389 * @dev_priv: i915 private structure
1390 * @pipe: pipe PLL to enable
1391 *
1392 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1393 * drives the transcoder clock.
1394 */
b6b4e185 1395static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1396{
ee7b9f93 1397 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1398 struct intel_pch_pll *pll;
92f2584a
JB		 1399 int reg;
1400 u32 val;
1401
48da64a8 1402 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1403 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1404 pll = intel_crtc->pch_pll;
1405 if (pll == NULL)
1406 return;
1407
1408 if (WARN_ON(pll->refcount == 0))
1409 return;
ee7b9f93
JB		 1410
1411 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1412 pll->pll_reg, pll->active, pll->on,
1413 intel_crtc->base.base.id);
92f2584a
JB		 1414
1415 /* PCH refclock must be enabled first */
1416 assert_pch_refclk_enabled(dev_priv);
1417
ee7b9f93 1418 if (pll->active++ && pll->on) {
92b27b08 1419 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1420 return;
1421 }
1422
1423 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1424
1425 reg = pll->pll_reg;
92f2584a
JB		 1426 val = I915_READ(reg);
1427 val |= DPLL_VCO_ENABLE;
1428 I915_WRITE(reg, val);
1429 POSTING_READ(reg);
1430 udelay(200);
ee7b9f93
JB		 1431
1432 pll->on = true;
92f2584a
JB		 1433}
1434
ee7b9f93 1435static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1436{
ee7b9f93
JB		 1437 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1438 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1439 int reg;
ee7b9f93 1440 u32 val;
4c609cb8 1441
92f2584a
JB		 1442 /* PCH only available on ILK+ */
1443 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1444 if (pll == NULL)
1445 return;
92f2584a 1446
48da64a8
CW		 1447 if (WARN_ON(pll->refcount == 0))
1448 return;
7a419866 1449
ee7b9f93
JB		 1450 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1451 pll->pll_reg, pll->active, pll->on,
1452 intel_crtc->base.base.id);
7a419866 1453
48da64a8 1454 if (WARN_ON(pll->active == 0)) {
92b27b08 1455 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1456 return;
1457 }
1458
ee7b9f93 1459 if (--pll->active) {
92b27b08 1460 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1461 return;
ee7b9f93
JB		 1462 }
1463
1464 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1465
1466 /* Make sure transcoder isn't still depending on us */
ab9412ba 1467 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1468
ee7b9f93 1469 reg = pll->pll_reg;
92f2584a
JB		 1470 val = I915_READ(reg);
1471 val &= ~DPLL_VCO_ENABLE;
1472 I915_WRITE(reg, val);
1473 POSTING_READ(reg);
1474 udelay(200);
ee7b9f93
JB		 1475
1476 pll->on = false;
92f2584a
JB		 1477}
1478
b8a4f404
PZ		 1479static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1480 enum pipe pipe)
040484af 1481{
23670b32 1482 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1483 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1484 uint32_t reg, val, pipeconf_val;
040484af
JB		 1485
1486 /* PCH only available on ILK+ */
1487 BUG_ON(dev_priv->info->gen < 5);
1488
1489 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1490 assert_pch_pll_enabled(dev_priv,
1491 to_intel_crtc(crtc)->pch_pll,
1492 to_intel_crtc(crtc));
040484af
JB		 1493
1494 /* FDI must be feeding us bits for PCH ports */
1495 assert_fdi_tx_enabled(dev_priv, pipe);
1496 assert_fdi_rx_enabled(dev_priv, pipe);
1497
23670b32
DV		 1498 if (HAS_PCH_CPT(dev)) {
1499 /* Workaround: Set the timing override bit before enabling the
1500 * pch transcoder. */
1501 reg = TRANS_CHICKEN2(pipe);
1502 val = I915_READ(reg);
1503 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1504 I915_WRITE(reg, val);
59c859d6 1505 }
23670b32 1506
ab9412ba 1507 reg = PCH_TRANSCONF(pipe);
040484af 1508 val = I915_READ(reg);
5f7f726d 1509 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1510
1511 if (HAS_PCH_IBX(dev_priv->dev)) {
1512 /*
1513 * make the BPC in transcoder be consistent with
1514 * that in pipeconf reg.
1515 */
dfd07d72
DV		 1516 val &= ~PIPECONF_BPC_MASK;
1517 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1518 }
5f7f726d
PZ		 1519
1520 val &= ~TRANS_INTERLACE_MASK;
1521 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1522 if (HAS_PCH_IBX(dev_priv->dev) &&
1523 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1524 val |= TRANS_LEGACY_INTERLACED_ILK;
1525 else
1526 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1527 else
1528 val |= TRANS_PROGRESSIVE;
1529
040484af
JB		 1530 I915_WRITE(reg, val | TRANS_ENABLE);
1531 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1532 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1533}
1534
8fb033d7 1535static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1536 enum transcoder cpu_transcoder)
040484af 1537{
8fb033d7 1538 u32 val, pipeconf_val;
8fb033d7
PZ		 1539
1540 /* PCH only available on ILK+ */
1541 BUG_ON(dev_priv->info->gen < 5);
1542
8fb033d7 1543 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1544 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1545 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1546
223a6fdf
PZ		 1547 /* Workaround: set timing override bit. */
1548 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1549 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1550 I915_WRITE(_TRANSA_CHICKEN2, val);
1551
25f3ef11 1552 val = TRANS_ENABLE;
937bb610 1553 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1554
9a76b1c6
PZ		 1555 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1556 PIPECONF_INTERLACED_ILK)
a35f2679 1557 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1558 else
1559 val |= TRANS_PROGRESSIVE;
1560
ab9412ba
DV		 1561 I915_WRITE(LPT_TRANSCONF, val);
1562 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1563 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1564}
1565
b8a4f404
PZ		 1566static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
040484af 1568{
23670b32
DV		 1569 struct drm_device *dev = dev_priv->dev;
1570 uint32_t reg, val;
040484af
JB		 1571
1572 /* FDI relies on the transcoder */
1573 assert_fdi_tx_disabled(dev_priv, pipe);
1574 assert_fdi_rx_disabled(dev_priv, pipe);
1575
291906f1
JB		 1576 /* Ports must be off as well */
1577 assert_pch_ports_disabled(dev_priv, pipe);
1578
ab9412ba 1579 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1580 val = I915_READ(reg);
1581 val &= ~TRANS_ENABLE;
1582 I915_WRITE(reg, val);
1583 /* wait for PCH transcoder off, transcoder state */
1584 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1585 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1586
1587 if (!HAS_PCH_IBX(dev)) {
1588 /* Workaround: Clear the timing override chicken bit again. */
1589 reg = TRANS_CHICKEN2(pipe);
1590 val = I915_READ(reg);
1591 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1592 I915_WRITE(reg, val);
1593 }
040484af
JB		 1594}
1595
ab4d966c 1596static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1597{
8fb033d7
PZ		 1598 u32 val;
1599
ab9412ba 1600 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1601 val &= ~TRANS_ENABLE;
ab9412ba 1602 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1603 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1604 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1605 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1606
1607 /* Workaround: clear timing override bit. */
1608 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1609 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1610 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1611}
1612
b24e7179 1613/**
309cfea8 1614 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1615 * @dev_priv: i915 private structure
1616 * @pipe: pipe to enable
040484af 1617 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1618 *
1619 * Enable @pipe, making sure that various hardware specific requirements
1620 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1621 *
1622 * @pipe should be %PIPE_A or %PIPE_B.
1623 *
1624 * Will wait until the pipe is actually running (i.e. first vblank) before
1625 * returning.
1626 */
040484af
JB		 1627static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1628 bool pch_port)
b24e7179 1629{
702e7a56
PZ		 1630 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1631 pipe);
1a240d4d 1632 enum pipe pch_transcoder;
b24e7179
JB		 1633 int reg;
1634 u32 val;
1635
58c6eaa2
DV		 1636 assert_planes_disabled(dev_priv, pipe);
1637 assert_sprites_disabled(dev_priv, pipe);
1638
681e5811 1639 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1640 pch_transcoder = TRANSCODER_A;
1641 else
1642 pch_transcoder = pipe;
1643
b24e7179
JB		 1644 /*
1645 * A pipe without a PLL won't actually be able to drive bits from
1646 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1647 * need the check.
1648 */
1649 if (!HAS_PCH_SPLIT(dev_priv->dev))
1650 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1651 else {
1652 if (pch_port) {
1653 /* if driving the PCH, we need FDI enabled */
cc391bbb 1654 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1655 assert_fdi_tx_pll_enabled(dev_priv,
1656 (enum pipe) cpu_transcoder);
040484af
JB		 1657 }
1658 /* FIXME: assert CPU port conditions for SNB+ */
1659 }
b24e7179 1660
702e7a56 1661 reg = PIPECONF(cpu_transcoder);
b24e7179 1662 val = I915_READ(reg);
00d70b15
CW		 1663 if (val & PIPECONF_ENABLE)
1664 return;
1665
1666 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1667 intel_wait_for_vblank(dev_priv->dev, pipe);
1668}
1669
1670/**
309cfea8 1671 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1672 * @dev_priv: i915 private structure
1673 * @pipe: pipe to disable
1674 *
1675 * Disable @pipe, making sure that various hardware specific requirements
1676 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1677 *
1678 * @pipe should be %PIPE_A or %PIPE_B.
1679 *
1680 * Will wait until the pipe has shut down before returning.
1681 */
1682static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1683 enum pipe pipe)
1684{
702e7a56
PZ		 1685 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1686 pipe);
b24e7179
JB		 1687 int reg;
1688 u32 val;
1689
1690 /*
1691 * Make sure planes won't keep trying to pump pixels to us,
1692 * or we might hang the display.
1693 */
1694 assert_planes_disabled(dev_priv, pipe);
19332d7a 1695 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1696
1697 /* Don't disable pipe A or pipe A PLLs if needed */
1698 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1699 return;
1700
702e7a56 1701 reg = PIPECONF(cpu_transcoder);
b24e7179 1702 val = I915_READ(reg);
00d70b15
CW		 1703 if ((val & PIPECONF_ENABLE) == 0)
1704 return;
1705
1706 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1707 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1708}
1709
d74362c9
KP		 1710/*
1711 * Plane regs are double buffered, going from enabled->disabled needs a
1712 * trigger in order to latch. The display address reg provides this.
1713 */
6f1d69b0 1714void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1715 enum plane plane)
1716{
14f86147
DL		 1717 if (dev_priv->info->gen >= 4)
1718 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1719 else
1720 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1721}
1722
b24e7179
JB		 1723/**
1724 * intel_enable_plane - enable a display plane on a given pipe
1725 * @dev_priv: i915 private structure
1726 * @plane: plane to enable
1727 * @pipe: pipe being fed
1728 *
1729 * Enable @plane on @pipe, making sure that @pipe is running first.
1730 */
1731static void intel_enable_plane(struct drm_i915_private *dev_priv,
1732 enum plane plane, enum pipe pipe)
1733{
1734 int reg;
1735 u32 val;
1736
1737 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1738 assert_pipe_enabled(dev_priv, pipe);
1739
1740 reg = DSPCNTR(plane);
1741 val = I915_READ(reg);
00d70b15
CW		 1742 if (val & DISPLAY_PLANE_ENABLE)
1743 return;
1744
1745 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1746 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1747 intel_wait_for_vblank(dev_priv->dev, pipe);
1748}
1749
b24e7179
JB		 1750/**
1751 * intel_disable_plane - disable a display plane
1752 * @dev_priv: i915 private structure
1753 * @plane: plane to disable
1754 * @pipe: pipe consuming the data
1755 *
1756 * Disable @plane; should be an independent operation.
1757 */
1758static void intel_disable_plane(struct drm_i915_private *dev_priv,
1759 enum plane plane, enum pipe pipe)
1760{
1761 int reg;
1762 u32 val;
1763
1764 reg = DSPCNTR(plane);
1765 val = I915_READ(reg);
00d70b15
CW		 1766 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1767 return;
1768
1769 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1770 intel_flush_display_plane(dev_priv, plane);
1771 intel_wait_for_vblank(dev_priv->dev, pipe);
1772}
1773
693db184
CW		 1774static bool need_vtd_wa(struct drm_device *dev)
1775{
1776#ifdef CONFIG_INTEL_IOMMU
1777 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1778 return true;
1779#endif
1780 return false;
1781}
1782
127bd2ac 1783int
48b956c5 1784intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1785 struct drm_i915_gem_object *obj,
919926ae 1786 struct intel_ring_buffer *pipelined)
6b95a207 1787{
ce453d81 1788 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1789 u32 alignment;
1790 int ret;
1791
05394f39 1792 switch (obj->tiling_mode) {
6b95a207 1793 case I915_TILING_NONE:
534843da
CW		 1794 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1795 alignment = 128 * 1024;
a6c45cf0 1796 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1797 alignment = 4 * 1024;
1798 else
1799 alignment = 64 * 1024;
6b95a207
KH		 1800 break;
1801 case I915_TILING_X:
1802 /* pin() will align the object as required by fence */
1803 alignment = 0;
1804 break;
1805 case I915_TILING_Y:
8bb6e959
DV		 1806 /* Despite that we check this in framebuffer_init userspace can
1807 * screw us over and change the tiling after the fact. Only
1808 * pinned buffers can't change their tiling. */
1809 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1810 return -EINVAL;
1811 default:
1812 BUG();
1813 }
1814
693db184
CW		 1815 /* Note that the w/a also requires 64 PTE of padding following the
1816 * bo. We currently fill all unused PTE with the shadow page and so
1817 * we should always have valid PTE following the scanout preventing
1818 * the VT-d warning.
1819 */
1820 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1821 alignment = 256 * 1024;
1822
ce453d81 1823 dev_priv->mm.interruptible = false;
2da3b9b9 1824 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1825 if (ret)
ce453d81 1826 goto err_interruptible;
6b95a207
KH		 1827
1828 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1829 * fence, whereas 965+ only requires a fence if using
1830 * framebuffer compression. For simplicity, we always install
1831 * a fence as the cost is not that onerous.
1832 */
06d98131 1833 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1834 if (ret)
1835 goto err_unpin;
1690e1eb 1836
9a5a53b3 1837 i915_gem_object_pin_fence(obj);
6b95a207 1838
ce453d81 1839 dev_priv->mm.interruptible = true;
6b95a207 1840 return 0;
48b956c5
CW		 1841
1842err_unpin:
1843 i915_gem_object_unpin(obj);
ce453d81
CW		 1844err_interruptible:
1845 dev_priv->mm.interruptible = true;
48b956c5 1846 return ret;
6b95a207
KH		 1847}
1848
1690e1eb
CW		 1849void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1850{
1851 i915_gem_object_unpin_fence(obj);
1852 i915_gem_object_unpin(obj);
1853}
1854
c2c75131
DV		 1855/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1856 * is assumed to be a power-of-two. */
bc752862
CW		 1857unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1858 unsigned int tiling_mode,
1859 unsigned int cpp,
1860 unsigned int pitch)
c2c75131 1861{
bc752862
CW		 1862 if (tiling_mode != I915_TILING_NONE) {
1863 unsigned int tile_rows, tiles;
c2c75131 1864
bc752862
CW		 1865 tile_rows = *y / 8;
1866 *y %= 8;
c2c75131 1867
bc752862
CW		 1868 tiles = *x / (512/cpp);
1869 *x %= 512/cpp;
1870
1871 return tile_rows * pitch * 8 + tiles * 4096;
1872 } else {
1873 unsigned int offset;
1874
1875 offset = *y * pitch + *x * cpp;
1876 *y = 0;
1877 *x = (offset & 4095) / cpp;
1878 return offset & -4096;
1879 }
c2c75131
DV		 1880}
1881
17638cd6
JB		 1882static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1883 int x, int y)
81255565
JB		 1884{
1885 struct drm_device *dev = crtc->dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1888 struct intel_framebuffer *intel_fb;
05394f39 1889 struct drm_i915_gem_object *obj;
81255565 1890 int plane = intel_crtc->plane;
e506a0c6 1891 unsigned long linear_offset;
81255565 1892 u32 dspcntr;
5eddb70b 1893 u32 reg;
81255565
JB		 1894
1895 switch (plane) {
1896 case 0:
1897 case 1:
1898 break;
1899 default:
84f44ce7 1900 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1901 return -EINVAL;
1902 }
1903
1904 intel_fb = to_intel_framebuffer(fb);
1905 obj = intel_fb->obj;
81255565 1906
5eddb70b
CW		 1907 reg = DSPCNTR(plane);
1908 dspcntr = I915_READ(reg);
81255565
JB		 1909 /* Mask out pixel format bits in case we change it */
1910 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1911 switch (fb->pixel_format) {
1912 case DRM_FORMAT_C8:
81255565
JB		 1913 dspcntr |= DISPPLANE_8BPP;
1914 break;
57779d06
VS		 1915 case DRM_FORMAT_XRGB1555:
1916 case DRM_FORMAT_ARGB1555:
1917 dspcntr |= DISPPLANE_BGRX555;
81255565 1918 break;
57779d06
VS		 1919 case DRM_FORMAT_RGB565:
1920 dspcntr |= DISPPLANE_BGRX565;
1921 break;
1922 case DRM_FORMAT_XRGB8888:
1923 case DRM_FORMAT_ARGB8888:
1924 dspcntr |= DISPPLANE_BGRX888;
1925 break;
1926 case DRM_FORMAT_XBGR8888:
1927 case DRM_FORMAT_ABGR8888:
1928 dspcntr |= DISPPLANE_RGBX888;
1929 break;
1930 case DRM_FORMAT_XRGB2101010:
1931 case DRM_FORMAT_ARGB2101010:
1932 dspcntr |= DISPPLANE_BGRX101010;
1933 break;
1934 case DRM_FORMAT_XBGR2101010:
1935 case DRM_FORMAT_ABGR2101010:
1936 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1937 break;
1938 default:
baba133a 1939 BUG();
81255565 1940 }
57779d06 1941
a6c45cf0 1942 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1943 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1944 dspcntr |= DISPPLANE_TILED;
1945 else
1946 dspcntr &= ~DISPPLANE_TILED;
1947 }
1948
5eddb70b 1949 I915_WRITE(reg, dspcntr);
81255565 1950
e506a0c6 1951 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1952
c2c75131
DV		 1953 if (INTEL_INFO(dev)->gen >= 4) {
1954 intel_crtc->dspaddr_offset =
bc752862
CW		 1955 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1956 fb->bits_per_pixel / 8,
1957 fb->pitches[0]);
c2c75131
DV		 1958 linear_offset -= intel_crtc->dspaddr_offset;
1959 } else {
e506a0c6 1960 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1961 }
e506a0c6
DV		 1962
1963 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1964 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1965 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1966 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1967 I915_MODIFY_DISPBASE(DSPSURF(plane),
1968 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1969 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1970 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1971 } else
e506a0c6 1972 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1973 POSTING_READ(reg);
81255565 1974
17638cd6
JB		 1975 return 0;
1976}
1977
1978static int ironlake_update_plane(struct drm_crtc *crtc,
1979 struct drm_framebuffer *fb, int x, int y)
1980{
1981 struct drm_device *dev = crtc->dev;
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984 struct intel_framebuffer *intel_fb;
1985 struct drm_i915_gem_object *obj;
1986 int plane = intel_crtc->plane;
e506a0c6 1987 unsigned long linear_offset;
17638cd6
JB		 1988 u32 dspcntr;
1989 u32 reg;
1990
1991 switch (plane) {
1992 case 0:
1993 case 1:
27f8227b 1994 case 2:
17638cd6
JB		 1995 break;
1996 default:
84f44ce7 1997 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1998 return -EINVAL;
1999 }
2000
2001 intel_fb = to_intel_framebuffer(fb);
2002 obj = intel_fb->obj;
2003
2004 reg = DSPCNTR(plane);
2005 dspcntr = I915_READ(reg);
2006 /* Mask out pixel format bits in case we change it */
2007 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2008 switch (fb->pixel_format) {
2009 case DRM_FORMAT_C8:
17638cd6
JB		 2010 dspcntr |= DISPPLANE_8BPP;
2011 break;
57779d06
VS		 2012 case DRM_FORMAT_RGB565:
2013 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2014 break;
57779d06
VS		 2015 case DRM_FORMAT_XRGB8888:
2016 case DRM_FORMAT_ARGB8888:
2017 dspcntr |= DISPPLANE_BGRX888;
2018 break;
2019 case DRM_FORMAT_XBGR8888:
2020 case DRM_FORMAT_ABGR8888:
2021 dspcntr |= DISPPLANE_RGBX888;
2022 break;
2023 case DRM_FORMAT_XRGB2101010:
2024 case DRM_FORMAT_ARGB2101010:
2025 dspcntr |= DISPPLANE_BGRX101010;
2026 break;
2027 case DRM_FORMAT_XBGR2101010:
2028 case DRM_FORMAT_ABGR2101010:
2029 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2030 break;
2031 default:
baba133a 2032 BUG();
17638cd6
JB		 2033 }
2034
2035 if (obj->tiling_mode != I915_TILING_NONE)
2036 dspcntr |= DISPPLANE_TILED;
2037 else
2038 dspcntr &= ~DISPPLANE_TILED;
2039
2040 /* must disable */
2041 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2042
2043 I915_WRITE(reg, dspcntr);
2044
e506a0c6 2045 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2046 intel_crtc->dspaddr_offset =
bc752862
CW		 2047 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2048 fb->bits_per_pixel / 8,
2049 fb->pitches[0]);
c2c75131 2050 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2051
e506a0c6
DV		 2052 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2053 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2054 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2055 I915_MODIFY_DISPBASE(DSPSURF(plane),
2056 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2057 if (IS_HASWELL(dev)) {
2058 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2059 } else {
2060 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2061 I915_WRITE(DSPLINOFF(plane), linear_offset);
2062 }
17638cd6
JB		 2063 POSTING_READ(reg);
2064
2065 return 0;
2066}
2067
2068/* Assume fb object is pinned & idle & fenced and just update base pointers */
2069static int
2070intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2071 int x, int y, enum mode_set_atomic state)
2072{
2073 struct drm_device *dev = crtc->dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2075
6b8e6ed0
CW		 2076 if (dev_priv->display.disable_fbc)
2077 dev_priv->display.disable_fbc(dev);
3dec0095 2078 intel_increase_pllclock(crtc);
81255565 2079
6b8e6ed0 2080 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2081}
2082
96a02917
VS		 2083void intel_display_handle_reset(struct drm_device *dev)
2084{
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 struct drm_crtc *crtc;
2087
2088 /*
2089 * Flips in the rings have been nuked by the reset,
2090 * so complete all pending flips so that user space
2091 * will get its events and not get stuck.
2092 *
2093 * Also update the base address of all primary
2094 * planes to the the last fb to make sure we're
2095 * showing the correct fb after a reset.
2096 *
2097 * Need to make two loops over the crtcs so that we
2098 * don't try to grab a crtc mutex before the
2099 * pending_flip_queue really got woken up.
2100 */
2101
2102 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2104 enum plane plane = intel_crtc->plane;
2105
2106 intel_prepare_page_flip(dev, plane);
2107 intel_finish_page_flip_plane(dev, plane);
2108 }
2109
2110 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2112
2113 mutex_lock(&crtc->mutex);
2114 if (intel_crtc->active)
2115 dev_priv->display.update_plane(crtc, crtc->fb,
2116 crtc->x, crtc->y);
2117 mutex_unlock(&crtc->mutex);
2118 }
2119}
2120
14667a4b
CW		 2121static int
2122intel_finish_fb(struct drm_framebuffer *old_fb)
2123{
2124 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2125 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2126 bool was_interruptible = dev_priv->mm.interruptible;
2127 int ret;
2128
14667a4b
CW		 2129 /* Big Hammer, we also need to ensure that any pending
2130 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2131 * current scanout is retired before unpinning the old
2132 * framebuffer.
2133 *
2134 * This should only fail upon a hung GPU, in which case we
2135 * can safely continue.
2136 */
2137 dev_priv->mm.interruptible = false;
2138 ret = i915_gem_object_finish_gpu(obj);
2139 dev_priv->mm.interruptible = was_interruptible;
2140
2141 return ret;
2142}
2143
198598d0
VS		 2144static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2145{
2146 struct drm_device *dev = crtc->dev;
2147 struct drm_i915_master_private *master_priv;
2148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2149
2150 if (!dev->primary->master)
2151 return;
2152
2153 master_priv = dev->primary->master->driver_priv;
2154 if (!master_priv->sarea_priv)
2155 return;
2156
2157 switch (intel_crtc->pipe) {
2158 case 0:
2159 master_priv->sarea_priv->pipeA_x = x;
2160 master_priv->sarea_priv->pipeA_y = y;
2161 break;
2162 case 1:
2163 master_priv->sarea_priv->pipeB_x = x;
2164 master_priv->sarea_priv->pipeB_y = y;
2165 break;
2166 default:
2167 break;
2168 }
2169}
2170
5c3b82e2 2171static int
3c4fdcfb 2172intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2173 struct drm_framebuffer *fb)
79e53945
JB		 2174{
2175 struct drm_device *dev = crtc->dev;
6b8e6ed0 2176 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2178 struct drm_framebuffer *old_fb;
5c3b82e2 2179 int ret;
79e53945
JB		 2180
2181 /* no fb bound */
94352cf9 2182 if (!fb) {
a5071c2f 2183 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2184 return 0;
2185 }
2186
7eb552ae 2187 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2188 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2189 plane_name(intel_crtc->plane),
2190 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2191 return -EINVAL;
79e53945
JB		 2192 }
2193
5c3b82e2 2194 mutex_lock(&dev->struct_mutex);
265db958 2195 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2196 to_intel_framebuffer(fb)->obj,
919926ae 2197 NULL);
5c3b82e2
CW		 2198 if (ret != 0) {
2199 mutex_unlock(&dev->struct_mutex);
a5071c2f 2200 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2201 return ret;
2202 }
79e53945 2203
94352cf9 2204 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2205 if (ret) {
94352cf9 2206 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2207 mutex_unlock(&dev->struct_mutex);
a5071c2f 2208 DRM_ERROR("failed to update base address\n");
4e6cfefc 2209 return ret;
79e53945 2210 }
3c4fdcfb 2211
94352cf9
DV		 2212 old_fb = crtc->fb;
2213 crtc->fb = fb;
6c4c86f5
DV		 2214 crtc->x = x;
2215 crtc->y = y;
94352cf9 2216
b7f1de28 2217 if (old_fb) {
d7697eea
DV		 2218 if (intel_crtc->active && old_fb != fb)
2219 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2220 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2221 }
652c393a 2222
6b8e6ed0 2223 intel_update_fbc(dev);
5c3b82e2 2224 mutex_unlock(&dev->struct_mutex);
79e53945 2225
198598d0 2226 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2227
2228 return 0;
79e53945
JB		 2229}
2230
5e84e1a4
ZW		 2231static void intel_fdi_normal_train(struct drm_crtc *crtc)
2232{
2233 struct drm_device *dev = crtc->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236 int pipe = intel_crtc->pipe;
2237 u32 reg, temp;
2238
2239 /* enable normal train */
2240 reg = FDI_TX_CTL(pipe);
2241 temp = I915_READ(reg);
61e499bf 2242 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2243 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2244 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2245 } else {
2246 temp &= ~FDI_LINK_TRAIN_NONE;
2247 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2248 }
5e84e1a4
ZW		 2249 I915_WRITE(reg, temp);
2250
2251 reg = FDI_RX_CTL(pipe);
2252 temp = I915_READ(reg);
2253 if (HAS_PCH_CPT(dev)) {
2254 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2255 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2256 } else {
2257 temp &= ~FDI_LINK_TRAIN_NONE;
2258 temp |= FDI_LINK_TRAIN_NONE;
2259 }
2260 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2261
2262 /* wait one idle pattern time */
2263 POSTING_READ(reg);
2264 udelay(1000);
357555c0
JB		 2265
2266 /* IVB wants error correction enabled */
2267 if (IS_IVYBRIDGE(dev))
2268 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2269 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2270}
2271
1e833f40
DV		 2272static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2273{
2274 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2275}
2276
01a415fd
DV		 2277static void ivb_modeset_global_resources(struct drm_device *dev)
2278{
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280 struct intel_crtc *pipe_B_crtc =
2281 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2282 struct intel_crtc *pipe_C_crtc =
2283 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2284 uint32_t temp;
2285
1e833f40
DV		 2286 /*
2287 * When everything is off disable fdi C so that we could enable fdi B
2288 * with all lanes. Note that we don't care about enabled pipes without
2289 * an enabled pch encoder.
2290 */
2291 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2292 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2293 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2294 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2295
2296 temp = I915_READ(SOUTH_CHICKEN1);
2297 temp &= ~FDI_BC_BIFURCATION_SELECT;
2298 DRM_DEBUG_KMS("disabling fdi C rx\n");
2299 I915_WRITE(SOUTH_CHICKEN1, temp);
2300 }
2301}
2302
8db9d77b
ZW		 2303/* The FDI link training functions for ILK/Ibexpeak. */
2304static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2305{
2306 struct drm_device *dev = crtc->dev;
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309 int pipe = intel_crtc->pipe;
0fc932b8 2310 int plane = intel_crtc->plane;
5eddb70b 2311 u32 reg, temp, tries;
8db9d77b 2312
0fc932b8
JB		 2313 /* FDI needs bits from pipe & plane first */
2314 assert_pipe_enabled(dev_priv, pipe);
2315 assert_plane_enabled(dev_priv, plane);
2316
e1a44743
AJ		 2317 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2318 for train result */
5eddb70b
CW		 2319 reg = FDI_RX_IMR(pipe);
2320 temp = I915_READ(reg);
e1a44743
AJ		 2321 temp &= ~FDI_RX_SYMBOL_LOCK;
2322 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2323 I915_WRITE(reg, temp);
2324 I915_READ(reg);
e1a44743
AJ		 2325 udelay(150);
2326
8db9d77b 2327 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2328 reg = FDI_TX_CTL(pipe);
2329 temp = I915_READ(reg);
627eb5a3
DV		 2330 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2331 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2332 temp &= ~FDI_LINK_TRAIN_NONE;
2333 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2334 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2335
5eddb70b
CW		 2336 reg = FDI_RX_CTL(pipe);
2337 temp = I915_READ(reg);
8db9d77b
ZW		 2338 temp &= ~FDI_LINK_TRAIN_NONE;
2339 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2340 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2341
2342 POSTING_READ(reg);
8db9d77b
ZW		 2343 udelay(150);
2344
5b2adf89 2345 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2346 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2347 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2348 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2349
5eddb70b 2350 reg = FDI_RX_IIR(pipe);
e1a44743 2351 for (tries = 0; tries < 5; tries++) {
5eddb70b 2352 temp = I915_READ(reg);
8db9d77b
ZW		 2353 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2354
2355 if ((temp & FDI_RX_BIT_LOCK)) {
2356 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2357 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2358 break;
2359 }
8db9d77b 2360 }
e1a44743 2361 if (tries == 5)
5eddb70b 2362 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2363
2364 /* Train 2 */
5eddb70b
CW		 2365 reg = FDI_TX_CTL(pipe);
2366 temp = I915_READ(reg);
8db9d77b
ZW		 2367 temp &= ~FDI_LINK_TRAIN_NONE;
2368 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2369 I915_WRITE(reg, temp);
8db9d77b 2370
5eddb70b
CW		 2371 reg = FDI_RX_CTL(pipe);
2372 temp = I915_READ(reg);
8db9d77b
ZW		 2373 temp &= ~FDI_LINK_TRAIN_NONE;
2374 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2375 I915_WRITE(reg, temp);
8db9d77b 2376
5eddb70b
CW		 2377 POSTING_READ(reg);
2378 udelay(150);
8db9d77b 2379
5eddb70b 2380 reg = FDI_RX_IIR(pipe);
e1a44743 2381 for (tries = 0; tries < 5; tries++) {
5eddb70b 2382 temp = I915_READ(reg);
8db9d77b
ZW		 2383 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2384
2385 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2386 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2387 DRM_DEBUG_KMS("FDI train 2 done.\n");
2388 break;
2389 }
8db9d77b 2390 }
e1a44743 2391 if (tries == 5)
5eddb70b 2392 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2393
2394 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2395
8db9d77b
ZW		 2396}
2397
0206e353 2398static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2399 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2400 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2401 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2402 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2403};
2404
2405/* The FDI link training functions for SNB/Cougarpoint. */
2406static void gen6_fdi_link_train(struct drm_crtc *crtc)
2407{
2408 struct drm_device *dev = crtc->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411 int pipe = intel_crtc->pipe;
fa37d39e 2412 u32 reg, temp, i, retry;
8db9d77b 2413
e1a44743
AJ		 2414 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2415 for train result */
5eddb70b
CW		 2416 reg = FDI_RX_IMR(pipe);
2417 temp = I915_READ(reg);
e1a44743
AJ		 2418 temp &= ~FDI_RX_SYMBOL_LOCK;
2419 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2420 I915_WRITE(reg, temp);
2421
2422 POSTING_READ(reg);
e1a44743
AJ		 2423 udelay(150);
2424
8db9d77b 2425 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
627eb5a3
DV		 2428 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2429 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_1;
2432 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2433 /* SNB-B */
2434 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2435 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2436
d74cf324
DV		 2437 I915_WRITE(FDI_RX_MISC(pipe),
2438 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2439
5eddb70b
CW		 2440 reg = FDI_RX_CTL(pipe);
2441 temp = I915_READ(reg);
8db9d77b
ZW		 2442 if (HAS_PCH_CPT(dev)) {
2443 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2444 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2445 } else {
2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 }
5eddb70b
CW		 2449 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2450
2451 POSTING_READ(reg);
8db9d77b
ZW		 2452 udelay(150);
2453
0206e353 2454 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2455 reg = FDI_TX_CTL(pipe);
2456 temp = I915_READ(reg);
8db9d77b
ZW		 2457 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2458 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2459 I915_WRITE(reg, temp);
2460
2461 POSTING_READ(reg);
8db9d77b
ZW		 2462 udelay(500);
2463
fa37d39e
SP		 2464 for (retry = 0; retry < 5; retry++) {
2465 reg = FDI_RX_IIR(pipe);
2466 temp = I915_READ(reg);
2467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468 if (temp & FDI_RX_BIT_LOCK) {
2469 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2470 DRM_DEBUG_KMS("FDI train 1 done.\n");
2471 break;
2472 }
2473 udelay(50);
8db9d77b 2474 }
fa37d39e
SP		 2475 if (retry < 5)
2476 break;
8db9d77b
ZW		 2477 }
2478 if (i == 4)
5eddb70b 2479 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2480
2481 /* Train 2 */
5eddb70b
CW		 2482 reg = FDI_TX_CTL(pipe);
2483 temp = I915_READ(reg);
8db9d77b
ZW		 2484 temp &= ~FDI_LINK_TRAIN_NONE;
2485 temp |= FDI_LINK_TRAIN_PATTERN_2;
2486 if (IS_GEN6(dev)) {
2487 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2488 /* SNB-B */
2489 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2490 }
5eddb70b 2491 I915_WRITE(reg, temp);
8db9d77b 2492
5eddb70b
CW		 2493 reg = FDI_RX_CTL(pipe);
2494 temp = I915_READ(reg);
8db9d77b
ZW		 2495 if (HAS_PCH_CPT(dev)) {
2496 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2498 } else {
2499 temp &= ~FDI_LINK_TRAIN_NONE;
2500 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501 }
5eddb70b
CW		 2502 I915_WRITE(reg, temp);
2503
2504 POSTING_READ(reg);
8db9d77b
ZW		 2505 udelay(150);
2506
0206e353 2507 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2508 reg = FDI_TX_CTL(pipe);
2509 temp = I915_READ(reg);
8db9d77b
ZW		 2510 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2512 I915_WRITE(reg, temp);
2513
2514 POSTING_READ(reg);
8db9d77b
ZW		 2515 udelay(500);
2516
fa37d39e
SP		 2517 for (retry = 0; retry < 5; retry++) {
2518 reg = FDI_RX_IIR(pipe);
2519 temp = I915_READ(reg);
2520 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521 if (temp & FDI_RX_SYMBOL_LOCK) {
2522 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2523 DRM_DEBUG_KMS("FDI train 2 done.\n");
2524 break;
2525 }
2526 udelay(50);
8db9d77b 2527 }
fa37d39e
SP		 2528 if (retry < 5)
2529 break;
8db9d77b
ZW		 2530 }
2531 if (i == 4)
5eddb70b 2532 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2533
2534 DRM_DEBUG_KMS("FDI train done.\n");
2535}
2536
357555c0
JB		 2537/* Manual link training for Ivy Bridge A0 parts */
2538static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2539{
2540 struct drm_device *dev = crtc->dev;
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2543 int pipe = intel_crtc->pipe;
2544 u32 reg, temp, i;
2545
2546 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2547 for train result */
2548 reg = FDI_RX_IMR(pipe);
2549 temp = I915_READ(reg);
2550 temp &= ~FDI_RX_SYMBOL_LOCK;
2551 temp &= ~FDI_RX_BIT_LOCK;
2552 I915_WRITE(reg, temp);
2553
2554 POSTING_READ(reg);
2555 udelay(150);
2556
01a415fd
DV		 2557 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2558 I915_READ(FDI_RX_IIR(pipe)));
2559
357555c0
JB		 2560 /* enable CPU FDI TX and PCH FDI RX */
2561 reg = FDI_TX_CTL(pipe);
2562 temp = I915_READ(reg);
627eb5a3
DV		 2563 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2564 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2565 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2566 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2567 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2568 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2569 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2570 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2571
d74cf324
DV		 2572 I915_WRITE(FDI_RX_MISC(pipe),
2573 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2574
357555c0
JB		 2575 reg = FDI_RX_CTL(pipe);
2576 temp = I915_READ(reg);
2577 temp &= ~FDI_LINK_TRAIN_AUTO;
2578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2580 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2581 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2582
2583 POSTING_READ(reg);
2584 udelay(150);
2585
0206e353 2586 for (i = 0; i < 4; i++) {
357555c0
JB		 2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590 temp |= snb_b_fdi_train_param[i];
2591 I915_WRITE(reg, temp);
2592
2593 POSTING_READ(reg);
2594 udelay(500);
2595
2596 reg = FDI_RX_IIR(pipe);
2597 temp = I915_READ(reg);
2598 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2599
2600 if (temp & FDI_RX_BIT_LOCK ||
2601 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2602 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2603 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2604 break;
2605 }
2606 }
2607 if (i == 4)
2608 DRM_ERROR("FDI train 1 fail!\n");
2609
2610 /* Train 2 */
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2615 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2617 I915_WRITE(reg, temp);
2618
2619 reg = FDI_RX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2622 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
2626 udelay(150);
2627
0206e353 2628 for (i = 0; i < 4; i++) {
357555c0
JB		 2629 reg = FDI_TX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2632 temp |= snb_b_fdi_train_param[i];
2633 I915_WRITE(reg, temp);
2634
2635 POSTING_READ(reg);
2636 udelay(500);
2637
2638 reg = FDI_RX_IIR(pipe);
2639 temp = I915_READ(reg);
2640 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2641
2642 if (temp & FDI_RX_SYMBOL_LOCK) {
2643 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2644 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2645 break;
2646 }
2647 }
2648 if (i == 4)
2649 DRM_ERROR("FDI train 2 fail!\n");
2650
2651 DRM_DEBUG_KMS("FDI train done.\n");
2652}
2653
88cefb6c 2654static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2655{
88cefb6c 2656 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2657 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2658 int pipe = intel_crtc->pipe;
5eddb70b 2659 u32 reg, temp;
79e53945 2660
c64e311e 2661
c98e9dcf 2662 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
627eb5a3
DV		 2665 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2667 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2668 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2669
2670 POSTING_READ(reg);
c98e9dcf
JB		 2671 udelay(200);
2672
2673 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2674 temp = I915_READ(reg);
2675 I915_WRITE(reg, temp | FDI_PCDCLK);
2676
2677 POSTING_READ(reg);
c98e9dcf
JB		 2678 udelay(200);
2679
20749730
PZ		 2680 /* Enable CPU FDI TX PLL, always on for Ironlake */
2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2684 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2685
20749730
PZ		 2686 POSTING_READ(reg);
2687 udelay(100);
6be4a607 2688 }
0e23b99d
JB		 2689}
2690
88cefb6c
DV		 2691static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2692{
2693 struct drm_device *dev = intel_crtc->base.dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 int pipe = intel_crtc->pipe;
2696 u32 reg, temp;
2697
2698 /* Switch from PCDclk to Rawclk */
2699 reg = FDI_RX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2702
2703 /* Disable CPU FDI TX PLL */
2704 reg = FDI_TX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2707
2708 POSTING_READ(reg);
2709 udelay(100);
2710
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2714
2715 /* Wait for the clocks to turn off. */
2716 POSTING_READ(reg);
2717 udelay(100);
2718}
2719
0fc932b8
JB		 2720static void ironlake_fdi_disable(struct drm_crtc *crtc)
2721{
2722 struct drm_device *dev = crtc->dev;
2723 struct drm_i915_private *dev_priv = dev->dev_private;
2724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2725 int pipe = intel_crtc->pipe;
2726 u32 reg, temp;
2727
2728 /* disable CPU FDI tx and PCH FDI rx */
2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2732 POSTING_READ(reg);
2733
2734 reg = FDI_RX_CTL(pipe);
2735 temp = I915_READ(reg);
2736 temp &= ~(0x7 << 16);
dfd07d72 2737 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2738 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2739
2740 POSTING_READ(reg);
2741 udelay(100);
2742
2743 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2744 if (HAS_PCH_IBX(dev)) {
2745 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2746 }
0fc932b8
JB		 2747
2748 /* still set train pattern 1 */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~FDI_LINK_TRAIN_NONE;
2752 temp |= FDI_LINK_TRAIN_PATTERN_1;
2753 I915_WRITE(reg, temp);
2754
2755 reg = FDI_RX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 if (HAS_PCH_CPT(dev)) {
2758 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2759 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2760 } else {
2761 temp &= ~FDI_LINK_TRAIN_NONE;
2762 temp |= FDI_LINK_TRAIN_PATTERN_1;
2763 }
2764 /* BPC in FDI rx is consistent with that in PIPECONF */
2765 temp &= ~(0x07 << 16);
dfd07d72 2766 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2767 I915_WRITE(reg, temp);
2768
2769 POSTING_READ(reg);
2770 udelay(100);
2771}
2772
5bb61643
CW		 2773static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2774{
2775 struct drm_device *dev = crtc->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2778 unsigned long flags;
2779 bool pending;
2780
10d83730
VS		 2781 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2782 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2783 return false;
2784
2785 spin_lock_irqsave(&dev->event_lock, flags);
2786 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2787 spin_unlock_irqrestore(&dev->event_lock, flags);
2788
2789 return pending;
2790}
2791
e6c3a2a6
CW		 2792static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2793{
0f91128d 2794 struct drm_device *dev = crtc->dev;
5bb61643 2795 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2796
2797 if (crtc->fb == NULL)
2798 return;
2799
2c10d571
DV		 2800 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2801
5bb61643
CW		 2802 wait_event(dev_priv->pending_flip_queue,
2803 !intel_crtc_has_pending_flip(crtc));
2804
0f91128d
CW		 2805 mutex_lock(&dev->struct_mutex);
2806 intel_finish_fb(crtc->fb);
2807 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2808}
2809
e615efe4
ED		 2810/* Program iCLKIP clock to the desired frequency */
2811static void lpt_program_iclkip(struct drm_crtc *crtc)
2812{
2813 struct drm_device *dev = crtc->dev;
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2816 u32 temp;
2817
09153000
DV		 2818 mutex_lock(&dev_priv->dpio_lock);
2819
e615efe4
ED		 2820 /* It is necessary to ungate the pixclk gate prior to programming
2821 * the divisors, and gate it back when it is done.
2822 */
2823 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2824
2825 /* Disable SSCCTL */
2826 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2827 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2828 SBI_SSCCTL_DISABLE,
2829 SBI_ICLK);
e615efe4
ED		 2830
2831 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2832 if (crtc->mode.clock == 20000) {
2833 auxdiv = 1;
2834 divsel = 0x41;
2835 phaseinc = 0x20;
2836 } else {
2837 /* The iCLK virtual clock root frequency is in MHz,
2838 * but the crtc->mode.clock in in KHz. To get the divisors,
2839 * it is necessary to divide one by another, so we
2840 * convert the virtual clock precision to KHz here for higher
2841 * precision.
2842 */
2843 u32 iclk_virtual_root_freq = 172800 * 1000;
2844 u32 iclk_pi_range = 64;
2845 u32 desired_divisor, msb_divisor_value, pi_value;
2846
2847 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2848 msb_divisor_value = desired_divisor / iclk_pi_range;
2849 pi_value = desired_divisor % iclk_pi_range;
2850
2851 auxdiv = 0;
2852 divsel = msb_divisor_value - 2;
2853 phaseinc = pi_value;
2854 }
2855
2856 /* This should not happen with any sane values */
2857 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2858 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2859 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2860 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2861
2862 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2863 crtc->mode.clock,
2864 auxdiv,
2865 divsel,
2866 phasedir,
2867 phaseinc);
2868
2869 /* Program SSCDIVINTPHASE6 */
988d6ee8 2870 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2871 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2872 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2873 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2874 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2875 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2876 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2877 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2878
2879 /* Program SSCAUXDIV */
988d6ee8 2880 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2881 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2882 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2883 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2884
2885 /* Enable modulator and associated divider */
988d6ee8 2886 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2887 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2888 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2889
2890 /* Wait for initialization time */
2891 udelay(24);
2892
2893 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2894
2895 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2896}
2897
275f01b2
DV		 2898static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2899 enum pipe pch_transcoder)
2900{
2901 struct drm_device *dev = crtc->base.dev;
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2904
2905 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2906 I915_READ(HTOTAL(cpu_transcoder)));
2907 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2908 I915_READ(HBLANK(cpu_transcoder)));
2909 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2910 I915_READ(HSYNC(cpu_transcoder)));
2911
2912 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2913 I915_READ(VTOTAL(cpu_transcoder)));
2914 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2915 I915_READ(VBLANK(cpu_transcoder)));
2916 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2917 I915_READ(VSYNC(cpu_transcoder)));
2918 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2919 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2920}
2921
f67a559d
JB		 2922/*
2923 * Enable PCH resources required for PCH ports:
2924 * - PCH PLLs
2925 * - FDI training & RX/TX
2926 * - update transcoder timings
2927 * - DP transcoding bits
2928 * - transcoder
2929 */
2930static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2931{
2932 struct drm_device *dev = crtc->dev;
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935 int pipe = intel_crtc->pipe;
ee7b9f93 2936 u32 reg, temp;
2c07245f 2937
ab9412ba 2938 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2939
cd986abb
DV		 2940 /* Write the TU size bits before fdi link training, so that error
2941 * detection works. */
2942 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2943 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2944
c98e9dcf 2945 /* For PCH output, training FDI link */
674cf967 2946 dev_priv->display.fdi_link_train(crtc);
2c07245f 2947
572deb37
DV		 2948 /* XXX: pch pll's can be enabled any time before we enable the PCH
2949 * transcoder, and we actually should do this to not upset any PCH
2950 * transcoder that already use the clock when we share it.
2951 *
2952 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2953 * unconditionally resets the pll - we need that to have the right LVDS
2954 * enable sequence. */
b6b4e185 2955 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 2956
303b81e0 2957 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2958 u32 sel;
4b645f14 2959
c98e9dcf 2960 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2961 switch (pipe) {
2962 default:
2963 case 0:
2964 temp |= TRANSA_DPLL_ENABLE;
2965 sel = TRANSA_DPLLB_SEL;
2966 break;
2967 case 1:
2968 temp |= TRANSB_DPLL_ENABLE;
2969 sel = TRANSB_DPLLB_SEL;
2970 break;
2971 case 2:
2972 temp |= TRANSC_DPLL_ENABLE;
2973 sel = TRANSC_DPLLB_SEL;
2974 break;
d64311ab 2975 }
ee7b9f93
JB		 2976 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2977 temp |= sel;
2978 else
2979 temp &= ~sel;
c98e9dcf 2980 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2981 }
5eddb70b 2982
d9b6cb56
JB		 2983 /* set transcoder timing, panel must allow it */
2984 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2985 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2986
303b81e0 2987 intel_fdi_normal_train(crtc);
5e84e1a4 2988
c98e9dcf
JB		 2989 /* For PCH DP, enable TRANS_DP_CTL */
2990 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2991 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2992 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2993 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2994 reg = TRANS_DP_CTL(pipe);
2995 temp = I915_READ(reg);
2996 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2997 TRANS_DP_SYNC_MASK |
2998 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2999 temp |= (TRANS_DP_OUTPUT_ENABLE |
3000 TRANS_DP_ENH_FRAMING);
9325c9f0 3001 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3002
3003 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3004 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3005 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3006 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3007
3008 switch (intel_trans_dp_port_sel(crtc)) {
3009 case PCH_DP_B:
5eddb70b 3010 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3011 break;
3012 case PCH_DP_C:
5eddb70b 3013 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3014 break;
3015 case PCH_DP_D:
5eddb70b 3016 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3017 break;
3018 default:
e95d41e1 3019 BUG();
32f9d658 3020 }
2c07245f 3021
5eddb70b 3022 I915_WRITE(reg, temp);
6be4a607 3023 }
b52eb4dc 3024
b8a4f404 3025 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3026}
3027
1507e5bd
PZ		 3028static void lpt_pch_enable(struct drm_crtc *crtc)
3029{
3030 struct drm_device *dev = crtc->dev;
3031 struct drm_i915_private *dev_priv = dev->dev_private;
3032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3033 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3034
ab9412ba 3035 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3036
8c52b5e8 3037 lpt_program_iclkip(crtc);
1507e5bd 3038
0540e488 3039 /* Set transcoder timing. */
275f01b2 3040 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3041
937bb610 3042 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3043}
3044
ee7b9f93
JB		 3045static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3046{
3047 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3048
3049 if (pll == NULL)
3050 return;
3051
3052 if (pll->refcount == 0) {
3053 WARN(1, "bad PCH PLL refcount\n");
3054 return;
3055 }
3056
3057 --pll->refcount;
3058 intel_crtc->pch_pll = NULL;
3059}
3060
3061static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3062{
3063 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3064 struct intel_pch_pll *pll;
3065 int i;
3066
3067 pll = intel_crtc->pch_pll;
3068 if (pll) {
3069 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3070 intel_crtc->base.base.id, pll->pll_reg);
3071 goto prepare;
3072 }
3073
98b6bd99
DV		 3074 if (HAS_PCH_IBX(dev_priv->dev)) {
3075 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3076 i = intel_crtc->pipe;
3077 pll = &dev_priv->pch_plls[i];
3078
3079 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3080 intel_crtc->base.base.id, pll->pll_reg);
3081
3082 goto found;
3083 }
3084
ee7b9f93
JB		 3085 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3086 pll = &dev_priv->pch_plls[i];
3087
3088 /* Only want to check enabled timings first */
3089 if (pll->refcount == 0)
3090 continue;
3091
3092 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3093 fp == I915_READ(pll->fp0_reg)) {
3094 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3095 intel_crtc->base.base.id,
3096 pll->pll_reg, pll->refcount, pll->active);
3097
3098 goto found;
3099 }
3100 }
3101
3102 /* Ok no matching timings, maybe there's a free one? */
3103 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3104 pll = &dev_priv->pch_plls[i];
3105 if (pll->refcount == 0) {
3106 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3107 intel_crtc->base.base.id, pll->pll_reg);
3108 goto found;
3109 }
3110 }
3111
3112 return NULL;
3113
3114found:
3115 intel_crtc->pch_pll = pll;
3116 pll->refcount++;
84f44ce7 3117 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3118prepare: /* separate function? */
3119 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3120
e04c7350
CW		 3121 /* Wait for the clocks to stabilize before rewriting the regs */
3122 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3123 POSTING_READ(pll->pll_reg);
3124 udelay(150);
e04c7350
CW		 3125
3126 I915_WRITE(pll->fp0_reg, fp);
3127 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3128 pll->on = false;
3129 return pll;
3130}
3131
a1520318 3132static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3133{
3134 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3135 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3136 u32 temp;
3137
3138 temp = I915_READ(dslreg);
3139 udelay(500);
3140 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3141 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3142 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3143 }
3144}
3145
b074cec8
JB		 3146static void ironlake_pfit_enable(struct intel_crtc *crtc)
3147{
3148 struct drm_device *dev = crtc->base.dev;
3149 struct drm_i915_private *dev_priv = dev->dev_private;
3150 int pipe = crtc->pipe;
3151
0ef37f3f 3152 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3153 /* Force use of hard-coded filter coefficients
3154 * as some pre-programmed values are broken,
3155 * e.g. x201.
3156 */
3157 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3158 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3159 PF_PIPE_SEL_IVB(pipe));
3160 else
3161 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3162 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3163 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3164 }
3165}
3166
f67a559d
JB		 3167static void ironlake_crtc_enable(struct drm_crtc *crtc)
3168{
3169 struct drm_device *dev = crtc->dev;
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3172 struct intel_encoder *encoder;
f67a559d
JB		 3173 int pipe = intel_crtc->pipe;
3174 int plane = intel_crtc->plane;
3175 u32 temp;
f67a559d 3176
08a48469
DV		 3177 WARN_ON(!crtc->enabled);
3178
f67a559d
JB		 3179 if (intel_crtc->active)
3180 return;
3181
3182 intel_crtc->active = true;
8664281b
PZ		 3183
3184 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3185 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3186
f67a559d
JB		 3187 intel_update_watermarks(dev);
3188
3189 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3190 temp = I915_READ(PCH_LVDS);
3191 if ((temp & LVDS_PORT_EN) == 0)
3192 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3193 }
3194
f67a559d 3195
5bfe2ac0 3196 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3197 /* Note: FDI PLL enabling _must_ be done before we enable the
3198 * cpu pipes, hence this is separate from all the other fdi/pch
3199 * enabling. */
88cefb6c 3200 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3201 } else {
3202 assert_fdi_tx_disabled(dev_priv, pipe);
3203 assert_fdi_rx_disabled(dev_priv, pipe);
3204 }
f67a559d 3205
bf49ec8c
DV		 3206 for_each_encoder_on_crtc(dev, crtc, encoder)
3207 if (encoder->pre_enable)
3208 encoder->pre_enable(encoder);
f67a559d
JB		 3209
3210 /* Enable panel fitting for LVDS */
b074cec8 3211 ironlake_pfit_enable(intel_crtc);
f67a559d 3212
9c54c0dd
JB		 3213 /*
3214 * On ILK+ LUT must be loaded before the pipe is running but with
3215 * clocks enabled
3216 */
3217 intel_crtc_load_lut(crtc);
3218
5bfe2ac0
DV		 3219 intel_enable_pipe(dev_priv, pipe,
3220 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3221 intel_enable_plane(dev_priv, plane, pipe);
3222
5bfe2ac0 3223 if (intel_crtc->config.has_pch_encoder)
f67a559d 3224 ironlake_pch_enable(crtc);
c98e9dcf 3225
d1ebd816 3226 mutex_lock(&dev->struct_mutex);
bed4a673 3227 intel_update_fbc(dev);
d1ebd816
BW		 3228 mutex_unlock(&dev->struct_mutex);
3229
6b383a7f 3230 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3231
fa5c73b1
DV		 3232 for_each_encoder_on_crtc(dev, crtc, encoder)
3233 encoder->enable(encoder);
61b77ddd
DV		 3234
3235 if (HAS_PCH_CPT(dev))
a1520318 3236 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3237
3238 /*
3239 * There seems to be a race in PCH platform hw (at least on some
3240 * outputs) where an enabled pipe still completes any pageflip right
3241 * away (as if the pipe is off) instead of waiting for vblank. As soon
3242 * as the first vblank happend, everything works as expected. Hence just
3243 * wait for one vblank before returning to avoid strange things
3244 * happening.
3245 */
3246 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3247}
3248
42db64ef
PZ		 3249/* IPS only exists on ULT machines and is tied to pipe A. */
3250static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3251{
3252 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3253}
3254
3255static void hsw_enable_ips(struct intel_crtc *crtc)
3256{
3257 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3258
3259 if (!crtc->config.ips_enabled)
3260 return;
3261
3262 /* We can only enable IPS after we enable a plane and wait for a vblank.
3263 * We guarantee that the plane is enabled by calling intel_enable_ips
3264 * only after intel_enable_plane. And intel_enable_plane already waits
3265 * for a vblank, so all we need to do here is to enable the IPS bit. */
3266 assert_plane_enabled(dev_priv, crtc->plane);
3267 I915_WRITE(IPS_CTL, IPS_ENABLE);
3268}
3269
3270static void hsw_disable_ips(struct intel_crtc *crtc)
3271{
3272 struct drm_device *dev = crtc->base.dev;
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274
3275 if (!crtc->config.ips_enabled)
3276 return;
3277
3278 assert_plane_enabled(dev_priv, crtc->plane);
3279 I915_WRITE(IPS_CTL, 0);
3280
3281 /* We need to wait for a vblank before we can disable the plane. */
3282 intel_wait_for_vblank(dev, crtc->pipe);
3283}
3284
4f771f10
PZ		 3285static void haswell_crtc_enable(struct drm_crtc *crtc)
3286{
3287 struct drm_device *dev = crtc->dev;
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290 struct intel_encoder *encoder;
3291 int pipe = intel_crtc->pipe;
3292 int plane = intel_crtc->plane;
4f771f10
PZ		 3293
3294 WARN_ON(!crtc->enabled);
3295
3296 if (intel_crtc->active)
3297 return;
3298
3299 intel_crtc->active = true;
8664281b
PZ		 3300
3301 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3302 if (intel_crtc->config.has_pch_encoder)
3303 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3304
4f771f10
PZ		 3305 intel_update_watermarks(dev);
3306
5bfe2ac0 3307 if (intel_crtc->config.has_pch_encoder)
04945641 3308 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3309
3310 for_each_encoder_on_crtc(dev, crtc, encoder)
3311 if (encoder->pre_enable)
3312 encoder->pre_enable(encoder);
3313
1f544388 3314 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3315
1f544388 3316 /* Enable panel fitting for eDP */
b074cec8 3317 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3318
3319 /*
3320 * On ILK+ LUT must be loaded before the pipe is running but with
3321 * clocks enabled
3322 */
3323 intel_crtc_load_lut(crtc);
3324
1f544388 3325 intel_ddi_set_pipe_settings(crtc);
8228c251 3326 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3327
5bfe2ac0
DV		 3328 intel_enable_pipe(dev_priv, pipe,
3329 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3330 intel_enable_plane(dev_priv, plane, pipe);
3331
42db64ef
PZ		 3332 hsw_enable_ips(intel_crtc);
3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3335 lpt_pch_enable(crtc);
4f771f10
PZ		 3336
3337 mutex_lock(&dev->struct_mutex);
3338 intel_update_fbc(dev);
3339 mutex_unlock(&dev->struct_mutex);
3340
3341 intel_crtc_update_cursor(crtc, true);
3342
3343 for_each_encoder_on_crtc(dev, crtc, encoder)
3344 encoder->enable(encoder);
3345
4f771f10
PZ		 3346 /*
3347 * There seems to be a race in PCH platform hw (at least on some
3348 * outputs) where an enabled pipe still completes any pageflip right
3349 * away (as if the pipe is off) instead of waiting for vblank. As soon
3350 * as the first vblank happend, everything works as expected. Hence just
3351 * wait for one vblank before returning to avoid strange things
3352 * happening.
3353 */
3354 intel_wait_for_vblank(dev, intel_crtc->pipe);
3355}
3356
3f8dce3a
DV		 3357static void ironlake_pfit_disable(struct intel_crtc *crtc)
3358{
3359 struct drm_device *dev = crtc->base.dev;
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 int pipe = crtc->pipe;
3362
3363 /* To avoid upsetting the power well on haswell only disable the pfit if
3364 * it's in use. The hw state code will make sure we get this right. */
3365 if (crtc->config.pch_pfit.size) {
3366 I915_WRITE(PF_CTL(pipe), 0);
3367 I915_WRITE(PF_WIN_POS(pipe), 0);
3368 I915_WRITE(PF_WIN_SZ(pipe), 0);
3369 }
3370}
3371
6be4a607
JB		 3372static void ironlake_crtc_disable(struct drm_crtc *crtc)
3373{
3374 struct drm_device *dev = crtc->dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3377 struct intel_encoder *encoder;
6be4a607
JB		 3378 int pipe = intel_crtc->pipe;
3379 int plane = intel_crtc->plane;
5eddb70b 3380 u32 reg, temp;
b52eb4dc 3381
ef9c3aee 3382
f7abfe8b
CW		 3383 if (!intel_crtc->active)
3384 return;
3385
ea9d758d
DV		 3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->disable(encoder);
3388
e6c3a2a6 3389 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3390 drm_vblank_off(dev, pipe);
6b383a7f 3391 intel_crtc_update_cursor(crtc, false);
5eddb70b 3392
b24e7179 3393 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3394
973d04f9
CW		 3395 if (dev_priv->cfb_plane == plane)
3396 intel_disable_fbc(dev);
2c07245f 3397
8664281b 3398 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3399 intel_disable_pipe(dev_priv, pipe);
32f9d658 3400
3f8dce3a 3401 ironlake_pfit_disable(intel_crtc);
2c07245f 3402
bf49ec8c
DV		 3403 for_each_encoder_on_crtc(dev, crtc, encoder)
3404 if (encoder->post_disable)
3405 encoder->post_disable(encoder);
2c07245f 3406
0fc932b8 3407 ironlake_fdi_disable(crtc);
249c0e64 3408
b8a4f404 3409 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3410 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3411
6be4a607
JB		 3412 if (HAS_PCH_CPT(dev)) {
3413 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3414 reg = TRANS_DP_CTL(pipe);
3415 temp = I915_READ(reg);
3416 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3417 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3418 I915_WRITE(reg, temp);
6be4a607
JB		 3419
3420 /* disable DPLL_SEL */
3421 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3422 switch (pipe) {
3423 case 0:
d64311ab 3424 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3425 break;
3426 case 1:
6be4a607 3427 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3428 break;
3429 case 2:
4b645f14 3430 /* C shares PLL A or B */
d64311ab 3431 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3432 break;
3433 default:
3434 BUG(); /* wtf */
3435 }
6be4a607 3436 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3437 }
e3421a18 3438
6be4a607 3439 /* disable PCH DPLL */
ee7b9f93 3440 intel_disable_pch_pll(intel_crtc);
8db9d77b 3441
88cefb6c 3442 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3443
f7abfe8b 3444 intel_crtc->active = false;
6b383a7f 3445 intel_update_watermarks(dev);
d1ebd816
BW		 3446
3447 mutex_lock(&dev->struct_mutex);
6b383a7f 3448 intel_update_fbc(dev);
d1ebd816 3449 mutex_unlock(&dev->struct_mutex);
6be4a607 3450}
1b3c7a47 3451
4f771f10 3452static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3453{
4f771f10
PZ		 3454 struct drm_device *dev = crtc->dev;
3455 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3457 struct intel_encoder *encoder;
3458 int pipe = intel_crtc->pipe;
3459 int plane = intel_crtc->plane;
3b117c8f 3460 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3461
4f771f10
PZ		 3462 if (!intel_crtc->active)
3463 return;
3464
3465 for_each_encoder_on_crtc(dev, crtc, encoder)
3466 encoder->disable(encoder);
3467
3468 intel_crtc_wait_for_pending_flips(crtc);
3469 drm_vblank_off(dev, pipe);
3470 intel_crtc_update_cursor(crtc, false);
3471
891348b2 3472 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3473 if (dev_priv->cfb_plane == plane)
3474 intel_disable_fbc(dev);
3475
42db64ef
PZ		 3476 hsw_disable_ips(intel_crtc);
3477
891348b2
RV		 3478 intel_disable_plane(dev_priv, plane, pipe);
3479
8664281b
PZ		 3480 if (intel_crtc->config.has_pch_encoder)
3481 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3482 intel_disable_pipe(dev_priv, pipe);
3483
ad80a810 3484 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3485
3f8dce3a 3486 ironlake_pfit_disable(intel_crtc);
4f771f10 3487
1f544388 3488 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3489
3490 for_each_encoder_on_crtc(dev, crtc, encoder)
3491 if (encoder->post_disable)
3492 encoder->post_disable(encoder);
3493
88adfff1 3494 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3495 lpt_disable_pch_transcoder(dev_priv);
8664281b 3496 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3497 intel_ddi_fdi_disable(crtc);
83616634 3498 }
4f771f10
PZ		 3499
3500 intel_crtc->active = false;
3501 intel_update_watermarks(dev);
3502
3503 mutex_lock(&dev->struct_mutex);
3504 intel_update_fbc(dev);
3505 mutex_unlock(&dev->struct_mutex);
3506}
3507
ee7b9f93
JB		 3508static void ironlake_crtc_off(struct drm_crtc *crtc)
3509{
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511 intel_put_pch_pll(intel_crtc);
3512}
3513
6441ab5f
PZ		 3514static void haswell_crtc_off(struct drm_crtc *crtc)
3515{
3516 intel_ddi_put_crtc_pll(crtc);
3517}
3518
02e792fb
DV		 3519static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3520{
02e792fb 3521 if (!enable && intel_crtc->overlay) {
23f09ce3 3522 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3523 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3524
23f09ce3 3525 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3526 dev_priv->mm.interruptible = false;
3527 (void) intel_overlay_switch_off(intel_crtc->overlay);
3528 dev_priv->mm.interruptible = true;
23f09ce3 3529 mutex_unlock(&dev->struct_mutex);
02e792fb 3530 }
02e792fb 3531
5dcdbcb0
CW		 3532 /* Let userspace switch the overlay on again. In most cases userspace
3533 * has to recompute where to put it anyway.
3534 */
02e792fb
DV		 3535}
3536
61bc95c1
EE		 3537/**
3538 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3539 * cursor plane briefly if not already running after enabling the display
3540 * plane.
3541 * This workaround avoids occasional blank screens when self refresh is
3542 * enabled.
3543 */
3544static void
3545g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3546{
3547 u32 cntl = I915_READ(CURCNTR(pipe));
3548
3549 if ((cntl & CURSOR_MODE) == 0) {
3550 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3551
3552 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3553 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3554 intel_wait_for_vblank(dev_priv->dev, pipe);
3555 I915_WRITE(CURCNTR(pipe), cntl);
3556 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3557 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3558 }
3559}
3560
2dd24552
JB		 3561static void i9xx_pfit_enable(struct intel_crtc *crtc)
3562{
3563 struct drm_device *dev = crtc->base.dev;
3564 struct drm_i915_private *dev_priv = dev->dev_private;
3565 struct intel_crtc_config *pipe_config = &crtc->config;
3566
328d8e82 3567 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3568 return;
3569
2dd24552 3570 /*
c0b03411
DV		 3571 * The panel fitter should only be adjusted whilst the pipe is disabled,
3572 * according to register description and PRM.
2dd24552 3573 */
c0b03411
DV		 3574 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3575 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3576
b074cec8
JB		 3577 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3578 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3579
3580 /* Border color in case we don't scale up to the full screen. Black by
3581 * default, change to something else for debugging. */
3582 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3583}
3584
89b667f8
JB		 3585static void valleyview_crtc_enable(struct drm_crtc *crtc)
3586{
3587 struct drm_device *dev = crtc->dev;
3588 struct drm_i915_private *dev_priv = dev->dev_private;
3589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3590 struct intel_encoder *encoder;
3591 int pipe = intel_crtc->pipe;
3592 int plane = intel_crtc->plane;
3593
3594 WARN_ON(!crtc->enabled);
3595
3596 if (intel_crtc->active)
3597 return;
3598
3599 intel_crtc->active = true;
3600 intel_update_watermarks(dev);
3601
3602 mutex_lock(&dev_priv->dpio_lock);
3603
3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 if (encoder->pre_pll_enable)
3606 encoder->pre_pll_enable(encoder);
3607
3608 intel_enable_pll(dev_priv, pipe);
3609
3610 for_each_encoder_on_crtc(dev, crtc, encoder)
3611 if (encoder->pre_enable)
3612 encoder->pre_enable(encoder);
3613
3614 /* VLV wants encoder enabling _before_ the pipe is up. */
3615 for_each_encoder_on_crtc(dev, crtc, encoder)
3616 encoder->enable(encoder);
3617
2dd24552
JB		 3618 /* Enable panel fitting for eDP */
3619 i9xx_pfit_enable(intel_crtc);
3620
89b667f8
JB		 3621 intel_enable_pipe(dev_priv, pipe, false);
3622 intel_enable_plane(dev_priv, plane, pipe);
3623
3624 intel_crtc_load_lut(crtc);
3625 intel_update_fbc(dev);
3626
3627 /* Give the overlay scaler a chance to enable if it's on this pipe */
3628 intel_crtc_dpms_overlay(intel_crtc, true);
3629 intel_crtc_update_cursor(crtc, true);
3630
3631 mutex_unlock(&dev_priv->dpio_lock);
3632}
3633
0b8765c6 3634static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3635{
3636 struct drm_device *dev = crtc->dev;
79e53945
JB		 3637 struct drm_i915_private *dev_priv = dev->dev_private;
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3639 struct intel_encoder *encoder;
79e53945 3640 int pipe = intel_crtc->pipe;
80824003 3641 int plane = intel_crtc->plane;
79e53945 3642
08a48469
DV		 3643 WARN_ON(!crtc->enabled);
3644
f7abfe8b
CW		 3645 if (intel_crtc->active)
3646 return;
3647
3648 intel_crtc->active = true;
6b383a7f
CW		 3649 intel_update_watermarks(dev);
3650
63d7bbe9 3651 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3652
3653 for_each_encoder_on_crtc(dev, crtc, encoder)
3654 if (encoder->pre_enable)
3655 encoder->pre_enable(encoder);
3656
2dd24552
JB		 3657 /* Enable panel fitting for LVDS */
3658 i9xx_pfit_enable(intel_crtc);
3659
040484af 3660 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3661 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3662 if (IS_G4X(dev))
3663 g4x_fixup_plane(dev_priv, pipe);
79e53945 3664
0b8765c6 3665 intel_crtc_load_lut(crtc);
bed4a673 3666 intel_update_fbc(dev);
79e53945 3667
0b8765c6
JB		 3668 /* Give the overlay scaler a chance to enable if it's on this pipe */
3669 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3670 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3671
fa5c73b1
DV		 3672 for_each_encoder_on_crtc(dev, crtc, encoder)
3673 encoder->enable(encoder);
0b8765c6 3674}
79e53945 3675
87476d63
DV		 3676static void i9xx_pfit_disable(struct intel_crtc *crtc)
3677{
3678 struct drm_device *dev = crtc->base.dev;
3679 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3680
328d8e82
DV		 3681 if (!crtc->config.gmch_pfit.control)
3682 return;
87476d63 3683
328d8e82 3684 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3685
328d8e82
DV		 3686 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3687 I915_READ(PFIT_CONTROL));
3688 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3689}
3690
0b8765c6
JB		 3691static void i9xx_crtc_disable(struct drm_crtc *crtc)
3692{
3693 struct drm_device *dev = crtc->dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3696 struct intel_encoder *encoder;
0b8765c6
JB		 3697 int pipe = intel_crtc->pipe;
3698 int plane = intel_crtc->plane;
ef9c3aee 3699
f7abfe8b
CW		 3700 if (!intel_crtc->active)
3701 return;
3702
ea9d758d
DV		 3703 for_each_encoder_on_crtc(dev, crtc, encoder)
3704 encoder->disable(encoder);
3705
0b8765c6 3706 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3707 intel_crtc_wait_for_pending_flips(crtc);
3708 drm_vblank_off(dev, pipe);
0b8765c6 3709 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3710 intel_crtc_update_cursor(crtc, false);
0b8765c6 3711
973d04f9
CW		 3712 if (dev_priv->cfb_plane == plane)
3713 intel_disable_fbc(dev);
79e53945 3714
b24e7179 3715 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3716 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3717
87476d63 3718 i9xx_pfit_disable(intel_crtc);
24a1f16d 3719
89b667f8
JB		 3720 for_each_encoder_on_crtc(dev, crtc, encoder)
3721 if (encoder->post_disable)
3722 encoder->post_disable(encoder);
3723
63d7bbe9 3724 intel_disable_pll(dev_priv, pipe);
0b8765c6 3725
f7abfe8b 3726 intel_crtc->active = false;
6b383a7f
CW		 3727 intel_update_fbc(dev);
3728 intel_update_watermarks(dev);
0b8765c6
JB		 3729}
3730
ee7b9f93
JB		 3731static void i9xx_crtc_off(struct drm_crtc *crtc)
3732{
3733}
3734
976f8a20
DV		 3735static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3736 bool enabled)
2c07245f
ZW		 3737{
3738 struct drm_device *dev = crtc->dev;
3739 struct drm_i915_master_private *master_priv;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741 int pipe = intel_crtc->pipe;
79e53945
JB		 3742
3743 if (!dev->primary->master)
3744 return;
3745
3746 master_priv = dev->primary->master->driver_priv;
3747 if (!master_priv->sarea_priv)
3748 return;
3749
79e53945
JB		 3750 switch (pipe) {
3751 case 0:
3752 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3753 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3754 break;
3755 case 1:
3756 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3757 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3758 break;
3759 default:
9db4a9c7 3760 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3761 break;
3762 }
79e53945
JB		 3763}
3764
976f8a20
DV		 3765/**
3766 * Sets the power management mode of the pipe and plane.
3767 */
3768void intel_crtc_update_dpms(struct drm_crtc *crtc)
3769{
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 struct intel_encoder *intel_encoder;
3773 bool enable = false;
3774
3775 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3776 enable |= intel_encoder->connectors_active;
3777
3778 if (enable)
3779 dev_priv->display.crtc_enable(crtc);
3780 else
3781 dev_priv->display.crtc_disable(crtc);
3782
3783 intel_crtc_update_sarea(crtc, enable);
3784}
3785
cdd59983
CW		 3786static void intel_crtc_disable(struct drm_crtc *crtc)
3787{
cdd59983 3788 struct drm_device *dev = crtc->dev;
976f8a20 3789 struct drm_connector *connector;
ee7b9f93 3790 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3792
976f8a20
DV		 3793 /* crtc should still be enabled when we disable it. */
3794 WARN_ON(!crtc->enabled);
3795
3796 dev_priv->display.crtc_disable(crtc);
c77bf565 3797 intel_crtc->eld_vld = false;
976f8a20 3798 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3799 dev_priv->display.off(crtc);
3800
931872fc
CW		 3801 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3802 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3803
3804 if (crtc->fb) {
3805 mutex_lock(&dev->struct_mutex);
1690e1eb 3806 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3807 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3808 crtc->fb = NULL;
3809 }
3810
3811 /* Update computed state. */
3812 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3813 if (!connector->encoder || !connector->encoder->crtc)
3814 continue;
3815
3816 if (connector->encoder->crtc != crtc)
3817 continue;
3818
3819 connector->dpms = DRM_MODE_DPMS_OFF;
3820 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3821 }
3822}
3823
a261b246 3824void intel_modeset_disable(struct drm_device *dev)
79e53945 3825{
a261b246
DV		 3826 struct drm_crtc *crtc;
3827
3828 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3829 if (crtc->enabled)
3830 intel_crtc_disable(crtc);
3831 }
79e53945
JB		 3832}
3833
ea5b213a 3834void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3835{
4ef69c7a 3836 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3837
ea5b213a
CW		 3838 drm_encoder_cleanup(encoder);
3839 kfree(intel_encoder);
7e7d76c3
JB		 3840}
3841
5ab432ef
DV		 3842/* Simple dpms helper for encodres with just one connector, no cloning and only
3843 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3844 * state of the entire output pipe. */
3845void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3846{
5ab432ef
DV		 3847 if (mode == DRM_MODE_DPMS_ON) {
3848 encoder->connectors_active = true;
3849
b2cabb0e 3850 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3851 } else {
3852 encoder->connectors_active = false;
3853
b2cabb0e 3854 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3855 }
79e53945
JB		 3856}
3857
0a91ca29
DV		 3858/* Cross check the actual hw state with our own modeset state tracking (and it's
3859 * internal consistency). */
b980514c 3860static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3861{
0a91ca29
DV		 3862 if (connector->get_hw_state(connector)) {
3863 struct intel_encoder *encoder = connector->encoder;
3864 struct drm_crtc *crtc;
3865 bool encoder_enabled;
3866 enum pipe pipe;
3867
3868 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3869 connector->base.base.id,
3870 drm_get_connector_name(&connector->base));
3871
3872 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3873 "wrong connector dpms state\n");
3874 WARN(connector->base.encoder != &encoder->base,
3875 "active connector not linked to encoder\n");
3876 WARN(!encoder->connectors_active,
3877 "encoder->connectors_active not set\n");
3878
3879 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3880 WARN(!encoder_enabled, "encoder not enabled\n");
3881 if (WARN_ON(!encoder->base.crtc))
3882 return;
3883
3884 crtc = encoder->base.crtc;
3885
3886 WARN(!crtc->enabled, "crtc not enabled\n");
3887 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3888 WARN(pipe != to_intel_crtc(crtc)->pipe,
3889 "encoder active on the wrong pipe\n");
3890 }
79e53945
JB		 3891}
3892
5ab432ef
DV		 3893/* Even simpler default implementation, if there's really no special case to
3894 * consider. */
3895void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3896{
5ab432ef 3897 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3898
5ab432ef
DV		 3899 /* All the simple cases only support two dpms states. */
3900 if (mode != DRM_MODE_DPMS_ON)
3901 mode = DRM_MODE_DPMS_OFF;
d4270e57 3902
5ab432ef
DV		 3903 if (mode == connector->dpms)
3904 return;
3905
3906 connector->dpms = mode;
3907
3908 /* Only need to change hw state when actually enabled */
3909 if (encoder->base.crtc)
3910 intel_encoder_dpms(encoder, mode);
3911 else
8af6cf88 3912 WARN_ON(encoder->connectors_active != false);
0a91ca29 3913
b980514c 3914 intel_modeset_check_state(connector->dev);
79e53945
JB		 3915}
3916
f0947c37
DV		 3917/* Simple connector->get_hw_state implementation for encoders that support only
3918 * one connector and no cloning and hence the encoder state determines the state
3919 * of the connector. */
3920bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3921{
24929352 3922 enum pipe pipe = 0;
f0947c37 3923 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3924
f0947c37 3925 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3926}
3927
1857e1da
DV		 3928static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3929 struct intel_crtc_config *pipe_config)
3930{
3931 struct drm_i915_private *dev_priv = dev->dev_private;
3932 struct intel_crtc *pipe_B_crtc =
3933 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3934
3935 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3936 pipe_name(pipe), pipe_config->fdi_lanes);
3937 if (pipe_config->fdi_lanes > 4) {
3938 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3939 pipe_name(pipe), pipe_config->fdi_lanes);
3940 return false;
3941 }
3942
3943 if (IS_HASWELL(dev)) {
3944 if (pipe_config->fdi_lanes > 2) {
3945 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3946 pipe_config->fdi_lanes);
3947 return false;
3948 } else {
3949 return true;
3950 }
3951 }
3952
3953 if (INTEL_INFO(dev)->num_pipes == 2)
3954 return true;
3955
3956 /* Ivybridge 3 pipe is really complicated */
3957 switch (pipe) {
3958 case PIPE_A:
3959 return true;
3960 case PIPE_B:
3961 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3962 pipe_config->fdi_lanes > 2) {
3963 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3964 pipe_name(pipe), pipe_config->fdi_lanes);
3965 return false;
3966 }
3967 return true;
3968 case PIPE_C:
1e833f40 3969 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3970 pipe_B_crtc->config.fdi_lanes <= 2) {
3971 if (pipe_config->fdi_lanes > 2) {
3972 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3973 pipe_name(pipe), pipe_config->fdi_lanes);
3974 return false;
3975 }
3976 } else {
3977 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3978 return false;
3979 }
3980 return true;
3981 default:
3982 BUG();
3983 }
3984}
3985
e29c22c0
DV		 3986#define RETRY 1
3987static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3988 struct intel_crtc_config *pipe_config)
877d48d5 3989{
1857e1da 3990 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 3991 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 3992 int lane, link_bw, fdi_dotclock;
e29c22c0 3993 bool setup_ok, needs_recompute = false;
877d48d5 3994
e29c22c0 3995retry:
877d48d5
DV		 3996 /* FDI is a binary signal running at ~2.7GHz, encoding
3997 * each output octet as 10 bits. The actual frequency
3998 * is stored as a divider into a 100MHz clock, and the
3999 * mode pixel clock is stored in units of 1KHz.
4000 * Hence the bw of each lane in terms of the mode signal
4001 * is:
4002 */
4003 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4004
ff9a6750 4005 fdi_dotclock = adjusted_mode->clock;
2bd89a07
DV		 4006 if (pipe_config->pixel_multiplier > 1)
4007 fdi_dotclock /= pipe_config->pixel_multiplier;
4008
4009 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4010 pipe_config->pipe_bpp);
4011
4012 pipe_config->fdi_lanes = lane;
4013
2bd89a07 4014 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4015 link_bw, &pipe_config->fdi_m_n);
1857e1da 4016
e29c22c0
DV		 4017 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4018 intel_crtc->pipe, pipe_config);
4019 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4020 pipe_config->pipe_bpp -= 2*3;
4021 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4022 pipe_config->pipe_bpp);
4023 needs_recompute = true;
4024 pipe_config->bw_constrained = true;
4025
4026 goto retry;
4027 }
4028
4029 if (needs_recompute)
4030 return RETRY;
4031
4032 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4033}
4034
42db64ef
PZ		 4035static void hsw_compute_ips_config(struct intel_crtc *crtc,
4036 struct intel_crtc_config *pipe_config)
4037{
3c4ca58c
PZ		 4038 pipe_config->ips_enabled = i915_enable_ips &&
4039 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4040 pipe_config->pipe_bpp == 24;
4041}
4042
e29c22c0
DV		 4043static int intel_crtc_compute_config(struct drm_crtc *crtc,
4044 struct intel_crtc_config *pipe_config)
79e53945 4045{
2c07245f 4046 struct drm_device *dev = crtc->dev;
b8cecdf5 4047 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
42db64ef 4048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
89749350 4049
bad720ff 4050 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4051 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4052 if (pipe_config->requested_mode.clock * 3
4053 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4054 return -EINVAL;
2c07245f 4055 }
89749350 4056
f9bef081
DV		 4057 /* All interlaced capable intel hw wants timings in frames. Note though
4058 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4059 * timings, so we need to be careful not to clobber these.*/
7ae89233 4060 if (!pipe_config->timings_set)
f9bef081 4061 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4062
8693a824
DL		 4063 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4064 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4065 */
4066 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4067 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4068 return -EINVAL;
44f46b42 4069
bd080ee5 4070 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4071 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4072 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4073 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4074 * for lvds. */
4075 pipe_config->pipe_bpp = 8*3;
4076 }
4077
42db64ef
PZ		 4078 if (IS_HASWELL(dev))
4079 hsw_compute_ips_config(intel_crtc, pipe_config);
4080
877d48d5 4081 if (pipe_config->has_pch_encoder)
42db64ef 4082 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
877d48d5 4083
e29c22c0 4084 return 0;
79e53945
JB		 4085}
4086
25eb05fc
JB		 4087static int valleyview_get_display_clock_speed(struct drm_device *dev)
4088{
4089 return 400000; /* FIXME */
4090}
4091
e70236a8
JB		 4092static int i945_get_display_clock_speed(struct drm_device *dev)
4093{
4094 return 400000;
4095}
79e53945 4096
e70236a8 4097static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4098{
e70236a8
JB		 4099 return 333000;
4100}
79e53945 4101
e70236a8
JB		 4102static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4103{
4104 return 200000;
4105}
79e53945 4106
e70236a8
JB		 4107static int i915gm_get_display_clock_speed(struct drm_device *dev)
4108{
4109 u16 gcfgc = 0;
79e53945 4110
e70236a8
JB		 4111 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4112
4113 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4114 return 133000;
4115 else {
4116 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4117 case GC_DISPLAY_CLOCK_333_MHZ:
4118 return 333000;
4119 default:
4120 case GC_DISPLAY_CLOCK_190_200_MHZ:
4121 return 190000;
79e53945 4122 }
e70236a8
JB		 4123 }
4124}
4125
4126static int i865_get_display_clock_speed(struct drm_device *dev)
4127{
4128 return 266000;
4129}
4130
4131static int i855_get_display_clock_speed(struct drm_device *dev)
4132{
4133 u16 hpllcc = 0;
4134 /* Assume that the hardware is in the high speed state. This
4135 * should be the default.
4136 */
4137 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4138 case GC_CLOCK_133_200:
4139 case GC_CLOCK_100_200:
4140 return 200000;
4141 case GC_CLOCK_166_250:
4142 return 250000;
4143 case GC_CLOCK_100_133:
79e53945 4144 return 133000;
e70236a8 4145 }
79e53945 4146
e70236a8
JB		 4147 /* Shouldn't happen */
4148 return 0;
4149}
79e53945 4150
e70236a8
JB		 4151static int i830_get_display_clock_speed(struct drm_device *dev)
4152{
4153 return 133000;
79e53945
JB		 4154}
4155
2c07245f 4156static void
a65851af 4157intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4158{
a65851af
VS		 4159 while (*num > DATA_LINK_M_N_MASK ||
4160 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4161 *num >>= 1;
4162 *den >>= 1;
4163 }
4164}
4165
a65851af
VS		 4166static void compute_m_n(unsigned int m, unsigned int n,
4167 uint32_t *ret_m, uint32_t *ret_n)
4168{
4169 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4170 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4171 intel_reduce_m_n_ratio(ret_m, ret_n);
4172}
4173
e69d0bc1
DV		 4174void
4175intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4176 int pixel_clock, int link_clock,
4177 struct intel_link_m_n *m_n)
2c07245f 4178{
e69d0bc1 4179 m_n->tu = 64;
a65851af
VS		 4180
4181 compute_m_n(bits_per_pixel * pixel_clock,
4182 link_clock * nlanes * 8,
4183 &m_n->gmch_m, &m_n->gmch_n);
4184
4185 compute_m_n(pixel_clock, link_clock,
4186 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4187}
4188
a7615030
CW		 4189static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4190{
72bbe58c
KP		 4191 if (i915_panel_use_ssc >= 0)
4192 return i915_panel_use_ssc != 0;
41aa3448 4193 return dev_priv->vbt.lvds_use_ssc
435793df 4194 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4195}
4196
a0c4da24
JB		 4197static int vlv_get_refclk(struct drm_crtc *crtc)
4198{
4199 struct drm_device *dev = crtc->dev;
4200 struct drm_i915_private *dev_priv = dev->dev_private;
4201 int refclk = 27000; /* for DP & HDMI */
4202
4203 return 100000; /* only one validated so far */
4204
4205 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4206 refclk = 96000;
4207 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4208 if (intel_panel_use_ssc(dev_priv))
4209 refclk = 100000;
4210 else
4211 refclk = 96000;
4212 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4213 refclk = 100000;
4214 }
4215
4216 return refclk;
4217}
4218
c65d77d8
JB		 4219static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4220{
4221 struct drm_device *dev = crtc->dev;
4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223 int refclk;
4224
a0c4da24
JB		 4225 if (IS_VALLEYVIEW(dev)) {
4226 refclk = vlv_get_refclk(crtc);
4227 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4228 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4229 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4230 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4231 refclk / 1000);
4232 } else if (!IS_GEN2(dev)) {
4233 refclk = 96000;
4234 } else {
4235 refclk = 48000;
4236 }
4237
4238 return refclk;
4239}
4240
7429e9d4
DV		 4241static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4242{
4243 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4244}
4245
4246static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4247{
4248 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4249}
4250
f47709a9 4251static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4252 intel_clock_t *reduced_clock)
4253{
f47709a9 4254 struct drm_device *dev = crtc->base.dev;
a7516a05 4255 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4256 int pipe = crtc->pipe;
a7516a05
JB		 4257 u32 fp, fp2 = 0;
4258
4259 if (IS_PINEVIEW(dev)) {
7429e9d4 4260 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4261 if (reduced_clock)
7429e9d4 4262 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4263 } else {
7429e9d4 4264 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4265 if (reduced_clock)
7429e9d4 4266 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4267 }
4268
4269 I915_WRITE(FP0(pipe), fp);
4270
f47709a9
DV		 4271 crtc->lowfreq_avail = false;
4272 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4273 reduced_clock && i915_powersave) {
4274 I915_WRITE(FP1(pipe), fp2);
f47709a9 4275 crtc->lowfreq_avail = true;
a7516a05
JB		 4276 } else {
4277 I915_WRITE(FP1(pipe), fp);
4278 }
4279}
4280
89b667f8
JB		 4281static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4282{
4283 u32 reg_val;
4284
4285 /*
4286 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4287 * and set it to a reasonable value instead.
4288 */
ae99258f 4289 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4290 reg_val &= 0xffffff00;
4291 reg_val |= 0x00000030;
ae99258f 4292 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4293
ae99258f 4294 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4295 reg_val &= 0x8cffffff;
4296 reg_val = 0x8c000000;
ae99258f 4297 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4298
ae99258f 4299 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4300 reg_val &= 0xffffff00;
ae99258f 4301 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4302
ae99258f 4303 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4304 reg_val &= 0x00ffffff;
4305 reg_val |= 0xb0000000;
ae99258f 4306 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4307}
4308
b551842d
DV		 4309static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4310 struct intel_link_m_n *m_n)
4311{
4312 struct drm_device *dev = crtc->base.dev;
4313 struct drm_i915_private *dev_priv = dev->dev_private;
4314 int pipe = crtc->pipe;
4315
e3b95f1e
DV		 4316 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4317 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4318 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4319 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4320}
4321
4322static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4323 struct intel_link_m_n *m_n)
4324{
4325 struct drm_device *dev = crtc->base.dev;
4326 struct drm_i915_private *dev_priv = dev->dev_private;
4327 int pipe = crtc->pipe;
4328 enum transcoder transcoder = crtc->config.cpu_transcoder;
4329
4330 if (INTEL_INFO(dev)->gen >= 5) {
4331 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4332 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4333 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4334 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4335 } else {
e3b95f1e
DV		 4336 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4337 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4338 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4339 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4340 }
4341}
4342
03afc4a2
DV		 4343static void intel_dp_set_m_n(struct intel_crtc *crtc)
4344{
4345 if (crtc->config.has_pch_encoder)
4346 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4347 else
4348 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4349}
4350
f47709a9 4351static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4352{
f47709a9 4353 struct drm_device *dev = crtc->base.dev;
a0c4da24 4354 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4355 struct intel_encoder *encoder;
f47709a9 4356 int pipe = crtc->pipe;
89b667f8 4357 u32 dpll, mdiv;
a0c4da24 4358 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4359 bool is_hdmi;
198a037f 4360 u32 coreclk, reg_val, dpll_md;
a0c4da24 4361
09153000
DV		 4362 mutex_lock(&dev_priv->dpio_lock);
4363
89b667f8 4364 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4365
f47709a9
DV		 4366 bestn = crtc->config.dpll.n;
4367 bestm1 = crtc->config.dpll.m1;
4368 bestm2 = crtc->config.dpll.m2;
4369 bestp1 = crtc->config.dpll.p1;
4370 bestp2 = crtc->config.dpll.p2;
a0c4da24 4371
89b667f8
JB		 4372 /* See eDP HDMI DPIO driver vbios notes doc */
4373
4374 /* PLL B needs special handling */
4375 if (pipe)
4376 vlv_pllb_recal_opamp(dev_priv);
4377
4378 /* Set up Tx target for periodic Rcomp update */
ae99258f 4379 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4380
4381 /* Disable target IRef on PLL */
ae99258f 4382 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4383 reg_val &= 0x00ffffff;
ae99258f 4384 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4385
4386 /* Disable fast lock */
ae99258f 4387 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4388
4389 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4390 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4391 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4392 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4393 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4394
4395 /*
4396 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4397 * but we don't support that).
4398 * Note: don't use the DAC post divider as it seems unstable.
4399 */
4400 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4401 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4402
89b667f8 4403 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4404 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4405
89b667f8 4406 /* Set HBR and RBR LPF coefficients */
ff9a6750 4407 if (crtc->config.port_clock == 162000 ||
89b667f8 4408 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4409 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4410 0x005f0021);
4411 else
ae99258f 4412 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4413 0x00d0000f);
4414
4415 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4416 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4417 /* Use SSC source */
4418 if (!pipe)
ae99258f 4419 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4420 0x0df40000);
4421 else
ae99258f 4422 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4423 0x0df70000);
4424 } else { /* HDMI or VGA */
4425 /* Use bend source */
4426 if (!pipe)
ae99258f 4427 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4428 0x0df70000);
4429 else
ae99258f 4430 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4431 0x0df40000);
4432 }
a0c4da24 4433
ae99258f 4434 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4435 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4436 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4437 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4438 coreclk |= 0x01000000;
ae99258f 4439 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4440
ae99258f 4441 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4442
89b667f8
JB		 4443 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4444 if (encoder->pre_pll_enable)
4445 encoder->pre_pll_enable(encoder);
2a8f64ca 4446
89b667f8
JB		 4447 /* Enable DPIO clock input */
4448 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4449 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4450 if (pipe)
4451 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4452
89b667f8 4453 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4454 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4455 POSTING_READ(DPLL(pipe));
4456 udelay(150);
a0c4da24 4457
89b667f8
JB		 4458 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4459 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4460
198a037f
DV		 4461 dpll_md = 0;
4462 if (crtc->config.pixel_multiplier > 1) {
4463 dpll_md = (crtc->config.pixel_multiplier - 1)
4464 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4465 }
198a037f
DV		 4466 I915_WRITE(DPLL_MD(pipe), dpll_md);
4467 POSTING_READ(DPLL_MD(pipe));
f47709a9 4468
89b667f8
JB		 4469 if (crtc->config.has_dp_encoder)
4470 intel_dp_set_m_n(crtc);
09153000
DV		 4471
4472 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4473}
4474
f47709a9
DV		 4475static void i9xx_update_pll(struct intel_crtc *crtc,
4476 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4477 int num_connectors)
4478{
f47709a9 4479 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4480 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4481 struct intel_encoder *encoder;
f47709a9 4482 int pipe = crtc->pipe;
eb1cbe48
DV		 4483 u32 dpll;
4484 bool is_sdvo;
f47709a9 4485 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4486
f47709a9 4487 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4488
f47709a9
DV		 4489 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4490 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4491
4492 dpll = DPLL_VGA_MODE_DIS;
4493
f47709a9 4494 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4495 dpll |= DPLLB_MODE_LVDS;
4496 else
4497 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4498
198a037f
DV		 4499 if ((crtc->config.pixel_multiplier > 1) &&
4500 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4501 dpll |= (crtc->config.pixel_multiplier - 1)
4502 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4503 }
198a037f
DV		 4504
4505 if (is_sdvo)
4506 dpll |= DPLL_DVO_HIGH_SPEED;
4507
f47709a9 4508 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4509 dpll |= DPLL_DVO_HIGH_SPEED;
4510
4511 /* compute bitmask from p1 value */
4512 if (IS_PINEVIEW(dev))
4513 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4514 else {
4515 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4516 if (IS_G4X(dev) && reduced_clock)
4517 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4518 }
4519 switch (clock->p2) {
4520 case 5:
4521 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4522 break;
4523 case 7:
4524 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4525 break;
4526 case 10:
4527 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4528 break;
4529 case 14:
4530 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4531 break;
4532 }
4533 if (INTEL_INFO(dev)->gen >= 4)
4534 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4535
09ede541 4536 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4537 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4538 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4539 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4540 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4541 else
4542 dpll |= PLL_REF_INPUT_DREFCLK;
4543
4544 dpll |= DPLL_VCO_ENABLE;
4545 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4546 POSTING_READ(DPLL(pipe));
4547 udelay(150);
4548
f47709a9 4549 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4550 if (encoder->pre_pll_enable)
4551 encoder->pre_pll_enable(encoder);
eb1cbe48 4552
f47709a9
DV		 4553 if (crtc->config.has_dp_encoder)
4554 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4555
4556 I915_WRITE(DPLL(pipe), dpll);
4557
4558 /* Wait for the clocks to stabilize. */
4559 POSTING_READ(DPLL(pipe));
4560 udelay(150);
4561
4562 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4563 u32 dpll_md = 0;
4564 if (crtc->config.pixel_multiplier > 1) {
4565 dpll_md = (crtc->config.pixel_multiplier - 1)
4566 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4567 }
198a037f 4568 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4569 } else {
4570 /* The pixel multiplier can only be updated once the
4571 * DPLL is enabled and the clocks are stable.
4572 *
4573 * So write it again.
4574 */
4575 I915_WRITE(DPLL(pipe), dpll);
4576 }
4577}
4578
f47709a9 4579static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4580 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4581 int num_connectors)
4582{
f47709a9 4583 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4584 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4585 struct intel_encoder *encoder;
f47709a9 4586 int pipe = crtc->pipe;
eb1cbe48 4587 u32 dpll;
f47709a9 4588 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4589
f47709a9 4590 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4591
eb1cbe48
DV		 4592 dpll = DPLL_VGA_MODE_DIS;
4593
f47709a9 4594 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4595 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4596 } else {
4597 if (clock->p1 == 2)
4598 dpll |= PLL_P1_DIVIDE_BY_TWO;
4599 else
4600 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4601 if (clock->p2 == 4)
4602 dpll |= PLL_P2_DIVIDE_BY_4;
4603 }
4604
f47709a9 4605 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4606 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4607 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4608 else
4609 dpll |= PLL_REF_INPUT_DREFCLK;
4610
4611 dpll |= DPLL_VCO_ENABLE;
4612 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4613 POSTING_READ(DPLL(pipe));
4614 udelay(150);
4615
f47709a9 4616 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4617 if (encoder->pre_pll_enable)
4618 encoder->pre_pll_enable(encoder);
eb1cbe48 4619
5b5896e4
DV		 4620 I915_WRITE(DPLL(pipe), dpll);
4621
4622 /* Wait for the clocks to stabilize. */
4623 POSTING_READ(DPLL(pipe));
4624 udelay(150);
4625
eb1cbe48
DV		 4626 /* The pixel multiplier can only be updated once the
4627 * DPLL is enabled and the clocks are stable.
4628 *
4629 * So write it again.
4630 */
4631 I915_WRITE(DPLL(pipe), dpll);
4632}
4633
8a654f3b 4634static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4635{
4636 struct drm_device *dev = intel_crtc->base.dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4639 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4640 struct drm_display_mode *adjusted_mode =
4641 &intel_crtc->config.adjusted_mode;
4642 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4643 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4644
4645 /* We need to be careful not to changed the adjusted mode, for otherwise
4646 * the hw state checker will get angry at the mismatch. */
4647 crtc_vtotal = adjusted_mode->crtc_vtotal;
4648 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4649
4650 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4651 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4652 crtc_vtotal -= 1;
4653 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4654 vsyncshift = adjusted_mode->crtc_hsync_start
4655 - adjusted_mode->crtc_htotal / 2;
4656 } else {
4657 vsyncshift = 0;
4658 }
4659
4660 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4661 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4662
fe2b8f9d 4663 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4664 (adjusted_mode->crtc_hdisplay - 1) |
4665 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4666 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4667 (adjusted_mode->crtc_hblank_start - 1) |
4668 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4669 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4670 (adjusted_mode->crtc_hsync_start - 1) |
4671 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4672
fe2b8f9d 4673 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4674 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4675 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4676 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4677 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4678 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4679 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4680 (adjusted_mode->crtc_vsync_start - 1) |
4681 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4682
b5e508d4
PZ		 4683 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4684 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4685 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4686 * bits. */
4687 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4688 (pipe == PIPE_B || pipe == PIPE_C))
4689 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4690
b0e77b9c
PZ		 4691 /* pipesrc controls the size that is scaled from, which should
4692 * always be the user's requested size.
4693 */
4694 I915_WRITE(PIPESRC(pipe),
4695 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4696}
4697
1bd1bd80
DV		 4698static void intel_get_pipe_timings(struct intel_crtc *crtc,
4699 struct intel_crtc_config *pipe_config)
4700{
4701 struct drm_device *dev = crtc->base.dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4704 uint32_t tmp;
4705
4706 tmp = I915_READ(HTOTAL(cpu_transcoder));
4707 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4708 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4709 tmp = I915_READ(HBLANK(cpu_transcoder));
4710 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4711 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4712 tmp = I915_READ(HSYNC(cpu_transcoder));
4713 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4714 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4715
4716 tmp = I915_READ(VTOTAL(cpu_transcoder));
4717 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4718 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4719 tmp = I915_READ(VBLANK(cpu_transcoder));
4720 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4721 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4722 tmp = I915_READ(VSYNC(cpu_transcoder));
4723 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4724 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4725
4726 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4727 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4728 pipe_config->adjusted_mode.crtc_vtotal += 1;
4729 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4730 }
4731
4732 tmp = I915_READ(PIPESRC(crtc->pipe));
4733 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4734 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4735}
4736
84b046f3
DV		 4737static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4738{
4739 struct drm_device *dev = intel_crtc->base.dev;
4740 struct drm_i915_private *dev_priv = dev->dev_private;
4741 uint32_t pipeconf;
4742
4743 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4744
4745 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4746 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4747 * core speed.
4748 *
4749 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4750 * pipe == 0 check?
4751 */
4752 if (intel_crtc->config.requested_mode.clock >
4753 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4754 pipeconf |= PIPECONF_DOUBLE_WIDE;
4755 else
4756 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4757 }
4758
ff9ce46e
DV		 4759 /* only g4x and later have fancy bpc/dither controls */
4760 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4761 pipeconf &= ~(PIPECONF_BPC_MASK |
4762 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4763
4764 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4765 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4766 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4767 PIPECONF_DITHER_TYPE_SP;
84b046f3 4768
ff9ce46e
DV		 4769 switch (intel_crtc->config.pipe_bpp) {
4770 case 18:
4771 pipeconf |= PIPECONF_6BPC;
4772 break;
4773 case 24:
4774 pipeconf |= PIPECONF_8BPC;
4775 break;
4776 case 30:
4777 pipeconf |= PIPECONF_10BPC;
4778 break;
4779 default:
4780 /* Case prevented by intel_choose_pipe_bpp_dither. */
4781 BUG();
84b046f3
DV		 4782 }
4783 }
4784
4785 if (HAS_PIPE_CXSR(dev)) {
4786 if (intel_crtc->lowfreq_avail) {
4787 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4788 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4789 } else {
4790 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4791 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4792 }
4793 }
4794
4795 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4796 if (!IS_GEN2(dev) &&
4797 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4798 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4799 else
4800 pipeconf |= PIPECONF_PROGRESSIVE;
4801
9c8e09b7
VS		 4802 if (IS_VALLEYVIEW(dev)) {
4803 if (intel_crtc->config.limited_color_range)
4804 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4805 else
4806 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4807 }
4808
84b046f3
DV		 4809 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4810 POSTING_READ(PIPECONF(intel_crtc->pipe));
4811}
4812
f564048e 4813static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4814 int x, int y,
94352cf9 4815 struct drm_framebuffer *fb)
79e53945
JB		 4816{
4817 struct drm_device *dev = crtc->dev;
4818 struct drm_i915_private *dev_priv = dev->dev_private;
4819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4820 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4821 int pipe = intel_crtc->pipe;
80824003 4822 int plane = intel_crtc->plane;
c751ce4f 4823 int refclk, num_connectors = 0;
652c393a 4824 intel_clock_t clock, reduced_clock;
84b046f3 4825 u32 dspcntr;
a16af721
DV		 4826 bool ok, has_reduced_clock = false;
4827 bool is_lvds = false;
5eddb70b 4828 struct intel_encoder *encoder;
d4906093 4829 const intel_limit_t *limit;
5c3b82e2 4830 int ret;
79e53945 4831
6c2b7c12 4832 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4833 switch (encoder->type) {
79e53945
JB		 4834 case INTEL_OUTPUT_LVDS:
4835 is_lvds = true;
4836 break;
79e53945 4837 }
43565a06 4838
c751ce4f 4839 num_connectors++;
79e53945
JB		 4840 }
4841
c65d77d8 4842 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4843
d4906093
ML		 4844 /*
4845 * Returns a set of divisors for the desired target clock with the given
4846 * refclk, or FALSE. The returned values represent the clock equation:
4847 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4848 */
1b894b59 4849 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4850 ok = dev_priv->display.find_dpll(limit, crtc,
4851 intel_crtc->config.port_clock,
ee9300bb
DV		 4852 refclk, NULL, &clock);
4853 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4854 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4855 return -EINVAL;
79e53945
JB		 4856 }
4857
cda4b7d3 4858 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4859 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4860
ddc9003c 4861 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4862 /*
4863 * Ensure we match the reduced clock's P to the target clock.
4864 * If the clocks don't match, we can't switch the display clock
4865 * by using the FP0/FP1. In such case we will disable the LVDS
4866 * downclock feature.
4867 */
ee9300bb
DV		 4868 has_reduced_clock =
4869 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4870 dev_priv->lvds_downclock,
ee9300bb 4871 refclk, &clock,
5eddb70b 4872 &reduced_clock);
7026d4ac 4873 }
f47709a9
DV		 4874 /* Compat-code for transition, will disappear. */
4875 if (!intel_crtc->config.clock_set) {
4876 intel_crtc->config.dpll.n = clock.n;
4877 intel_crtc->config.dpll.m1 = clock.m1;
4878 intel_crtc->config.dpll.m2 = clock.m2;
4879 intel_crtc->config.dpll.p1 = clock.p1;
4880 intel_crtc->config.dpll.p2 = clock.p2;
4881 }
7026d4ac 4882
eb1cbe48 4883 if (IS_GEN2(dev))
8a654f3b 4884 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4885 has_reduced_clock ? &reduced_clock : NULL,
4886 num_connectors);
a0c4da24 4887 else if (IS_VALLEYVIEW(dev))
f47709a9 4888 vlv_update_pll(intel_crtc);
79e53945 4889 else
f47709a9 4890 i9xx_update_pll(intel_crtc,
eb1cbe48 4891 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4892 num_connectors);
79e53945 4893
79e53945
JB		 4894 /* Set up the display plane register */
4895 dspcntr = DISPPLANE_GAMMA_ENABLE;
4896
da6ecc5d
JB		 4897 if (!IS_VALLEYVIEW(dev)) {
4898 if (pipe == 0)
4899 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4900 else
4901 dspcntr |= DISPPLANE_SEL_PIPE_B;
4902 }
79e53945 4903
8a654f3b 4904 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4905
4906 /* pipesrc and dspsize control the size that is scaled from,
4907 * which should always be the user's requested size.
79e53945 4908 */
929c77fb
EA		 4909 I915_WRITE(DSPSIZE(plane),
4910 ((mode->vdisplay - 1) << 16) |
4911 (mode->hdisplay - 1));
4912 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4913
84b046f3
DV		 4914 i9xx_set_pipeconf(intel_crtc);
4915
f564048e
EA		 4916 I915_WRITE(DSPCNTR(plane), dspcntr);
4917 POSTING_READ(DSPCNTR(plane));
4918
94352cf9 4919 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4920
4921 intel_update_watermarks(dev);
4922
f564048e
EA		 4923 return ret;
4924}
4925
2fa2fe9a
DV		 4926static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4927 struct intel_crtc_config *pipe_config)
4928{
4929 struct drm_device *dev = crtc->base.dev;
4930 struct drm_i915_private *dev_priv = dev->dev_private;
4931 uint32_t tmp;
4932
4933 tmp = I915_READ(PFIT_CONTROL);
4934
4935 if (INTEL_INFO(dev)->gen < 4) {
4936 if (crtc->pipe != PIPE_B)
4937 return;
4938
4939 /* gen2/3 store dither state in pfit control, needs to match */
4940 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4941 } else {
4942 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4943 return;
4944 }
4945
4946 if (!(tmp & PFIT_ENABLE))
4947 return;
4948
4949 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4950 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4951 if (INTEL_INFO(dev)->gen < 5)
4952 pipe_config->gmch_pfit.lvds_border_bits =
4953 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4954}
4955
0e8ffe1b
DV		 4956static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4957 struct intel_crtc_config *pipe_config)
4958{
4959 struct drm_device *dev = crtc->base.dev;
4960 struct drm_i915_private *dev_priv = dev->dev_private;
4961 uint32_t tmp;
4962
eccb140b
DV		 4963 pipe_config->cpu_transcoder = crtc->pipe;
4964
0e8ffe1b
DV		 4965 tmp = I915_READ(PIPECONF(crtc->pipe));
4966 if (!(tmp & PIPECONF_ENABLE))
4967 return false;
4968
1bd1bd80
DV		 4969 intel_get_pipe_timings(crtc, pipe_config);
4970
2fa2fe9a
DV		 4971 i9xx_get_pfit_config(crtc, pipe_config);
4972
0e8ffe1b
DV		 4973 return true;
4974}
4975
dde86e2d 4976static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4977{
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4980 struct intel_encoder *encoder;
74cfd7ac 4981 u32 val, final;
13d83a67 4982 bool has_lvds = false;
199e5d79 4983 bool has_cpu_edp = false;
199e5d79 4984 bool has_panel = false;
99eb6a01
KP		 4985 bool has_ck505 = false;
4986 bool can_ssc = false;
13d83a67
JB		 4987
4988 /* We need to take the global config into account */
199e5d79
KP		 4989 list_for_each_entry(encoder, &mode_config->encoder_list,
4990 base.head) {
4991 switch (encoder->type) {
4992 case INTEL_OUTPUT_LVDS:
4993 has_panel = true;
4994 has_lvds = true;
4995 break;
4996 case INTEL_OUTPUT_EDP:
4997 has_panel = true;
2de6905f 4998 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 4999 has_cpu_edp = true;
5000 break;
13d83a67
JB		 5001 }
5002 }
5003
99eb6a01 5004 if (HAS_PCH_IBX(dev)) {
41aa3448 5005 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5006 can_ssc = has_ck505;
5007 } else {
5008 has_ck505 = false;
5009 can_ssc = true;
5010 }
5011
2de6905f
ID		 5012 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5013 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5014
5015 /* Ironlake: try to setup display ref clock before DPLL
5016 * enabling. This is only under driver's control after
5017 * PCH B stepping, previous chipset stepping should be
5018 * ignoring this setting.
5019 */
74cfd7ac
CW		 5020 val = I915_READ(PCH_DREF_CONTROL);
5021
5022 /* As we must carefully and slowly disable/enable each source in turn,
5023 * compute the final state we want first and check if we need to
5024 * make any changes at all.
5025 */
5026 final = val;
5027 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5028 if (has_ck505)
5029 final |= DREF_NONSPREAD_CK505_ENABLE;
5030 else
5031 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5032
5033 final &= ~DREF_SSC_SOURCE_MASK;
5034 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5035 final &= ~DREF_SSC1_ENABLE;
5036
5037 if (has_panel) {
5038 final |= DREF_SSC_SOURCE_ENABLE;
5039
5040 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5041 final |= DREF_SSC1_ENABLE;
5042
5043 if (has_cpu_edp) {
5044 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5045 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5046 else
5047 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5048 } else
5049 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5050 } else {
5051 final |= DREF_SSC_SOURCE_DISABLE;
5052 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5053 }
5054
5055 if (final == val)
5056 return;
5057
13d83a67 5058 /* Always enable nonspread source */
74cfd7ac 5059 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5060
99eb6a01 5061 if (has_ck505)
74cfd7ac 5062 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5063 else
74cfd7ac 5064 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5065
199e5d79 5066 if (has_panel) {
74cfd7ac
CW		 5067 val &= ~DREF_SSC_SOURCE_MASK;
5068 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5069
199e5d79 5070 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5071 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5072 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5073 val |= DREF_SSC1_ENABLE;
e77166b5 5074 } else
74cfd7ac 5075 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5076
5077 /* Get SSC going before enabling the outputs */
74cfd7ac 5078 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5079 POSTING_READ(PCH_DREF_CONTROL);
5080 udelay(200);
5081
74cfd7ac 5082 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5083
5084 /* Enable CPU source on CPU attached eDP */
199e5d79 5085 if (has_cpu_edp) {
99eb6a01 5086 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5087 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5088 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5089 }
13d83a67 5090 else
74cfd7ac 5091 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5092 } else
74cfd7ac 5093 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5094
74cfd7ac 5095 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5096 POSTING_READ(PCH_DREF_CONTROL);
5097 udelay(200);
5098 } else {
5099 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5100
74cfd7ac 5101 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5102
5103 /* Turn off CPU output */
74cfd7ac 5104 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5105
74cfd7ac 5106 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5107 POSTING_READ(PCH_DREF_CONTROL);
5108 udelay(200);
5109
5110 /* Turn off the SSC source */
74cfd7ac
CW		 5111 val &= ~DREF_SSC_SOURCE_MASK;
5112 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5113
5114 /* Turn off SSC1 */
74cfd7ac 5115 val &= ~DREF_SSC1_ENABLE;
199e5d79 5116
74cfd7ac 5117 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5118 POSTING_READ(PCH_DREF_CONTROL);
5119 udelay(200);
5120 }
74cfd7ac
CW		 5121
5122 BUG_ON(val != final);
13d83a67
JB		 5123}
5124
dde86e2d
PZ		 5125/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5126static void lpt_init_pch_refclk(struct drm_device *dev)
5127{
5128 struct drm_i915_private *dev_priv = dev->dev_private;
5129 struct drm_mode_config *mode_config = &dev->mode_config;
5130 struct intel_encoder *encoder;
5131 bool has_vga = false;
5132 bool is_sdv = false;
5133 u32 tmp;
5134
5135 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5136 switch (encoder->type) {
5137 case INTEL_OUTPUT_ANALOG:
5138 has_vga = true;
5139 break;
5140 }
5141 }
5142
5143 if (!has_vga)
5144 return;
5145
c00db246
DV		 5146 mutex_lock(&dev_priv->dpio_lock);
5147
dde86e2d
PZ		 5148 /* XXX: Rip out SDV support once Haswell ships for real. */
5149 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5150 is_sdv = true;
5151
5152 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5153 tmp &= ~SBI_SSCCTL_DISABLE;
5154 tmp |= SBI_SSCCTL_PATHALT;
5155 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5156
5157 udelay(24);
5158
5159 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5160 tmp &= ~SBI_SSCCTL_PATHALT;
5161 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5162
5163 if (!is_sdv) {
5164 tmp = I915_READ(SOUTH_CHICKEN2);
5165 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5166 I915_WRITE(SOUTH_CHICKEN2, tmp);
5167
5168 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5169 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5170 DRM_ERROR("FDI mPHY reset assert timeout\n");
5171
5172 tmp = I915_READ(SOUTH_CHICKEN2);
5173 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5174 I915_WRITE(SOUTH_CHICKEN2, tmp);
5175
5176 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5177 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5178 100))
5179 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5180 }
5181
5182 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5183 tmp &= ~(0xFF << 24);
5184 tmp |= (0x12 << 24);
5185 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5186
dde86e2d
PZ		 5187 if (is_sdv) {
5188 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5189 tmp |= 0x7FFF;
5190 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5191 }
5192
5193 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5194 tmp |= (1 << 11);
5195 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5196
5197 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5198 tmp |= (1 << 11);
5199 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5200
5201 if (is_sdv) {
5202 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5203 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5204 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5205
5206 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5207 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5208 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5209
5210 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5211 tmp |= (0x3F << 8);
5212 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5213
5214 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5215 tmp |= (0x3F << 8);
5216 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5217 }
5218
5219 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5220 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5221 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5222
5223 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5224 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5225 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5226
5227 if (!is_sdv) {
5228 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5229 tmp &= ~(7 << 13);
5230 tmp |= (5 << 13);
5231 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5232
5233 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5234 tmp &= ~(7 << 13);
5235 tmp |= (5 << 13);
5236 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5237 }
5238
5239 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5240 tmp &= ~0xFF;
5241 tmp |= 0x1C;
5242 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5243
5244 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5245 tmp &= ~0xFF;
5246 tmp |= 0x1C;
5247 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5248
5249 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5250 tmp &= ~(0xFF << 16);
5251 tmp |= (0x1C << 16);
5252 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5253
5254 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5255 tmp &= ~(0xFF << 16);
5256 tmp |= (0x1C << 16);
5257 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5258
5259 if (!is_sdv) {
5260 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5261 tmp |= (1 << 27);
5262 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5263
5264 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5265 tmp |= (1 << 27);
5266 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5267
5268 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5269 tmp &= ~(0xF << 28);
5270 tmp |= (4 << 28);
5271 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5272
5273 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5274 tmp &= ~(0xF << 28);
5275 tmp |= (4 << 28);
5276 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5277 }
5278
5279 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5280 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5281 tmp |= SBI_DBUFF0_ENABLE;
5282 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5283
5284 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5285}
5286
5287/*
5288 * Initialize reference clocks when the driver loads
5289 */
5290void intel_init_pch_refclk(struct drm_device *dev)
5291{
5292 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5293 ironlake_init_pch_refclk(dev);
5294 else if (HAS_PCH_LPT(dev))
5295 lpt_init_pch_refclk(dev);
5296}
5297
d9d444cb
JB		 5298static int ironlake_get_refclk(struct drm_crtc *crtc)
5299{
5300 struct drm_device *dev = crtc->dev;
5301 struct drm_i915_private *dev_priv = dev->dev_private;
5302 struct intel_encoder *encoder;
d9d444cb
JB		 5303 int num_connectors = 0;
5304 bool is_lvds = false;
5305
6c2b7c12 5306 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5307 switch (encoder->type) {
5308 case INTEL_OUTPUT_LVDS:
5309 is_lvds = true;
5310 break;
d9d444cb
JB		 5311 }
5312 num_connectors++;
5313 }
5314
5315 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5316 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5317 dev_priv->vbt.lvds_ssc_freq);
5318 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5319 }
5320
5321 return 120000;
5322}
5323
6ff93609 5324static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5325{
c8203565 5326 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5328 int pipe = intel_crtc->pipe;
c8203565
PZ		 5329 uint32_t val;
5330
5331 val = I915_READ(PIPECONF(pipe));
5332
dfd07d72 5333 val &= ~PIPECONF_BPC_MASK;
965e0c48 5334 switch (intel_crtc->config.pipe_bpp) {
c8203565 5335 case 18:
dfd07d72 5336 val |= PIPECONF_6BPC;
c8203565
PZ		 5337 break;
5338 case 24:
dfd07d72 5339 val |= PIPECONF_8BPC;
c8203565
PZ		 5340 break;
5341 case 30:
dfd07d72 5342 val |= PIPECONF_10BPC;
c8203565
PZ		 5343 break;
5344 case 36:
dfd07d72 5345 val |= PIPECONF_12BPC;
c8203565
PZ		 5346 break;
5347 default:
cc769b62
PZ		 5348 /* Case prevented by intel_choose_pipe_bpp_dither. */
5349 BUG();
c8203565
PZ		 5350 }
5351
5352 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5353 if (intel_crtc->config.dither)
c8203565
PZ		 5354 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5355
5356 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5357 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5358 val |= PIPECONF_INTERLACED_ILK;
5359 else
5360 val |= PIPECONF_PROGRESSIVE;
5361
50f3b016 5362 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5363 val |= PIPECONF_COLOR_RANGE_SELECT;
5364 else
5365 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5366
c8203565
PZ		 5367 I915_WRITE(PIPECONF(pipe), val);
5368 POSTING_READ(PIPECONF(pipe));
5369}
5370
86d3efce
VS		 5371/*
5372 * Set up the pipe CSC unit.
5373 *
5374 * Currently only full range RGB to limited range RGB conversion
5375 * is supported, but eventually this should handle various
5376 * RGB<->YCbCr scenarios as well.
5377 */
50f3b016 5378static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5379{
5380 struct drm_device *dev = crtc->dev;
5381 struct drm_i915_private *dev_priv = dev->dev_private;
5382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5383 int pipe = intel_crtc->pipe;
5384 uint16_t coeff = 0x7800; /* 1.0 */
5385
5386 /*
5387 * TODO: Check what kind of values actually come out of the pipe
5388 * with these coeff/postoff values and adjust to get the best
5389 * accuracy. Perhaps we even need to take the bpc value into
5390 * consideration.
5391 */
5392
50f3b016 5393 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5394 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5395
5396 /*
5397 * GY/GU and RY/RU should be the other way around according
5398 * to BSpec, but reality doesn't agree. Just set them up in
5399 * a way that results in the correct picture.
5400 */
5401 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5402 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5403
5404 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5405 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5406
5407 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5408 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5409
5410 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5411 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5412 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5413
5414 if (INTEL_INFO(dev)->gen > 6) {
5415 uint16_t postoff = 0;
5416
50f3b016 5417 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5418 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5419
5420 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5421 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5422 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5423
5424 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5425 } else {
5426 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5427
50f3b016 5428 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5429 mode |= CSC_BLACK_SCREEN_OFFSET;
5430
5431 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5432 }
5433}
5434
6ff93609 5435static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5436{
5437 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5439 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5440 uint32_t val;
5441
702e7a56 5442 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5443
5444 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5445 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5446 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5447
5448 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5449 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5450 val |= PIPECONF_INTERLACED_ILK;
5451 else
5452 val |= PIPECONF_PROGRESSIVE;
5453
702e7a56
PZ		 5454 I915_WRITE(PIPECONF(cpu_transcoder), val);
5455 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5456}
5457
6591c6e4 5458static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5459 intel_clock_t *clock,
5460 bool *has_reduced_clock,
5461 intel_clock_t *reduced_clock)
5462{
5463 struct drm_device *dev = crtc->dev;
5464 struct drm_i915_private *dev_priv = dev->dev_private;
5465 struct intel_encoder *intel_encoder;
5466 int refclk;
d4906093 5467 const intel_limit_t *limit;
a16af721 5468 bool ret, is_lvds = false;
79e53945 5469
6591c6e4
PZ		 5470 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5471 switch (intel_encoder->type) {
79e53945
JB		 5472 case INTEL_OUTPUT_LVDS:
5473 is_lvds = true;
5474 break;
79e53945
JB		 5475 }
5476 }
5477
d9d444cb 5478 refclk = ironlake_get_refclk(crtc);
79e53945 5479
d4906093
ML		 5480 /*
5481 * Returns a set of divisors for the desired target clock with the given
5482 * refclk, or FALSE. The returned values represent the clock equation:
5483 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5484 */
1b894b59 5485 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5486 ret = dev_priv->display.find_dpll(limit, crtc,
5487 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5488 refclk, NULL, clock);
6591c6e4
PZ		 5489 if (!ret)
5490 return false;
cda4b7d3 5491
ddc9003c 5492 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5493 /*
5494 * Ensure we match the reduced clock's P to the target clock.
5495 * If the clocks don't match, we can't switch the display clock
5496 * by using the FP0/FP1. In such case we will disable the LVDS
5497 * downclock feature.
5498 */
ee9300bb
DV		 5499 *has_reduced_clock =
5500 dev_priv->display.find_dpll(limit, crtc,
5501 dev_priv->lvds_downclock,
5502 refclk, clock,
5503 reduced_clock);
652c393a 5504 }
61e9653f 5505
6591c6e4
PZ		 5506 return true;
5507}
5508
01a415fd
DV		 5509static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5510{
5511 struct drm_i915_private *dev_priv = dev->dev_private;
5512 uint32_t temp;
5513
5514 temp = I915_READ(SOUTH_CHICKEN1);
5515 if (temp & FDI_BC_BIFURCATION_SELECT)
5516 return;
5517
5518 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5519 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5520
5521 temp |= FDI_BC_BIFURCATION_SELECT;
5522 DRM_DEBUG_KMS("enabling fdi C rx\n");
5523 I915_WRITE(SOUTH_CHICKEN1, temp);
5524 POSTING_READ(SOUTH_CHICKEN1);
5525}
5526
ebfd86fd
DV		 5527static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5528{
5529 struct drm_device *dev = intel_crtc->base.dev;
5530 struct drm_i915_private *dev_priv = dev->dev_private;
5531
5532 switch (intel_crtc->pipe) {
5533 case PIPE_A:
5534 break;
5535 case PIPE_B:
5536 if (intel_crtc->config.fdi_lanes > 2)
5537 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5538 else
5539 cpt_enable_fdi_bc_bifurcation(dev);
5540
5541 break;
5542 case PIPE_C:
01a415fd
DV		 5543 cpt_enable_fdi_bc_bifurcation(dev);
5544
ebfd86fd 5545 break;
01a415fd
DV		 5546 default:
5547 BUG();
5548 }
5549}
5550
d4b1931c
PZ		 5551int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5552{
5553 /*
5554 * Account for spread spectrum to avoid
5555 * oversubscribing the link. Max center spread
5556 * is 2.5%; use 5% for safety's sake.
5557 */
5558 u32 bps = target_clock * bpp * 21 / 20;
5559 return bps / (link_bw * 8) + 1;
5560}
5561
7429e9d4
DV		 5562static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5563{
5564 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5565}
5566
de13a2e3 5567static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5568 u32 *fp,
9a7c7890 5569 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5570{
de13a2e3 5571 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5572 struct drm_device *dev = crtc->dev;
5573 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5574 struct intel_encoder *intel_encoder;
5575 uint32_t dpll;
6cc5f341 5576 int factor, num_connectors = 0;
09ede541 5577 bool is_lvds = false, is_sdvo = false;
79e53945 5578
de13a2e3
PZ		 5579 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5580 switch (intel_encoder->type) {
79e53945
JB		 5581 case INTEL_OUTPUT_LVDS:
5582 is_lvds = true;
5583 break;
5584 case INTEL_OUTPUT_SDVO:
7d57382e 5585 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5586 is_sdvo = true;
5587 break;
79e53945 5588 }
43565a06 5589
c751ce4f 5590 num_connectors++;
79e53945 5591 }
79e53945 5592
c1858123 5593 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5594 factor = 21;
5595 if (is_lvds) {
5596 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5597 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5598 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5599 factor = 25;
09ede541 5600 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5601 factor = 20;
c1858123 5602
7429e9d4 5603 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5604 *fp |= FP_CB_TUNE;
2c07245f 5605
9a7c7890
DV		 5606 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5607 *fp2 |= FP_CB_TUNE;
5608
5eddb70b 5609 dpll = 0;
2c07245f 5610
a07d6787
EA		 5611 if (is_lvds)
5612 dpll |= DPLLB_MODE_LVDS;
5613 else
5614 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5615
5616 if (intel_crtc->config.pixel_multiplier > 1) {
5617 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5618 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5619 }
198a037f
DV		 5620
5621 if (is_sdvo)
5622 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5623 if (intel_crtc->config.has_dp_encoder)
a07d6787 5624 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5625
a07d6787 5626 /* compute bitmask from p1 value */
7429e9d4 5627 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5628 /* also FPA1 */
7429e9d4 5629 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5630
7429e9d4 5631 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5632 case 5:
5633 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5634 break;
5635 case 7:
5636 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5637 break;
5638 case 10:
5639 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5640 break;
5641 case 14:
5642 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5643 break;
79e53945
JB		 5644 }
5645
b4c09f3b 5646 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5647 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5648 else
5649 dpll |= PLL_REF_INPUT_DREFCLK;
5650
de13a2e3
PZ		 5651 return dpll;
5652}
5653
5654static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5655 int x, int y,
5656 struct drm_framebuffer *fb)
5657{
5658 struct drm_device *dev = crtc->dev;
5659 struct drm_i915_private *dev_priv = dev->dev_private;
5660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5661 int pipe = intel_crtc->pipe;
5662 int plane = intel_crtc->plane;
5663 int num_connectors = 0;
5664 intel_clock_t clock, reduced_clock;
cbbab5bd 5665 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5666 bool ok, has_reduced_clock = false;
8b47047b 5667 bool is_lvds = false;
de13a2e3 5668 struct intel_encoder *encoder;
de13a2e3 5669 int ret;
de13a2e3
PZ		 5670
5671 for_each_encoder_on_crtc(dev, crtc, encoder) {
5672 switch (encoder->type) {
5673 case INTEL_OUTPUT_LVDS:
5674 is_lvds = true;
5675 break;
de13a2e3
PZ		 5676 }
5677
5678 num_connectors++;
a07d6787 5679 }
79e53945 5680
5dc5298b
PZ		 5681 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5682 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5683
ff9a6750 5684 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5685 &has_reduced_clock, &reduced_clock);
ee9300bb 5686 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5687 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5688 return -EINVAL;
79e53945 5689 }
f47709a9
DV		 5690 /* Compat-code for transition, will disappear. */
5691 if (!intel_crtc->config.clock_set) {
5692 intel_crtc->config.dpll.n = clock.n;
5693 intel_crtc->config.dpll.m1 = clock.m1;
5694 intel_crtc->config.dpll.m2 = clock.m2;
5695 intel_crtc->config.dpll.p1 = clock.p1;
5696 intel_crtc->config.dpll.p2 = clock.p2;
5697 }
79e53945 5698
de13a2e3
PZ		 5699 /* Ensure that the cursor is valid for the new mode before changing... */
5700 intel_crtc_update_cursor(crtc, true);
5701
5dc5298b 5702 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5703 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5704 struct intel_pch_pll *pll;
4b645f14 5705
7429e9d4 5706 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5707 if (has_reduced_clock)
7429e9d4 5708 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5709
7429e9d4 5710 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5711 &fp, &reduced_clock,
5712 has_reduced_clock ? &fp2 : NULL);
5713
ee7b9f93
JB		 5714 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5715 if (pll == NULL) {
84f44ce7
VS		 5716 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5717 pipe_name(pipe));
4b645f14
JB		 5718 return -EINVAL;
5719 }
ee7b9f93
JB		 5720 } else
5721 intel_put_pch_pll(intel_crtc);
79e53945 5722
03afc4a2
DV		 5723 if (intel_crtc->config.has_dp_encoder)
5724 intel_dp_set_m_n(intel_crtc);
79e53945 5725
dafd226c
DV		 5726 for_each_encoder_on_crtc(dev, crtc, encoder)
5727 if (encoder->pre_pll_enable)
5728 encoder->pre_pll_enable(encoder);
79e53945 5729
ee7b9f93
JB		 5730 if (intel_crtc->pch_pll) {
5731 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5732
32f9d658 5733 /* Wait for the clocks to stabilize. */
ee7b9f93 5734 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5735 udelay(150);
5736
8febb297
EA		 5737 /* The pixel multiplier can only be updated once the
5738 * DPLL is enabled and the clocks are stable.
5739 *
5740 * So write it again.
5741 */
ee7b9f93 5742 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5743 }
79e53945 5744
5eddb70b 5745 intel_crtc->lowfreq_avail = false;
ee7b9f93 5746 if (intel_crtc->pch_pll) {
4b645f14 5747 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5748 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5749 intel_crtc->lowfreq_avail = true;
4b645f14 5750 } else {
ee7b9f93 5751 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5752 }
5753 }
5754
8a654f3b 5755 intel_set_pipe_timings(intel_crtc);
5eddb70b 5756
ca3a0ff8 5757 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5758 intel_cpu_transcoder_set_m_n(intel_crtc,
5759 &intel_crtc->config.fdi_m_n);
5760 }
2c07245f 5761
ebfd86fd
DV		 5762 if (IS_IVYBRIDGE(dev))
5763 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5764
6ff93609 5765 ironlake_set_pipeconf(crtc);
79e53945 5766
a1f9e77e
PZ		 5767 /* Set up the display plane register */
5768 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5769 POSTING_READ(DSPCNTR(plane));
79e53945 5770
94352cf9 5771 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5772
5773 intel_update_watermarks(dev);
5774
1857e1da 5775 return ret;
79e53945
JB		 5776}
5777
72419203
DV		 5778static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5779 struct intel_crtc_config *pipe_config)
5780{
5781 struct drm_device *dev = crtc->base.dev;
5782 struct drm_i915_private *dev_priv = dev->dev_private;
5783 enum transcoder transcoder = pipe_config->cpu_transcoder;
5784
5785 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5786 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5787 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5788 & ~TU_SIZE_MASK;
5789 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5790 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5791 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5792}
5793
2fa2fe9a
DV		 5794static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5795 struct intel_crtc_config *pipe_config)
5796{
5797 struct drm_device *dev = crtc->base.dev;
5798 struct drm_i915_private *dev_priv = dev->dev_private;
5799 uint32_t tmp;
5800
5801 tmp = I915_READ(PF_CTL(crtc->pipe));
5802
5803 if (tmp & PF_ENABLE) {
5804 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5805 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5806
5807 /* We currently do not free assignements of panel fitters on
5808 * ivb/hsw (since we don't use the higher upscaling modes which
5809 * differentiates them) so just WARN about this case for now. */
5810 if (IS_GEN7(dev)) {
5811 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5812 PF_PIPE_SEL_IVB(crtc->pipe));
5813 }
2fa2fe9a
DV		 5814 }
5815}
5816
0e8ffe1b
DV		 5817static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5818 struct intel_crtc_config *pipe_config)
5819{
5820 struct drm_device *dev = crtc->base.dev;
5821 struct drm_i915_private *dev_priv = dev->dev_private;
5822 uint32_t tmp;
5823
eccb140b
DV		 5824 pipe_config->cpu_transcoder = crtc->pipe;
5825
0e8ffe1b
DV		 5826 tmp = I915_READ(PIPECONF(crtc->pipe));
5827 if (!(tmp & PIPECONF_ENABLE))
5828 return false;
5829
ab9412ba 5830 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5831 pipe_config->has_pch_encoder = true;
5832
627eb5a3
DV		 5833 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5834 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5835 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5836
5837 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5838 }
5839
1bd1bd80
DV		 5840 intel_get_pipe_timings(crtc, pipe_config);
5841
2fa2fe9a
DV		 5842 ironlake_get_pfit_config(crtc, pipe_config);
5843
0e8ffe1b
DV		 5844 return true;
5845}
5846
d6dd9eb1
DV		 5847static void haswell_modeset_global_resources(struct drm_device *dev)
5848{
d6dd9eb1
DV		 5849 bool enable = false;
5850 struct intel_crtc *crtc;
d6dd9eb1
DV		 5851
5852 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5853 if (!crtc->base.enabled)
5854 continue;
d6dd9eb1 5855
e7a639c4
DV		 5856 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5857 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5858 enable = true;
5859 }
5860
d6dd9eb1
DV		 5861 intel_set_power_well(dev, enable);
5862}
5863
09b4ddf9 5864static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5865 int x, int y,
5866 struct drm_framebuffer *fb)
5867{
5868 struct drm_device *dev = crtc->dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5871 int plane = intel_crtc->plane;
09b4ddf9 5872 int ret;
09b4ddf9 5873
ff9a6750 5874 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5875 return -EINVAL;
5876
09b4ddf9
PZ		 5877 /* Ensure that the cursor is valid for the new mode before changing... */
5878 intel_crtc_update_cursor(crtc, true);
5879
03afc4a2
DV		 5880 if (intel_crtc->config.has_dp_encoder)
5881 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5882
5883 intel_crtc->lowfreq_avail = false;
09b4ddf9 5884
8a654f3b 5885 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5886
ca3a0ff8 5887 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5888 intel_cpu_transcoder_set_m_n(intel_crtc,
5889 &intel_crtc->config.fdi_m_n);
5890 }
09b4ddf9 5891
6ff93609 5892 haswell_set_pipeconf(crtc);
09b4ddf9 5893
50f3b016 5894 intel_set_pipe_csc(crtc);
86d3efce 5895
09b4ddf9 5896 /* Set up the display plane register */
86d3efce 5897 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5898 POSTING_READ(DSPCNTR(plane));
5899
5900 ret = intel_pipe_set_base(crtc, x, y, fb);
5901
5902 intel_update_watermarks(dev);
5903
1f803ee5 5904 return ret;
79e53945
JB		 5905}
5906
0e8ffe1b
DV		 5907static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5908 struct intel_crtc_config *pipe_config)
5909{
5910 struct drm_device *dev = crtc->base.dev;
5911 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5912 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5913 uint32_t tmp;
5914
eccb140b
DV		 5915 pipe_config->cpu_transcoder = crtc->pipe;
5916 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5917 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5918 enum pipe trans_edp_pipe;
5919 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5920 default:
5921 WARN(1, "unknown pipe linked to edp transcoder\n");
5922 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5923 case TRANS_DDI_EDP_INPUT_A_ON:
5924 trans_edp_pipe = PIPE_A;
5925 break;
5926 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5927 trans_edp_pipe = PIPE_B;
5928 break;
5929 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5930 trans_edp_pipe = PIPE_C;
5931 break;
5932 }
5933
5934 if (trans_edp_pipe == crtc->pipe)
5935 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5936 }
5937
b97186f0 5938 if (!intel_display_power_enabled(dev,
eccb140b 5939 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5940 return false;
5941
eccb140b 5942 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5943 if (!(tmp & PIPECONF_ENABLE))
5944 return false;
5945
88adfff1 5946 /*
f196e6be 5947 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5948 * DDI E. So just check whether this pipe is wired to DDI E and whether
5949 * the PCH transcoder is on.
5950 */
eccb140b 5951 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5952 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5953 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5954 pipe_config->has_pch_encoder = true;
5955
627eb5a3
DV		 5956 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5957 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5958 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5959
5960 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5961 }
5962
1bd1bd80
DV		 5963 intel_get_pipe_timings(crtc, pipe_config);
5964
2fa2fe9a
DV		 5965 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5966 if (intel_display_power_enabled(dev, pfit_domain))
5967 ironlake_get_pfit_config(crtc, pipe_config);
5968
42db64ef
PZ		 5969 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5970 (I915_READ(IPS_CTL) & IPS_ENABLE);
5971
0e8ffe1b
DV		 5972 return true;
5973}
5974
f564048e 5975static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5976 int x, int y,
94352cf9 5977 struct drm_framebuffer *fb)
f564048e
EA		 5978{
5979 struct drm_device *dev = crtc->dev;
5980 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5981 struct drm_encoder_helper_funcs *encoder_funcs;
5982 struct intel_encoder *encoder;
0b701d27 5983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5984 struct drm_display_mode *adjusted_mode =
5985 &intel_crtc->config.adjusted_mode;
5986 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5987 int pipe = intel_crtc->pipe;
f564048e
EA		 5988 int ret;
5989
0b701d27 5990 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5991
b8cecdf5
DV		 5992 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5993
79e53945 5994 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5995
9256aa19
DV		 5996 if (ret != 0)
5997 return ret;
5998
5999 for_each_encoder_on_crtc(dev, crtc, encoder) {
6000 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6001 encoder->base.base.id,
6002 drm_get_encoder_name(&encoder->base),
6003 mode->base.id, mode->name);
6cc5f341
DV		 6004 if (encoder->mode_set) {
6005 encoder->mode_set(encoder);
6006 } else {
6007 encoder_funcs = encoder->base.helper_private;
6008 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6009 }
9256aa19
DV		 6010 }
6011
6012 return 0;
79e53945
JB		 6013}
6014
3a9627f4
WF		 6015static bool intel_eld_uptodate(struct drm_connector *connector,
6016 int reg_eldv, uint32_t bits_eldv,
6017 int reg_elda, uint32_t bits_elda,
6018 int reg_edid)
6019{
6020 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6021 uint8_t *eld = connector->eld;
6022 uint32_t i;
6023
6024 i = I915_READ(reg_eldv);
6025 i &= bits_eldv;
6026
6027 if (!eld[0])
6028 return !i;
6029
6030 if (!i)
6031 return false;
6032
6033 i = I915_READ(reg_elda);
6034 i &= ~bits_elda;
6035 I915_WRITE(reg_elda, i);
6036
6037 for (i = 0; i < eld[2]; i++)
6038 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6039 return false;
6040
6041 return true;
6042}
6043
e0dac65e
WF		 6044static void g4x_write_eld(struct drm_connector *connector,
6045 struct drm_crtc *crtc)
6046{
6047 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6048 uint8_t *eld = connector->eld;
6049 uint32_t eldv;
6050 uint32_t len;
6051 uint32_t i;
6052
6053 i = I915_READ(G4X_AUD_VID_DID);
6054
6055 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6056 eldv = G4X_ELDV_DEVCL_DEVBLC;
6057 else
6058 eldv = G4X_ELDV_DEVCTG;
6059
3a9627f4
WF		 6060 if (intel_eld_uptodate(connector,
6061 G4X_AUD_CNTL_ST, eldv,
6062 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6063 G4X_HDMIW_HDMIEDID))
6064 return;
6065
e0dac65e
WF		 6066 i = I915_READ(G4X_AUD_CNTL_ST);
6067 i &= ~(eldv | G4X_ELD_ADDR);
6068 len = (i >> 9) & 0x1f; /* ELD buffer size */
6069 I915_WRITE(G4X_AUD_CNTL_ST, i);
6070
6071 if (!eld[0])
6072 return;
6073
6074 len = min_t(uint8_t, eld[2], len);
6075 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6076 for (i = 0; i < len; i++)
6077 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6078
6079 i = I915_READ(G4X_AUD_CNTL_ST);
6080 i |= eldv;
6081 I915_WRITE(G4X_AUD_CNTL_ST, i);
6082}
6083
83358c85
WX		 6084static void haswell_write_eld(struct drm_connector *connector,
6085 struct drm_crtc *crtc)
6086{
6087 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6088 uint8_t *eld = connector->eld;
6089 struct drm_device *dev = crtc->dev;
7b9f35a6 6090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6091 uint32_t eldv;
6092 uint32_t i;
6093 int len;
6094 int pipe = to_intel_crtc(crtc)->pipe;
6095 int tmp;
6096
6097 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6098 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6099 int aud_config = HSW_AUD_CFG(pipe);
6100 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6101
6102
6103 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6104
6105 /* Audio output enable */
6106 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6107 tmp = I915_READ(aud_cntrl_st2);
6108 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6109 I915_WRITE(aud_cntrl_st2, tmp);
6110
6111 /* Wait for 1 vertical blank */
6112 intel_wait_for_vblank(dev, pipe);
6113
6114 /* Set ELD valid state */
6115 tmp = I915_READ(aud_cntrl_st2);
6116 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6117 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6118 I915_WRITE(aud_cntrl_st2, tmp);
6119 tmp = I915_READ(aud_cntrl_st2);
6120 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6121
6122 /* Enable HDMI mode */
6123 tmp = I915_READ(aud_config);
6124 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6125 /* clear N_programing_enable and N_value_index */
6126 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6127 I915_WRITE(aud_config, tmp);
6128
6129 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6130
6131 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6132 intel_crtc->eld_vld = true;
83358c85
WX		 6133
6134 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6135 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6136 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6137 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6138 } else
6139 I915_WRITE(aud_config, 0);
6140
6141 if (intel_eld_uptodate(connector,
6142 aud_cntrl_st2, eldv,
6143 aud_cntl_st, IBX_ELD_ADDRESS,
6144 hdmiw_hdmiedid))
6145 return;
6146
6147 i = I915_READ(aud_cntrl_st2);
6148 i &= ~eldv;
6149 I915_WRITE(aud_cntrl_st2, i);
6150
6151 if (!eld[0])
6152 return;
6153
6154 i = I915_READ(aud_cntl_st);
6155 i &= ~IBX_ELD_ADDRESS;
6156 I915_WRITE(aud_cntl_st, i);
6157 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6158 DRM_DEBUG_DRIVER("port num:%d\n", i);
6159
6160 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6161 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6162 for (i = 0; i < len; i++)
6163 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6164
6165 i = I915_READ(aud_cntrl_st2);
6166 i |= eldv;
6167 I915_WRITE(aud_cntrl_st2, i);
6168
6169}
6170
e0dac65e
WF		 6171static void ironlake_write_eld(struct drm_connector *connector,
6172 struct drm_crtc *crtc)
6173{
6174 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6175 uint8_t *eld = connector->eld;
6176 uint32_t eldv;
6177 uint32_t i;
6178 int len;
6179 int hdmiw_hdmiedid;
b6daa025 6180 int aud_config;
e0dac65e
WF		 6181 int aud_cntl_st;
6182 int aud_cntrl_st2;
9b138a83 6183 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6184
b3f33cbf 6185 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6186 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6187 aud_config = IBX_AUD_CFG(pipe);
6188 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6189 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6190 } else {
9b138a83
WX		 6191 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6192 aud_config = CPT_AUD_CFG(pipe);
6193 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6194 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6195 }
6196
9b138a83 6197 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6198
6199 i = I915_READ(aud_cntl_st);
9b138a83 6200 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6201 if (!i) {
6202 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6203 /* operate blindly on all ports */
1202b4c6
WF		 6204 eldv = IBX_ELD_VALIDB;
6205 eldv |= IBX_ELD_VALIDB << 4;
6206 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6207 } else {
2582a850 6208 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6209 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6210 }
6211
3a9627f4
WF		 6212 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6213 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6214 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6215 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6216 } else
6217 I915_WRITE(aud_config, 0);
e0dac65e 6218
3a9627f4
WF		 6219 if (intel_eld_uptodate(connector,
6220 aud_cntrl_st2, eldv,
6221 aud_cntl_st, IBX_ELD_ADDRESS,
6222 hdmiw_hdmiedid))
6223 return;
6224
e0dac65e
WF		 6225 i = I915_READ(aud_cntrl_st2);
6226 i &= ~eldv;
6227 I915_WRITE(aud_cntrl_st2, i);
6228
6229 if (!eld[0])
6230 return;
6231
e0dac65e 6232 i = I915_READ(aud_cntl_st);
1202b4c6 6233 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6234 I915_WRITE(aud_cntl_st, i);
6235
6236 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6237 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6238 for (i = 0; i < len; i++)
6239 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6240
6241 i = I915_READ(aud_cntrl_st2);
6242 i |= eldv;
6243 I915_WRITE(aud_cntrl_st2, i);
6244}
6245
6246void intel_write_eld(struct drm_encoder *encoder,
6247 struct drm_display_mode *mode)
6248{
6249 struct drm_crtc *crtc = encoder->crtc;
6250 struct drm_connector *connector;
6251 struct drm_device *dev = encoder->dev;
6252 struct drm_i915_private *dev_priv = dev->dev_private;
6253
6254 connector = drm_select_eld(encoder, mode);
6255 if (!connector)
6256 return;
6257
6258 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6259 connector->base.id,
6260 drm_get_connector_name(connector),
6261 connector->encoder->base.id,
6262 drm_get_encoder_name(connector->encoder));
6263
6264 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6265
6266 if (dev_priv->display.write_eld)
6267 dev_priv->display.write_eld(connector, crtc);
6268}
6269
79e53945
JB		 6270/** Loads the palette/gamma unit for the CRTC with the prepared values */
6271void intel_crtc_load_lut(struct drm_crtc *crtc)
6272{
6273 struct drm_device *dev = crtc->dev;
6274 struct drm_i915_private *dev_priv = dev->dev_private;
6275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6276 enum pipe pipe = intel_crtc->pipe;
6277 int palreg = PALETTE(pipe);
79e53945 6278 int i;
42db64ef 6279 bool reenable_ips = false;
79e53945
JB		 6280
6281 /* The clocks have to be on to load the palette. */
aed3f09d 6282 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6283 return;
6284
f2b115e6 6285 /* use legacy palette for Ironlake */
bad720ff 6286 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6287 palreg = LGC_PALETTE(pipe);
6288
6289 /* Workaround : Do not read or write the pipe palette/gamma data while
6290 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6291 */
6292 if (intel_crtc->config.ips_enabled &&
6293 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6294 GAMMA_MODE_MODE_SPLIT)) {
6295 hsw_disable_ips(intel_crtc);
6296 reenable_ips = true;
6297 }
2c07245f 6298
79e53945
JB		 6299 for (i = 0; i < 256; i++) {
6300 I915_WRITE(palreg + 4 * i,
6301 (intel_crtc->lut_r[i] << 16) |
6302 (intel_crtc->lut_g[i] << 8) |
6303 intel_crtc->lut_b[i]);
6304 }
42db64ef
PZ		 6305
6306 if (reenable_ips)
6307 hsw_enable_ips(intel_crtc);
79e53945
JB		 6308}
6309
560b85bb
CW		 6310static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6311{
6312 struct drm_device *dev = crtc->dev;
6313 struct drm_i915_private *dev_priv = dev->dev_private;
6314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6315 bool visible = base != 0;
6316 u32 cntl;
6317
6318 if (intel_crtc->cursor_visible == visible)
6319 return;
6320
9db4a9c7 6321 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6322 if (visible) {
6323 /* On these chipsets we can only modify the base whilst
6324 * the cursor is disabled.
6325 */
9db4a9c7 6326 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6327
6328 cntl &= ~(CURSOR_FORMAT_MASK);
6329 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6330 cntl |= CURSOR_ENABLE |
6331 CURSOR_GAMMA_ENABLE |
6332 CURSOR_FORMAT_ARGB;
6333 } else
6334 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6335 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6336
6337 intel_crtc->cursor_visible = visible;
6338}
6339
6340static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6341{
6342 struct drm_device *dev = crtc->dev;
6343 struct drm_i915_private *dev_priv = dev->dev_private;
6344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6345 int pipe = intel_crtc->pipe;
6346 bool visible = base != 0;
6347
6348 if (intel_crtc->cursor_visible != visible) {
548f245b 6349 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6350 if (base) {
6351 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6352 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6353 cntl |= pipe << 28; /* Connect to correct pipe */
6354 } else {
6355 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6356 cntl |= CURSOR_MODE_DISABLE;
6357 }
9db4a9c7 6358 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6359
6360 intel_crtc->cursor_visible = visible;
6361 }
6362 /* and commit changes on next vblank */
9db4a9c7 6363 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6364}
6365
65a21cd6
JB		 6366static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6367{
6368 struct drm_device *dev = crtc->dev;
6369 struct drm_i915_private *dev_priv = dev->dev_private;
6370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6371 int pipe = intel_crtc->pipe;
6372 bool visible = base != 0;
6373
6374 if (intel_crtc->cursor_visible != visible) {
6375 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6376 if (base) {
6377 cntl &= ~CURSOR_MODE;
6378 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6379 } else {
6380 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6381 cntl |= CURSOR_MODE_DISABLE;
6382 }
86d3efce
VS		 6383 if (IS_HASWELL(dev))
6384 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6385 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6386
6387 intel_crtc->cursor_visible = visible;
6388 }
6389 /* and commit changes on next vblank */
6390 I915_WRITE(CURBASE_IVB(pipe), base);
6391}
6392
cda4b7d3 6393/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6394static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6395 bool on)
cda4b7d3
CW		 6396{
6397 struct drm_device *dev = crtc->dev;
6398 struct drm_i915_private *dev_priv = dev->dev_private;
6399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6400 int pipe = intel_crtc->pipe;
6401 int x = intel_crtc->cursor_x;
6402 int y = intel_crtc->cursor_y;
560b85bb 6403 u32 base, pos;
cda4b7d3
CW		 6404 bool visible;
6405
6406 pos = 0;
6407
6b383a7f 6408 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6409 base = intel_crtc->cursor_addr;
6410 if (x > (int) crtc->fb->width)
6411 base = 0;
6412
6413 if (y > (int) crtc->fb->height)
6414 base = 0;
6415 } else
6416 base = 0;
6417
6418 if (x < 0) {
6419 if (x + intel_crtc->cursor_width < 0)
6420 base = 0;
6421
6422 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6423 x = -x;
6424 }
6425 pos |= x << CURSOR_X_SHIFT;
6426
6427 if (y < 0) {
6428 if (y + intel_crtc->cursor_height < 0)
6429 base = 0;
6430
6431 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6432 y = -y;
6433 }
6434 pos |= y << CURSOR_Y_SHIFT;
6435
6436 visible = base != 0;
560b85bb 6437 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6438 return;
6439
0cd83aa9 6440 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6441 I915_WRITE(CURPOS_IVB(pipe), pos);
6442 ivb_update_cursor(crtc, base);
6443 } else {
6444 I915_WRITE(CURPOS(pipe), pos);
6445 if (IS_845G(dev) || IS_I865G(dev))
6446 i845_update_cursor(crtc, base);
6447 else
6448 i9xx_update_cursor(crtc, base);
6449 }
cda4b7d3
CW		 6450}
6451
79e53945 6452static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6453 struct drm_file *file,
79e53945
JB		 6454 uint32_t handle,
6455 uint32_t width, uint32_t height)
6456{
6457 struct drm_device *dev = crtc->dev;
6458 struct drm_i915_private *dev_priv = dev->dev_private;
6459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6460 struct drm_i915_gem_object *obj;
cda4b7d3 6461 uint32_t addr;
3f8bc370 6462 int ret;
79e53945 6463
79e53945
JB		 6464 /* if we want to turn off the cursor ignore width and height */
6465 if (!handle) {
28c97730 6466 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6467 addr = 0;
05394f39 6468 obj = NULL;
5004417d 6469 mutex_lock(&dev->struct_mutex);
3f8bc370 6470 goto finish;
79e53945
JB		 6471 }
6472
6473 /* Currently we only support 64x64 cursors */
6474 if (width != 64 || height != 64) {
6475 DRM_ERROR("we currently only support 64x64 cursors\n");
6476 return -EINVAL;
6477 }
6478
05394f39 6479 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6480 if (&obj->base == NULL)
79e53945
JB		 6481 return -ENOENT;
6482
05394f39 6483 if (obj->base.size < width * height * 4) {
79e53945 6484 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6485 ret = -ENOMEM;
6486 goto fail;
79e53945
JB		 6487 }
6488
71acb5eb 6489 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6490 mutex_lock(&dev->struct_mutex);
b295d1b6 6491 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6492 unsigned alignment;
6493
d9e86c0e
CW		 6494 if (obj->tiling_mode) {
6495 DRM_ERROR("cursor cannot be tiled\n");
6496 ret = -EINVAL;
6497 goto fail_locked;
6498 }
6499
693db184
CW		 6500 /* Note that the w/a also requires 2 PTE of padding following
6501 * the bo. We currently fill all unused PTE with the shadow
6502 * page and so we should always have valid PTE following the
6503 * cursor preventing the VT-d warning.
6504 */
6505 alignment = 0;
6506 if (need_vtd_wa(dev))
6507 alignment = 64*1024;
6508
6509 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6510 if (ret) {
6511 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6512 goto fail_locked;
e7b526bb
CW		 6513 }
6514
d9e86c0e
CW		 6515 ret = i915_gem_object_put_fence(obj);
6516 if (ret) {
2da3b9b9 6517 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6518 goto fail_unpin;
6519 }
6520
05394f39 6521 addr = obj->gtt_offset;
71acb5eb 6522 } else {
6eeefaf3 6523 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6524 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6525 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6526 align);
71acb5eb
DA		 6527 if (ret) {
6528 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6529 goto fail_locked;
71acb5eb 6530 }
05394f39 6531 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6532 }
6533
a6c45cf0 6534 if (IS_GEN2(dev))
14b60391
JB		 6535 I915_WRITE(CURSIZE, (height << 12) | width);
6536
3f8bc370 6537 finish:
3f8bc370 6538 if (intel_crtc->cursor_bo) {
b295d1b6 6539 if (dev_priv->info->cursor_needs_physical) {
05394f39 6540 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6541 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6542 } else
6543 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6544 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6545 }
80824003 6546
7f9872e0 6547 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6548
6549 intel_crtc->cursor_addr = addr;
05394f39 6550 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6551 intel_crtc->cursor_width = width;
6552 intel_crtc->cursor_height = height;
6553
40ccc72b 6554 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6555
79e53945 6556 return 0;
e7b526bb 6557fail_unpin:
05394f39 6558 i915_gem_object_unpin(obj);
7f9872e0 6559fail_locked:
34b8686e 6560 mutex_unlock(&dev->struct_mutex);
bc9025bd 6561fail:
05394f39 6562 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6563 return ret;
79e53945
JB		 6564}
6565
6566static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6567{
79e53945 6568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6569
cda4b7d3
CW		 6570 intel_crtc->cursor_x = x;
6571 intel_crtc->cursor_y = y;
652c393a 6572
40ccc72b 6573 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6574
6575 return 0;
6576}
6577
6578/** Sets the color ramps on behalf of RandR */
6579void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6580 u16 blue, int regno)
6581{
6582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6583
6584 intel_crtc->lut_r[regno] = red >> 8;
6585 intel_crtc->lut_g[regno] = green >> 8;
6586 intel_crtc->lut_b[regno] = blue >> 8;
6587}
6588
b8c00ac5
DA		 6589void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6590 u16 *blue, int regno)
6591{
6592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6593
6594 *red = intel_crtc->lut_r[regno] << 8;
6595 *green = intel_crtc->lut_g[regno] << 8;
6596 *blue = intel_crtc->lut_b[regno] << 8;
6597}
6598
79e53945 6599static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6600 u16 *blue, uint32_t start, uint32_t size)
79e53945 6601{
7203425a 6602 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6604
7203425a 6605 for (i = start; i < end; i++) {
79e53945
JB		 6606 intel_crtc->lut_r[i] = red[i] >> 8;
6607 intel_crtc->lut_g[i] = green[i] >> 8;
6608 intel_crtc->lut_b[i] = blue[i] >> 8;
6609 }
6610
6611 intel_crtc_load_lut(crtc);
6612}
6613
79e53945
JB		 6614/* VESA 640x480x72Hz mode to set on the pipe */
6615static struct drm_display_mode load_detect_mode = {
6616 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6617 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6618};
6619
d2dff872
CW		 6620static struct drm_framebuffer *
6621intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6622 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6623 struct drm_i915_gem_object *obj)
6624{
6625 struct intel_framebuffer *intel_fb;
6626 int ret;
6627
6628 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6629 if (!intel_fb) {
6630 drm_gem_object_unreference_unlocked(&obj->base);
6631 return ERR_PTR(-ENOMEM);
6632 }
6633
6634 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6635 if (ret) {
6636 drm_gem_object_unreference_unlocked(&obj->base);
6637 kfree(intel_fb);
6638 return ERR_PTR(ret);
6639 }
6640
6641 return &intel_fb->base;
6642}
6643
6644static u32
6645intel_framebuffer_pitch_for_width(int width, int bpp)
6646{
6647 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6648 return ALIGN(pitch, 64);
6649}
6650
6651static u32
6652intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6653{
6654 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6655 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6656}
6657
6658static struct drm_framebuffer *
6659intel_framebuffer_create_for_mode(struct drm_device *dev,
6660 struct drm_display_mode *mode,
6661 int depth, int bpp)
6662{
6663 struct drm_i915_gem_object *obj;
0fed39bd 6664 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6665
6666 obj = i915_gem_alloc_object(dev,
6667 intel_framebuffer_size_for_mode(mode, bpp));
6668 if (obj == NULL)
6669 return ERR_PTR(-ENOMEM);
6670
6671 mode_cmd.width = mode->hdisplay;
6672 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6673 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6674 bpp);
5ca0c34a 6675 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6676
6677 return intel_framebuffer_create(dev, &mode_cmd, obj);
6678}
6679
6680static struct drm_framebuffer *
6681mode_fits_in_fbdev(struct drm_device *dev,
6682 struct drm_display_mode *mode)
6683{
6684 struct drm_i915_private *dev_priv = dev->dev_private;
6685 struct drm_i915_gem_object *obj;
6686 struct drm_framebuffer *fb;
6687
6688 if (dev_priv->fbdev == NULL)
6689 return NULL;
6690
6691 obj = dev_priv->fbdev->ifb.obj;
6692 if (obj == NULL)
6693 return NULL;
6694
6695 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6696 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6697 fb->bits_per_pixel))
d2dff872
CW		 6698 return NULL;
6699
01f2c773 6700 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6701 return NULL;
6702
6703 return fb;
6704}
6705
d2434ab7 6706bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6707 struct drm_display_mode *mode,
8261b191 6708 struct intel_load_detect_pipe *old)
79e53945
JB		 6709{
6710 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6711 struct intel_encoder *intel_encoder =
6712 intel_attached_encoder(connector);
79e53945 6713 struct drm_crtc *possible_crtc;
4ef69c7a 6714 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6715 struct drm_crtc *crtc = NULL;
6716 struct drm_device *dev = encoder->dev;
94352cf9 6717 struct drm_framebuffer *fb;
79e53945
JB		 6718 int i = -1;
6719
d2dff872
CW		 6720 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6721 connector->base.id, drm_get_connector_name(connector),
6722 encoder->base.id, drm_get_encoder_name(encoder));
6723
79e53945
JB		 6724 /*
6725 * Algorithm gets a little messy:
7a5e4805 6726 *
79e53945
JB		 6727 * - if the connector already has an assigned crtc, use it (but make
6728 * sure it's on first)
7a5e4805 6729 *
79e53945
JB		 6730 * - try to find the first unused crtc that can drive this connector,
6731 * and use that if we find one
79e53945
JB		 6732 */
6733
6734 /* See if we already have a CRTC for this connector */
6735 if (encoder->crtc) {
6736 crtc = encoder->crtc;
8261b191 6737
7b24056b
DV		 6738 mutex_lock(&crtc->mutex);
6739
24218aac 6740 old->dpms_mode = connector->dpms;
8261b191
CW		 6741 old->load_detect_temp = false;
6742
6743 /* Make sure the crtc and connector are running */
24218aac
DV		 6744 if (connector->dpms != DRM_MODE_DPMS_ON)
6745 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6746
7173188d 6747 return true;
79e53945
JB		 6748 }
6749
6750 /* Find an unused one (if possible) */
6751 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6752 i++;
6753 if (!(encoder->possible_crtcs & (1 << i)))
6754 continue;
6755 if (!possible_crtc->enabled) {
6756 crtc = possible_crtc;
6757 break;
6758 }
79e53945
JB		 6759 }
6760
6761 /*
6762 * If we didn't find an unused CRTC, don't use any.
6763 */
6764 if (!crtc) {
7173188d
CW		 6765 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6766 return false;
79e53945
JB		 6767 }
6768
7b24056b 6769 mutex_lock(&crtc->mutex);
fc303101
DV		 6770 intel_encoder->new_crtc = to_intel_crtc(crtc);
6771 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6772
6773 intel_crtc = to_intel_crtc(crtc);
24218aac 6774 old->dpms_mode = connector->dpms;
8261b191 6775 old->load_detect_temp = true;
d2dff872 6776 old->release_fb = NULL;
79e53945 6777
6492711d
CW		 6778 if (!mode)
6779 mode = &load_detect_mode;
79e53945 6780
d2dff872
CW		 6781 /* We need a framebuffer large enough to accommodate all accesses
6782 * that the plane may generate whilst we perform load detection.
6783 * We can not rely on the fbcon either being present (we get called
6784 * during its initialisation to detect all boot displays, or it may
6785 * not even exist) or that it is large enough to satisfy the
6786 * requested mode.
6787 */
94352cf9
DV		 6788 fb = mode_fits_in_fbdev(dev, mode);
6789 if (fb == NULL) {
d2dff872 6790 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6791 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6792 old->release_fb = fb;
d2dff872
CW		 6793 } else
6794 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6795 if (IS_ERR(fb)) {
d2dff872 6796 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6797 mutex_unlock(&crtc->mutex);
0e8b3d3e 6798 return false;
79e53945 6799 }
79e53945 6800
c0c36b94 6801 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6802 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6803 if (old->release_fb)
6804 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6805 mutex_unlock(&crtc->mutex);
0e8b3d3e 6806 return false;
79e53945 6807 }
7173188d 6808
79e53945 6809 /* let the connector get through one full cycle before testing */
9d0498a2 6810 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6811 return true;
79e53945
JB		 6812}
6813
d2434ab7 6814void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6815 struct intel_load_detect_pipe *old)
79e53945 6816{
d2434ab7
DV		 6817 struct intel_encoder *intel_encoder =
6818 intel_attached_encoder(connector);
4ef69c7a 6819 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6820 struct drm_crtc *crtc = encoder->crtc;
79e53945 6821
d2dff872
CW		 6822 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6823 connector->base.id, drm_get_connector_name(connector),
6824 encoder->base.id, drm_get_encoder_name(encoder));
6825
8261b191 6826 if (old->load_detect_temp) {
fc303101
DV		 6827 to_intel_connector(connector)->new_encoder = NULL;
6828 intel_encoder->new_crtc = NULL;
6829 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6830
36206361
DV		 6831 if (old->release_fb) {
6832 drm_framebuffer_unregister_private(old->release_fb);
6833 drm_framebuffer_unreference(old->release_fb);
6834 }
d2dff872 6835
67c96400 6836 mutex_unlock(&crtc->mutex);
0622a53c 6837 return;
79e53945
JB		 6838 }
6839
c751ce4f 6840 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6841 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6842 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6843
6844 mutex_unlock(&crtc->mutex);
79e53945
JB		 6845}
6846
6847/* Returns the clock of the currently programmed mode of the given pipe. */
6848static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6849{
6850 struct drm_i915_private *dev_priv = dev->dev_private;
6851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6852 int pipe = intel_crtc->pipe;
548f245b 6853 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6854 u32 fp;
6855 intel_clock_t clock;
6856
6857 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6858 fp = I915_READ(FP0(pipe));
79e53945 6859 else
39adb7a5 6860 fp = I915_READ(FP1(pipe));
79e53945
JB		 6861
6862 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6863 if (IS_PINEVIEW(dev)) {
6864 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6865 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6866 } else {
6867 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6868 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6869 }
6870
a6c45cf0 6871 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6872 if (IS_PINEVIEW(dev))
6873 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6874 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6875 else
6876 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6877 DPLL_FPA01_P1_POST_DIV_SHIFT);
6878
6879 switch (dpll & DPLL_MODE_MASK) {
6880 case DPLLB_MODE_DAC_SERIAL:
6881 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6882 5 : 10;
6883 break;
6884 case DPLLB_MODE_LVDS:
6885 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6886 7 : 14;
6887 break;
6888 default:
28c97730 6889 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6890 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6891 return 0;
6892 }
6893
ac58c3f0
DV		 6894 if (IS_PINEVIEW(dev))
6895 pineview_clock(96000, &clock);
6896 else
6897 i9xx_clock(96000, &clock);
79e53945
JB		 6898 } else {
6899 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6900
6901 if (is_lvds) {
6902 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6903 DPLL_FPA01_P1_POST_DIV_SHIFT);
6904 clock.p2 = 14;
6905
6906 if ((dpll & PLL_REF_INPUT_MASK) ==
6907 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6908 /* XXX: might not be 66MHz */
ac58c3f0 6909 i9xx_clock(66000, &clock);
79e53945 6910 } else
ac58c3f0 6911 i9xx_clock(48000, &clock);
79e53945
JB		 6912 } else {
6913 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6914 clock.p1 = 2;
6915 else {
6916 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6917 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6918 }
6919 if (dpll & PLL_P2_DIVIDE_BY_4)
6920 clock.p2 = 4;
6921 else
6922 clock.p2 = 2;
6923
ac58c3f0 6924 i9xx_clock(48000, &clock);
79e53945
JB		 6925 }
6926 }
6927
6928 /* XXX: It would be nice to validate the clocks, but we can't reuse
6929 * i830PllIsValid() because it relies on the xf86_config connector
6930 * configuration being accurate, which it isn't necessarily.
6931 */
6932
6933 return clock.dot;
6934}
6935
6936/** Returns the currently programmed mode of the given pipe. */
6937struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6938 struct drm_crtc *crtc)
6939{
548f245b 6940 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6942 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6943 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6944 int htot = I915_READ(HTOTAL(cpu_transcoder));
6945 int hsync = I915_READ(HSYNC(cpu_transcoder));
6946 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6947 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6948
6949 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6950 if (!mode)
6951 return NULL;
6952
6953 mode->clock = intel_crtc_clock_get(dev, crtc);
6954 mode->hdisplay = (htot & 0xffff) + 1;
6955 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6956 mode->hsync_start = (hsync & 0xffff) + 1;
6957 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6958 mode->vdisplay = (vtot & 0xffff) + 1;
6959 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6960 mode->vsync_start = (vsync & 0xffff) + 1;
6961 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6962
6963 drm_mode_set_name(mode);
79e53945
JB		 6964
6965 return mode;
6966}
6967
3dec0095 6968static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6969{
6970 struct drm_device *dev = crtc->dev;
6971 drm_i915_private_t *dev_priv = dev->dev_private;
6972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6973 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6974 int dpll_reg = DPLL(pipe);
6975 int dpll;
652c393a 6976
bad720ff 6977 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6978 return;
6979
6980 if (!dev_priv->lvds_downclock_avail)
6981 return;
6982
dbdc6479 6983 dpll = I915_READ(dpll_reg);
652c393a 6984 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6985 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6986
8ac5a6d5 6987 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6988
6989 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6990 I915_WRITE(dpll_reg, dpll);
9d0498a2 6991 intel_wait_for_vblank(dev, pipe);
dbdc6479 6992
652c393a
JB		 6993 dpll = I915_READ(dpll_reg);
6994 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6995 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6996 }
652c393a
JB		 6997}
6998
6999static void intel_decrease_pllclock(struct drm_crtc *crtc)
7000{
7001 struct drm_device *dev = crtc->dev;
7002 drm_i915_private_t *dev_priv = dev->dev_private;
7003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7004
bad720ff 7005 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7006 return;
7007
7008 if (!dev_priv->lvds_downclock_avail)
7009 return;
7010
7011 /*
7012 * Since this is called by a timer, we should never get here in
7013 * the manual case.
7014 */
7015 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7016 int pipe = intel_crtc->pipe;
7017 int dpll_reg = DPLL(pipe);
7018 int dpll;
f6e5b160 7019
44d98a61 7020 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7021
8ac5a6d5 7022 assert_panel_unlocked(dev_priv, pipe);
652c393a 7023
dc257cf1 7024 dpll = I915_READ(dpll_reg);
652c393a
JB		 7025 dpll |= DISPLAY_RATE_SELECT_FPA1;
7026 I915_WRITE(dpll_reg, dpll);
9d0498a2 7027 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7028 dpll = I915_READ(dpll_reg);
7029 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7030 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7031 }
7032
7033}
7034
f047e395
CW		 7035void intel_mark_busy(struct drm_device *dev)
7036{
f047e395
CW		 7037 i915_update_gfx_val(dev->dev_private);
7038}
7039
7040void intel_mark_idle(struct drm_device *dev)
652c393a 7041{
652c393a 7042 struct drm_crtc *crtc;
652c393a
JB		 7043
7044 if (!i915_powersave)
7045 return;
7046
652c393a 7047 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7048 if (!crtc->fb)
7049 continue;
7050
725a5b54 7051 intel_decrease_pllclock(crtc);
652c393a 7052 }
652c393a
JB		 7053}
7054
725a5b54 7055void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7056{
f047e395
CW		 7057 struct drm_device *dev = obj->base.dev;
7058 struct drm_crtc *crtc;
652c393a 7059
f047e395 7060 if (!i915_powersave)
acb87dfb
CW		 7061 return;
7062
652c393a
JB		 7063 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7064 if (!crtc->fb)
7065 continue;
7066
f047e395 7067 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7068 intel_increase_pllclock(crtc);
652c393a
JB		 7069 }
7070}
7071
79e53945
JB		 7072static void intel_crtc_destroy(struct drm_crtc *crtc)
7073{
7074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7075 struct drm_device *dev = crtc->dev;
7076 struct intel_unpin_work *work;
7077 unsigned long flags;
7078
7079 spin_lock_irqsave(&dev->event_lock, flags);
7080 work = intel_crtc->unpin_work;
7081 intel_crtc->unpin_work = NULL;
7082 spin_unlock_irqrestore(&dev->event_lock, flags);
7083
7084 if (work) {
7085 cancel_work_sync(&work->work);
7086 kfree(work);
7087 }
79e53945 7088
40ccc72b
MK		 7089 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7090
79e53945 7091 drm_crtc_cleanup(crtc);
67e77c5a 7092
79e53945
JB		 7093 kfree(intel_crtc);
7094}
7095
6b95a207
KH		 7096static void intel_unpin_work_fn(struct work_struct *__work)
7097{
7098 struct intel_unpin_work *work =
7099 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7100 struct drm_device *dev = work->crtc->dev;
6b95a207 7101
b4a98e57 7102 mutex_lock(&dev->struct_mutex);
1690e1eb 7103 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7104 drm_gem_object_unreference(&work->pending_flip_obj->base);
7105 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7106
b4a98e57
CW		 7107 intel_update_fbc(dev);
7108 mutex_unlock(&dev->struct_mutex);
7109
7110 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7111 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7112
6b95a207
KH		 7113 kfree(work);
7114}
7115
1afe3e9d 7116static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7117 struct drm_crtc *crtc)
6b95a207
KH		 7118{
7119 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7121 struct intel_unpin_work *work;
6b95a207
KH		 7122 unsigned long flags;
7123
7124 /* Ignore early vblank irqs */
7125 if (intel_crtc == NULL)
7126 return;
7127
7128 spin_lock_irqsave(&dev->event_lock, flags);
7129 work = intel_crtc->unpin_work;
e7d841ca
CW		 7130
7131 /* Ensure we don't miss a work->pending update ... */
7132 smp_rmb();
7133
7134 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7135 spin_unlock_irqrestore(&dev->event_lock, flags);
7136 return;
7137 }
7138
e7d841ca
CW		 7139 /* and that the unpin work is consistent wrt ->pending. */
7140 smp_rmb();
7141
6b95a207 7142 intel_crtc->unpin_work = NULL;
6b95a207 7143
45a066eb
RC		 7144 if (work->event)
7145 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7146
0af7e4df
MK		 7147 drm_vblank_put(dev, intel_crtc->pipe);
7148
6b95a207
KH		 7149 spin_unlock_irqrestore(&dev->event_lock, flags);
7150
2c10d571 7151 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7152
7153 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7154
7155 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7156}
7157
1afe3e9d
JB		 7158void intel_finish_page_flip(struct drm_device *dev, int pipe)
7159{
7160 drm_i915_private_t *dev_priv = dev->dev_private;
7161 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7162
49b14a5c 7163 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7164}
7165
7166void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7167{
7168 drm_i915_private_t *dev_priv = dev->dev_private;
7169 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7170
49b14a5c 7171 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7172}
7173
6b95a207
KH		 7174void intel_prepare_page_flip(struct drm_device *dev, int plane)
7175{
7176 drm_i915_private_t *dev_priv = dev->dev_private;
7177 struct intel_crtc *intel_crtc =
7178 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7179 unsigned long flags;
7180
e7d841ca
CW		 7181 /* NB: An MMIO update of the plane base pointer will also
7182 * generate a page-flip completion irq, i.e. every modeset
7183 * is also accompanied by a spurious intel_prepare_page_flip().
7184 */
6b95a207 7185 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7186 if (intel_crtc->unpin_work)
7187 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7188 spin_unlock_irqrestore(&dev->event_lock, flags);
7189}
7190
e7d841ca
CW		 7191inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7192{
7193 /* Ensure that the work item is consistent when activating it ... */
7194 smp_wmb();
7195 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7196 /* and that it is marked active as soon as the irq could fire. */
7197 smp_wmb();
7198}
7199
8c9f3aaf
JB		 7200static int intel_gen2_queue_flip(struct drm_device *dev,
7201 struct drm_crtc *crtc,
7202 struct drm_framebuffer *fb,
7203 struct drm_i915_gem_object *obj)
7204{
7205 struct drm_i915_private *dev_priv = dev->dev_private;
7206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7207 u32 flip_mask;
6d90c952 7208 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7209 int ret;
7210
6d90c952 7211 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7212 if (ret)
83d4092b 7213 goto err;
8c9f3aaf 7214
6d90c952 7215 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7216 if (ret)
83d4092b 7217 goto err_unpin;
8c9f3aaf
JB		 7218
7219 /* Can't queue multiple flips, so wait for the previous
7220 * one to finish before executing the next.
7221 */
7222 if (intel_crtc->plane)
7223 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7224 else
7225 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7226 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7227 intel_ring_emit(ring, MI_NOOP);
7228 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7229 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7230 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7231 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7232 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7233
7234 intel_mark_page_flip_active(intel_crtc);
6d90c952 7235 intel_ring_advance(ring);
83d4092b
CW		 7236 return 0;
7237
7238err_unpin:
7239 intel_unpin_fb_obj(obj);
7240err:
8c9f3aaf
JB		 7241 return ret;
7242}
7243
7244static int intel_gen3_queue_flip(struct drm_device *dev,
7245 struct drm_crtc *crtc,
7246 struct drm_framebuffer *fb,
7247 struct drm_i915_gem_object *obj)
7248{
7249 struct drm_i915_private *dev_priv = dev->dev_private;
7250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7251 u32 flip_mask;
6d90c952 7252 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7253 int ret;
7254
6d90c952 7255 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7256 if (ret)
83d4092b 7257 goto err;
8c9f3aaf 7258
6d90c952 7259 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7260 if (ret)
83d4092b 7261 goto err_unpin;
8c9f3aaf
JB		 7262
7263 if (intel_crtc->plane)
7264 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7265 else
7266 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7267 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7268 intel_ring_emit(ring, MI_NOOP);
7269 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7270 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7271 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7272 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7273 intel_ring_emit(ring, MI_NOOP);
7274
e7d841ca 7275 intel_mark_page_flip_active(intel_crtc);
6d90c952 7276 intel_ring_advance(ring);
83d4092b
CW		 7277 return 0;
7278
7279err_unpin:
7280 intel_unpin_fb_obj(obj);
7281err:
8c9f3aaf
JB		 7282 return ret;
7283}
7284
7285static int intel_gen4_queue_flip(struct drm_device *dev,
7286 struct drm_crtc *crtc,
7287 struct drm_framebuffer *fb,
7288 struct drm_i915_gem_object *obj)
7289{
7290 struct drm_i915_private *dev_priv = dev->dev_private;
7291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7292 uint32_t pf, pipesrc;
6d90c952 7293 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7294 int ret;
7295
6d90c952 7296 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7297 if (ret)
83d4092b 7298 goto err;
8c9f3aaf 7299
6d90c952 7300 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7301 if (ret)
83d4092b 7302 goto err_unpin;
8c9f3aaf
JB		 7303
7304 /* i965+ uses the linear or tiled offsets from the
7305 * Display Registers (which do not change across a page-flip)
7306 * so we need only reprogram the base address.
7307 */
6d90c952
DV		 7308 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7309 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7310 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7311 intel_ring_emit(ring,
7312 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7313 obj->tiling_mode);
8c9f3aaf
JB		 7314
7315 /* XXX Enabling the panel-fitter across page-flip is so far
7316 * untested on non-native modes, so ignore it for now.
7317 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7318 */
7319 pf = 0;
7320 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7321 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7322
7323 intel_mark_page_flip_active(intel_crtc);
6d90c952 7324 intel_ring_advance(ring);
83d4092b
CW		 7325 return 0;
7326
7327err_unpin:
7328 intel_unpin_fb_obj(obj);
7329err:
8c9f3aaf
JB		 7330 return ret;
7331}
7332
7333static int intel_gen6_queue_flip(struct drm_device *dev,
7334 struct drm_crtc *crtc,
7335 struct drm_framebuffer *fb,
7336 struct drm_i915_gem_object *obj)
7337{
7338 struct drm_i915_private *dev_priv = dev->dev_private;
7339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7340 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7341 uint32_t pf, pipesrc;
7342 int ret;
7343
6d90c952 7344 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7345 if (ret)
83d4092b 7346 goto err;
8c9f3aaf 7347
6d90c952 7348 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7349 if (ret)
83d4092b 7350 goto err_unpin;
8c9f3aaf 7351
6d90c952
DV		 7352 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7353 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7354 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7355 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7356
dc257cf1
DV		 7357 /* Contrary to the suggestions in the documentation,
7358 * "Enable Panel Fitter" does not seem to be required when page
7359 * flipping with a non-native mode, and worse causes a normal
7360 * modeset to fail.
7361 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7362 */
7363 pf = 0;
8c9f3aaf 7364 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7365 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7366
7367 intel_mark_page_flip_active(intel_crtc);
6d90c952 7368 intel_ring_advance(ring);
83d4092b
CW		 7369 return 0;
7370
7371err_unpin:
7372 intel_unpin_fb_obj(obj);
7373err:
8c9f3aaf
JB		 7374 return ret;
7375}
7376
7c9017e5
JB		 7377/*
7378 * On gen7 we currently use the blit ring because (in early silicon at least)
7379 * the render ring doesn't give us interrpts for page flip completion, which
7380 * means clients will hang after the first flip is queued. Fortunately the
7381 * blit ring generates interrupts properly, so use it instead.
7382 */
7383static int intel_gen7_queue_flip(struct drm_device *dev,
7384 struct drm_crtc *crtc,
7385 struct drm_framebuffer *fb,
7386 struct drm_i915_gem_object *obj)
7387{
7388 struct drm_i915_private *dev_priv = dev->dev_private;
7389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7390 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7391 uint32_t plane_bit = 0;
7c9017e5
JB		 7392 int ret;
7393
7394 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7395 if (ret)
83d4092b 7396 goto err;
7c9017e5 7397
cb05d8de
DV		 7398 switch(intel_crtc->plane) {
7399 case PLANE_A:
7400 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7401 break;
7402 case PLANE_B:
7403 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7404 break;
7405 case PLANE_C:
7406 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7407 break;
7408 default:
7409 WARN_ONCE(1, "unknown plane in flip command\n");
7410 ret = -ENODEV;
ab3951eb 7411 goto err_unpin;
cb05d8de
DV		 7412 }
7413
7c9017e5
JB		 7414 ret = intel_ring_begin(ring, 4);
7415 if (ret)
83d4092b 7416 goto err_unpin;
7c9017e5 7417
cb05d8de 7418 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7419 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7420 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7421 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7422
7423 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7424 intel_ring_advance(ring);
83d4092b
CW		 7425 return 0;
7426
7427err_unpin:
7428 intel_unpin_fb_obj(obj);
7429err:
7c9017e5
JB		 7430 return ret;
7431}
7432
8c9f3aaf
JB		 7433static int intel_default_queue_flip(struct drm_device *dev,
7434 struct drm_crtc *crtc,
7435 struct drm_framebuffer *fb,
7436 struct drm_i915_gem_object *obj)
7437{
7438 return -ENODEV;
7439}
7440
6b95a207
KH		 7441static int intel_crtc_page_flip(struct drm_crtc *crtc,
7442 struct drm_framebuffer *fb,
7443 struct drm_pending_vblank_event *event)
7444{
7445 struct drm_device *dev = crtc->dev;
7446 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7447 struct drm_framebuffer *old_fb = crtc->fb;
7448 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7450 struct intel_unpin_work *work;
8c9f3aaf 7451 unsigned long flags;
52e68630 7452 int ret;
6b95a207 7453
e6a595d2
VS		 7454 /* Can't change pixel format via MI display flips. */
7455 if (fb->pixel_format != crtc->fb->pixel_format)
7456 return -EINVAL;
7457
7458 /*
7459 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7460 * Note that pitch changes could also affect these register.
7461 */
7462 if (INTEL_INFO(dev)->gen > 3 &&
7463 (fb->offsets[0] != crtc->fb->offsets[0] ||
7464 fb->pitches[0] != crtc->fb->pitches[0]))
7465 return -EINVAL;
7466
6b95a207
KH		 7467 work = kzalloc(sizeof *work, GFP_KERNEL);
7468 if (work == NULL)
7469 return -ENOMEM;
7470
6b95a207 7471 work->event = event;
b4a98e57 7472 work->crtc = crtc;
4a35f83b 7473 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7474 INIT_WORK(&work->work, intel_unpin_work_fn);
7475
7317c75e
JB		 7476 ret = drm_vblank_get(dev, intel_crtc->pipe);
7477 if (ret)
7478 goto free_work;
7479
6b95a207
KH		 7480 /* We borrow the event spin lock for protecting unpin_work */
7481 spin_lock_irqsave(&dev->event_lock, flags);
7482 if (intel_crtc->unpin_work) {
7483 spin_unlock_irqrestore(&dev->event_lock, flags);
7484 kfree(work);
7317c75e 7485 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7486
7487 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7488 return -EBUSY;
7489 }
7490 intel_crtc->unpin_work = work;
7491 spin_unlock_irqrestore(&dev->event_lock, flags);
7492
b4a98e57
CW		 7493 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7494 flush_workqueue(dev_priv->wq);
7495
79158103
CW		 7496 ret = i915_mutex_lock_interruptible(dev);
7497 if (ret)
7498 goto cleanup;
6b95a207 7499
75dfca80 7500 /* Reference the objects for the scheduled work. */
05394f39
CW		 7501 drm_gem_object_reference(&work->old_fb_obj->base);
7502 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7503
7504 crtc->fb = fb;
96b099fd 7505
e1f99ce6 7506 work->pending_flip_obj = obj;
e1f99ce6 7507
4e5359cd
SF		 7508 work->enable_stall_check = true;
7509
b4a98e57 7510 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7511 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7512
8c9f3aaf
JB		 7513 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7514 if (ret)
7515 goto cleanup_pending;
6b95a207 7516
7782de3b 7517 intel_disable_fbc(dev);
f047e395 7518 intel_mark_fb_busy(obj);
6b95a207
KH		 7519 mutex_unlock(&dev->struct_mutex);
7520
e5510fac
JB		 7521 trace_i915_flip_request(intel_crtc->plane, obj);
7522
6b95a207 7523 return 0;
96b099fd 7524
8c9f3aaf 7525cleanup_pending:
b4a98e57 7526 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7527 crtc->fb = old_fb;
05394f39
CW		 7528 drm_gem_object_unreference(&work->old_fb_obj->base);
7529 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7530 mutex_unlock(&dev->struct_mutex);
7531
79158103 7532cleanup:
96b099fd
CW		 7533 spin_lock_irqsave(&dev->event_lock, flags);
7534 intel_crtc->unpin_work = NULL;
7535 spin_unlock_irqrestore(&dev->event_lock, flags);
7536
7317c75e
JB		 7537 drm_vblank_put(dev, intel_crtc->pipe);
7538free_work:
96b099fd
CW		 7539 kfree(work);
7540
7541 return ret;
6b95a207
KH		 7542}
7543
f6e5b160 7544static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7545 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7546 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7547};
7548
50f56119
DV		 7549static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7550 struct drm_crtc *crtc)
7551{
7552 struct drm_device *dev;
7553 struct drm_crtc *tmp;
7554 int crtc_mask = 1;
47f1c6c9 7555
50f56119 7556 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7557
50f56119 7558 dev = crtc->dev;
47f1c6c9 7559
50f56119
DV		 7560 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7561 if (tmp == crtc)
7562 break;
7563 crtc_mask <<= 1;
7564 }
47f1c6c9 7565
50f56119
DV		 7566 if (encoder->possible_crtcs & crtc_mask)
7567 return true;
7568 return false;
47f1c6c9 7569}
79e53945 7570
9a935856
DV		 7571/**
7572 * intel_modeset_update_staged_output_state
7573 *
7574 * Updates the staged output configuration state, e.g. after we've read out the
7575 * current hw state.
7576 */
7577static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7578{
9a935856
DV		 7579 struct intel_encoder *encoder;
7580 struct intel_connector *connector;
f6e5b160 7581
9a935856
DV		 7582 list_for_each_entry(connector, &dev->mode_config.connector_list,
7583 base.head) {
7584 connector->new_encoder =
7585 to_intel_encoder(connector->base.encoder);
7586 }
f6e5b160 7587
9a935856
DV		 7588 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7589 base.head) {
7590 encoder->new_crtc =
7591 to_intel_crtc(encoder->base.crtc);
7592 }
f6e5b160
CW		 7593}
7594
9a935856
DV		 7595/**
7596 * intel_modeset_commit_output_state
7597 *
7598 * This function copies the stage display pipe configuration to the real one.
7599 */
7600static void intel_modeset_commit_output_state(struct drm_device *dev)
7601{
7602 struct intel_encoder *encoder;
7603 struct intel_connector *connector;
f6e5b160 7604
9a935856
DV		 7605 list_for_each_entry(connector, &dev->mode_config.connector_list,
7606 base.head) {
7607 connector->base.encoder = &connector->new_encoder->base;
7608 }
f6e5b160 7609
9a935856
DV		 7610 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7611 base.head) {
7612 encoder->base.crtc = &encoder->new_crtc->base;
7613 }
7614}
7615
050f7aeb
DV		 7616static void
7617connected_sink_compute_bpp(struct intel_connector * connector,
7618 struct intel_crtc_config *pipe_config)
7619{
7620 int bpp = pipe_config->pipe_bpp;
7621
7622 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7623 connector->base.base.id,
7624 drm_get_connector_name(&connector->base));
7625
7626 /* Don't use an invalid EDID bpc value */
7627 if (connector->base.display_info.bpc &&
7628 connector->base.display_info.bpc * 3 < bpp) {
7629 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7630 bpp, connector->base.display_info.bpc*3);
7631 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7632 }
7633
7634 /* Clamp bpp to 8 on screens without EDID 1.4 */
7635 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7636 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7637 bpp);
7638 pipe_config->pipe_bpp = 24;
7639 }
7640}
7641
4e53c2e0 7642static int
050f7aeb
DV		 7643compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7644 struct drm_framebuffer *fb,
7645 struct intel_crtc_config *pipe_config)
4e53c2e0 7646{
050f7aeb
DV		 7647 struct drm_device *dev = crtc->base.dev;
7648 struct intel_connector *connector;
4e53c2e0
DV		 7649 int bpp;
7650
d42264b1
DV		 7651 switch (fb->pixel_format) {
7652 case DRM_FORMAT_C8:
4e53c2e0
DV		 7653 bpp = 8*3; /* since we go through a colormap */
7654 break;
d42264b1
DV		 7655 case DRM_FORMAT_XRGB1555:
7656 case DRM_FORMAT_ARGB1555:
7657 /* checked in intel_framebuffer_init already */
7658 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7659 return -EINVAL;
7660 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7661 bpp = 6*3; /* min is 18bpp */
7662 break;
d42264b1
DV		 7663 case DRM_FORMAT_XBGR8888:
7664 case DRM_FORMAT_ABGR8888:
7665 /* checked in intel_framebuffer_init already */
7666 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7667 return -EINVAL;
7668 case DRM_FORMAT_XRGB8888:
7669 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7670 bpp = 8*3;
7671 break;
d42264b1
DV		 7672 case DRM_FORMAT_XRGB2101010:
7673 case DRM_FORMAT_ARGB2101010:
7674 case DRM_FORMAT_XBGR2101010:
7675 case DRM_FORMAT_ABGR2101010:
7676 /* checked in intel_framebuffer_init already */
7677 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7678 return -EINVAL;
4e53c2e0
DV		 7679 bpp = 10*3;
7680 break;
baba133a 7681 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7682 default:
7683 DRM_DEBUG_KMS("unsupported depth\n");
7684 return -EINVAL;
7685 }
7686
4e53c2e0
DV		 7687 pipe_config->pipe_bpp = bpp;
7688
7689 /* Clamp display bpp to EDID value */
7690 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7691 base.head) {
1b829e05
DV		 7692 if (!connector->new_encoder ||
7693 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7694 continue;
7695
050f7aeb 7696 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7697 }
7698
7699 return bpp;
7700}
7701
c0b03411
DV		 7702static void intel_dump_pipe_config(struct intel_crtc *crtc,
7703 struct intel_crtc_config *pipe_config,
7704 const char *context)
7705{
7706 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7707 context, pipe_name(crtc->pipe));
7708
7709 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7710 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7711 pipe_config->pipe_bpp, pipe_config->dither);
7712 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7713 pipe_config->has_pch_encoder,
7714 pipe_config->fdi_lanes,
7715 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7716 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7717 pipe_config->fdi_m_n.tu);
7718 DRM_DEBUG_KMS("requested mode:\n");
7719 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7720 DRM_DEBUG_KMS("adjusted mode:\n");
7721 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7722 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7723 pipe_config->gmch_pfit.control,
7724 pipe_config->gmch_pfit.pgm_ratios,
7725 pipe_config->gmch_pfit.lvds_border_bits);
7726 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7727 pipe_config->pch_pfit.pos,
7728 pipe_config->pch_pfit.size);
42db64ef 7729 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7730}
7731
accfc0c5
DV		 7732static bool check_encoder_cloning(struct drm_crtc *crtc)
7733{
7734 int num_encoders = 0;
7735 bool uncloneable_encoders = false;
7736 struct intel_encoder *encoder;
7737
7738 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7739 base.head) {
7740 if (&encoder->new_crtc->base != crtc)
7741 continue;
7742
7743 num_encoders++;
7744 if (!encoder->cloneable)
7745 uncloneable_encoders = true;
7746 }
7747
7748 return !(num_encoders > 1 && uncloneable_encoders);
7749}
7750
b8cecdf5
DV		 7751static struct intel_crtc_config *
7752intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7753 struct drm_framebuffer *fb,
b8cecdf5 7754 struct drm_display_mode *mode)
ee7b9f93 7755{
7758a113 7756 struct drm_device *dev = crtc->dev;
7758a113
DV		 7757 struct drm_encoder_helper_funcs *encoder_funcs;
7758 struct intel_encoder *encoder;
b8cecdf5 7759 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7760 int plane_bpp, ret = -EINVAL;
7761 bool retry = true;
ee7b9f93 7762
accfc0c5
DV		 7763 if (!check_encoder_cloning(crtc)) {
7764 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7765 return ERR_PTR(-EINVAL);
7766 }
7767
b8cecdf5
DV		 7768 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7769 if (!pipe_config)
7758a113
DV		 7770 return ERR_PTR(-ENOMEM);
7771
b8cecdf5
DV		 7772 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7773 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7774 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
b8cecdf5 7775
050f7aeb
DV		 7776 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7777 * plane pixel format and any sink constraints into account. Returns the
7778 * source plane bpp so that dithering can be selected on mismatches
7779 * after encoders and crtc also have had their say. */
7780 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7781 fb, pipe_config);
4e53c2e0
DV		 7782 if (plane_bpp < 0)
7783 goto fail;
7784
e29c22c0 7785encoder_retry:
ff9a6750
DV		 7786 /* Ensure the port clock default is reset when retrying. */
7787 pipe_config->port_clock = 0;
7788
7758a113
DV		 7789 /* Pass our mode to the connectors and the CRTC to give them a chance to
7790 * adjust it according to limitations or connector properties, and also
7791 * a chance to reject the mode entirely.
47f1c6c9 7792 */
7758a113
DV		 7793 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7794 base.head) {
47f1c6c9 7795
7758a113
DV		 7796 if (&encoder->new_crtc->base != crtc)
7797 continue;
7ae89233
DV		 7798
7799 if (encoder->compute_config) {
7800 if (!(encoder->compute_config(encoder, pipe_config))) {
7801 DRM_DEBUG_KMS("Encoder config failure\n");
7802 goto fail;
7803 }
7804
7805 continue;
7806 }
7807
7758a113 7808 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7809 if (!(encoder_funcs->mode_fixup(&encoder->base,
7810 &pipe_config->requested_mode,
7811 &pipe_config->adjusted_mode))) {
7758a113
DV		 7812 DRM_DEBUG_KMS("Encoder fixup failed\n");
7813 goto fail;
7814 }
ee7b9f93 7815 }
47f1c6c9 7816
ff9a6750
DV		 7817 /* Set default port clock if not overwritten by the encoder. Needs to be
7818 * done afterwards in case the encoder adjusts the mode. */
7819 if (!pipe_config->port_clock)
7820 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7821
e29c22c0
DV		 7822 ret = intel_crtc_compute_config(crtc, pipe_config);
7823 if (ret < 0) {
7758a113
DV		 7824 DRM_DEBUG_KMS("CRTC fixup failed\n");
7825 goto fail;
ee7b9f93 7826 }
e29c22c0
DV		 7827
7828 if (ret == RETRY) {
7829 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7830 ret = -EINVAL;
7831 goto fail;
7832 }
7833
7834 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7835 retry = false;
7836 goto encoder_retry;
7837 }
7838
4e53c2e0
DV		 7839 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7840 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7841 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7842
b8cecdf5 7843 return pipe_config;
7758a113 7844fail:
b8cecdf5 7845 kfree(pipe_config);
e29c22c0 7846 return ERR_PTR(ret);
ee7b9f93 7847}
47f1c6c9 7848
e2e1ed41
DV		 7849/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7850 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7851static void
7852intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7853 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7854{
7855 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7856 struct drm_device *dev = crtc->dev;
7857 struct intel_encoder *encoder;
7858 struct intel_connector *connector;
7859 struct drm_crtc *tmp_crtc;
79e53945 7860
e2e1ed41 7861 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7862
e2e1ed41
DV		 7863 /* Check which crtcs have changed outputs connected to them, these need
7864 * to be part of the prepare_pipes mask. We don't (yet) support global
7865 * modeset across multiple crtcs, so modeset_pipes will only have one
7866 * bit set at most. */
7867 list_for_each_entry(connector, &dev->mode_config.connector_list,
7868 base.head) {
7869 if (connector->base.encoder == &connector->new_encoder->base)
7870 continue;
79e53945 7871
e2e1ed41
DV		 7872 if (connector->base.encoder) {
7873 tmp_crtc = connector->base.encoder->crtc;
7874
7875 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7876 }
7877
7878 if (connector->new_encoder)
7879 *prepare_pipes |=
7880 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7881 }
7882
e2e1ed41
DV		 7883 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7884 base.head) {
7885 if (encoder->base.crtc == &encoder->new_crtc->base)
7886 continue;
7887
7888 if (encoder->base.crtc) {
7889 tmp_crtc = encoder->base.crtc;
7890
7891 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7892 }
7893
7894 if (encoder->new_crtc)
7895 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7896 }
7897
e2e1ed41
DV		 7898 /* Check for any pipes that will be fully disabled ... */
7899 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7900 base.head) {
7901 bool used = false;
22fd0fab 7902
e2e1ed41
DV		 7903 /* Don't try to disable disabled crtcs. */
7904 if (!intel_crtc->base.enabled)
7905 continue;
7e7d76c3 7906
e2e1ed41
DV		 7907 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7908 base.head) {
7909 if (encoder->new_crtc == intel_crtc)
7910 used = true;
7911 }
7912
7913 if (!used)
7914 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7915 }
7916
e2e1ed41
DV		 7917
7918 /* set_mode is also used to update properties on life display pipes. */
7919 intel_crtc = to_intel_crtc(crtc);
7920 if (crtc->enabled)
7921 *prepare_pipes |= 1 << intel_crtc->pipe;
7922
b6c5164d
DV		 7923 /*
7924 * For simplicity do a full modeset on any pipe where the output routing
7925 * changed. We could be more clever, but that would require us to be
7926 * more careful with calling the relevant encoder->mode_set functions.
7927 */
e2e1ed41
DV		 7928 if (*prepare_pipes)
7929 *modeset_pipes = *prepare_pipes;
7930
7931 /* ... and mask these out. */
7932 *modeset_pipes &= ~(*disable_pipes);
7933 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7934
7935 /*
7936 * HACK: We don't (yet) fully support global modesets. intel_set_config
7937 * obies this rule, but the modeset restore mode of
7938 * intel_modeset_setup_hw_state does not.
7939 */
7940 *modeset_pipes &= 1 << intel_crtc->pipe;
7941 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7942
7943 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7944 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7945}
79e53945 7946
ea9d758d 7947static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7948{
ea9d758d 7949 struct drm_encoder *encoder;
f6e5b160 7950 struct drm_device *dev = crtc->dev;
f6e5b160 7951
ea9d758d
DV		 7952 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7953 if (encoder->crtc == crtc)
7954 return true;
7955
7956 return false;
7957}
7958
7959static void
7960intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7961{
7962 struct intel_encoder *intel_encoder;
7963 struct intel_crtc *intel_crtc;
7964 struct drm_connector *connector;
7965
7966 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7967 base.head) {
7968 if (!intel_encoder->base.crtc)
7969 continue;
7970
7971 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7972
7973 if (prepare_pipes & (1 << intel_crtc->pipe))
7974 intel_encoder->connectors_active = false;
7975 }
7976
7977 intel_modeset_commit_output_state(dev);
7978
7979 /* Update computed state. */
7980 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7981 base.head) {
7982 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7983 }
7984
7985 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7986 if (!connector->encoder || !connector->encoder->crtc)
7987 continue;
7988
7989 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7990
7991 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7992 struct drm_property *dpms_property =
7993 dev->mode_config.dpms_property;
7994
ea9d758d 7995 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7996 drm_object_property_set_value(&connector->base,
68d34720
DV		 7997 dpms_property,
7998 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7999
8000 intel_encoder = to_intel_encoder(connector->encoder);
8001 intel_encoder->connectors_active = true;
8002 }
8003 }
8004
8005}
8006
25c5b266
DV		 8007#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8008 list_for_each_entry((intel_crtc), \
8009 &(dev)->mode_config.crtc_list, \
8010 base.head) \
0973f18f 8011 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8012
0e8ffe1b 8013static bool
2fa2fe9a
DV		 8014intel_pipe_config_compare(struct drm_device *dev,
8015 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8016 struct intel_crtc_config *pipe_config)
8017{
08a24034
DV		 8018#define PIPE_CONF_CHECK_I(name) \
8019 if (current_config->name != pipe_config->name) { \
8020 DRM_ERROR("mismatch in " #name " " \
8021 "(expected %i, found %i)\n", \
8022 current_config->name, \
8023 pipe_config->name); \
8024 return false; \
88adfff1
DV		 8025 }
8026
1bd1bd80
DV		 8027#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8028 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8029 DRM_ERROR("mismatch in " #name " " \
8030 "(expected %i, found %i)\n", \
8031 current_config->name & (mask), \
8032 pipe_config->name & (mask)); \
8033 return false; \
8034 }
8035
eccb140b
DV		 8036 PIPE_CONF_CHECK_I(cpu_transcoder);
8037
08a24034
DV		 8038 PIPE_CONF_CHECK_I(has_pch_encoder);
8039 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8040 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8041 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8042 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8043 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8044 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8045
1bd1bd80
DV		 8046 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8047 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8048 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8049 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8050 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8051 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8052
8053 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8054 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8055 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8056 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8057 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8058 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8059
8060 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8061 DRM_MODE_FLAG_INTERLACE);
8062
045ac3b5
JB		 8063 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8064 DRM_MODE_FLAG_PHSYNC);
8065 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8066 DRM_MODE_FLAG_NHSYNC);
8067 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8068 DRM_MODE_FLAG_PVSYNC);
8069 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8070 DRM_MODE_FLAG_NVSYNC);
8071
1bd1bd80
DV		 8072 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8073 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8074
2fa2fe9a
DV		 8075 PIPE_CONF_CHECK_I(gmch_pfit.control);
8076 /* pfit ratios are autocomputed by the hw on gen4+ */
8077 if (INTEL_INFO(dev)->gen < 4)
8078 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8079 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8080 PIPE_CONF_CHECK_I(pch_pfit.pos);
8081 PIPE_CONF_CHECK_I(pch_pfit.size);
8082
42db64ef
PZ		 8083 PIPE_CONF_CHECK_I(ips_enabled);
8084
08a24034 8085#undef PIPE_CONF_CHECK_I
1bd1bd80 8086#undef PIPE_CONF_CHECK_FLAGS
627eb5a3 8087
0e8ffe1b
DV		 8088 return true;
8089}
8090
b980514c 8091void
8af6cf88
DV		 8092intel_modeset_check_state(struct drm_device *dev)
8093{
0e8ffe1b 8094 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8095 struct intel_crtc *crtc;
8096 struct intel_encoder *encoder;
8097 struct intel_connector *connector;
0e8ffe1b 8098 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8099
8100 list_for_each_entry(connector, &dev->mode_config.connector_list,
8101 base.head) {
8102 /* This also checks the encoder/connector hw state with the
8103 * ->get_hw_state callbacks. */
8104 intel_connector_check_state(connector);
8105
8106 WARN(&connector->new_encoder->base != connector->base.encoder,
8107 "connector's staged encoder doesn't match current encoder\n");
8108 }
8109
8110 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8111 base.head) {
8112 bool enabled = false;
8113 bool active = false;
8114 enum pipe pipe, tracked_pipe;
8115
8116 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8117 encoder->base.base.id,
8118 drm_get_encoder_name(&encoder->base));
8119
8120 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8121 "encoder's stage crtc doesn't match current crtc\n");
8122 WARN(encoder->connectors_active && !encoder->base.crtc,
8123 "encoder's active_connectors set, but no crtc\n");
8124
8125 list_for_each_entry(connector, &dev->mode_config.connector_list,
8126 base.head) {
8127 if (connector->base.encoder != &encoder->base)
8128 continue;
8129 enabled = true;
8130 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8131 active = true;
8132 }
8133 WARN(!!encoder->base.crtc != enabled,
8134 "encoder's enabled state mismatch "
8135 "(expected %i, found %i)\n",
8136 !!encoder->base.crtc, enabled);
8137 WARN(active && !encoder->base.crtc,
8138 "active encoder with no crtc\n");
8139
8140 WARN(encoder->connectors_active != active,
8141 "encoder's computed active state doesn't match tracked active state "
8142 "(expected %i, found %i)\n", active, encoder->connectors_active);
8143
8144 active = encoder->get_hw_state(encoder, &pipe);
8145 WARN(active != encoder->connectors_active,
8146 "encoder's hw state doesn't match sw tracking "
8147 "(expected %i, found %i)\n",
8148 encoder->connectors_active, active);
8149
8150 if (!encoder->base.crtc)
8151 continue;
8152
8153 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8154 WARN(active && pipe != tracked_pipe,
8155 "active encoder's pipe doesn't match"
8156 "(expected %i, found %i)\n",
8157 tracked_pipe, pipe);
8158
8159 }
8160
8161 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8162 base.head) {
8163 bool enabled = false;
8164 bool active = false;
8165
045ac3b5
JB		 8166 memset(&pipe_config, 0, sizeof(pipe_config));
8167
8af6cf88
DV		 8168 DRM_DEBUG_KMS("[CRTC:%d]\n",
8169 crtc->base.base.id);
8170
8171 WARN(crtc->active && !crtc->base.enabled,
8172 "active crtc, but not enabled in sw tracking\n");
8173
8174 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8175 base.head) {
8176 if (encoder->base.crtc != &crtc->base)
8177 continue;
8178 enabled = true;
8179 if (encoder->connectors_active)
8180 active = true;
045ac3b5
JB		 8181 if (encoder->get_config)
8182 encoder->get_config(encoder, &pipe_config);
8af6cf88
DV		 8183 }
8184 WARN(active != crtc->active,
8185 "crtc's computed active state doesn't match tracked active state "
8186 "(expected %i, found %i)\n", active, crtc->active);
8187 WARN(enabled != crtc->base.enabled,
8188 "crtc's computed enabled state doesn't match tracked enabled state "
8189 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8190
0e8ffe1b
DV		 8191 active = dev_priv->display.get_pipe_config(crtc,
8192 &pipe_config);
8193 WARN(crtc->active != active,
8194 "crtc active state doesn't match with hw state "
8195 "(expected %i, found %i)\n", crtc->active, active);
8196
c0b03411
DV		 8197 if (active &&
8198 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8199 WARN(1, "pipe state doesn't match!\n");
8200 intel_dump_pipe_config(crtc, &pipe_config,
8201 "[hw state]");
8202 intel_dump_pipe_config(crtc, &crtc->config,
8203 "[sw state]");
8204 }
8af6cf88
DV		 8205 }
8206}
8207
f30da187
DV		 8208static int __intel_set_mode(struct drm_crtc *crtc,
8209 struct drm_display_mode *mode,
8210 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8211{
8212 struct drm_device *dev = crtc->dev;
dbf2b54e 8213 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8214 struct drm_display_mode *saved_mode, *saved_hwmode;
8215 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8216 struct intel_crtc *intel_crtc;
8217 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8218 int ret = 0;
a6778b3c 8219
3ac18232 8220 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8221 if (!saved_mode)
8222 return -ENOMEM;
3ac18232 8223 saved_hwmode = saved_mode + 1;
a6778b3c 8224
e2e1ed41 8225 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8226 &prepare_pipes, &disable_pipes);
8227
3ac18232
TG		 8228 *saved_hwmode = crtc->hwmode;
8229 *saved_mode = crtc->mode;
a6778b3c 8230
25c5b266
DV		 8231 /* Hack: Because we don't (yet) support global modeset on multiple
8232 * crtcs, we don't keep track of the new mode for more than one crtc.
8233 * Hence simply check whether any bit is set in modeset_pipes in all the
8234 * pieces of code that are not yet converted to deal with mutliple crtcs
8235 * changing their mode at the same time. */
25c5b266 8236 if (modeset_pipes) {
4e53c2e0 8237 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8238 if (IS_ERR(pipe_config)) {
8239 ret = PTR_ERR(pipe_config);
8240 pipe_config = NULL;
8241
3ac18232 8242 goto out;
25c5b266 8243 }
c0b03411
DV		 8244 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8245 "[modeset]");
25c5b266 8246 }
a6778b3c 8247
460da916
DV		 8248 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8249 intel_crtc_disable(&intel_crtc->base);
8250
ea9d758d
DV		 8251 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8252 if (intel_crtc->base.enabled)
8253 dev_priv->display.crtc_disable(&intel_crtc->base);
8254 }
a6778b3c 8255
6c4c86f5
DV		 8256 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8257 * to set it here already despite that we pass it down the callchain.
f6e5b160 8258 */
b8cecdf5 8259 if (modeset_pipes) {
25c5b266 8260 crtc->mode = *mode;
b8cecdf5
DV		 8261 /* mode_set/enable/disable functions rely on a correct pipe
8262 * config. */
8263 to_intel_crtc(crtc)->config = *pipe_config;
8264 }
7758a113 8265
ea9d758d
DV		 8266 /* Only after disabling all output pipelines that will be changed can we
8267 * update the the output configuration. */
8268 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8269
47fab737
DV		 8270 if (dev_priv->display.modeset_global_resources)
8271 dev_priv->display.modeset_global_resources(dev);
8272
a6778b3c
DV		 8273 /* Set up the DPLL and any encoders state that needs to adjust or depend
8274 * on the DPLL.
f6e5b160 8275 */
25c5b266 8276 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8277 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8278 x, y, fb);
8279 if (ret)
8280 goto done;
a6778b3c
DV		 8281 }
8282
8283 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8284 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8285 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8286
25c5b266
DV		 8287 if (modeset_pipes) {
8288 /* Store real post-adjustment hardware mode. */
b8cecdf5 8289 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8290
25c5b266
DV		 8291 /* Calculate and store various constants which
8292 * are later needed by vblank and swap-completion
8293 * timestamping. They are derived from true hwmode.
8294 */
8295 drm_calc_timestamping_constants(crtc);
8296 }
a6778b3c
DV		 8297
8298 /* FIXME: add subpixel order */
8299done:
c0c36b94 8300 if (ret && crtc->enabled) {
3ac18232
TG		 8301 crtc->hwmode = *saved_hwmode;
8302 crtc->mode = *saved_mode;
a6778b3c
DV		 8303 }
8304
3ac18232 8305out:
b8cecdf5 8306 kfree(pipe_config);
3ac18232 8307 kfree(saved_mode);
a6778b3c 8308 return ret;
f6e5b160
CW		 8309}
8310
f30da187
DV		 8311int intel_set_mode(struct drm_crtc *crtc,
8312 struct drm_display_mode *mode,
8313 int x, int y, struct drm_framebuffer *fb)
8314{
8315 int ret;
8316
8317 ret = __intel_set_mode(crtc, mode, x, y, fb);
8318
8319 if (ret == 0)
8320 intel_modeset_check_state(crtc->dev);
8321
8322 return ret;
8323}
8324
c0c36b94
CW		 8325void intel_crtc_restore_mode(struct drm_crtc *crtc)
8326{
8327 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8328}
8329
25c5b266
DV		 8330#undef for_each_intel_crtc_masked
8331
d9e55608
DV		 8332static void intel_set_config_free(struct intel_set_config *config)
8333{
8334 if (!config)
8335 return;
8336
1aa4b628
DV		 8337 kfree(config->save_connector_encoders);
8338 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8339 kfree(config);
8340}
8341
85f9eb71
DV		 8342static int intel_set_config_save_state(struct drm_device *dev,
8343 struct intel_set_config *config)
8344{
85f9eb71
DV		 8345 struct drm_encoder *encoder;
8346 struct drm_connector *connector;
8347 int count;
8348
1aa4b628
DV		 8349 config->save_encoder_crtcs =
8350 kcalloc(dev->mode_config.num_encoder,
8351 sizeof(struct drm_crtc *), GFP_KERNEL);
8352 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8353 return -ENOMEM;
8354
1aa4b628
DV		 8355 config->save_connector_encoders =
8356 kcalloc(dev->mode_config.num_connector,
8357 sizeof(struct drm_encoder *), GFP_KERNEL);
8358 if (!config->save_connector_encoders)
85f9eb71
DV		 8359 return -ENOMEM;
8360
8361 /* Copy data. Note that driver private data is not affected.
8362 * Should anything bad happen only the expected state is
8363 * restored, not the drivers personal bookkeeping.
8364 */
85f9eb71
DV		 8365 count = 0;
8366 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8367 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8368 }
8369
8370 count = 0;
8371 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8372 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8373 }
8374
8375 return 0;
8376}
8377
8378static void intel_set_config_restore_state(struct drm_device *dev,
8379 struct intel_set_config *config)
8380{
9a935856
DV		 8381 struct intel_encoder *encoder;
8382 struct intel_connector *connector;
85f9eb71
DV		 8383 int count;
8384
85f9eb71 8385 count = 0;
9a935856
DV		 8386 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8387 encoder->new_crtc =
8388 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8389 }
8390
8391 count = 0;
9a935856
DV		 8392 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8393 connector->new_encoder =
8394 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8395 }
8396}
8397
5e2b584e
DV		 8398static void
8399intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8400 struct intel_set_config *config)
8401{
8402
8403 /* We should be able to check here if the fb has the same properties
8404 * and then just flip_or_move it */
8405 if (set->crtc->fb != set->fb) {
8406 /* If we have no fb then treat it as a full mode set */
8407 if (set->crtc->fb == NULL) {
8408 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8409 config->mode_changed = true;
8410 } else if (set->fb == NULL) {
8411 config->mode_changed = true;
72f4901e
DV		 8412 } else if (set->fb->pixel_format !=
8413 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8414 config->mode_changed = true;
8415 } else
8416 config->fb_changed = true;
8417 }
8418
835c5873 8419 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8420 config->fb_changed = true;
8421
8422 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8423 DRM_DEBUG_KMS("modes are different, full mode set\n");
8424 drm_mode_debug_printmodeline(&set->crtc->mode);
8425 drm_mode_debug_printmodeline(set->mode);
8426 config->mode_changed = true;
8427 }
8428}
8429
2e431051 8430static int
9a935856
DV		 8431intel_modeset_stage_output_state(struct drm_device *dev,
8432 struct drm_mode_set *set,
8433 struct intel_set_config *config)
50f56119 8434{
85f9eb71 8435 struct drm_crtc *new_crtc;
9a935856
DV		 8436 struct intel_connector *connector;
8437 struct intel_encoder *encoder;
2e431051 8438 int count, ro;
50f56119 8439
9abdda74 8440 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8441 * of connectors. For paranoia, double-check this. */
8442 WARN_ON(!set->fb && (set->num_connectors != 0));
8443 WARN_ON(set->fb && (set->num_connectors == 0));
8444
50f56119 8445 count = 0;
9a935856
DV		 8446 list_for_each_entry(connector, &dev->mode_config.connector_list,
8447 base.head) {
8448 /* Otherwise traverse passed in connector list and get encoders
8449 * for them. */
50f56119 8450 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8451 if (set->connectors[ro] == &connector->base) {
8452 connector->new_encoder = connector->encoder;
50f56119
DV		 8453 break;
8454 }
8455 }
8456
9a935856
DV		 8457 /* If we disable the crtc, disable all its connectors. Also, if
8458 * the connector is on the changing crtc but not on the new
8459 * connector list, disable it. */
8460 if ((!set->fb || ro == set->num_connectors) &&
8461 connector->base.encoder &&
8462 connector->base.encoder->crtc == set->crtc) {
8463 connector->new_encoder = NULL;
8464
8465 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8466 connector->base.base.id,
8467 drm_get_connector_name(&connector->base));
8468 }
8469
8470
8471 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8472 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8473 config->mode_changed = true;
50f56119
DV		 8474 }
8475 }
9a935856 8476 /* connector->new_encoder is now updated for all connectors. */
50f56119 8477
9a935856 8478 /* Update crtc of enabled connectors. */
50f56119 8479 count = 0;
9a935856
DV		 8480 list_for_each_entry(connector, &dev->mode_config.connector_list,
8481 base.head) {
8482 if (!connector->new_encoder)
50f56119
DV		 8483 continue;
8484
9a935856 8485 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8486
8487 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8488 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8489 new_crtc = set->crtc;
8490 }
8491
8492 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8493 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8494 new_crtc)) {
5e2b584e 8495 return -EINVAL;
50f56119 8496 }
9a935856
DV		 8497 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8498
8499 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8500 connector->base.base.id,
8501 drm_get_connector_name(&connector->base),
8502 new_crtc->base.id);
8503 }
8504
8505 /* Check for any encoders that needs to be disabled. */
8506 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8507 base.head) {
8508 list_for_each_entry(connector,
8509 &dev->mode_config.connector_list,
8510 base.head) {
8511 if (connector->new_encoder == encoder) {
8512 WARN_ON(!connector->new_encoder->new_crtc);
8513
8514 goto next_encoder;
8515 }
8516 }
8517 encoder->new_crtc = NULL;
8518next_encoder:
8519 /* Only now check for crtc changes so we don't miss encoders
8520 * that will be disabled. */
8521 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8522 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8523 config->mode_changed = true;
50f56119
DV		 8524 }
8525 }
9a935856 8526 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8527
2e431051
DV		 8528 return 0;
8529}
8530
8531static int intel_crtc_set_config(struct drm_mode_set *set)
8532{
8533 struct drm_device *dev;
2e431051
DV		 8534 struct drm_mode_set save_set;
8535 struct intel_set_config *config;
8536 int ret;
2e431051 8537
8d3e375e
DV		 8538 BUG_ON(!set);
8539 BUG_ON(!set->crtc);
8540 BUG_ON(!set->crtc->helper_private);
2e431051 8541
7e53f3a4
DV		 8542 /* Enforce sane interface api - has been abused by the fb helper. */
8543 BUG_ON(!set->mode && set->fb);
8544 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8545
2e431051
DV		 8546 if (set->fb) {
8547 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8548 set->crtc->base.id, set->fb->base.id,
8549 (int)set->num_connectors, set->x, set->y);
8550 } else {
8551 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8552 }
8553
8554 dev = set->crtc->dev;
8555
8556 ret = -ENOMEM;
8557 config = kzalloc(sizeof(*config), GFP_KERNEL);
8558 if (!config)
8559 goto out_config;
8560
8561 ret = intel_set_config_save_state(dev, config);
8562 if (ret)
8563 goto out_config;
8564
8565 save_set.crtc = set->crtc;
8566 save_set.mode = &set->crtc->mode;
8567 save_set.x = set->crtc->x;
8568 save_set.y = set->crtc->y;
8569 save_set.fb = set->crtc->fb;
8570
8571 /* Compute whether we need a full modeset, only an fb base update or no
8572 * change at all. In the future we might also check whether only the
8573 * mode changed, e.g. for LVDS where we only change the panel fitter in
8574 * such cases. */
8575 intel_set_config_compute_mode_changes(set, config);
8576
9a935856 8577 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8578 if (ret)
8579 goto fail;
8580
5e2b584e 8581 if (config->mode_changed) {
c0c36b94
CW		 8582 ret = intel_set_mode(set->crtc, set->mode,
8583 set->x, set->y, set->fb);
8584 if (ret) {
8585 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8586 set->crtc->base.id, ret);
87f1faa6
DV		 8587 goto fail;
8588 }
5e2b584e 8589 } else if (config->fb_changed) {
4878cae2
VS		 8590 intel_crtc_wait_for_pending_flips(set->crtc);
8591
4f660f49 8592 ret = intel_pipe_set_base(set->crtc,
94352cf9 8593 set->x, set->y, set->fb);
50f56119
DV		 8594 }
8595
d9e55608
DV		 8596 intel_set_config_free(config);
8597
50f56119
DV		 8598 return 0;
8599
8600fail:
85f9eb71 8601 intel_set_config_restore_state(dev, config);
50f56119
DV		 8602
8603 /* Try to restore the config */
5e2b584e 8604 if (config->mode_changed &&
c0c36b94
CW		 8605 intel_set_mode(save_set.crtc, save_set.mode,
8606 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8607 DRM_ERROR("failed to restore config after modeset failure\n");
8608
d9e55608
DV		 8609out_config:
8610 intel_set_config_free(config);
50f56119
DV		 8611 return ret;
8612}
f6e5b160
CW		 8613
8614static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8615 .cursor_set = intel_crtc_cursor_set,
8616 .cursor_move = intel_crtc_cursor_move,
8617 .gamma_set = intel_crtc_gamma_set,
50f56119 8618 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8619 .destroy = intel_crtc_destroy,
8620 .page_flip = intel_crtc_page_flip,
8621};
8622
79f689aa
PZ		 8623static void intel_cpu_pll_init(struct drm_device *dev)
8624{
affa9354 8625 if (HAS_DDI(dev))
79f689aa
PZ		 8626 intel_ddi_pll_init(dev);
8627}
8628
ee7b9f93
JB		 8629static void intel_pch_pll_init(struct drm_device *dev)
8630{
8631 drm_i915_private_t *dev_priv = dev->dev_private;
8632 int i;
8633
8634 if (dev_priv->num_pch_pll == 0) {
8635 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8636 return;
8637 }
8638
8639 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8640 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8641 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8642 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8643 }
8644}
8645
b358d0a6 8646static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8647{
22fd0fab 8648 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8649 struct intel_crtc *intel_crtc;
8650 int i;
8651
8652 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8653 if (intel_crtc == NULL)
8654 return;
8655
8656 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8657
8658 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8659 for (i = 0; i < 256; i++) {
8660 intel_crtc->lut_r[i] = i;
8661 intel_crtc->lut_g[i] = i;
8662 intel_crtc->lut_b[i] = i;
8663 }
8664
80824003
JB		 8665 /* Swap pipes & planes for FBC on pre-965 */
8666 intel_crtc->pipe = pipe;
8667 intel_crtc->plane = pipe;
e2e767ab 8668 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8669 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8670 intel_crtc->plane = !pipe;
80824003
JB		 8671 }
8672
22fd0fab
JB		 8673 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8674 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8675 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8676 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8677
79e53945 8678 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8679}
8680
08d7b3d1 8681int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8682 struct drm_file *file)
08d7b3d1 8683{
08d7b3d1 8684 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8685 struct drm_mode_object *drmmode_obj;
8686 struct intel_crtc *crtc;
08d7b3d1 8687
1cff8f6b
DV		 8688 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8689 return -ENODEV;
08d7b3d1 8690
c05422d5
DV		 8691 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8692 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8693
c05422d5 8694 if (!drmmode_obj) {
08d7b3d1
CW		 8695 DRM_ERROR("no such CRTC id\n");
8696 return -EINVAL;
8697 }
8698
c05422d5
DV		 8699 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8700 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8701
c05422d5 8702 return 0;
08d7b3d1
CW		 8703}
8704
66a9278e 8705static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8706{
66a9278e
DV		 8707 struct drm_device *dev = encoder->base.dev;
8708 struct intel_encoder *source_encoder;
79e53945 8709 int index_mask = 0;
79e53945
JB		 8710 int entry = 0;
8711
66a9278e
DV		 8712 list_for_each_entry(source_encoder,
8713 &dev->mode_config.encoder_list, base.head) {
8714
8715 if (encoder == source_encoder)
79e53945 8716 index_mask |= (1 << entry);
66a9278e
DV		 8717
8718 /* Intel hw has only one MUX where enocoders could be cloned. */
8719 if (encoder->cloneable && source_encoder->cloneable)
8720 index_mask |= (1 << entry);
8721
79e53945
JB		 8722 entry++;
8723 }
4ef69c7a 8724
79e53945
JB		 8725 return index_mask;
8726}
8727
4d302442
CW		 8728static bool has_edp_a(struct drm_device *dev)
8729{
8730 struct drm_i915_private *dev_priv = dev->dev_private;
8731
8732 if (!IS_MOBILE(dev))
8733 return false;
8734
8735 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8736 return false;
8737
8738 if (IS_GEN5(dev) &&
8739 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8740 return false;
8741
8742 return true;
8743}
8744
79e53945
JB		 8745static void intel_setup_outputs(struct drm_device *dev)
8746{
725e30ad 8747 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8748 struct intel_encoder *encoder;
cb0953d7 8749 bool dpd_is_edp = false;
f3cfcba6 8750 bool has_lvds;
79e53945 8751
f3cfcba6 8752 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8753 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8754 /* disable the panel fitter on everything but LVDS */
8755 I915_WRITE(PFIT_CONTROL, 0);
8756 }
79e53945 8757
c40c0f5b 8758 if (!IS_ULT(dev))
79935fca 8759 intel_crt_init(dev);
cb0953d7 8760
affa9354 8761 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8762 int found;
8763
8764 /* Haswell uses DDI functions to detect digital outputs */
8765 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8766 /* DDI A only supports eDP */
8767 if (found)
8768 intel_ddi_init(dev, PORT_A);
8769
8770 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8771 * register */
8772 found = I915_READ(SFUSE_STRAP);
8773
8774 if (found & SFUSE_STRAP_DDIB_DETECTED)
8775 intel_ddi_init(dev, PORT_B);
8776 if (found & SFUSE_STRAP_DDIC_DETECTED)
8777 intel_ddi_init(dev, PORT_C);
8778 if (found & SFUSE_STRAP_DDID_DETECTED)
8779 intel_ddi_init(dev, PORT_D);
8780 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8781 int found;
270b3042
DV		 8782 dpd_is_edp = intel_dpd_is_edp(dev);
8783
8784 if (has_edp_a(dev))
8785 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8786
dc0fa718 8787 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8788 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8789 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8790 if (!found)
e2debe91 8791 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8792 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8793 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8794 }
8795
dc0fa718 8796 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8797 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8798
dc0fa718 8799 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8800 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8801
5eb08b69 8802 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8803 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8804
270b3042 8805 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8806 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8807 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8808 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8809 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8810 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8811
dc0fa718 8812 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8813 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8814 PORT_B);
67cfc203
VS		 8815 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8816 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8817 }
103a196f 8818 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8819 bool found = false;
7d57382e 8820
e2debe91 8821 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8822 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8823 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8824 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8825 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8826 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8827 }
27185ae1 8828
e7281eab 8829 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8830 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8831 }
13520b05
KH		 8832
8833 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8834
e2debe91 8835 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8836 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8837 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8838 }
27185ae1 8839
e2debe91 8840 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8841
b01f2c3a
JB		 8842 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8843 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8844 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8845 }
e7281eab 8846 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8847 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8848 }
27185ae1 8849
b01f2c3a 8850 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8851 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8852 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8853 } else if (IS_GEN2(dev))
79e53945
JB		 8854 intel_dvo_init(dev);
8855
103a196f 8856 if (SUPPORTS_TV(dev))
79e53945
JB		 8857 intel_tv_init(dev);
8858
4ef69c7a
CW		 8859 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8860 encoder->base.possible_crtcs = encoder->crtc_mask;
8861 encoder->base.possible_clones =
66a9278e 8862 intel_encoder_clones(encoder);
79e53945 8863 }
47356eb6 8864
dde86e2d 8865 intel_init_pch_refclk(dev);
270b3042
DV		 8866
8867 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8868}
8869
8870static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8871{
8872 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8873
8874 drm_framebuffer_cleanup(fb);
05394f39 8875 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8876
8877 kfree(intel_fb);
8878}
8879
8880static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8881 struct drm_file *file,
79e53945
JB		 8882 unsigned int *handle)
8883{
8884 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8885 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8886
05394f39 8887 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8888}
8889
8890static const struct drm_framebuffer_funcs intel_fb_funcs = {
8891 .destroy = intel_user_framebuffer_destroy,
8892 .create_handle = intel_user_framebuffer_create_handle,
8893};
8894
38651674
DA		 8895int intel_framebuffer_init(struct drm_device *dev,
8896 struct intel_framebuffer *intel_fb,
308e5bcb 8897 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8898 struct drm_i915_gem_object *obj)
79e53945 8899{
79e53945
JB		 8900 int ret;
8901
c16ed4be
CW		 8902 if (obj->tiling_mode == I915_TILING_Y) {
8903 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8904 return -EINVAL;
c16ed4be 8905 }
57cd6508 8906
c16ed4be
CW		 8907 if (mode_cmd->pitches[0] & 63) {
8908 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8909 mode_cmd->pitches[0]);
57cd6508 8910 return -EINVAL;
c16ed4be 8911 }
57cd6508 8912
5d7bd705 8913 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8914 if (mode_cmd->pitches[0] > 32768) {
8915 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8916 mode_cmd->pitches[0]);
5d7bd705 8917 return -EINVAL;
c16ed4be 8918 }
5d7bd705
VS		 8919
8920 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8921 mode_cmd->pitches[0] != obj->stride) {
8922 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8923 mode_cmd->pitches[0], obj->stride);
5d7bd705 8924 return -EINVAL;
c16ed4be 8925 }
5d7bd705 8926
57779d06 8927 /* Reject formats not supported by any plane early. */
308e5bcb 8928 switch (mode_cmd->pixel_format) {
57779d06 8929 case DRM_FORMAT_C8:
04b3924d
VS		 8930 case DRM_FORMAT_RGB565:
8931 case DRM_FORMAT_XRGB8888:
8932 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8933 break;
8934 case DRM_FORMAT_XRGB1555:
8935 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8936 if (INTEL_INFO(dev)->gen > 3) {
8937 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8938 return -EINVAL;
c16ed4be 8939 }
57779d06
VS		 8940 break;
8941 case DRM_FORMAT_XBGR8888:
8942 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8943 case DRM_FORMAT_XRGB2101010:
8944 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8945 case DRM_FORMAT_XBGR2101010:
8946 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8947 if (INTEL_INFO(dev)->gen < 4) {
8948 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8949 return -EINVAL;
c16ed4be 8950 }
b5626747 8951 break;
04b3924d
VS		 8952 case DRM_FORMAT_YUYV:
8953 case DRM_FORMAT_UYVY:
8954 case DRM_FORMAT_YVYU:
8955 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8956 if (INTEL_INFO(dev)->gen < 5) {
8957 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8958 return -EINVAL;
c16ed4be 8959 }
57cd6508
CW		 8960 break;
8961 default:
c16ed4be 8962 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8963 return -EINVAL;
8964 }
8965
90f9a336
VS		 8966 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8967 if (mode_cmd->offsets[0] != 0)
8968 return -EINVAL;
8969
c7d73f6a
DV		 8970 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8971 intel_fb->obj = obj;
8972
79e53945
JB		 8973 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8974 if (ret) {
8975 DRM_ERROR("framebuffer init failed %d\n", ret);
8976 return ret;
8977 }
8978
79e53945
JB		 8979 return 0;
8980}
8981
79e53945
JB		 8982static struct drm_framebuffer *
8983intel_user_framebuffer_create(struct drm_device *dev,
8984 struct drm_file *filp,
308e5bcb 8985 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8986{
05394f39 8987 struct drm_i915_gem_object *obj;
79e53945 8988
308e5bcb
JB		 8989 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8990 mode_cmd->handles[0]));
c8725226 8991 if (&obj->base == NULL)
cce13ff7 8992 return ERR_PTR(-ENOENT);
79e53945 8993
d2dff872 8994 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8995}
8996
79e53945 8997static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8998 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8999 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9000};
9001
e70236a8
JB		 9002/* Set up chip specific display functions */
9003static void intel_init_display(struct drm_device *dev)
9004{
9005 struct drm_i915_private *dev_priv = dev->dev_private;
9006
ee9300bb
DV		 9007 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9008 dev_priv->display.find_dpll = g4x_find_best_dpll;
9009 else if (IS_VALLEYVIEW(dev))
9010 dev_priv->display.find_dpll = vlv_find_best_dpll;
9011 else if (IS_PINEVIEW(dev))
9012 dev_priv->display.find_dpll = pnv_find_best_dpll;
9013 else
9014 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9015
affa9354 9016 if (HAS_DDI(dev)) {
0e8ffe1b 9017 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9018 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9019 dev_priv->display.crtc_enable = haswell_crtc_enable;
9020 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9021 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9022 dev_priv->display.update_plane = ironlake_update_plane;
9023 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9024 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9025 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9026 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9027 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9028 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9029 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9030 } else if (IS_VALLEYVIEW(dev)) {
9031 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9032 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9033 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9034 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9035 dev_priv->display.off = i9xx_crtc_off;
9036 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9037 } else {
0e8ffe1b 9038 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9039 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9040 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9041 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9042 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9043 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9044 }
e70236a8 9045
e70236a8 9046 /* Returns the core display clock speed */
25eb05fc
JB		 9047 if (IS_VALLEYVIEW(dev))
9048 dev_priv->display.get_display_clock_speed =
9049 valleyview_get_display_clock_speed;
9050 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9051 dev_priv->display.get_display_clock_speed =
9052 i945_get_display_clock_speed;
9053 else if (IS_I915G(dev))
9054 dev_priv->display.get_display_clock_speed =
9055 i915_get_display_clock_speed;
f2b115e6 9056 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9057 dev_priv->display.get_display_clock_speed =
9058 i9xx_misc_get_display_clock_speed;
9059 else if (IS_I915GM(dev))
9060 dev_priv->display.get_display_clock_speed =
9061 i915gm_get_display_clock_speed;
9062 else if (IS_I865G(dev))
9063 dev_priv->display.get_display_clock_speed =
9064 i865_get_display_clock_speed;
f0f8a9ce 9065 else if (IS_I85X(dev))
e70236a8
JB		 9066 dev_priv->display.get_display_clock_speed =
9067 i855_get_display_clock_speed;
9068 else /* 852, 830 */
9069 dev_priv->display.get_display_clock_speed =
9070 i830_get_display_clock_speed;
9071
7f8a8569 9072 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9073 if (IS_GEN5(dev)) {
674cf967 9074 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9075 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9076 } else if (IS_GEN6(dev)) {
674cf967 9077 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9078 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9079 } else if (IS_IVYBRIDGE(dev)) {
9080 /* FIXME: detect B0+ stepping and use auto training */
9081 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9082 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9083 dev_priv->display.modeset_global_resources =
9084 ivb_modeset_global_resources;
c82e4d26
ED		 9085 } else if (IS_HASWELL(dev)) {
9086 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9087 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9088 dev_priv->display.modeset_global_resources =
9089 haswell_modeset_global_resources;
a0e63c22 9090 }
6067aaea 9091 } else if (IS_G4X(dev)) {
e0dac65e 9092 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9093 }
8c9f3aaf
JB		 9094
9095 /* Default just returns -ENODEV to indicate unsupported */
9096 dev_priv->display.queue_flip = intel_default_queue_flip;
9097
9098 switch (INTEL_INFO(dev)->gen) {
9099 case 2:
9100 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9101 break;
9102
9103 case 3:
9104 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9105 break;
9106
9107 case 4:
9108 case 5:
9109 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9110 break;
9111
9112 case 6:
9113 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9114 break;
7c9017e5
JB		 9115 case 7:
9116 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9117 break;
8c9f3aaf 9118 }
e70236a8
JB		 9119}
9120
b690e96c
JB		 9121/*
9122 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9123 * resume, or other times. This quirk makes sure that's the case for
9124 * affected systems.
9125 */
0206e353 9126static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9127{
9128 struct drm_i915_private *dev_priv = dev->dev_private;
9129
9130 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9131 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9132}
9133
435793df
KP		 9134/*
9135 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9136 */
9137static void quirk_ssc_force_disable(struct drm_device *dev)
9138{
9139 struct drm_i915_private *dev_priv = dev->dev_private;
9140 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9141 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9142}
9143
4dca20ef 9144/*
5a15ab5b
CE		 9145 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9146 * brightness value
4dca20ef
CE		 9147 */
9148static void quirk_invert_brightness(struct drm_device *dev)
9149{
9150 struct drm_i915_private *dev_priv = dev->dev_private;
9151 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9152 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9153}
9154
b690e96c
JB		 9155struct intel_quirk {
9156 int device;
9157 int subsystem_vendor;
9158 int subsystem_device;
9159 void (*hook)(struct drm_device *dev);
9160};
9161
5f85f176
EE		 9162/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9163struct intel_dmi_quirk {
9164 void (*hook)(struct drm_device *dev);
9165 const struct dmi_system_id (*dmi_id_list)[];
9166};
9167
9168static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9169{
9170 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9171 return 1;
9172}
9173
9174static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9175 {
9176 .dmi_id_list = &(const struct dmi_system_id[]) {
9177 {
9178 .callback = intel_dmi_reverse_brightness,
9179 .ident = "NCR Corporation",
9180 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9181 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9182 },
9183 },
9184 { } /* terminating entry */
9185 },
9186 .hook = quirk_invert_brightness,
9187 },
9188};
9189
c43b5634 9190static struct intel_quirk intel_quirks[] = {
b690e96c 9191 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9192 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9193
b690e96c
JB		 9194 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9195 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9196
b690e96c
JB		 9197 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9198 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9199
ccd0d36e 9200 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9201 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9202 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9203
9204 /* Lenovo U160 cannot use SSC on LVDS */
9205 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9206
9207 /* Sony Vaio Y cannot use SSC on LVDS */
9208 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9209
9210 /* Acer Aspire 5734Z must invert backlight brightness */
9211 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9212
9213 /* Acer/eMachines G725 */
9214 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9215
9216 /* Acer/eMachines e725 */
9217 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9218
9219 /* Acer/Packard Bell NCL20 */
9220 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9221
9222 /* Acer Aspire 4736Z */
9223 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9224};
9225
9226static void intel_init_quirks(struct drm_device *dev)
9227{
9228 struct pci_dev *d = dev->pdev;
9229 int i;
9230
9231 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9232 struct intel_quirk *q = &intel_quirks[i];
9233
9234 if (d->device == q->device &&
9235 (d->subsystem_vendor == q->subsystem_vendor ||
9236 q->subsystem_vendor == PCI_ANY_ID) &&
9237 (d->subsystem_device == q->subsystem_device ||
9238 q->subsystem_device == PCI_ANY_ID))
9239 q->hook(dev);
9240 }
5f85f176
EE		 9241 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9242 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9243 intel_dmi_quirks[i].hook(dev);
9244 }
b690e96c
JB		 9245}
9246
9cce37f4
JB		 9247/* Disable the VGA plane that we never use */
9248static void i915_disable_vga(struct drm_device *dev)
9249{
9250 struct drm_i915_private *dev_priv = dev->dev_private;
9251 u8 sr1;
766aa1c4 9252 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9253
9254 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9255 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9256 sr1 = inb(VGA_SR_DATA);
9257 outb(sr1 | 1<<5, VGA_SR_DATA);
9258 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9259 udelay(300);
9260
9261 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9262 POSTING_READ(vga_reg);
9263}
9264
f817586c
DV		 9265void intel_modeset_init_hw(struct drm_device *dev)
9266{
fa42e23c 9267 intel_init_power_well(dev);
0232e927 9268
a8f78b58
ED		 9269 intel_prepare_ddi(dev);
9270
f817586c
DV		 9271 intel_init_clock_gating(dev);
9272
79f5b2c7 9273 mutex_lock(&dev->struct_mutex);
8090c6b9 9274 intel_enable_gt_powersave(dev);
79f5b2c7 9275 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9276}
9277
7d708ee4
ID		 9278void intel_modeset_suspend_hw(struct drm_device *dev)
9279{
9280 intel_suspend_hw(dev);
9281}
9282
79e53945
JB		 9283void intel_modeset_init(struct drm_device *dev)
9284{
652c393a 9285 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9286 int i, j, ret;
79e53945
JB		 9287
9288 drm_mode_config_init(dev);
9289
9290 dev->mode_config.min_width = 0;
9291 dev->mode_config.min_height = 0;
9292
019d96cb
DA		 9293 dev->mode_config.preferred_depth = 24;
9294 dev->mode_config.prefer_shadow = 1;
9295
e6ecefaa 9296 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9297
b690e96c
JB		 9298 intel_init_quirks(dev);
9299
1fa61106
ED		 9300 intel_init_pm(dev);
9301
e3c74757
BW		 9302 if (INTEL_INFO(dev)->num_pipes == 0)
9303 return;
9304
e70236a8
JB		 9305 intel_init_display(dev);
9306
a6c45cf0
CW		 9307 if (IS_GEN2(dev)) {
9308 dev->mode_config.max_width = 2048;
9309 dev->mode_config.max_height = 2048;
9310 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9311 dev->mode_config.max_width = 4096;
9312 dev->mode_config.max_height = 4096;
79e53945 9313 } else {
a6c45cf0
CW		 9314 dev->mode_config.max_width = 8192;
9315 dev->mode_config.max_height = 8192;
79e53945 9316 }
5d4545ae 9317 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9318
28c97730 9319 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9320 INTEL_INFO(dev)->num_pipes,
9321 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9322
7eb552ae 9323 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9324 intel_crtc_init(dev, i);
7f1f3851
JB		 9325 for (j = 0; j < dev_priv->num_plane; j++) {
9326 ret = intel_plane_init(dev, i, j);
9327 if (ret)
06da8da2
VS		 9328 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9329 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9330 }
79e53945
JB		 9331 }
9332
79f689aa 9333 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9334 intel_pch_pll_init(dev);
9335
9cce37f4
JB		 9336 /* Just disable it once at startup */
9337 i915_disable_vga(dev);
79e53945 9338 intel_setup_outputs(dev);
11be49eb
CW		 9339
9340 /* Just in case the BIOS is doing something questionable. */
9341 intel_disable_fbc(dev);
2c7111db
CW		 9342}
9343
24929352
DV		 9344static void
9345intel_connector_break_all_links(struct intel_connector *connector)
9346{
9347 connector->base.dpms = DRM_MODE_DPMS_OFF;
9348 connector->base.encoder = NULL;
9349 connector->encoder->connectors_active = false;
9350 connector->encoder->base.crtc = NULL;
9351}
9352
7fad798e
DV		 9353static void intel_enable_pipe_a(struct drm_device *dev)
9354{
9355 struct intel_connector *connector;
9356 struct drm_connector *crt = NULL;
9357 struct intel_load_detect_pipe load_detect_temp;
9358
9359 /* We can't just switch on the pipe A, we need to set things up with a
9360 * proper mode and output configuration. As a gross hack, enable pipe A
9361 * by enabling the load detect pipe once. */
9362 list_for_each_entry(connector,
9363 &dev->mode_config.connector_list,
9364 base.head) {
9365 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9366 crt = &connector->base;
9367 break;
9368 }
9369 }
9370
9371 if (!crt)
9372 return;
9373
9374 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9375 intel_release_load_detect_pipe(crt, &load_detect_temp);
9376
652c393a 9377
7fad798e
DV		 9378}
9379
fa555837
DV		 9380static bool
9381intel_check_plane_mapping(struct intel_crtc *crtc)
9382{
7eb552ae
BW		 9383 struct drm_device *dev = crtc->base.dev;
9384 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9385 u32 reg, val;
9386
7eb552ae 9387 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9388 return true;
9389
9390 reg = DSPCNTR(!crtc->plane);
9391 val = I915_READ(reg);
9392
9393 if ((val & DISPLAY_PLANE_ENABLE) &&
9394 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9395 return false;
9396
9397 return true;
9398}
9399
24929352
DV		 9400static void intel_sanitize_crtc(struct intel_crtc *crtc)
9401{
9402 struct drm_device *dev = crtc->base.dev;
9403 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9404 u32 reg;
24929352 9405
24929352 9406 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9407 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9408 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9409
9410 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9411 * disable the crtc (and hence change the state) if it is wrong. Note
9412 * that gen4+ has a fixed plane -> pipe mapping. */
9413 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9414 struct intel_connector *connector;
9415 bool plane;
9416
24929352
DV		 9417 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9418 crtc->base.base.id);
9419
9420 /* Pipe has the wrong plane attached and the plane is active.
9421 * Temporarily change the plane mapping and disable everything
9422 * ... */
9423 plane = crtc->plane;
9424 crtc->plane = !plane;
9425 dev_priv->display.crtc_disable(&crtc->base);
9426 crtc->plane = plane;
9427
9428 /* ... and break all links. */
9429 list_for_each_entry(connector, &dev->mode_config.connector_list,
9430 base.head) {
9431 if (connector->encoder->base.crtc != &crtc->base)
9432 continue;
9433
9434 intel_connector_break_all_links(connector);
9435 }
9436
9437 WARN_ON(crtc->active);
9438 crtc->base.enabled = false;
9439 }
24929352 9440
7fad798e
DV		 9441 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9442 crtc->pipe == PIPE_A && !crtc->active) {
9443 /* BIOS forgot to enable pipe A, this mostly happens after
9444 * resume. Force-enable the pipe to fix this, the update_dpms
9445 * call below we restore the pipe to the right state, but leave
9446 * the required bits on. */
9447 intel_enable_pipe_a(dev);
9448 }
9449
24929352
DV		 9450 /* Adjust the state of the output pipe according to whether we
9451 * have active connectors/encoders. */
9452 intel_crtc_update_dpms(&crtc->base);
9453
9454 if (crtc->active != crtc->base.enabled) {
9455 struct intel_encoder *encoder;
9456
9457 /* This can happen either due to bugs in the get_hw_state
9458 * functions or because the pipe is force-enabled due to the
9459 * pipe A quirk. */
9460 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9461 crtc->base.base.id,
9462 crtc->base.enabled ? "enabled" : "disabled",
9463 crtc->active ? "enabled" : "disabled");
9464
9465 crtc->base.enabled = crtc->active;
9466
9467 /* Because we only establish the connector -> encoder ->
9468 * crtc links if something is active, this means the
9469 * crtc is now deactivated. Break the links. connector
9470 * -> encoder links are only establish when things are
9471 * actually up, hence no need to break them. */
9472 WARN_ON(crtc->active);
9473
9474 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9475 WARN_ON(encoder->connectors_active);
9476 encoder->base.crtc = NULL;
9477 }
9478 }
9479}
9480
9481static void intel_sanitize_encoder(struct intel_encoder *encoder)
9482{
9483 struct intel_connector *connector;
9484 struct drm_device *dev = encoder->base.dev;
9485
9486 /* We need to check both for a crtc link (meaning that the
9487 * encoder is active and trying to read from a pipe) and the
9488 * pipe itself being active. */
9489 bool has_active_crtc = encoder->base.crtc &&
9490 to_intel_crtc(encoder->base.crtc)->active;
9491
9492 if (encoder->connectors_active && !has_active_crtc) {
9493 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9494 encoder->base.base.id,
9495 drm_get_encoder_name(&encoder->base));
9496
9497 /* Connector is active, but has no active pipe. This is
9498 * fallout from our resume register restoring. Disable
9499 * the encoder manually again. */
9500 if (encoder->base.crtc) {
9501 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9502 encoder->base.base.id,
9503 drm_get_encoder_name(&encoder->base));
9504 encoder->disable(encoder);
9505 }
9506
9507 /* Inconsistent output/port/pipe state happens presumably due to
9508 * a bug in one of the get_hw_state functions. Or someplace else
9509 * in our code, like the register restore mess on resume. Clamp
9510 * things to off as a safer default. */
9511 list_for_each_entry(connector,
9512 &dev->mode_config.connector_list,
9513 base.head) {
9514 if (connector->encoder != encoder)
9515 continue;
9516
9517 intel_connector_break_all_links(connector);
9518 }
9519 }
9520 /* Enabled encoders without active connectors will be fixed in
9521 * the crtc fixup. */
9522}
9523
44cec740 9524void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9525{
9526 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9527 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9528
9529 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9530 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9531 i915_disable_vga(dev);
0fde901f
KM		 9532 }
9533}
9534
24929352
DV		 9535/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9536 * and i915 state tracking structures. */
45e2b5f6
DV		 9537void intel_modeset_setup_hw_state(struct drm_device *dev,
9538 bool force_restore)
24929352
DV		 9539{
9540 struct drm_i915_private *dev_priv = dev->dev_private;
9541 enum pipe pipe;
b5644d05 9542 struct drm_plane *plane;
24929352
DV		 9543 struct intel_crtc *crtc;
9544 struct intel_encoder *encoder;
9545 struct intel_connector *connector;
9546
0e8ffe1b
DV		 9547 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9548 base.head) {
88adfff1 9549 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9550
0e8ffe1b
DV		 9551 crtc->active = dev_priv->display.get_pipe_config(crtc,
9552 &crtc->config);
24929352
DV		 9553
9554 crtc->base.enabled = crtc->active;
9555
9556 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9557 crtc->base.base.id,
9558 crtc->active ? "enabled" : "disabled");
9559 }
9560
affa9354 9561 if (HAS_DDI(dev))
6441ab5f
PZ		 9562 intel_ddi_setup_hw_pll_state(dev);
9563
24929352
DV		 9564 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9565 base.head) {
9566 pipe = 0;
9567
9568 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9569 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9570 encoder->base.crtc = &crtc->base;
9571 if (encoder->get_config)
9572 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9573 } else {
9574 encoder->base.crtc = NULL;
9575 }
9576
9577 encoder->connectors_active = false;
9578 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9579 encoder->base.base.id,
9580 drm_get_encoder_name(&encoder->base),
9581 encoder->base.crtc ? "enabled" : "disabled",
9582 pipe);
9583 }
9584
9585 list_for_each_entry(connector, &dev->mode_config.connector_list,
9586 base.head) {
9587 if (connector->get_hw_state(connector)) {
9588 connector->base.dpms = DRM_MODE_DPMS_ON;
9589 connector->encoder->connectors_active = true;
9590 connector->base.encoder = &connector->encoder->base;
9591 } else {
9592 connector->base.dpms = DRM_MODE_DPMS_OFF;
9593 connector->base.encoder = NULL;
9594 }
9595 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9596 connector->base.base.id,
9597 drm_get_connector_name(&connector->base),
9598 connector->base.encoder ? "enabled" : "disabled");
9599 }
9600
9601 /* HW state is read out, now we need to sanitize this mess. */
9602 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9603 base.head) {
9604 intel_sanitize_encoder(encoder);
9605 }
9606
9607 for_each_pipe(pipe) {
9608 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9609 intel_sanitize_crtc(crtc);
c0b03411 9610 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9611 }
9a935856 9612
45e2b5f6 9613 if (force_restore) {
f30da187
DV		 9614 /*
9615 * We need to use raw interfaces for restoring state to avoid
9616 * checking (bogus) intermediate states.
9617 */
45e2b5f6 9618 for_each_pipe(pipe) {
b5644d05
JB		 9619 struct drm_crtc *crtc =
9620 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9621
9622 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9623 crtc->fb);
45e2b5f6 9624 }
b5644d05
JB		 9625 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9626 intel_plane_restore(plane);
0fde901f
KM		 9627
9628 i915_redisable_vga(dev);
45e2b5f6
DV		 9629 } else {
9630 intel_modeset_update_staged_output_state(dev);
9631 }
8af6cf88
DV		 9632
9633 intel_modeset_check_state(dev);
2e938892
DV		 9634
9635 drm_mode_config_reset(dev);
2c7111db
CW		 9636}
9637
9638void intel_modeset_gem_init(struct drm_device *dev)
9639{
1833b134 9640 intel_modeset_init_hw(dev);
02e792fb
DV		 9641
9642 intel_setup_overlay(dev);
24929352 9643
45e2b5f6 9644 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9645}
9646
9647void intel_modeset_cleanup(struct drm_device *dev)
9648{
652c393a
JB		 9649 struct drm_i915_private *dev_priv = dev->dev_private;
9650 struct drm_crtc *crtc;
9651 struct intel_crtc *intel_crtc;
9652
fd0c0642
DV		 9653 /*
9654 * Interrupts and polling as the first thing to avoid creating havoc.
9655 * Too much stuff here (turning of rps, connectors, ...) would
9656 * experience fancy races otherwise.
9657 */
9658 drm_irq_uninstall(dev);
9659 cancel_work_sync(&dev_priv->hotplug_work);
9660 /*
9661 * Due to the hpd irq storm handling the hotplug work can re-arm the
9662 * poll handlers. Hence disable polling after hpd handling is shut down.
9663 */
f87ea761 9664 drm_kms_helper_poll_fini(dev);
fd0c0642 9665
652c393a
JB		 9666 mutex_lock(&dev->struct_mutex);
9667
723bfd70
JB		 9668 intel_unregister_dsm_handler();
9669
652c393a
JB		 9670 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9671 /* Skip inactive CRTCs */
9672 if (!crtc->fb)
9673 continue;
9674
9675 intel_crtc = to_intel_crtc(crtc);
3dec0095 9676 intel_increase_pllclock(crtc);
652c393a
JB		 9677 }
9678
973d04f9 9679 intel_disable_fbc(dev);
e70236a8 9680
8090c6b9 9681 intel_disable_gt_powersave(dev);
0cdab21f 9682
930ebb46
DV		 9683 ironlake_teardown_rc6(dev);
9684
69341a5e
KH		 9685 mutex_unlock(&dev->struct_mutex);
9686
1630fe75
CW		 9687 /* flush any delayed tasks or pending work */
9688 flush_scheduled_work();
9689
dc652f90
JN		 9690 /* destroy backlight, if any, before the connectors */
9691 intel_panel_destroy_backlight(dev);
9692
79e53945 9693 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9694
9695 intel_cleanup_overlay(dev);
79e53945
JB		 9696}
9697
f1c79df3
ZW		 9698/*
9699 * Return which encoder is currently attached for connector.
9700 */
df0e9248 9701struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9702{
df0e9248
CW		 9703 return &intel_attached_encoder(connector)->base;
9704}
f1c79df3 9705
df0e9248
CW		 9706void intel_connector_attach_encoder(struct intel_connector *connector,
9707 struct intel_encoder *encoder)
9708{
9709 connector->encoder = encoder;
9710 drm_mode_connector_attach_encoder(&connector->base,
9711 &encoder->base);
79e53945 9712}
28d52043
DA		 9713
9714/*
9715 * set vga decode state - true == enable VGA decode
9716 */
9717int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9718{
9719 struct drm_i915_private *dev_priv = dev->dev_private;
9720 u16 gmch_ctrl;
9721
9722 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9723 if (state)
9724 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9725 else
9726 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9727 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9728 return 0;
9729}
c4a1d9e4
CW		 9730
9731#ifdef CONFIG_DEBUG_FS
9732#include <linux/seq_file.h>
9733
9734struct intel_display_error_state {
ff57f1b0
PZ		 9735
9736 u32 power_well_driver;
9737
c4a1d9e4
CW		 9738 struct intel_cursor_error_state {
9739 u32 control;
9740 u32 position;
9741 u32 base;
9742 u32 size;
52331309 9743 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9744
9745 struct intel_pipe_error_state {
ff57f1b0 9746 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9747 u32 conf;
9748 u32 source;
9749
9750 u32 htotal;
9751 u32 hblank;
9752 u32 hsync;
9753 u32 vtotal;
9754 u32 vblank;
9755 u32 vsync;
52331309 9756 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9757
9758 struct intel_plane_error_state {
9759 u32 control;
9760 u32 stride;
9761 u32 size;
9762 u32 pos;
9763 u32 addr;
9764 u32 surface;
9765 u32 tile_offset;
52331309 9766 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9767};
9768
9769struct intel_display_error_state *
9770intel_display_capture_error_state(struct drm_device *dev)
9771{
0206e353 9772 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9773 struct intel_display_error_state *error;
702e7a56 9774 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9775 int i;
9776
9777 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9778 if (error == NULL)
9779 return NULL;
9780
ff57f1b0
PZ		 9781 if (HAS_POWER_WELL(dev))
9782 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9783
52331309 9784 for_each_pipe(i) {
702e7a56 9785 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9786 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9787
a18c4c3d
PZ		 9788 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9789 error->cursor[i].control = I915_READ(CURCNTR(i));
9790 error->cursor[i].position = I915_READ(CURPOS(i));
9791 error->cursor[i].base = I915_READ(CURBASE(i));
9792 } else {
9793 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9794 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9795 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9796 }
c4a1d9e4
CW		 9797
9798 error->plane[i].control = I915_READ(DSPCNTR(i));
9799 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9800 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9801 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9802 error->plane[i].pos = I915_READ(DSPPOS(i));
9803 }
ca291363
PZ		 9804 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9805 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9806 if (INTEL_INFO(dev)->gen >= 4) {
9807 error->plane[i].surface = I915_READ(DSPSURF(i));
9808 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9809 }
9810
702e7a56 9811 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9812 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9813 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9814 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9815 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9816 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9817 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9818 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9819 }
9820
12d217c7
PZ		 9821 /* In the code above we read the registers without checking if the power
9822 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9823 * prevent the next I915_WRITE from detecting it and printing an error
9824 * message. */
9825 if (HAS_POWER_WELL(dev))
9826 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9827
c4a1d9e4
CW		 9828 return error;
9829}
9830
edc3d884
MK		 9831#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9832
c4a1d9e4 9833void
edc3d884 9834intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9835 struct drm_device *dev,
9836 struct intel_display_error_state *error)
9837{
9838 int i;
9839
edc3d884 9840 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9841 if (HAS_POWER_WELL(dev))
edc3d884 9842 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9843 error->power_well_driver);
52331309 9844 for_each_pipe(i) {
edc3d884
MK		 9845 err_printf(m, "Pipe [%d]:\n", i);
9846 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9847 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9848 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9849 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9850 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9851 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9852 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9853 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9854 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9855 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9856
9857 err_printf(m, "Plane [%d]:\n", i);
9858 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9859 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9860 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9861 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9862 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9863 }
4b71a570 9864 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9865 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9866 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9867 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9868 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9869 }
9870
edc3d884
MK		 9871 err_printf(m, "Cursor [%d]:\n", i);
9872 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9873 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9874 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9875 }
9876}
9877#endif
Linux kernel - Deliverables
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