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drm/i915: Move double wide mode handling into pipe_config
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
18442d08
VS		 50static void ironlake_pch_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
f1f644dc 52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
a0c4da24 401 else
65ce4bf5 402 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
406 else
407 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 408 } else {
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 410 limit = &intel_limits_i8xx_lvds;
5d536e28 411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 412 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 413 else
414 limit = &intel_limits_i8xx_dac;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
f3f08572 675 u32 updrate, minupdate, p;
a0c4da24
JB		 676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
a0c4da24
JB		 686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
688
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
694 if (p2 > 10)
695 p2 = p2 - 1;
696 p = p1 * p2;
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
701 m = m1 * m2;
702 vco = updrate * m;
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
707 bestppm = 0;
708 flag = 1;
709 }
710 if (absppm < bestppm - 10) {
711 bestppm = absppm;
712 flag = 1;
713 }
714 if (flag) {
715 bestn = n;
716 bestm1 = m1;
717 bestm2 = m2;
718 bestp1 = p1;
719 bestp2 = p2;
720 flag = 0;
721 }
722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
20ddf665
VS		 736bool intel_crtc_active(struct drm_crtc *crtc)
737{
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
742 *
743 * We can ditch the adjusted_mode.clock check as soon
744 * as Haswell has gained clock readout/fastboot support.
745 *
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
748 */
749 return intel_crtc->active && crtc->fb &&
750 intel_crtc->config.adjusted_mode.clock;
751}
752
a5c961d1
PZ		 753enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 enum pipe pipe)
755{
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758
3b117c8f 759 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 760}
761
a928d536
PZ		 762static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
766
767 frame = I915_READ(frame_reg);
768
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
771}
772
9d0498a2
JB		 773/**
774 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @dev: drm device
776 * @pipe: pipe to wait for
777 *
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 * mode setting code.
780 */
781void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 782{
9d0498a2 783 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 784 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 785
a928d536
PZ		 786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
788 return;
789 }
790
300387c0
CW		 791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
793 *
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
800 * vblanks...
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
803 */
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
806
9d0498a2 807 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
810 50))
9d0498a2
JB		 811 DRM_DEBUG_KMS("vblank wait timed out\n");
812}
813
ab7ad7f6
KP		 814/*
815 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 816 * @dev: drm device
817 * @pipe: pipe to wait for
818 *
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
822 *
ab7ad7f6
KP		 823 * On Gen4 and above:
824 * wait for the pipe register state bit to turn off
825 *
826 * Otherwise:
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
58e10eb9 829 *
9d0498a2 830 */
58e10eb9 831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 832{
833 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
835 pipe);
ab7ad7f6
KP		 836
837 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 838 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 839
840 /* Wait for the Pipe State to go off */
58e10eb9
CW		 841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
842 100))
284637d9 843 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 844 } else {
837ba00f 845 u32 last_line, line_mask;
58e10eb9 846 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
848
837ba00f
PZ		 849 if (IS_GEN2(dev))
850 line_mask = DSL_LINEMASK_GEN2;
851 else
852 line_mask = DSL_LINEMASK_GEN3;
853
ab7ad7f6
KP		 854 /* Wait for the display line to settle */
855 do {
837ba00f 856 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 857 mdelay(5);
837ba00f 858 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
284637d9 861 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 862 }
79e53945
JB		 863}
864
b0ea7d37
DL		 865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
c36346e3
DL		 877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
b0ea7d37
DL		 905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
b24e7179
JB		 910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
55607e8a
DV		 916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
b24e7179
JB		 918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
b24e7179 930
23538ef1
JN		 931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
55607e8a 949struct intel_shared_dpll *
e2b78267
DV		 950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
a43f6e0f 954 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 955 return NULL;
956
a43f6e0f 957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 958}
959
040484af 960/* For ILK+ */
55607e8a
DV		 961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
040484af 964{
040484af 965 bool cur_state;
5358901f 966 struct intel_dpll_hw_state hw_state;
040484af 967
9d82aa17
ED		 968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
92b27b08 973 if (WARN (!pll,
46edb027 974 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 975 return;
ee7b9f93 976
5358901f 977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 978 WARN(cur_state != state,
5358901f
DV		 979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
040484af 981}
040484af
JB		 982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
ad80a810
PZ		 989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
040484af 991
affa9354
PZ		 992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
ad80a810 994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 995 val = I915_READ(reg);
ad80a810 996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
d63fa0dc
PZ		 1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
bf507ef7 1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1037 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1038 return;
1039
040484af
JB		 1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
55607e8a
DV		 1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
040484af
JB		 1047{
1048 int reg;
1049 u32 val;
55607e8a 1050 bool cur_state;
040484af
JB		 1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
55607e8a
DV		 1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
040484af
JB		 1058}
1059
ea0760cf
JB		 1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
0de3b485 1066 bool locked = true;
ea0760cf
JB		 1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1086 pipe_name(pipe));
ea0760cf
JB		 1087}
1088
93ce0ba6
JN		 1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
b840d907
JB		 1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
b24e7179
JB		 1111{
1112 int reg;
1113 u32 val;
63d7bbe9 1114 bool cur_state;
702e7a56
PZ		 1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
b24e7179 1117
8e636784
DV		 1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
b97186f0
PZ		 1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
63d7bbe9
JB		 1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1133 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
b24e7179
JB		 1138{
1139 int reg;
1140 u32 val;
931872fc 1141 bool cur_state;
b24e7179
JB		 1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
931872fc
CW		 1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1149}
1150
931872fc
CW		 1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
b24e7179
JB		 1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
653e1026 1157 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
653e1026
VS		 1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
19ec1358 1169 return;
28c05794 1170 }
19ec1358 1171
b24e7179 1172 /* Need to check both planes against the pipe */
08e2a7de 1173 for_each_pipe(i) {
b24e7179
JB		 1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1181 }
1182}
1183
19332d7a
JB		 1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
20674eef 1187 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1188 int reg, i;
1189 u32 val;
1190
20674eef
VS		 1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & SPRITE_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
19332d7a 1207 val = I915_READ(reg);
20674eef 1208 WARN((val & DVS_ENABLE),
06da8da2 1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1210 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1211 }
1212}
1213
92f2584a
JB		 1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
9d82aa17
ED		 1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
92f2584a
JB		 1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
ab9412ba
DV		 1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
92f2584a
JB		 1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
ab9412ba 1237 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
92f2584a
JB		 1243}
1244
4e634389
KP		 1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1519b995
KP		 1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
dc0fa718 1266 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1271 return false;
1272 } else {
dc0fa718 1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
291906f1 1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1311 enum pipe pipe, int reg, u32 port_sel)
291906f1 1312{
47a05eca 1313 u32 val = I915_READ(reg);
4e634389 1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1316 reg, pipe_name(pipe));
de9a35ab 1317
75c5da27
DV		 1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
de9a35ab 1320 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
47a05eca 1326 u32 val = I915_READ(reg);
b70ad586 1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 reg, pipe_name(pipe));
de9a35ab 1330
dc0fa718 1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1332 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1333 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
291906f1 1341
f0575e92
KP		 1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1
JB		 1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
b70ad586 1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1356 pipe_name(pipe));
291906f1 1357
e2debe91
PZ		 1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1361}
1362
426115cf 1363static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1364{
426115cf
DV		 1365 struct drm_device *dev = crtc->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int reg = DPLL(crtc->pipe);
1368 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1369
426115cf 1370 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1371
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1377 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1378
426115cf
DV		 1379 I915_WRITE(reg, dpll);
1380 POSTING_READ(reg);
1381 udelay(150);
1382
1383 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1388
1389 /* We do this three times for luck */
426115cf 1390 I915_WRITE(reg, dpll);
87442f73
DV		 1391 POSTING_READ(reg);
1392 udelay(150); /* wait for warmup */
426115cf 1393 I915_WRITE(reg, dpll);
87442f73
DV		 1394 POSTING_READ(reg);
1395 udelay(150); /* wait for warmup */
426115cf 1396 I915_WRITE(reg, dpll);
87442f73
DV		 1397 POSTING_READ(reg);
1398 udelay(150); /* wait for warmup */
1399}
1400
66e3d5c0 1401static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1402{
66e3d5c0
DV		 1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1407
66e3d5c0 1408 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1409
63d7bbe9 1410 /* No really, not for ILK+ */
87442f73 1411 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1412
1413 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1414 if (IS_MOBILE(dev) && !IS_I830(dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1416
66e3d5c0
DV		 1417 I915_WRITE(reg, dpll);
1418
1419 /* Wait for the clocks to stabilize. */
1420 POSTING_READ(reg);
1421 udelay(150);
1422
1423 if (INTEL_INFO(dev)->gen >= 4) {
1424 I915_WRITE(DPLL_MD(crtc->pipe),
1425 crtc->config.dpll_hw_state.dpll_md);
1426 } else {
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1429 *
1430 * So write it again.
1431 */
1432 I915_WRITE(reg, dpll);
1433 }
63d7bbe9
JB		 1434
1435 /* We do this three times for luck */
66e3d5c0 1436 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1437 POSTING_READ(reg);
1438 udelay(150); /* wait for warmup */
66e3d5c0 1439 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1440 POSTING_READ(reg);
1441 udelay(150); /* wait for warmup */
66e3d5c0 1442 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1443 POSTING_READ(reg);
1444 udelay(150); /* wait for warmup */
1445}
1446
1447/**
50b44a44 1448 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1451 *
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1453 *
1454 * Note! This is for pre-ILK only.
1455 */
50b44a44 1456static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1457{
63d7bbe9
JB		 1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460 return;
1461
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv, pipe);
1464
50b44a44
DV		 1465 I915_WRITE(DPLL(pipe), 0);
1466 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1467}
1468
89b667f8
JB		 1469void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1470{
1471 u32 port_mask;
1472
1473 if (!port)
1474 port_mask = DPLL_PORTB_READY_MASK;
1475 else
1476 port_mask = DPLL_PORTC_READY_MASK;
1477
1478 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1479 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480 'B' + port, I915_READ(DPLL(0)));
1481}
1482
92f2584a 1483/**
e72f9fbf 1484 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1485 * @dev_priv: i915 private structure
1486 * @pipe: pipe PLL to enable
1487 *
1488 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489 * drives the transcoder clock.
1490 */
e2b78267 1491static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1492{
e2b78267
DV		 1493 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1494 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1495
48da64a8 1496 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1497 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1498 if (WARN_ON(pll == NULL))
48da64a8
CW		 1499 return;
1500
1501 if (WARN_ON(pll->refcount == 0))
1502 return;
ee7b9f93 1503
46edb027
DV		 1504 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505 pll->name, pll->active, pll->on,
e2b78267 1506 crtc->base.base.id);
92f2584a 1507
cdbd2316
DV		 1508 if (pll->active++) {
1509 WARN_ON(!pll->on);
e9d6944e 1510 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1511 return;
1512 }
f4a091c7 1513 WARN_ON(pll->on);
ee7b9f93 1514
46edb027 1515 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1516 pll->enable(dev_priv, pll);
ee7b9f93 1517 pll->on = true;
92f2584a
JB		 1518}
1519
e2b78267 1520static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1521{
e2b78267
DV		 1522 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1523 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1524
92f2584a
JB		 1525 /* PCH only available on ILK+ */
1526 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1527 if (WARN_ON(pll == NULL))
ee7b9f93 1528 return;
92f2584a 1529
48da64a8
CW		 1530 if (WARN_ON(pll->refcount == 0))
1531 return;
7a419866 1532
46edb027
DV		 1533 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534 pll->name, pll->active, pll->on,
e2b78267 1535 crtc->base.base.id);
7a419866 1536
48da64a8 1537 if (WARN_ON(pll->active == 0)) {
e9d6944e 1538 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1539 return;
1540 }
1541
e9d6944e 1542 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1543 WARN_ON(!pll->on);
cdbd2316 1544 if (--pll->active)
7a419866 1545 return;
ee7b9f93 1546
46edb027 1547 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1548 pll->disable(dev_priv, pll);
ee7b9f93 1549 pll->on = false;
92f2584a
JB		 1550}
1551
b8a4f404
PZ		 1552static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553 enum pipe pipe)
040484af 1554{
23670b32 1555 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1556 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1558 uint32_t reg, val, pipeconf_val;
040484af
JB		 1559
1560 /* PCH only available on ILK+ */
1561 BUG_ON(dev_priv->info->gen < 5);
1562
1563 /* Make sure PCH DPLL is enabled */
e72f9fbf 1564 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1565 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1566
1567 /* FDI must be feeding us bits for PCH ports */
1568 assert_fdi_tx_enabled(dev_priv, pipe);
1569 assert_fdi_rx_enabled(dev_priv, pipe);
1570
23670b32
DV		 1571 if (HAS_PCH_CPT(dev)) {
1572 /* Workaround: Set the timing override bit before enabling the
1573 * pch transcoder. */
1574 reg = TRANS_CHICKEN2(pipe);
1575 val = I915_READ(reg);
1576 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1577 I915_WRITE(reg, val);
59c859d6 1578 }
23670b32 1579
ab9412ba 1580 reg = PCH_TRANSCONF(pipe);
040484af 1581 val = I915_READ(reg);
5f7f726d 1582 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1583
1584 if (HAS_PCH_IBX(dev_priv->dev)) {
1585 /*
1586 * make the BPC in transcoder be consistent with
1587 * that in pipeconf reg.
1588 */
dfd07d72
DV		 1589 val &= ~PIPECONF_BPC_MASK;
1590 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1591 }
5f7f726d
PZ		 1592
1593 val &= ~TRANS_INTERLACE_MASK;
1594 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1595 if (HAS_PCH_IBX(dev_priv->dev) &&
1596 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1597 val |= TRANS_LEGACY_INTERLACED_ILK;
1598 else
1599 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1600 else
1601 val |= TRANS_PROGRESSIVE;
1602
040484af
JB		 1603 I915_WRITE(reg, val | TRANS_ENABLE);
1604 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1605 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1606}
1607
8fb033d7 1608static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1609 enum transcoder cpu_transcoder)
040484af 1610{
8fb033d7 1611 u32 val, pipeconf_val;
8fb033d7
PZ		 1612
1613 /* PCH only available on ILK+ */
1614 BUG_ON(dev_priv->info->gen < 5);
1615
8fb033d7 1616 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1617 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1618 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1619
223a6fdf
PZ		 1620 /* Workaround: set timing override bit. */
1621 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1623 I915_WRITE(_TRANSA_CHICKEN2, val);
1624
25f3ef11 1625 val = TRANS_ENABLE;
937bb610 1626 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1627
9a76b1c6
PZ		 1628 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1629 PIPECONF_INTERLACED_ILK)
a35f2679 1630 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1631 else
1632 val |= TRANS_PROGRESSIVE;
1633
ab9412ba
DV		 1634 I915_WRITE(LPT_TRANSCONF, val);
1635 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1636 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1637}
1638
b8a4f404
PZ		 1639static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1640 enum pipe pipe)
040484af 1641{
23670b32
DV		 1642 struct drm_device *dev = dev_priv->dev;
1643 uint32_t reg, val;
040484af
JB		 1644
1645 /* FDI relies on the transcoder */
1646 assert_fdi_tx_disabled(dev_priv, pipe);
1647 assert_fdi_rx_disabled(dev_priv, pipe);
1648
291906f1
JB		 1649 /* Ports must be off as well */
1650 assert_pch_ports_disabled(dev_priv, pipe);
1651
ab9412ba 1652 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1653 val = I915_READ(reg);
1654 val &= ~TRANS_ENABLE;
1655 I915_WRITE(reg, val);
1656 /* wait for PCH transcoder off, transcoder state */
1657 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1658 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1659
1660 if (!HAS_PCH_IBX(dev)) {
1661 /* Workaround: Clear the timing override chicken bit again. */
1662 reg = TRANS_CHICKEN2(pipe);
1663 val = I915_READ(reg);
1664 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1665 I915_WRITE(reg, val);
1666 }
040484af
JB		 1667}
1668
ab4d966c 1669static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1670{
8fb033d7
PZ		 1671 u32 val;
1672
ab9412ba 1673 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1674 val &= ~TRANS_ENABLE;
ab9412ba 1675 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1676 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1677 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1678 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1679
1680 /* Workaround: clear timing override bit. */
1681 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1682 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1683 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1684}
1685
b24e7179 1686/**
309cfea8 1687 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1688 * @dev_priv: i915 private structure
1689 * @pipe: pipe to enable
040484af 1690 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1691 *
1692 * Enable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe is actually running (i.e. first vblank) before
1698 * returning.
1699 */
040484af 1700static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1701 bool pch_port, bool dsi)
b24e7179 1702{
702e7a56
PZ		 1703 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1704 pipe);
1a240d4d 1705 enum pipe pch_transcoder;
b24e7179
JB		 1706 int reg;
1707 u32 val;
1708
58c6eaa2 1709 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1710 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1711 assert_sprites_disabled(dev_priv, pipe);
1712
681e5811 1713 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1714 pch_transcoder = TRANSCODER_A;
1715 else
1716 pch_transcoder = pipe;
1717
b24e7179
JB		 1718 /*
1719 * A pipe without a PLL won't actually be able to drive bits from
1720 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1721 * need the check.
1722 */
1723 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1724 if (dsi)
1725 assert_dsi_pll_enabled(dev_priv);
1726 else
1727 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1728 else {
1729 if (pch_port) {
1730 /* if driving the PCH, we need FDI enabled */
cc391bbb 1731 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1732 assert_fdi_tx_pll_enabled(dev_priv,
1733 (enum pipe) cpu_transcoder);
040484af
JB		 1734 }
1735 /* FIXME: assert CPU port conditions for SNB+ */
1736 }
b24e7179 1737
702e7a56 1738 reg = PIPECONF(cpu_transcoder);
b24e7179 1739 val = I915_READ(reg);
00d70b15
CW		 1740 if (val & PIPECONF_ENABLE)
1741 return;
1742
1743 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1744 intel_wait_for_vblank(dev_priv->dev, pipe);
1745}
1746
1747/**
309cfea8 1748 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1749 * @dev_priv: i915 private structure
1750 * @pipe: pipe to disable
1751 *
1752 * Disable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe has shut down before returning.
1758 */
1759static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1760 enum pipe pipe)
1761{
702e7a56
PZ		 1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
b24e7179
JB		 1764 int reg;
1765 u32 val;
1766
1767 /*
1768 * Make sure planes won't keep trying to pump pixels to us,
1769 * or we might hang the display.
1770 */
1771 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1772 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1773 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1774
1775 /* Don't disable pipe A or pipe A PLLs if needed */
1776 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1777 return;
1778
702e7a56 1779 reg = PIPECONF(cpu_transcoder);
b24e7179 1780 val = I915_READ(reg);
00d70b15
CW		 1781 if ((val & PIPECONF_ENABLE) == 0)
1782 return;
1783
1784 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1785 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1786}
1787
d74362c9
KP		 1788/*
1789 * Plane regs are double buffered, going from enabled->disabled needs a
1790 * trigger in order to latch. The display address reg provides this.
1791 */
6f1d69b0 1792void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1793 enum plane plane)
1794{
14f86147
DL		 1795 if (dev_priv->info->gen >= 4)
1796 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1797 else
1798 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1799}
1800
b24e7179
JB		 1801/**
1802 * intel_enable_plane - enable a display plane on a given pipe
1803 * @dev_priv: i915 private structure
1804 * @plane: plane to enable
1805 * @pipe: pipe being fed
1806 *
1807 * Enable @plane on @pipe, making sure that @pipe is running first.
1808 */
1809static void intel_enable_plane(struct drm_i915_private *dev_priv,
1810 enum plane plane, enum pipe pipe)
1811{
1812 int reg;
1813 u32 val;
1814
1815 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816 assert_pipe_enabled(dev_priv, pipe);
1817
1818 reg = DSPCNTR(plane);
1819 val = I915_READ(reg);
00d70b15
CW		 1820 if (val & DISPLAY_PLANE_ENABLE)
1821 return;
1822
1823 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1824 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1825 intel_wait_for_vblank(dev_priv->dev, pipe);
1826}
1827
b24e7179
JB		 1828/**
1829 * intel_disable_plane - disable a display plane
1830 * @dev_priv: i915 private structure
1831 * @plane: plane to disable
1832 * @pipe: pipe consuming the data
1833 *
1834 * Disable @plane; should be an independent operation.
1835 */
1836static void intel_disable_plane(struct drm_i915_private *dev_priv,
1837 enum plane plane, enum pipe pipe)
1838{
1839 int reg;
1840 u32 val;
1841
1842 reg = DSPCNTR(plane);
1843 val = I915_READ(reg);
00d70b15
CW		 1844 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1845 return;
1846
1847 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1848 intel_flush_display_plane(dev_priv, plane);
1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1850}
1851
693db184
CW		 1852static bool need_vtd_wa(struct drm_device *dev)
1853{
1854#ifdef CONFIG_INTEL_IOMMU
1855 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1856 return true;
1857#endif
1858 return false;
1859}
1860
127bd2ac 1861int
48b956c5 1862intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1863 struct drm_i915_gem_object *obj,
919926ae 1864 struct intel_ring_buffer *pipelined)
6b95a207 1865{
ce453d81 1866 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1867 u32 alignment;
1868 int ret;
1869
05394f39 1870 switch (obj->tiling_mode) {
6b95a207 1871 case I915_TILING_NONE:
534843da
CW		 1872 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1873 alignment = 128 * 1024;
a6c45cf0 1874 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1875 alignment = 4 * 1024;
1876 else
1877 alignment = 64 * 1024;
6b95a207
KH		 1878 break;
1879 case I915_TILING_X:
1880 /* pin() will align the object as required by fence */
1881 alignment = 0;
1882 break;
1883 case I915_TILING_Y:
8bb6e959
DV		 1884 /* Despite that we check this in framebuffer_init userspace can
1885 * screw us over and change the tiling after the fact. Only
1886 * pinned buffers can't change their tiling. */
1887 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1888 return -EINVAL;
1889 default:
1890 BUG();
1891 }
1892
693db184
CW		 1893 /* Note that the w/a also requires 64 PTE of padding following the
1894 * bo. We currently fill all unused PTE with the shadow page and so
1895 * we should always have valid PTE following the scanout preventing
1896 * the VT-d warning.
1897 */
1898 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1899 alignment = 256 * 1024;
1900
ce453d81 1901 dev_priv->mm.interruptible = false;
2da3b9b9 1902 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1903 if (ret)
ce453d81 1904 goto err_interruptible;
6b95a207
KH		 1905
1906 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907 * fence, whereas 965+ only requires a fence if using
1908 * framebuffer compression. For simplicity, we always install
1909 * a fence as the cost is not that onerous.
1910 */
06d98131 1911 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1912 if (ret)
1913 goto err_unpin;
1690e1eb 1914
9a5a53b3 1915 i915_gem_object_pin_fence(obj);
6b95a207 1916
ce453d81 1917 dev_priv->mm.interruptible = true;
6b95a207 1918 return 0;
48b956c5
CW		 1919
1920err_unpin:
cc98b413 1921 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1922err_interruptible:
1923 dev_priv->mm.interruptible = true;
48b956c5 1924 return ret;
6b95a207
KH		 1925}
1926
1690e1eb
CW		 1927void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1928{
1929 i915_gem_object_unpin_fence(obj);
cc98b413 1930 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1931}
1932
c2c75131
DV		 1933/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934 * is assumed to be a power-of-two. */
bc752862
CW		 1935unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1936 unsigned int tiling_mode,
1937 unsigned int cpp,
1938 unsigned int pitch)
c2c75131 1939{
bc752862
CW		 1940 if (tiling_mode != I915_TILING_NONE) {
1941 unsigned int tile_rows, tiles;
c2c75131 1942
bc752862
CW		 1943 tile_rows = *y / 8;
1944 *y %= 8;
c2c75131 1945
bc752862
CW		 1946 tiles = *x / (512/cpp);
1947 *x %= 512/cpp;
1948
1949 return tile_rows * pitch * 8 + tiles * 4096;
1950 } else {
1951 unsigned int offset;
1952
1953 offset = *y * pitch + *x * cpp;
1954 *y = 0;
1955 *x = (offset & 4095) / cpp;
1956 return offset & -4096;
1957 }
c2c75131
DV		 1958}
1959
17638cd6
JB		 1960static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1961 int x, int y)
81255565
JB		 1962{
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
05394f39 1967 struct drm_i915_gem_object *obj;
81255565 1968 int plane = intel_crtc->plane;
e506a0c6 1969 unsigned long linear_offset;
81255565 1970 u32 dspcntr;
5eddb70b 1971 u32 reg;
81255565
JB		 1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
1976 break;
1977 default:
84f44ce7 1978 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1979 return -EINVAL;
1980 }
1981
1982 intel_fb = to_intel_framebuffer(fb);
1983 obj = intel_fb->obj;
81255565 1984
5eddb70b
CW		 1985 reg = DSPCNTR(plane);
1986 dspcntr = I915_READ(reg);
81255565
JB		 1987 /* Mask out pixel format bits in case we change it */
1988 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1989 switch (fb->pixel_format) {
1990 case DRM_FORMAT_C8:
81255565
JB		 1991 dspcntr |= DISPPLANE_8BPP;
1992 break;
57779d06
VS		 1993 case DRM_FORMAT_XRGB1555:
1994 case DRM_FORMAT_ARGB1555:
1995 dspcntr |= DISPPLANE_BGRX555;
81255565 1996 break;
57779d06
VS		 1997 case DRM_FORMAT_RGB565:
1998 dspcntr |= DISPPLANE_BGRX565;
1999 break;
2000 case DRM_FORMAT_XRGB8888:
2001 case DRM_FORMAT_ARGB8888:
2002 dspcntr |= DISPPLANE_BGRX888;
2003 break;
2004 case DRM_FORMAT_XBGR8888:
2005 case DRM_FORMAT_ABGR8888:
2006 dspcntr |= DISPPLANE_RGBX888;
2007 break;
2008 case DRM_FORMAT_XRGB2101010:
2009 case DRM_FORMAT_ARGB2101010:
2010 dspcntr |= DISPPLANE_BGRX101010;
2011 break;
2012 case DRM_FORMAT_XBGR2101010:
2013 case DRM_FORMAT_ABGR2101010:
2014 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2015 break;
2016 default:
baba133a 2017 BUG();
81255565 2018 }
57779d06 2019
a6c45cf0 2020 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2021 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2022 dspcntr |= DISPPLANE_TILED;
2023 else
2024 dspcntr &= ~DISPPLANE_TILED;
2025 }
2026
de1aa629
VS		 2027 if (IS_G4X(dev))
2028 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2029
5eddb70b 2030 I915_WRITE(reg, dspcntr);
81255565 2031
e506a0c6 2032 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2033
c2c75131
DV		 2034 if (INTEL_INFO(dev)->gen >= 4) {
2035 intel_crtc->dspaddr_offset =
bc752862
CW		 2036 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2037 fb->bits_per_pixel / 8,
2038 fb->pitches[0]);
c2c75131
DV		 2039 linear_offset -= intel_crtc->dspaddr_offset;
2040 } else {
e506a0c6 2041 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2042 }
e506a0c6 2043
f343c5f6
BW		 2044 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2046 fb->pitches[0]);
01f2c773 2047 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2048 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2049 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2050 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2051 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2052 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2053 } else
f343c5f6 2054 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2055 POSTING_READ(reg);
81255565 2056
17638cd6
JB		 2057 return 0;
2058}
2059
2060static int ironlake_update_plane(struct drm_crtc *crtc,
2061 struct drm_framebuffer *fb, int x, int y)
2062{
2063 struct drm_device *dev = crtc->dev;
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2066 struct intel_framebuffer *intel_fb;
2067 struct drm_i915_gem_object *obj;
2068 int plane = intel_crtc->plane;
e506a0c6 2069 unsigned long linear_offset;
17638cd6
JB		 2070 u32 dspcntr;
2071 u32 reg;
2072
2073 switch (plane) {
2074 case 0:
2075 case 1:
27f8227b 2076 case 2:
17638cd6
JB		 2077 break;
2078 default:
84f44ce7 2079 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2080 return -EINVAL;
2081 }
2082
2083 intel_fb = to_intel_framebuffer(fb);
2084 obj = intel_fb->obj;
2085
2086 reg = DSPCNTR(plane);
2087 dspcntr = I915_READ(reg);
2088 /* Mask out pixel format bits in case we change it */
2089 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2090 switch (fb->pixel_format) {
2091 case DRM_FORMAT_C8:
17638cd6
JB		 2092 dspcntr |= DISPPLANE_8BPP;
2093 break;
57779d06
VS		 2094 case DRM_FORMAT_RGB565:
2095 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2096 break;
57779d06
VS		 2097 case DRM_FORMAT_XRGB8888:
2098 case DRM_FORMAT_ARGB8888:
2099 dspcntr |= DISPPLANE_BGRX888;
2100 break;
2101 case DRM_FORMAT_XBGR8888:
2102 case DRM_FORMAT_ABGR8888:
2103 dspcntr |= DISPPLANE_RGBX888;
2104 break;
2105 case DRM_FORMAT_XRGB2101010:
2106 case DRM_FORMAT_ARGB2101010:
2107 dspcntr |= DISPPLANE_BGRX101010;
2108 break;
2109 case DRM_FORMAT_XBGR2101010:
2110 case DRM_FORMAT_ABGR2101010:
2111 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2112 break;
2113 default:
baba133a 2114 BUG();
17638cd6
JB		 2115 }
2116
2117 if (obj->tiling_mode != I915_TILING_NONE)
2118 dspcntr |= DISPPLANE_TILED;
2119 else
2120 dspcntr &= ~DISPPLANE_TILED;
2121
1f5d76db
PZ		 2122 if (IS_HASWELL(dev))
2123 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2124 else
2125 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2126
2127 I915_WRITE(reg, dspcntr);
2128
e506a0c6 2129 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2130 intel_crtc->dspaddr_offset =
bc752862
CW		 2131 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2132 fb->bits_per_pixel / 8,
2133 fb->pitches[0]);
c2c75131 2134 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2135
f343c5f6
BW		 2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2138 fb->pitches[0]);
01f2c773 2139 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2140 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2141 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2142 if (IS_HASWELL(dev)) {
2143 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2144 } else {
2145 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2146 I915_WRITE(DSPLINOFF(plane), linear_offset);
2147 }
17638cd6
JB		 2148 POSTING_READ(reg);
2149
2150 return 0;
2151}
2152
2153/* Assume fb object is pinned & idle & fenced and just update base pointers */
2154static int
2155intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2156 int x, int y, enum mode_set_atomic state)
2157{
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2160
6b8e6ed0
CW		 2161 if (dev_priv->display.disable_fbc)
2162 dev_priv->display.disable_fbc(dev);
3dec0095 2163 intel_increase_pllclock(crtc);
81255565 2164
6b8e6ed0 2165 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2166}
2167
96a02917
VS		 2168void intel_display_handle_reset(struct drm_device *dev)
2169{
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 struct drm_crtc *crtc;
2172
2173 /*
2174 * Flips in the rings have been nuked by the reset,
2175 * so complete all pending flips so that user space
2176 * will get its events and not get stuck.
2177 *
2178 * Also update the base address of all primary
2179 * planes to the the last fb to make sure we're
2180 * showing the correct fb after a reset.
2181 *
2182 * Need to make two loops over the crtcs so that we
2183 * don't try to grab a crtc mutex before the
2184 * pending_flip_queue really got woken up.
2185 */
2186
2187 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2189 enum plane plane = intel_crtc->plane;
2190
2191 intel_prepare_page_flip(dev, plane);
2192 intel_finish_page_flip_plane(dev, plane);
2193 }
2194
2195 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198 mutex_lock(&crtc->mutex);
2199 if (intel_crtc->active)
2200 dev_priv->display.update_plane(crtc, crtc->fb,
2201 crtc->x, crtc->y);
2202 mutex_unlock(&crtc->mutex);
2203 }
2204}
2205
14667a4b
CW		 2206static int
2207intel_finish_fb(struct drm_framebuffer *old_fb)
2208{
2209 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2210 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2211 bool was_interruptible = dev_priv->mm.interruptible;
2212 int ret;
2213
14667a4b
CW		 2214 /* Big Hammer, we also need to ensure that any pending
2215 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216 * current scanout is retired before unpinning the old
2217 * framebuffer.
2218 *
2219 * This should only fail upon a hung GPU, in which case we
2220 * can safely continue.
2221 */
2222 dev_priv->mm.interruptible = false;
2223 ret = i915_gem_object_finish_gpu(obj);
2224 dev_priv->mm.interruptible = was_interruptible;
2225
2226 return ret;
2227}
2228
198598d0
VS		 2229static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2230{
2231 struct drm_device *dev = crtc->dev;
2232 struct drm_i915_master_private *master_priv;
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 if (!dev->primary->master)
2236 return;
2237
2238 master_priv = dev->primary->master->driver_priv;
2239 if (!master_priv->sarea_priv)
2240 return;
2241
2242 switch (intel_crtc->pipe) {
2243 case 0:
2244 master_priv->sarea_priv->pipeA_x = x;
2245 master_priv->sarea_priv->pipeA_y = y;
2246 break;
2247 case 1:
2248 master_priv->sarea_priv->pipeB_x = x;
2249 master_priv->sarea_priv->pipeB_y = y;
2250 break;
2251 default:
2252 break;
2253 }
2254}
2255
5c3b82e2 2256static int
3c4fdcfb 2257intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2258 struct drm_framebuffer *fb)
79e53945
JB		 2259{
2260 struct drm_device *dev = crtc->dev;
6b8e6ed0 2261 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2263 struct drm_framebuffer *old_fb;
5c3b82e2 2264 int ret;
79e53945
JB		 2265
2266 /* no fb bound */
94352cf9 2267 if (!fb) {
a5071c2f 2268 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2269 return 0;
2270 }
2271
7eb552ae 2272 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2273 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274 plane_name(intel_crtc->plane),
2275 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2276 return -EINVAL;
79e53945
JB		 2277 }
2278
5c3b82e2 2279 mutex_lock(&dev->struct_mutex);
265db958 2280 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2281 to_intel_framebuffer(fb)->obj,
919926ae 2282 NULL);
5c3b82e2
CW		 2283 if (ret != 0) {
2284 mutex_unlock(&dev->struct_mutex);
a5071c2f 2285 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2286 return ret;
2287 }
79e53945 2288
4d6a3e63
JB		 2289 /* Update pipe size and adjust fitter if needed */
2290 if (i915_fastboot) {
2291 I915_WRITE(PIPESRC(intel_crtc->pipe),
2292 ((crtc->mode.hdisplay - 1) << 16) |
2293 (crtc->mode.vdisplay - 1));
2294 if (!intel_crtc->config.pch_pfit.size &&
2295 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2296 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2297 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2298 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2299 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2300 }
2301 }
2302
94352cf9 2303 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2304 if (ret) {
94352cf9 2305 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2306 mutex_unlock(&dev->struct_mutex);
a5071c2f 2307 DRM_ERROR("failed to update base address\n");
4e6cfefc 2308 return ret;
79e53945 2309 }
3c4fdcfb 2310
94352cf9
DV		 2311 old_fb = crtc->fb;
2312 crtc->fb = fb;
6c4c86f5
DV		 2313 crtc->x = x;
2314 crtc->y = y;
94352cf9 2315
b7f1de28 2316 if (old_fb) {
d7697eea
DV		 2317 if (intel_crtc->active && old_fb != fb)
2318 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2319 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2320 }
652c393a 2321
6b8e6ed0 2322 intel_update_fbc(dev);
4906557e 2323 intel_edp_psr_update(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
1e833f40
DV		 2372static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373{
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375}
2376
01a415fd
DV		 2377static void ivb_modeset_global_resources(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
1e833f40
DV		 2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
8db9d77b
ZW		 2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
0fc932b8 2410 int plane = intel_crtc->plane;
5eddb70b 2411 u32 reg, temp, tries;
8db9d77b 2412
0fc932b8
JB		 2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
e1a44743
AJ		 2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
5eddb70b
CW		 2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
e1a44743
AJ		 2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
e1a44743
AJ		 2425 udelay(150);
2426
8db9d77b 2427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
627eb5a3
DV		 2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
8db9d77b
ZW		 2443 udelay(150);
2444
5b2adf89 2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 POSTING_READ(reg);
2478 udelay(150);
8db9d77b 2479
5eddb70b 2480 reg = FDI_RX_IIR(pipe);
e1a44743 2481 for (tries = 0; tries < 5; tries++) {
5eddb70b 2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
8db9d77b 2490 }
e1a44743 2491 if (tries == 5)
5eddb70b 2492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2493
2494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2495
8db9d77b
ZW		 2496}
2497
0206e353 2498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
fa37d39e 2512 u32 reg, temp, i, retry;
8db9d77b 2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
e1a44743
AJ		 2523 udelay(150);
2524
8db9d77b 2525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
627eb5a3
DV		 2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2536
d74cf324
DV		 2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
0206e353 2554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(500);
2563
fa37d39e
SP		 2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
8db9d77b 2574 }
fa37d39e
SP		 2575 if (retry < 5)
2576 break;
8db9d77b
ZW		 2577 }
2578 if (i == 4)
5eddb70b 2579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2580
2581 /* Train 2 */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
5eddb70b 2591 I915_WRITE(reg, temp);
8db9d77b 2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
357555c0
JB		 2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
139ccd3f 2644 u32 reg, temp, i, j;
357555c0
JB		 2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
01a415fd
DV		 2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
139ccd3f
JB		 2660 /* Try each vswing and preemphasis setting twice before moving on */
2661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2662 /* disable first in case we need to retry */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp &= ~FDI_TX_ENABLE;
2667 I915_WRITE(reg, temp);
357555c0 2668
139ccd3f
JB		 2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp &= ~FDI_RX_ENABLE;
2674 I915_WRITE(reg, temp);
357555c0 2675
139ccd3f 2676 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
139ccd3f
JB		 2679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2683 temp |= snb_b_fdi_train_param[j/2];
2684 temp |= FDI_COMPOSITE_SYNC;
2685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2686
139ccd3f
JB		 2687 I915_WRITE(FDI_RX_MISC(pipe),
2688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2689
139ccd3f 2690 reg = FDI_RX_CTL(pipe);
357555c0 2691 temp = I915_READ(reg);
139ccd3f
JB		 2692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2693 temp |= FDI_COMPOSITE_SYNC;
2694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2695
139ccd3f
JB		 2696 POSTING_READ(reg);
2697 udelay(1); /* should be 0.5us */
357555c0 2698
139ccd3f
JB		 2699 for (i = 0; i < 4; i++) {
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2703
139ccd3f
JB		 2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2708 i);
2709 break;
2710 }
2711 udelay(1); /* should be 0.5us */
2712 }
2713 if (i == 4) {
2714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2715 continue;
2716 }
357555c0 2717
139ccd3f 2718 /* Train 2 */
357555c0
JB		 2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
139ccd3f
JB		 2721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2723 I915_WRITE(reg, temp);
2724
2725 reg = FDI_RX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2729 I915_WRITE(reg, temp);
2730
2731 POSTING_READ(reg);
139ccd3f 2732 udelay(2); /* should be 1.5us */
357555c0 2733
139ccd3f
JB		 2734 for (i = 0; i < 4; i++) {
2735 reg = FDI_RX_IIR(pipe);
2736 temp = I915_READ(reg);
2737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2738
139ccd3f
JB		 2739 if (temp & FDI_RX_SYMBOL_LOCK ||
2740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2743 i);
2744 goto train_done;
2745 }
2746 udelay(2); /* should be 1.5us */
357555c0 2747 }
139ccd3f
JB		 2748 if (i == 4)
2749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2750 }
357555c0 2751
139ccd3f 2752train_done:
357555c0
JB		 2753 DRM_DEBUG_KMS("FDI train done.\n");
2754}
2755
88cefb6c 2756static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2757{
88cefb6c 2758 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2759 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2760 int pipe = intel_crtc->pipe;
5eddb70b 2761 u32 reg, temp;
79e53945 2762
c64e311e 2763
c98e9dcf 2764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
627eb5a3
DV		 2767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2771
2772 POSTING_READ(reg);
c98e9dcf
JB		 2773 udelay(200);
2774
2775 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2776 temp = I915_READ(reg);
2777 I915_WRITE(reg, temp | FDI_PCDCLK);
2778
2779 POSTING_READ(reg);
c98e9dcf
JB		 2780 udelay(200);
2781
20749730
PZ		 2782 /* Enable CPU FDI TX PLL, always on for Ironlake */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2787
20749730
PZ		 2788 POSTING_READ(reg);
2789 udelay(100);
6be4a607 2790 }
0e23b99d
JB		 2791}
2792
88cefb6c
DV		 2793static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2794{
2795 struct drm_device *dev = intel_crtc->base.dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 int pipe = intel_crtc->pipe;
2798 u32 reg, temp;
2799
2800 /* Switch from PCDclk to Rawclk */
2801 reg = FDI_RX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2804
2805 /* Disable CPU FDI TX PLL */
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2809
2810 POSTING_READ(reg);
2811 udelay(100);
2812
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2816
2817 /* Wait for the clocks to turn off. */
2818 POSTING_READ(reg);
2819 udelay(100);
2820}
2821
0fc932b8
JB		 2822static void ironlake_fdi_disable(struct drm_crtc *crtc)
2823{
2824 struct drm_device *dev = crtc->dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827 int pipe = intel_crtc->pipe;
2828 u32 reg, temp;
2829
2830 /* disable CPU FDI tx and PCH FDI rx */
2831 reg = FDI_TX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2834 POSTING_READ(reg);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 temp &= ~(0x7 << 16);
dfd07d72 2839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2841
2842 POSTING_READ(reg);
2843 udelay(100);
2844
2845 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2846 if (HAS_PCH_IBX(dev)) {
2847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2848 }
0fc932b8
JB		 2849
2850 /* still set train pattern 1 */
2851 reg = FDI_TX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 I915_WRITE(reg, temp);
2856
2857 reg = FDI_RX_CTL(pipe);
2858 temp = I915_READ(reg);
2859 if (HAS_PCH_CPT(dev)) {
2860 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2861 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2862 } else {
2863 temp &= ~FDI_LINK_TRAIN_NONE;
2864 temp |= FDI_LINK_TRAIN_PATTERN_1;
2865 }
2866 /* BPC in FDI rx is consistent with that in PIPECONF */
2867 temp &= ~(0x07 << 16);
dfd07d72 2868 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2869 I915_WRITE(reg, temp);
2870
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
5bb61643
CW		 2875static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2880 unsigned long flags;
2881 bool pending;
2882
10d83730
VS		 2883 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2884 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2885 return false;
2886
2887 spin_lock_irqsave(&dev->event_lock, flags);
2888 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2889 spin_unlock_irqrestore(&dev->event_lock, flags);
2890
2891 return pending;
2892}
2893
e6c3a2a6
CW		 2894static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2895{
0f91128d 2896 struct drm_device *dev = crtc->dev;
5bb61643 2897 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2898
2899 if (crtc->fb == NULL)
2900 return;
2901
2c10d571
DV		 2902 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2903
5bb61643
CW		 2904 wait_event(dev_priv->pending_flip_queue,
2905 !intel_crtc_has_pending_flip(crtc));
2906
0f91128d
CW		 2907 mutex_lock(&dev->struct_mutex);
2908 intel_finish_fb(crtc->fb);
2909 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2910}
2911
e615efe4
ED		 2912/* Program iCLKIP clock to the desired frequency */
2913static void lpt_program_iclkip(struct drm_crtc *crtc)
2914{
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
12d7ceed 2917 int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
e615efe4
ED		 2918 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2919 u32 temp;
2920
09153000
DV		 2921 mutex_lock(&dev_priv->dpio_lock);
2922
e615efe4
ED		 2923 /* It is necessary to ungate the pixclk gate prior to programming
2924 * the divisors, and gate it back when it is done.
2925 */
2926 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2927
2928 /* Disable SSCCTL */
2929 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2930 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2931 SBI_SSCCTL_DISABLE,
2932 SBI_ICLK);
e615efe4
ED		 2933
2934 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2935 if (clock == 20000) {
e615efe4
ED		 2936 auxdiv = 1;
2937 divsel = 0x41;
2938 phaseinc = 0x20;
2939 } else {
2940 /* The iCLK virtual clock root frequency is in MHz,
12d7ceed 2941 * but the adjusted_mode->clock in in KHz. To get the divisors,
e615efe4
ED		 2942 * it is necessary to divide one by another, so we
2943 * convert the virtual clock precision to KHz here for higher
2944 * precision.
2945 */
2946 u32 iclk_virtual_root_freq = 172800 * 1000;
2947 u32 iclk_pi_range = 64;
2948 u32 desired_divisor, msb_divisor_value, pi_value;
2949
12d7ceed 2950 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2951 msb_divisor_value = desired_divisor / iclk_pi_range;
2952 pi_value = desired_divisor % iclk_pi_range;
2953
2954 auxdiv = 0;
2955 divsel = msb_divisor_value - 2;
2956 phaseinc = pi_value;
2957 }
2958
2959 /* This should not happen with any sane values */
2960 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2961 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2962 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2963 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2964
2965 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2966 clock,
e615efe4
ED		 2967 auxdiv,
2968 divsel,
2969 phasedir,
2970 phaseinc);
2971
2972 /* Program SSCDIVINTPHASE6 */
988d6ee8 2973 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2974 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2975 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2976 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2977 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2978 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2979 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2980 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2981
2982 /* Program SSCAUXDIV */
988d6ee8 2983 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2984 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2986 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2987
2988 /* Enable modulator and associated divider */
988d6ee8 2989 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2990 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2991 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2992
2993 /* Wait for initialization time */
2994 udelay(24);
2995
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2997
2998 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2999}
3000
275f01b2
DV		 3001static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3002 enum pipe pch_transcoder)
3003{
3004 struct drm_device *dev = crtc->base.dev;
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3007
3008 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3009 I915_READ(HTOTAL(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3011 I915_READ(HBLANK(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3013 I915_READ(HSYNC(cpu_transcoder)));
3014
3015 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3016 I915_READ(VTOTAL(cpu_transcoder)));
3017 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3018 I915_READ(VBLANK(cpu_transcoder)));
3019 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3020 I915_READ(VSYNC(cpu_transcoder)));
3021 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3022 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3023}
3024
f67a559d
JB		 3025/*
3026 * Enable PCH resources required for PCH ports:
3027 * - PCH PLLs
3028 * - FDI training & RX/TX
3029 * - update transcoder timings
3030 * - DP transcoding bits
3031 * - transcoder
3032 */
3033static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038 int pipe = intel_crtc->pipe;
ee7b9f93 3039 u32 reg, temp;
2c07245f 3040
ab9412ba 3041 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3042
cd986abb
DV		 3043 /* Write the TU size bits before fdi link training, so that error
3044 * detection works. */
3045 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3046 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3047
c98e9dcf 3048 /* For PCH output, training FDI link */
674cf967 3049 dev_priv->display.fdi_link_train(crtc);
2c07245f 3050
3ad8a208
DV		 3051 /* We need to program the right clock selection before writing the pixel
3052 * mutliplier into the DPLL. */
303b81e0 3053 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3054 u32 sel;
4b645f14 3055
c98e9dcf 3056 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3057 temp |= TRANS_DPLL_ENABLE(pipe);
3058 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3059 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3060 temp |= sel;
3061 else
3062 temp &= ~sel;
c98e9dcf 3063 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3064 }
5eddb70b 3065
3ad8a208
DV		 3066 /* XXX: pch pll's can be enabled any time before we enable the PCH
3067 * transcoder, and we actually should do this to not upset any PCH
3068 * transcoder that already use the clock when we share it.
3069 *
3070 * Note that enable_shared_dpll tries to do the right thing, but
3071 * get_shared_dpll unconditionally resets the pll - we need that to have
3072 * the right LVDS enable sequence. */
3073 ironlake_enable_shared_dpll(intel_crtc);
3074
d9b6cb56
JB		 3075 /* set transcoder timing, panel must allow it */
3076 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3077 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3078
303b81e0 3079 intel_fdi_normal_train(crtc);
5e84e1a4 3080
c98e9dcf
JB		 3081 /* For PCH DP, enable TRANS_DP_CTL */
3082 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3083 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3085 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3086 reg = TRANS_DP_CTL(pipe);
3087 temp = I915_READ(reg);
3088 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3089 TRANS_DP_SYNC_MASK |
3090 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3091 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092 TRANS_DP_ENH_FRAMING);
9325c9f0 3093 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3094
3095 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3096 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3097 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3098 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3099
3100 switch (intel_trans_dp_port_sel(crtc)) {
3101 case PCH_DP_B:
5eddb70b 3102 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3103 break;
3104 case PCH_DP_C:
5eddb70b 3105 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3106 break;
3107 case PCH_DP_D:
5eddb70b 3108 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3109 break;
3110 default:
e95d41e1 3111 BUG();
32f9d658 3112 }
2c07245f 3113
5eddb70b 3114 I915_WRITE(reg, temp);
6be4a607 3115 }
b52eb4dc 3116
b8a4f404 3117 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3118}
3119
1507e5bd
PZ		 3120static void lpt_pch_enable(struct drm_crtc *crtc)
3121{
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3125 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3126
ab9412ba 3127 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3128
8c52b5e8 3129 lpt_program_iclkip(crtc);
1507e5bd 3130
0540e488 3131 /* Set transcoder timing. */
275f01b2 3132 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3133
937bb610 3134 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3135}
3136
e2b78267 3137static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3138{
e2b78267 3139 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3140
3141 if (pll == NULL)
3142 return;
3143
3144 if (pll->refcount == 0) {
46edb027 3145 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3146 return;
3147 }
3148
f4a091c7
DV		 3149 if (--pll->refcount == 0) {
3150 WARN_ON(pll->on);
3151 WARN_ON(pll->active);
3152 }
3153
a43f6e0f 3154 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3155}
3156
b89a1d39 3157static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3158{
e2b78267
DV		 3159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3160 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3161 enum intel_dpll_id i;
ee7b9f93 3162
ee7b9f93 3163 if (pll) {
46edb027
DV		 3164 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165 crtc->base.base.id, pll->name);
e2b78267 3166 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3167 }
3168
98b6bd99
DV		 3169 if (HAS_PCH_IBX(dev_priv->dev)) {
3170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3171 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3172 pll = &dev_priv->shared_dplls[i];
98b6bd99 3173
46edb027
DV		 3174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175 crtc->base.base.id, pll->name);
98b6bd99
DV		 3176
3177 goto found;
3178 }
3179
e72f9fbf
DV		 3180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3182
3183 /* Only want to check enabled timings first */
3184 if (pll->refcount == 0)
3185 continue;
3186
b89a1d39
DV		 3187 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3188 sizeof(pll->hw_state)) == 0) {
46edb027 3189 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3190 crtc->base.base.id,
46edb027 3191 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3192
3193 goto found;
3194 }
3195 }
3196
3197 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3198 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3199 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3200 if (pll->refcount == 0) {
46edb027
DV		 3201 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3203 goto found;
3204 }
3205 }
3206
3207 return NULL;
3208
3209found:
a43f6e0f 3210 crtc->config.shared_dpll = i;
46edb027
DV		 3211 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3212 pipe_name(crtc->pipe));
ee7b9f93 3213
cdbd2316 3214 if (pll->active == 0) {
66e985c0
DV		 3215 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3216 sizeof(pll->hw_state));
3217
46edb027 3218 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3219 WARN_ON(pll->on);
e9d6944e 3220 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3221
15bdd4cf 3222 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3223 }
3224 pll->refcount++;
e04c7350 3225
ee7b9f93
JB		 3226 return pll;
3227}
3228
a1520318 3229static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3230{
3231 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3232 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3233 u32 temp;
3234
3235 temp = I915_READ(dslreg);
3236 udelay(500);
3237 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3238 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3239 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3240 }
3241}
3242
b074cec8
JB		 3243static void ironlake_pfit_enable(struct intel_crtc *crtc)
3244{
3245 struct drm_device *dev = crtc->base.dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 int pipe = crtc->pipe;
3248
0ef37f3f 3249 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3250 /* Force use of hard-coded filter coefficients
3251 * as some pre-programmed values are broken,
3252 * e.g. x201.
3253 */
3254 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3256 PF_PIPE_SEL_IVB(pipe));
3257 else
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3259 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3260 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3261 }
3262}
3263
bb53d4ae
VS		 3264static void intel_enable_planes(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3268 struct intel_plane *intel_plane;
3269
3270 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3271 if (intel_plane->pipe == pipe)
3272 intel_plane_restore(&intel_plane->base);
3273}
3274
3275static void intel_disable_planes(struct drm_crtc *crtc)
3276{
3277 struct drm_device *dev = crtc->dev;
3278 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3279 struct intel_plane *intel_plane;
3280
3281 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3282 if (intel_plane->pipe == pipe)
3283 intel_plane_disable(&intel_plane->base);
3284}
3285
f67a559d
JB		 3286static void ironlake_crtc_enable(struct drm_crtc *crtc)
3287{
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3291 struct intel_encoder *encoder;
f67a559d
JB		 3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
f67a559d 3294
08a48469
DV		 3295 WARN_ON(!crtc->enabled);
3296
f67a559d
JB		 3297 if (intel_crtc->active)
3298 return;
3299
3300 intel_crtc->active = true;
8664281b
PZ		 3301
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3304
f6736a1a 3305 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3306 if (encoder->pre_enable)
3307 encoder->pre_enable(encoder);
f67a559d 3308
5bfe2ac0 3309 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3310 /* Note: FDI PLL enabling _must_ be done before we enable the
3311 * cpu pipes, hence this is separate from all the other fdi/pch
3312 * enabling. */
88cefb6c 3313 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3314 } else {
3315 assert_fdi_tx_disabled(dev_priv, pipe);
3316 assert_fdi_rx_disabled(dev_priv, pipe);
3317 }
f67a559d 3318
b074cec8 3319 ironlake_pfit_enable(intel_crtc);
f67a559d 3320
9c54c0dd
JB		 3321 /*
3322 * On ILK+ LUT must be loaded before the pipe is running but with
3323 * clocks enabled
3324 */
3325 intel_crtc_load_lut(crtc);
3326
f37fcc2a 3327 intel_update_watermarks(crtc);
5bfe2ac0 3328 intel_enable_pipe(dev_priv, pipe,
23538ef1 3329 intel_crtc->config.has_pch_encoder, false);
f67a559d 3330 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3331 intel_enable_planes(crtc);
5c38d48c 3332 intel_crtc_update_cursor(crtc, true);
f67a559d 3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder)
f67a559d 3335 ironlake_pch_enable(crtc);
c98e9dcf 3336
d1ebd816 3337 mutex_lock(&dev->struct_mutex);
bed4a673 3338 intel_update_fbc(dev);
d1ebd816
BW		 3339 mutex_unlock(&dev->struct_mutex);
3340
fa5c73b1
DV		 3341 for_each_encoder_on_crtc(dev, crtc, encoder)
3342 encoder->enable(encoder);
61b77ddd
DV		 3343
3344 if (HAS_PCH_CPT(dev))
a1520318 3345 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3346
3347 /*
3348 * There seems to be a race in PCH platform hw (at least on some
3349 * outputs) where an enabled pipe still completes any pageflip right
3350 * away (as if the pipe is off) instead of waiting for vblank. As soon
3351 * as the first vblank happend, everything works as expected. Hence just
3352 * wait for one vblank before returning to avoid strange things
3353 * happening.
3354 */
3355 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3356}
3357
42db64ef
PZ		 3358/* IPS only exists on ULT machines and is tied to pipe A. */
3359static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3360{
f5adf94e 3361 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3362}
3363
3364static void hsw_enable_ips(struct intel_crtc *crtc)
3365{
3366 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3367
3368 if (!crtc->config.ips_enabled)
3369 return;
3370
3371 /* We can only enable IPS after we enable a plane and wait for a vblank.
3372 * We guarantee that the plane is enabled by calling intel_enable_ips
3373 * only after intel_enable_plane. And intel_enable_plane already waits
3374 * for a vblank, so all we need to do here is to enable the IPS bit. */
3375 assert_plane_enabled(dev_priv, crtc->plane);
3376 I915_WRITE(IPS_CTL, IPS_ENABLE);
3377}
3378
3379static void hsw_disable_ips(struct intel_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->base.dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383
3384 if (!crtc->config.ips_enabled)
3385 return;
3386
3387 assert_plane_enabled(dev_priv, crtc->plane);
3388 I915_WRITE(IPS_CTL, 0);
3389
3390 /* We need to wait for a vblank before we can disable the plane. */
3391 intel_wait_for_vblank(dev, crtc->pipe);
3392}
3393
4f771f10
PZ		 3394static void haswell_crtc_enable(struct drm_crtc *crtc)
3395{
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 struct intel_encoder *encoder;
3400 int pipe = intel_crtc->pipe;
3401 int plane = intel_crtc->plane;
4f771f10
PZ		 3402
3403 WARN_ON(!crtc->enabled);
3404
3405 if (intel_crtc->active)
3406 return;
3407
3408 intel_crtc->active = true;
8664281b
PZ		 3409
3410 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3411 if (intel_crtc->config.has_pch_encoder)
3412 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3413
5bfe2ac0 3414 if (intel_crtc->config.has_pch_encoder)
04945641 3415 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3416
3417 for_each_encoder_on_crtc(dev, crtc, encoder)
3418 if (encoder->pre_enable)
3419 encoder->pre_enable(encoder);
3420
1f544388 3421 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3422
b074cec8 3423 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3424
3425 /*
3426 * On ILK+ LUT must be loaded before the pipe is running but with
3427 * clocks enabled
3428 */
3429 intel_crtc_load_lut(crtc);
3430
1f544388 3431 intel_ddi_set_pipe_settings(crtc);
8228c251 3432 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3433
f37fcc2a 3434 intel_update_watermarks(crtc);
5bfe2ac0 3435 intel_enable_pipe(dev_priv, pipe,
23538ef1 3436 intel_crtc->config.has_pch_encoder, false);
4f771f10 3437 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3438 intel_enable_planes(crtc);
5c38d48c 3439 intel_crtc_update_cursor(crtc, true);
4f771f10 3440
42db64ef
PZ		 3441 hsw_enable_ips(intel_crtc);
3442
5bfe2ac0 3443 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3444 lpt_pch_enable(crtc);
4f771f10
PZ		 3445
3446 mutex_lock(&dev->struct_mutex);
3447 intel_update_fbc(dev);
3448 mutex_unlock(&dev->struct_mutex);
3449
8807e55b 3450 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3451 encoder->enable(encoder);
8807e55b
JN		 3452 intel_opregion_notify_encoder(encoder, true);
3453 }
4f771f10 3454
4f771f10
PZ		 3455 /*
3456 * There seems to be a race in PCH platform hw (at least on some
3457 * outputs) where an enabled pipe still completes any pageflip right
3458 * away (as if the pipe is off) instead of waiting for vblank. As soon
3459 * as the first vblank happend, everything works as expected. Hence just
3460 * wait for one vblank before returning to avoid strange things
3461 * happening.
3462 */
3463 intel_wait_for_vblank(dev, intel_crtc->pipe);
3464}
3465
3f8dce3a
DV		 3466static void ironlake_pfit_disable(struct intel_crtc *crtc)
3467{
3468 struct drm_device *dev = crtc->base.dev;
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 int pipe = crtc->pipe;
3471
3472 /* To avoid upsetting the power well on haswell only disable the pfit if
3473 * it's in use. The hw state code will make sure we get this right. */
3474 if (crtc->config.pch_pfit.size) {
3475 I915_WRITE(PF_CTL(pipe), 0);
3476 I915_WRITE(PF_WIN_POS(pipe), 0);
3477 I915_WRITE(PF_WIN_SZ(pipe), 0);
3478 }
3479}
3480
6be4a607
JB		 3481static void ironlake_crtc_disable(struct drm_crtc *crtc)
3482{
3483 struct drm_device *dev = crtc->dev;
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3486 struct intel_encoder *encoder;
6be4a607
JB		 3487 int pipe = intel_crtc->pipe;
3488 int plane = intel_crtc->plane;
5eddb70b 3489 u32 reg, temp;
b52eb4dc 3490
ef9c3aee 3491
f7abfe8b
CW		 3492 if (!intel_crtc->active)
3493 return;
3494
ea9d758d
DV		 3495 for_each_encoder_on_crtc(dev, crtc, encoder)
3496 encoder->disable(encoder);
3497
e6c3a2a6 3498 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3499 drm_vblank_off(dev, pipe);
913d8d11 3500
5c3fe8b0 3501 if (dev_priv->fbc.plane == plane)
973d04f9 3502 intel_disable_fbc(dev);
2c07245f 3503
0d5b8c61 3504 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3505 intel_disable_planes(crtc);
0d5b8c61
VS		 3506 intel_disable_plane(dev_priv, plane, pipe);
3507
d925c59a
DV		 3508 if (intel_crtc->config.has_pch_encoder)
3509 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3510
b24e7179 3511 intel_disable_pipe(dev_priv, pipe);
32f9d658 3512
3f8dce3a 3513 ironlake_pfit_disable(intel_crtc);
2c07245f 3514
bf49ec8c
DV		 3515 for_each_encoder_on_crtc(dev, crtc, encoder)
3516 if (encoder->post_disable)
3517 encoder->post_disable(encoder);
2c07245f 3518
d925c59a
DV		 3519 if (intel_crtc->config.has_pch_encoder) {
3520 ironlake_fdi_disable(crtc);
913d8d11 3521
d925c59a
DV		 3522 ironlake_disable_pch_transcoder(dev_priv, pipe);
3523 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3524
d925c59a
DV		 3525 if (HAS_PCH_CPT(dev)) {
3526 /* disable TRANS_DP_CTL */
3527 reg = TRANS_DP_CTL(pipe);
3528 temp = I915_READ(reg);
3529 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3530 TRANS_DP_PORT_SEL_MASK);
3531 temp |= TRANS_DP_PORT_SEL_NONE;
3532 I915_WRITE(reg, temp);
3533
3534 /* disable DPLL_SEL */
3535 temp = I915_READ(PCH_DPLL_SEL);
11887397 3536 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3537 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3538 }
e3421a18 3539
d925c59a 3540 /* disable PCH DPLL */
e72f9fbf 3541 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3542
d925c59a
DV		 3543 ironlake_fdi_pll_disable(intel_crtc);
3544 }
6b383a7f 3545
f7abfe8b 3546 intel_crtc->active = false;
46ba614c 3547 intel_update_watermarks(crtc);
d1ebd816
BW		 3548
3549 mutex_lock(&dev->struct_mutex);
6b383a7f 3550 intel_update_fbc(dev);
d1ebd816 3551 mutex_unlock(&dev->struct_mutex);
6be4a607 3552}
1b3c7a47 3553
4f771f10 3554static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3555{
4f771f10
PZ		 3556 struct drm_device *dev = crtc->dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3559 struct intel_encoder *encoder;
3560 int pipe = intel_crtc->pipe;
3561 int plane = intel_crtc->plane;
3b117c8f 3562 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3563
4f771f10
PZ		 3564 if (!intel_crtc->active)
3565 return;
3566
8807e55b
JN		 3567 for_each_encoder_on_crtc(dev, crtc, encoder) {
3568 intel_opregion_notify_encoder(encoder, false);
4f771f10 3569 encoder->disable(encoder);
8807e55b 3570 }
4f771f10
PZ		 3571
3572 intel_crtc_wait_for_pending_flips(crtc);
3573 drm_vblank_off(dev, pipe);
4f771f10 3574
891348b2 3575 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3576 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3577 intel_disable_fbc(dev);
3578
42db64ef
PZ		 3579 hsw_disable_ips(intel_crtc);
3580
0d5b8c61 3581 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3582 intel_disable_planes(crtc);
891348b2
RV		 3583 intel_disable_plane(dev_priv, plane, pipe);
3584
8664281b
PZ		 3585 if (intel_crtc->config.has_pch_encoder)
3586 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3587 intel_disable_pipe(dev_priv, pipe);
3588
ad80a810 3589 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3590
3f8dce3a 3591 ironlake_pfit_disable(intel_crtc);
4f771f10 3592
1f544388 3593 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3594
3595 for_each_encoder_on_crtc(dev, crtc, encoder)
3596 if (encoder->post_disable)
3597 encoder->post_disable(encoder);
3598
88adfff1 3599 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3600 lpt_disable_pch_transcoder(dev_priv);
8664281b 3601 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3602 intel_ddi_fdi_disable(crtc);
83616634 3603 }
4f771f10
PZ		 3604
3605 intel_crtc->active = false;
46ba614c 3606 intel_update_watermarks(crtc);
4f771f10
PZ		 3607
3608 mutex_lock(&dev->struct_mutex);
3609 intel_update_fbc(dev);
3610 mutex_unlock(&dev->struct_mutex);
3611}
3612
ee7b9f93
JB		 3613static void ironlake_crtc_off(struct drm_crtc *crtc)
3614{
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3616 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3617}
3618
6441ab5f
PZ		 3619static void haswell_crtc_off(struct drm_crtc *crtc)
3620{
3621 intel_ddi_put_crtc_pll(crtc);
3622}
3623
02e792fb
DV		 3624static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3625{
02e792fb 3626 if (!enable && intel_crtc->overlay) {
23f09ce3 3627 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3628 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3629
23f09ce3 3630 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3631 dev_priv->mm.interruptible = false;
3632 (void) intel_overlay_switch_off(intel_crtc->overlay);
3633 dev_priv->mm.interruptible = true;
23f09ce3 3634 mutex_unlock(&dev->struct_mutex);
02e792fb 3635 }
02e792fb 3636
5dcdbcb0
CW		 3637 /* Let userspace switch the overlay on again. In most cases userspace
3638 * has to recompute where to put it anyway.
3639 */
02e792fb
DV		 3640}
3641
61bc95c1
EE		 3642/**
3643 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3644 * cursor plane briefly if not already running after enabling the display
3645 * plane.
3646 * This workaround avoids occasional blank screens when self refresh is
3647 * enabled.
3648 */
3649static void
3650g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3651{
3652 u32 cntl = I915_READ(CURCNTR(pipe));
3653
3654 if ((cntl & CURSOR_MODE) == 0) {
3655 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3656
3657 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3658 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3659 intel_wait_for_vblank(dev_priv->dev, pipe);
3660 I915_WRITE(CURCNTR(pipe), cntl);
3661 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3662 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3663 }
3664}
3665
2dd24552
JB		 3666static void i9xx_pfit_enable(struct intel_crtc *crtc)
3667{
3668 struct drm_device *dev = crtc->base.dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc_config *pipe_config = &crtc->config;
3671
328d8e82 3672 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3673 return;
3674
2dd24552 3675 /*
c0b03411
DV		 3676 * The panel fitter should only be adjusted whilst the pipe is disabled,
3677 * according to register description and PRM.
2dd24552 3678 */
c0b03411
DV		 3679 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3680 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3681
b074cec8
JB		 3682 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3683 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3684
3685 /* Border color in case we don't scale up to the full screen. Black by
3686 * default, change to something else for debugging. */
3687 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3688}
3689
89b667f8
JB		 3690static void valleyview_crtc_enable(struct drm_crtc *crtc)
3691{
3692 struct drm_device *dev = crtc->dev;
3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695 struct intel_encoder *encoder;
3696 int pipe = intel_crtc->pipe;
3697 int plane = intel_crtc->plane;
23538ef1 3698 bool is_dsi;
89b667f8
JB		 3699
3700 WARN_ON(!crtc->enabled);
3701
3702 if (intel_crtc->active)
3703 return;
3704
3705 intel_crtc->active = true;
89b667f8 3706
89b667f8
JB		 3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 if (encoder->pre_pll_enable)
3709 encoder->pre_pll_enable(encoder);
3710
23538ef1
JN		 3711 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3712
e9fd1c02
JN		 3713 if (!is_dsi)
3714 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3715
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->pre_enable)
3718 encoder->pre_enable(encoder);
3719
2dd24552
JB		 3720 i9xx_pfit_enable(intel_crtc);
3721
63cbb074
VS		 3722 intel_crtc_load_lut(crtc);
3723
f37fcc2a 3724 intel_update_watermarks(crtc);
23538ef1 3725 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3726 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3727 intel_enable_planes(crtc);
5c38d48c 3728 intel_crtc_update_cursor(crtc, true);
89b667f8 3729
89b667f8 3730 intel_update_fbc(dev);
5004945f
JN		 3731
3732 for_each_encoder_on_crtc(dev, crtc, encoder)
3733 encoder->enable(encoder);
89b667f8
JB		 3734}
3735
0b8765c6 3736static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3737{
3738 struct drm_device *dev = crtc->dev;
79e53945
JB		 3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3741 struct intel_encoder *encoder;
79e53945 3742 int pipe = intel_crtc->pipe;
80824003 3743 int plane = intel_crtc->plane;
79e53945 3744
08a48469
DV		 3745 WARN_ON(!crtc->enabled);
3746
f7abfe8b
CW		 3747 if (intel_crtc->active)
3748 return;
3749
3750 intel_crtc->active = true;
6b383a7f 3751
9d6d9f19
MK		 3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 if (encoder->pre_enable)
3754 encoder->pre_enable(encoder);
3755
f6736a1a
DV		 3756 i9xx_enable_pll(intel_crtc);
3757
2dd24552
JB		 3758 i9xx_pfit_enable(intel_crtc);
3759
63cbb074
VS		 3760 intel_crtc_load_lut(crtc);
3761
f37fcc2a 3762 intel_update_watermarks(crtc);
23538ef1 3763 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3764 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3765 intel_enable_planes(crtc);
22e407d7 3766 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3767 if (IS_G4X(dev))
3768 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3769 intel_crtc_update_cursor(crtc, true);
79e53945 3770
0b8765c6
JB		 3771 /* Give the overlay scaler a chance to enable if it's on this pipe */
3772 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3773
f440eb13 3774 intel_update_fbc(dev);
ef9c3aee 3775
fa5c73b1
DV		 3776 for_each_encoder_on_crtc(dev, crtc, encoder)
3777 encoder->enable(encoder);
0b8765c6 3778}
79e53945 3779
87476d63
DV		 3780static void i9xx_pfit_disable(struct intel_crtc *crtc)
3781{
3782 struct drm_device *dev = crtc->base.dev;
3783 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3784
328d8e82
DV		 3785 if (!crtc->config.gmch_pfit.control)
3786 return;
87476d63 3787
328d8e82 3788 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3789
328d8e82
DV		 3790 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3791 I915_READ(PFIT_CONTROL));
3792 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3793}
3794
0b8765c6
JB		 3795static void i9xx_crtc_disable(struct drm_crtc *crtc)
3796{
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3800 struct intel_encoder *encoder;
0b8765c6
JB		 3801 int pipe = intel_crtc->pipe;
3802 int plane = intel_crtc->plane;
ef9c3aee 3803
f7abfe8b
CW		 3804 if (!intel_crtc->active)
3805 return;
3806
ea9d758d
DV		 3807 for_each_encoder_on_crtc(dev, crtc, encoder)
3808 encoder->disable(encoder);
3809
0b8765c6 3810 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3811 intel_crtc_wait_for_pending_flips(crtc);
3812 drm_vblank_off(dev, pipe);
0b8765c6 3813
5c3fe8b0 3814 if (dev_priv->fbc.plane == plane)
973d04f9 3815 intel_disable_fbc(dev);
79e53945 3816
0d5b8c61
VS		 3817 intel_crtc_dpms_overlay(intel_crtc, false);
3818 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3819 intel_disable_planes(crtc);
b24e7179 3820 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3821
b24e7179 3822 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3823
87476d63 3824 i9xx_pfit_disable(intel_crtc);
24a1f16d 3825
89b667f8
JB		 3826 for_each_encoder_on_crtc(dev, crtc, encoder)
3827 if (encoder->post_disable)
3828 encoder->post_disable(encoder);
3829
e9fd1c02
JN		 3830 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3831 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3832
f7abfe8b 3833 intel_crtc->active = false;
46ba614c 3834 intel_update_watermarks(crtc);
f37fcc2a
VS		 3835
3836 intel_update_fbc(dev);
0b8765c6
JB		 3837}
3838
ee7b9f93
JB		 3839static void i9xx_crtc_off(struct drm_crtc *crtc)
3840{
3841}
3842
976f8a20
DV		 3843static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3844 bool enabled)
2c07245f
ZW		 3845{
3846 struct drm_device *dev = crtc->dev;
3847 struct drm_i915_master_private *master_priv;
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849 int pipe = intel_crtc->pipe;
79e53945
JB		 3850
3851 if (!dev->primary->master)
3852 return;
3853
3854 master_priv = dev->primary->master->driver_priv;
3855 if (!master_priv->sarea_priv)
3856 return;
3857
79e53945
JB		 3858 switch (pipe) {
3859 case 0:
3860 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3861 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3862 break;
3863 case 1:
3864 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3865 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3866 break;
3867 default:
9db4a9c7 3868 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3869 break;
3870 }
79e53945
JB		 3871}
3872
976f8a20
DV		 3873/**
3874 * Sets the power management mode of the pipe and plane.
3875 */
3876void intel_crtc_update_dpms(struct drm_crtc *crtc)
3877{
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct intel_encoder *intel_encoder;
3881 bool enable = false;
3882
3883 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3884 enable |= intel_encoder->connectors_active;
3885
3886 if (enable)
3887 dev_priv->display.crtc_enable(crtc);
3888 else
3889 dev_priv->display.crtc_disable(crtc);
3890
3891 intel_crtc_update_sarea(crtc, enable);
3892}
3893
cdd59983
CW		 3894static void intel_crtc_disable(struct drm_crtc *crtc)
3895{
cdd59983 3896 struct drm_device *dev = crtc->dev;
976f8a20 3897 struct drm_connector *connector;
ee7b9f93 3898 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3900
976f8a20
DV		 3901 /* crtc should still be enabled when we disable it. */
3902 WARN_ON(!crtc->enabled);
3903
3904 dev_priv->display.crtc_disable(crtc);
c77bf565 3905 intel_crtc->eld_vld = false;
976f8a20 3906 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3907 dev_priv->display.off(crtc);
3908
931872fc 3909 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3910 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3911 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3912
3913 if (crtc->fb) {
3914 mutex_lock(&dev->struct_mutex);
1690e1eb 3915 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3916 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3917 crtc->fb = NULL;
3918 }
3919
3920 /* Update computed state. */
3921 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3922 if (!connector->encoder || !connector->encoder->crtc)
3923 continue;
3924
3925 if (connector->encoder->crtc != crtc)
3926 continue;
3927
3928 connector->dpms = DRM_MODE_DPMS_OFF;
3929 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3930 }
3931}
3932
ea5b213a 3933void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3934{
4ef69c7a 3935 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3936
ea5b213a
CW		 3937 drm_encoder_cleanup(encoder);
3938 kfree(intel_encoder);
7e7d76c3
JB		 3939}
3940
9237329d 3941/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3942 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3943 * state of the entire output pipe. */
9237329d 3944static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3945{
5ab432ef
DV		 3946 if (mode == DRM_MODE_DPMS_ON) {
3947 encoder->connectors_active = true;
3948
b2cabb0e 3949 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3950 } else {
3951 encoder->connectors_active = false;
3952
b2cabb0e 3953 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3954 }
79e53945
JB		 3955}
3956
0a91ca29
DV		 3957/* Cross check the actual hw state with our own modeset state tracking (and it's
3958 * internal consistency). */
b980514c 3959static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3960{
0a91ca29
DV		 3961 if (connector->get_hw_state(connector)) {
3962 struct intel_encoder *encoder = connector->encoder;
3963 struct drm_crtc *crtc;
3964 bool encoder_enabled;
3965 enum pipe pipe;
3966
3967 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3968 connector->base.base.id,
3969 drm_get_connector_name(&connector->base));
3970
3971 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3972 "wrong connector dpms state\n");
3973 WARN(connector->base.encoder != &encoder->base,
3974 "active connector not linked to encoder\n");
3975 WARN(!encoder->connectors_active,
3976 "encoder->connectors_active not set\n");
3977
3978 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3979 WARN(!encoder_enabled, "encoder not enabled\n");
3980 if (WARN_ON(!encoder->base.crtc))
3981 return;
3982
3983 crtc = encoder->base.crtc;
3984
3985 WARN(!crtc->enabled, "crtc not enabled\n");
3986 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3987 WARN(pipe != to_intel_crtc(crtc)->pipe,
3988 "encoder active on the wrong pipe\n");
3989 }
79e53945
JB		 3990}
3991
5ab432ef
DV		 3992/* Even simpler default implementation, if there's really no special case to
3993 * consider. */
3994void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3995{
5ab432ef 3996 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3997
5ab432ef
DV		 3998 /* All the simple cases only support two dpms states. */
3999 if (mode != DRM_MODE_DPMS_ON)
4000 mode = DRM_MODE_DPMS_OFF;
d4270e57 4001
5ab432ef
DV		 4002 if (mode == connector->dpms)
4003 return;
4004
4005 connector->dpms = mode;
4006
4007 /* Only need to change hw state when actually enabled */
4008 if (encoder->base.crtc)
4009 intel_encoder_dpms(encoder, mode);
4010 else
8af6cf88 4011 WARN_ON(encoder->connectors_active != false);
0a91ca29 4012
b980514c 4013 intel_modeset_check_state(connector->dev);
79e53945
JB		 4014}
4015
f0947c37
DV		 4016/* Simple connector->get_hw_state implementation for encoders that support only
4017 * one connector and no cloning and hence the encoder state determines the state
4018 * of the connector. */
4019bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4020{
24929352 4021 enum pipe pipe = 0;
f0947c37 4022 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4023
f0947c37 4024 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4025}
4026
1857e1da
DV		 4027static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4028 struct intel_crtc_config *pipe_config)
4029{
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 struct intel_crtc *pipe_B_crtc =
4032 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4033
4034 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4035 pipe_name(pipe), pipe_config->fdi_lanes);
4036 if (pipe_config->fdi_lanes > 4) {
4037 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4038 pipe_name(pipe), pipe_config->fdi_lanes);
4039 return false;
4040 }
4041
4042 if (IS_HASWELL(dev)) {
4043 if (pipe_config->fdi_lanes > 2) {
4044 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4045 pipe_config->fdi_lanes);
4046 return false;
4047 } else {
4048 return true;
4049 }
4050 }
4051
4052 if (INTEL_INFO(dev)->num_pipes == 2)
4053 return true;
4054
4055 /* Ivybridge 3 pipe is really complicated */
4056 switch (pipe) {
4057 case PIPE_A:
4058 return true;
4059 case PIPE_B:
4060 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4061 pipe_config->fdi_lanes > 2) {
4062 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4063 pipe_name(pipe), pipe_config->fdi_lanes);
4064 return false;
4065 }
4066 return true;
4067 case PIPE_C:
1e833f40 4068 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4069 pipe_B_crtc->config.fdi_lanes <= 2) {
4070 if (pipe_config->fdi_lanes > 2) {
4071 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4072 pipe_name(pipe), pipe_config->fdi_lanes);
4073 return false;
4074 }
4075 } else {
4076 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4077 return false;
4078 }
4079 return true;
4080 default:
4081 BUG();
4082 }
4083}
4084
e29c22c0
DV		 4085#define RETRY 1
4086static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4087 struct intel_crtc_config *pipe_config)
877d48d5 4088{
1857e1da 4089 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4090 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4091 int lane, link_bw, fdi_dotclock;
e29c22c0 4092 bool setup_ok, needs_recompute = false;
877d48d5 4093
e29c22c0 4094retry:
877d48d5
DV		 4095 /* FDI is a binary signal running at ~2.7GHz, encoding
4096 * each output octet as 10 bits. The actual frequency
4097 * is stored as a divider into a 100MHz clock, and the
4098 * mode pixel clock is stored in units of 1KHz.
4099 * Hence the bw of each lane in terms of the mode signal
4100 * is:
4101 */
4102 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4103
ff9a6750 4104 fdi_dotclock = adjusted_mode->clock;
877d48d5 4105
2bd89a07 4106 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4107 pipe_config->pipe_bpp);
4108
4109 pipe_config->fdi_lanes = lane;
4110
2bd89a07 4111 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4112 link_bw, &pipe_config->fdi_m_n);
1857e1da 4113
e29c22c0
DV		 4114 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4115 intel_crtc->pipe, pipe_config);
4116 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4117 pipe_config->pipe_bpp -= 2*3;
4118 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4119 pipe_config->pipe_bpp);
4120 needs_recompute = true;
4121 pipe_config->bw_constrained = true;
4122
4123 goto retry;
4124 }
4125
4126 if (needs_recompute)
4127 return RETRY;
4128
4129 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4130}
4131
42db64ef
PZ		 4132static void hsw_compute_ips_config(struct intel_crtc *crtc,
4133 struct intel_crtc_config *pipe_config)
4134{
3c4ca58c
PZ		 4135 pipe_config->ips_enabled = i915_enable_ips &&
4136 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4137 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4138}
4139
a43f6e0f 4140static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4141 struct intel_crtc_config *pipe_config)
79e53945 4142{
a43f6e0f 4143 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4144 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4145
cf532bb2
VS		 4146 if (INTEL_INFO(dev)->gen < 4) {
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int clock_limit =
4149 dev_priv->display.get_display_clock_speed(dev);
4150
4151 /*
4152 * Enable pixel doubling when the dot clock
4153 * is > 90% of the (display) core speed.
4154 *
4155 * XXX: No double-wide on 915GM pipe B. Is that
4156 * the only reason for the pipe == PIPE_A check?
4157 */
4158 if (crtc->pipe == PIPE_A &&
4159 adjusted_mode->clock > clock_limit * 9 / 10)
4160 pipe_config->double_wide = true;
4161 }
4162
8693a824
DL		 4163 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4164 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4165 */
4166 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4167 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4168 return -EINVAL;
44f46b42 4169
bd080ee5 4170 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4171 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4172 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4173 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4174 * for lvds. */
4175 pipe_config->pipe_bpp = 8*3;
4176 }
4177
f5adf94e 4178 if (HAS_IPS(dev))
a43f6e0f
DV		 4179 hsw_compute_ips_config(crtc, pipe_config);
4180
4181 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4182 * clock survives for now. */
4183 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4184 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4185
877d48d5 4186 if (pipe_config->has_pch_encoder)
a43f6e0f 4187 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4188
e29c22c0 4189 return 0;
79e53945
JB		 4190}
4191
25eb05fc
JB		 4192static int valleyview_get_display_clock_speed(struct drm_device *dev)
4193{
4194 return 400000; /* FIXME */
4195}
4196
e70236a8
JB		 4197static int i945_get_display_clock_speed(struct drm_device *dev)
4198{
4199 return 400000;
4200}
79e53945 4201
e70236a8 4202static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4203{
e70236a8
JB		 4204 return 333000;
4205}
79e53945 4206
e70236a8
JB		 4207static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4208{
4209 return 200000;
4210}
79e53945 4211
257a7ffc
DV		 4212static int pnv_get_display_clock_speed(struct drm_device *dev)
4213{
4214 u16 gcfgc = 0;
4215
4216 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4217
4218 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4219 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4220 return 267000;
4221 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4222 return 333000;
4223 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4224 return 444000;
4225 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4226 return 200000;
4227 default:
4228 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4229 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4230 return 133000;
4231 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4232 return 167000;
4233 }
4234}
4235
e70236a8
JB		 4236static int i915gm_get_display_clock_speed(struct drm_device *dev)
4237{
4238 u16 gcfgc = 0;
79e53945 4239
e70236a8
JB		 4240 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4241
4242 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4243 return 133000;
4244 else {
4245 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4246 case GC_DISPLAY_CLOCK_333_MHZ:
4247 return 333000;
4248 default:
4249 case GC_DISPLAY_CLOCK_190_200_MHZ:
4250 return 190000;
79e53945 4251 }
e70236a8
JB		 4252 }
4253}
4254
4255static int i865_get_display_clock_speed(struct drm_device *dev)
4256{
4257 return 266000;
4258}
4259
4260static int i855_get_display_clock_speed(struct drm_device *dev)
4261{
4262 u16 hpllcc = 0;
4263 /* Assume that the hardware is in the high speed state. This
4264 * should be the default.
4265 */
4266 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4267 case GC_CLOCK_133_200:
4268 case GC_CLOCK_100_200:
4269 return 200000;
4270 case GC_CLOCK_166_250:
4271 return 250000;
4272 case GC_CLOCK_100_133:
79e53945 4273 return 133000;
e70236a8 4274 }
79e53945 4275
e70236a8
JB		 4276 /* Shouldn't happen */
4277 return 0;
4278}
79e53945 4279
e70236a8
JB		 4280static int i830_get_display_clock_speed(struct drm_device *dev)
4281{
4282 return 133000;
79e53945
JB		 4283}
4284
2c07245f 4285static void
a65851af 4286intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4287{
a65851af
VS		 4288 while (*num > DATA_LINK_M_N_MASK ||
4289 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4290 *num >>= 1;
4291 *den >>= 1;
4292 }
4293}
4294
a65851af
VS		 4295static void compute_m_n(unsigned int m, unsigned int n,
4296 uint32_t *ret_m, uint32_t *ret_n)
4297{
4298 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4299 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4300 intel_reduce_m_n_ratio(ret_m, ret_n);
4301}
4302
e69d0bc1
DV		 4303void
4304intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4305 int pixel_clock, int link_clock,
4306 struct intel_link_m_n *m_n)
2c07245f 4307{
e69d0bc1 4308 m_n->tu = 64;
a65851af
VS		 4309
4310 compute_m_n(bits_per_pixel * pixel_clock,
4311 link_clock * nlanes * 8,
4312 &m_n->gmch_m, &m_n->gmch_n);
4313
4314 compute_m_n(pixel_clock, link_clock,
4315 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4316}
4317
a7615030
CW		 4318static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4319{
72bbe58c
KP		 4320 if (i915_panel_use_ssc >= 0)
4321 return i915_panel_use_ssc != 0;
41aa3448 4322 return dev_priv->vbt.lvds_use_ssc
435793df 4323 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4324}
4325
c65d77d8
JB		 4326static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4327{
4328 struct drm_device *dev = crtc->dev;
4329 struct drm_i915_private *dev_priv = dev->dev_private;
4330 int refclk;
4331
a0c4da24 4332 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4333 refclk = 100000;
a0c4da24 4334 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4335 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4336 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4337 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4338 refclk / 1000);
4339 } else if (!IS_GEN2(dev)) {
4340 refclk = 96000;
4341 } else {
4342 refclk = 48000;
4343 }
4344
4345 return refclk;
4346}
4347
7429e9d4 4348static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4349{
7df00d7a 4350 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4351}
f47709a9 4352
7429e9d4
DV		 4353static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4354{
4355 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4356}
4357
f47709a9 4358static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4359 intel_clock_t *reduced_clock)
4360{
f47709a9 4361 struct drm_device *dev = crtc->base.dev;
a7516a05 4362 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4363 int pipe = crtc->pipe;
a7516a05
JB		 4364 u32 fp, fp2 = 0;
4365
4366 if (IS_PINEVIEW(dev)) {
7429e9d4 4367 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4368 if (reduced_clock)
7429e9d4 4369 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4370 } else {
7429e9d4 4371 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4372 if (reduced_clock)
7429e9d4 4373 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4374 }
4375
4376 I915_WRITE(FP0(pipe), fp);
8bcc2795 4377 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4378
f47709a9
DV		 4379 crtc->lowfreq_avail = false;
4380 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4381 reduced_clock && i915_powersave) {
4382 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4383 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4384 crtc->lowfreq_avail = true;
a7516a05
JB		 4385 } else {
4386 I915_WRITE(FP1(pipe), fp);
8bcc2795 4387 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4388 }
4389}
4390
5e69f97f
CML		 4391static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4392 pipe)
89b667f8
JB		 4393{
4394 u32 reg_val;
4395
4396 /*
4397 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4398 * and set it to a reasonable value instead.
4399 */
5e69f97f 4400 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4401 reg_val &= 0xffffff00;
4402 reg_val |= 0x00000030;
5e69f97f 4403 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4404
5e69f97f 4405 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4406 reg_val &= 0x8cffffff;
4407 reg_val = 0x8c000000;
5e69f97f 4408 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4409
5e69f97f 4410 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4411 reg_val &= 0xffffff00;
5e69f97f 4412 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4413
5e69f97f 4414 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4415 reg_val &= 0x00ffffff;
4416 reg_val |= 0xb0000000;
5e69f97f 4417 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4418}
4419
b551842d
DV		 4420static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4421 struct intel_link_m_n *m_n)
4422{
4423 struct drm_device *dev = crtc->base.dev;
4424 struct drm_i915_private *dev_priv = dev->dev_private;
4425 int pipe = crtc->pipe;
4426
e3b95f1e
DV		 4427 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4428 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4429 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4430 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4431}
4432
4433static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4434 struct intel_link_m_n *m_n)
4435{
4436 struct drm_device *dev = crtc->base.dev;
4437 struct drm_i915_private *dev_priv = dev->dev_private;
4438 int pipe = crtc->pipe;
4439 enum transcoder transcoder = crtc->config.cpu_transcoder;
4440
4441 if (INTEL_INFO(dev)->gen >= 5) {
4442 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4443 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4444 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4445 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4446 } else {
e3b95f1e
DV		 4447 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4448 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4449 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4450 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4451 }
4452}
4453
03afc4a2
DV		 4454static void intel_dp_set_m_n(struct intel_crtc *crtc)
4455{
4456 if (crtc->config.has_pch_encoder)
4457 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4458 else
4459 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4460}
4461
f47709a9 4462static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4463{
f47709a9 4464 struct drm_device *dev = crtc->base.dev;
a0c4da24 4465 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4466 int pipe = crtc->pipe;
89b667f8 4467 u32 dpll, mdiv;
a0c4da24 4468 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4469 u32 coreclk, reg_val, dpll_md;
a0c4da24 4470
09153000
DV		 4471 mutex_lock(&dev_priv->dpio_lock);
4472
f47709a9
DV		 4473 bestn = crtc->config.dpll.n;
4474 bestm1 = crtc->config.dpll.m1;
4475 bestm2 = crtc->config.dpll.m2;
4476 bestp1 = crtc->config.dpll.p1;
4477 bestp2 = crtc->config.dpll.p2;
a0c4da24 4478
89b667f8
JB		 4479 /* See eDP HDMI DPIO driver vbios notes doc */
4480
4481 /* PLL B needs special handling */
4482 if (pipe)
5e69f97f 4483 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4484
4485 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4486 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4487
4488 /* Disable target IRef on PLL */
5e69f97f 4489 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4490 reg_val &= 0x00ffffff;
5e69f97f 4491 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4492
4493 /* Disable fast lock */
5e69f97f 4494 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4495
4496 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4497 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4498 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4499 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4500 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4501
4502 /*
4503 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4504 * but we don't support that).
4505 * Note: don't use the DAC post divider as it seems unstable.
4506 */
4507 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4508 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4509
a0c4da24 4510 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4511 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4512
89b667f8 4513 /* Set HBR and RBR LPF coefficients */
ff9a6750 4514 if (crtc->config.port_clock == 162000 ||
99750bd4 4515 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4516 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4517 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4518 0x009f0003);
89b667f8 4519 else
5e69f97f 4520 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4521 0x00d0000f);
4522
4523 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4524 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4525 /* Use SSC source */
4526 if (!pipe)
5e69f97f 4527 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4528 0x0df40000);
4529 else
5e69f97f 4530 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4531 0x0df70000);
4532 } else { /* HDMI or VGA */
4533 /* Use bend source */
4534 if (!pipe)
5e69f97f 4535 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4536 0x0df70000);
4537 else
5e69f97f 4538 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4539 0x0df40000);
4540 }
a0c4da24 4541
5e69f97f 4542 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4543 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4544 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4545 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4546 coreclk |= 0x01000000;
5e69f97f 4547 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4548
5e69f97f 4549 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4550
89b667f8
JB		 4551 /* Enable DPIO clock input */
4552 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4553 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4554 if (pipe)
4555 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4556
4557 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4558 crtc->config.dpll_hw_state.dpll = dpll;
4559
ef1b460d
DV		 4560 dpll_md = (crtc->config.pixel_multiplier - 1)
4561 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4562 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4563
89b667f8
JB		 4564 if (crtc->config.has_dp_encoder)
4565 intel_dp_set_m_n(crtc);
09153000
DV		 4566
4567 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4568}
4569
f47709a9
DV		 4570static void i9xx_update_pll(struct intel_crtc *crtc,
4571 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4572 int num_connectors)
4573{
f47709a9 4574 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4575 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4576 u32 dpll;
4577 bool is_sdvo;
f47709a9 4578 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4579
f47709a9 4580 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4581
f47709a9
DV		 4582 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4583 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4584
4585 dpll = DPLL_VGA_MODE_DIS;
4586
f47709a9 4587 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4588 dpll |= DPLLB_MODE_LVDS;
4589 else
4590 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4591
ef1b460d 4592 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4593 dpll |= (crtc->config.pixel_multiplier - 1)
4594 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4595 }
198a037f
DV		 4596
4597 if (is_sdvo)
4a33e48d 4598 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4599
f47709a9 4600 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4601 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4602
4603 /* compute bitmask from p1 value */
4604 if (IS_PINEVIEW(dev))
4605 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4606 else {
4607 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4608 if (IS_G4X(dev) && reduced_clock)
4609 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4610 }
4611 switch (clock->p2) {
4612 case 5:
4613 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4614 break;
4615 case 7:
4616 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4617 break;
4618 case 10:
4619 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4620 break;
4621 case 14:
4622 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4623 break;
4624 }
4625 if (INTEL_INFO(dev)->gen >= 4)
4626 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4627
09ede541 4628 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4629 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4630 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4631 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4632 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4633 else
4634 dpll |= PLL_REF_INPUT_DREFCLK;
4635
4636 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4637 crtc->config.dpll_hw_state.dpll = dpll;
4638
eb1cbe48 4639 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4640 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4641 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4642 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4643 }
66e3d5c0
DV		 4644
4645 if (crtc->config.has_dp_encoder)
4646 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4647}
4648
f47709a9 4649static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4650 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4651 int num_connectors)
4652{
f47709a9 4653 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4654 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4655 u32 dpll;
f47709a9 4656 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4657
f47709a9 4658 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4659
eb1cbe48
DV		 4660 dpll = DPLL_VGA_MODE_DIS;
4661
f47709a9 4662 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4663 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4664 } else {
4665 if (clock->p1 == 2)
4666 dpll |= PLL_P1_DIVIDE_BY_TWO;
4667 else
4668 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4669 if (clock->p2 == 4)
4670 dpll |= PLL_P2_DIVIDE_BY_4;
4671 }
4672
4a33e48d
DV		 4673 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4674 dpll |= DPLL_DVO_2X_MODE;
4675
f47709a9 4676 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4677 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4678 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4679 else
4680 dpll |= PLL_REF_INPUT_DREFCLK;
4681
4682 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4683 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4684}
4685
8a654f3b 4686static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4687{
4688 struct drm_device *dev = intel_crtc->base.dev;
4689 struct drm_i915_private *dev_priv = dev->dev_private;
4690 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4691 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4692 struct drm_display_mode *adjusted_mode =
4693 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4694 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4695
4696 /* We need to be careful not to changed the adjusted mode, for otherwise
4697 * the hw state checker will get angry at the mismatch. */
4698 crtc_vtotal = adjusted_mode->crtc_vtotal;
4699 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4700
4701 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4702 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4703 crtc_vtotal -= 1;
4704 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4705 vsyncshift = adjusted_mode->crtc_hsync_start
4706 - adjusted_mode->crtc_htotal / 2;
4707 } else {
4708 vsyncshift = 0;
4709 }
4710
4711 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4712 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4713
fe2b8f9d 4714 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4715 (adjusted_mode->crtc_hdisplay - 1) |
4716 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4717 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4718 (adjusted_mode->crtc_hblank_start - 1) |
4719 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4720 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4721 (adjusted_mode->crtc_hsync_start - 1) |
4722 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4723
fe2b8f9d 4724 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4725 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4726 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4727 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4728 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4729 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4730 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4731 (adjusted_mode->crtc_vsync_start - 1) |
4732 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4733
b5e508d4
PZ		 4734 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4735 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4736 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4737 * bits. */
4738 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4739 (pipe == PIPE_B || pipe == PIPE_C))
4740 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4741
b0e77b9c
PZ		 4742 /* pipesrc controls the size that is scaled from, which should
4743 * always be the user's requested size.
4744 */
4745 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4746 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4747 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4748}
4749
1bd1bd80
DV		 4750static void intel_get_pipe_timings(struct intel_crtc *crtc,
4751 struct intel_crtc_config *pipe_config)
4752{
4753 struct drm_device *dev = crtc->base.dev;
4754 struct drm_i915_private *dev_priv = dev->dev_private;
4755 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4756 uint32_t tmp;
4757
4758 tmp = I915_READ(HTOTAL(cpu_transcoder));
4759 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4760 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4761 tmp = I915_READ(HBLANK(cpu_transcoder));
4762 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4763 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4764 tmp = I915_READ(HSYNC(cpu_transcoder));
4765 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4766 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4767
4768 tmp = I915_READ(VTOTAL(cpu_transcoder));
4769 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4770 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4771 tmp = I915_READ(VBLANK(cpu_transcoder));
4772 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4773 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4774 tmp = I915_READ(VSYNC(cpu_transcoder));
4775 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4776 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4777
4778 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4779 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4780 pipe_config->adjusted_mode.crtc_vtotal += 1;
4781 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4782 }
4783
4784 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4785 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4786 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4787
4788 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4789 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4790}
4791
babea61d
JB		 4792static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4793 struct intel_crtc_config *pipe_config)
4794{
4795 struct drm_crtc *crtc = &intel_crtc->base;
4796
4797 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4798 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4799 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4800 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4801
4802 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4803 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4804 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4805 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4806
4807 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4808
4809 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4810 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4811}
4812
84b046f3
DV		 4813static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4814{
4815 struct drm_device *dev = intel_crtc->base.dev;
4816 struct drm_i915_private *dev_priv = dev->dev_private;
4817 uint32_t pipeconf;
4818
9f11a9e4 4819 pipeconf = 0;
84b046f3 4820
cf532bb2
VS		 4821 if (intel_crtc->config.double_wide)
4822 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4823
ff9ce46e
DV		 4824 /* only g4x and later have fancy bpc/dither controls */
4825 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4826 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4827 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4828 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4829 PIPECONF_DITHER_TYPE_SP;
84b046f3 4830
ff9ce46e
DV		 4831 switch (intel_crtc->config.pipe_bpp) {
4832 case 18:
4833 pipeconf |= PIPECONF_6BPC;
4834 break;
4835 case 24:
4836 pipeconf |= PIPECONF_8BPC;
4837 break;
4838 case 30:
4839 pipeconf |= PIPECONF_10BPC;
4840 break;
4841 default:
4842 /* Case prevented by intel_choose_pipe_bpp_dither. */
4843 BUG();
84b046f3
DV		 4844 }
4845 }
4846
4847 if (HAS_PIPE_CXSR(dev)) {
4848 if (intel_crtc->lowfreq_avail) {
4849 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4850 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4851 } else {
4852 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4853 }
4854 }
4855
84b046f3
DV		 4856 if (!IS_GEN2(dev) &&
4857 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4858 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4859 else
4860 pipeconf |= PIPECONF_PROGRESSIVE;
4861
9f11a9e4
DV		 4862 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4863 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4864
84b046f3
DV		 4865 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4866 POSTING_READ(PIPECONF(intel_crtc->pipe));
4867}
4868
f564048e 4869static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4870 int x, int y,
94352cf9 4871 struct drm_framebuffer *fb)
79e53945
JB		 4872{
4873 struct drm_device *dev = crtc->dev;
4874 struct drm_i915_private *dev_priv = dev->dev_private;
4875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4876 int pipe = intel_crtc->pipe;
80824003 4877 int plane = intel_crtc->plane;
c751ce4f 4878 int refclk, num_connectors = 0;
652c393a 4879 intel_clock_t clock, reduced_clock;
84b046f3 4880 u32 dspcntr;
a16af721 4881 bool ok, has_reduced_clock = false;
e9fd1c02 4882 bool is_lvds = false, is_dsi = false;
5eddb70b 4883 struct intel_encoder *encoder;
d4906093 4884 const intel_limit_t *limit;
5c3b82e2 4885 int ret;
79e53945 4886
6c2b7c12 4887 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4888 switch (encoder->type) {
79e53945
JB		 4889 case INTEL_OUTPUT_LVDS:
4890 is_lvds = true;
4891 break;
e9fd1c02
JN		 4892 case INTEL_OUTPUT_DSI:
4893 is_dsi = true;
4894 break;
79e53945 4895 }
43565a06 4896
c751ce4f 4897 num_connectors++;
79e53945
JB		 4898 }
4899
c65d77d8 4900 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4901
65ce4bf5 4902 if (!is_dsi && !intel_crtc->config.clock_set) {
e9fd1c02
JN		 4903 /*
4904 * Returns a set of divisors for the desired target clock with
4905 * the given refclk, or FALSE. The returned values represent
4906 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4907 * 2) / p1 / p2.
4908 */
4909 limit = intel_limit(crtc, refclk);
4910 ok = dev_priv->display.find_dpll(limit, crtc,
4911 intel_crtc->config.port_clock,
4912 refclk, NULL, &clock);
4913 if (!ok && !intel_crtc->config.clock_set) {
4914 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4915 return -EINVAL;
4916 }
79e53945
JB		 4917 }
4918
cda4b7d3 4919 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4920 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4921
e9fd1c02 4922 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4923 /*
4924 * Ensure we match the reduced clock's P to the target clock.
4925 * If the clocks don't match, we can't switch the display clock
4926 * by using the FP0/FP1. In such case we will disable the LVDS
4927 * downclock feature.
4928 */
65ce4bf5 4929 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4930 has_reduced_clock =
4931 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4932 dev_priv->lvds_downclock,
ee9300bb 4933 refclk, &clock,
5eddb70b 4934 &reduced_clock);
7026d4ac 4935 }
f47709a9
DV		 4936 /* Compat-code for transition, will disappear. */
4937 if (!intel_crtc->config.clock_set) {
4938 intel_crtc->config.dpll.n = clock.n;
4939 intel_crtc->config.dpll.m1 = clock.m1;
4940 intel_crtc->config.dpll.m2 = clock.m2;
4941 intel_crtc->config.dpll.p1 = clock.p1;
4942 intel_crtc->config.dpll.p2 = clock.p2;
4943 }
7026d4ac 4944
e9fd1c02 4945 if (IS_GEN2(dev)) {
8a654f3b 4946 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4947 has_reduced_clock ? &reduced_clock : NULL,
4948 num_connectors);
e9fd1c02
JN		 4949 } else if (IS_VALLEYVIEW(dev)) {
4950 if (!is_dsi)
4951 vlv_update_pll(intel_crtc);
4952 } else {
f47709a9 4953 i9xx_update_pll(intel_crtc,
eb1cbe48 4954 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4955 num_connectors);
e9fd1c02 4956 }
79e53945 4957
79e53945
JB		 4958 /* Set up the display plane register */
4959 dspcntr = DISPPLANE_GAMMA_ENABLE;
4960
da6ecc5d
JB		 4961 if (!IS_VALLEYVIEW(dev)) {
4962 if (pipe == 0)
4963 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4964 else
4965 dspcntr |= DISPPLANE_SEL_PIPE_B;
4966 }
79e53945 4967
8a654f3b 4968 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4969
4970 /* pipesrc and dspsize control the size that is scaled from,
4971 * which should always be the user's requested size.
79e53945 4972 */
929c77fb 4973 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 4974 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4975 (intel_crtc->config.pipe_src_w - 1));
929c77fb 4976 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4977
84b046f3
DV		 4978 i9xx_set_pipeconf(intel_crtc);
4979
f564048e
EA		 4980 I915_WRITE(DSPCNTR(plane), dspcntr);
4981 POSTING_READ(DSPCNTR(plane));
4982
94352cf9 4983 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 4984
f564048e
EA		 4985 return ret;
4986}
4987
2fa2fe9a
DV		 4988static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4989 struct intel_crtc_config *pipe_config)
4990{
4991 struct drm_device *dev = crtc->base.dev;
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 uint32_t tmp;
4994
4995 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4996 if (!(tmp & PFIT_ENABLE))
4997 return;
2fa2fe9a 4998
06922821 4999 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5000 if (INTEL_INFO(dev)->gen < 4) {
5001 if (crtc->pipe != PIPE_B)
5002 return;
2fa2fe9a
DV		 5003 } else {
5004 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5005 return;
5006 }
5007
06922821 5008 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5009 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5010 if (INTEL_INFO(dev)->gen < 5)
5011 pipe_config->gmch_pfit.lvds_border_bits =
5012 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5013}
5014
0e8ffe1b
DV		 5015static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5016 struct intel_crtc_config *pipe_config)
5017{
5018 struct drm_device *dev = crtc->base.dev;
5019 struct drm_i915_private *dev_priv = dev->dev_private;
5020 uint32_t tmp;
5021
e143a21c 5022 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5023 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5024
0e8ffe1b
DV		 5025 tmp = I915_READ(PIPECONF(crtc->pipe));
5026 if (!(tmp & PIPECONF_ENABLE))
5027 return false;
5028
42571aef
VS		 5029 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5030 switch (tmp & PIPECONF_BPC_MASK) {
5031 case PIPECONF_6BPC:
5032 pipe_config->pipe_bpp = 18;
5033 break;
5034 case PIPECONF_8BPC:
5035 pipe_config->pipe_bpp = 24;
5036 break;
5037 case PIPECONF_10BPC:
5038 pipe_config->pipe_bpp = 30;
5039 break;
5040 default:
5041 break;
5042 }
5043 }
5044
1bd1bd80
DV		 5045 intel_get_pipe_timings(crtc, pipe_config);
5046
2fa2fe9a
DV		 5047 i9xx_get_pfit_config(crtc, pipe_config);
5048
6c49f241
DV		 5049 if (INTEL_INFO(dev)->gen >= 4) {
5050 tmp = I915_READ(DPLL_MD(crtc->pipe));
5051 pipe_config->pixel_multiplier =
5052 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5053 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5054 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5055 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5056 tmp = I915_READ(DPLL(crtc->pipe));
5057 pipe_config->pixel_multiplier =
5058 ((tmp & SDVO_MULTIPLIER_MASK)
5059 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5060 } else {
5061 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5062 * port and will be fixed up in the encoder->get_config
5063 * function. */
5064 pipe_config->pixel_multiplier = 1;
5065 }
8bcc2795
DV		 5066 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5067 if (!IS_VALLEYVIEW(dev)) {
5068 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5069 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5070 } else {
5071 /* Mask out read-only status bits. */
5072 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5073 DPLL_PORTC_READY_MASK |
5074 DPLL_PORTB_READY_MASK);
8bcc2795 5075 }
6c49f241 5076
18442d08
VS		 5077 i9xx_crtc_clock_get(crtc, pipe_config);
5078
0e8ffe1b
DV		 5079 return true;
5080}
5081
dde86e2d 5082static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5083{
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5086 struct intel_encoder *encoder;
74cfd7ac 5087 u32 val, final;
13d83a67 5088 bool has_lvds = false;
199e5d79 5089 bool has_cpu_edp = false;
199e5d79 5090 bool has_panel = false;
99eb6a01
KP		 5091 bool has_ck505 = false;
5092 bool can_ssc = false;
13d83a67
JB		 5093
5094 /* We need to take the global config into account */
199e5d79
KP		 5095 list_for_each_entry(encoder, &mode_config->encoder_list,
5096 base.head) {
5097 switch (encoder->type) {
5098 case INTEL_OUTPUT_LVDS:
5099 has_panel = true;
5100 has_lvds = true;
5101 break;
5102 case INTEL_OUTPUT_EDP:
5103 has_panel = true;
2de6905f 5104 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5105 has_cpu_edp = true;
5106 break;
13d83a67
JB		 5107 }
5108 }
5109
99eb6a01 5110 if (HAS_PCH_IBX(dev)) {
41aa3448 5111 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5112 can_ssc = has_ck505;
5113 } else {
5114 has_ck505 = false;
5115 can_ssc = true;
5116 }
5117
2de6905f
ID		 5118 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5119 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5120
5121 /* Ironlake: try to setup display ref clock before DPLL
5122 * enabling. This is only under driver's control after
5123 * PCH B stepping, previous chipset stepping should be
5124 * ignoring this setting.
5125 */
74cfd7ac
CW		 5126 val = I915_READ(PCH_DREF_CONTROL);
5127
5128 /* As we must carefully and slowly disable/enable each source in turn,
5129 * compute the final state we want first and check if we need to
5130 * make any changes at all.
5131 */
5132 final = val;
5133 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5134 if (has_ck505)
5135 final |= DREF_NONSPREAD_CK505_ENABLE;
5136 else
5137 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5138
5139 final &= ~DREF_SSC_SOURCE_MASK;
5140 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5141 final &= ~DREF_SSC1_ENABLE;
5142
5143 if (has_panel) {
5144 final |= DREF_SSC_SOURCE_ENABLE;
5145
5146 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5147 final |= DREF_SSC1_ENABLE;
5148
5149 if (has_cpu_edp) {
5150 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5151 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5152 else
5153 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5154 } else
5155 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5156 } else {
5157 final |= DREF_SSC_SOURCE_DISABLE;
5158 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5159 }
5160
5161 if (final == val)
5162 return;
5163
13d83a67 5164 /* Always enable nonspread source */
74cfd7ac 5165 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5166
99eb6a01 5167 if (has_ck505)
74cfd7ac 5168 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5169 else
74cfd7ac 5170 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5171
199e5d79 5172 if (has_panel) {
74cfd7ac
CW		 5173 val &= ~DREF_SSC_SOURCE_MASK;
5174 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5175
199e5d79 5176 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5177 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5178 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5179 val |= DREF_SSC1_ENABLE;
e77166b5 5180 } else
74cfd7ac 5181 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5182
5183 /* Get SSC going before enabling the outputs */
74cfd7ac 5184 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5185 POSTING_READ(PCH_DREF_CONTROL);
5186 udelay(200);
5187
74cfd7ac 5188 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5189
5190 /* Enable CPU source on CPU attached eDP */
199e5d79 5191 if (has_cpu_edp) {
99eb6a01 5192 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5193 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5194 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5195 }
13d83a67 5196 else
74cfd7ac 5197 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5198 } else
74cfd7ac 5199 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5200
74cfd7ac 5201 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5202 POSTING_READ(PCH_DREF_CONTROL);
5203 udelay(200);
5204 } else {
5205 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5206
74cfd7ac 5207 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5208
5209 /* Turn off CPU output */
74cfd7ac 5210 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5211
74cfd7ac 5212 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5213 POSTING_READ(PCH_DREF_CONTROL);
5214 udelay(200);
5215
5216 /* Turn off the SSC source */
74cfd7ac
CW		 5217 val &= ~DREF_SSC_SOURCE_MASK;
5218 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5219
5220 /* Turn off SSC1 */
74cfd7ac 5221 val &= ~DREF_SSC1_ENABLE;
199e5d79 5222
74cfd7ac 5223 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5224 POSTING_READ(PCH_DREF_CONTROL);
5225 udelay(200);
5226 }
74cfd7ac
CW		 5227
5228 BUG_ON(val != final);
13d83a67
JB		 5229}
5230
f31f2d55 5231static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5232{
f31f2d55 5233 uint32_t tmp;
dde86e2d 5234
0ff066a9
PZ		 5235 tmp = I915_READ(SOUTH_CHICKEN2);
5236 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5237 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5238
0ff066a9
PZ		 5239 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5240 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5241 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5242
0ff066a9
PZ		 5243 tmp = I915_READ(SOUTH_CHICKEN2);
5244 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5245 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5246
0ff066a9
PZ		 5247 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5248 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5249 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5250}
5251
5252/* WaMPhyProgramming:hsw */
5253static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5254{
5255 uint32_t tmp;
dde86e2d
PZ		 5256
5257 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5258 tmp &= ~(0xFF << 24);
5259 tmp |= (0x12 << 24);
5260 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5261
dde86e2d
PZ		 5262 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5263 tmp |= (1 << 11);
5264 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5265
5266 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5267 tmp |= (1 << 11);
5268 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5269
dde86e2d
PZ		 5270 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5271 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5272 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5273
5274 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5275 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5276 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5277
0ff066a9
PZ		 5278 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5279 tmp &= ~(7 << 13);
5280 tmp |= (5 << 13);
5281 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5282
0ff066a9
PZ		 5283 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5284 tmp &= ~(7 << 13);
5285 tmp |= (5 << 13);
5286 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5287
5288 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5289 tmp &= ~0xFF;
5290 tmp |= 0x1C;
5291 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5292
5293 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5294 tmp &= ~0xFF;
5295 tmp |= 0x1C;
5296 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5297
5298 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5299 tmp &= ~(0xFF << 16);
5300 tmp |= (0x1C << 16);
5301 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5302
5303 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5304 tmp &= ~(0xFF << 16);
5305 tmp |= (0x1C << 16);
5306 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5307
0ff066a9
PZ		 5308 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5309 tmp |= (1 << 27);
5310 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5311
0ff066a9
PZ		 5312 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5313 tmp |= (1 << 27);
5314 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5315
0ff066a9
PZ		 5316 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5317 tmp &= ~(0xF << 28);
5318 tmp |= (4 << 28);
5319 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5320
0ff066a9
PZ		 5321 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5322 tmp &= ~(0xF << 28);
5323 tmp |= (4 << 28);
5324 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5325}
5326
2fa86a1f
PZ		 5327/* Implements 3 different sequences from BSpec chapter "Display iCLK
5328 * Programming" based on the parameters passed:
5329 * - Sequence to enable CLKOUT_DP
5330 * - Sequence to enable CLKOUT_DP without spread
5331 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5332 */
5333static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5334 bool with_fdi)
f31f2d55
PZ		 5335{
5336 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5337 uint32_t reg, tmp;
5338
5339 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5340 with_spread = true;
5341 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5342 with_fdi, "LP PCH doesn't have FDI\n"))
5343 with_fdi = false;
f31f2d55
PZ		 5344
5345 mutex_lock(&dev_priv->dpio_lock);
5346
5347 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5348 tmp &= ~SBI_SSCCTL_DISABLE;
5349 tmp |= SBI_SSCCTL_PATHALT;
5350 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5351
5352 udelay(24);
5353
2fa86a1f
PZ		 5354 if (with_spread) {
5355 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5356 tmp &= ~SBI_SSCCTL_PATHALT;
5357 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5358
2fa86a1f
PZ		 5359 if (with_fdi) {
5360 lpt_reset_fdi_mphy(dev_priv);
5361 lpt_program_fdi_mphy(dev_priv);
5362 }
5363 }
dde86e2d 5364
2fa86a1f
PZ		 5365 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5366 SBI_GEN0 : SBI_DBUFF0;
5367 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5368 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5369 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5370
5371 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5372}
5373
47701c3b
PZ		 5374/* Sequence to disable CLKOUT_DP */
5375static void lpt_disable_clkout_dp(struct drm_device *dev)
5376{
5377 struct drm_i915_private *dev_priv = dev->dev_private;
5378 uint32_t reg, tmp;
5379
5380 mutex_lock(&dev_priv->dpio_lock);
5381
5382 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5383 SBI_GEN0 : SBI_DBUFF0;
5384 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5385 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5386 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5387
5388 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5389 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5390 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5391 tmp |= SBI_SSCCTL_PATHALT;
5392 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5393 udelay(32);
5394 }
5395 tmp |= SBI_SSCCTL_DISABLE;
5396 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5397 }
5398
5399 mutex_unlock(&dev_priv->dpio_lock);
5400}
5401
bf8fa3d3
PZ		 5402static void lpt_init_pch_refclk(struct drm_device *dev)
5403{
5404 struct drm_mode_config *mode_config = &dev->mode_config;
5405 struct intel_encoder *encoder;
5406 bool has_vga = false;
5407
5408 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5409 switch (encoder->type) {
5410 case INTEL_OUTPUT_ANALOG:
5411 has_vga = true;
5412 break;
5413 }
5414 }
5415
47701c3b
PZ		 5416 if (has_vga)
5417 lpt_enable_clkout_dp(dev, true, true);
5418 else
5419 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5420}
5421
dde86e2d
PZ		 5422/*
5423 * Initialize reference clocks when the driver loads
5424 */
5425void intel_init_pch_refclk(struct drm_device *dev)
5426{
5427 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5428 ironlake_init_pch_refclk(dev);
5429 else if (HAS_PCH_LPT(dev))
5430 lpt_init_pch_refclk(dev);
5431}
5432
d9d444cb
JB		 5433static int ironlake_get_refclk(struct drm_crtc *crtc)
5434{
5435 struct drm_device *dev = crtc->dev;
5436 struct drm_i915_private *dev_priv = dev->dev_private;
5437 struct intel_encoder *encoder;
d9d444cb
JB		 5438 int num_connectors = 0;
5439 bool is_lvds = false;
5440
6c2b7c12 5441 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5442 switch (encoder->type) {
5443 case INTEL_OUTPUT_LVDS:
5444 is_lvds = true;
5445 break;
d9d444cb
JB		 5446 }
5447 num_connectors++;
5448 }
5449
5450 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5451 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5452 dev_priv->vbt.lvds_ssc_freq);
5453 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5454 }
5455
5456 return 120000;
5457}
5458
6ff93609 5459static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5460{
c8203565 5461 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5463 int pipe = intel_crtc->pipe;
c8203565
PZ		 5464 uint32_t val;
5465
78114071 5466 val = 0;
c8203565 5467
965e0c48 5468 switch (intel_crtc->config.pipe_bpp) {
c8203565 5469 case 18:
dfd07d72 5470 val |= PIPECONF_6BPC;
c8203565
PZ		 5471 break;
5472 case 24:
dfd07d72 5473 val |= PIPECONF_8BPC;
c8203565
PZ		 5474 break;
5475 case 30:
dfd07d72 5476 val |= PIPECONF_10BPC;
c8203565
PZ		 5477 break;
5478 case 36:
dfd07d72 5479 val |= PIPECONF_12BPC;
c8203565
PZ		 5480 break;
5481 default:
cc769b62
PZ		 5482 /* Case prevented by intel_choose_pipe_bpp_dither. */
5483 BUG();
c8203565
PZ		 5484 }
5485
d8b32247 5486 if (intel_crtc->config.dither)
c8203565
PZ		 5487 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5488
6ff93609 5489 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5490 val |= PIPECONF_INTERLACED_ILK;
5491 else
5492 val |= PIPECONF_PROGRESSIVE;
5493
50f3b016 5494 if (intel_crtc->config.limited_color_range)
3685a8f3 5495 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5496
c8203565
PZ		 5497 I915_WRITE(PIPECONF(pipe), val);
5498 POSTING_READ(PIPECONF(pipe));
5499}
5500
86d3efce
VS		 5501/*
5502 * Set up the pipe CSC unit.
5503 *
5504 * Currently only full range RGB to limited range RGB conversion
5505 * is supported, but eventually this should handle various
5506 * RGB<->YCbCr scenarios as well.
5507 */
50f3b016 5508static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5509{
5510 struct drm_device *dev = crtc->dev;
5511 struct drm_i915_private *dev_priv = dev->dev_private;
5512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5513 int pipe = intel_crtc->pipe;
5514 uint16_t coeff = 0x7800; /* 1.0 */
5515
5516 /*
5517 * TODO: Check what kind of values actually come out of the pipe
5518 * with these coeff/postoff values and adjust to get the best
5519 * accuracy. Perhaps we even need to take the bpc value into
5520 * consideration.
5521 */
5522
50f3b016 5523 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5524 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5525
5526 /*
5527 * GY/GU and RY/RU should be the other way around according
5528 * to BSpec, but reality doesn't agree. Just set them up in
5529 * a way that results in the correct picture.
5530 */
5531 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5532 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5533
5534 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5535 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5536
5537 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5538 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5539
5540 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5541 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5542 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5543
5544 if (INTEL_INFO(dev)->gen > 6) {
5545 uint16_t postoff = 0;
5546
50f3b016 5547 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5548 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5549
5550 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5551 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5552 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5553
5554 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5555 } else {
5556 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5557
50f3b016 5558 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5559 mode |= CSC_BLACK_SCREEN_OFFSET;
5560
5561 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5562 }
5563}
5564
6ff93609 5565static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5566{
5567 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5569 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5570 uint32_t val;
5571
3eff4faa 5572 val = 0;
ee2b0b38 5573
d8b32247 5574 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5575 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5576
6ff93609 5577 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5578 val |= PIPECONF_INTERLACED_ILK;
5579 else
5580 val |= PIPECONF_PROGRESSIVE;
5581
702e7a56
PZ		 5582 I915_WRITE(PIPECONF(cpu_transcoder), val);
5583 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5584
5585 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5586 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5587}
5588
6591c6e4 5589static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5590 intel_clock_t *clock,
5591 bool *has_reduced_clock,
5592 intel_clock_t *reduced_clock)
5593{
5594 struct drm_device *dev = crtc->dev;
5595 struct drm_i915_private *dev_priv = dev->dev_private;
5596 struct intel_encoder *intel_encoder;
5597 int refclk;
d4906093 5598 const intel_limit_t *limit;
a16af721 5599 bool ret, is_lvds = false;
79e53945 5600
6591c6e4
PZ		 5601 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5602 switch (intel_encoder->type) {
79e53945
JB		 5603 case INTEL_OUTPUT_LVDS:
5604 is_lvds = true;
5605 break;
79e53945
JB		 5606 }
5607 }
5608
d9d444cb 5609 refclk = ironlake_get_refclk(crtc);
79e53945 5610
d4906093
ML		 5611 /*
5612 * Returns a set of divisors for the desired target clock with the given
5613 * refclk, or FALSE. The returned values represent the clock equation:
5614 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5615 */
1b894b59 5616 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5617 ret = dev_priv->display.find_dpll(limit, crtc,
5618 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5619 refclk, NULL, clock);
6591c6e4
PZ		 5620 if (!ret)
5621 return false;
cda4b7d3 5622
ddc9003c 5623 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5624 /*
5625 * Ensure we match the reduced clock's P to the target clock.
5626 * If the clocks don't match, we can't switch the display clock
5627 * by using the FP0/FP1. In such case we will disable the LVDS
5628 * downclock feature.
5629 */
ee9300bb
DV		 5630 *has_reduced_clock =
5631 dev_priv->display.find_dpll(limit, crtc,
5632 dev_priv->lvds_downclock,
5633 refclk, clock,
5634 reduced_clock);
652c393a 5635 }
61e9653f 5636
6591c6e4
PZ		 5637 return true;
5638}
5639
01a415fd
DV		 5640static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5641{
5642 struct drm_i915_private *dev_priv = dev->dev_private;
5643 uint32_t temp;
5644
5645 temp = I915_READ(SOUTH_CHICKEN1);
5646 if (temp & FDI_BC_BIFURCATION_SELECT)
5647 return;
5648
5649 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5650 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5651
5652 temp |= FDI_BC_BIFURCATION_SELECT;
5653 DRM_DEBUG_KMS("enabling fdi C rx\n");
5654 I915_WRITE(SOUTH_CHICKEN1, temp);
5655 POSTING_READ(SOUTH_CHICKEN1);
5656}
5657
ebfd86fd 5658static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5659{
5660 struct drm_device *dev = intel_crtc->base.dev;
5661 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5662
5663 switch (intel_crtc->pipe) {
5664 case PIPE_A:
ebfd86fd 5665 break;
01a415fd 5666 case PIPE_B:
ebfd86fd 5667 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5668 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5669 else
5670 cpt_enable_fdi_bc_bifurcation(dev);
5671
ebfd86fd 5672 break;
01a415fd 5673 case PIPE_C:
01a415fd
DV		 5674 cpt_enable_fdi_bc_bifurcation(dev);
5675
ebfd86fd 5676 break;
01a415fd
DV		 5677 default:
5678 BUG();
5679 }
5680}
5681
d4b1931c
PZ		 5682int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5683{
5684 /*
5685 * Account for spread spectrum to avoid
5686 * oversubscribing the link. Max center spread
5687 * is 2.5%; use 5% for safety's sake.
5688 */
5689 u32 bps = target_clock * bpp * 21 / 20;
5690 return bps / (link_bw * 8) + 1;
5691}
5692
7429e9d4 5693static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5694{
7429e9d4 5695 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5696}
5697
de13a2e3 5698static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5699 u32 *fp,
9a7c7890 5700 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5701{
de13a2e3 5702 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5703 struct drm_device *dev = crtc->dev;
5704 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5705 struct intel_encoder *intel_encoder;
5706 uint32_t dpll;
6cc5f341 5707 int factor, num_connectors = 0;
09ede541 5708 bool is_lvds = false, is_sdvo = false;
79e53945 5709
de13a2e3
PZ		 5710 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5711 switch (intel_encoder->type) {
79e53945
JB		 5712 case INTEL_OUTPUT_LVDS:
5713 is_lvds = true;
5714 break;
5715 case INTEL_OUTPUT_SDVO:
7d57382e 5716 case INTEL_OUTPUT_HDMI:
79e53945 5717 is_sdvo = true;
79e53945 5718 break;
79e53945 5719 }
43565a06 5720
c751ce4f 5721 num_connectors++;
79e53945 5722 }
79e53945 5723
c1858123 5724 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5725 factor = 21;
5726 if (is_lvds) {
5727 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5728 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5729 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5730 factor = 25;
09ede541 5731 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5732 factor = 20;
c1858123 5733
7429e9d4 5734 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5735 *fp |= FP_CB_TUNE;
2c07245f 5736
9a7c7890
DV		 5737 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5738 *fp2 |= FP_CB_TUNE;
5739
5eddb70b 5740 dpll = 0;
2c07245f 5741
a07d6787
EA		 5742 if (is_lvds)
5743 dpll |= DPLLB_MODE_LVDS;
5744 else
5745 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5746
ef1b460d
DV		 5747 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5748 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5749
5750 if (is_sdvo)
4a33e48d 5751 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5752 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5753 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5754
a07d6787 5755 /* compute bitmask from p1 value */
7429e9d4 5756 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5757 /* also FPA1 */
7429e9d4 5758 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5759
7429e9d4 5760 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5761 case 5:
5762 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5763 break;
5764 case 7:
5765 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5766 break;
5767 case 10:
5768 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5769 break;
5770 case 14:
5771 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5772 break;
79e53945
JB		 5773 }
5774
b4c09f3b 5775 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5776 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5777 else
5778 dpll |= PLL_REF_INPUT_DREFCLK;
5779
959e16d6 5780 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5781}
5782
5783static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5784 int x, int y,
5785 struct drm_framebuffer *fb)
5786{
5787 struct drm_device *dev = crtc->dev;
5788 struct drm_i915_private *dev_priv = dev->dev_private;
5789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5790 int pipe = intel_crtc->pipe;
5791 int plane = intel_crtc->plane;
5792 int num_connectors = 0;
5793 intel_clock_t clock, reduced_clock;
cbbab5bd 5794 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5795 bool ok, has_reduced_clock = false;
8b47047b 5796 bool is_lvds = false;
de13a2e3 5797 struct intel_encoder *encoder;
e2b78267 5798 struct intel_shared_dpll *pll;
de13a2e3 5799 int ret;
de13a2e3
PZ		 5800
5801 for_each_encoder_on_crtc(dev, crtc, encoder) {
5802 switch (encoder->type) {
5803 case INTEL_OUTPUT_LVDS:
5804 is_lvds = true;
5805 break;
de13a2e3
PZ		 5806 }
5807
5808 num_connectors++;
a07d6787 5809 }
79e53945 5810
5dc5298b
PZ		 5811 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5812 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5813
ff9a6750 5814 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5815 &has_reduced_clock, &reduced_clock);
ee9300bb 5816 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5817 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5818 return -EINVAL;
79e53945 5819 }
f47709a9
DV		 5820 /* Compat-code for transition, will disappear. */
5821 if (!intel_crtc->config.clock_set) {
5822 intel_crtc->config.dpll.n = clock.n;
5823 intel_crtc->config.dpll.m1 = clock.m1;
5824 intel_crtc->config.dpll.m2 = clock.m2;
5825 intel_crtc->config.dpll.p1 = clock.p1;
5826 intel_crtc->config.dpll.p2 = clock.p2;
5827 }
79e53945 5828
de13a2e3
PZ		 5829 /* Ensure that the cursor is valid for the new mode before changing... */
5830 intel_crtc_update_cursor(crtc, true);
5831
5dc5298b 5832 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5833 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5834 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5835 if (has_reduced_clock)
7429e9d4 5836 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5837
7429e9d4 5838 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5839 &fp, &reduced_clock,
5840 has_reduced_clock ? &fp2 : NULL);
5841
959e16d6 5842 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5843 intel_crtc->config.dpll_hw_state.fp0 = fp;
5844 if (has_reduced_clock)
5845 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5846 else
5847 intel_crtc->config.dpll_hw_state.fp1 = fp;
5848
b89a1d39 5849 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5850 if (pll == NULL) {
84f44ce7
VS		 5851 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5852 pipe_name(pipe));
4b645f14
JB		 5853 return -EINVAL;
5854 }
ee7b9f93 5855 } else
e72f9fbf 5856 intel_put_shared_dpll(intel_crtc);
79e53945 5857
03afc4a2
DV		 5858 if (intel_crtc->config.has_dp_encoder)
5859 intel_dp_set_m_n(intel_crtc);
79e53945 5860
bcd644e0
DV		 5861 if (is_lvds && has_reduced_clock && i915_powersave)
5862 intel_crtc->lowfreq_avail = true;
5863 else
5864 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5865
5866 if (intel_crtc->config.has_pch_encoder) {
5867 pll = intel_crtc_to_shared_dpll(intel_crtc);
5868
652c393a
JB		 5869 }
5870
8a654f3b 5871 intel_set_pipe_timings(intel_crtc);
5eddb70b 5872
ca3a0ff8 5873 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5874 intel_cpu_transcoder_set_m_n(intel_crtc,
5875 &intel_crtc->config.fdi_m_n);
5876 }
2c07245f 5877
ebfd86fd
DV		 5878 if (IS_IVYBRIDGE(dev))
5879 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5880
6ff93609 5881 ironlake_set_pipeconf(crtc);
79e53945 5882
a1f9e77e
PZ		 5883 /* Set up the display plane register */
5884 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5885 POSTING_READ(DSPCNTR(plane));
79e53945 5886
94352cf9 5887 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5888
1857e1da 5889 return ret;
79e53945
JB		 5890}
5891
eb14cb74
VS		 5892static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5893 struct intel_link_m_n *m_n)
5894{
5895 struct drm_device *dev = crtc->base.dev;
5896 struct drm_i915_private *dev_priv = dev->dev_private;
5897 enum pipe pipe = crtc->pipe;
5898
5899 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5900 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5901 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5902 & ~TU_SIZE_MASK;
5903 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5904 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5905 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5906}
5907
5908static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5909 enum transcoder transcoder,
5910 struct intel_link_m_n *m_n)
72419203
DV		 5911{
5912 struct drm_device *dev = crtc->base.dev;
5913 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74
VS		 5914 enum pipe pipe = crtc->pipe;
5915
5916 if (INTEL_INFO(dev)->gen >= 5) {
5917 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5918 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5919 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5920 & ~TU_SIZE_MASK;
5921 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5922 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5923 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5924 } else {
5925 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5926 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5927 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5928 & ~TU_SIZE_MASK;
5929 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5930 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5931 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5932 }
5933}
5934
5935void intel_dp_get_m_n(struct intel_crtc *crtc,
5936 struct intel_crtc_config *pipe_config)
5937{
5938 if (crtc->config.has_pch_encoder)
5939 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5940 else
5941 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5942 &pipe_config->dp_m_n);
5943}
72419203 5944
eb14cb74
VS		 5945static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5946 struct intel_crtc_config *pipe_config)
5947{
5948 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5949 &pipe_config->fdi_m_n);
72419203
DV		 5950}
5951
2fa2fe9a
DV		 5952static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5953 struct intel_crtc_config *pipe_config)
5954{
5955 struct drm_device *dev = crtc->base.dev;
5956 struct drm_i915_private *dev_priv = dev->dev_private;
5957 uint32_t tmp;
5958
5959 tmp = I915_READ(PF_CTL(crtc->pipe));
5960
5961 if (tmp & PF_ENABLE) {
5962 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5963 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5964
5965 /* We currently do not free assignements of panel fitters on
5966 * ivb/hsw (since we don't use the higher upscaling modes which
5967 * differentiates them) so just WARN about this case for now. */
5968 if (IS_GEN7(dev)) {
5969 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5970 PF_PIPE_SEL_IVB(crtc->pipe));
5971 }
2fa2fe9a 5972 }
79e53945
JB		 5973}
5974
0e8ffe1b
DV		 5975static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5976 struct intel_crtc_config *pipe_config)
5977{
5978 struct drm_device *dev = crtc->base.dev;
5979 struct drm_i915_private *dev_priv = dev->dev_private;
5980 uint32_t tmp;
5981
e143a21c 5982 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5983 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5984
0e8ffe1b
DV		 5985 tmp = I915_READ(PIPECONF(crtc->pipe));
5986 if (!(tmp & PIPECONF_ENABLE))
5987 return false;
5988
42571aef
VS		 5989 switch (tmp & PIPECONF_BPC_MASK) {
5990 case PIPECONF_6BPC:
5991 pipe_config->pipe_bpp = 18;
5992 break;
5993 case PIPECONF_8BPC:
5994 pipe_config->pipe_bpp = 24;
5995 break;
5996 case PIPECONF_10BPC:
5997 pipe_config->pipe_bpp = 30;
5998 break;
5999 case PIPECONF_12BPC:
6000 pipe_config->pipe_bpp = 36;
6001 break;
6002 default:
6003 break;
6004 }
6005
ab9412ba 6006 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6007 struct intel_shared_dpll *pll;
6008
88adfff1
DV		 6009 pipe_config->has_pch_encoder = true;
6010
627eb5a3
DV		 6011 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6012 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6013 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6014
6015 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6016
c0d43d62 6017 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6018 pipe_config->shared_dpll =
6019 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6020 } else {
6021 tmp = I915_READ(PCH_DPLL_SEL);
6022 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6023 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6024 else
6025 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6026 }
66e985c0
DV		 6027
6028 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6029
6030 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6031 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6032
6033 tmp = pipe_config->dpll_hw_state.dpll;
6034 pipe_config->pixel_multiplier =
6035 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6036 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6037
6038 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6039 } else {
6040 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6041 }
6042
1bd1bd80
DV		 6043 intel_get_pipe_timings(crtc, pipe_config);
6044
2fa2fe9a
DV		 6045 ironlake_get_pfit_config(crtc, pipe_config);
6046
0e8ffe1b
DV		 6047 return true;
6048}
6049
be256dc7
PZ		 6050static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6051{
6052 struct drm_device *dev = dev_priv->dev;
6053 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6054 struct intel_crtc *crtc;
6055 unsigned long irqflags;
bd633a7c 6056 uint32_t val;
be256dc7
PZ		 6057
6058 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6059 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6060 pipe_name(crtc->pipe));
6061
6062 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6063 WARN(plls->spll_refcount, "SPLL enabled\n");
6064 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6065 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6066 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6067 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6068 "CPU PWM1 enabled\n");
6069 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6070 "CPU PWM2 enabled\n");
6071 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6072 "PCH PWM1 enabled\n");
6073 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6074 "Utility pin enabled\n");
6075 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6076
6077 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6078 val = I915_READ(DEIMR);
6079 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6080 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6081 val = I915_READ(SDEIMR);
bd633a7c 6082 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6083 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6084 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6085}
6086
6087/*
6088 * This function implements pieces of two sequences from BSpec:
6089 * - Sequence for display software to disable LCPLL
6090 * - Sequence for display software to allow package C8+
6091 * The steps implemented here are just the steps that actually touch the LCPLL
6092 * register. Callers should take care of disabling all the display engine
6093 * functions, doing the mode unset, fixing interrupts, etc.
6094 */
6095void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6096 bool switch_to_fclk, bool allow_power_down)
6097{
6098 uint32_t val;
6099
6100 assert_can_disable_lcpll(dev_priv);
6101
6102 val = I915_READ(LCPLL_CTL);
6103
6104 if (switch_to_fclk) {
6105 val |= LCPLL_CD_SOURCE_FCLK;
6106 I915_WRITE(LCPLL_CTL, val);
6107
6108 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6109 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6110 DRM_ERROR("Switching to FCLK failed\n");
6111
6112 val = I915_READ(LCPLL_CTL);
6113 }
6114
6115 val |= LCPLL_PLL_DISABLE;
6116 I915_WRITE(LCPLL_CTL, val);
6117 POSTING_READ(LCPLL_CTL);
6118
6119 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6120 DRM_ERROR("LCPLL still locked\n");
6121
6122 val = I915_READ(D_COMP);
6123 val |= D_COMP_COMP_DISABLE;
6124 I915_WRITE(D_COMP, val);
6125 POSTING_READ(D_COMP);
6126 ndelay(100);
6127
6128 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6129 DRM_ERROR("D_COMP RCOMP still in progress\n");
6130
6131 if (allow_power_down) {
6132 val = I915_READ(LCPLL_CTL);
6133 val |= LCPLL_POWER_DOWN_ALLOW;
6134 I915_WRITE(LCPLL_CTL, val);
6135 POSTING_READ(LCPLL_CTL);
6136 }
6137}
6138
6139/*
6140 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6141 * source.
6142 */
6143void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6144{
6145 uint32_t val;
6146
6147 val = I915_READ(LCPLL_CTL);
6148
6149 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6150 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6151 return;
6152
215733fa
PZ		 6153 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6154 * we'll hang the machine! */
6155 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6156
be256dc7
PZ		 6157 if (val & LCPLL_POWER_DOWN_ALLOW) {
6158 val &= ~LCPLL_POWER_DOWN_ALLOW;
6159 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6160 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6161 }
6162
6163 val = I915_READ(D_COMP);
6164 val |= D_COMP_COMP_FORCE;
6165 val &= ~D_COMP_COMP_DISABLE;
6166 I915_WRITE(D_COMP, val);
35d8f2eb 6167 POSTING_READ(D_COMP);
be256dc7
PZ		 6168
6169 val = I915_READ(LCPLL_CTL);
6170 val &= ~LCPLL_PLL_DISABLE;
6171 I915_WRITE(LCPLL_CTL, val);
6172
6173 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6174 DRM_ERROR("LCPLL not locked yet\n");
6175
6176 if (val & LCPLL_CD_SOURCE_FCLK) {
6177 val = I915_READ(LCPLL_CTL);
6178 val &= ~LCPLL_CD_SOURCE_FCLK;
6179 I915_WRITE(LCPLL_CTL, val);
6180
6181 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6182 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6183 DRM_ERROR("Switching back to LCPLL failed\n");
6184 }
215733fa
PZ		 6185
6186 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6187}
6188
c67a470b
PZ		 6189void hsw_enable_pc8_work(struct work_struct *__work)
6190{
6191 struct drm_i915_private *dev_priv =
6192 container_of(to_delayed_work(__work), struct drm_i915_private,
6193 pc8.enable_work);
6194 struct drm_device *dev = dev_priv->dev;
6195 uint32_t val;
6196
6197 if (dev_priv->pc8.enabled)
6198 return;
6199
6200 DRM_DEBUG_KMS("Enabling package C8+\n");
6201
6202 dev_priv->pc8.enabled = true;
6203
6204 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6205 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6206 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6207 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6208 }
6209
6210 lpt_disable_clkout_dp(dev);
6211 hsw_pc8_disable_interrupts(dev);
6212 hsw_disable_lcpll(dev_priv, true, true);
6213}
6214
6215static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6216{
6217 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6218 WARN(dev_priv->pc8.disable_count < 1,
6219 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6220
6221 dev_priv->pc8.disable_count--;
6222 if (dev_priv->pc8.disable_count != 0)
6223 return;
6224
6225 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6226 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6227}
6228
6229static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6230{
6231 struct drm_device *dev = dev_priv->dev;
6232 uint32_t val;
6233
6234 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6235 WARN(dev_priv->pc8.disable_count < 0,
6236 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6237
6238 dev_priv->pc8.disable_count++;
6239 if (dev_priv->pc8.disable_count != 1)
6240 return;
6241
6242 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6243 if (!dev_priv->pc8.enabled)
6244 return;
6245
6246 DRM_DEBUG_KMS("Disabling package C8+\n");
6247
6248 hsw_restore_lcpll(dev_priv);
6249 hsw_pc8_restore_interrupts(dev);
6250 lpt_init_pch_refclk(dev);
6251
6252 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6253 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6254 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6255 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6256 }
6257
6258 intel_prepare_ddi(dev);
6259 i915_gem_init_swizzling(dev);
6260 mutex_lock(&dev_priv->rps.hw_lock);
6261 gen6_update_ring_freq(dev);
6262 mutex_unlock(&dev_priv->rps.hw_lock);
6263 dev_priv->pc8.enabled = false;
6264}
6265
6266void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6267{
6268 mutex_lock(&dev_priv->pc8.lock);
6269 __hsw_enable_package_c8(dev_priv);
6270 mutex_unlock(&dev_priv->pc8.lock);
6271}
6272
6273void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6274{
6275 mutex_lock(&dev_priv->pc8.lock);
6276 __hsw_disable_package_c8(dev_priv);
6277 mutex_unlock(&dev_priv->pc8.lock);
6278}
6279
6280static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6281{
6282 struct drm_device *dev = dev_priv->dev;
6283 struct intel_crtc *crtc;
6284 uint32_t val;
6285
6286 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6287 if (crtc->base.enabled)
6288 return false;
6289
6290 /* This case is still possible since we have the i915.disable_power_well
6291 * parameter and also the KVMr or something else might be requesting the
6292 * power well. */
6293 val = I915_READ(HSW_PWR_WELL_DRIVER);
6294 if (val != 0) {
6295 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6296 return false;
6297 }
6298
6299 return true;
6300}
6301
6302/* Since we're called from modeset_global_resources there's no way to
6303 * symmetrically increase and decrease the refcount, so we use
6304 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6305 * or not.
6306 */
6307static void hsw_update_package_c8(struct drm_device *dev)
6308{
6309 struct drm_i915_private *dev_priv = dev->dev_private;
6310 bool allow;
6311
6312 if (!i915_enable_pc8)
6313 return;
6314
6315 mutex_lock(&dev_priv->pc8.lock);
6316
6317 allow = hsw_can_enable_package_c8(dev_priv);
6318
6319 if (allow == dev_priv->pc8.requirements_met)
6320 goto done;
6321
6322 dev_priv->pc8.requirements_met = allow;
6323
6324 if (allow)
6325 __hsw_enable_package_c8(dev_priv);
6326 else
6327 __hsw_disable_package_c8(dev_priv);
6328
6329done:
6330 mutex_unlock(&dev_priv->pc8.lock);
6331}
6332
6333static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6334{
6335 if (!dev_priv->pc8.gpu_idle) {
6336 dev_priv->pc8.gpu_idle = true;
6337 hsw_enable_package_c8(dev_priv);
6338 }
6339}
6340
6341static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6342{
6343 if (dev_priv->pc8.gpu_idle) {
6344 dev_priv->pc8.gpu_idle = false;
6345 hsw_disable_package_c8(dev_priv);
6346 }
be256dc7
PZ		 6347}
6348
d6dd9eb1
DV		 6349static void haswell_modeset_global_resources(struct drm_device *dev)
6350{
d6dd9eb1
DV		 6351 bool enable = false;
6352 struct intel_crtc *crtc;
d6dd9eb1
DV		 6353
6354 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6355 if (!crtc->base.enabled)
6356 continue;
d6dd9eb1 6357
e7a639c4
DV		 6358 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6359 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6360 enable = true;
6361 }
6362
d6dd9eb1 6363 intel_set_power_well(dev, enable);
c67a470b
PZ		 6364
6365 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6366}
6367
09b4ddf9 6368static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6369 int x, int y,
6370 struct drm_framebuffer *fb)
6371{
6372 struct drm_device *dev = crtc->dev;
6373 struct drm_i915_private *dev_priv = dev->dev_private;
6374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6375 int plane = intel_crtc->plane;
09b4ddf9 6376 int ret;
09b4ddf9 6377
ff9a6750 6378 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6379 return -EINVAL;
6380
09b4ddf9
PZ		 6381 /* Ensure that the cursor is valid for the new mode before changing... */
6382 intel_crtc_update_cursor(crtc, true);
6383
03afc4a2
DV		 6384 if (intel_crtc->config.has_dp_encoder)
6385 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6386
6387 intel_crtc->lowfreq_avail = false;
09b4ddf9 6388
8a654f3b 6389 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6390
ca3a0ff8 6391 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6392 intel_cpu_transcoder_set_m_n(intel_crtc,
6393 &intel_crtc->config.fdi_m_n);
6394 }
09b4ddf9 6395
6ff93609 6396 haswell_set_pipeconf(crtc);
09b4ddf9 6397
50f3b016 6398 intel_set_pipe_csc(crtc);
86d3efce 6399
09b4ddf9 6400 /* Set up the display plane register */
86d3efce 6401 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6402 POSTING_READ(DSPCNTR(plane));
6403
6404 ret = intel_pipe_set_base(crtc, x, y, fb);
6405
1f803ee5 6406 return ret;
79e53945
JB		 6407}
6408
0e8ffe1b
DV		 6409static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6410 struct intel_crtc_config *pipe_config)
6411{
6412 struct drm_device *dev = crtc->base.dev;
6413 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6414 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6415 uint32_t tmp;
6416
e143a21c 6417 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6418 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6419
eccb140b
DV		 6420 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6421 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6422 enum pipe trans_edp_pipe;
6423 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6424 default:
6425 WARN(1, "unknown pipe linked to edp transcoder\n");
6426 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6427 case TRANS_DDI_EDP_INPUT_A_ON:
6428 trans_edp_pipe = PIPE_A;
6429 break;
6430 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6431 trans_edp_pipe = PIPE_B;
6432 break;
6433 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6434 trans_edp_pipe = PIPE_C;
6435 break;
6436 }
6437
6438 if (trans_edp_pipe == crtc->pipe)
6439 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6440 }
6441
b97186f0 6442 if (!intel_display_power_enabled(dev,
eccb140b 6443 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6444 return false;
6445
eccb140b 6446 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6447 if (!(tmp & PIPECONF_ENABLE))
6448 return false;
6449
88adfff1 6450 /*
f196e6be 6451 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6452 * DDI E. So just check whether this pipe is wired to DDI E and whether
6453 * the PCH transcoder is on.
6454 */
eccb140b 6455 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6456 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6457 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6458 pipe_config->has_pch_encoder = true;
6459
627eb5a3
DV		 6460 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6461 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6462 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6463
6464 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6465 }
6466
1bd1bd80
DV		 6467 intel_get_pipe_timings(crtc, pipe_config);
6468
2fa2fe9a
DV		 6469 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6470 if (intel_display_power_enabled(dev, pfit_domain))
6471 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6472
42db64ef
PZ		 6473 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6474 (I915_READ(IPS_CTL) & IPS_ENABLE);
6475
6c49f241
DV		 6476 pipe_config->pixel_multiplier = 1;
6477
0e8ffe1b
DV		 6478 return true;
6479}
6480
f564048e 6481static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6482 int x, int y,
94352cf9 6483 struct drm_framebuffer *fb)
f564048e
EA		 6484{
6485 struct drm_device *dev = crtc->dev;
6486 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6487 struct intel_encoder *encoder;
0b701d27 6488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6489 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6490 int pipe = intel_crtc->pipe;
f564048e
EA		 6491 int ret;
6492
0b701d27 6493 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6494
b8cecdf5
DV		 6495 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6496
79e53945 6497 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6498
9256aa19
DV		 6499 if (ret != 0)
6500 return ret;
6501
6502 for_each_encoder_on_crtc(dev, crtc, encoder) {
6503 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6504 encoder->base.base.id,
6505 drm_get_encoder_name(&encoder->base),
6506 mode->base.id, mode->name);
36f2d1f1 6507 encoder->mode_set(encoder);
9256aa19
DV		 6508 }
6509
6510 return 0;
79e53945
JB		 6511}
6512
3a9627f4
WF		 6513static bool intel_eld_uptodate(struct drm_connector *connector,
6514 int reg_eldv, uint32_t bits_eldv,
6515 int reg_elda, uint32_t bits_elda,
6516 int reg_edid)
6517{
6518 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6519 uint8_t *eld = connector->eld;
6520 uint32_t i;
6521
6522 i = I915_READ(reg_eldv);
6523 i &= bits_eldv;
6524
6525 if (!eld[0])
6526 return !i;
6527
6528 if (!i)
6529 return false;
6530
6531 i = I915_READ(reg_elda);
6532 i &= ~bits_elda;
6533 I915_WRITE(reg_elda, i);
6534
6535 for (i = 0; i < eld[2]; i++)
6536 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6537 return false;
6538
6539 return true;
6540}
6541
e0dac65e
WF		 6542static void g4x_write_eld(struct drm_connector *connector,
6543 struct drm_crtc *crtc)
6544{
6545 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6546 uint8_t *eld = connector->eld;
6547 uint32_t eldv;
6548 uint32_t len;
6549 uint32_t i;
6550
6551 i = I915_READ(G4X_AUD_VID_DID);
6552
6553 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6554 eldv = G4X_ELDV_DEVCL_DEVBLC;
6555 else
6556 eldv = G4X_ELDV_DEVCTG;
6557
3a9627f4
WF		 6558 if (intel_eld_uptodate(connector,
6559 G4X_AUD_CNTL_ST, eldv,
6560 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6561 G4X_HDMIW_HDMIEDID))
6562 return;
6563
e0dac65e
WF		 6564 i = I915_READ(G4X_AUD_CNTL_ST);
6565 i &= ~(eldv | G4X_ELD_ADDR);
6566 len = (i >> 9) & 0x1f; /* ELD buffer size */
6567 I915_WRITE(G4X_AUD_CNTL_ST, i);
6568
6569 if (!eld[0])
6570 return;
6571
6572 len = min_t(uint8_t, eld[2], len);
6573 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6574 for (i = 0; i < len; i++)
6575 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6576
6577 i = I915_READ(G4X_AUD_CNTL_ST);
6578 i |= eldv;
6579 I915_WRITE(G4X_AUD_CNTL_ST, i);
6580}
6581
83358c85
WX		 6582static void haswell_write_eld(struct drm_connector *connector,
6583 struct drm_crtc *crtc)
6584{
6585 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6586 uint8_t *eld = connector->eld;
6587 struct drm_device *dev = crtc->dev;
7b9f35a6 6588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6589 uint32_t eldv;
6590 uint32_t i;
6591 int len;
6592 int pipe = to_intel_crtc(crtc)->pipe;
6593 int tmp;
6594
6595 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6596 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6597 int aud_config = HSW_AUD_CFG(pipe);
6598 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6599
6600
6601 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6602
6603 /* Audio output enable */
6604 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6605 tmp = I915_READ(aud_cntrl_st2);
6606 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6607 I915_WRITE(aud_cntrl_st2, tmp);
6608
6609 /* Wait for 1 vertical blank */
6610 intel_wait_for_vblank(dev, pipe);
6611
6612 /* Set ELD valid state */
6613 tmp = I915_READ(aud_cntrl_st2);
6614 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6615 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6616 I915_WRITE(aud_cntrl_st2, tmp);
6617 tmp = I915_READ(aud_cntrl_st2);
6618 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6619
6620 /* Enable HDMI mode */
6621 tmp = I915_READ(aud_config);
6622 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6623 /* clear N_programing_enable and N_value_index */
6624 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6625 I915_WRITE(aud_config, tmp);
6626
6627 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6628
6629 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6630 intel_crtc->eld_vld = true;
83358c85
WX		 6631
6632 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6633 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6634 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6635 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6636 } else
6637 I915_WRITE(aud_config, 0);
6638
6639 if (intel_eld_uptodate(connector,
6640 aud_cntrl_st2, eldv,
6641 aud_cntl_st, IBX_ELD_ADDRESS,
6642 hdmiw_hdmiedid))
6643 return;
6644
6645 i = I915_READ(aud_cntrl_st2);
6646 i &= ~eldv;
6647 I915_WRITE(aud_cntrl_st2, i);
6648
6649 if (!eld[0])
6650 return;
6651
6652 i = I915_READ(aud_cntl_st);
6653 i &= ~IBX_ELD_ADDRESS;
6654 I915_WRITE(aud_cntl_st, i);
6655 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6656 DRM_DEBUG_DRIVER("port num:%d\n", i);
6657
6658 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6659 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6660 for (i = 0; i < len; i++)
6661 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6662
6663 i = I915_READ(aud_cntrl_st2);
6664 i |= eldv;
6665 I915_WRITE(aud_cntrl_st2, i);
6666
6667}
6668
e0dac65e
WF		 6669static void ironlake_write_eld(struct drm_connector *connector,
6670 struct drm_crtc *crtc)
6671{
6672 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6673 uint8_t *eld = connector->eld;
6674 uint32_t eldv;
6675 uint32_t i;
6676 int len;
6677 int hdmiw_hdmiedid;
b6daa025 6678 int aud_config;
e0dac65e
WF		 6679 int aud_cntl_st;
6680 int aud_cntrl_st2;
9b138a83 6681 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6682
b3f33cbf 6683 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6684 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6685 aud_config = IBX_AUD_CFG(pipe);
6686 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6687 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6688 } else {
9b138a83
WX		 6689 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6690 aud_config = CPT_AUD_CFG(pipe);
6691 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6692 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6693 }
6694
9b138a83 6695 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6696
6697 i = I915_READ(aud_cntl_st);
9b138a83 6698 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6699 if (!i) {
6700 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6701 /* operate blindly on all ports */
1202b4c6
WF		 6702 eldv = IBX_ELD_VALIDB;
6703 eldv |= IBX_ELD_VALIDB << 4;
6704 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6705 } else {
2582a850 6706 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6707 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6708 }
6709
3a9627f4
WF		 6710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6711 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6712 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6713 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6714 } else
6715 I915_WRITE(aud_config, 0);
e0dac65e 6716
3a9627f4
WF		 6717 if (intel_eld_uptodate(connector,
6718 aud_cntrl_st2, eldv,
6719 aud_cntl_st, IBX_ELD_ADDRESS,
6720 hdmiw_hdmiedid))
6721 return;
6722
e0dac65e
WF		 6723 i = I915_READ(aud_cntrl_st2);
6724 i &= ~eldv;
6725 I915_WRITE(aud_cntrl_st2, i);
6726
6727 if (!eld[0])
6728 return;
6729
e0dac65e 6730 i = I915_READ(aud_cntl_st);
1202b4c6 6731 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6732 I915_WRITE(aud_cntl_st, i);
6733
6734 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6735 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6736 for (i = 0; i < len; i++)
6737 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6738
6739 i = I915_READ(aud_cntrl_st2);
6740 i |= eldv;
6741 I915_WRITE(aud_cntrl_st2, i);
6742}
6743
6744void intel_write_eld(struct drm_encoder *encoder,
6745 struct drm_display_mode *mode)
6746{
6747 struct drm_crtc *crtc = encoder->crtc;
6748 struct drm_connector *connector;
6749 struct drm_device *dev = encoder->dev;
6750 struct drm_i915_private *dev_priv = dev->dev_private;
6751
6752 connector = drm_select_eld(encoder, mode);
6753 if (!connector)
6754 return;
6755
6756 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6757 connector->base.id,
6758 drm_get_connector_name(connector),
6759 connector->encoder->base.id,
6760 drm_get_encoder_name(connector->encoder));
6761
6762 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6763
6764 if (dev_priv->display.write_eld)
6765 dev_priv->display.write_eld(connector, crtc);
6766}
6767
79e53945
JB		 6768/** Loads the palette/gamma unit for the CRTC with the prepared values */
6769void intel_crtc_load_lut(struct drm_crtc *crtc)
6770{
6771 struct drm_device *dev = crtc->dev;
6772 struct drm_i915_private *dev_priv = dev->dev_private;
6773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6774 enum pipe pipe = intel_crtc->pipe;
6775 int palreg = PALETTE(pipe);
79e53945 6776 int i;
42db64ef 6777 bool reenable_ips = false;
79e53945
JB		 6778
6779 /* The clocks have to be on to load the palette. */
aed3f09d 6780 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6781 return;
6782
23538ef1
JN		 6783 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6784 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6785 assert_dsi_pll_enabled(dev_priv);
6786 else
6787 assert_pll_enabled(dev_priv, pipe);
6788 }
14420bd0 6789
f2b115e6 6790 /* use legacy palette for Ironlake */
bad720ff 6791 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6792 palreg = LGC_PALETTE(pipe);
6793
6794 /* Workaround : Do not read or write the pipe palette/gamma data while
6795 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6796 */
6797 if (intel_crtc->config.ips_enabled &&
6798 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6799 GAMMA_MODE_MODE_SPLIT)) {
6800 hsw_disable_ips(intel_crtc);
6801 reenable_ips = true;
6802 }
2c07245f 6803
79e53945
JB		 6804 for (i = 0; i < 256; i++) {
6805 I915_WRITE(palreg + 4 * i,
6806 (intel_crtc->lut_r[i] << 16) |
6807 (intel_crtc->lut_g[i] << 8) |
6808 intel_crtc->lut_b[i]);
6809 }
42db64ef
PZ		 6810
6811 if (reenable_ips)
6812 hsw_enable_ips(intel_crtc);
79e53945
JB		 6813}
6814
560b85bb
CW		 6815static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6816{
6817 struct drm_device *dev = crtc->dev;
6818 struct drm_i915_private *dev_priv = dev->dev_private;
6819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6820 bool visible = base != 0;
6821 u32 cntl;
6822
6823 if (intel_crtc->cursor_visible == visible)
6824 return;
6825
9db4a9c7 6826 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6827 if (visible) {
6828 /* On these chipsets we can only modify the base whilst
6829 * the cursor is disabled.
6830 */
9db4a9c7 6831 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6832
6833 cntl &= ~(CURSOR_FORMAT_MASK);
6834 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6835 cntl |= CURSOR_ENABLE |
6836 CURSOR_GAMMA_ENABLE |
6837 CURSOR_FORMAT_ARGB;
6838 } else
6839 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6840 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6841
6842 intel_crtc->cursor_visible = visible;
6843}
6844
6845static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6846{
6847 struct drm_device *dev = crtc->dev;
6848 struct drm_i915_private *dev_priv = dev->dev_private;
6849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6850 int pipe = intel_crtc->pipe;
6851 bool visible = base != 0;
6852
6853 if (intel_crtc->cursor_visible != visible) {
548f245b 6854 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6855 if (base) {
6856 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6857 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6858 cntl |= pipe << 28; /* Connect to correct pipe */
6859 } else {
6860 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6861 cntl |= CURSOR_MODE_DISABLE;
6862 }
9db4a9c7 6863 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6864
6865 intel_crtc->cursor_visible = visible;
6866 }
6867 /* and commit changes on next vblank */
9db4a9c7 6868 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6869}
6870
65a21cd6
JB		 6871static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6872{
6873 struct drm_device *dev = crtc->dev;
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6876 int pipe = intel_crtc->pipe;
6877 bool visible = base != 0;
6878
6879 if (intel_crtc->cursor_visible != visible) {
6880 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6881 if (base) {
6882 cntl &= ~CURSOR_MODE;
6883 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6884 } else {
6885 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6886 cntl |= CURSOR_MODE_DISABLE;
6887 }
1f5d76db 6888 if (IS_HASWELL(dev)) {
86d3efce 6889 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6890 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6891 }
65a21cd6
JB		 6892 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6893
6894 intel_crtc->cursor_visible = visible;
6895 }
6896 /* and commit changes on next vblank */
6897 I915_WRITE(CURBASE_IVB(pipe), base);
6898}
6899
cda4b7d3 6900/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6901static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6902 bool on)
cda4b7d3
CW		 6903{
6904 struct drm_device *dev = crtc->dev;
6905 struct drm_i915_private *dev_priv = dev->dev_private;
6906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6907 int pipe = intel_crtc->pipe;
6908 int x = intel_crtc->cursor_x;
6909 int y = intel_crtc->cursor_y;
d6e4db15 6910 u32 base = 0, pos = 0;
cda4b7d3
CW		 6911 bool visible;
6912
d6e4db15 6913 if (on)
cda4b7d3 6914 base = intel_crtc->cursor_addr;
cda4b7d3 6915
d6e4db15
VS		 6916 if (x >= intel_crtc->config.pipe_src_w)
6917 base = 0;
6918
6919 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 6920 base = 0;
6921
6922 if (x < 0) {
efc9064e 6923 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 6924 base = 0;
6925
6926 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6927 x = -x;
6928 }
6929 pos |= x << CURSOR_X_SHIFT;
6930
6931 if (y < 0) {
efc9064e 6932 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 6933 base = 0;
6934
6935 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6936 y = -y;
6937 }
6938 pos |= y << CURSOR_Y_SHIFT;
6939
6940 visible = base != 0;
560b85bb 6941 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6942 return;
6943
0cd83aa9 6944 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6945 I915_WRITE(CURPOS_IVB(pipe), pos);
6946 ivb_update_cursor(crtc, base);
6947 } else {
6948 I915_WRITE(CURPOS(pipe), pos);
6949 if (IS_845G(dev) || IS_I865G(dev))
6950 i845_update_cursor(crtc, base);
6951 else
6952 i9xx_update_cursor(crtc, base);
6953 }
cda4b7d3
CW		 6954}
6955
79e53945 6956static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6957 struct drm_file *file,
79e53945
JB		 6958 uint32_t handle,
6959 uint32_t width, uint32_t height)
6960{
6961 struct drm_device *dev = crtc->dev;
6962 struct drm_i915_private *dev_priv = dev->dev_private;
6963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6964 struct drm_i915_gem_object *obj;
cda4b7d3 6965 uint32_t addr;
3f8bc370 6966 int ret;
79e53945 6967
79e53945
JB		 6968 /* if we want to turn off the cursor ignore width and height */
6969 if (!handle) {
28c97730 6970 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6971 addr = 0;
05394f39 6972 obj = NULL;
5004417d 6973 mutex_lock(&dev->struct_mutex);
3f8bc370 6974 goto finish;
79e53945
JB		 6975 }
6976
6977 /* Currently we only support 64x64 cursors */
6978 if (width != 64 || height != 64) {
6979 DRM_ERROR("we currently only support 64x64 cursors\n");
6980 return -EINVAL;
6981 }
6982
05394f39 6983 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6984 if (&obj->base == NULL)
79e53945
JB		 6985 return -ENOENT;
6986
05394f39 6987 if (obj->base.size < width * height * 4) {
79e53945 6988 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6989 ret = -ENOMEM;
6990 goto fail;
79e53945
JB		 6991 }
6992
71acb5eb 6993 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6994 mutex_lock(&dev->struct_mutex);
b295d1b6 6995 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6996 unsigned alignment;
6997
d9e86c0e
CW		 6998 if (obj->tiling_mode) {
6999 DRM_ERROR("cursor cannot be tiled\n");
7000 ret = -EINVAL;
7001 goto fail_locked;
7002 }
7003
693db184
CW		 7004 /* Note that the w/a also requires 2 PTE of padding following
7005 * the bo. We currently fill all unused PTE with the shadow
7006 * page and so we should always have valid PTE following the
7007 * cursor preventing the VT-d warning.
7008 */
7009 alignment = 0;
7010 if (need_vtd_wa(dev))
7011 alignment = 64*1024;
7012
7013 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7014 if (ret) {
7015 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7016 goto fail_locked;
e7b526bb
CW		 7017 }
7018
d9e86c0e
CW		 7019 ret = i915_gem_object_put_fence(obj);
7020 if (ret) {
2da3b9b9 7021 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7022 goto fail_unpin;
7023 }
7024
f343c5f6 7025 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7026 } else {
6eeefaf3 7027 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7028 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7029 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7030 align);
71acb5eb
DA		 7031 if (ret) {
7032 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7033 goto fail_locked;
71acb5eb 7034 }
05394f39 7035 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7036 }
7037
a6c45cf0 7038 if (IS_GEN2(dev))
14b60391
JB		 7039 I915_WRITE(CURSIZE, (height << 12) | width);
7040
3f8bc370 7041 finish:
3f8bc370 7042 if (intel_crtc->cursor_bo) {
b295d1b6 7043 if (dev_priv->info->cursor_needs_physical) {
05394f39 7044 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7045 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7046 } else
cc98b413 7047 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7048 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7049 }
80824003 7050
7f9872e0 7051 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7052
7053 intel_crtc->cursor_addr = addr;
05394f39 7054 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7055 intel_crtc->cursor_width = width;
7056 intel_crtc->cursor_height = height;
7057
40ccc72b 7058 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7059
79e53945 7060 return 0;
e7b526bb 7061fail_unpin:
cc98b413 7062 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7063fail_locked:
34b8686e 7064 mutex_unlock(&dev->struct_mutex);
bc9025bd 7065fail:
05394f39 7066 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7067 return ret;
79e53945
JB		 7068}
7069
7070static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7071{
79e53945 7072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7073
cda4b7d3
CW		 7074 intel_crtc->cursor_x = x;
7075 intel_crtc->cursor_y = y;
652c393a 7076
40ccc72b 7077 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7078
7079 return 0;
7080}
7081
7082/** Sets the color ramps on behalf of RandR */
7083void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7084 u16 blue, int regno)
7085{
7086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7087
7088 intel_crtc->lut_r[regno] = red >> 8;
7089 intel_crtc->lut_g[regno] = green >> 8;
7090 intel_crtc->lut_b[regno] = blue >> 8;
7091}
7092
b8c00ac5
DA		 7093void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7094 u16 *blue, int regno)
7095{
7096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7097
7098 *red = intel_crtc->lut_r[regno] << 8;
7099 *green = intel_crtc->lut_g[regno] << 8;
7100 *blue = intel_crtc->lut_b[regno] << 8;
7101}
7102
79e53945 7103static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7104 u16 *blue, uint32_t start, uint32_t size)
79e53945 7105{
7203425a 7106 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7108
7203425a 7109 for (i = start; i < end; i++) {
79e53945
JB		 7110 intel_crtc->lut_r[i] = red[i] >> 8;
7111 intel_crtc->lut_g[i] = green[i] >> 8;
7112 intel_crtc->lut_b[i] = blue[i] >> 8;
7113 }
7114
7115 intel_crtc_load_lut(crtc);
7116}
7117
79e53945
JB		 7118/* VESA 640x480x72Hz mode to set on the pipe */
7119static struct drm_display_mode load_detect_mode = {
7120 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7121 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7122};
7123
d2dff872
CW		 7124static struct drm_framebuffer *
7125intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7126 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7127 struct drm_i915_gem_object *obj)
7128{
7129 struct intel_framebuffer *intel_fb;
7130 int ret;
7131
7132 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7133 if (!intel_fb) {
7134 drm_gem_object_unreference_unlocked(&obj->base);
7135 return ERR_PTR(-ENOMEM);
7136 }
7137
7138 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7139 if (ret) {
7140 drm_gem_object_unreference_unlocked(&obj->base);
7141 kfree(intel_fb);
7142 return ERR_PTR(ret);
7143 }
7144
7145 return &intel_fb->base;
7146}
7147
7148static u32
7149intel_framebuffer_pitch_for_width(int width, int bpp)
7150{
7151 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7152 return ALIGN(pitch, 64);
7153}
7154
7155static u32
7156intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7157{
7158 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7159 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7160}
7161
7162static struct drm_framebuffer *
7163intel_framebuffer_create_for_mode(struct drm_device *dev,
7164 struct drm_display_mode *mode,
7165 int depth, int bpp)
7166{
7167 struct drm_i915_gem_object *obj;
0fed39bd 7168 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7169
7170 obj = i915_gem_alloc_object(dev,
7171 intel_framebuffer_size_for_mode(mode, bpp));
7172 if (obj == NULL)
7173 return ERR_PTR(-ENOMEM);
7174
7175 mode_cmd.width = mode->hdisplay;
7176 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7177 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7178 bpp);
5ca0c34a 7179 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7180
7181 return intel_framebuffer_create(dev, &mode_cmd, obj);
7182}
7183
7184static struct drm_framebuffer *
7185mode_fits_in_fbdev(struct drm_device *dev,
7186 struct drm_display_mode *mode)
7187{
7188 struct drm_i915_private *dev_priv = dev->dev_private;
7189 struct drm_i915_gem_object *obj;
7190 struct drm_framebuffer *fb;
7191
7192 if (dev_priv->fbdev == NULL)
7193 return NULL;
7194
7195 obj = dev_priv->fbdev->ifb.obj;
7196 if (obj == NULL)
7197 return NULL;
7198
7199 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7200 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7201 fb->bits_per_pixel))
d2dff872
CW		 7202 return NULL;
7203
01f2c773 7204 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7205 return NULL;
7206
7207 return fb;
7208}
7209
d2434ab7 7210bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7211 struct drm_display_mode *mode,
8261b191 7212 struct intel_load_detect_pipe *old)
79e53945
JB		 7213{
7214 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7215 struct intel_encoder *intel_encoder =
7216 intel_attached_encoder(connector);
79e53945 7217 struct drm_crtc *possible_crtc;
4ef69c7a 7218 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7219 struct drm_crtc *crtc = NULL;
7220 struct drm_device *dev = encoder->dev;
94352cf9 7221 struct drm_framebuffer *fb;
79e53945
JB		 7222 int i = -1;
7223
d2dff872
CW		 7224 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7225 connector->base.id, drm_get_connector_name(connector),
7226 encoder->base.id, drm_get_encoder_name(encoder));
7227
79e53945
JB		 7228 /*
7229 * Algorithm gets a little messy:
7a5e4805 7230 *
79e53945
JB		 7231 * - if the connector already has an assigned crtc, use it (but make
7232 * sure it's on first)
7a5e4805 7233 *
79e53945
JB		 7234 * - try to find the first unused crtc that can drive this connector,
7235 * and use that if we find one
79e53945
JB		 7236 */
7237
7238 /* See if we already have a CRTC for this connector */
7239 if (encoder->crtc) {
7240 crtc = encoder->crtc;
8261b191 7241
7b24056b
DV		 7242 mutex_lock(&crtc->mutex);
7243
24218aac 7244 old->dpms_mode = connector->dpms;
8261b191
CW		 7245 old->load_detect_temp = false;
7246
7247 /* Make sure the crtc and connector are running */
24218aac
DV		 7248 if (connector->dpms != DRM_MODE_DPMS_ON)
7249 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7250
7173188d 7251 return true;
79e53945
JB		 7252 }
7253
7254 /* Find an unused one (if possible) */
7255 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7256 i++;
7257 if (!(encoder->possible_crtcs & (1 << i)))
7258 continue;
7259 if (!possible_crtc->enabled) {
7260 crtc = possible_crtc;
7261 break;
7262 }
79e53945
JB		 7263 }
7264
7265 /*
7266 * If we didn't find an unused CRTC, don't use any.
7267 */
7268 if (!crtc) {
7173188d
CW		 7269 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7270 return false;
79e53945
JB		 7271 }
7272
7b24056b 7273 mutex_lock(&crtc->mutex);
fc303101
DV		 7274 intel_encoder->new_crtc = to_intel_crtc(crtc);
7275 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7276
7277 intel_crtc = to_intel_crtc(crtc);
24218aac 7278 old->dpms_mode = connector->dpms;
8261b191 7279 old->load_detect_temp = true;
d2dff872 7280 old->release_fb = NULL;
79e53945 7281
6492711d
CW		 7282 if (!mode)
7283 mode = &load_detect_mode;
79e53945 7284
d2dff872
CW		 7285 /* We need a framebuffer large enough to accommodate all accesses
7286 * that the plane may generate whilst we perform load detection.
7287 * We can not rely on the fbcon either being present (we get called
7288 * during its initialisation to detect all boot displays, or it may
7289 * not even exist) or that it is large enough to satisfy the
7290 * requested mode.
7291 */
94352cf9
DV		 7292 fb = mode_fits_in_fbdev(dev, mode);
7293 if (fb == NULL) {
d2dff872 7294 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7295 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7296 old->release_fb = fb;
d2dff872
CW		 7297 } else
7298 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7299 if (IS_ERR(fb)) {
d2dff872 7300 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7301 mutex_unlock(&crtc->mutex);
0e8b3d3e 7302 return false;
79e53945 7303 }
79e53945 7304
c0c36b94 7305 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7306 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7307 if (old->release_fb)
7308 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7309 mutex_unlock(&crtc->mutex);
0e8b3d3e 7310 return false;
79e53945 7311 }
7173188d 7312
79e53945 7313 /* let the connector get through one full cycle before testing */
9d0498a2 7314 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7315 return true;
79e53945
JB		 7316}
7317
d2434ab7 7318void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7319 struct intel_load_detect_pipe *old)
79e53945 7320{
d2434ab7
DV		 7321 struct intel_encoder *intel_encoder =
7322 intel_attached_encoder(connector);
4ef69c7a 7323 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7324 struct drm_crtc *crtc = encoder->crtc;
79e53945 7325
d2dff872
CW		 7326 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7327 connector->base.id, drm_get_connector_name(connector),
7328 encoder->base.id, drm_get_encoder_name(encoder));
7329
8261b191 7330 if (old->load_detect_temp) {
fc303101
DV		 7331 to_intel_connector(connector)->new_encoder = NULL;
7332 intel_encoder->new_crtc = NULL;
7333 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7334
36206361
DV		 7335 if (old->release_fb) {
7336 drm_framebuffer_unregister_private(old->release_fb);
7337 drm_framebuffer_unreference(old->release_fb);
7338 }
d2dff872 7339
67c96400 7340 mutex_unlock(&crtc->mutex);
0622a53c 7341 return;
79e53945
JB		 7342 }
7343
c751ce4f 7344 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7345 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7346 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7347
7348 mutex_unlock(&crtc->mutex);
79e53945
JB		 7349}
7350
da4a1efa
VS		 7351static int i9xx_pll_refclk(struct drm_device *dev,
7352 const struct intel_crtc_config *pipe_config)
7353{
7354 struct drm_i915_private *dev_priv = dev->dev_private;
7355 u32 dpll = pipe_config->dpll_hw_state.dpll;
7356
7357 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7358 return dev_priv->vbt.lvds_ssc_freq * 1000;
7359 else if (HAS_PCH_SPLIT(dev))
7360 return 120000;
7361 else if (!IS_GEN2(dev))
7362 return 96000;
7363 else
7364 return 48000;
7365}
7366
79e53945 7367/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7368static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7369 struct intel_crtc_config *pipe_config)
79e53945 7370{
f1f644dc 7371 struct drm_device *dev = crtc->base.dev;
79e53945 7372 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7373 int pipe = pipe_config->cpu_transcoder;
293623f7 7374 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7375 u32 fp;
7376 intel_clock_t clock;
da4a1efa 7377 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7378
7379 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7380 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7381 else
293623f7 7382 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7383
7384 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7385 if (IS_PINEVIEW(dev)) {
7386 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7387 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7388 } else {
7389 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7390 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7391 }
7392
a6c45cf0 7393 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7394 if (IS_PINEVIEW(dev))
7395 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7396 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7397 else
7398 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7399 DPLL_FPA01_P1_POST_DIV_SHIFT);
7400
7401 switch (dpll & DPLL_MODE_MASK) {
7402 case DPLLB_MODE_DAC_SERIAL:
7403 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7404 5 : 10;
7405 break;
7406 case DPLLB_MODE_LVDS:
7407 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7408 7 : 14;
7409 break;
7410 default:
28c97730 7411 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7412 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7413 return;
79e53945
JB		 7414 }
7415
ac58c3f0 7416 if (IS_PINEVIEW(dev))
da4a1efa 7417 pineview_clock(refclk, &clock);
ac58c3f0 7418 else
da4a1efa 7419 i9xx_clock(refclk, &clock);
79e53945
JB		 7420 } else {
7421 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7422
7423 if (is_lvds) {
7424 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7425 DPLL_FPA01_P1_POST_DIV_SHIFT);
7426 clock.p2 = 14;
79e53945
JB		 7427 } else {
7428 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7429 clock.p1 = 2;
7430 else {
7431 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7432 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7433 }
7434 if (dpll & PLL_P2_DIVIDE_BY_4)
7435 clock.p2 = 4;
7436 else
7437 clock.p2 = 2;
79e53945 7438 }
da4a1efa
VS		 7439
7440 i9xx_clock(refclk, &clock);
79e53945
JB		 7441 }
7442
18442d08
VS		 7443 /*
7444 * This value includes pixel_multiplier. We will use
7445 * port_clock to compute adjusted_mode.clock in the
7446 * encoder's get_config() function.
7447 */
7448 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7449}
7450
6878da05
VS		 7451int intel_dotclock_calculate(int link_freq,
7452 const struct intel_link_m_n *m_n)
f1f644dc 7453{
f1f644dc
JB		 7454 /*
7455 * The calculation for the data clock is:
1041a02f 7456 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7457 * But we want to avoid losing precison if possible, so:
1041a02f 7458 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7459 *
7460 * and the link clock is simpler:
1041a02f 7461 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7462 */
7463
6878da05
VS		 7464 if (!m_n->link_n)
7465 return 0;
7466
7467 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7468}
7469
18442d08
VS		 7470static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7471 struct intel_crtc_config *pipe_config)
6878da05
VS		 7472{
7473 struct drm_device *dev = crtc->base.dev;
18442d08
VS		 7474
7475 /* read out port_clock from the DPLL */
7476 i9xx_crtc_clock_get(crtc, pipe_config);
6878da05 7477
f1f644dc 7478 /*
18442d08
VS		 7479 * This value does not include pixel_multiplier.
7480 * We will check that port_clock and adjusted_mode.clock
7481 * agree once we know their relationship in the encoder's
7482 * get_config() function.
79e53945 7483 */
18442d08
VS		 7484 pipe_config->adjusted_mode.clock =
7485 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7486 &pipe_config->fdi_m_n);
79e53945
JB		 7487}
7488
7489/** Returns the currently programmed mode of the given pipe. */
7490struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7491 struct drm_crtc *crtc)
7492{
548f245b 7493 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7495 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7496 struct drm_display_mode *mode;
f1f644dc 7497 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7498 int htot = I915_READ(HTOTAL(cpu_transcoder));
7499 int hsync = I915_READ(HSYNC(cpu_transcoder));
7500 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7501 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7502 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7503
7504 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7505 if (!mode)
7506 return NULL;
7507
f1f644dc
JB		 7508 /*
7509 * Construct a pipe_config sufficient for getting the clock info
7510 * back out of crtc_clock_get.
7511 *
7512 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7513 * to use a real value here instead.
7514 */
293623f7 7515 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7516 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7517 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7518 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7519 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7520 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7521
7522 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7523 mode->hdisplay = (htot & 0xffff) + 1;
7524 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7525 mode->hsync_start = (hsync & 0xffff) + 1;
7526 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7527 mode->vdisplay = (vtot & 0xffff) + 1;
7528 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7529 mode->vsync_start = (vsync & 0xffff) + 1;
7530 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7531
7532 drm_mode_set_name(mode);
79e53945
JB		 7533
7534 return mode;
7535}
7536
3dec0095 7537static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7538{
7539 struct drm_device *dev = crtc->dev;
7540 drm_i915_private_t *dev_priv = dev->dev_private;
7541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7542 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7543 int dpll_reg = DPLL(pipe);
7544 int dpll;
652c393a 7545
bad720ff 7546 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7547 return;
7548
7549 if (!dev_priv->lvds_downclock_avail)
7550 return;
7551
dbdc6479 7552 dpll = I915_READ(dpll_reg);
652c393a 7553 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7554 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7555
8ac5a6d5 7556 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7557
7558 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7559 I915_WRITE(dpll_reg, dpll);
9d0498a2 7560 intel_wait_for_vblank(dev, pipe);
dbdc6479 7561
652c393a
JB		 7562 dpll = I915_READ(dpll_reg);
7563 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7564 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7565 }
652c393a
JB		 7566}
7567
7568static void intel_decrease_pllclock(struct drm_crtc *crtc)
7569{
7570 struct drm_device *dev = crtc->dev;
7571 drm_i915_private_t *dev_priv = dev->dev_private;
7572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7573
bad720ff 7574 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7575 return;
7576
7577 if (!dev_priv->lvds_downclock_avail)
7578 return;
7579
7580 /*
7581 * Since this is called by a timer, we should never get here in
7582 * the manual case.
7583 */
7584 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7585 int pipe = intel_crtc->pipe;
7586 int dpll_reg = DPLL(pipe);
7587 int dpll;
f6e5b160 7588
44d98a61 7589 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7590
8ac5a6d5 7591 assert_panel_unlocked(dev_priv, pipe);
652c393a 7592
dc257cf1 7593 dpll = I915_READ(dpll_reg);
652c393a
JB		 7594 dpll |= DISPLAY_RATE_SELECT_FPA1;
7595 I915_WRITE(dpll_reg, dpll);
9d0498a2 7596 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7597 dpll = I915_READ(dpll_reg);
7598 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7599 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7600 }
7601
7602}
7603
f047e395
CW		 7604void intel_mark_busy(struct drm_device *dev)
7605{
c67a470b
PZ		 7606 struct drm_i915_private *dev_priv = dev->dev_private;
7607
7608 hsw_package_c8_gpu_busy(dev_priv);
7609 i915_update_gfx_val(dev_priv);
f047e395
CW		 7610}
7611
7612void intel_mark_idle(struct drm_device *dev)
652c393a 7613{
c67a470b 7614 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7615 struct drm_crtc *crtc;
652c393a 7616
c67a470b
PZ		 7617 hsw_package_c8_gpu_idle(dev_priv);
7618
652c393a
JB		 7619 if (!i915_powersave)
7620 return;
7621
652c393a 7622 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7623 if (!crtc->fb)
7624 continue;
7625
725a5b54 7626 intel_decrease_pllclock(crtc);
652c393a 7627 }
652c393a
JB		 7628}
7629
c65355bb
CW		 7630void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7631 struct intel_ring_buffer *ring)
652c393a 7632{
f047e395
CW		 7633 struct drm_device *dev = obj->base.dev;
7634 struct drm_crtc *crtc;
652c393a 7635
f047e395 7636 if (!i915_powersave)
acb87dfb
CW		 7637 return;
7638
652c393a
JB		 7639 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7640 if (!crtc->fb)
7641 continue;
7642
c65355bb
CW		 7643 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7644 continue;
7645
7646 intel_increase_pllclock(crtc);
7647 if (ring && intel_fbc_enabled(dev))
7648 ring->fbc_dirty = true;
652c393a
JB		 7649 }
7650}
7651
79e53945
JB		 7652static void intel_crtc_destroy(struct drm_crtc *crtc)
7653{
7654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7655 struct drm_device *dev = crtc->dev;
7656 struct intel_unpin_work *work;
7657 unsigned long flags;
7658
7659 spin_lock_irqsave(&dev->event_lock, flags);
7660 work = intel_crtc->unpin_work;
7661 intel_crtc->unpin_work = NULL;
7662 spin_unlock_irqrestore(&dev->event_lock, flags);
7663
7664 if (work) {
7665 cancel_work_sync(&work->work);
7666 kfree(work);
7667 }
79e53945 7668
40ccc72b
MK		 7669 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7670
79e53945 7671 drm_crtc_cleanup(crtc);
67e77c5a 7672
79e53945
JB		 7673 kfree(intel_crtc);
7674}
7675
6b95a207
KH		 7676static void intel_unpin_work_fn(struct work_struct *__work)
7677{
7678 struct intel_unpin_work *work =
7679 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7680 struct drm_device *dev = work->crtc->dev;
6b95a207 7681
b4a98e57 7682 mutex_lock(&dev->struct_mutex);
1690e1eb 7683 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7684 drm_gem_object_unreference(&work->pending_flip_obj->base);
7685 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7686
b4a98e57
CW		 7687 intel_update_fbc(dev);
7688 mutex_unlock(&dev->struct_mutex);
7689
7690 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7691 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7692
6b95a207
KH		 7693 kfree(work);
7694}
7695
1afe3e9d 7696static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7697 struct drm_crtc *crtc)
6b95a207
KH		 7698{
7699 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7701 struct intel_unpin_work *work;
6b95a207
KH		 7702 unsigned long flags;
7703
7704 /* Ignore early vblank irqs */
7705 if (intel_crtc == NULL)
7706 return;
7707
7708 spin_lock_irqsave(&dev->event_lock, flags);
7709 work = intel_crtc->unpin_work;
e7d841ca
CW		 7710
7711 /* Ensure we don't miss a work->pending update ... */
7712 smp_rmb();
7713
7714 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7715 spin_unlock_irqrestore(&dev->event_lock, flags);
7716 return;
7717 }
7718
e7d841ca
CW		 7719 /* and that the unpin work is consistent wrt ->pending. */
7720 smp_rmb();
7721
6b95a207 7722 intel_crtc->unpin_work = NULL;
6b95a207 7723
45a066eb
RC		 7724 if (work->event)
7725 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7726
0af7e4df
MK		 7727 drm_vblank_put(dev, intel_crtc->pipe);
7728
6b95a207
KH		 7729 spin_unlock_irqrestore(&dev->event_lock, flags);
7730
2c10d571 7731 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7732
7733 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7734
7735 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7736}
7737
1afe3e9d
JB		 7738void intel_finish_page_flip(struct drm_device *dev, int pipe)
7739{
7740 drm_i915_private_t *dev_priv = dev->dev_private;
7741 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7742
49b14a5c 7743 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7744}
7745
7746void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7747{
7748 drm_i915_private_t *dev_priv = dev->dev_private;
7749 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7750
49b14a5c 7751 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7752}
7753
6b95a207
KH		 7754void intel_prepare_page_flip(struct drm_device *dev, int plane)
7755{
7756 drm_i915_private_t *dev_priv = dev->dev_private;
7757 struct intel_crtc *intel_crtc =
7758 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7759 unsigned long flags;
7760
e7d841ca
CW		 7761 /* NB: An MMIO update of the plane base pointer will also
7762 * generate a page-flip completion irq, i.e. every modeset
7763 * is also accompanied by a spurious intel_prepare_page_flip().
7764 */
6b95a207 7765 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7766 if (intel_crtc->unpin_work)
7767 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7768 spin_unlock_irqrestore(&dev->event_lock, flags);
7769}
7770
e7d841ca
CW		 7771inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7772{
7773 /* Ensure that the work item is consistent when activating it ... */
7774 smp_wmb();
7775 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7776 /* and that it is marked active as soon as the irq could fire. */
7777 smp_wmb();
7778}
7779
8c9f3aaf
JB		 7780static int intel_gen2_queue_flip(struct drm_device *dev,
7781 struct drm_crtc *crtc,
7782 struct drm_framebuffer *fb,
ed8d1975
KP		 7783 struct drm_i915_gem_object *obj,
7784 uint32_t flags)
8c9f3aaf
JB		 7785{
7786 struct drm_i915_private *dev_priv = dev->dev_private;
7787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7788 u32 flip_mask;
6d90c952 7789 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7790 int ret;
7791
6d90c952 7792 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7793 if (ret)
83d4092b 7794 goto err;
8c9f3aaf 7795
6d90c952 7796 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7797 if (ret)
83d4092b 7798 goto err_unpin;
8c9f3aaf
JB		 7799
7800 /* Can't queue multiple flips, so wait for the previous
7801 * one to finish before executing the next.
7802 */
7803 if (intel_crtc->plane)
7804 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7805 else
7806 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7807 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7808 intel_ring_emit(ring, MI_NOOP);
7809 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7810 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7811 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7812 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7813 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7814
7815 intel_mark_page_flip_active(intel_crtc);
09246732 7816 __intel_ring_advance(ring);
83d4092b
CW		 7817 return 0;
7818
7819err_unpin:
7820 intel_unpin_fb_obj(obj);
7821err:
8c9f3aaf
JB		 7822 return ret;
7823}
7824
7825static int intel_gen3_queue_flip(struct drm_device *dev,
7826 struct drm_crtc *crtc,
7827 struct drm_framebuffer *fb,
ed8d1975
KP		 7828 struct drm_i915_gem_object *obj,
7829 uint32_t flags)
8c9f3aaf
JB		 7830{
7831 struct drm_i915_private *dev_priv = dev->dev_private;
7832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7833 u32 flip_mask;
6d90c952 7834 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7835 int ret;
7836
6d90c952 7837 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7838 if (ret)
83d4092b 7839 goto err;
8c9f3aaf 7840
6d90c952 7841 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7842 if (ret)
83d4092b 7843 goto err_unpin;
8c9f3aaf
JB		 7844
7845 if (intel_crtc->plane)
7846 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7847 else
7848 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7849 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7850 intel_ring_emit(ring, MI_NOOP);
7851 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7852 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7853 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7854 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7855 intel_ring_emit(ring, MI_NOOP);
7856
e7d841ca 7857 intel_mark_page_flip_active(intel_crtc);
09246732 7858 __intel_ring_advance(ring);
83d4092b
CW		 7859 return 0;
7860
7861err_unpin:
7862 intel_unpin_fb_obj(obj);
7863err:
8c9f3aaf
JB		 7864 return ret;
7865}
7866
7867static int intel_gen4_queue_flip(struct drm_device *dev,
7868 struct drm_crtc *crtc,
7869 struct drm_framebuffer *fb,
ed8d1975
KP		 7870 struct drm_i915_gem_object *obj,
7871 uint32_t flags)
8c9f3aaf
JB		 7872{
7873 struct drm_i915_private *dev_priv = dev->dev_private;
7874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7875 uint32_t pf, pipesrc;
6d90c952 7876 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7877 int ret;
7878
6d90c952 7879 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7880 if (ret)
83d4092b 7881 goto err;
8c9f3aaf 7882
6d90c952 7883 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7884 if (ret)
83d4092b 7885 goto err_unpin;
8c9f3aaf
JB		 7886
7887 /* i965+ uses the linear or tiled offsets from the
7888 * Display Registers (which do not change across a page-flip)
7889 * so we need only reprogram the base address.
7890 */
6d90c952
DV		 7891 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7892 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7893 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7894 intel_ring_emit(ring,
f343c5f6 7895 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7896 obj->tiling_mode);
8c9f3aaf
JB		 7897
7898 /* XXX Enabling the panel-fitter across page-flip is so far
7899 * untested on non-native modes, so ignore it for now.
7900 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7901 */
7902 pf = 0;
7903 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7904 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7905
7906 intel_mark_page_flip_active(intel_crtc);
09246732 7907 __intel_ring_advance(ring);
83d4092b
CW		 7908 return 0;
7909
7910err_unpin:
7911 intel_unpin_fb_obj(obj);
7912err:
8c9f3aaf
JB		 7913 return ret;
7914}
7915
7916static int intel_gen6_queue_flip(struct drm_device *dev,
7917 struct drm_crtc *crtc,
7918 struct drm_framebuffer *fb,
ed8d1975
KP		 7919 struct drm_i915_gem_object *obj,
7920 uint32_t flags)
8c9f3aaf
JB		 7921{
7922 struct drm_i915_private *dev_priv = dev->dev_private;
7923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7924 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7925 uint32_t pf, pipesrc;
7926 int ret;
7927
6d90c952 7928 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7929 if (ret)
83d4092b 7930 goto err;
8c9f3aaf 7931
6d90c952 7932 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7933 if (ret)
83d4092b 7934 goto err_unpin;
8c9f3aaf 7935
6d90c952
DV		 7936 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7937 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7938 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7939 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7940
dc257cf1
DV		 7941 /* Contrary to the suggestions in the documentation,
7942 * "Enable Panel Fitter" does not seem to be required when page
7943 * flipping with a non-native mode, and worse causes a normal
7944 * modeset to fail.
7945 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7946 */
7947 pf = 0;
8c9f3aaf 7948 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7949 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7950
7951 intel_mark_page_flip_active(intel_crtc);
09246732 7952 __intel_ring_advance(ring);
83d4092b
CW		 7953 return 0;
7954
7955err_unpin:
7956 intel_unpin_fb_obj(obj);
7957err:
8c9f3aaf
JB		 7958 return ret;
7959}
7960
7c9017e5
JB		 7961static int intel_gen7_queue_flip(struct drm_device *dev,
7962 struct drm_crtc *crtc,
7963 struct drm_framebuffer *fb,
ed8d1975
KP		 7964 struct drm_i915_gem_object *obj,
7965 uint32_t flags)
7c9017e5
JB		 7966{
7967 struct drm_i915_private *dev_priv = dev->dev_private;
7968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7969 struct intel_ring_buffer *ring;
cb05d8de 7970 uint32_t plane_bit = 0;
ffe74d75
CW		 7971 int len, ret;
7972
7973 ring = obj->ring;
7974 if (ring == NULL || ring->id != RCS)
7975 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7976
7977 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7978 if (ret)
83d4092b 7979 goto err;
7c9017e5 7980
cb05d8de
DV		 7981 switch(intel_crtc->plane) {
7982 case PLANE_A:
7983 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7984 break;
7985 case PLANE_B:
7986 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7987 break;
7988 case PLANE_C:
7989 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7990 break;
7991 default:
7992 WARN_ONCE(1, "unknown plane in flip command\n");
7993 ret = -ENODEV;
ab3951eb 7994 goto err_unpin;
cb05d8de
DV		 7995 }
7996
ffe74d75
CW		 7997 len = 4;
7998 if (ring->id == RCS)
7999 len += 6;
8000
8001 ret = intel_ring_begin(ring, len);
7c9017e5 8002 if (ret)
83d4092b 8003 goto err_unpin;
7c9017e5 8004
ffe74d75
CW		 8005 /* Unmask the flip-done completion message. Note that the bspec says that
8006 * we should do this for both the BCS and RCS, and that we must not unmask
8007 * more than one flip event at any time (or ensure that one flip message
8008 * can be sent by waiting for flip-done prior to queueing new flips).
8009 * Experimentation says that BCS works despite DERRMR masking all
8010 * flip-done completion events and that unmasking all planes at once
8011 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8012 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8013 */
8014 if (ring->id == RCS) {
8015 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8016 intel_ring_emit(ring, DERRMR);
8017 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8018 DERRMR_PIPEB_PRI_FLIP_DONE |
8019 DERRMR_PIPEC_PRI_FLIP_DONE));
8020 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8021 intel_ring_emit(ring, DERRMR);
8022 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8023 }
8024
cb05d8de 8025 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8026 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8027 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8028 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8029
8030 intel_mark_page_flip_active(intel_crtc);
09246732 8031 __intel_ring_advance(ring);
83d4092b
CW		 8032 return 0;
8033
8034err_unpin:
8035 intel_unpin_fb_obj(obj);
8036err:
7c9017e5
JB		 8037 return ret;
8038}
8039
8c9f3aaf
JB		 8040static int intel_default_queue_flip(struct drm_device *dev,
8041 struct drm_crtc *crtc,
8042 struct drm_framebuffer *fb,
ed8d1975
KP		 8043 struct drm_i915_gem_object *obj,
8044 uint32_t flags)
8c9f3aaf
JB		 8045{
8046 return -ENODEV;
8047}
8048
6b95a207
KH		 8049static int intel_crtc_page_flip(struct drm_crtc *crtc,
8050 struct drm_framebuffer *fb,
ed8d1975
KP		 8051 struct drm_pending_vblank_event *event,
8052 uint32_t page_flip_flags)
6b95a207
KH		 8053{
8054 struct drm_device *dev = crtc->dev;
8055 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8056 struct drm_framebuffer *old_fb = crtc->fb;
8057 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8059 struct intel_unpin_work *work;
8c9f3aaf 8060 unsigned long flags;
52e68630 8061 int ret;
6b95a207 8062
e6a595d2
VS		 8063 /* Can't change pixel format via MI display flips. */
8064 if (fb->pixel_format != crtc->fb->pixel_format)
8065 return -EINVAL;
8066
8067 /*
8068 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8069 * Note that pitch changes could also affect these register.
8070 */
8071 if (INTEL_INFO(dev)->gen > 3 &&
8072 (fb->offsets[0] != crtc->fb->offsets[0] ||
8073 fb->pitches[0] != crtc->fb->pitches[0]))
8074 return -EINVAL;
8075
6b95a207
KH		 8076 work = kzalloc(sizeof *work, GFP_KERNEL);
8077 if (work == NULL)
8078 return -ENOMEM;
8079
6b95a207 8080 work->event = event;
b4a98e57 8081 work->crtc = crtc;
4a35f83b 8082 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8083 INIT_WORK(&work->work, intel_unpin_work_fn);
8084
7317c75e
JB		 8085 ret = drm_vblank_get(dev, intel_crtc->pipe);
8086 if (ret)
8087 goto free_work;
8088
6b95a207
KH		 8089 /* We borrow the event spin lock for protecting unpin_work */
8090 spin_lock_irqsave(&dev->event_lock, flags);
8091 if (intel_crtc->unpin_work) {
8092 spin_unlock_irqrestore(&dev->event_lock, flags);
8093 kfree(work);
7317c75e 8094 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8095
8096 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8097 return -EBUSY;
8098 }
8099 intel_crtc->unpin_work = work;
8100 spin_unlock_irqrestore(&dev->event_lock, flags);
8101
b4a98e57
CW		 8102 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8103 flush_workqueue(dev_priv->wq);
8104
79158103
CW		 8105 ret = i915_mutex_lock_interruptible(dev);
8106 if (ret)
8107 goto cleanup;
6b95a207 8108
75dfca80 8109 /* Reference the objects for the scheduled work. */
05394f39
CW		 8110 drm_gem_object_reference(&work->old_fb_obj->base);
8111 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8112
8113 crtc->fb = fb;
96b099fd 8114
e1f99ce6 8115 work->pending_flip_obj = obj;
e1f99ce6 8116
4e5359cd
SF		 8117 work->enable_stall_check = true;
8118
b4a98e57 8119 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8120 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8121
ed8d1975 8122 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8123 if (ret)
8124 goto cleanup_pending;
6b95a207 8125
7782de3b 8126 intel_disable_fbc(dev);
c65355bb 8127 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8128 mutex_unlock(&dev->struct_mutex);
8129
e5510fac
JB		 8130 trace_i915_flip_request(intel_crtc->plane, obj);
8131
6b95a207 8132 return 0;
96b099fd 8133
8c9f3aaf 8134cleanup_pending:
b4a98e57 8135 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8136 crtc->fb = old_fb;
05394f39
CW		 8137 drm_gem_object_unreference(&work->old_fb_obj->base);
8138 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8139 mutex_unlock(&dev->struct_mutex);
8140
79158103 8141cleanup:
96b099fd
CW		 8142 spin_lock_irqsave(&dev->event_lock, flags);
8143 intel_crtc->unpin_work = NULL;
8144 spin_unlock_irqrestore(&dev->event_lock, flags);
8145
7317c75e
JB		 8146 drm_vblank_put(dev, intel_crtc->pipe);
8147free_work:
96b099fd
CW		 8148 kfree(work);
8149
8150 return ret;
6b95a207
KH		 8151}
8152
f6e5b160 8153static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8154 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8155 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8156};
8157
50f56119
DV		 8158static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8159 struct drm_crtc *crtc)
8160{
8161 struct drm_device *dev;
8162 struct drm_crtc *tmp;
8163 int crtc_mask = 1;
47f1c6c9 8164
50f56119 8165 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8166
50f56119 8167 dev = crtc->dev;
47f1c6c9 8168
50f56119
DV		 8169 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8170 if (tmp == crtc)
8171 break;
8172 crtc_mask <<= 1;
8173 }
47f1c6c9 8174
50f56119
DV		 8175 if (encoder->possible_crtcs & crtc_mask)
8176 return true;
8177 return false;
47f1c6c9 8178}
79e53945 8179
9a935856
DV		 8180/**
8181 * intel_modeset_update_staged_output_state
8182 *
8183 * Updates the staged output configuration state, e.g. after we've read out the
8184 * current hw state.
8185 */
8186static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8187{
9a935856
DV		 8188 struct intel_encoder *encoder;
8189 struct intel_connector *connector;
f6e5b160 8190
9a935856
DV		 8191 list_for_each_entry(connector, &dev->mode_config.connector_list,
8192 base.head) {
8193 connector->new_encoder =
8194 to_intel_encoder(connector->base.encoder);
8195 }
f6e5b160 8196
9a935856
DV		 8197 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8198 base.head) {
8199 encoder->new_crtc =
8200 to_intel_crtc(encoder->base.crtc);
8201 }
f6e5b160
CW		 8202}
8203
9a935856
DV		 8204/**
8205 * intel_modeset_commit_output_state
8206 *
8207 * This function copies the stage display pipe configuration to the real one.
8208 */
8209static void intel_modeset_commit_output_state(struct drm_device *dev)
8210{
8211 struct intel_encoder *encoder;
8212 struct intel_connector *connector;
f6e5b160 8213
9a935856
DV		 8214 list_for_each_entry(connector, &dev->mode_config.connector_list,
8215 base.head) {
8216 connector->base.encoder = &connector->new_encoder->base;
8217 }
f6e5b160 8218
9a935856
DV		 8219 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8220 base.head) {
8221 encoder->base.crtc = &encoder->new_crtc->base;
8222 }
8223}
8224
050f7aeb
DV		 8225static void
8226connected_sink_compute_bpp(struct intel_connector * connector,
8227 struct intel_crtc_config *pipe_config)
8228{
8229 int bpp = pipe_config->pipe_bpp;
8230
8231 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8232 connector->base.base.id,
8233 drm_get_connector_name(&connector->base));
8234
8235 /* Don't use an invalid EDID bpc value */
8236 if (connector->base.display_info.bpc &&
8237 connector->base.display_info.bpc * 3 < bpp) {
8238 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8239 bpp, connector->base.display_info.bpc*3);
8240 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8241 }
8242
8243 /* Clamp bpp to 8 on screens without EDID 1.4 */
8244 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8245 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8246 bpp);
8247 pipe_config->pipe_bpp = 24;
8248 }
8249}
8250
4e53c2e0 8251static int
050f7aeb
DV		 8252compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8253 struct drm_framebuffer *fb,
8254 struct intel_crtc_config *pipe_config)
4e53c2e0 8255{
050f7aeb
DV		 8256 struct drm_device *dev = crtc->base.dev;
8257 struct intel_connector *connector;
4e53c2e0
DV		 8258 int bpp;
8259
d42264b1
DV		 8260 switch (fb->pixel_format) {
8261 case DRM_FORMAT_C8:
4e53c2e0
DV		 8262 bpp = 8*3; /* since we go through a colormap */
8263 break;
d42264b1
DV		 8264 case DRM_FORMAT_XRGB1555:
8265 case DRM_FORMAT_ARGB1555:
8266 /* checked in intel_framebuffer_init already */
8267 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8268 return -EINVAL;
8269 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8270 bpp = 6*3; /* min is 18bpp */
8271 break;
d42264b1
DV		 8272 case DRM_FORMAT_XBGR8888:
8273 case DRM_FORMAT_ABGR8888:
8274 /* checked in intel_framebuffer_init already */
8275 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8276 return -EINVAL;
8277 case DRM_FORMAT_XRGB8888:
8278 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8279 bpp = 8*3;
8280 break;
d42264b1
DV		 8281 case DRM_FORMAT_XRGB2101010:
8282 case DRM_FORMAT_ARGB2101010:
8283 case DRM_FORMAT_XBGR2101010:
8284 case DRM_FORMAT_ABGR2101010:
8285 /* checked in intel_framebuffer_init already */
8286 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8287 return -EINVAL;
4e53c2e0
DV		 8288 bpp = 10*3;
8289 break;
baba133a 8290 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8291 default:
8292 DRM_DEBUG_KMS("unsupported depth\n");
8293 return -EINVAL;
8294 }
8295
4e53c2e0
DV		 8296 pipe_config->pipe_bpp = bpp;
8297
8298 /* Clamp display bpp to EDID value */
8299 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8300 base.head) {
1b829e05
DV		 8301 if (!connector->new_encoder ||
8302 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8303 continue;
8304
050f7aeb 8305 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8306 }
8307
8308 return bpp;
8309}
8310
c0b03411
DV		 8311static void intel_dump_pipe_config(struct intel_crtc *crtc,
8312 struct intel_crtc_config *pipe_config,
8313 const char *context)
8314{
8315 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8316 context, pipe_name(crtc->pipe));
8317
8318 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8319 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8320 pipe_config->pipe_bpp, pipe_config->dither);
8321 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8322 pipe_config->has_pch_encoder,
8323 pipe_config->fdi_lanes,
8324 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8325 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8326 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8327 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8328 pipe_config->has_dp_encoder,
8329 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8330 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8331 pipe_config->dp_m_n.tu);
c0b03411
DV		 8332 DRM_DEBUG_KMS("requested mode:\n");
8333 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8334 DRM_DEBUG_KMS("adjusted mode:\n");
8335 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
d71b8d4a 8336 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8337 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8338 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8339 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8340 pipe_config->gmch_pfit.control,
8341 pipe_config->gmch_pfit.pgm_ratios,
8342 pipe_config->gmch_pfit.lvds_border_bits);
8343 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8344 pipe_config->pch_pfit.pos,
8345 pipe_config->pch_pfit.size);
42db64ef 8346 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8347 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8348}
8349
accfc0c5
DV		 8350static bool check_encoder_cloning(struct drm_crtc *crtc)
8351{
8352 int num_encoders = 0;
8353 bool uncloneable_encoders = false;
8354 struct intel_encoder *encoder;
8355
8356 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8357 base.head) {
8358 if (&encoder->new_crtc->base != crtc)
8359 continue;
8360
8361 num_encoders++;
8362 if (!encoder->cloneable)
8363 uncloneable_encoders = true;
8364 }
8365
8366 return !(num_encoders > 1 && uncloneable_encoders);
8367}
8368
b8cecdf5
DV		 8369static struct intel_crtc_config *
8370intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8371 struct drm_framebuffer *fb,
b8cecdf5 8372 struct drm_display_mode *mode)
ee7b9f93 8373{
7758a113 8374 struct drm_device *dev = crtc->dev;
7758a113 8375 struct intel_encoder *encoder;
b8cecdf5 8376 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8377 int plane_bpp, ret = -EINVAL;
8378 bool retry = true;
ee7b9f93 8379
accfc0c5
DV		 8380 if (!check_encoder_cloning(crtc)) {
8381 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8382 return ERR_PTR(-EINVAL);
8383 }
8384
b8cecdf5
DV		 8385 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8386 if (!pipe_config)
7758a113
DV		 8387 return ERR_PTR(-ENOMEM);
8388
b8cecdf5
DV		 8389 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8390 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd
VS		 8391
8392 pipe_config->pipe_src_w = mode->hdisplay;
8393 pipe_config->pipe_src_h = mode->vdisplay;
8394
e143a21c
DV		 8395 pipe_config->cpu_transcoder =
8396 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8397 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8398
2960bc9c
ID		 8399 /*
8400 * Sanitize sync polarity flags based on requested ones. If neither
8401 * positive or negative polarity is requested, treat this as meaning
8402 * negative polarity.
8403 */
8404 if (!(pipe_config->adjusted_mode.flags &
8405 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8406 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8407
8408 if (!(pipe_config->adjusted_mode.flags &
8409 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8410 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8411
050f7aeb
DV		 8412 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8413 * plane pixel format and any sink constraints into account. Returns the
8414 * source plane bpp so that dithering can be selected on mismatches
8415 * after encoders and crtc also have had their say. */
8416 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8417 fb, pipe_config);
4e53c2e0
DV		 8418 if (plane_bpp < 0)
8419 goto fail;
8420
e29c22c0 8421encoder_retry:
ef1b460d 8422 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8423 pipe_config->port_clock = 0;
ef1b460d 8424 pipe_config->pixel_multiplier = 1;
ff9a6750 8425
135c81b8
DV		 8426 /* Fill in default crtc timings, allow encoders to overwrite them. */
8427 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8428
7758a113
DV		 8429 /* Pass our mode to the connectors and the CRTC to give them a chance to
8430 * adjust it according to limitations or connector properties, and also
8431 * a chance to reject the mode entirely.
47f1c6c9 8432 */
7758a113
DV		 8433 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8434 base.head) {
47f1c6c9 8435
7758a113
DV		 8436 if (&encoder->new_crtc->base != crtc)
8437 continue;
7ae89233 8438
efea6e8e
DV		 8439 if (!(encoder->compute_config(encoder, pipe_config))) {
8440 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8441 goto fail;
8442 }
ee7b9f93 8443 }
47f1c6c9 8444
ff9a6750
DV		 8445 /* Set default port clock if not overwritten by the encoder. Needs to be
8446 * done afterwards in case the encoder adjusts the mode. */
8447 if (!pipe_config->port_clock)
3c52f4eb
VS		 8448 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8449 pipe_config->pixel_multiplier;
ff9a6750 8450
a43f6e0f 8451 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8452 if (ret < 0) {
7758a113
DV		 8453 DRM_DEBUG_KMS("CRTC fixup failed\n");
8454 goto fail;
ee7b9f93 8455 }
e29c22c0
DV		 8456
8457 if (ret == RETRY) {
8458 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8459 ret = -EINVAL;
8460 goto fail;
8461 }
8462
8463 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8464 retry = false;
8465 goto encoder_retry;
8466 }
8467
4e53c2e0
DV		 8468 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8469 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8470 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8471
b8cecdf5 8472 return pipe_config;
7758a113 8473fail:
b8cecdf5 8474 kfree(pipe_config);
e29c22c0 8475 return ERR_PTR(ret);
ee7b9f93 8476}
47f1c6c9 8477
e2e1ed41
DV		 8478/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8479 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8480static void
8481intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8482 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8483{
8484 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8485 struct drm_device *dev = crtc->dev;
8486 struct intel_encoder *encoder;
8487 struct intel_connector *connector;
8488 struct drm_crtc *tmp_crtc;
79e53945 8489
e2e1ed41 8490 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8491
e2e1ed41
DV		 8492 /* Check which crtcs have changed outputs connected to them, these need
8493 * to be part of the prepare_pipes mask. We don't (yet) support global
8494 * modeset across multiple crtcs, so modeset_pipes will only have one
8495 * bit set at most. */
8496 list_for_each_entry(connector, &dev->mode_config.connector_list,
8497 base.head) {
8498 if (connector->base.encoder == &connector->new_encoder->base)
8499 continue;
79e53945 8500
e2e1ed41
DV		 8501 if (connector->base.encoder) {
8502 tmp_crtc = connector->base.encoder->crtc;
8503
8504 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8505 }
8506
8507 if (connector->new_encoder)
8508 *prepare_pipes |=
8509 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8510 }
8511
e2e1ed41
DV		 8512 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8513 base.head) {
8514 if (encoder->base.crtc == &encoder->new_crtc->base)
8515 continue;
8516
8517 if (encoder->base.crtc) {
8518 tmp_crtc = encoder->base.crtc;
8519
8520 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8521 }
8522
8523 if (encoder->new_crtc)
8524 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8525 }
8526
e2e1ed41
DV		 8527 /* Check for any pipes that will be fully disabled ... */
8528 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8529 base.head) {
8530 bool used = false;
22fd0fab 8531
e2e1ed41
DV		 8532 /* Don't try to disable disabled crtcs. */
8533 if (!intel_crtc->base.enabled)
8534 continue;
7e7d76c3 8535
e2e1ed41
DV		 8536 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8537 base.head) {
8538 if (encoder->new_crtc == intel_crtc)
8539 used = true;
8540 }
8541
8542 if (!used)
8543 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8544 }
8545
e2e1ed41
DV		 8546
8547 /* set_mode is also used to update properties on life display pipes. */
8548 intel_crtc = to_intel_crtc(crtc);
8549 if (crtc->enabled)
8550 *prepare_pipes |= 1 << intel_crtc->pipe;
8551
b6c5164d
DV		 8552 /*
8553 * For simplicity do a full modeset on any pipe where the output routing
8554 * changed. We could be more clever, but that would require us to be
8555 * more careful with calling the relevant encoder->mode_set functions.
8556 */
e2e1ed41
DV		 8557 if (*prepare_pipes)
8558 *modeset_pipes = *prepare_pipes;
8559
8560 /* ... and mask these out. */
8561 *modeset_pipes &= ~(*disable_pipes);
8562 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8563
8564 /*
8565 * HACK: We don't (yet) fully support global modesets. intel_set_config
8566 * obies this rule, but the modeset restore mode of
8567 * intel_modeset_setup_hw_state does not.
8568 */
8569 *modeset_pipes &= 1 << intel_crtc->pipe;
8570 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8571
8572 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8573 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8574}
79e53945 8575
ea9d758d 8576static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8577{
ea9d758d 8578 struct drm_encoder *encoder;
f6e5b160 8579 struct drm_device *dev = crtc->dev;
f6e5b160 8580
ea9d758d
DV		 8581 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8582 if (encoder->crtc == crtc)
8583 return true;
8584
8585 return false;
8586}
8587
8588static void
8589intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8590{
8591 struct intel_encoder *intel_encoder;
8592 struct intel_crtc *intel_crtc;
8593 struct drm_connector *connector;
8594
8595 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8596 base.head) {
8597 if (!intel_encoder->base.crtc)
8598 continue;
8599
8600 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8601
8602 if (prepare_pipes & (1 << intel_crtc->pipe))
8603 intel_encoder->connectors_active = false;
8604 }
8605
8606 intel_modeset_commit_output_state(dev);
8607
8608 /* Update computed state. */
8609 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8610 base.head) {
8611 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8612 }
8613
8614 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8615 if (!connector->encoder || !connector->encoder->crtc)
8616 continue;
8617
8618 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8619
8620 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8621 struct drm_property *dpms_property =
8622 dev->mode_config.dpms_property;
8623
ea9d758d 8624 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8625 drm_object_property_set_value(&connector->base,
68d34720
DV		 8626 dpms_property,
8627 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8628
8629 intel_encoder = to_intel_encoder(connector->encoder);
8630 intel_encoder->connectors_active = true;
8631 }
8632 }
8633
8634}
8635
3bd26263 8636static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8637{
3bd26263 8638 int diff;
f1f644dc
JB		 8639
8640 if (clock1 == clock2)
8641 return true;
8642
8643 if (!clock1 || !clock2)
8644 return false;
8645
8646 diff = abs(clock1 - clock2);
8647
8648 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8649 return true;
8650
8651 return false;
8652}
8653
25c5b266
DV		 8654#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8655 list_for_each_entry((intel_crtc), \
8656 &(dev)->mode_config.crtc_list, \
8657 base.head) \
0973f18f 8658 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8659
0e8ffe1b 8660static bool
2fa2fe9a
DV		 8661intel_pipe_config_compare(struct drm_device *dev,
8662 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8663 struct intel_crtc_config *pipe_config)
8664{
66e985c0
DV		 8665#define PIPE_CONF_CHECK_X(name) \
8666 if (current_config->name != pipe_config->name) { \
8667 DRM_ERROR("mismatch in " #name " " \
8668 "(expected 0x%08x, found 0x%08x)\n", \
8669 current_config->name, \
8670 pipe_config->name); \
8671 return false; \
8672 }
8673
08a24034
DV		 8674#define PIPE_CONF_CHECK_I(name) \
8675 if (current_config->name != pipe_config->name) { \
8676 DRM_ERROR("mismatch in " #name " " \
8677 "(expected %i, found %i)\n", \
8678 current_config->name, \
8679 pipe_config->name); \
8680 return false; \
88adfff1
DV		 8681 }
8682
1bd1bd80
DV		 8683#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8684 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8685 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8686 "(expected %i, found %i)\n", \
8687 current_config->name & (mask), \
8688 pipe_config->name & (mask)); \
8689 return false; \
8690 }
8691
5e550656
VS		 8692#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8693 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8694 DRM_ERROR("mismatch in " #name " " \
8695 "(expected %i, found %i)\n", \
8696 current_config->name, \
8697 pipe_config->name); \
8698 return false; \
8699 }
8700
bb760063
DV		 8701#define PIPE_CONF_QUIRK(quirk) \
8702 ((current_config->quirks | pipe_config->quirks) & (quirk))
8703
eccb140b
DV		 8704 PIPE_CONF_CHECK_I(cpu_transcoder);
8705
08a24034
DV		 8706 PIPE_CONF_CHECK_I(has_pch_encoder);
8707 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8708 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8709 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8710 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8711 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8712 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8713
eb14cb74
VS		 8714 PIPE_CONF_CHECK_I(has_dp_encoder);
8715 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8716 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8717 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8718 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8719 PIPE_CONF_CHECK_I(dp_m_n.tu);
8720
1bd1bd80
DV		 8721 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8722 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8723 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8724 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8725 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8726 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8727
8728 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8729 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8730 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8731 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8732 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8733 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8734
c93f54cf 8735 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8736
1bd1bd80
DV		 8737 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8738 DRM_MODE_FLAG_INTERLACE);
8739
bb760063
DV		 8740 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8741 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8742 DRM_MODE_FLAG_PHSYNC);
8743 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8744 DRM_MODE_FLAG_NHSYNC);
8745 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8746 DRM_MODE_FLAG_PVSYNC);
8747 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8748 DRM_MODE_FLAG_NVSYNC);
8749 }
045ac3b5 8750
37327abd
VS		 8751 PIPE_CONF_CHECK_I(pipe_src_w);
8752 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8753
2fa2fe9a
DV		 8754 PIPE_CONF_CHECK_I(gmch_pfit.control);
8755 /* pfit ratios are autocomputed by the hw on gen4+ */
8756 if (INTEL_INFO(dev)->gen < 4)
8757 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8758 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8759 PIPE_CONF_CHECK_I(pch_pfit.pos);
8760 PIPE_CONF_CHECK_I(pch_pfit.size);
8761
42db64ef
PZ		 8762 PIPE_CONF_CHECK_I(ips_enabled);
8763
c0d43d62 8764 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8765 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8766 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8767 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8768 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8769
42571aef
VS		 8770 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8771 PIPE_CONF_CHECK_I(pipe_bpp);
8772
d71b8d4a 8773 if (!IS_HASWELL(dev)) {
5e550656 8774 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
d71b8d4a
VS		 8775 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8776 }
5e550656 8777
66e985c0 8778#undef PIPE_CONF_CHECK_X
08a24034 8779#undef PIPE_CONF_CHECK_I
1bd1bd80 8780#undef PIPE_CONF_CHECK_FLAGS
5e550656 8781#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8782#undef PIPE_CONF_QUIRK
88adfff1 8783
0e8ffe1b
DV		 8784 return true;
8785}
8786
91d1b4bd
DV		 8787static void
8788check_connector_state(struct drm_device *dev)
8af6cf88 8789{
8af6cf88
DV		 8790 struct intel_connector *connector;
8791
8792 list_for_each_entry(connector, &dev->mode_config.connector_list,
8793 base.head) {
8794 /* This also checks the encoder/connector hw state with the
8795 * ->get_hw_state callbacks. */
8796 intel_connector_check_state(connector);
8797
8798 WARN(&connector->new_encoder->base != connector->base.encoder,
8799 "connector's staged encoder doesn't match current encoder\n");
8800 }
91d1b4bd
DV		 8801}
8802
8803static void
8804check_encoder_state(struct drm_device *dev)
8805{
8806 struct intel_encoder *encoder;
8807 struct intel_connector *connector;
8af6cf88
DV		 8808
8809 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8810 base.head) {
8811 bool enabled = false;
8812 bool active = false;
8813 enum pipe pipe, tracked_pipe;
8814
8815 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8816 encoder->base.base.id,
8817 drm_get_encoder_name(&encoder->base));
8818
8819 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8820 "encoder's stage crtc doesn't match current crtc\n");
8821 WARN(encoder->connectors_active && !encoder->base.crtc,
8822 "encoder's active_connectors set, but no crtc\n");
8823
8824 list_for_each_entry(connector, &dev->mode_config.connector_list,
8825 base.head) {
8826 if (connector->base.encoder != &encoder->base)
8827 continue;
8828 enabled = true;
8829 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8830 active = true;
8831 }
8832 WARN(!!encoder->base.crtc != enabled,
8833 "encoder's enabled state mismatch "
8834 "(expected %i, found %i)\n",
8835 !!encoder->base.crtc, enabled);
8836 WARN(active && !encoder->base.crtc,
8837 "active encoder with no crtc\n");
8838
8839 WARN(encoder->connectors_active != active,
8840 "encoder's computed active state doesn't match tracked active state "
8841 "(expected %i, found %i)\n", active, encoder->connectors_active);
8842
8843 active = encoder->get_hw_state(encoder, &pipe);
8844 WARN(active != encoder->connectors_active,
8845 "encoder's hw state doesn't match sw tracking "
8846 "(expected %i, found %i)\n",
8847 encoder->connectors_active, active);
8848
8849 if (!encoder->base.crtc)
8850 continue;
8851
8852 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8853 WARN(active && pipe != tracked_pipe,
8854 "active encoder's pipe doesn't match"
8855 "(expected %i, found %i)\n",
8856 tracked_pipe, pipe);
8857
8858 }
91d1b4bd
DV		 8859}
8860
8861static void
8862check_crtc_state(struct drm_device *dev)
8863{
8864 drm_i915_private_t *dev_priv = dev->dev_private;
8865 struct intel_crtc *crtc;
8866 struct intel_encoder *encoder;
8867 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8868
8869 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8870 base.head) {
8871 bool enabled = false;
8872 bool active = false;
8873
045ac3b5
JB		 8874 memset(&pipe_config, 0, sizeof(pipe_config));
8875
8af6cf88
DV		 8876 DRM_DEBUG_KMS("[CRTC:%d]\n",
8877 crtc->base.base.id);
8878
8879 WARN(crtc->active && !crtc->base.enabled,
8880 "active crtc, but not enabled in sw tracking\n");
8881
8882 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8883 base.head) {
8884 if (encoder->base.crtc != &crtc->base)
8885 continue;
8886 enabled = true;
8887 if (encoder->connectors_active)
8888 active = true;
8889 }
6c49f241 8890
8af6cf88
DV		 8891 WARN(active != crtc->active,
8892 "crtc's computed active state doesn't match tracked active state "
8893 "(expected %i, found %i)\n", active, crtc->active);
8894 WARN(enabled != crtc->base.enabled,
8895 "crtc's computed enabled state doesn't match tracked enabled state "
8896 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8897
0e8ffe1b
DV		 8898 active = dev_priv->display.get_pipe_config(crtc,
8899 &pipe_config);
d62cf62a
DV		 8900
8901 /* hw state is inconsistent with the pipe A quirk */
8902 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8903 active = crtc->active;
8904
6c49f241
DV		 8905 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8906 base.head) {
3eaba51c 8907 enum pipe pipe;
6c49f241
DV		 8908 if (encoder->base.crtc != &crtc->base)
8909 continue;
3eaba51c
VS		 8910 if (encoder->get_config &&
8911 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8912 encoder->get_config(encoder, &pipe_config);
8913 }
8914
0e8ffe1b
DV		 8915 WARN(crtc->active != active,
8916 "crtc active state doesn't match with hw state "
8917 "(expected %i, found %i)\n", crtc->active, active);
8918
c0b03411
DV		 8919 if (active &&
8920 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8921 WARN(1, "pipe state doesn't match!\n");
8922 intel_dump_pipe_config(crtc, &pipe_config,
8923 "[hw state]");
8924 intel_dump_pipe_config(crtc, &crtc->config,
8925 "[sw state]");
8926 }
8af6cf88
DV		 8927 }
8928}
8929
91d1b4bd
DV		 8930static void
8931check_shared_dpll_state(struct drm_device *dev)
8932{
8933 drm_i915_private_t *dev_priv = dev->dev_private;
8934 struct intel_crtc *crtc;
8935 struct intel_dpll_hw_state dpll_hw_state;
8936 int i;
5358901f
DV		 8937
8938 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8939 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8940 int enabled_crtcs = 0, active_crtcs = 0;
8941 bool active;
8942
8943 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8944
8945 DRM_DEBUG_KMS("%s\n", pll->name);
8946
8947 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8948
8949 WARN(pll->active > pll->refcount,
8950 "more active pll users than references: %i vs %i\n",
8951 pll->active, pll->refcount);
8952 WARN(pll->active && !pll->on,
8953 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8954 WARN(pll->on && !pll->active,
8955 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8956 WARN(pll->on != active,
8957 "pll on state mismatch (expected %i, found %i)\n",
8958 pll->on, active);
8959
8960 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8961 base.head) {
8962 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8963 enabled_crtcs++;
8964 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8965 active_crtcs++;
8966 }
8967 WARN(pll->active != active_crtcs,
8968 "pll active crtcs mismatch (expected %i, found %i)\n",
8969 pll->active, active_crtcs);
8970 WARN(pll->refcount != enabled_crtcs,
8971 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8972 pll->refcount, enabled_crtcs);
66e985c0
DV		 8973
8974 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8975 sizeof(dpll_hw_state)),
8976 "pll hw state mismatch\n");
5358901f 8977 }
8af6cf88
DV		 8978}
8979
91d1b4bd
DV		 8980void
8981intel_modeset_check_state(struct drm_device *dev)
8982{
8983 check_connector_state(dev);
8984 check_encoder_state(dev);
8985 check_crtc_state(dev);
8986 check_shared_dpll_state(dev);
8987}
8988
18442d08
VS		 8989void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
8990 int dotclock)
8991{
8992 /*
8993 * FDI already provided one idea for the dotclock.
8994 * Yell if the encoder disagrees.
8995 */
8996 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
8997 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
8998 pipe_config->adjusted_mode.clock, dotclock);
8999}
9000
f30da187
DV		 9001static int __intel_set_mode(struct drm_crtc *crtc,
9002 struct drm_display_mode *mode,
9003 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9004{
9005 struct drm_device *dev = crtc->dev;
dbf2b54e 9006 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9007 struct drm_display_mode *saved_mode, *saved_hwmode;
9008 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9009 struct intel_crtc *intel_crtc;
9010 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9011 int ret = 0;
a6778b3c 9012
3ac18232 9013 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9014 if (!saved_mode)
9015 return -ENOMEM;
3ac18232 9016 saved_hwmode = saved_mode + 1;
a6778b3c 9017
e2e1ed41 9018 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9019 &prepare_pipes, &disable_pipes);
9020
3ac18232
TG		 9021 *saved_hwmode = crtc->hwmode;
9022 *saved_mode = crtc->mode;
a6778b3c 9023
25c5b266
DV		 9024 /* Hack: Because we don't (yet) support global modeset on multiple
9025 * crtcs, we don't keep track of the new mode for more than one crtc.
9026 * Hence simply check whether any bit is set in modeset_pipes in all the
9027 * pieces of code that are not yet converted to deal with mutliple crtcs
9028 * changing their mode at the same time. */
25c5b266 9029 if (modeset_pipes) {
4e53c2e0 9030 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9031 if (IS_ERR(pipe_config)) {
9032 ret = PTR_ERR(pipe_config);
9033 pipe_config = NULL;
9034
3ac18232 9035 goto out;
25c5b266 9036 }
c0b03411
DV		 9037 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9038 "[modeset]");
25c5b266 9039 }
a6778b3c 9040
460da916
DV		 9041 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9042 intel_crtc_disable(&intel_crtc->base);
9043
ea9d758d
DV		 9044 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9045 if (intel_crtc->base.enabled)
9046 dev_priv->display.crtc_disable(&intel_crtc->base);
9047 }
a6778b3c 9048
6c4c86f5
DV		 9049 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9050 * to set it here already despite that we pass it down the callchain.
f6e5b160 9051 */
b8cecdf5 9052 if (modeset_pipes) {
25c5b266 9053 crtc->mode = *mode;
b8cecdf5
DV		 9054 /* mode_set/enable/disable functions rely on a correct pipe
9055 * config. */
9056 to_intel_crtc(crtc)->config = *pipe_config;
9057 }
7758a113 9058
ea9d758d
DV		 9059 /* Only after disabling all output pipelines that will be changed can we
9060 * update the the output configuration. */
9061 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9062
47fab737
DV		 9063 if (dev_priv->display.modeset_global_resources)
9064 dev_priv->display.modeset_global_resources(dev);
9065
a6778b3c
DV		 9066 /* Set up the DPLL and any encoders state that needs to adjust or depend
9067 * on the DPLL.
f6e5b160 9068 */
25c5b266 9069 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9070 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9071 x, y, fb);
9072 if (ret)
9073 goto done;
a6778b3c
DV		 9074 }
9075
9076 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9077 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9078 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9079
25c5b266
DV		 9080 if (modeset_pipes) {
9081 /* Store real post-adjustment hardware mode. */
b8cecdf5 9082 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9083
25c5b266
DV		 9084 /* Calculate and store various constants which
9085 * are later needed by vblank and swap-completion
9086 * timestamping. They are derived from true hwmode.
9087 */
9088 drm_calc_timestamping_constants(crtc);
9089 }
a6778b3c
DV		 9090
9091 /* FIXME: add subpixel order */
9092done:
c0c36b94 9093 if (ret && crtc->enabled) {
3ac18232
TG		 9094 crtc->hwmode = *saved_hwmode;
9095 crtc->mode = *saved_mode;
a6778b3c
DV		 9096 }
9097
3ac18232 9098out:
b8cecdf5 9099 kfree(pipe_config);
3ac18232 9100 kfree(saved_mode);
a6778b3c 9101 return ret;
f6e5b160
CW		 9102}
9103
e7457a9a
DL		 9104static int intel_set_mode(struct drm_crtc *crtc,
9105 struct drm_display_mode *mode,
9106 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9107{
9108 int ret;
9109
9110 ret = __intel_set_mode(crtc, mode, x, y, fb);
9111
9112 if (ret == 0)
9113 intel_modeset_check_state(crtc->dev);
9114
9115 return ret;
9116}
9117
c0c36b94
CW		 9118void intel_crtc_restore_mode(struct drm_crtc *crtc)
9119{
9120 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9121}
9122
25c5b266
DV		 9123#undef for_each_intel_crtc_masked
9124
d9e55608
DV		 9125static void intel_set_config_free(struct intel_set_config *config)
9126{
9127 if (!config)
9128 return;
9129
1aa4b628
DV		 9130 kfree(config->save_connector_encoders);
9131 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9132 kfree(config);
9133}
9134
85f9eb71
DV		 9135static int intel_set_config_save_state(struct drm_device *dev,
9136 struct intel_set_config *config)
9137{
85f9eb71
DV		 9138 struct drm_encoder *encoder;
9139 struct drm_connector *connector;
9140 int count;
9141
1aa4b628
DV		 9142 config->save_encoder_crtcs =
9143 kcalloc(dev->mode_config.num_encoder,
9144 sizeof(struct drm_crtc *), GFP_KERNEL);
9145 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9146 return -ENOMEM;
9147
1aa4b628
DV		 9148 config->save_connector_encoders =
9149 kcalloc(dev->mode_config.num_connector,
9150 sizeof(struct drm_encoder *), GFP_KERNEL);
9151 if (!config->save_connector_encoders)
85f9eb71
DV		 9152 return -ENOMEM;
9153
9154 /* Copy data. Note that driver private data is not affected.
9155 * Should anything bad happen only the expected state is
9156 * restored, not the drivers personal bookkeeping.
9157 */
85f9eb71
DV		 9158 count = 0;
9159 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9160 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9161 }
9162
9163 count = 0;
9164 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9165 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9166 }
9167
9168 return 0;
9169}
9170
9171static void intel_set_config_restore_state(struct drm_device *dev,
9172 struct intel_set_config *config)
9173{
9a935856
DV		 9174 struct intel_encoder *encoder;
9175 struct intel_connector *connector;
85f9eb71
DV		 9176 int count;
9177
85f9eb71 9178 count = 0;
9a935856
DV		 9179 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9180 encoder->new_crtc =
9181 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9182 }
9183
9184 count = 0;
9a935856
DV		 9185 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9186 connector->new_encoder =
9187 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9188 }
9189}
9190
e3de42b6 9191static bool
2e57f47d 9192is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9193{
9194 int i;
9195
2e57f47d
CW		 9196 if (set->num_connectors == 0)
9197 return false;
9198
9199 if (WARN_ON(set->connectors == NULL))
9200 return false;
9201
9202 for (i = 0; i < set->num_connectors; i++)
9203 if (set->connectors[i]->encoder &&
9204 set->connectors[i]->encoder->crtc == set->crtc &&
9205 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9206 return true;
9207
9208 return false;
9209}
9210
5e2b584e
DV		 9211static void
9212intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9213 struct intel_set_config *config)
9214{
9215
9216 /* We should be able to check here if the fb has the same properties
9217 * and then just flip_or_move it */
2e57f47d
CW		 9218 if (is_crtc_connector_off(set)) {
9219 config->mode_changed = true;
e3de42b6 9220 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9221 /* If we have no fb then treat it as a full mode set */
9222 if (set->crtc->fb == NULL) {
319d9827
JB		 9223 struct intel_crtc *intel_crtc =
9224 to_intel_crtc(set->crtc);
9225
9226 if (intel_crtc->active && i915_fastboot) {
9227 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9228 config->fb_changed = true;
9229 } else {
9230 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9231 config->mode_changed = true;
9232 }
5e2b584e
DV		 9233 } else if (set->fb == NULL) {
9234 config->mode_changed = true;
72f4901e
DV		 9235 } else if (set->fb->pixel_format !=
9236 set->crtc->fb->pixel_format) {
5e2b584e 9237 config->mode_changed = true;
e3de42b6 9238 } else {
5e2b584e 9239 config->fb_changed = true;
e3de42b6 9240 }
5e2b584e
DV		 9241 }
9242
835c5873 9243 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9244 config->fb_changed = true;
9245
9246 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9247 DRM_DEBUG_KMS("modes are different, full mode set\n");
9248 drm_mode_debug_printmodeline(&set->crtc->mode);
9249 drm_mode_debug_printmodeline(set->mode);
9250 config->mode_changed = true;
9251 }
a1d95703
CW		 9252
9253 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9254 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9255}
9256
2e431051 9257static int
9a935856
DV		 9258intel_modeset_stage_output_state(struct drm_device *dev,
9259 struct drm_mode_set *set,
9260 struct intel_set_config *config)
50f56119 9261{
85f9eb71 9262 struct drm_crtc *new_crtc;
9a935856
DV		 9263 struct intel_connector *connector;
9264 struct intel_encoder *encoder;
f3f08572 9265 int ro;
50f56119 9266
9abdda74 9267 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9268 * of connectors. For paranoia, double-check this. */
9269 WARN_ON(!set->fb && (set->num_connectors != 0));
9270 WARN_ON(set->fb && (set->num_connectors == 0));
9271
9a935856
DV		 9272 list_for_each_entry(connector, &dev->mode_config.connector_list,
9273 base.head) {
9274 /* Otherwise traverse passed in connector list and get encoders
9275 * for them. */
50f56119 9276 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9277 if (set->connectors[ro] == &connector->base) {
9278 connector->new_encoder = connector->encoder;
50f56119
DV		 9279 break;
9280 }
9281 }
9282
9a935856
DV		 9283 /* If we disable the crtc, disable all its connectors. Also, if
9284 * the connector is on the changing crtc but not on the new
9285 * connector list, disable it. */
9286 if ((!set->fb || ro == set->num_connectors) &&
9287 connector->base.encoder &&
9288 connector->base.encoder->crtc == set->crtc) {
9289 connector->new_encoder = NULL;
9290
9291 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9292 connector->base.base.id,
9293 drm_get_connector_name(&connector->base));
9294 }
9295
9296
9297 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9298 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9299 config->mode_changed = true;
50f56119
DV		 9300 }
9301 }
9a935856 9302 /* connector->new_encoder is now updated for all connectors. */
50f56119 9303
9a935856 9304 /* Update crtc of enabled connectors. */
9a935856
DV		 9305 list_for_each_entry(connector, &dev->mode_config.connector_list,
9306 base.head) {
9307 if (!connector->new_encoder)
50f56119
DV		 9308 continue;
9309
9a935856 9310 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9311
9312 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9313 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9314 new_crtc = set->crtc;
9315 }
9316
9317 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9318 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9319 new_crtc)) {
5e2b584e 9320 return -EINVAL;
50f56119 9321 }
9a935856
DV		 9322 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9323
9324 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9325 connector->base.base.id,
9326 drm_get_connector_name(&connector->base),
9327 new_crtc->base.id);
9328 }
9329
9330 /* Check for any encoders that needs to be disabled. */
9331 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9332 base.head) {
9333 list_for_each_entry(connector,
9334 &dev->mode_config.connector_list,
9335 base.head) {
9336 if (connector->new_encoder == encoder) {
9337 WARN_ON(!connector->new_encoder->new_crtc);
9338
9339 goto next_encoder;
9340 }
9341 }
9342 encoder->new_crtc = NULL;
9343next_encoder:
9344 /* Only now check for crtc changes so we don't miss encoders
9345 * that will be disabled. */
9346 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9347 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9348 config->mode_changed = true;
50f56119
DV		 9349 }
9350 }
9a935856 9351 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9352
2e431051
DV		 9353 return 0;
9354}
9355
9356static int intel_crtc_set_config(struct drm_mode_set *set)
9357{
9358 struct drm_device *dev;
2e431051
DV		 9359 struct drm_mode_set save_set;
9360 struct intel_set_config *config;
9361 int ret;
2e431051 9362
8d3e375e
DV		 9363 BUG_ON(!set);
9364 BUG_ON(!set->crtc);
9365 BUG_ON(!set->crtc->helper_private);
2e431051 9366
7e53f3a4
DV		 9367 /* Enforce sane interface api - has been abused by the fb helper. */
9368 BUG_ON(!set->mode && set->fb);
9369 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9370
2e431051
DV		 9371 if (set->fb) {
9372 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9373 set->crtc->base.id, set->fb->base.id,
9374 (int)set->num_connectors, set->x, set->y);
9375 } else {
9376 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9377 }
9378
9379 dev = set->crtc->dev;
9380
9381 ret = -ENOMEM;
9382 config = kzalloc(sizeof(*config), GFP_KERNEL);
9383 if (!config)
9384 goto out_config;
9385
9386 ret = intel_set_config_save_state(dev, config);
9387 if (ret)
9388 goto out_config;
9389
9390 save_set.crtc = set->crtc;
9391 save_set.mode = &set->crtc->mode;
9392 save_set.x = set->crtc->x;
9393 save_set.y = set->crtc->y;
9394 save_set.fb = set->crtc->fb;
9395
9396 /* Compute whether we need a full modeset, only an fb base update or no
9397 * change at all. In the future we might also check whether only the
9398 * mode changed, e.g. for LVDS where we only change the panel fitter in
9399 * such cases. */
9400 intel_set_config_compute_mode_changes(set, config);
9401
9a935856 9402 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9403 if (ret)
9404 goto fail;
9405
5e2b584e 9406 if (config->mode_changed) {
c0c36b94
CW		 9407 ret = intel_set_mode(set->crtc, set->mode,
9408 set->x, set->y, set->fb);
5e2b584e 9409 } else if (config->fb_changed) {
4878cae2
VS		 9410 intel_crtc_wait_for_pending_flips(set->crtc);
9411
4f660f49 9412 ret = intel_pipe_set_base(set->crtc,
94352cf9 9413 set->x, set->y, set->fb);
50f56119
DV		 9414 }
9415
2d05eae1 9416 if (ret) {
bf67dfeb
DV		 9417 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9418 set->crtc->base.id, ret);
50f56119 9419fail:
2d05eae1 9420 intel_set_config_restore_state(dev, config);
50f56119 9421
2d05eae1
CW		 9422 /* Try to restore the config */
9423 if (config->mode_changed &&
9424 intel_set_mode(save_set.crtc, save_set.mode,
9425 save_set.x, save_set.y, save_set.fb))
9426 DRM_ERROR("failed to restore config after modeset failure\n");
9427 }
50f56119 9428
d9e55608
DV		 9429out_config:
9430 intel_set_config_free(config);
50f56119
DV		 9431 return ret;
9432}
f6e5b160
CW		 9433
9434static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9435 .cursor_set = intel_crtc_cursor_set,
9436 .cursor_move = intel_crtc_cursor_move,
9437 .gamma_set = intel_crtc_gamma_set,
50f56119 9438 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9439 .destroy = intel_crtc_destroy,
9440 .page_flip = intel_crtc_page_flip,
9441};
9442
79f689aa
PZ		 9443static void intel_cpu_pll_init(struct drm_device *dev)
9444{
affa9354 9445 if (HAS_DDI(dev))
79f689aa
PZ		 9446 intel_ddi_pll_init(dev);
9447}
9448
5358901f
DV		 9449static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9450 struct intel_shared_dpll *pll,
9451 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9452{
5358901f 9453 uint32_t val;
ee7b9f93 9454
5358901f 9455 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9456 hw_state->dpll = val;
9457 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9458 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9459
9460 return val & DPLL_VCO_ENABLE;
9461}
9462
15bdd4cf
DV		 9463static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9464 struct intel_shared_dpll *pll)
9465{
9466 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9467 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9468}
9469
e7b903d2
DV		 9470static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9471 struct intel_shared_dpll *pll)
9472{
e7b903d2
DV		 9473 /* PCH refclock must be enabled first */
9474 assert_pch_refclk_enabled(dev_priv);
9475
15bdd4cf
DV		 9476 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9477
9478 /* Wait for the clocks to stabilize. */
9479 POSTING_READ(PCH_DPLL(pll->id));
9480 udelay(150);
9481
9482 /* The pixel multiplier can only be updated once the
9483 * DPLL is enabled and the clocks are stable.
9484 *
9485 * So write it again.
9486 */
9487 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9488 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9489 udelay(200);
9490}
9491
9492static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9493 struct intel_shared_dpll *pll)
9494{
9495 struct drm_device *dev = dev_priv->dev;
9496 struct intel_crtc *crtc;
e7b903d2
DV		 9497
9498 /* Make sure no transcoder isn't still depending on us. */
9499 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9500 if (intel_crtc_to_shared_dpll(crtc) == pll)
9501 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9502 }
9503
15bdd4cf
DV		 9504 I915_WRITE(PCH_DPLL(pll->id), 0);
9505 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9506 udelay(200);
9507}
9508
46edb027
DV		 9509static char *ibx_pch_dpll_names[] = {
9510 "PCH DPLL A",
9511 "PCH DPLL B",
9512};
9513
7c74ade1 9514static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9515{
e7b903d2 9516 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9517 int i;
9518
7c74ade1 9519 dev_priv->num_shared_dpll = 2;
ee7b9f93 9520
e72f9fbf 9521 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9522 dev_priv->shared_dplls[i].id = i;
9523 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9524 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9525 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9526 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9527 dev_priv->shared_dplls[i].get_hw_state =
9528 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9529 }
9530}
9531
7c74ade1
DV		 9532static void intel_shared_dpll_init(struct drm_device *dev)
9533{
e7b903d2 9534 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9535
9536 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9537 ibx_pch_dpll_init(dev);
9538 else
9539 dev_priv->num_shared_dpll = 0;
9540
9541 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9542 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9543 dev_priv->num_shared_dpll);
9544}
9545
b358d0a6 9546static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9547{
22fd0fab 9548 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9549 struct intel_crtc *intel_crtc;
9550 int i;
9551
9552 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9553 if (intel_crtc == NULL)
9554 return;
9555
9556 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9557
9558 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9559 for (i = 0; i < 256; i++) {
9560 intel_crtc->lut_r[i] = i;
9561 intel_crtc->lut_g[i] = i;
9562 intel_crtc->lut_b[i] = i;
9563 }
9564
80824003
JB		 9565 /* Swap pipes & planes for FBC on pre-965 */
9566 intel_crtc->pipe = pipe;
9567 intel_crtc->plane = pipe;
e2e767ab 9568 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9569 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9570 intel_crtc->plane = !pipe;
80824003
JB		 9571 }
9572
22fd0fab
JB		 9573 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9574 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9575 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9576 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9577
79e53945 9578 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9579}
9580
08d7b3d1 9581int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9582 struct drm_file *file)
08d7b3d1 9583{
08d7b3d1 9584 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9585 struct drm_mode_object *drmmode_obj;
9586 struct intel_crtc *crtc;
08d7b3d1 9587
1cff8f6b
DV		 9588 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9589 return -ENODEV;
08d7b3d1 9590
c05422d5
DV		 9591 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9592 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9593
c05422d5 9594 if (!drmmode_obj) {
08d7b3d1
CW		 9595 DRM_ERROR("no such CRTC id\n");
9596 return -EINVAL;
9597 }
9598
c05422d5
DV		 9599 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9600 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9601
c05422d5 9602 return 0;
08d7b3d1
CW		 9603}
9604
66a9278e 9605static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9606{
66a9278e
DV		 9607 struct drm_device *dev = encoder->base.dev;
9608 struct intel_encoder *source_encoder;
79e53945 9609 int index_mask = 0;
79e53945
JB		 9610 int entry = 0;
9611
66a9278e
DV		 9612 list_for_each_entry(source_encoder,
9613 &dev->mode_config.encoder_list, base.head) {
9614
9615 if (encoder == source_encoder)
79e53945 9616 index_mask |= (1 << entry);
66a9278e
DV		 9617
9618 /* Intel hw has only one MUX where enocoders could be cloned. */
9619 if (encoder->cloneable && source_encoder->cloneable)
9620 index_mask |= (1 << entry);
9621
79e53945
JB		 9622 entry++;
9623 }
4ef69c7a 9624
79e53945
JB		 9625 return index_mask;
9626}
9627
4d302442
CW		 9628static bool has_edp_a(struct drm_device *dev)
9629{
9630 struct drm_i915_private *dev_priv = dev->dev_private;
9631
9632 if (!IS_MOBILE(dev))
9633 return false;
9634
9635 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9636 return false;
9637
9638 if (IS_GEN5(dev) &&
9639 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9640 return false;
9641
9642 return true;
9643}
9644
79e53945
JB		 9645static void intel_setup_outputs(struct drm_device *dev)
9646{
725e30ad 9647 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9648 struct intel_encoder *encoder;
cb0953d7 9649 bool dpd_is_edp = false;
79e53945 9650
c9093354 9651 intel_lvds_init(dev);
79e53945 9652
c40c0f5b 9653 if (!IS_ULT(dev))
79935fca 9654 intel_crt_init(dev);
cb0953d7 9655
affa9354 9656 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9657 int found;
9658
9659 /* Haswell uses DDI functions to detect digital outputs */
9660 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9661 /* DDI A only supports eDP */
9662 if (found)
9663 intel_ddi_init(dev, PORT_A);
9664
9665 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9666 * register */
9667 found = I915_READ(SFUSE_STRAP);
9668
9669 if (found & SFUSE_STRAP_DDIB_DETECTED)
9670 intel_ddi_init(dev, PORT_B);
9671 if (found & SFUSE_STRAP_DDIC_DETECTED)
9672 intel_ddi_init(dev, PORT_C);
9673 if (found & SFUSE_STRAP_DDID_DETECTED)
9674 intel_ddi_init(dev, PORT_D);
9675 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9676 int found;
270b3042
DV		 9677 dpd_is_edp = intel_dpd_is_edp(dev);
9678
9679 if (has_edp_a(dev))
9680 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9681
dc0fa718 9682 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9683 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9684 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9685 if (!found)
e2debe91 9686 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9687 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9688 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9689 }
9690
dc0fa718 9691 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9692 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9693
dc0fa718 9694 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9695 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9696
5eb08b69 9697 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9698 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9699
270b3042 9700 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9701 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9702 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9703 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9704 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9705 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9706 PORT_C);
9707 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9708 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9709 PORT_C);
9710 }
19c03924 9711
dc0fa718 9712 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9713 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9714 PORT_B);
67cfc203
VS		 9715 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9716 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9717 }
3cfca973
JN		 9718
9719 intel_dsi_init(dev);
103a196f 9720 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9721 bool found = false;
7d57382e 9722
e2debe91 9723 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9724 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9725 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9726 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9727 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9728 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9729 }
27185ae1 9730
e7281eab 9731 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9732 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9733 }
13520b05
KH		 9734
9735 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9736
e2debe91 9737 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9738 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9739 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9740 }
27185ae1 9741
e2debe91 9742 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9743
b01f2c3a
JB		 9744 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9745 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9746 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9747 }
e7281eab 9748 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9749 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9750 }
27185ae1 9751
b01f2c3a 9752 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9753 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9754 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9755 } else if (IS_GEN2(dev))
79e53945
JB		 9756 intel_dvo_init(dev);
9757
103a196f 9758 if (SUPPORTS_TV(dev))
79e53945
JB		 9759 intel_tv_init(dev);
9760
4ef69c7a
CW		 9761 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9762 encoder->base.possible_crtcs = encoder->crtc_mask;
9763 encoder->base.possible_clones =
66a9278e 9764 intel_encoder_clones(encoder);
79e53945 9765 }
47356eb6 9766
dde86e2d 9767 intel_init_pch_refclk(dev);
270b3042
DV		 9768
9769 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9770}
9771
ddfe1567
CW		 9772void intel_framebuffer_fini(struct intel_framebuffer *fb)
9773{
9774 drm_framebuffer_cleanup(&fb->base);
9775 drm_gem_object_unreference_unlocked(&fb->obj->base);
9776}
9777
79e53945
JB		 9778static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9779{
9780 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9781
ddfe1567 9782 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9783 kfree(intel_fb);
9784}
9785
9786static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9787 struct drm_file *file,
79e53945
JB		 9788 unsigned int *handle)
9789{
9790 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9791 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9792
05394f39 9793 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9794}
9795
9796static const struct drm_framebuffer_funcs intel_fb_funcs = {
9797 .destroy = intel_user_framebuffer_destroy,
9798 .create_handle = intel_user_framebuffer_create_handle,
9799};
9800
38651674
DA		 9801int intel_framebuffer_init(struct drm_device *dev,
9802 struct intel_framebuffer *intel_fb,
308e5bcb 9803 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9804 struct drm_i915_gem_object *obj)
79e53945 9805{
a35cdaa0 9806 int pitch_limit;
79e53945
JB		 9807 int ret;
9808
c16ed4be
CW		 9809 if (obj->tiling_mode == I915_TILING_Y) {
9810 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9811 return -EINVAL;
c16ed4be 9812 }
57cd6508 9813
c16ed4be
CW		 9814 if (mode_cmd->pitches[0] & 63) {
9815 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9816 mode_cmd->pitches[0]);
57cd6508 9817 return -EINVAL;
c16ed4be 9818 }
57cd6508 9819
a35cdaa0
CW		 9820 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9821 pitch_limit = 32*1024;
9822 } else if (INTEL_INFO(dev)->gen >= 4) {
9823 if (obj->tiling_mode)
9824 pitch_limit = 16*1024;
9825 else
9826 pitch_limit = 32*1024;
9827 } else if (INTEL_INFO(dev)->gen >= 3) {
9828 if (obj->tiling_mode)
9829 pitch_limit = 8*1024;
9830 else
9831 pitch_limit = 16*1024;
9832 } else
9833 /* XXX DSPC is limited to 4k tiled */
9834 pitch_limit = 8*1024;
9835
9836 if (mode_cmd->pitches[0] > pitch_limit) {
9837 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9838 obj->tiling_mode ? "tiled" : "linear",
9839 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9840 return -EINVAL;
c16ed4be 9841 }
5d7bd705
VS		 9842
9843 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9844 mode_cmd->pitches[0] != obj->stride) {
9845 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9846 mode_cmd->pitches[0], obj->stride);
5d7bd705 9847 return -EINVAL;
c16ed4be 9848 }
5d7bd705 9849
57779d06 9850 /* Reject formats not supported by any plane early. */
308e5bcb 9851 switch (mode_cmd->pixel_format) {
57779d06 9852 case DRM_FORMAT_C8:
04b3924d
VS		 9853 case DRM_FORMAT_RGB565:
9854 case DRM_FORMAT_XRGB8888:
9855 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9856 break;
9857 case DRM_FORMAT_XRGB1555:
9858 case DRM_FORMAT_ARGB1555:
c16ed4be 9859 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9860 DRM_DEBUG("unsupported pixel format: %s\n",
9861 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9862 return -EINVAL;
c16ed4be 9863 }
57779d06
VS		 9864 break;
9865 case DRM_FORMAT_XBGR8888:
9866 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9867 case DRM_FORMAT_XRGB2101010:
9868 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9869 case DRM_FORMAT_XBGR2101010:
9870 case DRM_FORMAT_ABGR2101010:
c16ed4be 9871 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9872 DRM_DEBUG("unsupported pixel format: %s\n",
9873 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9874 return -EINVAL;
c16ed4be 9875 }
b5626747 9876 break;
04b3924d
VS		 9877 case DRM_FORMAT_YUYV:
9878 case DRM_FORMAT_UYVY:
9879 case DRM_FORMAT_YVYU:
9880 case DRM_FORMAT_VYUY:
c16ed4be 9881 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9882 DRM_DEBUG("unsupported pixel format: %s\n",
9883 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9884 return -EINVAL;
c16ed4be 9885 }
57cd6508
CW		 9886 break;
9887 default:
4ee62c76
VS		 9888 DRM_DEBUG("unsupported pixel format: %s\n",
9889 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9890 return -EINVAL;
9891 }
9892
90f9a336
VS		 9893 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9894 if (mode_cmd->offsets[0] != 0)
9895 return -EINVAL;
9896
c7d73f6a
DV		 9897 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9898 intel_fb->obj = obj;
9899
79e53945
JB		 9900 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9901 if (ret) {
9902 DRM_ERROR("framebuffer init failed %d\n", ret);
9903 return ret;
9904 }
9905
79e53945
JB		 9906 return 0;
9907}
9908
79e53945
JB		 9909static struct drm_framebuffer *
9910intel_user_framebuffer_create(struct drm_device *dev,
9911 struct drm_file *filp,
308e5bcb 9912 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9913{
05394f39 9914 struct drm_i915_gem_object *obj;
79e53945 9915
308e5bcb
JB		 9916 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9917 mode_cmd->handles[0]));
c8725226 9918 if (&obj->base == NULL)
cce13ff7 9919 return ERR_PTR(-ENOENT);
79e53945 9920
d2dff872 9921 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9922}
9923
79e53945 9924static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9925 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9926 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9927};
9928
e70236a8
JB		 9929/* Set up chip specific display functions */
9930static void intel_init_display(struct drm_device *dev)
9931{
9932 struct drm_i915_private *dev_priv = dev->dev_private;
9933
ee9300bb
DV		 9934 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9935 dev_priv->display.find_dpll = g4x_find_best_dpll;
9936 else if (IS_VALLEYVIEW(dev))
9937 dev_priv->display.find_dpll = vlv_find_best_dpll;
9938 else if (IS_PINEVIEW(dev))
9939 dev_priv->display.find_dpll = pnv_find_best_dpll;
9940 else
9941 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9942
affa9354 9943 if (HAS_DDI(dev)) {
0e8ffe1b 9944 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9945 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9946 dev_priv->display.crtc_enable = haswell_crtc_enable;
9947 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9948 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9949 dev_priv->display.update_plane = ironlake_update_plane;
9950 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9951 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9952 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9953 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9954 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9955 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9956 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9957 } else if (IS_VALLEYVIEW(dev)) {
9958 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9959 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9960 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9961 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9962 dev_priv->display.off = i9xx_crtc_off;
9963 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9964 } else {
0e8ffe1b 9965 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9966 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9967 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9968 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9969 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9970 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9971 }
e70236a8 9972
e70236a8 9973 /* Returns the core display clock speed */
25eb05fc
JB		 9974 if (IS_VALLEYVIEW(dev))
9975 dev_priv->display.get_display_clock_speed =
9976 valleyview_get_display_clock_speed;
9977 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9978 dev_priv->display.get_display_clock_speed =
9979 i945_get_display_clock_speed;
9980 else if (IS_I915G(dev))
9981 dev_priv->display.get_display_clock_speed =
9982 i915_get_display_clock_speed;
257a7ffc 9983 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9984 dev_priv->display.get_display_clock_speed =
9985 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9986 else if (IS_PINEVIEW(dev))
9987 dev_priv->display.get_display_clock_speed =
9988 pnv_get_display_clock_speed;
e70236a8
JB		 9989 else if (IS_I915GM(dev))
9990 dev_priv->display.get_display_clock_speed =
9991 i915gm_get_display_clock_speed;
9992 else if (IS_I865G(dev))
9993 dev_priv->display.get_display_clock_speed =
9994 i865_get_display_clock_speed;
f0f8a9ce 9995 else if (IS_I85X(dev))
e70236a8
JB		 9996 dev_priv->display.get_display_clock_speed =
9997 i855_get_display_clock_speed;
9998 else /* 852, 830 */
9999 dev_priv->display.get_display_clock_speed =
10000 i830_get_display_clock_speed;
10001
7f8a8569 10002 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10003 if (IS_GEN5(dev)) {
674cf967 10004 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10005 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10006 } else if (IS_GEN6(dev)) {
674cf967 10007 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10008 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10009 } else if (IS_IVYBRIDGE(dev)) {
10010 /* FIXME: detect B0+ stepping and use auto training */
10011 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10012 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10013 dev_priv->display.modeset_global_resources =
10014 ivb_modeset_global_resources;
c82e4d26
ED		 10015 } else if (IS_HASWELL(dev)) {
10016 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10017 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10018 dev_priv->display.modeset_global_resources =
10019 haswell_modeset_global_resources;
a0e63c22 10020 }
6067aaea 10021 } else if (IS_G4X(dev)) {
e0dac65e 10022 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10023 }
8c9f3aaf
JB		 10024
10025 /* Default just returns -ENODEV to indicate unsupported */
10026 dev_priv->display.queue_flip = intel_default_queue_flip;
10027
10028 switch (INTEL_INFO(dev)->gen) {
10029 case 2:
10030 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10031 break;
10032
10033 case 3:
10034 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10035 break;
10036
10037 case 4:
10038 case 5:
10039 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10040 break;
10041
10042 case 6:
10043 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10044 break;
7c9017e5
JB		 10045 case 7:
10046 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10047 break;
8c9f3aaf 10048 }
e70236a8
JB		 10049}
10050
b690e96c
JB		 10051/*
10052 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10053 * resume, or other times. This quirk makes sure that's the case for
10054 * affected systems.
10055 */
0206e353 10056static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10057{
10058 struct drm_i915_private *dev_priv = dev->dev_private;
10059
10060 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10061 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10062}
10063
435793df
KP		 10064/*
10065 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10066 */
10067static void quirk_ssc_force_disable(struct drm_device *dev)
10068{
10069 struct drm_i915_private *dev_priv = dev->dev_private;
10070 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10071 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10072}
10073
4dca20ef 10074/*
5a15ab5b
CE		 10075 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10076 * brightness value
4dca20ef
CE		 10077 */
10078static void quirk_invert_brightness(struct drm_device *dev)
10079{
10080 struct drm_i915_private *dev_priv = dev->dev_private;
10081 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10082 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10083}
10084
e85843be
KM		 10085/*
10086 * Some machines (Dell XPS13) suffer broken backlight controls if
10087 * BLM_PCH_PWM_ENABLE is set.
10088 */
10089static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10090{
10091 struct drm_i915_private *dev_priv = dev->dev_private;
10092 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10093 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10094}
10095
b690e96c
JB		 10096struct intel_quirk {
10097 int device;
10098 int subsystem_vendor;
10099 int subsystem_device;
10100 void (*hook)(struct drm_device *dev);
10101};
10102
5f85f176
EE		 10103/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10104struct intel_dmi_quirk {
10105 void (*hook)(struct drm_device *dev);
10106 const struct dmi_system_id (*dmi_id_list)[];
10107};
10108
10109static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10110{
10111 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10112 return 1;
10113}
10114
10115static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10116 {
10117 .dmi_id_list = &(const struct dmi_system_id[]) {
10118 {
10119 .callback = intel_dmi_reverse_brightness,
10120 .ident = "NCR Corporation",
10121 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10122 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10123 },
10124 },
10125 { } /* terminating entry */
10126 },
10127 .hook = quirk_invert_brightness,
10128 },
10129};
10130
c43b5634 10131static struct intel_quirk intel_quirks[] = {
b690e96c 10132 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10133 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10134
b690e96c
JB		 10135 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10136 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10137
b690e96c
JB		 10138 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10139 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10140
ccd0d36e 10141 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10142 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10143 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10144
10145 /* Lenovo U160 cannot use SSC on LVDS */
10146 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10147
10148 /* Sony Vaio Y cannot use SSC on LVDS */
10149 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10150
10151 /* Acer Aspire 5734Z must invert backlight brightness */
10152 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10153
10154 /* Acer/eMachines G725 */
10155 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10156
10157 /* Acer/eMachines e725 */
10158 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10159
10160 /* Acer/Packard Bell NCL20 */
10161 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10162
10163 /* Acer Aspire 4736Z */
10164 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10165
10166 /* Dell XPS13 HD Sandy Bridge */
10167 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10168 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10169 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10170};
10171
10172static void intel_init_quirks(struct drm_device *dev)
10173{
10174 struct pci_dev *d = dev->pdev;
10175 int i;
10176
10177 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10178 struct intel_quirk *q = &intel_quirks[i];
10179
10180 if (d->device == q->device &&
10181 (d->subsystem_vendor == q->subsystem_vendor ||
10182 q->subsystem_vendor == PCI_ANY_ID) &&
10183 (d->subsystem_device == q->subsystem_device ||
10184 q->subsystem_device == PCI_ANY_ID))
10185 q->hook(dev);
10186 }
5f85f176
EE		 10187 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10188 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10189 intel_dmi_quirks[i].hook(dev);
10190 }
b690e96c
JB		 10191}
10192
9cce37f4
JB		 10193/* Disable the VGA plane that we never use */
10194static void i915_disable_vga(struct drm_device *dev)
10195{
10196 struct drm_i915_private *dev_priv = dev->dev_private;
10197 u8 sr1;
766aa1c4 10198 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10199
10200 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10201 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10202 sr1 = inb(VGA_SR_DATA);
10203 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10204
10205 /* Disable VGA memory on Intel HD */
10206 if (HAS_PCH_SPLIT(dev)) {
10207 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10208 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10209 VGA_RSRC_NORMAL_IO |
10210 VGA_RSRC_NORMAL_MEM);
10211 }
10212
9cce37f4
JB		 10213 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10214 udelay(300);
10215
10216 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10217 POSTING_READ(vga_reg);
10218}
10219
81b5c7bc
AW		 10220static void i915_enable_vga(struct drm_device *dev)
10221{
10222 /* Enable VGA memory on Intel HD */
10223 if (HAS_PCH_SPLIT(dev)) {
10224 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10225 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10226 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10227 VGA_RSRC_LEGACY_MEM |
10228 VGA_RSRC_NORMAL_IO |
10229 VGA_RSRC_NORMAL_MEM);
10230 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10231 }
10232}
10233
f817586c
DV		 10234void intel_modeset_init_hw(struct drm_device *dev)
10235{
fa42e23c 10236 intel_init_power_well(dev);
0232e927 10237
a8f78b58
ED		 10238 intel_prepare_ddi(dev);
10239
f817586c
DV		 10240 intel_init_clock_gating(dev);
10241
79f5b2c7 10242 mutex_lock(&dev->struct_mutex);
8090c6b9 10243 intel_enable_gt_powersave(dev);
79f5b2c7 10244 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10245}
10246
7d708ee4
ID		 10247void intel_modeset_suspend_hw(struct drm_device *dev)
10248{
10249 intel_suspend_hw(dev);
10250}
10251
79e53945
JB		 10252void intel_modeset_init(struct drm_device *dev)
10253{
652c393a 10254 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10255 int i, j, ret;
79e53945
JB		 10256
10257 drm_mode_config_init(dev);
10258
10259 dev->mode_config.min_width = 0;
10260 dev->mode_config.min_height = 0;
10261
019d96cb
DA		 10262 dev->mode_config.preferred_depth = 24;
10263 dev->mode_config.prefer_shadow = 1;
10264
e6ecefaa 10265 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10266
b690e96c
JB		 10267 intel_init_quirks(dev);
10268
1fa61106
ED		 10269 intel_init_pm(dev);
10270
e3c74757
BW		 10271 if (INTEL_INFO(dev)->num_pipes == 0)
10272 return;
10273
e70236a8
JB		 10274 intel_init_display(dev);
10275
a6c45cf0
CW		 10276 if (IS_GEN2(dev)) {
10277 dev->mode_config.max_width = 2048;
10278 dev->mode_config.max_height = 2048;
10279 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10280 dev->mode_config.max_width = 4096;
10281 dev->mode_config.max_height = 4096;
79e53945 10282 } else {
a6c45cf0
CW		 10283 dev->mode_config.max_width = 8192;
10284 dev->mode_config.max_height = 8192;
79e53945 10285 }
5d4545ae 10286 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10287
28c97730 10288 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10289 INTEL_INFO(dev)->num_pipes,
10290 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10291
08e2a7de 10292 for_each_pipe(i) {
79e53945 10293 intel_crtc_init(dev, i);
7f1f3851
JB		 10294 for (j = 0; j < dev_priv->num_plane; j++) {
10295 ret = intel_plane_init(dev, i, j);
10296 if (ret)
06da8da2
VS		 10297 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10298 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10299 }
79e53945
JB		 10300 }
10301
79f689aa 10302 intel_cpu_pll_init(dev);
e72f9fbf 10303 intel_shared_dpll_init(dev);
ee7b9f93 10304
9cce37f4
JB		 10305 /* Just disable it once at startup */
10306 i915_disable_vga(dev);
79e53945 10307 intel_setup_outputs(dev);
11be49eb
CW		 10308
10309 /* Just in case the BIOS is doing something questionable. */
10310 intel_disable_fbc(dev);
2c7111db
CW		 10311}
10312
24929352
DV		 10313static void
10314intel_connector_break_all_links(struct intel_connector *connector)
10315{
10316 connector->base.dpms = DRM_MODE_DPMS_OFF;
10317 connector->base.encoder = NULL;
10318 connector->encoder->connectors_active = false;
10319 connector->encoder->base.crtc = NULL;
10320}
10321
7fad798e
DV		 10322static void intel_enable_pipe_a(struct drm_device *dev)
10323{
10324 struct intel_connector *connector;
10325 struct drm_connector *crt = NULL;
10326 struct intel_load_detect_pipe load_detect_temp;
10327
10328 /* We can't just switch on the pipe A, we need to set things up with a
10329 * proper mode and output configuration. As a gross hack, enable pipe A
10330 * by enabling the load detect pipe once. */
10331 list_for_each_entry(connector,
10332 &dev->mode_config.connector_list,
10333 base.head) {
10334 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10335 crt = &connector->base;
10336 break;
10337 }
10338 }
10339
10340 if (!crt)
10341 return;
10342
10343 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10344 intel_release_load_detect_pipe(crt, &load_detect_temp);
10345
652c393a 10346
7fad798e
DV		 10347}
10348
fa555837
DV		 10349static bool
10350intel_check_plane_mapping(struct intel_crtc *crtc)
10351{
7eb552ae
BW		 10352 struct drm_device *dev = crtc->base.dev;
10353 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10354 u32 reg, val;
10355
7eb552ae 10356 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10357 return true;
10358
10359 reg = DSPCNTR(!crtc->plane);
10360 val = I915_READ(reg);
10361
10362 if ((val & DISPLAY_PLANE_ENABLE) &&
10363 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10364 return false;
10365
10366 return true;
10367}
10368
24929352
DV		 10369static void intel_sanitize_crtc(struct intel_crtc *crtc)
10370{
10371 struct drm_device *dev = crtc->base.dev;
10372 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10373 u32 reg;
24929352 10374
24929352 10375 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10376 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10377 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10378
10379 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10380 * disable the crtc (and hence change the state) if it is wrong. Note
10381 * that gen4+ has a fixed plane -> pipe mapping. */
10382 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10383 struct intel_connector *connector;
10384 bool plane;
10385
24929352
DV		 10386 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10387 crtc->base.base.id);
10388
10389 /* Pipe has the wrong plane attached and the plane is active.
10390 * Temporarily change the plane mapping and disable everything
10391 * ... */
10392 plane = crtc->plane;
10393 crtc->plane = !plane;
10394 dev_priv->display.crtc_disable(&crtc->base);
10395 crtc->plane = plane;
10396
10397 /* ... and break all links. */
10398 list_for_each_entry(connector, &dev->mode_config.connector_list,
10399 base.head) {
10400 if (connector->encoder->base.crtc != &crtc->base)
10401 continue;
10402
10403 intel_connector_break_all_links(connector);
10404 }
10405
10406 WARN_ON(crtc->active);
10407 crtc->base.enabled = false;
10408 }
24929352 10409
7fad798e
DV		 10410 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10411 crtc->pipe == PIPE_A && !crtc->active) {
10412 /* BIOS forgot to enable pipe A, this mostly happens after
10413 * resume. Force-enable the pipe to fix this, the update_dpms
10414 * call below we restore the pipe to the right state, but leave
10415 * the required bits on. */
10416 intel_enable_pipe_a(dev);
10417 }
10418
24929352
DV		 10419 /* Adjust the state of the output pipe according to whether we
10420 * have active connectors/encoders. */
10421 intel_crtc_update_dpms(&crtc->base);
10422
10423 if (crtc->active != crtc->base.enabled) {
10424 struct intel_encoder *encoder;
10425
10426 /* This can happen either due to bugs in the get_hw_state
10427 * functions or because the pipe is force-enabled due to the
10428 * pipe A quirk. */
10429 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10430 crtc->base.base.id,
10431 crtc->base.enabled ? "enabled" : "disabled",
10432 crtc->active ? "enabled" : "disabled");
10433
10434 crtc->base.enabled = crtc->active;
10435
10436 /* Because we only establish the connector -> encoder ->
10437 * crtc links if something is active, this means the
10438 * crtc is now deactivated. Break the links. connector
10439 * -> encoder links are only establish when things are
10440 * actually up, hence no need to break them. */
10441 WARN_ON(crtc->active);
10442
10443 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10444 WARN_ON(encoder->connectors_active);
10445 encoder->base.crtc = NULL;
10446 }
10447 }
10448}
10449
10450static void intel_sanitize_encoder(struct intel_encoder *encoder)
10451{
10452 struct intel_connector *connector;
10453 struct drm_device *dev = encoder->base.dev;
10454
10455 /* We need to check both for a crtc link (meaning that the
10456 * encoder is active and trying to read from a pipe) and the
10457 * pipe itself being active. */
10458 bool has_active_crtc = encoder->base.crtc &&
10459 to_intel_crtc(encoder->base.crtc)->active;
10460
10461 if (encoder->connectors_active && !has_active_crtc) {
10462 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10463 encoder->base.base.id,
10464 drm_get_encoder_name(&encoder->base));
10465
10466 /* Connector is active, but has no active pipe. This is
10467 * fallout from our resume register restoring. Disable
10468 * the encoder manually again. */
10469 if (encoder->base.crtc) {
10470 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10471 encoder->base.base.id,
10472 drm_get_encoder_name(&encoder->base));
10473 encoder->disable(encoder);
10474 }
10475
10476 /* Inconsistent output/port/pipe state happens presumably due to
10477 * a bug in one of the get_hw_state functions. Or someplace else
10478 * in our code, like the register restore mess on resume. Clamp
10479 * things to off as a safer default. */
10480 list_for_each_entry(connector,
10481 &dev->mode_config.connector_list,
10482 base.head) {
10483 if (connector->encoder != encoder)
10484 continue;
10485
10486 intel_connector_break_all_links(connector);
10487 }
10488 }
10489 /* Enabled encoders without active connectors will be fixed in
10490 * the crtc fixup. */
10491}
10492
44cec740 10493void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10494{
10495 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10496 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10497
8dc8a27c
PZ		 10498 /* This function can be called both from intel_modeset_setup_hw_state or
10499 * at a very early point in our resume sequence, where the power well
10500 * structures are not yet restored. Since this function is at a very
10501 * paranoid "someone might have enabled VGA while we were not looking"
10502 * level, just check if the power well is enabled instead of trying to
10503 * follow the "don't touch the power well if we don't need it" policy
10504 * the rest of the driver uses. */
10505 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10506 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10507 return;
10508
0fde901f
KM		 10509 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10510 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10511 i915_disable_vga(dev);
0fde901f
KM		 10512 }
10513}
10514
30e984df 10515static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10516{
10517 struct drm_i915_private *dev_priv = dev->dev_private;
10518 enum pipe pipe;
24929352
DV		 10519 struct intel_crtc *crtc;
10520 struct intel_encoder *encoder;
10521 struct intel_connector *connector;
5358901f 10522 int i;
24929352 10523
0e8ffe1b
DV		 10524 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10525 base.head) {
88adfff1 10526 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10527
0e8ffe1b
DV		 10528 crtc->active = dev_priv->display.get_pipe_config(crtc,
10529 &crtc->config);
24929352
DV		 10530
10531 crtc->base.enabled = crtc->active;
10532
10533 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10534 crtc->base.base.id,
10535 crtc->active ? "enabled" : "disabled");
10536 }
10537
5358901f 10538 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10539 if (HAS_DDI(dev))
6441ab5f
PZ		 10540 intel_ddi_setup_hw_pll_state(dev);
10541
5358901f
DV		 10542 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10543 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10544
10545 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10546 pll->active = 0;
10547 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10548 base.head) {
10549 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10550 pll->active++;
10551 }
10552 pll->refcount = pll->active;
10553
35c95375
DV		 10554 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10555 pll->name, pll->refcount, pll->on);
5358901f
DV		 10556 }
10557
24929352
DV		 10558 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10559 base.head) {
10560 pipe = 0;
10561
10562 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10563 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10564 encoder->base.crtc = &crtc->base;
510d5f2f 10565 if (encoder->get_config)
045ac3b5 10566 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10567 } else {
10568 encoder->base.crtc = NULL;
10569 }
10570
10571 encoder->connectors_active = false;
10572 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10573 encoder->base.base.id,
10574 drm_get_encoder_name(&encoder->base),
10575 encoder->base.crtc ? "enabled" : "disabled",
10576 pipe);
10577 }
10578
10579 list_for_each_entry(connector, &dev->mode_config.connector_list,
10580 base.head) {
10581 if (connector->get_hw_state(connector)) {
10582 connector->base.dpms = DRM_MODE_DPMS_ON;
10583 connector->encoder->connectors_active = true;
10584 connector->base.encoder = &connector->encoder->base;
10585 } else {
10586 connector->base.dpms = DRM_MODE_DPMS_OFF;
10587 connector->base.encoder = NULL;
10588 }
10589 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10590 connector->base.base.id,
10591 drm_get_connector_name(&connector->base),
10592 connector->base.encoder ? "enabled" : "disabled");
10593 }
30e984df
DV		 10594}
10595
10596/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10597 * and i915 state tracking structures. */
10598void intel_modeset_setup_hw_state(struct drm_device *dev,
10599 bool force_restore)
10600{
10601 struct drm_i915_private *dev_priv = dev->dev_private;
10602 enum pipe pipe;
10603 struct drm_plane *plane;
10604 struct intel_crtc *crtc;
10605 struct intel_encoder *encoder;
35c95375 10606 int i;
30e984df
DV		 10607
10608 intel_modeset_readout_hw_state(dev);
24929352 10609
babea61d
JB		 10610 /*
10611 * Now that we have the config, copy it to each CRTC struct
10612 * Note that this could go away if we move to using crtc_config
10613 * checking everywhere.
10614 */
10615 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10616 base.head) {
10617 if (crtc->active && i915_fastboot) {
10618 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10619
10620 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10621 crtc->base.base.id);
10622 drm_mode_debug_printmodeline(&crtc->base.mode);
10623 }
10624 }
10625
24929352
DV		 10626 /* HW state is read out, now we need to sanitize this mess. */
10627 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10628 base.head) {
10629 intel_sanitize_encoder(encoder);
10630 }
10631
10632 for_each_pipe(pipe) {
10633 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10634 intel_sanitize_crtc(crtc);
c0b03411 10635 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10636 }
9a935856 10637
35c95375
DV		 10638 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10639 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10640
10641 if (!pll->on || pll->active)
10642 continue;
10643
10644 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10645
10646 pll->disable(dev_priv, pll);
10647 pll->on = false;
10648 }
10649
45e2b5f6 10650 if (force_restore) {
f30da187
DV		 10651 /*
10652 * We need to use raw interfaces for restoring state to avoid
10653 * checking (bogus) intermediate states.
10654 */
45e2b5f6 10655 for_each_pipe(pipe) {
b5644d05
JB		 10656 struct drm_crtc *crtc =
10657 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10658
10659 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10660 crtc->fb);
45e2b5f6 10661 }
b5644d05
JB		 10662 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10663 intel_plane_restore(plane);
0fde901f
KM		 10664
10665 i915_redisable_vga(dev);
45e2b5f6
DV		 10666 } else {
10667 intel_modeset_update_staged_output_state(dev);
10668 }
8af6cf88
DV		 10669
10670 intel_modeset_check_state(dev);
2e938892
DV		 10671
10672 drm_mode_config_reset(dev);
2c7111db
CW		 10673}
10674
10675void intel_modeset_gem_init(struct drm_device *dev)
10676{
1833b134 10677 intel_modeset_init_hw(dev);
02e792fb
DV		 10678
10679 intel_setup_overlay(dev);
24929352 10680
45e2b5f6 10681 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10682}
10683
10684void intel_modeset_cleanup(struct drm_device *dev)
10685{
652c393a
JB		 10686 struct drm_i915_private *dev_priv = dev->dev_private;
10687 struct drm_crtc *crtc;
652c393a 10688
fd0c0642
DV		 10689 /*
10690 * Interrupts and polling as the first thing to avoid creating havoc.
10691 * Too much stuff here (turning of rps, connectors, ...) would
10692 * experience fancy races otherwise.
10693 */
10694 drm_irq_uninstall(dev);
10695 cancel_work_sync(&dev_priv->hotplug_work);
10696 /*
10697 * Due to the hpd irq storm handling the hotplug work can re-arm the
10698 * poll handlers. Hence disable polling after hpd handling is shut down.
10699 */
f87ea761 10700 drm_kms_helper_poll_fini(dev);
fd0c0642 10701
652c393a
JB		 10702 mutex_lock(&dev->struct_mutex);
10703
723bfd70
JB		 10704 intel_unregister_dsm_handler();
10705
652c393a
JB		 10706 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10707 /* Skip inactive CRTCs */
10708 if (!crtc->fb)
10709 continue;
10710
3dec0095 10711 intel_increase_pllclock(crtc);
652c393a
JB		 10712 }
10713
973d04f9 10714 intel_disable_fbc(dev);
e70236a8 10715
81b5c7bc
AW		 10716 i915_enable_vga(dev);
10717
8090c6b9 10718 intel_disable_gt_powersave(dev);
0cdab21f 10719
930ebb46
DV		 10720 ironlake_teardown_rc6(dev);
10721
69341a5e
KH		 10722 mutex_unlock(&dev->struct_mutex);
10723
1630fe75
CW		 10724 /* flush any delayed tasks or pending work */
10725 flush_scheduled_work();
10726
dc652f90
JN		 10727 /* destroy backlight, if any, before the connectors */
10728 intel_panel_destroy_backlight(dev);
10729
79e53945 10730 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10731
10732 intel_cleanup_overlay(dev);
79e53945
JB		 10733}
10734
f1c79df3
ZW		 10735/*
10736 * Return which encoder is currently attached for connector.
10737 */
df0e9248 10738struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10739{
df0e9248
CW		 10740 return &intel_attached_encoder(connector)->base;
10741}
f1c79df3 10742
df0e9248
CW		 10743void intel_connector_attach_encoder(struct intel_connector *connector,
10744 struct intel_encoder *encoder)
10745{
10746 connector->encoder = encoder;
10747 drm_mode_connector_attach_encoder(&connector->base,
10748 &encoder->base);
79e53945 10749}
28d52043
DA		 10750
10751/*
10752 * set vga decode state - true == enable VGA decode
10753 */
10754int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10755{
10756 struct drm_i915_private *dev_priv = dev->dev_private;
10757 u16 gmch_ctrl;
10758
10759 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10760 if (state)
10761 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10762 else
10763 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10764 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10765 return 0;
10766}
c4a1d9e4 10767
c4a1d9e4 10768struct intel_display_error_state {
ff57f1b0
PZ		 10769
10770 u32 power_well_driver;
10771
63b66e5b
CW		 10772 int num_transcoders;
10773
c4a1d9e4
CW		 10774 struct intel_cursor_error_state {
10775 u32 control;
10776 u32 position;
10777 u32 base;
10778 u32 size;
52331309 10779 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10780
10781 struct intel_pipe_error_state {
c4a1d9e4 10782 u32 source;
52331309 10783 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10784
10785 struct intel_plane_error_state {
10786 u32 control;
10787 u32 stride;
10788 u32 size;
10789 u32 pos;
10790 u32 addr;
10791 u32 surface;
10792 u32 tile_offset;
52331309 10793 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10794
10795 struct intel_transcoder_error_state {
10796 enum transcoder cpu_transcoder;
10797
10798 u32 conf;
10799
10800 u32 htotal;
10801 u32 hblank;
10802 u32 hsync;
10803 u32 vtotal;
10804 u32 vblank;
10805 u32 vsync;
10806 } transcoder[4];
c4a1d9e4
CW		 10807};
10808
10809struct intel_display_error_state *
10810intel_display_capture_error_state(struct drm_device *dev)
10811{
0206e353 10812 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10813 struct intel_display_error_state *error;
63b66e5b
CW		 10814 int transcoders[] = {
10815 TRANSCODER_A,
10816 TRANSCODER_B,
10817 TRANSCODER_C,
10818 TRANSCODER_EDP,
10819 };
c4a1d9e4
CW		 10820 int i;
10821
63b66e5b
CW		 10822 if (INTEL_INFO(dev)->num_pipes == 0)
10823 return NULL;
10824
c4a1d9e4
CW		 10825 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10826 if (error == NULL)
10827 return NULL;
10828
ff57f1b0
PZ		 10829 if (HAS_POWER_WELL(dev))
10830 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10831
52331309 10832 for_each_pipe(i) {
a18c4c3d
PZ		 10833 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10834 error->cursor[i].control = I915_READ(CURCNTR(i));
10835 error->cursor[i].position = I915_READ(CURPOS(i));
10836 error->cursor[i].base = I915_READ(CURBASE(i));
10837 } else {
10838 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10839 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10840 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10841 }
c4a1d9e4
CW		 10842
10843 error->plane[i].control = I915_READ(DSPCNTR(i));
10844 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10845 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10846 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10847 error->plane[i].pos = I915_READ(DSPPOS(i));
10848 }
ca291363
PZ		 10849 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10850 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10851 if (INTEL_INFO(dev)->gen >= 4) {
10852 error->plane[i].surface = I915_READ(DSPSURF(i));
10853 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10854 }
10855
c4a1d9e4 10856 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10857 }
10858
10859 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10860 if (HAS_DDI(dev_priv->dev))
10861 error->num_transcoders++; /* Account for eDP. */
10862
10863 for (i = 0; i < error->num_transcoders; i++) {
10864 enum transcoder cpu_transcoder = transcoders[i];
10865
10866 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10867
10868 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10869 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10870 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10871 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10872 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10873 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10874 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10875 }
10876
12d217c7
PZ		 10877 /* In the code above we read the registers without checking if the power
10878 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10879 * prevent the next I915_WRITE from detecting it and printing an error
10880 * message. */
907b28c5 10881 intel_uncore_clear_errors(dev);
12d217c7 10882
c4a1d9e4
CW		 10883 return error;
10884}
10885
edc3d884
MK		 10886#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10887
c4a1d9e4 10888void
edc3d884 10889intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10890 struct drm_device *dev,
10891 struct intel_display_error_state *error)
10892{
10893 int i;
10894
63b66e5b
CW		 10895 if (!error)
10896 return;
10897
edc3d884 10898 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10899 if (HAS_POWER_WELL(dev))
edc3d884 10900 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10901 error->power_well_driver);
52331309 10902 for_each_pipe(i) {
edc3d884 10903 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10904 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10905
10906 err_printf(m, "Plane [%d]:\n", i);
10907 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10908 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10909 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10910 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10911 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10912 }
4b71a570 10913 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10914 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10915 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10916 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10917 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10918 }
10919
edc3d884
MK		 10920 err_printf(m, "Cursor [%d]:\n", i);
10921 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10922 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10923 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10924 }
63b66e5b
CW		 10925
10926 for (i = 0; i < error->num_transcoders; i++) {
10927 err_printf(m, " CPU transcoder: %c\n",
10928 transcoder_name(error->transcoder[i].cpu_transcoder));
10929 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10930 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10931 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10932 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10933 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10934 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10935 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10936 }
c4a1d9e4 10937}
Linux kernel - Deliverables
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