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drm/i915/bxt: fix RC6 residency time calculation
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
ea916ea0
KM		 75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
465c120c
MR		 79};
80
3d7d6510
MR		 81/* Cursor formats */
82static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84};
85
6b383a7f 86static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 87
f1f644dc 88static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 89 struct intel_crtc_state *pipe_config);
18442d08 90static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 91 struct intel_crtc_state *pipe_config);
f1f644dc 92
eb1bfe80
JB		 93static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
5b18e57c
DV		 97static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 99static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
29407aab 102static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 103static void haswell_set_pipeconf(struct drm_crtc *crtc);
104static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 105static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
d288f65f 107static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 108 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 109static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 111static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
bfd16b2a
ML		 115static void skylake_pfit_enable(struct intel_crtc *crtc);
116static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117static void ironlake_pfit_enable(struct intel_crtc *crtc);
043e9bda 118static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 119
79e53945 120typedef struct {
0206e353 121 int min, max;
79e53945
JB		 122} intel_range_t;
123
124typedef struct {
0206e353
AJ		 125 int dot_limit;
126 int p2_slow, p2_fast;
79e53945
JB		 127} intel_p2_t;
128
d4906093
ML		 129typedef struct intel_limit intel_limit_t;
130struct intel_limit {
0206e353
AJ		 131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
d4906093 133};
79e53945 134
bfa7df01
VS		 135/* returns HPLL frequency in kHz */
136static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137{
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147}
148
149static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151{
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169}
170
d2acd215
DV		 171int
172intel_pch_rawclk(struct drm_device *dev)
173{
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179}
180
79e50a4f
JN		 181/* hrawclock is 1/4 the FSB frequency */
182int intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
bfa7df01
VS		 214static void intel_update_czclk(struct drm_i915_private *dev_priv)
215{
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223}
224
021357ac
CW		 225static inline u32 /* units of 100MHz */
226intel_fdi_link_freq(struct drm_device *dev)
227{
8b99e68c
CW		 228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
021357ac
CW		 233}
234
5d536e28 235static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 236 .dot = { .min = 25000, .max = 350000 },
9c333719 237 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 238 .n = { .min = 2, .max = 16 },
0206e353
AJ		 239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 246};
247
5d536e28
DV		 248static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
9c333719 250 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 251 .n = { .min = 2, .max = 16 },
5d536e28
DV		 252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259};
260
e4b36699 261static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 262 .dot = { .min = 25000, .max = 350000 },
9c333719 263 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 264 .n = { .min = 2, .max = 16 },
0206e353
AJ		 265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
e4b36699 272};
273e27ca 273
e4b36699 274static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 285};
286
287static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 298};
299
273e27ca 300
e4b36699 301static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
044c7c41 313 },
e4b36699
KP		 314};
315
316static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 327};
328
329static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
044c7c41 340 },
e4b36699
KP		 341};
342
343static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
044c7c41 354 },
e4b36699
KP		 355};
356
f2b115e6 357static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 360 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
273e27ca 363 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 370};
371
f2b115e6 372static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 383};
384
273e27ca
EA		 385/* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
b91ad0ec 390static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 401};
402
b91ad0ec 403static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 414};
415
416static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 427};
428
273e27ca 429/* LVDS 100mhz refclk limits. */
b91ad0ec 430static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
0206e353 438 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 441};
442
443static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
0206e353 451 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 454};
455
dc730512 456static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 464 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 465 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
b99ab663 468 .p1 = { .min = 2, .max = 3 },
5fdc9c49 469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 470};
471
ef9348c8
CML		 472static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 480 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486};
487
5ab7b0b7
ID		 488static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
e6292556 491 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498};
499
cdba954e
ACO		 500static bool
501needs_modeset(struct drm_crtc_state *state)
502{
fc596660 503 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 504}
505
e0638cdf
PZ		 506/**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
4093561b 509bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 510{
409ee761 511 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 512 struct intel_encoder *encoder;
513
409ee761 514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 515 if (encoder->type == type)
516 return true;
517
518 return false;
519}
520
d0737e1d
ACO		 521/**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
a93e255f
ACO		 527static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
d0737e1d 529{
a93e255f 530 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 531 struct drm_connector *connector;
a93e255f 532 struct drm_connector_state *connector_state;
d0737e1d 533 struct intel_encoder *encoder;
a93e255f
ACO		 534 int i, num_connectors = 0;
535
da3ced29 536 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
d0737e1d 541
a93e255f
ACO		 542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
d0737e1d 544 return true;
a93e255f
ACO		 545 }
546
547 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 548
549 return false;
550}
551
a93e255f
ACO		 552static const intel_limit_t *
553intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 554{
a93e255f 555 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 556 const intel_limit_t *limit;
b91ad0ec 557
a93e255f 558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 559 if (intel_is_dual_link_lvds(dev)) {
1b894b59 560 if (refclk == 100000)
b91ad0ec
ZW		 561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
1b894b59 565 if (refclk == 100000)
b91ad0ec
ZW		 566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
c6bb3538 570 } else
b91ad0ec 571 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 572
573 return limit;
574}
575
a93e255f
ACO		 576static const intel_limit_t *
577intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 578{
a93e255f 579 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 580 const intel_limit_t *limit;
581
a93e255f 582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 583 if (intel_is_dual_link_lvds(dev))
e4b36699 584 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 585 else
e4b36699 586 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 589 limit = &intel_limits_g4x_hdmi;
a93e255f 590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 591 limit = &intel_limits_g4x_sdvo;
044c7c41 592 } else /* The option is for other outputs */
e4b36699 593 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 594
595 return limit;
596}
597
a93e255f
ACO		 598static const intel_limit_t *
599intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 600{
a93e255f 601 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 602 const intel_limit_t *limit;
603
5ab7b0b7
ID		 604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
a93e255f 607 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 608 else if (IS_G4X(dev)) {
a93e255f 609 limit = intel_g4x_limit(crtc_state);
f2b115e6 610 } else if (IS_PINEVIEW(dev)) {
a93e255f 611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 612 limit = &intel_limits_pineview_lvds;
2177832f 613 else
f2b115e6 614 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
a0c4da24 617 } else if (IS_VALLEYVIEW(dev)) {
dc730512 618 limit = &intel_limits_vlv;
a6c45cf0 619 } else if (!IS_GEN2(dev)) {
a93e255f 620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
79e53945 624 } else {
a93e255f 625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 626 limit = &intel_limits_i8xx_lvds;
a93e255f 627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 628 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 629 else
630 limit = &intel_limits_i8xx_dac;
79e53945
JB		 631 }
632 return limit;
633}
634
dccbea3b
ID		 635/*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
f2b115e6 643/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 644static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 645{
2177832f
SL		 646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
ed5ca77e 648 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 649 return 0;
fb03ac01
VS		 650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 652
653 return clock->dot;
2177832f
SL		 654}
655
7429e9d4
DV		 656static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657{
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659}
660
dccbea3b 661static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 662{
7429e9d4 663 clock->m = i9xx_dpll_compute_m(clock);
79e53945 664 clock->p = clock->p1 * clock->p2;
ed5ca77e 665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 666 return 0;
fb03ac01
VS		 667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 669
670 return clock->dot;
79e53945
JB		 671}
672
dccbea3b 673static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 674{
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 678 return 0;
589eca67
ID		 679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 681
682 return clock->dot / 5;
589eca67
ID		 683}
684
dccbea3b 685int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 686{
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 690 return 0;
ef9348c8
CML		 691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 694
695 return clock->dot / 5;
ef9348c8
CML		 696}
697
7c04d1d9 698#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 699/**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
1b894b59
CW		 704static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
79e53945 707{
f01b7962
VS		 708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
79e53945 710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 711 INTELPllInvalid("p1 out of range\n");
79e53945 712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 713 INTELPllInvalid("m2 out of range\n");
79e53945 714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 715 INTELPllInvalid("m1 out of range\n");
f01b7962 716
5ab7b0b7 717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
5ab7b0b7 721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
79e53945 728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 729 INTELPllInvalid("vco out of range\n");
79e53945
JB		 730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 734 INTELPllInvalid("dot out of range\n");
79e53945
JB		 735
736 return true;
737}
738
3b1429d9
VS		 739static int
740i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
79e53945 743{
3b1429d9 744 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 745
a93e255f 746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 747 /*
a210b028
DV		 748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
79e53945 751 */
1974cad0 752 if (intel_is_dual_link_lvds(dev))
3b1429d9 753 return limit->p2.p2_fast;
79e53945 754 else
3b1429d9 755 return limit->p2.p2_slow;
79e53945
JB		 756 } else {
757 if (target < limit->p2.dot_limit)
3b1429d9 758 return limit->p2.p2_slow;
79e53945 759 else
3b1429d9 760 return limit->p2.p2_fast;
79e53945 761 }
3b1429d9
VS		 762}
763
764static bool
765i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769{
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
79e53945 773
0206e353 774 memset(best_clock, 0, sizeof(*best_clock));
79e53945 775
3b1429d9
VS		 776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
42158660
ZY		 778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 782 if (clock.m2 >= clock.m1)
42158660
ZY		 783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 788 int this_err;
789
dccbea3b 790 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809}
810
811static bool
a93e255f
ACO		 812pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
79e53945 816{
3b1429d9 817 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 818 intel_clock_t clock;
79e53945
JB		 819 int err = target;
820
0206e353 821 memset(best_clock, 0, sizeof(*best_clock));
79e53945 822
3b1429d9
VS		 823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
42158660
ZY		 825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 833 int this_err;
834
dccbea3b 835 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
79e53945 838 continue;
cec2f356
SP		 839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
79e53945
JB		 842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854}
855
d4906093 856static bool
a93e255f
ACO		 857g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
d4906093 861{
3b1429d9 862 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 863 intel_clock_t clock;
864 int max_n;
3b1429d9 865 bool found = false;
6ba770dc
AJ		 866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 868
869 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
d4906093 873 max_n = limit->n.max;
f77f13e2 874 /* based on hardware requirement, prefer smaller n to precision */
d4906093 875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 876 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
dccbea3b 885 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
d4906093 888 continue;
1b894b59
CW		 889
890 this_err = abs(clock.dot - target);
d4906093
ML		 891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
2c07245f
ZW		 901 return found;
902}
903
d5dd62bd
ID		 904/*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913{
9ca3ba01
ID		 914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
24be4e46
ID		 924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
d5dd62bd
ID		 927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942}
943
a0c4da24 944static bool
a93e255f
ACO		 945vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
a0c4da24 949{
a93e255f 950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 951 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 952 intel_clock_t clock;
69e4f900 953 unsigned int bestppm = 1000000;
27e639bf
VS		 954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 956 bool found = false;
a0c4da24 957
6b4bf1c4
VS		 958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 961
962 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 967 clock.p = clock.p1 * clock.p2;
a0c4da24 968 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 970 unsigned int ppm;
69e4f900 971
6b4bf1c4
VS		 972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
dccbea3b 975 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 976
f01b7962
VS		 977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
43b0ac53
VS		 979 continue;
980
d5dd62bd
ID		 981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
6b4bf1c4 986
d5dd62bd
ID		 987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
a0c4da24
JB		 990 }
991 }
992 }
993 }
a0c4da24 994
49e497ef 995 return found;
a0c4da24 996}
a4fc5ed6 997
ef9348c8 998static bool
a93e255f
ACO		 999chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003{
a93e255f 1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 1005 struct drm_device *dev = crtc->base.dev;
9ca3ba01 1006 unsigned int best_error_ppm;
ef9348c8
CML		 1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 1012 best_error_ppm = 1000000;
ef9348c8
CML		 1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 1026 unsigned int error_ppm;
ef9348c8
CML		 1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
dccbea3b 1038 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
9ca3ba01
ID		 1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
ef9348c8
CML		 1050 }
1051 }
1052
1053 return found;
1054}
1055
5ab7b0b7
ID		 1056bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058{
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063}
1064
20ddf665
VS		 1065bool intel_crtc_active(struct drm_crtc *crtc)
1066{
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
241bfc38 1072 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 1073 * as Haswell has gained clock readout/fastboot support.
1074 *
66e514c1 1075 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1076 * properly reconstruct framebuffers.
c3d1f436
MR		 1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
20ddf665 1081 */
c3d1f436 1082 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1084}
1085
a5c961d1
PZ		 1086enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088{
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
6e3c9717 1092 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1093}
1094
fbf49ea2
VS		 1095static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096{
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1108 msleep(5);
fbf49ea2
VS		 1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112}
1113
ab7ad7f6
KP		 1114/*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1116 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
ab7ad7f6
KP		 1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
58e10eb9 1128 *
9d0498a2 1129 */
575f7ab7 1130static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1131{
575f7ab7 1132 struct drm_device *dev = crtc->base.dev;
9d0498a2 1133 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1135 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1138 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1139
1140 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
284637d9 1143 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1144 } else {
ab7ad7f6 1145 /* Wait for the display line to settle */
fbf49ea2 1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1147 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1148 }
79e53945
JB		 1149}
1150
b24e7179
JB		 1151static const char *state_string(bool enabled)
1152{
1153 return enabled ? "on" : "off";
1154}
1155
1156/* Only for pre-ILK configs */
55607e8a
DV		 1157void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
b24e7179
JB		 1159{
1160 int reg;
1161 u32 val;
1162 bool cur_state;
1163
1164 reg = DPLL(pipe);
1165 val = I915_READ(reg);
1166 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1167 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1168 "PLL state assertion failure (expected %s, current %s)\n",
1169 state_string(state), state_string(cur_state));
1170}
b24e7179 1171
23538ef1
JN		 1172/* XXX: the dsi pll is shared between MIPI DSI ports */
1173static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1174{
1175 u32 val;
1176 bool cur_state;
1177
a580516d 1178 mutex_lock(&dev_priv->sb_lock);
23538ef1 1179 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1180 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1181
1182 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1183 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1184 "DSI PLL state assertion failure (expected %s, current %s)\n",
1185 state_string(state), state_string(cur_state));
1186}
1187#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1189
55607e8a 1190struct intel_shared_dpll *
e2b78267
DV		 1191intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1192{
1193 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1194
6e3c9717 1195 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1196 return NULL;
1197
6e3c9717 1198 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1199}
1200
040484af 1201/* For ILK+ */
55607e8a
DV		 1202void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203 struct intel_shared_dpll *pll,
1204 bool state)
040484af 1205{
040484af 1206 bool cur_state;
5358901f 1207 struct intel_dpll_hw_state hw_state;
040484af 1208
92b27b08 1209 if (WARN (!pll,
46edb027 1210 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1211 return;
ee7b9f93 1212
5358901f 1213 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1214 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1215 "%s assertion failure (expected %s, current %s)\n",
1216 pll->name, state_string(state), state_string(cur_state));
040484af 1217}
040484af
JB		 1218
1219static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1221{
1222 int reg;
1223 u32 val;
1224 bool cur_state;
ad80a810
PZ		 1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
040484af 1227
affa9354
PZ		 1228 if (HAS_DDI(dev_priv->dev)) {
1229 /* DDI does not have a specific FDI_TX register */
ad80a810 1230 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1231 val = I915_READ(reg);
ad80a810 1232 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1233 } else {
1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & FDI_TX_ENABLE);
1237 }
e2c719b7 1238 I915_STATE_WARN(cur_state != state,
040484af
JB		 1239 "FDI TX state assertion failure (expected %s, current %s)\n",
1240 state_string(state), state_string(cur_state));
1241}
1242#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1243#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1244
1245static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, bool state)
1247{
1248 int reg;
1249 u32 val;
1250 bool cur_state;
1251
d63fa0dc
PZ		 1252 reg = FDI_RX_CTL(pipe);
1253 val = I915_READ(reg);
1254 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1255 I915_STATE_WARN(cur_state != state,
040484af
JB		 1256 "FDI RX state assertion failure (expected %s, current %s)\n",
1257 state_string(state), state_string(cur_state));
1258}
1259#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1260#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1261
1262static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg;
1266 u32 val;
1267
1268 /* ILK FDI PLL is always enabled */
3d13ef2e 1269 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1270 return;
1271
bf507ef7 1272 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1273 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1274 return;
1275
040484af
JB		 1276 reg = FDI_TX_CTL(pipe);
1277 val = I915_READ(reg);
e2c719b7 1278 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1279}
1280
55607e8a
DV		 1281void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1282 enum pipe pipe, bool state)
040484af
JB		 1283{
1284 int reg;
1285 u32 val;
55607e8a 1286 bool cur_state;
040484af
JB		 1287
1288 reg = FDI_RX_CTL(pipe);
1289 val = I915_READ(reg);
55607e8a 1290 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1291 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1292 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1293 state_string(state), state_string(cur_state));
040484af
JB		 1294}
1295
b680c37a
DV		 1296void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1297 enum pipe pipe)
ea0760cf 1298{
bedd4dba
JN		 1299 struct drm_device *dev = dev_priv->dev;
1300 int pp_reg;
ea0760cf
JB		 1301 u32 val;
1302 enum pipe panel_pipe = PIPE_A;
0de3b485 1303 bool locked = true;
ea0760cf 1304
bedd4dba
JN		 1305 if (WARN_ON(HAS_DDI(dev)))
1306 return;
1307
1308 if (HAS_PCH_SPLIT(dev)) {
1309 u32 port_sel;
1310
ea0760cf 1311 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1312 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1313
1314 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1315 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1316 panel_pipe = PIPE_B;
1317 /* XXX: else fix for eDP */
1318 } else if (IS_VALLEYVIEW(dev)) {
1319 /* presumably write lock depends on pipe, not port select */
1320 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1321 panel_pipe = pipe;
ea0760cf
JB		 1322 } else {
1323 pp_reg = PP_CONTROL;
bedd4dba
JN		 1324 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1325 panel_pipe = PIPE_B;
ea0760cf
JB		 1326 }
1327
1328 val = I915_READ(pp_reg);
1329 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1330 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1331 locked = false;
1332
e2c719b7 1333 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1334 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1335 pipe_name(pipe));
ea0760cf
JB		 1336}
1337
93ce0ba6
JN		 1338static void assert_cursor(struct drm_i915_private *dev_priv,
1339 enum pipe pipe, bool state)
1340{
1341 struct drm_device *dev = dev_priv->dev;
1342 bool cur_state;
1343
d9d82081 1344 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 1345 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
d9d82081 1346 else
5efb3e28 1347 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1348
e2c719b7 1349 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1350 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe), state_string(state), state_string(cur_state));
1352}
1353#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1354#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1355
b840d907
JB		 1356void assert_pipe(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, bool state)
b24e7179
JB		 1358{
1359 int reg;
1360 u32 val;
63d7bbe9 1361 bool cur_state;
702e7a56
PZ		 1362 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1363 pipe);
b24e7179 1364
b6b5d049
VS		 1365 /* if we need the pipe quirk it must be always on */
1366 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1367 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1368 state = true;
1369
f458ebbc 1370 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1371 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1372 cur_state = false;
1373 } else {
1374 reg = PIPECONF(cpu_transcoder);
1375 val = I915_READ(reg);
1376 cur_state = !!(val & PIPECONF_ENABLE);
1377 }
1378
e2c719b7 1379 I915_STATE_WARN(cur_state != state,
63d7bbe9 1380 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1381 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1382}
1383
931872fc
CW		 1384static void assert_plane(struct drm_i915_private *dev_priv,
1385 enum plane plane, bool state)
b24e7179
JB		 1386{
1387 int reg;
1388 u32 val;
931872fc 1389 bool cur_state;
b24e7179
JB		 1390
1391 reg = DSPCNTR(plane);
1392 val = I915_READ(reg);
931872fc 1393 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1394 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1395 "plane %c assertion failure (expected %s, current %s)\n",
1396 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1397}
1398
931872fc
CW		 1399#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1400#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1401
b24e7179
JB		 1402static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe)
1404{
653e1026 1405 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1406 int reg, i;
1407 u32 val;
1408 int cur_pipe;
1409
653e1026
VS		 1410 /* Primary planes are fixed to pipes on gen4+ */
1411 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1412 reg = DSPCNTR(pipe);
1413 val = I915_READ(reg);
e2c719b7 1414 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1415 "plane %c assertion failure, should be disabled but not\n",
1416 plane_name(pipe));
19ec1358 1417 return;
28c05794 1418 }
19ec1358 1419
b24e7179 1420 /* Need to check both planes against the pipe */
055e393f 1421 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1422 reg = DSPCNTR(i);
1423 val = I915_READ(reg);
1424 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1425 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1426 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1427 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1428 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1429 }
1430}
1431
19332d7a
JB		 1432static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434{
20674eef 1435 struct drm_device *dev = dev_priv->dev;
1fe47785 1436 int reg, sprite;
19332d7a
JB		 1437 u32 val;
1438
7feb8b88 1439 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1440 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1441 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1442 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1443 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1444 sprite, pipe_name(pipe));
1445 }
1446 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1447 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1448 reg = SPCNTR(pipe, sprite);
20674eef 1449 val = I915_READ(reg);
e2c719b7 1450 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1451 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1452 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1453 }
1454 } else if (INTEL_INFO(dev)->gen >= 7) {
1455 reg = SPRCTL(pipe);
19332d7a 1456 val = I915_READ(reg);
e2c719b7 1457 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1458 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1459 plane_name(pipe), pipe_name(pipe));
1460 } else if (INTEL_INFO(dev)->gen >= 5) {
1461 reg = DVSCNTR(pipe);
19332d7a 1462 val = I915_READ(reg);
e2c719b7 1463 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1464 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1465 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1466 }
1467}
1468
08c71e5e
VS		 1469static void assert_vblank_disabled(struct drm_crtc *crtc)
1470{
e2c719b7 1471 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1472 drm_crtc_vblank_put(crtc);
1473}
1474
89eff4be 1475static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1476{
1477 u32 val;
1478 bool enabled;
1479
e2c719b7 1480 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1481
92f2584a
JB		 1482 val = I915_READ(PCH_DREF_CONTROL);
1483 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1484 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1485 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1486}
1487
ab9412ba
DV		 1488static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1489 enum pipe pipe)
92f2584a
JB		 1490{
1491 int reg;
1492 u32 val;
1493 bool enabled;
1494
ab9412ba 1495 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1496 val = I915_READ(reg);
1497 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1498 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1499 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1500 pipe_name(pipe));
92f2584a
JB		 1501}
1502
4e634389
KP		 1503static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1504 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1505{
1506 if ((val & DP_PORT_EN) == 0)
1507 return false;
1508
1509 if (HAS_PCH_CPT(dev_priv->dev)) {
1510 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1511 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1512 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1513 return false;
44f37d1f
CML		 1514 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1515 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1516 return false;
f0575e92
KP		 1517 } else {
1518 if ((val & DP_PIPE_MASK) != (pipe << 30))
1519 return false;
1520 }
1521 return true;
1522}
1523
1519b995
KP		 1524static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
dc0fa718 1527 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1528 return false;
1529
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1531 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1532 return false;
44f37d1f
CML		 1533 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1534 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1535 return false;
1519b995 1536 } else {
dc0fa718 1537 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1538 return false;
1539 }
1540 return true;
1541}
1542
1543static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1544 enum pipe pipe, u32 val)
1545{
1546 if ((val & LVDS_PORT_EN) == 0)
1547 return false;
1548
1549 if (HAS_PCH_CPT(dev_priv->dev)) {
1550 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1551 return false;
1552 } else {
1553 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1554 return false;
1555 }
1556 return true;
1557}
1558
1559static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1560 enum pipe pipe, u32 val)
1561{
1562 if ((val & ADPA_DAC_ENABLE) == 0)
1563 return false;
1564 if (HAS_PCH_CPT(dev_priv->dev)) {
1565 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1566 return false;
1567 } else {
1568 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1569 return false;
1570 }
1571 return true;
1572}
1573
291906f1 1574static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1575 enum pipe pipe, int reg, u32 port_sel)
291906f1 1576{
47a05eca 1577 u32 val = I915_READ(reg);
e2c719b7 1578 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1579 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1580 reg, pipe_name(pipe));
de9a35ab 1581
e2c719b7 1582 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1583 && (val & DP_PIPEB_SELECT),
de9a35ab 1584 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1585}
1586
1587static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1588 enum pipe pipe, int reg)
1589{
47a05eca 1590 u32 val = I915_READ(reg);
e2c719b7 1591 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1592 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1593 reg, pipe_name(pipe));
de9a35ab 1594
e2c719b7 1595 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1596 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1597 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1598}
1599
1600static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1601 enum pipe pipe)
1602{
1603 int reg;
1604 u32 val;
291906f1 1605
f0575e92
KP		 1606 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1607 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1608 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1609
1610 reg = PCH_ADPA;
1611 val = I915_READ(reg);
e2c719b7 1612 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1613 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1614 pipe_name(pipe));
291906f1
JB		 1615
1616 reg = PCH_LVDS;
1617 val = I915_READ(reg);
e2c719b7 1618 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1619 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1620 pipe_name(pipe));
291906f1 1621
e2debe91
PZ		 1622 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1623 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1624 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1625}
1626
d288f65f 1627static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1628 const struct intel_crtc_state *pipe_config)
87442f73 1629{
426115cf
DV		 1630 struct drm_device *dev = crtc->base.dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 int reg = DPLL(crtc->pipe);
d288f65f 1633 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1634
426115cf 1635 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1636
1637 /* No really, not for ILK+ */
1638 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1639
1640 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1641 if (IS_MOBILE(dev_priv->dev))
426115cf 1642 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1643
426115cf
DV		 1644 I915_WRITE(reg, dpll);
1645 POSTING_READ(reg);
1646 udelay(150);
1647
1648 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1649 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1650
d288f65f 1651 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1652 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1653
1654 /* We do this three times for luck */
426115cf 1655 I915_WRITE(reg, dpll);
87442f73
DV		 1656 POSTING_READ(reg);
1657 udelay(150); /* wait for warmup */
426115cf 1658 I915_WRITE(reg, dpll);
87442f73
DV		 1659 POSTING_READ(reg);
1660 udelay(150); /* wait for warmup */
426115cf 1661 I915_WRITE(reg, dpll);
87442f73
DV		 1662 POSTING_READ(reg);
1663 udelay(150); /* wait for warmup */
1664}
1665
d288f65f 1666static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1667 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1668{
1669 struct drm_device *dev = crtc->base.dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 int pipe = crtc->pipe;
1672 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1673 u32 tmp;
1674
1675 assert_pipe_disabled(dev_priv, crtc->pipe);
1676
1677 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1678
a580516d 1679 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1680
1681 /* Enable back the 10bit clock to display controller */
1682 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1683 tmp |= DPIO_DCLKP_EN;
1684 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1685
54433e91
VS		 1686 mutex_unlock(&dev_priv->sb_lock);
1687
9d556c99
CML		 1688 /*
1689 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1690 */
1691 udelay(1);
1692
1693 /* Enable PLL */
d288f65f 1694 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1695
1696 /* Check PLL is locked */
a11b0703 1697 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1698 DRM_ERROR("PLL %d failed to lock\n", pipe);
1699
a11b0703 1700 /* not sure when this should be written */
d288f65f 1701 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1702 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1703}
1704
1c4e0274
VS		 1705static int intel_num_dvo_pipes(struct drm_device *dev)
1706{
1707 struct intel_crtc *crtc;
1708 int count = 0;
1709
1710 for_each_intel_crtc(dev, crtc)
3538b9df 1711 count += crtc->base.state->active &&
409ee761 1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1713
1714 return count;
1715}
1716
66e3d5c0 1717static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1718{
66e3d5c0
DV		 1719 struct drm_device *dev = crtc->base.dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 int reg = DPLL(crtc->pipe);
6e3c9717 1722 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1723
66e3d5c0 1724 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1725
63d7bbe9 1726 /* No really, not for ILK+ */
3d13ef2e 1727 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1728
1729 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1730 if (IS_MOBILE(dev) && !IS_I830(dev))
1731 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1732
1c4e0274
VS		 1733 /* Enable DVO 2x clock on both PLLs if necessary */
1734 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1735 /*
1736 * It appears to be important that we don't enable this
1737 * for the current pipe before otherwise configuring the
1738 * PLL. No idea how this should be handled if multiple
1739 * DVO outputs are enabled simultaneosly.
1740 */
1741 dpll |= DPLL_DVO_2X_MODE;
1742 I915_WRITE(DPLL(!crtc->pipe),
1743 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1744 }
66e3d5c0
DV		 1745
1746 /* Wait for the clocks to stabilize. */
1747 POSTING_READ(reg);
1748 udelay(150);
1749
1750 if (INTEL_INFO(dev)->gen >= 4) {
1751 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1752 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1753 } else {
1754 /* The pixel multiplier can only be updated once the
1755 * DPLL is enabled and the clocks are stable.
1756 *
1757 * So write it again.
1758 */
1759 I915_WRITE(reg, dpll);
1760 }
63d7bbe9
JB		 1761
1762 /* We do this three times for luck */
66e3d5c0 1763 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1764 POSTING_READ(reg);
1765 udelay(150); /* wait for warmup */
66e3d5c0 1766 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1767 POSTING_READ(reg);
1768 udelay(150); /* wait for warmup */
66e3d5c0 1769 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1770 POSTING_READ(reg);
1771 udelay(150); /* wait for warmup */
1772}
1773
1774/**
50b44a44 1775 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1776 * @dev_priv: i915 private structure
1777 * @pipe: pipe PLL to disable
1778 *
1779 * Disable the PLL for @pipe, making sure the pipe is off first.
1780 *
1781 * Note! This is for pre-ILK only.
1782 */
1c4e0274 1783static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1784{
1c4e0274
VS		 1785 struct drm_device *dev = crtc->base.dev;
1786 struct drm_i915_private *dev_priv = dev->dev_private;
1787 enum pipe pipe = crtc->pipe;
1788
1789 /* Disable DVO 2x clock on both PLLs if necessary */
1790 if (IS_I830(dev) &&
409ee761 1791 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1792 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1793 I915_WRITE(DPLL(PIPE_B),
1794 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1795 I915_WRITE(DPLL(PIPE_A),
1796 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1797 }
1798
b6b5d049
VS		 1799 /* Don't disable pipe or pipe PLLs if needed */
1800 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1801 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1802 return;
1803
1804 /* Make sure the pipe isn't still relying on us */
1805 assert_pipe_disabled(dev_priv, pipe);
1806
b8afb911 1807 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1808 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1809}
1810
f6071166
JB		 1811static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812{
b8afb911 1813 u32 val;
f6071166
JB		 1814
1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
1817
e5cbfbfb
ID		 1818 /*
1819 * Leave integrated clock source and reference clock enabled for pipe B.
1820 * The latter is needed for VGA hotplug / manual detection.
1821 */
b8afb911 1822 val = DPLL_VGA_MODE_DIS;
f6071166 1823 if (pipe == PIPE_B)
60bfe44f 1824 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1825 I915_WRITE(DPLL(pipe), val);
1826 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1827
1828}
1829
1830static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1831{
d752048d 1832 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1833 u32 val;
1834
a11b0703
VS		 1835 /* Make sure the pipe isn't still relying on us */
1836 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1837
a11b0703 1838 /* Set PLL en = 0 */
60bfe44f
VS		 1839 val = DPLL_SSC_REF_CLK_CHV |
1840 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1841 if (pipe != PIPE_A)
1842 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1843 I915_WRITE(DPLL(pipe), val);
1844 POSTING_READ(DPLL(pipe));
d752048d 1845
a580516d 1846 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1847
1848 /* Disable 10bit clock to display controller */
1849 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1850 val &= ~DPIO_DCLKP_EN;
1851 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1852
a580516d 1853 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1854}
1855
e4607fcf 1856void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1857 struct intel_digital_port *dport,
1858 unsigned int expected_mask)
89b667f8
JB		 1859{
1860 u32 port_mask;
00fc31b7 1861 int dpll_reg;
89b667f8 1862
e4607fcf
CML		 1863 switch (dport->port) {
1864 case PORT_B:
89b667f8 1865 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1866 dpll_reg = DPLL(0);
e4607fcf
CML		 1867 break;
1868 case PORT_C:
89b667f8 1869 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1870 dpll_reg = DPLL(0);
9b6de0a1 1871 expected_mask <<= 4;
00fc31b7
CML		 1872 break;
1873 case PORT_D:
1874 port_mask = DPLL_PORTD_READY_MASK;
1875 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1876 break;
1877 default:
1878 BUG();
1879 }
89b667f8 1880
9b6de0a1
VS		 1881 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1882 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1883 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1884}
1885
b14b1055
DV		 1886static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1887{
1888 struct drm_device *dev = crtc->base.dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1891
be19f0ff
CW		 1892 if (WARN_ON(pll == NULL))
1893 return;
1894
3e369b76 1895 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1896 if (pll->active == 0) {
1897 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1898 WARN_ON(pll->on);
1899 assert_shared_dpll_disabled(dev_priv, pll);
1900
1901 pll->mode_set(dev_priv, pll);
1902 }
1903}
1904
92f2584a 1905/**
85b3894f 1906 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1907 * @dev_priv: i915 private structure
1908 * @pipe: pipe PLL to enable
1909 *
1910 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1911 * drives the transcoder clock.
1912 */
85b3894f 1913static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1914{
3d13ef2e
DL		 1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1918
87a875bb 1919 if (WARN_ON(pll == NULL))
48da64a8
CW		 1920 return;
1921
3e369b76 1922 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1923 return;
ee7b9f93 1924
74dd6928 1925 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1926 pll->name, pll->active, pll->on,
e2b78267 1927 crtc->base.base.id);
92f2584a 1928
cdbd2316
DV		 1929 if (pll->active++) {
1930 WARN_ON(!pll->on);
e9d6944e 1931 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1932 return;
1933 }
f4a091c7 1934 WARN_ON(pll->on);
ee7b9f93 1935
bd2bb1b9
PZ		 1936 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1937
46edb027 1938 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1939 pll->enable(dev_priv, pll);
ee7b9f93 1940 pll->on = true;
92f2584a
JB		 1941}
1942
f6daaec2 1943static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1944{
3d13ef2e
DL		 1945 struct drm_device *dev = crtc->base.dev;
1946 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1947 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1948
92f2584a 1949 /* PCH only available on ILK+ */
80aa9312
JB		 1950 if (INTEL_INFO(dev)->gen < 5)
1951 return;
1952
eddfcbcd
ML		 1953 if (pll == NULL)
1954 return;
92f2584a 1955
eddfcbcd 1956 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1957 return;
7a419866 1958
46edb027
DV		 1959 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1960 pll->name, pll->active, pll->on,
e2b78267 1961 crtc->base.base.id);
7a419866 1962
48da64a8 1963 if (WARN_ON(pll->active == 0)) {
e9d6944e 1964 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1965 return;
1966 }
1967
e9d6944e 1968 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1969 WARN_ON(!pll->on);
cdbd2316 1970 if (--pll->active)
7a419866 1971 return;
ee7b9f93 1972
46edb027 1973 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1974 pll->disable(dev_priv, pll);
ee7b9f93 1975 pll->on = false;
bd2bb1b9
PZ		 1976
1977 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1978}
1979
b8a4f404
PZ		 1980static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1981 enum pipe pipe)
040484af 1982{
23670b32 1983 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1984 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1986 uint32_t reg, val, pipeconf_val;
040484af
JB		 1987
1988 /* PCH only available on ILK+ */
55522f37 1989 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1990
1991 /* Make sure PCH DPLL is enabled */
e72f9fbf 1992 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1993 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1994
1995 /* FDI must be feeding us bits for PCH ports */
1996 assert_fdi_tx_enabled(dev_priv, pipe);
1997 assert_fdi_rx_enabled(dev_priv, pipe);
1998
23670b32
DV		 1999 if (HAS_PCH_CPT(dev)) {
2000 /* Workaround: Set the timing override bit before enabling the
2001 * pch transcoder. */
2002 reg = TRANS_CHICKEN2(pipe);
2003 val = I915_READ(reg);
2004 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2005 I915_WRITE(reg, val);
59c859d6 2006 }
23670b32 2007
ab9412ba 2008 reg = PCH_TRANSCONF(pipe);
040484af 2009 val = I915_READ(reg);
5f7f726d 2010 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2011
2012 if (HAS_PCH_IBX(dev_priv->dev)) {
2013 /*
c5de7c6f
VS		 2014 * Make the BPC in transcoder be consistent with
2015 * that in pipeconf reg. For HDMI we must use 8bpc
2016 * here for both 8bpc and 12bpc.
e9bcff5c 2017 */
dfd07d72 2018 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2019 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2020 val |= PIPECONF_8BPC;
2021 else
2022 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2023 }
5f7f726d
PZ		 2024
2025 val &= ~TRANS_INTERLACE_MASK;
2026 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2027 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2028 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2029 val |= TRANS_LEGACY_INTERLACED_ILK;
2030 else
2031 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2032 else
2033 val |= TRANS_PROGRESSIVE;
2034
040484af
JB		 2035 I915_WRITE(reg, val | TRANS_ENABLE);
2036 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2037 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2038}
2039
8fb033d7 2040static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2041 enum transcoder cpu_transcoder)
040484af 2042{
8fb033d7 2043 u32 val, pipeconf_val;
8fb033d7
PZ		 2044
2045 /* PCH only available on ILK+ */
55522f37 2046 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2047
8fb033d7 2048 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2049 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2050 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2051
223a6fdf 2052 /* Workaround: set timing override bit. */
36c0d0cf 2053 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2054 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2055 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
223a6fdf 2056
25f3ef11 2057 val = TRANS_ENABLE;
937bb610 2058 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2059
9a76b1c6
PZ		 2060 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2061 PIPECONF_INTERLACED_ILK)
a35f2679 2062 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2063 else
2064 val |= TRANS_PROGRESSIVE;
2065
ab9412ba
DV		 2066 I915_WRITE(LPT_TRANSCONF, val);
2067 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2068 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2069}
2070
b8a4f404
PZ		 2071static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2072 enum pipe pipe)
040484af 2073{
23670b32
DV		 2074 struct drm_device *dev = dev_priv->dev;
2075 uint32_t reg, val;
040484af
JB		 2076
2077 /* FDI relies on the transcoder */
2078 assert_fdi_tx_disabled(dev_priv, pipe);
2079 assert_fdi_rx_disabled(dev_priv, pipe);
2080
291906f1
JB		 2081 /* Ports must be off as well */
2082 assert_pch_ports_disabled(dev_priv, pipe);
2083
ab9412ba 2084 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2085 val = I915_READ(reg);
2086 val &= ~TRANS_ENABLE;
2087 I915_WRITE(reg, val);
2088 /* wait for PCH transcoder off, transcoder state */
2089 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2090 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2091
2092 if (!HAS_PCH_IBX(dev)) {
2093 /* Workaround: Clear the timing override chicken bit again. */
2094 reg = TRANS_CHICKEN2(pipe);
2095 val = I915_READ(reg);
2096 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2097 I915_WRITE(reg, val);
2098 }
040484af
JB		 2099}
2100
ab4d966c 2101static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2102{
8fb033d7
PZ		 2103 u32 val;
2104
ab9412ba 2105 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2106 val &= ~TRANS_ENABLE;
ab9412ba 2107 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2108 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2109 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2110 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2111
2112 /* Workaround: clear timing override bit. */
36c0d0cf 2113 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2114 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2115 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
040484af
JB		 2116}
2117
b24e7179 2118/**
309cfea8 2119 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2120 * @crtc: crtc responsible for the pipe
b24e7179 2121 *
0372264a 2122 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2123 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2124 */
e1fdc473 2125static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2126{
0372264a
PZ		 2127 struct drm_device *dev = crtc->base.dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2130 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2131 pipe);
1a240d4d 2132 enum pipe pch_transcoder;
b24e7179
JB		 2133 int reg;
2134 u32 val;
2135
9e2ee2dd
VS		 2136 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2137
58c6eaa2 2138 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2139 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2140 assert_sprites_disabled(dev_priv, pipe);
2141
681e5811 2142 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2143 pch_transcoder = TRANSCODER_A;
2144 else
2145 pch_transcoder = pipe;
2146
b24e7179
JB		 2147 /*
2148 * A pipe without a PLL won't actually be able to drive bits from
2149 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2150 * need the check.
2151 */
50360403 2152 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2153 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2154 assert_dsi_pll_enabled(dev_priv);
2155 else
2156 assert_pll_enabled(dev_priv, pipe);
040484af 2157 else {
6e3c9717 2158 if (crtc->config->has_pch_encoder) {
040484af 2159 /* if driving the PCH, we need FDI enabled */
cc391bbb 2160 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2161 assert_fdi_tx_pll_enabled(dev_priv,
2162 (enum pipe) cpu_transcoder);
040484af
JB		 2163 }
2164 /* FIXME: assert CPU port conditions for SNB+ */
2165 }
b24e7179 2166
702e7a56 2167 reg = PIPECONF(cpu_transcoder);
b24e7179 2168 val = I915_READ(reg);
7ad25d48 2169 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2170 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2171 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2172 return;
7ad25d48 2173 }
00d70b15
CW		 2174
2175 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2176 POSTING_READ(reg);
b24e7179
JB		 2177}
2178
2179/**
309cfea8 2180 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2181 * @crtc: crtc whose pipes is to be disabled
b24e7179 2182 *
575f7ab7
VS		 2183 * Disable the pipe of @crtc, making sure that various hardware
2184 * specific requirements are met, if applicable, e.g. plane
2185 * disabled, panel fitter off, etc.
b24e7179
JB		 2186 *
2187 * Will wait until the pipe has shut down before returning.
2188 */
575f7ab7 2189static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2190{
575f7ab7 2191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2192 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2193 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2194 int reg;
2195 u32 val;
2196
9e2ee2dd
VS		 2197 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2198
b24e7179
JB		 2199 /*
2200 * Make sure planes won't keep trying to pump pixels to us,
2201 * or we might hang the display.
2202 */
2203 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2204 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2205 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2206
702e7a56 2207 reg = PIPECONF(cpu_transcoder);
b24e7179 2208 val = I915_READ(reg);
00d70b15
CW		 2209 if ((val & PIPECONF_ENABLE) == 0)
2210 return;
2211
67adc644
VS		 2212 /*
2213 * Double wide has implications for planes
2214 * so best keep it disabled when not needed.
2215 */
6e3c9717 2216 if (crtc->config->double_wide)
67adc644
VS		 2217 val &= ~PIPECONF_DOUBLE_WIDE;
2218
2219 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2220 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2221 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2222 val &= ~PIPECONF_ENABLE;
2223
2224 I915_WRITE(reg, val);
2225 if ((val & PIPECONF_ENABLE) == 0)
2226 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2227}
2228
693db184
CW		 2229static bool need_vtd_wa(struct drm_device *dev)
2230{
2231#ifdef CONFIG_INTEL_IOMMU
2232 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2233 return true;
2234#endif
2235 return false;
2236}
2237
50470bb0 2238unsigned int
6761dd31 2239intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
fe47ea0c 2240 uint64_t fb_format_modifier, unsigned int plane)
a57ce0b2 2241{
6761dd31
TU		 2242 unsigned int tile_height;
2243 uint32_t pixel_bytes;
a57ce0b2 2244
b5d0e9bf
DL		 2245 switch (fb_format_modifier) {
2246 case DRM_FORMAT_MOD_NONE:
2247 tile_height = 1;
2248 break;
2249 case I915_FORMAT_MOD_X_TILED:
2250 tile_height = IS_GEN2(dev) ? 16 : 8;
2251 break;
2252 case I915_FORMAT_MOD_Y_TILED:
2253 tile_height = 32;
2254 break;
2255 case I915_FORMAT_MOD_Yf_TILED:
fe47ea0c 2256 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
6761dd31 2257 switch (pixel_bytes) {
b5d0e9bf 2258 default:
6761dd31 2259 case 1:
b5d0e9bf
DL		 2260 tile_height = 64;
2261 break;
6761dd31
TU		 2262 case 2:
2263 case 4:
b5d0e9bf
DL		 2264 tile_height = 32;
2265 break;
6761dd31 2266 case 8:
b5d0e9bf
DL		 2267 tile_height = 16;
2268 break;
6761dd31 2269 case 16:
b5d0e9bf
DL		 2270 WARN_ONCE(1,
2271 "128-bit pixels are not supported for display!");
2272 tile_height = 16;
2273 break;
2274 }
2275 break;
2276 default:
2277 MISSING_CASE(fb_format_modifier);
2278 tile_height = 1;
2279 break;
2280 }
091df6cb 2281
6761dd31
TU		 2282 return tile_height;
2283}
2284
2285unsigned int
2286intel_fb_align_height(struct drm_device *dev, unsigned int height,
2287 uint32_t pixel_format, uint64_t fb_format_modifier)
2288{
2289 return ALIGN(height, intel_tile_height(dev, pixel_format,
fe47ea0c 2290 fb_format_modifier, 0));
a57ce0b2
JB		 2291}
2292
f64b98cd
TU		 2293static int
2294intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2295 const struct drm_plane_state *plane_state)
2296{
50470bb0 2297 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2298 unsigned int tile_height, tile_pitch;
50470bb0 2299
f64b98cd
TU		 2300 *view = i915_ggtt_view_normal;
2301
50470bb0
TU		 2302 if (!plane_state)
2303 return 0;
2304
121920fa 2305 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2306 return 0;
2307
9abc4648 2308 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2309
2310 info->height = fb->height;
2311 info->pixel_format = fb->pixel_format;
2312 info->pitch = fb->pitches[0];
89e3e142 2313 info->uv_offset = fb->offsets[1];
50470bb0
TU		 2314 info->fb_modifier = fb->modifier[0];
2315
84fe03f7 2316 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
fe47ea0c 2317 fb->modifier[0], 0);
84fe03f7
TU		 2318 tile_pitch = PAGE_SIZE / tile_height;
2319 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2320 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2321 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2322
89e3e142
TU		 2323 if (info->pixel_format == DRM_FORMAT_NV12) {
2324 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2325 fb->modifier[0], 1);
2326 tile_pitch = PAGE_SIZE / tile_height;
2327 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2328 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2329 tile_height);
2330 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2331 PAGE_SIZE;
2332 }
2333
f64b98cd
TU		 2334 return 0;
2335}
2336
4e9a86b6
VS		 2337static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2338{
2339 if (INTEL_INFO(dev_priv)->gen >= 9)
2340 return 256 * 1024;
985b8bb4
VS		 2341 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2342 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2343 return 128 * 1024;
2344 else if (INTEL_INFO(dev_priv)->gen >= 4)
2345 return 4 * 1024;
2346 else
44c5905e 2347 return 0;
4e9a86b6
VS		 2348}
2349
127bd2ac 2350int
850c4cdc
TU		 2351intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2352 struct drm_framebuffer *fb,
82bc3b2d 2353 const struct drm_plane_state *plane_state,
91af127f
JH		 2354 struct intel_engine_cs *pipelined,
2355 struct drm_i915_gem_request **pipelined_request)
6b95a207 2356{
850c4cdc 2357 struct drm_device *dev = fb->dev;
ce453d81 2358 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2359 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2360 struct i915_ggtt_view view;
6b95a207
KH		 2361 u32 alignment;
2362 int ret;
2363
ebcdd39e
MR		 2364 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2365
7b911adc
TU		 2366 switch (fb->modifier[0]) {
2367 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2368 alignment = intel_linear_alignment(dev_priv);
6b95a207 2369 break;
7b911adc 2370 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2371 if (INTEL_INFO(dev)->gen >= 9)
2372 alignment = 256 * 1024;
2373 else {
2374 /* pin() will align the object as required by fence */
2375 alignment = 0;
2376 }
6b95a207 2377 break;
7b911adc 2378 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2379 case I915_FORMAT_MOD_Yf_TILED:
2380 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2381 "Y tiling bo slipped through, driver bug!\n"))
2382 return -EINVAL;
2383 alignment = 1 * 1024 * 1024;
2384 break;
6b95a207 2385 default:
7b911adc
TU		 2386 MISSING_CASE(fb->modifier[0]);
2387 return -EINVAL;
6b95a207
KH		 2388 }
2389
f64b98cd
TU		 2390 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2391 if (ret)
2392 return ret;
2393
693db184
CW		 2394 /* Note that the w/a also requires 64 PTE of padding following the
2395 * bo. We currently fill all unused PTE with the shadow page and so
2396 * we should always have valid PTE following the scanout preventing
2397 * the VT-d warning.
2398 */
2399 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2400 alignment = 256 * 1024;
2401
d6dd6843
PZ		 2402 /*
2403 * Global gtt pte registers are special registers which actually forward
2404 * writes to a chunk of system memory. Which means that there is no risk
2405 * that the register values disappear as soon as we call
2406 * intel_runtime_pm_put(), so it is correct to wrap only the
2407 * pin/unpin/fence and not more.
2408 */
2409 intel_runtime_pm_get(dev_priv);
2410
ce453d81 2411 dev_priv->mm.interruptible = false;
e6617330 2412 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2413 pipelined_request, &view);
48b956c5 2414 if (ret)
ce453d81 2415 goto err_interruptible;
6b95a207
KH		 2416
2417 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2418 * fence, whereas 965+ only requires a fence if using
2419 * framebuffer compression. For simplicity, we always install
2420 * a fence as the cost is not that onerous.
2421 */
06d98131 2422 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2423 if (ret == -EDEADLK) {
2424 /*
2425 * -EDEADLK means there are no free fences
2426 * no pending flips.
2427 *
2428 * This is propagated to atomic, but it uses
2429 * -EDEADLK to force a locking recovery, so
2430 * change the returned error to -EBUSY.
2431 */
2432 ret = -EBUSY;
2433 goto err_unpin;
2434 } else if (ret)
9a5a53b3 2435 goto err_unpin;
1690e1eb 2436
9a5a53b3 2437 i915_gem_object_pin_fence(obj);
6b95a207 2438
ce453d81 2439 dev_priv->mm.interruptible = true;
d6dd6843 2440 intel_runtime_pm_put(dev_priv);
6b95a207 2441 return 0;
48b956c5
CW		 2442
2443err_unpin:
f64b98cd 2444 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2445err_interruptible:
2446 dev_priv->mm.interruptible = true;
d6dd6843 2447 intel_runtime_pm_put(dev_priv);
48b956c5 2448 return ret;
6b95a207
KH		 2449}
2450
82bc3b2d
TU		 2451static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2452 const struct drm_plane_state *plane_state)
1690e1eb 2453{
82bc3b2d 2454 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2455 struct i915_ggtt_view view;
2456 int ret;
82bc3b2d 2457
ebcdd39e
MR		 2458 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2459
f64b98cd
TU		 2460 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2461 WARN_ONCE(ret, "Couldn't get view from plane state!");
2462
1690e1eb 2463 i915_gem_object_unpin_fence(obj);
f64b98cd 2464 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2465}
2466
c2c75131
DV		 2467/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2468 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2469unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2470 int *x, int *y,
bc752862
CW		 2471 unsigned int tiling_mode,
2472 unsigned int cpp,
2473 unsigned int pitch)
c2c75131 2474{
bc752862
CW		 2475 if (tiling_mode != I915_TILING_NONE) {
2476 unsigned int tile_rows, tiles;
c2c75131 2477
bc752862
CW		 2478 tile_rows = *y / 8;
2479 *y %= 8;
c2c75131 2480
bc752862
CW		 2481 tiles = *x / (512/cpp);
2482 *x %= 512/cpp;
2483
2484 return tile_rows * pitch * 8 + tiles * 4096;
2485 } else {
4e9a86b6 2486 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2487 unsigned int offset;
2488
2489 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2490 *y = (offset & alignment) / pitch;
2491 *x = ((offset & alignment) - *y * pitch) / cpp;
2492 return offset & ~alignment;
bc752862 2493 }
c2c75131
DV		 2494}
2495
b35d63fa 2496static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2497{
2498 switch (format) {
2499 case DISPPLANE_8BPP:
2500 return DRM_FORMAT_C8;
2501 case DISPPLANE_BGRX555:
2502 return DRM_FORMAT_XRGB1555;
2503 case DISPPLANE_BGRX565:
2504 return DRM_FORMAT_RGB565;
2505 default:
2506 case DISPPLANE_BGRX888:
2507 return DRM_FORMAT_XRGB8888;
2508 case DISPPLANE_RGBX888:
2509 return DRM_FORMAT_XBGR8888;
2510 case DISPPLANE_BGRX101010:
2511 return DRM_FORMAT_XRGB2101010;
2512 case DISPPLANE_RGBX101010:
2513 return DRM_FORMAT_XBGR2101010;
2514 }
2515}
2516
bc8d7dff
DL		 2517static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2518{
2519 switch (format) {
2520 case PLANE_CTL_FORMAT_RGB_565:
2521 return DRM_FORMAT_RGB565;
2522 default:
2523 case PLANE_CTL_FORMAT_XRGB_8888:
2524 if (rgb_order) {
2525 if (alpha)
2526 return DRM_FORMAT_ABGR8888;
2527 else
2528 return DRM_FORMAT_XBGR8888;
2529 } else {
2530 if (alpha)
2531 return DRM_FORMAT_ARGB8888;
2532 else
2533 return DRM_FORMAT_XRGB8888;
2534 }
2535 case PLANE_CTL_FORMAT_XRGB_2101010:
2536 if (rgb_order)
2537 return DRM_FORMAT_XBGR2101010;
2538 else
2539 return DRM_FORMAT_XRGB2101010;
2540 }
2541}
2542
5724dbd1 2543static bool
f6936e29
DV		 2544intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2545 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2546{
2547 struct drm_device *dev = crtc->base.dev;
2548 struct drm_i915_gem_object *obj = NULL;
2549 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2550 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2551 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2552 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2553 PAGE_SIZE);
2554
2555 size_aligned -= base_aligned;
46f297fb 2556
ff2652ea
CW		 2557 if (plane_config->size == 0)
2558 return false;
2559
f37b5c2b
DV		 2560 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2561 base_aligned,
2562 base_aligned,
2563 size_aligned);
46f297fb 2564 if (!obj)
484b41dd 2565 return false;
46f297fb 2566
49af449b
DL		 2567 obj->tiling_mode = plane_config->tiling;
2568 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2569 obj->stride = fb->pitches[0];
46f297fb 2570
6bf129df
DL		 2571 mode_cmd.pixel_format = fb->pixel_format;
2572 mode_cmd.width = fb->width;
2573 mode_cmd.height = fb->height;
2574 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2575 mode_cmd.modifier[0] = fb->modifier[0];
2576 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2577
2578 mutex_lock(&dev->struct_mutex);
6bf129df 2579 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2580 &mode_cmd, obj)) {
46f297fb
JB		 2581 DRM_DEBUG_KMS("intel fb init failed\n");
2582 goto out_unref_obj;
2583 }
46f297fb 2584 mutex_unlock(&dev->struct_mutex);
484b41dd 2585
f6936e29 2586 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2587 return true;
46f297fb
JB		 2588
2589out_unref_obj:
2590 drm_gem_object_unreference(&obj->base);
2591 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2592 return false;
2593}
2594
afd65eb4
MR		 2595/* Update plane->state->fb to match plane->fb after driver-internal updates */
2596static void
2597update_state_fb(struct drm_plane *plane)
2598{
2599 if (plane->fb == plane->state->fb)
2600 return;
2601
2602 if (plane->state->fb)
2603 drm_framebuffer_unreference(plane->state->fb);
2604 plane->state->fb = plane->fb;
2605 if (plane->state->fb)
2606 drm_framebuffer_reference(plane->state->fb);
2607}
2608
5724dbd1 2609static void
f6936e29
DV		 2610intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2611 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2612{
2613 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2614 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2615 struct drm_crtc *c;
2616 struct intel_crtc *i;
2ff8fde1 2617 struct drm_i915_gem_object *obj;
88595ac9 2618 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2619 struct drm_plane_state *plane_state = primary->state;
88595ac9 2620 struct drm_framebuffer *fb;
484b41dd 2621
2d14030b 2622 if (!plane_config->fb)
484b41dd
JB		 2623 return;
2624
f6936e29 2625 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2626 fb = &plane_config->fb->base;
2627 goto valid_fb;
f55548b5 2628 }
484b41dd 2629
2d14030b 2630 kfree(plane_config->fb);
484b41dd
JB		 2631
2632 /*
2633 * Failed to alloc the obj, check to see if we should share
2634 * an fb with another CRTC instead
2635 */
70e1e0ec 2636 for_each_crtc(dev, c) {
484b41dd
JB		 2637 i = to_intel_crtc(c);
2638
2639 if (c == &intel_crtc->base)
2640 continue;
2641
2ff8fde1
MR		 2642 if (!i->active)
2643 continue;
2644
88595ac9
DV		 2645 fb = c->primary->fb;
2646 if (!fb)
484b41dd
JB		 2647 continue;
2648
88595ac9 2649 obj = intel_fb_obj(fb);
2ff8fde1 2650 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2651 drm_framebuffer_reference(fb);
2652 goto valid_fb;
484b41dd
JB		 2653 }
2654 }
88595ac9
DV		 2655
2656 return;
2657
2658valid_fb:
be5651f2
ML		 2659 plane_state->src_x = plane_state->src_y = 0;
2660 plane_state->src_w = fb->width << 16;
2661 plane_state->src_h = fb->height << 16;
2662
2663 plane_state->crtc_x = plane_state->src_y = 0;
2664 plane_state->crtc_w = fb->width;
2665 plane_state->crtc_h = fb->height;
2666
88595ac9
DV		 2667 obj = intel_fb_obj(fb);
2668 if (obj->tiling_mode != I915_TILING_NONE)
2669 dev_priv->preserve_bios_swizzle = true;
2670
be5651f2
ML		 2671 drm_framebuffer_reference(fb);
2672 primary->fb = primary->state->fb = fb;
36750f28 2673 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2674 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2675 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2676}
2677
29b9bde6
DV		 2678static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2679 struct drm_framebuffer *fb,
2680 int x, int y)
81255565
JB		 2681{
2682 struct drm_device *dev = crtc->dev;
2683 struct drm_i915_private *dev_priv = dev->dev_private;
2684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2685 struct drm_plane *primary = crtc->primary;
2686 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2687 struct drm_i915_gem_object *obj;
81255565 2688 int plane = intel_crtc->plane;
e506a0c6 2689 unsigned long linear_offset;
81255565 2690 u32 dspcntr;
f45651ba 2691 u32 reg = DSPCNTR(plane);
48404c1e 2692 int pixel_size;
f45651ba 2693
b70709a6 2694 if (!visible || !fb) {
fdd508a6
VS		 2695 I915_WRITE(reg, 0);
2696 if (INTEL_INFO(dev)->gen >= 4)
2697 I915_WRITE(DSPSURF(plane), 0);
2698 else
2699 I915_WRITE(DSPADDR(plane), 0);
2700 POSTING_READ(reg);
2701 return;
2702 }
2703
c9ba6fad
VS		 2704 obj = intel_fb_obj(fb);
2705 if (WARN_ON(obj == NULL))
2706 return;
2707
2708 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2709
f45651ba
VS		 2710 dspcntr = DISPPLANE_GAMMA_ENABLE;
2711
fdd508a6 2712 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2713
2714 if (INTEL_INFO(dev)->gen < 4) {
2715 if (intel_crtc->pipe == PIPE_B)
2716 dspcntr |= DISPPLANE_SEL_PIPE_B;
2717
2718 /* pipesrc and dspsize control the size that is scaled from,
2719 * which should always be the user's requested size.
2720 */
2721 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2722 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2723 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2724 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2725 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2726 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2727 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2728 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2729 I915_WRITE(PRIMPOS(plane), 0);
2730 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2731 }
81255565 2732
57779d06
VS		 2733 switch (fb->pixel_format) {
2734 case DRM_FORMAT_C8:
81255565
JB		 2735 dspcntr |= DISPPLANE_8BPP;
2736 break;
57779d06 2737 case DRM_FORMAT_XRGB1555:
57779d06 2738 dspcntr |= DISPPLANE_BGRX555;
81255565 2739 break;
57779d06
VS		 2740 case DRM_FORMAT_RGB565:
2741 dspcntr |= DISPPLANE_BGRX565;
2742 break;
2743 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2744 dspcntr |= DISPPLANE_BGRX888;
2745 break;
2746 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2747 dspcntr |= DISPPLANE_RGBX888;
2748 break;
2749 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2750 dspcntr |= DISPPLANE_BGRX101010;
2751 break;
2752 case DRM_FORMAT_XBGR2101010:
57779d06 2753 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2754 break;
2755 default:
baba133a 2756 BUG();
81255565 2757 }
57779d06 2758
f45651ba
VS		 2759 if (INTEL_INFO(dev)->gen >= 4 &&
2760 obj->tiling_mode != I915_TILING_NONE)
2761 dspcntr |= DISPPLANE_TILED;
81255565 2762
de1aa629
VS		 2763 if (IS_G4X(dev))
2764 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2765
b9897127 2766 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2767
c2c75131
DV		 2768 if (INTEL_INFO(dev)->gen >= 4) {
2769 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2770 intel_gen4_compute_page_offset(dev_priv,
2771 &x, &y, obj->tiling_mode,
b9897127 2772 pixel_size,
bc752862 2773 fb->pitches[0]);
c2c75131
DV		 2774 linear_offset -= intel_crtc->dspaddr_offset;
2775 } else {
e506a0c6 2776 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2777 }
e506a0c6 2778
8e7d688b 2779 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2780 dspcntr |= DISPPLANE_ROTATE_180;
2781
6e3c9717
ACO		 2782 x += (intel_crtc->config->pipe_src_w - 1);
2783 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2784
2785 /* Finding the last pixel of the last line of the display
2786 data and adding to linear_offset*/
2787 linear_offset +=
6e3c9717
ACO		 2788 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2789 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2790 }
2791
2db3366b
PZ		 2792 intel_crtc->adjusted_x = x;
2793 intel_crtc->adjusted_y = y;
2794
48404c1e
SJ		 2795 I915_WRITE(reg, dspcntr);
2796
01f2c773 2797 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2798 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2799 I915_WRITE(DSPSURF(plane),
2800 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2801 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2802 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2803 } else
f343c5f6 2804 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2805 POSTING_READ(reg);
17638cd6
JB		 2806}
2807
29b9bde6
DV		 2808static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2809 struct drm_framebuffer *fb,
2810 int x, int y)
17638cd6
JB		 2811{
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2815 struct drm_plane *primary = crtc->primary;
2816 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2817 struct drm_i915_gem_object *obj;
17638cd6 2818 int plane = intel_crtc->plane;
e506a0c6 2819 unsigned long linear_offset;
17638cd6 2820 u32 dspcntr;
f45651ba 2821 u32 reg = DSPCNTR(plane);
48404c1e 2822 int pixel_size;
f45651ba 2823
b70709a6 2824 if (!visible || !fb) {
fdd508a6
VS		 2825 I915_WRITE(reg, 0);
2826 I915_WRITE(DSPSURF(plane), 0);
2827 POSTING_READ(reg);
2828 return;
2829 }
2830
c9ba6fad
VS		 2831 obj = intel_fb_obj(fb);
2832 if (WARN_ON(obj == NULL))
2833 return;
2834
2835 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2836
f45651ba
VS		 2837 dspcntr = DISPPLANE_GAMMA_ENABLE;
2838
fdd508a6 2839 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2840
2841 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2842 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2843
57779d06
VS		 2844 switch (fb->pixel_format) {
2845 case DRM_FORMAT_C8:
17638cd6
JB		 2846 dspcntr |= DISPPLANE_8BPP;
2847 break;
57779d06
VS		 2848 case DRM_FORMAT_RGB565:
2849 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2850 break;
57779d06 2851 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2852 dspcntr |= DISPPLANE_BGRX888;
2853 break;
2854 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2855 dspcntr |= DISPPLANE_RGBX888;
2856 break;
2857 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2858 dspcntr |= DISPPLANE_BGRX101010;
2859 break;
2860 case DRM_FORMAT_XBGR2101010:
57779d06 2861 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2862 break;
2863 default:
baba133a 2864 BUG();
17638cd6
JB		 2865 }
2866
2867 if (obj->tiling_mode != I915_TILING_NONE)
2868 dspcntr |= DISPPLANE_TILED;
17638cd6 2869
f45651ba 2870 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2871 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2872
b9897127 2873 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2874 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2875 intel_gen4_compute_page_offset(dev_priv,
2876 &x, &y, obj->tiling_mode,
b9897127 2877 pixel_size,
bc752862 2878 fb->pitches[0]);
c2c75131 2879 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2880 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2881 dspcntr |= DISPPLANE_ROTATE_180;
2882
2883 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2884 x += (intel_crtc->config->pipe_src_w - 1);
2885 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2886
2887 /* Finding the last pixel of the last line of the display
2888 data and adding to linear_offset*/
2889 linear_offset +=
6e3c9717
ACO		 2890 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2891 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2892 }
2893 }
2894
2db3366b
PZ		 2895 intel_crtc->adjusted_x = x;
2896 intel_crtc->adjusted_y = y;
2897
48404c1e 2898 I915_WRITE(reg, dspcntr);
17638cd6 2899
01f2c773 2900 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2901 I915_WRITE(DSPSURF(plane),
2902 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2903 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2904 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2905 } else {
2906 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2907 I915_WRITE(DSPLINOFF(plane), linear_offset);
2908 }
17638cd6 2909 POSTING_READ(reg);
17638cd6
JB		 2910}
2911
b321803d
DL		 2912u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2913 uint32_t pixel_format)
2914{
2915 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2916
2917 /*
2918 * The stride is either expressed as a multiple of 64 bytes
2919 * chunks for linear buffers or in number of tiles for tiled
2920 * buffers.
2921 */
2922 switch (fb_modifier) {
2923 case DRM_FORMAT_MOD_NONE:
2924 return 64;
2925 case I915_FORMAT_MOD_X_TILED:
2926 if (INTEL_INFO(dev)->gen == 2)
2927 return 128;
2928 return 512;
2929 case I915_FORMAT_MOD_Y_TILED:
2930 /* No need to check for old gens and Y tiling since this is
2931 * about the display engine and those will be blocked before
2932 * we get here.
2933 */
2934 return 128;
2935 case I915_FORMAT_MOD_Yf_TILED:
2936 if (bits_per_pixel == 8)
2937 return 64;
2938 else
2939 return 128;
2940 default:
2941 MISSING_CASE(fb_modifier);
2942 return 64;
2943 }
2944}
2945
121920fa 2946unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
dedf278c
TU		 2947 struct drm_i915_gem_object *obj,
2948 unsigned int plane)
121920fa 2949{
9abc4648 2950 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
dedf278c
TU		 2951 struct i915_vma *vma;
2952 unsigned char *offset;
121920fa
TU		 2953
2954 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2955 view = &i915_ggtt_view_rotated;
121920fa 2956
dedf278c
TU		 2957 vma = i915_gem_obj_to_ggtt_view(obj, view);
2958 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2959 view->type))
2960 return -1;
2961
2962 offset = (unsigned char *)vma->node.start;
2963
2964 if (plane == 1) {
2965 offset += vma->ggtt_view.rotation_info.uv_start_page *
2966 PAGE_SIZE;
2967 }
2968
2969 return (unsigned long)offset;
121920fa
TU		 2970}
2971
e435d6e5
ML		 2972static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2973{
2974 struct drm_device *dev = intel_crtc->base.dev;
2975 struct drm_i915_private *dev_priv = dev->dev_private;
2976
2977 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2978 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2979 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2980}
2981
a1b2278e
CK		 2982/*
2983 * This function detaches (aka. unbinds) unused scalers in hardware
2984 */
0583236e 2985static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2986{
a1b2278e
CK		 2987 struct intel_crtc_scaler_state *scaler_state;
2988 int i;
2989
a1b2278e
CK		 2990 scaler_state = &intel_crtc->config->scaler_state;
2991
2992 /* loop through and disable scalers that aren't in use */
2993 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2994 if (!scaler_state->scalers[i].in_use)
2995 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2996 }
2997}
2998
6156a456 2999u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 3000{
6156a456 3001 switch (pixel_format) {
d161cf7a 3002 case DRM_FORMAT_C8:
c34ce3d1 3003 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 3004 case DRM_FORMAT_RGB565:
c34ce3d1 3005 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 3006 case DRM_FORMAT_XBGR8888:
c34ce3d1 3007 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 3008 case DRM_FORMAT_XRGB8888:
c34ce3d1 3009 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 3010 /*
3011 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3012 * to be already pre-multiplied. We need to add a knob (or a different
3013 * DRM_FORMAT) for user-space to configure that.
3014 */
f75fb42a 3015 case DRM_FORMAT_ABGR8888:
c34ce3d1 3016 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 3017 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 3018 case DRM_FORMAT_ARGB8888:
c34ce3d1 3019 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 3020 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 3021 case DRM_FORMAT_XRGB2101010:
c34ce3d1 3022 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 3023 case DRM_FORMAT_XBGR2101010:
c34ce3d1 3024 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 3025 case DRM_FORMAT_YUYV:
c34ce3d1 3026 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 3027 case DRM_FORMAT_YVYU:
c34ce3d1 3028 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 3029 case DRM_FORMAT_UYVY:
c34ce3d1 3030 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 3031 case DRM_FORMAT_VYUY:
c34ce3d1 3032 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 3033 default:
4249eeef 3034 MISSING_CASE(pixel_format);
70d21f0e 3035 }
8cfcba41 3036
c34ce3d1 3037 return 0;
6156a456 3038}
70d21f0e 3039
6156a456
CK		 3040u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3041{
6156a456 3042 switch (fb_modifier) {
30af77c4 3043 case DRM_FORMAT_MOD_NONE:
70d21f0e 3044 break;
30af77c4 3045 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3046 return PLANE_CTL_TILED_X;
b321803d 3047 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3048 return PLANE_CTL_TILED_Y;
b321803d 3049 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3050 return PLANE_CTL_TILED_YF;
70d21f0e 3051 default:
6156a456 3052 MISSING_CASE(fb_modifier);
70d21f0e 3053 }
8cfcba41 3054
c34ce3d1 3055 return 0;
6156a456 3056}
70d21f0e 3057
6156a456
CK		 3058u32 skl_plane_ctl_rotation(unsigned int rotation)
3059{
3b7a5119 3060 switch (rotation) {
6156a456
CK		 3061 case BIT(DRM_ROTATE_0):
3062 break;
1e8df167
SJ		 3063 /*
3064 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3065 * while i915 HW rotation is clockwise, thats why this swapping.
3066 */
3b7a5119 3067 case BIT(DRM_ROTATE_90):
1e8df167 3068 return PLANE_CTL_ROTATE_270;
3b7a5119 3069 case BIT(DRM_ROTATE_180):
c34ce3d1 3070 return PLANE_CTL_ROTATE_180;
3b7a5119 3071 case BIT(DRM_ROTATE_270):
1e8df167 3072 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3073 default:
3074 MISSING_CASE(rotation);
3075 }
3076
c34ce3d1 3077 return 0;
6156a456
CK		 3078}
3079
3080static void skylake_update_primary_plane(struct drm_crtc *crtc,
3081 struct drm_framebuffer *fb,
3082 int x, int y)
3083{
3084 struct drm_device *dev = crtc->dev;
3085 struct drm_i915_private *dev_priv = dev->dev_private;
3086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3087 struct drm_plane *plane = crtc->primary;
3088 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3089 struct drm_i915_gem_object *obj;
3090 int pipe = intel_crtc->pipe;
3091 u32 plane_ctl, stride_div, stride;
3092 u32 tile_height, plane_offset, plane_size;
3093 unsigned int rotation;
3094 int x_offset, y_offset;
3095 unsigned long surf_addr;
6156a456
CK		 3096 struct intel_crtc_state *crtc_state = intel_crtc->config;
3097 struct intel_plane_state *plane_state;
3098 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3099 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3100 int scaler_id = -1;
3101
6156a456
CK		 3102 plane_state = to_intel_plane_state(plane->state);
3103
b70709a6 3104 if (!visible || !fb) {
6156a456
CK		 3105 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3106 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3107 POSTING_READ(PLANE_CTL(pipe, 0));
3108 return;
3b7a5119 3109 }
70d21f0e 3110
6156a456
CK		 3111 plane_ctl = PLANE_CTL_ENABLE |
3112 PLANE_CTL_PIPE_GAMMA_ENABLE |
3113 PLANE_CTL_PIPE_CSC_ENABLE;
3114
3115 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3116 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3117 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3118
3119 rotation = plane->state->rotation;
3120 plane_ctl |= skl_plane_ctl_rotation(rotation);
3121
b321803d
DL		 3122 obj = intel_fb_obj(fb);
3123 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3124 fb->pixel_format);
dedf278c 3125 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3b7a5119 3126
6156a456
CK		 3127 /*
3128 * FIXME: intel_plane_state->src, dst aren't set when transitional
3129 * update_plane helpers are called from legacy paths.
3130 * Once full atomic crtc is available, below check can be avoided.
3131 */
3132 if (drm_rect_width(&plane_state->src)) {
3133 scaler_id = plane_state->scaler_id;
3134 src_x = plane_state->src.x1 >> 16;
3135 src_y = plane_state->src.y1 >> 16;
3136 src_w = drm_rect_width(&plane_state->src) >> 16;
3137 src_h = drm_rect_height(&plane_state->src) >> 16;
3138 dst_x = plane_state->dst.x1;
3139 dst_y = plane_state->dst.y1;
3140 dst_w = drm_rect_width(&plane_state->dst);
3141 dst_h = drm_rect_height(&plane_state->dst);
3142
3143 WARN_ON(x != src_x || y != src_y);
3144 } else {
3145 src_w = intel_crtc->config->pipe_src_w;
3146 src_h = intel_crtc->config->pipe_src_h;
3147 }
3148
3b7a5119
SJ		 3149 if (intel_rotation_90_or_270(rotation)) {
3150 /* stride = Surface height in tiles */
2614f17d 3151 tile_height = intel_tile_height(dev, fb->pixel_format,
fe47ea0c 3152 fb->modifier[0], 0);
3b7a5119 3153 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3154 x_offset = stride * tile_height - y - src_h;
3b7a5119 3155 y_offset = x;
6156a456 3156 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3157 } else {
3158 stride = fb->pitches[0] / stride_div;
3159 x_offset = x;
3160 y_offset = y;
6156a456 3161 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3162 }
3163 plane_offset = y_offset << 16 | x_offset;
b321803d 3164
2db3366b
PZ		 3165 intel_crtc->adjusted_x = x_offset;
3166 intel_crtc->adjusted_y = y_offset;
3167
70d21f0e 3168 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3169 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3170 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3171 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3172
3173 if (scaler_id >= 0) {
3174 uint32_t ps_ctrl = 0;
3175
3176 WARN_ON(!dst_w || !dst_h);
3177 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3178 crtc_state->scaler_state.scalers[scaler_id].mode;
3179 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3180 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3181 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3182 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3183 I915_WRITE(PLANE_POS(pipe, 0), 0);
3184 } else {
3185 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3186 }
3187
121920fa 3188 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3189
3190 POSTING_READ(PLANE_SURF(pipe, 0));
3191}
3192
17638cd6
JB		 3193/* Assume fb object is pinned & idle & fenced and just update base pointers */
3194static int
3195intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3196 int x, int y, enum mode_set_atomic state)
3197{
3198 struct drm_device *dev = crtc->dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3200
ff2a3117 3201 if (dev_priv->fbc.disable_fbc)
7733b49b 3202 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3203
29b9bde6
DV		 3204 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3205
3206 return 0;
81255565
JB		 3207}
3208
7514747d 3209static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3210{
96a02917
VS		 3211 struct drm_crtc *crtc;
3212
70e1e0ec 3213 for_each_crtc(dev, crtc) {
96a02917
VS		 3214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3215 enum plane plane = intel_crtc->plane;
3216
3217 intel_prepare_page_flip(dev, plane);
3218 intel_finish_page_flip_plane(dev, plane);
3219 }
7514747d
VS		 3220}
3221
3222static void intel_update_primary_planes(struct drm_device *dev)
3223{
7514747d 3224 struct drm_crtc *crtc;
96a02917 3225
70e1e0ec 3226 for_each_crtc(dev, crtc) {
11c22da6
ML		 3227 struct intel_plane *plane = to_intel_plane(crtc->primary);
3228 struct intel_plane_state *plane_state;
96a02917 3229
11c22da6
ML		 3230 drm_modeset_lock_crtc(crtc, &plane->base);
3231
3232 plane_state = to_intel_plane_state(plane->base.state);
3233
3234 if (plane_state->base.fb)
3235 plane->commit_plane(&plane->base, plane_state);
3236
3237 drm_modeset_unlock_crtc(crtc);
96a02917
VS		 3238 }
3239}
3240
7514747d
VS		 3241void intel_prepare_reset(struct drm_device *dev)
3242{
3243 /* no reset support for gen2 */
3244 if (IS_GEN2(dev))
3245 return;
3246
3247 /* reset doesn't touch the display */
3248 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3249 return;
3250
3251 drm_modeset_lock_all(dev);
f98ce92f
VS		 3252 /*
3253 * Disabling the crtcs gracefully seems nicer. Also the
3254 * g33 docs say we should at least disable all the planes.
3255 */
6b72d486 3256 intel_display_suspend(dev);
7514747d
VS		 3257}
3258
3259void intel_finish_reset(struct drm_device *dev)
3260{
3261 struct drm_i915_private *dev_priv = to_i915(dev);
3262
3263 /*
3264 * Flips in the rings will be nuked by the reset,
3265 * so complete all pending flips so that user space
3266 * will get its events and not get stuck.
3267 */
3268 intel_complete_page_flips(dev);
3269
3270 /* no reset support for gen2 */
3271 if (IS_GEN2(dev))
3272 return;
3273
3274 /* reset doesn't touch the display */
3275 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3276 /*
3277 * Flips in the rings have been nuked by the reset,
3278 * so update the base address of all primary
3279 * planes to the the last fb to make sure we're
3280 * showing the correct fb after a reset.
11c22da6
ML		 3281 *
3282 * FIXME: Atomic will make this obsolete since we won't schedule
3283 * CS-based flips (which might get lost in gpu resets) any more.
7514747d
VS		 3284 */
3285 intel_update_primary_planes(dev);
3286 return;
3287 }
3288
3289 /*
3290 * The display has been reset as well,
3291 * so need a full re-initialization.
3292 */
3293 intel_runtime_pm_disable_interrupts(dev_priv);
3294 intel_runtime_pm_enable_interrupts(dev_priv);
3295
3296 intel_modeset_init_hw(dev);
3297
3298 spin_lock_irq(&dev_priv->irq_lock);
3299 if (dev_priv->display.hpd_irq_setup)
3300 dev_priv->display.hpd_irq_setup(dev);
3301 spin_unlock_irq(&dev_priv->irq_lock);
3302
043e9bda 3303 intel_display_resume(dev);
7514747d
VS		 3304
3305 intel_hpd_init(dev_priv);
3306
3307 drm_modeset_unlock_all(dev);
3308}
3309
2e2f351d 3310static void
14667a4b
CW		 3311intel_finish_fb(struct drm_framebuffer *old_fb)
3312{
2ff8fde1 3313 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3314 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3315 bool was_interruptible = dev_priv->mm.interruptible;
3316 int ret;
3317
14667a4b
CW		 3318 /* Big Hammer, we also need to ensure that any pending
3319 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3320 * current scanout is retired before unpinning the old
2e2f351d
CW		 3321 * framebuffer. Note that we rely on userspace rendering
3322 * into the buffer attached to the pipe they are waiting
3323 * on. If not, userspace generates a GPU hang with IPEHR
3324 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3325 *
3326 * This should only fail upon a hung GPU, in which case we
3327 * can safely continue.
3328 */
3329 dev_priv->mm.interruptible = false;
2e2f351d 3330 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3331 dev_priv->mm.interruptible = was_interruptible;
3332
2e2f351d 3333 WARN_ON(ret);
14667a4b
CW		 3334}
3335
7d5e3799
CW		 3336static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3337{
3338 struct drm_device *dev = crtc->dev;
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3341 bool pending;
3342
3343 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3344 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3345 return false;
3346
5e2d7afc 3347 spin_lock_irq(&dev->event_lock);
7d5e3799 3348 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3349 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3350
3351 return pending;
3352}
3353
bfd16b2a
ML		 3354static void intel_update_pipe_config(struct intel_crtc *crtc,
3355 struct intel_crtc_state *old_crtc_state)
e30e8f75
GP		 3356{
3357 struct drm_device *dev = crtc->base.dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
bfd16b2a
ML		 3359 struct intel_crtc_state *pipe_config =
3360 to_intel_crtc_state(crtc->base.state);
e30e8f75 3361
bfd16b2a
ML		 3362 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3363 crtc->base.mode = crtc->base.state->mode;
3364
3365 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3366 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3367 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
e30e8f75 3368
44522d85
ML		 3369 if (HAS_DDI(dev))
3370 intel_set_pipe_csc(&crtc->base);
3371
e30e8f75
GP		 3372 /*
3373 * Update pipe size and adjust fitter if needed: the reason for this is
3374 * that in compute_mode_changes we check the native mode (not the pfit
3375 * mode) to see if we can flip rather than do a full mode set. In the
3376 * fastboot case, we'll flip, but if we don't update the pipesrc and
3377 * pfit state, we'll end up with a big fb scanned out into the wrong
3378 * sized surface.
e30e8f75
GP		 3379 */
3380
e30e8f75 3381 I915_WRITE(PIPESRC(crtc->pipe),
bfd16b2a
ML		 3382 ((pipe_config->pipe_src_w - 1) << 16) |
3383 (pipe_config->pipe_src_h - 1));
3384
3385 /* on skylake this is done by detaching scalers */
3386 if (INTEL_INFO(dev)->gen >= 9) {
3387 skl_detach_scalers(crtc);
3388
3389 if (pipe_config->pch_pfit.enabled)
3390 skylake_pfit_enable(crtc);
3391 } else if (HAS_PCH_SPLIT(dev)) {
3392 if (pipe_config->pch_pfit.enabled)
3393 ironlake_pfit_enable(crtc);
3394 else if (old_crtc_state->pch_pfit.enabled)
3395 ironlake_pfit_disable(crtc, true);
e30e8f75 3396 }
e30e8f75
GP		 3397}
3398
5e84e1a4
ZW		 3399static void intel_fdi_normal_train(struct drm_crtc *crtc)
3400{
3401 struct drm_device *dev = crtc->dev;
3402 struct drm_i915_private *dev_priv = dev->dev_private;
3403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3404 int pipe = intel_crtc->pipe;
3405 u32 reg, temp;
3406
3407 /* enable normal train */
3408 reg = FDI_TX_CTL(pipe);
3409 temp = I915_READ(reg);
61e499bf 3410 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3411 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3412 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3413 } else {
3414 temp &= ~FDI_LINK_TRAIN_NONE;
3415 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3416 }
5e84e1a4
ZW		 3417 I915_WRITE(reg, temp);
3418
3419 reg = FDI_RX_CTL(pipe);
3420 temp = I915_READ(reg);
3421 if (HAS_PCH_CPT(dev)) {
3422 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3423 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3424 } else {
3425 temp &= ~FDI_LINK_TRAIN_NONE;
3426 temp |= FDI_LINK_TRAIN_NONE;
3427 }
3428 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3429
3430 /* wait one idle pattern time */
3431 POSTING_READ(reg);
3432 udelay(1000);
357555c0
JB		 3433
3434 /* IVB wants error correction enabled */
3435 if (IS_IVYBRIDGE(dev))
3436 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3437 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3438}
3439
8db9d77b
ZW		 3440/* The FDI link training functions for ILK/Ibexpeak. */
3441static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3442{
3443 struct drm_device *dev = crtc->dev;
3444 struct drm_i915_private *dev_priv = dev->dev_private;
3445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3446 int pipe = intel_crtc->pipe;
5eddb70b 3447 u32 reg, temp, tries;
8db9d77b 3448
1c8562f6 3449 /* FDI needs bits from pipe first */
0fc932b8 3450 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3451
e1a44743
AJ		 3452 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3453 for train result */
5eddb70b
CW		 3454 reg = FDI_RX_IMR(pipe);
3455 temp = I915_READ(reg);
e1a44743
AJ		 3456 temp &= ~FDI_RX_SYMBOL_LOCK;
3457 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3458 I915_WRITE(reg, temp);
3459 I915_READ(reg);
e1a44743
AJ		 3460 udelay(150);
3461
8db9d77b 3462 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3463 reg = FDI_TX_CTL(pipe);
3464 temp = I915_READ(reg);
627eb5a3 3465 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3466 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3467 temp &= ~FDI_LINK_TRAIN_NONE;
3468 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3469 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3470
5eddb70b
CW		 3471 reg = FDI_RX_CTL(pipe);
3472 temp = I915_READ(reg);
8db9d77b
ZW		 3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3475 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3476
3477 POSTING_READ(reg);
8db9d77b
ZW		 3478 udelay(150);
3479
5b2adf89 3480 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3481 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3482 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3483 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3484
5eddb70b 3485 reg = FDI_RX_IIR(pipe);
e1a44743 3486 for (tries = 0; tries < 5; tries++) {
5eddb70b 3487 temp = I915_READ(reg);
8db9d77b
ZW		 3488 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3489
3490 if ((temp & FDI_RX_BIT_LOCK)) {
3491 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3492 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3493 break;
3494 }
8db9d77b 3495 }
e1a44743 3496 if (tries == 5)
5eddb70b 3497 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3498
3499 /* Train 2 */
5eddb70b
CW		 3500 reg = FDI_TX_CTL(pipe);
3501 temp = I915_READ(reg);
8db9d77b
ZW		 3502 temp &= ~FDI_LINK_TRAIN_NONE;
3503 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3504 I915_WRITE(reg, temp);
8db9d77b 3505
5eddb70b
CW		 3506 reg = FDI_RX_CTL(pipe);
3507 temp = I915_READ(reg);
8db9d77b
ZW		 3508 temp &= ~FDI_LINK_TRAIN_NONE;
3509 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3510 I915_WRITE(reg, temp);
8db9d77b 3511
5eddb70b
CW		 3512 POSTING_READ(reg);
3513 udelay(150);
8db9d77b 3514
5eddb70b 3515 reg = FDI_RX_IIR(pipe);
e1a44743 3516 for (tries = 0; tries < 5; tries++) {
5eddb70b 3517 temp = I915_READ(reg);
8db9d77b
ZW		 3518 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3519
3520 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3521 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3522 DRM_DEBUG_KMS("FDI train 2 done.\n");
3523 break;
3524 }
8db9d77b 3525 }
e1a44743 3526 if (tries == 5)
5eddb70b 3527 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3528
3529 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3530
8db9d77b
ZW		 3531}
3532
0206e353 3533static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3534 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3535 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3536 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3537 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3538};
3539
3540/* The FDI link training functions for SNB/Cougarpoint. */
3541static void gen6_fdi_link_train(struct drm_crtc *crtc)
3542{
3543 struct drm_device *dev = crtc->dev;
3544 struct drm_i915_private *dev_priv = dev->dev_private;
3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546 int pipe = intel_crtc->pipe;
fa37d39e 3547 u32 reg, temp, i, retry;
8db9d77b 3548
e1a44743
AJ		 3549 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3550 for train result */
5eddb70b
CW		 3551 reg = FDI_RX_IMR(pipe);
3552 temp = I915_READ(reg);
e1a44743
AJ		 3553 temp &= ~FDI_RX_SYMBOL_LOCK;
3554 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3555 I915_WRITE(reg, temp);
3556
3557 POSTING_READ(reg);
e1a44743
AJ		 3558 udelay(150);
3559
8db9d77b 3560 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
627eb5a3 3563 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3564 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3565 temp &= ~FDI_LINK_TRAIN_NONE;
3566 temp |= FDI_LINK_TRAIN_PATTERN_1;
3567 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3568 /* SNB-B */
3569 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3570 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3571
d74cf324
DV		 3572 I915_WRITE(FDI_RX_MISC(pipe),
3573 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3574
5eddb70b
CW		 3575 reg = FDI_RX_CTL(pipe);
3576 temp = I915_READ(reg);
8db9d77b
ZW		 3577 if (HAS_PCH_CPT(dev)) {
3578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3579 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3580 } else {
3581 temp &= ~FDI_LINK_TRAIN_NONE;
3582 temp |= FDI_LINK_TRAIN_PATTERN_1;
3583 }
5eddb70b
CW		 3584 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3585
3586 POSTING_READ(reg);
8db9d77b
ZW		 3587 udelay(150);
3588
0206e353 3589 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3590 reg = FDI_TX_CTL(pipe);
3591 temp = I915_READ(reg);
8db9d77b
ZW		 3592 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3594 I915_WRITE(reg, temp);
3595
3596 POSTING_READ(reg);
8db9d77b
ZW		 3597 udelay(500);
3598
fa37d39e
SP		 3599 for (retry = 0; retry < 5; retry++) {
3600 reg = FDI_RX_IIR(pipe);
3601 temp = I915_READ(reg);
3602 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603 if (temp & FDI_RX_BIT_LOCK) {
3604 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3605 DRM_DEBUG_KMS("FDI train 1 done.\n");
3606 break;
3607 }
3608 udelay(50);
8db9d77b 3609 }
fa37d39e
SP		 3610 if (retry < 5)
3611 break;
8db9d77b
ZW		 3612 }
3613 if (i == 4)
5eddb70b 3614 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3615
3616 /* Train 2 */
5eddb70b
CW		 3617 reg = FDI_TX_CTL(pipe);
3618 temp = I915_READ(reg);
8db9d77b
ZW		 3619 temp &= ~FDI_LINK_TRAIN_NONE;
3620 temp |= FDI_LINK_TRAIN_PATTERN_2;
3621 if (IS_GEN6(dev)) {
3622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3623 /* SNB-B */
3624 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3625 }
5eddb70b 3626 I915_WRITE(reg, temp);
8db9d77b 3627
5eddb70b
CW		 3628 reg = FDI_RX_CTL(pipe);
3629 temp = I915_READ(reg);
8db9d77b
ZW		 3630 if (HAS_PCH_CPT(dev)) {
3631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3632 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3633 } else {
3634 temp &= ~FDI_LINK_TRAIN_NONE;
3635 temp |= FDI_LINK_TRAIN_PATTERN_2;
3636 }
5eddb70b
CW		 3637 I915_WRITE(reg, temp);
3638
3639 POSTING_READ(reg);
8db9d77b
ZW		 3640 udelay(150);
3641
0206e353 3642 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3643 reg = FDI_TX_CTL(pipe);
3644 temp = I915_READ(reg);
8db9d77b
ZW		 3645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3646 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3647 I915_WRITE(reg, temp);
3648
3649 POSTING_READ(reg);
8db9d77b
ZW		 3650 udelay(500);
3651
fa37d39e
SP		 3652 for (retry = 0; retry < 5; retry++) {
3653 reg = FDI_RX_IIR(pipe);
3654 temp = I915_READ(reg);
3655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3656 if (temp & FDI_RX_SYMBOL_LOCK) {
3657 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3658 DRM_DEBUG_KMS("FDI train 2 done.\n");
3659 break;
3660 }
3661 udelay(50);
8db9d77b 3662 }
fa37d39e
SP		 3663 if (retry < 5)
3664 break;
8db9d77b
ZW		 3665 }
3666 if (i == 4)
5eddb70b 3667 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3668
3669 DRM_DEBUG_KMS("FDI train done.\n");
3670}
3671
357555c0
JB		 3672/* Manual link training for Ivy Bridge A0 parts */
3673static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3674{
3675 struct drm_device *dev = crtc->dev;
3676 struct drm_i915_private *dev_priv = dev->dev_private;
3677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3678 int pipe = intel_crtc->pipe;
139ccd3f 3679 u32 reg, temp, i, j;
357555c0
JB		 3680
3681 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3682 for train result */
3683 reg = FDI_RX_IMR(pipe);
3684 temp = I915_READ(reg);
3685 temp &= ~FDI_RX_SYMBOL_LOCK;
3686 temp &= ~FDI_RX_BIT_LOCK;
3687 I915_WRITE(reg, temp);
3688
3689 POSTING_READ(reg);
3690 udelay(150);
3691
01a415fd
DV		 3692 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3693 I915_READ(FDI_RX_IIR(pipe)));
3694
139ccd3f
JB		 3695 /* Try each vswing and preemphasis setting twice before moving on */
3696 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3697 /* disable first in case we need to retry */
3698 reg = FDI_TX_CTL(pipe);
3699 temp = I915_READ(reg);
3700 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3701 temp &= ~FDI_TX_ENABLE;
3702 I915_WRITE(reg, temp);
357555c0 3703
139ccd3f
JB		 3704 reg = FDI_RX_CTL(pipe);
3705 temp = I915_READ(reg);
3706 temp &= ~FDI_LINK_TRAIN_AUTO;
3707 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3708 temp &= ~FDI_RX_ENABLE;
3709 I915_WRITE(reg, temp);
357555c0 3710
139ccd3f 3711 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3712 reg = FDI_TX_CTL(pipe);
3713 temp = I915_READ(reg);
139ccd3f 3714 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3715 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3716 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3717 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3718 temp |= snb_b_fdi_train_param[j/2];
3719 temp |= FDI_COMPOSITE_SYNC;
3720 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3721
139ccd3f
JB		 3722 I915_WRITE(FDI_RX_MISC(pipe),
3723 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3724
139ccd3f 3725 reg = FDI_RX_CTL(pipe);
357555c0 3726 temp = I915_READ(reg);
139ccd3f
JB		 3727 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3728 temp |= FDI_COMPOSITE_SYNC;
3729 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3730
139ccd3f
JB		 3731 POSTING_READ(reg);
3732 udelay(1); /* should be 0.5us */
357555c0 3733
139ccd3f
JB		 3734 for (i = 0; i < 4; i++) {
3735 reg = FDI_RX_IIR(pipe);
3736 temp = I915_READ(reg);
3737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3738
139ccd3f
JB		 3739 if (temp & FDI_RX_BIT_LOCK ||
3740 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3741 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3742 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3743 i);
3744 break;
3745 }
3746 udelay(1); /* should be 0.5us */
3747 }
3748 if (i == 4) {
3749 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3750 continue;
3751 }
357555c0 3752
139ccd3f 3753 /* Train 2 */
357555c0
JB		 3754 reg = FDI_TX_CTL(pipe);
3755 temp = I915_READ(reg);
139ccd3f
JB		 3756 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3757 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3758 I915_WRITE(reg, temp);
3759
3760 reg = FDI_RX_CTL(pipe);
3761 temp = I915_READ(reg);
3762 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3763 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3764 I915_WRITE(reg, temp);
3765
3766 POSTING_READ(reg);
139ccd3f 3767 udelay(2); /* should be 1.5us */
357555c0 3768
139ccd3f
JB		 3769 for (i = 0; i < 4; i++) {
3770 reg = FDI_RX_IIR(pipe);
3771 temp = I915_READ(reg);
3772 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3773
139ccd3f
JB		 3774 if (temp & FDI_RX_SYMBOL_LOCK ||
3775 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3776 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3777 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3778 i);
3779 goto train_done;
3780 }
3781 udelay(2); /* should be 1.5us */
357555c0 3782 }
139ccd3f
JB		 3783 if (i == 4)
3784 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3785 }
357555c0 3786
139ccd3f 3787train_done:
357555c0
JB		 3788 DRM_DEBUG_KMS("FDI train done.\n");
3789}
3790
88cefb6c 3791static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3792{
88cefb6c 3793 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3794 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3795 int pipe = intel_crtc->pipe;
5eddb70b 3796 u32 reg, temp;
79e53945 3797
c64e311e 3798
c98e9dcf 3799 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3800 reg = FDI_RX_CTL(pipe);
3801 temp = I915_READ(reg);
627eb5a3 3802 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3803 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3804 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3805 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3806
3807 POSTING_READ(reg);
c98e9dcf
JB		 3808 udelay(200);
3809
3810 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3811 temp = I915_READ(reg);
3812 I915_WRITE(reg, temp | FDI_PCDCLK);
3813
3814 POSTING_READ(reg);
c98e9dcf
JB		 3815 udelay(200);
3816
20749730
PZ		 3817 /* Enable CPU FDI TX PLL, always on for Ironlake */
3818 reg = FDI_TX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3821 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3822
20749730
PZ		 3823 POSTING_READ(reg);
3824 udelay(100);
6be4a607 3825 }
0e23b99d
JB		 3826}
3827
88cefb6c
DV		 3828static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3829{
3830 struct drm_device *dev = intel_crtc->base.dev;
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832 int pipe = intel_crtc->pipe;
3833 u32 reg, temp;
3834
3835 /* Switch from PCDclk to Rawclk */
3836 reg = FDI_RX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3839
3840 /* Disable CPU FDI TX PLL */
3841 reg = FDI_TX_CTL(pipe);
3842 temp = I915_READ(reg);
3843 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3844
3845 POSTING_READ(reg);
3846 udelay(100);
3847
3848 reg = FDI_RX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3851
3852 /* Wait for the clocks to turn off. */
3853 POSTING_READ(reg);
3854 udelay(100);
3855}
3856
0fc932b8
JB		 3857static void ironlake_fdi_disable(struct drm_crtc *crtc)
3858{
3859 struct drm_device *dev = crtc->dev;
3860 struct drm_i915_private *dev_priv = dev->dev_private;
3861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862 int pipe = intel_crtc->pipe;
3863 u32 reg, temp;
3864
3865 /* disable CPU FDI tx and PCH FDI rx */
3866 reg = FDI_TX_CTL(pipe);
3867 temp = I915_READ(reg);
3868 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3869 POSTING_READ(reg);
3870
3871 reg = FDI_RX_CTL(pipe);
3872 temp = I915_READ(reg);
3873 temp &= ~(0x7 << 16);
dfd07d72 3874 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3875 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3876
3877 POSTING_READ(reg);
3878 udelay(100);
3879
3880 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3881 if (HAS_PCH_IBX(dev))
6f06ce18 3882 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3883
3884 /* still set train pattern 1 */
3885 reg = FDI_TX_CTL(pipe);
3886 temp = I915_READ(reg);
3887 temp &= ~FDI_LINK_TRAIN_NONE;
3888 temp |= FDI_LINK_TRAIN_PATTERN_1;
3889 I915_WRITE(reg, temp);
3890
3891 reg = FDI_RX_CTL(pipe);
3892 temp = I915_READ(reg);
3893 if (HAS_PCH_CPT(dev)) {
3894 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3895 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3896 } else {
3897 temp &= ~FDI_LINK_TRAIN_NONE;
3898 temp |= FDI_LINK_TRAIN_PATTERN_1;
3899 }
3900 /* BPC in FDI rx is consistent with that in PIPECONF */
3901 temp &= ~(0x07 << 16);
dfd07d72 3902 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3903 I915_WRITE(reg, temp);
3904
3905 POSTING_READ(reg);
3906 udelay(100);
3907}
3908
5dce5b93
CW		 3909bool intel_has_pending_fb_unpin(struct drm_device *dev)
3910{
3911 struct intel_crtc *crtc;
3912
3913 /* Note that we don't need to be called with mode_config.lock here
3914 * as our list of CRTC objects is static for the lifetime of the
3915 * device and so cannot disappear as we iterate. Similarly, we can
3916 * happily treat the predicates as racy, atomic checks as userspace
3917 * cannot claim and pin a new fb without at least acquring the
3918 * struct_mutex and so serialising with us.
3919 */
d3fcc808 3920 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3921 if (atomic_read(&crtc->unpin_work_count) == 0)
3922 continue;
3923
3924 if (crtc->unpin_work)
3925 intel_wait_for_vblank(dev, crtc->pipe);
3926
3927 return true;
3928 }
3929
3930 return false;
3931}
3932
d6bbafa1
CW		 3933static void page_flip_completed(struct intel_crtc *intel_crtc)
3934{
3935 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3936 struct intel_unpin_work *work = intel_crtc->unpin_work;
3937
3938 /* ensure that the unpin work is consistent wrt ->pending. */
3939 smp_rmb();
3940 intel_crtc->unpin_work = NULL;
3941
3942 if (work->event)
3943 drm_send_vblank_event(intel_crtc->base.dev,
3944 intel_crtc->pipe,
3945 work->event);
3946
3947 drm_crtc_vblank_put(&intel_crtc->base);
3948
3949 wake_up_all(&dev_priv->pending_flip_queue);
3950 queue_work(dev_priv->wq, &work->work);
3951
3952 trace_i915_flip_complete(intel_crtc->plane,
3953 work->pending_flip_obj);
3954}
3955
46a55d30 3956void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3957{
0f91128d 3958 struct drm_device *dev = crtc->dev;
5bb61643 3959 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3960
2c10d571 3961 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3962 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3963 !intel_crtc_has_pending_flip(crtc),
3964 60*HZ) == 0)) {
3965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3966
5e2d7afc 3967 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3968 if (intel_crtc->unpin_work) {
3969 WARN_ONCE(1, "Removing stuck page flip\n");
3970 page_flip_completed(intel_crtc);
3971 }
5e2d7afc 3972 spin_unlock_irq(&dev->event_lock);
9c787942 3973 }
5bb61643 3974
975d568a
CW		 3975 if (crtc->primary->fb) {
3976 mutex_lock(&dev->struct_mutex);
3977 intel_finish_fb(crtc->primary->fb);
3978 mutex_unlock(&dev->struct_mutex);
3979 }
e6c3a2a6
CW		 3980}
3981
e615efe4
ED		 3982/* Program iCLKIP clock to the desired frequency */
3983static void lpt_program_iclkip(struct drm_crtc *crtc)
3984{
3985 struct drm_device *dev = crtc->dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3987 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3988 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3989 u32 temp;
3990
a580516d 3991 mutex_lock(&dev_priv->sb_lock);
09153000 3992
e615efe4
ED		 3993 /* It is necessary to ungate the pixclk gate prior to programming
3994 * the divisors, and gate it back when it is done.
3995 */
3996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3997
3998 /* Disable SSCCTL */
3999 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 4000 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
4001 SBI_SSCCTL_DISABLE,
4002 SBI_ICLK);
e615efe4
ED		 4003
4004 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 4005 if (clock == 20000) {
e615efe4
ED		 4006 auxdiv = 1;
4007 divsel = 0x41;
4008 phaseinc = 0x20;
4009 } else {
4010 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 4011 * but the adjusted_mode->crtc_clock in in KHz. To get the
4012 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 4013 * convert the virtual clock precision to KHz here for higher
4014 * precision.
4015 */
4016 u32 iclk_virtual_root_freq = 172800 * 1000;
4017 u32 iclk_pi_range = 64;
4018 u32 desired_divisor, msb_divisor_value, pi_value;
4019
12d7ceed 4020 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 4021 msb_divisor_value = desired_divisor / iclk_pi_range;
4022 pi_value = desired_divisor % iclk_pi_range;
4023
4024 auxdiv = 0;
4025 divsel = msb_divisor_value - 2;
4026 phaseinc = pi_value;
4027 }
4028
4029 /* This should not happen with any sane values */
4030 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4031 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4032 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4033 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4034
4035 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4036 clock,
e615efe4
ED		 4037 auxdiv,
4038 divsel,
4039 phasedir,
4040 phaseinc);
4041
4042 /* Program SSCDIVINTPHASE6 */
988d6ee8 4043 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 4044 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4045 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4046 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4047 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4048 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4049 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4050 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4051
4052 /* Program SSCAUXDIV */
988d6ee8 4053 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4054 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4055 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4056 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4057
4058 /* Enable modulator and associated divider */
988d6ee8 4059 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4060 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4061 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4062
4063 /* Wait for initialization time */
4064 udelay(24);
4065
4066 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4067
a580516d 4068 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4069}
4070
275f01b2
DV		 4071static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4072 enum pipe pch_transcoder)
4073{
4074 struct drm_device *dev = crtc->base.dev;
4075 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4076 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4077
4078 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4079 I915_READ(HTOTAL(cpu_transcoder)));
4080 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4081 I915_READ(HBLANK(cpu_transcoder)));
4082 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4083 I915_READ(HSYNC(cpu_transcoder)));
4084
4085 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4086 I915_READ(VTOTAL(cpu_transcoder)));
4087 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4088 I915_READ(VBLANK(cpu_transcoder)));
4089 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4090 I915_READ(VSYNC(cpu_transcoder)));
4091 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4092 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4093}
4094
003632d9 4095static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4096{
4097 struct drm_i915_private *dev_priv = dev->dev_private;
4098 uint32_t temp;
4099
4100 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4101 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4102 return;
4103
4104 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4105 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4106
003632d9
ACO		 4107 temp &= ~FDI_BC_BIFURCATION_SELECT;
4108 if (enable)
4109 temp |= FDI_BC_BIFURCATION_SELECT;
4110
4111 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4112 I915_WRITE(SOUTH_CHICKEN1, temp);
4113 POSTING_READ(SOUTH_CHICKEN1);
4114}
4115
4116static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4117{
4118 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4119
4120 switch (intel_crtc->pipe) {
4121 case PIPE_A:
4122 break;
4123 case PIPE_B:
6e3c9717 4124 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4125 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4126 else
003632d9 4127 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4128
4129 break;
4130 case PIPE_C:
003632d9 4131 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4132
4133 break;
4134 default:
4135 BUG();
4136 }
4137}
4138
f67a559d
JB		 4139/*
4140 * Enable PCH resources required for PCH ports:
4141 * - PCH PLLs
4142 * - FDI training & RX/TX
4143 * - update transcoder timings
4144 * - DP transcoding bits
4145 * - transcoder
4146 */
4147static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4148{
4149 struct drm_device *dev = crtc->dev;
4150 struct drm_i915_private *dev_priv = dev->dev_private;
4151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4152 int pipe = intel_crtc->pipe;
ee7b9f93 4153 u32 reg, temp;
2c07245f 4154
ab9412ba 4155 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4156
1fbc0d78
DV		 4157 if (IS_IVYBRIDGE(dev))
4158 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4159
cd986abb
DV		 4160 /* Write the TU size bits before fdi link training, so that error
4161 * detection works. */
4162 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4163 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4164
c98e9dcf 4165 /* For PCH output, training FDI link */
674cf967 4166 dev_priv->display.fdi_link_train(crtc);
2c07245f 4167
3ad8a208
DV		 4168 /* We need to program the right clock selection before writing the pixel
4169 * mutliplier into the DPLL. */
303b81e0 4170 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4171 u32 sel;
4b645f14 4172
c98e9dcf 4173 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4174 temp |= TRANS_DPLL_ENABLE(pipe);
4175 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4176 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4177 temp |= sel;
4178 else
4179 temp &= ~sel;
c98e9dcf 4180 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4181 }
5eddb70b 4182
3ad8a208
DV		 4183 /* XXX: pch pll's can be enabled any time before we enable the PCH
4184 * transcoder, and we actually should do this to not upset any PCH
4185 * transcoder that already use the clock when we share it.
4186 *
4187 * Note that enable_shared_dpll tries to do the right thing, but
4188 * get_shared_dpll unconditionally resets the pll - we need that to have
4189 * the right LVDS enable sequence. */
85b3894f 4190 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4191
d9b6cb56
JB		 4192 /* set transcoder timing, panel must allow it */
4193 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4194 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4195
303b81e0 4196 intel_fdi_normal_train(crtc);
5e84e1a4 4197
c98e9dcf 4198 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4199 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4200 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4201 reg = TRANS_DP_CTL(pipe);
4202 temp = I915_READ(reg);
4203 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4204 TRANS_DP_SYNC_MASK |
4205 TRANS_DP_BPC_MASK);
e3ef4479 4206 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4207 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4208
4209 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4210 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4211 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4212 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4213
4214 switch (intel_trans_dp_port_sel(crtc)) {
4215 case PCH_DP_B:
5eddb70b 4216 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4217 break;
4218 case PCH_DP_C:
5eddb70b 4219 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4220 break;
4221 case PCH_DP_D:
5eddb70b 4222 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4223 break;
4224 default:
e95d41e1 4225 BUG();
32f9d658 4226 }
2c07245f 4227
5eddb70b 4228 I915_WRITE(reg, temp);
6be4a607 4229 }
b52eb4dc 4230
b8a4f404 4231 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4232}
4233
1507e5bd
PZ		 4234static void lpt_pch_enable(struct drm_crtc *crtc)
4235{
4236 struct drm_device *dev = crtc->dev;
4237 struct drm_i915_private *dev_priv = dev->dev_private;
4238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4239 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4240
ab9412ba 4241 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4242
8c52b5e8 4243 lpt_program_iclkip(crtc);
1507e5bd 4244
0540e488 4245 /* Set transcoder timing. */
275f01b2 4246 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4247
937bb610 4248 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4249}
4250
190f68c5
ACO		 4251struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4252 struct intel_crtc_state *crtc_state)
ee7b9f93 4253{
e2b78267 4254 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4255 struct intel_shared_dpll *pll;
de419ab6 4256 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4257 enum intel_dpll_id i;
ee7b9f93 4258
de419ab6
ML		 4259 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4260
98b6bd99
DV		 4261 if (HAS_PCH_IBX(dev_priv->dev)) {
4262 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4263 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4264 pll = &dev_priv->shared_dplls[i];
98b6bd99 4265
46edb027
DV		 4266 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4267 crtc->base.base.id, pll->name);
98b6bd99 4268
de419ab6 4269 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4270
98b6bd99
DV		 4271 goto found;
4272 }
4273
bcddf610
S		 4274 if (IS_BROXTON(dev_priv->dev)) {
4275 /* PLL is attached to port in bxt */
4276 struct intel_encoder *encoder;
4277 struct intel_digital_port *intel_dig_port;
4278
4279 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4280 if (WARN_ON(!encoder))
4281 return NULL;
4282
4283 intel_dig_port = enc_to_dig_port(&encoder->base);
4284 /* 1:1 mapping between ports and PLLs */
4285 i = (enum intel_dpll_id)intel_dig_port->port;
4286 pll = &dev_priv->shared_dplls[i];
4287 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4288 crtc->base.base.id, pll->name);
de419ab6 4289 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4290
4291 goto found;
4292 }
4293
e72f9fbf
DV		 4294 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4295 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4296
4297 /* Only want to check enabled timings first */
de419ab6 4298 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4299 continue;
4300
190f68c5 4301 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4302 &shared_dpll[i].hw_state,
4303 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4304 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4305 crtc->base.base.id, pll->name,
de419ab6 4306 shared_dpll[i].crtc_mask,
8bd31e67 4307 pll->active);
ee7b9f93
JB		 4308 goto found;
4309 }
4310 }
4311
4312 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4313 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4314 pll = &dev_priv->shared_dplls[i];
de419ab6 4315 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4316 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4317 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4318 goto found;
4319 }
4320 }
4321
4322 return NULL;
4323
4324found:
de419ab6
ML		 4325 if (shared_dpll[i].crtc_mask == 0)
4326 shared_dpll[i].hw_state =
4327 crtc_state->dpll_hw_state;
f2a69f44 4328
190f68c5 4329 crtc_state->shared_dpll = i;
46edb027
DV		 4330 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4331 pipe_name(crtc->pipe));
ee7b9f93 4332
de419ab6 4333 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4334
ee7b9f93
JB		 4335 return pll;
4336}
4337
de419ab6 4338static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4339{
de419ab6
ML		 4340 struct drm_i915_private *dev_priv = to_i915(state->dev);
4341 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4342 struct intel_shared_dpll *pll;
4343 enum intel_dpll_id i;
4344
de419ab6
ML		 4345 if (!to_intel_atomic_state(state)->dpll_set)
4346 return;
8bd31e67 4347
de419ab6 4348 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4349 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4350 pll = &dev_priv->shared_dplls[i];
de419ab6 4351 pll->config = shared_dpll[i];
8bd31e67
ACO		 4352 }
4353}
4354
a1520318 4355static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4356{
4357 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4358 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4359 u32 temp;
4360
4361 temp = I915_READ(dslreg);
4362 udelay(500);
4363 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4364 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4365 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4366 }
4367}
4368
86adf9d7
ML		 4369static int
4370skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4371 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4372 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4373{
86adf9d7
ML		 4374 struct intel_crtc_scaler_state *scaler_state =
4375 &crtc_state->scaler_state;
4376 struct intel_crtc *intel_crtc =
4377 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4378 int need_scaling;
6156a456
CK		 4379
4380 need_scaling = intel_rotation_90_or_270(rotation) ?
4381 (src_h != dst_w || src_w != dst_h):
4382 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4383
4384 /*
4385 * if plane is being disabled or scaler is no more required or force detach
4386 * - free scaler binded to this plane/crtc
4387 * - in order to do this, update crtc->scaler_usage
4388 *
4389 * Here scaler state in crtc_state is set free so that
4390 * scaler can be assigned to other user. Actual register
4391 * update to free the scaler is done in plane/panel-fit programming.
4392 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4393 */
86adf9d7 4394 if (force_detach || !need_scaling) {
a1b2278e 4395 if (*scaler_id >= 0) {
86adf9d7 4396 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4397 scaler_state->scalers[*scaler_id].in_use = 0;
4398
86adf9d7
ML		 4399 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4400 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4401 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4402 scaler_state->scaler_users);
4403 *scaler_id = -1;
4404 }
4405 return 0;
4406 }
4407
4408 /* range checks */
4409 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4410 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4411
4412 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4413 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4414 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4415 "size is out of scaler range\n",
86adf9d7 4416 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4417 return -EINVAL;
4418 }
4419
86adf9d7
ML		 4420 /* mark this plane as a scaler user in crtc_state */
4421 scaler_state->scaler_users |= (1 << scaler_user);
4422 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4423 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4424 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4425 scaler_state->scaler_users);
4426
4427 return 0;
4428}
4429
4430/**
4431 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4432 *
4433 * @state: crtc's scaler state
86adf9d7
ML		 4434 *
4435 * Return
4436 * 0 - scaler_usage updated successfully
4437 * error - requested scaling cannot be supported or other error condition
4438 */
e435d6e5 4439int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4440{
4441 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
7c5f93b0 4442 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
86adf9d7
ML		 4443
4444 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4445 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4446
e435d6e5 4447 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4448 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4449 state->pipe_src_w, state->pipe_src_h,
aad941d5 4450 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
86adf9d7
ML		 4451}
4452
4453/**
4454 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4455 *
4456 * @state: crtc's scaler state
86adf9d7
ML		 4457 * @plane_state: atomic plane state to update
4458 *
4459 * Return
4460 * 0 - scaler_usage updated successfully
4461 * error - requested scaling cannot be supported or other error condition
4462 */
da20eabd
ML		 4463static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4464 struct intel_plane_state *plane_state)
86adf9d7
ML		 4465{
4466
4467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4468 struct intel_plane *intel_plane =
4469 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4470 struct drm_framebuffer *fb = plane_state->base.fb;
4471 int ret;
4472
4473 bool force_detach = !fb || !plane_state->visible;
4474
4475 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4476 intel_plane->base.base.id, intel_crtc->pipe,
4477 drm_plane_index(&intel_plane->base));
4478
4479 ret = skl_update_scaler(crtc_state, force_detach,
4480 drm_plane_index(&intel_plane->base),
4481 &plane_state->scaler_id,
4482 plane_state->base.rotation,
4483 drm_rect_width(&plane_state->src) >> 16,
4484 drm_rect_height(&plane_state->src) >> 16,
4485 drm_rect_width(&plane_state->dst),
4486 drm_rect_height(&plane_state->dst));
4487
4488 if (ret || plane_state->scaler_id < 0)
4489 return ret;
4490
a1b2278e 4491 /* check colorkey */
818ed961 4492 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4493 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4494 intel_plane->base.base.id);
a1b2278e
CK		 4495 return -EINVAL;
4496 }
4497
4498 /* Check src format */
86adf9d7
ML		 4499 switch (fb->pixel_format) {
4500 case DRM_FORMAT_RGB565:
4501 case DRM_FORMAT_XBGR8888:
4502 case DRM_FORMAT_XRGB8888:
4503 case DRM_FORMAT_ABGR8888:
4504 case DRM_FORMAT_ARGB8888:
4505 case DRM_FORMAT_XRGB2101010:
4506 case DRM_FORMAT_XBGR2101010:
4507 case DRM_FORMAT_YUYV:
4508 case DRM_FORMAT_YVYU:
4509 case DRM_FORMAT_UYVY:
4510 case DRM_FORMAT_VYUY:
4511 break;
4512 default:
4513 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4514 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4515 return -EINVAL;
a1b2278e
CK		 4516 }
4517
a1b2278e
CK		 4518 return 0;
4519}
4520
e435d6e5
ML		 4521static void skylake_scaler_disable(struct intel_crtc *crtc)
4522{
4523 int i;
4524
4525 for (i = 0; i < crtc->num_scalers; i++)
4526 skl_detach_scaler(crtc, i);
4527}
4528
4529static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4530{
4531 struct drm_device *dev = crtc->base.dev;
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 int pipe = crtc->pipe;
a1b2278e
CK		 4534 struct intel_crtc_scaler_state *scaler_state =
4535 &crtc->config->scaler_state;
4536
4537 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4538
6e3c9717 4539 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4540 int id;
4541
4542 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4543 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4544 return;
4545 }
4546
4547 id = scaler_state->scaler_id;
4548 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4549 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4550 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4551 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4552
4553 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4554 }
4555}
4556
b074cec8
JB		 4557static void ironlake_pfit_enable(struct intel_crtc *crtc)
4558{
4559 struct drm_device *dev = crtc->base.dev;
4560 struct drm_i915_private *dev_priv = dev->dev_private;
4561 int pipe = crtc->pipe;
4562
6e3c9717 4563 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4564 /* Force use of hard-coded filter coefficients
4565 * as some pre-programmed values are broken,
4566 * e.g. x201.
4567 */
4568 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4569 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4570 PF_PIPE_SEL_IVB(pipe));
4571 else
4572 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4573 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4574 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4575 }
4576}
4577
20bc8673 4578void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4579{
cea165c3
VS		 4580 struct drm_device *dev = crtc->base.dev;
4581 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4582
6e3c9717 4583 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4584 return;
4585
cea165c3
VS		 4586 /* We can only enable IPS after we enable a plane and wait for a vblank */
4587 intel_wait_for_vblank(dev, crtc->pipe);
4588
d77e4531 4589 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4590 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4591 mutex_lock(&dev_priv->rps.hw_lock);
4592 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4593 mutex_unlock(&dev_priv->rps.hw_lock);
4594 /* Quoting Art Runyan: "its not safe to expect any particular
4595 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4596 * mailbox." Moreover, the mailbox may return a bogus state,
4597 * so we need to just enable it and continue on.
2a114cc1
BW		 4598 */
4599 } else {
4600 I915_WRITE(IPS_CTL, IPS_ENABLE);
4601 /* The bit only becomes 1 in the next vblank, so this wait here
4602 * is essentially intel_wait_for_vblank. If we don't have this
4603 * and don't wait for vblanks until the end of crtc_enable, then
4604 * the HW state readout code will complain that the expected
4605 * IPS_CTL value is not the one we read. */
4606 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4607 DRM_ERROR("Timed out waiting for IPS enable\n");
4608 }
d77e4531
PZ		 4609}
4610
20bc8673 4611void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4612{
4613 struct drm_device *dev = crtc->base.dev;
4614 struct drm_i915_private *dev_priv = dev->dev_private;
4615
6e3c9717 4616 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4617 return;
4618
4619 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4620 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4621 mutex_lock(&dev_priv->rps.hw_lock);
4622 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4623 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4624 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4625 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4626 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4627 } else {
2a114cc1 4628 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4629 POSTING_READ(IPS_CTL);
4630 }
d77e4531
PZ		 4631
4632 /* We need to wait for a vblank before we can disable the plane. */
4633 intel_wait_for_vblank(dev, crtc->pipe);
4634}
4635
4636/** Loads the palette/gamma unit for the CRTC with the prepared values */
4637static void intel_crtc_load_lut(struct drm_crtc *crtc)
4638{
4639 struct drm_device *dev = crtc->dev;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4642 enum pipe pipe = intel_crtc->pipe;
d77e4531
PZ		 4643 int i;
4644 bool reenable_ips = false;
4645
4646 /* The clocks have to be on to load the palette. */
53d9f4e9 4647 if (!crtc->state->active)
d77e4531
PZ		 4648 return;
4649
50360403 4650 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4651 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4652 assert_dsi_pll_enabled(dev_priv);
4653 else
4654 assert_pll_enabled(dev_priv, pipe);
4655 }
4656
d77e4531
PZ		 4657 /* Workaround : Do not read or write the pipe palette/gamma data while
4658 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4659 */
6e3c9717 4660 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4661 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4662 GAMMA_MODE_MODE_SPLIT)) {
4663 hsw_disable_ips(intel_crtc);
4664 reenable_ips = true;
4665 }
4666
4667 for (i = 0; i < 256; i++) {
f65a9c5b
VS		 4668 u32 palreg;
4669
4670 if (HAS_GMCH_DISPLAY(dev))
4671 palreg = PALETTE(pipe, i);
4672 else
4673 palreg = LGC_PALETTE(pipe, i);
4674
4675 I915_WRITE(palreg,
d77e4531
PZ		 4676 (intel_crtc->lut_r[i] << 16) |
4677 (intel_crtc->lut_g[i] << 8) |
4678 intel_crtc->lut_b[i]);
4679 }
4680
4681 if (reenable_ips)
4682 hsw_enable_ips(intel_crtc);
4683}
4684
7cac945f 4685static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4686{
7cac945f 4687 if (intel_crtc->overlay) {
d3eedb1a
VS		 4688 struct drm_device *dev = intel_crtc->base.dev;
4689 struct drm_i915_private *dev_priv = dev->dev_private;
4690
4691 mutex_lock(&dev->struct_mutex);
4692 dev_priv->mm.interruptible = false;
4693 (void) intel_overlay_switch_off(intel_crtc->overlay);
4694 dev_priv->mm.interruptible = true;
4695 mutex_unlock(&dev->struct_mutex);
4696 }
4697
4698 /* Let userspace switch the overlay on again. In most cases userspace
4699 * has to recompute where to put it anyway.
4700 */
4701}
4702
87d4300a
ML		 4703/**
4704 * intel_post_enable_primary - Perform operations after enabling primary plane
4705 * @crtc: the CRTC whose primary plane was just enabled
4706 *
4707 * Performs potentially sleeping operations that must be done after the primary
4708 * plane is enabled, such as updating FBC and IPS. Note that this may be
4709 * called due to an explicit primary plane update, or due to an implicit
4710 * re-enable that is caused when a sprite plane is updated to no longer
4711 * completely hide the primary plane.
4712 */
4713static void
4714intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4715{
4716 struct drm_device *dev = crtc->dev;
87d4300a 4717 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719 int pipe = intel_crtc->pipe;
a5c4d7bc 4720
87d4300a
ML		 4721 /*
4722 * BDW signals flip done immediately if the plane
4723 * is disabled, even if the plane enable is already
4724 * armed to occur at the next vblank :(
4725 */
4726 if (IS_BROADWELL(dev))
4727 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4728
87d4300a
ML		 4729 /*
4730 * FIXME IPS should be fine as long as one plane is
4731 * enabled, but in practice it seems to have problems
4732 * when going from primary only to sprite only and vice
4733 * versa.
4734 */
a5c4d7bc
VS		 4735 hsw_enable_ips(intel_crtc);
4736
f99d7069 4737 /*
87d4300a
ML		 4738 * Gen2 reports pipe underruns whenever all planes are disabled.
4739 * So don't enable underrun reporting before at least some planes
4740 * are enabled.
4741 * FIXME: Need to fix the logic to work when we turn off all planes
4742 * but leave the pipe running.
f99d7069 4743 */
87d4300a
ML		 4744 if (IS_GEN2(dev))
4745 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4746
4747 /* Underruns don't raise interrupts, so check manually. */
4748 if (HAS_GMCH_DISPLAY(dev))
4749 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4750}
4751
87d4300a
ML		 4752/**
4753 * intel_pre_disable_primary - Perform operations before disabling primary plane
4754 * @crtc: the CRTC whose primary plane is to be disabled
4755 *
4756 * Performs potentially sleeping operations that must be done before the
4757 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4758 * be called due to an explicit primary plane update, or due to an implicit
4759 * disable that is caused when a sprite plane completely hides the primary
4760 * plane.
4761 */
4762static void
4763intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4764{
4765 struct drm_device *dev = crtc->dev;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768 int pipe = intel_crtc->pipe;
a5c4d7bc 4769
87d4300a
ML		 4770 /*
4771 * Gen2 reports pipe underruns whenever all planes are disabled.
4772 * So diasble underrun reporting before all the planes get disabled.
4773 * FIXME: Need to fix the logic to work when we turn off all planes
4774 * but leave the pipe running.
4775 */
4776 if (IS_GEN2(dev))
4777 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4778
87d4300a
ML		 4779 /*
4780 * Vblank time updates from the shadow to live plane control register
4781 * are blocked if the memory self-refresh mode is active at that
4782 * moment. So to make sure the plane gets truly disabled, disable
4783 * first the self-refresh mode. The self-refresh enable bit in turn
4784 * will be checked/applied by the HW only at the next frame start
4785 * event which is after the vblank start event, so we need to have a
4786 * wait-for-vblank between disabling the plane and the pipe.
4787 */
262cd2e1 4788 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4789 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4790 dev_priv->wm.vlv.cxsr = false;
4791 intel_wait_for_vblank(dev, pipe);
4792 }
87d4300a 4793
87d4300a
ML		 4794 /*
4795 * FIXME IPS should be fine as long as one plane is
4796 * enabled, but in practice it seems to have problems
4797 * when going from primary only to sprite only and vice
4798 * versa.
4799 */
a5c4d7bc 4800 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4801}
4802
ac21b225
ML		 4803static void intel_post_plane_update(struct intel_crtc *crtc)
4804{
4805 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4806 struct drm_device *dev = crtc->base.dev;
7733b49b 4807 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4808 struct drm_plane *plane;
4809
4810 if (atomic->wait_vblank)
4811 intel_wait_for_vblank(dev, crtc->pipe);
4812
4813 intel_frontbuffer_flip(dev, atomic->fb_bits);
4814
852eb00d
VS		 4815 if (atomic->disable_cxsr)
4816 crtc->wm.cxsr_allowed = true;
4817
f015c551
VS		 4818 if (crtc->atomic.update_wm_post)
4819 intel_update_watermarks(&crtc->base);
4820
c80ac854 4821 if (atomic->update_fbc)
7733b49b 4822 intel_fbc_update(dev_priv);
ac21b225
ML		 4823
4824 if (atomic->post_enable_primary)
4825 intel_post_enable_primary(&crtc->base);
4826
4827 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4828 intel_update_sprite_watermarks(plane, &crtc->base,
4829 0, 0, 0, false, false);
4830
4831 memset(atomic, 0, sizeof(*atomic));
4832}
4833
4834static void intel_pre_plane_update(struct intel_crtc *crtc)
4835{
4836 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4837 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4838 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4839 struct drm_plane *p;
4840
4841 /* Track fb's for any planes being disabled */
ac21b225
ML		 4842 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4843 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4844
4845 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4846 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4847 plane->frontbuffer_bit);
ac21b225
ML		 4848 mutex_unlock(&dev->struct_mutex);
4849 }
4850
4851 if (atomic->wait_for_flips)
4852 intel_crtc_wait_for_pending_flips(&crtc->base);
4853
c80ac854 4854 if (atomic->disable_fbc)
25ad93fd 4855 intel_fbc_disable_crtc(crtc);
ac21b225 4856
066cf55b
RV		 4857 if (crtc->atomic.disable_ips)
4858 hsw_disable_ips(crtc);
4859
ac21b225
ML		 4860 if (atomic->pre_disable_primary)
4861 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4862
4863 if (atomic->disable_cxsr) {
4864 crtc->wm.cxsr_allowed = false;
4865 intel_set_memory_cxsr(dev_priv, false);
4866 }
ac21b225
ML		 4867}
4868
d032ffa0 4869static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4870{
4871 struct drm_device *dev = crtc->dev;
4872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4873 struct drm_plane *p;
87d4300a
ML		 4874 int pipe = intel_crtc->pipe;
4875
7cac945f 4876 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4877
d032ffa0
ML		 4878 drm_for_each_plane_mask(p, dev, plane_mask)
4879 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4880
f99d7069
DV		 4881 /*
4882 * FIXME: Once we grow proper nuclear flip support out of this we need
4883 * to compute the mask of flip planes precisely. For the time being
4884 * consider this a flip to a NULL plane.
4885 */
4886 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4887}
4888
f67a559d
JB		 4889static void ironlake_crtc_enable(struct drm_crtc *crtc)
4890{
4891 struct drm_device *dev = crtc->dev;
4892 struct drm_i915_private *dev_priv = dev->dev_private;
4893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4894 struct intel_encoder *encoder;
f67a559d 4895 int pipe = intel_crtc->pipe;
f67a559d 4896
53d9f4e9 4897 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4898 return;
4899
6e3c9717 4900 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4901 intel_prepare_shared_dpll(intel_crtc);
4902
6e3c9717 4903 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4904 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4905
4906 intel_set_pipe_timings(intel_crtc);
4907
6e3c9717 4908 if (intel_crtc->config->has_pch_encoder) {
29407aab 4909 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4910 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4911 }
4912
4913 ironlake_set_pipeconf(crtc);
4914
f67a559d 4915 intel_crtc->active = true;
8664281b 4916
a72e4c9f
DV		 4917 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4918 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4919
f6736a1a 4920 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4921 if (encoder->pre_enable)
4922 encoder->pre_enable(encoder);
f67a559d 4923
6e3c9717 4924 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4925 /* Note: FDI PLL enabling _must_ be done before we enable the
4926 * cpu pipes, hence this is separate from all the other fdi/pch
4927 * enabling. */
88cefb6c 4928 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4929 } else {
4930 assert_fdi_tx_disabled(dev_priv, pipe);
4931 assert_fdi_rx_disabled(dev_priv, pipe);
4932 }
f67a559d 4933
b074cec8 4934 ironlake_pfit_enable(intel_crtc);
f67a559d 4935
9c54c0dd
JB		 4936 /*
4937 * On ILK+ LUT must be loaded before the pipe is running but with
4938 * clocks enabled
4939 */
4940 intel_crtc_load_lut(crtc);
4941
f37fcc2a 4942 intel_update_watermarks(crtc);
e1fdc473 4943 intel_enable_pipe(intel_crtc);
f67a559d 4944
6e3c9717 4945 if (intel_crtc->config->has_pch_encoder)
f67a559d 4946 ironlake_pch_enable(crtc);
c98e9dcf 4947
f9b61ff6
DV		 4948 assert_vblank_disabled(crtc);
4949 drm_crtc_vblank_on(crtc);
4950
fa5c73b1
DV		 4951 for_each_encoder_on_crtc(dev, crtc, encoder)
4952 encoder->enable(encoder);
61b77ddd
DV		 4953
4954 if (HAS_PCH_CPT(dev))
a1520318 4955 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4956}
4957
42db64ef
PZ		 4958/* IPS only exists on ULT machines and is tied to pipe A. */
4959static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4960{
f5adf94e 4961 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4962}
4963
4f771f10
PZ		 4964static void haswell_crtc_enable(struct drm_crtc *crtc)
4965{
4966 struct drm_device *dev = crtc->dev;
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969 struct intel_encoder *encoder;
99d736a2
ML		 4970 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4971 struct intel_crtc_state *pipe_config =
4972 to_intel_crtc_state(crtc->state);
4f771f10 4973
53d9f4e9 4974 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4975 return;
4976
df8ad70c
DV		 4977 if (intel_crtc_to_shared_dpll(intel_crtc))
4978 intel_enable_shared_dpll(intel_crtc);
4979
6e3c9717 4980 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4981 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4982
4983 intel_set_pipe_timings(intel_crtc);
4984
6e3c9717
ACO		 4985 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4986 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4987 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4988 }
4989
6e3c9717 4990 if (intel_crtc->config->has_pch_encoder) {
229fca97 4991 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4992 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4993 }
4994
4995 haswell_set_pipeconf(crtc);
4996
4997 intel_set_pipe_csc(crtc);
4998
4f771f10 4999 intel_crtc->active = true;
8664281b 5000
a72e4c9f 5001 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5002 for_each_encoder_on_crtc(dev, crtc, encoder)
5003 if (encoder->pre_enable)
5004 encoder->pre_enable(encoder);
5005
6e3c9717 5006 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5007 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5008 true);
4fe9467d
ID		 5009 dev_priv->display.fdi_link_train(crtc);
5010 }
5011
1f544388 5012 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5013
1c132b44 5014 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5015 skylake_pfit_enable(intel_crtc);
ff6d9f55 5016 else
1c132b44 5017 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 5018
5019 /*
5020 * On ILK+ LUT must be loaded before the pipe is running but with
5021 * clocks enabled
5022 */
5023 intel_crtc_load_lut(crtc);
5024
1f544388 5025 intel_ddi_set_pipe_settings(crtc);
8228c251 5026 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5027
f37fcc2a 5028 intel_update_watermarks(crtc);
e1fdc473 5029 intel_enable_pipe(intel_crtc);
42db64ef 5030
6e3c9717 5031 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5032 lpt_pch_enable(crtc);
4f771f10 5033
6e3c9717 5034 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5035 intel_ddi_set_vc_payload_alloc(crtc, true);
5036
f9b61ff6
DV		 5037 assert_vblank_disabled(crtc);
5038 drm_crtc_vblank_on(crtc);
5039
8807e55b 5040 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5041 encoder->enable(encoder);
8807e55b
JN		 5042 intel_opregion_notify_encoder(encoder, true);
5043 }
4f771f10 5044
e4916946
PZ		 5045 /* If we change the relative order between pipe/planes enabling, we need
5046 * to change the workaround. */
99d736a2
ML		 5047 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5048 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5049 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5050 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5051 }
4f771f10
PZ		 5052}
5053
bfd16b2a 5054static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
3f8dce3a
DV		 5055{
5056 struct drm_device *dev = crtc->base.dev;
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 int pipe = crtc->pipe;
5059
5060 /* To avoid upsetting the power well on haswell only disable the pfit if
5061 * it's in use. The hw state code will make sure we get this right. */
bfd16b2a 5062 if (force || crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5063 I915_WRITE(PF_CTL(pipe), 0);
5064 I915_WRITE(PF_WIN_POS(pipe), 0);
5065 I915_WRITE(PF_WIN_SZ(pipe), 0);
5066 }
5067}
5068
6be4a607
JB		 5069static void ironlake_crtc_disable(struct drm_crtc *crtc)
5070{
5071 struct drm_device *dev = crtc->dev;
5072 struct drm_i915_private *dev_priv = dev->dev_private;
5073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5074 struct intel_encoder *encoder;
6be4a607 5075 int pipe = intel_crtc->pipe;
5eddb70b 5076 u32 reg, temp;
b52eb4dc 5077
ea9d758d
DV		 5078 for_each_encoder_on_crtc(dev, crtc, encoder)
5079 encoder->disable(encoder);
5080
f9b61ff6
DV		 5081 drm_crtc_vblank_off(crtc);
5082 assert_vblank_disabled(crtc);
5083
6e3c9717 5084 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5085 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5086
575f7ab7 5087 intel_disable_pipe(intel_crtc);
32f9d658 5088
bfd16b2a 5089 ironlake_pfit_disable(intel_crtc, false);
2c07245f 5090
5a74f70a
VS		 5091 if (intel_crtc->config->has_pch_encoder)
5092 ironlake_fdi_disable(crtc);
5093
bf49ec8c
DV		 5094 for_each_encoder_on_crtc(dev, crtc, encoder)
5095 if (encoder->post_disable)
5096 encoder->post_disable(encoder);
2c07245f 5097
6e3c9717 5098 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5099 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5100
d925c59a
DV		 5101 if (HAS_PCH_CPT(dev)) {
5102 /* disable TRANS_DP_CTL */
5103 reg = TRANS_DP_CTL(pipe);
5104 temp = I915_READ(reg);
5105 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5106 TRANS_DP_PORT_SEL_MASK);
5107 temp |= TRANS_DP_PORT_SEL_NONE;
5108 I915_WRITE(reg, temp);
5109
5110 /* disable DPLL_SEL */
5111 temp = I915_READ(PCH_DPLL_SEL);
11887397 5112 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5113 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5114 }
e3421a18 5115
d925c59a
DV		 5116 ironlake_fdi_pll_disable(intel_crtc);
5117 }
e4ca0612
PJ		 5118
5119 intel_crtc->active = false;
5120 intel_update_watermarks(crtc);
6be4a607 5121}
1b3c7a47 5122
4f771f10 5123static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5124{
4f771f10
PZ		 5125 struct drm_device *dev = crtc->dev;
5126 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5128 struct intel_encoder *encoder;
6e3c9717 5129 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5130
8807e55b
JN		 5131 for_each_encoder_on_crtc(dev, crtc, encoder) {
5132 intel_opregion_notify_encoder(encoder, false);
4f771f10 5133 encoder->disable(encoder);
8807e55b 5134 }
4f771f10 5135
f9b61ff6
DV		 5136 drm_crtc_vblank_off(crtc);
5137 assert_vblank_disabled(crtc);
5138
6e3c9717 5139 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5140 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5141 false);
575f7ab7 5142 intel_disable_pipe(intel_crtc);
4f771f10 5143
6e3c9717 5144 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5145 intel_ddi_set_vc_payload_alloc(crtc, false);
5146
ad80a810 5147 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5148
1c132b44 5149 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5150 skylake_scaler_disable(intel_crtc);
ff6d9f55 5151 else
bfd16b2a 5152 ironlake_pfit_disable(intel_crtc, false);
4f771f10 5153
1f544388 5154 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5155
6e3c9717 5156 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5157 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5158 intel_ddi_fdi_disable(crtc);
83616634 5159 }
4f771f10 5160
97b040aa
ID		 5161 for_each_encoder_on_crtc(dev, crtc, encoder)
5162 if (encoder->post_disable)
5163 encoder->post_disable(encoder);
e4ca0612
PJ		 5164
5165 intel_crtc->active = false;
5166 intel_update_watermarks(crtc);
4f771f10
PZ		 5167}
5168
2dd24552
JB		 5169static void i9xx_pfit_enable(struct intel_crtc *crtc)
5170{
5171 struct drm_device *dev = crtc->base.dev;
5172 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5173 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5174
681a8504 5175 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5176 return;
5177
2dd24552 5178 /*
c0b03411
DV		 5179 * The panel fitter should only be adjusted whilst the pipe is disabled,
5180 * according to register description and PRM.
2dd24552 5181 */
c0b03411
DV		 5182 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5183 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5184
b074cec8
JB		 5185 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5186 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5187
5188 /* Border color in case we don't scale up to the full screen. Black by
5189 * default, change to something else for debugging. */
5190 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5191}
5192
d05410f9
DA		 5193static enum intel_display_power_domain port_to_power_domain(enum port port)
5194{
5195 switch (port) {
5196 case PORT_A:
5197 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5198 case PORT_B:
5199 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5200 case PORT_C:
5201 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5202 case PORT_D:
5203 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ		 5204 case PORT_E:
5205 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA		 5206 default:
5207 WARN_ON_ONCE(1);
5208 return POWER_DOMAIN_PORT_OTHER;
5209 }
5210}
5211
77d22dca
ID		 5212#define for_each_power_domain(domain, mask) \
5213 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5214 if ((1 << (domain)) & (mask))
5215
319be8ae
ID		 5216enum intel_display_power_domain
5217intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5218{
5219 struct drm_device *dev = intel_encoder->base.dev;
5220 struct intel_digital_port *intel_dig_port;
5221
5222 switch (intel_encoder->type) {
5223 case INTEL_OUTPUT_UNKNOWN:
5224 /* Only DDI platforms should ever use this output type */
5225 WARN_ON_ONCE(!HAS_DDI(dev));
5226 case INTEL_OUTPUT_DISPLAYPORT:
5227 case INTEL_OUTPUT_HDMI:
5228 case INTEL_OUTPUT_EDP:
5229 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5230 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5231 case INTEL_OUTPUT_DP_MST:
5232 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5233 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5234 case INTEL_OUTPUT_ANALOG:
5235 return POWER_DOMAIN_PORT_CRT;
5236 case INTEL_OUTPUT_DSI:
5237 return POWER_DOMAIN_PORT_DSI;
5238 default:
5239 return POWER_DOMAIN_PORT_OTHER;
5240 }
5241}
5242
5243static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5244{
319be8ae
ID		 5245 struct drm_device *dev = crtc->dev;
5246 struct intel_encoder *intel_encoder;
5247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5248 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5249 unsigned long mask;
5250 enum transcoder transcoder;
5251
292b990e
ML		 5252 if (!crtc->state->active)
5253 return 0;
5254
77d22dca
ID		 5255 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5256
5257 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5258 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5259 if (intel_crtc->config->pch_pfit.enabled ||
5260 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5261 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5262
319be8ae
ID		 5263 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5264 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5265
77d22dca
ID		 5266 return mask;
5267}
5268
292b990e 5269static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5270{
292b990e
ML		 5271 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5273 enum intel_display_power_domain domain;
5274 unsigned long domains, new_domains, old_domains;
77d22dca 5275
292b990e
ML		 5276 old_domains = intel_crtc->enabled_power_domains;
5277 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5278
292b990e
ML		 5279 domains = new_domains & ~old_domains;
5280
5281 for_each_power_domain(domain, domains)
5282 intel_display_power_get(dev_priv, domain);
5283
5284 return old_domains & ~new_domains;
5285}
5286
5287static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5288 unsigned long domains)
5289{
5290 enum intel_display_power_domain domain;
5291
5292 for_each_power_domain(domain, domains)
5293 intel_display_power_put(dev_priv, domain);
5294}
77d22dca 5295
292b990e
ML		 5296static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5297{
5298 struct drm_device *dev = state->dev;
5299 struct drm_i915_private *dev_priv = dev->dev_private;
5300 unsigned long put_domains[I915_MAX_PIPES] = {};
5301 struct drm_crtc_state *crtc_state;
5302 struct drm_crtc *crtc;
5303 int i;
77d22dca 5304
292b990e
ML		 5305 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5306 if (needs_modeset(crtc->state))
5307 put_domains[to_intel_crtc(crtc)->pipe] =
5308 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5309 }
5310
27c329ed
ML		 5311 if (dev_priv->display.modeset_commit_cdclk) {
5312 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5313
5314 if (cdclk != dev_priv->cdclk_freq &&
5315 !WARN_ON(!state->allow_modeset))
5316 dev_priv->display.modeset_commit_cdclk(state);
5317 }
50f6e502 5318
292b990e
ML		 5319 for (i = 0; i < I915_MAX_PIPES; i++)
5320 if (put_domains[i])
5321 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5322}
5323
adafdc6f
MK		 5324static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5325{
5326 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5327
5328 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5329 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5330 return max_cdclk_freq;
5331 else if (IS_CHERRYVIEW(dev_priv))
5332 return max_cdclk_freq*95/100;
5333 else if (INTEL_INFO(dev_priv)->gen < 4)
5334 return 2*max_cdclk_freq*90/100;
5335 else
5336 return max_cdclk_freq*90/100;
5337}
5338
560a7ae4
DL		 5339static void intel_update_max_cdclk(struct drm_device *dev)
5340{
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5342
5343 if (IS_SKYLAKE(dev)) {
5344 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5345
5346 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5347 dev_priv->max_cdclk_freq = 675000;
5348 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5349 dev_priv->max_cdclk_freq = 540000;
5350 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5351 dev_priv->max_cdclk_freq = 450000;
5352 else
5353 dev_priv->max_cdclk_freq = 337500;
5354 } else if (IS_BROADWELL(dev)) {
5355 /*
5356 * FIXME with extra cooling we can allow
5357 * 540 MHz for ULX and 675 Mhz for ULT.
5358 * How can we know if extra cooling is
5359 * available? PCI ID, VTB, something else?
5360 */
5361 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5362 dev_priv->max_cdclk_freq = 450000;
5363 else if (IS_BDW_ULX(dev))
5364 dev_priv->max_cdclk_freq = 450000;
5365 else if (IS_BDW_ULT(dev))
5366 dev_priv->max_cdclk_freq = 540000;
5367 else
5368 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5369 } else if (IS_CHERRYVIEW(dev)) {
5370 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5371 } else if (IS_VALLEYVIEW(dev)) {
5372 dev_priv->max_cdclk_freq = 400000;
5373 } else {
5374 /* otherwise assume cdclk is fixed */
5375 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5376 }
5377
adafdc6f
MK		 5378 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5379
560a7ae4
DL		 5380 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5381 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5382
5383 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5384 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5385}
5386
5387static void intel_update_cdclk(struct drm_device *dev)
5388{
5389 struct drm_i915_private *dev_priv = dev->dev_private;
5390
5391 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5392 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5393 dev_priv->cdclk_freq);
5394
5395 /*
5396 * Program the gmbus_freq based on the cdclk frequency.
5397 * BSpec erroneously claims we should aim for 4MHz, but
5398 * in fact 1MHz is the correct frequency.
5399 */
5400 if (IS_VALLEYVIEW(dev)) {
5401 /*
5402 * Program the gmbus_freq based on the cdclk frequency.
5403 * BSpec erroneously claims we should aim for 4MHz, but
5404 * in fact 1MHz is the correct frequency.
5405 */
5406 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5407 }
5408
5409 if (dev_priv->max_cdclk_freq == 0)
5410 intel_update_max_cdclk(dev);
5411}
5412
70d0c574 5413static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5414{
5415 struct drm_i915_private *dev_priv = dev->dev_private;
5416 uint32_t divider;
5417 uint32_t ratio;
5418 uint32_t current_freq;
5419 int ret;
5420
5421 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5422 switch (frequency) {
5423 case 144000:
5424 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5425 ratio = BXT_DE_PLL_RATIO(60);
5426 break;
5427 case 288000:
5428 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5429 ratio = BXT_DE_PLL_RATIO(60);
5430 break;
5431 case 384000:
5432 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5433 ratio = BXT_DE_PLL_RATIO(60);
5434 break;
5435 case 576000:
5436 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5437 ratio = BXT_DE_PLL_RATIO(60);
5438 break;
5439 case 624000:
5440 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5441 ratio = BXT_DE_PLL_RATIO(65);
5442 break;
5443 case 19200:
5444 /*
5445 * Bypass frequency with DE PLL disabled. Init ratio, divider
5446 * to suppress GCC warning.
5447 */
5448 ratio = 0;
5449 divider = 0;
5450 break;
5451 default:
5452 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5453
5454 return;
5455 }
5456
5457 mutex_lock(&dev_priv->rps.hw_lock);
5458 /* Inform power controller of upcoming frequency change */
5459 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5460 0x80000000);
5461 mutex_unlock(&dev_priv->rps.hw_lock);
5462
5463 if (ret) {
5464 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5465 ret, frequency);
5466 return;
5467 }
5468
5469 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5470 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5471 current_freq = current_freq * 500 + 1000;
5472
5473 /*
5474 * DE PLL has to be disabled when
5475 * - setting to 19.2MHz (bypass, PLL isn't used)
5476 * - before setting to 624MHz (PLL needs toggling)
5477 * - before setting to any frequency from 624MHz (PLL needs toggling)
5478 */
5479 if (frequency == 19200 || frequency == 624000 ||
5480 current_freq == 624000) {
5481 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5482 /* Timeout 200us */
5483 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5484 1))
5485 DRM_ERROR("timout waiting for DE PLL unlock\n");
5486 }
5487
5488 if (frequency != 19200) {
5489 uint32_t val;
5490
5491 val = I915_READ(BXT_DE_PLL_CTL);
5492 val &= ~BXT_DE_PLL_RATIO_MASK;
5493 val |= ratio;
5494 I915_WRITE(BXT_DE_PLL_CTL, val);
5495
5496 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5497 /* Timeout 200us */
5498 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5499 DRM_ERROR("timeout waiting for DE PLL lock\n");
5500
5501 val = I915_READ(CDCLK_CTL);
5502 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5503 val |= divider;
5504 /*
5505 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5506 * enable otherwise.
5507 */
5508 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5509 if (frequency >= 500000)
5510 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5511
5512 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5513 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5514 val |= (frequency - 1000) / 500;
5515 I915_WRITE(CDCLK_CTL, val);
5516 }
5517
5518 mutex_lock(&dev_priv->rps.hw_lock);
5519 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5520 DIV_ROUND_UP(frequency, 25000));
5521 mutex_unlock(&dev_priv->rps.hw_lock);
5522
5523 if (ret) {
5524 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5525 ret, frequency);
5526 return;
5527 }
5528
a47871bd 5529 intel_update_cdclk(dev);
f8437dd1
VK		 5530}
5531
5532void broxton_init_cdclk(struct drm_device *dev)
5533{
5534 struct drm_i915_private *dev_priv = dev->dev_private;
5535 uint32_t val;
5536
5537 /*
5538 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5539 * or else the reset will hang because there is no PCH to respond.
5540 * Move the handshake programming to initialization sequence.
5541 * Previously was left up to BIOS.
5542 */
5543 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5544 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5545 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5546
5547 /* Enable PG1 for cdclk */
5548 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5549
5550 /* check if cd clock is enabled */
5551 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5552 DRM_DEBUG_KMS("Display already initialized\n");
5553 return;
5554 }
5555
5556 /*
5557 * FIXME:
5558 * - The initial CDCLK needs to be read from VBT.
5559 * Need to make this change after VBT has changes for BXT.
5560 * - check if setting the max (or any) cdclk freq is really necessary
5561 * here, it belongs to modeset time
5562 */
5563 broxton_set_cdclk(dev, 624000);
5564
5565 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5566 POSTING_READ(DBUF_CTL);
5567
f8437dd1
VK		 5568 udelay(10);
5569
5570 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5571 DRM_ERROR("DBuf power enable timeout!\n");
5572}
5573
5574void broxton_uninit_cdclk(struct drm_device *dev)
5575{
5576 struct drm_i915_private *dev_priv = dev->dev_private;
5577
5578 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5579 POSTING_READ(DBUF_CTL);
5580
f8437dd1
VK		 5581 udelay(10);
5582
5583 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5584 DRM_ERROR("DBuf power disable timeout!\n");
5585
5586 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5587 broxton_set_cdclk(dev, 19200);
5588
5589 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5590}
5591
5d96d8af
DL		 5592static const struct skl_cdclk_entry {
5593 unsigned int freq;
5594 unsigned int vco;
5595} skl_cdclk_frequencies[] = {
5596 { .freq = 308570, .vco = 8640 },
5597 { .freq = 337500, .vco = 8100 },
5598 { .freq = 432000, .vco = 8640 },
5599 { .freq = 450000, .vco = 8100 },
5600 { .freq = 540000, .vco = 8100 },
5601 { .freq = 617140, .vco = 8640 },
5602 { .freq = 675000, .vco = 8100 },
5603};
5604
5605static unsigned int skl_cdclk_decimal(unsigned int freq)
5606{
5607 return (freq - 1000) / 500;
5608}
5609
5610static unsigned int skl_cdclk_get_vco(unsigned int freq)
5611{
5612 unsigned int i;
5613
5614 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5615 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5616
5617 if (e->freq == freq)
5618 return e->vco;
5619 }
5620
5621 return 8100;
5622}
5623
5624static void
5625skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5626{
5627 unsigned int min_freq;
5628 u32 val;
5629
5630 /* select the minimum CDCLK before enabling DPLL 0 */
5631 val = I915_READ(CDCLK_CTL);
5632 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5633 val |= CDCLK_FREQ_337_308;
5634
5635 if (required_vco == 8640)
5636 min_freq = 308570;
5637 else
5638 min_freq = 337500;
5639
5640 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5641
5642 I915_WRITE(CDCLK_CTL, val);
5643 POSTING_READ(CDCLK_CTL);
5644
5645 /*
5646 * We always enable DPLL0 with the lowest link rate possible, but still
5647 * taking into account the VCO required to operate the eDP panel at the
5648 * desired frequency. The usual DP link rates operate with a VCO of
5649 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5650 * The modeset code is responsible for the selection of the exact link
5651 * rate later on, with the constraint of choosing a frequency that
5652 * works with required_vco.
5653 */
5654 val = I915_READ(DPLL_CTRL1);
5655
5656 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5657 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5658 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5659 if (required_vco == 8640)
5660 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5661 SKL_DPLL0);
5662 else
5663 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5664 SKL_DPLL0);
5665
5666 I915_WRITE(DPLL_CTRL1, val);
5667 POSTING_READ(DPLL_CTRL1);
5668
5669 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5670
5671 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5672 DRM_ERROR("DPLL0 not locked\n");
5673}
5674
5675static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5676{
5677 int ret;
5678 u32 val;
5679
5680 /* inform PCU we want to change CDCLK */
5681 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5682 mutex_lock(&dev_priv->rps.hw_lock);
5683 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5684 mutex_unlock(&dev_priv->rps.hw_lock);
5685
5686 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5687}
5688
5689static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5690{
5691 unsigned int i;
5692
5693 for (i = 0; i < 15; i++) {
5694 if (skl_cdclk_pcu_ready(dev_priv))
5695 return true;
5696 udelay(10);
5697 }
5698
5699 return false;
5700}
5701
5702static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5703{
560a7ae4 5704 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5705 u32 freq_select, pcu_ack;
5706
5707 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5708
5709 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5710 DRM_ERROR("failed to inform PCU about cdclk change\n");
5711 return;
5712 }
5713
5714 /* set CDCLK_CTL */
5715 switch(freq) {
5716 case 450000:
5717 case 432000:
5718 freq_select = CDCLK_FREQ_450_432;
5719 pcu_ack = 1;
5720 break;
5721 case 540000:
5722 freq_select = CDCLK_FREQ_540;
5723 pcu_ack = 2;
5724 break;
5725 case 308570:
5726 case 337500:
5727 default:
5728 freq_select = CDCLK_FREQ_337_308;
5729 pcu_ack = 0;
5730 break;
5731 case 617140:
5732 case 675000:
5733 freq_select = CDCLK_FREQ_675_617;
5734 pcu_ack = 3;
5735 break;
5736 }
5737
5738 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5739 POSTING_READ(CDCLK_CTL);
5740
5741 /* inform PCU of the change */
5742 mutex_lock(&dev_priv->rps.hw_lock);
5743 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5744 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5745
5746 intel_update_cdclk(dev);
5d96d8af
DL		 5747}
5748
5749void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5750{
5751 /* disable DBUF power */
5752 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5753 POSTING_READ(DBUF_CTL);
5754
5755 udelay(10);
5756
5757 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5758 DRM_ERROR("DBuf power disable timeout\n");
5759
4e961e42
AM		 5760 /*
5761 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5762 */
5763 if (dev_priv->csr.dmc_payload) {
5764 /* disable DPLL0 */
5765 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5766 ~LCPLL_PLL_ENABLE);
5767 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5768 DRM_ERROR("Couldn't disable DPLL0\n");
5769 }
5d96d8af
DL		 5770
5771 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5772}
5773
5774void skl_init_cdclk(struct drm_i915_private *dev_priv)
5775{
5776 u32 val;
5777 unsigned int required_vco;
5778
5779 /* enable PCH reset handshake */
5780 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5781 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5782
5783 /* enable PG1 and Misc I/O */
5784 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5785
39d9b85a
GW		 5786 /* DPLL0 not enabled (happens on early BIOS versions) */
5787 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5788 /* enable DPLL0 */
5789 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5790 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5791 }
5792
5d96d8af
DL		 5793 /* set CDCLK to the frequency the BIOS chose */
5794 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5795
5796 /* enable DBUF power */
5797 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5798 POSTING_READ(DBUF_CTL);
5799
5800 udelay(10);
5801
5802 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5803 DRM_ERROR("DBuf power enable timeout\n");
5804}
5805
30a970c6
JB		 5806/* Adjust CDclk dividers to allow high res or save power if possible */
5807static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5808{
5809 struct drm_i915_private *dev_priv = dev->dev_private;
5810 u32 val, cmd;
5811
164dfd28
VK		 5812 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5813 != dev_priv->cdclk_freq);
d60c4473 5814
dfcab17e 5815 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5816 cmd = 2;
dfcab17e 5817 else if (cdclk == 266667)
30a970c6
JB		 5818 cmd = 1;
5819 else
5820 cmd = 0;
5821
5822 mutex_lock(&dev_priv->rps.hw_lock);
5823 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5824 val &= ~DSPFREQGUAR_MASK;
5825 val |= (cmd << DSPFREQGUAR_SHIFT);
5826 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5827 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5828 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5829 50)) {
5830 DRM_ERROR("timed out waiting for CDclk change\n");
5831 }
5832 mutex_unlock(&dev_priv->rps.hw_lock);
5833
54433e91
VS		 5834 mutex_lock(&dev_priv->sb_lock);
5835
dfcab17e 5836 if (cdclk == 400000) {
6bcda4f0 5837 u32 divider;
30a970c6 5838
6bcda4f0 5839 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5840
30a970c6
JB		 5841 /* adjust cdclk divider */
5842 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
87d5d259 5843 val &= ~CCK_FREQUENCY_VALUES;
30a970c6
JB		 5844 val |= divider;
5845 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5846
5847 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
87d5d259 5848 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
a877e801
VS		 5849 50))
5850 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5851 }
5852
30a970c6
JB		 5853 /* adjust self-refresh exit latency value */
5854 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5855 val &= ~0x7f;
5856
5857 /*
5858 * For high bandwidth configs, we set a higher latency in the bunit
5859 * so that the core display fetch happens in time to avoid underruns.
5860 */
dfcab17e 5861 if (cdclk == 400000)
30a970c6
JB		 5862 val |= 4500 / 250; /* 4.5 usec */
5863 else
5864 val |= 3000 / 250; /* 3.0 usec */
5865 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5866
a580516d 5867 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5868
b6283055 5869 intel_update_cdclk(dev);
30a970c6
JB		 5870}
5871
383c5a6a
VS		 5872static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5873{
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5875 u32 val, cmd;
5876
164dfd28
VK		 5877 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5878 != dev_priv->cdclk_freq);
383c5a6a
VS		 5879
5880 switch (cdclk) {
383c5a6a
VS		 5881 case 333333:
5882 case 320000:
383c5a6a 5883 case 266667:
383c5a6a 5884 case 200000:
383c5a6a
VS		 5885 break;
5886 default:
5f77eeb0 5887 MISSING_CASE(cdclk);
383c5a6a
VS		 5888 return;
5889 }
5890
9d0d3fda
VS		 5891 /*
5892 * Specs are full of misinformation, but testing on actual
5893 * hardware has shown that we just need to write the desired
5894 * CCK divider into the Punit register.
5895 */
5896 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5897
383c5a6a
VS		 5898 mutex_lock(&dev_priv->rps.hw_lock);
5899 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5900 val &= ~DSPFREQGUAR_MASK_CHV;
5901 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5902 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5903 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5904 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5905 50)) {
5906 DRM_ERROR("timed out waiting for CDclk change\n");
5907 }
5908 mutex_unlock(&dev_priv->rps.hw_lock);
5909
b6283055 5910 intel_update_cdclk(dev);
383c5a6a
VS		 5911}
5912
30a970c6
JB		 5913static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5914 int max_pixclk)
5915{
6bcda4f0 5916 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5917 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5918
30a970c6
JB		 5919 /*
5920 * Really only a few cases to deal with, as only 4 CDclks are supported:
5921 * 200MHz
5922 * 267MHz
29dc7ef3 5923 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5924 * 400MHz (VLV only)
5925 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5926 * of the lower bin and adjust if needed.
e37c67a1
VS		 5927 *
5928 * We seem to get an unstable or solid color picture at 200MHz.
5929 * Not sure what's wrong. For now use 200MHz only when all pipes
5930 * are off.
30a970c6 5931 */
6cca3195
VS		 5932 if (!IS_CHERRYVIEW(dev_priv) &&
5933 max_pixclk > freq_320*limit/100)
dfcab17e 5934 return 400000;
6cca3195 5935 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5936 return freq_320;
e37c67a1 5937 else if (max_pixclk > 0)
dfcab17e 5938 return 266667;
e37c67a1
VS		 5939 else
5940 return 200000;
30a970c6
JB		 5941}
5942
f8437dd1
VK		 5943static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5944 int max_pixclk)
5945{
5946 /*
5947 * FIXME:
5948 * - remove the guardband, it's not needed on BXT
5949 * - set 19.2MHz bypass frequency if there are no active pipes
5950 */
5951 if (max_pixclk > 576000*9/10)
5952 return 624000;
5953 else if (max_pixclk > 384000*9/10)
5954 return 576000;
5955 else if (max_pixclk > 288000*9/10)
5956 return 384000;
5957 else if (max_pixclk > 144000*9/10)
5958 return 288000;
5959 else
5960 return 144000;
5961}
5962
a821fc46
ACO		 5963/* Compute the max pixel clock for new configuration. Uses atomic state if
5964 * that's non-NULL, look at current state otherwise. */
5965static int intel_mode_max_pixclk(struct drm_device *dev,
5966 struct drm_atomic_state *state)
30a970c6 5967{
30a970c6 5968 struct intel_crtc *intel_crtc;
304603f4 5969 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5970 int max_pixclk = 0;
5971
d3fcc808 5972 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5973 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5974 if (IS_ERR(crtc_state))
5975 return PTR_ERR(crtc_state);
5976
5977 if (!crtc_state->base.enable)
5978 continue;
5979
5980 max_pixclk = max(max_pixclk,
5981 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5982 }
5983
5984 return max_pixclk;
5985}
5986
27c329ed 5987static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5988{
27c329ed
ML		 5989 struct drm_device *dev = state->dev;
5990 struct drm_i915_private *dev_priv = dev->dev_private;
5991 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5992
304603f4
ACO		 5993 if (max_pixclk < 0)
5994 return max_pixclk;
30a970c6 5995
27c329ed
ML		 5996 to_intel_atomic_state(state)->cdclk =
5997 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5998
27c329ed
ML		 5999 return 0;
6000}
304603f4 6001
27c329ed
ML		 6002static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6003{
6004 struct drm_device *dev = state->dev;
6005 struct drm_i915_private *dev_priv = dev->dev_private;
6006 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 6007
27c329ed
ML		 6008 if (max_pixclk < 0)
6009 return max_pixclk;
85a96e7a 6010
27c329ed
ML		 6011 to_intel_atomic_state(state)->cdclk =
6012 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 6013
27c329ed 6014 return 0;
30a970c6
JB		 6015}
6016
1e69cd74
VS		 6017static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6018{
6019 unsigned int credits, default_credits;
6020
6021 if (IS_CHERRYVIEW(dev_priv))
6022 default_credits = PFI_CREDIT(12);
6023 else
6024 default_credits = PFI_CREDIT(8);
6025
bfa7df01 6026 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
1e69cd74
VS		 6027 /* CHV suggested value is 31 or 63 */
6028 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 6029 credits = PFI_CREDIT_63;
1e69cd74
VS		 6030 else
6031 credits = PFI_CREDIT(15);
6032 } else {
6033 credits = default_credits;
6034 }
6035
6036 /*
6037 * WA - write default credits before re-programming
6038 * FIXME: should we also set the resend bit here?
6039 */
6040 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6041 default_credits);
6042
6043 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6044 credits | PFI_CREDIT_RESEND);
6045
6046 /*
6047 * FIXME is this guaranteed to clear
6048 * immediately or should we poll for it?
6049 */
6050 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6051}
6052
27c329ed 6053static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 6054{
a821fc46 6055 struct drm_device *dev = old_state->dev;
27c329ed 6056 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 6057 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 6058
27c329ed
ML		 6059 /*
6060 * FIXME: We can end up here with all power domains off, yet
6061 * with a CDCLK frequency other than the minimum. To account
6062 * for this take the PIPE-A power domain, which covers the HW
6063 * blocks needed for the following programming. This can be
6064 * removed once it's guaranteed that we get here either with
6065 * the minimum CDCLK set, or the required power domains
6066 * enabled.
6067 */
6068 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6069
27c329ed
ML		 6070 if (IS_CHERRYVIEW(dev))
6071 cherryview_set_cdclk(dev, req_cdclk);
6072 else
6073 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6074
27c329ed 6075 vlv_program_pfi_credits(dev_priv);
1e69cd74 6076
27c329ed 6077 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6078}
6079
89b667f8
JB		 6080static void valleyview_crtc_enable(struct drm_crtc *crtc)
6081{
6082 struct drm_device *dev = crtc->dev;
a72e4c9f 6083 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6085 struct intel_encoder *encoder;
6086 int pipe = intel_crtc->pipe;
23538ef1 6087 bool is_dsi;
89b667f8 6088
53d9f4e9 6089 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6090 return;
6091
409ee761 6092 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6093
6e3c9717 6094 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6095 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6096
6097 intel_set_pipe_timings(intel_crtc);
6098
c14b0485
VS		 6099 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6100 struct drm_i915_private *dev_priv = dev->dev_private;
6101
6102 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6103 I915_WRITE(CHV_CANVAS(pipe), 0);
6104 }
6105
5b18e57c
DV		 6106 i9xx_set_pipeconf(intel_crtc);
6107
89b667f8 6108 intel_crtc->active = true;
89b667f8 6109
a72e4c9f 6110 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6111
89b667f8
JB		 6112 for_each_encoder_on_crtc(dev, crtc, encoder)
6113 if (encoder->pre_pll_enable)
6114 encoder->pre_pll_enable(encoder);
6115
9d556c99 6116 if (!is_dsi) {
c0b4c660
VS		 6117 if (IS_CHERRYVIEW(dev)) {
6118 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6119 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6120 } else {
6121 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6122 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6123 }
9d556c99 6124 }
89b667f8
JB		 6125
6126 for_each_encoder_on_crtc(dev, crtc, encoder)
6127 if (encoder->pre_enable)
6128 encoder->pre_enable(encoder);
6129
2dd24552
JB		 6130 i9xx_pfit_enable(intel_crtc);
6131
63cbb074
VS		 6132 intel_crtc_load_lut(crtc);
6133
e1fdc473 6134 intel_enable_pipe(intel_crtc);
be6a6f8e 6135
4b3a9526
VS		 6136 assert_vblank_disabled(crtc);
6137 drm_crtc_vblank_on(crtc);
6138
f9b61ff6
DV		 6139 for_each_encoder_on_crtc(dev, crtc, encoder)
6140 encoder->enable(encoder);
89b667f8
JB		 6141}
6142
f13c2ef3
DV		 6143static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6144{
6145 struct drm_device *dev = crtc->base.dev;
6146 struct drm_i915_private *dev_priv = dev->dev_private;
6147
6e3c9717
ACO		 6148 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6149 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6150}
6151
0b8765c6 6152static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6153{
6154 struct drm_device *dev = crtc->dev;
a72e4c9f 6155 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6157 struct intel_encoder *encoder;
79e53945 6158 int pipe = intel_crtc->pipe;
79e53945 6159
53d9f4e9 6160 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6161 return;
6162
f13c2ef3
DV		 6163 i9xx_set_pll_dividers(intel_crtc);
6164
6e3c9717 6165 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6166 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6167
6168 intel_set_pipe_timings(intel_crtc);
6169
5b18e57c
DV		 6170 i9xx_set_pipeconf(intel_crtc);
6171
f7abfe8b 6172 intel_crtc->active = true;
6b383a7f 6173
4a3436e8 6174 if (!IS_GEN2(dev))
a72e4c9f 6175 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6176
9d6d9f19
MK		 6177 for_each_encoder_on_crtc(dev, crtc, encoder)
6178 if (encoder->pre_enable)
6179 encoder->pre_enable(encoder);
6180
f6736a1a
DV		 6181 i9xx_enable_pll(intel_crtc);
6182
2dd24552
JB		 6183 i9xx_pfit_enable(intel_crtc);
6184
63cbb074
VS		 6185 intel_crtc_load_lut(crtc);
6186
f37fcc2a 6187 intel_update_watermarks(crtc);
e1fdc473 6188 intel_enable_pipe(intel_crtc);
be6a6f8e 6189
4b3a9526
VS		 6190 assert_vblank_disabled(crtc);
6191 drm_crtc_vblank_on(crtc);
6192
f9b61ff6
DV		 6193 for_each_encoder_on_crtc(dev, crtc, encoder)
6194 encoder->enable(encoder);
0b8765c6 6195}
79e53945 6196
87476d63
DV		 6197static void i9xx_pfit_disable(struct intel_crtc *crtc)
6198{
6199 struct drm_device *dev = crtc->base.dev;
6200 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6201
6e3c9717 6202 if (!crtc->config->gmch_pfit.control)
328d8e82 6203 return;
87476d63 6204
328d8e82 6205 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6206
328d8e82
DV		 6207 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6208 I915_READ(PFIT_CONTROL));
6209 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6210}
6211
0b8765c6
JB		 6212static void i9xx_crtc_disable(struct drm_crtc *crtc)
6213{
6214 struct drm_device *dev = crtc->dev;
6215 struct drm_i915_private *dev_priv = dev->dev_private;
6216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6217 struct intel_encoder *encoder;
0b8765c6 6218 int pipe = intel_crtc->pipe;
ef9c3aee 6219
6304cd91
VS		 6220 /*
6221 * On gen2 planes are double buffered but the pipe isn't, so we must
6222 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6223 * We also need to wait on all gmch platforms because of the
6224 * self-refresh mode constraint explained above.
6304cd91 6225 */
564ed191 6226 intel_wait_for_vblank(dev, pipe);
6304cd91 6227
4b3a9526
VS		 6228 for_each_encoder_on_crtc(dev, crtc, encoder)
6229 encoder->disable(encoder);
6230
f9b61ff6
DV		 6231 drm_crtc_vblank_off(crtc);
6232 assert_vblank_disabled(crtc);
6233
575f7ab7 6234 intel_disable_pipe(intel_crtc);
24a1f16d 6235
87476d63 6236 i9xx_pfit_disable(intel_crtc);
24a1f16d 6237
89b667f8
JB		 6238 for_each_encoder_on_crtc(dev, crtc, encoder)
6239 if (encoder->post_disable)
6240 encoder->post_disable(encoder);
6241
409ee761 6242 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6243 if (IS_CHERRYVIEW(dev))
6244 chv_disable_pll(dev_priv, pipe);
6245 else if (IS_VALLEYVIEW(dev))
6246 vlv_disable_pll(dev_priv, pipe);
6247 else
1c4e0274 6248 i9xx_disable_pll(intel_crtc);
076ed3b2 6249 }
0b8765c6 6250
d6db995f
VS		 6251 for_each_encoder_on_crtc(dev, crtc, encoder)
6252 if (encoder->post_pll_disable)
6253 encoder->post_pll_disable(encoder);
6254
4a3436e8 6255 if (!IS_GEN2(dev))
a72e4c9f 6256 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ		 6257
6258 intel_crtc->active = false;
6259 intel_update_watermarks(crtc);
0b8765c6
JB		 6260}
6261
b17d48e2
ML		 6262static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6263{
6264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6265 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6266 enum intel_display_power_domain domain;
6267 unsigned long domains;
6268
6269 if (!intel_crtc->active)
6270 return;
6271
a539205a
ML		 6272 if (to_intel_plane_state(crtc->primary->state)->visible) {
6273 intel_crtc_wait_for_pending_flips(crtc);
6274 intel_pre_disable_primary(crtc);
6275 }
6276
d032ffa0 6277 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6278 dev_priv->display.crtc_disable(crtc);
1f7457b1 6279 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6280
6281 domains = intel_crtc->enabled_power_domains;
6282 for_each_power_domain(domain, domains)
6283 intel_display_power_put(dev_priv, domain);
6284 intel_crtc->enabled_power_domains = 0;
6285}
6286
6b72d486
ML		 6287/*
6288 * turn all crtc's off, but do not adjust state
6289 * This has to be paired with a call to intel_modeset_setup_hw_state.
6290 */
70e0bd74 6291int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6292{
70e0bd74
ML		 6293 struct drm_mode_config *config = &dev->mode_config;
6294 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6295 struct drm_atomic_state *state;
6b72d486 6296 struct drm_crtc *crtc;
70e0bd74
ML		 6297 unsigned crtc_mask = 0;
6298 int ret = 0;
6299
6300 if (WARN_ON(!ctx))
6301 return 0;
6302
6303 lockdep_assert_held(&ctx->ww_ctx);
6304 state = drm_atomic_state_alloc(dev);
6305 if (WARN_ON(!state))
6306 return -ENOMEM;
6307
6308 state->acquire_ctx = ctx;
6309 state->allow_modeset = true;
6310
6311 for_each_crtc(dev, crtc) {
6312 struct drm_crtc_state *crtc_state =
6313 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6314
70e0bd74
ML		 6315 ret = PTR_ERR_OR_ZERO(crtc_state);
6316 if (ret)
6317 goto free;
6318
6319 if (!crtc_state->active)
6320 continue;
6321
6322 crtc_state->active = false;
6323 crtc_mask |= 1 << drm_crtc_index(crtc);
6324 }
6325
6326 if (crtc_mask) {
74c090b1 6327 ret = drm_atomic_commit(state);
70e0bd74
ML		 6328
6329 if (!ret) {
6330 for_each_crtc(dev, crtc)
6331 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6332 crtc->state->active = true;
6333
6334 return ret;
6335 }
6336 }
6337
6338free:
6339 if (ret)
6340 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6341 drm_atomic_state_free(state);
6342 return ret;
ee7b9f93
JB		 6343}
6344
ea5b213a 6345void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6346{
4ef69c7a 6347 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6348
ea5b213a
CW		 6349 drm_encoder_cleanup(encoder);
6350 kfree(intel_encoder);
7e7d76c3
JB		 6351}
6352
0a91ca29
DV		 6353/* Cross check the actual hw state with our own modeset state tracking (and it's
6354 * internal consistency). */
b980514c 6355static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6356{
35dd3c64
ML		 6357 struct drm_crtc *crtc = connector->base.state->crtc;
6358
6359 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6360 connector->base.base.id,
6361 connector->base.name);
6362
0a91ca29 6363 if (connector->get_hw_state(connector)) {
e85376cb 6364 struct intel_encoder *encoder = connector->encoder;
35dd3c64 6365 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6366
35dd3c64
ML		 6367 I915_STATE_WARN(!crtc,
6368 "connector enabled without attached crtc\n");
0a91ca29 6369
35dd3c64
ML		 6370 if (!crtc)
6371 return;
6372
6373 I915_STATE_WARN(!crtc->state->active,
6374 "connector is active, but attached crtc isn't\n");
6375
e85376cb 6376 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
35dd3c64
ML		 6377 return;
6378
e85376cb 6379 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
35dd3c64
ML		 6380 "atomic encoder doesn't match attached encoder\n");
6381
e85376cb 6382 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
35dd3c64
ML		 6383 "attached encoder crtc differs from connector crtc\n");
6384 } else {
4d688a2a
ML		 6385 I915_STATE_WARN(crtc && crtc->state->active,
6386 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6387 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6388 "best encoder set without crtc!\n");
0a91ca29 6389 }
79e53945
JB		 6390}
6391
08d9bc92
ACO		 6392int intel_connector_init(struct intel_connector *connector)
6393{
6394 struct drm_connector_state *connector_state;
6395
6396 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6397 if (!connector_state)
6398 return -ENOMEM;
6399
6400 connector->base.state = connector_state;
6401 return 0;
6402}
6403
6404struct intel_connector *intel_connector_alloc(void)
6405{
6406 struct intel_connector *connector;
6407
6408 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6409 if (!connector)
6410 return NULL;
6411
6412 if (intel_connector_init(connector) < 0) {
6413 kfree(connector);
6414 return NULL;
6415 }
6416
6417 return connector;
6418}
6419
f0947c37
DV		 6420/* Simple connector->get_hw_state implementation for encoders that support only
6421 * one connector and no cloning and hence the encoder state determines the state
6422 * of the connector. */
6423bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6424{
24929352 6425 enum pipe pipe = 0;
f0947c37 6426 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6427
f0947c37 6428 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6429}
6430
6d293983 6431static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6432{
6d293983
ACO		 6433 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6434 return crtc_state->fdi_lanes;
d272ddfa
VS		 6435
6436 return 0;
6437}
6438
6d293983 6439static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6440 struct intel_crtc_state *pipe_config)
1857e1da 6441{
6d293983
ACO		 6442 struct drm_atomic_state *state = pipe_config->base.state;
6443 struct intel_crtc *other_crtc;
6444 struct intel_crtc_state *other_crtc_state;
6445
1857e1da
DV		 6446 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6447 pipe_name(pipe), pipe_config->fdi_lanes);
6448 if (pipe_config->fdi_lanes > 4) {
6449 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6450 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6451 return -EINVAL;
1857e1da
DV		 6452 }
6453
bafb6553 6454 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6455 if (pipe_config->fdi_lanes > 2) {
6456 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6457 pipe_config->fdi_lanes);
6d293983 6458 return -EINVAL;
1857e1da 6459 } else {
6d293983 6460 return 0;
1857e1da
DV		 6461 }
6462 }
6463
6464 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6465 return 0;
1857e1da
DV		 6466
6467 /* Ivybridge 3 pipe is really complicated */
6468 switch (pipe) {
6469 case PIPE_A:
6d293983 6470 return 0;
1857e1da 6471 case PIPE_B:
6d293983
ACO		 6472 if (pipe_config->fdi_lanes <= 2)
6473 return 0;
6474
6475 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6476 other_crtc_state =
6477 intel_atomic_get_crtc_state(state, other_crtc);
6478 if (IS_ERR(other_crtc_state))
6479 return PTR_ERR(other_crtc_state);
6480
6481 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6482 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6483 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6484 return -EINVAL;
1857e1da 6485 }
6d293983 6486 return 0;
1857e1da 6487 case PIPE_C:
251cc67c
VS		 6488 if (pipe_config->fdi_lanes > 2) {
6489 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6490 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6491 return -EINVAL;
251cc67c 6492 }
6d293983
ACO		 6493
6494 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6495 other_crtc_state =
6496 intel_atomic_get_crtc_state(state, other_crtc);
6497 if (IS_ERR(other_crtc_state))
6498 return PTR_ERR(other_crtc_state);
6499
6500 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6501 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6502 return -EINVAL;
1857e1da 6503 }
6d293983 6504 return 0;
1857e1da
DV		 6505 default:
6506 BUG();
6507 }
6508}
6509
e29c22c0
DV		 6510#define RETRY 1
6511static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6512 struct intel_crtc_state *pipe_config)
877d48d5 6513{
1857e1da 6514 struct drm_device *dev = intel_crtc->base.dev;
7c5f93b0 6515 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6516 int lane, link_bw, fdi_dotclock, ret;
6517 bool needs_recompute = false;
877d48d5 6518
e29c22c0 6519retry:
877d48d5
DV		 6520 /* FDI is a binary signal running at ~2.7GHz, encoding
6521 * each output octet as 10 bits. The actual frequency
6522 * is stored as a divider into a 100MHz clock, and the
6523 * mode pixel clock is stored in units of 1KHz.
6524 * Hence the bw of each lane in terms of the mode signal
6525 * is:
6526 */
6527 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6528
241bfc38 6529 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6530
2bd89a07 6531 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6532 pipe_config->pipe_bpp);
6533
6534 pipe_config->fdi_lanes = lane;
6535
2bd89a07 6536 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6537 link_bw, &pipe_config->fdi_m_n);
1857e1da 6538
6d293983
ACO		 6539 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6540 intel_crtc->pipe, pipe_config);
6541 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6542 pipe_config->pipe_bpp -= 2*3;
6543 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6544 pipe_config->pipe_bpp);
6545 needs_recompute = true;
6546 pipe_config->bw_constrained = true;
6547
6548 goto retry;
6549 }
6550
6551 if (needs_recompute)
6552 return RETRY;
6553
6d293983 6554 return ret;
877d48d5
DV		 6555}
6556
8cfb3407
VS		 6557static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6558 struct intel_crtc_state *pipe_config)
6559{
6560 if (pipe_config->pipe_bpp > 24)
6561 return false;
6562
6563 /* HSW can handle pixel rate up to cdclk? */
6564 if (IS_HASWELL(dev_priv->dev))
6565 return true;
6566
6567 /*
b432e5cf
VS		 6568 * We compare against max which means we must take
6569 * the increased cdclk requirement into account when
6570 * calculating the new cdclk.
6571 *
6572 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6573 */
6574 return ilk_pipe_pixel_rate(pipe_config) <=
6575 dev_priv->max_cdclk_freq * 95 / 100;
6576}
6577
42db64ef 6578static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6579 struct intel_crtc_state *pipe_config)
42db64ef 6580{
8cfb3407
VS		 6581 struct drm_device *dev = crtc->base.dev;
6582 struct drm_i915_private *dev_priv = dev->dev_private;
6583
d330a953 6584 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6585 hsw_crtc_supports_ips(crtc) &&
6586 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6587}
6588
a43f6e0f 6589static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6590 struct intel_crtc_state *pipe_config)
79e53945 6591{
a43f6e0f 6592 struct drm_device *dev = crtc->base.dev;
8bd31e67 6593 struct drm_i915_private *dev_priv = dev->dev_private;
7c5f93b0 6594 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6595
ad3a4479 6596 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6597 if (INTEL_INFO(dev)->gen < 4) {
44913155 6598 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6599
6600 /*
6601 * Enable pixel doubling when the dot clock
6602 * is > 90% of the (display) core speed.
6603 *
b397c96b
VS		 6604 * GDG double wide on either pipe,
6605 * otherwise pipe A only.
cf532bb2 6606 */
b397c96b 6607 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6608 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6609 clock_limit *= 2;
cf532bb2 6610 pipe_config->double_wide = true;
ad3a4479
VS		 6611 }
6612
241bfc38 6613 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6614 return -EINVAL;
2c07245f 6615 }
89749350 6616
1d1d0e27
VS		 6617 /*
6618 * Pipe horizontal size must be even in:
6619 * - DVO ganged mode
6620 * - LVDS dual channel mode
6621 * - Double wide pipe
6622 */
a93e255f 6623 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6624 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6625 pipe_config->pipe_src_w &= ~1;
6626
8693a824
DL		 6627 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6628 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6629 */
6630 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
aad941d5 6631 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
e29c22c0 6632 return -EINVAL;
44f46b42 6633
f5adf94e 6634 if (HAS_IPS(dev))
a43f6e0f
DV		 6635 hsw_compute_ips_config(crtc, pipe_config);
6636
877d48d5 6637 if (pipe_config->has_pch_encoder)
a43f6e0f 6638 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6639
cf5a15be 6640 return 0;
79e53945
JB		 6641}
6642
1652d19e
VS		 6643static int skylake_get_display_clock_speed(struct drm_device *dev)
6644{
6645 struct drm_i915_private *dev_priv = to_i915(dev);
6646 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6647 uint32_t cdctl = I915_READ(CDCLK_CTL);
6648 uint32_t linkrate;
6649
414355a7 6650 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6651 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6652
6653 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6654 return 540000;
6655
6656 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6657 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6658
71cd8423
DL		 6659 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6660 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6661 /* vco 8640 */
6662 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6663 case CDCLK_FREQ_450_432:
6664 return 432000;
6665 case CDCLK_FREQ_337_308:
6666 return 308570;
6667 case CDCLK_FREQ_675_617:
6668 return 617140;
6669 default:
6670 WARN(1, "Unknown cd freq selection\n");
6671 }
6672 } else {
6673 /* vco 8100 */
6674 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6675 case CDCLK_FREQ_450_432:
6676 return 450000;
6677 case CDCLK_FREQ_337_308:
6678 return 337500;
6679 case CDCLK_FREQ_675_617:
6680 return 675000;
6681 default:
6682 WARN(1, "Unknown cd freq selection\n");
6683 }
6684 }
6685
6686 /* error case, do as if DPLL0 isn't enabled */
6687 return 24000;
6688}
6689
acd3f3d3
BP		 6690static int broxton_get_display_clock_speed(struct drm_device *dev)
6691{
6692 struct drm_i915_private *dev_priv = to_i915(dev);
6693 uint32_t cdctl = I915_READ(CDCLK_CTL);
6694 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6695 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6696 int cdclk;
6697
6698 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6699 return 19200;
6700
6701 cdclk = 19200 * pll_ratio / 2;
6702
6703 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6704 case BXT_CDCLK_CD2X_DIV_SEL_1:
6705 return cdclk; /* 576MHz or 624MHz */
6706 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6707 return cdclk * 2 / 3; /* 384MHz */
6708 case BXT_CDCLK_CD2X_DIV_SEL_2:
6709 return cdclk / 2; /* 288MHz */
6710 case BXT_CDCLK_CD2X_DIV_SEL_4:
6711 return cdclk / 4; /* 144MHz */
6712 }
6713
6714 /* error case, do as if DE PLL isn't enabled */
6715 return 19200;
6716}
6717
1652d19e
VS		 6718static int broadwell_get_display_clock_speed(struct drm_device *dev)
6719{
6720 struct drm_i915_private *dev_priv = dev->dev_private;
6721 uint32_t lcpll = I915_READ(LCPLL_CTL);
6722 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6723
6724 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6725 return 800000;
6726 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6727 return 450000;
6728 else if (freq == LCPLL_CLK_FREQ_450)
6729 return 450000;
6730 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6731 return 540000;
6732 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6733 return 337500;
6734 else
6735 return 675000;
6736}
6737
6738static int haswell_get_display_clock_speed(struct drm_device *dev)
6739{
6740 struct drm_i915_private *dev_priv = dev->dev_private;
6741 uint32_t lcpll = I915_READ(LCPLL_CTL);
6742 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6743
6744 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6745 return 800000;
6746 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6747 return 450000;
6748 else if (freq == LCPLL_CLK_FREQ_450)
6749 return 450000;
6750 else if (IS_HSW_ULT(dev))
6751 return 337500;
6752 else
6753 return 540000;
79e53945
JB		 6754}
6755
25eb05fc
JB		 6756static int valleyview_get_display_clock_speed(struct drm_device *dev)
6757{
bfa7df01
VS		 6758 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6759 CCK_DISPLAY_CLOCK_CONTROL);
25eb05fc
JB		 6760}
6761
b37a6434
VS		 6762static int ilk_get_display_clock_speed(struct drm_device *dev)
6763{
6764 return 450000;
6765}
6766
e70236a8
JB		 6767static int i945_get_display_clock_speed(struct drm_device *dev)
6768{
6769 return 400000;
6770}
79e53945 6771
e70236a8 6772static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6773{
e907f170 6774 return 333333;
e70236a8 6775}
79e53945 6776
e70236a8
JB		 6777static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6778{
6779 return 200000;
6780}
79e53945 6781
257a7ffc
DV		 6782static int pnv_get_display_clock_speed(struct drm_device *dev)
6783{
6784 u16 gcfgc = 0;
6785
6786 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6787
6788 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6789 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6790 return 266667;
257a7ffc 6791 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6792 return 333333;
257a7ffc 6793 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6794 return 444444;
257a7ffc
DV		 6795 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6796 return 200000;
6797 default:
6798 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6799 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6800 return 133333;
257a7ffc 6801 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6802 return 166667;
257a7ffc
DV		 6803 }
6804}
6805
e70236a8
JB		 6806static int i915gm_get_display_clock_speed(struct drm_device *dev)
6807{
6808 u16 gcfgc = 0;
79e53945 6809
e70236a8
JB		 6810 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6811
6812 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6813 return 133333;
e70236a8
JB		 6814 else {
6815 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6816 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6817 return 333333;
e70236a8
JB		 6818 default:
6819 case GC_DISPLAY_CLOCK_190_200_MHZ:
6820 return 190000;
79e53945 6821 }
e70236a8
JB		 6822 }
6823}
6824
6825static int i865_get_display_clock_speed(struct drm_device *dev)
6826{
e907f170 6827 return 266667;
e70236a8
JB		 6828}
6829
1b1d2716 6830static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6831{
6832 u16 hpllcc = 0;
1b1d2716 6833
65cd2b3f
VS		 6834 /*
6835 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6836 * encoding is different :(
6837 * FIXME is this the right way to detect 852GM/852GMV?
6838 */
6839 if (dev->pdev->revision == 0x1)
6840 return 133333;
6841
1b1d2716
VS		 6842 pci_bus_read_config_word(dev->pdev->bus,
6843 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6844
e70236a8
JB		 6845 /* Assume that the hardware is in the high speed state. This
6846 * should be the default.
6847 */
6848 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6849 case GC_CLOCK_133_200:
1b1d2716 6850 case GC_CLOCK_133_200_2:
e70236a8
JB		 6851 case GC_CLOCK_100_200:
6852 return 200000;
6853 case GC_CLOCK_166_250:
6854 return 250000;
6855 case GC_CLOCK_100_133:
e907f170 6856 return 133333;
1b1d2716
VS		 6857 case GC_CLOCK_133_266:
6858 case GC_CLOCK_133_266_2:
6859 case GC_CLOCK_166_266:
6860 return 266667;
e70236a8 6861 }
79e53945 6862
e70236a8
JB		 6863 /* Shouldn't happen */
6864 return 0;
6865}
79e53945 6866
e70236a8
JB		 6867static int i830_get_display_clock_speed(struct drm_device *dev)
6868{
e907f170 6869 return 133333;
79e53945
JB		 6870}
6871
34edce2f
VS		 6872static unsigned int intel_hpll_vco(struct drm_device *dev)
6873{
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875 static const unsigned int blb_vco[8] = {
6876 [0] = 3200000,
6877 [1] = 4000000,
6878 [2] = 5333333,
6879 [3] = 4800000,
6880 [4] = 6400000,
6881 };
6882 static const unsigned int pnv_vco[8] = {
6883 [0] = 3200000,
6884 [1] = 4000000,
6885 [2] = 5333333,
6886 [3] = 4800000,
6887 [4] = 2666667,
6888 };
6889 static const unsigned int cl_vco[8] = {
6890 [0] = 3200000,
6891 [1] = 4000000,
6892 [2] = 5333333,
6893 [3] = 6400000,
6894 [4] = 3333333,
6895 [5] = 3566667,
6896 [6] = 4266667,
6897 };
6898 static const unsigned int elk_vco[8] = {
6899 [0] = 3200000,
6900 [1] = 4000000,
6901 [2] = 5333333,
6902 [3] = 4800000,
6903 };
6904 static const unsigned int ctg_vco[8] = {
6905 [0] = 3200000,
6906 [1] = 4000000,
6907 [2] = 5333333,
6908 [3] = 6400000,
6909 [4] = 2666667,
6910 [5] = 4266667,
6911 };
6912 const unsigned int *vco_table;
6913 unsigned int vco;
6914 uint8_t tmp = 0;
6915
6916 /* FIXME other chipsets? */
6917 if (IS_GM45(dev))
6918 vco_table = ctg_vco;
6919 else if (IS_G4X(dev))
6920 vco_table = elk_vco;
6921 else if (IS_CRESTLINE(dev))
6922 vco_table = cl_vco;
6923 else if (IS_PINEVIEW(dev))
6924 vco_table = pnv_vco;
6925 else if (IS_G33(dev))
6926 vco_table = blb_vco;
6927 else
6928 return 0;
6929
6930 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6931
6932 vco = vco_table[tmp & 0x7];
6933 if (vco == 0)
6934 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6935 else
6936 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6937
6938 return vco;
6939}
6940
6941static int gm45_get_display_clock_speed(struct drm_device *dev)
6942{
6943 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6944 uint16_t tmp = 0;
6945
6946 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6947
6948 cdclk_sel = (tmp >> 12) & 0x1;
6949
6950 switch (vco) {
6951 case 2666667:
6952 case 4000000:
6953 case 5333333:
6954 return cdclk_sel ? 333333 : 222222;
6955 case 3200000:
6956 return cdclk_sel ? 320000 : 228571;
6957 default:
6958 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6959 return 222222;
6960 }
6961}
6962
6963static int i965gm_get_display_clock_speed(struct drm_device *dev)
6964{
6965 static const uint8_t div_3200[] = { 16, 10, 8 };
6966 static const uint8_t div_4000[] = { 20, 12, 10 };
6967 static const uint8_t div_5333[] = { 24, 16, 14 };
6968 const uint8_t *div_table;
6969 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6970 uint16_t tmp = 0;
6971
6972 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6973
6974 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6975
6976 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6977 goto fail;
6978
6979 switch (vco) {
6980 case 3200000:
6981 div_table = div_3200;
6982 break;
6983 case 4000000:
6984 div_table = div_4000;
6985 break;
6986 case 5333333:
6987 div_table = div_5333;
6988 break;
6989 default:
6990 goto fail;
6991 }
6992
6993 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6994
caf4e252 6995fail:
34edce2f
VS		 6996 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6997 return 200000;
6998}
6999
7000static int g33_get_display_clock_speed(struct drm_device *dev)
7001{
7002 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7003 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7004 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7005 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7006 const uint8_t *div_table;
7007 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7008 uint16_t tmp = 0;
7009
7010 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7011
7012 cdclk_sel = (tmp >> 4) & 0x7;
7013
7014 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7015 goto fail;
7016
7017 switch (vco) {
7018 case 3200000:
7019 div_table = div_3200;
7020 break;
7021 case 4000000:
7022 div_table = div_4000;
7023 break;
7024 case 4800000:
7025 div_table = div_4800;
7026 break;
7027 case 5333333:
7028 div_table = div_5333;
7029 break;
7030 default:
7031 goto fail;
7032 }
7033
7034 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7035
caf4e252 7036fail:
34edce2f
VS		 7037 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7038 return 190476;
7039}
7040
2c07245f 7041static void
a65851af 7042intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7043{
a65851af
VS		 7044 while (*num > DATA_LINK_M_N_MASK ||
7045 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7046 *num >>= 1;
7047 *den >>= 1;
7048 }
7049}
7050
a65851af
VS		 7051static void compute_m_n(unsigned int m, unsigned int n,
7052 uint32_t *ret_m, uint32_t *ret_n)
7053{
7054 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7055 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7056 intel_reduce_m_n_ratio(ret_m, ret_n);
7057}
7058
e69d0bc1
DV		 7059void
7060intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7061 int pixel_clock, int link_clock,
7062 struct intel_link_m_n *m_n)
2c07245f 7063{
e69d0bc1 7064 m_n->tu = 64;
a65851af
VS		 7065
7066 compute_m_n(bits_per_pixel * pixel_clock,
7067 link_clock * nlanes * 8,
7068 &m_n->gmch_m, &m_n->gmch_n);
7069
7070 compute_m_n(pixel_clock, link_clock,
7071 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7072}
7073
a7615030
CW		 7074static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7075{
d330a953
JN		 7076 if (i915.panel_use_ssc >= 0)
7077 return i915.panel_use_ssc != 0;
41aa3448 7078 return dev_priv->vbt.lvds_use_ssc
435793df 7079 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7080}
7081
a93e255f
ACO		 7082static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7083 int num_connectors)
c65d77d8 7084{
a93e255f 7085 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7086 struct drm_i915_private *dev_priv = dev->dev_private;
7087 int refclk;
7088
a93e255f
ACO		 7089 WARN_ON(!crtc_state->base.state);
7090
5ab7b0b7 7091 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7092 refclk = 100000;
a93e255f 7093 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7094 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7095 refclk = dev_priv->vbt.lvds_ssc_freq;
7096 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7097 } else if (!IS_GEN2(dev)) {
7098 refclk = 96000;
7099 } else {
7100 refclk = 48000;
7101 }
7102
7103 return refclk;
7104}
7105
7429e9d4 7106static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7107{
7df00d7a 7108 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7109}
f47709a9 7110
7429e9d4
DV		 7111static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7112{
7113 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7114}
7115
f47709a9 7116static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7117 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7118 intel_clock_t *reduced_clock)
7119{
f47709a9 7120 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7121 u32 fp, fp2 = 0;
7122
7123 if (IS_PINEVIEW(dev)) {
190f68c5 7124 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7125 if (reduced_clock)
7429e9d4 7126 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7127 } else {
190f68c5 7128 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7129 if (reduced_clock)
7429e9d4 7130 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7131 }
7132
190f68c5 7133 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7134
f47709a9 7135 crtc->lowfreq_avail = false;
a93e255f 7136 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7137 reduced_clock) {
190f68c5 7138 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7139 crtc->lowfreq_avail = true;
a7516a05 7140 } else {
190f68c5 7141 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7142 }
7143}
7144
5e69f97f
CML		 7145static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7146 pipe)
89b667f8
JB		 7147{
7148 u32 reg_val;
7149
7150 /*
7151 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7152 * and set it to a reasonable value instead.
7153 */
ab3c759a 7154 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7155 reg_val &= 0xffffff00;
7156 reg_val |= 0x00000030;
ab3c759a 7157 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7158
ab3c759a 7159 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7160 reg_val &= 0x8cffffff;
7161 reg_val = 0x8c000000;
ab3c759a 7162 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7163
ab3c759a 7164 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7165 reg_val &= 0xffffff00;
ab3c759a 7166 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7167
ab3c759a 7168 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7169 reg_val &= 0x00ffffff;
7170 reg_val |= 0xb0000000;
ab3c759a 7171 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7172}
7173
b551842d
DV		 7174static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7175 struct intel_link_m_n *m_n)
7176{
7177 struct drm_device *dev = crtc->base.dev;
7178 struct drm_i915_private *dev_priv = dev->dev_private;
7179 int pipe = crtc->pipe;
7180
e3b95f1e
DV		 7181 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7182 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7183 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7184 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7185}
7186
7187static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7188 struct intel_link_m_n *m_n,
7189 struct intel_link_m_n *m2_n2)
b551842d
DV		 7190{
7191 struct drm_device *dev = crtc->base.dev;
7192 struct drm_i915_private *dev_priv = dev->dev_private;
7193 int pipe = crtc->pipe;
6e3c9717 7194 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7195
7196 if (INTEL_INFO(dev)->gen >= 5) {
7197 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7198 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7199 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7200 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7201 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7202 * for gen < 8) and if DRRS is supported (to make sure the
7203 * registers are not unnecessarily accessed).
7204 */
44395bfe 7205 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7206 crtc->config->has_drrs) {
f769cd24
VK		 7207 I915_WRITE(PIPE_DATA_M2(transcoder),
7208 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7209 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7210 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7211 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7212 }
b551842d 7213 } else {
e3b95f1e
DV		 7214 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7215 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7216 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7217 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7218 }
7219}
7220
fe3cd48d 7221void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7222{
fe3cd48d
R		 7223 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7224
7225 if (m_n == M1_N1) {
7226 dp_m_n = &crtc->config->dp_m_n;
7227 dp_m2_n2 = &crtc->config->dp_m2_n2;
7228 } else if (m_n == M2_N2) {
7229
7230 /*
7231 * M2_N2 registers are not supported. Hence m2_n2 divider value
7232 * needs to be programmed into M1_N1.
7233 */
7234 dp_m_n = &crtc->config->dp_m2_n2;
7235 } else {
7236 DRM_ERROR("Unsupported divider value\n");
7237 return;
7238 }
7239
6e3c9717
ACO		 7240 if (crtc->config->has_pch_encoder)
7241 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7242 else
fe3cd48d 7243 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7244}
7245
251ac862
DV		 7246static void vlv_compute_dpll(struct intel_crtc *crtc,
7247 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7248{
7249 u32 dpll, dpll_md;
7250
7251 /*
7252 * Enable DPIO clock input. We should never disable the reference
7253 * clock for pipe B, since VGA hotplug / manual detection depends
7254 * on it.
7255 */
60bfe44f
VS		 7256 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7257 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7258 /* We should never disable this, set it here for state tracking */
7259 if (crtc->pipe == PIPE_B)
7260 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7261 dpll |= DPLL_VCO_ENABLE;
d288f65f 7262 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7263
d288f65f 7264 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7265 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7266 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7267}
7268
d288f65f 7269static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7270 const struct intel_crtc_state *pipe_config)
a0c4da24 7271{
f47709a9 7272 struct drm_device *dev = crtc->base.dev;
a0c4da24 7273 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7274 int pipe = crtc->pipe;
bdd4b6a6 7275 u32 mdiv;
a0c4da24 7276 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7277 u32 coreclk, reg_val;
a0c4da24 7278
a580516d 7279 mutex_lock(&dev_priv->sb_lock);
09153000 7280
d288f65f
VS		 7281 bestn = pipe_config->dpll.n;
7282 bestm1 = pipe_config->dpll.m1;
7283 bestm2 = pipe_config->dpll.m2;
7284 bestp1 = pipe_config->dpll.p1;
7285 bestp2 = pipe_config->dpll.p2;
a0c4da24 7286
89b667f8
JB		 7287 /* See eDP HDMI DPIO driver vbios notes doc */
7288
7289 /* PLL B needs special handling */
bdd4b6a6 7290 if (pipe == PIPE_B)
5e69f97f 7291 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7292
7293 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7295
7296 /* Disable target IRef on PLL */
ab3c759a 7297 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7298 reg_val &= 0x00ffffff;
ab3c759a 7299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7300
7301 /* Disable fast lock */
ab3c759a 7302 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7303
7304 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7305 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7306 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7307 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7308 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7309
7310 /*
7311 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7312 * but we don't support that).
7313 * Note: don't use the DAC post divider as it seems unstable.
7314 */
7315 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7317
a0c4da24 7318 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7319 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7320
89b667f8 7321 /* Set HBR and RBR LPF coefficients */
d288f65f 7322 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7323 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7324 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7326 0x009f0003);
89b667f8 7327 else
ab3c759a 7328 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7329 0x00d0000f);
7330
681a8504 7331 if (pipe_config->has_dp_encoder) {
89b667f8 7332 /* Use SSC source */
bdd4b6a6 7333 if (pipe == PIPE_A)
ab3c759a 7334 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7335 0x0df40000);
7336 else
ab3c759a 7337 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7338 0x0df70000);
7339 } else { /* HDMI or VGA */
7340 /* Use bend source */
bdd4b6a6 7341 if (pipe == PIPE_A)
ab3c759a 7342 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7343 0x0df70000);
7344 else
ab3c759a 7345 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7346 0x0df40000);
7347 }
a0c4da24 7348
ab3c759a 7349 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7350 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7351 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7352 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7353 coreclk |= 0x01000000;
ab3c759a 7354 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7355
ab3c759a 7356 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7357 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7358}
7359
251ac862
DV		 7360static void chv_compute_dpll(struct intel_crtc *crtc,
7361 struct intel_crtc_state *pipe_config)
1ae0d137 7362{
60bfe44f
VS		 7363 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7364 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7365 DPLL_VCO_ENABLE;
7366 if (crtc->pipe != PIPE_A)
d288f65f 7367 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7368
d288f65f
VS		 7369 pipe_config->dpll_hw_state.dpll_md =
7370 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7371}
7372
d288f65f 7373static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7374 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7375{
7376 struct drm_device *dev = crtc->base.dev;
7377 struct drm_i915_private *dev_priv = dev->dev_private;
7378 int pipe = crtc->pipe;
7379 int dpll_reg = DPLL(crtc->pipe);
7380 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7381 u32 loopfilter, tribuf_calcntr;
9d556c99 7382 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7383 u32 dpio_val;
9cbe40c1 7384 int vco;
9d556c99 7385
d288f65f
VS		 7386 bestn = pipe_config->dpll.n;
7387 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7388 bestm1 = pipe_config->dpll.m1;
7389 bestm2 = pipe_config->dpll.m2 >> 22;
7390 bestp1 = pipe_config->dpll.p1;
7391 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7392 vco = pipe_config->dpll.vco;
a945ce7e 7393 dpio_val = 0;
9cbe40c1 7394 loopfilter = 0;
9d556c99
CML		 7395
7396 /*
7397 * Enable Refclk and SSC
7398 */
a11b0703 7399 I915_WRITE(dpll_reg,
d288f65f 7400 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7401
a580516d 7402 mutex_lock(&dev_priv->sb_lock);
9d556c99 7403
9d556c99
CML		 7404 /* p1 and p2 divider */
7405 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7406 5 << DPIO_CHV_S1_DIV_SHIFT |
7407 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7408 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7409 1 << DPIO_CHV_K_DIV_SHIFT);
7410
7411 /* Feedback post-divider - m2 */
7412 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7413
7414 /* Feedback refclk divider - n and m1 */
7415 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7416 DPIO_CHV_M1_DIV_BY_2 |
7417 1 << DPIO_CHV_N_DIV_SHIFT);
7418
7419 /* M2 fraction division */
25a25dfc 7420 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7421
7422 /* M2 fraction division enable */
a945ce7e
VP		 7423 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7424 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7425 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7426 if (bestm2_frac)
7427 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7428 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7429
de3a0fde
VP		 7430 /* Program digital lock detect threshold */
7431 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7432 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7433 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7434 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7435 if (!bestm2_frac)
7436 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7437 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7438
9d556c99 7439 /* Loop filter */
9cbe40c1
VP		 7440 if (vco == 5400000) {
7441 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7442 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7443 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7444 tribuf_calcntr = 0x9;
7445 } else if (vco <= 6200000) {
7446 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7447 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7448 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7449 tribuf_calcntr = 0x9;
7450 } else if (vco <= 6480000) {
7451 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7452 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7453 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7454 tribuf_calcntr = 0x8;
7455 } else {
7456 /* Not supported. Apply the same limits as in the max case */
7457 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7458 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7459 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7460 tribuf_calcntr = 0;
7461 }
9d556c99
CML		 7462 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7463
968040b2 7464 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7465 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7466 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7467 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7468
9d556c99
CML		 7469 /* AFC Recal */
7470 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7471 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7472 DPIO_AFC_RECAL);
7473
a580516d 7474 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7475}
7476
d288f65f
VS		 7477/**
7478 * vlv_force_pll_on - forcibly enable just the PLL
7479 * @dev_priv: i915 private structure
7480 * @pipe: pipe PLL to enable
7481 * @dpll: PLL configuration
7482 *
7483 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7484 * in cases where we need the PLL enabled even when @pipe is not going to
7485 * be enabled.
7486 */
7487void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7488 const struct dpll *dpll)
7489{
7490 struct intel_crtc *crtc =
7491 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7492 struct intel_crtc_state pipe_config = {
a93e255f 7493 .base.crtc = &crtc->base,
d288f65f
VS		 7494 .pixel_multiplier = 1,
7495 .dpll = *dpll,
7496 };
7497
7498 if (IS_CHERRYVIEW(dev)) {
251ac862 7499 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7500 chv_prepare_pll(crtc, &pipe_config);
7501 chv_enable_pll(crtc, &pipe_config);
7502 } else {
251ac862 7503 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7504 vlv_prepare_pll(crtc, &pipe_config);
7505 vlv_enable_pll(crtc, &pipe_config);
7506 }
7507}
7508
7509/**
7510 * vlv_force_pll_off - forcibly disable just the PLL
7511 * @dev_priv: i915 private structure
7512 * @pipe: pipe PLL to disable
7513 *
7514 * Disable the PLL for @pipe. To be used in cases where we need
7515 * the PLL enabled even when @pipe is not going to be enabled.
7516 */
7517void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7518{
7519 if (IS_CHERRYVIEW(dev))
7520 chv_disable_pll(to_i915(dev), pipe);
7521 else
7522 vlv_disable_pll(to_i915(dev), pipe);
7523}
7524
251ac862
DV		 7525static void i9xx_compute_dpll(struct intel_crtc *crtc,
7526 struct intel_crtc_state *crtc_state,
7527 intel_clock_t *reduced_clock,
7528 int num_connectors)
eb1cbe48 7529{
f47709a9 7530 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7531 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7532 u32 dpll;
7533 bool is_sdvo;
190f68c5 7534 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7535
190f68c5 7536 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7537
a93e255f
ACO		 7538 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7539 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7540
7541 dpll = DPLL_VGA_MODE_DIS;
7542
a93e255f 7543 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7544 dpll |= DPLLB_MODE_LVDS;
7545 else
7546 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7547
ef1b460d 7548 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7549 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7550 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7551 }
198a037f
DV		 7552
7553 if (is_sdvo)
4a33e48d 7554 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7555
190f68c5 7556 if (crtc_state->has_dp_encoder)
4a33e48d 7557 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7558
7559 /* compute bitmask from p1 value */
7560 if (IS_PINEVIEW(dev))
7561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7562 else {
7563 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7564 if (IS_G4X(dev) && reduced_clock)
7565 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7566 }
7567 switch (clock->p2) {
7568 case 5:
7569 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7570 break;
7571 case 7:
7572 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7573 break;
7574 case 10:
7575 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7576 break;
7577 case 14:
7578 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7579 break;
7580 }
7581 if (INTEL_INFO(dev)->gen >= 4)
7582 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7583
190f68c5 7584 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7585 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7586 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7587 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7588 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7589 else
7590 dpll |= PLL_REF_INPUT_DREFCLK;
7591
7592 dpll |= DPLL_VCO_ENABLE;
190f68c5 7593 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7594
eb1cbe48 7595 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7596 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7597 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7598 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7599 }
7600}
7601
251ac862
DV		 7602static void i8xx_compute_dpll(struct intel_crtc *crtc,
7603 struct intel_crtc_state *crtc_state,
7604 intel_clock_t *reduced_clock,
7605 int num_connectors)
eb1cbe48 7606{
f47709a9 7607 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7608 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7609 u32 dpll;
190f68c5 7610 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7611
190f68c5 7612 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7613
eb1cbe48
DV		 7614 dpll = DPLL_VGA_MODE_DIS;
7615
a93e255f 7616 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7617 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7618 } else {
7619 if (clock->p1 == 2)
7620 dpll |= PLL_P1_DIVIDE_BY_TWO;
7621 else
7622 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7623 if (clock->p2 == 4)
7624 dpll |= PLL_P2_DIVIDE_BY_4;
7625 }
7626
a93e255f 7627 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7628 dpll |= DPLL_DVO_2X_MODE;
7629
a93e255f 7630 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7631 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7632 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7633 else
7634 dpll |= PLL_REF_INPUT_DREFCLK;
7635
7636 dpll |= DPLL_VCO_ENABLE;
190f68c5 7637 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7638}
7639
8a654f3b 7640static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7641{
7642 struct drm_device *dev = intel_crtc->base.dev;
7643 struct drm_i915_private *dev_priv = dev->dev_private;
7644 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7645 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7c5f93b0 7646 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7647 uint32_t crtc_vtotal, crtc_vblank_end;
7648 int vsyncshift = 0;
4d8a62ea
DV		 7649
7650 /* We need to be careful not to changed the adjusted mode, for otherwise
7651 * the hw state checker will get angry at the mismatch. */
7652 crtc_vtotal = adjusted_mode->crtc_vtotal;
7653 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7654
609aeaca 7655 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7656 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7657 crtc_vtotal -= 1;
7658 crtc_vblank_end -= 1;
609aeaca 7659
409ee761 7660 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7661 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7662 else
7663 vsyncshift = adjusted_mode->crtc_hsync_start -
7664 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7665 if (vsyncshift < 0)
7666 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7667 }
7668
7669 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7670 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7671
fe2b8f9d 7672 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7673 (adjusted_mode->crtc_hdisplay - 1) |
7674 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7675 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7676 (adjusted_mode->crtc_hblank_start - 1) |
7677 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7678 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7679 (adjusted_mode->crtc_hsync_start - 1) |
7680 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7681
fe2b8f9d 7682 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7683 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7684 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7685 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7686 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7687 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7688 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7689 (adjusted_mode->crtc_vsync_start - 1) |
7690 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7691
b5e508d4
PZ		 7692 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7693 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7694 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7695 * bits. */
7696 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7697 (pipe == PIPE_B || pipe == PIPE_C))
7698 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7699
b0e77b9c
PZ		 7700 /* pipesrc controls the size that is scaled from, which should
7701 * always be the user's requested size.
7702 */
7703 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7704 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7705 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7706}
7707
1bd1bd80 7708static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7709 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7710{
7711 struct drm_device *dev = crtc->base.dev;
7712 struct drm_i915_private *dev_priv = dev->dev_private;
7713 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7714 uint32_t tmp;
7715
7716 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7717 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7718 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7719 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7720 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7721 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7722 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7723 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7724 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7725
7726 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7727 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7728 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7729 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7730 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7731 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7732 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7733 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7734 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7735
7736 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7737 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7738 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7739 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7740 }
7741
7742 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7743 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7744 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7745
2d112de7
ACO		 7746 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7747 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7748}
7749
f6a83288 7750void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7751 struct intel_crtc_state *pipe_config)
babea61d 7752{
2d112de7
ACO		 7753 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7754 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7755 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7756 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7757
2d112de7
ACO		 7758 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7759 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7760 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7761 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7762
2d112de7 7763 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7764 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7765
2d112de7
ACO		 7766 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7767 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7768
7769 mode->hsync = drm_mode_hsync(mode);
7770 mode->vrefresh = drm_mode_vrefresh(mode);
7771 drm_mode_set_name(mode);
babea61d
JB		 7772}
7773
84b046f3
DV		 7774static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7775{
7776 struct drm_device *dev = intel_crtc->base.dev;
7777 struct drm_i915_private *dev_priv = dev->dev_private;
7778 uint32_t pipeconf;
7779
9f11a9e4 7780 pipeconf = 0;
84b046f3 7781
b6b5d049
VS		 7782 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7783 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7784 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7785
6e3c9717 7786 if (intel_crtc->config->double_wide)
cf532bb2 7787 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7788
ff9ce46e
DV		 7789 /* only g4x and later have fancy bpc/dither controls */
7790 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7791 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7792 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7793 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7794 PIPECONF_DITHER_TYPE_SP;
84b046f3 7795
6e3c9717 7796 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7797 case 18:
7798 pipeconf |= PIPECONF_6BPC;
7799 break;
7800 case 24:
7801 pipeconf |= PIPECONF_8BPC;
7802 break;
7803 case 30:
7804 pipeconf |= PIPECONF_10BPC;
7805 break;
7806 default:
7807 /* Case prevented by intel_choose_pipe_bpp_dither. */
7808 BUG();
84b046f3
DV		 7809 }
7810 }
7811
7812 if (HAS_PIPE_CXSR(dev)) {
7813 if (intel_crtc->lowfreq_avail) {
7814 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7815 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7816 } else {
7817 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7818 }
7819 }
7820
6e3c9717 7821 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7822 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7823 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7824 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7825 else
7826 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7827 } else
84b046f3
DV		 7828 pipeconf |= PIPECONF_PROGRESSIVE;
7829
6e3c9717 7830 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7831 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7832
84b046f3
DV		 7833 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7834 POSTING_READ(PIPECONF(intel_crtc->pipe));
7835}
7836
190f68c5
ACO		 7837static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7838 struct intel_crtc_state *crtc_state)
79e53945 7839{
c7653199 7840 struct drm_device *dev = crtc->base.dev;
79e53945 7841 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7842 int refclk, num_connectors = 0;
c329a4ec
DV		 7843 intel_clock_t clock;
7844 bool ok;
7845 bool is_dsi = false;
5eddb70b 7846 struct intel_encoder *encoder;
d4906093 7847 const intel_limit_t *limit;
55bb9992 7848 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7849 struct drm_connector *connector;
55bb9992
ACO		 7850 struct drm_connector_state *connector_state;
7851 int i;
79e53945 7852
dd3cd74a
ACO		 7853 memset(&crtc_state->dpll_hw_state, 0,
7854 sizeof(crtc_state->dpll_hw_state));
7855
da3ced29 7856 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7857 if (connector_state->crtc != &crtc->base)
7858 continue;
7859
7860 encoder = to_intel_encoder(connector_state->best_encoder);
7861
5eddb70b 7862 switch (encoder->type) {
e9fd1c02
JN		 7863 case INTEL_OUTPUT_DSI:
7864 is_dsi = true;
7865 break;
6847d71b
PZ		 7866 default:
7867 break;
79e53945 7868 }
43565a06 7869
c751ce4f 7870 num_connectors++;
79e53945
JB		 7871 }
7872
f2335330 7873 if (is_dsi)
5b18e57c 7874 return 0;
f2335330 7875
190f68c5 7876 if (!crtc_state->clock_set) {
a93e255f 7877 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7878
e9fd1c02
JN		 7879 /*
7880 * Returns a set of divisors for the desired target clock with
7881 * the given refclk, or FALSE. The returned values represent
7882 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7883 * 2) / p1 / p2.
7884 */
a93e255f
ACO		 7885 limit = intel_limit(crtc_state, refclk);
7886 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7887 crtc_state->port_clock,
e9fd1c02 7888 refclk, NULL, &clock);
f2335330 7889 if (!ok) {
e9fd1c02
JN		 7890 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7891 return -EINVAL;
7892 }
79e53945 7893
f2335330 7894 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7895 crtc_state->dpll.n = clock.n;
7896 crtc_state->dpll.m1 = clock.m1;
7897 crtc_state->dpll.m2 = clock.m2;
7898 crtc_state->dpll.p1 = clock.p1;
7899 crtc_state->dpll.p2 = clock.p2;
f47709a9 7900 }
7026d4ac 7901
e9fd1c02 7902 if (IS_GEN2(dev)) {
c329a4ec 7903 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7904 num_connectors);
9d556c99 7905 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7906 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7907 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7908 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7909 } else {
c329a4ec 7910 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7911 num_connectors);
e9fd1c02 7912 }
79e53945 7913
c8f7a0db 7914 return 0;
f564048e
EA		 7915}
7916
2fa2fe9a 7917static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7918 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7919{
7920 struct drm_device *dev = crtc->base.dev;
7921 struct drm_i915_private *dev_priv = dev->dev_private;
7922 uint32_t tmp;
7923
dc9e7dec
VS		 7924 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7925 return;
7926
2fa2fe9a 7927 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7928 if (!(tmp & PFIT_ENABLE))
7929 return;
2fa2fe9a 7930
06922821 7931 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7932 if (INTEL_INFO(dev)->gen < 4) {
7933 if (crtc->pipe != PIPE_B)
7934 return;
2fa2fe9a
DV		 7935 } else {
7936 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7937 return;
7938 }
7939
06922821 7940 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7941 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7942 if (INTEL_INFO(dev)->gen < 5)
7943 pipe_config->gmch_pfit.lvds_border_bits =
7944 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7945}
7946
acbec814 7947static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7948 struct intel_crtc_state *pipe_config)
acbec814
JB		 7949{
7950 struct drm_device *dev = crtc->base.dev;
7951 struct drm_i915_private *dev_priv = dev->dev_private;
7952 int pipe = pipe_config->cpu_transcoder;
7953 intel_clock_t clock;
7954 u32 mdiv;
662c6ecb 7955 int refclk = 100000;
acbec814 7956
f573de5a
SK		 7957 /* In case of MIPI DPLL will not even be used */
7958 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7959 return;
7960
a580516d 7961 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7962 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7963 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7964
7965 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7966 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7967 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7968 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7969 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7970
dccbea3b 7971 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7972}
7973
5724dbd1
DL		 7974static void
7975i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7976 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7977{
7978 struct drm_device *dev = crtc->base.dev;
7979 struct drm_i915_private *dev_priv = dev->dev_private;
7980 u32 val, base, offset;
7981 int pipe = crtc->pipe, plane = crtc->plane;
7982 int fourcc, pixel_format;
6761dd31 7983 unsigned int aligned_height;
b113d5ee 7984 struct drm_framebuffer *fb;
1b842c89 7985 struct intel_framebuffer *intel_fb;
1ad292b5 7986
42a7b088
DL		 7987 val = I915_READ(DSPCNTR(plane));
7988 if (!(val & DISPLAY_PLANE_ENABLE))
7989 return;
7990
d9806c9f 7991 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7992 if (!intel_fb) {
1ad292b5
JB		 7993 DRM_DEBUG_KMS("failed to alloc fb\n");
7994 return;
7995 }
7996
1b842c89
DL		 7997 fb = &intel_fb->base;
7998
18c5247e
DV		 7999 if (INTEL_INFO(dev)->gen >= 4) {
8000 if (val & DISPPLANE_TILED) {
49af449b 8001 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8002 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8003 }
8004 }
1ad292b5
JB		 8005
8006 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8007 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8008 fb->pixel_format = fourcc;
8009 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8010
8011 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8012 if (plane_config->tiling)
1ad292b5
JB		 8013 offset = I915_READ(DSPTILEOFF(plane));
8014 else
8015 offset = I915_READ(DSPLINOFF(plane));
8016 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8017 } else {
8018 base = I915_READ(DSPADDR(plane));
8019 }
8020 plane_config->base = base;
8021
8022 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8023 fb->width = ((val >> 16) & 0xfff) + 1;
8024 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8025
8026 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8027 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8028
b113d5ee 8029 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8030 fb->pixel_format,
8031 fb->modifier[0]);
1ad292b5 8032
f37b5c2b 8033 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8034
2844a921
DL		 8035 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8036 pipe_name(pipe), plane, fb->width, fb->height,
8037 fb->bits_per_pixel, base, fb->pitches[0],
8038 plane_config->size);
1ad292b5 8039
2d14030b 8040 plane_config->fb = intel_fb;
1ad292b5
JB		 8041}
8042
70b23a98 8043static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8044 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8045{
8046 struct drm_device *dev = crtc->base.dev;
8047 struct drm_i915_private *dev_priv = dev->dev_private;
8048 int pipe = pipe_config->cpu_transcoder;
8049 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8050 intel_clock_t clock;
0d7b6b11 8051 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 8052 int refclk = 100000;
8053
a580516d 8054 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8055 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8056 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8057 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8058 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8059 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8060 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8061
8062 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8063 clock.m2 = (pll_dw0 & 0xff) << 22;
8064 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8065 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8066 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8067 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8068 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8069
dccbea3b 8070 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8071}
8072
0e8ffe1b 8073static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8074 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8075{
8076 struct drm_device *dev = crtc->base.dev;
8077 struct drm_i915_private *dev_priv = dev->dev_private;
8078 uint32_t tmp;
8079
f458ebbc
DV		 8080 if (!intel_display_power_is_enabled(dev_priv,
8081 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8082 return false;
8083
e143a21c 8084 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8085 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8086
0e8ffe1b
DV		 8087 tmp = I915_READ(PIPECONF(crtc->pipe));
8088 if (!(tmp & PIPECONF_ENABLE))
8089 return false;
8090
42571aef
VS		 8091 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8092 switch (tmp & PIPECONF_BPC_MASK) {
8093 case PIPECONF_6BPC:
8094 pipe_config->pipe_bpp = 18;
8095 break;
8096 case PIPECONF_8BPC:
8097 pipe_config->pipe_bpp = 24;
8098 break;
8099 case PIPECONF_10BPC:
8100 pipe_config->pipe_bpp = 30;
8101 break;
8102 default:
8103 break;
8104 }
8105 }
8106
b5a9fa09
DV		 8107 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8108 pipe_config->limited_color_range = true;
8109
282740f7
VS		 8110 if (INTEL_INFO(dev)->gen < 4)
8111 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8112
1bd1bd80
DV		 8113 intel_get_pipe_timings(crtc, pipe_config);
8114
2fa2fe9a
DV		 8115 i9xx_get_pfit_config(crtc, pipe_config);
8116
6c49f241
DV		 8117 if (INTEL_INFO(dev)->gen >= 4) {
8118 tmp = I915_READ(DPLL_MD(crtc->pipe));
8119 pipe_config->pixel_multiplier =
8120 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8121 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8122 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8123 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8124 tmp = I915_READ(DPLL(crtc->pipe));
8125 pipe_config->pixel_multiplier =
8126 ((tmp & SDVO_MULTIPLIER_MASK)
8127 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8128 } else {
8129 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8130 * port and will be fixed up in the encoder->get_config
8131 * function. */
8132 pipe_config->pixel_multiplier = 1;
8133 }
8bcc2795
DV		 8134 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8135 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8136 /*
8137 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8138 * on 830. Filter it out here so that we don't
8139 * report errors due to that.
8140 */
8141 if (IS_I830(dev))
8142 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8143
8bcc2795
DV		 8144 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8145 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8146 } else {
8147 /* Mask out read-only status bits. */
8148 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8149 DPLL_PORTC_READY_MASK |
8150 DPLL_PORTB_READY_MASK);
8bcc2795 8151 }
6c49f241 8152
70b23a98
VS		 8153 if (IS_CHERRYVIEW(dev))
8154 chv_crtc_clock_get(crtc, pipe_config);
8155 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8156 vlv_crtc_clock_get(crtc, pipe_config);
8157 else
8158 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8159
0f64614d
VS		 8160 /*
8161 * Normally the dotclock is filled in by the encoder .get_config()
8162 * but in case the pipe is enabled w/o any ports we need a sane
8163 * default.
8164 */
8165 pipe_config->base.adjusted_mode.crtc_clock =
8166 pipe_config->port_clock / pipe_config->pixel_multiplier;
8167
0e8ffe1b
DV		 8168 return true;
8169}
8170
dde86e2d 8171static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8172{
8173 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8174 struct intel_encoder *encoder;
74cfd7ac 8175 u32 val, final;
13d83a67 8176 bool has_lvds = false;
199e5d79 8177 bool has_cpu_edp = false;
199e5d79 8178 bool has_panel = false;
99eb6a01
KP		 8179 bool has_ck505 = false;
8180 bool can_ssc = false;
13d83a67
JB		 8181
8182 /* We need to take the global config into account */
b2784e15 8183 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8184 switch (encoder->type) {
8185 case INTEL_OUTPUT_LVDS:
8186 has_panel = true;
8187 has_lvds = true;
8188 break;
8189 case INTEL_OUTPUT_EDP:
8190 has_panel = true;
2de6905f 8191 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8192 has_cpu_edp = true;
8193 break;
6847d71b
PZ		 8194 default:
8195 break;
13d83a67
JB		 8196 }
8197 }
8198
99eb6a01 8199 if (HAS_PCH_IBX(dev)) {
41aa3448 8200 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8201 can_ssc = has_ck505;
8202 } else {
8203 has_ck505 = false;
8204 can_ssc = true;
8205 }
8206
2de6905f
ID		 8207 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8208 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8209
8210 /* Ironlake: try to setup display ref clock before DPLL
8211 * enabling. This is only under driver's control after
8212 * PCH B stepping, previous chipset stepping should be
8213 * ignoring this setting.
8214 */
74cfd7ac
CW		 8215 val = I915_READ(PCH_DREF_CONTROL);
8216
8217 /* As we must carefully and slowly disable/enable each source in turn,
8218 * compute the final state we want first and check if we need to
8219 * make any changes at all.
8220 */
8221 final = val;
8222 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8223 if (has_ck505)
8224 final |= DREF_NONSPREAD_CK505_ENABLE;
8225 else
8226 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8227
8228 final &= ~DREF_SSC_SOURCE_MASK;
8229 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8230 final &= ~DREF_SSC1_ENABLE;
8231
8232 if (has_panel) {
8233 final |= DREF_SSC_SOURCE_ENABLE;
8234
8235 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8236 final |= DREF_SSC1_ENABLE;
8237
8238 if (has_cpu_edp) {
8239 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8240 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8241 else
8242 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8243 } else
8244 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8245 } else {
8246 final |= DREF_SSC_SOURCE_DISABLE;
8247 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8248 }
8249
8250 if (final == val)
8251 return;
8252
13d83a67 8253 /* Always enable nonspread source */
74cfd7ac 8254 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8255
99eb6a01 8256 if (has_ck505)
74cfd7ac 8257 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8258 else
74cfd7ac 8259 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8260
199e5d79 8261 if (has_panel) {
74cfd7ac
CW		 8262 val &= ~DREF_SSC_SOURCE_MASK;
8263 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8264
199e5d79 8265 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8266 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8267 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8268 val |= DREF_SSC1_ENABLE;
e77166b5 8269 } else
74cfd7ac 8270 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8271
8272 /* Get SSC going before enabling the outputs */
74cfd7ac 8273 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8274 POSTING_READ(PCH_DREF_CONTROL);
8275 udelay(200);
8276
74cfd7ac 8277 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8278
8279 /* Enable CPU source on CPU attached eDP */
199e5d79 8280 if (has_cpu_edp) {
99eb6a01 8281 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8282 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8283 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8284 } else
74cfd7ac 8285 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8286 } else
74cfd7ac 8287 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8288
74cfd7ac 8289 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8290 POSTING_READ(PCH_DREF_CONTROL);
8291 udelay(200);
8292 } else {
8293 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8294
74cfd7ac 8295 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8296
8297 /* Turn off CPU output */
74cfd7ac 8298 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8299
74cfd7ac 8300 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8301 POSTING_READ(PCH_DREF_CONTROL);
8302 udelay(200);
8303
8304 /* Turn off the SSC source */
74cfd7ac
CW		 8305 val &= ~DREF_SSC_SOURCE_MASK;
8306 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8307
8308 /* Turn off SSC1 */
74cfd7ac 8309 val &= ~DREF_SSC1_ENABLE;
199e5d79 8310
74cfd7ac 8311 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8312 POSTING_READ(PCH_DREF_CONTROL);
8313 udelay(200);
8314 }
74cfd7ac
CW		 8315
8316 BUG_ON(val != final);
13d83a67
JB		 8317}
8318
f31f2d55 8319static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8320{
f31f2d55 8321 uint32_t tmp;
dde86e2d 8322
0ff066a9
PZ		 8323 tmp = I915_READ(SOUTH_CHICKEN2);
8324 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8325 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8326
0ff066a9
PZ		 8327 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8328 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8329 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8330
0ff066a9
PZ		 8331 tmp = I915_READ(SOUTH_CHICKEN2);
8332 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8333 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8334
0ff066a9
PZ		 8335 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8336 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8337 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8338}
8339
8340/* WaMPhyProgramming:hsw */
8341static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8342{
8343 uint32_t tmp;
dde86e2d
PZ		 8344
8345 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8346 tmp &= ~(0xFF << 24);
8347 tmp |= (0x12 << 24);
8348 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8349
dde86e2d
PZ		 8350 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8351 tmp |= (1 << 11);
8352 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8353
8354 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8355 tmp |= (1 << 11);
8356 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8357
dde86e2d
PZ		 8358 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8359 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8360 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8361
8362 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8363 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8364 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8365
0ff066a9
PZ		 8366 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8367 tmp &= ~(7 << 13);
8368 tmp |= (5 << 13);
8369 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8370
0ff066a9
PZ		 8371 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8372 tmp &= ~(7 << 13);
8373 tmp |= (5 << 13);
8374 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8375
8376 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8377 tmp &= ~0xFF;
8378 tmp |= 0x1C;
8379 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8380
8381 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8382 tmp &= ~0xFF;
8383 tmp |= 0x1C;
8384 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8385
8386 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8387 tmp &= ~(0xFF << 16);
8388 tmp |= (0x1C << 16);
8389 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8390
8391 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8392 tmp &= ~(0xFF << 16);
8393 tmp |= (0x1C << 16);
8394 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8395
0ff066a9
PZ		 8396 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8397 tmp |= (1 << 27);
8398 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8399
0ff066a9
PZ		 8400 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8401 tmp |= (1 << 27);
8402 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8403
0ff066a9
PZ		 8404 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8405 tmp &= ~(0xF << 28);
8406 tmp |= (4 << 28);
8407 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8408
0ff066a9
PZ		 8409 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8410 tmp &= ~(0xF << 28);
8411 tmp |= (4 << 28);
8412 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8413}
8414
2fa86a1f
PZ		 8415/* Implements 3 different sequences from BSpec chapter "Display iCLK
8416 * Programming" based on the parameters passed:
8417 * - Sequence to enable CLKOUT_DP
8418 * - Sequence to enable CLKOUT_DP without spread
8419 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8420 */
8421static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8422 bool with_fdi)
f31f2d55
PZ		 8423{
8424 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8425 uint32_t reg, tmp;
8426
8427 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8428 with_spread = true;
c2699524 8429 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8430 with_fdi = false;
f31f2d55 8431
a580516d 8432 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8433
8434 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8435 tmp &= ~SBI_SSCCTL_DISABLE;
8436 tmp |= SBI_SSCCTL_PATHALT;
8437 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8438
8439 udelay(24);
8440
2fa86a1f
PZ		 8441 if (with_spread) {
8442 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8443 tmp &= ~SBI_SSCCTL_PATHALT;
8444 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8445
2fa86a1f
PZ		 8446 if (with_fdi) {
8447 lpt_reset_fdi_mphy(dev_priv);
8448 lpt_program_fdi_mphy(dev_priv);
8449 }
8450 }
dde86e2d 8451
c2699524 8452 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ		 8453 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8454 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8455 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8456
a580516d 8457 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8458}
8459
47701c3b
PZ		 8460/* Sequence to disable CLKOUT_DP */
8461static void lpt_disable_clkout_dp(struct drm_device *dev)
8462{
8463 struct drm_i915_private *dev_priv = dev->dev_private;
8464 uint32_t reg, tmp;
8465
a580516d 8466 mutex_lock(&dev_priv->sb_lock);
47701c3b 8467
c2699524 8468 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ		 8469 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8470 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8471 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8472
8473 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8474 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8475 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8476 tmp |= SBI_SSCCTL_PATHALT;
8477 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8478 udelay(32);
8479 }
8480 tmp |= SBI_SSCCTL_DISABLE;
8481 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8482 }
8483
a580516d 8484 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8485}
8486
bf8fa3d3
PZ		 8487static void lpt_init_pch_refclk(struct drm_device *dev)
8488{
bf8fa3d3
PZ		 8489 struct intel_encoder *encoder;
8490 bool has_vga = false;
8491
b2784e15 8492 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8493 switch (encoder->type) {
8494 case INTEL_OUTPUT_ANALOG:
8495 has_vga = true;
8496 break;
6847d71b
PZ		 8497 default:
8498 break;
bf8fa3d3
PZ		 8499 }
8500 }
8501
47701c3b
PZ		 8502 if (has_vga)
8503 lpt_enable_clkout_dp(dev, true, true);
8504 else
8505 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8506}
8507
dde86e2d
PZ		 8508/*
8509 * Initialize reference clocks when the driver loads
8510 */
8511void intel_init_pch_refclk(struct drm_device *dev)
8512{
8513 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8514 ironlake_init_pch_refclk(dev);
8515 else if (HAS_PCH_LPT(dev))
8516 lpt_init_pch_refclk(dev);
8517}
8518
55bb9992 8519static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8520{
55bb9992 8521 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8522 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8523 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8524 struct drm_connector *connector;
55bb9992 8525 struct drm_connector_state *connector_state;
d9d444cb 8526 struct intel_encoder *encoder;
55bb9992 8527 int num_connectors = 0, i;
d9d444cb
JB		 8528 bool is_lvds = false;
8529
da3ced29 8530 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8531 if (connector_state->crtc != crtc_state->base.crtc)
8532 continue;
8533
8534 encoder = to_intel_encoder(connector_state->best_encoder);
8535
d9d444cb
JB		 8536 switch (encoder->type) {
8537 case INTEL_OUTPUT_LVDS:
8538 is_lvds = true;
8539 break;
6847d71b
PZ		 8540 default:
8541 break;
d9d444cb
JB		 8542 }
8543 num_connectors++;
8544 }
8545
8546 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8547 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8548 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8549 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8550 }
8551
8552 return 120000;
8553}
8554
6ff93609 8555static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8556{
c8203565 8557 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8559 int pipe = intel_crtc->pipe;
c8203565
PZ		 8560 uint32_t val;
8561
78114071 8562 val = 0;
c8203565 8563
6e3c9717 8564 switch (intel_crtc->config->pipe_bpp) {
c8203565 8565 case 18:
dfd07d72 8566 val |= PIPECONF_6BPC;
c8203565
PZ		 8567 break;
8568 case 24:
dfd07d72 8569 val |= PIPECONF_8BPC;
c8203565
PZ		 8570 break;
8571 case 30:
dfd07d72 8572 val |= PIPECONF_10BPC;
c8203565
PZ		 8573 break;
8574 case 36:
dfd07d72 8575 val |= PIPECONF_12BPC;
c8203565
PZ		 8576 break;
8577 default:
cc769b62
PZ		 8578 /* Case prevented by intel_choose_pipe_bpp_dither. */
8579 BUG();
c8203565
PZ		 8580 }
8581
6e3c9717 8582 if (intel_crtc->config->dither)
c8203565
PZ		 8583 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8584
6e3c9717 8585 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8586 val |= PIPECONF_INTERLACED_ILK;
8587 else
8588 val |= PIPECONF_PROGRESSIVE;
8589
6e3c9717 8590 if (intel_crtc->config->limited_color_range)
3685a8f3 8591 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8592
c8203565
PZ		 8593 I915_WRITE(PIPECONF(pipe), val);
8594 POSTING_READ(PIPECONF(pipe));
8595}
8596
86d3efce
VS		 8597/*
8598 * Set up the pipe CSC unit.
8599 *
8600 * Currently only full range RGB to limited range RGB conversion
8601 * is supported, but eventually this should handle various
8602 * RGB<->YCbCr scenarios as well.
8603 */
50f3b016 8604static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8605{
8606 struct drm_device *dev = crtc->dev;
8607 struct drm_i915_private *dev_priv = dev->dev_private;
8608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8609 int pipe = intel_crtc->pipe;
8610 uint16_t coeff = 0x7800; /* 1.0 */
8611
8612 /*
8613 * TODO: Check what kind of values actually come out of the pipe
8614 * with these coeff/postoff values and adjust to get the best
8615 * accuracy. Perhaps we even need to take the bpc value into
8616 * consideration.
8617 */
8618
6e3c9717 8619 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8620 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8621
8622 /*
8623 * GY/GU and RY/RU should be the other way around according
8624 * to BSpec, but reality doesn't agree. Just set them up in
8625 * a way that results in the correct picture.
8626 */
8627 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8628 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8629
8630 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8631 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8632
8633 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8634 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8635
8636 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8637 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8638 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8639
8640 if (INTEL_INFO(dev)->gen > 6) {
8641 uint16_t postoff = 0;
8642
6e3c9717 8643 if (intel_crtc->config->limited_color_range)
32cf0cb0 8644 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8645
8646 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8647 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8648 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8649
8650 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8651 } else {
8652 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8653
6e3c9717 8654 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8655 mode |= CSC_BLACK_SCREEN_OFFSET;
8656
8657 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8658 }
8659}
8660
6ff93609 8661static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8662{
756f85cf
PZ		 8663 struct drm_device *dev = crtc->dev;
8664 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8666 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8667 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8668 uint32_t val;
8669
3eff4faa 8670 val = 0;
ee2b0b38 8671
6e3c9717 8672 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8673 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8674
6e3c9717 8675 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8676 val |= PIPECONF_INTERLACED_ILK;
8677 else
8678 val |= PIPECONF_PROGRESSIVE;
8679
702e7a56
PZ		 8680 I915_WRITE(PIPECONF(cpu_transcoder), val);
8681 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8682
8683 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8684 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8685
3cdf122c 8686 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8687 val = 0;
8688
6e3c9717 8689 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8690 case 18:
8691 val |= PIPEMISC_DITHER_6_BPC;
8692 break;
8693 case 24:
8694 val |= PIPEMISC_DITHER_8_BPC;
8695 break;
8696 case 30:
8697 val |= PIPEMISC_DITHER_10_BPC;
8698 break;
8699 case 36:
8700 val |= PIPEMISC_DITHER_12_BPC;
8701 break;
8702 default:
8703 /* Case prevented by pipe_config_set_bpp. */
8704 BUG();
8705 }
8706
6e3c9717 8707 if (intel_crtc->config->dither)
756f85cf
PZ		 8708 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8709
8710 I915_WRITE(PIPEMISC(pipe), val);
8711 }
ee2b0b38
PZ		 8712}
8713
6591c6e4 8714static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8715 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8716 intel_clock_t *clock,
8717 bool *has_reduced_clock,
8718 intel_clock_t *reduced_clock)
8719{
8720 struct drm_device *dev = crtc->dev;
8721 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8722 int refclk;
d4906093 8723 const intel_limit_t *limit;
c329a4ec 8724 bool ret;
79e53945 8725
55bb9992 8726 refclk = ironlake_get_refclk(crtc_state);
79e53945 8727
d4906093
ML		 8728 /*
8729 * Returns a set of divisors for the desired target clock with the given
8730 * refclk, or FALSE. The returned values represent the clock equation:
8731 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8732 */
a93e255f
ACO		 8733 limit = intel_limit(crtc_state, refclk);
8734 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8735 crtc_state->port_clock,
ee9300bb 8736 refclk, NULL, clock);
6591c6e4
PZ		 8737 if (!ret)
8738 return false;
cda4b7d3 8739
6591c6e4
PZ		 8740 return true;
8741}
8742
d4b1931c
PZ		 8743int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8744{
8745 /*
8746 * Account for spread spectrum to avoid
8747 * oversubscribing the link. Max center spread
8748 * is 2.5%; use 5% for safety's sake.
8749 */
8750 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8751 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8752}
8753
7429e9d4 8754static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8755{
7429e9d4 8756 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8757}
8758
de13a2e3 8759static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8760 struct intel_crtc_state *crtc_state,
7429e9d4 8761 u32 *fp,
9a7c7890 8762 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8763{
de13a2e3 8764 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8765 struct drm_device *dev = crtc->dev;
8766 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8767 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8768 struct drm_connector *connector;
55bb9992
ACO		 8769 struct drm_connector_state *connector_state;
8770 struct intel_encoder *encoder;
de13a2e3 8771 uint32_t dpll;
55bb9992 8772 int factor, num_connectors = 0, i;
09ede541 8773 bool is_lvds = false, is_sdvo = false;
79e53945 8774
da3ced29 8775 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8776 if (connector_state->crtc != crtc_state->base.crtc)
8777 continue;
8778
8779 encoder = to_intel_encoder(connector_state->best_encoder);
8780
8781 switch (encoder->type) {
79e53945
JB		 8782 case INTEL_OUTPUT_LVDS:
8783 is_lvds = true;
8784 break;
8785 case INTEL_OUTPUT_SDVO:
7d57382e 8786 case INTEL_OUTPUT_HDMI:
79e53945 8787 is_sdvo = true;
79e53945 8788 break;
6847d71b
PZ		 8789 default:
8790 break;
79e53945 8791 }
43565a06 8792
c751ce4f 8793 num_connectors++;
79e53945 8794 }
79e53945 8795
c1858123 8796 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8797 factor = 21;
8798 if (is_lvds) {
8799 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8800 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8801 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8802 factor = 25;
190f68c5 8803 } else if (crtc_state->sdvo_tv_clock)
8febb297 8804 factor = 20;
c1858123 8805
190f68c5 8806 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8807 *fp |= FP_CB_TUNE;
2c07245f 8808
9a7c7890
DV		 8809 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8810 *fp2 |= FP_CB_TUNE;
8811
5eddb70b 8812 dpll = 0;
2c07245f 8813
a07d6787
EA		 8814 if (is_lvds)
8815 dpll |= DPLLB_MODE_LVDS;
8816 else
8817 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8818
190f68c5 8819 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8820 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8821
8822 if (is_sdvo)
4a33e48d 8823 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8824 if (crtc_state->has_dp_encoder)
4a33e48d 8825 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8826
a07d6787 8827 /* compute bitmask from p1 value */
190f68c5 8828 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8829 /* also FPA1 */
190f68c5 8830 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8831
190f68c5 8832 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8833 case 5:
8834 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8835 break;
8836 case 7:
8837 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8838 break;
8839 case 10:
8840 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8841 break;
8842 case 14:
8843 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8844 break;
79e53945
JB		 8845 }
8846
b4c09f3b 8847 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8848 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8849 else
8850 dpll |= PLL_REF_INPUT_DREFCLK;
8851
959e16d6 8852 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8853}
8854
190f68c5
ACO		 8855static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8856 struct intel_crtc_state *crtc_state)
de13a2e3 8857{
c7653199 8858 struct drm_device *dev = crtc->base.dev;
de13a2e3 8859 intel_clock_t clock, reduced_clock;
cbbab5bd 8860 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8861 bool ok, has_reduced_clock = false;
8b47047b 8862 bool is_lvds = false;
e2b78267 8863 struct intel_shared_dpll *pll;
de13a2e3 8864
dd3cd74a
ACO		 8865 memset(&crtc_state->dpll_hw_state, 0,
8866 sizeof(crtc_state->dpll_hw_state));
8867
409ee761 8868 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8869
5dc5298b
PZ		 8870 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8871 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8872
190f68c5 8873 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8874 &has_reduced_clock, &reduced_clock);
190f68c5 8875 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8876 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8877 return -EINVAL;
79e53945 8878 }
f47709a9 8879 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8880 if (!crtc_state->clock_set) {
8881 crtc_state->dpll.n = clock.n;
8882 crtc_state->dpll.m1 = clock.m1;
8883 crtc_state->dpll.m2 = clock.m2;
8884 crtc_state->dpll.p1 = clock.p1;
8885 crtc_state->dpll.p2 = clock.p2;
f47709a9 8886 }
79e53945 8887
5dc5298b 8888 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8889 if (crtc_state->has_pch_encoder) {
8890 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8891 if (has_reduced_clock)
7429e9d4 8892 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8893
190f68c5 8894 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8895 &fp, &reduced_clock,
8896 has_reduced_clock ? &fp2 : NULL);
8897
190f68c5
ACO		 8898 crtc_state->dpll_hw_state.dpll = dpll;
8899 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8900 if (has_reduced_clock)
190f68c5 8901 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8902 else
190f68c5 8903 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8904
190f68c5 8905 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8906 if (pll == NULL) {
84f44ce7 8907 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8908 pipe_name(crtc->pipe));
4b645f14
JB		 8909 return -EINVAL;
8910 }
3fb37703 8911 }
79e53945 8912
ab585dea 8913 if (is_lvds && has_reduced_clock)
c7653199 8914 crtc->lowfreq_avail = true;
bcd644e0 8915 else
c7653199 8916 crtc->lowfreq_avail = false;
e2b78267 8917
c8f7a0db 8918 return 0;
79e53945
JB		 8919}
8920
eb14cb74
VS		 8921static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8922 struct intel_link_m_n *m_n)
8923{
8924 struct drm_device *dev = crtc->base.dev;
8925 struct drm_i915_private *dev_priv = dev->dev_private;
8926 enum pipe pipe = crtc->pipe;
8927
8928 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8929 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8930 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8931 & ~TU_SIZE_MASK;
8932 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8933 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8934 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8935}
8936
8937static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8938 enum transcoder transcoder,
b95af8be
VK		 8939 struct intel_link_m_n *m_n,
8940 struct intel_link_m_n *m2_n2)
72419203
DV		 8941{
8942 struct drm_device *dev = crtc->base.dev;
8943 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8944 enum pipe pipe = crtc->pipe;
72419203 8945
eb14cb74
VS		 8946 if (INTEL_INFO(dev)->gen >= 5) {
8947 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8948 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8949 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8950 & ~TU_SIZE_MASK;
8951 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8952 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8953 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8954 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8955 * gen < 8) and if DRRS is supported (to make sure the
8956 * registers are not unnecessarily read).
8957 */
8958 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8959 crtc->config->has_drrs) {
b95af8be
VK		 8960 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8961 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8962 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8963 & ~TU_SIZE_MASK;
8964 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8965 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8966 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8967 }
eb14cb74
VS		 8968 } else {
8969 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8970 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8971 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8972 & ~TU_SIZE_MASK;
8973 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8974 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8975 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8976 }
8977}
8978
8979void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8980 struct intel_crtc_state *pipe_config)
eb14cb74 8981{
681a8504 8982 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8983 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8984 else
8985 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8986 &pipe_config->dp_m_n,
8987 &pipe_config->dp_m2_n2);
eb14cb74 8988}
72419203 8989
eb14cb74 8990static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8991 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8992{
8993 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8994 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8995}
8996
bd2e244f 8997static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8998 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8999{
9000 struct drm_device *dev = crtc->base.dev;
9001 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9002 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9003 uint32_t ps_ctrl = 0;
9004 int id = -1;
9005 int i;
bd2e244f 9006
a1b2278e
CK		 9007 /* find scaler attached to this pipe */
9008 for (i = 0; i < crtc->num_scalers; i++) {
9009 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9010 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9011 id = i;
9012 pipe_config->pch_pfit.enabled = true;
9013 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9014 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9015 break;
9016 }
9017 }
bd2e244f 9018
a1b2278e
CK		 9019 scaler_state->scaler_id = id;
9020 if (id >= 0) {
9021 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9022 } else {
9023 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9024 }
9025}
9026
5724dbd1
DL		 9027static void
9028skylake_get_initial_plane_config(struct intel_crtc *crtc,
9029 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9030{
9031 struct drm_device *dev = crtc->base.dev;
9032 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9033 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9034 int pipe = crtc->pipe;
9035 int fourcc, pixel_format;
6761dd31 9036 unsigned int aligned_height;
bc8d7dff 9037 struct drm_framebuffer *fb;
1b842c89 9038 struct intel_framebuffer *intel_fb;
bc8d7dff 9039
d9806c9f 9040 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9041 if (!intel_fb) {
bc8d7dff
DL		 9042 DRM_DEBUG_KMS("failed to alloc fb\n");
9043 return;
9044 }
9045
1b842c89
DL		 9046 fb = &intel_fb->base;
9047
bc8d7dff 9048 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9049 if (!(val & PLANE_CTL_ENABLE))
9050 goto error;
9051
bc8d7dff
DL		 9052 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9053 fourcc = skl_format_to_fourcc(pixel_format,
9054 val & PLANE_CTL_ORDER_RGBX,
9055 val & PLANE_CTL_ALPHA_MASK);
9056 fb->pixel_format = fourcc;
9057 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9058
40f46283
DL		 9059 tiling = val & PLANE_CTL_TILED_MASK;
9060 switch (tiling) {
9061 case PLANE_CTL_TILED_LINEAR:
9062 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9063 break;
9064 case PLANE_CTL_TILED_X:
9065 plane_config->tiling = I915_TILING_X;
9066 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9067 break;
9068 case PLANE_CTL_TILED_Y:
9069 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9070 break;
9071 case PLANE_CTL_TILED_YF:
9072 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9073 break;
9074 default:
9075 MISSING_CASE(tiling);
9076 goto error;
9077 }
9078
bc8d7dff
DL		 9079 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9080 plane_config->base = base;
9081
9082 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9083
9084 val = I915_READ(PLANE_SIZE(pipe, 0));
9085 fb->height = ((val >> 16) & 0xfff) + 1;
9086 fb->width = ((val >> 0) & 0x1fff) + 1;
9087
9088 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9089 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9090 fb->pixel_format);
bc8d7dff
DL		 9091 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9092
9093 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9094 fb->pixel_format,
9095 fb->modifier[0]);
bc8d7dff 9096
f37b5c2b 9097 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9098
9099 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9100 pipe_name(pipe), fb->width, fb->height,
9101 fb->bits_per_pixel, base, fb->pitches[0],
9102 plane_config->size);
9103
2d14030b 9104 plane_config->fb = intel_fb;
bc8d7dff
DL		 9105 return;
9106
9107error:
9108 kfree(fb);
9109}
9110
2fa2fe9a 9111static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9112 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9113{
9114 struct drm_device *dev = crtc->base.dev;
9115 struct drm_i915_private *dev_priv = dev->dev_private;
9116 uint32_t tmp;
9117
9118 tmp = I915_READ(PF_CTL(crtc->pipe));
9119
9120 if (tmp & PF_ENABLE) {
fd4daa9c 9121 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9122 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9123 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9124
9125 /* We currently do not free assignements of panel fitters on
9126 * ivb/hsw (since we don't use the higher upscaling modes which
9127 * differentiates them) so just WARN about this case for now. */
9128 if (IS_GEN7(dev)) {
9129 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9130 PF_PIPE_SEL_IVB(crtc->pipe));
9131 }
2fa2fe9a 9132 }
79e53945
JB		 9133}
9134
5724dbd1
DL		 9135static void
9136ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9137 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9138{
9139 struct drm_device *dev = crtc->base.dev;
9140 struct drm_i915_private *dev_priv = dev->dev_private;
9141 u32 val, base, offset;
aeee5a49 9142 int pipe = crtc->pipe;
4c6baa59 9143 int fourcc, pixel_format;
6761dd31 9144 unsigned int aligned_height;
b113d5ee 9145 struct drm_framebuffer *fb;
1b842c89 9146 struct intel_framebuffer *intel_fb;
4c6baa59 9147
42a7b088
DL		 9148 val = I915_READ(DSPCNTR(pipe));
9149 if (!(val & DISPLAY_PLANE_ENABLE))
9150 return;
9151
d9806c9f 9152 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9153 if (!intel_fb) {
4c6baa59
JB		 9154 DRM_DEBUG_KMS("failed to alloc fb\n");
9155 return;
9156 }
9157
1b842c89
DL		 9158 fb = &intel_fb->base;
9159
18c5247e
DV		 9160 if (INTEL_INFO(dev)->gen >= 4) {
9161 if (val & DISPPLANE_TILED) {
49af449b 9162 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9163 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9164 }
9165 }
4c6baa59
JB		 9166
9167 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9168 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9169 fb->pixel_format = fourcc;
9170 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9171
aeee5a49 9172 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9173 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9174 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9175 } else {
49af449b 9176 if (plane_config->tiling)
aeee5a49 9177 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9178 else
aeee5a49 9179 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9180 }
9181 plane_config->base = base;
9182
9183 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9184 fb->width = ((val >> 16) & 0xfff) + 1;
9185 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9186
9187 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9188 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9189
b113d5ee 9190 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9191 fb->pixel_format,
9192 fb->modifier[0]);
4c6baa59 9193
f37b5c2b 9194 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9195
2844a921
DL		 9196 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9197 pipe_name(pipe), fb->width, fb->height,
9198 fb->bits_per_pixel, base, fb->pitches[0],
9199 plane_config->size);
b113d5ee 9200
2d14030b 9201 plane_config->fb = intel_fb;
4c6baa59
JB		 9202}
9203
0e8ffe1b 9204static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9205 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9206{
9207 struct drm_device *dev = crtc->base.dev;
9208 struct drm_i915_private *dev_priv = dev->dev_private;
9209 uint32_t tmp;
9210
f458ebbc
DV		 9211 if (!intel_display_power_is_enabled(dev_priv,
9212 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9213 return false;
9214
e143a21c 9215 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9216 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9217
0e8ffe1b
DV		 9218 tmp = I915_READ(PIPECONF(crtc->pipe));
9219 if (!(tmp & PIPECONF_ENABLE))
9220 return false;
9221
42571aef
VS		 9222 switch (tmp & PIPECONF_BPC_MASK) {
9223 case PIPECONF_6BPC:
9224 pipe_config->pipe_bpp = 18;
9225 break;
9226 case PIPECONF_8BPC:
9227 pipe_config->pipe_bpp = 24;
9228 break;
9229 case PIPECONF_10BPC:
9230 pipe_config->pipe_bpp = 30;
9231 break;
9232 case PIPECONF_12BPC:
9233 pipe_config->pipe_bpp = 36;
9234 break;
9235 default:
9236 break;
9237 }
9238
b5a9fa09
DV		 9239 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9240 pipe_config->limited_color_range = true;
9241
ab9412ba 9242 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9243 struct intel_shared_dpll *pll;
9244
88adfff1
DV		 9245 pipe_config->has_pch_encoder = true;
9246
627eb5a3
DV		 9247 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9248 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9249 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9250
9251 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9252
c0d43d62 9253 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9254 pipe_config->shared_dpll =
9255 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9256 } else {
9257 tmp = I915_READ(PCH_DPLL_SEL);
9258 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9259 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9260 else
9261 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9262 }
66e985c0
DV		 9263
9264 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9265
9266 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9267 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9268
9269 tmp = pipe_config->dpll_hw_state.dpll;
9270 pipe_config->pixel_multiplier =
9271 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9272 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9273
9274 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9275 } else {
9276 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9277 }
9278
1bd1bd80
DV		 9279 intel_get_pipe_timings(crtc, pipe_config);
9280
2fa2fe9a
DV		 9281 ironlake_get_pfit_config(crtc, pipe_config);
9282
0e8ffe1b
DV		 9283 return true;
9284}
9285
be256dc7
PZ		 9286static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9287{
9288 struct drm_device *dev = dev_priv->dev;
be256dc7 9289 struct intel_crtc *crtc;
be256dc7 9290
d3fcc808 9291 for_each_intel_crtc(dev, crtc)
e2c719b7 9292 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9293 pipe_name(crtc->pipe));
9294
e2c719b7
RC		 9295 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9296 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9297 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9298 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9299 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9300 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9301 "CPU PWM1 enabled\n");
c5107b87 9302 if (IS_HASWELL(dev))
e2c719b7 9303 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9304 "CPU PWM2 enabled\n");
e2c719b7 9305 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9306 "PCH PWM1 enabled\n");
e2c719b7 9307 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9308 "Utility pin enabled\n");
e2c719b7 9309 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9310
9926ada1
PZ		 9311 /*
9312 * In theory we can still leave IRQs enabled, as long as only the HPD
9313 * interrupts remain enabled. We used to check for that, but since it's
9314 * gen-specific and since we only disable LCPLL after we fully disable
9315 * the interrupts, the check below should be enough.
9316 */
e2c719b7 9317 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9318}
9319
9ccd5aeb
PZ		 9320static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9321{
9322 struct drm_device *dev = dev_priv->dev;
9323
9324 if (IS_HASWELL(dev))
9325 return I915_READ(D_COMP_HSW);
9326 else
9327 return I915_READ(D_COMP_BDW);
9328}
9329
3c4c9b81
PZ		 9330static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9331{
9332 struct drm_device *dev = dev_priv->dev;
9333
9334 if (IS_HASWELL(dev)) {
9335 mutex_lock(&dev_priv->rps.hw_lock);
9336 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9337 val))
f475dadf 9338 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9339 mutex_unlock(&dev_priv->rps.hw_lock);
9340 } else {
9ccd5aeb
PZ		 9341 I915_WRITE(D_COMP_BDW, val);
9342 POSTING_READ(D_COMP_BDW);
3c4c9b81 9343 }
be256dc7
PZ		 9344}
9345
9346/*
9347 * This function implements pieces of two sequences from BSpec:
9348 * - Sequence for display software to disable LCPLL
9349 * - Sequence for display software to allow package C8+
9350 * The steps implemented here are just the steps that actually touch the LCPLL
9351 * register. Callers should take care of disabling all the display engine
9352 * functions, doing the mode unset, fixing interrupts, etc.
9353 */
6ff58d53
PZ		 9354static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9355 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9356{
9357 uint32_t val;
9358
9359 assert_can_disable_lcpll(dev_priv);
9360
9361 val = I915_READ(LCPLL_CTL);
9362
9363 if (switch_to_fclk) {
9364 val |= LCPLL_CD_SOURCE_FCLK;
9365 I915_WRITE(LCPLL_CTL, val);
9366
9367 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9368 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9369 DRM_ERROR("Switching to FCLK failed\n");
9370
9371 val = I915_READ(LCPLL_CTL);
9372 }
9373
9374 val |= LCPLL_PLL_DISABLE;
9375 I915_WRITE(LCPLL_CTL, val);
9376 POSTING_READ(LCPLL_CTL);
9377
9378 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9379 DRM_ERROR("LCPLL still locked\n");
9380
9ccd5aeb 9381 val = hsw_read_dcomp(dev_priv);
be256dc7 9382 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9383 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9384 ndelay(100);
9385
9ccd5aeb
PZ		 9386 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9387 1))
be256dc7
PZ		 9388 DRM_ERROR("D_COMP RCOMP still in progress\n");
9389
9390 if (allow_power_down) {
9391 val = I915_READ(LCPLL_CTL);
9392 val |= LCPLL_POWER_DOWN_ALLOW;
9393 I915_WRITE(LCPLL_CTL, val);
9394 POSTING_READ(LCPLL_CTL);
9395 }
9396}
9397
9398/*
9399 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9400 * source.
9401 */
6ff58d53 9402static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9403{
9404 uint32_t val;
9405
9406 val = I915_READ(LCPLL_CTL);
9407
9408 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9409 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9410 return;
9411
a8a8bd54
PZ		 9412 /*
9413 * Make sure we're not on PC8 state before disabling PC8, otherwise
9414 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9415 */
59bad947 9416 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9417
be256dc7
PZ		 9418 if (val & LCPLL_POWER_DOWN_ALLOW) {
9419 val &= ~LCPLL_POWER_DOWN_ALLOW;
9420 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9421 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9422 }
9423
9ccd5aeb 9424 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9425 val |= D_COMP_COMP_FORCE;
9426 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9427 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9428
9429 val = I915_READ(LCPLL_CTL);
9430 val &= ~LCPLL_PLL_DISABLE;
9431 I915_WRITE(LCPLL_CTL, val);
9432
9433 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9434 DRM_ERROR("LCPLL not locked yet\n");
9435
9436 if (val & LCPLL_CD_SOURCE_FCLK) {
9437 val = I915_READ(LCPLL_CTL);
9438 val &= ~LCPLL_CD_SOURCE_FCLK;
9439 I915_WRITE(LCPLL_CTL, val);
9440
9441 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9442 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9443 DRM_ERROR("Switching back to LCPLL failed\n");
9444 }
215733fa 9445
59bad947 9446 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9447 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9448}
9449
765dab67
PZ		 9450/*
9451 * Package states C8 and deeper are really deep PC states that can only be
9452 * reached when all the devices on the system allow it, so even if the graphics
9453 * device allows PC8+, it doesn't mean the system will actually get to these
9454 * states. Our driver only allows PC8+ when going into runtime PM.
9455 *
9456 * The requirements for PC8+ are that all the outputs are disabled, the power
9457 * well is disabled and most interrupts are disabled, and these are also
9458 * requirements for runtime PM. When these conditions are met, we manually do
9459 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9460 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9461 * hang the machine.
9462 *
9463 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9464 * the state of some registers, so when we come back from PC8+ we need to
9465 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9466 * need to take care of the registers kept by RC6. Notice that this happens even
9467 * if we don't put the device in PCI D3 state (which is what currently happens
9468 * because of the runtime PM support).
9469 *
9470 * For more, read "Display Sequences for Package C8" on the hardware
9471 * documentation.
9472 */
a14cb6fc 9473void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9474{
c67a470b
PZ		 9475 struct drm_device *dev = dev_priv->dev;
9476 uint32_t val;
9477
c67a470b
PZ		 9478 DRM_DEBUG_KMS("Enabling package C8+\n");
9479
c2699524 9480 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9481 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9482 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9483 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9484 }
9485
9486 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9487 hsw_disable_lcpll(dev_priv, true, true);
9488}
9489
a14cb6fc 9490void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9491{
9492 struct drm_device *dev = dev_priv->dev;
9493 uint32_t val;
9494
c67a470b
PZ		 9495 DRM_DEBUG_KMS("Disabling package C8+\n");
9496
9497 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9498 lpt_init_pch_refclk(dev);
9499
c2699524 9500 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9501 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9502 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9503 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9504 }
9505
9506 intel_prepare_ddi(dev);
c67a470b
PZ		 9507}
9508
27c329ed 9509static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9510{
a821fc46 9511 struct drm_device *dev = old_state->dev;
27c329ed 9512 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9513
27c329ed 9514 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9515}
9516
b432e5cf 9517/* compute the max rate for new configuration */
27c329ed 9518static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9519{
b432e5cf 9520 struct intel_crtc *intel_crtc;
27c329ed 9521 struct intel_crtc_state *crtc_state;
b432e5cf 9522 int max_pixel_rate = 0;
b432e5cf 9523
27c329ed
ML		 9524 for_each_intel_crtc(state->dev, intel_crtc) {
9525 int pixel_rate;
9526
9527 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9528 if (IS_ERR(crtc_state))
9529 return PTR_ERR(crtc_state);
9530
9531 if (!crtc_state->base.enable)
b432e5cf
VS		 9532 continue;
9533
27c329ed 9534 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9535
9536 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9537 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9538 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9539
9540 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9541 }
9542
9543 return max_pixel_rate;
9544}
9545
9546static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9547{
9548 struct drm_i915_private *dev_priv = dev->dev_private;
9549 uint32_t val, data;
9550 int ret;
9551
9552 if (WARN((I915_READ(LCPLL_CTL) &
9553 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9554 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9555 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9556 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9557 "trying to change cdclk frequency with cdclk not enabled\n"))
9558 return;
9559
9560 mutex_lock(&dev_priv->rps.hw_lock);
9561 ret = sandybridge_pcode_write(dev_priv,
9562 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9563 mutex_unlock(&dev_priv->rps.hw_lock);
9564 if (ret) {
9565 DRM_ERROR("failed to inform pcode about cdclk change\n");
9566 return;
9567 }
9568
9569 val = I915_READ(LCPLL_CTL);
9570 val |= LCPLL_CD_SOURCE_FCLK;
9571 I915_WRITE(LCPLL_CTL, val);
9572
9573 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9574 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9575 DRM_ERROR("Switching to FCLK failed\n");
9576
9577 val = I915_READ(LCPLL_CTL);
9578 val &= ~LCPLL_CLK_FREQ_MASK;
9579
9580 switch (cdclk) {
9581 case 450000:
9582 val |= LCPLL_CLK_FREQ_450;
9583 data = 0;
9584 break;
9585 case 540000:
9586 val |= LCPLL_CLK_FREQ_54O_BDW;
9587 data = 1;
9588 break;
9589 case 337500:
9590 val |= LCPLL_CLK_FREQ_337_5_BDW;
9591 data = 2;
9592 break;
9593 case 675000:
9594 val |= LCPLL_CLK_FREQ_675_BDW;
9595 data = 3;
9596 break;
9597 default:
9598 WARN(1, "invalid cdclk frequency\n");
9599 return;
9600 }
9601
9602 I915_WRITE(LCPLL_CTL, val);
9603
9604 val = I915_READ(LCPLL_CTL);
9605 val &= ~LCPLL_CD_SOURCE_FCLK;
9606 I915_WRITE(LCPLL_CTL, val);
9607
9608 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9609 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9610 DRM_ERROR("Switching back to LCPLL failed\n");
9611
9612 mutex_lock(&dev_priv->rps.hw_lock);
9613 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9614 mutex_unlock(&dev_priv->rps.hw_lock);
9615
9616 intel_update_cdclk(dev);
9617
9618 WARN(cdclk != dev_priv->cdclk_freq,
9619 "cdclk requested %d kHz but got %d kHz\n",
9620 cdclk, dev_priv->cdclk_freq);
9621}
9622
27c329ed 9623static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9624{
27c329ed
ML		 9625 struct drm_i915_private *dev_priv = to_i915(state->dev);
9626 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9627 int cdclk;
9628
9629 /*
9630 * FIXME should also account for plane ratio
9631 * once 64bpp pixel formats are supported.
9632 */
27c329ed 9633 if (max_pixclk > 540000)
b432e5cf 9634 cdclk = 675000;
27c329ed 9635 else if (max_pixclk > 450000)
b432e5cf 9636 cdclk = 540000;
27c329ed 9637 else if (max_pixclk > 337500)
b432e5cf
VS		 9638 cdclk = 450000;
9639 else
9640 cdclk = 337500;
9641
9642 /*
9643 * FIXME move the cdclk caclulation to
9644 * compute_config() so we can fail gracegully.
9645 */
9646 if (cdclk > dev_priv->max_cdclk_freq) {
9647 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9648 cdclk, dev_priv->max_cdclk_freq);
9649 cdclk = dev_priv->max_cdclk_freq;
9650 }
9651
27c329ed 9652 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9653
9654 return 0;
9655}
9656
27c329ed 9657static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9658{
27c329ed
ML		 9659 struct drm_device *dev = old_state->dev;
9660 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9661
27c329ed 9662 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9663}
9664
190f68c5
ACO		 9665static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9666 struct intel_crtc_state *crtc_state)
09b4ddf9 9667{
190f68c5 9668 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9669 return -EINVAL;
716c2e55 9670
c7653199 9671 crtc->lowfreq_avail = false;
644cef34 9672
c8f7a0db 9673 return 0;
79e53945
JB		 9674}
9675
3760b59c
S		 9676static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9677 enum port port,
9678 struct intel_crtc_state *pipe_config)
9679{
9680 switch (port) {
9681 case PORT_A:
9682 pipe_config->ddi_pll_sel = SKL_DPLL0;
9683 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9684 break;
9685 case PORT_B:
9686 pipe_config->ddi_pll_sel = SKL_DPLL1;
9687 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9688 break;
9689 case PORT_C:
9690 pipe_config->ddi_pll_sel = SKL_DPLL2;
9691 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9692 break;
9693 default:
9694 DRM_ERROR("Incorrect port type\n");
9695 }
9696}
9697
96b7dfb7
S		 9698static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9699 enum port port,
5cec258b 9700 struct intel_crtc_state *pipe_config)
96b7dfb7 9701{
3148ade7 9702 u32 temp, dpll_ctl1;
96b7dfb7
S		 9703
9704 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9705 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9706
9707 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9708 case SKL_DPLL0:
9709 /*
9710 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9711 * of the shared DPLL framework and thus needs to be read out
9712 * separately
9713 */
9714 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9715 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9716 break;
96b7dfb7
S		 9717 case SKL_DPLL1:
9718 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9719 break;
9720 case SKL_DPLL2:
9721 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9722 break;
9723 case SKL_DPLL3:
9724 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9725 break;
96b7dfb7
S		 9726 }
9727}
9728
7d2c8175
DL		 9729static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9730 enum port port,
5cec258b 9731 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9732{
9733 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9734
9735 switch (pipe_config->ddi_pll_sel) {
9736 case PORT_CLK_SEL_WRPLL1:
9737 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9738 break;
9739 case PORT_CLK_SEL_WRPLL2:
9740 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9741 break;
9742 }
9743}
9744
26804afd 9745static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9746 struct intel_crtc_state *pipe_config)
26804afd
DV		 9747{
9748 struct drm_device *dev = crtc->base.dev;
9749 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9750 struct intel_shared_dpll *pll;
26804afd
DV		 9751 enum port port;
9752 uint32_t tmp;
9753
9754 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9755
9756 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9757
96b7dfb7
S		 9758 if (IS_SKYLAKE(dev))
9759 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9760 else if (IS_BROXTON(dev))
9761 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9762 else
9763 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9764
d452c5b6
DV		 9765 if (pipe_config->shared_dpll >= 0) {
9766 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9767
9768 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9769 &pipe_config->dpll_hw_state));
9770 }
9771
26804afd
DV		 9772 /*
9773 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9774 * DDI E. So just check whether this pipe is wired to DDI E and whether
9775 * the PCH transcoder is on.
9776 */
ca370455
DL		 9777 if (INTEL_INFO(dev)->gen < 9 &&
9778 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9779 pipe_config->has_pch_encoder = true;
9780
9781 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9782 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9783 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9784
9785 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9786 }
9787}
9788
0e8ffe1b 9789static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9790 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9791{
9792 struct drm_device *dev = crtc->base.dev;
9793 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9794 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9795 uint32_t tmp;
9796
f458ebbc 9797 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9798 POWER_DOMAIN_PIPE(crtc->pipe)))
9799 return false;
9800
e143a21c 9801 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9802 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9803
eccb140b
DV		 9804 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9805 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9806 enum pipe trans_edp_pipe;
9807 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9808 default:
9809 WARN(1, "unknown pipe linked to edp transcoder\n");
9810 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9811 case TRANS_DDI_EDP_INPUT_A_ON:
9812 trans_edp_pipe = PIPE_A;
9813 break;
9814 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9815 trans_edp_pipe = PIPE_B;
9816 break;
9817 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9818 trans_edp_pipe = PIPE_C;
9819 break;
9820 }
9821
9822 if (trans_edp_pipe == crtc->pipe)
9823 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9824 }
9825
f458ebbc 9826 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9827 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9828 return false;
9829
eccb140b 9830 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9831 if (!(tmp & PIPECONF_ENABLE))
9832 return false;
9833
26804afd 9834 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9835
1bd1bd80
DV		 9836 intel_get_pipe_timings(crtc, pipe_config);
9837
a1b2278e
CK		 9838 if (INTEL_INFO(dev)->gen >= 9) {
9839 skl_init_scalers(dev, crtc, pipe_config);
9840 }
9841
2fa2fe9a 9842 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9843
9844 if (INTEL_INFO(dev)->gen >= 9) {
9845 pipe_config->scaler_state.scaler_id = -1;
9846 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9847 }
9848
bd2e244f 9849 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
1c132b44 9850 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 9851 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9852 else
1c132b44 9853 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 9854 }
88adfff1 9855
e59150dc
JB		 9856 if (IS_HASWELL(dev))
9857 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9858 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9859
ebb69c95
CT		 9860 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9861 pipe_config->pixel_multiplier =
9862 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9863 } else {
9864 pipe_config->pixel_multiplier = 1;
9865 }
6c49f241 9866
0e8ffe1b
DV		 9867 return true;
9868}
9869
560b85bb
CW		 9870static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9871{
9872 struct drm_device *dev = crtc->dev;
9873 struct drm_i915_private *dev_priv = dev->dev_private;
9874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9875 uint32_t cntl = 0, size = 0;
560b85bb 9876
dc41c154 9877 if (base) {
3dd512fb
MR		 9878 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9879 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9880 unsigned int stride = roundup_pow_of_two(width) * 4;
9881
9882 switch (stride) {
9883 default:
9884 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9885 width, stride);
9886 stride = 256;
9887 /* fallthrough */
9888 case 256:
9889 case 512:
9890 case 1024:
9891 case 2048:
9892 break;
4b0e333e
CW		 9893 }
9894
dc41c154
VS		 9895 cntl |= CURSOR_ENABLE |
9896 CURSOR_GAMMA_ENABLE |
9897 CURSOR_FORMAT_ARGB |
9898 CURSOR_STRIDE(stride);
9899
9900 size = (height << 12) | width;
4b0e333e 9901 }
560b85bb 9902
dc41c154
VS		 9903 if (intel_crtc->cursor_cntl != 0 &&
9904 (intel_crtc->cursor_base != base ||
9905 intel_crtc->cursor_size != size ||
9906 intel_crtc->cursor_cntl != cntl)) {
9907 /* On these chipsets we can only modify the base/size/stride
9908 * whilst the cursor is disabled.
9909 */
0b87c24e
VS		 9910 I915_WRITE(CURCNTR(PIPE_A), 0);
9911 POSTING_READ(CURCNTR(PIPE_A));
dc41c154 9912 intel_crtc->cursor_cntl = 0;
4b0e333e 9913 }
560b85bb 9914
99d1f387 9915 if (intel_crtc->cursor_base != base) {
0b87c24e 9916 I915_WRITE(CURBASE(PIPE_A), base);
99d1f387
VS		 9917 intel_crtc->cursor_base = base;
9918 }
4726e0b0 9919
dc41c154
VS		 9920 if (intel_crtc->cursor_size != size) {
9921 I915_WRITE(CURSIZE, size);
9922 intel_crtc->cursor_size = size;
4b0e333e 9923 }
560b85bb 9924
4b0e333e 9925 if (intel_crtc->cursor_cntl != cntl) {
0b87c24e
VS		 9926 I915_WRITE(CURCNTR(PIPE_A), cntl);
9927 POSTING_READ(CURCNTR(PIPE_A));
4b0e333e 9928 intel_crtc->cursor_cntl = cntl;
560b85bb 9929 }
560b85bb
CW		 9930}
9931
560b85bb 9932static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9933{
9934 struct drm_device *dev = crtc->dev;
9935 struct drm_i915_private *dev_priv = dev->dev_private;
9936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9937 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9938 uint32_t cntl;
9939
9940 cntl = 0;
9941 if (base) {
9942 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9943 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9944 case 64:
9945 cntl |= CURSOR_MODE_64_ARGB_AX;
9946 break;
9947 case 128:
9948 cntl |= CURSOR_MODE_128_ARGB_AX;
9949 break;
9950 case 256:
9951 cntl |= CURSOR_MODE_256_ARGB_AX;
9952 break;
9953 default:
3dd512fb 9954 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9955 return;
65a21cd6 9956 }
4b0e333e 9957 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9958
9959 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9960 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9961 }
65a21cd6 9962
8e7d688b 9963 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9964 cntl |= CURSOR_ROTATE_180;
9965
4b0e333e
CW		 9966 if (intel_crtc->cursor_cntl != cntl) {
9967 I915_WRITE(CURCNTR(pipe), cntl);
9968 POSTING_READ(CURCNTR(pipe));
9969 intel_crtc->cursor_cntl = cntl;
65a21cd6 9970 }
4b0e333e 9971
65a21cd6 9972 /* and commit changes on next vblank */
5efb3e28
VS		 9973 I915_WRITE(CURBASE(pipe), base);
9974 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9975
9976 intel_crtc->cursor_base = base;
65a21cd6
JB		 9977}
9978
cda4b7d3 9979/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9980static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9981 bool on)
cda4b7d3
CW		 9982{
9983 struct drm_device *dev = crtc->dev;
9984 struct drm_i915_private *dev_priv = dev->dev_private;
9985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9986 int pipe = intel_crtc->pipe;
9b4101be
ML		 9987 struct drm_plane_state *cursor_state = crtc->cursor->state;
9988 int x = cursor_state->crtc_x;
9989 int y = cursor_state->crtc_y;
d6e4db15 9990 u32 base = 0, pos = 0;
cda4b7d3 9991
d6e4db15 9992 if (on)
cda4b7d3 9993 base = intel_crtc->cursor_addr;
cda4b7d3 9994
6e3c9717 9995 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9996 base = 0;
9997
6e3c9717 9998 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9999 base = 0;
10000
10001 if (x < 0) {
9b4101be 10002 if (x + cursor_state->crtc_w <= 0)
cda4b7d3
CW		 10003 base = 0;
10004
10005 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10006 x = -x;
10007 }
10008 pos |= x << CURSOR_X_SHIFT;
10009
10010 if (y < 0) {
9b4101be 10011 if (y + cursor_state->crtc_h <= 0)
cda4b7d3
CW		 10012 base = 0;
10013
10014 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10015 y = -y;
10016 }
10017 pos |= y << CURSOR_Y_SHIFT;
10018
4b0e333e 10019 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10020 return;
10021
5efb3e28
VS		 10022 I915_WRITE(CURPOS(pipe), pos);
10023
4398ad45
VS		 10024 /* ILK+ do this automagically */
10025 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10026 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9b4101be
ML		 10027 base += (cursor_state->crtc_h *
10028 cursor_state->crtc_w - 1) * 4;
4398ad45
VS		 10029 }
10030
8ac54669 10031 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10032 i845_update_cursor(crtc, base);
10033 else
10034 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10035}
10036
dc41c154
VS		 10037static bool cursor_size_ok(struct drm_device *dev,
10038 uint32_t width, uint32_t height)
10039{
10040 if (width == 0 || height == 0)
10041 return false;
10042
10043 /*
10044 * 845g/865g are special in that they are only limited by
10045 * the width of their cursors, the height is arbitrary up to
10046 * the precision of the register. Everything else requires
10047 * square cursors, limited to a few power-of-two sizes.
10048 */
10049 if (IS_845G(dev) || IS_I865G(dev)) {
10050 if ((width & 63) != 0)
10051 return false;
10052
10053 if (width > (IS_845G(dev) ? 64 : 512))
10054 return false;
10055
10056 if (height > 1023)
10057 return false;
10058 } else {
10059 switch (width | height) {
10060 case 256:
10061 case 128:
10062 if (IS_GEN2(dev))
10063 return false;
10064 case 64:
10065 break;
10066 default:
10067 return false;
10068 }
10069 }
10070
10071 return true;
10072}
10073
79e53945 10074static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10075 u16 *blue, uint32_t start, uint32_t size)
79e53945 10076{
7203425a 10077 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10079
7203425a 10080 for (i = start; i < end; i++) {
79e53945
JB		 10081 intel_crtc->lut_r[i] = red[i] >> 8;
10082 intel_crtc->lut_g[i] = green[i] >> 8;
10083 intel_crtc->lut_b[i] = blue[i] >> 8;
10084 }
10085
10086 intel_crtc_load_lut(crtc);
10087}
10088
79e53945
JB		 10089/* VESA 640x480x72Hz mode to set on the pipe */
10090static struct drm_display_mode load_detect_mode = {
10091 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10092 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10093};
10094
a8bb6818
DV		 10095struct drm_framebuffer *
10096__intel_framebuffer_create(struct drm_device *dev,
10097 struct drm_mode_fb_cmd2 *mode_cmd,
10098 struct drm_i915_gem_object *obj)
d2dff872
CW		 10099{
10100 struct intel_framebuffer *intel_fb;
10101 int ret;
10102
10103 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10104 if (!intel_fb) {
6ccb81f2 10105 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10106 return ERR_PTR(-ENOMEM);
10107 }
10108
10109 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10110 if (ret)
10111 goto err;
d2dff872
CW		 10112
10113 return &intel_fb->base;
dd4916c5 10114err:
6ccb81f2 10115 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10116 kfree(intel_fb);
10117
10118 return ERR_PTR(ret);
d2dff872
CW		 10119}
10120
b5ea642a 10121static struct drm_framebuffer *
a8bb6818
DV		 10122intel_framebuffer_create(struct drm_device *dev,
10123 struct drm_mode_fb_cmd2 *mode_cmd,
10124 struct drm_i915_gem_object *obj)
10125{
10126 struct drm_framebuffer *fb;
10127 int ret;
10128
10129 ret = i915_mutex_lock_interruptible(dev);
10130 if (ret)
10131 return ERR_PTR(ret);
10132 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10133 mutex_unlock(&dev->struct_mutex);
10134
10135 return fb;
10136}
10137
d2dff872
CW		 10138static u32
10139intel_framebuffer_pitch_for_width(int width, int bpp)
10140{
10141 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10142 return ALIGN(pitch, 64);
10143}
10144
10145static u32
10146intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10147{
10148 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10149 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10150}
10151
10152static struct drm_framebuffer *
10153intel_framebuffer_create_for_mode(struct drm_device *dev,
10154 struct drm_display_mode *mode,
10155 int depth, int bpp)
10156{
10157 struct drm_i915_gem_object *obj;
0fed39bd 10158 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10159
10160 obj = i915_gem_alloc_object(dev,
10161 intel_framebuffer_size_for_mode(mode, bpp));
10162 if (obj == NULL)
10163 return ERR_PTR(-ENOMEM);
10164
10165 mode_cmd.width = mode->hdisplay;
10166 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10167 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10168 bpp);
5ca0c34a 10169 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10170
10171 return intel_framebuffer_create(dev, &mode_cmd, obj);
10172}
10173
10174static struct drm_framebuffer *
10175mode_fits_in_fbdev(struct drm_device *dev,
10176 struct drm_display_mode *mode)
10177{
0695726e 10178#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10179 struct drm_i915_private *dev_priv = dev->dev_private;
10180 struct drm_i915_gem_object *obj;
10181 struct drm_framebuffer *fb;
10182
4c0e5528 10183 if (!dev_priv->fbdev)
d2dff872
CW		 10184 return NULL;
10185
4c0e5528 10186 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10187 return NULL;
10188
4c0e5528
DV		 10189 obj = dev_priv->fbdev->fb->obj;
10190 BUG_ON(!obj);
10191
8bcd4553 10192 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10193 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10194 fb->bits_per_pixel))
d2dff872
CW		 10195 return NULL;
10196
01f2c773 10197 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10198 return NULL;
10199
10200 return fb;
4520f53a
DV		 10201#else
10202 return NULL;
10203#endif
d2dff872
CW		 10204}
10205
d3a40d1b
ACO		 10206static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10207 struct drm_crtc *crtc,
10208 struct drm_display_mode *mode,
10209 struct drm_framebuffer *fb,
10210 int x, int y)
10211{
10212 struct drm_plane_state *plane_state;
10213 int hdisplay, vdisplay;
10214 int ret;
10215
10216 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10217 if (IS_ERR(plane_state))
10218 return PTR_ERR(plane_state);
10219
10220 if (mode)
10221 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10222 else
10223 hdisplay = vdisplay = 0;
10224
10225 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10226 if (ret)
10227 return ret;
10228 drm_atomic_set_fb_for_plane(plane_state, fb);
10229 plane_state->crtc_x = 0;
10230 plane_state->crtc_y = 0;
10231 plane_state->crtc_w = hdisplay;
10232 plane_state->crtc_h = vdisplay;
10233 plane_state->src_x = x << 16;
10234 plane_state->src_y = y << 16;
10235 plane_state->src_w = hdisplay << 16;
10236 plane_state->src_h = vdisplay << 16;
10237
10238 return 0;
10239}
10240
d2434ab7 10241bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10242 struct drm_display_mode *mode,
51fd371b
RC		 10243 struct intel_load_detect_pipe *old,
10244 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10245{
10246 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10247 struct intel_encoder *intel_encoder =
10248 intel_attached_encoder(connector);
79e53945 10249 struct drm_crtc *possible_crtc;
4ef69c7a 10250 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10251 struct drm_crtc *crtc = NULL;
10252 struct drm_device *dev = encoder->dev;
94352cf9 10253 struct drm_framebuffer *fb;
51fd371b 10254 struct drm_mode_config *config = &dev->mode_config;
83a57153 10255 struct drm_atomic_state *state = NULL;
944b0c76 10256 struct drm_connector_state *connector_state;
4be07317 10257 struct intel_crtc_state *crtc_state;
51fd371b 10258 int ret, i = -1;
79e53945 10259
d2dff872 10260 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10261 connector->base.id, connector->name,
8e329a03 10262 encoder->base.id, encoder->name);
d2dff872 10263
51fd371b
RC		 10264retry:
10265 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10266 if (ret)
ad3c558f 10267 goto fail;
6e9f798d 10268
79e53945
JB		 10269 /*
10270 * Algorithm gets a little messy:
7a5e4805 10271 *
79e53945
JB		 10272 * - if the connector already has an assigned crtc, use it (but make
10273 * sure it's on first)
7a5e4805 10274 *
79e53945
JB		 10275 * - try to find the first unused crtc that can drive this connector,
10276 * and use that if we find one
79e53945
JB		 10277 */
10278
10279 /* See if we already have a CRTC for this connector */
10280 if (encoder->crtc) {
10281 crtc = encoder->crtc;
8261b191 10282
51fd371b 10283 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10284 if (ret)
ad3c558f 10285 goto fail;
4d02e2de 10286 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10287 if (ret)
ad3c558f 10288 goto fail;
7b24056b 10289
24218aac 10290 old->dpms_mode = connector->dpms;
8261b191
CW		 10291 old->load_detect_temp = false;
10292
10293 /* Make sure the crtc and connector are running */
24218aac
DV		 10294 if (connector->dpms != DRM_MODE_DPMS_ON)
10295 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10296
7173188d 10297 return true;
79e53945
JB		 10298 }
10299
10300 /* Find an unused one (if possible) */
70e1e0ec 10301 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10302 i++;
10303 if (!(encoder->possible_crtcs & (1 << i)))
10304 continue;
83d65738 10305 if (possible_crtc->state->enable)
a459249c 10306 continue;
a459249c
VS		 10307
10308 crtc = possible_crtc;
10309 break;
79e53945
JB		 10310 }
10311
10312 /*
10313 * If we didn't find an unused CRTC, don't use any.
10314 */
10315 if (!crtc) {
7173188d 10316 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10317 goto fail;
79e53945
JB		 10318 }
10319
51fd371b
RC		 10320 ret = drm_modeset_lock(&crtc->mutex, ctx);
10321 if (ret)
ad3c558f 10322 goto fail;
4d02e2de
DV		 10323 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10324 if (ret)
ad3c558f 10325 goto fail;
79e53945
JB		 10326
10327 intel_crtc = to_intel_crtc(crtc);
24218aac 10328 old->dpms_mode = connector->dpms;
8261b191 10329 old->load_detect_temp = true;
d2dff872 10330 old->release_fb = NULL;
79e53945 10331
83a57153
ACO		 10332 state = drm_atomic_state_alloc(dev);
10333 if (!state)
10334 return false;
10335
10336 state->acquire_ctx = ctx;
10337
944b0c76
ACO		 10338 connector_state = drm_atomic_get_connector_state(state, connector);
10339 if (IS_ERR(connector_state)) {
10340 ret = PTR_ERR(connector_state);
10341 goto fail;
10342 }
10343
10344 connector_state->crtc = crtc;
10345 connector_state->best_encoder = &intel_encoder->base;
10346
4be07317
ACO		 10347 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10348 if (IS_ERR(crtc_state)) {
10349 ret = PTR_ERR(crtc_state);
10350 goto fail;
10351 }
10352
49d6fa21 10353 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10354
6492711d
CW		 10355 if (!mode)
10356 mode = &load_detect_mode;
79e53945 10357
d2dff872
CW		 10358 /* We need a framebuffer large enough to accommodate all accesses
10359 * that the plane may generate whilst we perform load detection.
10360 * We can not rely on the fbcon either being present (we get called
10361 * during its initialisation to detect all boot displays, or it may
10362 * not even exist) or that it is large enough to satisfy the
10363 * requested mode.
10364 */
94352cf9
DV		 10365 fb = mode_fits_in_fbdev(dev, mode);
10366 if (fb == NULL) {
d2dff872 10367 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10368 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10369 old->release_fb = fb;
d2dff872
CW		 10370 } else
10371 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10372 if (IS_ERR(fb)) {
d2dff872 10373 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10374 goto fail;
79e53945 10375 }
79e53945 10376
d3a40d1b
ACO		 10377 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10378 if (ret)
10379 goto fail;
10380
8c7b5ccb
ACO		 10381 drm_mode_copy(&crtc_state->base.mode, mode);
10382
74c090b1 10383 if (drm_atomic_commit(state)) {
6492711d 10384 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10385 if (old->release_fb)
10386 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10387 goto fail;
79e53945 10388 }
9128b040 10389 crtc->primary->crtc = crtc;
7173188d 10390
79e53945 10391 /* let the connector get through one full cycle before testing */
9d0498a2 10392 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10393 return true;
412b61d8 10394
ad3c558f 10395fail:
e5d958ef
ACO		 10396 drm_atomic_state_free(state);
10397 state = NULL;
83a57153 10398
51fd371b
RC		 10399 if (ret == -EDEADLK) {
10400 drm_modeset_backoff(ctx);
10401 goto retry;
10402 }
10403
412b61d8 10404 return false;
79e53945
JB		 10405}
10406
d2434ab7 10407void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10408 struct intel_load_detect_pipe *old,
10409 struct drm_modeset_acquire_ctx *ctx)
79e53945 10410{
83a57153 10411 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10412 struct intel_encoder *intel_encoder =
10413 intel_attached_encoder(connector);
4ef69c7a 10414 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10415 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10417 struct drm_atomic_state *state;
944b0c76 10418 struct drm_connector_state *connector_state;
4be07317 10419 struct intel_crtc_state *crtc_state;
d3a40d1b 10420 int ret;
79e53945 10421
d2dff872 10422 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10423 connector->base.id, connector->name,
8e329a03 10424 encoder->base.id, encoder->name);
d2dff872 10425
8261b191 10426 if (old->load_detect_temp) {
83a57153 10427 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10428 if (!state)
10429 goto fail;
83a57153
ACO		 10430
10431 state->acquire_ctx = ctx;
10432
944b0c76
ACO		 10433 connector_state = drm_atomic_get_connector_state(state, connector);
10434 if (IS_ERR(connector_state))
10435 goto fail;
10436
4be07317
ACO		 10437 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10438 if (IS_ERR(crtc_state))
10439 goto fail;
10440
944b0c76
ACO		 10441 connector_state->best_encoder = NULL;
10442 connector_state->crtc = NULL;
10443
49d6fa21 10444 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10445
d3a40d1b
ACO		 10446 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10447 0, 0);
10448 if (ret)
10449 goto fail;
10450
74c090b1 10451 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10452 if (ret)
10453 goto fail;
d2dff872 10454
36206361
DV		 10455 if (old->release_fb) {
10456 drm_framebuffer_unregister_private(old->release_fb);
10457 drm_framebuffer_unreference(old->release_fb);
10458 }
d2dff872 10459
0622a53c 10460 return;
79e53945
JB		 10461 }
10462
c751ce4f 10463 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10464 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10465 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10466
10467 return;
10468fail:
10469 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10470 drm_atomic_state_free(state);
79e53945
JB		 10471}
10472
da4a1efa 10473static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10474 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10475{
10476 struct drm_i915_private *dev_priv = dev->dev_private;
10477 u32 dpll = pipe_config->dpll_hw_state.dpll;
10478
10479 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10480 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10481 else if (HAS_PCH_SPLIT(dev))
10482 return 120000;
10483 else if (!IS_GEN2(dev))
10484 return 96000;
10485 else
10486 return 48000;
10487}
10488
79e53945 10489/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10490static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10491 struct intel_crtc_state *pipe_config)
79e53945 10492{
f1f644dc 10493 struct drm_device *dev = crtc->base.dev;
79e53945 10494 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10495 int pipe = pipe_config->cpu_transcoder;
293623f7 10496 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10497 u32 fp;
10498 intel_clock_t clock;
dccbea3b 10499 int port_clock;
da4a1efa 10500 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10501
10502 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10503 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10504 else
293623f7 10505 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10506
10507 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10508 if (IS_PINEVIEW(dev)) {
10509 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10510 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10511 } else {
10512 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10513 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10514 }
10515
a6c45cf0 10516 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10517 if (IS_PINEVIEW(dev))
10518 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10519 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10520 else
10521 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10522 DPLL_FPA01_P1_POST_DIV_SHIFT);
10523
10524 switch (dpll & DPLL_MODE_MASK) {
10525 case DPLLB_MODE_DAC_SERIAL:
10526 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10527 5 : 10;
10528 break;
10529 case DPLLB_MODE_LVDS:
10530 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10531 7 : 14;
10532 break;
10533 default:
28c97730 10534 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10535 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10536 return;
79e53945
JB		 10537 }
10538
ac58c3f0 10539 if (IS_PINEVIEW(dev))
dccbea3b 10540 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10541 else
dccbea3b 10542 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10543 } else {
0fb58223 10544 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10545 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10546
10547 if (is_lvds) {
10548 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10549 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10550
10551 if (lvds & LVDS_CLKB_POWER_UP)
10552 clock.p2 = 7;
10553 else
10554 clock.p2 = 14;
79e53945
JB		 10555 } else {
10556 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10557 clock.p1 = 2;
10558 else {
10559 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10560 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10561 }
10562 if (dpll & PLL_P2_DIVIDE_BY_4)
10563 clock.p2 = 4;
10564 else
10565 clock.p2 = 2;
79e53945 10566 }
da4a1efa 10567
dccbea3b 10568 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10569 }
10570
18442d08
VS		 10571 /*
10572 * This value includes pixel_multiplier. We will use
241bfc38 10573 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10574 * encoder's get_config() function.
10575 */
dccbea3b 10576 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10577}
10578
6878da05
VS		 10579int intel_dotclock_calculate(int link_freq,
10580 const struct intel_link_m_n *m_n)
f1f644dc 10581{
f1f644dc
JB		 10582 /*
10583 * The calculation for the data clock is:
1041a02f 10584 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10585 * But we want to avoid losing precison if possible, so:
1041a02f 10586 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10587 *
10588 * and the link clock is simpler:
1041a02f 10589 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10590 */
10591
6878da05
VS		 10592 if (!m_n->link_n)
10593 return 0;
f1f644dc 10594
6878da05
VS		 10595 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10596}
f1f644dc 10597
18442d08 10598static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10599 struct intel_crtc_state *pipe_config)
6878da05
VS		 10600{
10601 struct drm_device *dev = crtc->base.dev;
79e53945 10602
18442d08
VS		 10603 /* read out port_clock from the DPLL */
10604 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10605
f1f644dc 10606 /*
18442d08 10607 * This value does not include pixel_multiplier.
241bfc38 10608 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10609 * agree once we know their relationship in the encoder's
10610 * get_config() function.
79e53945 10611 */
2d112de7 10612 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10613 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10614 &pipe_config->fdi_m_n);
79e53945
JB		 10615}
10616
10617/** Returns the currently programmed mode of the given pipe. */
10618struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10619 struct drm_crtc *crtc)
10620{
548f245b 10621 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10623 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10624 struct drm_display_mode *mode;
5cec258b 10625 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10626 int htot = I915_READ(HTOTAL(cpu_transcoder));
10627 int hsync = I915_READ(HSYNC(cpu_transcoder));
10628 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10629 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10630 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10631
10632 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10633 if (!mode)
10634 return NULL;
10635
f1f644dc
JB		 10636 /*
10637 * Construct a pipe_config sufficient for getting the clock info
10638 * back out of crtc_clock_get.
10639 *
10640 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10641 * to use a real value here instead.
10642 */
293623f7 10643 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10644 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10645 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10646 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10647 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10648 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10649
773ae034 10650 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10651 mode->hdisplay = (htot & 0xffff) + 1;
10652 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10653 mode->hsync_start = (hsync & 0xffff) + 1;
10654 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10655 mode->vdisplay = (vtot & 0xffff) + 1;
10656 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10657 mode->vsync_start = (vsync & 0xffff) + 1;
10658 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10659
10660 drm_mode_set_name(mode);
79e53945
JB		 10661
10662 return mode;
10663}
10664
f047e395
CW		 10665void intel_mark_busy(struct drm_device *dev)
10666{
c67a470b
PZ		 10667 struct drm_i915_private *dev_priv = dev->dev_private;
10668
f62a0076
CW		 10669 if (dev_priv->mm.busy)
10670 return;
10671
43694d69 10672 intel_runtime_pm_get(dev_priv);
c67a470b 10673 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10674 if (INTEL_INFO(dev)->gen >= 6)
10675 gen6_rps_busy(dev_priv);
f62a0076 10676 dev_priv->mm.busy = true;
f047e395
CW		 10677}
10678
10679void intel_mark_idle(struct drm_device *dev)
652c393a 10680{
c67a470b 10681 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10682
f62a0076
CW		 10683 if (!dev_priv->mm.busy)
10684 return;
10685
10686 dev_priv->mm.busy = false;
10687
3d13ef2e 10688 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10689 gen6_rps_idle(dev->dev_private);
bb4cdd53 10690
43694d69 10691 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10692}
10693
79e53945
JB		 10694static void intel_crtc_destroy(struct drm_crtc *crtc)
10695{
10696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10697 struct drm_device *dev = crtc->dev;
10698 struct intel_unpin_work *work;
67e77c5a 10699
5e2d7afc 10700 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10701 work = intel_crtc->unpin_work;
10702 intel_crtc->unpin_work = NULL;
5e2d7afc 10703 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10704
10705 if (work) {
10706 cancel_work_sync(&work->work);
10707 kfree(work);
10708 }
79e53945
JB		 10709
10710 drm_crtc_cleanup(crtc);
67e77c5a 10711
79e53945
JB		 10712 kfree(intel_crtc);
10713}
10714
6b95a207
KH		 10715static void intel_unpin_work_fn(struct work_struct *__work)
10716{
10717 struct intel_unpin_work *work =
10718 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10719 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10720 struct drm_device *dev = crtc->base.dev;
10721 struct drm_plane *primary = crtc->base.primary;
6b95a207 10722
b4a98e57 10723 mutex_lock(&dev->struct_mutex);
a9ff8714 10724 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10725 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10726
f06cc1b9 10727 if (work->flip_queued_req)
146d84f0 10728 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10729 mutex_unlock(&dev->struct_mutex);
10730
a9ff8714 10731 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10732 drm_framebuffer_unreference(work->old_fb);
f99d7069 10733
a9ff8714
VS		 10734 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10735 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10736
6b95a207
KH		 10737 kfree(work);
10738}
10739
1afe3e9d 10740static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10741 struct drm_crtc *crtc)
6b95a207 10742{
6b95a207
KH		 10743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10744 struct intel_unpin_work *work;
6b95a207
KH		 10745 unsigned long flags;
10746
10747 /* Ignore early vblank irqs */
10748 if (intel_crtc == NULL)
10749 return;
10750
f326038a
DV		 10751 /*
10752 * This is called both by irq handlers and the reset code (to complete
10753 * lost pageflips) so needs the full irqsave spinlocks.
10754 */
6b95a207
KH		 10755 spin_lock_irqsave(&dev->event_lock, flags);
10756 work = intel_crtc->unpin_work;
e7d841ca
CW		 10757
10758 /* Ensure we don't miss a work->pending update ... */
10759 smp_rmb();
10760
10761 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10762 spin_unlock_irqrestore(&dev->event_lock, flags);
10763 return;
10764 }
10765
d6bbafa1 10766 page_flip_completed(intel_crtc);
0af7e4df 10767
6b95a207 10768 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10769}
10770
1afe3e9d
JB		 10771void intel_finish_page_flip(struct drm_device *dev, int pipe)
10772{
fbee40df 10773 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10774 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10775
49b14a5c 10776 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10777}
10778
10779void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10780{
fbee40df 10781 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10782 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10783
49b14a5c 10784 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10785}
10786
75f7f3ec
VS		 10787/* Is 'a' after or equal to 'b'? */
10788static bool g4x_flip_count_after_eq(u32 a, u32 b)
10789{
10790 return !((a - b) & 0x80000000);
10791}
10792
10793static bool page_flip_finished(struct intel_crtc *crtc)
10794{
10795 struct drm_device *dev = crtc->base.dev;
10796 struct drm_i915_private *dev_priv = dev->dev_private;
10797
bdfa7542
VS		 10798 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10799 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10800 return true;
10801
75f7f3ec
VS		 10802 /*
10803 * The relevant registers doen't exist on pre-ctg.
10804 * As the flip done interrupt doesn't trigger for mmio
10805 * flips on gmch platforms, a flip count check isn't
10806 * really needed there. But since ctg has the registers,
10807 * include it in the check anyway.
10808 */
10809 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10810 return true;
10811
10812 /*
10813 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10814 * used the same base address. In that case the mmio flip might
10815 * have completed, but the CS hasn't even executed the flip yet.
10816 *
10817 * A flip count check isn't enough as the CS might have updated
10818 * the base address just after start of vblank, but before we
10819 * managed to process the interrupt. This means we'd complete the
10820 * CS flip too soon.
10821 *
10822 * Combining both checks should get us a good enough result. It may
10823 * still happen that the CS flip has been executed, but has not
10824 * yet actually completed. But in case the base address is the same
10825 * anyway, we don't really care.
10826 */
10827 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10828 crtc->unpin_work->gtt_offset &&
10829 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10830 crtc->unpin_work->flip_count);
10831}
10832
6b95a207
KH		 10833void intel_prepare_page_flip(struct drm_device *dev, int plane)
10834{
fbee40df 10835 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10836 struct intel_crtc *intel_crtc =
10837 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10838 unsigned long flags;
10839
f326038a
DV		 10840
10841 /*
10842 * This is called both by irq handlers and the reset code (to complete
10843 * lost pageflips) so needs the full irqsave spinlocks.
10844 *
10845 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10846 * generate a page-flip completion irq, i.e. every modeset
10847 * is also accompanied by a spurious intel_prepare_page_flip().
10848 */
6b95a207 10849 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10850 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10851 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10852 spin_unlock_irqrestore(&dev->event_lock, flags);
10853}
10854
eba905b2 10855static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10856{
10857 /* Ensure that the work item is consistent when activating it ... */
10858 smp_wmb();
10859 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10860 /* and that it is marked active as soon as the irq could fire. */
10861 smp_wmb();
10862}
10863
8c9f3aaf
JB		 10864static int intel_gen2_queue_flip(struct drm_device *dev,
10865 struct drm_crtc *crtc,
10866 struct drm_framebuffer *fb,
ed8d1975 10867 struct drm_i915_gem_object *obj,
6258fbe2 10868 struct drm_i915_gem_request *req,
ed8d1975 10869 uint32_t flags)
8c9f3aaf 10870{
6258fbe2 10871 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10873 u32 flip_mask;
10874 int ret;
10875
5fb9de1a 10876 ret = intel_ring_begin(req, 6);
8c9f3aaf 10877 if (ret)
4fa62c89 10878 return ret;
8c9f3aaf
JB		 10879
10880 /* Can't queue multiple flips, so wait for the previous
10881 * one to finish before executing the next.
10882 */
10883 if (intel_crtc->plane)
10884 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10885 else
10886 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10887 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10888 intel_ring_emit(ring, MI_NOOP);
10889 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10890 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10891 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10892 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10893 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10894
10895 intel_mark_page_flip_active(intel_crtc);
83d4092b 10896 return 0;
8c9f3aaf
JB		 10897}
10898
10899static int intel_gen3_queue_flip(struct drm_device *dev,
10900 struct drm_crtc *crtc,
10901 struct drm_framebuffer *fb,
ed8d1975 10902 struct drm_i915_gem_object *obj,
6258fbe2 10903 struct drm_i915_gem_request *req,
ed8d1975 10904 uint32_t flags)
8c9f3aaf 10905{
6258fbe2 10906 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10908 u32 flip_mask;
10909 int ret;
10910
5fb9de1a 10911 ret = intel_ring_begin(req, 6);
8c9f3aaf 10912 if (ret)
4fa62c89 10913 return ret;
8c9f3aaf
JB		 10914
10915 if (intel_crtc->plane)
10916 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10917 else
10918 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10919 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10920 intel_ring_emit(ring, MI_NOOP);
10921 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10922 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10923 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10924 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10925 intel_ring_emit(ring, MI_NOOP);
10926
e7d841ca 10927 intel_mark_page_flip_active(intel_crtc);
83d4092b 10928 return 0;
8c9f3aaf
JB		 10929}
10930
10931static int intel_gen4_queue_flip(struct drm_device *dev,
10932 struct drm_crtc *crtc,
10933 struct drm_framebuffer *fb,
ed8d1975 10934 struct drm_i915_gem_object *obj,
6258fbe2 10935 struct drm_i915_gem_request *req,
ed8d1975 10936 uint32_t flags)
8c9f3aaf 10937{
6258fbe2 10938 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10939 struct drm_i915_private *dev_priv = dev->dev_private;
10940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10941 uint32_t pf, pipesrc;
10942 int ret;
10943
5fb9de1a 10944 ret = intel_ring_begin(req, 4);
8c9f3aaf 10945 if (ret)
4fa62c89 10946 return ret;
8c9f3aaf
JB		 10947
10948 /* i965+ uses the linear or tiled offsets from the
10949 * Display Registers (which do not change across a page-flip)
10950 * so we need only reprogram the base address.
10951 */
6d90c952
DV		 10952 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10953 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10954 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10955 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10956 obj->tiling_mode);
8c9f3aaf
JB		 10957
10958 /* XXX Enabling the panel-fitter across page-flip is so far
10959 * untested on non-native modes, so ignore it for now.
10960 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10961 */
10962 pf = 0;
10963 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10964 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10965
10966 intel_mark_page_flip_active(intel_crtc);
83d4092b 10967 return 0;
8c9f3aaf
JB		 10968}
10969
10970static int intel_gen6_queue_flip(struct drm_device *dev,
10971 struct drm_crtc *crtc,
10972 struct drm_framebuffer *fb,
ed8d1975 10973 struct drm_i915_gem_object *obj,
6258fbe2 10974 struct drm_i915_gem_request *req,
ed8d1975 10975 uint32_t flags)
8c9f3aaf 10976{
6258fbe2 10977 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10978 struct drm_i915_private *dev_priv = dev->dev_private;
10979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10980 uint32_t pf, pipesrc;
10981 int ret;
10982
5fb9de1a 10983 ret = intel_ring_begin(req, 4);
8c9f3aaf 10984 if (ret)
4fa62c89 10985 return ret;
8c9f3aaf 10986
6d90c952
DV		 10987 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10988 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10989 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10990 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10991
dc257cf1
DV		 10992 /* Contrary to the suggestions in the documentation,
10993 * "Enable Panel Fitter" does not seem to be required when page
10994 * flipping with a non-native mode, and worse causes a normal
10995 * modeset to fail.
10996 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10997 */
10998 pf = 0;
8c9f3aaf 10999 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11000 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11001
11002 intel_mark_page_flip_active(intel_crtc);
83d4092b 11003 return 0;
8c9f3aaf
JB		 11004}
11005
7c9017e5
JB		 11006static int intel_gen7_queue_flip(struct drm_device *dev,
11007 struct drm_crtc *crtc,
11008 struct drm_framebuffer *fb,
ed8d1975 11009 struct drm_i915_gem_object *obj,
6258fbe2 11010 struct drm_i915_gem_request *req,
ed8d1975 11011 uint32_t flags)
7c9017e5 11012{
6258fbe2 11013 struct intel_engine_cs *ring = req->ring;
7c9017e5 11014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11015 uint32_t plane_bit = 0;
ffe74d75
CW		 11016 int len, ret;
11017
eba905b2 11018 switch (intel_crtc->plane) {
cb05d8de
DV		 11019 case PLANE_A:
11020 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11021 break;
11022 case PLANE_B:
11023 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11024 break;
11025 case PLANE_C:
11026 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11027 break;
11028 default:
11029 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11030 return -ENODEV;
cb05d8de
DV		 11031 }
11032
ffe74d75 11033 len = 4;
f476828a 11034 if (ring->id == RCS) {
ffe74d75 11035 len += 6;
f476828a
DL		 11036 /*
11037 * On Gen 8, SRM is now taking an extra dword to accommodate
11038 * 48bits addresses, and we need a NOOP for the batch size to
11039 * stay even.
11040 */
11041 if (IS_GEN8(dev))
11042 len += 2;
11043 }
ffe74d75 11044
f66fab8e
VS		 11045 /*
11046 * BSpec MI_DISPLAY_FLIP for IVB:
11047 * "The full packet must be contained within the same cache line."
11048 *
11049 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11050 * cacheline, if we ever start emitting more commands before
11051 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11052 * then do the cacheline alignment, and finally emit the
11053 * MI_DISPLAY_FLIP.
11054 */
bba09b12 11055 ret = intel_ring_cacheline_align(req);
f66fab8e 11056 if (ret)
4fa62c89 11057 return ret;
f66fab8e 11058
5fb9de1a 11059 ret = intel_ring_begin(req, len);
7c9017e5 11060 if (ret)
4fa62c89 11061 return ret;
7c9017e5 11062
ffe74d75
CW		 11063 /* Unmask the flip-done completion message. Note that the bspec says that
11064 * we should do this for both the BCS and RCS, and that we must not unmask
11065 * more than one flip event at any time (or ensure that one flip message
11066 * can be sent by waiting for flip-done prior to queueing new flips).
11067 * Experimentation says that BCS works despite DERRMR masking all
11068 * flip-done completion events and that unmasking all planes at once
11069 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11070 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11071 */
11072 if (ring->id == RCS) {
11073 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11074 intel_ring_emit(ring, DERRMR);
11075 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11076 DERRMR_PIPEB_PRI_FLIP_DONE |
11077 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11078 if (IS_GEN8(dev))
f1afe24f 11079 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11080 MI_SRM_LRM_GLOBAL_GTT);
11081 else
f1afe24f 11082 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11083 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11084 intel_ring_emit(ring, DERRMR);
11085 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11086 if (IS_GEN8(dev)) {
11087 intel_ring_emit(ring, 0);
11088 intel_ring_emit(ring, MI_NOOP);
11089 }
ffe74d75
CW		 11090 }
11091
cb05d8de 11092 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11093 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11094 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11095 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11096
11097 intel_mark_page_flip_active(intel_crtc);
83d4092b 11098 return 0;
7c9017e5
JB		 11099}
11100
84c33a64
SG		 11101static bool use_mmio_flip(struct intel_engine_cs *ring,
11102 struct drm_i915_gem_object *obj)
11103{
11104 /*
11105 * This is not being used for older platforms, because
11106 * non-availability of flip done interrupt forces us to use
11107 * CS flips. Older platforms derive flip done using some clever
11108 * tricks involving the flip_pending status bits and vblank irqs.
11109 * So using MMIO flips there would disrupt this mechanism.
11110 */
11111
8e09bf83
CW		 11112 if (ring == NULL)
11113 return true;
11114
84c33a64
SG		 11115 if (INTEL_INFO(ring->dev)->gen < 5)
11116 return false;
11117
11118 if (i915.use_mmio_flip < 0)
11119 return false;
11120 else if (i915.use_mmio_flip > 0)
11121 return true;
14bf993e
OM		 11122 else if (i915.enable_execlists)
11123 return true;
84c33a64 11124 else
b4716185 11125 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11126}
11127
ff944564
DL		 11128static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11129{
11130 struct drm_device *dev = intel_crtc->base.dev;
11131 struct drm_i915_private *dev_priv = dev->dev_private;
11132 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11133 const enum pipe pipe = intel_crtc->pipe;
11134 u32 ctl, stride;
11135
11136 ctl = I915_READ(PLANE_CTL(pipe, 0));
11137 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11138 switch (fb->modifier[0]) {
11139 case DRM_FORMAT_MOD_NONE:
11140 break;
11141 case I915_FORMAT_MOD_X_TILED:
ff944564 11142 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11143 break;
11144 case I915_FORMAT_MOD_Y_TILED:
11145 ctl |= PLANE_CTL_TILED_Y;
11146 break;
11147 case I915_FORMAT_MOD_Yf_TILED:
11148 ctl |= PLANE_CTL_TILED_YF;
11149 break;
11150 default:
11151 MISSING_CASE(fb->modifier[0]);
11152 }
ff944564
DL		 11153
11154 /*
11155 * The stride is either expressed as a multiple of 64 bytes chunks for
11156 * linear buffers or in number of tiles for tiled buffers.
11157 */
2ebef630
TU		 11158 stride = fb->pitches[0] /
11159 intel_fb_stride_alignment(dev, fb->modifier[0],
11160 fb->pixel_format);
ff944564
DL		 11161
11162 /*
11163 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11164 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11165 */
11166 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11167 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11168
11169 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11170 POSTING_READ(PLANE_SURF(pipe, 0));
11171}
11172
11173static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11174{
11175 struct drm_device *dev = intel_crtc->base.dev;
11176 struct drm_i915_private *dev_priv = dev->dev_private;
11177 struct intel_framebuffer *intel_fb =
11178 to_intel_framebuffer(intel_crtc->base.primary->fb);
11179 struct drm_i915_gem_object *obj = intel_fb->obj;
11180 u32 dspcntr;
11181 u32 reg;
11182
84c33a64
SG		 11183 reg = DSPCNTR(intel_crtc->plane);
11184 dspcntr = I915_READ(reg);
11185
c5d97472
DL		 11186 if (obj->tiling_mode != I915_TILING_NONE)
11187 dspcntr |= DISPPLANE_TILED;
11188 else
11189 dspcntr &= ~DISPPLANE_TILED;
11190
84c33a64
SG		 11191 I915_WRITE(reg, dspcntr);
11192
11193 I915_WRITE(DSPSURF(intel_crtc->plane),
11194 intel_crtc->unpin_work->gtt_offset);
11195 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11196
ff944564
DL		 11197}
11198
11199/*
11200 * XXX: This is the temporary way to update the plane registers until we get
11201 * around to using the usual plane update functions for MMIO flips
11202 */
11203static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11204{
11205 struct drm_device *dev = intel_crtc->base.dev;
ff944564
DL		 11206
11207 intel_mark_page_flip_active(intel_crtc);
11208
34e0adbb 11209 intel_pipe_update_start(intel_crtc);
ff944564
DL		 11210
11211 if (INTEL_INFO(dev)->gen >= 9)
11212 skl_do_mmio_flip(intel_crtc);
11213 else
11214 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11215 ilk_do_mmio_flip(intel_crtc);
11216
34e0adbb 11217 intel_pipe_update_end(intel_crtc);
84c33a64
SG		 11218}
11219
9362c7c5 11220static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11221{
b2cfe0ab
CW		 11222 struct intel_mmio_flip *mmio_flip =
11223 container_of(work, struct intel_mmio_flip, work);
84c33a64 11224
eed29a5b
DV		 11225 if (mmio_flip->req)
11226 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11227 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11228 false, NULL,
11229 &mmio_flip->i915->rps.mmioflips));
84c33a64 11230
b2cfe0ab
CW		 11231 intel_do_mmio_flip(mmio_flip->crtc);
11232
eed29a5b 11233 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11234 kfree(mmio_flip);
84c33a64
SG		 11235}
11236
11237static int intel_queue_mmio_flip(struct drm_device *dev,
11238 struct drm_crtc *crtc,
11239 struct drm_framebuffer *fb,
11240 struct drm_i915_gem_object *obj,
11241 struct intel_engine_cs *ring,
11242 uint32_t flags)
11243{
b2cfe0ab
CW		 11244 struct intel_mmio_flip *mmio_flip;
11245
11246 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11247 if (mmio_flip == NULL)
11248 return -ENOMEM;
84c33a64 11249
bcafc4e3 11250 mmio_flip->i915 = to_i915(dev);
eed29a5b 11251 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11252 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11253
b2cfe0ab
CW		 11254 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11255 schedule_work(&mmio_flip->work);
84c33a64 11256
84c33a64
SG		 11257 return 0;
11258}
11259
8c9f3aaf
JB		 11260static int intel_default_queue_flip(struct drm_device *dev,
11261 struct drm_crtc *crtc,
11262 struct drm_framebuffer *fb,
ed8d1975 11263 struct drm_i915_gem_object *obj,
6258fbe2 11264 struct drm_i915_gem_request *req,
ed8d1975 11265 uint32_t flags)
8c9f3aaf
JB		 11266{
11267 return -ENODEV;
11268}
11269
d6bbafa1
CW		 11270static bool __intel_pageflip_stall_check(struct drm_device *dev,
11271 struct drm_crtc *crtc)
11272{
11273 struct drm_i915_private *dev_priv = dev->dev_private;
11274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11275 struct intel_unpin_work *work = intel_crtc->unpin_work;
11276 u32 addr;
11277
11278 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11279 return true;
11280
908565c2
CW		 11281 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11282 return false;
11283
d6bbafa1
CW		 11284 if (!work->enable_stall_check)
11285 return false;
11286
11287 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11288 if (work->flip_queued_req &&
11289 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11290 return false;
11291
1e3feefd 11292 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11293 }
11294
1e3feefd 11295 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11296 return false;
11297
11298 /* Potential stall - if we see that the flip has happened,
11299 * assume a missed interrupt. */
11300 if (INTEL_INFO(dev)->gen >= 4)
11301 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11302 else
11303 addr = I915_READ(DSPADDR(intel_crtc->plane));
11304
11305 /* There is a potential issue here with a false positive after a flip
11306 * to the same address. We could address this by checking for a
11307 * non-incrementing frame counter.
11308 */
11309 return addr == work->gtt_offset;
11310}
11311
11312void intel_check_page_flip(struct drm_device *dev, int pipe)
11313{
11314 struct drm_i915_private *dev_priv = dev->dev_private;
11315 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11317 struct intel_unpin_work *work;
f326038a 11318
6c51d46f 11319 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11320
11321 if (crtc == NULL)
11322 return;
11323
f326038a 11324 spin_lock(&dev->event_lock);
6ad790c0
CW		 11325 work = intel_crtc->unpin_work;
11326 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11327 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11328 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11329 page_flip_completed(intel_crtc);
6ad790c0 11330 work = NULL;
d6bbafa1 11331 }
6ad790c0
CW		 11332 if (work != NULL &&
11333 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11334 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11335 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11336}
11337
6b95a207
KH		 11338static int intel_crtc_page_flip(struct drm_crtc *crtc,
11339 struct drm_framebuffer *fb,
ed8d1975
KP		 11340 struct drm_pending_vblank_event *event,
11341 uint32_t page_flip_flags)
6b95a207
KH		 11342{
11343 struct drm_device *dev = crtc->dev;
11344 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11345 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11346 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11348 struct drm_plane *primary = crtc->primary;
a071fa00 11349 enum pipe pipe = intel_crtc->pipe;
6b95a207 11350 struct intel_unpin_work *work;
a4872ba6 11351 struct intel_engine_cs *ring;
cf5d8a46 11352 bool mmio_flip;
91af127f 11353 struct drm_i915_gem_request *request = NULL;
52e68630 11354 int ret;
6b95a207 11355
2ff8fde1
MR		 11356 /*
11357 * drm_mode_page_flip_ioctl() should already catch this, but double
11358 * check to be safe. In the future we may enable pageflipping from
11359 * a disabled primary plane.
11360 */
11361 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11362 return -EBUSY;
11363
e6a595d2 11364 /* Can't change pixel format via MI display flips. */
f4510a27 11365 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11366 return -EINVAL;
11367
11368 /*
11369 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11370 * Note that pitch changes could also affect these register.
11371 */
11372 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11373 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11374 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11375 return -EINVAL;
11376
f900db47
CW		 11377 if (i915_terminally_wedged(&dev_priv->gpu_error))
11378 goto out_hang;
11379
b14c5679 11380 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11381 if (work == NULL)
11382 return -ENOMEM;
11383
6b95a207 11384 work->event = event;
b4a98e57 11385 work->crtc = crtc;
ab8d6675 11386 work->old_fb = old_fb;
6b95a207
KH		 11387 INIT_WORK(&work->work, intel_unpin_work_fn);
11388
87b6b101 11389 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11390 if (ret)
11391 goto free_work;
11392
6b95a207 11393 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11394 spin_lock_irq(&dev->event_lock);
6b95a207 11395 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11396 /* Before declaring the flip queue wedged, check if
11397 * the hardware completed the operation behind our backs.
11398 */
11399 if (__intel_pageflip_stall_check(dev, crtc)) {
11400 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11401 page_flip_completed(intel_crtc);
11402 } else {
11403 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11404 spin_unlock_irq(&dev->event_lock);
468f0b44 11405
d6bbafa1
CW		 11406 drm_crtc_vblank_put(crtc);
11407 kfree(work);
11408 return -EBUSY;
11409 }
6b95a207
KH		 11410 }
11411 intel_crtc->unpin_work = work;
5e2d7afc 11412 spin_unlock_irq(&dev->event_lock);
6b95a207 11413
b4a98e57
CW		 11414 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11415 flush_workqueue(dev_priv->wq);
11416
75dfca80 11417 /* Reference the objects for the scheduled work. */
ab8d6675 11418 drm_framebuffer_reference(work->old_fb);
05394f39 11419 drm_gem_object_reference(&obj->base);
6b95a207 11420
f4510a27 11421 crtc->primary->fb = fb;
afd65eb4 11422 update_state_fb(crtc->primary);
1ed1f968 11423
e1f99ce6 11424 work->pending_flip_obj = obj;
e1f99ce6 11425
89ed88ba
CW		 11426 ret = i915_mutex_lock_interruptible(dev);
11427 if (ret)
11428 goto cleanup;
11429
b4a98e57 11430 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11431 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11432
75f7f3ec 11433 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11434 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11435
4fa62c89
VS		 11436 if (IS_VALLEYVIEW(dev)) {
11437 ring = &dev_priv->ring[BCS];
ab8d6675 11438 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11439 /* vlv: DISPLAY_FLIP fails to change tiling */
11440 ring = NULL;
48bf5b2d 11441 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11442 ring = &dev_priv->ring[BCS];
4fa62c89 11443 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11444 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11445 if (ring == NULL || ring->id != RCS)
11446 ring = &dev_priv->ring[BCS];
11447 } else {
11448 ring = &dev_priv->ring[RCS];
11449 }
11450
cf5d8a46
CW		 11451 mmio_flip = use_mmio_flip(ring, obj);
11452
11453 /* When using CS flips, we want to emit semaphores between rings.
11454 * However, when using mmio flips we will create a task to do the
11455 * synchronisation, so all we want here is to pin the framebuffer
11456 * into the display plane and skip any waits.
11457 */
82bc3b2d 11458 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11459 crtc->primary->state,
91af127f 11460 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11461 if (ret)
11462 goto cleanup_pending;
6b95a207 11463
dedf278c
TU		 11464 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11465 obj, 0);
11466 work->gtt_offset += intel_crtc->dspaddr_offset;
4fa62c89 11467
cf5d8a46 11468 if (mmio_flip) {
84c33a64
SG		 11469 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11470 page_flip_flags);
d6bbafa1
CW		 11471 if (ret)
11472 goto cleanup_unpin;
11473
f06cc1b9
JH		 11474 i915_gem_request_assign(&work->flip_queued_req,
11475 obj->last_write_req);
d6bbafa1 11476 } else {
6258fbe2
JH		 11477 if (!request) {
11478 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11479 if (ret)
11480 goto cleanup_unpin;
11481 }
11482
11483 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11484 page_flip_flags);
11485 if (ret)
11486 goto cleanup_unpin;
11487
6258fbe2 11488 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11489 }
11490
91af127f 11491 if (request)
75289874 11492 i915_add_request_no_flush(request);
91af127f 11493
1e3feefd 11494 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11495 work->enable_stall_check = true;
4fa62c89 11496
ab8d6675 11497 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11498 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11499 mutex_unlock(&dev->struct_mutex);
a071fa00 11500
4e1e26f1 11501 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11502 intel_frontbuffer_flip_prepare(dev,
11503 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11504
e5510fac
JB		 11505 trace_i915_flip_request(intel_crtc->plane, obj);
11506
6b95a207 11507 return 0;
96b099fd 11508
4fa62c89 11509cleanup_unpin:
82bc3b2d 11510 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11511cleanup_pending:
91af127f
JH		 11512 if (request)
11513 i915_gem_request_cancel(request);
b4a98e57 11514 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11515 mutex_unlock(&dev->struct_mutex);
11516cleanup:
f4510a27 11517 crtc->primary->fb = old_fb;
afd65eb4 11518 update_state_fb(crtc->primary);
89ed88ba
CW		 11519
11520 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11521 drm_framebuffer_unreference(work->old_fb);
96b099fd 11522
5e2d7afc 11523 spin_lock_irq(&dev->event_lock);
96b099fd 11524 intel_crtc->unpin_work = NULL;
5e2d7afc 11525 spin_unlock_irq(&dev->event_lock);
96b099fd 11526
87b6b101 11527 drm_crtc_vblank_put(crtc);
7317c75e 11528free_work:
96b099fd
CW		 11529 kfree(work);
11530
f900db47 11531 if (ret == -EIO) {
02e0efb5
ML		 11532 struct drm_atomic_state *state;
11533 struct drm_plane_state *plane_state;
11534
f900db47 11535out_hang:
02e0efb5
ML		 11536 state = drm_atomic_state_alloc(dev);
11537 if (!state)
11538 return -ENOMEM;
11539 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11540
11541retry:
11542 plane_state = drm_atomic_get_plane_state(state, primary);
11543 ret = PTR_ERR_OR_ZERO(plane_state);
11544 if (!ret) {
11545 drm_atomic_set_fb_for_plane(plane_state, fb);
11546
11547 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11548 if (!ret)
11549 ret = drm_atomic_commit(state);
11550 }
11551
11552 if (ret == -EDEADLK) {
11553 drm_modeset_backoff(state->acquire_ctx);
11554 drm_atomic_state_clear(state);
11555 goto retry;
11556 }
11557
11558 if (ret)
11559 drm_atomic_state_free(state);
11560
f0d3dad3 11561 if (ret == 0 && event) {
5e2d7afc 11562 spin_lock_irq(&dev->event_lock);
a071fa00 11563 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11564 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11565 }
f900db47 11566 }
96b099fd 11567 return ret;
6b95a207
KH		 11568}
11569
da20eabd
ML		 11570
11571/**
11572 * intel_wm_need_update - Check whether watermarks need updating
11573 * @plane: drm plane
11574 * @state: new plane state
11575 *
11576 * Check current plane state versus the new one to determine whether
11577 * watermarks need to be recalculated.
11578 *
11579 * Returns true or false.
11580 */
11581static bool intel_wm_need_update(struct drm_plane *plane,
11582 struct drm_plane_state *state)
11583{
11584 /* Update watermarks on tiling changes. */
11585 if (!plane->state->fb || !state->fb ||
11586 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11587 plane->state->rotation != state->rotation)
11588 return true;
11589
11590 if (plane->state->crtc_w != state->crtc_w)
11591 return true;
11592
11593 return false;
11594}
11595
11596int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11597 struct drm_plane_state *plane_state)
11598{
11599 struct drm_crtc *crtc = crtc_state->crtc;
11600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11601 struct drm_plane *plane = plane_state->plane;
11602 struct drm_device *dev = crtc->dev;
11603 struct drm_i915_private *dev_priv = dev->dev_private;
11604 struct intel_plane_state *old_plane_state =
11605 to_intel_plane_state(plane->state);
11606 int idx = intel_crtc->base.base.id, ret;
11607 int i = drm_plane_index(plane);
11608 bool mode_changed = needs_modeset(crtc_state);
11609 bool was_crtc_enabled = crtc->state->active;
11610 bool is_crtc_enabled = crtc_state->active;
11611
11612 bool turn_off, turn_on, visible, was_visible;
11613 struct drm_framebuffer *fb = plane_state->fb;
11614
11615 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11616 plane->type != DRM_PLANE_TYPE_CURSOR) {
11617 ret = skl_update_scaler_plane(
11618 to_intel_crtc_state(crtc_state),
11619 to_intel_plane_state(plane_state));
11620 if (ret)
11621 return ret;
11622 }
11623
11624 /*
11625 * Disabling a plane is always okay; we just need to update
11626 * fb tracking in a special way since cleanup_fb() won't
11627 * get called by the plane helpers.
11628 */
11629 if (old_plane_state->base.fb && !fb)
11630 intel_crtc->atomic.disabled_planes |= 1 << i;
11631
da20eabd
ML		 11632 was_visible = old_plane_state->visible;
11633 visible = to_intel_plane_state(plane_state)->visible;
11634
11635 if (!was_crtc_enabled && WARN_ON(was_visible))
11636 was_visible = false;
11637
11638 if (!is_crtc_enabled && WARN_ON(visible))
11639 visible = false;
11640
11641 if (!was_visible && !visible)
11642 return 0;
11643
11644 turn_off = was_visible && (!visible || mode_changed);
11645 turn_on = visible && (!was_visible || mode_changed);
11646
11647 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11648 plane->base.id, fb ? fb->base.id : -1);
11649
11650 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11651 plane->base.id, was_visible, visible,
11652 turn_off, turn_on, mode_changed);
11653
852eb00d 11654 if (turn_on) {
f015c551 11655 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11656 /* must disable cxsr around plane enable/disable */
11657 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11658 intel_crtc->atomic.disable_cxsr = true;
11659 /* to potentially re-enable cxsr */
11660 intel_crtc->atomic.wait_vblank = true;
11661 intel_crtc->atomic.update_wm_post = true;
11662 }
11663 } else if (turn_off) {
f015c551 11664 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11665 /* must disable cxsr around plane enable/disable */
11666 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11667 if (is_crtc_enabled)
11668 intel_crtc->atomic.wait_vblank = true;
11669 intel_crtc->atomic.disable_cxsr = true;
11670 }
11671 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11672 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11673 }
da20eabd 11674
8be6ca85 11675 if (visible || was_visible)
a9ff8714
VS		 11676 intel_crtc->atomic.fb_bits |=
11677 to_intel_plane(plane)->frontbuffer_bit;
11678
da20eabd
ML		 11679 switch (plane->type) {
11680 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11681 intel_crtc->atomic.wait_for_flips = true;
11682 intel_crtc->atomic.pre_disable_primary = turn_off;
11683 intel_crtc->atomic.post_enable_primary = turn_on;
11684
066cf55b
RV		 11685 if (turn_off) {
11686 /*
11687 * FIXME: Actually if we will still have any other
11688 * plane enabled on the pipe we could let IPS enabled
11689 * still, but for now lets consider that when we make
11690 * primary invisible by setting DSPCNTR to 0 on
11691 * update_primary_plane function IPS needs to be
11692 * disable.
11693 */
11694 intel_crtc->atomic.disable_ips = true;
11695
da20eabd 11696 intel_crtc->atomic.disable_fbc = true;
066cf55b 11697 }
da20eabd
ML		 11698
11699 /*
11700 * FBC does not work on some platforms for rotated
11701 * planes, so disable it when rotation is not 0 and
11702 * update it when rotation is set back to 0.
11703 *
11704 * FIXME: This is redundant with the fbc update done in
11705 * the primary plane enable function except that that
11706 * one is done too late. We eventually need to unify
11707 * this.
11708 */
11709
11710 if (visible &&
11711 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11712 dev_priv->fbc.crtc == intel_crtc &&
11713 plane_state->rotation != BIT(DRM_ROTATE_0))
11714 intel_crtc->atomic.disable_fbc = true;
11715
11716 /*
11717 * BDW signals flip done immediately if the plane
11718 * is disabled, even if the plane enable is already
11719 * armed to occur at the next vblank :(
11720 */
11721 if (turn_on && IS_BROADWELL(dev))
11722 intel_crtc->atomic.wait_vblank = true;
11723
11724 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11725 break;
11726 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11727 break;
11728 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11729 if (turn_off && !mode_changed) {
da20eabd
ML		 11730 intel_crtc->atomic.wait_vblank = true;
11731 intel_crtc->atomic.update_sprite_watermarks |=
11732 1 << i;
11733 }
da20eabd
ML		 11734 }
11735 return 0;
11736}
11737
6d3a1ce7
ML		 11738static bool encoders_cloneable(const struct intel_encoder *a,
11739 const struct intel_encoder *b)
11740{
11741 /* masks could be asymmetric, so check both ways */
11742 return a == b || (a->cloneable & (1 << b->type) &&
11743 b->cloneable & (1 << a->type));
11744}
11745
11746static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11747 struct intel_crtc *crtc,
11748 struct intel_encoder *encoder)
11749{
11750 struct intel_encoder *source_encoder;
11751 struct drm_connector *connector;
11752 struct drm_connector_state *connector_state;
11753 int i;
11754
11755 for_each_connector_in_state(state, connector, connector_state, i) {
11756 if (connector_state->crtc != &crtc->base)
11757 continue;
11758
11759 source_encoder =
11760 to_intel_encoder(connector_state->best_encoder);
11761 if (!encoders_cloneable(encoder, source_encoder))
11762 return false;
11763 }
11764
11765 return true;
11766}
11767
11768static bool check_encoder_cloning(struct drm_atomic_state *state,
11769 struct intel_crtc *crtc)
11770{
11771 struct intel_encoder *encoder;
11772 struct drm_connector *connector;
11773 struct drm_connector_state *connector_state;
11774 int i;
11775
11776 for_each_connector_in_state(state, connector, connector_state, i) {
11777 if (connector_state->crtc != &crtc->base)
11778 continue;
11779
11780 encoder = to_intel_encoder(connector_state->best_encoder);
11781 if (!check_single_encoder_cloning(state, crtc, encoder))
11782 return false;
11783 }
11784
11785 return true;
11786}
11787
11788static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11789 struct drm_crtc_state *crtc_state)
11790{
cf5a15be 11791 struct drm_device *dev = crtc->dev;
ad421372 11792 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11794 struct intel_crtc_state *pipe_config =
11795 to_intel_crtc_state(crtc_state);
6d3a1ce7 11796 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11797 int ret;
6d3a1ce7
ML		 11798 bool mode_changed = needs_modeset(crtc_state);
11799
11800 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11801 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11802 return -EINVAL;
11803 }
11804
852eb00d
VS		 11805 if (mode_changed && !crtc_state->active)
11806 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11807
ad421372
ML		 11808 if (mode_changed && crtc_state->enable &&
11809 dev_priv->display.crtc_compute_clock &&
11810 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11811 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11812 pipe_config);
11813 if (ret)
11814 return ret;
11815 }
11816
e435d6e5
ML		 11817 ret = 0;
11818 if (INTEL_INFO(dev)->gen >= 9) {
11819 if (mode_changed)
11820 ret = skl_update_scaler_crtc(pipe_config);
11821
11822 if (!ret)
11823 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11824 pipe_config);
11825 }
11826
11827 return ret;
6d3a1ce7
ML		 11828}
11829
65b38e0d 11830static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11831 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11832 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11833 .atomic_begin = intel_begin_crtc_commit,
11834 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11835 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11836};
11837
d29b2f9d
ACO		 11838static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11839{
11840 struct intel_connector *connector;
11841
11842 for_each_intel_connector(dev, connector) {
11843 if (connector->base.encoder) {
11844 connector->base.state->best_encoder =
11845 connector->base.encoder;
11846 connector->base.state->crtc =
11847 connector->base.encoder->crtc;
11848 } else {
11849 connector->base.state->best_encoder = NULL;
11850 connector->base.state->crtc = NULL;
11851 }
11852 }
11853}
11854
050f7aeb 11855static void
eba905b2 11856connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11857 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11858{
11859 int bpp = pipe_config->pipe_bpp;
11860
11861 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11862 connector->base.base.id,
c23cc417 11863 connector->base.name);
050f7aeb
DV		 11864
11865 /* Don't use an invalid EDID bpc value */
11866 if (connector->base.display_info.bpc &&
11867 connector->base.display_info.bpc * 3 < bpp) {
11868 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11869 bpp, connector->base.display_info.bpc*3);
11870 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11871 }
11872
11873 /* Clamp bpp to 8 on screens without EDID 1.4 */
11874 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11875 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11876 bpp);
11877 pipe_config->pipe_bpp = 24;
11878 }
11879}
11880
4e53c2e0 11881static int
050f7aeb 11882compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11883 struct intel_crtc_state *pipe_config)
4e53c2e0 11884{
050f7aeb 11885 struct drm_device *dev = crtc->base.dev;
1486017f 11886 struct drm_atomic_state *state;
da3ced29
ACO		 11887 struct drm_connector *connector;
11888 struct drm_connector_state *connector_state;
1486017f 11889 int bpp, i;
4e53c2e0 11890
d328c9d7 11891 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11892 bpp = 10*3;
d328c9d7
DV		 11893 else if (INTEL_INFO(dev)->gen >= 5)
11894 bpp = 12*3;
11895 else
11896 bpp = 8*3;
11897
4e53c2e0 11898
4e53c2e0
DV		 11899 pipe_config->pipe_bpp = bpp;
11900
1486017f
ACO		 11901 state = pipe_config->base.state;
11902
4e53c2e0 11903 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11904 for_each_connector_in_state(state, connector, connector_state, i) {
11905 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11906 continue;
11907
da3ced29
ACO		 11908 connected_sink_compute_bpp(to_intel_connector(connector),
11909 pipe_config);
4e53c2e0
DV		 11910 }
11911
11912 return bpp;
11913}
11914
644db711
DV		 11915static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11916{
11917 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11918 "type: 0x%x flags: 0x%x\n",
1342830c 11919 mode->crtc_clock,
644db711
DV		 11920 mode->crtc_hdisplay, mode->crtc_hsync_start,
11921 mode->crtc_hsync_end, mode->crtc_htotal,
11922 mode->crtc_vdisplay, mode->crtc_vsync_start,
11923 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11924}
11925
c0b03411 11926static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11927 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11928 const char *context)
11929{
6a60cd87
CK		 11930 struct drm_device *dev = crtc->base.dev;
11931 struct drm_plane *plane;
11932 struct intel_plane *intel_plane;
11933 struct intel_plane_state *state;
11934 struct drm_framebuffer *fb;
11935
11936 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11937 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11938
11939 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11940 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11941 pipe_config->pipe_bpp, pipe_config->dither);
11942 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11943 pipe_config->has_pch_encoder,
11944 pipe_config->fdi_lanes,
11945 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11946 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11947 pipe_config->fdi_m_n.tu);
90a6b7b0 11948 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11949 pipe_config->has_dp_encoder,
90a6b7b0 11950 pipe_config->lane_count,
eb14cb74
VS		 11951 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11952 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11953 pipe_config->dp_m_n.tu);
b95af8be 11954
90a6b7b0 11955 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11956 pipe_config->has_dp_encoder,
90a6b7b0 11957 pipe_config->lane_count,
b95af8be
VK		 11958 pipe_config->dp_m2_n2.gmch_m,
11959 pipe_config->dp_m2_n2.gmch_n,
11960 pipe_config->dp_m2_n2.link_m,
11961 pipe_config->dp_m2_n2.link_n,
11962 pipe_config->dp_m2_n2.tu);
11963
55072d19
DV		 11964 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11965 pipe_config->has_audio,
11966 pipe_config->has_infoframe);
11967
c0b03411 11968 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11969 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11970 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11971 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11972 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11973 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11974 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11975 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11976 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11977 crtc->num_scalers,
11978 pipe_config->scaler_state.scaler_users,
11979 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11980 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11981 pipe_config->gmch_pfit.control,
11982 pipe_config->gmch_pfit.pgm_ratios,
11983 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11984 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11985 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11986 pipe_config->pch_pfit.size,
11987 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11988 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11989 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11990
415ff0f6 11991 if (IS_BROXTON(dev)) {
05712c15 11992 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11993 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11994 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 11995 pipe_config->ddi_pll_sel,
11996 pipe_config->dpll_hw_state.ebb0,
05712c15 11997 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 11998 pipe_config->dpll_hw_state.pll0,
11999 pipe_config->dpll_hw_state.pll1,
12000 pipe_config->dpll_hw_state.pll2,
12001 pipe_config->dpll_hw_state.pll3,
12002 pipe_config->dpll_hw_state.pll6,
12003 pipe_config->dpll_hw_state.pll8,
05712c15 12004 pipe_config->dpll_hw_state.pll9,
c8453338 12005 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 12006 pipe_config->dpll_hw_state.pcsdw12);
12007 } else if (IS_SKYLAKE(dev)) {
12008 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12009 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12010 pipe_config->ddi_pll_sel,
12011 pipe_config->dpll_hw_state.ctrl1,
12012 pipe_config->dpll_hw_state.cfgcr1,
12013 pipe_config->dpll_hw_state.cfgcr2);
12014 } else if (HAS_DDI(dev)) {
12015 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12016 pipe_config->ddi_pll_sel,
12017 pipe_config->dpll_hw_state.wrpll);
12018 } else {
12019 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12020 "fp0: 0x%x, fp1: 0x%x\n",
12021 pipe_config->dpll_hw_state.dpll,
12022 pipe_config->dpll_hw_state.dpll_md,
12023 pipe_config->dpll_hw_state.fp0,
12024 pipe_config->dpll_hw_state.fp1);
12025 }
12026
6a60cd87
CK		 12027 DRM_DEBUG_KMS("planes on this crtc\n");
12028 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12029 intel_plane = to_intel_plane(plane);
12030 if (intel_plane->pipe != crtc->pipe)
12031 continue;
12032
12033 state = to_intel_plane_state(plane->state);
12034 fb = state->base.fb;
12035 if (!fb) {
12036 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12037 "disabled, scaler_id = %d\n",
12038 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12039 plane->base.id, intel_plane->pipe,
12040 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12041 drm_plane_index(plane), state->scaler_id);
12042 continue;
12043 }
12044
12045 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12046 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12047 plane->base.id, intel_plane->pipe,
12048 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12049 drm_plane_index(plane));
12050 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12051 fb->base.id, fb->width, fb->height, fb->pixel_format);
12052 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12053 state->scaler_id,
12054 state->src.x1 >> 16, state->src.y1 >> 16,
12055 drm_rect_width(&state->src) >> 16,
12056 drm_rect_height(&state->src) >> 16,
12057 state->dst.x1, state->dst.y1,
12058 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12059 }
c0b03411
DV		 12060}
12061
5448a00d 12062static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12063{
5448a00d
ACO		 12064 struct drm_device *dev = state->dev;
12065 struct intel_encoder *encoder;
da3ced29 12066 struct drm_connector *connector;
5448a00d 12067 struct drm_connector_state *connector_state;
00f0b378 12068 unsigned int used_ports = 0;
5448a00d 12069 int i;
00f0b378
VS		 12070
12071 /*
12072 * Walk the connector list instead of the encoder
12073 * list to detect the problem on ddi platforms
12074 * where there's just one encoder per digital port.
12075 */
da3ced29 12076 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12077 if (!connector_state->best_encoder)
00f0b378
VS		 12078 continue;
12079
5448a00d
ACO		 12080 encoder = to_intel_encoder(connector_state->best_encoder);
12081
12082 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12083
12084 switch (encoder->type) {
12085 unsigned int port_mask;
12086 case INTEL_OUTPUT_UNKNOWN:
12087 if (WARN_ON(!HAS_DDI(dev)))
12088 break;
12089 case INTEL_OUTPUT_DISPLAYPORT:
12090 case INTEL_OUTPUT_HDMI:
12091 case INTEL_OUTPUT_EDP:
12092 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12093
12094 /* the same port mustn't appear more than once */
12095 if (used_ports & port_mask)
12096 return false;
12097
12098 used_ports |= port_mask;
12099 default:
12100 break;
12101 }
12102 }
12103
12104 return true;
12105}
12106
83a57153
ACO		 12107static void
12108clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12109{
12110 struct drm_crtc_state tmp_state;
663a3640 12111 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12112 struct intel_dpll_hw_state dpll_hw_state;
12113 enum intel_dpll_id shared_dpll;
8504c74c 12114 uint32_t ddi_pll_sel;
c4e2d043 12115 bool force_thru;
83a57153 12116
7546a384
ACO		 12117 /* FIXME: before the switch to atomic started, a new pipe_config was
12118 * kzalloc'd. Code that depends on any field being zero should be
12119 * fixed, so that the crtc_state can be safely duplicated. For now,
12120 * only fields that are know to not cause problems are preserved. */
12121
83a57153 12122 tmp_state = crtc_state->base;
663a3640 12123 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12124 shared_dpll = crtc_state->shared_dpll;
12125 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12126 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12127 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12128
83a57153 12129 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12130
83a57153 12131 crtc_state->base = tmp_state;
663a3640 12132 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12133 crtc_state->shared_dpll = shared_dpll;
12134 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12135 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12136 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12137}
12138
548ee15b 12139static int
b8cecdf5 12140intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12141 struct intel_crtc_state *pipe_config)
ee7b9f93 12142{
b359283a 12143 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12144 struct intel_encoder *encoder;
da3ced29 12145 struct drm_connector *connector;
0b901879 12146 struct drm_connector_state *connector_state;
d328c9d7 12147 int base_bpp, ret = -EINVAL;
0b901879 12148 int i;
e29c22c0 12149 bool retry = true;
ee7b9f93 12150
83a57153 12151 clear_intel_crtc_state(pipe_config);
7758a113 12152
e143a21c
DV		 12153 pipe_config->cpu_transcoder =
12154 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12155
2960bc9c
ID		 12156 /*
12157 * Sanitize sync polarity flags based on requested ones. If neither
12158 * positive or negative polarity is requested, treat this as meaning
12159 * negative polarity.
12160 */
2d112de7 12161 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12162 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12163 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12164
2d112de7 12165 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12166 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12167 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12168
d328c9d7
DV		 12169 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12170 pipe_config);
12171 if (base_bpp < 0)
4e53c2e0
DV		 12172 goto fail;
12173
e41a56be
VS		 12174 /*
12175 * Determine the real pipe dimensions. Note that stereo modes can
12176 * increase the actual pipe size due to the frame doubling and
12177 * insertion of additional space for blanks between the frame. This
12178 * is stored in the crtc timings. We use the requested mode to do this
12179 * computation to clearly distinguish it from the adjusted mode, which
12180 * can be changed by the connectors in the below retry loop.
12181 */
2d112de7 12182 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12183 &pipe_config->pipe_src_w,
12184 &pipe_config->pipe_src_h);
e41a56be 12185
e29c22c0 12186encoder_retry:
ef1b460d 12187 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12188 pipe_config->port_clock = 0;
ef1b460d 12189 pipe_config->pixel_multiplier = 1;
ff9a6750 12190
135c81b8 12191 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12192 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12193 CRTC_STEREO_DOUBLE);
135c81b8 12194
7758a113
DV		 12195 /* Pass our mode to the connectors and the CRTC to give them a chance to
12196 * adjust it according to limitations or connector properties, and also
12197 * a chance to reject the mode entirely.
47f1c6c9 12198 */
da3ced29 12199 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12200 if (connector_state->crtc != crtc)
7758a113 12201 continue;
7ae89233 12202
0b901879
ACO		 12203 encoder = to_intel_encoder(connector_state->best_encoder);
12204
efea6e8e
DV		 12205 if (!(encoder->compute_config(encoder, pipe_config))) {
12206 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12207 goto fail;
12208 }
ee7b9f93 12209 }
47f1c6c9 12210
ff9a6750
DV		 12211 /* Set default port clock if not overwritten by the encoder. Needs to be
12212 * done afterwards in case the encoder adjusts the mode. */
12213 if (!pipe_config->port_clock)
2d112de7 12214 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12215 * pipe_config->pixel_multiplier;
ff9a6750 12216
a43f6e0f 12217 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12218 if (ret < 0) {
7758a113
DV		 12219 DRM_DEBUG_KMS("CRTC fixup failed\n");
12220 goto fail;
ee7b9f93 12221 }
e29c22c0
DV		 12222
12223 if (ret == RETRY) {
12224 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12225 ret = -EINVAL;
12226 goto fail;
12227 }
12228
12229 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12230 retry = false;
12231 goto encoder_retry;
12232 }
12233
e8fa4270
DV		 12234 /* Dithering seems to not pass-through bits correctly when it should, so
12235 * only enable it on 6bpc panels. */
12236 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12237 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12238 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12239
7758a113 12240fail:
548ee15b 12241 return ret;
ee7b9f93 12242}
47f1c6c9 12243
ea9d758d 12244static void
4740b0f2 12245intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12246{
0a9ab303
ACO		 12247 struct drm_crtc *crtc;
12248 struct drm_crtc_state *crtc_state;
8a75d157 12249 int i;
ea9d758d 12250
7668851f 12251 /* Double check state. */
8a75d157 12252 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12253 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12254
12255 /* Update hwmode for vblank functions */
12256 if (crtc->state->active)
12257 crtc->hwmode = crtc->state->adjusted_mode;
12258 else
12259 crtc->hwmode.crtc_clock = 0;
ea9d758d 12260 }
ea9d758d
DV		 12261}
12262
3bd26263 12263static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12264{
3bd26263 12265 int diff;
f1f644dc
JB		 12266
12267 if (clock1 == clock2)
12268 return true;
12269
12270 if (!clock1 || !clock2)
12271 return false;
12272
12273 diff = abs(clock1 - clock2);
12274
12275 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12276 return true;
12277
12278 return false;
12279}
12280
25c5b266
DV		 12281#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12282 list_for_each_entry((intel_crtc), \
12283 &(dev)->mode_config.crtc_list, \
12284 base.head) \
0973f18f 12285 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12286
cfb23ed6
ML		 12287static bool
12288intel_compare_m_n(unsigned int m, unsigned int n,
12289 unsigned int m2, unsigned int n2,
12290 bool exact)
12291{
12292 if (m == m2 && n == n2)
12293 return true;
12294
12295 if (exact || !m || !n || !m2 || !n2)
12296 return false;
12297
12298 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12299
12300 if (m > m2) {
12301 while (m > m2) {
12302 m2 <<= 1;
12303 n2 <<= 1;
12304 }
12305 } else if (m < m2) {
12306 while (m < m2) {
12307 m <<= 1;
12308 n <<= 1;
12309 }
12310 }
12311
12312 return m == m2 && n == n2;
12313}
12314
12315static bool
12316intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12317 struct intel_link_m_n *m2_n2,
12318 bool adjust)
12319{
12320 if (m_n->tu == m2_n2->tu &&
12321 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12322 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12323 intel_compare_m_n(m_n->link_m, m_n->link_n,
12324 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12325 if (adjust)
12326 *m2_n2 = *m_n;
12327
12328 return true;
12329 }
12330
12331 return false;
12332}
12333
0e8ffe1b 12334static bool
2fa2fe9a 12335intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12336 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12337 struct intel_crtc_state *pipe_config,
12338 bool adjust)
0e8ffe1b 12339{
cfb23ed6
ML		 12340 bool ret = true;
12341
12342#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12343 do { \
12344 if (!adjust) \
12345 DRM_ERROR(fmt, ##__VA_ARGS__); \
12346 else \
12347 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12348 } while (0)
12349
66e985c0
DV		 12350#define PIPE_CONF_CHECK_X(name) \
12351 if (current_config->name != pipe_config->name) { \
cfb23ed6 12352 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12353 "(expected 0x%08x, found 0x%08x)\n", \
12354 current_config->name, \
12355 pipe_config->name); \
cfb23ed6 12356 ret = false; \
66e985c0
DV		 12357 }
12358
08a24034
DV		 12359#define PIPE_CONF_CHECK_I(name) \
12360 if (current_config->name != pipe_config->name) { \
cfb23ed6 12361 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12362 "(expected %i, found %i)\n", \
12363 current_config->name, \
12364 pipe_config->name); \
cfb23ed6
ML		 12365 ret = false; \
12366 }
12367
12368#define PIPE_CONF_CHECK_M_N(name) \
12369 if (!intel_compare_link_m_n(&current_config->name, \
12370 &pipe_config->name,\
12371 adjust)) { \
12372 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12373 "(expected tu %i gmch %i/%i link %i/%i, " \
12374 "found tu %i, gmch %i/%i link %i/%i)\n", \
12375 current_config->name.tu, \
12376 current_config->name.gmch_m, \
12377 current_config->name.gmch_n, \
12378 current_config->name.link_m, \
12379 current_config->name.link_n, \
12380 pipe_config->name.tu, \
12381 pipe_config->name.gmch_m, \
12382 pipe_config->name.gmch_n, \
12383 pipe_config->name.link_m, \
12384 pipe_config->name.link_n); \
12385 ret = false; \
12386 }
12387
12388#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12389 if (!intel_compare_link_m_n(&current_config->name, \
12390 &pipe_config->name, adjust) && \
12391 !intel_compare_link_m_n(&current_config->alt_name, \
12392 &pipe_config->name, adjust)) { \
12393 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12394 "(expected tu %i gmch %i/%i link %i/%i, " \
12395 "or tu %i gmch %i/%i link %i/%i, " \
12396 "found tu %i, gmch %i/%i link %i/%i)\n", \
12397 current_config->name.tu, \
12398 current_config->name.gmch_m, \
12399 current_config->name.gmch_n, \
12400 current_config->name.link_m, \
12401 current_config->name.link_n, \
12402 current_config->alt_name.tu, \
12403 current_config->alt_name.gmch_m, \
12404 current_config->alt_name.gmch_n, \
12405 current_config->alt_name.link_m, \
12406 current_config->alt_name.link_n, \
12407 pipe_config->name.tu, \
12408 pipe_config->name.gmch_m, \
12409 pipe_config->name.gmch_n, \
12410 pipe_config->name.link_m, \
12411 pipe_config->name.link_n); \
12412 ret = false; \
88adfff1
DV		 12413 }
12414
b95af8be
VK		 12415/* This is required for BDW+ where there is only one set of registers for
12416 * switching between high and low RR.
12417 * This macro can be used whenever a comparison has to be made between one
12418 * hw state and multiple sw state variables.
12419 */
12420#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12421 if ((current_config->name != pipe_config->name) && \
12422 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12423 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12424 "(expected %i or %i, found %i)\n", \
12425 current_config->name, \
12426 current_config->alt_name, \
12427 pipe_config->name); \
cfb23ed6 12428 ret = false; \
b95af8be
VK		 12429 }
12430
1bd1bd80
DV		 12431#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12432 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12433 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12434 "(expected %i, found %i)\n", \
12435 current_config->name & (mask), \
12436 pipe_config->name & (mask)); \
cfb23ed6 12437 ret = false; \
1bd1bd80
DV		 12438 }
12439
5e550656
VS		 12440#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12441 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12442 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12443 "(expected %i, found %i)\n", \
12444 current_config->name, \
12445 pipe_config->name); \
cfb23ed6 12446 ret = false; \
5e550656
VS		 12447 }
12448
bb760063
DV		 12449#define PIPE_CONF_QUIRK(quirk) \
12450 ((current_config->quirks | pipe_config->quirks) & (quirk))
12451
eccb140b
DV		 12452 PIPE_CONF_CHECK_I(cpu_transcoder);
12453
08a24034
DV		 12454 PIPE_CONF_CHECK_I(has_pch_encoder);
12455 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12456 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12457
eb14cb74 12458 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12459 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12460
12461 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12462 PIPE_CONF_CHECK_M_N(dp_m_n);
12463
12464 PIPE_CONF_CHECK_I(has_drrs);
12465 if (current_config->has_drrs)
12466 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12467 } else
12468 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12469
2d112de7
ACO		 12470 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12471 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12472 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12473 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12474 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12475 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12476
2d112de7
ACO		 12477 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12478 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12479 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12480 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12481 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12482 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12483
c93f54cf 12484 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12485 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12486 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12487 IS_VALLEYVIEW(dev))
12488 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12489 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12490
9ed109a7
DV		 12491 PIPE_CONF_CHECK_I(has_audio);
12492
2d112de7 12493 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12494 DRM_MODE_FLAG_INTERLACE);
12495
bb760063 12496 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12497 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12498 DRM_MODE_FLAG_PHSYNC);
2d112de7 12499 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12500 DRM_MODE_FLAG_NHSYNC);
2d112de7 12501 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12502 DRM_MODE_FLAG_PVSYNC);
2d112de7 12503 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12504 DRM_MODE_FLAG_NVSYNC);
12505 }
045ac3b5 12506
333b8ca8 12507 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV		 12508 /* pfit ratios are autocomputed by the hw on gen4+ */
12509 if (INTEL_INFO(dev)->gen < 4)
12510 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
333b8ca8 12511 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12512
bfd16b2a
ML		 12513 if (!adjust) {
12514 PIPE_CONF_CHECK_I(pipe_src_w);
12515 PIPE_CONF_CHECK_I(pipe_src_h);
12516
12517 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12518 if (current_config->pch_pfit.enabled) {
12519 PIPE_CONF_CHECK_X(pch_pfit.pos);
12520 PIPE_CONF_CHECK_X(pch_pfit.size);
12521 }
2fa2fe9a 12522
7aefe2b5
ML		 12523 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12524 }
a1b2278e 12525
e59150dc
JB		 12526 /* BDW+ don't expose a synchronous way to read the state */
12527 if (IS_HASWELL(dev))
12528 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12529
282740f7
VS		 12530 PIPE_CONF_CHECK_I(double_wide);
12531
26804afd
DV		 12532 PIPE_CONF_CHECK_X(ddi_pll_sel);
12533
c0d43d62 12534 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12535 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12536 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12537 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12538 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12539 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12540 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12541 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12542 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12543
42571aef
VS		 12544 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12545 PIPE_CONF_CHECK_I(pipe_bpp);
12546
2d112de7 12547 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12548 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12549
66e985c0 12550#undef PIPE_CONF_CHECK_X
08a24034 12551#undef PIPE_CONF_CHECK_I
b95af8be 12552#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12553#undef PIPE_CONF_CHECK_FLAGS
5e550656 12554#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12555#undef PIPE_CONF_QUIRK
cfb23ed6 12556#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12557
cfb23ed6 12558 return ret;
0e8ffe1b
DV		 12559}
12560
08db6652
DL		 12561static void check_wm_state(struct drm_device *dev)
12562{
12563 struct drm_i915_private *dev_priv = dev->dev_private;
12564 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12565 struct intel_crtc *intel_crtc;
12566 int plane;
12567
12568 if (INTEL_INFO(dev)->gen < 9)
12569 return;
12570
12571 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12572 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12573
12574 for_each_intel_crtc(dev, intel_crtc) {
12575 struct skl_ddb_entry *hw_entry, *sw_entry;
12576 const enum pipe pipe = intel_crtc->pipe;
12577
12578 if (!intel_crtc->active)
12579 continue;
12580
12581 /* planes */
dd740780 12582 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12583 hw_entry = &hw_ddb.plane[pipe][plane];
12584 sw_entry = &sw_ddb->plane[pipe][plane];
12585
12586 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12587 continue;
12588
12589 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12590 "(expected (%u,%u), found (%u,%u))\n",
12591 pipe_name(pipe), plane + 1,
12592 sw_entry->start, sw_entry->end,
12593 hw_entry->start, hw_entry->end);
12594 }
12595
12596 /* cursor */
12597 hw_entry = &hw_ddb.cursor[pipe];
12598 sw_entry = &sw_ddb->cursor[pipe];
12599
12600 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12601 continue;
12602
12603 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12604 "(expected (%u,%u), found (%u,%u))\n",
12605 pipe_name(pipe),
12606 sw_entry->start, sw_entry->end,
12607 hw_entry->start, hw_entry->end);
12608 }
12609}
12610
91d1b4bd 12611static void
35dd3c64
ML		 12612check_connector_state(struct drm_device *dev,
12613 struct drm_atomic_state *old_state)
8af6cf88 12614{
35dd3c64
ML		 12615 struct drm_connector_state *old_conn_state;
12616 struct drm_connector *connector;
12617 int i;
8af6cf88 12618
35dd3c64
ML		 12619 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12620 struct drm_encoder *encoder = connector->encoder;
12621 struct drm_connector_state *state = connector->state;
ad3c558f 12622
8af6cf88
DV		 12623 /* This also checks the encoder/connector hw state with the
12624 * ->get_hw_state callbacks. */
35dd3c64 12625 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12626
ad3c558f 12627 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12628 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12629 }
91d1b4bd
DV		 12630}
12631
12632static void
12633check_encoder_state(struct drm_device *dev)
12634{
12635 struct intel_encoder *encoder;
12636 struct intel_connector *connector;
8af6cf88 12637
b2784e15 12638 for_each_intel_encoder(dev, encoder) {
8af6cf88 12639 bool enabled = false;
4d20cd86 12640 enum pipe pipe;
8af6cf88
DV		 12641
12642 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12643 encoder->base.base.id,
8e329a03 12644 encoder->base.name);
8af6cf88 12645
3a3371ff 12646 for_each_intel_connector(dev, connector) {
4d20cd86 12647 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12648 continue;
12649 enabled = true;
ad3c558f
ML		 12650
12651 I915_STATE_WARN(connector->base.state->crtc !=
12652 encoder->base.crtc,
12653 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12654 }
0e32b39c 12655
e2c719b7 12656 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12657 "encoder's enabled state mismatch "
12658 "(expected %i, found %i)\n",
12659 !!encoder->base.crtc, enabled);
7c60d198
ML		 12660
12661 if (!encoder->base.crtc) {
4d20cd86 12662 bool active;
7c60d198 12663
4d20cd86
ML		 12664 active = encoder->get_hw_state(encoder, &pipe);
12665 I915_STATE_WARN(active,
12666 "encoder detached but still enabled on pipe %c.\n",
12667 pipe_name(pipe));
7c60d198 12668 }
8af6cf88 12669 }
91d1b4bd
DV		 12670}
12671
12672static void
4d20cd86 12673check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12674{
fbee40df 12675 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12676 struct intel_encoder *encoder;
4d20cd86
ML		 12677 struct drm_crtc_state *old_crtc_state;
12678 struct drm_crtc *crtc;
12679 int i;
8af6cf88 12680
4d20cd86
ML		 12681 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12683 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12684 bool active;
8af6cf88 12685
bfd16b2a
ML		 12686 if (!needs_modeset(crtc->state) &&
12687 !to_intel_crtc_state(crtc->state)->update_pipe)
4d20cd86 12688 continue;
045ac3b5 12689
4d20cd86
ML		 12690 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12691 pipe_config = to_intel_crtc_state(old_crtc_state);
12692 memset(pipe_config, 0, sizeof(*pipe_config));
12693 pipe_config->base.crtc = crtc;
12694 pipe_config->base.state = old_state;
8af6cf88 12695
4d20cd86
ML		 12696 DRM_DEBUG_KMS("[CRTC:%d]\n",
12697 crtc->base.id);
8af6cf88 12698
4d20cd86
ML		 12699 active = dev_priv->display.get_pipe_config(intel_crtc,
12700 pipe_config);
d62cf62a 12701
b6b5d049 12702 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12703 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12704 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12705 active = crtc->state->active;
6c49f241 12706
4d20cd86 12707 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12708 "crtc active state doesn't match with hw state "
4d20cd86 12709 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12710
4d20cd86 12711 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12712 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12713 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12714
12715 for_each_encoder_on_crtc(dev, crtc, encoder) {
12716 enum pipe pipe;
12717
12718 active = encoder->get_hw_state(encoder, &pipe);
12719 I915_STATE_WARN(active != crtc->state->active,
12720 "[ENCODER:%i] active %i with crtc active %i\n",
12721 encoder->base.base.id, active, crtc->state->active);
12722
12723 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12724 "Encoder connected to wrong pipe %c\n",
12725 pipe_name(pipe));
12726
12727 if (active)
12728 encoder->get_config(encoder, pipe_config);
12729 }
53d9f4e9 12730
4d20cd86 12731 if (!crtc->state->active)
cfb23ed6
ML		 12732 continue;
12733
4d20cd86
ML		 12734 sw_config = to_intel_crtc_state(crtc->state);
12735 if (!intel_pipe_config_compare(dev, sw_config,
12736 pipe_config, false)) {
e2c719b7 12737 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12738 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12739 "[hw state]");
4d20cd86 12740 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12741 "[sw state]");
12742 }
8af6cf88
DV		 12743 }
12744}
12745
91d1b4bd
DV		 12746static void
12747check_shared_dpll_state(struct drm_device *dev)
12748{
fbee40df 12749 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12750 struct intel_crtc *crtc;
12751 struct intel_dpll_hw_state dpll_hw_state;
12752 int i;
5358901f
DV		 12753
12754 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12755 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12756 int enabled_crtcs = 0, active_crtcs = 0;
12757 bool active;
12758
12759 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12760
12761 DRM_DEBUG_KMS("%s\n", pll->name);
12762
12763 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12764
e2c719b7 12765 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12766 "more active pll users than references: %i vs %i\n",
3e369b76 12767 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12768 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12769 "pll in active use but not on in sw tracking\n");
e2c719b7 12770 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12771 "pll in on but not on in use in sw tracking\n");
e2c719b7 12772 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12773 "pll on state mismatch (expected %i, found %i)\n",
12774 pll->on, active);
12775
d3fcc808 12776 for_each_intel_crtc(dev, crtc) {
83d65738 12777 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12778 enabled_crtcs++;
12779 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12780 active_crtcs++;
12781 }
e2c719b7 12782 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12783 "pll active crtcs mismatch (expected %i, found %i)\n",
12784 pll->active, active_crtcs);
e2c719b7 12785 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12786 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12787 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12788
e2c719b7 12789 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12790 sizeof(dpll_hw_state)),
12791 "pll hw state mismatch\n");
5358901f 12792 }
8af6cf88
DV		 12793}
12794
ee165b1a
ML		 12795static void
12796intel_modeset_check_state(struct drm_device *dev,
12797 struct drm_atomic_state *old_state)
91d1b4bd 12798{
08db6652 12799 check_wm_state(dev);
35dd3c64 12800 check_connector_state(dev, old_state);
91d1b4bd 12801 check_encoder_state(dev);
4d20cd86 12802 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12803 check_shared_dpll_state(dev);
12804}
12805
5cec258b 12806void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12807 int dotclock)
12808{
12809 /*
12810 * FDI already provided one idea for the dotclock.
12811 * Yell if the encoder disagrees.
12812 */
2d112de7 12813 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12814 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12815 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12816}
12817
80715b2f
VS		 12818static void update_scanline_offset(struct intel_crtc *crtc)
12819{
12820 struct drm_device *dev = crtc->base.dev;
12821
12822 /*
12823 * The scanline counter increments at the leading edge of hsync.
12824 *
12825 * On most platforms it starts counting from vtotal-1 on the
12826 * first active line. That means the scanline counter value is
12827 * always one less than what we would expect. Ie. just after
12828 * start of vblank, which also occurs at start of hsync (on the
12829 * last active line), the scanline counter will read vblank_start-1.
12830 *
12831 * On gen2 the scanline counter starts counting from 1 instead
12832 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12833 * to keep the value positive), instead of adding one.
12834 *
12835 * On HSW+ the behaviour of the scanline counter depends on the output
12836 * type. For DP ports it behaves like most other platforms, but on HDMI
12837 * there's an extra 1 line difference. So we need to add two instead of
12838 * one to the value.
12839 */
12840 if (IS_GEN2(dev)) {
124abe07 12841 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12842 int vtotal;
12843
124abe07
VS		 12844 vtotal = adjusted_mode->crtc_vtotal;
12845 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
80715b2f
VS		 12846 vtotal /= 2;
12847
12848 crtc->scanline_offset = vtotal - 1;
12849 } else if (HAS_DDI(dev) &&
409ee761 12850 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12851 crtc->scanline_offset = 2;
12852 } else
12853 crtc->scanline_offset = 1;
12854}
12855
ad421372 12856static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12857{
225da59b 12858 struct drm_device *dev = state->dev;
ed6739ef 12859 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12860 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12861 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12862 struct intel_crtc_state *intel_crtc_state;
12863 struct drm_crtc *crtc;
12864 struct drm_crtc_state *crtc_state;
0a9ab303 12865 int i;
ed6739ef
ACO		 12866
12867 if (!dev_priv->display.crtc_compute_clock)
ad421372 12868 return;
ed6739ef 12869
0a9ab303 12870 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12871 int dpll;
12872
0a9ab303 12873 intel_crtc = to_intel_crtc(crtc);
4978cc93 12874 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12875 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12876
ad421372 12877 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12878 continue;
12879
ad421372 12880 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12881
ad421372
ML		 12882 if (!shared_dpll)
12883 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12884
ad421372
ML		 12885 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12886 }
ed6739ef
ACO		 12887}
12888
99d736a2
ML		 12889/*
12890 * This implements the workaround described in the "notes" section of the mode
12891 * set sequence documentation. When going from no pipes or single pipe to
12892 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12893 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12894 */
12895static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12896{
12897 struct drm_crtc_state *crtc_state;
12898 struct intel_crtc *intel_crtc;
12899 struct drm_crtc *crtc;
12900 struct intel_crtc_state *first_crtc_state = NULL;
12901 struct intel_crtc_state *other_crtc_state = NULL;
12902 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12903 int i;
12904
12905 /* look at all crtc's that are going to be enabled in during modeset */
12906 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12907 intel_crtc = to_intel_crtc(crtc);
12908
12909 if (!crtc_state->active || !needs_modeset(crtc_state))
12910 continue;
12911
12912 if (first_crtc_state) {
12913 other_crtc_state = to_intel_crtc_state(crtc_state);
12914 break;
12915 } else {
12916 first_crtc_state = to_intel_crtc_state(crtc_state);
12917 first_pipe = intel_crtc->pipe;
12918 }
12919 }
12920
12921 /* No workaround needed? */
12922 if (!first_crtc_state)
12923 return 0;
12924
12925 /* w/a possibly needed, check how many crtc's are already enabled. */
12926 for_each_intel_crtc(state->dev, intel_crtc) {
12927 struct intel_crtc_state *pipe_config;
12928
12929 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12930 if (IS_ERR(pipe_config))
12931 return PTR_ERR(pipe_config);
12932
12933 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12934
12935 if (!pipe_config->base.active ||
12936 needs_modeset(&pipe_config->base))
12937 continue;
12938
12939 /* 2 or more enabled crtcs means no need for w/a */
12940 if (enabled_pipe != INVALID_PIPE)
12941 return 0;
12942
12943 enabled_pipe = intel_crtc->pipe;
12944 }
12945
12946 if (enabled_pipe != INVALID_PIPE)
12947 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12948 else if (other_crtc_state)
12949 other_crtc_state->hsw_workaround_pipe = first_pipe;
12950
12951 return 0;
12952}
12953
27c329ed
ML		 12954static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12955{
12956 struct drm_crtc *crtc;
12957 struct drm_crtc_state *crtc_state;
12958 int ret = 0;
12959
12960 /* add all active pipes to the state */
12961 for_each_crtc(state->dev, crtc) {
12962 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12963 if (IS_ERR(crtc_state))
12964 return PTR_ERR(crtc_state);
12965
12966 if (!crtc_state->active || needs_modeset(crtc_state))
12967 continue;
12968
12969 crtc_state->mode_changed = true;
12970
12971 ret = drm_atomic_add_affected_connectors(state, crtc);
12972 if (ret)
12973 break;
12974
12975 ret = drm_atomic_add_affected_planes(state, crtc);
12976 if (ret)
12977 break;
12978 }
12979
12980 return ret;
12981}
12982
c347a676 12983static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12984{
12985 struct drm_device *dev = state->dev;
27c329ed 12986 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12987 int ret;
12988
b359283a
ML		 12989 if (!check_digital_port_conflicts(state)) {
12990 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12991 return -EINVAL;
12992 }
12993
054518dd
ACO		 12994 /*
12995 * See if the config requires any additional preparation, e.g.
12996 * to adjust global state with pipes off. We need to do this
12997 * here so we can get the modeset_pipe updated config for the new
12998 * mode set on this crtc. For other crtcs we need to use the
12999 * adjusted_mode bits in the crtc directly.
13000 */
27c329ed
ML		 13001 if (dev_priv->display.modeset_calc_cdclk) {
13002 unsigned int cdclk;
b432e5cf 13003
27c329ed
ML		 13004 ret = dev_priv->display.modeset_calc_cdclk(state);
13005
13006 cdclk = to_intel_atomic_state(state)->cdclk;
13007 if (!ret && cdclk != dev_priv->cdclk_freq)
13008 ret = intel_modeset_all_pipes(state);
13009
13010 if (ret < 0)
054518dd 13011 return ret;
27c329ed
ML		 13012 } else
13013 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13014
ad421372 13015 intel_modeset_clear_plls(state);
054518dd 13016
99d736a2 13017 if (IS_HASWELL(dev))
ad421372 13018 return haswell_mode_set_planes_workaround(state);
99d736a2 13019
ad421372 13020 return 0;
c347a676
ACO		 13021}
13022
74c090b1
ML		 13023/**
13024 * intel_atomic_check - validate state object
13025 * @dev: drm device
13026 * @state: state to validate
13027 */
13028static int intel_atomic_check(struct drm_device *dev,
13029 struct drm_atomic_state *state)
c347a676
ACO		 13030{
13031 struct drm_crtc *crtc;
13032 struct drm_crtc_state *crtc_state;
13033 int ret, i;
61333b60 13034 bool any_ms = false;
c347a676 13035
74c090b1 13036 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 13037 if (ret)
13038 return ret;
13039
c347a676 13040 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 13041 struct intel_crtc_state *pipe_config =
13042 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 13043
13044 /* Catch I915_MODE_FLAG_INHERITED */
13045 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13046 crtc_state->mode_changed = true;
cfb23ed6 13047
61333b60
ML		 13048 if (!crtc_state->enable) {
13049 if (needs_modeset(crtc_state))
13050 any_ms = true;
c347a676 13051 continue;
61333b60 13052 }
c347a676 13053
26495481 13054 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 13055 continue;
13056
26495481
DV		 13057 /* FIXME: For only active_changed we shouldn't need to do any
13058 * state recomputation at all. */
13059
1ed51de9
DV		 13060 ret = drm_atomic_add_affected_connectors(state, crtc);
13061 if (ret)
13062 return ret;
b359283a 13063
cfb23ed6 13064 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13065 if (ret)
13066 return ret;
13067
6764e9f8 13068 if (intel_pipe_config_compare(state->dev,
cfb23ed6 13069 to_intel_crtc_state(crtc->state),
1ed51de9 13070 pipe_config, true)) {
26495481 13071 crtc_state->mode_changed = false;
bfd16b2a 13072 to_intel_crtc_state(crtc_state)->update_pipe = true;
26495481
DV		 13073 }
13074
13075 if (needs_modeset(crtc_state)) {
13076 any_ms = true;
cfb23ed6
ML		 13077
13078 ret = drm_atomic_add_affected_planes(state, crtc);
13079 if (ret)
13080 return ret;
13081 }
61333b60 13082
26495481
DV		 13083 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13084 needs_modeset(crtc_state) ?
13085 "[modeset]" : "[fastset]");
c347a676
ACO		 13086 }
13087
61333b60
ML		 13088 if (any_ms) {
13089 ret = intel_modeset_checks(state);
13090
13091 if (ret)
13092 return ret;
27c329ed
ML		 13093 } else
13094 to_intel_atomic_state(state)->cdclk =
13095 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13096
13097 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13098}
13099
74c090b1
ML		 13100/**
13101 * intel_atomic_commit - commit validated state object
13102 * @dev: DRM device
13103 * @state: the top-level driver state object
13104 * @async: asynchronous commit
13105 *
13106 * This function commits a top-level state object that has been validated
13107 * with drm_atomic_helper_check().
13108 *
13109 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13110 * we can only handle plane-related operations and do not yet support
13111 * asynchronous commit.
13112 *
13113 * RETURNS
13114 * Zero for success or -errno.
13115 */
13116static int intel_atomic_commit(struct drm_device *dev,
13117 struct drm_atomic_state *state,
13118 bool async)
a6778b3c 13119{
fbee40df 13120 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13121 struct drm_crtc *crtc;
13122 struct drm_crtc_state *crtc_state;
c0c36b94 13123 int ret = 0;
0a9ab303 13124 int i;
61333b60 13125 bool any_ms = false;
a6778b3c 13126
74c090b1
ML		 13127 if (async) {
13128 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13129 return -EINVAL;
13130 }
13131
d4afb8cc
ACO		 13132 ret = drm_atomic_helper_prepare_planes(dev, state);
13133 if (ret)
13134 return ret;
13135
1c5e19f8
ML		 13136 drm_atomic_helper_swap_state(dev, state);
13137
0a9ab303 13138 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13140
61333b60
ML		 13141 if (!needs_modeset(crtc->state))
13142 continue;
13143
13144 any_ms = true;
a539205a 13145 intel_pre_plane_update(intel_crtc);
460da916 13146
a539205a
ML		 13147 if (crtc_state->active) {
13148 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13149 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13150 intel_crtc->active = false;
13151 intel_disable_shared_dpll(intel_crtc);
a539205a 13152 }
b8cecdf5 13153 }
7758a113 13154
ea9d758d
DV		 13155 /* Only after disabling all output pipelines that will be changed can we
13156 * update the the output configuration. */
4740b0f2 13157 intel_modeset_update_crtc_state(state);
f6e5b160 13158
4740b0f2
ML		 13159 if (any_ms) {
13160 intel_shared_dpll_commit(state);
13161
13162 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13163 modeset_update_crtc_power_domains(state);
4740b0f2 13164 }
47fab737 13165
a6778b3c 13166 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13167 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13169 bool modeset = needs_modeset(crtc->state);
bfd16b2a
ML		 13170 bool update_pipe = !modeset &&
13171 to_intel_crtc_state(crtc->state)->update_pipe;
13172 unsigned long put_domains = 0;
f6ac4b2a
ML		 13173
13174 if (modeset && crtc->state->active) {
a539205a
ML		 13175 update_scanline_offset(to_intel_crtc(crtc));
13176 dev_priv->display.crtc_enable(crtc);
13177 }
80715b2f 13178
bfd16b2a
ML		 13179 if (update_pipe) {
13180 put_domains = modeset_get_crtc_power_domains(crtc);
13181
13182 /* make sure intel_modeset_check_state runs */
13183 any_ms = true;
13184 }
13185
f6ac4b2a
ML		 13186 if (!modeset)
13187 intel_pre_plane_update(intel_crtc);
13188
a539205a 13189 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
bfd16b2a
ML		 13190
13191 if (put_domains)
13192 modeset_put_power_domains(dev_priv, put_domains);
13193
f6ac4b2a 13194 intel_post_plane_update(intel_crtc);
80715b2f 13195 }
a6778b3c 13196
a6778b3c 13197 /* FIXME: add subpixel order */
83a57153 13198
74c090b1 13199 drm_atomic_helper_wait_for_vblanks(dev, state);
d4afb8cc 13200 drm_atomic_helper_cleanup_planes(dev, state);
2bfb4627 13201
74c090b1 13202 if (any_ms)
ee165b1a
ML		 13203 intel_modeset_check_state(dev, state);
13204
13205 drm_atomic_state_free(state);
f30da187 13206
74c090b1 13207 return 0;
7f27126e
JB		 13208}
13209
c0c36b94
CW		 13210void intel_crtc_restore_mode(struct drm_crtc *crtc)
13211{
83a57153
ACO		 13212 struct drm_device *dev = crtc->dev;
13213 struct drm_atomic_state *state;
e694eb02 13214 struct drm_crtc_state *crtc_state;
2bfb4627 13215 int ret;
83a57153
ACO		 13216
13217 state = drm_atomic_state_alloc(dev);
13218 if (!state) {
e694eb02 13219 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13220 crtc->base.id);
13221 return;
13222 }
13223
e694eb02 13224 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13225
e694eb02
ML		 13226retry:
13227 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13228 ret = PTR_ERR_OR_ZERO(crtc_state);
13229 if (!ret) {
13230 if (!crtc_state->active)
13231 goto out;
83a57153 13232
e694eb02 13233 crtc_state->mode_changed = true;
74c090b1 13234 ret = drm_atomic_commit(state);
83a57153
ACO		 13235 }
13236
e694eb02
ML		 13237 if (ret == -EDEADLK) {
13238 drm_atomic_state_clear(state);
13239 drm_modeset_backoff(state->acquire_ctx);
13240 goto retry;
4ed9fb37 13241 }
4be07317 13242
2bfb4627 13243 if (ret)
e694eb02 13244out:
2bfb4627 13245 drm_atomic_state_free(state);
c0c36b94
CW		 13246}
13247
25c5b266
DV		 13248#undef for_each_intel_crtc_masked
13249
f6e5b160 13250static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13251 .gamma_set = intel_crtc_gamma_set,
74c090b1 13252 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13253 .destroy = intel_crtc_destroy,
13254 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13255 .atomic_duplicate_state = intel_crtc_duplicate_state,
13256 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13257};
13258
5358901f
DV		 13259static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13260 struct intel_shared_dpll *pll,
13261 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13262{
5358901f 13263 uint32_t val;
ee7b9f93 13264
f458ebbc 13265 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13266 return false;
13267
5358901f 13268 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13269 hw_state->dpll = val;
13270 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13271 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13272
13273 return val & DPLL_VCO_ENABLE;
13274}
13275
15bdd4cf
DV		 13276static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13277 struct intel_shared_dpll *pll)
13278{
3e369b76
ACO		 13279 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13280 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13281}
13282
e7b903d2
DV		 13283static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13284 struct intel_shared_dpll *pll)
13285{
e7b903d2 13286 /* PCH refclock must be enabled first */
89eff4be 13287 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13288
3e369b76 13289 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13290
13291 /* Wait for the clocks to stabilize. */
13292 POSTING_READ(PCH_DPLL(pll->id));
13293 udelay(150);
13294
13295 /* The pixel multiplier can only be updated once the
13296 * DPLL is enabled and the clocks are stable.
13297 *
13298 * So write it again.
13299 */
3e369b76 13300 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13301 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13302 udelay(200);
13303}
13304
13305static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13306 struct intel_shared_dpll *pll)
13307{
13308 struct drm_device *dev = dev_priv->dev;
13309 struct intel_crtc *crtc;
e7b903d2
DV		 13310
13311 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13312 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13313 if (intel_crtc_to_shared_dpll(crtc) == pll)
13314 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13315 }
13316
15bdd4cf
DV		 13317 I915_WRITE(PCH_DPLL(pll->id), 0);
13318 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13319 udelay(200);
13320}
13321
46edb027
DV		 13322static char *ibx_pch_dpll_names[] = {
13323 "PCH DPLL A",
13324 "PCH DPLL B",
13325};
13326
7c74ade1 13327static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13328{
e7b903d2 13329 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13330 int i;
13331
7c74ade1 13332 dev_priv->num_shared_dpll = 2;
ee7b9f93 13333
e72f9fbf 13334 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13335 dev_priv->shared_dplls[i].id = i;
13336 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13337 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13338 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13339 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13340 dev_priv->shared_dplls[i].get_hw_state =
13341 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13342 }
13343}
13344
7c74ade1
DV		 13345static void intel_shared_dpll_init(struct drm_device *dev)
13346{
e7b903d2 13347 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13348
9cd86933
DV		 13349 if (HAS_DDI(dev))
13350 intel_ddi_pll_init(dev);
13351 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13352 ibx_pch_dpll_init(dev);
13353 else
13354 dev_priv->num_shared_dpll = 0;
13355
13356 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13357}
13358
6beb8c23
MR		 13359/**
13360 * intel_prepare_plane_fb - Prepare fb for usage on plane
13361 * @plane: drm plane to prepare for
13362 * @fb: framebuffer to prepare for presentation
13363 *
13364 * Prepares a framebuffer for usage on a display plane. Generally this
13365 * involves pinning the underlying object and updating the frontbuffer tracking
13366 * bits. Some older platforms need special physical address handling for
13367 * cursor planes.
13368 *
13369 * Returns 0 on success, negative error code on failure.
13370 */
13371int
13372intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee 13373 const struct drm_plane_state *new_state)
465c120c
MR		 13374{
13375 struct drm_device *dev = plane->dev;
844f9111 13376 struct drm_framebuffer *fb = new_state->fb;
6beb8c23 13377 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13378 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13379 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13380 int ret = 0;
465c120c 13381
ea2c67bb 13382 if (!obj)
465c120c
MR		 13383 return 0;
13384
6beb8c23 13385 mutex_lock(&dev->struct_mutex);
465c120c 13386
6beb8c23
MR		 13387 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13388 INTEL_INFO(dev)->cursor_needs_physical) {
13389 int align = IS_I830(dev) ? 16 * 1024 : 256;
13390 ret = i915_gem_object_attach_phys(obj, align);
13391 if (ret)
13392 DRM_DEBUG_KMS("failed to attach phys object\n");
13393 } else {
91af127f 13394 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13395 }
465c120c 13396
6beb8c23 13397 if (ret == 0)
a9ff8714 13398 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13399
4c34574f 13400 mutex_unlock(&dev->struct_mutex);
465c120c 13401
6beb8c23
MR		 13402 return ret;
13403}
13404
38f3ce3a
MR		 13405/**
13406 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13407 * @plane: drm plane to clean up for
13408 * @fb: old framebuffer that was on plane
13409 *
13410 * Cleans up a framebuffer that has just been removed from a plane.
13411 */
13412void
13413intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee 13414 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13415{
13416 struct drm_device *dev = plane->dev;
844f9111 13417 struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
38f3ce3a 13418
844f9111 13419 if (!obj)
38f3ce3a
MR		 13420 return;
13421
13422 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13423 !INTEL_INFO(dev)->cursor_needs_physical) {
13424 mutex_lock(&dev->struct_mutex);
844f9111 13425 intel_unpin_fb_obj(old_state->fb, old_state);
38f3ce3a
MR		 13426 mutex_unlock(&dev->struct_mutex);
13427 }
465c120c
MR		 13428}
13429
6156a456
CK		 13430int
13431skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13432{
13433 int max_scale;
13434 struct drm_device *dev;
13435 struct drm_i915_private *dev_priv;
13436 int crtc_clock, cdclk;
13437
13438 if (!intel_crtc || !crtc_state)
13439 return DRM_PLANE_HELPER_NO_SCALING;
13440
13441 dev = intel_crtc->base.dev;
13442 dev_priv = dev->dev_private;
13443 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13444 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13445
13446 if (!crtc_clock || !cdclk)
13447 return DRM_PLANE_HELPER_NO_SCALING;
13448
13449 /*
13450 * skl max scale is lower of:
13451 * close to 3 but not 3, -1 is for that purpose
13452 * or
13453 * cdclk/crtc_clock
13454 */
13455 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13456
13457 return max_scale;
13458}
13459
465c120c 13460static int
3c692a41 13461intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13462 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13463 struct intel_plane_state *state)
13464{
2b875c22
MR		 13465 struct drm_crtc *crtc = state->base.crtc;
13466 struct drm_framebuffer *fb = state->base.fb;
6156a456 13467 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13468 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13469 bool can_position = false;
465c120c 13470
061e4b8d
ML		 13471 /* use scaler when colorkey is not required */
13472 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13473 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13474 min_scale = 1;
13475 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13476 can_position = true;
6156a456 13477 }
d8106366 13478
061e4b8d
ML		 13479 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13480 &state->dst, &state->clip,
da20eabd
ML		 13481 min_scale, max_scale,
13482 can_position, true,
13483 &state->visible);
14af293f
GP		 13484}
13485
13486static void
13487intel_commit_primary_plane(struct drm_plane *plane,
13488 struct intel_plane_state *state)
13489{
2b875c22
MR		 13490 struct drm_crtc *crtc = state->base.crtc;
13491 struct drm_framebuffer *fb = state->base.fb;
13492 struct drm_device *dev = plane->dev;
14af293f 13493 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13494 struct intel_crtc *intel_crtc;
14af293f
GP		 13495 struct drm_rect *src = &state->src;
13496
ea2c67bb
MR		 13497 crtc = crtc ? crtc : plane->crtc;
13498 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13499
13500 plane->fb = fb;
9dc806fc
MR		 13501 crtc->x = src->x1 >> 16;
13502 crtc->y = src->y1 >> 16;
ccc759dc 13503
a539205a 13504 if (!crtc->state->active)
302d19ac 13505 return;
465c120c 13506
d4b08630
ML		 13507 dev_priv->display.update_primary_plane(crtc, fb,
13508 state->src.x1 >> 16,
13509 state->src.y1 >> 16);
465c120c
MR		 13510}
13511
a8ad0d8e
ML		 13512static void
13513intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13514 struct drm_crtc *crtc)
a8ad0d8e
ML		 13515{
13516 struct drm_device *dev = plane->dev;
13517 struct drm_i915_private *dev_priv = dev->dev_private;
13518
a8ad0d8e
ML		 13519 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13520}
13521
613d2b27
ML		 13522static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13523 struct drm_crtc_state *old_crtc_state)
3c692a41 13524{
32b7eeec 13525 struct drm_device *dev = crtc->dev;
3c692a41 13526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
bfd16b2a
ML		 13527 struct intel_crtc_state *old_intel_state =
13528 to_intel_crtc_state(old_crtc_state);
13529 bool modeset = needs_modeset(crtc->state);
3c692a41 13530
f015c551 13531 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13532 intel_update_watermarks(crtc);
3c692a41 13533
c34c9ee4 13534 /* Perform vblank evasion around commit operation */
a539205a 13535 if (crtc->state->active)
34e0adbb 13536 intel_pipe_update_start(intel_crtc);
0583236e 13537
bfd16b2a
ML		 13538 if (modeset)
13539 return;
13540
13541 if (to_intel_crtc_state(crtc->state)->update_pipe)
13542 intel_update_pipe_config(intel_crtc, old_intel_state);
13543 else if (INTEL_INFO(dev)->gen >= 9)
0583236e 13544 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13545}
13546
613d2b27
ML		 13547static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13548 struct drm_crtc_state *old_crtc_state)
32b7eeec 13549{
32b7eeec 13550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13551
8f539a83 13552 if (crtc->state->active)
34e0adbb 13553 intel_pipe_update_end(intel_crtc);
3c692a41
GP		 13554}
13555
cf4c7c12 13556/**
4a3b8769
MR		 13557 * intel_plane_destroy - destroy a plane
13558 * @plane: plane to destroy
cf4c7c12 13559 *
4a3b8769
MR		 13560 * Common destruction function for all types of planes (primary, cursor,
13561 * sprite).
cf4c7c12 13562 */
4a3b8769 13563void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13564{
13565 struct intel_plane *intel_plane = to_intel_plane(plane);
13566 drm_plane_cleanup(plane);
13567 kfree(intel_plane);
13568}
13569
65a3fea0 13570const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13571 .update_plane = drm_atomic_helper_update_plane,
13572 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13573 .destroy = intel_plane_destroy,
c196e1d6 13574 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13575 .atomic_get_property = intel_plane_atomic_get_property,
13576 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13577 .atomic_duplicate_state = intel_plane_duplicate_state,
13578 .atomic_destroy_state = intel_plane_destroy_state,
13579
465c120c
MR		 13580};
13581
13582static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13583 int pipe)
13584{
13585 struct intel_plane *primary;
8e7d688b 13586 struct intel_plane_state *state;
465c120c 13587 const uint32_t *intel_primary_formats;
45e3743a 13588 unsigned int num_formats;
465c120c
MR		 13589
13590 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13591 if (primary == NULL)
13592 return NULL;
13593
8e7d688b
MR		 13594 state = intel_create_plane_state(&primary->base);
13595 if (!state) {
ea2c67bb
MR		 13596 kfree(primary);
13597 return NULL;
13598 }
8e7d688b 13599 primary->base.state = &state->base;
ea2c67bb 13600
465c120c
MR		 13601 primary->can_scale = false;
13602 primary->max_downscale = 1;
6156a456
CK		 13603 if (INTEL_INFO(dev)->gen >= 9) {
13604 primary->can_scale = true;
af99ceda 13605 state->scaler_id = -1;
6156a456 13606 }
465c120c
MR		 13607 primary->pipe = pipe;
13608 primary->plane = pipe;
a9ff8714 13609 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13610 primary->check_plane = intel_check_primary_plane;
13611 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13612 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13613 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13614 primary->plane = !pipe;
13615
6c0fd451
DL		 13616 if (INTEL_INFO(dev)->gen >= 9) {
13617 intel_primary_formats = skl_primary_formats;
13618 num_formats = ARRAY_SIZE(skl_primary_formats);
13619 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13620 intel_primary_formats = i965_primary_formats;
13621 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13622 } else {
13623 intel_primary_formats = i8xx_primary_formats;
13624 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13625 }
13626
13627 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13628 &intel_plane_funcs,
465c120c
MR		 13629 intel_primary_formats, num_formats,
13630 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13631
3b7a5119
SJ		 13632 if (INTEL_INFO(dev)->gen >= 4)
13633 intel_create_rotation_property(dev, primary);
48404c1e 13634
ea2c67bb
MR		 13635 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13636
465c120c
MR		 13637 return &primary->base;
13638}
13639
3b7a5119
SJ		 13640void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13641{
13642 if (!dev->mode_config.rotation_property) {
13643 unsigned long flags = BIT(DRM_ROTATE_0) |
13644 BIT(DRM_ROTATE_180);
13645
13646 if (INTEL_INFO(dev)->gen >= 9)
13647 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13648
13649 dev->mode_config.rotation_property =
13650 drm_mode_create_rotation_property(dev, flags);
13651 }
13652 if (dev->mode_config.rotation_property)
13653 drm_object_attach_property(&plane->base.base,
13654 dev->mode_config.rotation_property,
13655 plane->base.state->rotation);
13656}
13657
3d7d6510 13658static int
852e787c 13659intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13660 struct intel_crtc_state *crtc_state,
852e787c 13661 struct intel_plane_state *state)
3d7d6510 13662{
061e4b8d 13663 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13664 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13665 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13666 unsigned stride;
13667 int ret;
3d7d6510 13668
061e4b8d
ML		 13669 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13670 &state->dst, &state->clip,
3d7d6510
MR		 13671 DRM_PLANE_HELPER_NO_SCALING,
13672 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13673 true, true, &state->visible);
757f9a3e
GP		 13674 if (ret)
13675 return ret;
13676
757f9a3e
GP		 13677 /* if we want to turn off the cursor ignore width and height */
13678 if (!obj)
da20eabd 13679 return 0;
757f9a3e 13680
757f9a3e 13681 /* Check for which cursor types we support */
061e4b8d 13682 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13683 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13684 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13685 return -EINVAL;
13686 }
13687
ea2c67bb
MR		 13688 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13689 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13690 DRM_DEBUG_KMS("buffer is too small\n");
13691 return -ENOMEM;
13692 }
13693
3a656b54 13694 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13695 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13696 return -EINVAL;
32b7eeec
MR		 13697 }
13698
da20eabd 13699 return 0;
852e787c 13700}
3d7d6510 13701
a8ad0d8e
ML		 13702static void
13703intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13704 struct drm_crtc *crtc)
a8ad0d8e 13705{
a8ad0d8e
ML		 13706 intel_crtc_update_cursor(crtc, false);
13707}
13708
f4a2cf29 13709static void
852e787c
GP		 13710intel_commit_cursor_plane(struct drm_plane *plane,
13711 struct intel_plane_state *state)
13712{
2b875c22 13713 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13714 struct drm_device *dev = plane->dev;
13715 struct intel_crtc *intel_crtc;
2b875c22 13716 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13717 uint32_t addr;
852e787c 13718
ea2c67bb
MR		 13719 crtc = crtc ? crtc : plane->crtc;
13720 intel_crtc = to_intel_crtc(crtc);
13721
a912f12f
GP		 13722 if (intel_crtc->cursor_bo == obj)
13723 goto update;
4ed91096 13724
f4a2cf29 13725 if (!obj)
a912f12f 13726 addr = 0;
f4a2cf29 13727 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13728 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13729 else
a912f12f 13730 addr = obj->phys_handle->busaddr;
852e787c 13731
a912f12f
GP		 13732 intel_crtc->cursor_addr = addr;
13733 intel_crtc->cursor_bo = obj;
852e787c 13734
302d19ac 13735update:
a539205a 13736 if (crtc->state->active)
a912f12f 13737 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13738}
13739
3d7d6510
MR		 13740static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13741 int pipe)
13742{
13743 struct intel_plane *cursor;
8e7d688b 13744 struct intel_plane_state *state;
3d7d6510
MR		 13745
13746 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13747 if (cursor == NULL)
13748 return NULL;
13749
8e7d688b
MR		 13750 state = intel_create_plane_state(&cursor->base);
13751 if (!state) {
ea2c67bb
MR		 13752 kfree(cursor);
13753 return NULL;
13754 }
8e7d688b 13755 cursor->base.state = &state->base;
ea2c67bb 13756
3d7d6510
MR		 13757 cursor->can_scale = false;
13758 cursor->max_downscale = 1;
13759 cursor->pipe = pipe;
13760 cursor->plane = pipe;
a9ff8714 13761 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13762 cursor->check_plane = intel_check_cursor_plane;
13763 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13764 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13765
13766 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13767 &intel_plane_funcs,
3d7d6510
MR		 13768 intel_cursor_formats,
13769 ARRAY_SIZE(intel_cursor_formats),
13770 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13771
13772 if (INTEL_INFO(dev)->gen >= 4) {
13773 if (!dev->mode_config.rotation_property)
13774 dev->mode_config.rotation_property =
13775 drm_mode_create_rotation_property(dev,
13776 BIT(DRM_ROTATE_0) |
13777 BIT(DRM_ROTATE_180));
13778 if (dev->mode_config.rotation_property)
13779 drm_object_attach_property(&cursor->base.base,
13780 dev->mode_config.rotation_property,
8e7d688b 13781 state->base.rotation);
4398ad45
VS		 13782 }
13783
af99ceda
CK		 13784 if (INTEL_INFO(dev)->gen >=9)
13785 state->scaler_id = -1;
13786
ea2c67bb
MR		 13787 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13788
3d7d6510
MR		 13789 return &cursor->base;
13790}
13791
549e2bfb
CK		 13792static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13793 struct intel_crtc_state *crtc_state)
13794{
13795 int i;
13796 struct intel_scaler *intel_scaler;
13797 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13798
13799 for (i = 0; i < intel_crtc->num_scalers; i++) {
13800 intel_scaler = &scaler_state->scalers[i];
13801 intel_scaler->in_use = 0;
549e2bfb
CK		 13802 intel_scaler->mode = PS_SCALER_MODE_DYN;
13803 }
13804
13805 scaler_state->scaler_id = -1;
13806}
13807
b358d0a6 13808static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13809{
fbee40df 13810 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13811 struct intel_crtc *intel_crtc;
f5de6e07 13812 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13813 struct drm_plane *primary = NULL;
13814 struct drm_plane *cursor = NULL;
465c120c 13815 int i, ret;
79e53945 13816
955382f3 13817 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13818 if (intel_crtc == NULL)
13819 return;
13820
f5de6e07
ACO		 13821 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13822 if (!crtc_state)
13823 goto fail;
550acefd
ACO		 13824 intel_crtc->config = crtc_state;
13825 intel_crtc->base.state = &crtc_state->base;
07878248 13826 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13827
549e2bfb
CK		 13828 /* initialize shared scalers */
13829 if (INTEL_INFO(dev)->gen >= 9) {
13830 if (pipe == PIPE_C)
13831 intel_crtc->num_scalers = 1;
13832 else
13833 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13834
13835 skl_init_scalers(dev, intel_crtc, crtc_state);
13836 }
13837
465c120c 13838 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13839 if (!primary)
13840 goto fail;
13841
13842 cursor = intel_cursor_plane_create(dev, pipe);
13843 if (!cursor)
13844 goto fail;
13845
465c120c 13846 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13847 cursor, &intel_crtc_funcs);
13848 if (ret)
13849 goto fail;
79e53945
JB		 13850
13851 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13852 for (i = 0; i < 256; i++) {
13853 intel_crtc->lut_r[i] = i;
13854 intel_crtc->lut_g[i] = i;
13855 intel_crtc->lut_b[i] = i;
13856 }
13857
1f1c2e24
VS		 13858 /*
13859 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13860 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13861 */
80824003
JB		 13862 intel_crtc->pipe = pipe;
13863 intel_crtc->plane = pipe;
3a77c4c4 13864 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13865 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13866 intel_crtc->plane = !pipe;
80824003
JB		 13867 }
13868
4b0e333e
CW		 13869 intel_crtc->cursor_base = ~0;
13870 intel_crtc->cursor_cntl = ~0;
dc41c154 13871 intel_crtc->cursor_size = ~0;
8d7849db 13872
852eb00d
VS		 13873 intel_crtc->wm.cxsr_allowed = true;
13874
22fd0fab
JB		 13875 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13876 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13877 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13878 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13879
79e53945 13880 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13881
13882 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13883 return;
13884
13885fail:
13886 if (primary)
13887 drm_plane_cleanup(primary);
13888 if (cursor)
13889 drm_plane_cleanup(cursor);
f5de6e07 13890 kfree(crtc_state);
3d7d6510 13891 kfree(intel_crtc);
79e53945
JB		 13892}
13893
752aa88a
JB		 13894enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13895{
13896 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13897 struct drm_device *dev = connector->base.dev;
752aa88a 13898
51fd371b 13899 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13900
d3babd3f 13901 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13902 return INVALID_PIPE;
13903
13904 return to_intel_crtc(encoder->crtc)->pipe;
13905}
13906
08d7b3d1 13907int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13908 struct drm_file *file)
08d7b3d1 13909{
08d7b3d1 13910 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13911 struct drm_crtc *drmmode_crtc;
c05422d5 13912 struct intel_crtc *crtc;
08d7b3d1 13913
7707e653 13914 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13915
7707e653 13916 if (!drmmode_crtc) {
08d7b3d1 13917 DRM_ERROR("no such CRTC id\n");
3f2c2057 13918 return -ENOENT;
08d7b3d1
CW		 13919 }
13920
7707e653 13921 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13922 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13923
c05422d5 13924 return 0;
08d7b3d1
CW		 13925}
13926
66a9278e 13927static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13928{
66a9278e
DV		 13929 struct drm_device *dev = encoder->base.dev;
13930 struct intel_encoder *source_encoder;
79e53945 13931 int index_mask = 0;
79e53945
JB		 13932 int entry = 0;
13933
b2784e15 13934 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13935 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13936 index_mask |= (1 << entry);
13937
79e53945
JB		 13938 entry++;
13939 }
4ef69c7a 13940
79e53945
JB		 13941 return index_mask;
13942}
13943
4d302442
CW		 13944static bool has_edp_a(struct drm_device *dev)
13945{
13946 struct drm_i915_private *dev_priv = dev->dev_private;
13947
13948 if (!IS_MOBILE(dev))
13949 return false;
13950
13951 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13952 return false;
13953
e3589908 13954 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13955 return false;
13956
13957 return true;
13958}
13959
84b4e042
JB		 13960static bool intel_crt_present(struct drm_device *dev)
13961{
13962 struct drm_i915_private *dev_priv = dev->dev_private;
13963
884497ed
DL		 13964 if (INTEL_INFO(dev)->gen >= 9)
13965 return false;
13966
cf404ce4 13967 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13968 return false;
13969
13970 if (IS_CHERRYVIEW(dev))
13971 return false;
13972
13973 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13974 return false;
13975
13976 return true;
13977}
13978
79e53945
JB		 13979static void intel_setup_outputs(struct drm_device *dev)
13980{
725e30ad 13981 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13982 struct intel_encoder *encoder;
cb0953d7 13983 bool dpd_is_edp = false;
79e53945 13984
c9093354 13985 intel_lvds_init(dev);
79e53945 13986
84b4e042 13987 if (intel_crt_present(dev))
79935fca 13988 intel_crt_init(dev);
cb0953d7 13989
c776eb2e
VK		 13990 if (IS_BROXTON(dev)) {
13991 /*
13992 * FIXME: Broxton doesn't support port detection via the
13993 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13994 * detect the ports.
13995 */
13996 intel_ddi_init(dev, PORT_A);
13997 intel_ddi_init(dev, PORT_B);
13998 intel_ddi_init(dev, PORT_C);
13999 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14000 int found;
14001
de31facd
JB		 14002 /*
14003 * Haswell uses DDI functions to detect digital outputs.
14004 * On SKL pre-D0 the strap isn't connected, so we assume
14005 * it's there.
14006 */
77179400 14007 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
de31facd 14008 /* WaIgnoreDDIAStrap: skl */
5a2376d1 14009 if (found || IS_SKYLAKE(dev))
0e72a5b5
ED		 14010 intel_ddi_init(dev, PORT_A);
14011
14012 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14013 * register */
14014 found = I915_READ(SFUSE_STRAP);
14015
14016 if (found & SFUSE_STRAP_DDIB_DETECTED)
14017 intel_ddi_init(dev, PORT_B);
14018 if (found & SFUSE_STRAP_DDIC_DETECTED)
14019 intel_ddi_init(dev, PORT_C);
14020 if (found & SFUSE_STRAP_DDID_DETECTED)
14021 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 14022 /*
14023 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14024 */
14025 if (IS_SKYLAKE(dev) &&
14026 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14027 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14028 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14029 intel_ddi_init(dev, PORT_E);
14030
0e72a5b5 14031 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14032 int found;
5d8a7752 14033 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14034
14035 if (has_edp_a(dev))
14036 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14037
dc0fa718 14038 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14039 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14040 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14041 if (!found)
e2debe91 14042 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14043 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14044 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14045 }
14046
dc0fa718 14047 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14048 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14049
dc0fa718 14050 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14051 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14052
5eb08b69 14053 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14054 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14055
270b3042 14056 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14057 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14058 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14059 /*
14060 * The DP_DETECTED bit is the latched state of the DDC
14061 * SDA pin at boot. However since eDP doesn't require DDC
14062 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14063 * eDP ports may have been muxed to an alternate function.
14064 * Thus we can't rely on the DP_DETECTED bit alone to detect
14065 * eDP ports. Consult the VBT as well as DP_DETECTED to
14066 * detect eDP ports.
14067 */
e66eb81d 14068 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
d2182a66 14069 !intel_dp_is_edp(dev, PORT_B))
e66eb81d
VS		 14070 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14071 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
e17ac6db 14072 intel_dp_is_edp(dev, PORT_B))
e66eb81d 14073 intel_dp_init(dev, VLV_DP_B, PORT_B);
585a94b8 14074
e66eb81d 14075 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
d2182a66 14076 !intel_dp_is_edp(dev, PORT_C))
e66eb81d
VS		 14077 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14078 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
e17ac6db 14079 intel_dp_is_edp(dev, PORT_C))
e66eb81d 14080 intel_dp_init(dev, VLV_DP_C, PORT_C);
19c03924 14081
9418c1f1 14082 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14083 /* eDP not supported on port D, so don't check VBT */
e66eb81d
VS		 14084 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14085 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14086 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14087 intel_dp_init(dev, CHV_DP_D, PORT_D);
9418c1f1
VS		 14088 }
14089
3cfca973 14090 intel_dsi_init(dev);
09da55dc 14091 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14092 bool found = false;
7d57382e 14093
e2debe91 14094 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14095 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14096 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14097 if (!found && IS_G4X(dev)) {
b01f2c3a 14098 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14099 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14100 }
27185ae1 14101
3fec3d2f 14102 if (!found && IS_G4X(dev))
ab9d7c30 14103 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14104 }
13520b05
KH		 14105
14106 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14107
e2debe91 14108 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14109 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14110 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14111 }
27185ae1 14112
e2debe91 14113 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14114
3fec3d2f 14115 if (IS_G4X(dev)) {
b01f2c3a 14116 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14117 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14118 }
3fec3d2f 14119 if (IS_G4X(dev))
ab9d7c30 14120 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14121 }
27185ae1 14122
3fec3d2f 14123 if (IS_G4X(dev) &&
e7281eab 14124 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14125 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14126 } else if (IS_GEN2(dev))
79e53945
JB		 14127 intel_dvo_init(dev);
14128
103a196f 14129 if (SUPPORTS_TV(dev))
79e53945
JB		 14130 intel_tv_init(dev);
14131
0bc12bcb 14132 intel_psr_init(dev);
7c8f8a70 14133
b2784e15 14134 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14135 encoder->base.possible_crtcs = encoder->crtc_mask;
14136 encoder->base.possible_clones =
66a9278e 14137 intel_encoder_clones(encoder);
79e53945 14138 }
47356eb6 14139
dde86e2d 14140 intel_init_pch_refclk(dev);
270b3042
DV		 14141
14142 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14143}
14144
14145static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14146{
60a5ca01 14147 struct drm_device *dev = fb->dev;
79e53945 14148 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14149
ef2d633e 14150 drm_framebuffer_cleanup(fb);
60a5ca01 14151 mutex_lock(&dev->struct_mutex);
ef2d633e 14152 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14153 drm_gem_object_unreference(&intel_fb->obj->base);
14154 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14155 kfree(intel_fb);
14156}
14157
14158static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14159 struct drm_file *file,
79e53945
JB		 14160 unsigned int *handle)
14161{
14162 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14163 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14164
05394f39 14165 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14166}
14167
86c98588
RV		 14168static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14169 struct drm_file *file,
14170 unsigned flags, unsigned color,
14171 struct drm_clip_rect *clips,
14172 unsigned num_clips)
14173{
14174 struct drm_device *dev = fb->dev;
14175 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14176 struct drm_i915_gem_object *obj = intel_fb->obj;
14177
14178 mutex_lock(&dev->struct_mutex);
74b4ea1e 14179 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14180 mutex_unlock(&dev->struct_mutex);
14181
14182 return 0;
14183}
14184
79e53945
JB		 14185static const struct drm_framebuffer_funcs intel_fb_funcs = {
14186 .destroy = intel_user_framebuffer_destroy,
14187 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14188 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14189};
14190
b321803d
DL		 14191static
14192u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14193 uint32_t pixel_format)
14194{
14195 u32 gen = INTEL_INFO(dev)->gen;
14196
14197 if (gen >= 9) {
14198 /* "The stride in bytes must not exceed the of the size of 8K
14199 * pixels and 32K bytes."
14200 */
14201 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14202 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14203 return 32*1024;
14204 } else if (gen >= 4) {
14205 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14206 return 16*1024;
14207 else
14208 return 32*1024;
14209 } else if (gen >= 3) {
14210 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14211 return 8*1024;
14212 else
14213 return 16*1024;
14214 } else {
14215 /* XXX DSPC is limited to 4k tiled */
14216 return 8*1024;
14217 }
14218}
14219
b5ea642a
DV		 14220static int intel_framebuffer_init(struct drm_device *dev,
14221 struct intel_framebuffer *intel_fb,
14222 struct drm_mode_fb_cmd2 *mode_cmd,
14223 struct drm_i915_gem_object *obj)
79e53945 14224{
6761dd31 14225 unsigned int aligned_height;
79e53945 14226 int ret;
b321803d 14227 u32 pitch_limit, stride_alignment;
79e53945 14228
dd4916c5
DV		 14229 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14230
2a80eada
DV		 14231 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14232 /* Enforce that fb modifier and tiling mode match, but only for
14233 * X-tiled. This is needed for FBC. */
14234 if (!!(obj->tiling_mode == I915_TILING_X) !=
14235 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14236 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14237 return -EINVAL;
14238 }
14239 } else {
14240 if (obj->tiling_mode == I915_TILING_X)
14241 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14242 else if (obj->tiling_mode == I915_TILING_Y) {
14243 DRM_DEBUG("No Y tiling for legacy addfb\n");
14244 return -EINVAL;
14245 }
14246 }
14247
9a8f0a12
TU		 14248 /* Passed in modifier sanity checking. */
14249 switch (mode_cmd->modifier[0]) {
14250 case I915_FORMAT_MOD_Y_TILED:
14251 case I915_FORMAT_MOD_Yf_TILED:
14252 if (INTEL_INFO(dev)->gen < 9) {
14253 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14254 mode_cmd->modifier[0]);
14255 return -EINVAL;
14256 }
14257 case DRM_FORMAT_MOD_NONE:
14258 case I915_FORMAT_MOD_X_TILED:
14259 break;
14260 default:
c0f40428
JB		 14261 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14262 mode_cmd->modifier[0]);
57cd6508 14263 return -EINVAL;
c16ed4be 14264 }
57cd6508 14265
b321803d
DL		 14266 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14267 mode_cmd->pixel_format);
14268 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14269 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14270 mode_cmd->pitches[0], stride_alignment);
57cd6508 14271 return -EINVAL;
c16ed4be 14272 }
57cd6508 14273
b321803d
DL		 14274 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14275 mode_cmd->pixel_format);
a35cdaa0 14276 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14277 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14278 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14279 "tiled" : "linear",
a35cdaa0 14280 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14281 return -EINVAL;
c16ed4be 14282 }
5d7bd705 14283
2a80eada 14284 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14285 mode_cmd->pitches[0] != obj->stride) {
14286 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14287 mode_cmd->pitches[0], obj->stride);
5d7bd705 14288 return -EINVAL;
c16ed4be 14289 }
5d7bd705 14290
57779d06 14291 /* Reject formats not supported by any plane early. */
308e5bcb 14292 switch (mode_cmd->pixel_format) {
57779d06 14293 case DRM_FORMAT_C8:
04b3924d
VS		 14294 case DRM_FORMAT_RGB565:
14295 case DRM_FORMAT_XRGB8888:
14296 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14297 break;
14298 case DRM_FORMAT_XRGB1555:
c16ed4be 14299 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14300 DRM_DEBUG("unsupported pixel format: %s\n",
14301 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14302 return -EINVAL;
c16ed4be 14303 }
57779d06 14304 break;
57779d06 14305 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14306 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14307 DRM_DEBUG("unsupported pixel format: %s\n",
14308 drm_get_format_name(mode_cmd->pixel_format));
14309 return -EINVAL;
14310 }
14311 break;
14312 case DRM_FORMAT_XBGR8888:
04b3924d 14313 case DRM_FORMAT_XRGB2101010:
57779d06 14314 case DRM_FORMAT_XBGR2101010:
c16ed4be 14315 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14316 DRM_DEBUG("unsupported pixel format: %s\n",
14317 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14318 return -EINVAL;
c16ed4be 14319 }
b5626747 14320 break;
7531208b
DL		 14321 case DRM_FORMAT_ABGR2101010:
14322 if (!IS_VALLEYVIEW(dev)) {
14323 DRM_DEBUG("unsupported pixel format: %s\n",
14324 drm_get_format_name(mode_cmd->pixel_format));
14325 return -EINVAL;
14326 }
14327 break;
04b3924d
VS		 14328 case DRM_FORMAT_YUYV:
14329 case DRM_FORMAT_UYVY:
14330 case DRM_FORMAT_YVYU:
14331 case DRM_FORMAT_VYUY:
c16ed4be 14332 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14333 DRM_DEBUG("unsupported pixel format: %s\n",
14334 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14335 return -EINVAL;
c16ed4be 14336 }
57cd6508
CW		 14337 break;
14338 default:
4ee62c76
VS		 14339 DRM_DEBUG("unsupported pixel format: %s\n",
14340 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14341 return -EINVAL;
14342 }
14343
90f9a336
VS		 14344 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14345 if (mode_cmd->offsets[0] != 0)
14346 return -EINVAL;
14347
ec2c981e 14348 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14349 mode_cmd->pixel_format,
14350 mode_cmd->modifier[0]);
53155c0a
DV		 14351 /* FIXME drm helper for size checks (especially planar formats)? */
14352 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14353 return -EINVAL;
14354
c7d73f6a
DV		 14355 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14356 intel_fb->obj = obj;
80075d49 14357 intel_fb->obj->framebuffer_references++;
c7d73f6a 14358
79e53945
JB		 14359 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14360 if (ret) {
14361 DRM_ERROR("framebuffer init failed %d\n", ret);
14362 return ret;
14363 }
14364
79e53945
JB		 14365 return 0;
14366}
14367
79e53945
JB		 14368static struct drm_framebuffer *
14369intel_user_framebuffer_create(struct drm_device *dev,
14370 struct drm_file *filp,
308e5bcb 14371 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14372{
05394f39 14373 struct drm_i915_gem_object *obj;
79e53945 14374
308e5bcb
JB		 14375 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14376 mode_cmd->handles[0]));
c8725226 14377 if (&obj->base == NULL)
cce13ff7 14378 return ERR_PTR(-ENOENT);
79e53945 14379
d2dff872 14380 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14381}
14382
0695726e 14383#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14384static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14385{
14386}
14387#endif
14388
79e53945 14389static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14390 .fb_create = intel_user_framebuffer_create,
0632fef6 14391 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14392 .atomic_check = intel_atomic_check,
14393 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14394 .atomic_state_alloc = intel_atomic_state_alloc,
14395 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14396};
14397
e70236a8
JB		 14398/* Set up chip specific display functions */
14399static void intel_init_display(struct drm_device *dev)
14400{
14401 struct drm_i915_private *dev_priv = dev->dev_private;
14402
ee9300bb
DV		 14403 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14404 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14405 else if (IS_CHERRYVIEW(dev))
14406 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14407 else if (IS_VALLEYVIEW(dev))
14408 dev_priv->display.find_dpll = vlv_find_best_dpll;
14409 else if (IS_PINEVIEW(dev))
14410 dev_priv->display.find_dpll = pnv_find_best_dpll;
14411 else
14412 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14413
bc8d7dff
DL		 14414 if (INTEL_INFO(dev)->gen >= 9) {
14415 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14416 dev_priv->display.get_initial_plane_config =
14417 skylake_get_initial_plane_config;
bc8d7dff
DL		 14418 dev_priv->display.crtc_compute_clock =
14419 haswell_crtc_compute_clock;
14420 dev_priv->display.crtc_enable = haswell_crtc_enable;
14421 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14422 dev_priv->display.update_primary_plane =
14423 skylake_update_primary_plane;
14424 } else if (HAS_DDI(dev)) {
0e8ffe1b 14425 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14426 dev_priv->display.get_initial_plane_config =
14427 ironlake_get_initial_plane_config;
797d0259
ACO		 14428 dev_priv->display.crtc_compute_clock =
14429 haswell_crtc_compute_clock;
4f771f10
PZ		 14430 dev_priv->display.crtc_enable = haswell_crtc_enable;
14431 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14432 dev_priv->display.update_primary_plane =
14433 ironlake_update_primary_plane;
09b4ddf9 14434 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14435 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14436 dev_priv->display.get_initial_plane_config =
14437 ironlake_get_initial_plane_config;
3fb37703
ACO		 14438 dev_priv->display.crtc_compute_clock =
14439 ironlake_crtc_compute_clock;
76e5a89c
DV		 14440 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14441 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14442 dev_priv->display.update_primary_plane =
14443 ironlake_update_primary_plane;
89b667f8
JB		 14444 } else if (IS_VALLEYVIEW(dev)) {
14445 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14446 dev_priv->display.get_initial_plane_config =
14447 i9xx_get_initial_plane_config;
d6dfee7a 14448 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14449 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14450 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14451 dev_priv->display.update_primary_plane =
14452 i9xx_update_primary_plane;
f564048e 14453 } else {
0e8ffe1b 14454 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14455 dev_priv->display.get_initial_plane_config =
14456 i9xx_get_initial_plane_config;
d6dfee7a 14457 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14458 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14459 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14460 dev_priv->display.update_primary_plane =
14461 i9xx_update_primary_plane;
f564048e 14462 }
e70236a8 14463
e70236a8 14464 /* Returns the core display clock speed */
1652d19e
VS		 14465 if (IS_SKYLAKE(dev))
14466 dev_priv->display.get_display_clock_speed =
14467 skylake_get_display_clock_speed;
acd3f3d3
BP		 14468 else if (IS_BROXTON(dev))
14469 dev_priv->display.get_display_clock_speed =
14470 broxton_get_display_clock_speed;
1652d19e
VS		 14471 else if (IS_BROADWELL(dev))
14472 dev_priv->display.get_display_clock_speed =
14473 broadwell_get_display_clock_speed;
14474 else if (IS_HASWELL(dev))
14475 dev_priv->display.get_display_clock_speed =
14476 haswell_get_display_clock_speed;
14477 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14478 dev_priv->display.get_display_clock_speed =
14479 valleyview_get_display_clock_speed;
b37a6434
VS		 14480 else if (IS_GEN5(dev))
14481 dev_priv->display.get_display_clock_speed =
14482 ilk_get_display_clock_speed;
a7c66cd8 14483 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14484 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14485 dev_priv->display.get_display_clock_speed =
14486 i945_get_display_clock_speed;
34edce2f
VS		 14487 else if (IS_GM45(dev))
14488 dev_priv->display.get_display_clock_speed =
14489 gm45_get_display_clock_speed;
14490 else if (IS_CRESTLINE(dev))
14491 dev_priv->display.get_display_clock_speed =
14492 i965gm_get_display_clock_speed;
14493 else if (IS_PINEVIEW(dev))
14494 dev_priv->display.get_display_clock_speed =
14495 pnv_get_display_clock_speed;
14496 else if (IS_G33(dev) || IS_G4X(dev))
14497 dev_priv->display.get_display_clock_speed =
14498 g33_get_display_clock_speed;
e70236a8
JB		 14499 else if (IS_I915G(dev))
14500 dev_priv->display.get_display_clock_speed =
14501 i915_get_display_clock_speed;
257a7ffc 14502 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14503 dev_priv->display.get_display_clock_speed =
14504 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14505 else if (IS_PINEVIEW(dev))
14506 dev_priv->display.get_display_clock_speed =
14507 pnv_get_display_clock_speed;
e70236a8
JB		 14508 else if (IS_I915GM(dev))
14509 dev_priv->display.get_display_clock_speed =
14510 i915gm_get_display_clock_speed;
14511 else if (IS_I865G(dev))
14512 dev_priv->display.get_display_clock_speed =
14513 i865_get_display_clock_speed;
f0f8a9ce 14514 else if (IS_I85X(dev))
e70236a8 14515 dev_priv->display.get_display_clock_speed =
1b1d2716 14516 i85x_get_display_clock_speed;
623e01e5
VS		 14517 else { /* 830 */
14518 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14519 dev_priv->display.get_display_clock_speed =
14520 i830_get_display_clock_speed;
623e01e5 14521 }
e70236a8 14522
7c10a2b5 14523 if (IS_GEN5(dev)) {
3bb11b53 14524 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14525 } else if (IS_GEN6(dev)) {
14526 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14527 } else if (IS_IVYBRIDGE(dev)) {
14528 /* FIXME: detect B0+ stepping and use auto training */
14529 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14530 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14531 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14532 if (IS_BROADWELL(dev)) {
14533 dev_priv->display.modeset_commit_cdclk =
14534 broadwell_modeset_commit_cdclk;
14535 dev_priv->display.modeset_calc_cdclk =
14536 broadwell_modeset_calc_cdclk;
14537 }
30a970c6 14538 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14539 dev_priv->display.modeset_commit_cdclk =
14540 valleyview_modeset_commit_cdclk;
14541 dev_priv->display.modeset_calc_cdclk =
14542 valleyview_modeset_calc_cdclk;
f8437dd1 14543 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14544 dev_priv->display.modeset_commit_cdclk =
14545 broxton_modeset_commit_cdclk;
14546 dev_priv->display.modeset_calc_cdclk =
14547 broxton_modeset_calc_cdclk;
e70236a8 14548 }
8c9f3aaf 14549
8c9f3aaf
JB		 14550 switch (INTEL_INFO(dev)->gen) {
14551 case 2:
14552 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14553 break;
14554
14555 case 3:
14556 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14557 break;
14558
14559 case 4:
14560 case 5:
14561 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14562 break;
14563
14564 case 6:
14565 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14566 break;
7c9017e5 14567 case 7:
4e0bbc31 14568 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14569 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14570 break;
830c81db 14571 case 9:
ba343e02
TU		 14572 /* Drop through - unsupported since execlist only. */
14573 default:
14574 /* Default just returns -ENODEV to indicate unsupported */
14575 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14576 }
7bd688cd 14577
e39b999a 14578 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14579}
14580
b690e96c
JB		 14581/*
14582 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14583 * resume, or other times. This quirk makes sure that's the case for
14584 * affected systems.
14585 */
0206e353 14586static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14587{
14588 struct drm_i915_private *dev_priv = dev->dev_private;
14589
14590 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14591 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14592}
14593
b6b5d049
VS		 14594static void quirk_pipeb_force(struct drm_device *dev)
14595{
14596 struct drm_i915_private *dev_priv = dev->dev_private;
14597
14598 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14599 DRM_INFO("applying pipe b force quirk\n");
14600}
14601
435793df
KP		 14602/*
14603 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14604 */
14605static void quirk_ssc_force_disable(struct drm_device *dev)
14606{
14607 struct drm_i915_private *dev_priv = dev->dev_private;
14608 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14609 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14610}
14611
4dca20ef 14612/*
5a15ab5b
CE		 14613 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14614 * brightness value
4dca20ef
CE		 14615 */
14616static void quirk_invert_brightness(struct drm_device *dev)
14617{
14618 struct drm_i915_private *dev_priv = dev->dev_private;
14619 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14620 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14621}
14622
9c72cc6f
SD		 14623/* Some VBT's incorrectly indicate no backlight is present */
14624static void quirk_backlight_present(struct drm_device *dev)
14625{
14626 struct drm_i915_private *dev_priv = dev->dev_private;
14627 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14628 DRM_INFO("applying backlight present quirk\n");
14629}
14630
b690e96c
JB		 14631struct intel_quirk {
14632 int device;
14633 int subsystem_vendor;
14634 int subsystem_device;
14635 void (*hook)(struct drm_device *dev);
14636};
14637
5f85f176
EE		 14638/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14639struct intel_dmi_quirk {
14640 void (*hook)(struct drm_device *dev);
14641 const struct dmi_system_id (*dmi_id_list)[];
14642};
14643
14644static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14645{
14646 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14647 return 1;
14648}
14649
14650static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14651 {
14652 .dmi_id_list = &(const struct dmi_system_id[]) {
14653 {
14654 .callback = intel_dmi_reverse_brightness,
14655 .ident = "NCR Corporation",
14656 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14657 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14658 },
14659 },
14660 { } /* terminating entry */
14661 },
14662 .hook = quirk_invert_brightness,
14663 },
14664};
14665
c43b5634 14666static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14667 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14668 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14669
b690e96c
JB		 14670 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14671 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14672
5f080c0f
VS		 14673 /* 830 needs to leave pipe A & dpll A up */
14674 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14675
b6b5d049
VS		 14676 /* 830 needs to leave pipe B & dpll B up */
14677 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14678
435793df
KP		 14679 /* Lenovo U160 cannot use SSC on LVDS */
14680 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14681
14682 /* Sony Vaio Y cannot use SSC on LVDS */
14683 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14684
be505f64
AH		 14685 /* Acer Aspire 5734Z must invert backlight brightness */
14686 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14687
14688 /* Acer/eMachines G725 */
14689 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14690
14691 /* Acer/eMachines e725 */
14692 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14693
14694 /* Acer/Packard Bell NCL20 */
14695 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14696
14697 /* Acer Aspire 4736Z */
14698 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14699
14700 /* Acer Aspire 5336 */
14701 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14702
14703 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14704 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14705
dfb3d47b
SD		 14706 /* Acer C720 Chromebook (Core i3 4005U) */
14707 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14708
b2a9601c 14709 /* Apple Macbook 2,1 (Core 2 T7400) */
14710 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14711
d4967d8c
SD		 14712 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14713 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14714
14715 /* HP Chromebook 14 (Celeron 2955U) */
14716 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14717
14718 /* Dell Chromebook 11 */
14719 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14720};
14721
14722static void intel_init_quirks(struct drm_device *dev)
14723{
14724 struct pci_dev *d = dev->pdev;
14725 int i;
14726
14727 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14728 struct intel_quirk *q = &intel_quirks[i];
14729
14730 if (d->device == q->device &&
14731 (d->subsystem_vendor == q->subsystem_vendor ||
14732 q->subsystem_vendor == PCI_ANY_ID) &&
14733 (d->subsystem_device == q->subsystem_device ||
14734 q->subsystem_device == PCI_ANY_ID))
14735 q->hook(dev);
14736 }
5f85f176
EE		 14737 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14738 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14739 intel_dmi_quirks[i].hook(dev);
14740 }
b690e96c
JB		 14741}
14742
9cce37f4
JB		 14743/* Disable the VGA plane that we never use */
14744static void i915_disable_vga(struct drm_device *dev)
14745{
14746 struct drm_i915_private *dev_priv = dev->dev_private;
14747 u8 sr1;
766aa1c4 14748 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14749
2b37c616 14750 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14751 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14752 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14753 sr1 = inb(VGA_SR_DATA);
14754 outb(sr1 | 1<<5, VGA_SR_DATA);
14755 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14756 udelay(300);
14757
01f5a626 14758 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14759 POSTING_READ(vga_reg);
14760}
14761
f817586c
DV		 14762void intel_modeset_init_hw(struct drm_device *dev)
14763{
b6283055 14764 intel_update_cdclk(dev);
a8f78b58 14765 intel_prepare_ddi(dev);
f817586c 14766 intel_init_clock_gating(dev);
8090c6b9 14767 intel_enable_gt_powersave(dev);
f817586c
DV		 14768}
14769
79e53945
JB		 14770void intel_modeset_init(struct drm_device *dev)
14771{
652c393a 14772 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14773 int sprite, ret;
8cc87b75 14774 enum pipe pipe;
46f297fb 14775 struct intel_crtc *crtc;
79e53945
JB		 14776
14777 drm_mode_config_init(dev);
14778
14779 dev->mode_config.min_width = 0;
14780 dev->mode_config.min_height = 0;
14781
019d96cb
DA		 14782 dev->mode_config.preferred_depth = 24;
14783 dev->mode_config.prefer_shadow = 1;
14784
25bab385
TU		 14785 dev->mode_config.allow_fb_modifiers = true;
14786
e6ecefaa 14787 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14788
b690e96c
JB		 14789 intel_init_quirks(dev);
14790
1fa61106
ED		 14791 intel_init_pm(dev);
14792
e3c74757
BW		 14793 if (INTEL_INFO(dev)->num_pipes == 0)
14794 return;
14795
69f92f67
LW		 14796 /*
14797 * There may be no VBT; and if the BIOS enabled SSC we can
14798 * just keep using it to avoid unnecessary flicker. Whereas if the
14799 * BIOS isn't using it, don't assume it will work even if the VBT
14800 * indicates as much.
14801 */
14802 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14803 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14804 DREF_SSC1_ENABLE);
14805
14806 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14807 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14808 bios_lvds_use_ssc ? "en" : "dis",
14809 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14810 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14811 }
14812 }
14813
e70236a8 14814 intel_init_display(dev);
7c10a2b5 14815 intel_init_audio(dev);
e70236a8 14816
a6c45cf0
CW		 14817 if (IS_GEN2(dev)) {
14818 dev->mode_config.max_width = 2048;
14819 dev->mode_config.max_height = 2048;
14820 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14821 dev->mode_config.max_width = 4096;
14822 dev->mode_config.max_height = 4096;
79e53945 14823 } else {
a6c45cf0
CW		 14824 dev->mode_config.max_width = 8192;
14825 dev->mode_config.max_height = 8192;
79e53945 14826 }
068be561 14827
dc41c154
VS		 14828 if (IS_845G(dev) || IS_I865G(dev)) {
14829 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14830 dev->mode_config.cursor_height = 1023;
14831 } else if (IS_GEN2(dev)) {
068be561
DL		 14832 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14833 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14834 } else {
14835 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14836 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14837 }
14838
5d4545ae 14839 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14840
28c97730 14841 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14842 INTEL_INFO(dev)->num_pipes,
14843 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14844
055e393f 14845 for_each_pipe(dev_priv, pipe) {
8cc87b75 14846 intel_crtc_init(dev, pipe);
3bdcfc0c 14847 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14848 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14849 if (ret)
06da8da2 14850 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14851 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14852 }
79e53945
JB		 14853 }
14854
bfa7df01
VS		 14855 intel_update_czclk(dev_priv);
14856 intel_update_cdclk(dev);
14857
e72f9fbf 14858 intel_shared_dpll_init(dev);
ee7b9f93 14859
9cce37f4
JB		 14860 /* Just disable it once at startup */
14861 i915_disable_vga(dev);
79e53945 14862 intel_setup_outputs(dev);
11be49eb
CW		 14863
14864 /* Just in case the BIOS is doing something questionable. */
7733b49b 14865 intel_fbc_disable(dev_priv);
fa9fa083 14866
6e9f798d 14867 drm_modeset_lock_all(dev);
043e9bda 14868 intel_modeset_setup_hw_state(dev);
6e9f798d 14869 drm_modeset_unlock_all(dev);
46f297fb 14870
d3fcc808 14871 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 14872 struct intel_initial_plane_config plane_config = {};
14873
46f297fb
JB		 14874 if (!crtc->active)
14875 continue;
14876
46f297fb 14877 /*
46f297fb
JB		 14878 * Note that reserving the BIOS fb up front prevents us
14879 * from stuffing other stolen allocations like the ring
14880 * on top. This prevents some ugliness at boot time, and
14881 * can even allow for smooth boot transitions if the BIOS
14882 * fb is large enough for the active pipe configuration.
14883 */
eeebeac5
ML		 14884 dev_priv->display.get_initial_plane_config(crtc,
14885 &plane_config);
14886
14887 /*
14888 * If the fb is shared between multiple heads, we'll
14889 * just get the first one.
14890 */
14891 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14892 }
2c7111db
CW		 14893}
14894
7fad798e
DV		 14895static void intel_enable_pipe_a(struct drm_device *dev)
14896{
14897 struct intel_connector *connector;
14898 struct drm_connector *crt = NULL;
14899 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14900 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14901
14902 /* We can't just switch on the pipe A, we need to set things up with a
14903 * proper mode and output configuration. As a gross hack, enable pipe A
14904 * by enabling the load detect pipe once. */
3a3371ff 14905 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14906 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14907 crt = &connector->base;
14908 break;
14909 }
14910 }
14911
14912 if (!crt)
14913 return;
14914
208bf9fd 14915 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14916 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14917}
14918
fa555837
DV		 14919static bool
14920intel_check_plane_mapping(struct intel_crtc *crtc)
14921{
7eb552ae
BW		 14922 struct drm_device *dev = crtc->base.dev;
14923 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14924 u32 reg, val;
14925
7eb552ae 14926 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14927 return true;
14928
14929 reg = DSPCNTR(!crtc->plane);
14930 val = I915_READ(reg);
14931
14932 if ((val & DISPLAY_PLANE_ENABLE) &&
14933 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14934 return false;
14935
14936 return true;
14937}
14938
02e93c35
VS		 14939static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14940{
14941 struct drm_device *dev = crtc->base.dev;
14942 struct intel_encoder *encoder;
14943
14944 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14945 return true;
14946
14947 return false;
14948}
14949
24929352
DV		 14950static void intel_sanitize_crtc(struct intel_crtc *crtc)
14951{
14952 struct drm_device *dev = crtc->base.dev;
14953 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14954 u32 reg;
24929352 14955
24929352 14956 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14957 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14958 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14959
d3eaf884 14960 /* restore vblank interrupts to correct state */
9625604c 14961 drm_crtc_vblank_reset(&crtc->base);
d297e103 14962 if (crtc->active) {
f9cd7b88
VS		 14963 struct intel_plane *plane;
14964
9625604c 14965 drm_crtc_vblank_on(&crtc->base);
f9cd7b88
VS		 14966
14967 /* Disable everything but the primary plane */
14968 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14969 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14970 continue;
14971
14972 plane->disable_plane(&plane->base, &crtc->base);
14973 }
9625604c 14974 }
d3eaf884 14975
24929352 14976 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14977 * disable the crtc (and hence change the state) if it is wrong. Note
14978 * that gen4+ has a fixed plane -> pipe mapping. */
14979 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14980 bool plane;
14981
24929352
DV		 14982 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14983 crtc->base.base.id);
14984
14985 /* Pipe has the wrong plane attached and the plane is active.
14986 * Temporarily change the plane mapping and disable everything
14987 * ... */
14988 plane = crtc->plane;
b70709a6 14989 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14990 crtc->plane = !plane;
b17d48e2 14991 intel_crtc_disable_noatomic(&crtc->base);
24929352 14992 crtc->plane = plane;
24929352 14993 }
24929352 14994
7fad798e
DV		 14995 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14996 crtc->pipe == PIPE_A && !crtc->active) {
14997 /* BIOS forgot to enable pipe A, this mostly happens after
14998 * resume. Force-enable the pipe to fix this, the update_dpms
14999 * call below we restore the pipe to the right state, but leave
15000 * the required bits on. */
15001 intel_enable_pipe_a(dev);
15002 }
15003
24929352
DV		 15004 /* Adjust the state of the output pipe according to whether we
15005 * have active connectors/encoders. */
02e93c35 15006 if (!intel_crtc_has_encoders(crtc))
b17d48e2 15007 intel_crtc_disable_noatomic(&crtc->base);
24929352 15008
53d9f4e9 15009 if (crtc->active != crtc->base.state->active) {
02e93c35 15010 struct intel_encoder *encoder;
24929352
DV		 15011
15012 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15013 * functions or because of calls to intel_crtc_disable_noatomic,
15014 * or because the pipe is force-enabled due to the
24929352
DV		 15015 * pipe A quirk. */
15016 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15017 crtc->base.base.id,
83d65738 15018 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15019 crtc->active ? "enabled" : "disabled");
15020
4be40c98 15021 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 15022 crtc->base.state->active = crtc->active;
24929352
DV		 15023 crtc->base.enabled = crtc->active;
15024
15025 /* Because we only establish the connector -> encoder ->
15026 * crtc links if something is active, this means the
15027 * crtc is now deactivated. Break the links. connector
15028 * -> encoder links are only establish when things are
15029 * actually up, hence no need to break them. */
15030 WARN_ON(crtc->active);
15031
2d406bb0 15032 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 15033 encoder->base.crtc = NULL;
24929352 15034 }
c5ab3bc0 15035
a3ed6aad 15036 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15037 /*
15038 * We start out with underrun reporting disabled to avoid races.
15039 * For correct bookkeeping mark this on active crtcs.
15040 *
c5ab3bc0
DV		 15041 * Also on gmch platforms we dont have any hardware bits to
15042 * disable the underrun reporting. Which means we need to start
15043 * out with underrun reporting disabled also on inactive pipes,
15044 * since otherwise we'll complain about the garbage we read when
15045 * e.g. coming up after runtime pm.
15046 *
4cc31489
DV		 15047 * No protection against concurrent access is required - at
15048 * worst a fifo underrun happens which also sets this to false.
15049 */
15050 crtc->cpu_fifo_underrun_disabled = true;
15051 crtc->pch_fifo_underrun_disabled = true;
15052 }
24929352
DV		 15053}
15054
15055static void intel_sanitize_encoder(struct intel_encoder *encoder)
15056{
15057 struct intel_connector *connector;
15058 struct drm_device *dev = encoder->base.dev;
873ffe69 15059 bool active = false;
24929352
DV		 15060
15061 /* We need to check both for a crtc link (meaning that the
15062 * encoder is active and trying to read from a pipe) and the
15063 * pipe itself being active. */
15064 bool has_active_crtc = encoder->base.crtc &&
15065 to_intel_crtc(encoder->base.crtc)->active;
15066
873ffe69
ML		 15067 for_each_intel_connector(dev, connector) {
15068 if (connector->base.encoder != &encoder->base)
15069 continue;
15070
15071 active = true;
15072 break;
15073 }
15074
15075 if (active && !has_active_crtc) {
24929352
DV		 15076 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15077 encoder->base.base.id,
8e329a03 15078 encoder->base.name);
24929352
DV		 15079
15080 /* Connector is active, but has no active pipe. This is
15081 * fallout from our resume register restoring. Disable
15082 * the encoder manually again. */
15083 if (encoder->base.crtc) {
15084 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15085 encoder->base.base.id,
8e329a03 15086 encoder->base.name);
24929352 15087 encoder->disable(encoder);
a62d1497
VS		 15088 if (encoder->post_disable)
15089 encoder->post_disable(encoder);
24929352 15090 }
7f1950fb 15091 encoder->base.crtc = NULL;
24929352
DV		 15092
15093 /* Inconsistent output/port/pipe state happens presumably due to
15094 * a bug in one of the get_hw_state functions. Or someplace else
15095 * in our code, like the register restore mess on resume. Clamp
15096 * things to off as a safer default. */
3a3371ff 15097 for_each_intel_connector(dev, connector) {
24929352
DV		 15098 if (connector->encoder != encoder)
15099 continue;
7f1950fb
EE		 15100 connector->base.dpms = DRM_MODE_DPMS_OFF;
15101 connector->base.encoder = NULL;
24929352
DV		 15102 }
15103 }
15104 /* Enabled encoders without active connectors will be fixed in
15105 * the crtc fixup. */
15106}
15107
04098753 15108void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15109{
15110 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15111 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15112
04098753
ID		 15113 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15114 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15115 i915_disable_vga(dev);
15116 }
15117}
15118
15119void i915_redisable_vga(struct drm_device *dev)
15120{
15121 struct drm_i915_private *dev_priv = dev->dev_private;
15122
8dc8a27c
PZ		 15123 /* This function can be called both from intel_modeset_setup_hw_state or
15124 * at a very early point in our resume sequence, where the power well
15125 * structures are not yet restored. Since this function is at a very
15126 * paranoid "someone might have enabled VGA while we were not looking"
15127 * level, just check if the power well is enabled instead of trying to
15128 * follow the "don't touch the power well if we don't need it" policy
15129 * the rest of the driver uses. */
f458ebbc 15130 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15131 return;
15132
04098753 15133 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15134}
15135
f9cd7b88 15136static bool primary_get_hw_state(struct intel_plane *plane)
98ec7739 15137{
f9cd7b88 15138 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
98ec7739 15139
f9cd7b88 15140 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
d032ffa0
ML		 15141}
15142
f9cd7b88
VS		 15143/* FIXME read out full plane state for all planes */
15144static void readout_plane_state(struct intel_crtc *crtc)
d032ffa0 15145{
b26d3ea3 15146 struct drm_plane *primary = crtc->base.primary;
f9cd7b88 15147 struct intel_plane_state *plane_state =
b26d3ea3 15148 to_intel_plane_state(primary->state);
d032ffa0 15149
f9cd7b88 15150 plane_state->visible =
b26d3ea3
ML		 15151 primary_get_hw_state(to_intel_plane(primary));
15152
15153 if (plane_state->visible)
15154 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
98ec7739
VS		 15155}
15156
30e984df 15157static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15158{
15159 struct drm_i915_private *dev_priv = dev->dev_private;
15160 enum pipe pipe;
24929352
DV		 15161 struct intel_crtc *crtc;
15162 struct intel_encoder *encoder;
15163 struct intel_connector *connector;
5358901f 15164 int i;
24929352 15165
d3fcc808 15166 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15167 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15168 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15169 crtc->config->base.crtc = &crtc->base;
3b117c8f 15170
0e8ffe1b 15171 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15172 crtc->config);
24929352 15173
49d6fa21 15174 crtc->base.state->active = crtc->active;
24929352 15175 crtc->base.enabled = crtc->active;
b70709a6 15176
f9cd7b88 15177 readout_plane_state(crtc);
24929352
DV		 15178
15179 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15180 crtc->base.base.id,
15181 crtc->active ? "enabled" : "disabled");
15182 }
15183
5358901f
DV		 15184 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15185 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15186
3e369b76
ACO		 15187 pll->on = pll->get_hw_state(dev_priv, pll,
15188 &pll->config.hw_state);
5358901f 15189 pll->active = 0;
3e369b76 15190 pll->config.crtc_mask = 0;
d3fcc808 15191 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15192 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15193 pll->active++;
3e369b76 15194 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15195 }
5358901f 15196 }
5358901f 15197
1e6f2ddc 15198 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15199 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15200
3e369b76 15201 if (pll->config.crtc_mask)
bd2bb1b9 15202 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15203 }
15204
b2784e15 15205 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15206 pipe = 0;
15207
15208 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15209 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15210 encoder->base.crtc = &crtc->base;
6e3c9717 15211 encoder->get_config(encoder, crtc->config);
24929352
DV		 15212 } else {
15213 encoder->base.crtc = NULL;
15214 }
15215
6f2bcceb 15216 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15217 encoder->base.base.id,
8e329a03 15218 encoder->base.name,
24929352 15219 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15220 pipe_name(pipe));
24929352
DV		 15221 }
15222
3a3371ff 15223 for_each_intel_connector(dev, connector) {
24929352
DV		 15224 if (connector->get_hw_state(connector)) {
15225 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15226 connector->base.encoder = &connector->encoder->base;
15227 } else {
15228 connector->base.dpms = DRM_MODE_DPMS_OFF;
15229 connector->base.encoder = NULL;
15230 }
15231 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15232 connector->base.base.id,
c23cc417 15233 connector->base.name,
24929352
DV		 15234 connector->base.encoder ? "enabled" : "disabled");
15235 }
7f4c6284
VS		 15236
15237 for_each_intel_crtc(dev, crtc) {
15238 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15239
15240 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15241 if (crtc->base.state->active) {
15242 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15243 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15244 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15245
15246 /*
15247 * The initial mode needs to be set in order to keep
15248 * the atomic core happy. It wants a valid mode if the
15249 * crtc's enabled, so we do the above call.
15250 *
15251 * At this point some state updated by the connectors
15252 * in their ->detect() callback has not run yet, so
15253 * no recalculation can be done yet.
15254 *
15255 * Even if we could do a recalculation and modeset
15256 * right now it would cause a double modeset if
15257 * fbdev or userspace chooses a different initial mode.
15258 *
15259 * If that happens, someone indicated they wanted a
15260 * mode change, which means it's safe to do a full
15261 * recalculation.
15262 */
15263 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
9eca6832
VS		 15264
15265 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15266 update_scanline_offset(crtc);
7f4c6284
VS		 15267 }
15268 }
30e984df
DV		 15269}
15270
043e9bda
ML		 15271/* Scan out the current hw modeset state,
15272 * and sanitizes it to the current state
15273 */
15274static void
15275intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15276{
15277 struct drm_i915_private *dev_priv = dev->dev_private;
15278 enum pipe pipe;
30e984df
DV		 15279 struct intel_crtc *crtc;
15280 struct intel_encoder *encoder;
35c95375 15281 int i;
30e984df
DV		 15282
15283 intel_modeset_readout_hw_state(dev);
24929352
DV		 15284
15285 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15286 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15287 intel_sanitize_encoder(encoder);
15288 }
15289
055e393f 15290 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15291 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15292 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15293 intel_dump_pipe_config(crtc, crtc->config,
15294 "[setup_hw_state]");
24929352 15295 }
9a935856 15296
d29b2f9d
ACO		 15297 intel_modeset_update_connector_atomic_state(dev);
15298
35c95375
DV		 15299 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15300 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15301
15302 if (!pll->on || pll->active)
15303 continue;
15304
15305 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15306
15307 pll->disable(dev_priv, pll);
15308 pll->on = false;
15309 }
15310
26e1fe4f 15311 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15312 vlv_wm_get_hw_state(dev);
15313 else if (IS_GEN9(dev))
3078999f
PB		 15314 skl_wm_get_hw_state(dev);
15315 else if (HAS_PCH_SPLIT(dev))
243e6a44 15316 ilk_wm_get_hw_state(dev);
292b990e
ML		 15317
15318 for_each_intel_crtc(dev, crtc) {
15319 unsigned long put_domains;
15320
15321 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15322 if (WARN_ON(put_domains))
15323 modeset_put_power_domains(dev_priv, put_domains);
15324 }
15325 intel_display_set_init_power(dev_priv, false);
043e9bda 15326}
7d0bc1ea 15327
043e9bda
ML		 15328void intel_display_resume(struct drm_device *dev)
15329{
15330 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15331 struct intel_connector *conn;
15332 struct intel_plane *plane;
15333 struct drm_crtc *crtc;
15334 int ret;
f30da187 15335
043e9bda
ML		 15336 if (!state)
15337 return;
15338
15339 state->acquire_ctx = dev->mode_config.acquire_ctx;
15340
15341 /* preserve complete old state, including dpll */
15342 intel_atomic_get_shared_dpll_state(state);
15343
15344 for_each_crtc(dev, crtc) {
15345 struct drm_crtc_state *crtc_state =
15346 drm_atomic_get_crtc_state(state, crtc);
15347
15348 ret = PTR_ERR_OR_ZERO(crtc_state);
15349 if (ret)
15350 goto err;
15351
15352 /* force a restore */
15353 crtc_state->mode_changed = true;
45e2b5f6 15354 }
8af6cf88 15355
043e9bda
ML		 15356 for_each_intel_plane(dev, plane) {
15357 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15358 if (ret)
15359 goto err;
15360 }
15361
15362 for_each_intel_connector(dev, conn) {
15363 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15364 if (ret)
15365 goto err;
15366 }
15367
15368 intel_modeset_setup_hw_state(dev);
15369
15370 i915_redisable_vga(dev);
74c090b1 15371 ret = drm_atomic_commit(state);
043e9bda
ML		 15372 if (!ret)
15373 return;
15374
15375err:
15376 DRM_ERROR("Restoring old state failed with %i\n", ret);
15377 drm_atomic_state_free(state);
2c7111db
CW		 15378}
15379
15380void intel_modeset_gem_init(struct drm_device *dev)
15381{
484b41dd 15382 struct drm_crtc *c;
2ff8fde1 15383 struct drm_i915_gem_object *obj;
e0d6149b 15384 int ret;
484b41dd 15385
ae48434c
ID		 15386 mutex_lock(&dev->struct_mutex);
15387 intel_init_gt_powersave(dev);
15388 mutex_unlock(&dev->struct_mutex);
15389
1833b134 15390 intel_modeset_init_hw(dev);
02e792fb
DV		 15391
15392 intel_setup_overlay(dev);
484b41dd
JB		 15393
15394 /*
15395 * Make sure any fbs we allocated at startup are properly
15396 * pinned & fenced. When we do the allocation it's too early
15397 * for this.
15398 */
70e1e0ec 15399 for_each_crtc(dev, c) {
2ff8fde1
MR		 15400 obj = intel_fb_obj(c->primary->fb);
15401 if (obj == NULL)
484b41dd
JB		 15402 continue;
15403
e0d6149b
TU		 15404 mutex_lock(&dev->struct_mutex);
15405 ret = intel_pin_and_fence_fb_obj(c->primary,
15406 c->primary->fb,
15407 c->primary->state,
91af127f 15408 NULL, NULL);
e0d6149b
TU		 15409 mutex_unlock(&dev->struct_mutex);
15410 if (ret) {
484b41dd
JB		 15411 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15412 to_intel_crtc(c)->pipe);
66e514c1
DA		 15413 drm_framebuffer_unreference(c->primary->fb);
15414 c->primary->fb = NULL;
36750f28 15415 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15416 update_state_fb(c->primary);
36750f28 15417 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15418 }
15419 }
0962c3c9
VS		 15420
15421 intel_backlight_register(dev);
79e53945
JB		 15422}
15423
4932e2c3
ID		 15424void intel_connector_unregister(struct intel_connector *intel_connector)
15425{
15426 struct drm_connector *connector = &intel_connector->base;
15427
15428 intel_panel_destroy_backlight(connector);
34ea3d38 15429 drm_connector_unregister(connector);
4932e2c3
ID		 15430}
15431
79e53945
JB		 15432void intel_modeset_cleanup(struct drm_device *dev)
15433{
652c393a 15434 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15435 struct drm_connector *connector;
652c393a 15436
2eb5252e
ID		 15437 intel_disable_gt_powersave(dev);
15438
0962c3c9
VS		 15439 intel_backlight_unregister(dev);
15440
fd0c0642
DV		 15441 /*
15442 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15443 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15444 * experience fancy races otherwise.
15445 */
2aeb7d3a 15446 intel_irq_uninstall(dev_priv);
eb21b92b 15447
fd0c0642
DV		 15448 /*
15449 * Due to the hpd irq storm handling the hotplug work can re-arm the
15450 * poll handlers. Hence disable polling after hpd handling is shut down.
15451 */
f87ea761 15452 drm_kms_helper_poll_fini(dev);
fd0c0642 15453
723bfd70
JB		 15454 intel_unregister_dsm_handler();
15455
7733b49b 15456 intel_fbc_disable(dev_priv);
69341a5e 15457
1630fe75
CW		 15458 /* flush any delayed tasks or pending work */
15459 flush_scheduled_work();
15460
db31af1d
JN		 15461 /* destroy the backlight and sysfs files before encoders/connectors */
15462 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15463 struct intel_connector *intel_connector;
15464
15465 intel_connector = to_intel_connector(connector);
15466 intel_connector->unregister(intel_connector);
db31af1d 15467 }
d9255d57 15468
79e53945 15469 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15470
15471 intel_cleanup_overlay(dev);
ae48434c
ID		 15472
15473 mutex_lock(&dev->struct_mutex);
15474 intel_cleanup_gt_powersave(dev);
15475 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15476}
15477
f1c79df3
ZW		 15478/*
15479 * Return which encoder is currently attached for connector.
15480 */
df0e9248 15481struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15482{
df0e9248
CW		 15483 return &intel_attached_encoder(connector)->base;
15484}
f1c79df3 15485
df0e9248
CW		 15486void intel_connector_attach_encoder(struct intel_connector *connector,
15487 struct intel_encoder *encoder)
15488{
15489 connector->encoder = encoder;
15490 drm_mode_connector_attach_encoder(&connector->base,
15491 &encoder->base);
79e53945 15492}
28d52043
DA		 15493
15494/*
15495 * set vga decode state - true == enable VGA decode
15496 */
15497int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15498{
15499 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15500 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15501 u16 gmch_ctrl;
15502
75fa041d
CW		 15503 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15504 DRM_ERROR("failed to read control word\n");
15505 return -EIO;
15506 }
15507
c0cc8a55
CW		 15508 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15509 return 0;
15510
28d52043
DA		 15511 if (state)
15512 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15513 else
15514 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15515
15516 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15517 DRM_ERROR("failed to write control word\n");
15518 return -EIO;
15519 }
15520
28d52043
DA		 15521 return 0;
15522}
c4a1d9e4 15523
c4a1d9e4 15524struct intel_display_error_state {
ff57f1b0
PZ		 15525
15526 u32 power_well_driver;
15527
63b66e5b
CW		 15528 int num_transcoders;
15529
c4a1d9e4
CW		 15530 struct intel_cursor_error_state {
15531 u32 control;
15532 u32 position;
15533 u32 base;
15534 u32 size;
52331309 15535 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15536
15537 struct intel_pipe_error_state {
ddf9c536 15538 bool power_domain_on;
c4a1d9e4 15539 u32 source;
f301b1e1 15540 u32 stat;
52331309 15541 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15542
15543 struct intel_plane_error_state {
15544 u32 control;
15545 u32 stride;
15546 u32 size;
15547 u32 pos;
15548 u32 addr;
15549 u32 surface;
15550 u32 tile_offset;
52331309 15551 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15552
15553 struct intel_transcoder_error_state {
ddf9c536 15554 bool power_domain_on;
63b66e5b
CW		 15555 enum transcoder cpu_transcoder;
15556
15557 u32 conf;
15558
15559 u32 htotal;
15560 u32 hblank;
15561 u32 hsync;
15562 u32 vtotal;
15563 u32 vblank;
15564 u32 vsync;
15565 } transcoder[4];
c4a1d9e4
CW		 15566};
15567
15568struct intel_display_error_state *
15569intel_display_capture_error_state(struct drm_device *dev)
15570{
fbee40df 15571 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15572 struct intel_display_error_state *error;
63b66e5b
CW		 15573 int transcoders[] = {
15574 TRANSCODER_A,
15575 TRANSCODER_B,
15576 TRANSCODER_C,
15577 TRANSCODER_EDP,
15578 };
c4a1d9e4
CW		 15579 int i;
15580
63b66e5b
CW		 15581 if (INTEL_INFO(dev)->num_pipes == 0)
15582 return NULL;
15583
9d1cb914 15584 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15585 if (error == NULL)
15586 return NULL;
15587
190be112 15588 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15589 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15590
055e393f 15591 for_each_pipe(dev_priv, i) {
ddf9c536 15592 error->pipe[i].power_domain_on =
f458ebbc
DV		 15593 __intel_display_power_is_enabled(dev_priv,
15594 POWER_DOMAIN_PIPE(i));
ddf9c536 15595 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15596 continue;
15597
5efb3e28
VS		 15598 error->cursor[i].control = I915_READ(CURCNTR(i));
15599 error->cursor[i].position = I915_READ(CURPOS(i));
15600 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15601
15602 error->plane[i].control = I915_READ(DSPCNTR(i));
15603 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15604 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15605 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15606 error->plane[i].pos = I915_READ(DSPPOS(i));
15607 }
ca291363
PZ		 15608 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15609 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15610 if (INTEL_INFO(dev)->gen >= 4) {
15611 error->plane[i].surface = I915_READ(DSPSURF(i));
15612 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15613 }
15614
c4a1d9e4 15615 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15616
3abfce77 15617 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15618 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15619 }
15620
15621 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15622 if (HAS_DDI(dev_priv->dev))
15623 error->num_transcoders++; /* Account for eDP. */
15624
15625 for (i = 0; i < error->num_transcoders; i++) {
15626 enum transcoder cpu_transcoder = transcoders[i];
15627
ddf9c536 15628 error->transcoder[i].power_domain_on =
f458ebbc 15629 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15630 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15631 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15632 continue;
15633
63b66e5b
CW		 15634 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15635
15636 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15637 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15638 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15639 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15640 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15641 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15642 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15643 }
15644
15645 return error;
15646}
15647
edc3d884
MK		 15648#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15649
c4a1d9e4 15650void
edc3d884 15651intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15652 struct drm_device *dev,
15653 struct intel_display_error_state *error)
15654{
055e393f 15655 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15656 int i;
15657
63b66e5b
CW		 15658 if (!error)
15659 return;
15660
edc3d884 15661 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15662 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15663 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15664 error->power_well_driver);
055e393f 15665 for_each_pipe(dev_priv, i) {
edc3d884 15666 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15667 err_printf(m, " Power: %s\n",
15668 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15669 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15670 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15671
15672 err_printf(m, "Plane [%d]:\n", i);
15673 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15674 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15675 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15676 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15677 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15678 }
4b71a570 15679 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15680 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15681 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15682 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15683 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15684 }
15685
edc3d884
MK		 15686 err_printf(m, "Cursor [%d]:\n", i);
15687 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15688 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15689 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15690 }
63b66e5b
CW		 15691
15692 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15693 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15694 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15695 err_printf(m, " Power: %s\n",
15696 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15697 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15698 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15699 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15700 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15701 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15702 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15703 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15704 }
c4a1d9e4 15705}
e2fcdaa9
VS		 15706
15707void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15708{
15709 struct intel_crtc *crtc;
15710
15711 for_each_intel_crtc(dev, crtc) {
15712 struct intel_unpin_work *work;
e2fcdaa9 15713
5e2d7afc 15714 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15715
15716 work = crtc->unpin_work;
15717
15718 if (work && work->event &&
15719 work->event->base.file_priv == file) {
15720 kfree(work->event);
15721 work->event = NULL;
15722 }
15723
5e2d7afc 15724 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15725 }
15726}
Linux kernel - Deliverables
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