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drm/i915: Don't display the boot CDCLK twice
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB		 91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV		 95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML		 113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA		 116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB		 126} intel_range_t;
127
128typedef struct {
0206e353
AJ		 129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB		 131} intel_p2_t;
132
d4906093
ML		 133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ		 135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV		 139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW		 149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW		 152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW		 157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ		 163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 170};
171
5d536e28
DV		 172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV		 176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP		 265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP		 279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 307};
308
273e27ca
EA		 309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 394};
395
ef9348c8
CML		 396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID		 412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS		 424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS		 430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 432}
433
e0638cdf
PZ		 434/**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
4093561b 437bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 438{
409ee761 439 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 440 struct intel_encoder *encoder;
441
409ee761 442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 443 if (encoder->type == type)
444 return true;
445
446 return false;
447}
448
d0737e1d
ACO		 449/**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
a93e255f
ACO		 455static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
d0737e1d 457{
a93e255f 458 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 459 struct drm_connector *connector;
a93e255f 460 struct drm_connector_state *connector_state;
d0737e1d 461 struct intel_encoder *encoder;
a93e255f
ACO		 462 int i, num_connectors = 0;
463
da3ced29 464 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
d0737e1d 469
a93e255f
ACO		 470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
d0737e1d 472 return true;
a93e255f
ACO		 473 }
474
475 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 476
477 return false;
478}
479
a93e255f
ACO		 480static const intel_limit_t *
481intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 482{
a93e255f 483 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 484 const intel_limit_t *limit;
b91ad0ec 485
a93e255f 486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 487 if (intel_is_dual_link_lvds(dev)) {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW		 489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
c6bb3538 498 } else
b91ad0ec 499 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 500
501 return limit;
502}
503
a93e255f
ACO		 504static const intel_limit_t *
505intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 506{
a93e255f 507 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 508 const intel_limit_t *limit;
509
a93e255f 510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 511 if (intel_is_dual_link_lvds(dev))
e4b36699 512 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 513 else
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
a93e255f 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
044c7c41 520 } else /* The option is for other outputs */
e4b36699 521 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 530 const intel_limit_t *limit;
531
5ab7b0b7
ID		 532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
a93e255f 535 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 536 else if (IS_G4X(dev)) {
a93e255f 537 limit = intel_g4x_limit(crtc_state);
f2b115e6 538 } else if (IS_PINEVIEW(dev)) {
a93e255f 539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 540 limit = &intel_limits_pineview_lvds;
2177832f 541 else
f2b115e6 542 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
a0c4da24 545 } else if (IS_VALLEYVIEW(dev)) {
dc730512 546 limit = &intel_limits_vlv;
a6c45cf0 547 } else if (!IS_GEN2(dev)) {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
79e53945 552 } else {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 554 limit = &intel_limits_i8xx_lvds;
a93e255f 555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 556 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 557 else
558 limit = &intel_limits_i8xx_dac;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
fb03ac01
VS		 570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 572}
573
7429e9d4
DV		 574static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575{
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577}
578
ac58c3f0 579static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 580{
7429e9d4 581 clock->m = i9xx_dpll_compute_m(clock);
79e53945 582 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
fb03ac01
VS		 585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 587}
588
ef9348c8
CML		 589static void chv_clock(int refclk, intel_clock_t *clock)
590{
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598}
599
7c04d1d9 600#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 601/**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
1b894b59
CW		 606static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
79e53945 609{
f01b7962
VS		 610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
79e53945 612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 613 INTELPllInvalid("p1 out of range\n");
79e53945 614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 615 INTELPllInvalid("m2 out of range\n");
79e53945 616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 617 INTELPllInvalid("m1 out of range\n");
f01b7962 618
5ab7b0b7 619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
5ab7b0b7 623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
79e53945 630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 631 INTELPllInvalid("vco out of range\n");
79e53945
JB		 632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 636 INTELPllInvalid("dot out of range\n");
79e53945
JB		 637
638 return true;
639}
640
d4906093 641static bool
a93e255f
ACO		 642i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
cec2f356
SP		 644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
79e53945 646{
a93e255f 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 648 struct drm_device *dev = crtc->base.dev;
79e53945 649 intel_clock_t clock;
79e53945
JB		 650 int err = target;
651
a93e255f 652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 653 /*
a210b028
DV		 654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
79e53945 657 */
1974cad0 658 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
0206e353 669 memset(best_clock, 0, sizeof(*best_clock));
79e53945 670
42158660
ZY		 671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 675 if (clock.m2 >= clock.m1)
42158660
ZY		 676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 681 int this_err;
682
ac58c3f0
DV		 683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702}
703
704static bool
a93e255f
ACO		 705pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
79e53945 709{
a93e255f 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 711 struct drm_device *dev = crtc->base.dev;
79e53945 712 intel_clock_t clock;
79e53945
JB		 713 int err = target;
714
a93e255f 715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 716 /*
a210b028
DV		 717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
79e53945 720 */
1974cad0 721 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
0206e353 732 memset(best_clock, 0, sizeof(*best_clock));
79e53945 733
42158660
ZY		 734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 742 int this_err;
743
ac58c3f0 744 pineview_clock(refclk, &clock);
1b894b59
CW		 745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
79e53945 747 continue;
cec2f356
SP		 748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
79e53945
JB		 751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763}
764
d4906093 765static bool
a93e255f
ACO		 766g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
d4906093 770{
a93e255f 771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 772 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 773 intel_clock_t clock;
774 int max_n;
775 bool found;
6ba770dc
AJ		 776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 778 found = false;
779
a93e255f 780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 781 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
f77f13e2 794 /* based on hardware requirement, prefer smaller n to precision */
d4906093 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 796 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
ac58c3f0 805 i9xx_clock(refclk, &clock);
1b894b59
CW		 806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
d4906093 808 continue;
1b894b59
CW		 809
810 this_err = abs(clock.dot - target);
d4906093
ML		 811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
2c07245f
ZW		 821 return found;
822}
823
d5dd62bd
ID		 824/*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833{
9ca3ba01
ID		 834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
24be4e46
ID		 844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
d5dd62bd
ID		 847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862}
863
a0c4da24 864static bool
a93e255f
ACO		 865vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
a0c4da24 869{
a93e255f 870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 871 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 872 intel_clock_t clock;
69e4f900 873 unsigned int bestppm = 1000000;
27e639bf
VS		 874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 876 bool found = false;
a0c4da24 877
6b4bf1c4
VS		 878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 881
882 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 887 clock.p = clock.p1 * clock.p2;
a0c4da24 888 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 890 unsigned int ppm;
69e4f900 891
6b4bf1c4
VS		 892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
43b0ac53 896
f01b7962
VS		 897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
43b0ac53
VS		 899 continue;
900
d5dd62bd
ID		 901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
6b4bf1c4 906
d5dd62bd
ID		 907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
a0c4da24
JB		 910 }
911 }
912 }
913 }
a0c4da24 914
49e497ef 915 return found;
a0c4da24 916}
a4fc5ed6 917
ef9348c8 918static bool
a93e255f
ACO		 919chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923{
a93e255f 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 925 struct drm_device *dev = crtc->base.dev;
9ca3ba01 926 unsigned int best_error_ppm;
ef9348c8
CML		 927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 932 best_error_ppm = 1000000;
ef9348c8
CML		 933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 946 unsigned int error_ppm;
ef9348c8
CML		 947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
9ca3ba01
ID		 963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
ef9348c8
CML		 970 }
971 }
972
973 return found;
974}
975
5ab7b0b7
ID		 976bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978{
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983}
984
20ddf665
VS		 985bool intel_crtc_active(struct drm_crtc *crtc)
986{
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
241bfc38 992 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 993 * as Haswell has gained clock readout/fastboot support.
994 *
66e514c1 995 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 996 * properly reconstruct framebuffers.
c3d1f436
MR		 997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
20ddf665 1001 */
c3d1f436 1002 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1004}
1005
a5c961d1
PZ		 1006enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008{
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
6e3c9717 1012 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1013}
1014
fbf49ea2
VS		 1015static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032}
1033
ab7ad7f6
KP		 1034/*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1036 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
ab7ad7f6
KP		 1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
58e10eb9 1048 *
9d0498a2 1049 */
575f7ab7 1050static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1051{
575f7ab7 1052 struct drm_device *dev = crtc->base.dev;
9d0498a2 1053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1055 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1058 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1059
1060 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 } else {
ab7ad7f6 1065 /* Wait for the display line to settle */
fbf49ea2 1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1067 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1068 }
79e53945
JB		 1069}
1070
b0ea7d37
DL		 1071/*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080{
1081 u32 bit;
1082
c36346e3 1083 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1084 switch (port->port) {
c36346e3
DL		 1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
eba905b2 1098 switch (port->port) {
c36346e3
DL		 1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
b0ea7d37
DL		 1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114}
1115
b24e7179
JB		 1116static const char *state_string(bool enabled)
1117{
1118 return enabled ? "on" : "off";
1119}
1120
1121/* Only for pre-ILK configs */
55607e8a
DV		 1122void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
b24e7179
JB		 1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1132 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
b24e7179 1136
23538ef1
JN		 1137/* XXX: the dsi pll is shared between MIPI DSI ports */
1138static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139{
1140 u32 val;
1141 bool cur_state;
1142
a580516d 1143 mutex_lock(&dev_priv->sb_lock);
23538ef1 1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1145 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1146
1147 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1148 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151}
1152#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
55607e8a 1155struct intel_shared_dpll *
e2b78267
DV		 1156intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157{
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
6e3c9717 1160 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1161 return NULL;
1162
6e3c9717 1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1164}
1165
040484af 1166/* For ILK+ */
55607e8a
DV		 1167void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
040484af 1170{
040484af 1171 bool cur_state;
5358901f 1172 struct intel_dpll_hw_state hw_state;
040484af 1173
92b27b08 1174 if (WARN (!pll,
46edb027 1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1176 return;
ee7b9f93 1177
5358901f 1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1179 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
040484af 1182}
040484af
JB		 1183
1184static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186{
1187 int reg;
1188 u32 val;
1189 bool cur_state;
ad80a810
PZ		 1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
040484af 1192
affa9354
PZ		 1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
ad80a810 1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1196 val = I915_READ(reg);
ad80a810 1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
e2c719b7 1203 I915_STATE_WARN(cur_state != state,
040484af
JB		 1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206}
1207#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212{
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
d63fa0dc
PZ		 1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1220 I915_STATE_WARN(cur_state != state,
040484af
JB		 1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223}
1224#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229{
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
3d13ef2e 1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1235 return;
1236
bf507ef7 1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1238 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1239 return;
1240
040484af
JB		 1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
e2c719b7 1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1244}
1245
55607e8a
DV		 1246void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
040484af
JB		 1248{
1249 int reg;
1250 u32 val;
55607e8a 1251 bool cur_state;
040484af
JB		 1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
55607e8a 1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
040484af
JB		 1259}
1260
b680c37a
DV		 1261void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
ea0760cf 1263{
bedd4dba
JN		 1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
ea0760cf
JB		 1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
0de3b485 1268 bool locked = true;
ea0760cf 1269
bedd4dba
JN		 1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
ea0760cf 1276 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
ea0760cf
JB		 1287 } else {
1288 pp_reg = PP_CONTROL;
bedd4dba
JN		 1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
ea0760cf
JB		 1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1296 locked = false;
1297
e2c719b7 1298 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1299 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1300 pipe_name(pipe));
ea0760cf
JB		 1301}
1302
93ce0ba6
JN		 1303static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305{
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
d9d82081 1309 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1311 else
5efb3e28 1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1313
e2c719b7 1314 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317}
1318#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
b840d907
JB		 1321void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
b24e7179
JB		 1323{
1324 int reg;
1325 u32 val;
63d7bbe9 1326 bool cur_state;
702e7a56
PZ		 1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
b24e7179 1329
b6b5d049
VS		 1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1333 state = true;
1334
f458ebbc 1335 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
63d7bbe9 1345 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1346 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
b24e7179
JB		 1351{
1352 int reg;
1353 u32 val;
931872fc 1354 bool cur_state;
b24e7179
JB		 1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
931872fc 1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1359 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1362}
1363
931872fc
CW		 1364#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
b24e7179
JB		 1367static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369{
653e1026 1370 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
653e1026
VS		 1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
e2c719b7 1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
19ec1358 1382 return;
28c05794 1383 }
19ec1358 1384
b24e7179 1385 /* Need to check both planes against the pipe */
055e393f 1386 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1394 }
1395}
1396
19332d7a
JB		 1397static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
20674eef 1400 struct drm_device *dev = dev_priv->dev;
1fe47785 1401 int reg, sprite;
19332d7a
JB		 1402 u32 val;
1403
7feb8b88 1404 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1406 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1412 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1413 reg = SPCNTR(pipe, sprite);
20674eef 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1417 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
19332d7a 1421 val = I915_READ(reg);
e2c719b7 1422 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1430 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1431 }
1432}
1433
08c71e5e
VS		 1434static void assert_vblank_disabled(struct drm_crtc *crtc)
1435{
e2c719b7 1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1437 drm_crtc_vblank_put(crtc);
1438}
1439
89eff4be 1440static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1441{
1442 u32 val;
1443 bool enabled;
1444
e2c719b7 1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1446
92f2584a
JB		 1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1451}
1452
ab9412ba
DV		 1453static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
92f2584a
JB		 1455{
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
ab9412ba 1460 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1463 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
92f2584a
JB		 1466}
1467
4e634389
KP		 1468static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1470{
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
44f37d1f
CML		 1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
f0575e92
KP		 1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487}
1488
1519b995
KP		 1489static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
dc0fa718 1492 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1497 return false;
44f37d1f
CML		 1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1519b995 1501 } else {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1503 return false;
1504 }
1505 return true;
1506}
1507
1508static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510{
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
1524static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537}
1538
291906f1 1539static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1540 enum pipe pipe, int reg, u32 port_sel)
291906f1 1541{
47a05eca 1542 u32 val = I915_READ(reg);
e2c719b7 1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1545 reg, pipe_name(pipe));
de9a35ab 1546
e2c719b7 1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1548 && (val & DP_PIPEB_SELECT),
de9a35ab 1549 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1550}
1551
1552static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554{
47a05eca 1555 u32 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 reg, pipe_name(pipe));
de9a35ab 1559
e2c719b7 1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1561 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1562 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1563}
1564
1565static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567{
1568 int reg;
1569 u32 val;
291906f1 1570
f0575e92
KP		 1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
e2c719b7 1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1579 pipe_name(pipe));
291906f1
JB		 1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
e2debe91
PZ		 1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1590}
1591
40e9cf64
JB		 1592static void intel_init_dpio(struct drm_device *dev)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
a09caddd
CML		 1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
5382f5f3
JB		 1610}
1611
d288f65f 1612static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
87442f73 1614{
426115cf
DV		 1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
d288f65f 1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1619
426115cf 1620 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1626 if (IS_MOBILE(dev_priv->dev))
426115cf 1627 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1628
426115cf
DV		 1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
d288f65f 1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1637 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1638
1639 /* We do this three times for luck */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
DV		 1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
DV		 1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649}
1650
d288f65f 1651static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1652 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1653{
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
a580516d 1664 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
54433e91
VS		 1671 mutex_unlock(&dev_priv->sb_lock);
1672
9d556c99
CML		 1673 /*
1674 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1675 */
1676 udelay(1);
1677
1678 /* Enable PLL */
d288f65f 1679 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1680
1681 /* Check PLL is locked */
a11b0703 1682 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1683 DRM_ERROR("PLL %d failed to lock\n", pipe);
1684
a11b0703 1685 /* not sure when this should be written */
d288f65f 1686 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1687 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1688}
1689
1c4e0274
VS		 1690static int intel_num_dvo_pipes(struct drm_device *dev)
1691{
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
409ee761 1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1698
1699 return count;
1700}
1701
66e3d5c0 1702static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1703{
66e3d5c0
DV		 1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
6e3c9717 1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1708
66e3d5c0 1709 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1710
63d7bbe9 1711 /* No really, not for ILK+ */
3d13ef2e 1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1713
1714 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1717
1c4e0274
VS		 1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
66e3d5c0
DV		 1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1737 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
63d7bbe9
JB		 1746
1747 /* We do this three times for luck */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757}
1758
1759/**
50b44a44 1760 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1c4e0274 1768static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1769{
1c4e0274
VS		 1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
409ee761 1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
b6b5d049
VS		 1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
50b44a44
DV		 1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1794}
1795
f6071166
JB		 1796static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797{
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
e5cbfbfb
ID		 1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
f6071166 1807 if (pipe == PIPE_B)
e5cbfbfb 1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1811
1812}
1813
1814static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815{
d752048d 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1817 u32 val;
1818
a11b0703
VS		 1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1821
a11b0703 1822 /* Set PLL en = 0 */
d17ec4ce 1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
d752048d 1828
a580516d 1829 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
61407f6d
VS		 1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
a580516d 1847 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1848}
1849
e4607fcf 1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
89b667f8
JB		 1853{
1854 u32 port_mask;
00fc31b7 1855 int dpll_reg;
89b667f8 1856
e4607fcf
CML		 1857 switch (dport->port) {
1858 case PORT_B:
89b667f8 1859 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
e4607fcf
CML		 1861 break;
1862 case PORT_C:
89b667f8 1863 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1864 dpll_reg = DPLL(0);
9b6de0a1 1865 expected_mask <<= 4;
00fc31b7
CML		 1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1870 break;
1871 default:
1872 BUG();
1873 }
89b667f8 1874
9b6de0a1
VS		 1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1878}
1879
b14b1055
DV		 1880static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881{
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
be19f0ff
CW		 1886 if (WARN_ON(pll == NULL))
1887 return;
1888
3e369b76 1889 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897}
1898
92f2584a 1899/**
85b3894f 1900 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
85b3894f 1907static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1908{
3d13ef2e
DL		 1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1912
87a875bb 1913 if (WARN_ON(pll == NULL))
48da64a8
CW		 1914 return;
1915
3e369b76 1916 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1917 return;
ee7b9f93 1918
74dd6928 1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1920 pll->name, pll->active, pll->on,
e2b78267 1921 crtc->base.base.id);
92f2584a 1922
cdbd2316
DV		 1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
e9d6944e 1925 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1926 return;
1927 }
f4a091c7 1928 WARN_ON(pll->on);
ee7b9f93 1929
bd2bb1b9
PZ		 1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
46edb027 1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1933 pll->enable(dev_priv, pll);
ee7b9f93 1934 pll->on = true;
92f2584a
JB		 1935}
1936
f6daaec2 1937static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1938{
3d13ef2e
DL		 1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1942
92f2584a 1943 /* PCH only available on ILK+ */
3d13ef2e 1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1945 if (WARN_ON(pll == NULL))
ee7b9f93 1946 return;
92f2584a 1947
3e369b76 1948 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1949 return;
7a419866 1950
46edb027
DV		 1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
e2b78267 1953 crtc->base.base.id);
7a419866 1954
48da64a8 1955 if (WARN_ON(pll->active == 0)) {
e9d6944e 1956 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1957 return;
1958 }
1959
e9d6944e 1960 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1961 WARN_ON(!pll->on);
cdbd2316 1962 if (--pll->active)
7a419866 1963 return;
ee7b9f93 1964
46edb027 1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1966 pll->disable(dev_priv, pll);
ee7b9f93 1967 pll->on = false;
bd2bb1b9
PZ		 1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1970}
1971
b8a4f404
PZ		 1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
040484af 1974{
23670b32 1975 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1978 uint32_t reg, val, pipeconf_val;
040484af
JB		 1979
1980 /* PCH only available on ILK+ */
55522f37 1981 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1982
1983 /* Make sure PCH DPLL is enabled */
e72f9fbf 1984 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1985 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
23670b32
DV		 1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
59c859d6 1998 }
23670b32 1999
ab9412ba 2000 reg = PCH_TRANSCONF(pipe);
040484af 2001 val = I915_READ(reg);
5f7f726d 2002 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
dfd07d72
DV		 2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2011 }
5f7f726d
PZ		 2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2015 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
040484af
JB		 2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2026}
2027
8fb033d7 2028static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2029 enum transcoder cpu_transcoder)
040484af 2030{
8fb033d7 2031 u32 val, pipeconf_val;
8fb033d7
PZ		 2032
2033 /* PCH only available on ILK+ */
55522f37 2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2035
8fb033d7 2036 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2039
223a6fdf
PZ		 2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
25f3ef11 2045 val = TRANS_ENABLE;
937bb610 2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2047
9a76b1c6
PZ		 2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
a35f2679 2050 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
ab9412ba
DV		 2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2056 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2057}
2058
b8a4f404
PZ		 2059static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
040484af 2061{
23670b32
DV		 2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
040484af
JB		 2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
291906f1
JB		 2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
ab9412ba 2072 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
040484af
JB		 2087}
2088
ab4d966c 2089static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2090{
8fb033d7
PZ		 2091 u32 val;
2092
ab9412ba 2093 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2094 val &= ~TRANS_ENABLE;
ab9412ba 2095 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2096 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2098 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2103 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2104}
2105
b24e7179 2106/**
309cfea8 2107 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2108 * @crtc: crtc responsible for the pipe
b24e7179 2109 *
0372264a 2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2112 */
e1fdc473 2113static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2114{
0372264a
PZ		 2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
1a240d4d 2120 enum pipe pch_transcoder;
b24e7179
JB		 2121 int reg;
2122 u32 val;
2123
58c6eaa2 2124 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2125 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2126 assert_sprites_disabled(dev_priv, pipe);
2127
681e5811 2128 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
b24e7179
JB		 2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
50360403 2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
040484af 2143 else {
6e3c9717 2144 if (crtc->config->has_pch_encoder) {
040484af 2145 /* if driving the PCH, we need FDI enabled */
cc391bbb 2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
040484af
JB		 2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
b24e7179 2152
702e7a56 2153 reg = PIPECONF(cpu_transcoder);
b24e7179 2154 val = I915_READ(reg);
7ad25d48 2155 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2158 return;
7ad25d48 2159 }
00d70b15
CW		 2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2162 POSTING_READ(reg);
b24e7179
JB		 2163}
2164
2165/**
309cfea8 2166 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2167 * @crtc: crtc whose pipes is to be disabled
b24e7179 2168 *
575f7ab7
VS		 2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
b24e7179
JB		 2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
575f7ab7 2175static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2176{
575f7ab7 2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2179 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2188 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2189 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2190
702e7a56 2191 reg = PIPECONF(cpu_transcoder);
b24e7179 2192 val = I915_READ(reg);
00d70b15
CW		 2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
67adc644
VS		 2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
6e3c9717 2200 if (crtc->config->double_wide)
67adc644
VS		 2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2211}
2212
2213/**
262ca2b0 2214 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2215 * @plane: plane to be enabled
2216 * @crtc: crtc for the plane
b24e7179 2217 *
fdd508a6 2218 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2219 */
fdd508a6
VS		 2220static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2221 struct drm_crtc *crtc)
b24e7179 2222{
fdd508a6
VS		 2223 struct drm_device *dev = plane->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2226
2227 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2228 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2229 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2230
fdd508a6
VS		 2231 dev_priv->display.update_primary_plane(crtc, plane->fb,
2232 crtc->x, crtc->y);
b24e7179
JB		 2233}
2234
693db184
CW		 2235static bool need_vtd_wa(struct drm_device *dev)
2236{
2237#ifdef CONFIG_INTEL_IOMMU
2238 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2239 return true;
2240#endif
2241 return false;
2242}
2243
50470bb0 2244unsigned int
6761dd31
TU		 2245intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2246 uint64_t fb_format_modifier)
a57ce0b2 2247{
6761dd31
TU		 2248 unsigned int tile_height;
2249 uint32_t pixel_bytes;
a57ce0b2 2250
b5d0e9bf
DL		 2251 switch (fb_format_modifier) {
2252 case DRM_FORMAT_MOD_NONE:
2253 tile_height = 1;
2254 break;
2255 case I915_FORMAT_MOD_X_TILED:
2256 tile_height = IS_GEN2(dev) ? 16 : 8;
2257 break;
2258 case I915_FORMAT_MOD_Y_TILED:
2259 tile_height = 32;
2260 break;
2261 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2262 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2263 switch (pixel_bytes) {
b5d0e9bf 2264 default:
6761dd31 2265 case 1:
b5d0e9bf
DL		 2266 tile_height = 64;
2267 break;
6761dd31
TU		 2268 case 2:
2269 case 4:
b5d0e9bf
DL		 2270 tile_height = 32;
2271 break;
6761dd31 2272 case 8:
b5d0e9bf
DL		 2273 tile_height = 16;
2274 break;
6761dd31 2275 case 16:
b5d0e9bf
DL		 2276 WARN_ONCE(1,
2277 "128-bit pixels are not supported for display!");
2278 tile_height = 16;
2279 break;
2280 }
2281 break;
2282 default:
2283 MISSING_CASE(fb_format_modifier);
2284 tile_height = 1;
2285 break;
2286 }
091df6cb 2287
6761dd31
TU		 2288 return tile_height;
2289}
2290
2291unsigned int
2292intel_fb_align_height(struct drm_device *dev, unsigned int height,
2293 uint32_t pixel_format, uint64_t fb_format_modifier)
2294{
2295 return ALIGN(height, intel_tile_height(dev, pixel_format,
2296 fb_format_modifier));
a57ce0b2
JB		 2297}
2298
f64b98cd
TU		 2299static int
2300intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2301 const struct drm_plane_state *plane_state)
2302{
50470bb0 2303 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2304
f64b98cd
TU		 2305 *view = i915_ggtt_view_normal;
2306
50470bb0
TU		 2307 if (!plane_state)
2308 return 0;
2309
121920fa 2310 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2311 return 0;
2312
9abc4648 2313 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2314
2315 info->height = fb->height;
2316 info->pixel_format = fb->pixel_format;
2317 info->pitch = fb->pitches[0];
2318 info->fb_modifier = fb->modifier[0];
2319
f64b98cd
TU		 2320 return 0;
2321}
2322
127bd2ac 2323int
850c4cdc
TU		 2324intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2325 struct drm_framebuffer *fb,
82bc3b2d 2326 const struct drm_plane_state *plane_state,
a4872ba6 2327 struct intel_engine_cs *pipelined)
6b95a207 2328{
850c4cdc 2329 struct drm_device *dev = fb->dev;
ce453d81 2330 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2331 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2332 struct i915_ggtt_view view;
6b95a207
KH		 2333 u32 alignment;
2334 int ret;
2335
ebcdd39e
MR		 2336 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2337
7b911adc
TU		 2338 switch (fb->modifier[0]) {
2339 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2340 if (INTEL_INFO(dev)->gen >= 9)
2341 alignment = 256 * 1024;
2342 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2343 alignment = 128 * 1024;
a6c45cf0 2344 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2345 alignment = 4 * 1024;
2346 else
2347 alignment = 64 * 1024;
6b95a207 2348 break;
7b911adc 2349 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else {
2353 /* pin() will align the object as required by fence */
2354 alignment = 0;
2355 }
6b95a207 2356 break;
7b911adc 2357 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2358 case I915_FORMAT_MOD_Yf_TILED:
2359 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2361 return -EINVAL;
2362 alignment = 1 * 1024 * 1024;
2363 break;
6b95a207 2364 default:
7b911adc
TU		 2365 MISSING_CASE(fb->modifier[0]);
2366 return -EINVAL;
6b95a207
KH		 2367 }
2368
f64b98cd
TU		 2369 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370 if (ret)
2371 return ret;
2372
693db184
CW		 2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2376 * the VT-d warning.
2377 */
2378 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379 alignment = 256 * 1024;
2380
d6dd6843
PZ		 2381 /*
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2387 */
2388 intel_runtime_pm_get(dev_priv);
2389
ce453d81 2390 dev_priv->mm.interruptible = false;
e6617330 2391 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2392 &view);
48b956c5 2393 if (ret)
ce453d81 2394 goto err_interruptible;
6b95a207
KH		 2395
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2400 */
06d98131 2401 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2402 if (ret)
2403 goto err_unpin;
1690e1eb 2404
9a5a53b3 2405 i915_gem_object_pin_fence(obj);
6b95a207 2406
ce453d81 2407 dev_priv->mm.interruptible = true;
d6dd6843 2408 intel_runtime_pm_put(dev_priv);
6b95a207 2409 return 0;
48b956c5
CW		 2410
2411err_unpin:
f64b98cd 2412 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2413err_interruptible:
2414 dev_priv->mm.interruptible = true;
d6dd6843 2415 intel_runtime_pm_put(dev_priv);
48b956c5 2416 return ret;
6b95a207
KH		 2417}
2418
82bc3b2d
TU		 2419static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2420 const struct drm_plane_state *plane_state)
1690e1eb 2421{
82bc3b2d 2422 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2423 struct i915_ggtt_view view;
2424 int ret;
82bc3b2d 2425
ebcdd39e
MR		 2426 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2427
f64b98cd
TU		 2428 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2429 WARN_ONCE(ret, "Couldn't get view from plane state!");
2430
1690e1eb 2431 i915_gem_object_unpin_fence(obj);
f64b98cd 2432 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2433}
2434
c2c75131
DV		 2435/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2436 * is assumed to be a power-of-two. */
bc752862
CW		 2437unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2438 unsigned int tiling_mode,
2439 unsigned int cpp,
2440 unsigned int pitch)
c2c75131 2441{
bc752862
CW		 2442 if (tiling_mode != I915_TILING_NONE) {
2443 unsigned int tile_rows, tiles;
c2c75131 2444
bc752862
CW		 2445 tile_rows = *y / 8;
2446 *y %= 8;
c2c75131 2447
bc752862
CW		 2448 tiles = *x / (512/cpp);
2449 *x %= 512/cpp;
2450
2451 return tile_rows * pitch * 8 + tiles * 4096;
2452 } else {
2453 unsigned int offset;
2454
2455 offset = *y * pitch + *x * cpp;
2456 *y = 0;
2457 *x = (offset & 4095) / cpp;
2458 return offset & -4096;
2459 }
c2c75131
DV		 2460}
2461
b35d63fa 2462static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2463{
2464 switch (format) {
2465 case DISPPLANE_8BPP:
2466 return DRM_FORMAT_C8;
2467 case DISPPLANE_BGRX555:
2468 return DRM_FORMAT_XRGB1555;
2469 case DISPPLANE_BGRX565:
2470 return DRM_FORMAT_RGB565;
2471 default:
2472 case DISPPLANE_BGRX888:
2473 return DRM_FORMAT_XRGB8888;
2474 case DISPPLANE_RGBX888:
2475 return DRM_FORMAT_XBGR8888;
2476 case DISPPLANE_BGRX101010:
2477 return DRM_FORMAT_XRGB2101010;
2478 case DISPPLANE_RGBX101010:
2479 return DRM_FORMAT_XBGR2101010;
2480 }
2481}
2482
bc8d7dff
DL		 2483static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484{
2485 switch (format) {
2486 case PLANE_CTL_FORMAT_RGB_565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case PLANE_CTL_FORMAT_XRGB_8888:
2490 if (rgb_order) {
2491 if (alpha)
2492 return DRM_FORMAT_ABGR8888;
2493 else
2494 return DRM_FORMAT_XBGR8888;
2495 } else {
2496 if (alpha)
2497 return DRM_FORMAT_ARGB8888;
2498 else
2499 return DRM_FORMAT_XRGB8888;
2500 }
2501 case PLANE_CTL_FORMAT_XRGB_2101010:
2502 if (rgb_order)
2503 return DRM_FORMAT_XBGR2101010;
2504 else
2505 return DRM_FORMAT_XRGB2101010;
2506 }
2507}
2508
5724dbd1 2509static bool
f6936e29
DV		 2510intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2512{
2513 struct drm_device *dev = crtc->base.dev;
2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2516 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
46f297fb 2522
ff2652ea
CW		 2523 if (plane_config->size == 0)
2524 return false;
2525
f37b5c2b
DV		 2526 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2527 base_aligned,
2528 base_aligned,
2529 size_aligned);
46f297fb 2530 if (!obj)
484b41dd 2531 return false;
46f297fb 2532
49af449b
DL		 2533 obj->tiling_mode = plane_config->tiling;
2534 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2535 obj->stride = fb->pitches[0];
46f297fb 2536
6bf129df
DL		 2537 mode_cmd.pixel_format = fb->pixel_format;
2538 mode_cmd.width = fb->width;
2539 mode_cmd.height = fb->height;
2540 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2541 mode_cmd.modifier[0] = fb->modifier[0];
2542 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2543
2544 mutex_lock(&dev->struct_mutex);
6bf129df 2545 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2546 &mode_cmd, obj)) {
46f297fb
JB		 2547 DRM_DEBUG_KMS("intel fb init failed\n");
2548 goto out_unref_obj;
2549 }
46f297fb 2550 mutex_unlock(&dev->struct_mutex);
484b41dd 2551
f6936e29 2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2553 return true;
46f297fb
JB		 2554
2555out_unref_obj:
2556 drm_gem_object_unreference(&obj->base);
2557 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2558 return false;
2559}
2560
afd65eb4
MR		 2561/* Update plane->state->fb to match plane->fb after driver-internal updates */
2562static void
2563update_state_fb(struct drm_plane *plane)
2564{
2565 if (plane->fb == plane->state->fb)
2566 return;
2567
2568 if (plane->state->fb)
2569 drm_framebuffer_unreference(plane->state->fb);
2570 plane->state->fb = plane->fb;
2571 if (plane->state->fb)
2572 drm_framebuffer_reference(plane->state->fb);
2573}
2574
5724dbd1 2575static void
f6936e29
DV		 2576intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2578{
2579 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2580 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2581 struct drm_crtc *c;
2582 struct intel_crtc *i;
2ff8fde1 2583 struct drm_i915_gem_object *obj;
88595ac9
DV		 2584 struct drm_plane *primary = intel_crtc->base.primary;
2585 struct drm_framebuffer *fb;
484b41dd 2586
2d14030b 2587 if (!plane_config->fb)
484b41dd
JB		 2588 return;
2589
f6936e29 2590 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2591 fb = &plane_config->fb->base;
2592 goto valid_fb;
f55548b5 2593 }
484b41dd 2594
2d14030b 2595 kfree(plane_config->fb);
484b41dd
JB		 2596
2597 /*
2598 * Failed to alloc the obj, check to see if we should share
2599 * an fb with another CRTC instead
2600 */
70e1e0ec 2601 for_each_crtc(dev, c) {
484b41dd
JB		 2602 i = to_intel_crtc(c);
2603
2604 if (c == &intel_crtc->base)
2605 continue;
2606
2ff8fde1
MR		 2607 if (!i->active)
2608 continue;
2609
88595ac9
DV		 2610 fb = c->primary->fb;
2611 if (!fb)
484b41dd
JB		 2612 continue;
2613
88595ac9 2614 obj = intel_fb_obj(fb);
2ff8fde1 2615 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2616 drm_framebuffer_reference(fb);
2617 goto valid_fb;
484b41dd
JB		 2618 }
2619 }
88595ac9
DV		 2620
2621 return;
2622
2623valid_fb:
2624 obj = intel_fb_obj(fb);
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dev_priv->preserve_bios_swizzle = true;
2627
2628 primary->fb = fb;
2629 primary->state->crtc = &intel_crtc->base;
2630 primary->crtc = &intel_crtc->base;
2631 update_state_fb(primary);
2632 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2633}
2634
29b9bde6
DV		 2635static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2636 struct drm_framebuffer *fb,
2637 int x, int y)
81255565
JB		 2638{
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2642 struct drm_plane *primary = crtc->primary;
2643 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2644 struct drm_i915_gem_object *obj;
81255565 2645 int plane = intel_crtc->plane;
e506a0c6 2646 unsigned long linear_offset;
81255565 2647 u32 dspcntr;
f45651ba 2648 u32 reg = DSPCNTR(plane);
48404c1e 2649 int pixel_size;
f45651ba 2650
b70709a6 2651 if (!visible || !fb) {
fdd508a6
VS		 2652 I915_WRITE(reg, 0);
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2655 else
2656 I915_WRITE(DSPADDR(plane), 0);
2657 POSTING_READ(reg);
2658 return;
2659 }
2660
c9ba6fad
VS		 2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2663 return;
2664
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
f45651ba
VS		 2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
fdd508a6 2669 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2670
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2677 */
2678 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2681 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2688 }
81255565 2689
57779d06
VS		 2690 switch (fb->pixel_format) {
2691 case DRM_FORMAT_C8:
81255565
JB		 2692 dspcntr |= DISPPLANE_8BPP;
2693 break;
57779d06 2694 case DRM_FORMAT_XRGB1555:
57779d06 2695 dspcntr |= DISPPLANE_BGRX555;
81255565 2696 break;
57779d06
VS		 2697 case DRM_FORMAT_RGB565:
2698 dspcntr |= DISPPLANE_BGRX565;
2699 break;
2700 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2701 dspcntr |= DISPPLANE_BGRX888;
2702 break;
2703 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2704 dspcntr |= DISPPLANE_RGBX888;
2705 break;
2706 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2707 dspcntr |= DISPPLANE_BGRX101010;
2708 break;
2709 case DRM_FORMAT_XBGR2101010:
57779d06 2710 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2711 break;
2712 default:
baba133a 2713 BUG();
81255565 2714 }
57779d06 2715
f45651ba
VS		 2716 if (INTEL_INFO(dev)->gen >= 4 &&
2717 obj->tiling_mode != I915_TILING_NONE)
2718 dspcntr |= DISPPLANE_TILED;
81255565 2719
de1aa629
VS		 2720 if (IS_G4X(dev))
2721 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2722
b9897127 2723 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2724
c2c75131
DV		 2725 if (INTEL_INFO(dev)->gen >= 4) {
2726 intel_crtc->dspaddr_offset =
bc752862 2727 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2728 pixel_size,
bc752862 2729 fb->pitches[0]);
c2c75131
DV		 2730 linear_offset -= intel_crtc->dspaddr_offset;
2731 } else {
e506a0c6 2732 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2733 }
e506a0c6 2734
8e7d688b 2735 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2736 dspcntr |= DISPPLANE_ROTATE_180;
2737
6e3c9717
ACO		 2738 x += (intel_crtc->config->pipe_src_w - 1);
2739 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2740
2741 /* Finding the last pixel of the last line of the display
2742 data and adding to linear_offset*/
2743 linear_offset +=
6e3c9717
ACO		 2744 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2745 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2746 }
2747
2748 I915_WRITE(reg, dspcntr);
2749
01f2c773 2750 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2751 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2752 I915_WRITE(DSPSURF(plane),
2753 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2755 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2756 } else
f343c5f6 2757 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2758 POSTING_READ(reg);
17638cd6
JB		 2759}
2760
29b9bde6
DV		 2761static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 struct drm_framebuffer *fb,
2763 int x, int y)
17638cd6
JB		 2764{
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2768 struct drm_plane *primary = crtc->primary;
2769 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2770 struct drm_i915_gem_object *obj;
17638cd6 2771 int plane = intel_crtc->plane;
e506a0c6 2772 unsigned long linear_offset;
17638cd6 2773 u32 dspcntr;
f45651ba 2774 u32 reg = DSPCNTR(plane);
48404c1e 2775 int pixel_size;
f45651ba 2776
b70709a6 2777 if (!visible || !fb) {
fdd508a6
VS		 2778 I915_WRITE(reg, 0);
2779 I915_WRITE(DSPSURF(plane), 0);
2780 POSTING_READ(reg);
2781 return;
2782 }
2783
c9ba6fad
VS		 2784 obj = intel_fb_obj(fb);
2785 if (WARN_ON(obj == NULL))
2786 return;
2787
2788 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
f45651ba
VS		 2790 dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
fdd508a6 2792 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2793
2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2796
57779d06
VS		 2797 switch (fb->pixel_format) {
2798 case DRM_FORMAT_C8:
17638cd6
JB		 2799 dspcntr |= DISPPLANE_8BPP;
2800 break;
57779d06
VS		 2801 case DRM_FORMAT_RGB565:
2802 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2803 break;
57779d06 2804 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2805 dspcntr |= DISPPLANE_BGRX888;
2806 break;
2807 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2808 dspcntr |= DISPPLANE_RGBX888;
2809 break;
2810 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2811 dspcntr |= DISPPLANE_BGRX101010;
2812 break;
2813 case DRM_FORMAT_XBGR2101010:
57779d06 2814 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2815 break;
2816 default:
baba133a 2817 BUG();
17638cd6
JB		 2818 }
2819
2820 if (obj->tiling_mode != I915_TILING_NONE)
2821 dspcntr |= DISPPLANE_TILED;
17638cd6 2822
f45651ba 2823 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2825
b9897127 2826 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2827 intel_crtc->dspaddr_offset =
bc752862 2828 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2829 pixel_size,
bc752862 2830 fb->pitches[0]);
c2c75131 2831 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2832 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2833 dspcntr |= DISPPLANE_ROTATE_180;
2834
2835 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2836 x += (intel_crtc->config->pipe_src_w - 1);
2837 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2838
2839 /* Finding the last pixel of the last line of the display
2840 data and adding to linear_offset*/
2841 linear_offset +=
6e3c9717
ACO		 2842 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2843 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2844 }
2845 }
2846
2847 I915_WRITE(reg, dspcntr);
17638cd6 2848
01f2c773 2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
17638cd6 2858 POSTING_READ(reg);
17638cd6
JB		 2859}
2860
b321803d
DL		 2861u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2862 uint32_t pixel_format)
2863{
2864 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2865
2866 /*
2867 * The stride is either expressed as a multiple of 64 bytes
2868 * chunks for linear buffers or in number of tiles for tiled
2869 * buffers.
2870 */
2871 switch (fb_modifier) {
2872 case DRM_FORMAT_MOD_NONE:
2873 return 64;
2874 case I915_FORMAT_MOD_X_TILED:
2875 if (INTEL_INFO(dev)->gen == 2)
2876 return 128;
2877 return 512;
2878 case I915_FORMAT_MOD_Y_TILED:
2879 /* No need to check for old gens and Y tiling since this is
2880 * about the display engine and those will be blocked before
2881 * we get here.
2882 */
2883 return 128;
2884 case I915_FORMAT_MOD_Yf_TILED:
2885 if (bits_per_pixel == 8)
2886 return 64;
2887 else
2888 return 128;
2889 default:
2890 MISSING_CASE(fb_modifier);
2891 return 64;
2892 }
2893}
2894
121920fa
TU		 2895unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2896 struct drm_i915_gem_object *obj)
2897{
9abc4648 2898 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2899
2900 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2901 view = &i915_ggtt_view_rotated;
121920fa
TU		 2902
2903 return i915_gem_obj_ggtt_offset_view(obj, view);
2904}
2905
a1b2278e
CK		 2906/*
2907 * This function detaches (aka. unbinds) unused scalers in hardware
2908 */
2909void skl_detach_scalers(struct intel_crtc *intel_crtc)
2910{
2911 struct drm_device *dev;
2912 struct drm_i915_private *dev_priv;
2913 struct intel_crtc_scaler_state *scaler_state;
2914 int i;
2915
2916 if (!intel_crtc || !intel_crtc->config)
2917 return;
2918
2919 dev = intel_crtc->base.dev;
2920 dev_priv = dev->dev_private;
2921 scaler_state = &intel_crtc->config->scaler_state;
2922
2923 /* loop through and disable scalers that aren't in use */
2924 for (i = 0; i < intel_crtc->num_scalers; i++) {
2925 if (!scaler_state->scalers[i].in_use) {
2926 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2927 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2928 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2929 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2930 intel_crtc->base.base.id, intel_crtc->pipe, i);
2931 }
2932 }
2933}
2934
6156a456 2935u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2936{
6156a456 2937 switch (pixel_format) {
d161cf7a 2938 case DRM_FORMAT_C8:
c34ce3d1 2939 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2940 case DRM_FORMAT_RGB565:
c34ce3d1 2941 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2942 case DRM_FORMAT_XBGR8888:
c34ce3d1 2943 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2944 case DRM_FORMAT_XRGB8888:
c34ce3d1 2945 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2946 /*
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2950 */
f75fb42a 2951 case DRM_FORMAT_ABGR8888:
c34ce3d1 2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2954 case DRM_FORMAT_ARGB8888:
c34ce3d1 2955 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2957 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2959 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2960 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2961 case DRM_FORMAT_YUYV:
c34ce3d1 2962 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2963 case DRM_FORMAT_YVYU:
c34ce3d1 2964 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2965 case DRM_FORMAT_UYVY:
c34ce3d1 2966 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2967 case DRM_FORMAT_VYUY:
c34ce3d1 2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2969 default:
4249eeef 2970 MISSING_CASE(pixel_format);
70d21f0e 2971 }
8cfcba41 2972
c34ce3d1 2973 return 0;
6156a456 2974}
70d21f0e 2975
6156a456
CK		 2976u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2977{
6156a456 2978 switch (fb_modifier) {
30af77c4 2979 case DRM_FORMAT_MOD_NONE:
70d21f0e 2980 break;
30af77c4 2981 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2982 return PLANE_CTL_TILED_X;
b321803d 2983 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2984 return PLANE_CTL_TILED_Y;
b321803d 2985 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2986 return PLANE_CTL_TILED_YF;
70d21f0e 2987 default:
6156a456 2988 MISSING_CASE(fb_modifier);
70d21f0e 2989 }
8cfcba41 2990
c34ce3d1 2991 return 0;
6156a456 2992}
70d21f0e 2993
6156a456
CK		 2994u32 skl_plane_ctl_rotation(unsigned int rotation)
2995{
3b7a5119 2996 switch (rotation) {
6156a456
CK		 2997 case BIT(DRM_ROTATE_0):
2998 break;
1e8df167
SJ		 2999 /*
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3002 */
3b7a5119 3003 case BIT(DRM_ROTATE_90):
1e8df167 3004 return PLANE_CTL_ROTATE_270;
3b7a5119 3005 case BIT(DRM_ROTATE_180):
c34ce3d1 3006 return PLANE_CTL_ROTATE_180;
3b7a5119 3007 case BIT(DRM_ROTATE_270):
1e8df167 3008 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3009 default:
3010 MISSING_CASE(rotation);
3011 }
3012
c34ce3d1 3013 return 0;
6156a456
CK		 3014}
3015
3016static void skylake_update_primary_plane(struct drm_crtc *crtc,
3017 struct drm_framebuffer *fb,
3018 int x, int y)
3019{
3020 struct drm_device *dev = crtc->dev;
3021 struct drm_i915_private *dev_priv = dev->dev_private;
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3023 struct drm_plane *plane = crtc->primary;
3024 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3025 struct drm_i915_gem_object *obj;
3026 int pipe = intel_crtc->pipe;
3027 u32 plane_ctl, stride_div, stride;
3028 u32 tile_height, plane_offset, plane_size;
3029 unsigned int rotation;
3030 int x_offset, y_offset;
3031 unsigned long surf_addr;
6156a456
CK		 3032 struct intel_crtc_state *crtc_state = intel_crtc->config;
3033 struct intel_plane_state *plane_state;
3034 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3035 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3036 int scaler_id = -1;
3037
6156a456
CK		 3038 plane_state = to_intel_plane_state(plane->state);
3039
b70709a6 3040 if (!visible || !fb) {
6156a456
CK		 3041 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3042 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3043 POSTING_READ(PLANE_CTL(pipe, 0));
3044 return;
3b7a5119 3045 }
70d21f0e 3046
6156a456
CK		 3047 plane_ctl = PLANE_CTL_ENABLE |
3048 PLANE_CTL_PIPE_GAMMA_ENABLE |
3049 PLANE_CTL_PIPE_CSC_ENABLE;
3050
3051 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3052 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3053 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3054
3055 rotation = plane->state->rotation;
3056 plane_ctl |= skl_plane_ctl_rotation(rotation);
3057
b321803d
DL		 3058 obj = intel_fb_obj(fb);
3059 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3060 fb->pixel_format);
3b7a5119
SJ		 3061 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3062
6156a456
CK		 3063 /*
3064 * FIXME: intel_plane_state->src, dst aren't set when transitional
3065 * update_plane helpers are called from legacy paths.
3066 * Once full atomic crtc is available, below check can be avoided.
3067 */
3068 if (drm_rect_width(&plane_state->src)) {
3069 scaler_id = plane_state->scaler_id;
3070 src_x = plane_state->src.x1 >> 16;
3071 src_y = plane_state->src.y1 >> 16;
3072 src_w = drm_rect_width(&plane_state->src) >> 16;
3073 src_h = drm_rect_height(&plane_state->src) >> 16;
3074 dst_x = plane_state->dst.x1;
3075 dst_y = plane_state->dst.y1;
3076 dst_w = drm_rect_width(&plane_state->dst);
3077 dst_h = drm_rect_height(&plane_state->dst);
3078
3079 WARN_ON(x != src_x || y != src_y);
3080 } else {
3081 src_w = intel_crtc->config->pipe_src_w;
3082 src_h = intel_crtc->config->pipe_src_h;
3083 }
3084
3b7a5119
SJ		 3085 if (intel_rotation_90_or_270(rotation)) {
3086 /* stride = Surface height in tiles */
2614f17d 3087 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3088 fb->modifier[0]);
3089 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3090 x_offset = stride * tile_height - y - src_h;
3b7a5119 3091 y_offset = x;
6156a456 3092 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3093 } else {
3094 stride = fb->pitches[0] / stride_div;
3095 x_offset = x;
3096 y_offset = y;
6156a456 3097 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3098 }
3099 plane_offset = y_offset << 16 | x_offset;
b321803d 3100
70d21f0e 3101 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3102 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3103 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3104 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3105
3106 if (scaler_id >= 0) {
3107 uint32_t ps_ctrl = 0;
3108
3109 WARN_ON(!dst_w || !dst_h);
3110 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3111 crtc_state->scaler_state.scalers[scaler_id].mode;
3112 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3113 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3114 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3115 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3116 I915_WRITE(PLANE_POS(pipe, 0), 0);
3117 } else {
3118 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3119 }
3120
121920fa 3121 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3122
3123 POSTING_READ(PLANE_SURF(pipe, 0));
3124}
3125
17638cd6
JB		 3126/* Assume fb object is pinned & idle & fenced and just update base pointers */
3127static int
3128intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3129 int x, int y, enum mode_set_atomic state)
3130{
3131 struct drm_device *dev = crtc->dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3133
6b8e6ed0
CW		 3134 if (dev_priv->display.disable_fbc)
3135 dev_priv->display.disable_fbc(dev);
81255565 3136
29b9bde6
DV		 3137 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3138
3139 return 0;
81255565
JB		 3140}
3141
7514747d 3142static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3143{
96a02917
VS		 3144 struct drm_crtc *crtc;
3145
70e1e0ec 3146 for_each_crtc(dev, crtc) {
96a02917
VS		 3147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3148 enum plane plane = intel_crtc->plane;
3149
3150 intel_prepare_page_flip(dev, plane);
3151 intel_finish_page_flip_plane(dev, plane);
3152 }
7514747d
VS		 3153}
3154
3155static void intel_update_primary_planes(struct drm_device *dev)
3156{
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct drm_crtc *crtc;
96a02917 3159
70e1e0ec 3160 for_each_crtc(dev, crtc) {
96a02917
VS		 3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162
51fd371b 3163 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3164 /*
3165 * FIXME: Once we have proper support for primary planes (and
3166 * disabling them without disabling the entire crtc) allow again
66e514c1 3167 * a NULL crtc->primary->fb.
947fdaad 3168 */
f4510a27 3169 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3170 dev_priv->display.update_primary_plane(crtc,
66e514c1 3171 crtc->primary->fb,
262ca2b0
MR		 3172 crtc->x,
3173 crtc->y);
51fd371b 3174 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3175 }
3176}
3177
ce22dba9
ML		 3178void intel_crtc_reset(struct intel_crtc *crtc)
3179{
3180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3181
3182 if (!crtc->active)
3183 return;
3184
3185 intel_crtc_disable_planes(&crtc->base);
3186 dev_priv->display.crtc_disable(&crtc->base);
3187 dev_priv->display.crtc_enable(&crtc->base);
3188 intel_crtc_enable_planes(&crtc->base);
3189}
3190
7514747d
VS		 3191void intel_prepare_reset(struct drm_device *dev)
3192{
f98ce92f
VS		 3193 struct drm_i915_private *dev_priv = to_i915(dev);
3194 struct intel_crtc *crtc;
3195
7514747d
VS		 3196 /* no reset support for gen2 */
3197 if (IS_GEN2(dev))
3198 return;
3199
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202 return;
3203
3204 drm_modeset_lock_all(dev);
f98ce92f
VS		 3205
3206 /*
3207 * Disabling the crtcs gracefully seems nicer. Also the
3208 * g33 docs say we should at least disable all the planes.
3209 */
3210 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3211 if (!crtc->active)
3212 continue;
3213
3214 intel_crtc_disable_planes(&crtc->base);
3215 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3216 }
7514747d
VS		 3217}
3218
3219void intel_finish_reset(struct drm_device *dev)
3220{
3221 struct drm_i915_private *dev_priv = to_i915(dev);
3222
3223 /*
3224 * Flips in the rings will be nuked by the reset,
3225 * so complete all pending flips so that user space
3226 * will get its events and not get stuck.
3227 */
3228 intel_complete_page_flips(dev);
3229
3230 /* no reset support for gen2 */
3231 if (IS_GEN2(dev))
3232 return;
3233
3234 /* reset doesn't touch the display */
3235 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3236 /*
3237 * Flips in the rings have been nuked by the reset,
3238 * so update the base address of all primary
3239 * planes to the the last fb to make sure we're
3240 * showing the correct fb after a reset.
3241 */
3242 intel_update_primary_planes(dev);
3243 return;
3244 }
3245
3246 /*
3247 * The display has been reset as well,
3248 * so need a full re-initialization.
3249 */
3250 intel_runtime_pm_disable_interrupts(dev_priv);
3251 intel_runtime_pm_enable_interrupts(dev_priv);
3252
3253 intel_modeset_init_hw(dev);
3254
3255 spin_lock_irq(&dev_priv->irq_lock);
3256 if (dev_priv->display.hpd_irq_setup)
3257 dev_priv->display.hpd_irq_setup(dev);
3258 spin_unlock_irq(&dev_priv->irq_lock);
3259
3260 intel_modeset_setup_hw_state(dev, true);
3261
3262 intel_hpd_init(dev_priv);
3263
3264 drm_modeset_unlock_all(dev);
3265}
3266
2e2f351d 3267static void
14667a4b
CW		 3268intel_finish_fb(struct drm_framebuffer *old_fb)
3269{
2ff8fde1 3270 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3271 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3272 bool was_interruptible = dev_priv->mm.interruptible;
3273 int ret;
3274
14667a4b
CW		 3275 /* Big Hammer, we also need to ensure that any pending
3276 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3277 * current scanout is retired before unpinning the old
2e2f351d
CW		 3278 * framebuffer. Note that we rely on userspace rendering
3279 * into the buffer attached to the pipe they are waiting
3280 * on. If not, userspace generates a GPU hang with IPEHR
3281 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3282 *
3283 * This should only fail upon a hung GPU, in which case we
3284 * can safely continue.
3285 */
3286 dev_priv->mm.interruptible = false;
2e2f351d 3287 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3288 dev_priv->mm.interruptible = was_interruptible;
3289
2e2f351d 3290 WARN_ON(ret);
14667a4b
CW		 3291}
3292
7d5e3799
CW		 3293static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3294{
3295 struct drm_device *dev = crtc->dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3298 bool pending;
3299
3300 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3301 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3302 return false;
3303
5e2d7afc 3304 spin_lock_irq(&dev->event_lock);
7d5e3799 3305 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3306 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3307
3308 return pending;
3309}
3310
e30e8f75
GP		 3311static void intel_update_pipe_size(struct intel_crtc *crtc)
3312{
3313 struct drm_device *dev = crtc->base.dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 const struct drm_display_mode *adjusted_mode;
3316
3317 if (!i915.fastboot)
3318 return;
3319
3320 /*
3321 * Update pipe size and adjust fitter if needed: the reason for this is
3322 * that in compute_mode_changes we check the native mode (not the pfit
3323 * mode) to see if we can flip rather than do a full mode set. In the
3324 * fastboot case, we'll flip, but if we don't update the pipesrc and
3325 * pfit state, we'll end up with a big fb scanned out into the wrong
3326 * sized surface.
3327 *
3328 * To fix this properly, we need to hoist the checks up into
3329 * compute_mode_changes (or above), check the actual pfit state and
3330 * whether the platform allows pfit disable with pipe active, and only
3331 * then update the pipesrc and pfit state, even on the flip path.
3332 */
3333
6e3c9717 3334 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3335
3336 I915_WRITE(PIPESRC(crtc->pipe),
3337 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3338 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3339 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3340 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3341 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3342 I915_WRITE(PF_CTL(crtc->pipe), 0);
3343 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3344 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3345 }
6e3c9717
ACO		 3346 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3347 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3348}
3349
5e84e1a4
ZW		 3350static void intel_fdi_normal_train(struct drm_crtc *crtc)
3351{
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355 int pipe = intel_crtc->pipe;
3356 u32 reg, temp;
3357
3358 /* enable normal train */
3359 reg = FDI_TX_CTL(pipe);
3360 temp = I915_READ(reg);
61e499bf 3361 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3362 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3363 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3364 } else {
3365 temp &= ~FDI_LINK_TRAIN_NONE;
3366 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3367 }
5e84e1a4
ZW		 3368 I915_WRITE(reg, temp);
3369
3370 reg = FDI_RX_CTL(pipe);
3371 temp = I915_READ(reg);
3372 if (HAS_PCH_CPT(dev)) {
3373 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3374 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3375 } else {
3376 temp &= ~FDI_LINK_TRAIN_NONE;
3377 temp |= FDI_LINK_TRAIN_NONE;
3378 }
3379 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3380
3381 /* wait one idle pattern time */
3382 POSTING_READ(reg);
3383 udelay(1000);
357555c0
JB		 3384
3385 /* IVB wants error correction enabled */
3386 if (IS_IVYBRIDGE(dev))
3387 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3388 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3389}
3390
8db9d77b
ZW		 3391/* The FDI link training functions for ILK/Ibexpeak. */
3392static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3393{
3394 struct drm_device *dev = crtc->dev;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3397 int pipe = intel_crtc->pipe;
5eddb70b 3398 u32 reg, temp, tries;
8db9d77b 3399
1c8562f6 3400 /* FDI needs bits from pipe first */
0fc932b8 3401 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3402
e1a44743
AJ		 3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404 for train result */
5eddb70b
CW		 3405 reg = FDI_RX_IMR(pipe);
3406 temp = I915_READ(reg);
e1a44743
AJ		 3407 temp &= ~FDI_RX_SYMBOL_LOCK;
3408 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3409 I915_WRITE(reg, temp);
3410 I915_READ(reg);
e1a44743
AJ		 3411 udelay(150);
3412
8db9d77b 3413 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3414 reg = FDI_TX_CTL(pipe);
3415 temp = I915_READ(reg);
627eb5a3 3416 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3417 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3420 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3421
5eddb70b
CW		 3422 reg = FDI_RX_CTL(pipe);
3423 temp = I915_READ(reg);
8db9d77b
ZW		 3424 temp &= ~FDI_LINK_TRAIN_NONE;
3425 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3426 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428 POSTING_READ(reg);
8db9d77b
ZW		 3429 udelay(150);
3430
5b2adf89 3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3435
5eddb70b 3436 reg = FDI_RX_IIR(pipe);
e1a44743 3437 for (tries = 0; tries < 5; tries++) {
5eddb70b 3438 temp = I915_READ(reg);
8db9d77b
ZW		 3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441 if ((temp & FDI_RX_BIT_LOCK)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3443 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3444 break;
3445 }
8db9d77b 3446 }
e1a44743 3447 if (tries == 5)
5eddb70b 3448 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3449
3450 /* Train 2 */
5eddb70b
CW		 3451 reg = FDI_TX_CTL(pipe);
3452 temp = I915_READ(reg);
8db9d77b
ZW		 3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3455 I915_WRITE(reg, temp);
8db9d77b 3456
5eddb70b
CW		 3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
8db9d77b
ZW		 3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3461 I915_WRITE(reg, temp);
8db9d77b 3462
5eddb70b
CW		 3463 POSTING_READ(reg);
3464 udelay(150);
8db9d77b 3465
5eddb70b 3466 reg = FDI_RX_IIR(pipe);
e1a44743 3467 for (tries = 0; tries < 5; tries++) {
5eddb70b 3468 temp = I915_READ(reg);
8db9d77b
ZW		 3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3472 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3474 break;
3475 }
8db9d77b 3476 }
e1a44743 3477 if (tries == 5)
5eddb70b 3478 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3479
3480 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3481
8db9d77b
ZW		 3482}
3483
0206e353 3484static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489};
3490
3491/* The FDI link training functions for SNB/Cougarpoint. */
3492static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493{
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
fa37d39e 3498 u32 reg, temp, i, retry;
8db9d77b 3499
e1a44743
AJ		 3500 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3501 for train result */
5eddb70b
CW		 3502 reg = FDI_RX_IMR(pipe);
3503 temp = I915_READ(reg);
e1a44743
AJ		 3504 temp &= ~FDI_RX_SYMBOL_LOCK;
3505 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3506 I915_WRITE(reg, temp);
3507
3508 POSTING_READ(reg);
e1a44743
AJ		 3509 udelay(150);
3510
8db9d77b 3511 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3512 reg = FDI_TX_CTL(pipe);
3513 temp = I915_READ(reg);
627eb5a3 3514 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3515 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3516 temp &= ~FDI_LINK_TRAIN_NONE;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1;
3518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3519 /* SNB-B */
3520 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3521 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3522
d74cf324
DV		 3523 I915_WRITE(FDI_RX_MISC(pipe),
3524 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3525
5eddb70b
CW		 3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
8db9d77b
ZW		 3528 if (HAS_PCH_CPT(dev)) {
3529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3530 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3531 } else {
3532 temp &= ~FDI_LINK_TRAIN_NONE;
3533 temp |= FDI_LINK_TRAIN_PATTERN_1;
3534 }
5eddb70b
CW		 3535 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536
3537 POSTING_READ(reg);
8db9d77b
ZW		 3538 udelay(150);
3539
0206e353 3540 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3541 reg = FDI_TX_CTL(pipe);
3542 temp = I915_READ(reg);
8db9d77b
ZW		 3543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3544 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3545 I915_WRITE(reg, temp);
3546
3547 POSTING_READ(reg);
8db9d77b
ZW		 3548 udelay(500);
3549
fa37d39e
SP		 3550 for (retry = 0; retry < 5; retry++) {
3551 reg = FDI_RX_IIR(pipe);
3552 temp = I915_READ(reg);
3553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3554 if (temp & FDI_RX_BIT_LOCK) {
3555 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3556 DRM_DEBUG_KMS("FDI train 1 done.\n");
3557 break;
3558 }
3559 udelay(50);
8db9d77b 3560 }
fa37d39e
SP		 3561 if (retry < 5)
3562 break;
8db9d77b
ZW		 3563 }
3564 if (i == 4)
5eddb70b 3565 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3566
3567 /* Train 2 */
5eddb70b
CW		 3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
8db9d77b
ZW		 3570 temp &= ~FDI_LINK_TRAIN_NONE;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2;
3572 if (IS_GEN6(dev)) {
3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 /* SNB-B */
3575 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3576 }
5eddb70b 3577 I915_WRITE(reg, temp);
8db9d77b 3578
5eddb70b
CW		 3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
8db9d77b
ZW		 3581 if (HAS_PCH_CPT(dev)) {
3582 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3584 } else {
3585 temp &= ~FDI_LINK_TRAIN_NONE;
3586 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587 }
5eddb70b
CW		 3588 I915_WRITE(reg, temp);
3589
3590 POSTING_READ(reg);
8db9d77b
ZW		 3591 udelay(150);
3592
0206e353 3593 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
8db9d77b
ZW		 3596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
8db9d77b
ZW		 3601 udelay(500);
3602
fa37d39e
SP		 3603 for (retry = 0; retry < 5; retry++) {
3604 reg = FDI_RX_IIR(pipe);
3605 temp = I915_READ(reg);
3606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3607 if (temp & FDI_RX_SYMBOL_LOCK) {
3608 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3609 DRM_DEBUG_KMS("FDI train 2 done.\n");
3610 break;
3611 }
3612 udelay(50);
8db9d77b 3613 }
fa37d39e
SP		 3614 if (retry < 5)
3615 break;
8db9d77b
ZW		 3616 }
3617 if (i == 4)
5eddb70b 3618 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3619
3620 DRM_DEBUG_KMS("FDI train done.\n");
3621}
3622
357555c0
JB		 3623/* Manual link training for Ivy Bridge A0 parts */
3624static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3625{
3626 struct drm_device *dev = crtc->dev;
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629 int pipe = intel_crtc->pipe;
139ccd3f 3630 u32 reg, temp, i, j;
357555c0
JB		 3631
3632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3633 for train result */
3634 reg = FDI_RX_IMR(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~FDI_RX_SYMBOL_LOCK;
3637 temp &= ~FDI_RX_BIT_LOCK;
3638 I915_WRITE(reg, temp);
3639
3640 POSTING_READ(reg);
3641 udelay(150);
3642
01a415fd
DV		 3643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3644 I915_READ(FDI_RX_IIR(pipe)));
3645
139ccd3f
JB		 3646 /* Try each vswing and preemphasis setting twice before moving on */
3647 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3648 /* disable first in case we need to retry */
3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3652 temp &= ~FDI_TX_ENABLE;
3653 I915_WRITE(reg, temp);
357555c0 3654
139ccd3f
JB		 3655 reg = FDI_RX_CTL(pipe);
3656 temp = I915_READ(reg);
3657 temp &= ~FDI_LINK_TRAIN_AUTO;
3658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659 temp &= ~FDI_RX_ENABLE;
3660 I915_WRITE(reg, temp);
357555c0 3661
139ccd3f 3662 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
139ccd3f 3665 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3667 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3669 temp |= snb_b_fdi_train_param[j/2];
3670 temp |= FDI_COMPOSITE_SYNC;
3671 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3672
139ccd3f
JB		 3673 I915_WRITE(FDI_RX_MISC(pipe),
3674 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3675
139ccd3f 3676 reg = FDI_RX_CTL(pipe);
357555c0 3677 temp = I915_READ(reg);
139ccd3f
JB		 3678 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3679 temp |= FDI_COMPOSITE_SYNC;
3680 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3681
139ccd3f
JB		 3682 POSTING_READ(reg);
3683 udelay(1); /* should be 0.5us */
357555c0 3684
139ccd3f
JB		 3685 for (i = 0; i < 4; i++) {
3686 reg = FDI_RX_IIR(pipe);
3687 temp = I915_READ(reg);
3688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3689
139ccd3f
JB		 3690 if (temp & FDI_RX_BIT_LOCK ||
3691 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3692 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3693 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3694 i);
3695 break;
3696 }
3697 udelay(1); /* should be 0.5us */
3698 }
3699 if (i == 4) {
3700 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3701 continue;
3702 }
357555c0 3703
139ccd3f 3704 /* Train 2 */
357555c0
JB		 3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
139ccd3f
JB		 3707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3709 I915_WRITE(reg, temp);
3710
3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3715 I915_WRITE(reg, temp);
3716
3717 POSTING_READ(reg);
139ccd3f 3718 udelay(2); /* should be 1.5us */
357555c0 3719
139ccd3f
JB		 3720 for (i = 0; i < 4; i++) {
3721 reg = FDI_RX_IIR(pipe);
3722 temp = I915_READ(reg);
3723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3724
139ccd3f
JB		 3725 if (temp & FDI_RX_SYMBOL_LOCK ||
3726 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3727 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3728 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3729 i);
3730 goto train_done;
3731 }
3732 udelay(2); /* should be 1.5us */
357555c0 3733 }
139ccd3f
JB		 3734 if (i == 4)
3735 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3736 }
357555c0 3737
139ccd3f 3738train_done:
357555c0
JB		 3739 DRM_DEBUG_KMS("FDI train done.\n");
3740}
3741
88cefb6c 3742static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3743{
88cefb6c 3744 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3745 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3746 int pipe = intel_crtc->pipe;
5eddb70b 3747 u32 reg, temp;
79e53945 3748
c64e311e 3749
c98e9dcf 3750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3751 reg = FDI_RX_CTL(pipe);
3752 temp = I915_READ(reg);
627eb5a3 3753 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3754 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3755 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3756 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3757
3758 POSTING_READ(reg);
c98e9dcf
JB		 3759 udelay(200);
3760
3761 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3762 temp = I915_READ(reg);
3763 I915_WRITE(reg, temp | FDI_PCDCLK);
3764
3765 POSTING_READ(reg);
c98e9dcf
JB		 3766 udelay(200);
3767
20749730
PZ		 3768 /* Enable CPU FDI TX PLL, always on for Ironlake */
3769 reg = FDI_TX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3772 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3773
20749730
PZ		 3774 POSTING_READ(reg);
3775 udelay(100);
6be4a607 3776 }
0e23b99d
JB		 3777}
3778
88cefb6c
DV		 3779static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3780{
3781 struct drm_device *dev = intel_crtc->base.dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 int pipe = intel_crtc->pipe;
3784 u32 reg, temp;
3785
3786 /* Switch from PCDclk to Rawclk */
3787 reg = FDI_RX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3790
3791 /* Disable CPU FDI TX PLL */
3792 reg = FDI_TX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3795
3796 POSTING_READ(reg);
3797 udelay(100);
3798
3799 reg = FDI_RX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3802
3803 /* Wait for the clocks to turn off. */
3804 POSTING_READ(reg);
3805 udelay(100);
3806}
3807
0fc932b8
JB		 3808static void ironlake_fdi_disable(struct drm_crtc *crtc)
3809{
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 int pipe = intel_crtc->pipe;
3814 u32 reg, temp;
3815
3816 /* disable CPU FDI tx and PCH FDI rx */
3817 reg = FDI_TX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3820 POSTING_READ(reg);
3821
3822 reg = FDI_RX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~(0x7 << 16);
dfd07d72 3825 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3826 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3827
3828 POSTING_READ(reg);
3829 udelay(100);
3830
3831 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3832 if (HAS_PCH_IBX(dev))
6f06ce18 3833 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3834
3835 /* still set train pattern 1 */
3836 reg = FDI_TX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~FDI_LINK_TRAIN_NONE;
3839 temp |= FDI_LINK_TRAIN_PATTERN_1;
3840 I915_WRITE(reg, temp);
3841
3842 reg = FDI_RX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 if (HAS_PCH_CPT(dev)) {
3845 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3846 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3847 } else {
3848 temp &= ~FDI_LINK_TRAIN_NONE;
3849 temp |= FDI_LINK_TRAIN_PATTERN_1;
3850 }
3851 /* BPC in FDI rx is consistent with that in PIPECONF */
3852 temp &= ~(0x07 << 16);
dfd07d72 3853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3854 I915_WRITE(reg, temp);
3855
3856 POSTING_READ(reg);
3857 udelay(100);
3858}
3859
5dce5b93
CW		 3860bool intel_has_pending_fb_unpin(struct drm_device *dev)
3861{
3862 struct intel_crtc *crtc;
3863
3864 /* Note that we don't need to be called with mode_config.lock here
3865 * as our list of CRTC objects is static for the lifetime of the
3866 * device and so cannot disappear as we iterate. Similarly, we can
3867 * happily treat the predicates as racy, atomic checks as userspace
3868 * cannot claim and pin a new fb without at least acquring the
3869 * struct_mutex and so serialising with us.
3870 */
d3fcc808 3871 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3872 if (atomic_read(&crtc->unpin_work_count) == 0)
3873 continue;
3874
3875 if (crtc->unpin_work)
3876 intel_wait_for_vblank(dev, crtc->pipe);
3877
3878 return true;
3879 }
3880
3881 return false;
3882}
3883
d6bbafa1
CW		 3884static void page_flip_completed(struct intel_crtc *intel_crtc)
3885{
3886 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3887 struct intel_unpin_work *work = intel_crtc->unpin_work;
3888
3889 /* ensure that the unpin work is consistent wrt ->pending. */
3890 smp_rmb();
3891 intel_crtc->unpin_work = NULL;
3892
3893 if (work->event)
3894 drm_send_vblank_event(intel_crtc->base.dev,
3895 intel_crtc->pipe,
3896 work->event);
3897
3898 drm_crtc_vblank_put(&intel_crtc->base);
3899
3900 wake_up_all(&dev_priv->pending_flip_queue);
3901 queue_work(dev_priv->wq, &work->work);
3902
3903 trace_i915_flip_complete(intel_crtc->plane,
3904 work->pending_flip_obj);
3905}
3906
46a55d30 3907void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3908{
0f91128d 3909 struct drm_device *dev = crtc->dev;
5bb61643 3910 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3911
2c10d571 3912 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3913 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3914 !intel_crtc_has_pending_flip(crtc),
3915 60*HZ) == 0)) {
3916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3917
5e2d7afc 3918 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3919 if (intel_crtc->unpin_work) {
3920 WARN_ONCE(1, "Removing stuck page flip\n");
3921 page_flip_completed(intel_crtc);
3922 }
5e2d7afc 3923 spin_unlock_irq(&dev->event_lock);
9c787942 3924 }
5bb61643 3925
975d568a
CW		 3926 if (crtc->primary->fb) {
3927 mutex_lock(&dev->struct_mutex);
3928 intel_finish_fb(crtc->primary->fb);
3929 mutex_unlock(&dev->struct_mutex);
3930 }
e6c3a2a6
CW		 3931}
3932
e615efe4
ED		 3933/* Program iCLKIP clock to the desired frequency */
3934static void lpt_program_iclkip(struct drm_crtc *crtc)
3935{
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3938 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3939 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3940 u32 temp;
3941
a580516d 3942 mutex_lock(&dev_priv->sb_lock);
09153000 3943
e615efe4
ED		 3944 /* It is necessary to ungate the pixclk gate prior to programming
3945 * the divisors, and gate it back when it is done.
3946 */
3947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3948
3949 /* Disable SSCCTL */
3950 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3951 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3952 SBI_SSCCTL_DISABLE,
3953 SBI_ICLK);
e615efe4
ED		 3954
3955 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3956 if (clock == 20000) {
e615efe4
ED		 3957 auxdiv = 1;
3958 divsel = 0x41;
3959 phaseinc = 0x20;
3960 } else {
3961 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3962 * but the adjusted_mode->crtc_clock in in KHz. To get the
3963 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3964 * convert the virtual clock precision to KHz here for higher
3965 * precision.
3966 */
3967 u32 iclk_virtual_root_freq = 172800 * 1000;
3968 u32 iclk_pi_range = 64;
3969 u32 desired_divisor, msb_divisor_value, pi_value;
3970
12d7ceed 3971 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3972 msb_divisor_value = desired_divisor / iclk_pi_range;
3973 pi_value = desired_divisor % iclk_pi_range;
3974
3975 auxdiv = 0;
3976 divsel = msb_divisor_value - 2;
3977 phaseinc = pi_value;
3978 }
3979
3980 /* This should not happen with any sane values */
3981 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3982 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3984 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3985
3986 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3987 clock,
e615efe4
ED		 3988 auxdiv,
3989 divsel,
3990 phasedir,
3991 phaseinc);
3992
3993 /* Program SSCDIVINTPHASE6 */
988d6ee8 3994 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3995 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3996 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3997 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3999 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4000 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4001 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4002
4003 /* Program SSCAUXDIV */
988d6ee8 4004 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4005 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4006 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4007 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4008
4009 /* Enable modulator and associated divider */
988d6ee8 4010 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4011 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4012 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4013
4014 /* Wait for initialization time */
4015 udelay(24);
4016
4017 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4018
a580516d 4019 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4020}
4021
275f01b2
DV		 4022static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023 enum pipe pch_transcoder)
4024{
4025 struct drm_device *dev = crtc->base.dev;
4026 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4027 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4028
4029 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030 I915_READ(HTOTAL(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032 I915_READ(HBLANK(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034 I915_READ(HSYNC(cpu_transcoder)));
4035
4036 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037 I915_READ(VTOTAL(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039 I915_READ(VBLANK(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041 I915_READ(VSYNC(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044}
4045
003632d9 4046static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4047{
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 uint32_t temp;
4050
4051 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4052 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4053 return;
4054
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
003632d9
ACO		 4058 temp &= ~FDI_BC_BIFURCATION_SELECT;
4059 if (enable)
4060 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4063 I915_WRITE(SOUTH_CHICKEN1, temp);
4064 POSTING_READ(SOUTH_CHICKEN1);
4065}
4066
4067static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068{
4069 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4070
4071 switch (intel_crtc->pipe) {
4072 case PIPE_A:
4073 break;
4074 case PIPE_B:
6e3c9717 4075 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4076 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4077 else
003632d9 4078 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4079
4080 break;
4081 case PIPE_C:
003632d9 4082 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4083
4084 break;
4085 default:
4086 BUG();
4087 }
4088}
4089
f67a559d
JB		 4090/*
4091 * Enable PCH resources required for PCH ports:
4092 * - PCH PLLs
4093 * - FDI training & RX/TX
4094 * - update transcoder timings
4095 * - DP transcoding bits
4096 * - transcoder
4097 */
4098static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4099{
4100 struct drm_device *dev = crtc->dev;
4101 struct drm_i915_private *dev_priv = dev->dev_private;
4102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4103 int pipe = intel_crtc->pipe;
ee7b9f93 4104 u32 reg, temp;
2c07245f 4105
ab9412ba 4106 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4107
1fbc0d78
DV		 4108 if (IS_IVYBRIDGE(dev))
4109 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4110
cd986abb
DV		 4111 /* Write the TU size bits before fdi link training, so that error
4112 * detection works. */
4113 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4114 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4115
c98e9dcf 4116 /* For PCH output, training FDI link */
674cf967 4117 dev_priv->display.fdi_link_train(crtc);
2c07245f 4118
3ad8a208
DV		 4119 /* We need to program the right clock selection before writing the pixel
4120 * mutliplier into the DPLL. */
303b81e0 4121 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4122 u32 sel;
4b645f14 4123
c98e9dcf 4124 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4125 temp |= TRANS_DPLL_ENABLE(pipe);
4126 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4127 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4128 temp |= sel;
4129 else
4130 temp &= ~sel;
c98e9dcf 4131 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4132 }
5eddb70b 4133
3ad8a208
DV		 4134 /* XXX: pch pll's can be enabled any time before we enable the PCH
4135 * transcoder, and we actually should do this to not upset any PCH
4136 * transcoder that already use the clock when we share it.
4137 *
4138 * Note that enable_shared_dpll tries to do the right thing, but
4139 * get_shared_dpll unconditionally resets the pll - we need that to have
4140 * the right LVDS enable sequence. */
85b3894f 4141 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4142
d9b6cb56
JB		 4143 /* set transcoder timing, panel must allow it */
4144 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4145 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4146
303b81e0 4147 intel_fdi_normal_train(crtc);
5e84e1a4 4148
c98e9dcf 4149 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4150 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4151 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4152 reg = TRANS_DP_CTL(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4155 TRANS_DP_SYNC_MASK |
4156 TRANS_DP_BPC_MASK);
e3ef4479 4157 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4158 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4159
4160 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4161 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4162 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4163 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4164
4165 switch (intel_trans_dp_port_sel(crtc)) {
4166 case PCH_DP_B:
5eddb70b 4167 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4168 break;
4169 case PCH_DP_C:
5eddb70b 4170 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4171 break;
4172 case PCH_DP_D:
5eddb70b 4173 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4174 break;
4175 default:
e95d41e1 4176 BUG();
32f9d658 4177 }
2c07245f 4178
5eddb70b 4179 I915_WRITE(reg, temp);
6be4a607 4180 }
b52eb4dc 4181
b8a4f404 4182 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4183}
4184
1507e5bd
PZ		 4185static void lpt_pch_enable(struct drm_crtc *crtc)
4186{
4187 struct drm_device *dev = crtc->dev;
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4190 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4191
ab9412ba 4192 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4193
8c52b5e8 4194 lpt_program_iclkip(crtc);
1507e5bd 4195
0540e488 4196 /* Set transcoder timing. */
275f01b2 4197 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4198
937bb610 4199 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4200}
4201
716c2e55 4202void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4203{
e2b78267 4204 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4205
4206 if (pll == NULL)
4207 return;
4208
3e369b76 4209 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4210 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4211 return;
4212 }
4213
3e369b76
ACO		 4214 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4215 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4216 WARN_ON(pll->on);
4217 WARN_ON(pll->active);
4218 }
4219
6e3c9717 4220 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4221}
4222
190f68c5
ACO		 4223struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4224 struct intel_crtc_state *crtc_state)
ee7b9f93 4225{
e2b78267 4226 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4227 struct intel_shared_dpll *pll;
e2b78267 4228 enum intel_dpll_id i;
ee7b9f93 4229
98b6bd99
DV		 4230 if (HAS_PCH_IBX(dev_priv->dev)) {
4231 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4232 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4233 pll = &dev_priv->shared_dplls[i];
98b6bd99 4234
46edb027
DV		 4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc->base.base.id, pll->name);
98b6bd99 4237
8bd31e67 4238 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4239
98b6bd99
DV		 4240 goto found;
4241 }
4242
bcddf610
S		 4243 if (IS_BROXTON(dev_priv->dev)) {
4244 /* PLL is attached to port in bxt */
4245 struct intel_encoder *encoder;
4246 struct intel_digital_port *intel_dig_port;
4247
4248 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4249 if (WARN_ON(!encoder))
4250 return NULL;
4251
4252 intel_dig_port = enc_to_dig_port(&encoder->base);
4253 /* 1:1 mapping between ports and PLLs */
4254 i = (enum intel_dpll_id)intel_dig_port->port;
4255 pll = &dev_priv->shared_dplls[i];
4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc->base.base.id, pll->name);
4258 WARN_ON(pll->new_config->crtc_mask);
4259
4260 goto found;
4261 }
4262
e72f9fbf
DV		 4263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4265
4266 /* Only want to check enabled timings first */
8bd31e67 4267 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4268 continue;
4269
190f68c5 4270 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4271 &pll->new_config->hw_state,
4272 sizeof(pll->new_config->hw_state)) == 0) {
4273 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4274 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4275 pll->new_config->crtc_mask,
4276 pll->active);
ee7b9f93
JB		 4277 goto found;
4278 }
4279 }
4280
4281 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4282 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4283 pll = &dev_priv->shared_dplls[i];
8bd31e67 4284 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4285 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4286 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4287 goto found;
4288 }
4289 }
4290
4291 return NULL;
4292
4293found:
8bd31e67 4294 if (pll->new_config->crtc_mask == 0)
190f68c5 4295 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4296
190f68c5 4297 crtc_state->shared_dpll = i;
46edb027
DV		 4298 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4299 pipe_name(crtc->pipe));
ee7b9f93 4300
8bd31e67 4301 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4302
ee7b9f93
JB		 4303 return pll;
4304}
4305
8bd31e67
ACO		 4306/**
4307 * intel_shared_dpll_start_config - start a new PLL staged config
4308 * @dev_priv: DRM device
4309 * @clear_pipes: mask of pipes that will have their PLLs freed
4310 *
4311 * Starts a new PLL staged config, copying the current config but
4312 * releasing the references of pipes specified in clear_pipes.
4313 */
4314static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4315 unsigned clear_pipes)
4316{
4317 struct intel_shared_dpll *pll;
4318 enum intel_dpll_id i;
4319
4320 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4321 pll = &dev_priv->shared_dplls[i];
4322
4323 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4324 GFP_KERNEL);
4325 if (!pll->new_config)
4326 goto cleanup;
4327
4328 pll->new_config->crtc_mask &= ~clear_pipes;
4329 }
4330
4331 return 0;
4332
4333cleanup:
4334 while (--i >= 0) {
4335 pll = &dev_priv->shared_dplls[i];
f354d733 4336 kfree(pll->new_config);
8bd31e67
ACO		 4337 pll->new_config = NULL;
4338 }
4339
4340 return -ENOMEM;
4341}
4342
4343static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4344{
4345 struct intel_shared_dpll *pll;
4346 enum intel_dpll_id i;
4347
4348 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4349 pll = &dev_priv->shared_dplls[i];
4350
4351 WARN_ON(pll->new_config == &pll->config);
4352
4353 pll->config = *pll->new_config;
4354 kfree(pll->new_config);
4355 pll->new_config = NULL;
4356 }
4357}
4358
4359static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4360{
4361 struct intel_shared_dpll *pll;
4362 enum intel_dpll_id i;
4363
4364 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4365 pll = &dev_priv->shared_dplls[i];
4366
4367 WARN_ON(pll->new_config == &pll->config);
4368
4369 kfree(pll->new_config);
4370 pll->new_config = NULL;
4371 }
4372}
4373
a1520318 4374static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4375{
4376 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4377 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4378 u32 temp;
4379
4380 temp = I915_READ(dslreg);
4381 udelay(500);
4382 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4383 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4384 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4385 }
4386}
4387
a1b2278e
CK		 4388/**
4389 * skl_update_scaler_users - Stages update to crtc's scaler state
4390 * @intel_crtc: crtc
4391 * @crtc_state: crtc_state
4392 * @plane: plane (NULL indicates crtc is requesting update)
4393 * @plane_state: plane's state
4394 * @force_detach: request unconditional detachment of scaler
4395 *
4396 * This function updates scaler state for requested plane or crtc.
4397 * To request scaler usage update for a plane, caller shall pass plane pointer.
4398 * To request scaler usage update for crtc, caller shall pass plane pointer
4399 * as NULL.
4400 *
4401 * Return
4402 * 0 - scaler_usage updated successfully
4403 * error - requested scaling cannot be supported or other error condition
4404 */
4405int
4406skl_update_scaler_users(
4407 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4408 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4409 int force_detach)
4410{
4411 int need_scaling;
4412 int idx;
4413 int src_w, src_h, dst_w, dst_h;
4414 int *scaler_id;
4415 struct drm_framebuffer *fb;
4416 struct intel_crtc_scaler_state *scaler_state;
6156a456 4417 unsigned int rotation;
a1b2278e
CK		 4418
4419 if (!intel_crtc || !crtc_state)
4420 return 0;
4421
4422 scaler_state = &crtc_state->scaler_state;
4423
4424 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4425 fb = intel_plane ? plane_state->base.fb : NULL;
4426
4427 if (intel_plane) {
4428 src_w = drm_rect_width(&plane_state->src) >> 16;
4429 src_h = drm_rect_height(&plane_state->src) >> 16;
4430 dst_w = drm_rect_width(&plane_state->dst);
4431 dst_h = drm_rect_height(&plane_state->dst);
4432 scaler_id = &plane_state->scaler_id;
6156a456 4433 rotation = plane_state->base.rotation;
a1b2278e
CK		 4434 } else {
4435 struct drm_display_mode *adjusted_mode =
4436 &crtc_state->base.adjusted_mode;
4437 src_w = crtc_state->pipe_src_w;
4438 src_h = crtc_state->pipe_src_h;
4439 dst_w = adjusted_mode->hdisplay;
4440 dst_h = adjusted_mode->vdisplay;
4441 scaler_id = &scaler_state->scaler_id;
6156a456 4442 rotation = DRM_ROTATE_0;
a1b2278e 4443 }
6156a456
CK		 4444
4445 need_scaling = intel_rotation_90_or_270(rotation) ?
4446 (src_h != dst_w || src_w != dst_h):
4447 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4448
4449 /*
4450 * if plane is being disabled or scaler is no more required or force detach
4451 * - free scaler binded to this plane/crtc
4452 * - in order to do this, update crtc->scaler_usage
4453 *
4454 * Here scaler state in crtc_state is set free so that
4455 * scaler can be assigned to other user. Actual register
4456 * update to free the scaler is done in plane/panel-fit programming.
4457 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4458 */
4459 if (force_detach || !need_scaling || (intel_plane &&
4460 (!fb || !plane_state->visible))) {
4461 if (*scaler_id >= 0) {
4462 scaler_state->scaler_users &= ~(1 << idx);
4463 scaler_state->scalers[*scaler_id].in_use = 0;
4464
4465 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4466 "crtc_state = %p scaler_users = 0x%x\n",
4467 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4468 intel_plane ? intel_plane->base.base.id :
4469 intel_crtc->base.base.id, crtc_state,
4470 scaler_state->scaler_users);
4471 *scaler_id = -1;
4472 }
4473 return 0;
4474 }
4475
4476 /* range checks */
4477 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4478 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4479
4480 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4481 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4482 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4483 "size is out of scaler range\n",
4484 intel_plane ? "PLANE" : "CRTC",
4485 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4486 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4487 return -EINVAL;
4488 }
4489
4490 /* check colorkey */
225c228a
CK		 4491 if (WARN_ON(intel_plane &&
4492 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4493 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4494 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4495 return -EINVAL;
4496 }
4497
4498 /* Check src format */
4499 if (intel_plane) {
4500 switch (fb->pixel_format) {
4501 case DRM_FORMAT_RGB565:
4502 case DRM_FORMAT_XBGR8888:
4503 case DRM_FORMAT_XRGB8888:
4504 case DRM_FORMAT_ABGR8888:
4505 case DRM_FORMAT_ARGB8888:
4506 case DRM_FORMAT_XRGB2101010:
a1b2278e 4507 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4508 case DRM_FORMAT_YUYV:
4509 case DRM_FORMAT_YVYU:
4510 case DRM_FORMAT_UYVY:
4511 case DRM_FORMAT_VYUY:
4512 break;
4513 default:
4514 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4515 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4516 return -EINVAL;
4517 }
4518 }
4519
4520 /* mark this plane as a scaler user in crtc_state */
4521 scaler_state->scaler_users |= (1 << idx);
4522 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4523 "crtc_state = %p scaler_users = 0x%x\n",
4524 intel_plane ? "PLANE" : "CRTC",
4525 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4526 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4527 return 0;
4528}
4529
4530static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4531{
4532 struct drm_device *dev = crtc->base.dev;
4533 struct drm_i915_private *dev_priv = dev->dev_private;
4534 int pipe = crtc->pipe;
a1b2278e
CK		 4535 struct intel_crtc_scaler_state *scaler_state =
4536 &crtc->config->scaler_state;
4537
4538 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4539
4540 /* To update pfit, first update scaler state */
4541 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4542 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4543 skl_detach_scalers(crtc);
4544 if (!enable)
4545 return;
bd2e244f 4546
6e3c9717 4547 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4548 int id;
4549
4550 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4551 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4552 return;
4553 }
4554
4555 id = scaler_state->scaler_id;
4556 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4557 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4558 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4559 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4560
4561 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4562 }
4563}
4564
b074cec8
JB		 4565static void ironlake_pfit_enable(struct intel_crtc *crtc)
4566{
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569 int pipe = crtc->pipe;
4570
6e3c9717 4571 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4572 /* Force use of hard-coded filter coefficients
4573 * as some pre-programmed values are broken,
4574 * e.g. x201.
4575 */
4576 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4577 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4578 PF_PIPE_SEL_IVB(pipe));
4579 else
4580 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4581 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4582 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4583 }
4584}
4585
4a3b8769 4586static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4587{
4588 struct drm_device *dev = crtc->dev;
4589 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4590 struct drm_plane *plane;
bb53d4ae
VS		 4591 struct intel_plane *intel_plane;
4592
af2b653b
MR		 4593 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4594 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4595 if (intel_plane->pipe == pipe)
4596 intel_plane_restore(&intel_plane->base);
af2b653b 4597 }
bb53d4ae
VS		 4598}
4599
20bc8673 4600void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4601{
cea165c3
VS		 4602 struct drm_device *dev = crtc->base.dev;
4603 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4604
6e3c9717 4605 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4606 return;
4607
cea165c3
VS		 4608 /* We can only enable IPS after we enable a plane and wait for a vblank */
4609 intel_wait_for_vblank(dev, crtc->pipe);
4610
d77e4531 4611 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4612 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4613 mutex_lock(&dev_priv->rps.hw_lock);
4614 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4615 mutex_unlock(&dev_priv->rps.hw_lock);
4616 /* Quoting Art Runyan: "its not safe to expect any particular
4617 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4618 * mailbox." Moreover, the mailbox may return a bogus state,
4619 * so we need to just enable it and continue on.
2a114cc1
BW		 4620 */
4621 } else {
4622 I915_WRITE(IPS_CTL, IPS_ENABLE);
4623 /* The bit only becomes 1 in the next vblank, so this wait here
4624 * is essentially intel_wait_for_vblank. If we don't have this
4625 * and don't wait for vblanks until the end of crtc_enable, then
4626 * the HW state readout code will complain that the expected
4627 * IPS_CTL value is not the one we read. */
4628 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4629 DRM_ERROR("Timed out waiting for IPS enable\n");
4630 }
d77e4531
PZ		 4631}
4632
20bc8673 4633void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4634{
4635 struct drm_device *dev = crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
6e3c9717 4638 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4639 return;
4640
4641 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4642 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4643 mutex_lock(&dev_priv->rps.hw_lock);
4644 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4645 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4646 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4647 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4648 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4649 } else {
2a114cc1 4650 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4651 POSTING_READ(IPS_CTL);
4652 }
d77e4531
PZ		 4653
4654 /* We need to wait for a vblank before we can disable the plane. */
4655 intel_wait_for_vblank(dev, crtc->pipe);
4656}
4657
4658/** Loads the palette/gamma unit for the CRTC with the prepared values */
4659static void intel_crtc_load_lut(struct drm_crtc *crtc)
4660{
4661 struct drm_device *dev = crtc->dev;
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664 enum pipe pipe = intel_crtc->pipe;
4665 int palreg = PALETTE(pipe);
4666 int i;
4667 bool reenable_ips = false;
4668
4669 /* The clocks have to be on to load the palette. */
83d65738 4670 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4671 return;
4672
50360403 4673 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4674 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4675 assert_dsi_pll_enabled(dev_priv);
4676 else
4677 assert_pll_enabled(dev_priv, pipe);
4678 }
4679
4680 /* use legacy palette for Ironlake */
7a1db49a 4681 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4682 palreg = LGC_PALETTE(pipe);
4683
4684 /* Workaround : Do not read or write the pipe palette/gamma data while
4685 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4686 */
6e3c9717 4687 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4688 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4689 GAMMA_MODE_MODE_SPLIT)) {
4690 hsw_disable_ips(intel_crtc);
4691 reenable_ips = true;
4692 }
4693
4694 for (i = 0; i < 256; i++) {
4695 I915_WRITE(palreg + 4 * i,
4696 (intel_crtc->lut_r[i] << 16) |
4697 (intel_crtc->lut_g[i] << 8) |
4698 intel_crtc->lut_b[i]);
4699 }
4700
4701 if (reenable_ips)
4702 hsw_enable_ips(intel_crtc);
4703}
4704
7cac945f 4705static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4706{
7cac945f 4707 if (intel_crtc->overlay) {
d3eedb1a
VS		 4708 struct drm_device *dev = intel_crtc->base.dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710
4711 mutex_lock(&dev->struct_mutex);
4712 dev_priv->mm.interruptible = false;
4713 (void) intel_overlay_switch_off(intel_crtc->overlay);
4714 dev_priv->mm.interruptible = true;
4715 mutex_unlock(&dev->struct_mutex);
4716 }
4717
4718 /* Let userspace switch the overlay on again. In most cases userspace
4719 * has to recompute where to put it anyway.
4720 */
4721}
4722
87d4300a
ML		 4723/**
4724 * intel_post_enable_primary - Perform operations after enabling primary plane
4725 * @crtc: the CRTC whose primary plane was just enabled
4726 *
4727 * Performs potentially sleeping operations that must be done after the primary
4728 * plane is enabled, such as updating FBC and IPS. Note that this may be
4729 * called due to an explicit primary plane update, or due to an implicit
4730 * re-enable that is caused when a sprite plane is updated to no longer
4731 * completely hide the primary plane.
4732 */
4733static void
4734intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4735{
4736 struct drm_device *dev = crtc->dev;
87d4300a 4737 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739 int pipe = intel_crtc->pipe;
a5c4d7bc 4740
87d4300a
ML		 4741 /*
4742 * BDW signals flip done immediately if the plane
4743 * is disabled, even if the plane enable is already
4744 * armed to occur at the next vblank :(
4745 */
4746 if (IS_BROADWELL(dev))
4747 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4748
87d4300a
ML		 4749 /*
4750 * FIXME IPS should be fine as long as one plane is
4751 * enabled, but in practice it seems to have problems
4752 * when going from primary only to sprite only and vice
4753 * versa.
4754 */
a5c4d7bc
VS		 4755 hsw_enable_ips(intel_crtc);
4756
4757 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4758 intel_fbc_update(dev);
a5c4d7bc 4759 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4760
4761 /*
87d4300a
ML		 4762 * Gen2 reports pipe underruns whenever all planes are disabled.
4763 * So don't enable underrun reporting before at least some planes
4764 * are enabled.
4765 * FIXME: Need to fix the logic to work when we turn off all planes
4766 * but leave the pipe running.
f99d7069 4767 */
87d4300a
ML		 4768 if (IS_GEN2(dev))
4769 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4770
4771 /* Underruns don't raise interrupts, so check manually. */
4772 if (HAS_GMCH_DISPLAY(dev))
4773 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4774}
4775
87d4300a
ML		 4776/**
4777 * intel_pre_disable_primary - Perform operations before disabling primary plane
4778 * @crtc: the CRTC whose primary plane is to be disabled
4779 *
4780 * Performs potentially sleeping operations that must be done before the
4781 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4782 * be called due to an explicit primary plane update, or due to an implicit
4783 * disable that is caused when a sprite plane completely hides the primary
4784 * plane.
4785 */
4786static void
4787intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4788{
4789 struct drm_device *dev = crtc->dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4792 int pipe = intel_crtc->pipe;
a5c4d7bc 4793
87d4300a
ML		 4794 /*
4795 * Gen2 reports pipe underruns whenever all planes are disabled.
4796 * So diasble underrun reporting before all the planes get disabled.
4797 * FIXME: Need to fix the logic to work when we turn off all planes
4798 * but leave the pipe running.
4799 */
4800 if (IS_GEN2(dev))
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4802
87d4300a
ML		 4803 /*
4804 * Vblank time updates from the shadow to live plane control register
4805 * are blocked if the memory self-refresh mode is active at that
4806 * moment. So to make sure the plane gets truly disabled, disable
4807 * first the self-refresh mode. The self-refresh enable bit in turn
4808 * will be checked/applied by the HW only at the next frame start
4809 * event which is after the vblank start event, so we need to have a
4810 * wait-for-vblank between disabling the plane and the pipe.
4811 */
4812 if (HAS_GMCH_DISPLAY(dev))
4813 intel_set_memory_cxsr(dev_priv, false);
4814
4815 mutex_lock(&dev->struct_mutex);
e35fef21 4816 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4817 intel_fbc_disable(dev);
87d4300a 4818 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4819
87d4300a
ML		 4820 /*
4821 * FIXME IPS should be fine as long as one plane is
4822 * enabled, but in practice it seems to have problems
4823 * when going from primary only to sprite only and vice
4824 * versa.
4825 */
a5c4d7bc 4826 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4827}
4828
4829static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4830{
2d847d45
RV		 4831 struct drm_device *dev = crtc->dev;
4832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4833 int pipe = intel_crtc->pipe;
4834
87d4300a
ML		 4835 intel_enable_primary_hw_plane(crtc->primary, crtc);
4836 intel_enable_sprite_planes(crtc);
4837 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4838
4839 intel_post_enable_primary(crtc);
2d847d45
RV		 4840
4841 /*
4842 * FIXME: Once we grow proper nuclear flip support out of this we need
4843 * to compute the mask of flip planes precisely. For the time being
4844 * consider this a flip to a NULL plane.
4845 */
4846 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
87d4300a
ML		 4847}
4848
4849static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4850{
4851 struct drm_device *dev = crtc->dev;
4852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4853 struct intel_plane *intel_plane;
4854 int pipe = intel_crtc->pipe;
4855
4856 intel_crtc_wait_for_pending_flips(crtc);
4857
4858 intel_pre_disable_primary(crtc);
a5c4d7bc 4859
7cac945f 4860 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4861 for_each_intel_plane(dev, intel_plane) {
4862 if (intel_plane->pipe == pipe) {
4863 struct drm_crtc *from = intel_plane->base.crtc;
4864
4865 intel_plane->disable_plane(&intel_plane->base,
4866 from ?: crtc, true);
4867 }
4868 }
f98551ae 4869
f99d7069
DV		 4870 /*
4871 * FIXME: Once we grow proper nuclear flip support out of this we need
4872 * to compute the mask of flip planes precisely. For the time being
4873 * consider this a flip to a NULL plane.
4874 */
4875 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4876}
4877
f67a559d
JB		 4878static void ironlake_crtc_enable(struct drm_crtc *crtc)
4879{
4880 struct drm_device *dev = crtc->dev;
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4883 struct intel_encoder *encoder;
f67a559d 4884 int pipe = intel_crtc->pipe;
f67a559d 4885
83d65738 4886 WARN_ON(!crtc->state->enable);
08a48469 4887
f67a559d
JB		 4888 if (intel_crtc->active)
4889 return;
4890
6e3c9717 4891 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4892 intel_prepare_shared_dpll(intel_crtc);
4893
6e3c9717 4894 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4895 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4896
4897 intel_set_pipe_timings(intel_crtc);
4898
6e3c9717 4899 if (intel_crtc->config->has_pch_encoder) {
29407aab 4900 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4901 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4902 }
4903
4904 ironlake_set_pipeconf(crtc);
4905
f67a559d 4906 intel_crtc->active = true;
8664281b 4907
a72e4c9f
DV		 4908 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4909 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4910
f6736a1a 4911 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4912 if (encoder->pre_enable)
4913 encoder->pre_enable(encoder);
f67a559d 4914
6e3c9717 4915 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4916 /* Note: FDI PLL enabling _must_ be done before we enable the
4917 * cpu pipes, hence this is separate from all the other fdi/pch
4918 * enabling. */
88cefb6c 4919 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4920 } else {
4921 assert_fdi_tx_disabled(dev_priv, pipe);
4922 assert_fdi_rx_disabled(dev_priv, pipe);
4923 }
f67a559d 4924
b074cec8 4925 ironlake_pfit_enable(intel_crtc);
f67a559d 4926
9c54c0dd
JB		 4927 /*
4928 * On ILK+ LUT must be loaded before the pipe is running but with
4929 * clocks enabled
4930 */
4931 intel_crtc_load_lut(crtc);
4932
f37fcc2a 4933 intel_update_watermarks(crtc);
e1fdc473 4934 intel_enable_pipe(intel_crtc);
f67a559d 4935
6e3c9717 4936 if (intel_crtc->config->has_pch_encoder)
f67a559d 4937 ironlake_pch_enable(crtc);
c98e9dcf 4938
f9b61ff6
DV		 4939 assert_vblank_disabled(crtc);
4940 drm_crtc_vblank_on(crtc);
4941
fa5c73b1
DV		 4942 for_each_encoder_on_crtc(dev, crtc, encoder)
4943 encoder->enable(encoder);
61b77ddd
DV		 4944
4945 if (HAS_PCH_CPT(dev))
a1520318 4946 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4947}
4948
42db64ef
PZ		 4949/* IPS only exists on ULT machines and is tied to pipe A. */
4950static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4951{
f5adf94e 4952 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4953}
4954
e4916946
PZ		 4955/*
4956 * This implements the workaround described in the "notes" section of the mode
4957 * set sequence documentation. When going from no pipes or single pipe to
4958 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4959 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4960 */
4961static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4962{
4963 struct drm_device *dev = crtc->base.dev;
4964 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4965
4966 /* We want to get the other_active_crtc only if there's only 1 other
4967 * active crtc. */
d3fcc808 4968 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4969 if (!crtc_it->active || crtc_it == crtc)
4970 continue;
4971
4972 if (other_active_crtc)
4973 return;
4974
4975 other_active_crtc = crtc_it;
4976 }
4977 if (!other_active_crtc)
4978 return;
4979
4980 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4981 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4982}
4983
4f771f10
PZ		 4984static void haswell_crtc_enable(struct drm_crtc *crtc)
4985{
4986 struct drm_device *dev = crtc->dev;
4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4989 struct intel_encoder *encoder;
4990 int pipe = intel_crtc->pipe;
4f771f10 4991
83d65738 4992 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4993
4994 if (intel_crtc->active)
4995 return;
4996
df8ad70c
DV		 4997 if (intel_crtc_to_shared_dpll(intel_crtc))
4998 intel_enable_shared_dpll(intel_crtc);
4999
6e3c9717 5000 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5001 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 5002
5003 intel_set_pipe_timings(intel_crtc);
5004
6e3c9717
ACO		 5005 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5006 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5007 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 5008 }
5009
6e3c9717 5010 if (intel_crtc->config->has_pch_encoder) {
229fca97 5011 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5012 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 5013 }
5014
5015 haswell_set_pipeconf(crtc);
5016
5017 intel_set_pipe_csc(crtc);
5018
4f771f10 5019 intel_crtc->active = true;
8664281b 5020
a72e4c9f 5021 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5022 for_each_encoder_on_crtc(dev, crtc, encoder)
5023 if (encoder->pre_enable)
5024 encoder->pre_enable(encoder);
5025
6e3c9717 5026 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5027 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5028 true);
4fe9467d
ID		 5029 dev_priv->display.fdi_link_train(crtc);
5030 }
5031
1f544388 5032 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5033
ff6d9f55 5034 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5035 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5036 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5037 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5038 else
5039 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5040
5041 /*
5042 * On ILK+ LUT must be loaded before the pipe is running but with
5043 * clocks enabled
5044 */
5045 intel_crtc_load_lut(crtc);
5046
1f544388 5047 intel_ddi_set_pipe_settings(crtc);
8228c251 5048 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5049
f37fcc2a 5050 intel_update_watermarks(crtc);
e1fdc473 5051 intel_enable_pipe(intel_crtc);
42db64ef 5052
6e3c9717 5053 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5054 lpt_pch_enable(crtc);
4f771f10 5055
6e3c9717 5056 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5057 intel_ddi_set_vc_payload_alloc(crtc, true);
5058
f9b61ff6
DV		 5059 assert_vblank_disabled(crtc);
5060 drm_crtc_vblank_on(crtc);
5061
8807e55b 5062 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5063 encoder->enable(encoder);
8807e55b
JN		 5064 intel_opregion_notify_encoder(encoder, true);
5065 }
4f771f10 5066
e4916946
PZ		 5067 /* If we change the relative order between pipe/planes enabling, we need
5068 * to change the workaround. */
5069 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5070}
5071
3f8dce3a
DV		 5072static void ironlake_pfit_disable(struct intel_crtc *crtc)
5073{
5074 struct drm_device *dev = crtc->base.dev;
5075 struct drm_i915_private *dev_priv = dev->dev_private;
5076 int pipe = crtc->pipe;
5077
5078 /* To avoid upsetting the power well on haswell only disable the pfit if
5079 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5080 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5081 I915_WRITE(PF_CTL(pipe), 0);
5082 I915_WRITE(PF_WIN_POS(pipe), 0);
5083 I915_WRITE(PF_WIN_SZ(pipe), 0);
5084 }
5085}
5086
6be4a607
JB		 5087static void ironlake_crtc_disable(struct drm_crtc *crtc)
5088{
5089 struct drm_device *dev = crtc->dev;
5090 struct drm_i915_private *dev_priv = dev->dev_private;
5091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5092 struct intel_encoder *encoder;
6be4a607 5093 int pipe = intel_crtc->pipe;
5eddb70b 5094 u32 reg, temp;
b52eb4dc 5095
f7abfe8b
CW		 5096 if (!intel_crtc->active)
5097 return;
5098
ea9d758d
DV		 5099 for_each_encoder_on_crtc(dev, crtc, encoder)
5100 encoder->disable(encoder);
5101
f9b61ff6
DV		 5102 drm_crtc_vblank_off(crtc);
5103 assert_vblank_disabled(crtc);
5104
6e3c9717 5105 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5106 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5107
575f7ab7 5108 intel_disable_pipe(intel_crtc);
32f9d658 5109
3f8dce3a 5110 ironlake_pfit_disable(intel_crtc);
2c07245f 5111
5a74f70a
VS		 5112 if (intel_crtc->config->has_pch_encoder)
5113 ironlake_fdi_disable(crtc);
5114
bf49ec8c
DV		 5115 for_each_encoder_on_crtc(dev, crtc, encoder)
5116 if (encoder->post_disable)
5117 encoder->post_disable(encoder);
2c07245f 5118
6e3c9717 5119 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5120 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5121
d925c59a
DV		 5122 if (HAS_PCH_CPT(dev)) {
5123 /* disable TRANS_DP_CTL */
5124 reg = TRANS_DP_CTL(pipe);
5125 temp = I915_READ(reg);
5126 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5127 TRANS_DP_PORT_SEL_MASK);
5128 temp |= TRANS_DP_PORT_SEL_NONE;
5129 I915_WRITE(reg, temp);
5130
5131 /* disable DPLL_SEL */
5132 temp = I915_READ(PCH_DPLL_SEL);
11887397 5133 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5134 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5135 }
e3421a18 5136
d925c59a 5137 /* disable PCH DPLL */
e72f9fbf 5138 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5139
d925c59a
DV		 5140 ironlake_fdi_pll_disable(intel_crtc);
5141 }
6b383a7f 5142
f7abfe8b 5143 intel_crtc->active = false;
46ba614c 5144 intel_update_watermarks(crtc);
d1ebd816
BW		 5145
5146 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5147 intel_fbc_update(dev);
d1ebd816 5148 mutex_unlock(&dev->struct_mutex);
6be4a607 5149}
1b3c7a47 5150
4f771f10 5151static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5152{
4f771f10
PZ		 5153 struct drm_device *dev = crtc->dev;
5154 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5156 struct intel_encoder *encoder;
6e3c9717 5157 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5158
4f771f10
PZ		 5159 if (!intel_crtc->active)
5160 return;
5161
8807e55b
JN		 5162 for_each_encoder_on_crtc(dev, crtc, encoder) {
5163 intel_opregion_notify_encoder(encoder, false);
4f771f10 5164 encoder->disable(encoder);
8807e55b 5165 }
4f771f10 5166
f9b61ff6
DV		 5167 drm_crtc_vblank_off(crtc);
5168 assert_vblank_disabled(crtc);
5169
6e3c9717 5170 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5171 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5172 false);
575f7ab7 5173 intel_disable_pipe(intel_crtc);
4f771f10 5174
6e3c9717 5175 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5176 intel_ddi_set_vc_payload_alloc(crtc, false);
5177
ad80a810 5178 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5179
ff6d9f55 5180 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5181 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5182 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5183 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5184 else
5185 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5186
1f544388 5187 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5188
6e3c9717 5189 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5190 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5191 intel_ddi_fdi_disable(crtc);
83616634 5192 }
4f771f10 5193
97b040aa
ID		 5194 for_each_encoder_on_crtc(dev, crtc, encoder)
5195 if (encoder->post_disable)
5196 encoder->post_disable(encoder);
5197
4f771f10 5198 intel_crtc->active = false;
46ba614c 5199 intel_update_watermarks(crtc);
4f771f10
PZ		 5200
5201 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5202 intel_fbc_update(dev);
4f771f10 5203 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5204
5205 if (intel_crtc_to_shared_dpll(intel_crtc))
5206 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5207}
5208
ee7b9f93
JB		 5209static void ironlake_crtc_off(struct drm_crtc *crtc)
5210{
5211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5212 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5213}
5214
6441ab5f 5215
2dd24552
JB		 5216static void i9xx_pfit_enable(struct intel_crtc *crtc)
5217{
5218 struct drm_device *dev = crtc->base.dev;
5219 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5220 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5221
681a8504 5222 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5223 return;
5224
2dd24552 5225 /*
c0b03411
DV		 5226 * The panel fitter should only be adjusted whilst the pipe is disabled,
5227 * according to register description and PRM.
2dd24552 5228 */
c0b03411
DV		 5229 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5230 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5231
b074cec8
JB		 5232 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5233 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5234
5235 /* Border color in case we don't scale up to the full screen. Black by
5236 * default, change to something else for debugging. */
5237 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5238}
5239
d05410f9
DA		 5240static enum intel_display_power_domain port_to_power_domain(enum port port)
5241{
5242 switch (port) {
5243 case PORT_A:
5244 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5245 case PORT_B:
5246 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5247 case PORT_C:
5248 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5249 case PORT_D:
5250 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5251 default:
5252 WARN_ON_ONCE(1);
5253 return POWER_DOMAIN_PORT_OTHER;
5254 }
5255}
5256
77d22dca
ID		 5257#define for_each_power_domain(domain, mask) \
5258 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5259 if ((1 << (domain)) & (mask))
5260
319be8ae
ID		 5261enum intel_display_power_domain
5262intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5263{
5264 struct drm_device *dev = intel_encoder->base.dev;
5265 struct intel_digital_port *intel_dig_port;
5266
5267 switch (intel_encoder->type) {
5268 case INTEL_OUTPUT_UNKNOWN:
5269 /* Only DDI platforms should ever use this output type */
5270 WARN_ON_ONCE(!HAS_DDI(dev));
5271 case INTEL_OUTPUT_DISPLAYPORT:
5272 case INTEL_OUTPUT_HDMI:
5273 case INTEL_OUTPUT_EDP:
5274 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5275 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5276 case INTEL_OUTPUT_DP_MST:
5277 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5278 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5279 case INTEL_OUTPUT_ANALOG:
5280 return POWER_DOMAIN_PORT_CRT;
5281 case INTEL_OUTPUT_DSI:
5282 return POWER_DOMAIN_PORT_DSI;
5283 default:
5284 return POWER_DOMAIN_PORT_OTHER;
5285 }
5286}
5287
5288static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5289{
319be8ae
ID		 5290 struct drm_device *dev = crtc->dev;
5291 struct intel_encoder *intel_encoder;
5292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5293 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5294 unsigned long mask;
5295 enum transcoder transcoder;
5296
5297 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5298
5299 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5300 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5301 if (intel_crtc->config->pch_pfit.enabled ||
5302 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5303 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5304
319be8ae
ID		 5305 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5306 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5307
77d22dca
ID		 5308 return mask;
5309}
5310
679dacd4 5311static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5312{
679dacd4 5313 struct drm_device *dev = state->dev;
77d22dca
ID		 5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5316 struct intel_crtc *crtc;
5317
5318 /*
5319 * First get all needed power domains, then put all unneeded, to avoid
5320 * any unnecessary toggling of the power wells.
5321 */
d3fcc808 5322 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5323 enum intel_display_power_domain domain;
5324
83d65738 5325 if (!crtc->base.state->enable)
77d22dca
ID		 5326 continue;
5327
319be8ae 5328 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5329
5330 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5331 intel_display_power_get(dev_priv, domain);
5332 }
5333
50f6e502 5334 if (dev_priv->display.modeset_global_resources)
679dacd4 5335 dev_priv->display.modeset_global_resources(state);
50f6e502 5336
d3fcc808 5337 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5338 enum intel_display_power_domain domain;
5339
5340 for_each_power_domain(domain, crtc->enabled_power_domains)
5341 intel_display_power_put(dev_priv, domain);
5342
5343 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5344 }
5345
5346 intel_display_set_init_power(dev_priv, false);
5347}
5348
70d0c574 5349static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5350{
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 uint32_t divider;
5353 uint32_t ratio;
5354 uint32_t current_freq;
5355 int ret;
5356
5357 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5358 switch (frequency) {
5359 case 144000:
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5361 ratio = BXT_DE_PLL_RATIO(60);
5362 break;
5363 case 288000:
5364 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5365 ratio = BXT_DE_PLL_RATIO(60);
5366 break;
5367 case 384000:
5368 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5369 ratio = BXT_DE_PLL_RATIO(60);
5370 break;
5371 case 576000:
5372 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5373 ratio = BXT_DE_PLL_RATIO(60);
5374 break;
5375 case 624000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5377 ratio = BXT_DE_PLL_RATIO(65);
5378 break;
5379 case 19200:
5380 /*
5381 * Bypass frequency with DE PLL disabled. Init ratio, divider
5382 * to suppress GCC warning.
5383 */
5384 ratio = 0;
5385 divider = 0;
5386 break;
5387 default:
5388 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5389
5390 return;
5391 }
5392
5393 mutex_lock(&dev_priv->rps.hw_lock);
5394 /* Inform power controller of upcoming frequency change */
5395 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5396 0x80000000);
5397 mutex_unlock(&dev_priv->rps.hw_lock);
5398
5399 if (ret) {
5400 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5401 ret, frequency);
5402 return;
5403 }
5404
5405 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5406 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5407 current_freq = current_freq * 500 + 1000;
5408
5409 /*
5410 * DE PLL has to be disabled when
5411 * - setting to 19.2MHz (bypass, PLL isn't used)
5412 * - before setting to 624MHz (PLL needs toggling)
5413 * - before setting to any frequency from 624MHz (PLL needs toggling)
5414 */
5415 if (frequency == 19200 || frequency == 624000 ||
5416 current_freq == 624000) {
5417 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5418 /* Timeout 200us */
5419 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5420 1))
5421 DRM_ERROR("timout waiting for DE PLL unlock\n");
5422 }
5423
5424 if (frequency != 19200) {
5425 uint32_t val;
5426
5427 val = I915_READ(BXT_DE_PLL_CTL);
5428 val &= ~BXT_DE_PLL_RATIO_MASK;
5429 val |= ratio;
5430 I915_WRITE(BXT_DE_PLL_CTL, val);
5431
5432 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5433 /* Timeout 200us */
5434 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5435 DRM_ERROR("timeout waiting for DE PLL lock\n");
5436
5437 val = I915_READ(CDCLK_CTL);
5438 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5439 val |= divider;
5440 /*
5441 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5442 * enable otherwise.
5443 */
5444 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5445 if (frequency >= 500000)
5446 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447
5448 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5449 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5450 val |= (frequency - 1000) / 500;
5451 I915_WRITE(CDCLK_CTL, val);
5452 }
5453
5454 mutex_lock(&dev_priv->rps.hw_lock);
5455 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5456 DIV_ROUND_UP(frequency, 25000));
5457 mutex_unlock(&dev_priv->rps.hw_lock);
5458
5459 if (ret) {
5460 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5461 ret, frequency);
5462 return;
5463 }
5464
5465 dev_priv->cdclk_freq = frequency;
5466}
5467
5468void broxton_init_cdclk(struct drm_device *dev)
5469{
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 uint32_t val;
5472
5473 /*
5474 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5475 * or else the reset will hang because there is no PCH to respond.
5476 * Move the handshake programming to initialization sequence.
5477 * Previously was left up to BIOS.
5478 */
5479 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5480 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5481 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5482
5483 /* Enable PG1 for cdclk */
5484 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5485
5486 /* check if cd clock is enabled */
5487 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5488 DRM_DEBUG_KMS("Display already initialized\n");
5489 return;
5490 }
5491
5492 /*
5493 * FIXME:
5494 * - The initial CDCLK needs to be read from VBT.
5495 * Need to make this change after VBT has changes for BXT.
5496 * - check if setting the max (or any) cdclk freq is really necessary
5497 * here, it belongs to modeset time
5498 */
5499 broxton_set_cdclk(dev, 624000);
5500
5501 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5502 POSTING_READ(DBUF_CTL);
5503
f8437dd1
VK		 5504 udelay(10);
5505
5506 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5507 DRM_ERROR("DBuf power enable timeout!\n");
5508}
5509
5510void broxton_uninit_cdclk(struct drm_device *dev)
5511{
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513
5514 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5515 POSTING_READ(DBUF_CTL);
5516
f8437dd1
VK		 5517 udelay(10);
5518
5519 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5520 DRM_ERROR("DBuf power disable timeout!\n");
5521
5522 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5523 broxton_set_cdclk(dev, 19200);
5524
5525 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5526}
5527
5d96d8af
DL		 5528static const struct skl_cdclk_entry {
5529 unsigned int freq;
5530 unsigned int vco;
5531} skl_cdclk_frequencies[] = {
5532 { .freq = 308570, .vco = 8640 },
5533 { .freq = 337500, .vco = 8100 },
5534 { .freq = 432000, .vco = 8640 },
5535 { .freq = 450000, .vco = 8100 },
5536 { .freq = 540000, .vco = 8100 },
5537 { .freq = 617140, .vco = 8640 },
5538 { .freq = 675000, .vco = 8100 },
5539};
5540
5541static unsigned int skl_cdclk_decimal(unsigned int freq)
5542{
5543 return (freq - 1000) / 500;
5544}
5545
5546static unsigned int skl_cdclk_get_vco(unsigned int freq)
5547{
5548 unsigned int i;
5549
5550 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5551 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5552
5553 if (e->freq == freq)
5554 return e->vco;
5555 }
5556
5557 return 8100;
5558}
5559
5560static void
5561skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5562{
5563 unsigned int min_freq;
5564 u32 val;
5565
5566 /* select the minimum CDCLK before enabling DPLL 0 */
5567 val = I915_READ(CDCLK_CTL);
5568 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5569 val |= CDCLK_FREQ_337_308;
5570
5571 if (required_vco == 8640)
5572 min_freq = 308570;
5573 else
5574 min_freq = 337500;
5575
5576 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5577
5578 I915_WRITE(CDCLK_CTL, val);
5579 POSTING_READ(CDCLK_CTL);
5580
5581 /*
5582 * We always enable DPLL0 with the lowest link rate possible, but still
5583 * taking into account the VCO required to operate the eDP panel at the
5584 * desired frequency. The usual DP link rates operate with a VCO of
5585 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5586 * The modeset code is responsible for the selection of the exact link
5587 * rate later on, with the constraint of choosing a frequency that
5588 * works with required_vco.
5589 */
5590 val = I915_READ(DPLL_CTRL1);
5591
5592 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5593 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5594 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5595 if (required_vco == 8640)
5596 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5597 SKL_DPLL0);
5598 else
5599 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5600 SKL_DPLL0);
5601
5602 I915_WRITE(DPLL_CTRL1, val);
5603 POSTING_READ(DPLL_CTRL1);
5604
5605 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5606
5607 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5608 DRM_ERROR("DPLL0 not locked\n");
5609}
5610
5611static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5612{
5613 int ret;
5614 u32 val;
5615
5616 /* inform PCU we want to change CDCLK */
5617 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5618 mutex_lock(&dev_priv->rps.hw_lock);
5619 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5620 mutex_unlock(&dev_priv->rps.hw_lock);
5621
5622 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5623}
5624
5625static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5626{
5627 unsigned int i;
5628
5629 for (i = 0; i < 15; i++) {
5630 if (skl_cdclk_pcu_ready(dev_priv))
5631 return true;
5632 udelay(10);
5633 }
5634
5635 return false;
5636}
5637
5638static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5639{
5640 u32 freq_select, pcu_ack;
5641
5642 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5643
5644 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5645 DRM_ERROR("failed to inform PCU about cdclk change\n");
5646 return;
5647 }
5648
5649 /* set CDCLK_CTL */
5650 switch(freq) {
5651 case 450000:
5652 case 432000:
5653 freq_select = CDCLK_FREQ_450_432;
5654 pcu_ack = 1;
5655 break;
5656 case 540000:
5657 freq_select = CDCLK_FREQ_540;
5658 pcu_ack = 2;
5659 break;
5660 case 308570:
5661 case 337500:
5662 default:
5663 freq_select = CDCLK_FREQ_337_308;
5664 pcu_ack = 0;
5665 break;
5666 case 617140:
5667 case 675000:
5668 freq_select = CDCLK_FREQ_675_617;
5669 pcu_ack = 3;
5670 break;
5671 }
5672
5673 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5674 POSTING_READ(CDCLK_CTL);
5675
5676 /* inform PCU of the change */
5677 mutex_lock(&dev_priv->rps.hw_lock);
5678 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5679 mutex_unlock(&dev_priv->rps.hw_lock);
5680}
5681
5682void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5683{
5684 /* disable DBUF power */
5685 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5686 POSTING_READ(DBUF_CTL);
5687
5688 udelay(10);
5689
5690 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5691 DRM_ERROR("DBuf power disable timeout\n");
5692
5693 /* disable DPLL0 */
5694 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5695 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5696 DRM_ERROR("Couldn't disable DPLL0\n");
5697
5698 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5699}
5700
5701void skl_init_cdclk(struct drm_i915_private *dev_priv)
5702{
5703 u32 val;
5704 unsigned int required_vco;
5705
5706 /* enable PCH reset handshake */
5707 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5708 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5709
5710 /* enable PG1 and Misc I/O */
5711 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5712
5713 /* DPLL0 already enabed !? */
5714 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5715 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5716 return;
5717 }
5718
5719 /* enable DPLL0 */
5720 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5721 skl_dpll0_enable(dev_priv, required_vco);
5722
5723 /* set CDCLK to the frequency the BIOS chose */
5724 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5725
5726 /* enable DBUF power */
5727 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5728 POSTING_READ(DBUF_CTL);
5729
5730 udelay(10);
5731
5732 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5733 DRM_ERROR("DBuf power enable timeout\n");
5734}
5735
dfcab17e 5736/* returns HPLL frequency in kHz */
f8bf63fd 5737static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5738{
586f49dc 5739 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5740
586f49dc 5741 /* Obtain SKU information */
a580516d 5742 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5743 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5744 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5745 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5746
dfcab17e 5747 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5748}
5749
44913155
VS		 5750static void intel_update_max_cdclk(struct drm_device *dev)
5751{
5752 struct drm_i915_private *dev_priv = dev->dev_private;
5753
a9419e84
DL		 5754 if (IS_SKYLAKE(dev)) {
5755 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5756
5757 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5758 dev_priv->max_cdclk_freq = 675000;
5759 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5760 dev_priv->max_cdclk_freq = 540000;
5761 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5762 dev_priv->max_cdclk_freq = 450000;
5763 else
5764 dev_priv->max_cdclk_freq = 337500;
5765 } else if (IS_BROADWELL(dev)) {
b432e5cf
VS		 5766 /*
5767 * FIXME with extra cooling we can allow
5768 * 540 MHz for ULX and 675 Mhz for ULT.
5769 * How can we know if extra cooling is
5770 * available? PCI ID, VTB, something else?
5771 */
5772 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5773 dev_priv->max_cdclk_freq = 450000;
5774 else if (IS_BDW_ULX(dev))
5775 dev_priv->max_cdclk_freq = 450000;
5776 else if (IS_BDW_ULT(dev))
5777 dev_priv->max_cdclk_freq = 540000;
5778 else
5779 dev_priv->max_cdclk_freq = 675000;
5780 } else if (IS_VALLEYVIEW(dev)) {
44913155
VS		 5781 dev_priv->max_cdclk_freq = 400000;
5782 } else {
5783 /* otherwise assume cdclk is fixed */
5784 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5785 }
5786
5787 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5788 dev_priv->max_cdclk_freq);
5789}
5790
b6283055 5791static void intel_update_cdclk(struct drm_device *dev)
f8bf63fd
VS		 5792{
5793 struct drm_i915_private *dev_priv = dev->dev_private;
5794
164dfd28 5795 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5796 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5797 dev_priv->cdclk_freq);
f8bf63fd
VS		 5798
5799 /*
5800 * Program the gmbus_freq based on the cdclk frequency.
5801 * BSpec erroneously claims we should aim for 4MHz, but
5802 * in fact 1MHz is the correct frequency.
5803 */
b6283055
VS		 5804 if (IS_VALLEYVIEW(dev)) {
5805 /*
5806 * Program the gmbus_freq based on the cdclk frequency.
5807 * BSpec erroneously claims we should aim for 4MHz, but
5808 * in fact 1MHz is the correct frequency.
5809 */
5810 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5811 }
44913155
VS		 5812
5813 if (dev_priv->max_cdclk_freq == 0)
5814 intel_update_max_cdclk(dev);
f8bf63fd
VS		 5815}
5816
30a970c6
JB		 5817/* Adjust CDclk dividers to allow high res or save power if possible */
5818static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5819{
5820 struct drm_i915_private *dev_priv = dev->dev_private;
5821 u32 val, cmd;
5822
164dfd28
VK		 5823 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5824 != dev_priv->cdclk_freq);
d60c4473 5825
dfcab17e 5826 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5827 cmd = 2;
dfcab17e 5828 else if (cdclk == 266667)
30a970c6
JB		 5829 cmd = 1;
5830 else
5831 cmd = 0;
5832
5833 mutex_lock(&dev_priv->rps.hw_lock);
5834 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5835 val &= ~DSPFREQGUAR_MASK;
5836 val |= (cmd << DSPFREQGUAR_SHIFT);
5837 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5838 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5839 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5840 50)) {
5841 DRM_ERROR("timed out waiting for CDclk change\n");
5842 }
5843 mutex_unlock(&dev_priv->rps.hw_lock);
5844
54433e91
VS		 5845 mutex_lock(&dev_priv->sb_lock);
5846
dfcab17e 5847 if (cdclk == 400000) {
6bcda4f0 5848 u32 divider;
30a970c6 5849
6bcda4f0 5850 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5851
30a970c6
JB		 5852 /* adjust cdclk divider */
5853 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5854 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5855 val |= divider;
5856 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5857
5858 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5859 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5860 50))
5861 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5862 }
5863
30a970c6
JB		 5864 /* adjust self-refresh exit latency value */
5865 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5866 val &= ~0x7f;
5867
5868 /*
5869 * For high bandwidth configs, we set a higher latency in the bunit
5870 * so that the core display fetch happens in time to avoid underruns.
5871 */
dfcab17e 5872 if (cdclk == 400000)
30a970c6
JB		 5873 val |= 4500 / 250; /* 4.5 usec */
5874 else
5875 val |= 3000 / 250; /* 3.0 usec */
5876 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5877
a580516d 5878 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5879
b6283055 5880 intel_update_cdclk(dev);
30a970c6
JB		 5881}
5882
383c5a6a
VS		 5883static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5884{
5885 struct drm_i915_private *dev_priv = dev->dev_private;
5886 u32 val, cmd;
5887
164dfd28
VK		 5888 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5889 != dev_priv->cdclk_freq);
383c5a6a
VS		 5890
5891 switch (cdclk) {
383c5a6a
VS		 5892 case 333333:
5893 case 320000:
383c5a6a 5894 case 266667:
383c5a6a 5895 case 200000:
383c5a6a
VS		 5896 break;
5897 default:
5f77eeb0 5898 MISSING_CASE(cdclk);
383c5a6a
VS		 5899 return;
5900 }
5901
9d0d3fda
VS		 5902 /*
5903 * Specs are full of misinformation, but testing on actual
5904 * hardware has shown that we just need to write the desired
5905 * CCK divider into the Punit register.
5906 */
5907 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5908
383c5a6a
VS		 5909 mutex_lock(&dev_priv->rps.hw_lock);
5910 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5911 val &= ~DSPFREQGUAR_MASK_CHV;
5912 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5913 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5914 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5915 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5916 50)) {
5917 DRM_ERROR("timed out waiting for CDclk change\n");
5918 }
5919 mutex_unlock(&dev_priv->rps.hw_lock);
5920
b6283055 5921 intel_update_cdclk(dev);
383c5a6a
VS		 5922}
5923
30a970c6
JB		 5924static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5925 int max_pixclk)
5926{
6bcda4f0 5927 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5928 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5929
30a970c6
JB		 5930 /*
5931 * Really only a few cases to deal with, as only 4 CDclks are supported:
5932 * 200MHz
5933 * 267MHz
29dc7ef3 5934 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5935 * 400MHz (VLV only)
5936 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5937 * of the lower bin and adjust if needed.
e37c67a1
VS		 5938 *
5939 * We seem to get an unstable or solid color picture at 200MHz.
5940 * Not sure what's wrong. For now use 200MHz only when all pipes
5941 * are off.
30a970c6 5942 */
6cca3195
VS		 5943 if (!IS_CHERRYVIEW(dev_priv) &&
5944 max_pixclk > freq_320*limit/100)
dfcab17e 5945 return 400000;
6cca3195 5946 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5947 return freq_320;
e37c67a1 5948 else if (max_pixclk > 0)
dfcab17e 5949 return 266667;
e37c67a1
VS		 5950 else
5951 return 200000;
30a970c6
JB		 5952}
5953
f8437dd1
VK		 5954static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5955 int max_pixclk)
5956{
5957 /*
5958 * FIXME:
5959 * - remove the guardband, it's not needed on BXT
5960 * - set 19.2MHz bypass frequency if there are no active pipes
5961 */
5962 if (max_pixclk > 576000*9/10)
5963 return 624000;
5964 else if (max_pixclk > 384000*9/10)
5965 return 576000;
5966 else if (max_pixclk > 288000*9/10)
5967 return 384000;
5968 else if (max_pixclk > 144000*9/10)
5969 return 288000;
5970 else
5971 return 144000;
5972}
5973
a821fc46
ACO		 5974/* Compute the max pixel clock for new configuration. Uses atomic state if
5975 * that's non-NULL, look at current state otherwise. */
5976static int intel_mode_max_pixclk(struct drm_device *dev,
5977 struct drm_atomic_state *state)
30a970c6 5978{
30a970c6 5979 struct intel_crtc *intel_crtc;
304603f4 5980 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5981 int max_pixclk = 0;
5982
d3fcc808 5983 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5984 if (state)
5985 crtc_state =
5986 intel_atomic_get_crtc_state(state, intel_crtc);
5987 else
5988 crtc_state = intel_crtc->config;
304603f4
ACO		 5989 if (IS_ERR(crtc_state))
5990 return PTR_ERR(crtc_state);
5991
5992 if (!crtc_state->base.enable)
5993 continue;
5994
5995 max_pixclk = max(max_pixclk,
5996 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5997 }
5998
5999 return max_pixclk;
6000}
6001
0a9ab303 6002static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 6003{
304603f4 6004 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 6005 struct drm_crtc *crtc;
6006 struct drm_crtc_state *crtc_state;
a821fc46 6007 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 6008 int cdclk, i;
30a970c6 6009
304603f4
ACO		 6010 if (max_pixclk < 0)
6011 return max_pixclk;
30a970c6 6012
f8437dd1
VK		 6013 if (IS_VALLEYVIEW(dev_priv))
6014 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
6015 else
6016 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
6017
6018 if (cdclk == dev_priv->cdclk_freq)
304603f4 6019 return 0;
30a970c6 6020
0a9ab303
ACO		 6021 /* add all active pipes to the state */
6022 for_each_crtc(state->dev, crtc) {
6023 if (!crtc->state->enable)
6024 continue;
6025
6026 crtc_state = drm_atomic_get_crtc_state(state, crtc);
6027 if (IS_ERR(crtc_state))
6028 return PTR_ERR(crtc_state);
6029 }
6030
2f2d7aa1 6031 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 6032 for_each_crtc_in_state(state, crtc, crtc_state, i)
6033 if (crtc_state->enable)
6034 crtc_state->mode_changed = true;
304603f4
ACO		 6035
6036 return 0;
30a970c6
JB		 6037}
6038
1e69cd74
VS		 6039static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6040{
6041 unsigned int credits, default_credits;
6042
6043 if (IS_CHERRYVIEW(dev_priv))
6044 default_credits = PFI_CREDIT(12);
6045 else
6046 default_credits = PFI_CREDIT(8);
6047
164dfd28 6048 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 6049 /* CHV suggested value is 31 or 63 */
6050 if (IS_CHERRYVIEW(dev_priv))
6051 credits = PFI_CREDIT_31;
6052 else
6053 credits = PFI_CREDIT(15);
6054 } else {
6055 credits = default_credits;
6056 }
6057
6058 /*
6059 * WA - write default credits before re-programming
6060 * FIXME: should we also set the resend bit here?
6061 */
6062 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6063 default_credits);
6064
6065 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6066 credits | PFI_CREDIT_RESEND);
6067
6068 /*
6069 * FIXME is this guaranteed to clear
6070 * immediately or should we poll for it?
6071 */
6072 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6073}
6074
a821fc46 6075static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 6076{
a821fc46 6077 struct drm_device *dev = old_state->dev;
30a970c6 6078 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 6079 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 6080 int req_cdclk;
6081
a821fc46
ACO		 6082 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6083 * never fail. */
304603f4
ACO		 6084 if (WARN_ON(max_pixclk < 0))
6085 return;
30a970c6 6086
304603f4 6087 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6088
164dfd28 6089 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 6090 /*
6091 * FIXME: We can end up here with all power domains off, yet
6092 * with a CDCLK frequency other than the minimum. To account
6093 * for this take the PIPE-A power domain, which covers the HW
6094 * blocks needed for the following programming. This can be
6095 * removed once it's guaranteed that we get here either with
6096 * the minimum CDCLK set, or the required power domains
6097 * enabled.
6098 */
6099 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6100
383c5a6a
VS		 6101 if (IS_CHERRYVIEW(dev))
6102 cherryview_set_cdclk(dev, req_cdclk);
6103 else
6104 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6105
1e69cd74
VS		 6106 vlv_program_pfi_credits(dev_priv);
6107
738c05c0 6108 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6109 }
30a970c6
JB		 6110}
6111
89b667f8
JB		 6112static void valleyview_crtc_enable(struct drm_crtc *crtc)
6113{
6114 struct drm_device *dev = crtc->dev;
a72e4c9f 6115 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6117 struct intel_encoder *encoder;
6118 int pipe = intel_crtc->pipe;
23538ef1 6119 bool is_dsi;
89b667f8 6120
83d65738 6121 WARN_ON(!crtc->state->enable);
89b667f8
JB		 6122
6123 if (intel_crtc->active)
6124 return;
6125
409ee761 6126 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6127
1ae0d137
VS		 6128 if (!is_dsi) {
6129 if (IS_CHERRYVIEW(dev))
6e3c9717 6130 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6131 else
6e3c9717 6132 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6133 }
5b18e57c 6134
6e3c9717 6135 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6136 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6137
6138 intel_set_pipe_timings(intel_crtc);
6139
c14b0485
VS		 6140 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6141 struct drm_i915_private *dev_priv = dev->dev_private;
6142
6143 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6144 I915_WRITE(CHV_CANVAS(pipe), 0);
6145 }
6146
5b18e57c
DV		 6147 i9xx_set_pipeconf(intel_crtc);
6148
89b667f8 6149 intel_crtc->active = true;
89b667f8 6150
a72e4c9f 6151 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6152
89b667f8
JB		 6153 for_each_encoder_on_crtc(dev, crtc, encoder)
6154 if (encoder->pre_pll_enable)
6155 encoder->pre_pll_enable(encoder);
6156
9d556c99
CML		 6157 if (!is_dsi) {
6158 if (IS_CHERRYVIEW(dev))
6e3c9717 6159 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6160 else
6e3c9717 6161 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6162 }
89b667f8
JB		 6163
6164 for_each_encoder_on_crtc(dev, crtc, encoder)
6165 if (encoder->pre_enable)
6166 encoder->pre_enable(encoder);
6167
2dd24552
JB		 6168 i9xx_pfit_enable(intel_crtc);
6169
63cbb074
VS		 6170 intel_crtc_load_lut(crtc);
6171
f37fcc2a 6172 intel_update_watermarks(crtc);
e1fdc473 6173 intel_enable_pipe(intel_crtc);
be6a6f8e 6174
4b3a9526
VS		 6175 assert_vblank_disabled(crtc);
6176 drm_crtc_vblank_on(crtc);
6177
f9b61ff6
DV		 6178 for_each_encoder_on_crtc(dev, crtc, encoder)
6179 encoder->enable(encoder);
89b667f8
JB		 6180}
6181
f13c2ef3
DV		 6182static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6183{
6184 struct drm_device *dev = crtc->base.dev;
6185 struct drm_i915_private *dev_priv = dev->dev_private;
6186
6e3c9717
ACO		 6187 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6188 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6189}
6190
0b8765c6 6191static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6192{
6193 struct drm_device *dev = crtc->dev;
a72e4c9f 6194 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6196 struct intel_encoder *encoder;
79e53945 6197 int pipe = intel_crtc->pipe;
79e53945 6198
83d65738 6199 WARN_ON(!crtc->state->enable);
08a48469 6200
f7abfe8b
CW		 6201 if (intel_crtc->active)
6202 return;
6203
f13c2ef3
DV		 6204 i9xx_set_pll_dividers(intel_crtc);
6205
6e3c9717 6206 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6207 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6208
6209 intel_set_pipe_timings(intel_crtc);
6210
5b18e57c
DV		 6211 i9xx_set_pipeconf(intel_crtc);
6212
f7abfe8b 6213 intel_crtc->active = true;
6b383a7f 6214
4a3436e8 6215 if (!IS_GEN2(dev))
a72e4c9f 6216 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6217
9d6d9f19
MK		 6218 for_each_encoder_on_crtc(dev, crtc, encoder)
6219 if (encoder->pre_enable)
6220 encoder->pre_enable(encoder);
6221
f6736a1a
DV		 6222 i9xx_enable_pll(intel_crtc);
6223
2dd24552
JB		 6224 i9xx_pfit_enable(intel_crtc);
6225
63cbb074
VS		 6226 intel_crtc_load_lut(crtc);
6227
f37fcc2a 6228 intel_update_watermarks(crtc);
e1fdc473 6229 intel_enable_pipe(intel_crtc);
be6a6f8e 6230
4b3a9526
VS		 6231 assert_vblank_disabled(crtc);
6232 drm_crtc_vblank_on(crtc);
6233
f9b61ff6
DV		 6234 for_each_encoder_on_crtc(dev, crtc, encoder)
6235 encoder->enable(encoder);
0b8765c6 6236}
79e53945 6237
87476d63
DV		 6238static void i9xx_pfit_disable(struct intel_crtc *crtc)
6239{
6240 struct drm_device *dev = crtc->base.dev;
6241 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6242
6e3c9717 6243 if (!crtc->config->gmch_pfit.control)
328d8e82 6244 return;
87476d63 6245
328d8e82 6246 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6247
328d8e82
DV		 6248 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6249 I915_READ(PFIT_CONTROL));
6250 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6251}
6252
0b8765c6
JB		 6253static void i9xx_crtc_disable(struct drm_crtc *crtc)
6254{
6255 struct drm_device *dev = crtc->dev;
6256 struct drm_i915_private *dev_priv = dev->dev_private;
6257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6258 struct intel_encoder *encoder;
0b8765c6 6259 int pipe = intel_crtc->pipe;
ef9c3aee 6260
f7abfe8b
CW		 6261 if (!intel_crtc->active)
6262 return;
6263
6304cd91
VS		 6264 /*
6265 * On gen2 planes are double buffered but the pipe isn't, so we must
6266 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6267 * We also need to wait on all gmch platforms because of the
6268 * self-refresh mode constraint explained above.
6304cd91 6269 */
564ed191 6270 intel_wait_for_vblank(dev, pipe);
6304cd91 6271
4b3a9526
VS		 6272 for_each_encoder_on_crtc(dev, crtc, encoder)
6273 encoder->disable(encoder);
6274
f9b61ff6
DV		 6275 drm_crtc_vblank_off(crtc);
6276 assert_vblank_disabled(crtc);
6277
575f7ab7 6278 intel_disable_pipe(intel_crtc);
24a1f16d 6279
87476d63 6280 i9xx_pfit_disable(intel_crtc);
24a1f16d 6281
89b667f8
JB		 6282 for_each_encoder_on_crtc(dev, crtc, encoder)
6283 if (encoder->post_disable)
6284 encoder->post_disable(encoder);
6285
409ee761 6286 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6287 if (IS_CHERRYVIEW(dev))
6288 chv_disable_pll(dev_priv, pipe);
6289 else if (IS_VALLEYVIEW(dev))
6290 vlv_disable_pll(dev_priv, pipe);
6291 else
1c4e0274 6292 i9xx_disable_pll(intel_crtc);
076ed3b2 6293 }
0b8765c6 6294
4a3436e8 6295 if (!IS_GEN2(dev))
a72e4c9f 6296 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6297
f7abfe8b 6298 intel_crtc->active = false;
46ba614c 6299 intel_update_watermarks(crtc);
f37fcc2a 6300
efa9624e 6301 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6302 intel_fbc_update(dev);
efa9624e 6303 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6304}
6305
ee7b9f93
JB		 6306static void i9xx_crtc_off(struct drm_crtc *crtc)
6307{
6308}
6309
b04c5bd6
BF		 6310/* Master function to enable/disable CRTC and corresponding power wells */
6311void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6312{
6313 struct drm_device *dev = crtc->dev;
6314 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6316 enum intel_display_power_domain domain;
6317 unsigned long domains;
976f8a20 6318
0e572fe7
DV		 6319 if (enable) {
6320 if (!intel_crtc->active) {
e1e9fb84
DV		 6321 domains = get_crtc_power_domains(crtc);
6322 for_each_power_domain(domain, domains)
6323 intel_display_power_get(dev_priv, domain);
6324 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6325
6326 dev_priv->display.crtc_enable(crtc);
ce22dba9 6327 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6328 }
6329 } else {
6330 if (intel_crtc->active) {
ce22dba9 6331 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6332 dev_priv->display.crtc_disable(crtc);
6333
e1e9fb84
DV		 6334 domains = intel_crtc->enabled_power_domains;
6335 for_each_power_domain(domain, domains)
6336 intel_display_power_put(dev_priv, domain);
6337 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6338 }
6339 }
b04c5bd6
BF		 6340}
6341
6342/**
6343 * Sets the power management mode of the pipe and plane.
6344 */
6345void intel_crtc_update_dpms(struct drm_crtc *crtc)
6346{
6347 struct drm_device *dev = crtc->dev;
6348 struct intel_encoder *intel_encoder;
6349 bool enable = false;
6350
6351 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6352 enable |= intel_encoder->connectors_active;
6353
6354 intel_crtc_control(crtc, enable);
0f63cca2
ACO		 6355
6356 crtc->state->active = enable;
976f8a20
DV		 6357}
6358
cdd59983
CW		 6359static void intel_crtc_disable(struct drm_crtc *crtc)
6360{
cdd59983 6361 struct drm_device *dev = crtc->dev;
976f8a20 6362 struct drm_connector *connector;
ee7b9f93 6363 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6364
976f8a20 6365 /* crtc should still be enabled when we disable it. */
83d65738 6366 WARN_ON(!crtc->state->enable);
976f8a20 6367
ce22dba9 6368 intel_crtc_disable_planes(crtc);
976f8a20 6369 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6370 dev_priv->display.off(crtc);
6371
70a101f8 6372 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6373
6374 /* Update computed state. */
6375 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6376 if (!connector->encoder || !connector->encoder->crtc)
6377 continue;
6378
6379 if (connector->encoder->crtc != crtc)
6380 continue;
6381
6382 connector->dpms = DRM_MODE_DPMS_OFF;
6383 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6384 }
6385}
6386
ea5b213a 6387void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6388{
4ef69c7a 6389 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6390
ea5b213a
CW		 6391 drm_encoder_cleanup(encoder);
6392 kfree(intel_encoder);
7e7d76c3
JB		 6393}
6394
9237329d 6395/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6396 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6397 * state of the entire output pipe. */
9237329d 6398static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6399{
5ab432ef
DV		 6400 if (mode == DRM_MODE_DPMS_ON) {
6401 encoder->connectors_active = true;
6402
b2cabb0e 6403 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6404 } else {
6405 encoder->connectors_active = false;
6406
b2cabb0e 6407 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6408 }
79e53945
JB		 6409}
6410
0a91ca29
DV		 6411/* Cross check the actual hw state with our own modeset state tracking (and it's
6412 * internal consistency). */
b980514c 6413static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6414{
0a91ca29
DV		 6415 if (connector->get_hw_state(connector)) {
6416 struct intel_encoder *encoder = connector->encoder;
6417 struct drm_crtc *crtc;
6418 bool encoder_enabled;
6419 enum pipe pipe;
6420
6421 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6422 connector->base.base.id,
c23cc417 6423 connector->base.name);
0a91ca29 6424
0e32b39c
DA		 6425 /* there is no real hw state for MST connectors */
6426 if (connector->mst_port)
6427 return;
6428
e2c719b7 6429 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6430 "wrong connector dpms state\n");
e2c719b7 6431 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6432 "active connector not linked to encoder\n");
0a91ca29 6433
36cd7444 6434 if (encoder) {
e2c719b7 6435 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6436 "encoder->connectors_active not set\n");
6437
6438 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6439 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6440 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6441 return;
0a91ca29 6442
36cd7444 6443 crtc = encoder->base.crtc;
0a91ca29 6444
83d65738
MR		 6445 I915_STATE_WARN(!crtc->state->enable,
6446 "crtc not enabled\n");
e2c719b7
RC		 6447 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6448 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6449 "encoder active on the wrong pipe\n");
6450 }
0a91ca29 6451 }
79e53945
JB		 6452}
6453
08d9bc92
ACO		 6454int intel_connector_init(struct intel_connector *connector)
6455{
6456 struct drm_connector_state *connector_state;
6457
6458 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6459 if (!connector_state)
6460 return -ENOMEM;
6461
6462 connector->base.state = connector_state;
6463 return 0;
6464}
6465
6466struct intel_connector *intel_connector_alloc(void)
6467{
6468 struct intel_connector *connector;
6469
6470 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6471 if (!connector)
6472 return NULL;
6473
6474 if (intel_connector_init(connector) < 0) {
6475 kfree(connector);
6476 return NULL;
6477 }
6478
6479 return connector;
6480}
6481
5ab432ef
DV		 6482/* Even simpler default implementation, if there's really no special case to
6483 * consider. */
6484void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6485{
5ab432ef
DV		 6486 /* All the simple cases only support two dpms states. */
6487 if (mode != DRM_MODE_DPMS_ON)
6488 mode = DRM_MODE_DPMS_OFF;
d4270e57 6489
5ab432ef
DV		 6490 if (mode == connector->dpms)
6491 return;
6492
6493 connector->dpms = mode;
6494
6495 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6496 if (connector->encoder)
6497 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6498
b980514c 6499 intel_modeset_check_state(connector->dev);
79e53945
JB		 6500}
6501
f0947c37
DV		 6502/* Simple connector->get_hw_state implementation for encoders that support only
6503 * one connector and no cloning and hence the encoder state determines the state
6504 * of the connector. */
6505bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6506{
24929352 6507 enum pipe pipe = 0;
f0947c37 6508 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6509
f0947c37 6510 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6511}
6512
6d293983 6513static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6514{
6d293983
ACO		 6515 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6516 return crtc_state->fdi_lanes;
d272ddfa
VS		 6517
6518 return 0;
6519}
6520
6d293983 6521static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6522 struct intel_crtc_state *pipe_config)
1857e1da 6523{
6d293983
ACO		 6524 struct drm_atomic_state *state = pipe_config->base.state;
6525 struct intel_crtc *other_crtc;
6526 struct intel_crtc_state *other_crtc_state;
6527
1857e1da
DV		 6528 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6529 pipe_name(pipe), pipe_config->fdi_lanes);
6530 if (pipe_config->fdi_lanes > 4) {
6531 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6532 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6533 return -EINVAL;
1857e1da
DV		 6534 }
6535
bafb6553 6536 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6537 if (pipe_config->fdi_lanes > 2) {
6538 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6539 pipe_config->fdi_lanes);
6d293983 6540 return -EINVAL;
1857e1da 6541 } else {
6d293983 6542 return 0;
1857e1da
DV		 6543 }
6544 }
6545
6546 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6547 return 0;
1857e1da
DV		 6548
6549 /* Ivybridge 3 pipe is really complicated */
6550 switch (pipe) {
6551 case PIPE_A:
6d293983 6552 return 0;
1857e1da 6553 case PIPE_B:
6d293983
ACO		 6554 if (pipe_config->fdi_lanes <= 2)
6555 return 0;
6556
6557 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6558 other_crtc_state =
6559 intel_atomic_get_crtc_state(state, other_crtc);
6560 if (IS_ERR(other_crtc_state))
6561 return PTR_ERR(other_crtc_state);
6562
6563 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6564 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6565 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6566 return -EINVAL;
1857e1da 6567 }
6d293983 6568 return 0;
1857e1da 6569 case PIPE_C:
251cc67c
VS		 6570 if (pipe_config->fdi_lanes > 2) {
6571 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6572 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6573 return -EINVAL;
251cc67c 6574 }
6d293983
ACO		 6575
6576 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6577 other_crtc_state =
6578 intel_atomic_get_crtc_state(state, other_crtc);
6579 if (IS_ERR(other_crtc_state))
6580 return PTR_ERR(other_crtc_state);
6581
6582 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6583 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6584 return -EINVAL;
1857e1da 6585 }
6d293983 6586 return 0;
1857e1da
DV		 6587 default:
6588 BUG();
6589 }
6590}
6591
e29c22c0
DV		 6592#define RETRY 1
6593static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6594 struct intel_crtc_state *pipe_config)
877d48d5 6595{
1857e1da 6596 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6597 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6598 int lane, link_bw, fdi_dotclock, ret;
6599 bool needs_recompute = false;
877d48d5 6600
e29c22c0 6601retry:
877d48d5
DV		 6602 /* FDI is a binary signal running at ~2.7GHz, encoding
6603 * each output octet as 10 bits. The actual frequency
6604 * is stored as a divider into a 100MHz clock, and the
6605 * mode pixel clock is stored in units of 1KHz.
6606 * Hence the bw of each lane in terms of the mode signal
6607 * is:
6608 */
6609 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6610
241bfc38 6611 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6612
2bd89a07 6613 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6614 pipe_config->pipe_bpp);
6615
6616 pipe_config->fdi_lanes = lane;
6617
2bd89a07 6618 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6619 link_bw, &pipe_config->fdi_m_n);
1857e1da 6620
6d293983
ACO		 6621 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6622 intel_crtc->pipe, pipe_config);
6623 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6624 pipe_config->pipe_bpp -= 2*3;
6625 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6626 pipe_config->pipe_bpp);
6627 needs_recompute = true;
6628 pipe_config->bw_constrained = true;
6629
6630 goto retry;
6631 }
6632
6633 if (needs_recompute)
6634 return RETRY;
6635
6d293983 6636 return ret;
877d48d5
DV		 6637}
6638
8cfb3407
VS		 6639static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6640 struct intel_crtc_state *pipe_config)
6641{
6642 if (pipe_config->pipe_bpp > 24)
6643 return false;
6644
6645 /* HSW can handle pixel rate up to cdclk? */
6646 if (IS_HASWELL(dev_priv->dev))
6647 return true;
6648
6649 /*
b432e5cf
VS		 6650 * We compare against max which means we must take
6651 * the increased cdclk requirement into account when
6652 * calculating the new cdclk.
6653 *
6654 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6655 */
6656 return ilk_pipe_pixel_rate(pipe_config) <=
6657 dev_priv->max_cdclk_freq * 95 / 100;
6658}
6659
42db64ef 6660static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6661 struct intel_crtc_state *pipe_config)
42db64ef 6662{
8cfb3407
VS		 6663 struct drm_device *dev = crtc->base.dev;
6664 struct drm_i915_private *dev_priv = dev->dev_private;
6665
d330a953 6666 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6667 hsw_crtc_supports_ips(crtc) &&
6668 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6669}
6670
a43f6e0f 6671static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6672 struct intel_crtc_state *pipe_config)
79e53945 6673{
a43f6e0f 6674 struct drm_device *dev = crtc->base.dev;
8bd31e67 6675 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6676 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6677 int ret;
89749350 6678
ad3a4479 6679 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6680 if (INTEL_INFO(dev)->gen < 4) {
44913155 6681 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6682
6683 /*
6684 * Enable pixel doubling when the dot clock
6685 * is > 90% of the (display) core speed.
6686 *
b397c96b
VS		 6687 * GDG double wide on either pipe,
6688 * otherwise pipe A only.
cf532bb2 6689 */
b397c96b 6690 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6691 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6692 clock_limit *= 2;
cf532bb2 6693 pipe_config->double_wide = true;
ad3a4479
VS		 6694 }
6695
241bfc38 6696 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6697 return -EINVAL;
2c07245f 6698 }
89749350 6699
1d1d0e27
VS		 6700 /*
6701 * Pipe horizontal size must be even in:
6702 * - DVO ganged mode
6703 * - LVDS dual channel mode
6704 * - Double wide pipe
6705 */
a93e255f 6706 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6707 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6708 pipe_config->pipe_src_w &= ~1;
6709
8693a824
DL		 6710 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6711 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6712 */
6713 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6714 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6715 return -EINVAL;
44f46b42 6716
f5adf94e 6717 if (HAS_IPS(dev))
a43f6e0f
DV		 6718 hsw_compute_ips_config(crtc, pipe_config);
6719
877d48d5 6720 if (pipe_config->has_pch_encoder)
a43f6e0f 6721 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6722
d03c93d4
CK		 6723 /* FIXME: remove below call once atomic mode set is place and all crtc
6724 * related checks called from atomic_crtc_check function */
6725 ret = 0;
6726 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6727 crtc, pipe_config->base.state);
6728 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6729
6730 return ret;
79e53945
JB		 6731}
6732
1652d19e
VS		 6733static int skylake_get_display_clock_speed(struct drm_device *dev)
6734{
6735 struct drm_i915_private *dev_priv = to_i915(dev);
6736 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6737 uint32_t cdctl = I915_READ(CDCLK_CTL);
6738 uint32_t linkrate;
6739
414355a7 6740 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6741 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6742
6743 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6744 return 540000;
6745
6746 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6747 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6748
71cd8423
DL		 6749 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6750 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6751 /* vco 8640 */
6752 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6753 case CDCLK_FREQ_450_432:
6754 return 432000;
6755 case CDCLK_FREQ_337_308:
6756 return 308570;
6757 case CDCLK_FREQ_675_617:
6758 return 617140;
6759 default:
6760 WARN(1, "Unknown cd freq selection\n");
6761 }
6762 } else {
6763 /* vco 8100 */
6764 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6765 case CDCLK_FREQ_450_432:
6766 return 450000;
6767 case CDCLK_FREQ_337_308:
6768 return 337500;
6769 case CDCLK_FREQ_675_617:
6770 return 675000;
6771 default:
6772 WARN(1, "Unknown cd freq selection\n");
6773 }
6774 }
6775
6776 /* error case, do as if DPLL0 isn't enabled */
6777 return 24000;
6778}
6779
6780static int broadwell_get_display_clock_speed(struct drm_device *dev)
6781{
6782 struct drm_i915_private *dev_priv = dev->dev_private;
6783 uint32_t lcpll = I915_READ(LCPLL_CTL);
6784 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6785
6786 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6787 return 800000;
6788 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6789 return 450000;
6790 else if (freq == LCPLL_CLK_FREQ_450)
6791 return 450000;
6792 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6793 return 540000;
6794 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6795 return 337500;
6796 else
6797 return 675000;
6798}
6799
6800static int haswell_get_display_clock_speed(struct drm_device *dev)
6801{
6802 struct drm_i915_private *dev_priv = dev->dev_private;
6803 uint32_t lcpll = I915_READ(LCPLL_CTL);
6804 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6805
6806 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6807 return 800000;
6808 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6809 return 450000;
6810 else if (freq == LCPLL_CLK_FREQ_450)
6811 return 450000;
6812 else if (IS_HSW_ULT(dev))
6813 return 337500;
6814 else
6815 return 540000;
79e53945
JB		 6816}
6817
25eb05fc
JB		 6818static int valleyview_get_display_clock_speed(struct drm_device *dev)
6819{
d197b7d3 6820 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6821 u32 val;
6822 int divider;
6823
6bcda4f0
VS		 6824 if (dev_priv->hpll_freq == 0)
6825 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6826
a580516d 6827 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6828 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6829 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6830
6831 divider = val & DISPLAY_FREQUENCY_VALUES;
6832
7d007f40
VS		 6833 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6834 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6835 "cdclk change in progress\n");
6836
6bcda4f0 6837 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6838}
6839
b37a6434
VS		 6840static int ilk_get_display_clock_speed(struct drm_device *dev)
6841{
6842 return 450000;
6843}
6844
e70236a8
JB		 6845static int i945_get_display_clock_speed(struct drm_device *dev)
6846{
6847 return 400000;
6848}
79e53945 6849
e70236a8 6850static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6851{
e907f170 6852 return 333333;
e70236a8 6853}
79e53945 6854
e70236a8
JB		 6855static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6856{
6857 return 200000;
6858}
79e53945 6859
257a7ffc
DV		 6860static int pnv_get_display_clock_speed(struct drm_device *dev)
6861{
6862 u16 gcfgc = 0;
6863
6864 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6865
6866 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6867 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6868 return 266667;
257a7ffc 6869 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6870 return 333333;
257a7ffc 6871 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6872 return 444444;
257a7ffc
DV		 6873 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6874 return 200000;
6875 default:
6876 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6877 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6878 return 133333;
257a7ffc 6879 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6880 return 166667;
257a7ffc
DV		 6881 }
6882}
6883
e70236a8
JB		 6884static int i915gm_get_display_clock_speed(struct drm_device *dev)
6885{
6886 u16 gcfgc = 0;
79e53945 6887
e70236a8
JB		 6888 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6889
6890 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6891 return 133333;
e70236a8
JB		 6892 else {
6893 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6894 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6895 return 333333;
e70236a8
JB		 6896 default:
6897 case GC_DISPLAY_CLOCK_190_200_MHZ:
6898 return 190000;
79e53945 6899 }
e70236a8
JB		 6900 }
6901}
6902
6903static int i865_get_display_clock_speed(struct drm_device *dev)
6904{
e907f170 6905 return 266667;
e70236a8
JB		 6906}
6907
1b1d2716 6908static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6909{
6910 u16 hpllcc = 0;
1b1d2716 6911
65cd2b3f
VS		 6912 /*
6913 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6914 * encoding is different :(
6915 * FIXME is this the right way to detect 852GM/852GMV?
6916 */
6917 if (dev->pdev->revision == 0x1)
6918 return 133333;
6919
1b1d2716
VS		 6920 pci_bus_read_config_word(dev->pdev->bus,
6921 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6922
e70236a8
JB		 6923 /* Assume that the hardware is in the high speed state. This
6924 * should be the default.
6925 */
6926 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6927 case GC_CLOCK_133_200:
1b1d2716 6928 case GC_CLOCK_133_200_2:
e70236a8
JB		 6929 case GC_CLOCK_100_200:
6930 return 200000;
6931 case GC_CLOCK_166_250:
6932 return 250000;
6933 case GC_CLOCK_100_133:
e907f170 6934 return 133333;
1b1d2716
VS		 6935 case GC_CLOCK_133_266:
6936 case GC_CLOCK_133_266_2:
6937 case GC_CLOCK_166_266:
6938 return 266667;
e70236a8 6939 }
79e53945 6940
e70236a8
JB		 6941 /* Shouldn't happen */
6942 return 0;
6943}
79e53945 6944
e70236a8
JB		 6945static int i830_get_display_clock_speed(struct drm_device *dev)
6946{
e907f170 6947 return 133333;
79e53945
JB		 6948}
6949
34edce2f
VS		 6950static unsigned int intel_hpll_vco(struct drm_device *dev)
6951{
6952 struct drm_i915_private *dev_priv = dev->dev_private;
6953 static const unsigned int blb_vco[8] = {
6954 [0] = 3200000,
6955 [1] = 4000000,
6956 [2] = 5333333,
6957 [3] = 4800000,
6958 [4] = 6400000,
6959 };
6960 static const unsigned int pnv_vco[8] = {
6961 [0] = 3200000,
6962 [1] = 4000000,
6963 [2] = 5333333,
6964 [3] = 4800000,
6965 [4] = 2666667,
6966 };
6967 static const unsigned int cl_vco[8] = {
6968 [0] = 3200000,
6969 [1] = 4000000,
6970 [2] = 5333333,
6971 [3] = 6400000,
6972 [4] = 3333333,
6973 [5] = 3566667,
6974 [6] = 4266667,
6975 };
6976 static const unsigned int elk_vco[8] = {
6977 [0] = 3200000,
6978 [1] = 4000000,
6979 [2] = 5333333,
6980 [3] = 4800000,
6981 };
6982 static const unsigned int ctg_vco[8] = {
6983 [0] = 3200000,
6984 [1] = 4000000,
6985 [2] = 5333333,
6986 [3] = 6400000,
6987 [4] = 2666667,
6988 [5] = 4266667,
6989 };
6990 const unsigned int *vco_table;
6991 unsigned int vco;
6992 uint8_t tmp = 0;
6993
6994 /* FIXME other chipsets? */
6995 if (IS_GM45(dev))
6996 vco_table = ctg_vco;
6997 else if (IS_G4X(dev))
6998 vco_table = elk_vco;
6999 else if (IS_CRESTLINE(dev))
7000 vco_table = cl_vco;
7001 else if (IS_PINEVIEW(dev))
7002 vco_table = pnv_vco;
7003 else if (IS_G33(dev))
7004 vco_table = blb_vco;
7005 else
7006 return 0;
7007
7008 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7009
7010 vco = vco_table[tmp & 0x7];
7011 if (vco == 0)
7012 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7013 else
7014 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7015
7016 return vco;
7017}
7018
7019static int gm45_get_display_clock_speed(struct drm_device *dev)
7020{
7021 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7022 uint16_t tmp = 0;
7023
7024 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7025
7026 cdclk_sel = (tmp >> 12) & 0x1;
7027
7028 switch (vco) {
7029 case 2666667:
7030 case 4000000:
7031 case 5333333:
7032 return cdclk_sel ? 333333 : 222222;
7033 case 3200000:
7034 return cdclk_sel ? 320000 : 228571;
7035 default:
7036 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7037 return 222222;
7038 }
7039}
7040
7041static int i965gm_get_display_clock_speed(struct drm_device *dev)
7042{
7043 static const uint8_t div_3200[] = { 16, 10, 8 };
7044 static const uint8_t div_4000[] = { 20, 12, 10 };
7045 static const uint8_t div_5333[] = { 24, 16, 14 };
7046 const uint8_t *div_table;
7047 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7048 uint16_t tmp = 0;
7049
7050 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7051
7052 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7053
7054 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7055 goto fail;
7056
7057 switch (vco) {
7058 case 3200000:
7059 div_table = div_3200;
7060 break;
7061 case 4000000:
7062 div_table = div_4000;
7063 break;
7064 case 5333333:
7065 div_table = div_5333;
7066 break;
7067 default:
7068 goto fail;
7069 }
7070
7071 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7072
7073 fail:
7074 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7075 return 200000;
7076}
7077
7078static int g33_get_display_clock_speed(struct drm_device *dev)
7079{
7080 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7081 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7082 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7083 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7084 const uint8_t *div_table;
7085 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7086 uint16_t tmp = 0;
7087
7088 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7089
7090 cdclk_sel = (tmp >> 4) & 0x7;
7091
7092 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7093 goto fail;
7094
7095 switch (vco) {
7096 case 3200000:
7097 div_table = div_3200;
7098 break;
7099 case 4000000:
7100 div_table = div_4000;
7101 break;
7102 case 4800000:
7103 div_table = div_4800;
7104 break;
7105 case 5333333:
7106 div_table = div_5333;
7107 break;
7108 default:
7109 goto fail;
7110 }
7111
7112 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7113
7114 fail:
7115 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7116 return 190476;
7117}
7118
2c07245f 7119static void
a65851af 7120intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7121{
a65851af
VS		 7122 while (*num > DATA_LINK_M_N_MASK ||
7123 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7124 *num >>= 1;
7125 *den >>= 1;
7126 }
7127}
7128
a65851af
VS		 7129static void compute_m_n(unsigned int m, unsigned int n,
7130 uint32_t *ret_m, uint32_t *ret_n)
7131{
7132 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7133 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7134 intel_reduce_m_n_ratio(ret_m, ret_n);
7135}
7136
e69d0bc1
DV		 7137void
7138intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7139 int pixel_clock, int link_clock,
7140 struct intel_link_m_n *m_n)
2c07245f 7141{
e69d0bc1 7142 m_n->tu = 64;
a65851af
VS		 7143
7144 compute_m_n(bits_per_pixel * pixel_clock,
7145 link_clock * nlanes * 8,
7146 &m_n->gmch_m, &m_n->gmch_n);
7147
7148 compute_m_n(pixel_clock, link_clock,
7149 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7150}
7151
a7615030
CW		 7152static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7153{
d330a953
JN		 7154 if (i915.panel_use_ssc >= 0)
7155 return i915.panel_use_ssc != 0;
41aa3448 7156 return dev_priv->vbt.lvds_use_ssc
435793df 7157 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7158}
7159
a93e255f
ACO		 7160static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7161 int num_connectors)
c65d77d8 7162{
a93e255f 7163 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7164 struct drm_i915_private *dev_priv = dev->dev_private;
7165 int refclk;
7166
a93e255f
ACO		 7167 WARN_ON(!crtc_state->base.state);
7168
5ab7b0b7 7169 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7170 refclk = 100000;
a93e255f 7171 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7172 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7173 refclk = dev_priv->vbt.lvds_ssc_freq;
7174 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7175 } else if (!IS_GEN2(dev)) {
7176 refclk = 96000;
7177 } else {
7178 refclk = 48000;
7179 }
7180
7181 return refclk;
7182}
7183
7429e9d4 7184static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7185{
7df00d7a 7186 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7187}
f47709a9 7188
7429e9d4
DV		 7189static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7190{
7191 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7192}
7193
f47709a9 7194static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7195 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7196 intel_clock_t *reduced_clock)
7197{
f47709a9 7198 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7199 u32 fp, fp2 = 0;
7200
7201 if (IS_PINEVIEW(dev)) {
190f68c5 7202 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7203 if (reduced_clock)
7429e9d4 7204 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7205 } else {
190f68c5 7206 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7207 if (reduced_clock)
7429e9d4 7208 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7209 }
7210
190f68c5 7211 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7212
f47709a9 7213 crtc->lowfreq_avail = false;
a93e255f 7214 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7215 reduced_clock) {
190f68c5 7216 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7217 crtc->lowfreq_avail = true;
a7516a05 7218 } else {
190f68c5 7219 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7220 }
7221}
7222
5e69f97f
CML		 7223static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7224 pipe)
89b667f8
JB		 7225{
7226 u32 reg_val;
7227
7228 /*
7229 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7230 * and set it to a reasonable value instead.
7231 */
ab3c759a 7232 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7233 reg_val &= 0xffffff00;
7234 reg_val |= 0x00000030;
ab3c759a 7235 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7236
ab3c759a 7237 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7238 reg_val &= 0x8cffffff;
7239 reg_val = 0x8c000000;
ab3c759a 7240 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7241
ab3c759a 7242 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7243 reg_val &= 0xffffff00;
ab3c759a 7244 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7245
ab3c759a 7246 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7247 reg_val &= 0x00ffffff;
7248 reg_val |= 0xb0000000;
ab3c759a 7249 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7250}
7251
b551842d
DV		 7252static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7253 struct intel_link_m_n *m_n)
7254{
7255 struct drm_device *dev = crtc->base.dev;
7256 struct drm_i915_private *dev_priv = dev->dev_private;
7257 int pipe = crtc->pipe;
7258
e3b95f1e
DV		 7259 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7260 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7261 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7262 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7263}
7264
7265static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7266 struct intel_link_m_n *m_n,
7267 struct intel_link_m_n *m2_n2)
b551842d
DV		 7268{
7269 struct drm_device *dev = crtc->base.dev;
7270 struct drm_i915_private *dev_priv = dev->dev_private;
7271 int pipe = crtc->pipe;
6e3c9717 7272 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7273
7274 if (INTEL_INFO(dev)->gen >= 5) {
7275 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7276 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7277 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7278 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7279 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7280 * for gen < 8) and if DRRS is supported (to make sure the
7281 * registers are not unnecessarily accessed).
7282 */
44395bfe 7283 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7284 crtc->config->has_drrs) {
f769cd24
VK		 7285 I915_WRITE(PIPE_DATA_M2(transcoder),
7286 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7287 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7288 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7289 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7290 }
b551842d 7291 } else {
e3b95f1e
DV		 7292 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7293 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7294 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7295 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7296 }
7297}
7298
fe3cd48d 7299void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7300{
fe3cd48d
R		 7301 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7302
7303 if (m_n == M1_N1) {
7304 dp_m_n = &crtc->config->dp_m_n;
7305 dp_m2_n2 = &crtc->config->dp_m2_n2;
7306 } else if (m_n == M2_N2) {
7307
7308 /*
7309 * M2_N2 registers are not supported. Hence m2_n2 divider value
7310 * needs to be programmed into M1_N1.
7311 */
7312 dp_m_n = &crtc->config->dp_m2_n2;
7313 } else {
7314 DRM_ERROR("Unsupported divider value\n");
7315 return;
7316 }
7317
6e3c9717
ACO		 7318 if (crtc->config->has_pch_encoder)
7319 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7320 else
fe3cd48d 7321 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7322}
7323
d288f65f 7324static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7325 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7326{
7327 u32 dpll, dpll_md;
7328
7329 /*
7330 * Enable DPIO clock input. We should never disable the reference
7331 * clock for pipe B, since VGA hotplug / manual detection depends
7332 * on it.
7333 */
7334 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7335 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7336 /* We should never disable this, set it here for state tracking */
7337 if (crtc->pipe == PIPE_B)
7338 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7339 dpll |= DPLL_VCO_ENABLE;
d288f65f 7340 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7341
d288f65f 7342 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7343 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7344 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7345}
7346
d288f65f 7347static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7348 const struct intel_crtc_state *pipe_config)
a0c4da24 7349{
f47709a9 7350 struct drm_device *dev = crtc->base.dev;
a0c4da24 7351 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7352 int pipe = crtc->pipe;
bdd4b6a6 7353 u32 mdiv;
a0c4da24 7354 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7355 u32 coreclk, reg_val;
a0c4da24 7356
a580516d 7357 mutex_lock(&dev_priv->sb_lock);
09153000 7358
d288f65f
VS		 7359 bestn = pipe_config->dpll.n;
7360 bestm1 = pipe_config->dpll.m1;
7361 bestm2 = pipe_config->dpll.m2;
7362 bestp1 = pipe_config->dpll.p1;
7363 bestp2 = pipe_config->dpll.p2;
a0c4da24 7364
89b667f8
JB		 7365 /* See eDP HDMI DPIO driver vbios notes doc */
7366
7367 /* PLL B needs special handling */
bdd4b6a6 7368 if (pipe == PIPE_B)
5e69f97f 7369 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7370
7371 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7373
7374 /* Disable target IRef on PLL */
ab3c759a 7375 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7376 reg_val &= 0x00ffffff;
ab3c759a 7377 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7378
7379 /* Disable fast lock */
ab3c759a 7380 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7381
7382 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7383 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7384 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7385 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7386 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7387
7388 /*
7389 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7390 * but we don't support that).
7391 * Note: don't use the DAC post divider as it seems unstable.
7392 */
7393 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7394 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7395
a0c4da24 7396 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7397 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7398
89b667f8 7399 /* Set HBR and RBR LPF coefficients */
d288f65f 7400 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7401 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7402 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7403 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7404 0x009f0003);
89b667f8 7405 else
ab3c759a 7406 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7407 0x00d0000f);
7408
681a8504 7409 if (pipe_config->has_dp_encoder) {
89b667f8 7410 /* Use SSC source */
bdd4b6a6 7411 if (pipe == PIPE_A)
ab3c759a 7412 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7413 0x0df40000);
7414 else
ab3c759a 7415 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7416 0x0df70000);
7417 } else { /* HDMI or VGA */
7418 /* Use bend source */
bdd4b6a6 7419 if (pipe == PIPE_A)
ab3c759a 7420 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7421 0x0df70000);
7422 else
ab3c759a 7423 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7424 0x0df40000);
7425 }
a0c4da24 7426
ab3c759a 7427 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7428 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7430 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7431 coreclk |= 0x01000000;
ab3c759a 7432 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7433
ab3c759a 7434 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7435 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7436}
7437
d288f65f 7438static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7439 struct intel_crtc_state *pipe_config)
1ae0d137 7440{
d288f65f 7441 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7442 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7443 DPLL_VCO_ENABLE;
7444 if (crtc->pipe != PIPE_A)
d288f65f 7445 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7446
d288f65f
VS		 7447 pipe_config->dpll_hw_state.dpll_md =
7448 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7449}
7450
d288f65f 7451static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7452 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7453{
7454 struct drm_device *dev = crtc->base.dev;
7455 struct drm_i915_private *dev_priv = dev->dev_private;
7456 int pipe = crtc->pipe;
7457 int dpll_reg = DPLL(crtc->pipe);
7458 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7459 u32 loopfilter, tribuf_calcntr;
9d556c99 7460 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7461 u32 dpio_val;
9cbe40c1 7462 int vco;
9d556c99 7463
d288f65f
VS		 7464 bestn = pipe_config->dpll.n;
7465 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7466 bestm1 = pipe_config->dpll.m1;
7467 bestm2 = pipe_config->dpll.m2 >> 22;
7468 bestp1 = pipe_config->dpll.p1;
7469 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7470 vco = pipe_config->dpll.vco;
a945ce7e 7471 dpio_val = 0;
9cbe40c1 7472 loopfilter = 0;
9d556c99
CML		 7473
7474 /*
7475 * Enable Refclk and SSC
7476 */
a11b0703 7477 I915_WRITE(dpll_reg,
d288f65f 7478 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7479
a580516d 7480 mutex_lock(&dev_priv->sb_lock);
9d556c99 7481
9d556c99
CML		 7482 /* p1 and p2 divider */
7483 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7484 5 << DPIO_CHV_S1_DIV_SHIFT |
7485 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7486 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7487 1 << DPIO_CHV_K_DIV_SHIFT);
7488
7489 /* Feedback post-divider - m2 */
7490 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7491
7492 /* Feedback refclk divider - n and m1 */
7493 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7494 DPIO_CHV_M1_DIV_BY_2 |
7495 1 << DPIO_CHV_N_DIV_SHIFT);
7496
7497 /* M2 fraction division */
a945ce7e
VP		 7498 if (bestm2_frac)
7499 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7500
7501 /* M2 fraction division enable */
a945ce7e
VP		 7502 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7503 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7504 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7505 if (bestm2_frac)
7506 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7507 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7508
de3a0fde
VP		 7509 /* Program digital lock detect threshold */
7510 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7511 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7512 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7513 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7514 if (!bestm2_frac)
7515 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7516 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7517
9d556c99 7518 /* Loop filter */
9cbe40c1
VP		 7519 if (vco == 5400000) {
7520 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7521 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7522 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7523 tribuf_calcntr = 0x9;
7524 } else if (vco <= 6200000) {
7525 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7526 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7527 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7528 tribuf_calcntr = 0x9;
7529 } else if (vco <= 6480000) {
7530 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7531 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7532 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7533 tribuf_calcntr = 0x8;
7534 } else {
7535 /* Not supported. Apply the same limits as in the max case */
7536 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7537 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7538 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7539 tribuf_calcntr = 0;
7540 }
9d556c99
CML		 7541 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7542
968040b2 7543 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7544 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7545 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7546 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7547
9d556c99
CML		 7548 /* AFC Recal */
7549 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7550 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7551 DPIO_AFC_RECAL);
7552
a580516d 7553 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7554}
7555
d288f65f
VS		 7556/**
7557 * vlv_force_pll_on - forcibly enable just the PLL
7558 * @dev_priv: i915 private structure
7559 * @pipe: pipe PLL to enable
7560 * @dpll: PLL configuration
7561 *
7562 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7563 * in cases where we need the PLL enabled even when @pipe is not going to
7564 * be enabled.
7565 */
7566void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7567 const struct dpll *dpll)
7568{
7569 struct intel_crtc *crtc =
7570 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7571 struct intel_crtc_state pipe_config = {
a93e255f 7572 .base.crtc = &crtc->base,
d288f65f
VS		 7573 .pixel_multiplier = 1,
7574 .dpll = *dpll,
7575 };
7576
7577 if (IS_CHERRYVIEW(dev)) {
7578 chv_update_pll(crtc, &pipe_config);
7579 chv_prepare_pll(crtc, &pipe_config);
7580 chv_enable_pll(crtc, &pipe_config);
7581 } else {
7582 vlv_update_pll(crtc, &pipe_config);
7583 vlv_prepare_pll(crtc, &pipe_config);
7584 vlv_enable_pll(crtc, &pipe_config);
7585 }
7586}
7587
7588/**
7589 * vlv_force_pll_off - forcibly disable just the PLL
7590 * @dev_priv: i915 private structure
7591 * @pipe: pipe PLL to disable
7592 *
7593 * Disable the PLL for @pipe. To be used in cases where we need
7594 * the PLL enabled even when @pipe is not going to be enabled.
7595 */
7596void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7597{
7598 if (IS_CHERRYVIEW(dev))
7599 chv_disable_pll(to_i915(dev), pipe);
7600 else
7601 vlv_disable_pll(to_i915(dev), pipe);
7602}
7603
f47709a9 7604static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7605 struct intel_crtc_state *crtc_state,
f47709a9 7606 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7607 int num_connectors)
7608{
f47709a9 7609 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7610 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7611 u32 dpll;
7612 bool is_sdvo;
190f68c5 7613 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7614
190f68c5 7615 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7616
a93e255f
ACO		 7617 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7618 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7619
7620 dpll = DPLL_VGA_MODE_DIS;
7621
a93e255f 7622 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7623 dpll |= DPLLB_MODE_LVDS;
7624 else
7625 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7626
ef1b460d 7627 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7628 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7629 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7630 }
198a037f
DV		 7631
7632 if (is_sdvo)
4a33e48d 7633 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7634
190f68c5 7635 if (crtc_state->has_dp_encoder)
4a33e48d 7636 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7637
7638 /* compute bitmask from p1 value */
7639 if (IS_PINEVIEW(dev))
7640 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7641 else {
7642 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7643 if (IS_G4X(dev) && reduced_clock)
7644 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7645 }
7646 switch (clock->p2) {
7647 case 5:
7648 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7649 break;
7650 case 7:
7651 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7652 break;
7653 case 10:
7654 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7655 break;
7656 case 14:
7657 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7658 break;
7659 }
7660 if (INTEL_INFO(dev)->gen >= 4)
7661 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7662
190f68c5 7663 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7664 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7665 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7666 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7667 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7668 else
7669 dpll |= PLL_REF_INPUT_DREFCLK;
7670
7671 dpll |= DPLL_VCO_ENABLE;
190f68c5 7672 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7673
eb1cbe48 7674 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7675 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7676 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7677 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7678 }
7679}
7680
f47709a9 7681static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7682 struct intel_crtc_state *crtc_state,
f47709a9 7683 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7684 int num_connectors)
7685{
f47709a9 7686 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7687 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7688 u32 dpll;
190f68c5 7689 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7690
190f68c5 7691 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7692
eb1cbe48
DV		 7693 dpll = DPLL_VGA_MODE_DIS;
7694
a93e255f 7695 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7696 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7697 } else {
7698 if (clock->p1 == 2)
7699 dpll |= PLL_P1_DIVIDE_BY_TWO;
7700 else
7701 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7702 if (clock->p2 == 4)
7703 dpll |= PLL_P2_DIVIDE_BY_4;
7704 }
7705
a93e255f 7706 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7707 dpll |= DPLL_DVO_2X_MODE;
7708
a93e255f 7709 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7710 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7711 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7712 else
7713 dpll |= PLL_REF_INPUT_DREFCLK;
7714
7715 dpll |= DPLL_VCO_ENABLE;
190f68c5 7716 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7717}
7718
8a654f3b 7719static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7720{
7721 struct drm_device *dev = intel_crtc->base.dev;
7722 struct drm_i915_private *dev_priv = dev->dev_private;
7723 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7724 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7725 struct drm_display_mode *adjusted_mode =
6e3c9717 7726 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7727 uint32_t crtc_vtotal, crtc_vblank_end;
7728 int vsyncshift = 0;
4d8a62ea
DV		 7729
7730 /* We need to be careful not to changed the adjusted mode, for otherwise
7731 * the hw state checker will get angry at the mismatch. */
7732 crtc_vtotal = adjusted_mode->crtc_vtotal;
7733 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7734
609aeaca 7735 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7736 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7737 crtc_vtotal -= 1;
7738 crtc_vblank_end -= 1;
609aeaca 7739
409ee761 7740 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7741 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7742 else
7743 vsyncshift = adjusted_mode->crtc_hsync_start -
7744 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7745 if (vsyncshift < 0)
7746 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7747 }
7748
7749 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7750 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7751
fe2b8f9d 7752 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7753 (adjusted_mode->crtc_hdisplay - 1) |
7754 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7755 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7756 (adjusted_mode->crtc_hblank_start - 1) |
7757 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7758 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7759 (adjusted_mode->crtc_hsync_start - 1) |
7760 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7761
fe2b8f9d 7762 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7763 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7764 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7765 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7766 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7767 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7768 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7769 (adjusted_mode->crtc_vsync_start - 1) |
7770 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7771
b5e508d4
PZ		 7772 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7773 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7774 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7775 * bits. */
7776 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7777 (pipe == PIPE_B || pipe == PIPE_C))
7778 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7779
b0e77b9c
PZ		 7780 /* pipesrc controls the size that is scaled from, which should
7781 * always be the user's requested size.
7782 */
7783 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7784 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7785 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7786}
7787
1bd1bd80 7788static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7789 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7790{
7791 struct drm_device *dev = crtc->base.dev;
7792 struct drm_i915_private *dev_priv = dev->dev_private;
7793 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7794 uint32_t tmp;
7795
7796 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7797 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7798 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7799 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7800 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7801 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7802 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7803 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7804 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7805
7806 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7807 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7808 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7809 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7810 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7811 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7812 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7813 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7814 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7815
7816 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7817 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7818 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7819 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7820 }
7821
7822 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7823 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7824 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7825
2d112de7
ACO		 7826 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7827 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7828}
7829
f6a83288 7830void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7831 struct intel_crtc_state *pipe_config)
babea61d 7832{
2d112de7
ACO		 7833 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7834 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7835 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7836 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7837
2d112de7
ACO		 7838 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7839 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7840 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7841 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7842
2d112de7 7843 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7844
2d112de7
ACO		 7845 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7846 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7847}
7848
84b046f3
DV		 7849static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7850{
7851 struct drm_device *dev = intel_crtc->base.dev;
7852 struct drm_i915_private *dev_priv = dev->dev_private;
7853 uint32_t pipeconf;
7854
9f11a9e4 7855 pipeconf = 0;
84b046f3 7856
b6b5d049
VS		 7857 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7858 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7859 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7860
6e3c9717 7861 if (intel_crtc->config->double_wide)
cf532bb2 7862 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7863
ff9ce46e
DV		 7864 /* only g4x and later have fancy bpc/dither controls */
7865 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7866 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7867 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7868 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7869 PIPECONF_DITHER_TYPE_SP;
84b046f3 7870
6e3c9717 7871 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7872 case 18:
7873 pipeconf |= PIPECONF_6BPC;
7874 break;
7875 case 24:
7876 pipeconf |= PIPECONF_8BPC;
7877 break;
7878 case 30:
7879 pipeconf |= PIPECONF_10BPC;
7880 break;
7881 default:
7882 /* Case prevented by intel_choose_pipe_bpp_dither. */
7883 BUG();
84b046f3
DV		 7884 }
7885 }
7886
7887 if (HAS_PIPE_CXSR(dev)) {
7888 if (intel_crtc->lowfreq_avail) {
7889 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7890 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7891 } else {
7892 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7893 }
7894 }
7895
6e3c9717 7896 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7897 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7898 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7899 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7900 else
7901 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7902 } else
84b046f3
DV		 7903 pipeconf |= PIPECONF_PROGRESSIVE;
7904
6e3c9717 7905 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7906 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7907
84b046f3
DV		 7908 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7909 POSTING_READ(PIPECONF(intel_crtc->pipe));
7910}
7911
190f68c5
ACO		 7912static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7913 struct intel_crtc_state *crtc_state)
79e53945 7914{
c7653199 7915 struct drm_device *dev = crtc->base.dev;
79e53945 7916 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7917 int refclk, num_connectors = 0;
652c393a 7918 intel_clock_t clock, reduced_clock;
a16af721 7919 bool ok, has_reduced_clock = false;
e9fd1c02 7920 bool is_lvds = false, is_dsi = false;
5eddb70b 7921 struct intel_encoder *encoder;
d4906093 7922 const intel_limit_t *limit;
55bb9992 7923 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7924 struct drm_connector *connector;
55bb9992
ACO		 7925 struct drm_connector_state *connector_state;
7926 int i;
79e53945 7927
dd3cd74a
ACO		 7928 memset(&crtc_state->dpll_hw_state, 0,
7929 sizeof(crtc_state->dpll_hw_state));
7930
da3ced29 7931 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7932 if (connector_state->crtc != &crtc->base)
7933 continue;
7934
7935 encoder = to_intel_encoder(connector_state->best_encoder);
7936
5eddb70b 7937 switch (encoder->type) {
79e53945
JB		 7938 case INTEL_OUTPUT_LVDS:
7939 is_lvds = true;
7940 break;
e9fd1c02
JN		 7941 case INTEL_OUTPUT_DSI:
7942 is_dsi = true;
7943 break;
6847d71b
PZ		 7944 default:
7945 break;
79e53945 7946 }
43565a06 7947
c751ce4f 7948 num_connectors++;
79e53945
JB		 7949 }
7950
f2335330 7951 if (is_dsi)
5b18e57c 7952 return 0;
f2335330 7953
190f68c5 7954 if (!crtc_state->clock_set) {
a93e255f 7955 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7956
e9fd1c02
JN		 7957 /*
7958 * Returns a set of divisors for the desired target clock with
7959 * the given refclk, or FALSE. The returned values represent
7960 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7961 * 2) / p1 / p2.
7962 */
a93e255f
ACO		 7963 limit = intel_limit(crtc_state, refclk);
7964 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7965 crtc_state->port_clock,
e9fd1c02 7966 refclk, NULL, &clock);
f2335330 7967 if (!ok) {
e9fd1c02
JN		 7968 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7969 return -EINVAL;
7970 }
79e53945 7971
f2335330
JN		 7972 if (is_lvds && dev_priv->lvds_downclock_avail) {
7973 /*
7974 * Ensure we match the reduced clock's P to the target
7975 * clock. If the clocks don't match, we can't switch
7976 * the display clock by using the FP0/FP1. In such case
7977 * we will disable the LVDS downclock feature.
7978 */
7979 has_reduced_clock =
a93e255f 7980 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7981 dev_priv->lvds_downclock,
7982 refclk, &clock,
7983 &reduced_clock);
7984 }
7985 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7986 crtc_state->dpll.n = clock.n;
7987 crtc_state->dpll.m1 = clock.m1;
7988 crtc_state->dpll.m2 = clock.m2;
7989 crtc_state->dpll.p1 = clock.p1;
7990 crtc_state->dpll.p2 = clock.p2;
f47709a9 7991 }
7026d4ac 7992
e9fd1c02 7993 if (IS_GEN2(dev)) {
190f68c5 7994 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7995 has_reduced_clock ? &reduced_clock : NULL,
7996 num_connectors);
9d556c99 7997 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7998 chv_update_pll(crtc, crtc_state);
e9fd1c02 7999 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 8000 vlv_update_pll(crtc, crtc_state);
e9fd1c02 8001 } else {
190f68c5 8002 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 8003 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 8004 num_connectors);
e9fd1c02 8005 }
79e53945 8006
c8f7a0db 8007 return 0;
f564048e
EA		 8008}
8009
2fa2fe9a 8010static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8011 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8012{
8013 struct drm_device *dev = crtc->base.dev;
8014 struct drm_i915_private *dev_priv = dev->dev_private;
8015 uint32_t tmp;
8016
dc9e7dec
VS		 8017 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8018 return;
8019
2fa2fe9a 8020 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 8021 if (!(tmp & PFIT_ENABLE))
8022 return;
2fa2fe9a 8023
06922821 8024 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 8025 if (INTEL_INFO(dev)->gen < 4) {
8026 if (crtc->pipe != PIPE_B)
8027 return;
2fa2fe9a
DV		 8028 } else {
8029 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8030 return;
8031 }
8032
06922821 8033 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 8034 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8035 if (INTEL_INFO(dev)->gen < 5)
8036 pipe_config->gmch_pfit.lvds_border_bits =
8037 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8038}
8039
acbec814 8040static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8041 struct intel_crtc_state *pipe_config)
acbec814
JB		 8042{
8043 struct drm_device *dev = crtc->base.dev;
8044 struct drm_i915_private *dev_priv = dev->dev_private;
8045 int pipe = pipe_config->cpu_transcoder;
8046 intel_clock_t clock;
8047 u32 mdiv;
662c6ecb 8048 int refclk = 100000;
acbec814 8049
f573de5a
SK		 8050 /* In case of MIPI DPLL will not even be used */
8051 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8052 return;
8053
a580516d 8054 mutex_lock(&dev_priv->sb_lock);
ab3c759a 8055 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 8056 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 8057
8058 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8059 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8060 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8061 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8062 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8063
f646628b 8064 vlv_clock(refclk, &clock);
acbec814 8065
f646628b
VS		 8066 /* clock.dot is the fast clock */
8067 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 8068}
8069
5724dbd1
DL		 8070static void
8071i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8072 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 8073{
8074 struct drm_device *dev = crtc->base.dev;
8075 struct drm_i915_private *dev_priv = dev->dev_private;
8076 u32 val, base, offset;
8077 int pipe = crtc->pipe, plane = crtc->plane;
8078 int fourcc, pixel_format;
6761dd31 8079 unsigned int aligned_height;
b113d5ee 8080 struct drm_framebuffer *fb;
1b842c89 8081 struct intel_framebuffer *intel_fb;
1ad292b5 8082
42a7b088
DL		 8083 val = I915_READ(DSPCNTR(plane));
8084 if (!(val & DISPLAY_PLANE_ENABLE))
8085 return;
8086
d9806c9f 8087 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8088 if (!intel_fb) {
1ad292b5
JB		 8089 DRM_DEBUG_KMS("failed to alloc fb\n");
8090 return;
8091 }
8092
1b842c89
DL		 8093 fb = &intel_fb->base;
8094
18c5247e
DV		 8095 if (INTEL_INFO(dev)->gen >= 4) {
8096 if (val & DISPPLANE_TILED) {
49af449b 8097 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8098 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8099 }
8100 }
1ad292b5
JB		 8101
8102 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8103 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8104 fb->pixel_format = fourcc;
8105 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8106
8107 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8108 if (plane_config->tiling)
1ad292b5
JB		 8109 offset = I915_READ(DSPTILEOFF(plane));
8110 else
8111 offset = I915_READ(DSPLINOFF(plane));
8112 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8113 } else {
8114 base = I915_READ(DSPADDR(plane));
8115 }
8116 plane_config->base = base;
8117
8118 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8119 fb->width = ((val >> 16) & 0xfff) + 1;
8120 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8121
8122 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8123 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8124
b113d5ee 8125 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8126 fb->pixel_format,
8127 fb->modifier[0]);
1ad292b5 8128
f37b5c2b 8129 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8130
2844a921
DL		 8131 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8132 pipe_name(pipe), plane, fb->width, fb->height,
8133 fb->bits_per_pixel, base, fb->pitches[0],
8134 plane_config->size);
1ad292b5 8135
2d14030b 8136 plane_config->fb = intel_fb;
1ad292b5
JB		 8137}
8138
70b23a98 8139static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8140 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8141{
8142 struct drm_device *dev = crtc->base.dev;
8143 struct drm_i915_private *dev_priv = dev->dev_private;
8144 int pipe = pipe_config->cpu_transcoder;
8145 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8146 intel_clock_t clock;
8147 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8148 int refclk = 100000;
8149
a580516d 8150 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8151 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8152 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8153 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8154 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8155 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8156
8157 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8158 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8159 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8160 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8161 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8162
8163 chv_clock(refclk, &clock);
8164
8165 /* clock.dot is the fast clock */
8166 pipe_config->port_clock = clock.dot / 5;
8167}
8168
0e8ffe1b 8169static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8170 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8171{
8172 struct drm_device *dev = crtc->base.dev;
8173 struct drm_i915_private *dev_priv = dev->dev_private;
8174 uint32_t tmp;
8175
f458ebbc
DV		 8176 if (!intel_display_power_is_enabled(dev_priv,
8177 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8178 return false;
8179
e143a21c 8180 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8181 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8182
0e8ffe1b
DV		 8183 tmp = I915_READ(PIPECONF(crtc->pipe));
8184 if (!(tmp & PIPECONF_ENABLE))
8185 return false;
8186
42571aef
VS		 8187 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8188 switch (tmp & PIPECONF_BPC_MASK) {
8189 case PIPECONF_6BPC:
8190 pipe_config->pipe_bpp = 18;
8191 break;
8192 case PIPECONF_8BPC:
8193 pipe_config->pipe_bpp = 24;
8194 break;
8195 case PIPECONF_10BPC:
8196 pipe_config->pipe_bpp = 30;
8197 break;
8198 default:
8199 break;
8200 }
8201 }
8202
b5a9fa09
DV		 8203 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8204 pipe_config->limited_color_range = true;
8205
282740f7
VS		 8206 if (INTEL_INFO(dev)->gen < 4)
8207 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8208
1bd1bd80
DV		 8209 intel_get_pipe_timings(crtc, pipe_config);
8210
2fa2fe9a
DV		 8211 i9xx_get_pfit_config(crtc, pipe_config);
8212
6c49f241
DV		 8213 if (INTEL_INFO(dev)->gen >= 4) {
8214 tmp = I915_READ(DPLL_MD(crtc->pipe));
8215 pipe_config->pixel_multiplier =
8216 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8217 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8218 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8219 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8220 tmp = I915_READ(DPLL(crtc->pipe));
8221 pipe_config->pixel_multiplier =
8222 ((tmp & SDVO_MULTIPLIER_MASK)
8223 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8224 } else {
8225 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8226 * port and will be fixed up in the encoder->get_config
8227 * function. */
8228 pipe_config->pixel_multiplier = 1;
8229 }
8bcc2795
DV		 8230 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8231 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8232 /*
8233 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8234 * on 830. Filter it out here so that we don't
8235 * report errors due to that.
8236 */
8237 if (IS_I830(dev))
8238 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8239
8bcc2795
DV		 8240 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8241 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8242 } else {
8243 /* Mask out read-only status bits. */
8244 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8245 DPLL_PORTC_READY_MASK |
8246 DPLL_PORTB_READY_MASK);
8bcc2795 8247 }
6c49f241 8248
70b23a98
VS		 8249 if (IS_CHERRYVIEW(dev))
8250 chv_crtc_clock_get(crtc, pipe_config);
8251 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8252 vlv_crtc_clock_get(crtc, pipe_config);
8253 else
8254 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8255
0e8ffe1b
DV		 8256 return true;
8257}
8258
dde86e2d 8259static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8260{
8261 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8262 struct intel_encoder *encoder;
74cfd7ac 8263 u32 val, final;
13d83a67 8264 bool has_lvds = false;
199e5d79 8265 bool has_cpu_edp = false;
199e5d79 8266 bool has_panel = false;
99eb6a01
KP		 8267 bool has_ck505 = false;
8268 bool can_ssc = false;
13d83a67
JB		 8269
8270 /* We need to take the global config into account */
b2784e15 8271 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8272 switch (encoder->type) {
8273 case INTEL_OUTPUT_LVDS:
8274 has_panel = true;
8275 has_lvds = true;
8276 break;
8277 case INTEL_OUTPUT_EDP:
8278 has_panel = true;
2de6905f 8279 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8280 has_cpu_edp = true;
8281 break;
6847d71b
PZ		 8282 default:
8283 break;
13d83a67
JB		 8284 }
8285 }
8286
99eb6a01 8287 if (HAS_PCH_IBX(dev)) {
41aa3448 8288 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8289 can_ssc = has_ck505;
8290 } else {
8291 has_ck505 = false;
8292 can_ssc = true;
8293 }
8294
2de6905f
ID		 8295 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8296 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8297
8298 /* Ironlake: try to setup display ref clock before DPLL
8299 * enabling. This is only under driver's control after
8300 * PCH B stepping, previous chipset stepping should be
8301 * ignoring this setting.
8302 */
74cfd7ac
CW		 8303 val = I915_READ(PCH_DREF_CONTROL);
8304
8305 /* As we must carefully and slowly disable/enable each source in turn,
8306 * compute the final state we want first and check if we need to
8307 * make any changes at all.
8308 */
8309 final = val;
8310 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8311 if (has_ck505)
8312 final |= DREF_NONSPREAD_CK505_ENABLE;
8313 else
8314 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8315
8316 final &= ~DREF_SSC_SOURCE_MASK;
8317 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8318 final &= ~DREF_SSC1_ENABLE;
8319
8320 if (has_panel) {
8321 final |= DREF_SSC_SOURCE_ENABLE;
8322
8323 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8324 final |= DREF_SSC1_ENABLE;
8325
8326 if (has_cpu_edp) {
8327 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8328 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8329 else
8330 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8331 } else
8332 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8333 } else {
8334 final |= DREF_SSC_SOURCE_DISABLE;
8335 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8336 }
8337
8338 if (final == val)
8339 return;
8340
13d83a67 8341 /* Always enable nonspread source */
74cfd7ac 8342 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8343
99eb6a01 8344 if (has_ck505)
74cfd7ac 8345 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8346 else
74cfd7ac 8347 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8348
199e5d79 8349 if (has_panel) {
74cfd7ac
CW		 8350 val &= ~DREF_SSC_SOURCE_MASK;
8351 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8352
199e5d79 8353 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8354 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8355 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8356 val |= DREF_SSC1_ENABLE;
e77166b5 8357 } else
74cfd7ac 8358 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8359
8360 /* Get SSC going before enabling the outputs */
74cfd7ac 8361 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8362 POSTING_READ(PCH_DREF_CONTROL);
8363 udelay(200);
8364
74cfd7ac 8365 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8366
8367 /* Enable CPU source on CPU attached eDP */
199e5d79 8368 if (has_cpu_edp) {
99eb6a01 8369 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8370 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8371 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8372 } else
74cfd7ac 8373 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8374 } else
74cfd7ac 8375 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8376
74cfd7ac 8377 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8378 POSTING_READ(PCH_DREF_CONTROL);
8379 udelay(200);
8380 } else {
8381 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8382
74cfd7ac 8383 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8384
8385 /* Turn off CPU output */
74cfd7ac 8386 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8387
74cfd7ac 8388 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8389 POSTING_READ(PCH_DREF_CONTROL);
8390 udelay(200);
8391
8392 /* Turn off the SSC source */
74cfd7ac
CW		 8393 val &= ~DREF_SSC_SOURCE_MASK;
8394 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8395
8396 /* Turn off SSC1 */
74cfd7ac 8397 val &= ~DREF_SSC1_ENABLE;
199e5d79 8398
74cfd7ac 8399 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8400 POSTING_READ(PCH_DREF_CONTROL);
8401 udelay(200);
8402 }
74cfd7ac
CW		 8403
8404 BUG_ON(val != final);
13d83a67
JB		 8405}
8406
f31f2d55 8407static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8408{
f31f2d55 8409 uint32_t tmp;
dde86e2d 8410
0ff066a9
PZ		 8411 tmp = I915_READ(SOUTH_CHICKEN2);
8412 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8413 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8414
0ff066a9
PZ		 8415 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8416 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8417 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8418
0ff066a9
PZ		 8419 tmp = I915_READ(SOUTH_CHICKEN2);
8420 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8421 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8422
0ff066a9
PZ		 8423 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8424 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8425 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8426}
8427
8428/* WaMPhyProgramming:hsw */
8429static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8430{
8431 uint32_t tmp;
dde86e2d
PZ		 8432
8433 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8434 tmp &= ~(0xFF << 24);
8435 tmp |= (0x12 << 24);
8436 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8437
dde86e2d
PZ		 8438 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8439 tmp |= (1 << 11);
8440 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8441
8442 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8443 tmp |= (1 << 11);
8444 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8445
dde86e2d
PZ		 8446 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8447 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8448 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8449
8450 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8451 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8452 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8453
0ff066a9
PZ		 8454 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8455 tmp &= ~(7 << 13);
8456 tmp |= (5 << 13);
8457 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8458
0ff066a9
PZ		 8459 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8460 tmp &= ~(7 << 13);
8461 tmp |= (5 << 13);
8462 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8463
8464 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8465 tmp &= ~0xFF;
8466 tmp |= 0x1C;
8467 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8468
8469 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8470 tmp &= ~0xFF;
8471 tmp |= 0x1C;
8472 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8473
8474 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8475 tmp &= ~(0xFF << 16);
8476 tmp |= (0x1C << 16);
8477 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8478
8479 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8480 tmp &= ~(0xFF << 16);
8481 tmp |= (0x1C << 16);
8482 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8483
0ff066a9
PZ		 8484 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8485 tmp |= (1 << 27);
8486 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8487
0ff066a9
PZ		 8488 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8489 tmp |= (1 << 27);
8490 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8491
0ff066a9
PZ		 8492 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8493 tmp &= ~(0xF << 28);
8494 tmp |= (4 << 28);
8495 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8496
0ff066a9
PZ		 8497 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8498 tmp &= ~(0xF << 28);
8499 tmp |= (4 << 28);
8500 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8501}
8502
2fa86a1f
PZ		 8503/* Implements 3 different sequences from BSpec chapter "Display iCLK
8504 * Programming" based on the parameters passed:
8505 * - Sequence to enable CLKOUT_DP
8506 * - Sequence to enable CLKOUT_DP without spread
8507 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8508 */
8509static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8510 bool with_fdi)
f31f2d55
PZ		 8511{
8512 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8513 uint32_t reg, tmp;
8514
8515 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8516 with_spread = true;
8517 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8518 with_fdi, "LP PCH doesn't have FDI\n"))
8519 with_fdi = false;
f31f2d55 8520
a580516d 8521 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8522
8523 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8524 tmp &= ~SBI_SSCCTL_DISABLE;
8525 tmp |= SBI_SSCCTL_PATHALT;
8526 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8527
8528 udelay(24);
8529
2fa86a1f
PZ		 8530 if (with_spread) {
8531 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8532 tmp &= ~SBI_SSCCTL_PATHALT;
8533 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8534
2fa86a1f
PZ		 8535 if (with_fdi) {
8536 lpt_reset_fdi_mphy(dev_priv);
8537 lpt_program_fdi_mphy(dev_priv);
8538 }
8539 }
dde86e2d 8540
2fa86a1f
PZ		 8541 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8542 SBI_GEN0 : SBI_DBUFF0;
8543 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8544 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8545 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8546
a580516d 8547 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8548}
8549
47701c3b
PZ		 8550/* Sequence to disable CLKOUT_DP */
8551static void lpt_disable_clkout_dp(struct drm_device *dev)
8552{
8553 struct drm_i915_private *dev_priv = dev->dev_private;
8554 uint32_t reg, tmp;
8555
a580516d 8556 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8557
8558 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8559 SBI_GEN0 : SBI_DBUFF0;
8560 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8561 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8562 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8563
8564 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8565 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8566 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8567 tmp |= SBI_SSCCTL_PATHALT;
8568 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8569 udelay(32);
8570 }
8571 tmp |= SBI_SSCCTL_DISABLE;
8572 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8573 }
8574
a580516d 8575 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8576}
8577
bf8fa3d3
PZ		 8578static void lpt_init_pch_refclk(struct drm_device *dev)
8579{
bf8fa3d3
PZ		 8580 struct intel_encoder *encoder;
8581 bool has_vga = false;
8582
b2784e15 8583 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8584 switch (encoder->type) {
8585 case INTEL_OUTPUT_ANALOG:
8586 has_vga = true;
8587 break;
6847d71b
PZ		 8588 default:
8589 break;
bf8fa3d3
PZ		 8590 }
8591 }
8592
47701c3b
PZ		 8593 if (has_vga)
8594 lpt_enable_clkout_dp(dev, true, true);
8595 else
8596 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8597}
8598
dde86e2d
PZ		 8599/*
8600 * Initialize reference clocks when the driver loads
8601 */
8602void intel_init_pch_refclk(struct drm_device *dev)
8603{
8604 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8605 ironlake_init_pch_refclk(dev);
8606 else if (HAS_PCH_LPT(dev))
8607 lpt_init_pch_refclk(dev);
8608}
8609
55bb9992 8610static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8611{
55bb9992 8612 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8613 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8614 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8615 struct drm_connector *connector;
55bb9992 8616 struct drm_connector_state *connector_state;
d9d444cb 8617 struct intel_encoder *encoder;
55bb9992 8618 int num_connectors = 0, i;
d9d444cb
JB		 8619 bool is_lvds = false;
8620
da3ced29 8621 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8622 if (connector_state->crtc != crtc_state->base.crtc)
8623 continue;
8624
8625 encoder = to_intel_encoder(connector_state->best_encoder);
8626
d9d444cb
JB		 8627 switch (encoder->type) {
8628 case INTEL_OUTPUT_LVDS:
8629 is_lvds = true;
8630 break;
6847d71b
PZ		 8631 default:
8632 break;
d9d444cb
JB		 8633 }
8634 num_connectors++;
8635 }
8636
8637 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8638 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8639 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8640 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8641 }
8642
8643 return 120000;
8644}
8645
6ff93609 8646static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8647{
c8203565 8648 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8650 int pipe = intel_crtc->pipe;
c8203565
PZ		 8651 uint32_t val;
8652
78114071 8653 val = 0;
c8203565 8654
6e3c9717 8655 switch (intel_crtc->config->pipe_bpp) {
c8203565 8656 case 18:
dfd07d72 8657 val |= PIPECONF_6BPC;
c8203565
PZ		 8658 break;
8659 case 24:
dfd07d72 8660 val |= PIPECONF_8BPC;
c8203565
PZ		 8661 break;
8662 case 30:
dfd07d72 8663 val |= PIPECONF_10BPC;
c8203565
PZ		 8664 break;
8665 case 36:
dfd07d72 8666 val |= PIPECONF_12BPC;
c8203565
PZ		 8667 break;
8668 default:
cc769b62
PZ		 8669 /* Case prevented by intel_choose_pipe_bpp_dither. */
8670 BUG();
c8203565
PZ		 8671 }
8672
6e3c9717 8673 if (intel_crtc->config->dither)
c8203565
PZ		 8674 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8675
6e3c9717 8676 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8677 val |= PIPECONF_INTERLACED_ILK;
8678 else
8679 val |= PIPECONF_PROGRESSIVE;
8680
6e3c9717 8681 if (intel_crtc->config->limited_color_range)
3685a8f3 8682 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8683
c8203565
PZ		 8684 I915_WRITE(PIPECONF(pipe), val);
8685 POSTING_READ(PIPECONF(pipe));
8686}
8687
86d3efce
VS		 8688/*
8689 * Set up the pipe CSC unit.
8690 *
8691 * Currently only full range RGB to limited range RGB conversion
8692 * is supported, but eventually this should handle various
8693 * RGB<->YCbCr scenarios as well.
8694 */
50f3b016 8695static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8696{
8697 struct drm_device *dev = crtc->dev;
8698 struct drm_i915_private *dev_priv = dev->dev_private;
8699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8700 int pipe = intel_crtc->pipe;
8701 uint16_t coeff = 0x7800; /* 1.0 */
8702
8703 /*
8704 * TODO: Check what kind of values actually come out of the pipe
8705 * with these coeff/postoff values and adjust to get the best
8706 * accuracy. Perhaps we even need to take the bpc value into
8707 * consideration.
8708 */
8709
6e3c9717 8710 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8711 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8712
8713 /*
8714 * GY/GU and RY/RU should be the other way around according
8715 * to BSpec, but reality doesn't agree. Just set them up in
8716 * a way that results in the correct picture.
8717 */
8718 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8719 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8720
8721 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8722 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8723
8724 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8725 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8726
8727 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8728 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8729 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8730
8731 if (INTEL_INFO(dev)->gen > 6) {
8732 uint16_t postoff = 0;
8733
6e3c9717 8734 if (intel_crtc->config->limited_color_range)
32cf0cb0 8735 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8736
8737 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8738 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8739 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8740
8741 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8742 } else {
8743 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8744
6e3c9717 8745 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8746 mode |= CSC_BLACK_SCREEN_OFFSET;
8747
8748 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8749 }
8750}
8751
6ff93609 8752static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8753{
756f85cf
PZ		 8754 struct drm_device *dev = crtc->dev;
8755 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8757 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8758 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8759 uint32_t val;
8760
3eff4faa 8761 val = 0;
ee2b0b38 8762
6e3c9717 8763 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8764 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8765
6e3c9717 8766 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8767 val |= PIPECONF_INTERLACED_ILK;
8768 else
8769 val |= PIPECONF_PROGRESSIVE;
8770
702e7a56
PZ		 8771 I915_WRITE(PIPECONF(cpu_transcoder), val);
8772 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8773
8774 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8775 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8776
3cdf122c 8777 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8778 val = 0;
8779
6e3c9717 8780 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8781 case 18:
8782 val |= PIPEMISC_DITHER_6_BPC;
8783 break;
8784 case 24:
8785 val |= PIPEMISC_DITHER_8_BPC;
8786 break;
8787 case 30:
8788 val |= PIPEMISC_DITHER_10_BPC;
8789 break;
8790 case 36:
8791 val |= PIPEMISC_DITHER_12_BPC;
8792 break;
8793 default:
8794 /* Case prevented by pipe_config_set_bpp. */
8795 BUG();
8796 }
8797
6e3c9717 8798 if (intel_crtc->config->dither)
756f85cf
PZ		 8799 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8800
8801 I915_WRITE(PIPEMISC(pipe), val);
8802 }
ee2b0b38
PZ		 8803}
8804
6591c6e4 8805static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8806 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8807 intel_clock_t *clock,
8808 bool *has_reduced_clock,
8809 intel_clock_t *reduced_clock)
8810{
8811 struct drm_device *dev = crtc->dev;
8812 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8813 int refclk;
d4906093 8814 const intel_limit_t *limit;
a16af721 8815 bool ret, is_lvds = false;
79e53945 8816
a93e255f 8817 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8818
55bb9992 8819 refclk = ironlake_get_refclk(crtc_state);
79e53945 8820
d4906093
ML		 8821 /*
8822 * Returns a set of divisors for the desired target clock with the given
8823 * refclk, or FALSE. The returned values represent the clock equation:
8824 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8825 */
a93e255f
ACO		 8826 limit = intel_limit(crtc_state, refclk);
8827 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8828 crtc_state->port_clock,
ee9300bb 8829 refclk, NULL, clock);
6591c6e4
PZ		 8830 if (!ret)
8831 return false;
cda4b7d3 8832
ddc9003c 8833 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8834 /*
8835 * Ensure we match the reduced clock's P to the target clock.
8836 * If the clocks don't match, we can't switch the display clock
8837 * by using the FP0/FP1. In such case we will disable the LVDS
8838 * downclock feature.
8839 */
ee9300bb 8840 *has_reduced_clock =
a93e255f 8841 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8842 dev_priv->lvds_downclock,
8843 refclk, clock,
8844 reduced_clock);
652c393a 8845 }
61e9653f 8846
6591c6e4
PZ		 8847 return true;
8848}
8849
d4b1931c
PZ		 8850int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8851{
8852 /*
8853 * Account for spread spectrum to avoid
8854 * oversubscribing the link. Max center spread
8855 * is 2.5%; use 5% for safety's sake.
8856 */
8857 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8858 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8859}
8860
7429e9d4 8861static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8862{
7429e9d4 8863 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8864}
8865
de13a2e3 8866static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8867 struct intel_crtc_state *crtc_state,
7429e9d4 8868 u32 *fp,
9a7c7890 8869 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8870{
de13a2e3 8871 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8872 struct drm_device *dev = crtc->dev;
8873 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8874 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8875 struct drm_connector *connector;
55bb9992
ACO		 8876 struct drm_connector_state *connector_state;
8877 struct intel_encoder *encoder;
de13a2e3 8878 uint32_t dpll;
55bb9992 8879 int factor, num_connectors = 0, i;
09ede541 8880 bool is_lvds = false, is_sdvo = false;
79e53945 8881
da3ced29 8882 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8883 if (connector_state->crtc != crtc_state->base.crtc)
8884 continue;
8885
8886 encoder = to_intel_encoder(connector_state->best_encoder);
8887
8888 switch (encoder->type) {
79e53945
JB		 8889 case INTEL_OUTPUT_LVDS:
8890 is_lvds = true;
8891 break;
8892 case INTEL_OUTPUT_SDVO:
7d57382e 8893 case INTEL_OUTPUT_HDMI:
79e53945 8894 is_sdvo = true;
79e53945 8895 break;
6847d71b
PZ		 8896 default:
8897 break;
79e53945 8898 }
43565a06 8899
c751ce4f 8900 num_connectors++;
79e53945 8901 }
79e53945 8902
c1858123 8903 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8904 factor = 21;
8905 if (is_lvds) {
8906 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8907 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8908 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8909 factor = 25;
190f68c5 8910 } else if (crtc_state->sdvo_tv_clock)
8febb297 8911 factor = 20;
c1858123 8912
190f68c5 8913 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8914 *fp |= FP_CB_TUNE;
2c07245f 8915
9a7c7890
DV		 8916 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8917 *fp2 |= FP_CB_TUNE;
8918
5eddb70b 8919 dpll = 0;
2c07245f 8920
a07d6787
EA		 8921 if (is_lvds)
8922 dpll |= DPLLB_MODE_LVDS;
8923 else
8924 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8925
190f68c5 8926 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8927 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8928
8929 if (is_sdvo)
4a33e48d 8930 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8931 if (crtc_state->has_dp_encoder)
4a33e48d 8932 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8933
a07d6787 8934 /* compute bitmask from p1 value */
190f68c5 8935 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8936 /* also FPA1 */
190f68c5 8937 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8938
190f68c5 8939 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8940 case 5:
8941 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8942 break;
8943 case 7:
8944 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8945 break;
8946 case 10:
8947 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8948 break;
8949 case 14:
8950 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8951 break;
79e53945
JB		 8952 }
8953
b4c09f3b 8954 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8955 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8956 else
8957 dpll |= PLL_REF_INPUT_DREFCLK;
8958
959e16d6 8959 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8960}
8961
190f68c5
ACO		 8962static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8963 struct intel_crtc_state *crtc_state)
de13a2e3 8964{
c7653199 8965 struct drm_device *dev = crtc->base.dev;
de13a2e3 8966 intel_clock_t clock, reduced_clock;
cbbab5bd 8967 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8968 bool ok, has_reduced_clock = false;
8b47047b 8969 bool is_lvds = false;
e2b78267 8970 struct intel_shared_dpll *pll;
de13a2e3 8971
dd3cd74a
ACO		 8972 memset(&crtc_state->dpll_hw_state, 0,
8973 sizeof(crtc_state->dpll_hw_state));
8974
409ee761 8975 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8976
5dc5298b
PZ		 8977 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8978 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8979
190f68c5 8980 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8981 &has_reduced_clock, &reduced_clock);
190f68c5 8982 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8983 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8984 return -EINVAL;
79e53945 8985 }
f47709a9 8986 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8987 if (!crtc_state->clock_set) {
8988 crtc_state->dpll.n = clock.n;
8989 crtc_state->dpll.m1 = clock.m1;
8990 crtc_state->dpll.m2 = clock.m2;
8991 crtc_state->dpll.p1 = clock.p1;
8992 crtc_state->dpll.p2 = clock.p2;
f47709a9 8993 }
79e53945 8994
5dc5298b 8995 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8996 if (crtc_state->has_pch_encoder) {
8997 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8998 if (has_reduced_clock)
7429e9d4 8999 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 9000
190f68c5 9001 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 9002 &fp, &reduced_clock,
9003 has_reduced_clock ? &fp2 : NULL);
9004
190f68c5
ACO		 9005 crtc_state->dpll_hw_state.dpll = dpll;
9006 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 9007 if (has_reduced_clock)
190f68c5 9008 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 9009 else
190f68c5 9010 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 9011
190f68c5 9012 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 9013 if (pll == NULL) {
84f44ce7 9014 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 9015 pipe_name(crtc->pipe));
4b645f14
JB		 9016 return -EINVAL;
9017 }
3fb37703 9018 }
79e53945 9019
ab585dea 9020 if (is_lvds && has_reduced_clock)
c7653199 9021 crtc->lowfreq_avail = true;
bcd644e0 9022 else
c7653199 9023 crtc->lowfreq_avail = false;
e2b78267 9024
c8f7a0db 9025 return 0;
79e53945
JB		 9026}
9027
eb14cb74
VS		 9028static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9029 struct intel_link_m_n *m_n)
9030{
9031 struct drm_device *dev = crtc->base.dev;
9032 struct drm_i915_private *dev_priv = dev->dev_private;
9033 enum pipe pipe = crtc->pipe;
9034
9035 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9036 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9037 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9038 & ~TU_SIZE_MASK;
9039 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9040 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9041 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9042}
9043
9044static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9045 enum transcoder transcoder,
b95af8be
VK		 9046 struct intel_link_m_n *m_n,
9047 struct intel_link_m_n *m2_n2)
72419203
DV		 9048{
9049 struct drm_device *dev = crtc->base.dev;
9050 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 9051 enum pipe pipe = crtc->pipe;
72419203 9052
eb14cb74
VS		 9053 if (INTEL_INFO(dev)->gen >= 5) {
9054 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9055 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9056 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9057 & ~TU_SIZE_MASK;
9058 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9059 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9060 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 9061 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9062 * gen < 8) and if DRRS is supported (to make sure the
9063 * registers are not unnecessarily read).
9064 */
9065 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 9066 crtc->config->has_drrs) {
b95af8be
VK		 9067 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9068 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9069 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9070 & ~TU_SIZE_MASK;
9071 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9072 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9073 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9074 }
eb14cb74
VS		 9075 } else {
9076 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9077 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9078 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9079 & ~TU_SIZE_MASK;
9080 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9081 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9082 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9083 }
9084}
9085
9086void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9087 struct intel_crtc_state *pipe_config)
eb14cb74 9088{
681a8504 9089 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9090 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9091 else
9092 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9093 &pipe_config->dp_m_n,
9094 &pipe_config->dp_m2_n2);
eb14cb74 9095}
72419203 9096
eb14cb74 9097static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9098 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9099{
9100 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9101 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9102}
9103
bd2e244f 9104static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9105 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9106{
9107 struct drm_device *dev = crtc->base.dev;
9108 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9109 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9110 uint32_t ps_ctrl = 0;
9111 int id = -1;
9112 int i;
bd2e244f 9113
a1b2278e
CK		 9114 /* find scaler attached to this pipe */
9115 for (i = 0; i < crtc->num_scalers; i++) {
9116 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9117 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9118 id = i;
9119 pipe_config->pch_pfit.enabled = true;
9120 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9121 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9122 break;
9123 }
9124 }
bd2e244f 9125
a1b2278e
CK		 9126 scaler_state->scaler_id = id;
9127 if (id >= 0) {
9128 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9129 } else {
9130 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9131 }
9132}
9133
5724dbd1
DL		 9134static void
9135skylake_get_initial_plane_config(struct intel_crtc *crtc,
9136 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9137{
9138 struct drm_device *dev = crtc->base.dev;
9139 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9140 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9141 int pipe = crtc->pipe;
9142 int fourcc, pixel_format;
6761dd31 9143 unsigned int aligned_height;
bc8d7dff 9144 struct drm_framebuffer *fb;
1b842c89 9145 struct intel_framebuffer *intel_fb;
bc8d7dff 9146
d9806c9f 9147 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9148 if (!intel_fb) {
bc8d7dff
DL		 9149 DRM_DEBUG_KMS("failed to alloc fb\n");
9150 return;
9151 }
9152
1b842c89
DL		 9153 fb = &intel_fb->base;
9154
bc8d7dff 9155 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9156 if (!(val & PLANE_CTL_ENABLE))
9157 goto error;
9158
bc8d7dff
DL		 9159 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9160 fourcc = skl_format_to_fourcc(pixel_format,
9161 val & PLANE_CTL_ORDER_RGBX,
9162 val & PLANE_CTL_ALPHA_MASK);
9163 fb->pixel_format = fourcc;
9164 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9165
40f46283
DL		 9166 tiling = val & PLANE_CTL_TILED_MASK;
9167 switch (tiling) {
9168 case PLANE_CTL_TILED_LINEAR:
9169 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9170 break;
9171 case PLANE_CTL_TILED_X:
9172 plane_config->tiling = I915_TILING_X;
9173 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9174 break;
9175 case PLANE_CTL_TILED_Y:
9176 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9177 break;
9178 case PLANE_CTL_TILED_YF:
9179 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9180 break;
9181 default:
9182 MISSING_CASE(tiling);
9183 goto error;
9184 }
9185
bc8d7dff
DL		 9186 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9187 plane_config->base = base;
9188
9189 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9190
9191 val = I915_READ(PLANE_SIZE(pipe, 0));
9192 fb->height = ((val >> 16) & 0xfff) + 1;
9193 fb->width = ((val >> 0) & 0x1fff) + 1;
9194
9195 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9196 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9197 fb->pixel_format);
bc8d7dff
DL		 9198 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9199
9200 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9201 fb->pixel_format,
9202 fb->modifier[0]);
bc8d7dff 9203
f37b5c2b 9204 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9205
9206 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9207 pipe_name(pipe), fb->width, fb->height,
9208 fb->bits_per_pixel, base, fb->pitches[0],
9209 plane_config->size);
9210
2d14030b 9211 plane_config->fb = intel_fb;
bc8d7dff
DL		 9212 return;
9213
9214error:
9215 kfree(fb);
9216}
9217
2fa2fe9a 9218static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9219 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9220{
9221 struct drm_device *dev = crtc->base.dev;
9222 struct drm_i915_private *dev_priv = dev->dev_private;
9223 uint32_t tmp;
9224
9225 tmp = I915_READ(PF_CTL(crtc->pipe));
9226
9227 if (tmp & PF_ENABLE) {
fd4daa9c 9228 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9229 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9230 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9231
9232 /* We currently do not free assignements of panel fitters on
9233 * ivb/hsw (since we don't use the higher upscaling modes which
9234 * differentiates them) so just WARN about this case for now. */
9235 if (IS_GEN7(dev)) {
9236 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9237 PF_PIPE_SEL_IVB(crtc->pipe));
9238 }
2fa2fe9a 9239 }
79e53945
JB		 9240}
9241
5724dbd1
DL		 9242static void
9243ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9244 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9245{
9246 struct drm_device *dev = crtc->base.dev;
9247 struct drm_i915_private *dev_priv = dev->dev_private;
9248 u32 val, base, offset;
aeee5a49 9249 int pipe = crtc->pipe;
4c6baa59 9250 int fourcc, pixel_format;
6761dd31 9251 unsigned int aligned_height;
b113d5ee 9252 struct drm_framebuffer *fb;
1b842c89 9253 struct intel_framebuffer *intel_fb;
4c6baa59 9254
42a7b088
DL		 9255 val = I915_READ(DSPCNTR(pipe));
9256 if (!(val & DISPLAY_PLANE_ENABLE))
9257 return;
9258
d9806c9f 9259 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9260 if (!intel_fb) {
4c6baa59
JB		 9261 DRM_DEBUG_KMS("failed to alloc fb\n");
9262 return;
9263 }
9264
1b842c89
DL		 9265 fb = &intel_fb->base;
9266
18c5247e
DV		 9267 if (INTEL_INFO(dev)->gen >= 4) {
9268 if (val & DISPPLANE_TILED) {
49af449b 9269 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9270 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9271 }
9272 }
4c6baa59
JB		 9273
9274 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9275 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9276 fb->pixel_format = fourcc;
9277 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9278
aeee5a49 9279 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9280 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9281 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9282 } else {
49af449b 9283 if (plane_config->tiling)
aeee5a49 9284 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9285 else
aeee5a49 9286 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9287 }
9288 plane_config->base = base;
9289
9290 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9291 fb->width = ((val >> 16) & 0xfff) + 1;
9292 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9293
9294 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9295 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9296
b113d5ee 9297 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9298 fb->pixel_format,
9299 fb->modifier[0]);
4c6baa59 9300
f37b5c2b 9301 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9302
2844a921
DL		 9303 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9304 pipe_name(pipe), fb->width, fb->height,
9305 fb->bits_per_pixel, base, fb->pitches[0],
9306 plane_config->size);
b113d5ee 9307
2d14030b 9308 plane_config->fb = intel_fb;
4c6baa59
JB		 9309}
9310
0e8ffe1b 9311static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9312 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9313{
9314 struct drm_device *dev = crtc->base.dev;
9315 struct drm_i915_private *dev_priv = dev->dev_private;
9316 uint32_t tmp;
9317
f458ebbc
DV		 9318 if (!intel_display_power_is_enabled(dev_priv,
9319 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9320 return false;
9321
e143a21c 9322 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9323 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9324
0e8ffe1b
DV		 9325 tmp = I915_READ(PIPECONF(crtc->pipe));
9326 if (!(tmp & PIPECONF_ENABLE))
9327 return false;
9328
42571aef
VS		 9329 switch (tmp & PIPECONF_BPC_MASK) {
9330 case PIPECONF_6BPC:
9331 pipe_config->pipe_bpp = 18;
9332 break;
9333 case PIPECONF_8BPC:
9334 pipe_config->pipe_bpp = 24;
9335 break;
9336 case PIPECONF_10BPC:
9337 pipe_config->pipe_bpp = 30;
9338 break;
9339 case PIPECONF_12BPC:
9340 pipe_config->pipe_bpp = 36;
9341 break;
9342 default:
9343 break;
9344 }
9345
b5a9fa09
DV		 9346 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9347 pipe_config->limited_color_range = true;
9348
ab9412ba 9349 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9350 struct intel_shared_dpll *pll;
9351
88adfff1
DV		 9352 pipe_config->has_pch_encoder = true;
9353
627eb5a3
DV		 9354 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9355 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9356 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9357
9358 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9359
c0d43d62 9360 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9361 pipe_config->shared_dpll =
9362 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9363 } else {
9364 tmp = I915_READ(PCH_DPLL_SEL);
9365 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9366 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9367 else
9368 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9369 }
66e985c0
DV		 9370
9371 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9372
9373 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9374 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9375
9376 tmp = pipe_config->dpll_hw_state.dpll;
9377 pipe_config->pixel_multiplier =
9378 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9379 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9380
9381 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9382 } else {
9383 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9384 }
9385
1bd1bd80
DV		 9386 intel_get_pipe_timings(crtc, pipe_config);
9387
2fa2fe9a
DV		 9388 ironlake_get_pfit_config(crtc, pipe_config);
9389
0e8ffe1b
DV		 9390 return true;
9391}
9392
be256dc7
PZ		 9393static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9394{
9395 struct drm_device *dev = dev_priv->dev;
be256dc7 9396 struct intel_crtc *crtc;
be256dc7 9397
d3fcc808 9398 for_each_intel_crtc(dev, crtc)
e2c719b7 9399 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9400 pipe_name(crtc->pipe));
9401
e2c719b7
RC		 9402 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9403 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9404 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9405 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9406 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9407 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9408 "CPU PWM1 enabled\n");
c5107b87 9409 if (IS_HASWELL(dev))
e2c719b7 9410 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9411 "CPU PWM2 enabled\n");
e2c719b7 9412 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9413 "PCH PWM1 enabled\n");
e2c719b7 9414 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9415 "Utility pin enabled\n");
e2c719b7 9416 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9417
9926ada1
PZ		 9418 /*
9419 * In theory we can still leave IRQs enabled, as long as only the HPD
9420 * interrupts remain enabled. We used to check for that, but since it's
9421 * gen-specific and since we only disable LCPLL after we fully disable
9422 * the interrupts, the check below should be enough.
9423 */
e2c719b7 9424 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9425}
9426
9ccd5aeb
PZ		 9427static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9428{
9429 struct drm_device *dev = dev_priv->dev;
9430
9431 if (IS_HASWELL(dev))
9432 return I915_READ(D_COMP_HSW);
9433 else
9434 return I915_READ(D_COMP_BDW);
9435}
9436
3c4c9b81
PZ		 9437static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9438{
9439 struct drm_device *dev = dev_priv->dev;
9440
9441 if (IS_HASWELL(dev)) {
9442 mutex_lock(&dev_priv->rps.hw_lock);
9443 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9444 val))
f475dadf 9445 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9446 mutex_unlock(&dev_priv->rps.hw_lock);
9447 } else {
9ccd5aeb
PZ		 9448 I915_WRITE(D_COMP_BDW, val);
9449 POSTING_READ(D_COMP_BDW);
3c4c9b81 9450 }
be256dc7
PZ		 9451}
9452
9453/*
9454 * This function implements pieces of two sequences from BSpec:
9455 * - Sequence for display software to disable LCPLL
9456 * - Sequence for display software to allow package C8+
9457 * The steps implemented here are just the steps that actually touch the LCPLL
9458 * register. Callers should take care of disabling all the display engine
9459 * functions, doing the mode unset, fixing interrupts, etc.
9460 */
6ff58d53
PZ		 9461static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9462 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9463{
9464 uint32_t val;
9465
9466 assert_can_disable_lcpll(dev_priv);
9467
9468 val = I915_READ(LCPLL_CTL);
9469
9470 if (switch_to_fclk) {
9471 val |= LCPLL_CD_SOURCE_FCLK;
9472 I915_WRITE(LCPLL_CTL, val);
9473
9474 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9475 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9476 DRM_ERROR("Switching to FCLK failed\n");
9477
9478 val = I915_READ(LCPLL_CTL);
9479 }
9480
9481 val |= LCPLL_PLL_DISABLE;
9482 I915_WRITE(LCPLL_CTL, val);
9483 POSTING_READ(LCPLL_CTL);
9484
9485 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9486 DRM_ERROR("LCPLL still locked\n");
9487
9ccd5aeb 9488 val = hsw_read_dcomp(dev_priv);
be256dc7 9489 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9490 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9491 ndelay(100);
9492
9ccd5aeb
PZ		 9493 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9494 1))
be256dc7
PZ		 9495 DRM_ERROR("D_COMP RCOMP still in progress\n");
9496
9497 if (allow_power_down) {
9498 val = I915_READ(LCPLL_CTL);
9499 val |= LCPLL_POWER_DOWN_ALLOW;
9500 I915_WRITE(LCPLL_CTL, val);
9501 POSTING_READ(LCPLL_CTL);
9502 }
9503}
9504
9505/*
9506 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9507 * source.
9508 */
6ff58d53 9509static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9510{
9511 uint32_t val;
9512
9513 val = I915_READ(LCPLL_CTL);
9514
9515 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9516 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9517 return;
9518
a8a8bd54
PZ		 9519 /*
9520 * Make sure we're not on PC8 state before disabling PC8, otherwise
9521 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9522 */
59bad947 9523 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9524
be256dc7
PZ		 9525 if (val & LCPLL_POWER_DOWN_ALLOW) {
9526 val &= ~LCPLL_POWER_DOWN_ALLOW;
9527 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9528 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9529 }
9530
9ccd5aeb 9531 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9532 val |= D_COMP_COMP_FORCE;
9533 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9534 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9535
9536 val = I915_READ(LCPLL_CTL);
9537 val &= ~LCPLL_PLL_DISABLE;
9538 I915_WRITE(LCPLL_CTL, val);
9539
9540 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9541 DRM_ERROR("LCPLL not locked yet\n");
9542
9543 if (val & LCPLL_CD_SOURCE_FCLK) {
9544 val = I915_READ(LCPLL_CTL);
9545 val &= ~LCPLL_CD_SOURCE_FCLK;
9546 I915_WRITE(LCPLL_CTL, val);
9547
9548 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9549 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9550 DRM_ERROR("Switching back to LCPLL failed\n");
9551 }
215733fa 9552
59bad947 9553 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9554 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9555}
9556
765dab67
PZ		 9557/*
9558 * Package states C8 and deeper are really deep PC states that can only be
9559 * reached when all the devices on the system allow it, so even if the graphics
9560 * device allows PC8+, it doesn't mean the system will actually get to these
9561 * states. Our driver only allows PC8+ when going into runtime PM.
9562 *
9563 * The requirements for PC8+ are that all the outputs are disabled, the power
9564 * well is disabled and most interrupts are disabled, and these are also
9565 * requirements for runtime PM. When these conditions are met, we manually do
9566 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9567 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9568 * hang the machine.
9569 *
9570 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9571 * the state of some registers, so when we come back from PC8+ we need to
9572 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9573 * need to take care of the registers kept by RC6. Notice that this happens even
9574 * if we don't put the device in PCI D3 state (which is what currently happens
9575 * because of the runtime PM support).
9576 *
9577 * For more, read "Display Sequences for Package C8" on the hardware
9578 * documentation.
9579 */
a14cb6fc 9580void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9581{
c67a470b
PZ		 9582 struct drm_device *dev = dev_priv->dev;
9583 uint32_t val;
9584
c67a470b
PZ		 9585 DRM_DEBUG_KMS("Enabling package C8+\n");
9586
c67a470b
PZ		 9587 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9588 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9589 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9590 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9591 }
9592
9593 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9594 hsw_disable_lcpll(dev_priv, true, true);
9595}
9596
a14cb6fc 9597void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9598{
9599 struct drm_device *dev = dev_priv->dev;
9600 uint32_t val;
9601
c67a470b
PZ		 9602 DRM_DEBUG_KMS("Disabling package C8+\n");
9603
9604 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9605 lpt_init_pch_refclk(dev);
9606
9607 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9608 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9609 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9610 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9611 }
9612
9613 intel_prepare_ddi(dev);
c67a470b
PZ		 9614}
9615
a821fc46 9616static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9617{
a821fc46 9618 struct drm_device *dev = old_state->dev;
f8437dd1 9619 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9620 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9621 int req_cdclk;
9622
9623 /* see the comment in valleyview_modeset_global_resources */
9624 if (WARN_ON(max_pixclk < 0))
9625 return;
9626
9627 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9628
9629 if (req_cdclk != dev_priv->cdclk_freq)
9630 broxton_set_cdclk(dev, req_cdclk);
9631}
9632
b432e5cf
VS		 9633/* compute the max rate for new configuration */
9634static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9635{
9636 struct drm_device *dev = dev_priv->dev;
9637 struct intel_crtc *intel_crtc;
9638 struct drm_crtc *crtc;
9639 int max_pixel_rate = 0;
9640 int pixel_rate;
9641
9642 for_each_crtc(dev, crtc) {
9643 if (!crtc->state->enable)
9644 continue;
9645
9646 intel_crtc = to_intel_crtc(crtc);
9647 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9648
9649 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9650 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9651 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9652
9653 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9654 }
9655
9656 return max_pixel_rate;
9657}
9658
9659static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9660{
9661 struct drm_i915_private *dev_priv = dev->dev_private;
9662 uint32_t val, data;
9663 int ret;
9664
9665 if (WARN((I915_READ(LCPLL_CTL) &
9666 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9667 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9668 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9669 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9670 "trying to change cdclk frequency with cdclk not enabled\n"))
9671 return;
9672
9673 mutex_lock(&dev_priv->rps.hw_lock);
9674 ret = sandybridge_pcode_write(dev_priv,
9675 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9676 mutex_unlock(&dev_priv->rps.hw_lock);
9677 if (ret) {
9678 DRM_ERROR("failed to inform pcode about cdclk change\n");
9679 return;
9680 }
9681
9682 val = I915_READ(LCPLL_CTL);
9683 val |= LCPLL_CD_SOURCE_FCLK;
9684 I915_WRITE(LCPLL_CTL, val);
9685
9686 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9687 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9688 DRM_ERROR("Switching to FCLK failed\n");
9689
9690 val = I915_READ(LCPLL_CTL);
9691 val &= ~LCPLL_CLK_FREQ_MASK;
9692
9693 switch (cdclk) {
9694 case 450000:
9695 val |= LCPLL_CLK_FREQ_450;
9696 data = 0;
9697 break;
9698 case 540000:
9699 val |= LCPLL_CLK_FREQ_54O_BDW;
9700 data = 1;
9701 break;
9702 case 337500:
9703 val |= LCPLL_CLK_FREQ_337_5_BDW;
9704 data = 2;
9705 break;
9706 case 675000:
9707 val |= LCPLL_CLK_FREQ_675_BDW;
9708 data = 3;
9709 break;
9710 default:
9711 WARN(1, "invalid cdclk frequency\n");
9712 return;
9713 }
9714
9715 I915_WRITE(LCPLL_CTL, val);
9716
9717 val = I915_READ(LCPLL_CTL);
9718 val &= ~LCPLL_CD_SOURCE_FCLK;
9719 I915_WRITE(LCPLL_CTL, val);
9720
9721 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9722 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9723 DRM_ERROR("Switching back to LCPLL failed\n");
9724
9725 mutex_lock(&dev_priv->rps.hw_lock);
9726 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9727 mutex_unlock(&dev_priv->rps.hw_lock);
9728
9729 intel_update_cdclk(dev);
9730
9731 WARN(cdclk != dev_priv->cdclk_freq,
9732 "cdclk requested %d kHz but got %d kHz\n",
9733 cdclk, dev_priv->cdclk_freq);
9734}
9735
9736static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9737 int max_pixel_rate)
9738{
9739 int cdclk;
9740
9741 /*
9742 * FIXME should also account for plane ratio
9743 * once 64bpp pixel formats are supported.
9744 */
9745 if (max_pixel_rate > 540000)
9746 cdclk = 675000;
9747 else if (max_pixel_rate > 450000)
9748 cdclk = 540000;
9749 else if (max_pixel_rate > 337500)
9750 cdclk = 450000;
9751 else
9752 cdclk = 337500;
9753
9754 /*
9755 * FIXME move the cdclk caclulation to
9756 * compute_config() so we can fail gracegully.
9757 */
9758 if (cdclk > dev_priv->max_cdclk_freq) {
9759 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9760 cdclk, dev_priv->max_cdclk_freq);
9761 cdclk = dev_priv->max_cdclk_freq;
9762 }
9763
9764 return cdclk;
9765}
9766
9767static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9768{
9769 struct drm_i915_private *dev_priv = to_i915(state->dev);
9770 struct drm_crtc *crtc;
9771 struct drm_crtc_state *crtc_state;
9772 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9773 int cdclk, i;
9774
9775 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9776
9777 if (cdclk == dev_priv->cdclk_freq)
9778 return 0;
9779
9780 /* add all active pipes to the state */
9781 for_each_crtc(state->dev, crtc) {
9782 if (!crtc->state->enable)
9783 continue;
9784
9785 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9786 if (IS_ERR(crtc_state))
9787 return PTR_ERR(crtc_state);
9788 }
9789
9790 /* disable/enable all currently active pipes while we change cdclk */
9791 for_each_crtc_in_state(state, crtc, crtc_state, i)
9792 if (crtc_state->enable)
9793 crtc_state->mode_changed = true;
9794
9795 return 0;
9796}
9797
9798static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9799{
9800 struct drm_device *dev = state->dev;
9801 struct drm_i915_private *dev_priv = dev->dev_private;
9802 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9803 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9804
9805 if (req_cdclk != dev_priv->cdclk_freq)
9806 broadwell_set_cdclk(dev, req_cdclk);
9807}
9808
190f68c5
ACO		 9809static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9810 struct intel_crtc_state *crtc_state)
09b4ddf9 9811{
190f68c5 9812 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9813 return -EINVAL;
716c2e55 9814
c7653199 9815 crtc->lowfreq_avail = false;
644cef34 9816
c8f7a0db 9817 return 0;
79e53945
JB		 9818}
9819
3760b59c
S		 9820static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9821 enum port port,
9822 struct intel_crtc_state *pipe_config)
9823{
9824 switch (port) {
9825 case PORT_A:
9826 pipe_config->ddi_pll_sel = SKL_DPLL0;
9827 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9828 break;
9829 case PORT_B:
9830 pipe_config->ddi_pll_sel = SKL_DPLL1;
9831 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9832 break;
9833 case PORT_C:
9834 pipe_config->ddi_pll_sel = SKL_DPLL2;
9835 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9836 break;
9837 default:
9838 DRM_ERROR("Incorrect port type\n");
9839 }
9840}
9841
96b7dfb7
S		 9842static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9843 enum port port,
5cec258b 9844 struct intel_crtc_state *pipe_config)
96b7dfb7 9845{
3148ade7 9846 u32 temp, dpll_ctl1;
96b7dfb7
S		 9847
9848 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9849 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9850
9851 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9852 case SKL_DPLL0:
9853 /*
9854 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9855 * of the shared DPLL framework and thus needs to be read out
9856 * separately
9857 */
9858 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9859 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9860 break;
96b7dfb7
S		 9861 case SKL_DPLL1:
9862 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9863 break;
9864 case SKL_DPLL2:
9865 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9866 break;
9867 case SKL_DPLL3:
9868 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9869 break;
96b7dfb7
S		 9870 }
9871}
9872
7d2c8175
DL		 9873static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9874 enum port port,
5cec258b 9875 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9876{
9877 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9878
9879 switch (pipe_config->ddi_pll_sel) {
9880 case PORT_CLK_SEL_WRPLL1:
9881 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9882 break;
9883 case PORT_CLK_SEL_WRPLL2:
9884 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9885 break;
9886 }
9887}
9888
26804afd 9889static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9890 struct intel_crtc_state *pipe_config)
26804afd
DV		 9891{
9892 struct drm_device *dev = crtc->base.dev;
9893 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9894 struct intel_shared_dpll *pll;
26804afd
DV		 9895 enum port port;
9896 uint32_t tmp;
9897
9898 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9899
9900 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9901
96b7dfb7
S		 9902 if (IS_SKYLAKE(dev))
9903 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9904 else if (IS_BROXTON(dev))
9905 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9906 else
9907 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9908
d452c5b6
DV		 9909 if (pipe_config->shared_dpll >= 0) {
9910 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9911
9912 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9913 &pipe_config->dpll_hw_state));
9914 }
9915
26804afd
DV		 9916 /*
9917 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9918 * DDI E. So just check whether this pipe is wired to DDI E and whether
9919 * the PCH transcoder is on.
9920 */
ca370455
DL		 9921 if (INTEL_INFO(dev)->gen < 9 &&
9922 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9923 pipe_config->has_pch_encoder = true;
9924
9925 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9926 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9927 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9928
9929 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9930 }
9931}
9932
0e8ffe1b 9933static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9934 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9935{
9936 struct drm_device *dev = crtc->base.dev;
9937 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9938 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9939 uint32_t tmp;
9940
f458ebbc 9941 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9942 POWER_DOMAIN_PIPE(crtc->pipe)))
9943 return false;
9944
e143a21c 9945 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9946 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9947
eccb140b
DV		 9948 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9949 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9950 enum pipe trans_edp_pipe;
9951 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9952 default:
9953 WARN(1, "unknown pipe linked to edp transcoder\n");
9954 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9955 case TRANS_DDI_EDP_INPUT_A_ON:
9956 trans_edp_pipe = PIPE_A;
9957 break;
9958 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9959 trans_edp_pipe = PIPE_B;
9960 break;
9961 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9962 trans_edp_pipe = PIPE_C;
9963 break;
9964 }
9965
9966 if (trans_edp_pipe == crtc->pipe)
9967 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9968 }
9969
f458ebbc 9970 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9971 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9972 return false;
9973
eccb140b 9974 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9975 if (!(tmp & PIPECONF_ENABLE))
9976 return false;
9977
26804afd 9978 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9979
1bd1bd80
DV		 9980 intel_get_pipe_timings(crtc, pipe_config);
9981
a1b2278e
CK		 9982 if (INTEL_INFO(dev)->gen >= 9) {
9983 skl_init_scalers(dev, crtc, pipe_config);
9984 }
9985
2fa2fe9a 9986 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9987
9988 if (INTEL_INFO(dev)->gen >= 9) {
9989 pipe_config->scaler_state.scaler_id = -1;
9990 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9991 }
9992
bd2e244f 9993 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9994 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9995 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9996 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9997 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9998 else
9999 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 10000 }
88adfff1 10001
e59150dc
JB		 10002 if (IS_HASWELL(dev))
10003 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10004 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 10005
ebb69c95
CT		 10006 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10007 pipe_config->pixel_multiplier =
10008 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10009 } else {
10010 pipe_config->pixel_multiplier = 1;
10011 }
6c49f241 10012
0e8ffe1b
DV		 10013 return true;
10014}
10015
560b85bb
CW		 10016static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
10017{
10018 struct drm_device *dev = crtc->dev;
10019 struct drm_i915_private *dev_priv = dev->dev_private;
10020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 10021 uint32_t cntl = 0, size = 0;
560b85bb 10022
dc41c154 10023 if (base) {
3dd512fb
MR		 10024 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
10025 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 10026 unsigned int stride = roundup_pow_of_two(width) * 4;
10027
10028 switch (stride) {
10029 default:
10030 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10031 width, stride);
10032 stride = 256;
10033 /* fallthrough */
10034 case 256:
10035 case 512:
10036 case 1024:
10037 case 2048:
10038 break;
4b0e333e
CW		 10039 }
10040
dc41c154
VS		 10041 cntl |= CURSOR_ENABLE |
10042 CURSOR_GAMMA_ENABLE |
10043 CURSOR_FORMAT_ARGB |
10044 CURSOR_STRIDE(stride);
10045
10046 size = (height << 12) | width;
4b0e333e 10047 }
560b85bb 10048
dc41c154
VS		 10049 if (intel_crtc->cursor_cntl != 0 &&
10050 (intel_crtc->cursor_base != base ||
10051 intel_crtc->cursor_size != size ||
10052 intel_crtc->cursor_cntl != cntl)) {
10053 /* On these chipsets we can only modify the base/size/stride
10054 * whilst the cursor is disabled.
10055 */
10056 I915_WRITE(_CURACNTR, 0);
4b0e333e 10057 POSTING_READ(_CURACNTR);
dc41c154 10058 intel_crtc->cursor_cntl = 0;
4b0e333e 10059 }
560b85bb 10060
99d1f387 10061 if (intel_crtc->cursor_base != base) {
9db4a9c7 10062 I915_WRITE(_CURABASE, base);
99d1f387
VS		 10063 intel_crtc->cursor_base = base;
10064 }
4726e0b0 10065
dc41c154
VS		 10066 if (intel_crtc->cursor_size != size) {
10067 I915_WRITE(CURSIZE, size);
10068 intel_crtc->cursor_size = size;
4b0e333e 10069 }
560b85bb 10070
4b0e333e 10071 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 10072 I915_WRITE(_CURACNTR, cntl);
10073 POSTING_READ(_CURACNTR);
4b0e333e 10074 intel_crtc->cursor_cntl = cntl;
560b85bb 10075 }
560b85bb
CW		 10076}
10077
560b85bb 10078static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 10079{
10080 struct drm_device *dev = crtc->dev;
10081 struct drm_i915_private *dev_priv = dev->dev_private;
10082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10083 int pipe = intel_crtc->pipe;
4b0e333e
CW		 10084 uint32_t cntl;
10085
10086 cntl = 0;
10087 if (base) {
10088 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 10089 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 10090 case 64:
10091 cntl |= CURSOR_MODE_64_ARGB_AX;
10092 break;
10093 case 128:
10094 cntl |= CURSOR_MODE_128_ARGB_AX;
10095 break;
10096 case 256:
10097 cntl |= CURSOR_MODE_256_ARGB_AX;
10098 break;
10099 default:
3dd512fb 10100 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 10101 return;
65a21cd6 10102 }
4b0e333e 10103 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 10104
10105 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10106 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 10107 }
65a21cd6 10108
8e7d688b 10109 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 10110 cntl |= CURSOR_ROTATE_180;
10111
4b0e333e
CW		 10112 if (intel_crtc->cursor_cntl != cntl) {
10113 I915_WRITE(CURCNTR(pipe), cntl);
10114 POSTING_READ(CURCNTR(pipe));
10115 intel_crtc->cursor_cntl = cntl;
65a21cd6 10116 }
4b0e333e 10117
65a21cd6 10118 /* and commit changes on next vblank */
5efb3e28
VS		 10119 I915_WRITE(CURBASE(pipe), base);
10120 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 10121
10122 intel_crtc->cursor_base = base;
65a21cd6
JB		 10123}
10124
cda4b7d3 10125/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 10126static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10127 bool on)
cda4b7d3
CW		 10128{
10129 struct drm_device *dev = crtc->dev;
10130 struct drm_i915_private *dev_priv = dev->dev_private;
10131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10132 int pipe = intel_crtc->pipe;
3d7d6510
MR		 10133 int x = crtc->cursor_x;
10134 int y = crtc->cursor_y;
d6e4db15 10135 u32 base = 0, pos = 0;
cda4b7d3 10136
d6e4db15 10137 if (on)
cda4b7d3 10138 base = intel_crtc->cursor_addr;
cda4b7d3 10139
6e3c9717 10140 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 10141 base = 0;
10142
6e3c9717 10143 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 10144 base = 0;
10145
10146 if (x < 0) {
3dd512fb 10147 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 10148 base = 0;
10149
10150 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10151 x = -x;
10152 }
10153 pos |= x << CURSOR_X_SHIFT;
10154
10155 if (y < 0) {
3dd512fb 10156 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 10157 base = 0;
10158
10159 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10160 y = -y;
10161 }
10162 pos |= y << CURSOR_Y_SHIFT;
10163
4b0e333e 10164 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10165 return;
10166
5efb3e28
VS		 10167 I915_WRITE(CURPOS(pipe), pos);
10168
4398ad45
VS		 10169 /* ILK+ do this automagically */
10170 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10171 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 10172 base += (intel_crtc->base.cursor->state->crtc_h *
10173 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 10174 }
10175
8ac54669 10176 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10177 i845_update_cursor(crtc, base);
10178 else
10179 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10180}
10181
dc41c154
VS		 10182static bool cursor_size_ok(struct drm_device *dev,
10183 uint32_t width, uint32_t height)
10184{
10185 if (width == 0 || height == 0)
10186 return false;
10187
10188 /*
10189 * 845g/865g are special in that they are only limited by
10190 * the width of their cursors, the height is arbitrary up to
10191 * the precision of the register. Everything else requires
10192 * square cursors, limited to a few power-of-two sizes.
10193 */
10194 if (IS_845G(dev) || IS_I865G(dev)) {
10195 if ((width & 63) != 0)
10196 return false;
10197
10198 if (width > (IS_845G(dev) ? 64 : 512))
10199 return false;
10200
10201 if (height > 1023)
10202 return false;
10203 } else {
10204 switch (width | height) {
10205 case 256:
10206 case 128:
10207 if (IS_GEN2(dev))
10208 return false;
10209 case 64:
10210 break;
10211 default:
10212 return false;
10213 }
10214 }
10215
10216 return true;
10217}
10218
79e53945 10219static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10220 u16 *blue, uint32_t start, uint32_t size)
79e53945 10221{
7203425a 10222 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10224
7203425a 10225 for (i = start; i < end; i++) {
79e53945
JB		 10226 intel_crtc->lut_r[i] = red[i] >> 8;
10227 intel_crtc->lut_g[i] = green[i] >> 8;
10228 intel_crtc->lut_b[i] = blue[i] >> 8;
10229 }
10230
10231 intel_crtc_load_lut(crtc);
10232}
10233
79e53945
JB		 10234/* VESA 640x480x72Hz mode to set on the pipe */
10235static struct drm_display_mode load_detect_mode = {
10236 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10237 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10238};
10239
a8bb6818
DV		 10240struct drm_framebuffer *
10241__intel_framebuffer_create(struct drm_device *dev,
10242 struct drm_mode_fb_cmd2 *mode_cmd,
10243 struct drm_i915_gem_object *obj)
d2dff872
CW		 10244{
10245 struct intel_framebuffer *intel_fb;
10246 int ret;
10247
10248 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10249 if (!intel_fb) {
6ccb81f2 10250 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10251 return ERR_PTR(-ENOMEM);
10252 }
10253
10254 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10255 if (ret)
10256 goto err;
d2dff872
CW		 10257
10258 return &intel_fb->base;
dd4916c5 10259err:
6ccb81f2 10260 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10261 kfree(intel_fb);
10262
10263 return ERR_PTR(ret);
d2dff872
CW		 10264}
10265
b5ea642a 10266static struct drm_framebuffer *
a8bb6818
DV		 10267intel_framebuffer_create(struct drm_device *dev,
10268 struct drm_mode_fb_cmd2 *mode_cmd,
10269 struct drm_i915_gem_object *obj)
10270{
10271 struct drm_framebuffer *fb;
10272 int ret;
10273
10274 ret = i915_mutex_lock_interruptible(dev);
10275 if (ret)
10276 return ERR_PTR(ret);
10277 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10278 mutex_unlock(&dev->struct_mutex);
10279
10280 return fb;
10281}
10282
d2dff872
CW		 10283static u32
10284intel_framebuffer_pitch_for_width(int width, int bpp)
10285{
10286 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10287 return ALIGN(pitch, 64);
10288}
10289
10290static u32
10291intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10292{
10293 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10294 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10295}
10296
10297static struct drm_framebuffer *
10298intel_framebuffer_create_for_mode(struct drm_device *dev,
10299 struct drm_display_mode *mode,
10300 int depth, int bpp)
10301{
10302 struct drm_i915_gem_object *obj;
0fed39bd 10303 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10304
10305 obj = i915_gem_alloc_object(dev,
10306 intel_framebuffer_size_for_mode(mode, bpp));
10307 if (obj == NULL)
10308 return ERR_PTR(-ENOMEM);
10309
10310 mode_cmd.width = mode->hdisplay;
10311 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10312 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10313 bpp);
5ca0c34a 10314 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10315
10316 return intel_framebuffer_create(dev, &mode_cmd, obj);
10317}
10318
10319static struct drm_framebuffer *
10320mode_fits_in_fbdev(struct drm_device *dev,
10321 struct drm_display_mode *mode)
10322{
4520f53a 10323#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10324 struct drm_i915_private *dev_priv = dev->dev_private;
10325 struct drm_i915_gem_object *obj;
10326 struct drm_framebuffer *fb;
10327
4c0e5528 10328 if (!dev_priv->fbdev)
d2dff872
CW		 10329 return NULL;
10330
4c0e5528 10331 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10332 return NULL;
10333
4c0e5528
DV		 10334 obj = dev_priv->fbdev->fb->obj;
10335 BUG_ON(!obj);
10336
8bcd4553 10337 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10338 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10339 fb->bits_per_pixel))
d2dff872
CW		 10340 return NULL;
10341
01f2c773 10342 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10343 return NULL;
10344
10345 return fb;
4520f53a
DV		 10346#else
10347 return NULL;
10348#endif
d2dff872
CW		 10349}
10350
d3a40d1b
ACO		 10351static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10352 struct drm_crtc *crtc,
10353 struct drm_display_mode *mode,
10354 struct drm_framebuffer *fb,
10355 int x, int y)
10356{
10357 struct drm_plane_state *plane_state;
10358 int hdisplay, vdisplay;
10359 int ret;
10360
10361 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10362 if (IS_ERR(plane_state))
10363 return PTR_ERR(plane_state);
10364
10365 if (mode)
10366 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10367 else
10368 hdisplay = vdisplay = 0;
10369
10370 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10371 if (ret)
10372 return ret;
10373 drm_atomic_set_fb_for_plane(plane_state, fb);
10374 plane_state->crtc_x = 0;
10375 plane_state->crtc_y = 0;
10376 plane_state->crtc_w = hdisplay;
10377 plane_state->crtc_h = vdisplay;
10378 plane_state->src_x = x << 16;
10379 plane_state->src_y = y << 16;
10380 plane_state->src_w = hdisplay << 16;
10381 plane_state->src_h = vdisplay << 16;
10382
10383 return 0;
10384}
10385
d2434ab7 10386bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10387 struct drm_display_mode *mode,
51fd371b
RC		 10388 struct intel_load_detect_pipe *old,
10389 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10390{
10391 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10392 struct intel_encoder *intel_encoder =
10393 intel_attached_encoder(connector);
79e53945 10394 struct drm_crtc *possible_crtc;
4ef69c7a 10395 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10396 struct drm_crtc *crtc = NULL;
10397 struct drm_device *dev = encoder->dev;
94352cf9 10398 struct drm_framebuffer *fb;
51fd371b 10399 struct drm_mode_config *config = &dev->mode_config;
83a57153 10400 struct drm_atomic_state *state = NULL;
944b0c76 10401 struct drm_connector_state *connector_state;
4be07317 10402 struct intel_crtc_state *crtc_state;
51fd371b 10403 int ret, i = -1;
79e53945 10404
d2dff872 10405 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10406 connector->base.id, connector->name,
8e329a03 10407 encoder->base.id, encoder->name);
d2dff872 10408
51fd371b
RC		 10409retry:
10410 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10411 if (ret)
10412 goto fail_unlock;
6e9f798d 10413
79e53945
JB		 10414 /*
10415 * Algorithm gets a little messy:
7a5e4805 10416 *
79e53945
JB		 10417 * - if the connector already has an assigned crtc, use it (but make
10418 * sure it's on first)
7a5e4805 10419 *
79e53945
JB		 10420 * - try to find the first unused crtc that can drive this connector,
10421 * and use that if we find one
79e53945
JB		 10422 */
10423
10424 /* See if we already have a CRTC for this connector */
10425 if (encoder->crtc) {
10426 crtc = encoder->crtc;
8261b191 10427
51fd371b 10428 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10429 if (ret)
10430 goto fail_unlock;
10431 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10432 if (ret)
10433 goto fail_unlock;
7b24056b 10434
24218aac 10435 old->dpms_mode = connector->dpms;
8261b191
CW		 10436 old->load_detect_temp = false;
10437
10438 /* Make sure the crtc and connector are running */
24218aac
DV		 10439 if (connector->dpms != DRM_MODE_DPMS_ON)
10440 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10441
7173188d 10442 return true;
79e53945
JB		 10443 }
10444
10445 /* Find an unused one (if possible) */
70e1e0ec 10446 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10447 i++;
10448 if (!(encoder->possible_crtcs & (1 << i)))
10449 continue;
83d65738 10450 if (possible_crtc->state->enable)
a459249c
VS		 10451 continue;
10452 /* This can occur when applying the pipe A quirk on resume. */
10453 if (to_intel_crtc(possible_crtc)->new_enabled)
10454 continue;
10455
10456 crtc = possible_crtc;
10457 break;
79e53945
JB		 10458 }
10459
10460 /*
10461 * If we didn't find an unused CRTC, don't use any.
10462 */
10463 if (!crtc) {
7173188d 10464 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10465 goto fail_unlock;
79e53945
JB		 10466 }
10467
51fd371b
RC		 10468 ret = drm_modeset_lock(&crtc->mutex, ctx);
10469 if (ret)
4d02e2de
DV		 10470 goto fail_unlock;
10471 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10472 if (ret)
51fd371b 10473 goto fail_unlock;
fc303101
DV		 10474 intel_encoder->new_crtc = to_intel_crtc(crtc);
10475 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10476
10477 intel_crtc = to_intel_crtc(crtc);
412b61d8 10478 intel_crtc->new_enabled = true;
24218aac 10479 old->dpms_mode = connector->dpms;
8261b191 10480 old->load_detect_temp = true;
d2dff872 10481 old->release_fb = NULL;
79e53945 10482
83a57153
ACO		 10483 state = drm_atomic_state_alloc(dev);
10484 if (!state)
10485 return false;
10486
10487 state->acquire_ctx = ctx;
10488
944b0c76
ACO		 10489 connector_state = drm_atomic_get_connector_state(state, connector);
10490 if (IS_ERR(connector_state)) {
10491 ret = PTR_ERR(connector_state);
10492 goto fail;
10493 }
10494
10495 connector_state->crtc = crtc;
10496 connector_state->best_encoder = &intel_encoder->base;
10497
4be07317
ACO		 10498 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10499 if (IS_ERR(crtc_state)) {
10500 ret = PTR_ERR(crtc_state);
10501 goto fail;
10502 }
10503
49d6fa21 10504 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10505
6492711d
CW		 10506 if (!mode)
10507 mode = &load_detect_mode;
79e53945 10508
d2dff872
CW		 10509 /* We need a framebuffer large enough to accommodate all accesses
10510 * that the plane may generate whilst we perform load detection.
10511 * We can not rely on the fbcon either being present (we get called
10512 * during its initialisation to detect all boot displays, or it may
10513 * not even exist) or that it is large enough to satisfy the
10514 * requested mode.
10515 */
94352cf9
DV		 10516 fb = mode_fits_in_fbdev(dev, mode);
10517 if (fb == NULL) {
d2dff872 10518 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10519 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10520 old->release_fb = fb;
d2dff872
CW		 10521 } else
10522 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10523 if (IS_ERR(fb)) {
d2dff872 10524 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10525 goto fail;
79e53945 10526 }
79e53945 10527
d3a40d1b
ACO		 10528 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10529 if (ret)
10530 goto fail;
10531
8c7b5ccb
ACO		 10532 drm_mode_copy(&crtc_state->base.mode, mode);
10533
10534 if (intel_set_mode(crtc, state)) {
6492711d 10535 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10536 if (old->release_fb)
10537 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10538 goto fail;
79e53945 10539 }
9128b040 10540 crtc->primary->crtc = crtc;
7173188d 10541
79e53945 10542 /* let the connector get through one full cycle before testing */
9d0498a2 10543 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10544 return true;
412b61d8
VS		 10545
10546 fail:
83d65738 10547 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10548fail_unlock:
e5d958ef
ACO		 10549 drm_atomic_state_free(state);
10550 state = NULL;
83a57153 10551
51fd371b
RC		 10552 if (ret == -EDEADLK) {
10553 drm_modeset_backoff(ctx);
10554 goto retry;
10555 }
10556
412b61d8 10557 return false;
79e53945
JB		 10558}
10559
d2434ab7 10560void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10561 struct intel_load_detect_pipe *old,
10562 struct drm_modeset_acquire_ctx *ctx)
79e53945 10563{
83a57153 10564 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10565 struct intel_encoder *intel_encoder =
10566 intel_attached_encoder(connector);
4ef69c7a 10567 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10568 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10570 struct drm_atomic_state *state;
944b0c76 10571 struct drm_connector_state *connector_state;
4be07317 10572 struct intel_crtc_state *crtc_state;
d3a40d1b 10573 int ret;
79e53945 10574
d2dff872 10575 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10576 connector->base.id, connector->name,
8e329a03 10577 encoder->base.id, encoder->name);
d2dff872 10578
8261b191 10579 if (old->load_detect_temp) {
83a57153 10580 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10581 if (!state)
10582 goto fail;
83a57153
ACO		 10583
10584 state->acquire_ctx = ctx;
10585
944b0c76
ACO		 10586 connector_state = drm_atomic_get_connector_state(state, connector);
10587 if (IS_ERR(connector_state))
10588 goto fail;
10589
4be07317
ACO		 10590 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10591 if (IS_ERR(crtc_state))
10592 goto fail;
10593
fc303101
DV		 10594 to_intel_connector(connector)->new_encoder = NULL;
10595 intel_encoder->new_crtc = NULL;
412b61d8 10596 intel_crtc->new_enabled = false;
944b0c76
ACO		 10597
10598 connector_state->best_encoder = NULL;
10599 connector_state->crtc = NULL;
10600
49d6fa21 10601 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10602
d3a40d1b
ACO		 10603 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10604 0, 0);
10605 if (ret)
10606 goto fail;
10607
2bfb4627
ACO		 10608 ret = intel_set_mode(crtc, state);
10609 if (ret)
10610 goto fail;
d2dff872 10611
36206361
DV		 10612 if (old->release_fb) {
10613 drm_framebuffer_unregister_private(old->release_fb);
10614 drm_framebuffer_unreference(old->release_fb);
10615 }
d2dff872 10616
0622a53c 10617 return;
79e53945
JB		 10618 }
10619
c751ce4f 10620 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10621 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10622 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10623
10624 return;
10625fail:
10626 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10627 drm_atomic_state_free(state);
79e53945
JB		 10628}
10629
da4a1efa 10630static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10631 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10632{
10633 struct drm_i915_private *dev_priv = dev->dev_private;
10634 u32 dpll = pipe_config->dpll_hw_state.dpll;
10635
10636 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10637 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10638 else if (HAS_PCH_SPLIT(dev))
10639 return 120000;
10640 else if (!IS_GEN2(dev))
10641 return 96000;
10642 else
10643 return 48000;
10644}
10645
79e53945 10646/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10647static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10648 struct intel_crtc_state *pipe_config)
79e53945 10649{
f1f644dc 10650 struct drm_device *dev = crtc->base.dev;
79e53945 10651 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10652 int pipe = pipe_config->cpu_transcoder;
293623f7 10653 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10654 u32 fp;
10655 intel_clock_t clock;
da4a1efa 10656 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10657
10658 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10659 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10660 else
293623f7 10661 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10662
10663 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10664 if (IS_PINEVIEW(dev)) {
10665 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10666 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10667 } else {
10668 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10669 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10670 }
10671
a6c45cf0 10672 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10673 if (IS_PINEVIEW(dev))
10674 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10675 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10676 else
10677 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10678 DPLL_FPA01_P1_POST_DIV_SHIFT);
10679
10680 switch (dpll & DPLL_MODE_MASK) {
10681 case DPLLB_MODE_DAC_SERIAL:
10682 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10683 5 : 10;
10684 break;
10685 case DPLLB_MODE_LVDS:
10686 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10687 7 : 14;
10688 break;
10689 default:
28c97730 10690 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10691 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10692 return;
79e53945
JB		 10693 }
10694
ac58c3f0 10695 if (IS_PINEVIEW(dev))
da4a1efa 10696 pineview_clock(refclk, &clock);
ac58c3f0 10697 else
da4a1efa 10698 i9xx_clock(refclk, &clock);
79e53945 10699 } else {
0fb58223 10700 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10701 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10702
10703 if (is_lvds) {
10704 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10705 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10706
10707 if (lvds & LVDS_CLKB_POWER_UP)
10708 clock.p2 = 7;
10709 else
10710 clock.p2 = 14;
79e53945
JB		 10711 } else {
10712 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10713 clock.p1 = 2;
10714 else {
10715 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10716 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10717 }
10718 if (dpll & PLL_P2_DIVIDE_BY_4)
10719 clock.p2 = 4;
10720 else
10721 clock.p2 = 2;
79e53945 10722 }
da4a1efa
VS		 10723
10724 i9xx_clock(refclk, &clock);
79e53945
JB		 10725 }
10726
18442d08
VS		 10727 /*
10728 * This value includes pixel_multiplier. We will use
241bfc38 10729 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10730 * encoder's get_config() function.
10731 */
10732 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10733}
10734
6878da05
VS		 10735int intel_dotclock_calculate(int link_freq,
10736 const struct intel_link_m_n *m_n)
f1f644dc 10737{
f1f644dc
JB		 10738 /*
10739 * The calculation for the data clock is:
1041a02f 10740 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10741 * But we want to avoid losing precison if possible, so:
1041a02f 10742 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10743 *
10744 * and the link clock is simpler:
1041a02f 10745 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10746 */
10747
6878da05
VS		 10748 if (!m_n->link_n)
10749 return 0;
f1f644dc 10750
6878da05
VS		 10751 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10752}
f1f644dc 10753
18442d08 10754static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10755 struct intel_crtc_state *pipe_config)
6878da05
VS		 10756{
10757 struct drm_device *dev = crtc->base.dev;
79e53945 10758
18442d08
VS		 10759 /* read out port_clock from the DPLL */
10760 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10761
f1f644dc 10762 /*
18442d08 10763 * This value does not include pixel_multiplier.
241bfc38 10764 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10765 * agree once we know their relationship in the encoder's
10766 * get_config() function.
79e53945 10767 */
2d112de7 10768 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10769 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10770 &pipe_config->fdi_m_n);
79e53945
JB		 10771}
10772
10773/** Returns the currently programmed mode of the given pipe. */
10774struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10775 struct drm_crtc *crtc)
10776{
548f245b 10777 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10779 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10780 struct drm_display_mode *mode;
5cec258b 10781 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10782 int htot = I915_READ(HTOTAL(cpu_transcoder));
10783 int hsync = I915_READ(HSYNC(cpu_transcoder));
10784 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10785 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10786 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10787
10788 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10789 if (!mode)
10790 return NULL;
10791
f1f644dc
JB		 10792 /*
10793 * Construct a pipe_config sufficient for getting the clock info
10794 * back out of crtc_clock_get.
10795 *
10796 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10797 * to use a real value here instead.
10798 */
293623f7 10799 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10800 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10801 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10802 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10803 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10804 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10805
773ae034 10806 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10807 mode->hdisplay = (htot & 0xffff) + 1;
10808 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10809 mode->hsync_start = (hsync & 0xffff) + 1;
10810 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10811 mode->vdisplay = (vtot & 0xffff) + 1;
10812 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10813 mode->vsync_start = (vsync & 0xffff) + 1;
10814 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10815
10816 drm_mode_set_name(mode);
79e53945
JB		 10817
10818 return mode;
10819}
10820
652c393a
JB		 10821static void intel_decrease_pllclock(struct drm_crtc *crtc)
10822{
10823 struct drm_device *dev = crtc->dev;
fbee40df 10824 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10826
baff296c 10827 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10828 return;
10829
10830 if (!dev_priv->lvds_downclock_avail)
10831 return;
10832
10833 /*
10834 * Since this is called by a timer, we should never get here in
10835 * the manual case.
10836 */
10837 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10838 int pipe = intel_crtc->pipe;
10839 int dpll_reg = DPLL(pipe);
10840 int dpll;
f6e5b160 10841
44d98a61 10842 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10843
8ac5a6d5 10844 assert_panel_unlocked(dev_priv, pipe);
652c393a 10845
dc257cf1 10846 dpll = I915_READ(dpll_reg);
652c393a
JB		 10847 dpll |= DISPLAY_RATE_SELECT_FPA1;
10848 I915_WRITE(dpll_reg, dpll);
9d0498a2 10849 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10850 dpll = I915_READ(dpll_reg);
10851 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10852 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10853 }
10854
10855}
10856
f047e395
CW		 10857void intel_mark_busy(struct drm_device *dev)
10858{
c67a470b
PZ		 10859 struct drm_i915_private *dev_priv = dev->dev_private;
10860
f62a0076
CW		 10861 if (dev_priv->mm.busy)
10862 return;
10863
43694d69 10864 intel_runtime_pm_get(dev_priv);
c67a470b 10865 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10866 if (INTEL_INFO(dev)->gen >= 6)
10867 gen6_rps_busy(dev_priv);
f62a0076 10868 dev_priv->mm.busy = true;
f047e395
CW		 10869}
10870
10871void intel_mark_idle(struct drm_device *dev)
652c393a 10872{
c67a470b 10873 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10874 struct drm_crtc *crtc;
652c393a 10875
f62a0076
CW		 10876 if (!dev_priv->mm.busy)
10877 return;
10878
10879 dev_priv->mm.busy = false;
10880
70e1e0ec 10881 for_each_crtc(dev, crtc) {
f4510a27 10882 if (!crtc->primary->fb)
652c393a
JB		 10883 continue;
10884
725a5b54 10885 intel_decrease_pllclock(crtc);
652c393a 10886 }
b29c19b6 10887
3d13ef2e 10888 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10889 gen6_rps_idle(dev->dev_private);
bb4cdd53 10890
43694d69 10891 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10892}
10893
79e53945
JB		 10894static void intel_crtc_destroy(struct drm_crtc *crtc)
10895{
10896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10897 struct drm_device *dev = crtc->dev;
10898 struct intel_unpin_work *work;
67e77c5a 10899
5e2d7afc 10900 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10901 work = intel_crtc->unpin_work;
10902 intel_crtc->unpin_work = NULL;
5e2d7afc 10903 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10904
10905 if (work) {
10906 cancel_work_sync(&work->work);
10907 kfree(work);
10908 }
79e53945
JB		 10909
10910 drm_crtc_cleanup(crtc);
67e77c5a 10911
79e53945
JB		 10912 kfree(intel_crtc);
10913}
10914
6b95a207
KH		 10915static void intel_unpin_work_fn(struct work_struct *__work)
10916{
10917 struct intel_unpin_work *work =
10918 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10919 struct drm_device *dev = work->crtc->dev;
f99d7069 10920 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10921
b4a98e57 10922 mutex_lock(&dev->struct_mutex);
82bc3b2d 10923 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10924 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10925
7ff0ebcc 10926 intel_fbc_update(dev);
f06cc1b9
JH		 10927
10928 if (work->flip_queued_req)
146d84f0 10929 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10930 mutex_unlock(&dev->struct_mutex);
10931
f99d7069 10932 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10933 drm_framebuffer_unreference(work->old_fb);
f99d7069 10934
b4a98e57
CW		 10935 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10936 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10937
6b95a207
KH		 10938 kfree(work);
10939}
10940
1afe3e9d 10941static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10942 struct drm_crtc *crtc)
6b95a207 10943{
6b95a207
KH		 10944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10945 struct intel_unpin_work *work;
6b95a207
KH		 10946 unsigned long flags;
10947
10948 /* Ignore early vblank irqs */
10949 if (intel_crtc == NULL)
10950 return;
10951
f326038a
DV		 10952 /*
10953 * This is called both by irq handlers and the reset code (to complete
10954 * lost pageflips) so needs the full irqsave spinlocks.
10955 */
6b95a207
KH		 10956 spin_lock_irqsave(&dev->event_lock, flags);
10957 work = intel_crtc->unpin_work;
e7d841ca
CW		 10958
10959 /* Ensure we don't miss a work->pending update ... */
10960 smp_rmb();
10961
10962 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10963 spin_unlock_irqrestore(&dev->event_lock, flags);
10964 return;
10965 }
10966
d6bbafa1 10967 page_flip_completed(intel_crtc);
0af7e4df 10968
6b95a207 10969 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10970}
10971
1afe3e9d
JB		 10972void intel_finish_page_flip(struct drm_device *dev, int pipe)
10973{
fbee40df 10974 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10975 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10976
49b14a5c 10977 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10978}
10979
10980void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10981{
fbee40df 10982 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10983 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10984
49b14a5c 10985 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10986}
10987
75f7f3ec
VS		 10988/* Is 'a' after or equal to 'b'? */
10989static bool g4x_flip_count_after_eq(u32 a, u32 b)
10990{
10991 return !((a - b) & 0x80000000);
10992}
10993
10994static bool page_flip_finished(struct intel_crtc *crtc)
10995{
10996 struct drm_device *dev = crtc->base.dev;
10997 struct drm_i915_private *dev_priv = dev->dev_private;
10998
bdfa7542
VS		 10999 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
11000 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
11001 return true;
11002
75f7f3ec
VS		 11003 /*
11004 * The relevant registers doen't exist on pre-ctg.
11005 * As the flip done interrupt doesn't trigger for mmio
11006 * flips on gmch platforms, a flip count check isn't
11007 * really needed there. But since ctg has the registers,
11008 * include it in the check anyway.
11009 */
11010 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11011 return true;
11012
11013 /*
11014 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11015 * used the same base address. In that case the mmio flip might
11016 * have completed, but the CS hasn't even executed the flip yet.
11017 *
11018 * A flip count check isn't enough as the CS might have updated
11019 * the base address just after start of vblank, but before we
11020 * managed to process the interrupt. This means we'd complete the
11021 * CS flip too soon.
11022 *
11023 * Combining both checks should get us a good enough result. It may
11024 * still happen that the CS flip has been executed, but has not
11025 * yet actually completed. But in case the base address is the same
11026 * anyway, we don't really care.
11027 */
11028 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11029 crtc->unpin_work->gtt_offset &&
11030 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
11031 crtc->unpin_work->flip_count);
11032}
11033
6b95a207
KH		 11034void intel_prepare_page_flip(struct drm_device *dev, int plane)
11035{
fbee40df 11036 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 11037 struct intel_crtc *intel_crtc =
11038 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11039 unsigned long flags;
11040
f326038a
DV		 11041
11042 /*
11043 * This is called both by irq handlers and the reset code (to complete
11044 * lost pageflips) so needs the full irqsave spinlocks.
11045 *
11046 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 11047 * generate a page-flip completion irq, i.e. every modeset
11048 * is also accompanied by a spurious intel_prepare_page_flip().
11049 */
6b95a207 11050 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 11051 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 11052 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 11053 spin_unlock_irqrestore(&dev->event_lock, flags);
11054}
11055
eba905b2 11056static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 11057{
11058 /* Ensure that the work item is consistent when activating it ... */
11059 smp_wmb();
11060 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
11061 /* and that it is marked active as soon as the irq could fire. */
11062 smp_wmb();
11063}
11064
8c9f3aaf
JB		 11065static int intel_gen2_queue_flip(struct drm_device *dev,
11066 struct drm_crtc *crtc,
11067 struct drm_framebuffer *fb,
ed8d1975 11068 struct drm_i915_gem_object *obj,
a4872ba6 11069 struct intel_engine_cs *ring,
ed8d1975 11070 uint32_t flags)
8c9f3aaf 11071{
8c9f3aaf 11072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11073 u32 flip_mask;
11074 int ret;
11075
6d90c952 11076 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11077 if (ret)
4fa62c89 11078 return ret;
8c9f3aaf
JB		 11079
11080 /* Can't queue multiple flips, so wait for the previous
11081 * one to finish before executing the next.
11082 */
11083 if (intel_crtc->plane)
11084 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11085 else
11086 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11087 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11088 intel_ring_emit(ring, MI_NOOP);
11089 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11090 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11091 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11092 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 11093 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 11094
11095 intel_mark_page_flip_active(intel_crtc);
09246732 11096 __intel_ring_advance(ring);
83d4092b 11097 return 0;
8c9f3aaf
JB		 11098}
11099
11100static int intel_gen3_queue_flip(struct drm_device *dev,
11101 struct drm_crtc *crtc,
11102 struct drm_framebuffer *fb,
ed8d1975 11103 struct drm_i915_gem_object *obj,
a4872ba6 11104 struct intel_engine_cs *ring,
ed8d1975 11105 uint32_t flags)
8c9f3aaf 11106{
8c9f3aaf 11107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11108 u32 flip_mask;
11109 int ret;
11110
6d90c952 11111 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11112 if (ret)
4fa62c89 11113 return ret;
8c9f3aaf
JB		 11114
11115 if (intel_crtc->plane)
11116 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11117 else
11118 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11119 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11120 intel_ring_emit(ring, MI_NOOP);
11121 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11122 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11123 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11124 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 11125 intel_ring_emit(ring, MI_NOOP);
11126
e7d841ca 11127 intel_mark_page_flip_active(intel_crtc);
09246732 11128 __intel_ring_advance(ring);
83d4092b 11129 return 0;
8c9f3aaf
JB		 11130}
11131
11132static int intel_gen4_queue_flip(struct drm_device *dev,
11133 struct drm_crtc *crtc,
11134 struct drm_framebuffer *fb,
ed8d1975 11135 struct drm_i915_gem_object *obj,
a4872ba6 11136 struct intel_engine_cs *ring,
ed8d1975 11137 uint32_t flags)
8c9f3aaf
JB		 11138{
11139 struct drm_i915_private *dev_priv = dev->dev_private;
11140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11141 uint32_t pf, pipesrc;
11142 int ret;
11143
6d90c952 11144 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11145 if (ret)
4fa62c89 11146 return ret;
8c9f3aaf
JB		 11147
11148 /* i965+ uses the linear or tiled offsets from the
11149 * Display Registers (which do not change across a page-flip)
11150 * so we need only reprogram the base address.
11151 */
6d90c952
DV		 11152 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11153 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11154 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11155 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 11156 obj->tiling_mode);
8c9f3aaf
JB		 11157
11158 /* XXX Enabling the panel-fitter across page-flip is so far
11159 * untested on non-native modes, so ignore it for now.
11160 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11161 */
11162 pf = 0;
11163 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11164 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11165
11166 intel_mark_page_flip_active(intel_crtc);
09246732 11167 __intel_ring_advance(ring);
83d4092b 11168 return 0;
8c9f3aaf
JB		 11169}
11170
11171static int intel_gen6_queue_flip(struct drm_device *dev,
11172 struct drm_crtc *crtc,
11173 struct drm_framebuffer *fb,
ed8d1975 11174 struct drm_i915_gem_object *obj,
a4872ba6 11175 struct intel_engine_cs *ring,
ed8d1975 11176 uint32_t flags)
8c9f3aaf
JB		 11177{
11178 struct drm_i915_private *dev_priv = dev->dev_private;
11179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11180 uint32_t pf, pipesrc;
11181 int ret;
11182
6d90c952 11183 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11184 if (ret)
4fa62c89 11185 return ret;
8c9f3aaf 11186
6d90c952
DV		 11187 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11188 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11189 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 11190 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 11191
dc257cf1
DV		 11192 /* Contrary to the suggestions in the documentation,
11193 * "Enable Panel Fitter" does not seem to be required when page
11194 * flipping with a non-native mode, and worse causes a normal
11195 * modeset to fail.
11196 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11197 */
11198 pf = 0;
8c9f3aaf 11199 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11200 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11201
11202 intel_mark_page_flip_active(intel_crtc);
09246732 11203 __intel_ring_advance(ring);
83d4092b 11204 return 0;
8c9f3aaf
JB		 11205}
11206
7c9017e5
JB		 11207static int intel_gen7_queue_flip(struct drm_device *dev,
11208 struct drm_crtc *crtc,
11209 struct drm_framebuffer *fb,
ed8d1975 11210 struct drm_i915_gem_object *obj,
a4872ba6 11211 struct intel_engine_cs *ring,
ed8d1975 11212 uint32_t flags)
7c9017e5 11213{
7c9017e5 11214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11215 uint32_t plane_bit = 0;
ffe74d75
CW		 11216 int len, ret;
11217
eba905b2 11218 switch (intel_crtc->plane) {
cb05d8de
DV		 11219 case PLANE_A:
11220 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11221 break;
11222 case PLANE_B:
11223 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11224 break;
11225 case PLANE_C:
11226 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11227 break;
11228 default:
11229 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11230 return -ENODEV;
cb05d8de
DV		 11231 }
11232
ffe74d75 11233 len = 4;
f476828a 11234 if (ring->id == RCS) {
ffe74d75 11235 len += 6;
f476828a
DL		 11236 /*
11237 * On Gen 8, SRM is now taking an extra dword to accommodate
11238 * 48bits addresses, and we need a NOOP for the batch size to
11239 * stay even.
11240 */
11241 if (IS_GEN8(dev))
11242 len += 2;
11243 }
ffe74d75 11244
f66fab8e
VS		 11245 /*
11246 * BSpec MI_DISPLAY_FLIP for IVB:
11247 * "The full packet must be contained within the same cache line."
11248 *
11249 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11250 * cacheline, if we ever start emitting more commands before
11251 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11252 * then do the cacheline alignment, and finally emit the
11253 * MI_DISPLAY_FLIP.
11254 */
11255 ret = intel_ring_cacheline_align(ring);
11256 if (ret)
4fa62c89 11257 return ret;
f66fab8e 11258
ffe74d75 11259 ret = intel_ring_begin(ring, len);
7c9017e5 11260 if (ret)
4fa62c89 11261 return ret;
7c9017e5 11262
ffe74d75
CW		 11263 /* Unmask the flip-done completion message. Note that the bspec says that
11264 * we should do this for both the BCS and RCS, and that we must not unmask
11265 * more than one flip event at any time (or ensure that one flip message
11266 * can be sent by waiting for flip-done prior to queueing new flips).
11267 * Experimentation says that BCS works despite DERRMR masking all
11268 * flip-done completion events and that unmasking all planes at once
11269 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11270 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11271 */
11272 if (ring->id == RCS) {
11273 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11274 intel_ring_emit(ring, DERRMR);
11275 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11276 DERRMR_PIPEB_PRI_FLIP_DONE |
11277 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11278 if (IS_GEN8(dev))
11279 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11280 MI_SRM_LRM_GLOBAL_GTT);
11281 else
11282 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11283 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11284 intel_ring_emit(ring, DERRMR);
11285 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11286 if (IS_GEN8(dev)) {
11287 intel_ring_emit(ring, 0);
11288 intel_ring_emit(ring, MI_NOOP);
11289 }
ffe74d75
CW		 11290 }
11291
cb05d8de 11292 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11293 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11294 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11295 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11296
11297 intel_mark_page_flip_active(intel_crtc);
09246732 11298 __intel_ring_advance(ring);
83d4092b 11299 return 0;
7c9017e5
JB		 11300}
11301
84c33a64
SG		 11302static bool use_mmio_flip(struct intel_engine_cs *ring,
11303 struct drm_i915_gem_object *obj)
11304{
11305 /*
11306 * This is not being used for older platforms, because
11307 * non-availability of flip done interrupt forces us to use
11308 * CS flips. Older platforms derive flip done using some clever
11309 * tricks involving the flip_pending status bits and vblank irqs.
11310 * So using MMIO flips there would disrupt this mechanism.
11311 */
11312
8e09bf83
CW		 11313 if (ring == NULL)
11314 return true;
11315
84c33a64
SG		 11316 if (INTEL_INFO(ring->dev)->gen < 5)
11317 return false;
11318
11319 if (i915.use_mmio_flip < 0)
11320 return false;
11321 else if (i915.use_mmio_flip > 0)
11322 return true;
14bf993e
OM		 11323 else if (i915.enable_execlists)
11324 return true;
84c33a64 11325 else
b4716185 11326 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11327}
11328
ff944564
DL		 11329static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11330{
11331 struct drm_device *dev = intel_crtc->base.dev;
11332 struct drm_i915_private *dev_priv = dev->dev_private;
11333 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11334 const enum pipe pipe = intel_crtc->pipe;
11335 u32 ctl, stride;
11336
11337 ctl = I915_READ(PLANE_CTL(pipe, 0));
11338 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11339 switch (fb->modifier[0]) {
11340 case DRM_FORMAT_MOD_NONE:
11341 break;
11342 case I915_FORMAT_MOD_X_TILED:
ff944564 11343 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11344 break;
11345 case I915_FORMAT_MOD_Y_TILED:
11346 ctl |= PLANE_CTL_TILED_Y;
11347 break;
11348 case I915_FORMAT_MOD_Yf_TILED:
11349 ctl |= PLANE_CTL_TILED_YF;
11350 break;
11351 default:
11352 MISSING_CASE(fb->modifier[0]);
11353 }
ff944564
DL		 11354
11355 /*
11356 * The stride is either expressed as a multiple of 64 bytes chunks for
11357 * linear buffers or in number of tiles for tiled buffers.
11358 */
2ebef630
TU		 11359 stride = fb->pitches[0] /
11360 intel_fb_stride_alignment(dev, fb->modifier[0],
11361 fb->pixel_format);
ff944564
DL		 11362
11363 /*
11364 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11365 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11366 */
11367 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11368 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11369
11370 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11371 POSTING_READ(PLANE_SURF(pipe, 0));
11372}
11373
11374static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11375{
11376 struct drm_device *dev = intel_crtc->base.dev;
11377 struct drm_i915_private *dev_priv = dev->dev_private;
11378 struct intel_framebuffer *intel_fb =
11379 to_intel_framebuffer(intel_crtc->base.primary->fb);
11380 struct drm_i915_gem_object *obj = intel_fb->obj;
11381 u32 dspcntr;
11382 u32 reg;
11383
84c33a64
SG		 11384 reg = DSPCNTR(intel_crtc->plane);
11385 dspcntr = I915_READ(reg);
11386
c5d97472
DL		 11387 if (obj->tiling_mode != I915_TILING_NONE)
11388 dspcntr |= DISPPLANE_TILED;
11389 else
11390 dspcntr &= ~DISPPLANE_TILED;
11391
84c33a64
SG		 11392 I915_WRITE(reg, dspcntr);
11393
11394 I915_WRITE(DSPSURF(intel_crtc->plane),
11395 intel_crtc->unpin_work->gtt_offset);
11396 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11397
ff944564
DL		 11398}
11399
11400/*
11401 * XXX: This is the temporary way to update the plane registers until we get
11402 * around to using the usual plane update functions for MMIO flips
11403 */
11404static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11405{
11406 struct drm_device *dev = intel_crtc->base.dev;
11407 bool atomic_update;
11408 u32 start_vbl_count;
11409
11410 intel_mark_page_flip_active(intel_crtc);
11411
11412 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11413
11414 if (INTEL_INFO(dev)->gen >= 9)
11415 skl_do_mmio_flip(intel_crtc);
11416 else
11417 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11418 ilk_do_mmio_flip(intel_crtc);
11419
9362c7c5
ACO		 11420 if (atomic_update)
11421 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11422}
11423
9362c7c5 11424static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11425{
b2cfe0ab
CW		 11426 struct intel_mmio_flip *mmio_flip =
11427 container_of(work, struct intel_mmio_flip, work);
84c33a64 11428
eed29a5b
DV		 11429 if (mmio_flip->req)
11430 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11431 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11432 false, NULL,
11433 &mmio_flip->i915->rps.mmioflips));
84c33a64 11434
b2cfe0ab
CW		 11435 intel_do_mmio_flip(mmio_flip->crtc);
11436
eed29a5b 11437 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11438 kfree(mmio_flip);
84c33a64
SG		 11439}
11440
11441static int intel_queue_mmio_flip(struct drm_device *dev,
11442 struct drm_crtc *crtc,
11443 struct drm_framebuffer *fb,
11444 struct drm_i915_gem_object *obj,
11445 struct intel_engine_cs *ring,
11446 uint32_t flags)
11447{
b2cfe0ab
CW		 11448 struct intel_mmio_flip *mmio_flip;
11449
11450 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11451 if (mmio_flip == NULL)
11452 return -ENOMEM;
84c33a64 11453
bcafc4e3 11454 mmio_flip->i915 = to_i915(dev);
eed29a5b 11455 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11456 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11457
b2cfe0ab
CW		 11458 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11459 schedule_work(&mmio_flip->work);
84c33a64 11460
84c33a64
SG		 11461 return 0;
11462}
11463
8c9f3aaf
JB		 11464static int intel_default_queue_flip(struct drm_device *dev,
11465 struct drm_crtc *crtc,
11466 struct drm_framebuffer *fb,
ed8d1975 11467 struct drm_i915_gem_object *obj,
a4872ba6 11468 struct intel_engine_cs *ring,
ed8d1975 11469 uint32_t flags)
8c9f3aaf
JB		 11470{
11471 return -ENODEV;
11472}
11473
d6bbafa1
CW		 11474static bool __intel_pageflip_stall_check(struct drm_device *dev,
11475 struct drm_crtc *crtc)
11476{
11477 struct drm_i915_private *dev_priv = dev->dev_private;
11478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11479 struct intel_unpin_work *work = intel_crtc->unpin_work;
11480 u32 addr;
11481
11482 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11483 return true;
11484
11485 if (!work->enable_stall_check)
11486 return false;
11487
11488 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11489 if (work->flip_queued_req &&
11490 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11491 return false;
11492
1e3feefd 11493 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11494 }
11495
1e3feefd 11496 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11497 return false;
11498
11499 /* Potential stall - if we see that the flip has happened,
11500 * assume a missed interrupt. */
11501 if (INTEL_INFO(dev)->gen >= 4)
11502 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11503 else
11504 addr = I915_READ(DSPADDR(intel_crtc->plane));
11505
11506 /* There is a potential issue here with a false positive after a flip
11507 * to the same address. We could address this by checking for a
11508 * non-incrementing frame counter.
11509 */
11510 return addr == work->gtt_offset;
11511}
11512
11513void intel_check_page_flip(struct drm_device *dev, int pipe)
11514{
11515 struct drm_i915_private *dev_priv = dev->dev_private;
11516 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11518 struct intel_unpin_work *work;
f326038a 11519
6c51d46f 11520 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11521
11522 if (crtc == NULL)
11523 return;
11524
f326038a 11525 spin_lock(&dev->event_lock);
6ad790c0
CW		 11526 work = intel_crtc->unpin_work;
11527 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11528 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11529 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11530 page_flip_completed(intel_crtc);
6ad790c0 11531 work = NULL;
d6bbafa1 11532 }
6ad790c0
CW		 11533 if (work != NULL &&
11534 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11535 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11536 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11537}
11538
6b95a207
KH		 11539static int intel_crtc_page_flip(struct drm_crtc *crtc,
11540 struct drm_framebuffer *fb,
ed8d1975
KP		 11541 struct drm_pending_vblank_event *event,
11542 uint32_t page_flip_flags)
6b95a207
KH		 11543{
11544 struct drm_device *dev = crtc->dev;
11545 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11546 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11547 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11549 struct drm_plane *primary = crtc->primary;
a071fa00 11550 enum pipe pipe = intel_crtc->pipe;
6b95a207 11551 struct intel_unpin_work *work;
a4872ba6 11552 struct intel_engine_cs *ring;
cf5d8a46 11553 bool mmio_flip;
52e68630 11554 int ret;
6b95a207 11555
2ff8fde1
MR		 11556 /*
11557 * drm_mode_page_flip_ioctl() should already catch this, but double
11558 * check to be safe. In the future we may enable pageflipping from
11559 * a disabled primary plane.
11560 */
11561 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11562 return -EBUSY;
11563
e6a595d2 11564 /* Can't change pixel format via MI display flips. */
f4510a27 11565 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11566 return -EINVAL;
11567
11568 /*
11569 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11570 * Note that pitch changes could also affect these register.
11571 */
11572 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11573 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11574 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11575 return -EINVAL;
11576
f900db47
CW		 11577 if (i915_terminally_wedged(&dev_priv->gpu_error))
11578 goto out_hang;
11579
b14c5679 11580 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11581 if (work == NULL)
11582 return -ENOMEM;
11583
6b95a207 11584 work->event = event;
b4a98e57 11585 work->crtc = crtc;
ab8d6675 11586 work->old_fb = old_fb;
6b95a207
KH		 11587 INIT_WORK(&work->work, intel_unpin_work_fn);
11588
87b6b101 11589 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11590 if (ret)
11591 goto free_work;
11592
6b95a207 11593 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11594 spin_lock_irq(&dev->event_lock);
6b95a207 11595 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11596 /* Before declaring the flip queue wedged, check if
11597 * the hardware completed the operation behind our backs.
11598 */
11599 if (__intel_pageflip_stall_check(dev, crtc)) {
11600 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11601 page_flip_completed(intel_crtc);
11602 } else {
11603 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11604 spin_unlock_irq(&dev->event_lock);
468f0b44 11605
d6bbafa1
CW		 11606 drm_crtc_vblank_put(crtc);
11607 kfree(work);
11608 return -EBUSY;
11609 }
6b95a207
KH		 11610 }
11611 intel_crtc->unpin_work = work;
5e2d7afc 11612 spin_unlock_irq(&dev->event_lock);
6b95a207 11613
b4a98e57
CW		 11614 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11615 flush_workqueue(dev_priv->wq);
11616
75dfca80 11617 /* Reference the objects for the scheduled work. */
ab8d6675 11618 drm_framebuffer_reference(work->old_fb);
05394f39 11619 drm_gem_object_reference(&obj->base);
6b95a207 11620
f4510a27 11621 crtc->primary->fb = fb;
afd65eb4 11622 update_state_fb(crtc->primary);
1ed1f968 11623
e1f99ce6 11624 work->pending_flip_obj = obj;
e1f99ce6 11625
89ed88ba
CW		 11626 ret = i915_mutex_lock_interruptible(dev);
11627 if (ret)
11628 goto cleanup;
11629
b4a98e57 11630 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11631 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11632
75f7f3ec 11633 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11634 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11635
4fa62c89
VS		 11636 if (IS_VALLEYVIEW(dev)) {
11637 ring = &dev_priv->ring[BCS];
ab8d6675 11638 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11639 /* vlv: DISPLAY_FLIP fails to change tiling */
11640 ring = NULL;
48bf5b2d 11641 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11642 ring = &dev_priv->ring[BCS];
4fa62c89 11643 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11644 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11645 if (ring == NULL || ring->id != RCS)
11646 ring = &dev_priv->ring[BCS];
11647 } else {
11648 ring = &dev_priv->ring[RCS];
11649 }
11650
cf5d8a46
CW		 11651 mmio_flip = use_mmio_flip(ring, obj);
11652
11653 /* When using CS flips, we want to emit semaphores between rings.
11654 * However, when using mmio flips we will create a task to do the
11655 * synchronisation, so all we want here is to pin the framebuffer
11656 * into the display plane and skip any waits.
11657 */
82bc3b2d 11658 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11659 crtc->primary->state,
b4716185 11660 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11661 if (ret)
11662 goto cleanup_pending;
6b95a207 11663
121920fa
TU		 11664 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11665 + intel_crtc->dspaddr_offset;
4fa62c89 11666
cf5d8a46 11667 if (mmio_flip) {
84c33a64
SG		 11668 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11669 page_flip_flags);
d6bbafa1
CW		 11670 if (ret)
11671 goto cleanup_unpin;
11672
f06cc1b9
JH		 11673 i915_gem_request_assign(&work->flip_queued_req,
11674 obj->last_write_req);
d6bbafa1 11675 } else {
d94b5030
CW		 11676 if (obj->last_write_req) {
11677 ret = i915_gem_check_olr(obj->last_write_req);
11678 if (ret)
11679 goto cleanup_unpin;
11680 }
11681
84c33a64 11682 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11683 page_flip_flags);
11684 if (ret)
11685 goto cleanup_unpin;
11686
f06cc1b9
JH		 11687 i915_gem_request_assign(&work->flip_queued_req,
11688 intel_ring_get_request(ring));
d6bbafa1
CW		 11689 }
11690
1e3feefd 11691 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11692 work->enable_stall_check = true;
4fa62c89 11693
ab8d6675 11694 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11695 INTEL_FRONTBUFFER_PRIMARY(pipe));
11696
7ff0ebcc 11697 intel_fbc_disable(dev);
f99d7069 11698 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11699 mutex_unlock(&dev->struct_mutex);
11700
e5510fac
JB		 11701 trace_i915_flip_request(intel_crtc->plane, obj);
11702
6b95a207 11703 return 0;
96b099fd 11704
4fa62c89 11705cleanup_unpin:
82bc3b2d 11706 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11707cleanup_pending:
b4a98e57 11708 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11709 mutex_unlock(&dev->struct_mutex);
11710cleanup:
f4510a27 11711 crtc->primary->fb = old_fb;
afd65eb4 11712 update_state_fb(crtc->primary);
89ed88ba
CW		 11713
11714 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11715 drm_framebuffer_unreference(work->old_fb);
96b099fd 11716
5e2d7afc 11717 spin_lock_irq(&dev->event_lock);
96b099fd 11718 intel_crtc->unpin_work = NULL;
5e2d7afc 11719 spin_unlock_irq(&dev->event_lock);
96b099fd 11720
87b6b101 11721 drm_crtc_vblank_put(crtc);
7317c75e 11722free_work:
96b099fd
CW		 11723 kfree(work);
11724
f900db47
CW		 11725 if (ret == -EIO) {
11726out_hang:
53a366b9 11727 ret = intel_plane_restore(primary);
f0d3dad3 11728 if (ret == 0 && event) {
5e2d7afc 11729 spin_lock_irq(&dev->event_lock);
a071fa00 11730 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11731 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11732 }
f900db47 11733 }
96b099fd 11734 return ret;
6b95a207
KH		 11735}
11736
65b38e0d 11737static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11738 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11739 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11740 .atomic_begin = intel_begin_crtc_commit,
11741 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11742};
11743
9a935856
DV		 11744/**
11745 * intel_modeset_update_staged_output_state
11746 *
11747 * Updates the staged output configuration state, e.g. after we've read out the
11748 * current hw state.
11749 */
11750static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11751{
7668851f 11752 struct intel_crtc *crtc;
9a935856
DV		 11753 struct intel_encoder *encoder;
11754 struct intel_connector *connector;
f6e5b160 11755
3a3371ff 11756 for_each_intel_connector(dev, connector) {
9a935856
DV		 11757 connector->new_encoder =
11758 to_intel_encoder(connector->base.encoder);
11759 }
f6e5b160 11760
b2784e15 11761 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11762 encoder->new_crtc =
11763 to_intel_crtc(encoder->base.crtc);
11764 }
7668851f 11765
d3fcc808 11766 for_each_intel_crtc(dev, crtc) {
83d65738 11767 crtc->new_enabled = crtc->base.state->enable;
7668851f 11768 }
f6e5b160
CW		 11769}
11770
d29b2f9d
ACO		 11771/* Transitional helper to copy current connector/encoder state to
11772 * connector->state. This is needed so that code that is partially
11773 * converted to atomic does the right thing.
11774 */
11775static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11776{
11777 struct intel_connector *connector;
11778
11779 for_each_intel_connector(dev, connector) {
11780 if (connector->base.encoder) {
11781 connector->base.state->best_encoder =
11782 connector->base.encoder;
11783 connector->base.state->crtc =
11784 connector->base.encoder->crtc;
11785 } else {
11786 connector->base.state->best_encoder = NULL;
11787 connector->base.state->crtc = NULL;
11788 }
11789 }
11790}
11791
a821fc46 11792/* Fixup legacy state after an atomic state swap.
9a935856 11793 */
a821fc46 11794static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11795{
a821fc46 11796 struct intel_crtc *crtc;
9a935856 11797 struct intel_encoder *encoder;
a821fc46 11798 struct intel_connector *connector;
d5432a9d 11799
a821fc46
ACO		 11800 for_each_intel_connector(state->dev, connector) {
11801 connector->base.encoder = connector->base.state->best_encoder;
11802 if (connector->base.encoder)
11803 connector->base.encoder->crtc =
11804 connector->base.state->crtc;
9a935856 11805 }
f6e5b160 11806
d5432a9d
ACO		 11807 /* Update crtc of disabled encoders */
11808 for_each_intel_encoder(state->dev, encoder) {
11809 int num_connectors = 0;
11810
a821fc46
ACO		 11811 for_each_intel_connector(state->dev, connector)
11812 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO		 11813 num_connectors++;
11814
11815 if (num_connectors == 0)
11816 encoder->base.crtc = NULL;
9a935856 11817 }
7668851f 11818
a821fc46
ACO		 11819 for_each_intel_crtc(state->dev, crtc) {
11820 crtc->base.enabled = crtc->base.state->enable;
11821 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11822 }
d29b2f9d 11823
d5432a9d
ACO		 11824 /* Copy the new configuration to the staged state, to keep the few
11825 * pieces of code that haven't been converted yet happy */
11826 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV		 11827}
11828
050f7aeb 11829static void
eba905b2 11830connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11831 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11832{
11833 int bpp = pipe_config->pipe_bpp;
11834
11835 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11836 connector->base.base.id,
c23cc417 11837 connector->base.name);
050f7aeb
DV		 11838
11839 /* Don't use an invalid EDID bpc value */
11840 if (connector->base.display_info.bpc &&
11841 connector->base.display_info.bpc * 3 < bpp) {
11842 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11843 bpp, connector->base.display_info.bpc*3);
11844 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11845 }
11846
11847 /* Clamp bpp to 8 on screens without EDID 1.4 */
11848 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11849 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11850 bpp);
11851 pipe_config->pipe_bpp = 24;
11852 }
11853}
11854
4e53c2e0 11855static int
050f7aeb 11856compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11857 struct intel_crtc_state *pipe_config)
4e53c2e0 11858{
050f7aeb 11859 struct drm_device *dev = crtc->base.dev;
1486017f 11860 struct drm_atomic_state *state;
da3ced29
ACO		 11861 struct drm_connector *connector;
11862 struct drm_connector_state *connector_state;
1486017f 11863 int bpp, i;
4e53c2e0 11864
d328c9d7 11865 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11866 bpp = 10*3;
d328c9d7
DV		 11867 else if (INTEL_INFO(dev)->gen >= 5)
11868 bpp = 12*3;
11869 else
11870 bpp = 8*3;
11871
4e53c2e0 11872
4e53c2e0
DV		 11873 pipe_config->pipe_bpp = bpp;
11874
1486017f
ACO		 11875 state = pipe_config->base.state;
11876
4e53c2e0 11877 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11878 for_each_connector_in_state(state, connector, connector_state, i) {
11879 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11880 continue;
11881
da3ced29
ACO		 11882 connected_sink_compute_bpp(to_intel_connector(connector),
11883 pipe_config);
4e53c2e0
DV		 11884 }
11885
11886 return bpp;
11887}
11888
644db711
DV		 11889static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11890{
11891 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11892 "type: 0x%x flags: 0x%x\n",
1342830c 11893 mode->crtc_clock,
644db711
DV		 11894 mode->crtc_hdisplay, mode->crtc_hsync_start,
11895 mode->crtc_hsync_end, mode->crtc_htotal,
11896 mode->crtc_vdisplay, mode->crtc_vsync_start,
11897 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11898}
11899
c0b03411 11900static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11901 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11902 const char *context)
11903{
6a60cd87
CK		 11904 struct drm_device *dev = crtc->base.dev;
11905 struct drm_plane *plane;
11906 struct intel_plane *intel_plane;
11907 struct intel_plane_state *state;
11908 struct drm_framebuffer *fb;
11909
11910 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11911 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11912
11913 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11914 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11915 pipe_config->pipe_bpp, pipe_config->dither);
11916 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11917 pipe_config->has_pch_encoder,
11918 pipe_config->fdi_lanes,
11919 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11920 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11921 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11922 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11923 pipe_config->has_dp_encoder,
11924 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11925 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11926 pipe_config->dp_m_n.tu);
b95af8be
VK		 11927
11928 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11929 pipe_config->has_dp_encoder,
11930 pipe_config->dp_m2_n2.gmch_m,
11931 pipe_config->dp_m2_n2.gmch_n,
11932 pipe_config->dp_m2_n2.link_m,
11933 pipe_config->dp_m2_n2.link_n,
11934 pipe_config->dp_m2_n2.tu);
11935
55072d19
DV		 11936 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11937 pipe_config->has_audio,
11938 pipe_config->has_infoframe);
11939
c0b03411 11940 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11941 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11942 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11943 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11944 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11945 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11946 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11947 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11948 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11949 crtc->num_scalers,
11950 pipe_config->scaler_state.scaler_users,
11951 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11952 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11953 pipe_config->gmch_pfit.control,
11954 pipe_config->gmch_pfit.pgm_ratios,
11955 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11956 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11957 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11958 pipe_config->pch_pfit.size,
11959 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11960 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11961 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11962
415ff0f6
TU		 11963 if (IS_BROXTON(dev)) {
11964 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11965 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11966 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11967 pipe_config->ddi_pll_sel,
11968 pipe_config->dpll_hw_state.ebb0,
11969 pipe_config->dpll_hw_state.pll0,
11970 pipe_config->dpll_hw_state.pll1,
11971 pipe_config->dpll_hw_state.pll2,
11972 pipe_config->dpll_hw_state.pll3,
11973 pipe_config->dpll_hw_state.pll6,
11974 pipe_config->dpll_hw_state.pll8,
11975 pipe_config->dpll_hw_state.pcsdw12);
11976 } else if (IS_SKYLAKE(dev)) {
11977 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11978 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11979 pipe_config->ddi_pll_sel,
11980 pipe_config->dpll_hw_state.ctrl1,
11981 pipe_config->dpll_hw_state.cfgcr1,
11982 pipe_config->dpll_hw_state.cfgcr2);
11983 } else if (HAS_DDI(dev)) {
11984 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11985 pipe_config->ddi_pll_sel,
11986 pipe_config->dpll_hw_state.wrpll);
11987 } else {
11988 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11989 "fp0: 0x%x, fp1: 0x%x\n",
11990 pipe_config->dpll_hw_state.dpll,
11991 pipe_config->dpll_hw_state.dpll_md,
11992 pipe_config->dpll_hw_state.fp0,
11993 pipe_config->dpll_hw_state.fp1);
11994 }
11995
6a60cd87
CK		 11996 DRM_DEBUG_KMS("planes on this crtc\n");
11997 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11998 intel_plane = to_intel_plane(plane);
11999 if (intel_plane->pipe != crtc->pipe)
12000 continue;
12001
12002 state = to_intel_plane_state(plane->state);
12003 fb = state->base.fb;
12004 if (!fb) {
12005 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12006 "disabled, scaler_id = %d\n",
12007 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12008 plane->base.id, intel_plane->pipe,
12009 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12010 drm_plane_index(plane), state->scaler_id);
12011 continue;
12012 }
12013
12014 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12015 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12016 plane->base.id, intel_plane->pipe,
12017 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12018 drm_plane_index(plane));
12019 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12020 fb->base.id, fb->width, fb->height, fb->pixel_format);
12021 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12022 state->scaler_id,
12023 state->src.x1 >> 16, state->src.y1 >> 16,
12024 drm_rect_width(&state->src) >> 16,
12025 drm_rect_height(&state->src) >> 16,
12026 state->dst.x1, state->dst.y1,
12027 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12028 }
c0b03411
DV		 12029}
12030
bc079e8b
VS		 12031static bool encoders_cloneable(const struct intel_encoder *a,
12032 const struct intel_encoder *b)
accfc0c5 12033{
bc079e8b
VS		 12034 /* masks could be asymmetric, so check both ways */
12035 return a == b || (a->cloneable & (1 << b->type) &&
12036 b->cloneable & (1 << a->type));
12037}
12038
98a221da
ACO		 12039static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12040 struct intel_crtc *crtc,
bc079e8b
VS		 12041 struct intel_encoder *encoder)
12042{
bc079e8b 12043 struct intel_encoder *source_encoder;
da3ced29 12044 struct drm_connector *connector;
98a221da
ACO		 12045 struct drm_connector_state *connector_state;
12046 int i;
bc079e8b 12047
da3ced29 12048 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 12049 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 12050 continue;
12051
98a221da
ACO		 12052 source_encoder =
12053 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 12054 if (!encoders_cloneable(encoder, source_encoder))
12055 return false;
12056 }
12057
12058 return true;
12059}
12060
98a221da
ACO		 12061static bool check_encoder_cloning(struct drm_atomic_state *state,
12062 struct intel_crtc *crtc)
bc079e8b 12063{
accfc0c5 12064 struct intel_encoder *encoder;
da3ced29 12065 struct drm_connector *connector;
98a221da
ACO		 12066 struct drm_connector_state *connector_state;
12067 int i;
accfc0c5 12068
da3ced29 12069 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 12070 if (connector_state->crtc != &crtc->base)
12071 continue;
12072
12073 encoder = to_intel_encoder(connector_state->best_encoder);
12074 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 12075 return false;
accfc0c5
DV		 12076 }
12077
bc079e8b 12078 return true;
accfc0c5
DV		 12079}
12080
5448a00d 12081static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12082{
5448a00d
ACO		 12083 struct drm_device *dev = state->dev;
12084 struct intel_encoder *encoder;
da3ced29 12085 struct drm_connector *connector;
5448a00d 12086 struct drm_connector_state *connector_state;
00f0b378 12087 unsigned int used_ports = 0;
5448a00d 12088 int i;
00f0b378
VS		 12089
12090 /*
12091 * Walk the connector list instead of the encoder
12092 * list to detect the problem on ddi platforms
12093 * where there's just one encoder per digital port.
12094 */
da3ced29 12095 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12096 if (!connector_state->best_encoder)
00f0b378
VS		 12097 continue;
12098
5448a00d
ACO		 12099 encoder = to_intel_encoder(connector_state->best_encoder);
12100
12101 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12102
12103 switch (encoder->type) {
12104 unsigned int port_mask;
12105 case INTEL_OUTPUT_UNKNOWN:
12106 if (WARN_ON(!HAS_DDI(dev)))
12107 break;
12108 case INTEL_OUTPUT_DISPLAYPORT:
12109 case INTEL_OUTPUT_HDMI:
12110 case INTEL_OUTPUT_EDP:
12111 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12112
12113 /* the same port mustn't appear more than once */
12114 if (used_ports & port_mask)
12115 return false;
12116
12117 used_ports |= port_mask;
12118 default:
12119 break;
12120 }
12121 }
12122
12123 return true;
12124}
12125
83a57153
ACO		 12126static void
12127clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12128{
12129 struct drm_crtc_state tmp_state;
663a3640 12130 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12131 struct intel_dpll_hw_state dpll_hw_state;
12132 enum intel_dpll_id shared_dpll;
8504c74c 12133 uint32_t ddi_pll_sel;
83a57153 12134
7546a384
ACO		 12135 /* FIXME: before the switch to atomic started, a new pipe_config was
12136 * kzalloc'd. Code that depends on any field being zero should be
12137 * fixed, so that the crtc_state can be safely duplicated. For now,
12138 * only fields that are know to not cause problems are preserved. */
12139
83a57153 12140 tmp_state = crtc_state->base;
663a3640 12141 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12142 shared_dpll = crtc_state->shared_dpll;
12143 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12144 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12145
83a57153 12146 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12147
83a57153 12148 crtc_state->base = tmp_state;
663a3640 12149 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12150 crtc_state->shared_dpll = shared_dpll;
12151 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12152 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12153}
12154
548ee15b 12155static int
b8cecdf5 12156intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 12157 struct drm_atomic_state *state,
12158 struct intel_crtc_state *pipe_config)
ee7b9f93 12159{
7758a113 12160 struct intel_encoder *encoder;
da3ced29 12161 struct drm_connector *connector;
0b901879 12162 struct drm_connector_state *connector_state;
d328c9d7 12163 int base_bpp, ret = -EINVAL;
0b901879 12164 int i;
e29c22c0 12165 bool retry = true;
ee7b9f93 12166
98a221da 12167 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 12168 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 12169 return -EINVAL;
accfc0c5
DV		 12170 }
12171
5448a00d 12172 if (!check_digital_port_conflicts(state)) {
00f0b378 12173 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 12174 return -EINVAL;
00f0b378
VS		 12175 }
12176
83a57153 12177 clear_intel_crtc_state(pipe_config);
7758a113 12178
e143a21c
DV		 12179 pipe_config->cpu_transcoder =
12180 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12181
2960bc9c
ID		 12182 /*
12183 * Sanitize sync polarity flags based on requested ones. If neither
12184 * positive or negative polarity is requested, treat this as meaning
12185 * negative polarity.
12186 */
2d112de7 12187 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12188 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12189 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12190
2d112de7 12191 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12192 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12193 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12194
050f7aeb
DV		 12195 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12196 * plane pixel format and any sink constraints into account. Returns the
12197 * source plane bpp so that dithering can be selected on mismatches
12198 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12199 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12200 pipe_config);
12201 if (base_bpp < 0)
4e53c2e0
DV		 12202 goto fail;
12203
e41a56be
VS		 12204 /*
12205 * Determine the real pipe dimensions. Note that stereo modes can
12206 * increase the actual pipe size due to the frame doubling and
12207 * insertion of additional space for blanks between the frame. This
12208 * is stored in the crtc timings. We use the requested mode to do this
12209 * computation to clearly distinguish it from the adjusted mode, which
12210 * can be changed by the connectors in the below retry loop.
12211 */
2d112de7 12212 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12213 &pipe_config->pipe_src_w,
12214 &pipe_config->pipe_src_h);
e41a56be 12215
e29c22c0 12216encoder_retry:
ef1b460d 12217 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12218 pipe_config->port_clock = 0;
ef1b460d 12219 pipe_config->pixel_multiplier = 1;
ff9a6750 12220
135c81b8 12221 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12222 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12223 CRTC_STEREO_DOUBLE);
135c81b8 12224
7758a113
DV		 12225 /* Pass our mode to the connectors and the CRTC to give them a chance to
12226 * adjust it according to limitations or connector properties, and also
12227 * a chance to reject the mode entirely.
47f1c6c9 12228 */
da3ced29 12229 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12230 if (connector_state->crtc != crtc)
7758a113 12231 continue;
7ae89233 12232
0b901879
ACO		 12233 encoder = to_intel_encoder(connector_state->best_encoder);
12234
efea6e8e
DV		 12235 if (!(encoder->compute_config(encoder, pipe_config))) {
12236 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12237 goto fail;
12238 }
ee7b9f93 12239 }
47f1c6c9 12240
ff9a6750
DV		 12241 /* Set default port clock if not overwritten by the encoder. Needs to be
12242 * done afterwards in case the encoder adjusts the mode. */
12243 if (!pipe_config->port_clock)
2d112de7 12244 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12245 * pipe_config->pixel_multiplier;
ff9a6750 12246
a43f6e0f 12247 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12248 if (ret < 0) {
7758a113
DV		 12249 DRM_DEBUG_KMS("CRTC fixup failed\n");
12250 goto fail;
ee7b9f93 12251 }
e29c22c0
DV		 12252
12253 if (ret == RETRY) {
12254 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12255 ret = -EINVAL;
12256 goto fail;
12257 }
12258
12259 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12260 retry = false;
12261 goto encoder_retry;
12262 }
12263
d328c9d7 12264 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12265 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12266 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12267
548ee15b 12268 return 0;
7758a113 12269fail:
548ee15b 12270 return ret;
ee7b9f93 12271}
47f1c6c9 12272
ea9d758d 12273static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12274{
ea9d758d 12275 struct drm_encoder *encoder;
f6e5b160 12276 struct drm_device *dev = crtc->dev;
f6e5b160 12277
ea9d758d
DV		 12278 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12279 if (encoder->crtc == crtc)
12280 return true;
12281
12282 return false;
12283}
12284
0a9ab303
ACO		 12285static bool
12286needs_modeset(struct drm_crtc_state *state)
12287{
12288 return state->mode_changed || state->active_changed;
12289}
12290
ea9d758d 12291static void
0a9ab303 12292intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12293{
0a9ab303 12294 struct drm_device *dev = state->dev;
ba41c0de 12295 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 12296 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12297 struct drm_crtc *crtc;
12298 struct drm_crtc_state *crtc_state;
ea9d758d 12299 struct drm_connector *connector;
0a9ab303 12300 int i;
ea9d758d 12301
ba41c0de
DV		 12302 intel_shared_dpll_commit(dev_priv);
12303
b2784e15 12304 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12305 if (!intel_encoder->base.crtc)
12306 continue;
12307
bd4b4827
ACO		 12308 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12309 if (crtc != intel_encoder->base.crtc)
12310 continue;
0a9ab303 12311
bd4b4827
ACO		 12312 if (crtc_state->enable && needs_modeset(crtc_state))
12313 intel_encoder->connectors_active = false;
ea9d758d 12314
bd4b4827
ACO		 12315 break;
12316 }
ea9d758d
DV		 12317 }
12318
a821fc46
ACO		 12319 drm_atomic_helper_swap_state(state->dev, state);
12320 intel_modeset_fixup_state(state);
ea9d758d 12321
7668851f 12322 /* Double check state. */
0a9ab303
ACO		 12323 for_each_crtc(dev, crtc) {
12324 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV		 12325 }
12326
12327 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12328 if (!connector->encoder || !connector->encoder->crtc)
12329 continue;
12330
bd4b4827
ACO		 12331 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12332 if (crtc != connector->encoder->crtc)
12333 continue;
0a9ab303 12334
bd4b4827
ACO		 12335 if (crtc->state->enable && needs_modeset(crtc->state)) {
12336 struct drm_property *dpms_property =
12337 dev->mode_config.dpms_property;
ea9d758d 12338
bd4b4827
ACO		 12339 connector->dpms = DRM_MODE_DPMS_ON;
12340 drm_object_property_set_value(&connector->base,
12341 dpms_property,
12342 DRM_MODE_DPMS_ON);
68d34720 12343
bd4b4827
ACO		 12344 intel_encoder = to_intel_encoder(connector->encoder);
12345 intel_encoder->connectors_active = true;
12346 }
ea9d758d 12347
bd4b4827 12348 break;
ea9d758d
DV		 12349 }
12350 }
12351
12352}
12353
3bd26263 12354static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12355{
3bd26263 12356 int diff;
f1f644dc
JB		 12357
12358 if (clock1 == clock2)
12359 return true;
12360
12361 if (!clock1 || !clock2)
12362 return false;
12363
12364 diff = abs(clock1 - clock2);
12365
12366 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12367 return true;
12368
12369 return false;
12370}
12371
25c5b266
DV		 12372#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12373 list_for_each_entry((intel_crtc), \
12374 &(dev)->mode_config.crtc_list, \
12375 base.head) \
0973f18f 12376 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12377
0e8ffe1b 12378static bool
2fa2fe9a 12379intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12380 struct intel_crtc_state *current_config,
12381 struct intel_crtc_state *pipe_config)
0e8ffe1b 12382{
66e985c0
DV		 12383#define PIPE_CONF_CHECK_X(name) \
12384 if (current_config->name != pipe_config->name) { \
12385 DRM_ERROR("mismatch in " #name " " \
12386 "(expected 0x%08x, found 0x%08x)\n", \
12387 current_config->name, \
12388 pipe_config->name); \
12389 return false; \
12390 }
12391
08a24034
DV		 12392#define PIPE_CONF_CHECK_I(name) \
12393 if (current_config->name != pipe_config->name) { \
12394 DRM_ERROR("mismatch in " #name " " \
12395 "(expected %i, found %i)\n", \
12396 current_config->name, \
12397 pipe_config->name); \
12398 return false; \
88adfff1
DV		 12399 }
12400
b95af8be
VK		 12401/* This is required for BDW+ where there is only one set of registers for
12402 * switching between high and low RR.
12403 * This macro can be used whenever a comparison has to be made between one
12404 * hw state and multiple sw state variables.
12405 */
12406#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12407 if ((current_config->name != pipe_config->name) && \
12408 (current_config->alt_name != pipe_config->name)) { \
12409 DRM_ERROR("mismatch in " #name " " \
12410 "(expected %i or %i, found %i)\n", \
12411 current_config->name, \
12412 current_config->alt_name, \
12413 pipe_config->name); \
12414 return false; \
12415 }
12416
1bd1bd80
DV		 12417#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12418 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12419 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12420 "(expected %i, found %i)\n", \
12421 current_config->name & (mask), \
12422 pipe_config->name & (mask)); \
12423 return false; \
12424 }
12425
5e550656
VS		 12426#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12427 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12428 DRM_ERROR("mismatch in " #name " " \
12429 "(expected %i, found %i)\n", \
12430 current_config->name, \
12431 pipe_config->name); \
12432 return false; \
12433 }
12434
bb760063
DV		 12435#define PIPE_CONF_QUIRK(quirk) \
12436 ((current_config->quirks | pipe_config->quirks) & (quirk))
12437
eccb140b
DV		 12438 PIPE_CONF_CHECK_I(cpu_transcoder);
12439
08a24034
DV		 12440 PIPE_CONF_CHECK_I(has_pch_encoder);
12441 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12442 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12443 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12444 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12445 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12446 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12447
eb14cb74 12448 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12449
12450 if (INTEL_INFO(dev)->gen < 8) {
12451 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12452 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12453 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12454 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12455 PIPE_CONF_CHECK_I(dp_m_n.tu);
12456
12457 if (current_config->has_drrs) {
12458 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12459 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12460 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12461 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12462 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12463 }
12464 } else {
12465 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12466 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12467 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12468 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12469 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12470 }
eb14cb74 12471
2d112de7
ACO		 12472 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12473 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12474 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12475 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12476 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12477 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12478
2d112de7
ACO		 12479 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12480 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12481 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12482 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12483 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12484 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12485
c93f54cf 12486 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12487 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12488 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12489 IS_VALLEYVIEW(dev))
12490 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12491 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12492
9ed109a7
DV		 12493 PIPE_CONF_CHECK_I(has_audio);
12494
2d112de7 12495 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12496 DRM_MODE_FLAG_INTERLACE);
12497
bb760063 12498 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12499 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12500 DRM_MODE_FLAG_PHSYNC);
2d112de7 12501 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12502 DRM_MODE_FLAG_NHSYNC);
2d112de7 12503 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12504 DRM_MODE_FLAG_PVSYNC);
2d112de7 12505 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12506 DRM_MODE_FLAG_NVSYNC);
12507 }
045ac3b5 12508
37327abd
VS		 12509 PIPE_CONF_CHECK_I(pipe_src_w);
12510 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12511
9953599b
DV		 12512 /*
12513 * FIXME: BIOS likes to set up a cloned config with lvds+external
12514 * screen. Since we don't yet re-compute the pipe config when moving
12515 * just the lvds port away to another pipe the sw tracking won't match.
12516 *
12517 * Proper atomic modesets with recomputed global state will fix this.
12518 * Until then just don't check gmch state for inherited modes.
12519 */
12520 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12521 PIPE_CONF_CHECK_I(gmch_pfit.control);
12522 /* pfit ratios are autocomputed by the hw on gen4+ */
12523 if (INTEL_INFO(dev)->gen < 4)
12524 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12525 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12526 }
12527
fd4daa9c
CW		 12528 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12529 if (current_config->pch_pfit.enabled) {
12530 PIPE_CONF_CHECK_I(pch_pfit.pos);
12531 PIPE_CONF_CHECK_I(pch_pfit.size);
12532 }
2fa2fe9a 12533
a1b2278e
CK		 12534 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12535
e59150dc
JB		 12536 /* BDW+ don't expose a synchronous way to read the state */
12537 if (IS_HASWELL(dev))
12538 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12539
282740f7
VS		 12540 PIPE_CONF_CHECK_I(double_wide);
12541
26804afd
DV		 12542 PIPE_CONF_CHECK_X(ddi_pll_sel);
12543
c0d43d62 12544 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12545 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12546 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12547 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12548 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12549 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12550 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12551 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12552 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12553
42571aef
VS		 12554 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12555 PIPE_CONF_CHECK_I(pipe_bpp);
12556
2d112de7 12557 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12558 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12559
66e985c0 12560#undef PIPE_CONF_CHECK_X
08a24034 12561#undef PIPE_CONF_CHECK_I
b95af8be 12562#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12563#undef PIPE_CONF_CHECK_FLAGS
5e550656 12564#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12565#undef PIPE_CONF_QUIRK
88adfff1 12566
0e8ffe1b
DV		 12567 return true;
12568}
12569
08db6652
DL		 12570static void check_wm_state(struct drm_device *dev)
12571{
12572 struct drm_i915_private *dev_priv = dev->dev_private;
12573 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12574 struct intel_crtc *intel_crtc;
12575 int plane;
12576
12577 if (INTEL_INFO(dev)->gen < 9)
12578 return;
12579
12580 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12581 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12582
12583 for_each_intel_crtc(dev, intel_crtc) {
12584 struct skl_ddb_entry *hw_entry, *sw_entry;
12585 const enum pipe pipe = intel_crtc->pipe;
12586
12587 if (!intel_crtc->active)
12588 continue;
12589
12590 /* planes */
dd740780 12591 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12592 hw_entry = &hw_ddb.plane[pipe][plane];
12593 sw_entry = &sw_ddb->plane[pipe][plane];
12594
12595 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12596 continue;
12597
12598 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12599 "(expected (%u,%u), found (%u,%u))\n",
12600 pipe_name(pipe), plane + 1,
12601 sw_entry->start, sw_entry->end,
12602 hw_entry->start, hw_entry->end);
12603 }
12604
12605 /* cursor */
12606 hw_entry = &hw_ddb.cursor[pipe];
12607 sw_entry = &sw_ddb->cursor[pipe];
12608
12609 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12610 continue;
12611
12612 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12613 "(expected (%u,%u), found (%u,%u))\n",
12614 pipe_name(pipe),
12615 sw_entry->start, sw_entry->end,
12616 hw_entry->start, hw_entry->end);
12617 }
12618}
12619
91d1b4bd
DV		 12620static void
12621check_connector_state(struct drm_device *dev)
8af6cf88 12622{
8af6cf88
DV		 12623 struct intel_connector *connector;
12624
3a3371ff 12625 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12626 /* This also checks the encoder/connector hw state with the
12627 * ->get_hw_state callbacks. */
12628 intel_connector_check_state(connector);
12629
e2c719b7 12630 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12631 "connector's staged encoder doesn't match current encoder\n");
12632 }
91d1b4bd
DV		 12633}
12634
12635static void
12636check_encoder_state(struct drm_device *dev)
12637{
12638 struct intel_encoder *encoder;
12639 struct intel_connector *connector;
8af6cf88 12640
b2784e15 12641 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12642 bool enabled = false;
12643 bool active = false;
12644 enum pipe pipe, tracked_pipe;
12645
12646 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12647 encoder->base.base.id,
8e329a03 12648 encoder->base.name);
8af6cf88 12649
e2c719b7 12650 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12651 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12652 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12653 "encoder's active_connectors set, but no crtc\n");
12654
3a3371ff 12655 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12656 if (connector->base.encoder != &encoder->base)
12657 continue;
12658 enabled = true;
12659 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12660 active = true;
12661 }
0e32b39c
DA		 12662 /*
12663 * for MST connectors if we unplug the connector is gone
12664 * away but the encoder is still connected to a crtc
12665 * until a modeset happens in response to the hotplug.
12666 */
12667 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12668 continue;
12669
e2c719b7 12670 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12671 "encoder's enabled state mismatch "
12672 "(expected %i, found %i)\n",
12673 !!encoder->base.crtc, enabled);
e2c719b7 12674 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12675 "active encoder with no crtc\n");
12676
e2c719b7 12677 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12678 "encoder's computed active state doesn't match tracked active state "
12679 "(expected %i, found %i)\n", active, encoder->connectors_active);
12680
12681 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12682 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12683 "encoder's hw state doesn't match sw tracking "
12684 "(expected %i, found %i)\n",
12685 encoder->connectors_active, active);
12686
12687 if (!encoder->base.crtc)
12688 continue;
12689
12690 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12691 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12692 "active encoder's pipe doesn't match"
12693 "(expected %i, found %i)\n",
12694 tracked_pipe, pipe);
12695
12696 }
91d1b4bd
DV		 12697}
12698
12699static void
12700check_crtc_state(struct drm_device *dev)
12701{
fbee40df 12702 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12703 struct intel_crtc *crtc;
12704 struct intel_encoder *encoder;
5cec258b 12705 struct intel_crtc_state pipe_config;
8af6cf88 12706
d3fcc808 12707 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12708 bool enabled = false;
12709 bool active = false;
12710
045ac3b5
JB		 12711 memset(&pipe_config, 0, sizeof(pipe_config));
12712
8af6cf88
DV		 12713 DRM_DEBUG_KMS("[CRTC:%d]\n",
12714 crtc->base.base.id);
12715
83d65738 12716 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12717 "active crtc, but not enabled in sw tracking\n");
12718
b2784e15 12719 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12720 if (encoder->base.crtc != &crtc->base)
12721 continue;
12722 enabled = true;
12723 if (encoder->connectors_active)
12724 active = true;
12725 }
6c49f241 12726
e2c719b7 12727 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12728 "crtc's computed active state doesn't match tracked active state "
12729 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12730 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12731 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12732 "(expected %i, found %i)\n", enabled,
12733 crtc->base.state->enable);
8af6cf88 12734
0e8ffe1b
DV		 12735 active = dev_priv->display.get_pipe_config(crtc,
12736 &pipe_config);
d62cf62a 12737
b6b5d049
VS		 12738 /* hw state is inconsistent with the pipe quirk */
12739 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12740 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12741 active = crtc->active;
12742
b2784e15 12743 for_each_intel_encoder(dev, encoder) {
3eaba51c 12744 enum pipe pipe;
6c49f241
DV		 12745 if (encoder->base.crtc != &crtc->base)
12746 continue;
1d37b689 12747 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12748 encoder->get_config(encoder, &pipe_config);
12749 }
12750
e2c719b7 12751 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12752 "crtc active state doesn't match with hw state "
12753 "(expected %i, found %i)\n", crtc->active, active);
12754
c0b03411 12755 if (active &&
6e3c9717 12756 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12757 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12758 intel_dump_pipe_config(crtc, &pipe_config,
12759 "[hw state]");
6e3c9717 12760 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12761 "[sw state]");
12762 }
8af6cf88
DV		 12763 }
12764}
12765
91d1b4bd
DV		 12766static void
12767check_shared_dpll_state(struct drm_device *dev)
12768{
fbee40df 12769 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12770 struct intel_crtc *crtc;
12771 struct intel_dpll_hw_state dpll_hw_state;
12772 int i;
5358901f
DV		 12773
12774 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12775 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12776 int enabled_crtcs = 0, active_crtcs = 0;
12777 bool active;
12778
12779 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12780
12781 DRM_DEBUG_KMS("%s\n", pll->name);
12782
12783 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12784
e2c719b7 12785 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12786 "more active pll users than references: %i vs %i\n",
3e369b76 12787 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12788 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12789 "pll in active use but not on in sw tracking\n");
e2c719b7 12790 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12791 "pll in on but not on in use in sw tracking\n");
e2c719b7 12792 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12793 "pll on state mismatch (expected %i, found %i)\n",
12794 pll->on, active);
12795
d3fcc808 12796 for_each_intel_crtc(dev, crtc) {
83d65738 12797 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12798 enabled_crtcs++;
12799 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12800 active_crtcs++;
12801 }
e2c719b7 12802 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12803 "pll active crtcs mismatch (expected %i, found %i)\n",
12804 pll->active, active_crtcs);
e2c719b7 12805 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12806 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12807 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12808
e2c719b7 12809 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12810 sizeof(dpll_hw_state)),
12811 "pll hw state mismatch\n");
5358901f 12812 }
8af6cf88
DV		 12813}
12814
91d1b4bd
DV		 12815void
12816intel_modeset_check_state(struct drm_device *dev)
12817{
08db6652 12818 check_wm_state(dev);
91d1b4bd
DV		 12819 check_connector_state(dev);
12820 check_encoder_state(dev);
12821 check_crtc_state(dev);
12822 check_shared_dpll_state(dev);
12823}
12824
5cec258b 12825void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12826 int dotclock)
12827{
12828 /*
12829 * FDI already provided one idea for the dotclock.
12830 * Yell if the encoder disagrees.
12831 */
2d112de7 12832 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12833 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12834 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12835}
12836
80715b2f
VS		 12837static void update_scanline_offset(struct intel_crtc *crtc)
12838{
12839 struct drm_device *dev = crtc->base.dev;
12840
12841 /*
12842 * The scanline counter increments at the leading edge of hsync.
12843 *
12844 * On most platforms it starts counting from vtotal-1 on the
12845 * first active line. That means the scanline counter value is
12846 * always one less than what we would expect. Ie. just after
12847 * start of vblank, which also occurs at start of hsync (on the
12848 * last active line), the scanline counter will read vblank_start-1.
12849 *
12850 * On gen2 the scanline counter starts counting from 1 instead
12851 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12852 * to keep the value positive), instead of adding one.
12853 *
12854 * On HSW+ the behaviour of the scanline counter depends on the output
12855 * type. For DP ports it behaves like most other platforms, but on HDMI
12856 * there's an extra 1 line difference. So we need to add two instead of
12857 * one to the value.
12858 */
12859 if (IS_GEN2(dev)) {
6e3c9717 12860 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12861 int vtotal;
12862
12863 vtotal = mode->crtc_vtotal;
12864 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12865 vtotal /= 2;
12866
12867 crtc->scanline_offset = vtotal - 1;
12868 } else if (HAS_DDI(dev) &&
409ee761 12869 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12870 crtc->scanline_offset = 2;
12871 } else
12872 crtc->scanline_offset = 1;
12873}
12874
5cec258b 12875static struct intel_crtc_state *
7f27126e 12876intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12877 struct drm_atomic_state *state)
7f27126e 12878{
548ee15b 12879 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12880 int ret = 0;
12881
12882 ret = drm_atomic_add_affected_connectors(state, crtc);
12883 if (ret)
12884 return ERR_PTR(ret);
7f27126e 12885
8c7b5ccb
ACO		 12886 ret = drm_atomic_helper_check_modeset(state->dev, state);
12887 if (ret)
12888 return ERR_PTR(ret);
7f27126e 12889
7f27126e
JB		 12890 /*
12891 * Note this needs changes when we start tracking multiple modes
12892 * and crtcs. At that point we'll need to compute the whole config
12893 * (i.e. one pipe_config for each crtc) rather than just the one
12894 * for this crtc.
12895 */
548ee15b
ACO		 12896 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12897 if (IS_ERR(pipe_config))
12898 return pipe_config;
83a57153 12899
4fed33f6 12900 if (!pipe_config->base.enable)
548ee15b 12901 return pipe_config;
7f27126e 12902
8c7b5ccb 12903 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12904 if (ret)
12905 return ERR_PTR(ret);
12906
8d8c9b51
ACO		 12907 /* Check things that can only be changed through modeset */
12908 if (pipe_config->has_audio !=
12909 to_intel_crtc(crtc)->config->has_audio)
12910 pipe_config->base.mode_changed = true;
12911
12912 /*
12913 * Note we have an issue here with infoframes: current code
12914 * only updates them on the full mode set path per hw
12915 * requirements. So here we should be checking for any
12916 * required changes and forcing a mode set.
12917 */
12918
548ee15b 12919 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12920
8c7b5ccb
ACO		 12921 ret = drm_atomic_helper_check_planes(state->dev, state);
12922 if (ret)
12923 return ERR_PTR(ret);
12924
548ee15b 12925 return pipe_config;
7f27126e
JB		 12926}
12927
0a9ab303 12928static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12929{
225da59b 12930 struct drm_device *dev = state->dev;
ed6739ef 12931 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12932 unsigned clear_pipes = 0;
ed6739ef 12933 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12934 struct intel_crtc_state *intel_crtc_state;
12935 struct drm_crtc *crtc;
12936 struct drm_crtc_state *crtc_state;
ed6739ef 12937 int ret = 0;
0a9ab303 12938 int i;
ed6739ef
ACO		 12939
12940 if (!dev_priv->display.crtc_compute_clock)
12941 return 0;
12942
0a9ab303
ACO		 12943 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12944 intel_crtc = to_intel_crtc(crtc);
4978cc93 12945 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12946
4978cc93 12947 if (needs_modeset(crtc_state)) {
0a9ab303 12948 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12949 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12950 }
0a9ab303
ACO		 12951 }
12952
ed6739ef
ACO		 12953 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12954 if (ret)
12955 goto done;
12956
0a9ab303
ACO		 12957 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12958 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12959 continue;
12960
0a9ab303
ACO		 12961 intel_crtc = to_intel_crtc(crtc);
12962 intel_crtc_state = to_intel_crtc_state(crtc_state);
12963
ed6739ef 12964 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12965 intel_crtc_state);
ed6739ef
ACO		 12966 if (ret) {
12967 intel_shared_dpll_abort_config(dev_priv);
12968 goto done;
12969 }
12970 }
12971
12972done:
12973 return ret;
12974}
12975
054518dd
ACO		 12976/* Code that should eventually be part of atomic_check() */
12977static int __intel_set_mode_checks(struct drm_atomic_state *state)
12978{
12979 struct drm_device *dev = state->dev;
12980 int ret;
12981
12982 /*
12983 * See if the config requires any additional preparation, e.g.
12984 * to adjust global state with pipes off. We need to do this
12985 * here so we can get the modeset_pipe updated config for the new
12986 * mode set on this crtc. For other crtcs we need to use the
12987 * adjusted_mode bits in the crtc directly.
12988 */
b432e5cf
VS		 12989 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12990 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12991 ret = valleyview_modeset_global_pipes(state);
12992 else
12993 ret = broadwell_modeset_global_pipes(state);
12994
054518dd
ACO		 12995 if (ret)
12996 return ret;
12997 }
12998
12999 ret = __intel_set_mode_setup_plls(state);
13000 if (ret)
13001 return ret;
13002
13003 return 0;
13004}
13005
0a9ab303 13006static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 13007 struct intel_crtc_state *pipe_config)
a6778b3c 13008{
0a9ab303 13009 struct drm_device *dev = modeset_crtc->dev;
fbee40df 13010 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 13011 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 13012 struct drm_crtc *crtc;
13013 struct drm_crtc_state *crtc_state;
c0c36b94 13014 int ret = 0;
0a9ab303 13015 int i;
a6778b3c 13016
054518dd
ACO		 13017 ret = __intel_set_mode_checks(state);
13018 if (ret < 0)
13019 return ret;
13020
d4afb8cc
ACO		 13021 ret = drm_atomic_helper_prepare_planes(dev, state);
13022 if (ret)
13023 return ret;
13024
0a9ab303
ACO		 13025 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13026 if (!needs_modeset(crtc_state))
13027 continue;
460da916 13028
0a9ab303
ACO		 13029 if (!crtc_state->enable) {
13030 intel_crtc_disable(crtc);
13031 } else if (crtc->state->enable) {
13032 intel_crtc_disable_planes(crtc);
13033 dev_priv->display.crtc_disable(crtc);
ce22dba9 13034 }
ea9d758d 13035 }
a6778b3c 13036
6c4c86f5
DV		 13037 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
13038 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 13039 *
13040 * Note we'll need to fix this up when we start tracking multiple
13041 * pipes; here we assume a single modeset_pipe and only track the
13042 * single crtc and mode.
f6e5b160 13043 */
0a9ab303 13044 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 13045 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS		 13046
13047 /*
13048 * Calculate and store various constants which
13049 * are later needed by vblank and swap-completion
13050 * timestamping. They are derived from true hwmode.
13051 */
0a9ab303 13052 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 13053 &pipe_config->base.adjusted_mode);
b8cecdf5 13054 }
7758a113 13055
ea9d758d
DV		 13056 /* Only after disabling all output pipelines that will be changed can we
13057 * update the the output configuration. */
0a9ab303 13058 intel_modeset_update_state(state);
f6e5b160 13059
a821fc46
ACO		 13060 /* The state has been swaped above, so state actually contains the
13061 * old state now. */
13062
304603f4 13063 modeset_update_crtc_power_domains(state);
47fab737 13064
d4afb8cc 13065 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 13066
13067 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13068 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 13069 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 13070 continue;
13071
13072 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 13073
0a9ab303
ACO		 13074 dev_priv->display.crtc_enable(crtc);
13075 intel_crtc_enable_planes(crtc);
80715b2f 13076 }
a6778b3c 13077
a6778b3c 13078 /* FIXME: add subpixel order */
83a57153 13079
d4afb8cc
ACO		 13080 drm_atomic_helper_cleanup_planes(dev, state);
13081
2bfb4627
ACO		 13082 drm_atomic_state_free(state);
13083
9eb45f22 13084 return 0;
f6e5b160
CW		 13085}
13086
0a9ab303 13087static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 13088 struct intel_crtc_state *pipe_config)
f30da187
DV		 13089{
13090 int ret;
13091
8c7b5ccb 13092 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 13093
13094 if (ret == 0)
13095 intel_modeset_check_state(crtc->dev);
13096
13097 return ret;
13098}
13099
7f27126e 13100static int intel_set_mode(struct drm_crtc *crtc,
83a57153 13101 struct drm_atomic_state *state)
7f27126e 13102{
5cec258b 13103 struct intel_crtc_state *pipe_config;
83a57153 13104 int ret = 0;
7f27126e 13105
8c7b5ccb 13106 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 13107 if (IS_ERR(pipe_config)) {
13108 ret = PTR_ERR(pipe_config);
13109 goto out;
13110 }
13111
8c7b5ccb 13112 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 13113 if (ret)
13114 goto out;
7f27126e 13115
83a57153
ACO		 13116out:
13117 return ret;
7f27126e
JB		 13118}
13119
c0c36b94
CW		 13120void intel_crtc_restore_mode(struct drm_crtc *crtc)
13121{
83a57153
ACO		 13122 struct drm_device *dev = crtc->dev;
13123 struct drm_atomic_state *state;
4be07317 13124 struct intel_crtc *intel_crtc;
83a57153
ACO		 13125 struct intel_encoder *encoder;
13126 struct intel_connector *connector;
13127 struct drm_connector_state *connector_state;
4be07317 13128 struct intel_crtc_state *crtc_state;
2bfb4627 13129 int ret;
83a57153
ACO		 13130
13131 state = drm_atomic_state_alloc(dev);
13132 if (!state) {
13133 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13134 crtc->base.id);
13135 return;
13136 }
13137
13138 state->acquire_ctx = dev->mode_config.acquire_ctx;
13139
13140 /* The force restore path in the HW readout code relies on the staged
13141 * config still keeping the user requested config while the actual
13142 * state has been overwritten by the configuration read from HW. We
13143 * need to copy the staged config to the atomic state, otherwise the
13144 * mode set will just reapply the state the HW is already in. */
13145 for_each_intel_encoder(dev, encoder) {
13146 if (&encoder->new_crtc->base != crtc)
13147 continue;
13148
13149 for_each_intel_connector(dev, connector) {
13150 if (connector->new_encoder != encoder)
13151 continue;
13152
13153 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13154 if (IS_ERR(connector_state)) {
13155 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13156 connector->base.base.id,
13157 connector->base.name,
13158 PTR_ERR(connector_state));
13159 continue;
13160 }
13161
13162 connector_state->crtc = crtc;
13163 connector_state->best_encoder = &encoder->base;
13164 }
13165 }
13166
4be07317
ACO		 13167 for_each_intel_crtc(dev, intel_crtc) {
13168 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13169 continue;
13170
13171 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13172 if (IS_ERR(crtc_state)) {
13173 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13174 intel_crtc->base.base.id,
13175 PTR_ERR(crtc_state));
13176 continue;
13177 }
13178
49d6fa21
ML		 13179 crtc_state->base.active = crtc_state->base.enable =
13180 intel_crtc->new_enabled;
8c7b5ccb
ACO		 13181
13182 if (&intel_crtc->base == crtc)
13183 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 13184 }
13185
d3a40d1b
ACO		 13186 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13187 crtc->primary->fb, crtc->x, crtc->y);
13188
2bfb4627
ACO		 13189 ret = intel_set_mode(crtc, state);
13190 if (ret)
13191 drm_atomic_state_free(state);
c0c36b94
CW		 13192}
13193
25c5b266
DV		 13194#undef for_each_intel_crtc_masked
13195
b7885264
ACO		 13196static bool intel_connector_in_mode_set(struct intel_connector *connector,
13197 struct drm_mode_set *set)
13198{
13199 int ro;
13200
13201 for (ro = 0; ro < set->num_connectors; ro++)
13202 if (set->connectors[ro] == &connector->base)
13203 return true;
13204
13205 return false;
13206}
13207
2e431051 13208static int
9a935856
DV		 13209intel_modeset_stage_output_state(struct drm_device *dev,
13210 struct drm_mode_set *set,
944b0c76 13211 struct drm_atomic_state *state)
50f56119 13212{
9a935856 13213 struct intel_connector *connector;
d5432a9d 13214 struct drm_connector *drm_connector;
944b0c76 13215 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13216 struct drm_crtc *crtc;
13217 struct drm_crtc_state *crtc_state;
13218 int i, ret;
50f56119 13219
9abdda74 13220 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13221 * of connectors. For paranoia, double-check this. */
13222 WARN_ON(!set->fb && (set->num_connectors != 0));
13223 WARN_ON(set->fb && (set->num_connectors == 0));
13224
3a3371ff 13225 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13226 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13227
d5432a9d
ACO		 13228 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13229 continue;
13230
13231 connector_state =
13232 drm_atomic_get_connector_state(state, &connector->base);
13233 if (IS_ERR(connector_state))
13234 return PTR_ERR(connector_state);
13235
b7885264
ACO		 13236 if (in_mode_set) {
13237 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13238 connector_state->best_encoder =
13239 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13240 }
13241
d5432a9d 13242 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13243 continue;
13244
9a935856
DV		 13245 /* If we disable the crtc, disable all its connectors. Also, if
13246 * the connector is on the changing crtc but not on the new
13247 * connector list, disable it. */
b7885264 13248 if (!set->fb || !in_mode_set) {
d5432a9d 13249 connector_state->best_encoder = NULL;
9a935856
DV		 13250
13251 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13252 connector->base.base.id,
c23cc417 13253 connector->base.name);
9a935856 13254 }
50f56119 13255 }
9a935856 13256 /* connector->new_encoder is now updated for all connectors. */
50f56119 13257
d5432a9d
ACO		 13258 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13259 connector = to_intel_connector(drm_connector);
13260
13261 if (!connector_state->best_encoder) {
13262 ret = drm_atomic_set_crtc_for_connector(connector_state,
13263 NULL);
13264 if (ret)
13265 return ret;
7668851f 13266
50f56119 13267 continue;
d5432a9d 13268 }
50f56119 13269
d5432a9d
ACO		 13270 if (intel_connector_in_mode_set(connector, set)) {
13271 struct drm_crtc *crtc = connector->base.state->crtc;
13272
13273 /* If this connector was in a previous crtc, add it
13274 * to the state. We might need to disable it. */
13275 if (crtc) {
13276 crtc_state =
13277 drm_atomic_get_crtc_state(state, crtc);
13278 if (IS_ERR(crtc_state))
13279 return PTR_ERR(crtc_state);
13280 }
13281
13282 ret = drm_atomic_set_crtc_for_connector(connector_state,
13283 set->crtc);
13284 if (ret)
13285 return ret;
13286 }
50f56119
DV		 13287
13288 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13289 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13290 connector_state->crtc)) {
5e2b584e 13291 return -EINVAL;
50f56119 13292 }
944b0c76 13293
9a935856
DV		 13294 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13295 connector->base.base.id,
c23cc417 13296 connector->base.name,
d5432a9d 13297 connector_state->crtc->base.id);
944b0c76 13298
d5432a9d
ACO		 13299 if (connector_state->best_encoder != &connector->encoder->base)
13300 connector->encoder =
13301 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13302 }
7668851f 13303
d5432a9d 13304 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13305 bool has_connectors;
13306
d5432a9d
ACO		 13307 ret = drm_atomic_add_affected_connectors(state, crtc);
13308 if (ret)
13309 return ret;
4be07317 13310
49d6fa21
ML		 13311 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13312 if (has_connectors != crtc_state->enable)
13313 crtc_state->enable =
13314 crtc_state->active = has_connectors;
7668851f
VS		 13315 }
13316
8c7b5ccb
ACO		 13317 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13318 set->fb, set->x, set->y);
13319 if (ret)
13320 return ret;
13321
13322 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13323 if (IS_ERR(crtc_state))
13324 return PTR_ERR(crtc_state);
13325
13326 if (set->mode)
13327 drm_mode_copy(&crtc_state->mode, set->mode);
13328
13329 if (set->num_connectors)
13330 crtc_state->active = true;
13331
2e431051
DV		 13332 return 0;
13333}
13334
bb546623
ACO		 13335static bool primary_plane_visible(struct drm_crtc *crtc)
13336{
13337 struct intel_plane_state *plane_state =
13338 to_intel_plane_state(crtc->primary->state);
13339
13340 return plane_state->visible;
13341}
13342
2e431051
DV		 13343static int intel_crtc_set_config(struct drm_mode_set *set)
13344{
13345 struct drm_device *dev;
83a57153 13346 struct drm_atomic_state *state = NULL;
5cec258b 13347 struct intel_crtc_state *pipe_config;
bb546623 13348 bool primary_plane_was_visible;
2e431051 13349 int ret;
2e431051 13350
8d3e375e
DV		 13351 BUG_ON(!set);
13352 BUG_ON(!set->crtc);
13353 BUG_ON(!set->crtc->helper_private);
2e431051 13354
7e53f3a4
DV		 13355 /* Enforce sane interface api - has been abused by the fb helper. */
13356 BUG_ON(!set->mode && set->fb);
13357 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13358
2e431051
DV		 13359 if (set->fb) {
13360 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13361 set->crtc->base.id, set->fb->base.id,
13362 (int)set->num_connectors, set->x, set->y);
13363 } else {
13364 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13365 }
13366
13367 dev = set->crtc->dev;
13368
83a57153 13369 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13370 if (!state)
13371 return -ENOMEM;
83a57153
ACO		 13372
13373 state->acquire_ctx = dev->mode_config.acquire_ctx;
13374
462a425a 13375 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13376 if (ret)
7cbf41d6 13377 goto out;
2e431051 13378
8c7b5ccb 13379 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 13380 if (IS_ERR(pipe_config)) {
6ac0483b 13381 ret = PTR_ERR(pipe_config);
7cbf41d6 13382 goto out;
20664591 13383 }
50f52756 13384
1f9954d0
JB		 13385 intel_update_pipe_size(to_intel_crtc(set->crtc));
13386
bb546623
ACO		 13387 primary_plane_was_visible = primary_plane_visible(set->crtc);
13388
8c7b5ccb 13389 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 13390
13391 if (ret == 0 &&
13392 pipe_config->base.enable &&
13393 pipe_config->base.planes_changed &&
13394 !needs_modeset(&pipe_config->base)) {
3b150f08 13395 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 13396
13397 /*
13398 * We need to make sure the primary plane is re-enabled if it
13399 * has previously been turned off.
13400 */
bb546623
ACO		 13401 if (ret == 0 && !primary_plane_was_visible &&
13402 primary_plane_visible(set->crtc)) {
3b150f08 13403 WARN_ON(!intel_crtc->active);
87d4300a 13404 intel_post_enable_primary(set->crtc);
3b150f08
MR		 13405 }
13406
7ca51a3a
JB		 13407 /*
13408 * In the fastboot case this may be our only check of the
13409 * state after boot. It would be better to only do it on
13410 * the first update, but we don't have a nice way of doing that
13411 * (and really, set_config isn't used much for high freq page
13412 * flipping, so increasing its cost here shouldn't be a big
13413 * deal).
13414 */
d330a953 13415 if (i915.fastboot && ret == 0)
7ca51a3a 13416 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 13417 }
13418
2d05eae1 13419 if (ret) {
bf67dfeb
DV		 13420 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13421 set->crtc->base.id, ret);
2d05eae1 13422 }
50f56119 13423
7cbf41d6 13424out:
2bfb4627
ACO		 13425 if (ret)
13426 drm_atomic_state_free(state);
50f56119
DV		 13427 return ret;
13428}
f6e5b160
CW		 13429
13430static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13431 .gamma_set = intel_crtc_gamma_set,
50f56119 13432 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13433 .destroy = intel_crtc_destroy,
13434 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13435 .atomic_duplicate_state = intel_crtc_duplicate_state,
13436 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13437};
13438
5358901f
DV		 13439static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13440 struct intel_shared_dpll *pll,
13441 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13442{
5358901f 13443 uint32_t val;
ee7b9f93 13444
f458ebbc 13445 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13446 return false;
13447
5358901f 13448 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13449 hw_state->dpll = val;
13450 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13451 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13452
13453 return val & DPLL_VCO_ENABLE;
13454}
13455
15bdd4cf
DV		 13456static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13457 struct intel_shared_dpll *pll)
13458{
3e369b76
ACO		 13459 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13460 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13461}
13462
e7b903d2
DV		 13463static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13464 struct intel_shared_dpll *pll)
13465{
e7b903d2 13466 /* PCH refclock must be enabled first */
89eff4be 13467 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13468
3e369b76 13469 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13470
13471 /* Wait for the clocks to stabilize. */
13472 POSTING_READ(PCH_DPLL(pll->id));
13473 udelay(150);
13474
13475 /* The pixel multiplier can only be updated once the
13476 * DPLL is enabled and the clocks are stable.
13477 *
13478 * So write it again.
13479 */
3e369b76 13480 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13481 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13482 udelay(200);
13483}
13484
13485static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13486 struct intel_shared_dpll *pll)
13487{
13488 struct drm_device *dev = dev_priv->dev;
13489 struct intel_crtc *crtc;
e7b903d2
DV		 13490
13491 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13492 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13493 if (intel_crtc_to_shared_dpll(crtc) == pll)
13494 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13495 }
13496
15bdd4cf
DV		 13497 I915_WRITE(PCH_DPLL(pll->id), 0);
13498 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13499 udelay(200);
13500}
13501
46edb027
DV		 13502static char *ibx_pch_dpll_names[] = {
13503 "PCH DPLL A",
13504 "PCH DPLL B",
13505};
13506
7c74ade1 13507static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13508{
e7b903d2 13509 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13510 int i;
13511
7c74ade1 13512 dev_priv->num_shared_dpll = 2;
ee7b9f93 13513
e72f9fbf 13514 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13515 dev_priv->shared_dplls[i].id = i;
13516 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13517 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13518 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13519 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13520 dev_priv->shared_dplls[i].get_hw_state =
13521 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13522 }
13523}
13524
7c74ade1
DV		 13525static void intel_shared_dpll_init(struct drm_device *dev)
13526{
e7b903d2 13527 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13528
b6283055
VS		 13529 intel_update_cdclk(dev);
13530
9cd86933
DV		 13531 if (HAS_DDI(dev))
13532 intel_ddi_pll_init(dev);
13533 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13534 ibx_pch_dpll_init(dev);
13535 else
13536 dev_priv->num_shared_dpll = 0;
13537
13538 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13539}
13540
1fc0a8f7
TU		 13541/**
13542 * intel_wm_need_update - Check whether watermarks need updating
13543 * @plane: drm plane
13544 * @state: new plane state
13545 *
13546 * Check current plane state versus the new one to determine whether
13547 * watermarks need to be recalculated.
13548 *
13549 * Returns true or false.
13550 */
13551bool intel_wm_need_update(struct drm_plane *plane,
13552 struct drm_plane_state *state)
13553{
13554 /* Update watermarks on tiling changes. */
13555 if (!plane->state->fb || !state->fb ||
13556 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13557 plane->state->rotation != state->rotation)
13558 return true;
13559
13560 return false;
13561}
13562
6beb8c23
MR		 13563/**
13564 * intel_prepare_plane_fb - Prepare fb for usage on plane
13565 * @plane: drm plane to prepare for
13566 * @fb: framebuffer to prepare for presentation
13567 *
13568 * Prepares a framebuffer for usage on a display plane. Generally this
13569 * involves pinning the underlying object and updating the frontbuffer tracking
13570 * bits. Some older platforms need special physical address handling for
13571 * cursor planes.
13572 *
13573 * Returns 0 on success, negative error code on failure.
13574 */
13575int
13576intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13577 struct drm_framebuffer *fb,
13578 const struct drm_plane_state *new_state)
465c120c
MR		 13579{
13580 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13581 struct intel_plane *intel_plane = to_intel_plane(plane);
13582 enum pipe pipe = intel_plane->pipe;
13583 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13584 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13585 unsigned frontbuffer_bits = 0;
13586 int ret = 0;
465c120c 13587
ea2c67bb 13588 if (!obj)
465c120c
MR		 13589 return 0;
13590
6beb8c23
MR		 13591 switch (plane->type) {
13592 case DRM_PLANE_TYPE_PRIMARY:
13593 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13594 break;
13595 case DRM_PLANE_TYPE_CURSOR:
13596 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13597 break;
13598 case DRM_PLANE_TYPE_OVERLAY:
13599 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13600 break;
13601 }
465c120c 13602
6beb8c23 13603 mutex_lock(&dev->struct_mutex);
465c120c 13604
6beb8c23
MR		 13605 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13606 INTEL_INFO(dev)->cursor_needs_physical) {
13607 int align = IS_I830(dev) ? 16 * 1024 : 256;
13608 ret = i915_gem_object_attach_phys(obj, align);
13609 if (ret)
13610 DRM_DEBUG_KMS("failed to attach phys object\n");
13611 } else {
82bc3b2d 13612 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13613 }
465c120c 13614
6beb8c23
MR		 13615 if (ret == 0)
13616 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13617
4c34574f 13618 mutex_unlock(&dev->struct_mutex);
465c120c 13619
6beb8c23
MR		 13620 return ret;
13621}
13622
38f3ce3a
MR		 13623/**
13624 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13625 * @plane: drm plane to clean up for
13626 * @fb: old framebuffer that was on plane
13627 *
13628 * Cleans up a framebuffer that has just been removed from a plane.
13629 */
13630void
13631intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13632 struct drm_framebuffer *fb,
13633 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13634{
13635 struct drm_device *dev = plane->dev;
13636 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13637
13638 if (WARN_ON(!obj))
13639 return;
13640
13641 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13642 !INTEL_INFO(dev)->cursor_needs_physical) {
13643 mutex_lock(&dev->struct_mutex);
82bc3b2d 13644 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13645 mutex_unlock(&dev->struct_mutex);
13646 }
465c120c
MR		 13647}
13648
6156a456
CK		 13649int
13650skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13651{
13652 int max_scale;
13653 struct drm_device *dev;
13654 struct drm_i915_private *dev_priv;
13655 int crtc_clock, cdclk;
13656
13657 if (!intel_crtc || !crtc_state)
13658 return DRM_PLANE_HELPER_NO_SCALING;
13659
13660 dev = intel_crtc->base.dev;
13661 dev_priv = dev->dev_private;
13662 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13663 cdclk = dev_priv->display.get_display_clock_speed(dev);
13664
13665 if (!crtc_clock || !cdclk)
13666 return DRM_PLANE_HELPER_NO_SCALING;
13667
13668 /*
13669 * skl max scale is lower of:
13670 * close to 3 but not 3, -1 is for that purpose
13671 * or
13672 * cdclk/crtc_clock
13673 */
13674 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13675
13676 return max_scale;
13677}
13678
465c120c 13679static int
3c692a41
GP		 13680intel_check_primary_plane(struct drm_plane *plane,
13681 struct intel_plane_state *state)
13682{
32b7eeec
MR		 13683 struct drm_device *dev = plane->dev;
13684 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13685 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13686 struct intel_crtc *intel_crtc;
6156a456 13687 struct intel_crtc_state *crtc_state;
2b875c22 13688 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13689 struct drm_rect *dest = &state->dst;
13690 struct drm_rect *src = &state->src;
13691 const struct drm_rect *clip = &state->clip;
d8106366 13692 bool can_position = false;
6156a456
CK		 13693 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13694 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13695 int ret;
13696
ea2c67bb
MR		 13697 crtc = crtc ? crtc : plane->crtc;
13698 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13699 crtc_state = state->base.state ?
13700 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13701
6156a456 13702 if (INTEL_INFO(dev)->gen >= 9) {
225c228a
CK		 13703 /* use scaler when colorkey is not required */
13704 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13705 min_scale = 1;
13706 max_scale = skl_max_scale(intel_crtc, crtc_state);
13707 }
d8106366 13708 can_position = true;
6156a456 13709 }
d8106366 13710
c59cb179
MR		 13711 ret = drm_plane_helper_check_update(plane, crtc, fb,
13712 src, dest, clip,
6156a456
CK		 13713 min_scale,
13714 max_scale,
d8106366
SJ		 13715 can_position, true,
13716 &state->visible);
c59cb179
MR		 13717 if (ret)
13718 return ret;
465c120c 13719
32b7eeec 13720 if (intel_crtc->active) {
b70709a6
ML		 13721 struct intel_plane_state *old_state =
13722 to_intel_plane_state(plane->state);
13723
32b7eeec
MR		 13724 intel_crtc->atomic.wait_for_flips = true;
13725
13726 /*
13727 * FBC does not work on some platforms for rotated
13728 * planes, so disable it when rotation is not 0 and
13729 * update it when rotation is set back to 0.
13730 *
13731 * FIXME: This is redundant with the fbc update done in
13732 * the primary plane enable function except that that
13733 * one is done too late. We eventually need to unify
13734 * this.
13735 */
b70709a6 13736 if (state->visible &&
32b7eeec 13737 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13738 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13739 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13740 intel_crtc->atomic.disable_fbc = true;
13741 }
13742
b70709a6 13743 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13744 /*
13745 * BDW signals flip done immediately if the plane
13746 * is disabled, even if the plane enable is already
13747 * armed to occur at the next vblank :(
13748 */
b70709a6 13749 if (IS_BROADWELL(dev))
32b7eeec
MR		 13750 intel_crtc->atomic.wait_vblank = true;
13751 }
13752
13753 intel_crtc->atomic.fb_bits |=
13754 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13755
13756 intel_crtc->atomic.update_fbc = true;
0fda6568 13757
1fc0a8f7 13758 if (intel_wm_need_update(plane, &state->base))
0fda6568 13759 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13760 }
13761
6156a456
CK		 13762 if (INTEL_INFO(dev)->gen >= 9) {
13763 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13764 to_intel_plane(plane), state, 0);
13765 if (ret)
13766 return ret;
13767 }
13768
14af293f
GP		 13769 return 0;
13770}
13771
13772static void
13773intel_commit_primary_plane(struct drm_plane *plane,
13774 struct intel_plane_state *state)
13775{
2b875c22
MR		 13776 struct drm_crtc *crtc = state->base.crtc;
13777 struct drm_framebuffer *fb = state->base.fb;
13778 struct drm_device *dev = plane->dev;
14af293f 13779 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13780 struct intel_crtc *intel_crtc;
14af293f
GP		 13781 struct drm_rect *src = &state->src;
13782
ea2c67bb
MR		 13783 crtc = crtc ? crtc : plane->crtc;
13784 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13785
13786 plane->fb = fb;
9dc806fc
MR		 13787 crtc->x = src->x1 >> 16;
13788 crtc->y = src->y1 >> 16;
ccc759dc 13789
ccc759dc 13790 if (intel_crtc->active) {
27321ae8 13791 if (state->visible)
ccc759dc
GP		 13792 /* FIXME: kill this fastboot hack */
13793 intel_update_pipe_size(intel_crtc);
465c120c 13794
27321ae8
ML		 13795 dev_priv->display.update_primary_plane(crtc, plane->fb,
13796 crtc->x, crtc->y);
ccc759dc 13797 }
465c120c
MR		 13798}
13799
a8ad0d8e
ML		 13800static void
13801intel_disable_primary_plane(struct drm_plane *plane,
13802 struct drm_crtc *crtc,
13803 bool force)
13804{
13805 struct drm_device *dev = plane->dev;
13806 struct drm_i915_private *dev_priv = dev->dev_private;
13807
a8ad0d8e
ML		 13808 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13809}
13810
32b7eeec 13811static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13812{
32b7eeec 13813 struct drm_device *dev = crtc->dev;
140fd38d 13814 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13816 struct intel_plane *intel_plane;
13817 struct drm_plane *p;
13818 unsigned fb_bits = 0;
13819
13820 /* Track fb's for any planes being disabled */
13821 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13822 intel_plane = to_intel_plane(p);
13823
13824 if (intel_crtc->atomic.disabled_planes &
13825 (1 << drm_plane_index(p))) {
13826 switch (p->type) {
13827 case DRM_PLANE_TYPE_PRIMARY:
13828 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13829 break;
13830 case DRM_PLANE_TYPE_CURSOR:
13831 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13832 break;
13833 case DRM_PLANE_TYPE_OVERLAY:
13834 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13835 break;
13836 }
3c692a41 13837
ea2c67bb
MR		 13838 mutex_lock(&dev->struct_mutex);
13839 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13840 mutex_unlock(&dev->struct_mutex);
13841 }
13842 }
3c692a41 13843
32b7eeec
MR		 13844 if (intel_crtc->atomic.wait_for_flips)
13845 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13846
32b7eeec
MR		 13847 if (intel_crtc->atomic.disable_fbc)
13848 intel_fbc_disable(dev);
3c692a41 13849
32b7eeec
MR		 13850 if (intel_crtc->atomic.pre_disable_primary)
13851 intel_pre_disable_primary(crtc);
3c692a41 13852
32b7eeec
MR		 13853 if (intel_crtc->atomic.update_wm)
13854 intel_update_watermarks(crtc);
3c692a41 13855
32b7eeec 13856 intel_runtime_pm_get(dev_priv);
3c692a41 13857
c34c9ee4
MR		 13858 /* Perform vblank evasion around commit operation */
13859 if (intel_crtc->active)
13860 intel_crtc->atomic.evade =
13861 intel_pipe_update_start(intel_crtc,
13862 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13863}
13864
13865static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13866{
13867 struct drm_device *dev = crtc->dev;
13868 struct drm_i915_private *dev_priv = dev->dev_private;
13869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13870 struct drm_plane *p;
13871
c34c9ee4
MR		 13872 if (intel_crtc->atomic.evade)
13873 intel_pipe_update_end(intel_crtc,
13874 intel_crtc->atomic.start_vbl_count);
3c692a41 13875
140fd38d 13876 intel_runtime_pm_put(dev_priv);
3c692a41 13877
32b7eeec
MR		 13878 if (intel_crtc->atomic.wait_vblank)
13879 intel_wait_for_vblank(dev, intel_crtc->pipe);
13880
13881 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13882
13883 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13884 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13885 intel_fbc_update(dev);
ccc759dc 13886 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13887 }
3c692a41 13888
32b7eeec
MR		 13889 if (intel_crtc->atomic.post_enable_primary)
13890 intel_post_enable_primary(crtc);
3c692a41 13891
32b7eeec
MR		 13892 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13893 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13894 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13895 false, false);
13896
13897 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13898}
13899
cf4c7c12 13900/**
4a3b8769
MR		 13901 * intel_plane_destroy - destroy a plane
13902 * @plane: plane to destroy
cf4c7c12 13903 *
4a3b8769
MR		 13904 * Common destruction function for all types of planes (primary, cursor,
13905 * sprite).
cf4c7c12 13906 */
4a3b8769 13907void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13908{
13909 struct intel_plane *intel_plane = to_intel_plane(plane);
13910 drm_plane_cleanup(plane);
13911 kfree(intel_plane);
13912}
13913
65a3fea0 13914const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13915 .update_plane = drm_atomic_helper_update_plane,
13916 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13917 .destroy = intel_plane_destroy,
c196e1d6 13918 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13919 .atomic_get_property = intel_plane_atomic_get_property,
13920 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13921 .atomic_duplicate_state = intel_plane_duplicate_state,
13922 .atomic_destroy_state = intel_plane_destroy_state,
13923
465c120c
MR		 13924};
13925
13926static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13927 int pipe)
13928{
13929 struct intel_plane *primary;
8e7d688b 13930 struct intel_plane_state *state;
465c120c
MR		 13931 const uint32_t *intel_primary_formats;
13932 int num_formats;
13933
13934 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13935 if (primary == NULL)
13936 return NULL;
13937
8e7d688b
MR		 13938 state = intel_create_plane_state(&primary->base);
13939 if (!state) {
ea2c67bb
MR		 13940 kfree(primary);
13941 return NULL;
13942 }
8e7d688b 13943 primary->base.state = &state->base;
ea2c67bb 13944
465c120c
MR		 13945 primary->can_scale = false;
13946 primary->max_downscale = 1;
6156a456
CK		 13947 if (INTEL_INFO(dev)->gen >= 9) {
13948 primary->can_scale = true;
af99ceda 13949 state->scaler_id = -1;
6156a456 13950 }
465c120c
MR		 13951 primary->pipe = pipe;
13952 primary->plane = pipe;
c59cb179
MR		 13953 primary->check_plane = intel_check_primary_plane;
13954 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13955 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13956 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13957 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13958 primary->plane = !pipe;
13959
6c0fd451
DL		 13960 if (INTEL_INFO(dev)->gen >= 9) {
13961 intel_primary_formats = skl_primary_formats;
13962 num_formats = ARRAY_SIZE(skl_primary_formats);
13963 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13964 intel_primary_formats = i965_primary_formats;
13965 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13966 } else {
13967 intel_primary_formats = i8xx_primary_formats;
13968 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13969 }
13970
13971 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13972 &intel_plane_funcs,
465c120c
MR		 13973 intel_primary_formats, num_formats,
13974 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13975
3b7a5119
SJ		 13976 if (INTEL_INFO(dev)->gen >= 4)
13977 intel_create_rotation_property(dev, primary);
48404c1e 13978
ea2c67bb
MR		 13979 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13980
465c120c
MR		 13981 return &primary->base;
13982}
13983
3b7a5119
SJ		 13984void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13985{
13986 if (!dev->mode_config.rotation_property) {
13987 unsigned long flags = BIT(DRM_ROTATE_0) |
13988 BIT(DRM_ROTATE_180);
13989
13990 if (INTEL_INFO(dev)->gen >= 9)
13991 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13992
13993 dev->mode_config.rotation_property =
13994 drm_mode_create_rotation_property(dev, flags);
13995 }
13996 if (dev->mode_config.rotation_property)
13997 drm_object_attach_property(&plane->base.base,
13998 dev->mode_config.rotation_property,
13999 plane->base.state->rotation);
14000}
14001
3d7d6510 14002static int
852e787c
GP		 14003intel_check_cursor_plane(struct drm_plane *plane,
14004 struct intel_plane_state *state)
3d7d6510 14005{
2b875c22 14006 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 14007 struct drm_device *dev = plane->dev;
2b875c22 14008 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 14009 struct drm_rect *dest = &state->dst;
14010 struct drm_rect *src = &state->src;
14011 const struct drm_rect *clip = &state->clip;
757f9a3e 14012 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 14013 struct intel_crtc *intel_crtc;
757f9a3e
GP		 14014 unsigned stride;
14015 int ret;
3d7d6510 14016
ea2c67bb
MR		 14017 crtc = crtc ? crtc : plane->crtc;
14018 intel_crtc = to_intel_crtc(crtc);
14019
757f9a3e 14020 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 14021 src, dest, clip,
3d7d6510
MR		 14022 DRM_PLANE_HELPER_NO_SCALING,
14023 DRM_PLANE_HELPER_NO_SCALING,
852e787c 14024 true, true, &state->visible);
757f9a3e
GP		 14025 if (ret)
14026 return ret;
14027
14028
14029 /* if we want to turn off the cursor ignore width and height */
14030 if (!obj)
32b7eeec 14031 goto finish;
757f9a3e 14032
757f9a3e 14033 /* Check for which cursor types we support */
ea2c67bb
MR		 14034 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
14035 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14036 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 14037 return -EINVAL;
14038 }
14039
ea2c67bb
MR		 14040 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14041 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 14042 DRM_DEBUG_KMS("buffer is too small\n");
14043 return -ENOMEM;
14044 }
14045
3a656b54 14046 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 14047 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14048 ret = -EINVAL;
14049 }
757f9a3e 14050
32b7eeec
MR		 14051finish:
14052 if (intel_crtc->active) {
3749f463 14053 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 14054 intel_crtc->atomic.update_wm = true;
14055
14056 intel_crtc->atomic.fb_bits |=
14057 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
14058 }
14059
757f9a3e 14060 return ret;
852e787c 14061}
3d7d6510 14062
a8ad0d8e
ML		 14063static void
14064intel_disable_cursor_plane(struct drm_plane *plane,
14065 struct drm_crtc *crtc,
14066 bool force)
14067{
14068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14069
14070 if (!force) {
14071 plane->fb = NULL;
14072 intel_crtc->cursor_bo = NULL;
14073 intel_crtc->cursor_addr = 0;
14074 }
14075
14076 intel_crtc_update_cursor(crtc, false);
14077}
14078
f4a2cf29 14079static void
852e787c
GP		 14080intel_commit_cursor_plane(struct drm_plane *plane,
14081 struct intel_plane_state *state)
14082{
2b875c22 14083 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 14084 struct drm_device *dev = plane->dev;
14085 struct intel_crtc *intel_crtc;
2b875c22 14086 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 14087 uint32_t addr;
852e787c 14088
ea2c67bb
MR		 14089 crtc = crtc ? crtc : plane->crtc;
14090 intel_crtc = to_intel_crtc(crtc);
14091
2b875c22 14092 plane->fb = state->base.fb;
ea2c67bb
MR		 14093 crtc->cursor_x = state->base.crtc_x;
14094 crtc->cursor_y = state->base.crtc_y;
14095
a912f12f
GP		 14096 if (intel_crtc->cursor_bo == obj)
14097 goto update;
4ed91096 14098
f4a2cf29 14099 if (!obj)
a912f12f 14100 addr = 0;
f4a2cf29 14101 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 14102 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 14103 else
a912f12f 14104 addr = obj->phys_handle->busaddr;
852e787c 14105
a912f12f
GP		 14106 intel_crtc->cursor_addr = addr;
14107 intel_crtc->cursor_bo = obj;
14108update:
852e787c 14109
32b7eeec 14110 if (intel_crtc->active)
a912f12f 14111 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 14112}
14113
3d7d6510
MR		 14114static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14115 int pipe)
14116{
14117 struct intel_plane *cursor;
8e7d688b 14118 struct intel_plane_state *state;
3d7d6510
MR		 14119
14120 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14121 if (cursor == NULL)
14122 return NULL;
14123
8e7d688b
MR		 14124 state = intel_create_plane_state(&cursor->base);
14125 if (!state) {
ea2c67bb
MR		 14126 kfree(cursor);
14127 return NULL;
14128 }
8e7d688b 14129 cursor->base.state = &state->base;
ea2c67bb 14130
3d7d6510
MR		 14131 cursor->can_scale = false;
14132 cursor->max_downscale = 1;
14133 cursor->pipe = pipe;
14134 cursor->plane = pipe;
c59cb179
MR		 14135 cursor->check_plane = intel_check_cursor_plane;
14136 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 14137 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 14138
14139 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14140 &intel_plane_funcs,
3d7d6510
MR		 14141 intel_cursor_formats,
14142 ARRAY_SIZE(intel_cursor_formats),
14143 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14144
14145 if (INTEL_INFO(dev)->gen >= 4) {
14146 if (!dev->mode_config.rotation_property)
14147 dev->mode_config.rotation_property =
14148 drm_mode_create_rotation_property(dev,
14149 BIT(DRM_ROTATE_0) |
14150 BIT(DRM_ROTATE_180));
14151 if (dev->mode_config.rotation_property)
14152 drm_object_attach_property(&cursor->base.base,
14153 dev->mode_config.rotation_property,
8e7d688b 14154 state->base.rotation);
4398ad45
VS		 14155 }
14156
af99ceda
CK		 14157 if (INTEL_INFO(dev)->gen >=9)
14158 state->scaler_id = -1;
14159
ea2c67bb
MR		 14160 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14161
3d7d6510
MR		 14162 return &cursor->base;
14163}
14164
549e2bfb
CK		 14165static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14166 struct intel_crtc_state *crtc_state)
14167{
14168 int i;
14169 struct intel_scaler *intel_scaler;
14170 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14171
14172 for (i = 0; i < intel_crtc->num_scalers; i++) {
14173 intel_scaler = &scaler_state->scalers[i];
14174 intel_scaler->in_use = 0;
14175 intel_scaler->id = i;
14176
14177 intel_scaler->mode = PS_SCALER_MODE_DYN;
14178 }
14179
14180 scaler_state->scaler_id = -1;
14181}
14182
b358d0a6 14183static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14184{
fbee40df 14185 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14186 struct intel_crtc *intel_crtc;
f5de6e07 14187 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14188 struct drm_plane *primary = NULL;
14189 struct drm_plane *cursor = NULL;
465c120c 14190 int i, ret;
79e53945 14191
955382f3 14192 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14193 if (intel_crtc == NULL)
14194 return;
14195
f5de6e07
ACO		 14196 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14197 if (!crtc_state)
14198 goto fail;
550acefd
ACO		 14199 intel_crtc->config = crtc_state;
14200 intel_crtc->base.state = &crtc_state->base;
07878248 14201 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14202
549e2bfb
CK		 14203 /* initialize shared scalers */
14204 if (INTEL_INFO(dev)->gen >= 9) {
14205 if (pipe == PIPE_C)
14206 intel_crtc->num_scalers = 1;
14207 else
14208 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14209
14210 skl_init_scalers(dev, intel_crtc, crtc_state);
14211 }
14212
465c120c 14213 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14214 if (!primary)
14215 goto fail;
14216
14217 cursor = intel_cursor_plane_create(dev, pipe);
14218 if (!cursor)
14219 goto fail;
14220
465c120c 14221 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14222 cursor, &intel_crtc_funcs);
14223 if (ret)
14224 goto fail;
79e53945
JB		 14225
14226 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14227 for (i = 0; i < 256; i++) {
14228 intel_crtc->lut_r[i] = i;
14229 intel_crtc->lut_g[i] = i;
14230 intel_crtc->lut_b[i] = i;
14231 }
14232
1f1c2e24
VS		 14233 /*
14234 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14235 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14236 */
80824003
JB		 14237 intel_crtc->pipe = pipe;
14238 intel_crtc->plane = pipe;
3a77c4c4 14239 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14240 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14241 intel_crtc->plane = !pipe;
80824003
JB		 14242 }
14243
4b0e333e
CW		 14244 intel_crtc->cursor_base = ~0;
14245 intel_crtc->cursor_cntl = ~0;
dc41c154 14246 intel_crtc->cursor_size = ~0;
8d7849db 14247
22fd0fab
JB		 14248 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14249 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14250 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14251 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14252
79e53945 14253 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14254
14255 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14256 return;
14257
14258fail:
14259 if (primary)
14260 drm_plane_cleanup(primary);
14261 if (cursor)
14262 drm_plane_cleanup(cursor);
f5de6e07 14263 kfree(crtc_state);
3d7d6510 14264 kfree(intel_crtc);
79e53945
JB		 14265}
14266
752aa88a
JB		 14267enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14268{
14269 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14270 struct drm_device *dev = connector->base.dev;
752aa88a 14271
51fd371b 14272 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14273
d3babd3f 14274 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14275 return INVALID_PIPE;
14276
14277 return to_intel_crtc(encoder->crtc)->pipe;
14278}
14279
08d7b3d1 14280int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14281 struct drm_file *file)
08d7b3d1 14282{
08d7b3d1 14283 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14284 struct drm_crtc *drmmode_crtc;
c05422d5 14285 struct intel_crtc *crtc;
08d7b3d1 14286
7707e653 14287 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14288
7707e653 14289 if (!drmmode_crtc) {
08d7b3d1 14290 DRM_ERROR("no such CRTC id\n");
3f2c2057 14291 return -ENOENT;
08d7b3d1
CW		 14292 }
14293
7707e653 14294 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14295 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14296
c05422d5 14297 return 0;
08d7b3d1
CW		 14298}
14299
66a9278e 14300static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14301{
66a9278e
DV		 14302 struct drm_device *dev = encoder->base.dev;
14303 struct intel_encoder *source_encoder;
79e53945 14304 int index_mask = 0;
79e53945
JB		 14305 int entry = 0;
14306
b2784e15 14307 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14308 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14309 index_mask |= (1 << entry);
14310
79e53945
JB		 14311 entry++;
14312 }
4ef69c7a 14313
79e53945
JB		 14314 return index_mask;
14315}
14316
4d302442
CW		 14317static bool has_edp_a(struct drm_device *dev)
14318{
14319 struct drm_i915_private *dev_priv = dev->dev_private;
14320
14321 if (!IS_MOBILE(dev))
14322 return false;
14323
14324 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14325 return false;
14326
e3589908 14327 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14328 return false;
14329
14330 return true;
14331}
14332
84b4e042
JB		 14333static bool intel_crt_present(struct drm_device *dev)
14334{
14335 struct drm_i915_private *dev_priv = dev->dev_private;
14336
884497ed
DL		 14337 if (INTEL_INFO(dev)->gen >= 9)
14338 return false;
14339
cf404ce4 14340 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14341 return false;
14342
14343 if (IS_CHERRYVIEW(dev))
14344 return false;
14345
14346 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14347 return false;
14348
14349 return true;
14350}
14351
79e53945
JB		 14352static void intel_setup_outputs(struct drm_device *dev)
14353{
725e30ad 14354 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14355 struct intel_encoder *encoder;
cb0953d7 14356 bool dpd_is_edp = false;
79e53945 14357
c9093354 14358 intel_lvds_init(dev);
79e53945 14359
84b4e042 14360 if (intel_crt_present(dev))
79935fca 14361 intel_crt_init(dev);
cb0953d7 14362
c776eb2e
VK		 14363 if (IS_BROXTON(dev)) {
14364 /*
14365 * FIXME: Broxton doesn't support port detection via the
14366 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14367 * detect the ports.
14368 */
14369 intel_ddi_init(dev, PORT_A);
14370 intel_ddi_init(dev, PORT_B);
14371 intel_ddi_init(dev, PORT_C);
14372 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14373 int found;
14374
de31facd
JB		 14375 /*
14376 * Haswell uses DDI functions to detect digital outputs.
14377 * On SKL pre-D0 the strap isn't connected, so we assume
14378 * it's there.
14379 */
0e72a5b5 14380 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14381 /* WaIgnoreDDIAStrap: skl */
14382 if (found ||
14383 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14384 intel_ddi_init(dev, PORT_A);
14385
14386 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14387 * register */
14388 found = I915_READ(SFUSE_STRAP);
14389
14390 if (found & SFUSE_STRAP_DDIB_DETECTED)
14391 intel_ddi_init(dev, PORT_B);
14392 if (found & SFUSE_STRAP_DDIC_DETECTED)
14393 intel_ddi_init(dev, PORT_C);
14394 if (found & SFUSE_STRAP_DDID_DETECTED)
14395 intel_ddi_init(dev, PORT_D);
14396 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14397 int found;
5d8a7752 14398 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14399
14400 if (has_edp_a(dev))
14401 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14402
dc0fa718 14403 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14404 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14405 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14406 if (!found)
e2debe91 14407 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14408 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14409 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14410 }
14411
dc0fa718 14412 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14413 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14414
dc0fa718 14415 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14416 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14417
5eb08b69 14418 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14419 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14420
270b3042 14421 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14422 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14423 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14424 /*
14425 * The DP_DETECTED bit is the latched state of the DDC
14426 * SDA pin at boot. However since eDP doesn't require DDC
14427 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14428 * eDP ports may have been muxed to an alternate function.
14429 * Thus we can't rely on the DP_DETECTED bit alone to detect
14430 * eDP ports. Consult the VBT as well as DP_DETECTED to
14431 * detect eDP ports.
14432 */
d2182a66
VS		 14433 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14434 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14435 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14436 PORT_B);
e17ac6db
VS		 14437 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14438 intel_dp_is_edp(dev, PORT_B))
14439 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14440
d2182a66
VS		 14441 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14442 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14443 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14444 PORT_C);
e17ac6db
VS		 14445 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14446 intel_dp_is_edp(dev, PORT_C))
14447 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14448
9418c1f1 14449 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14450 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14451 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14452 PORT_D);
e17ac6db
VS		 14453 /* eDP not supported on port D, so don't check VBT */
14454 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14455 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14456 }
14457
3cfca973 14458 intel_dsi_init(dev);
103a196f 14459 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14460 bool found = false;
7d57382e 14461
e2debe91 14462 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14463 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14464 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14465 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14466 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14467 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14468 }
27185ae1 14469
e7281eab 14470 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14471 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14472 }
13520b05
KH		 14473
14474 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14475
e2debe91 14476 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14477 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14478 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14479 }
27185ae1 14480
e2debe91 14481 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14482
b01f2c3a
JB		 14483 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14484 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14485 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14486 }
e7281eab 14487 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14488 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14489 }
27185ae1 14490
b01f2c3a 14491 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14492 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14493 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14494 } else if (IS_GEN2(dev))
79e53945
JB		 14495 intel_dvo_init(dev);
14496
103a196f 14497 if (SUPPORTS_TV(dev))
79e53945
JB		 14498 intel_tv_init(dev);
14499
0bc12bcb 14500 intel_psr_init(dev);
7c8f8a70 14501
b2784e15 14502 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14503 encoder->base.possible_crtcs = encoder->crtc_mask;
14504 encoder->base.possible_clones =
66a9278e 14505 intel_encoder_clones(encoder);
79e53945 14506 }
47356eb6 14507
dde86e2d 14508 intel_init_pch_refclk(dev);
270b3042
DV		 14509
14510 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14511}
14512
14513static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14514{
60a5ca01 14515 struct drm_device *dev = fb->dev;
79e53945 14516 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14517
ef2d633e 14518 drm_framebuffer_cleanup(fb);
60a5ca01 14519 mutex_lock(&dev->struct_mutex);
ef2d633e 14520 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14521 drm_gem_object_unreference(&intel_fb->obj->base);
14522 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14523 kfree(intel_fb);
14524}
14525
14526static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14527 struct drm_file *file,
79e53945
JB		 14528 unsigned int *handle)
14529{
14530 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14531 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14532
05394f39 14533 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14534}
14535
14536static const struct drm_framebuffer_funcs intel_fb_funcs = {
14537 .destroy = intel_user_framebuffer_destroy,
14538 .create_handle = intel_user_framebuffer_create_handle,
14539};
14540
b321803d
DL		 14541static
14542u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14543 uint32_t pixel_format)
14544{
14545 u32 gen = INTEL_INFO(dev)->gen;
14546
14547 if (gen >= 9) {
14548 /* "The stride in bytes must not exceed the of the size of 8K
14549 * pixels and 32K bytes."
14550 */
14551 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14552 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14553 return 32*1024;
14554 } else if (gen >= 4) {
14555 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14556 return 16*1024;
14557 else
14558 return 32*1024;
14559 } else if (gen >= 3) {
14560 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14561 return 8*1024;
14562 else
14563 return 16*1024;
14564 } else {
14565 /* XXX DSPC is limited to 4k tiled */
14566 return 8*1024;
14567 }
14568}
14569
b5ea642a
DV		 14570static int intel_framebuffer_init(struct drm_device *dev,
14571 struct intel_framebuffer *intel_fb,
14572 struct drm_mode_fb_cmd2 *mode_cmd,
14573 struct drm_i915_gem_object *obj)
79e53945 14574{
6761dd31 14575 unsigned int aligned_height;
79e53945 14576 int ret;
b321803d 14577 u32 pitch_limit, stride_alignment;
79e53945 14578
dd4916c5
DV		 14579 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14580
2a80eada
DV		 14581 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14582 /* Enforce that fb modifier and tiling mode match, but only for
14583 * X-tiled. This is needed for FBC. */
14584 if (!!(obj->tiling_mode == I915_TILING_X) !=
14585 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14586 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14587 return -EINVAL;
14588 }
14589 } else {
14590 if (obj->tiling_mode == I915_TILING_X)
14591 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14592 else if (obj->tiling_mode == I915_TILING_Y) {
14593 DRM_DEBUG("No Y tiling for legacy addfb\n");
14594 return -EINVAL;
14595 }
14596 }
14597
9a8f0a12
TU		 14598 /* Passed in modifier sanity checking. */
14599 switch (mode_cmd->modifier[0]) {
14600 case I915_FORMAT_MOD_Y_TILED:
14601 case I915_FORMAT_MOD_Yf_TILED:
14602 if (INTEL_INFO(dev)->gen < 9) {
14603 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14604 mode_cmd->modifier[0]);
14605 return -EINVAL;
14606 }
14607 case DRM_FORMAT_MOD_NONE:
14608 case I915_FORMAT_MOD_X_TILED:
14609 break;
14610 default:
c0f40428
JB		 14611 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14612 mode_cmd->modifier[0]);
57cd6508 14613 return -EINVAL;
c16ed4be 14614 }
57cd6508 14615
b321803d
DL		 14616 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14617 mode_cmd->pixel_format);
14618 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14619 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14620 mode_cmd->pitches[0], stride_alignment);
57cd6508 14621 return -EINVAL;
c16ed4be 14622 }
57cd6508 14623
b321803d
DL		 14624 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14625 mode_cmd->pixel_format);
a35cdaa0 14626 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14627 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14628 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14629 "tiled" : "linear",
a35cdaa0 14630 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14631 return -EINVAL;
c16ed4be 14632 }
5d7bd705 14633
2a80eada 14634 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14635 mode_cmd->pitches[0] != obj->stride) {
14636 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14637 mode_cmd->pitches[0], obj->stride);
5d7bd705 14638 return -EINVAL;
c16ed4be 14639 }
5d7bd705 14640
57779d06 14641 /* Reject formats not supported by any plane early. */
308e5bcb 14642 switch (mode_cmd->pixel_format) {
57779d06 14643 case DRM_FORMAT_C8:
04b3924d
VS		 14644 case DRM_FORMAT_RGB565:
14645 case DRM_FORMAT_XRGB8888:
14646 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14647 break;
14648 case DRM_FORMAT_XRGB1555:
c16ed4be 14649 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14650 DRM_DEBUG("unsupported pixel format: %s\n",
14651 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14652 return -EINVAL;
c16ed4be 14653 }
57779d06 14654 break;
57779d06 14655 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14656 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14657 DRM_DEBUG("unsupported pixel format: %s\n",
14658 drm_get_format_name(mode_cmd->pixel_format));
14659 return -EINVAL;
14660 }
14661 break;
14662 case DRM_FORMAT_XBGR8888:
04b3924d 14663 case DRM_FORMAT_XRGB2101010:
57779d06 14664 case DRM_FORMAT_XBGR2101010:
c16ed4be 14665 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14666 DRM_DEBUG("unsupported pixel format: %s\n",
14667 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14668 return -EINVAL;
c16ed4be 14669 }
b5626747 14670 break;
7531208b
DL		 14671 case DRM_FORMAT_ABGR2101010:
14672 if (!IS_VALLEYVIEW(dev)) {
14673 DRM_DEBUG("unsupported pixel format: %s\n",
14674 drm_get_format_name(mode_cmd->pixel_format));
14675 return -EINVAL;
14676 }
14677 break;
04b3924d
VS		 14678 case DRM_FORMAT_YUYV:
14679 case DRM_FORMAT_UYVY:
14680 case DRM_FORMAT_YVYU:
14681 case DRM_FORMAT_VYUY:
c16ed4be 14682 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14683 DRM_DEBUG("unsupported pixel format: %s\n",
14684 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14685 return -EINVAL;
c16ed4be 14686 }
57cd6508
CW		 14687 break;
14688 default:
4ee62c76
VS		 14689 DRM_DEBUG("unsupported pixel format: %s\n",
14690 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14691 return -EINVAL;
14692 }
14693
90f9a336
VS		 14694 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14695 if (mode_cmd->offsets[0] != 0)
14696 return -EINVAL;
14697
ec2c981e 14698 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14699 mode_cmd->pixel_format,
14700 mode_cmd->modifier[0]);
53155c0a
DV		 14701 /* FIXME drm helper for size checks (especially planar formats)? */
14702 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14703 return -EINVAL;
14704
c7d73f6a
DV		 14705 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14706 intel_fb->obj = obj;
80075d49 14707 intel_fb->obj->framebuffer_references++;
c7d73f6a 14708
79e53945
JB		 14709 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14710 if (ret) {
14711 DRM_ERROR("framebuffer init failed %d\n", ret);
14712 return ret;
14713 }
14714
79e53945
JB		 14715 return 0;
14716}
14717
79e53945
JB		 14718static struct drm_framebuffer *
14719intel_user_framebuffer_create(struct drm_device *dev,
14720 struct drm_file *filp,
308e5bcb 14721 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14722{
05394f39 14723 struct drm_i915_gem_object *obj;
79e53945 14724
308e5bcb
JB		 14725 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14726 mode_cmd->handles[0]));
c8725226 14727 if (&obj->base == NULL)
cce13ff7 14728 return ERR_PTR(-ENOENT);
79e53945 14729
d2dff872 14730 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14731}
14732
4520f53a 14733#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14734static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14735{
14736}
14737#endif
14738
79e53945 14739static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14740 .fb_create = intel_user_framebuffer_create,
0632fef6 14741 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14742 .atomic_check = intel_atomic_check,
14743 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14744};
14745
e70236a8
JB		 14746/* Set up chip specific display functions */
14747static void intel_init_display(struct drm_device *dev)
14748{
14749 struct drm_i915_private *dev_priv = dev->dev_private;
14750
ee9300bb
DV		 14751 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14752 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14753 else if (IS_CHERRYVIEW(dev))
14754 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14755 else if (IS_VALLEYVIEW(dev))
14756 dev_priv->display.find_dpll = vlv_find_best_dpll;
14757 else if (IS_PINEVIEW(dev))
14758 dev_priv->display.find_dpll = pnv_find_best_dpll;
14759 else
14760 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14761
bc8d7dff
DL		 14762 if (INTEL_INFO(dev)->gen >= 9) {
14763 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14764 dev_priv->display.get_initial_plane_config =
14765 skylake_get_initial_plane_config;
bc8d7dff
DL		 14766 dev_priv->display.crtc_compute_clock =
14767 haswell_crtc_compute_clock;
14768 dev_priv->display.crtc_enable = haswell_crtc_enable;
14769 dev_priv->display.crtc_disable = haswell_crtc_disable;
14770 dev_priv->display.off = ironlake_crtc_off;
14771 dev_priv->display.update_primary_plane =
14772 skylake_update_primary_plane;
14773 } else if (HAS_DDI(dev)) {
0e8ffe1b 14774 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14775 dev_priv->display.get_initial_plane_config =
14776 ironlake_get_initial_plane_config;
797d0259
ACO		 14777 dev_priv->display.crtc_compute_clock =
14778 haswell_crtc_compute_clock;
4f771f10
PZ		 14779 dev_priv->display.crtc_enable = haswell_crtc_enable;
14780 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14781 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14782 dev_priv->display.update_primary_plane =
14783 ironlake_update_primary_plane;
09b4ddf9 14784 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14785 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14786 dev_priv->display.get_initial_plane_config =
14787 ironlake_get_initial_plane_config;
3fb37703
ACO		 14788 dev_priv->display.crtc_compute_clock =
14789 ironlake_crtc_compute_clock;
76e5a89c
DV		 14790 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14791 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14792 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14793 dev_priv->display.update_primary_plane =
14794 ironlake_update_primary_plane;
89b667f8
JB		 14795 } else if (IS_VALLEYVIEW(dev)) {
14796 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14797 dev_priv->display.get_initial_plane_config =
14798 i9xx_get_initial_plane_config;
d6dfee7a 14799 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14800 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14801 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14802 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14803 dev_priv->display.update_primary_plane =
14804 i9xx_update_primary_plane;
f564048e 14805 } else {
0e8ffe1b 14806 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14807 dev_priv->display.get_initial_plane_config =
14808 i9xx_get_initial_plane_config;
d6dfee7a 14809 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14810 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14811 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14812 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14813 dev_priv->display.update_primary_plane =
14814 i9xx_update_primary_plane;
f564048e 14815 }
e70236a8 14816
e70236a8 14817 /* Returns the core display clock speed */
1652d19e
VS		 14818 if (IS_SKYLAKE(dev))
14819 dev_priv->display.get_display_clock_speed =
14820 skylake_get_display_clock_speed;
14821 else if (IS_BROADWELL(dev))
14822 dev_priv->display.get_display_clock_speed =
14823 broadwell_get_display_clock_speed;
14824 else if (IS_HASWELL(dev))
14825 dev_priv->display.get_display_clock_speed =
14826 haswell_get_display_clock_speed;
14827 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14828 dev_priv->display.get_display_clock_speed =
14829 valleyview_get_display_clock_speed;
b37a6434
VS		 14830 else if (IS_GEN5(dev))
14831 dev_priv->display.get_display_clock_speed =
14832 ilk_get_display_clock_speed;
a7c66cd8 14833 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14834 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14835 dev_priv->display.get_display_clock_speed =
14836 i945_get_display_clock_speed;
34edce2f
VS		 14837 else if (IS_GM45(dev))
14838 dev_priv->display.get_display_clock_speed =
14839 gm45_get_display_clock_speed;
14840 else if (IS_CRESTLINE(dev))
14841 dev_priv->display.get_display_clock_speed =
14842 i965gm_get_display_clock_speed;
14843 else if (IS_PINEVIEW(dev))
14844 dev_priv->display.get_display_clock_speed =
14845 pnv_get_display_clock_speed;
14846 else if (IS_G33(dev) || IS_G4X(dev))
14847 dev_priv->display.get_display_clock_speed =
14848 g33_get_display_clock_speed;
e70236a8
JB		 14849 else if (IS_I915G(dev))
14850 dev_priv->display.get_display_clock_speed =
14851 i915_get_display_clock_speed;
257a7ffc 14852 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14853 dev_priv->display.get_display_clock_speed =
14854 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14855 else if (IS_PINEVIEW(dev))
14856 dev_priv->display.get_display_clock_speed =
14857 pnv_get_display_clock_speed;
e70236a8
JB		 14858 else if (IS_I915GM(dev))
14859 dev_priv->display.get_display_clock_speed =
14860 i915gm_get_display_clock_speed;
14861 else if (IS_I865G(dev))
14862 dev_priv->display.get_display_clock_speed =
14863 i865_get_display_clock_speed;
f0f8a9ce 14864 else if (IS_I85X(dev))
e70236a8 14865 dev_priv->display.get_display_clock_speed =
1b1d2716 14866 i85x_get_display_clock_speed;
623e01e5
VS		 14867 else { /* 830 */
14868 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14869 dev_priv->display.get_display_clock_speed =
14870 i830_get_display_clock_speed;
623e01e5 14871 }
e70236a8 14872
7c10a2b5 14873 if (IS_GEN5(dev)) {
3bb11b53 14874 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14875 } else if (IS_GEN6(dev)) {
14876 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14877 } else if (IS_IVYBRIDGE(dev)) {
14878 /* FIXME: detect B0+ stepping and use auto training */
14879 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14880 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14881 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
b432e5cf
VS		 14882 if (IS_BROADWELL(dev))
14883 dev_priv->display.modeset_global_resources =
14884 broadwell_modeset_global_resources;
30a970c6
JB		 14885 } else if (IS_VALLEYVIEW(dev)) {
14886 dev_priv->display.modeset_global_resources =
14887 valleyview_modeset_global_resources;
f8437dd1
VK		 14888 } else if (IS_BROXTON(dev)) {
14889 dev_priv->display.modeset_global_resources =
14890 broxton_modeset_global_resources;
e70236a8 14891 }
8c9f3aaf 14892
8c9f3aaf
JB		 14893 switch (INTEL_INFO(dev)->gen) {
14894 case 2:
14895 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14896 break;
14897
14898 case 3:
14899 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14900 break;
14901
14902 case 4:
14903 case 5:
14904 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14905 break;
14906
14907 case 6:
14908 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14909 break;
7c9017e5 14910 case 7:
4e0bbc31 14911 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14912 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14913 break;
830c81db 14914 case 9:
ba343e02
TU		 14915 /* Drop through - unsupported since execlist only. */
14916 default:
14917 /* Default just returns -ENODEV to indicate unsupported */
14918 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14919 }
7bd688cd
JN		 14920
14921 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14922
14923 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14924}
14925
b690e96c
JB		 14926/*
14927 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14928 * resume, or other times. This quirk makes sure that's the case for
14929 * affected systems.
14930 */
0206e353 14931static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14932{
14933 struct drm_i915_private *dev_priv = dev->dev_private;
14934
14935 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14936 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14937}
14938
b6b5d049
VS		 14939static void quirk_pipeb_force(struct drm_device *dev)
14940{
14941 struct drm_i915_private *dev_priv = dev->dev_private;
14942
14943 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14944 DRM_INFO("applying pipe b force quirk\n");
14945}
14946
435793df
KP		 14947/*
14948 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14949 */
14950static void quirk_ssc_force_disable(struct drm_device *dev)
14951{
14952 struct drm_i915_private *dev_priv = dev->dev_private;
14953 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14954 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14955}
14956
4dca20ef 14957/*
5a15ab5b
CE		 14958 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14959 * brightness value
4dca20ef
CE		 14960 */
14961static void quirk_invert_brightness(struct drm_device *dev)
14962{
14963 struct drm_i915_private *dev_priv = dev->dev_private;
14964 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14965 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14966}
14967
9c72cc6f
SD		 14968/* Some VBT's incorrectly indicate no backlight is present */
14969static void quirk_backlight_present(struct drm_device *dev)
14970{
14971 struct drm_i915_private *dev_priv = dev->dev_private;
14972 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14973 DRM_INFO("applying backlight present quirk\n");
14974}
14975
b690e96c
JB		 14976struct intel_quirk {
14977 int device;
14978 int subsystem_vendor;
14979 int subsystem_device;
14980 void (*hook)(struct drm_device *dev);
14981};
14982
5f85f176
EE		 14983/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14984struct intel_dmi_quirk {
14985 void (*hook)(struct drm_device *dev);
14986 const struct dmi_system_id (*dmi_id_list)[];
14987};
14988
14989static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14990{
14991 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14992 return 1;
14993}
14994
14995static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14996 {
14997 .dmi_id_list = &(const struct dmi_system_id[]) {
14998 {
14999 .callback = intel_dmi_reverse_brightness,
15000 .ident = "NCR Corporation",
15001 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15002 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15003 },
15004 },
15005 { } /* terminating entry */
15006 },
15007 .hook = quirk_invert_brightness,
15008 },
15009};
15010
c43b5634 15011static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 15012 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15013 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15014
b690e96c
JB		 15015 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15016 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15017
5f080c0f
VS		 15018 /* 830 needs to leave pipe A & dpll A up */
15019 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15020
b6b5d049
VS		 15021 /* 830 needs to leave pipe B & dpll B up */
15022 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15023
435793df
KP		 15024 /* Lenovo U160 cannot use SSC on LVDS */
15025 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 15026
15027 /* Sony Vaio Y cannot use SSC on LVDS */
15028 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 15029
be505f64
AH		 15030 /* Acer Aspire 5734Z must invert backlight brightness */
15031 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15032
15033 /* Acer/eMachines G725 */
15034 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15035
15036 /* Acer/eMachines e725 */
15037 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15038
15039 /* Acer/Packard Bell NCL20 */
15040 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15041
15042 /* Acer Aspire 4736Z */
15043 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 15044
15045 /* Acer Aspire 5336 */
15046 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 15047
15048 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15049 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 15050
dfb3d47b
SD		 15051 /* Acer C720 Chromebook (Core i3 4005U) */
15052 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15053
b2a9601c 15054 /* Apple Macbook 2,1 (Core 2 T7400) */
15055 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15056
d4967d8c
SD		 15057 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15058 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 15059
15060 /* HP Chromebook 14 (Celeron 2955U) */
15061 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 15062
15063 /* Dell Chromebook 11 */
15064 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 15065};
15066
15067static void intel_init_quirks(struct drm_device *dev)
15068{
15069 struct pci_dev *d = dev->pdev;
15070 int i;
15071
15072 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15073 struct intel_quirk *q = &intel_quirks[i];
15074
15075 if (d->device == q->device &&
15076 (d->subsystem_vendor == q->subsystem_vendor ||
15077 q->subsystem_vendor == PCI_ANY_ID) &&
15078 (d->subsystem_device == q->subsystem_device ||
15079 q->subsystem_device == PCI_ANY_ID))
15080 q->hook(dev);
15081 }
5f85f176
EE		 15082 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15083 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15084 intel_dmi_quirks[i].hook(dev);
15085 }
b690e96c
JB		 15086}
15087
9cce37f4
JB		 15088/* Disable the VGA plane that we never use */
15089static void i915_disable_vga(struct drm_device *dev)
15090{
15091 struct drm_i915_private *dev_priv = dev->dev_private;
15092 u8 sr1;
766aa1c4 15093 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 15094
2b37c616 15095 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 15096 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 15097 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 15098 sr1 = inb(VGA_SR_DATA);
15099 outb(sr1 | 1<<5, VGA_SR_DATA);
15100 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15101 udelay(300);
15102
01f5a626 15103 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 15104 POSTING_READ(vga_reg);
15105}
15106
f817586c
DV		 15107void intel_modeset_init_hw(struct drm_device *dev)
15108{
b6283055 15109 intel_update_cdclk(dev);
a8f78b58 15110 intel_prepare_ddi(dev);
f817586c 15111 intel_init_clock_gating(dev);
8090c6b9 15112 intel_enable_gt_powersave(dev);
f817586c
DV		 15113}
15114
79e53945
JB		 15115void intel_modeset_init(struct drm_device *dev)
15116{
652c393a 15117 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 15118 int sprite, ret;
8cc87b75 15119 enum pipe pipe;
46f297fb 15120 struct intel_crtc *crtc;
79e53945
JB		 15121
15122 drm_mode_config_init(dev);
15123
15124 dev->mode_config.min_width = 0;
15125 dev->mode_config.min_height = 0;
15126
019d96cb
DA		 15127 dev->mode_config.preferred_depth = 24;
15128 dev->mode_config.prefer_shadow = 1;
15129
25bab385
TU		 15130 dev->mode_config.allow_fb_modifiers = true;
15131
e6ecefaa 15132 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15133
b690e96c
JB		 15134 intel_init_quirks(dev);
15135
1fa61106
ED		 15136 intel_init_pm(dev);
15137
e3c74757
BW		 15138 if (INTEL_INFO(dev)->num_pipes == 0)
15139 return;
15140
e70236a8 15141 intel_init_display(dev);
7c10a2b5 15142 intel_init_audio(dev);
e70236a8 15143
a6c45cf0
CW		 15144 if (IS_GEN2(dev)) {
15145 dev->mode_config.max_width = 2048;
15146 dev->mode_config.max_height = 2048;
15147 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15148 dev->mode_config.max_width = 4096;
15149 dev->mode_config.max_height = 4096;
79e53945 15150 } else {
a6c45cf0
CW		 15151 dev->mode_config.max_width = 8192;
15152 dev->mode_config.max_height = 8192;
79e53945 15153 }
068be561 15154
dc41c154
VS		 15155 if (IS_845G(dev) || IS_I865G(dev)) {
15156 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15157 dev->mode_config.cursor_height = 1023;
15158 } else if (IS_GEN2(dev)) {
068be561
DL		 15159 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15160 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15161 } else {
15162 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15163 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15164 }
15165
5d4545ae 15166 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15167
28c97730 15168 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15169 INTEL_INFO(dev)->num_pipes,
15170 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15171
055e393f 15172 for_each_pipe(dev_priv, pipe) {
8cc87b75 15173 intel_crtc_init(dev, pipe);
3bdcfc0c 15174 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15175 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15176 if (ret)
06da8da2 15177 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15178 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15179 }
79e53945
JB		 15180 }
15181
f42bb70d
JB		 15182 intel_init_dpio(dev);
15183
e72f9fbf 15184 intel_shared_dpll_init(dev);
ee7b9f93 15185
9cce37f4
JB		 15186 /* Just disable it once at startup */
15187 i915_disable_vga(dev);
79e53945 15188 intel_setup_outputs(dev);
11be49eb
CW		 15189
15190 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15191 intel_fbc_disable(dev);
fa9fa083 15192
6e9f798d 15193 drm_modeset_lock_all(dev);
fa9fa083 15194 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15195 drm_modeset_unlock_all(dev);
46f297fb 15196
d3fcc808 15197 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15198 if (!crtc->active)
15199 continue;
15200
46f297fb 15201 /*
46f297fb
JB		 15202 * Note that reserving the BIOS fb up front prevents us
15203 * from stuffing other stolen allocations like the ring
15204 * on top. This prevents some ugliness at boot time, and
15205 * can even allow for smooth boot transitions if the BIOS
15206 * fb is large enough for the active pipe configuration.
15207 */
5724dbd1
DL		 15208 if (dev_priv->display.get_initial_plane_config) {
15209 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15210 &crtc->plane_config);
15211 /*
15212 * If the fb is shared between multiple heads, we'll
15213 * just get the first one.
15214 */
f6936e29 15215 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15216 }
46f297fb 15217 }
2c7111db
CW		 15218}
15219
7fad798e
DV		 15220static void intel_enable_pipe_a(struct drm_device *dev)
15221{
15222 struct intel_connector *connector;
15223 struct drm_connector *crt = NULL;
15224 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15225 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15226
15227 /* We can't just switch on the pipe A, we need to set things up with a
15228 * proper mode and output configuration. As a gross hack, enable pipe A
15229 * by enabling the load detect pipe once. */
3a3371ff 15230 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15231 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15232 crt = &connector->base;
15233 break;
15234 }
15235 }
15236
15237 if (!crt)
15238 return;
15239
208bf9fd 15240 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15241 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15242}
15243
fa555837
DV		 15244static bool
15245intel_check_plane_mapping(struct intel_crtc *crtc)
15246{
7eb552ae
BW		 15247 struct drm_device *dev = crtc->base.dev;
15248 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15249 u32 reg, val;
15250
7eb552ae 15251 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15252 return true;
15253
15254 reg = DSPCNTR(!crtc->plane);
15255 val = I915_READ(reg);
15256
15257 if ((val & DISPLAY_PLANE_ENABLE) &&
15258 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15259 return false;
15260
15261 return true;
15262}
15263
24929352
DV		 15264static void intel_sanitize_crtc(struct intel_crtc *crtc)
15265{
15266 struct drm_device *dev = crtc->base.dev;
15267 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15268 u32 reg;
24929352 15269
24929352 15270 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15271 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15272 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15273
d3eaf884 15274 /* restore vblank interrupts to correct state */
9625604c 15275 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15276 if (crtc->active) {
15277 update_scanline_offset(crtc);
9625604c
DV		 15278 drm_crtc_vblank_on(&crtc->base);
15279 }
d3eaf884 15280
24929352 15281 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15282 * disable the crtc (and hence change the state) if it is wrong. Note
15283 * that gen4+ has a fixed plane -> pipe mapping. */
15284 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15285 struct intel_connector *connector;
15286 bool plane;
15287
24929352
DV		 15288 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15289 crtc->base.base.id);
15290
15291 /* Pipe has the wrong plane attached and the plane is active.
15292 * Temporarily change the plane mapping and disable everything
15293 * ... */
15294 plane = crtc->plane;
b70709a6 15295 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15296 crtc->plane = !plane;
ce22dba9 15297 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 15298 dev_priv->display.crtc_disable(&crtc->base);
15299 crtc->plane = plane;
15300
15301 /* ... and break all links. */
3a3371ff 15302 for_each_intel_connector(dev, connector) {
24929352
DV		 15303 if (connector->encoder->base.crtc != &crtc->base)
15304 continue;
15305
7f1950fb
EE		 15306 connector->base.dpms = DRM_MODE_DPMS_OFF;
15307 connector->base.encoder = NULL;
24929352 15308 }
7f1950fb
EE		 15309 /* multiple connectors may have the same encoder:
15310 * handle them and break crtc link separately */
3a3371ff 15311 for_each_intel_connector(dev, connector)
7f1950fb
EE		 15312 if (connector->encoder->base.crtc == &crtc->base) {
15313 connector->encoder->base.crtc = NULL;
15314 connector->encoder->connectors_active = false;
15315 }
24929352
DV		 15316
15317 WARN_ON(crtc->active);
83d65738 15318 crtc->base.state->enable = false;
49d6fa21 15319 crtc->base.state->active = false;
24929352
DV		 15320 crtc->base.enabled = false;
15321 }
24929352 15322
7fad798e
DV		 15323 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15324 crtc->pipe == PIPE_A && !crtc->active) {
15325 /* BIOS forgot to enable pipe A, this mostly happens after
15326 * resume. Force-enable the pipe to fix this, the update_dpms
15327 * call below we restore the pipe to the right state, but leave
15328 * the required bits on. */
15329 intel_enable_pipe_a(dev);
15330 }
15331
24929352
DV		 15332 /* Adjust the state of the output pipe according to whether we
15333 * have active connectors/encoders. */
15334 intel_crtc_update_dpms(&crtc->base);
15335
83d65738 15336 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 15337 struct intel_encoder *encoder;
15338
15339 /* This can happen either due to bugs in the get_hw_state
15340 * functions or because the pipe is force-enabled due to the
15341 * pipe A quirk. */
15342 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15343 crtc->base.base.id,
83d65738 15344 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15345 crtc->active ? "enabled" : "disabled");
15346
83d65738 15347 crtc->base.state->enable = crtc->active;
49d6fa21 15348 crtc->base.state->active = crtc->active;
24929352
DV		 15349 crtc->base.enabled = crtc->active;
15350
15351 /* Because we only establish the connector -> encoder ->
15352 * crtc links if something is active, this means the
15353 * crtc is now deactivated. Break the links. connector
15354 * -> encoder links are only establish when things are
15355 * actually up, hence no need to break them. */
15356 WARN_ON(crtc->active);
15357
15358 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15359 WARN_ON(encoder->connectors_active);
15360 encoder->base.crtc = NULL;
15361 }
15362 }
c5ab3bc0 15363
a3ed6aad 15364 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15365 /*
15366 * We start out with underrun reporting disabled to avoid races.
15367 * For correct bookkeeping mark this on active crtcs.
15368 *
c5ab3bc0
DV		 15369 * Also on gmch platforms we dont have any hardware bits to
15370 * disable the underrun reporting. Which means we need to start
15371 * out with underrun reporting disabled also on inactive pipes,
15372 * since otherwise we'll complain about the garbage we read when
15373 * e.g. coming up after runtime pm.
15374 *
4cc31489
DV		 15375 * No protection against concurrent access is required - at
15376 * worst a fifo underrun happens which also sets this to false.
15377 */
15378 crtc->cpu_fifo_underrun_disabled = true;
15379 crtc->pch_fifo_underrun_disabled = true;
15380 }
24929352
DV		 15381}
15382
15383static void intel_sanitize_encoder(struct intel_encoder *encoder)
15384{
15385 struct intel_connector *connector;
15386 struct drm_device *dev = encoder->base.dev;
15387
15388 /* We need to check both for a crtc link (meaning that the
15389 * encoder is active and trying to read from a pipe) and the
15390 * pipe itself being active. */
15391 bool has_active_crtc = encoder->base.crtc &&
15392 to_intel_crtc(encoder->base.crtc)->active;
15393
15394 if (encoder->connectors_active && !has_active_crtc) {
15395 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15396 encoder->base.base.id,
8e329a03 15397 encoder->base.name);
24929352
DV		 15398
15399 /* Connector is active, but has no active pipe. This is
15400 * fallout from our resume register restoring. Disable
15401 * the encoder manually again. */
15402 if (encoder->base.crtc) {
15403 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15404 encoder->base.base.id,
8e329a03 15405 encoder->base.name);
24929352 15406 encoder->disable(encoder);
a62d1497
VS		 15407 if (encoder->post_disable)
15408 encoder->post_disable(encoder);
24929352 15409 }
7f1950fb
EE		 15410 encoder->base.crtc = NULL;
15411 encoder->connectors_active = false;
24929352
DV		 15412
15413 /* Inconsistent output/port/pipe state happens presumably due to
15414 * a bug in one of the get_hw_state functions. Or someplace else
15415 * in our code, like the register restore mess on resume. Clamp
15416 * things to off as a safer default. */
3a3371ff 15417 for_each_intel_connector(dev, connector) {
24929352
DV		 15418 if (connector->encoder != encoder)
15419 continue;
7f1950fb
EE		 15420 connector->base.dpms = DRM_MODE_DPMS_OFF;
15421 connector->base.encoder = NULL;
24929352
DV		 15422 }
15423 }
15424 /* Enabled encoders without active connectors will be fixed in
15425 * the crtc fixup. */
15426}
15427
04098753 15428void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15429{
15430 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15431 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15432
04098753
ID		 15433 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15434 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15435 i915_disable_vga(dev);
15436 }
15437}
15438
15439void i915_redisable_vga(struct drm_device *dev)
15440{
15441 struct drm_i915_private *dev_priv = dev->dev_private;
15442
8dc8a27c
PZ		 15443 /* This function can be called both from intel_modeset_setup_hw_state or
15444 * at a very early point in our resume sequence, where the power well
15445 * structures are not yet restored. Since this function is at a very
15446 * paranoid "someone might have enabled VGA while we were not looking"
15447 * level, just check if the power well is enabled instead of trying to
15448 * follow the "don't touch the power well if we don't need it" policy
15449 * the rest of the driver uses. */
f458ebbc 15450 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15451 return;
15452
04098753 15453 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15454}
15455
98ec7739
VS		 15456static bool primary_get_hw_state(struct intel_crtc *crtc)
15457{
15458 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15459
15460 if (!crtc->active)
15461 return false;
15462
15463 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15464}
15465
30e984df 15466static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15467{
15468 struct drm_i915_private *dev_priv = dev->dev_private;
15469 enum pipe pipe;
24929352
DV		 15470 struct intel_crtc *crtc;
15471 struct intel_encoder *encoder;
15472 struct intel_connector *connector;
5358901f 15473 int i;
24929352 15474
d3fcc808 15475 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15476 struct drm_plane *primary = crtc->base.primary;
15477 struct intel_plane_state *plane_state;
15478
6e3c9717 15479 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15480
6e3c9717 15481 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15482
0e8ffe1b 15483 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15484 crtc->config);
24929352 15485
83d65738 15486 crtc->base.state->enable = crtc->active;
49d6fa21 15487 crtc->base.state->active = crtc->active;
24929352 15488 crtc->base.enabled = crtc->active;
b70709a6
ML		 15489
15490 plane_state = to_intel_plane_state(primary->state);
15491 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15492
15493 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15494 crtc->base.base.id,
15495 crtc->active ? "enabled" : "disabled");
15496 }
15497
5358901f
DV		 15498 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15499 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15500
3e369b76
ACO		 15501 pll->on = pll->get_hw_state(dev_priv, pll,
15502 &pll->config.hw_state);
5358901f 15503 pll->active = 0;
3e369b76 15504 pll->config.crtc_mask = 0;
d3fcc808 15505 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15506 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15507 pll->active++;
3e369b76 15508 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15509 }
5358901f 15510 }
5358901f 15511
1e6f2ddc 15512 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15513 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15514
3e369b76 15515 if (pll->config.crtc_mask)
bd2bb1b9 15516 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15517 }
15518
b2784e15 15519 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15520 pipe = 0;
15521
15522 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15523 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15524 encoder->base.crtc = &crtc->base;
6e3c9717 15525 encoder->get_config(encoder, crtc->config);
24929352
DV		 15526 } else {
15527 encoder->base.crtc = NULL;
15528 }
15529
15530 encoder->connectors_active = false;
6f2bcceb 15531 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15532 encoder->base.base.id,
8e329a03 15533 encoder->base.name,
24929352 15534 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15535 pipe_name(pipe));
24929352
DV		 15536 }
15537
3a3371ff 15538 for_each_intel_connector(dev, connector) {
24929352
DV		 15539 if (connector->get_hw_state(connector)) {
15540 connector->base.dpms = DRM_MODE_DPMS_ON;
15541 connector->encoder->connectors_active = true;
15542 connector->base.encoder = &connector->encoder->base;
15543 } else {
15544 connector->base.dpms = DRM_MODE_DPMS_OFF;
15545 connector->base.encoder = NULL;
15546 }
15547 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15548 connector->base.base.id,
c23cc417 15549 connector->base.name,
24929352
DV		 15550 connector->base.encoder ? "enabled" : "disabled");
15551 }
30e984df
DV		 15552}
15553
15554/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15555 * and i915 state tracking structures. */
15556void intel_modeset_setup_hw_state(struct drm_device *dev,
15557 bool force_restore)
15558{
15559 struct drm_i915_private *dev_priv = dev->dev_private;
15560 enum pipe pipe;
30e984df
DV		 15561 struct intel_crtc *crtc;
15562 struct intel_encoder *encoder;
35c95375 15563 int i;
30e984df
DV		 15564
15565 intel_modeset_readout_hw_state(dev);
24929352 15566
babea61d
JB		 15567 /*
15568 * Now that we have the config, copy it to each CRTC struct
15569 * Note that this could go away if we move to using crtc_config
15570 * checking everywhere.
15571 */
d3fcc808 15572 for_each_intel_crtc(dev, crtc) {
d330a953 15573 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15574 intel_mode_from_pipe_config(&crtc->base.mode,
15575 crtc->config);
babea61d
JB		 15576 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15577 crtc->base.base.id);
15578 drm_mode_debug_printmodeline(&crtc->base.mode);
15579 }
15580 }
15581
24929352 15582 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15583 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15584 intel_sanitize_encoder(encoder);
15585 }
15586
055e393f 15587 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15588 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15589 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15590 intel_dump_pipe_config(crtc, crtc->config,
15591 "[setup_hw_state]");
24929352 15592 }
9a935856 15593
d29b2f9d
ACO		 15594 intel_modeset_update_connector_atomic_state(dev);
15595
35c95375
DV		 15596 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15597 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15598
15599 if (!pll->on || pll->active)
15600 continue;
15601
15602 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15603
15604 pll->disable(dev_priv, pll);
15605 pll->on = false;
15606 }
15607
3078999f
PB		 15608 if (IS_GEN9(dev))
15609 skl_wm_get_hw_state(dev);
15610 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15611 ilk_wm_get_hw_state(dev);
15612
45e2b5f6 15613 if (force_restore) {
7d0bc1ea
VS		 15614 i915_redisable_vga(dev);
15615
f30da187
DV		 15616 /*
15617 * We need to use raw interfaces for restoring state to avoid
15618 * checking (bogus) intermediate states.
15619 */
055e393f 15620 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15621 struct drm_crtc *crtc =
15622 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15623
83a57153 15624 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15625 }
15626 } else {
15627 intel_modeset_update_staged_output_state(dev);
15628 }
8af6cf88
DV		 15629
15630 intel_modeset_check_state(dev);
2c7111db
CW		 15631}
15632
15633void intel_modeset_gem_init(struct drm_device *dev)
15634{
92122789 15635 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15636 struct drm_crtc *c;
2ff8fde1 15637 struct drm_i915_gem_object *obj;
e0d6149b 15638 int ret;
484b41dd 15639
ae48434c
ID		 15640 mutex_lock(&dev->struct_mutex);
15641 intel_init_gt_powersave(dev);
15642 mutex_unlock(&dev->struct_mutex);
15643
92122789
JB		 15644 /*
15645 * There may be no VBT; and if the BIOS enabled SSC we can
15646 * just keep using it to avoid unnecessary flicker. Whereas if the
15647 * BIOS isn't using it, don't assume it will work even if the VBT
15648 * indicates as much.
15649 */
15650 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15651 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15652 DREF_SSC1_ENABLE);
15653
1833b134 15654 intel_modeset_init_hw(dev);
02e792fb
DV		 15655
15656 intel_setup_overlay(dev);
484b41dd
JB		 15657
15658 /*
15659 * Make sure any fbs we allocated at startup are properly
15660 * pinned & fenced. When we do the allocation it's too early
15661 * for this.
15662 */
70e1e0ec 15663 for_each_crtc(dev, c) {
2ff8fde1
MR		 15664 obj = intel_fb_obj(c->primary->fb);
15665 if (obj == NULL)
484b41dd
JB		 15666 continue;
15667
e0d6149b
TU		 15668 mutex_lock(&dev->struct_mutex);
15669 ret = intel_pin_and_fence_fb_obj(c->primary,
15670 c->primary->fb,
15671 c->primary->state,
15672 NULL);
15673 mutex_unlock(&dev->struct_mutex);
15674 if (ret) {
484b41dd
JB		 15675 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15676 to_intel_crtc(c)->pipe);
66e514c1
DA		 15677 drm_framebuffer_unreference(c->primary->fb);
15678 c->primary->fb = NULL;
afd65eb4 15679 update_state_fb(c->primary);
484b41dd
JB		 15680 }
15681 }
0962c3c9
VS		 15682
15683 intel_backlight_register(dev);
79e53945
JB		 15684}
15685
4932e2c3
ID		 15686void intel_connector_unregister(struct intel_connector *intel_connector)
15687{
15688 struct drm_connector *connector = &intel_connector->base;
15689
15690 intel_panel_destroy_backlight(connector);
34ea3d38 15691 drm_connector_unregister(connector);
4932e2c3
ID		 15692}
15693
79e53945
JB		 15694void intel_modeset_cleanup(struct drm_device *dev)
15695{
652c393a 15696 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15697 struct drm_connector *connector;
652c393a 15698
2eb5252e
ID		 15699 intel_disable_gt_powersave(dev);
15700
0962c3c9
VS		 15701 intel_backlight_unregister(dev);
15702
fd0c0642
DV		 15703 /*
15704 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15705 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15706 * experience fancy races otherwise.
15707 */
2aeb7d3a 15708 intel_irq_uninstall(dev_priv);
eb21b92b 15709
fd0c0642
DV		 15710 /*
15711 * Due to the hpd irq storm handling the hotplug work can re-arm the
15712 * poll handlers. Hence disable polling after hpd handling is shut down.
15713 */
f87ea761 15714 drm_kms_helper_poll_fini(dev);
fd0c0642 15715
652c393a
JB		 15716 mutex_lock(&dev->struct_mutex);
15717
723bfd70
JB		 15718 intel_unregister_dsm_handler();
15719
7ff0ebcc 15720 intel_fbc_disable(dev);
e70236a8 15721
69341a5e
KH		 15722 mutex_unlock(&dev->struct_mutex);
15723
1630fe75
CW		 15724 /* flush any delayed tasks or pending work */
15725 flush_scheduled_work();
15726
db31af1d
JN		 15727 /* destroy the backlight and sysfs files before encoders/connectors */
15728 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15729 struct intel_connector *intel_connector;
15730
15731 intel_connector = to_intel_connector(connector);
15732 intel_connector->unregister(intel_connector);
db31af1d 15733 }
d9255d57 15734
79e53945 15735 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15736
15737 intel_cleanup_overlay(dev);
ae48434c
ID		 15738
15739 mutex_lock(&dev->struct_mutex);
15740 intel_cleanup_gt_powersave(dev);
15741 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15742}
15743
f1c79df3
ZW		 15744/*
15745 * Return which encoder is currently attached for connector.
15746 */
df0e9248 15747struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15748{
df0e9248
CW		 15749 return &intel_attached_encoder(connector)->base;
15750}
f1c79df3 15751
df0e9248
CW		 15752void intel_connector_attach_encoder(struct intel_connector *connector,
15753 struct intel_encoder *encoder)
15754{
15755 connector->encoder = encoder;
15756 drm_mode_connector_attach_encoder(&connector->base,
15757 &encoder->base);
79e53945 15758}
28d52043
DA		 15759
15760/*
15761 * set vga decode state - true == enable VGA decode
15762 */
15763int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15764{
15765 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15766 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15767 u16 gmch_ctrl;
15768
75fa041d
CW		 15769 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15770 DRM_ERROR("failed to read control word\n");
15771 return -EIO;
15772 }
15773
c0cc8a55
CW		 15774 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15775 return 0;
15776
28d52043
DA		 15777 if (state)
15778 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15779 else
15780 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15781
15782 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15783 DRM_ERROR("failed to write control word\n");
15784 return -EIO;
15785 }
15786
28d52043
DA		 15787 return 0;
15788}
c4a1d9e4 15789
c4a1d9e4 15790struct intel_display_error_state {
ff57f1b0
PZ		 15791
15792 u32 power_well_driver;
15793
63b66e5b
CW		 15794 int num_transcoders;
15795
c4a1d9e4
CW		 15796 struct intel_cursor_error_state {
15797 u32 control;
15798 u32 position;
15799 u32 base;
15800 u32 size;
52331309 15801 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15802
15803 struct intel_pipe_error_state {
ddf9c536 15804 bool power_domain_on;
c4a1d9e4 15805 u32 source;
f301b1e1 15806 u32 stat;
52331309 15807 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15808
15809 struct intel_plane_error_state {
15810 u32 control;
15811 u32 stride;
15812 u32 size;
15813 u32 pos;
15814 u32 addr;
15815 u32 surface;
15816 u32 tile_offset;
52331309 15817 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15818
15819 struct intel_transcoder_error_state {
ddf9c536 15820 bool power_domain_on;
63b66e5b
CW		 15821 enum transcoder cpu_transcoder;
15822
15823 u32 conf;
15824
15825 u32 htotal;
15826 u32 hblank;
15827 u32 hsync;
15828 u32 vtotal;
15829 u32 vblank;
15830 u32 vsync;
15831 } transcoder[4];
c4a1d9e4
CW		 15832};
15833
15834struct intel_display_error_state *
15835intel_display_capture_error_state(struct drm_device *dev)
15836{
fbee40df 15837 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15838 struct intel_display_error_state *error;
63b66e5b
CW		 15839 int transcoders[] = {
15840 TRANSCODER_A,
15841 TRANSCODER_B,
15842 TRANSCODER_C,
15843 TRANSCODER_EDP,
15844 };
c4a1d9e4
CW		 15845 int i;
15846
63b66e5b
CW		 15847 if (INTEL_INFO(dev)->num_pipes == 0)
15848 return NULL;
15849
9d1cb914 15850 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15851 if (error == NULL)
15852 return NULL;
15853
190be112 15854 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15855 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15856
055e393f 15857 for_each_pipe(dev_priv, i) {
ddf9c536 15858 error->pipe[i].power_domain_on =
f458ebbc
DV		 15859 __intel_display_power_is_enabled(dev_priv,
15860 POWER_DOMAIN_PIPE(i));
ddf9c536 15861 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15862 continue;
15863
5efb3e28
VS		 15864 error->cursor[i].control = I915_READ(CURCNTR(i));
15865 error->cursor[i].position = I915_READ(CURPOS(i));
15866 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15867
15868 error->plane[i].control = I915_READ(DSPCNTR(i));
15869 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15870 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15871 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15872 error->plane[i].pos = I915_READ(DSPPOS(i));
15873 }
ca291363
PZ		 15874 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15875 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15876 if (INTEL_INFO(dev)->gen >= 4) {
15877 error->plane[i].surface = I915_READ(DSPSURF(i));
15878 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15879 }
15880
c4a1d9e4 15881 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15882
3abfce77 15883 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15884 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15885 }
15886
15887 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15888 if (HAS_DDI(dev_priv->dev))
15889 error->num_transcoders++; /* Account for eDP. */
15890
15891 for (i = 0; i < error->num_transcoders; i++) {
15892 enum transcoder cpu_transcoder = transcoders[i];
15893
ddf9c536 15894 error->transcoder[i].power_domain_on =
f458ebbc 15895 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15896 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15897 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15898 continue;
15899
63b66e5b
CW		 15900 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15901
15902 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15903 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15904 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15905 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15906 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15907 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15908 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15909 }
15910
15911 return error;
15912}
15913
edc3d884
MK		 15914#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15915
c4a1d9e4 15916void
edc3d884 15917intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15918 struct drm_device *dev,
15919 struct intel_display_error_state *error)
15920{
055e393f 15921 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15922 int i;
15923
63b66e5b
CW		 15924 if (!error)
15925 return;
15926
edc3d884 15927 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15928 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15929 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15930 error->power_well_driver);
055e393f 15931 for_each_pipe(dev_priv, i) {
edc3d884 15932 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15933 err_printf(m, " Power: %s\n",
15934 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15935 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15936 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15937
15938 err_printf(m, "Plane [%d]:\n", i);
15939 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15940 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15941 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15942 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15943 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15944 }
4b71a570 15945 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15946 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15947 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15948 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15949 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15950 }
15951
edc3d884
MK		 15952 err_printf(m, "Cursor [%d]:\n", i);
15953 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15954 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15955 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15956 }
63b66e5b
CW		 15957
15958 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15959 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15960 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15961 err_printf(m, " Power: %s\n",
15962 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15963 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15964 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15965 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15966 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15967 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15968 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15969 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15970 }
c4a1d9e4 15971}
e2fcdaa9
VS		 15972
15973void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15974{
15975 struct intel_crtc *crtc;
15976
15977 for_each_intel_crtc(dev, crtc) {
15978 struct intel_unpin_work *work;
e2fcdaa9 15979
5e2d7afc 15980 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15981
15982 work = crtc->unpin_work;
15983
15984 if (work && work->event &&
15985 work->event->base.file_priv == file) {
15986 kfree(work->event);
15987 work->event = NULL;
15988 }
15989
5e2d7afc 15990 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15991 }
15992}
Linux kernel - Deliverables
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