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drm/i915: Ensure cache flushes prior to doing CS flips
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
8c7b5ccb 85static int intel_set_mode(struct drm_crtc *crtc,
83a57153 86 struct drm_atomic_state *state);
eb1bfe80
JB		 87static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
5b18e57c
DV		 91static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 93static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
29407aab 96static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 97static void haswell_set_pipeconf(struct drm_crtc *crtc);
98static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 99static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 100 const struct intel_crtc_state *pipe_config);
d288f65f 101static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 102 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 103static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 105static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
106 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 107static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
108 int num_connectors);
ce22dba9
ML		 109static void intel_crtc_enable_planes(struct drm_crtc *crtc);
110static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 111
0e32b39c
DA		 112static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
113{
114 if (!connector->mst_port)
115 return connector->encoder;
116 else
117 return &connector->mst_port->mst_encoders[pipe]->base;
118}
119
79e53945 120typedef struct {
0206e353 121 int min, max;
79e53945
JB		 122} intel_range_t;
123
124typedef struct {
0206e353
AJ		 125 int dot_limit;
126 int p2_slow, p2_fast;
79e53945
JB		 127} intel_p2_t;
128
d4906093
ML		 129typedef struct intel_limit intel_limit_t;
130struct intel_limit {
0206e353
AJ		 131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
d4906093 133};
79e53945 134
d2acd215
DV		 135int
136intel_pch_rawclk(struct drm_device *dev)
137{
138 struct drm_i915_private *dev_priv = dev->dev_private;
139
140 WARN_ON(!HAS_PCH_SPLIT(dev));
141
142 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
143}
144
021357ac
CW		 145static inline u32 /* units of 100MHz */
146intel_fdi_link_freq(struct drm_device *dev)
147{
8b99e68c
CW		 148 if (IS_GEN5(dev)) {
149 struct drm_i915_private *dev_priv = dev->dev_private;
150 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
151 } else
152 return 27;
021357ac
CW		 153}
154
5d536e28 155static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 156 .dot = { .min = 25000, .max = 350000 },
9c333719 157 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 158 .n = { .min = 2, .max = 16 },
0206e353
AJ		 159 .m = { .min = 96, .max = 140 },
160 .m1 = { .min = 18, .max = 26 },
161 .m2 = { .min = 6, .max = 16 },
162 .p = { .min = 4, .max = 128 },
163 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 166};
167
5d536e28
DV		 168static const intel_limit_t intel_limits_i8xx_dvo = {
169 .dot = { .min = 25000, .max = 350000 },
9c333719 170 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 171 .n = { .min = 2, .max = 16 },
5d536e28
DV		 172 .m = { .min = 96, .max = 140 },
173 .m1 = { .min = 18, .max = 26 },
174 .m2 = { .min = 6, .max = 16 },
175 .p = { .min = 4, .max = 128 },
176 .p1 = { .min = 2, .max = 33 },
177 .p2 = { .dot_limit = 165000,
178 .p2_slow = 4, .p2_fast = 4 },
179};
180
e4b36699 181static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 182 .dot = { .min = 25000, .max = 350000 },
9c333719 183 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 184 .n = { .min = 2, .max = 16 },
0206e353
AJ		 185 .m = { .min = 96, .max = 140 },
186 .m1 = { .min = 18, .max = 26 },
187 .m2 = { .min = 6, .max = 16 },
188 .p = { .min = 4, .max = 128 },
189 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 14, .p2_fast = 7 },
e4b36699 192};
273e27ca 193
e4b36699 194static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 195 .dot = { .min = 20000, .max = 400000 },
196 .vco = { .min = 1400000, .max = 2800000 },
197 .n = { .min = 1, .max = 6 },
198 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 199 .m1 = { .min = 8, .max = 18 },
200 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 201 .p = { .min = 5, .max = 80 },
202 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 203 .p2 = { .dot_limit = 200000,
204 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 205};
206
207static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 208 .dot = { .min = 20000, .max = 400000 },
209 .vco = { .min = 1400000, .max = 2800000 },
210 .n = { .min = 1, .max = 6 },
211 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 212 .m1 = { .min = 8, .max = 18 },
213 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 214 .p = { .min = 7, .max = 98 },
215 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 216 .p2 = { .dot_limit = 112000,
217 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 218};
219
273e27ca 220
e4b36699 221static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 222 .dot = { .min = 25000, .max = 270000 },
223 .vco = { .min = 1750000, .max = 3500000},
224 .n = { .min = 1, .max = 4 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 10, .max = 30 },
229 .p1 = { .min = 1, .max = 3},
230 .p2 = { .dot_limit = 270000,
231 .p2_slow = 10,
232 .p2_fast = 10
044c7c41 233 },
e4b36699
KP		 234};
235
236static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 237 .dot = { .min = 22000, .max = 400000 },
238 .vco = { .min = 1750000, .max = 3500000},
239 .n = { .min = 1, .max = 4 },
240 .m = { .min = 104, .max = 138 },
241 .m1 = { .min = 16, .max = 23 },
242 .m2 = { .min = 5, .max = 11 },
243 .p = { .min = 5, .max = 80 },
244 .p1 = { .min = 1, .max = 8},
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 247};
248
249static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 250 .dot = { .min = 20000, .max = 115000 },
251 .vco = { .min = 1750000, .max = 3500000 },
252 .n = { .min = 1, .max = 3 },
253 .m = { .min = 104, .max = 138 },
254 .m1 = { .min = 17, .max = 23 },
255 .m2 = { .min = 5, .max = 11 },
256 .p = { .min = 28, .max = 112 },
257 .p1 = { .min = 2, .max = 8 },
258 .p2 = { .dot_limit = 0,
259 .p2_slow = 14, .p2_fast = 14
044c7c41 260 },
e4b36699
KP		 261};
262
263static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 264 .dot = { .min = 80000, .max = 224000 },
265 .vco = { .min = 1750000, .max = 3500000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 104, .max = 138 },
268 .m1 = { .min = 17, .max = 23 },
269 .m2 = { .min = 5, .max = 11 },
270 .p = { .min = 14, .max = 42 },
271 .p1 = { .min = 2, .max = 6 },
272 .p2 = { .dot_limit = 0,
273 .p2_slow = 7, .p2_fast = 7
044c7c41 274 },
e4b36699
KP		 275};
276
f2b115e6 277static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 278 .dot = { .min = 20000, .max = 400000},
279 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 280 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 281 .n = { .min = 3, .max = 6 },
282 .m = { .min = 2, .max = 256 },
273e27ca 283 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 284 .m1 = { .min = 0, .max = 0 },
285 .m2 = { .min = 0, .max = 254 },
286 .p = { .min = 5, .max = 80 },
287 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 288 .p2 = { .dot_limit = 200000,
289 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 290};
291
f2b115e6 292static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 293 .dot = { .min = 20000, .max = 400000 },
294 .vco = { .min = 1700000, .max = 3500000 },
295 .n = { .min = 3, .max = 6 },
296 .m = { .min = 2, .max = 256 },
297 .m1 = { .min = 0, .max = 0 },
298 .m2 = { .min = 0, .max = 254 },
299 .p = { .min = 7, .max = 112 },
300 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 301 .p2 = { .dot_limit = 112000,
302 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 303};
304
273e27ca
EA		 305/* Ironlake / Sandybridge
306 *
307 * We calculate clock using (register_value + 2) for N/M1/M2, so here
308 * the range value for them is (actual_value - 2).
309 */
b91ad0ec 310static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 5 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 5, .max = 80 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 321};
322
b91ad0ec 323static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 324 .dot = { .min = 25000, .max = 350000 },
325 .vco = { .min = 1760000, .max = 3510000 },
326 .n = { .min = 1, .max = 3 },
327 .m = { .min = 79, .max = 118 },
328 .m1 = { .min = 12, .max = 22 },
329 .m2 = { .min = 5, .max = 9 },
330 .p = { .min = 28, .max = 112 },
331 .p1 = { .min = 2, .max = 8 },
332 .p2 = { .dot_limit = 225000,
333 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 334};
335
336static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 337 .dot = { .min = 25000, .max = 350000 },
338 .vco = { .min = 1760000, .max = 3510000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 79, .max = 127 },
341 .m1 = { .min = 12, .max = 22 },
342 .m2 = { .min = 5, .max = 9 },
343 .p = { .min = 14, .max = 56 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 225000,
346 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 347};
348
273e27ca 349/* LVDS 100mhz refclk limits. */
b91ad0ec 350static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 351 .dot = { .min = 25000, .max = 350000 },
352 .vco = { .min = 1760000, .max = 3510000 },
353 .n = { .min = 1, .max = 2 },
354 .m = { .min = 79, .max = 126 },
355 .m1 = { .min = 12, .max = 22 },
356 .m2 = { .min = 5, .max = 9 },
357 .p = { .min = 28, .max = 112 },
0206e353 358 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 359 .p2 = { .dot_limit = 225000,
360 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374};
375
dc730512 376static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 384 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 385 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
b99ab663 388 .p1 = { .min = 2, .max = 3 },
5fdc9c49 389 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 390};
391
ef9348c8
CML		 392static const intel_limit_t intel_limits_chv = {
393 /*
394 * These are the data rate limits (measured in fast clocks)
395 * since those are the strictest limits we have. The fast
396 * clock and actual rate limits are more relaxed, so checking
397 * them would make no difference.
398 */
399 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 400 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 401 .n = { .min = 1, .max = 1 },
402 .m1 = { .min = 2, .max = 2 },
403 .m2 = { .min = 24 << 22, .max = 175 << 22 },
404 .p1 = { .min = 2, .max = 4 },
405 .p2 = { .p2_slow = 1, .p2_fast = 14 },
406};
407
5ab7b0b7
ID		 408static const intel_limit_t intel_limits_bxt = {
409 /* FIXME: find real dot limits */
410 .dot = { .min = 0, .max = INT_MAX },
411 .vco = { .min = 4800000, .max = 6480000 },
412 .n = { .min = 1, .max = 1 },
413 .m1 = { .min = 2, .max = 2 },
414 /* FIXME: find real m2 limits */
415 .m2 = { .min = 2 << 22, .max = 255 << 22 },
416 .p1 = { .min = 2, .max = 4 },
417 .p2 = { .p2_slow = 1, .p2_fast = 20 },
418};
419
6b4bf1c4
VS		 420static void vlv_clock(int refclk, intel_clock_t *clock)
421{
422 clock->m = clock->m1 * clock->m2;
423 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 424 if (WARN_ON(clock->n == 0 || clock->p == 0))
425 return;
fb03ac01
VS		 426 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
427 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 428}
429
e0638cdf
PZ		 430/**
431 * Returns whether any output on the specified pipe is of the specified type
432 */
4093561b 433bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 434{
409ee761 435 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 436 struct intel_encoder *encoder;
437
409ee761 438 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 439 if (encoder->type == type)
440 return true;
441
442 return false;
443}
444
d0737e1d
ACO		 445/**
446 * Returns whether any output on the specified pipe will have the specified
447 * type after a staged modeset is complete, i.e., the same as
448 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
449 * encoder->crtc.
450 */
a93e255f
ACO		 451static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
452 int type)
d0737e1d 453{
a93e255f 454 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 455 struct drm_connector *connector;
a93e255f 456 struct drm_connector_state *connector_state;
d0737e1d 457 struct intel_encoder *encoder;
a93e255f
ACO		 458 int i, num_connectors = 0;
459
da3ced29 460 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 461 if (connector_state->crtc != crtc_state->base.crtc)
462 continue;
463
464 num_connectors++;
d0737e1d 465
a93e255f
ACO		 466 encoder = to_intel_encoder(connector_state->best_encoder);
467 if (encoder->type == type)
d0737e1d 468 return true;
a93e255f
ACO		 469 }
470
471 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 472
473 return false;
474}
475
a93e255f
ACO		 476static const intel_limit_t *
477intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 478{
a93e255f 479 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 480 const intel_limit_t *limit;
b91ad0ec 481
a93e255f 482 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 483 if (intel_is_dual_link_lvds(dev)) {
1b894b59 484 if (refclk == 100000)
b91ad0ec
ZW		 485 limit = &intel_limits_ironlake_dual_lvds_100m;
486 else
487 limit = &intel_limits_ironlake_dual_lvds;
488 } else {
1b894b59 489 if (refclk == 100000)
b91ad0ec
ZW		 490 limit = &intel_limits_ironlake_single_lvds_100m;
491 else
492 limit = &intel_limits_ironlake_single_lvds;
493 }
c6bb3538 494 } else
b91ad0ec 495 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 496
497 return limit;
498}
499
a93e255f
ACO		 500static const intel_limit_t *
501intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 502{
a93e255f 503 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 504 const intel_limit_t *limit;
505
a93e255f 506 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 507 if (intel_is_dual_link_lvds(dev))
e4b36699 508 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 509 else
e4b36699 510 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
512 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 513 limit = &intel_limits_g4x_hdmi;
a93e255f 514 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 515 limit = &intel_limits_g4x_sdvo;
044c7c41 516 } else /* The option is for other outputs */
e4b36699 517 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 518
519 return limit;
520}
521
a93e255f
ACO		 522static const intel_limit_t *
523intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 524{
a93e255f 525 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 526 const intel_limit_t *limit;
527
5ab7b0b7
ID		 528 if (IS_BROXTON(dev))
529 limit = &intel_limits_bxt;
530 else if (HAS_PCH_SPLIT(dev))
a93e255f 531 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 532 else if (IS_G4X(dev)) {
a93e255f 533 limit = intel_g4x_limit(crtc_state);
f2b115e6 534 } else if (IS_PINEVIEW(dev)) {
a93e255f 535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 536 limit = &intel_limits_pineview_lvds;
2177832f 537 else
f2b115e6 538 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 539 } else if (IS_CHERRYVIEW(dev)) {
540 limit = &intel_limits_chv;
a0c4da24 541 } else if (IS_VALLEYVIEW(dev)) {
dc730512 542 limit = &intel_limits_vlv;
a6c45cf0 543 } else if (!IS_GEN2(dev)) {
a93e255f 544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 545 limit = &intel_limits_i9xx_lvds;
546 else
547 limit = &intel_limits_i9xx_sdvo;
79e53945 548 } else {
a93e255f 549 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 550 limit = &intel_limits_i8xx_lvds;
a93e255f 551 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 552 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 553 else
554 limit = &intel_limits_i8xx_dac;
79e53945
JB		 555 }
556 return limit;
557}
558
f2b115e6
AJ		 559/* m1 is reserved as 0 in Pineview, n is a ring counter */
560static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 561{
2177832f
SL		 562 clock->m = clock->m2 + 2;
563 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 564 if (WARN_ON(clock->n == 0 || clock->p == 0))
565 return;
fb03ac01
VS		 566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 568}
569
7429e9d4
DV		 570static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571{
572 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
573}
574
ac58c3f0 575static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 576{
7429e9d4 577 clock->m = i9xx_dpll_compute_m(clock);
79e53945 578 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 579 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 return;
fb03ac01
VS		 581 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
582 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 583}
584
ef9348c8
CML		 585static void chv_clock(int refclk, intel_clock_t *clock)
586{
587 clock->m = clock->m1 * clock->m2;
588 clock->p = clock->p1 * clock->p2;
589 if (WARN_ON(clock->n == 0 || clock->p == 0))
590 return;
591 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
592 clock->n << 22);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594}
595
7c04d1d9 596#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 597/**
598 * Returns whether the given set of divisors are valid for a given refclk with
599 * the given connectors.
600 */
601
1b894b59
CW		 602static bool intel_PLL_is_valid(struct drm_device *dev,
603 const intel_limit_t *limit,
604 const intel_clock_t *clock)
79e53945 605{
f01b7962
VS		 606 if (clock->n < limit->n.min || limit->n.max < clock->n)
607 INTELPllInvalid("n out of range\n");
79e53945 608 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 609 INTELPllInvalid("p1 out of range\n");
79e53945 610 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 611 INTELPllInvalid("m2 out of range\n");
79e53945 612 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 613 INTELPllInvalid("m1 out of range\n");
f01b7962 614
5ab7b0b7 615 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 616 if (clock->m1 <= clock->m2)
617 INTELPllInvalid("m1 <= m2\n");
618
5ab7b0b7 619 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 620 if (clock->p < limit->p.min || limit->p.max < clock->p)
621 INTELPllInvalid("p out of range\n");
622 if (clock->m < limit->m.min || limit->m.max < clock->m)
623 INTELPllInvalid("m out of range\n");
624 }
625
79e53945 626 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 627 INTELPllInvalid("vco out of range\n");
79e53945
JB		 628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
630 */
631 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 632 INTELPllInvalid("dot out of range\n");
79e53945
JB		 633
634 return true;
635}
636
d4906093 637static bool
a93e255f
ACO		 638i9xx_find_best_dpll(const intel_limit_t *limit,
639 struct intel_crtc_state *crtc_state,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
79e53945 642{
a93e255f 643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 644 struct drm_device *dev = crtc->base.dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a93e255f 648 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 671 if (clock.m2 >= clock.m1)
42158660
ZY		 672 break;
673 for (clock.n = limit->n.min;
674 clock.n <= limit->n.max; clock.n++) {
675 for (clock.p1 = limit->p1.min;
676 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 677 int this_err;
678
ac58c3f0
DV		 679 i9xx_clock(refclk, &clock);
680 if (!intel_PLL_is_valid(dev, limit,
681 &clock))
682 continue;
683 if (match_clock &&
684 clock.p != match_clock->p)
685 continue;
686
687 this_err = abs(clock.dot - target);
688 if (this_err < err) {
689 *best_clock = clock;
690 err = this_err;
691 }
692 }
693 }
694 }
695 }
696
697 return (err != target);
698}
699
700static bool
a93e255f
ACO		 701pnv_find_best_dpll(const intel_limit_t *limit,
702 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
79e53945 705{
a93e255f 706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 707 struct drm_device *dev = crtc->base.dev;
79e53945 708 intel_clock_t clock;
79e53945
JB		 709 int err = target;
710
a93e255f 711 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 712 /*
a210b028
DV		 713 * For LVDS just rely on its current settings for dual-channel.
714 * We haven't figured out how to reliably set up different
715 * single/dual channel state, if we even can.
79e53945 716 */
1974cad0 717 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
0206e353 728 memset(best_clock, 0, sizeof(*best_clock));
79e53945 729
42158660
ZY		 730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 738 int this_err;
739
ac58c3f0 740 pineview_clock(refclk, &clock);
1b894b59
CW		 741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
79e53945 743 continue;
cec2f356
SP		 744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
79e53945
JB		 747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759}
760
d4906093 761static bool
a93e255f
ACO		 762g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
d4906093 766{
a93e255f 767 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 768 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 769 intel_clock_t clock;
770 int max_n;
771 bool found;
6ba770dc
AJ		 772 /* approximately equals target * 0.00585 */
773 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 774 found = false;
775
a93e255f 776 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 777 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 778 clock.p2 = limit->p2.p2_fast;
779 else
780 clock.p2 = limit->p2.p2_slow;
781 } else {
782 if (target < limit->p2.dot_limit)
783 clock.p2 = limit->p2.p2_slow;
784 else
785 clock.p2 = limit->p2.p2_fast;
786 }
787
788 memset(best_clock, 0, sizeof(*best_clock));
789 max_n = limit->n.max;
f77f13e2 790 /* based on hardware requirement, prefer smaller n to precision */
d4906093 791 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 792 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 793 for (clock.m1 = limit->m1.max;
794 clock.m1 >= limit->m1.min; clock.m1--) {
795 for (clock.m2 = limit->m2.max;
796 clock.m2 >= limit->m2.min; clock.m2--) {
797 for (clock.p1 = limit->p1.max;
798 clock.p1 >= limit->p1.min; clock.p1--) {
799 int this_err;
800
ac58c3f0 801 i9xx_clock(refclk, &clock);
1b894b59
CW		 802 if (!intel_PLL_is_valid(dev, limit,
803 &clock))
d4906093 804 continue;
1b894b59
CW		 805
806 this_err = abs(clock.dot - target);
d4906093
ML		 807 if (this_err < err_most) {
808 *best_clock = clock;
809 err_most = this_err;
810 max_n = clock.n;
811 found = true;
812 }
813 }
814 }
815 }
816 }
2c07245f
ZW		 817 return found;
818}
819
d5dd62bd
ID		 820/*
821 * Check if the calculated PLL configuration is more optimal compared to the
822 * best configuration and error found so far. Return the calculated error.
823 */
824static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
825 const intel_clock_t *calculated_clock,
826 const intel_clock_t *best_clock,
827 unsigned int best_error_ppm,
828 unsigned int *error_ppm)
829{
9ca3ba01
ID		 830 /*
831 * For CHV ignore the error and consider only the P value.
832 * Prefer a bigger P value based on HW requirements.
833 */
834 if (IS_CHERRYVIEW(dev)) {
835 *error_ppm = 0;
836
837 return calculated_clock->p > best_clock->p;
838 }
839
24be4e46
ID		 840 if (WARN_ON_ONCE(!target_freq))
841 return false;
842
d5dd62bd
ID		 843 *error_ppm = div_u64(1000000ULL *
844 abs(target_freq - calculated_clock->dot),
845 target_freq);
846 /*
847 * Prefer a better P value over a better (smaller) error if the error
848 * is small. Ensure this preference for future configurations too by
849 * setting the error to 0.
850 */
851 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
852 *error_ppm = 0;
853
854 return true;
855 }
856
857 return *error_ppm + 10 < best_error_ppm;
858}
859
a0c4da24 860static bool
a93e255f
ACO		 861vlv_find_best_dpll(const intel_limit_t *limit,
862 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
a0c4da24 865{
a93e255f 866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 867 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 868 intel_clock_t clock;
69e4f900 869 unsigned int bestppm = 1000000;
27e639bf
VS		 870 /* min update 19.2 MHz */
871 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 872 bool found = false;
a0c4da24 873
6b4bf1c4
VS		 874 target *= 5; /* fast clock */
875
876 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 877
878 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 879 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 880 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 881 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 882 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 883 clock.p = clock.p1 * clock.p2;
a0c4da24 884 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 885 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 886 unsigned int ppm;
69e4f900 887
6b4bf1c4
VS		 888 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
889 refclk * clock.m1);
890
891 vlv_clock(refclk, &clock);
43b0ac53 892
f01b7962
VS		 893 if (!intel_PLL_is_valid(dev, limit,
894 &clock))
43b0ac53
VS		 895 continue;
896
d5dd62bd
ID		 897 if (!vlv_PLL_is_optimal(dev, target,
898 &clock,
899 best_clock,
900 bestppm, &ppm))
901 continue;
6b4bf1c4 902
d5dd62bd
ID		 903 *best_clock = clock;
904 bestppm = ppm;
905 found = true;
a0c4da24
JB		 906 }
907 }
908 }
909 }
a0c4da24 910
49e497ef 911 return found;
a0c4da24 912}
a4fc5ed6 913
ef9348c8 914static bool
a93e255f
ACO		 915chv_find_best_dpll(const intel_limit_t *limit,
916 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 917 int target, int refclk, intel_clock_t *match_clock,
918 intel_clock_t *best_clock)
919{
a93e255f 920 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 921 struct drm_device *dev = crtc->base.dev;
9ca3ba01 922 unsigned int best_error_ppm;
ef9348c8
CML		 923 intel_clock_t clock;
924 uint64_t m2;
925 int found = false;
926
927 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 928 best_error_ppm = 1000000;
ef9348c8
CML		 929
930 /*
931 * Based on hardware doc, the n always set to 1, and m1 always
932 * set to 2. If requires to support 200Mhz refclk, we need to
933 * revisit this because n may not 1 anymore.
934 */
935 clock.n = 1, clock.m1 = 2;
936 target *= 5; /* fast clock */
937
938 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
939 for (clock.p2 = limit->p2.p2_fast;
940 clock.p2 >= limit->p2.p2_slow;
941 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 942 unsigned int error_ppm;
ef9348c8
CML		 943
944 clock.p = clock.p1 * clock.p2;
945
946 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
947 clock.n) << 22, refclk * clock.m1);
948
949 if (m2 > INT_MAX/clock.m1)
950 continue;
951
952 clock.m2 = m2;
953
954 chv_clock(refclk, &clock);
955
956 if (!intel_PLL_is_valid(dev, limit, &clock))
957 continue;
958
9ca3ba01
ID		 959 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
960 best_error_ppm, &error_ppm))
961 continue;
962
963 *best_clock = clock;
964 best_error_ppm = error_ppm;
965 found = true;
ef9348c8
CML		 966 }
967 }
968
969 return found;
970}
971
5ab7b0b7
ID		 972bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
973 intel_clock_t *best_clock)
974{
975 int refclk = i9xx_get_refclk(crtc_state, 0);
976
977 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
978 target_clock, refclk, NULL, best_clock);
979}
980
20ddf665
VS		 981bool intel_crtc_active(struct drm_crtc *crtc)
982{
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984
985 /* Be paranoid as we can arrive here with only partial
986 * state retrieved from the hardware during setup.
987 *
241bfc38 988 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 989 * as Haswell has gained clock readout/fastboot support.
990 *
66e514c1 991 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 992 * properly reconstruct framebuffers.
c3d1f436
MR		 993 *
994 * FIXME: The intel_crtc->active here should be switched to
995 * crtc->state->active once we have proper CRTC states wired up
996 * for atomic.
20ddf665 997 */
c3d1f436 998 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 999 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1000}
1001
a5c961d1
PZ		 1002enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1003 enum pipe pipe)
1004{
1005 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007
6e3c9717 1008 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1009}
1010
fbf49ea2
VS		 1011static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1012{
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 u32 reg = PIPEDSL(pipe);
1015 u32 line1, line2;
1016 u32 line_mask;
1017
1018 if (IS_GEN2(dev))
1019 line_mask = DSL_LINEMASK_GEN2;
1020 else
1021 line_mask = DSL_LINEMASK_GEN3;
1022
1023 line1 = I915_READ(reg) & line_mask;
1024 mdelay(5);
1025 line2 = I915_READ(reg) & line_mask;
1026
1027 return line1 == line2;
1028}
1029
ab7ad7f6
KP		 1030/*
1031 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1032 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1033 *
1034 * After disabling a pipe, we can't wait for vblank in the usual way,
1035 * spinning on the vblank interrupt status bit, since we won't actually
1036 * see an interrupt when the pipe is disabled.
1037 *
ab7ad7f6
KP		 1038 * On Gen4 and above:
1039 * wait for the pipe register state bit to turn off
1040 *
1041 * Otherwise:
1042 * wait for the display line value to settle (it usually
1043 * ends up stopping at the start of the next frame).
58e10eb9 1044 *
9d0498a2 1045 */
575f7ab7 1046static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1047{
575f7ab7 1048 struct drm_device *dev = crtc->base.dev;
9d0498a2 1049 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1050 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1051 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1052
1053 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1054 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1055
1056 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1057 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1058 100))
284637d9 1059 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1060 } else {
ab7ad7f6 1061 /* Wait for the display line to settle */
fbf49ea2 1062 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 }
79e53945
JB		 1065}
1066
b0ea7d37
DL		 1067/*
1068 * ibx_digital_port_connected - is the specified port connected?
1069 * @dev_priv: i915 private structure
1070 * @port: the port to test
1071 *
1072 * Returns true if @port is connected, false otherwise.
1073 */
1074bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1075 struct intel_digital_port *port)
1076{
1077 u32 bit;
1078
c36346e3 1079 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1080 switch (port->port) {
c36346e3
DL		 1081 case PORT_B:
1082 bit = SDE_PORTB_HOTPLUG;
1083 break;
1084 case PORT_C:
1085 bit = SDE_PORTC_HOTPLUG;
1086 break;
1087 case PORT_D:
1088 bit = SDE_PORTD_HOTPLUG;
1089 break;
1090 default:
1091 return true;
1092 }
1093 } else {
eba905b2 1094 switch (port->port) {
c36346e3
DL		 1095 case PORT_B:
1096 bit = SDE_PORTB_HOTPLUG_CPT;
1097 break;
1098 case PORT_C:
1099 bit = SDE_PORTC_HOTPLUG_CPT;
1100 break;
1101 case PORT_D:
1102 bit = SDE_PORTD_HOTPLUG_CPT;
1103 break;
1104 default:
1105 return true;
1106 }
b0ea7d37
DL		 1107 }
1108
1109 return I915_READ(SDEISR) & bit;
1110}
1111
b24e7179
JB		 1112static const char *state_string(bool enabled)
1113{
1114 return enabled ? "on" : "off";
1115}
1116
1117/* Only for pre-ILK configs */
55607e8a
DV		 1118void assert_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
b24e7179
JB		 1120{
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124
1125 reg = DPLL(pipe);
1126 val = I915_READ(reg);
1127 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1128 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1131}
b24e7179 1132
23538ef1
JN		 1133/* XXX: the dsi pll is shared between MIPI DSI ports */
1134static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135{
1136 u32 val;
1137 bool cur_state;
1138
1139 mutex_lock(&dev_priv->dpio_lock);
1140 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141 mutex_unlock(&dev_priv->dpio_lock);
1142
1143 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1144 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state), state_string(cur_state));
1147}
1148#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
55607e8a 1151struct intel_shared_dpll *
e2b78267
DV		 1152intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153{
1154 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
6e3c9717 1156 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1157 return NULL;
1158
6e3c9717 1159 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1160}
1161
040484af 1162/* For ILK+ */
55607e8a
DV		 1163void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164 struct intel_shared_dpll *pll,
1165 bool state)
040484af 1166{
040484af 1167 bool cur_state;
5358901f 1168 struct intel_dpll_hw_state hw_state;
040484af 1169
92b27b08 1170 if (WARN (!pll,
46edb027 1171 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1172 return;
ee7b9f93 1173
5358901f 1174 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1175 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1176 "%s assertion failure (expected %s, current %s)\n",
1177 pll->name, state_string(state), state_string(cur_state));
040484af 1178}
040484af
JB		 1179
1180static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182{
1183 int reg;
1184 u32 val;
1185 bool cur_state;
ad80a810
PZ		 1186 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187 pipe);
040484af 1188
affa9354
PZ		 1189 if (HAS_DDI(dev_priv->dev)) {
1190 /* DDI does not have a specific FDI_TX register */
ad80a810 1191 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1192 val = I915_READ(reg);
ad80a810 1193 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1194 } else {
1195 reg = FDI_TX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_TX_ENABLE);
1198 }
e2c719b7 1199 I915_STATE_WARN(cur_state != state,
040484af
JB		 1200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1202}
1203#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1208{
1209 int reg;
1210 u32 val;
1211 bool cur_state;
1212
d63fa0dc
PZ		 1213 reg = FDI_RX_CTL(pipe);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1216 I915_STATE_WARN(cur_state != state,
040484af
JB		 1217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state), state_string(cur_state));
1219}
1220#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224 enum pipe pipe)
1225{
1226 int reg;
1227 u32 val;
1228
1229 /* ILK FDI PLL is always enabled */
3d13ef2e 1230 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1231 return;
1232
bf507ef7 1233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1234 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1235 return;
1236
040484af
JB		 1237 reg = FDI_TX_CTL(pipe);
1238 val = I915_READ(reg);
e2c719b7 1239 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1240}
1241
55607e8a
DV		 1242void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
040484af
JB		 1244{
1245 int reg;
1246 u32 val;
55607e8a 1247 bool cur_state;
040484af
JB		 1248
1249 reg = FDI_RX_CTL(pipe);
1250 val = I915_READ(reg);
55607e8a 1251 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1252 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state), state_string(cur_state));
040484af
JB		 1255}
1256
b680c37a
DV		 1257void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
ea0760cf 1259{
bedd4dba
JN		 1260 struct drm_device *dev = dev_priv->dev;
1261 int pp_reg;
ea0760cf
JB		 1262 u32 val;
1263 enum pipe panel_pipe = PIPE_A;
0de3b485 1264 bool locked = true;
ea0760cf 1265
bedd4dba
JN		 1266 if (WARN_ON(HAS_DDI(dev)))
1267 return;
1268
1269 if (HAS_PCH_SPLIT(dev)) {
1270 u32 port_sel;
1271
ea0760cf 1272 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1273 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277 panel_pipe = PIPE_B;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282 panel_pipe = pipe;
ea0760cf
JB		 1283 } else {
1284 pp_reg = PP_CONTROL;
bedd4dba
JN		 1285 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
ea0760cf
JB		 1287 }
1288
1289 val = I915_READ(pp_reg);
1290 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1291 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1292 locked = false;
1293
e2c719b7 1294 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1295 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1296 pipe_name(pipe));
ea0760cf
JB		 1297}
1298
93ce0ba6
JN		 1299static void assert_cursor(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, bool state)
1301{
1302 struct drm_device *dev = dev_priv->dev;
1303 bool cur_state;
1304
d9d82081 1305 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1306 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1307 else
5efb3e28 1308 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1309
e2c719b7 1310 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), state_string(state), state_string(cur_state));
1313}
1314#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
b840d907
JB		 1317void assert_pipe(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, bool state)
b24e7179
JB		 1319{
1320 int reg;
1321 u32 val;
63d7bbe9 1322 bool cur_state;
702e7a56
PZ		 1323 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324 pipe);
b24e7179 1325
b6b5d049
VS		 1326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1329 state = true;
1330
f458ebbc 1331 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1332 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1333 cur_state = false;
1334 } else {
1335 reg = PIPECONF(cpu_transcoder);
1336 val = I915_READ(reg);
1337 cur_state = !!(val & PIPECONF_ENABLE);
1338 }
1339
e2c719b7 1340 I915_STATE_WARN(cur_state != state,
63d7bbe9 1341 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1342 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1343}
1344
931872fc
CW		 1345static void assert_plane(struct drm_i915_private *dev_priv,
1346 enum plane plane, bool state)
b24e7179
JB		 1347{
1348 int reg;
1349 u32 val;
931872fc 1350 bool cur_state;
b24e7179
JB		 1351
1352 reg = DSPCNTR(plane);
1353 val = I915_READ(reg);
931872fc 1354 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1355 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1358}
1359
931872fc
CW		 1360#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
b24e7179
JB		 1363static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe)
1365{
653e1026 1366 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1367 int reg, i;
1368 u32 val;
1369 int cur_pipe;
1370
653e1026
VS		 1371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1373 reg = DSPCNTR(pipe);
1374 val = I915_READ(reg);
e2c719b7 1375 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1376 "plane %c assertion failure, should be disabled but not\n",
1377 plane_name(pipe));
19ec1358 1378 return;
28c05794 1379 }
19ec1358 1380
b24e7179 1381 /* Need to check both planes against the pipe */
055e393f 1382 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1383 reg = DSPCNTR(i);
1384 val = I915_READ(reg);
1385 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1387 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1390 }
1391}
1392
19332d7a
JB		 1393static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe)
1395{
20674eef 1396 struct drm_device *dev = dev_priv->dev;
1fe47785 1397 int reg, sprite;
19332d7a
JB		 1398 u32 val;
1399
7feb8b88 1400 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1401 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1402 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1403 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite, pipe_name(pipe));
1406 }
1407 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1408 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1409 reg = SPCNTR(pipe, sprite);
20674eef 1410 val = I915_READ(reg);
e2c719b7 1411 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1413 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1414 }
1415 } else if (INTEL_INFO(dev)->gen >= 7) {
1416 reg = SPRCTL(pipe);
19332d7a 1417 val = I915_READ(reg);
e2c719b7 1418 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 reg = DVSCNTR(pipe);
19332d7a 1423 val = I915_READ(reg);
e2c719b7 1424 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1426 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1427 }
1428}
1429
08c71e5e
VS		 1430static void assert_vblank_disabled(struct drm_crtc *crtc)
1431{
e2c719b7 1432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1433 drm_crtc_vblank_put(crtc);
1434}
1435
89eff4be 1436static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1437{
1438 u32 val;
1439 bool enabled;
1440
e2c719b7 1441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1442
92f2584a
JB		 1443 val = I915_READ(PCH_DREF_CONTROL);
1444 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1446 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1447}
1448
ab9412ba
DV		 1449static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe)
92f2584a
JB		 1451{
1452 int reg;
1453 u32 val;
1454 bool enabled;
1455
ab9412ba 1456 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1457 val = I915_READ(reg);
1458 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1459 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 pipe_name(pipe));
92f2584a
JB		 1462}
1463
4e634389
KP		 1464static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1466{
1467 if ((val & DP_PORT_EN) == 0)
1468 return false;
1469
1470 if (HAS_PCH_CPT(dev_priv->dev)) {
1471 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474 return false;
44f37d1f
CML		 1475 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477 return false;
f0575e92
KP		 1478 } else {
1479 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480 return false;
1481 }
1482 return true;
1483}
1484
1519b995
KP		 1485static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, u32 val)
1487{
dc0fa718 1488 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1489 return false;
1490
1491 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1492 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1493 return false;
44f37d1f
CML		 1494 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496 return false;
1519b995 1497 } else {
dc0fa718 1498 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1499 return false;
1500 }
1501 return true;
1502}
1503
1504static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505 enum pipe pipe, u32 val)
1506{
1507 if ((val & LVDS_PORT_EN) == 0)
1508 return false;
1509
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 return false;
1513 } else {
1514 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515 return false;
1516 }
1517 return true;
1518}
1519
1520static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521 enum pipe pipe, u32 val)
1522{
1523 if ((val & ADPA_DAC_ENABLE) == 0)
1524 return false;
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530 return false;
1531 }
1532 return true;
1533}
1534
291906f1 1535static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1536 enum pipe pipe, int reg, u32 port_sel)
291906f1 1537{
47a05eca 1538 u32 val = I915_READ(reg);
e2c719b7 1539 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1541 reg, pipe_name(pipe));
de9a35ab 1542
e2c719b7 1543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1544 && (val & DP_PIPEB_SELECT),
de9a35ab 1545 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1546}
1547
1548static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, int reg)
1550{
47a05eca 1551 u32 val = I915_READ(reg);
e2c719b7 1552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1554 reg, pipe_name(pipe));
de9a35ab 1555
e2c719b7 1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1557 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1558 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1559}
1560
1561static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562 enum pipe pipe)
1563{
1564 int reg;
1565 u32 val;
291906f1 1566
f0575e92
KP		 1567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1570
1571 reg = PCH_ADPA;
1572 val = I915_READ(reg);
e2c719b7 1573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1574 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1575 pipe_name(pipe));
291906f1
JB		 1576
1577 reg = PCH_LVDS;
1578 val = I915_READ(reg);
e2c719b7 1579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1581 pipe_name(pipe));
291906f1 1582
e2debe91
PZ		 1583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1586}
1587
40e9cf64
JB		 1588static void intel_init_dpio(struct drm_device *dev)
1589{
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 if (!IS_VALLEYVIEW(dev))
1593 return;
1594
a09caddd
CML		 1595 /*
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599 */
1600 if (IS_CHERRYVIEW(dev)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603 } else {
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 }
5382f5f3
JB		 1606}
1607
d288f65f 1608static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1609 const struct intel_crtc_state *pipe_config)
87442f73 1610{
426115cf
DV		 1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
d288f65f 1614 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1615
426115cf 1616 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1617
1618 /* No really, not for ILK+ */
1619 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1622 if (IS_MOBILE(dev_priv->dev))
426115cf 1623 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1624
426115cf
DV		 1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
d288f65f 1632 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1633 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1634
1635 /* We do this three times for luck */
426115cf 1636 I915_WRITE(reg, dpll);
87442f73
DV		 1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
426115cf 1639 I915_WRITE(reg, dpll);
87442f73
DV		 1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
426115cf 1642 I915_WRITE(reg, dpll);
87442f73
DV		 1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645}
1646
d288f65f 1647static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1648 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1649{
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 int pipe = crtc->pipe;
1653 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1654 u32 tmp;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660 mutex_lock(&dev_priv->dpio_lock);
1661
1662 /* Enable back the 10bit clock to display controller */
1663 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664 tmp |= DPIO_DCLKP_EN;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667 /*
1668 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1669 */
1670 udelay(1);
1671
1672 /* Enable PLL */
d288f65f 1673 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1674
1675 /* Check PLL is locked */
a11b0703 1676 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1677 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678
a11b0703 1679 /* not sure when this should be written */
d288f65f 1680 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1681 POSTING_READ(DPLL_MD(pipe));
1682
9d556c99
CML		 1683 mutex_unlock(&dev_priv->dpio_lock);
1684}
1685
1c4e0274
VS		 1686static int intel_num_dvo_pipes(struct drm_device *dev)
1687{
1688 struct intel_crtc *crtc;
1689 int count = 0;
1690
1691 for_each_intel_crtc(dev, crtc)
1692 count += crtc->active &&
409ee761 1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1694
1695 return count;
1696}
1697
66e3d5c0 1698static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1699{
66e3d5c0
DV		 1700 struct drm_device *dev = crtc->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int reg = DPLL(crtc->pipe);
6e3c9717 1703 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1704
66e3d5c0 1705 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1706
63d7bbe9 1707 /* No really, not for ILK+ */
3d13ef2e 1708 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1709
1710 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1711 if (IS_MOBILE(dev) && !IS_I830(dev))
1712 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1713
1c4e0274
VS		 1714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716 /*
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1721 */
1722 dpll |= DPLL_DVO_2X_MODE;
1723 I915_WRITE(DPLL(!crtc->pipe),
1724 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725 }
66e3d5c0
DV		 1726
1727 /* Wait for the clocks to stabilize. */
1728 POSTING_READ(reg);
1729 udelay(150);
1730
1731 if (INTEL_INFO(dev)->gen >= 4) {
1732 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1733 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1734 } else {
1735 /* The pixel multiplier can only be updated once the
1736 * DPLL is enabled and the clocks are stable.
1737 *
1738 * So write it again.
1739 */
1740 I915_WRITE(reg, dpll);
1741 }
63d7bbe9
JB		 1742
1743 /* We do this three times for luck */
66e3d5c0 1744 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
66e3d5c0 1747 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
66e3d5c0 1750 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1751 POSTING_READ(reg);
1752 udelay(150); /* wait for warmup */
1753}
1754
1755/**
50b44a44 1756 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1757 * @dev_priv: i915 private structure
1758 * @pipe: pipe PLL to disable
1759 *
1760 * Disable the PLL for @pipe, making sure the pipe is off first.
1761 *
1762 * Note! This is for pre-ILK only.
1763 */
1c4e0274 1764static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1765{
1c4e0274
VS		 1766 struct drm_device *dev = crtc->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 enum pipe pipe = crtc->pipe;
1769
1770 /* Disable DVO 2x clock on both PLLs if necessary */
1771 if (IS_I830(dev) &&
409ee761 1772 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1773 intel_num_dvo_pipes(dev) == 1) {
1774 I915_WRITE(DPLL(PIPE_B),
1775 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776 I915_WRITE(DPLL(PIPE_A),
1777 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778 }
1779
b6b5d049
VS		 1780 /* Don't disable pipe or pipe PLLs if needed */
1781 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1783 return;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
50b44a44
DV		 1788 I915_WRITE(DPLL(pipe), 0);
1789 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1790}
1791
f6071166
JB		 1792static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793{
1794 u32 val = 0;
1795
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv, pipe);
1798
e5cbfbfb
ID		 1799 /*
1800 * Leave integrated clock source and reference clock enabled for pipe B.
1801 * The latter is needed for VGA hotplug / manual detection.
1802 */
f6071166 1803 if (pipe == PIPE_B)
e5cbfbfb 1804 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1805 I915_WRITE(DPLL(pipe), val);
1806 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1807
1808}
1809
1810static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1811{
d752048d 1812 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1813 u32 val;
1814
a11b0703
VS		 1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1817
a11b0703 1818 /* Set PLL en = 0 */
d17ec4ce 1819 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
d752048d
VS		 1824
1825 mutex_lock(&dev_priv->dpio_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
61407f6d
VS		 1832 /* disable left/right clock distribution */
1833 if (pipe != PIPE_B) {
1834 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1835 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1836 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837 } else {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1839 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1841 }
1842
d752048d 1843 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1844}
1845
e4607fcf 1846void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1847 struct intel_digital_port *dport,
1848 unsigned int expected_mask)
89b667f8
JB		 1849{
1850 u32 port_mask;
00fc31b7 1851 int dpll_reg;
89b667f8 1852
e4607fcf
CML		 1853 switch (dport->port) {
1854 case PORT_B:
89b667f8 1855 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1856 dpll_reg = DPLL(0);
e4607fcf
CML		 1857 break;
1858 case PORT_C:
89b667f8 1859 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
9b6de0a1 1861 expected_mask <<= 4;
00fc31b7
CML		 1862 break;
1863 case PORT_D:
1864 port_mask = DPLL_PORTD_READY_MASK;
1865 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1866 break;
1867 default:
1868 BUG();
1869 }
89b667f8 1870
9b6de0a1
VS		 1871 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1872 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1873 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1874}
1875
b14b1055
DV		 1876static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877{
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
be19f0ff
CW		 1882 if (WARN_ON(pll == NULL))
1883 return;
1884
3e369b76 1885 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1886 if (pll->active == 0) {
1887 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 WARN_ON(pll->on);
1889 assert_shared_dpll_disabled(dev_priv, pll);
1890
1891 pll->mode_set(dev_priv, pll);
1892 }
1893}
1894
92f2584a 1895/**
85b3894f 1896 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1897 * @dev_priv: i915 private structure
1898 * @pipe: pipe PLL to enable
1899 *
1900 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901 * drives the transcoder clock.
1902 */
85b3894f 1903static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1904{
3d13ef2e
DL		 1905 struct drm_device *dev = crtc->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1908
87a875bb 1909 if (WARN_ON(pll == NULL))
48da64a8
CW		 1910 return;
1911
3e369b76 1912 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1913 return;
ee7b9f93 1914
74dd6928 1915 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1916 pll->name, pll->active, pll->on,
e2b78267 1917 crtc->base.base.id);
92f2584a 1918
cdbd2316
DV		 1919 if (pll->active++) {
1920 WARN_ON(!pll->on);
e9d6944e 1921 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1922 return;
1923 }
f4a091c7 1924 WARN_ON(pll->on);
ee7b9f93 1925
bd2bb1b9
PZ		 1926 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927
46edb027 1928 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1929 pll->enable(dev_priv, pll);
ee7b9f93 1930 pll->on = true;
92f2584a
JB		 1931}
1932
f6daaec2 1933static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1934{
3d13ef2e
DL		 1935 struct drm_device *dev = crtc->base.dev;
1936 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1937 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1938
92f2584a 1939 /* PCH only available on ILK+ */
3d13ef2e 1940 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1941 if (WARN_ON(pll == NULL))
ee7b9f93 1942 return;
92f2584a 1943
3e369b76 1944 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1945 return;
7a419866 1946
46edb027
DV		 1947 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948 pll->name, pll->active, pll->on,
e2b78267 1949 crtc->base.base.id);
7a419866 1950
48da64a8 1951 if (WARN_ON(pll->active == 0)) {
e9d6944e 1952 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1953 return;
1954 }
1955
e9d6944e 1956 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1957 WARN_ON(!pll->on);
cdbd2316 1958 if (--pll->active)
7a419866 1959 return;
ee7b9f93 1960
46edb027 1961 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1962 pll->disable(dev_priv, pll);
ee7b9f93 1963 pll->on = false;
bd2bb1b9
PZ		 1964
1965 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1966}
1967
b8a4f404
PZ		 1968static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum pipe pipe)
040484af 1970{
23670b32 1971 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1974 uint32_t reg, val, pipeconf_val;
040484af
JB		 1975
1976 /* PCH only available on ILK+ */
55522f37 1977 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1978
1979 /* Make sure PCH DPLL is enabled */
e72f9fbf 1980 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1981 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1982
1983 /* FDI must be feeding us bits for PCH ports */
1984 assert_fdi_tx_enabled(dev_priv, pipe);
1985 assert_fdi_rx_enabled(dev_priv, pipe);
1986
23670b32
DV		 1987 if (HAS_PCH_CPT(dev)) {
1988 /* Workaround: Set the timing override bit before enabling the
1989 * pch transcoder. */
1990 reg = TRANS_CHICKEN2(pipe);
1991 val = I915_READ(reg);
1992 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(reg, val);
59c859d6 1994 }
23670b32 1995
ab9412ba 1996 reg = PCH_TRANSCONF(pipe);
040484af 1997 val = I915_READ(reg);
5f7f726d 1998 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1999
2000 if (HAS_PCH_IBX(dev_priv->dev)) {
2001 /*
2002 * make the BPC in transcoder be consistent with
2003 * that in pipeconf reg.
2004 */
dfd07d72
DV		 2005 val &= ~PIPECONF_BPC_MASK;
2006 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2007 }
5f7f726d
PZ		 2008
2009 val &= ~TRANS_INTERLACE_MASK;
2010 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2011 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2012 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2013 val |= TRANS_LEGACY_INTERLACED_ILK;
2014 else
2015 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2016 else
2017 val |= TRANS_PROGRESSIVE;
2018
040484af
JB		 2019 I915_WRITE(reg, val | TRANS_ENABLE);
2020 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2021 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2022}
2023
8fb033d7 2024static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2025 enum transcoder cpu_transcoder)
040484af 2026{
8fb033d7 2027 u32 val, pipeconf_val;
8fb033d7
PZ		 2028
2029 /* PCH only available on ILK+ */
55522f37 2030 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2031
8fb033d7 2032 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2033 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2034 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2035
223a6fdf
PZ		 2036 /* Workaround: set timing override bit. */
2037 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2038 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2039 I915_WRITE(_TRANSA_CHICKEN2, val);
2040
25f3ef11 2041 val = TRANS_ENABLE;
937bb610 2042 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2043
9a76b1c6
PZ		 2044 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2045 PIPECONF_INTERLACED_ILK)
a35f2679 2046 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2047 else
2048 val |= TRANS_PROGRESSIVE;
2049
ab9412ba
DV		 2050 I915_WRITE(LPT_TRANSCONF, val);
2051 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2052 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2053}
2054
b8a4f404
PZ		 2055static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2056 enum pipe pipe)
040484af 2057{
23670b32
DV		 2058 struct drm_device *dev = dev_priv->dev;
2059 uint32_t reg, val;
040484af
JB		 2060
2061 /* FDI relies on the transcoder */
2062 assert_fdi_tx_disabled(dev_priv, pipe);
2063 assert_fdi_rx_disabled(dev_priv, pipe);
2064
291906f1
JB		 2065 /* Ports must be off as well */
2066 assert_pch_ports_disabled(dev_priv, pipe);
2067
ab9412ba 2068 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2069 val = I915_READ(reg);
2070 val &= ~TRANS_ENABLE;
2071 I915_WRITE(reg, val);
2072 /* wait for PCH transcoder off, transcoder state */
2073 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2074 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2075
2076 if (!HAS_PCH_IBX(dev)) {
2077 /* Workaround: Clear the timing override chicken bit again. */
2078 reg = TRANS_CHICKEN2(pipe);
2079 val = I915_READ(reg);
2080 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2081 I915_WRITE(reg, val);
2082 }
040484af
JB		 2083}
2084
ab4d966c 2085static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2086{
8fb033d7
PZ		 2087 u32 val;
2088
ab9412ba 2089 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2090 val &= ~TRANS_ENABLE;
ab9412ba 2091 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2092 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2093 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2094 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2095
2096 /* Workaround: clear timing override bit. */
2097 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2098 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2099 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2100}
2101
b24e7179 2102/**
309cfea8 2103 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2104 * @crtc: crtc responsible for the pipe
b24e7179 2105 *
0372264a 2106 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2107 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2108 */
e1fdc473 2109static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2110{
0372264a
PZ		 2111 struct drm_device *dev = crtc->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2114 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2115 pipe);
1a240d4d 2116 enum pipe pch_transcoder;
b24e7179
JB		 2117 int reg;
2118 u32 val;
2119
58c6eaa2 2120 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2121 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2122 assert_sprites_disabled(dev_priv, pipe);
2123
681e5811 2124 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2125 pch_transcoder = TRANSCODER_A;
2126 else
2127 pch_transcoder = pipe;
2128
b24e7179
JB		 2129 /*
2130 * A pipe without a PLL won't actually be able to drive bits from
2131 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2132 * need the check.
2133 */
50360403 2134 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2136 assert_dsi_pll_enabled(dev_priv);
2137 else
2138 assert_pll_enabled(dev_priv, pipe);
040484af 2139 else {
6e3c9717 2140 if (crtc->config->has_pch_encoder) {
040484af 2141 /* if driving the PCH, we need FDI enabled */
cc391bbb 2142 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2143 assert_fdi_tx_pll_enabled(dev_priv,
2144 (enum pipe) cpu_transcoder);
040484af
JB		 2145 }
2146 /* FIXME: assert CPU port conditions for SNB+ */
2147 }
b24e7179 2148
702e7a56 2149 reg = PIPECONF(cpu_transcoder);
b24e7179 2150 val = I915_READ(reg);
7ad25d48 2151 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2152 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2154 return;
7ad25d48 2155 }
00d70b15
CW		 2156
2157 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2158 POSTING_READ(reg);
b24e7179
JB		 2159}
2160
2161/**
309cfea8 2162 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2163 * @crtc: crtc whose pipes is to be disabled
b24e7179 2164 *
575f7ab7
VS		 2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
b24e7179
JB		 2168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
575f7ab7 2171static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2172{
575f7ab7 2173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2175 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2176 int reg;
2177 u32 val;
2178
2179 /*
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2182 */
2183 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2184 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2185 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2186
702e7a56 2187 reg = PIPECONF(cpu_transcoder);
b24e7179 2188 val = I915_READ(reg);
00d70b15
CW		 2189 if ((val & PIPECONF_ENABLE) == 0)
2190 return;
2191
67adc644
VS		 2192 /*
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2195 */
6e3c9717 2196 if (crtc->config->double_wide)
67adc644
VS		 2197 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2202 val &= ~PIPECONF_ENABLE;
2203
2204 I915_WRITE(reg, val);
2205 if ((val & PIPECONF_ENABLE) == 0)
2206 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2207}
2208
d74362c9
KP		 2209/*
2210 * Plane regs are double buffered, going from enabled->disabled needs a
2211 * trigger in order to latch. The display address reg provides this.
2212 */
1dba99f4
VS		 2213void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2214 enum plane plane)
d74362c9 2215{
3d13ef2e
DL		 2216 struct drm_device *dev = dev_priv->dev;
2217 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2218
2219 I915_WRITE(reg, I915_READ(reg));
2220 POSTING_READ(reg);
d74362c9
KP		 2221}
2222
b24e7179 2223/**
262ca2b0 2224 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2225 * @plane: plane to be enabled
2226 * @crtc: crtc for the plane
b24e7179 2227 *
fdd508a6 2228 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2229 */
fdd508a6
VS		 2230static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2231 struct drm_crtc *crtc)
b24e7179 2232{
fdd508a6
VS		 2233 struct drm_device *dev = plane->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2236
2237 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2238 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2239 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2240
fdd508a6
VS		 2241 dev_priv->display.update_primary_plane(crtc, plane->fb,
2242 crtc->x, crtc->y);
b24e7179
JB		 2243}
2244
693db184
CW		 2245static bool need_vtd_wa(struct drm_device *dev)
2246{
2247#ifdef CONFIG_INTEL_IOMMU
2248 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2249 return true;
2250#endif
2251 return false;
2252}
2253
50470bb0 2254unsigned int
6761dd31
TU		 2255intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2256 uint64_t fb_format_modifier)
a57ce0b2 2257{
6761dd31
TU		 2258 unsigned int tile_height;
2259 uint32_t pixel_bytes;
a57ce0b2 2260
b5d0e9bf
DL		 2261 switch (fb_format_modifier) {
2262 case DRM_FORMAT_MOD_NONE:
2263 tile_height = 1;
2264 break;
2265 case I915_FORMAT_MOD_X_TILED:
2266 tile_height = IS_GEN2(dev) ? 16 : 8;
2267 break;
2268 case I915_FORMAT_MOD_Y_TILED:
2269 tile_height = 32;
2270 break;
2271 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2272 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2273 switch (pixel_bytes) {
b5d0e9bf 2274 default:
6761dd31 2275 case 1:
b5d0e9bf
DL		 2276 tile_height = 64;
2277 break;
6761dd31
TU		 2278 case 2:
2279 case 4:
b5d0e9bf
DL		 2280 tile_height = 32;
2281 break;
6761dd31 2282 case 8:
b5d0e9bf
DL		 2283 tile_height = 16;
2284 break;
6761dd31 2285 case 16:
b5d0e9bf
DL		 2286 WARN_ONCE(1,
2287 "128-bit pixels are not supported for display!");
2288 tile_height = 16;
2289 break;
2290 }
2291 break;
2292 default:
2293 MISSING_CASE(fb_format_modifier);
2294 tile_height = 1;
2295 break;
2296 }
091df6cb 2297
6761dd31
TU		 2298 return tile_height;
2299}
2300
2301unsigned int
2302intel_fb_align_height(struct drm_device *dev, unsigned int height,
2303 uint32_t pixel_format, uint64_t fb_format_modifier)
2304{
2305 return ALIGN(height, intel_tile_height(dev, pixel_format,
2306 fb_format_modifier));
a57ce0b2
JB		 2307}
2308
f64b98cd
TU		 2309static int
2310intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2311 const struct drm_plane_state *plane_state)
2312{
50470bb0 2313 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2314
f64b98cd
TU		 2315 *view = i915_ggtt_view_normal;
2316
50470bb0
TU		 2317 if (!plane_state)
2318 return 0;
2319
121920fa 2320 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2321 return 0;
2322
9abc4648 2323 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2324
2325 info->height = fb->height;
2326 info->pixel_format = fb->pixel_format;
2327 info->pitch = fb->pitches[0];
2328 info->fb_modifier = fb->modifier[0];
2329
f64b98cd
TU		 2330 return 0;
2331}
2332
127bd2ac 2333int
850c4cdc
TU		 2334intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2335 struct drm_framebuffer *fb,
82bc3b2d 2336 const struct drm_plane_state *plane_state,
a4872ba6 2337 struct intel_engine_cs *pipelined)
6b95a207 2338{
850c4cdc 2339 struct drm_device *dev = fb->dev;
ce453d81 2340 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2341 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2342 struct i915_ggtt_view view;
6b95a207
KH		 2343 u32 alignment;
2344 int ret;
2345
ebcdd39e
MR		 2346 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2347
7b911adc
TU		 2348 switch (fb->modifier[0]) {
2349 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2353 alignment = 128 * 1024;
a6c45cf0 2354 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2355 alignment = 4 * 1024;
2356 else
2357 alignment = 64 * 1024;
6b95a207 2358 break;
7b911adc 2359 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2360 if (INTEL_INFO(dev)->gen >= 9)
2361 alignment = 256 * 1024;
2362 else {
2363 /* pin() will align the object as required by fence */
2364 alignment = 0;
2365 }
6b95a207 2366 break;
7b911adc 2367 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2368 case I915_FORMAT_MOD_Yf_TILED:
2369 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2370 "Y tiling bo slipped through, driver bug!\n"))
2371 return -EINVAL;
2372 alignment = 1 * 1024 * 1024;
2373 break;
6b95a207 2374 default:
7b911adc
TU		 2375 MISSING_CASE(fb->modifier[0]);
2376 return -EINVAL;
6b95a207
KH		 2377 }
2378
f64b98cd
TU		 2379 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2380 if (ret)
2381 return ret;
2382
693db184
CW		 2383 /* Note that the w/a also requires 64 PTE of padding following the
2384 * bo. We currently fill all unused PTE with the shadow page and so
2385 * we should always have valid PTE following the scanout preventing
2386 * the VT-d warning.
2387 */
2388 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2389 alignment = 256 * 1024;
2390
d6dd6843
PZ		 2391 /*
2392 * Global gtt pte registers are special registers which actually forward
2393 * writes to a chunk of system memory. Which means that there is no risk
2394 * that the register values disappear as soon as we call
2395 * intel_runtime_pm_put(), so it is correct to wrap only the
2396 * pin/unpin/fence and not more.
2397 */
2398 intel_runtime_pm_get(dev_priv);
2399
ce453d81 2400 dev_priv->mm.interruptible = false;
e6617330 2401 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2402 &view);
48b956c5 2403 if (ret)
ce453d81 2404 goto err_interruptible;
6b95a207
KH		 2405
2406 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2407 * fence, whereas 965+ only requires a fence if using
2408 * framebuffer compression. For simplicity, we always install
2409 * a fence as the cost is not that onerous.
2410 */
06d98131 2411 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2412 if (ret)
2413 goto err_unpin;
1690e1eb 2414
9a5a53b3 2415 i915_gem_object_pin_fence(obj);
6b95a207 2416
ce453d81 2417 dev_priv->mm.interruptible = true;
d6dd6843 2418 intel_runtime_pm_put(dev_priv);
6b95a207 2419 return 0;
48b956c5
CW		 2420
2421err_unpin:
f64b98cd 2422 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2423err_interruptible:
2424 dev_priv->mm.interruptible = true;
d6dd6843 2425 intel_runtime_pm_put(dev_priv);
48b956c5 2426 return ret;
6b95a207
KH		 2427}
2428
82bc3b2d
TU		 2429static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2430 const struct drm_plane_state *plane_state)
1690e1eb 2431{
82bc3b2d 2432 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2433 struct i915_ggtt_view view;
2434 int ret;
82bc3b2d 2435
ebcdd39e
MR		 2436 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2437
f64b98cd
TU		 2438 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2439 WARN_ONCE(ret, "Couldn't get view from plane state!");
2440
1690e1eb 2441 i915_gem_object_unpin_fence(obj);
f64b98cd 2442 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2443}
2444
c2c75131
DV		 2445/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2446 * is assumed to be a power-of-two. */
bc752862
CW		 2447unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2448 unsigned int tiling_mode,
2449 unsigned int cpp,
2450 unsigned int pitch)
c2c75131 2451{
bc752862
CW		 2452 if (tiling_mode != I915_TILING_NONE) {
2453 unsigned int tile_rows, tiles;
c2c75131 2454
bc752862
CW		 2455 tile_rows = *y / 8;
2456 *y %= 8;
c2c75131 2457
bc752862
CW		 2458 tiles = *x / (512/cpp);
2459 *x %= 512/cpp;
2460
2461 return tile_rows * pitch * 8 + tiles * 4096;
2462 } else {
2463 unsigned int offset;
2464
2465 offset = *y * pitch + *x * cpp;
2466 *y = 0;
2467 *x = (offset & 4095) / cpp;
2468 return offset & -4096;
2469 }
c2c75131
DV		 2470}
2471
b35d63fa 2472static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2473{
2474 switch (format) {
2475 case DISPPLANE_8BPP:
2476 return DRM_FORMAT_C8;
2477 case DISPPLANE_BGRX555:
2478 return DRM_FORMAT_XRGB1555;
2479 case DISPPLANE_BGRX565:
2480 return DRM_FORMAT_RGB565;
2481 default:
2482 case DISPPLANE_BGRX888:
2483 return DRM_FORMAT_XRGB8888;
2484 case DISPPLANE_RGBX888:
2485 return DRM_FORMAT_XBGR8888;
2486 case DISPPLANE_BGRX101010:
2487 return DRM_FORMAT_XRGB2101010;
2488 case DISPPLANE_RGBX101010:
2489 return DRM_FORMAT_XBGR2101010;
2490 }
2491}
2492
bc8d7dff
DL		 2493static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2494{
2495 switch (format) {
2496 case PLANE_CTL_FORMAT_RGB_565:
2497 return DRM_FORMAT_RGB565;
2498 default:
2499 case PLANE_CTL_FORMAT_XRGB_8888:
2500 if (rgb_order) {
2501 if (alpha)
2502 return DRM_FORMAT_ABGR8888;
2503 else
2504 return DRM_FORMAT_XBGR8888;
2505 } else {
2506 if (alpha)
2507 return DRM_FORMAT_ARGB8888;
2508 else
2509 return DRM_FORMAT_XRGB8888;
2510 }
2511 case PLANE_CTL_FORMAT_XRGB_2101010:
2512 if (rgb_order)
2513 return DRM_FORMAT_XBGR2101010;
2514 else
2515 return DRM_FORMAT_XRGB2101010;
2516 }
2517}
2518
5724dbd1 2519static bool
f6936e29
DV		 2520intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2521 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2522{
2523 struct drm_device *dev = crtc->base.dev;
2524 struct drm_i915_gem_object *obj = NULL;
2525 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2526 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2527 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2528 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2529 PAGE_SIZE);
2530
2531 size_aligned -= base_aligned;
46f297fb 2532
ff2652ea
CW		 2533 if (plane_config->size == 0)
2534 return false;
2535
f37b5c2b
DV		 2536 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2537 base_aligned,
2538 base_aligned,
2539 size_aligned);
46f297fb 2540 if (!obj)
484b41dd 2541 return false;
46f297fb 2542
49af449b
DL		 2543 obj->tiling_mode = plane_config->tiling;
2544 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2545 obj->stride = fb->pitches[0];
46f297fb 2546
6bf129df
DL		 2547 mode_cmd.pixel_format = fb->pixel_format;
2548 mode_cmd.width = fb->width;
2549 mode_cmd.height = fb->height;
2550 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2551 mode_cmd.modifier[0] = fb->modifier[0];
2552 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2553
2554 mutex_lock(&dev->struct_mutex);
6bf129df 2555 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2556 &mode_cmd, obj)) {
46f297fb
JB		 2557 DRM_DEBUG_KMS("intel fb init failed\n");
2558 goto out_unref_obj;
2559 }
46f297fb 2560 mutex_unlock(&dev->struct_mutex);
484b41dd 2561
f6936e29 2562 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2563 return true;
46f297fb
JB		 2564
2565out_unref_obj:
2566 drm_gem_object_unreference(&obj->base);
2567 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2568 return false;
2569}
2570
afd65eb4
MR		 2571/* Update plane->state->fb to match plane->fb after driver-internal updates */
2572static void
2573update_state_fb(struct drm_plane *plane)
2574{
2575 if (plane->fb == plane->state->fb)
2576 return;
2577
2578 if (plane->state->fb)
2579 drm_framebuffer_unreference(plane->state->fb);
2580 plane->state->fb = plane->fb;
2581 if (plane->state->fb)
2582 drm_framebuffer_reference(plane->state->fb);
2583}
2584
5724dbd1 2585static void
f6936e29
DV		 2586intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2587 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2588{
2589 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2590 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2591 struct drm_crtc *c;
2592 struct intel_crtc *i;
2ff8fde1 2593 struct drm_i915_gem_object *obj;
88595ac9
DV		 2594 struct drm_plane *primary = intel_crtc->base.primary;
2595 struct drm_framebuffer *fb;
484b41dd 2596
2d14030b 2597 if (!plane_config->fb)
484b41dd
JB		 2598 return;
2599
f6936e29 2600 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2601 fb = &plane_config->fb->base;
2602 goto valid_fb;
f55548b5 2603 }
484b41dd 2604
2d14030b 2605 kfree(plane_config->fb);
484b41dd
JB		 2606
2607 /*
2608 * Failed to alloc the obj, check to see if we should share
2609 * an fb with another CRTC instead
2610 */
70e1e0ec 2611 for_each_crtc(dev, c) {
484b41dd
JB		 2612 i = to_intel_crtc(c);
2613
2614 if (c == &intel_crtc->base)
2615 continue;
2616
2ff8fde1
MR		 2617 if (!i->active)
2618 continue;
2619
88595ac9
DV		 2620 fb = c->primary->fb;
2621 if (!fb)
484b41dd
JB		 2622 continue;
2623
88595ac9 2624 obj = intel_fb_obj(fb);
2ff8fde1 2625 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2626 drm_framebuffer_reference(fb);
2627 goto valid_fb;
484b41dd
JB		 2628 }
2629 }
88595ac9
DV		 2630
2631 return;
2632
2633valid_fb:
2634 obj = intel_fb_obj(fb);
2635 if (obj->tiling_mode != I915_TILING_NONE)
2636 dev_priv->preserve_bios_swizzle = true;
2637
2638 primary->fb = fb;
2639 primary->state->crtc = &intel_crtc->base;
2640 primary->crtc = &intel_crtc->base;
2641 update_state_fb(primary);
2642 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2643}
2644
29b9bde6
DV		 2645static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2646 struct drm_framebuffer *fb,
2647 int x, int y)
81255565
JB		 2648{
2649 struct drm_device *dev = crtc->dev;
2650 struct drm_i915_private *dev_priv = dev->dev_private;
2651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2652 struct drm_plane *primary = crtc->primary;
2653 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2654 struct drm_i915_gem_object *obj;
81255565 2655 int plane = intel_crtc->plane;
e506a0c6 2656 unsigned long linear_offset;
81255565 2657 u32 dspcntr;
f45651ba 2658 u32 reg = DSPCNTR(plane);
48404c1e 2659 int pixel_size;
f45651ba 2660
b70709a6 2661 if (!visible || !fb) {
fdd508a6
VS		 2662 I915_WRITE(reg, 0);
2663 if (INTEL_INFO(dev)->gen >= 4)
2664 I915_WRITE(DSPSURF(plane), 0);
2665 else
2666 I915_WRITE(DSPADDR(plane), 0);
2667 POSTING_READ(reg);
2668 return;
2669 }
2670
c9ba6fad
VS		 2671 obj = intel_fb_obj(fb);
2672 if (WARN_ON(obj == NULL))
2673 return;
2674
2675 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2676
f45651ba
VS		 2677 dspcntr = DISPPLANE_GAMMA_ENABLE;
2678
fdd508a6 2679 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2680
2681 if (INTEL_INFO(dev)->gen < 4) {
2682 if (intel_crtc->pipe == PIPE_B)
2683 dspcntr |= DISPPLANE_SEL_PIPE_B;
2684
2685 /* pipesrc and dspsize control the size that is scaled from,
2686 * which should always be the user's requested size.
2687 */
2688 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2689 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2690 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2691 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2692 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2693 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2694 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2695 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2696 I915_WRITE(PRIMPOS(plane), 0);
2697 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2698 }
81255565 2699
57779d06
VS		 2700 switch (fb->pixel_format) {
2701 case DRM_FORMAT_C8:
81255565
JB		 2702 dspcntr |= DISPPLANE_8BPP;
2703 break;
57779d06
VS		 2704 case DRM_FORMAT_XRGB1555:
2705 case DRM_FORMAT_ARGB1555:
2706 dspcntr |= DISPPLANE_BGRX555;
81255565 2707 break;
57779d06
VS		 2708 case DRM_FORMAT_RGB565:
2709 dspcntr |= DISPPLANE_BGRX565;
2710 break;
2711 case DRM_FORMAT_XRGB8888:
2712 case DRM_FORMAT_ARGB8888:
2713 dspcntr |= DISPPLANE_BGRX888;
2714 break;
2715 case DRM_FORMAT_XBGR8888:
2716 case DRM_FORMAT_ABGR8888:
2717 dspcntr |= DISPPLANE_RGBX888;
2718 break;
2719 case DRM_FORMAT_XRGB2101010:
2720 case DRM_FORMAT_ARGB2101010:
2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
2724 case DRM_FORMAT_ABGR2101010:
2725 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2726 break;
2727 default:
baba133a 2728 BUG();
81255565 2729 }
57779d06 2730
f45651ba
VS		 2731 if (INTEL_INFO(dev)->gen >= 4 &&
2732 obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
81255565 2734
de1aa629
VS		 2735 if (IS_G4X(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
b9897127 2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2739
c2c75131
DV		 2740 if (INTEL_INFO(dev)->gen >= 4) {
2741 intel_crtc->dspaddr_offset =
bc752862 2742 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2743 pixel_size,
bc752862 2744 fb->pitches[0]);
c2c75131
DV		 2745 linear_offset -= intel_crtc->dspaddr_offset;
2746 } else {
e506a0c6 2747 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2748 }
e506a0c6 2749
8e7d688b 2750 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2751 dspcntr |= DISPPLANE_ROTATE_180;
2752
6e3c9717
ACO		 2753 x += (intel_crtc->config->pipe_src_w - 1);
2754 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2755
2756 /* Finding the last pixel of the last line of the display
2757 data and adding to linear_offset*/
2758 linear_offset +=
6e3c9717
ACO		 2759 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2760 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2761 }
2762
2763 I915_WRITE(reg, dspcntr);
2764
01f2c773 2765 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2766 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2767 I915_WRITE(DSPSURF(plane),
2768 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2769 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2770 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2771 } else
f343c5f6 2772 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2773 POSTING_READ(reg);
17638cd6
JB		 2774}
2775
29b9bde6
DV		 2776static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2777 struct drm_framebuffer *fb,
2778 int x, int y)
17638cd6
JB		 2779{
2780 struct drm_device *dev = crtc->dev;
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2783 struct drm_plane *primary = crtc->primary;
2784 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2785 struct drm_i915_gem_object *obj;
17638cd6 2786 int plane = intel_crtc->plane;
e506a0c6 2787 unsigned long linear_offset;
17638cd6 2788 u32 dspcntr;
f45651ba 2789 u32 reg = DSPCNTR(plane);
48404c1e 2790 int pixel_size;
f45651ba 2791
b70709a6 2792 if (!visible || !fb) {
fdd508a6
VS		 2793 I915_WRITE(reg, 0);
2794 I915_WRITE(DSPSURF(plane), 0);
2795 POSTING_READ(reg);
2796 return;
2797 }
2798
c9ba6fad
VS		 2799 obj = intel_fb_obj(fb);
2800 if (WARN_ON(obj == NULL))
2801 return;
2802
2803 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2804
f45651ba
VS		 2805 dspcntr = DISPPLANE_GAMMA_ENABLE;
2806
fdd508a6 2807 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2808
2809 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2811
57779d06
VS		 2812 switch (fb->pixel_format) {
2813 case DRM_FORMAT_C8:
17638cd6
JB		 2814 dspcntr |= DISPPLANE_8BPP;
2815 break;
57779d06
VS		 2816 case DRM_FORMAT_RGB565:
2817 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2818 break;
57779d06
VS		 2819 case DRM_FORMAT_XRGB8888:
2820 case DRM_FORMAT_ARGB8888:
2821 dspcntr |= DISPPLANE_BGRX888;
2822 break;
2823 case DRM_FORMAT_XBGR8888:
2824 case DRM_FORMAT_ABGR8888:
2825 dspcntr |= DISPPLANE_RGBX888;
2826 break;
2827 case DRM_FORMAT_XRGB2101010:
2828 case DRM_FORMAT_ARGB2101010:
2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
2832 case DRM_FORMAT_ABGR2101010:
2833 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2834 break;
2835 default:
baba133a 2836 BUG();
17638cd6
JB		 2837 }
2838
2839 if (obj->tiling_mode != I915_TILING_NONE)
2840 dspcntr |= DISPPLANE_TILED;
17638cd6 2841
f45651ba 2842 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2843 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2844
b9897127 2845 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2846 intel_crtc->dspaddr_offset =
bc752862 2847 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2848 pixel_size,
bc752862 2849 fb->pitches[0]);
c2c75131 2850 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
6e3c9717
ACO		 2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2863 }
2864 }
2865
2866 I915_WRITE(reg, dspcntr);
17638cd6 2867
01f2c773 2868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873 } else {
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876 }
17638cd6 2877 POSTING_READ(reg);
17638cd6
JB		 2878}
2879
b321803d
DL		 2880u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881 uint32_t pixel_format)
2882{
2883 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885 /*
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2888 * buffers.
2889 */
2890 switch (fb_modifier) {
2891 case DRM_FORMAT_MOD_NONE:
2892 return 64;
2893 case I915_FORMAT_MOD_X_TILED:
2894 if (INTEL_INFO(dev)->gen == 2)
2895 return 128;
2896 return 512;
2897 case I915_FORMAT_MOD_Y_TILED:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2900 * we get here.
2901 */
2902 return 128;
2903 case I915_FORMAT_MOD_Yf_TILED:
2904 if (bits_per_pixel == 8)
2905 return 64;
2906 else
2907 return 128;
2908 default:
2909 MISSING_CASE(fb_modifier);
2910 return 64;
2911 }
2912}
2913
121920fa
TU		 2914unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915 struct drm_i915_gem_object *obj)
2916{
9abc4648 2917 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2918
2919 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2920 view = &i915_ggtt_view_rotated;
121920fa
TU		 2921
2922 return i915_gem_obj_ggtt_offset_view(obj, view);
2923}
2924
a1b2278e
CK		 2925/*
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2927 */
2928void skl_detach_scalers(struct intel_crtc *intel_crtc)
2929{
2930 struct drm_device *dev;
2931 struct drm_i915_private *dev_priv;
2932 struct intel_crtc_scaler_state *scaler_state;
2933 int i;
2934
2935 if (!intel_crtc || !intel_crtc->config)
2936 return;
2937
2938 dev = intel_crtc->base.dev;
2939 dev_priv = dev->dev_private;
2940 scaler_state = &intel_crtc->config->scaler_state;
2941
2942 /* loop through and disable scalers that aren't in use */
2943 for (i = 0; i < intel_crtc->num_scalers; i++) {
2944 if (!scaler_state->scalers[i].in_use) {
2945 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2947 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2948 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949 intel_crtc->base.base.id, intel_crtc->pipe, i);
2950 }
2951 }
2952}
2953
6156a456 2954u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2955{
6156a456
CK		 2956 u32 plane_ctl_format = 0;
2957 switch (pixel_format) {
70d21f0e 2958 case DRM_FORMAT_RGB565:
6156a456 2959 plane_ctl_format = PLANE_CTL_FORMAT_RGB_565;
f75fb42a 2960 break;
70d21f0e 2961 case DRM_FORMAT_XBGR8888:
6156a456
CK		 2962 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2963 break;
2964 case DRM_FORMAT_XRGB8888:
2965 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888;
70d21f0e 2966 break;
6156a456
CK		 2967 /*
2968 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2969 * to be already pre-multiplied. We need to add a knob (or a different
2970 * DRM_FORMAT) for user-space to configure that.
2971 */
f75fb42a 2972 case DRM_FORMAT_ABGR8888:
6156a456
CK		 2973 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2974 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2975 break;
2976 case DRM_FORMAT_ARGB8888:
2977 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 |
2978 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
f75fb42a 2979 break;
70d21f0e 2980 case DRM_FORMAT_XRGB2101010:
6156a456 2981 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e
DL		 2982 break;
2983 case DRM_FORMAT_XBGR2101010:
6156a456
CK		 2984 plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2985 break;
2986 case DRM_FORMAT_YUYV:
2987 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2988 break;
2989 case DRM_FORMAT_YVYU:
2990 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2991 break;
2992 case DRM_FORMAT_UYVY:
2993 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2994 break;
2995 case DRM_FORMAT_VYUY:
2996 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e
DL		 2997 break;
2998 default:
2999 BUG();
3000 }
6156a456
CK		 3001 return plane_ctl_format;
3002}
70d21f0e 3003
6156a456
CK		 3004u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3005{
3006 u32 plane_ctl_tiling = 0;
3007 switch (fb_modifier) {
30af77c4 3008 case DRM_FORMAT_MOD_NONE:
70d21f0e 3009 break;
30af77c4 3010 case I915_FORMAT_MOD_X_TILED:
6156a456 3011 plane_ctl_tiling = PLANE_CTL_TILED_X;
b321803d
DL		 3012 break;
3013 case I915_FORMAT_MOD_Y_TILED:
6156a456 3014 plane_ctl_tiling = PLANE_CTL_TILED_Y;
b321803d
DL		 3015 break;
3016 case I915_FORMAT_MOD_Yf_TILED:
6156a456 3017 plane_ctl_tiling = PLANE_CTL_TILED_YF;
70d21f0e
DL		 3018 break;
3019 default:
6156a456 3020 MISSING_CASE(fb_modifier);
70d21f0e 3021 }
6156a456
CK		 3022 return plane_ctl_tiling;
3023}
70d21f0e 3024
6156a456
CK		 3025u32 skl_plane_ctl_rotation(unsigned int rotation)
3026{
3027 u32 plane_ctl_rotation = 0;
3b7a5119 3028 switch (rotation) {
6156a456
CK		 3029 case BIT(DRM_ROTATE_0):
3030 break;
3b7a5119 3031 case BIT(DRM_ROTATE_90):
6156a456 3032 plane_ctl_rotation = PLANE_CTL_ROTATE_90;
3b7a5119 3033 break;
3b7a5119 3034 case BIT(DRM_ROTATE_180):
6156a456 3035 plane_ctl_rotation = PLANE_CTL_ROTATE_180;
3b7a5119 3036 break;
3b7a5119 3037 case BIT(DRM_ROTATE_270):
6156a456 3038 plane_ctl_rotation = PLANE_CTL_ROTATE_270;
3b7a5119 3039 break;
6156a456
CK		 3040 default:
3041 MISSING_CASE(rotation);
3042 }
3043
3044 return plane_ctl_rotation;
3045}
3046
3047static void skylake_update_primary_plane(struct drm_crtc *crtc,
3048 struct drm_framebuffer *fb,
3049 int x, int y)
3050{
3051 struct drm_device *dev = crtc->dev;
3052 struct drm_i915_private *dev_priv = dev->dev_private;
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3054 struct drm_plane *plane = crtc->primary;
3055 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3056 struct drm_i915_gem_object *obj;
3057 int pipe = intel_crtc->pipe;
3058 u32 plane_ctl, stride_div, stride;
3059 u32 tile_height, plane_offset, plane_size;
3060 unsigned int rotation;
3061 int x_offset, y_offset;
3062 unsigned long surf_addr;
6156a456
CK		 3063 struct intel_crtc_state *crtc_state = intel_crtc->config;
3064 struct intel_plane_state *plane_state;
3065 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3066 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3067 int scaler_id = -1;
3068
6156a456
CK		 3069 plane_state = to_intel_plane_state(plane->state);
3070
b70709a6 3071 if (!visible || !fb) {
6156a456
CK		 3072 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3073 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3074 POSTING_READ(PLANE_CTL(pipe, 0));
3075 return;
3b7a5119 3076 }
70d21f0e 3077
6156a456
CK		 3078 plane_ctl = PLANE_CTL_ENABLE |
3079 PLANE_CTL_PIPE_GAMMA_ENABLE |
3080 PLANE_CTL_PIPE_CSC_ENABLE;
3081
3082 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3083 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3084 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3085
3086 rotation = plane->state->rotation;
3087 plane_ctl |= skl_plane_ctl_rotation(rotation);
3088
b321803d
DL		 3089 obj = intel_fb_obj(fb);
3090 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3091 fb->pixel_format);
3b7a5119
SJ		 3092 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3093
6156a456
CK		 3094 /*
3095 * FIXME: intel_plane_state->src, dst aren't set when transitional
3096 * update_plane helpers are called from legacy paths.
3097 * Once full atomic crtc is available, below check can be avoided.
3098 */
3099 if (drm_rect_width(&plane_state->src)) {
3100 scaler_id = plane_state->scaler_id;
3101 src_x = plane_state->src.x1 >> 16;
3102 src_y = plane_state->src.y1 >> 16;
3103 src_w = drm_rect_width(&plane_state->src) >> 16;
3104 src_h = drm_rect_height(&plane_state->src) >> 16;
3105 dst_x = plane_state->dst.x1;
3106 dst_y = plane_state->dst.y1;
3107 dst_w = drm_rect_width(&plane_state->dst);
3108 dst_h = drm_rect_height(&plane_state->dst);
3109
3110 WARN_ON(x != src_x || y != src_y);
3111 } else {
3112 src_w = intel_crtc->config->pipe_src_w;
3113 src_h = intel_crtc->config->pipe_src_h;
3114 }
3115
3b7a5119
SJ		 3116 if (intel_rotation_90_or_270(rotation)) {
3117 /* stride = Surface height in tiles */
2614f17d 3118 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3119 fb->modifier[0]);
3120 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3121 x_offset = stride * tile_height - y - src_h;
3b7a5119 3122 y_offset = x;
6156a456 3123 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3124 } else {
3125 stride = fb->pitches[0] / stride_div;
3126 x_offset = x;
3127 y_offset = y;
6156a456 3128 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3129 }
3130 plane_offset = y_offset << 16 | x_offset;
b321803d 3131
70d21f0e 3132 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3133 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3134 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3135 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3136
3137 if (scaler_id >= 0) {
3138 uint32_t ps_ctrl = 0;
3139
3140 WARN_ON(!dst_w || !dst_h);
3141 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3142 crtc_state->scaler_state.scalers[scaler_id].mode;
3143 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3144 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3145 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3146 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3147 I915_WRITE(PLANE_POS(pipe, 0), 0);
3148 } else {
3149 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3150 }
3151
121920fa 3152 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3153
3154 POSTING_READ(PLANE_SURF(pipe, 0));
3155}
3156
17638cd6
JB		 3157/* Assume fb object is pinned & idle & fenced and just update base pointers */
3158static int
3159intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3160 int x, int y, enum mode_set_atomic state)
3161{
3162 struct drm_device *dev = crtc->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3164
6b8e6ed0
CW		 3165 if (dev_priv->display.disable_fbc)
3166 dev_priv->display.disable_fbc(dev);
81255565 3167
29b9bde6
DV		 3168 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3169
3170 return 0;
81255565
JB		 3171}
3172
7514747d 3173static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3174{
96a02917
VS		 3175 struct drm_crtc *crtc;
3176
70e1e0ec 3177 for_each_crtc(dev, crtc) {
96a02917
VS		 3178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3179 enum plane plane = intel_crtc->plane;
3180
3181 intel_prepare_page_flip(dev, plane);
3182 intel_finish_page_flip_plane(dev, plane);
3183 }
7514747d
VS		 3184}
3185
3186static void intel_update_primary_planes(struct drm_device *dev)
3187{
3188 struct drm_i915_private *dev_priv = dev->dev_private;
3189 struct drm_crtc *crtc;
96a02917 3190
70e1e0ec 3191 for_each_crtc(dev, crtc) {
96a02917
VS		 3192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193
51fd371b 3194 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3195 /*
3196 * FIXME: Once we have proper support for primary planes (and
3197 * disabling them without disabling the entire crtc) allow again
66e514c1 3198 * a NULL crtc->primary->fb.
947fdaad 3199 */
f4510a27 3200 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3201 dev_priv->display.update_primary_plane(crtc,
66e514c1 3202 crtc->primary->fb,
262ca2b0
MR		 3203 crtc->x,
3204 crtc->y);
51fd371b 3205 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3206 }
3207}
3208
ce22dba9
ML		 3209void intel_crtc_reset(struct intel_crtc *crtc)
3210{
3211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3212
3213 if (!crtc->active)
3214 return;
3215
3216 intel_crtc_disable_planes(&crtc->base);
3217 dev_priv->display.crtc_disable(&crtc->base);
3218 dev_priv->display.crtc_enable(&crtc->base);
3219 intel_crtc_enable_planes(&crtc->base);
3220}
3221
7514747d
VS		 3222void intel_prepare_reset(struct drm_device *dev)
3223{
f98ce92f
VS		 3224 struct drm_i915_private *dev_priv = to_i915(dev);
3225 struct intel_crtc *crtc;
3226
7514747d
VS		 3227 /* no reset support for gen2 */
3228 if (IS_GEN2(dev))
3229 return;
3230
3231 /* reset doesn't touch the display */
3232 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3233 return;
3234
3235 drm_modeset_lock_all(dev);
f98ce92f
VS		 3236
3237 /*
3238 * Disabling the crtcs gracefully seems nicer. Also the
3239 * g33 docs say we should at least disable all the planes.
3240 */
3241 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3242 if (!crtc->active)
3243 continue;
3244
3245 intel_crtc_disable_planes(&crtc->base);
3246 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3247 }
7514747d
VS		 3248}
3249
3250void intel_finish_reset(struct drm_device *dev)
3251{
3252 struct drm_i915_private *dev_priv = to_i915(dev);
3253
3254 /*
3255 * Flips in the rings will be nuked by the reset,
3256 * so complete all pending flips so that user space
3257 * will get its events and not get stuck.
3258 */
3259 intel_complete_page_flips(dev);
3260
3261 /* no reset support for gen2 */
3262 if (IS_GEN2(dev))
3263 return;
3264
3265 /* reset doesn't touch the display */
3266 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3267 /*
3268 * Flips in the rings have been nuked by the reset,
3269 * so update the base address of all primary
3270 * planes to the the last fb to make sure we're
3271 * showing the correct fb after a reset.
3272 */
3273 intel_update_primary_planes(dev);
3274 return;
3275 }
3276
3277 /*
3278 * The display has been reset as well,
3279 * so need a full re-initialization.
3280 */
3281 intel_runtime_pm_disable_interrupts(dev_priv);
3282 intel_runtime_pm_enable_interrupts(dev_priv);
3283
3284 intel_modeset_init_hw(dev);
3285
3286 spin_lock_irq(&dev_priv->irq_lock);
3287 if (dev_priv->display.hpd_irq_setup)
3288 dev_priv->display.hpd_irq_setup(dev);
3289 spin_unlock_irq(&dev_priv->irq_lock);
3290
3291 intel_modeset_setup_hw_state(dev, true);
3292
3293 intel_hpd_init(dev_priv);
3294
3295 drm_modeset_unlock_all(dev);
3296}
3297
2e2f351d 3298static void
14667a4b
CW		 3299intel_finish_fb(struct drm_framebuffer *old_fb)
3300{
2ff8fde1 3301 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3302 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3303 bool was_interruptible = dev_priv->mm.interruptible;
3304 int ret;
3305
14667a4b
CW		 3306 /* Big Hammer, we also need to ensure that any pending
3307 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3308 * current scanout is retired before unpinning the old
2e2f351d
CW		 3309 * framebuffer. Note that we rely on userspace rendering
3310 * into the buffer attached to the pipe they are waiting
3311 * on. If not, userspace generates a GPU hang with IPEHR
3312 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3313 *
3314 * This should only fail upon a hung GPU, in which case we
3315 * can safely continue.
3316 */
3317 dev_priv->mm.interruptible = false;
2e2f351d 3318 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3319 dev_priv->mm.interruptible = was_interruptible;
3320
2e2f351d 3321 WARN_ON(ret);
14667a4b
CW		 3322}
3323
7d5e3799
CW		 3324static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3325{
3326 struct drm_device *dev = crtc->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3329 bool pending;
3330
3331 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3332 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3333 return false;
3334
5e2d7afc 3335 spin_lock_irq(&dev->event_lock);
7d5e3799 3336 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3337 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3338
3339 return pending;
3340}
3341
e30e8f75
GP		 3342static void intel_update_pipe_size(struct intel_crtc *crtc)
3343{
3344 struct drm_device *dev = crtc->base.dev;
3345 struct drm_i915_private *dev_priv = dev->dev_private;
3346 const struct drm_display_mode *adjusted_mode;
3347
3348 if (!i915.fastboot)
3349 return;
3350
3351 /*
3352 * Update pipe size and adjust fitter if needed: the reason for this is
3353 * that in compute_mode_changes we check the native mode (not the pfit
3354 * mode) to see if we can flip rather than do a full mode set. In the
3355 * fastboot case, we'll flip, but if we don't update the pipesrc and
3356 * pfit state, we'll end up with a big fb scanned out into the wrong
3357 * sized surface.
3358 *
3359 * To fix this properly, we need to hoist the checks up into
3360 * compute_mode_changes (or above), check the actual pfit state and
3361 * whether the platform allows pfit disable with pipe active, and only
3362 * then update the pipesrc and pfit state, even on the flip path.
3363 */
3364
6e3c9717 3365 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3366
3367 I915_WRITE(PIPESRC(crtc->pipe),
3368 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3369 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3370 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3371 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3372 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3373 I915_WRITE(PF_CTL(crtc->pipe), 0);
3374 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3375 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3376 }
6e3c9717
ACO		 3377 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3378 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3379}
3380
5e84e1a4
ZW		 3381static void intel_fdi_normal_train(struct drm_crtc *crtc)
3382{
3383 struct drm_device *dev = crtc->dev;
3384 struct drm_i915_private *dev_priv = dev->dev_private;
3385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3386 int pipe = intel_crtc->pipe;
3387 u32 reg, temp;
3388
3389 /* enable normal train */
3390 reg = FDI_TX_CTL(pipe);
3391 temp = I915_READ(reg);
61e499bf 3392 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3393 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3394 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3395 } else {
3396 temp &= ~FDI_LINK_TRAIN_NONE;
3397 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3398 }
5e84e1a4
ZW		 3399 I915_WRITE(reg, temp);
3400
3401 reg = FDI_RX_CTL(pipe);
3402 temp = I915_READ(reg);
3403 if (HAS_PCH_CPT(dev)) {
3404 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3405 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3406 } else {
3407 temp &= ~FDI_LINK_TRAIN_NONE;
3408 temp |= FDI_LINK_TRAIN_NONE;
3409 }
3410 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3411
3412 /* wait one idle pattern time */
3413 POSTING_READ(reg);
3414 udelay(1000);
357555c0
JB		 3415
3416 /* IVB wants error correction enabled */
3417 if (IS_IVYBRIDGE(dev))
3418 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3419 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3420}
3421
8db9d77b
ZW		 3422/* The FDI link training functions for ILK/Ibexpeak. */
3423static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3424{
3425 struct drm_device *dev = crtc->dev;
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3428 int pipe = intel_crtc->pipe;
5eddb70b 3429 u32 reg, temp, tries;
8db9d77b 3430
1c8562f6 3431 /* FDI needs bits from pipe first */
0fc932b8 3432 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3433
e1a44743
AJ		 3434 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3435 for train result */
5eddb70b
CW		 3436 reg = FDI_RX_IMR(pipe);
3437 temp = I915_READ(reg);
e1a44743
AJ		 3438 temp &= ~FDI_RX_SYMBOL_LOCK;
3439 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3440 I915_WRITE(reg, temp);
3441 I915_READ(reg);
e1a44743
AJ		 3442 udelay(150);
3443
8db9d77b 3444 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3445 reg = FDI_TX_CTL(pipe);
3446 temp = I915_READ(reg);
627eb5a3 3447 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3448 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3449 temp &= ~FDI_LINK_TRAIN_NONE;
3450 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3451 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3452
5eddb70b
CW		 3453 reg = FDI_RX_CTL(pipe);
3454 temp = I915_READ(reg);
8db9d77b
ZW		 3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3457 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3458
3459 POSTING_READ(reg);
8db9d77b
ZW		 3460 udelay(150);
3461
5b2adf89 3462 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3463 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3464 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3465 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3466
5eddb70b 3467 reg = FDI_RX_IIR(pipe);
e1a44743 3468 for (tries = 0; tries < 5; tries++) {
5eddb70b 3469 temp = I915_READ(reg);
8db9d77b
ZW		 3470 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3471
3472 if ((temp & FDI_RX_BIT_LOCK)) {
3473 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3474 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3475 break;
3476 }
8db9d77b 3477 }
e1a44743 3478 if (tries == 5)
5eddb70b 3479 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3480
3481 /* Train 2 */
5eddb70b
CW		 3482 reg = FDI_TX_CTL(pipe);
3483 temp = I915_READ(reg);
8db9d77b
ZW		 3484 temp &= ~FDI_LINK_TRAIN_NONE;
3485 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3486 I915_WRITE(reg, temp);
8db9d77b 3487
5eddb70b
CW		 3488 reg = FDI_RX_CTL(pipe);
3489 temp = I915_READ(reg);
8db9d77b
ZW		 3490 temp &= ~FDI_LINK_TRAIN_NONE;
3491 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3492 I915_WRITE(reg, temp);
8db9d77b 3493
5eddb70b
CW		 3494 POSTING_READ(reg);
3495 udelay(150);
8db9d77b 3496
5eddb70b 3497 reg = FDI_RX_IIR(pipe);
e1a44743 3498 for (tries = 0; tries < 5; tries++) {
5eddb70b 3499 temp = I915_READ(reg);
8db9d77b
ZW		 3500 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3501
3502 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3503 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3504 DRM_DEBUG_KMS("FDI train 2 done.\n");
3505 break;
3506 }
8db9d77b 3507 }
e1a44743 3508 if (tries == 5)
5eddb70b 3509 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3510
3511 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3512
8db9d77b
ZW		 3513}
3514
0206e353 3515static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3516 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3517 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3518 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3519 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3520};
3521
3522/* The FDI link training functions for SNB/Cougarpoint. */
3523static void gen6_fdi_link_train(struct drm_crtc *crtc)
3524{
3525 struct drm_device *dev = crtc->dev;
3526 struct drm_i915_private *dev_priv = dev->dev_private;
3527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3528 int pipe = intel_crtc->pipe;
fa37d39e 3529 u32 reg, temp, i, retry;
8db9d77b 3530
e1a44743
AJ		 3531 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3532 for train result */
5eddb70b
CW		 3533 reg = FDI_RX_IMR(pipe);
3534 temp = I915_READ(reg);
e1a44743
AJ		 3535 temp &= ~FDI_RX_SYMBOL_LOCK;
3536 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3537 I915_WRITE(reg, temp);
3538
3539 POSTING_READ(reg);
e1a44743
AJ		 3540 udelay(150);
3541
8db9d77b 3542 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3543 reg = FDI_TX_CTL(pipe);
3544 temp = I915_READ(reg);
627eb5a3 3545 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3547 temp &= ~FDI_LINK_TRAIN_NONE;
3548 temp |= FDI_LINK_TRAIN_PATTERN_1;
3549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3550 /* SNB-B */
3551 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3552 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3553
d74cf324
DV		 3554 I915_WRITE(FDI_RX_MISC(pipe),
3555 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3556
5eddb70b
CW		 3557 reg = FDI_RX_CTL(pipe);
3558 temp = I915_READ(reg);
8db9d77b
ZW		 3559 if (HAS_PCH_CPT(dev)) {
3560 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3561 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3562 } else {
3563 temp &= ~FDI_LINK_TRAIN_NONE;
3564 temp |= FDI_LINK_TRAIN_PATTERN_1;
3565 }
5eddb70b
CW		 3566 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3567
3568 POSTING_READ(reg);
8db9d77b
ZW		 3569 udelay(150);
3570
0206e353 3571 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3572 reg = FDI_TX_CTL(pipe);
3573 temp = I915_READ(reg);
8db9d77b
ZW		 3574 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3575 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3576 I915_WRITE(reg, temp);
3577
3578 POSTING_READ(reg);
8db9d77b
ZW		 3579 udelay(500);
3580
fa37d39e
SP		 3581 for (retry = 0; retry < 5; retry++) {
3582 reg = FDI_RX_IIR(pipe);
3583 temp = I915_READ(reg);
3584 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3585 if (temp & FDI_RX_BIT_LOCK) {
3586 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3587 DRM_DEBUG_KMS("FDI train 1 done.\n");
3588 break;
3589 }
3590 udelay(50);
8db9d77b 3591 }
fa37d39e
SP		 3592 if (retry < 5)
3593 break;
8db9d77b
ZW		 3594 }
3595 if (i == 4)
5eddb70b 3596 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3597
3598 /* Train 2 */
5eddb70b
CW		 3599 reg = FDI_TX_CTL(pipe);
3600 temp = I915_READ(reg);
8db9d77b
ZW		 3601 temp &= ~FDI_LINK_TRAIN_NONE;
3602 temp |= FDI_LINK_TRAIN_PATTERN_2;
3603 if (IS_GEN6(dev)) {
3604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3605 /* SNB-B */
3606 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3607 }
5eddb70b 3608 I915_WRITE(reg, temp);
8db9d77b 3609
5eddb70b
CW		 3610 reg = FDI_RX_CTL(pipe);
3611 temp = I915_READ(reg);
8db9d77b
ZW		 3612 if (HAS_PCH_CPT(dev)) {
3613 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3614 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3615 } else {
3616 temp &= ~FDI_LINK_TRAIN_NONE;
3617 temp |= FDI_LINK_TRAIN_PATTERN_2;
3618 }
5eddb70b
CW		 3619 I915_WRITE(reg, temp);
3620
3621 POSTING_READ(reg);
8db9d77b
ZW		 3622 udelay(150);
3623
0206e353 3624 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3625 reg = FDI_TX_CTL(pipe);
3626 temp = I915_READ(reg);
8db9d77b
ZW		 3627 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3628 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3629 I915_WRITE(reg, temp);
3630
3631 POSTING_READ(reg);
8db9d77b
ZW		 3632 udelay(500);
3633
fa37d39e
SP		 3634 for (retry = 0; retry < 5; retry++) {
3635 reg = FDI_RX_IIR(pipe);
3636 temp = I915_READ(reg);
3637 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3638 if (temp & FDI_RX_SYMBOL_LOCK) {
3639 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3640 DRM_DEBUG_KMS("FDI train 2 done.\n");
3641 break;
3642 }
3643 udelay(50);
8db9d77b 3644 }
fa37d39e
SP		 3645 if (retry < 5)
3646 break;
8db9d77b
ZW		 3647 }
3648 if (i == 4)
5eddb70b 3649 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3650
3651 DRM_DEBUG_KMS("FDI train done.\n");
3652}
3653
357555c0
JB		 3654/* Manual link training for Ivy Bridge A0 parts */
3655static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3656{
3657 struct drm_device *dev = crtc->dev;
3658 struct drm_i915_private *dev_priv = dev->dev_private;
3659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3660 int pipe = intel_crtc->pipe;
139ccd3f 3661 u32 reg, temp, i, j;
357555c0
JB		 3662
3663 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3664 for train result */
3665 reg = FDI_RX_IMR(pipe);
3666 temp = I915_READ(reg);
3667 temp &= ~FDI_RX_SYMBOL_LOCK;
3668 temp &= ~FDI_RX_BIT_LOCK;
3669 I915_WRITE(reg, temp);
3670
3671 POSTING_READ(reg);
3672 udelay(150);
3673
01a415fd
DV		 3674 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3675 I915_READ(FDI_RX_IIR(pipe)));
3676
139ccd3f
JB		 3677 /* Try each vswing and preemphasis setting twice before moving on */
3678 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3679 /* disable first in case we need to retry */
3680 reg = FDI_TX_CTL(pipe);
3681 temp = I915_READ(reg);
3682 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3683 temp &= ~FDI_TX_ENABLE;
3684 I915_WRITE(reg, temp);
357555c0 3685
139ccd3f
JB		 3686 reg = FDI_RX_CTL(pipe);
3687 temp = I915_READ(reg);
3688 temp &= ~FDI_LINK_TRAIN_AUTO;
3689 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3690 temp &= ~FDI_RX_ENABLE;
3691 I915_WRITE(reg, temp);
357555c0 3692
139ccd3f 3693 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3694 reg = FDI_TX_CTL(pipe);
3695 temp = I915_READ(reg);
139ccd3f 3696 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3697 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3698 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3699 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3700 temp |= snb_b_fdi_train_param[j/2];
3701 temp |= FDI_COMPOSITE_SYNC;
3702 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3703
139ccd3f
JB		 3704 I915_WRITE(FDI_RX_MISC(pipe),
3705 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3706
139ccd3f 3707 reg = FDI_RX_CTL(pipe);
357555c0 3708 temp = I915_READ(reg);
139ccd3f
JB		 3709 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3710 temp |= FDI_COMPOSITE_SYNC;
3711 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3712
139ccd3f
JB		 3713 POSTING_READ(reg);
3714 udelay(1); /* should be 0.5us */
357555c0 3715
139ccd3f
JB		 3716 for (i = 0; i < 4; i++) {
3717 reg = FDI_RX_IIR(pipe);
3718 temp = I915_READ(reg);
3719 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3720
139ccd3f
JB		 3721 if (temp & FDI_RX_BIT_LOCK ||
3722 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3723 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3724 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3725 i);
3726 break;
3727 }
3728 udelay(1); /* should be 0.5us */
3729 }
3730 if (i == 4) {
3731 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3732 continue;
3733 }
357555c0 3734
139ccd3f 3735 /* Train 2 */
357555c0
JB		 3736 reg = FDI_TX_CTL(pipe);
3737 temp = I915_READ(reg);
139ccd3f
JB		 3738 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3739 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3740 I915_WRITE(reg, temp);
3741
3742 reg = FDI_RX_CTL(pipe);
3743 temp = I915_READ(reg);
3744 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3745 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3746 I915_WRITE(reg, temp);
3747
3748 POSTING_READ(reg);
139ccd3f 3749 udelay(2); /* should be 1.5us */
357555c0 3750
139ccd3f
JB		 3751 for (i = 0; i < 4; i++) {
3752 reg = FDI_RX_IIR(pipe);
3753 temp = I915_READ(reg);
3754 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3755
139ccd3f
JB		 3756 if (temp & FDI_RX_SYMBOL_LOCK ||
3757 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3758 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3759 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3760 i);
3761 goto train_done;
3762 }
3763 udelay(2); /* should be 1.5us */
357555c0 3764 }
139ccd3f
JB		 3765 if (i == 4)
3766 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3767 }
357555c0 3768
139ccd3f 3769train_done:
357555c0
JB		 3770 DRM_DEBUG_KMS("FDI train done.\n");
3771}
3772
88cefb6c 3773static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3774{
88cefb6c 3775 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3776 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3777 int pipe = intel_crtc->pipe;
5eddb70b 3778 u32 reg, temp;
79e53945 3779
c64e311e 3780
c98e9dcf 3781 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3782 reg = FDI_RX_CTL(pipe);
3783 temp = I915_READ(reg);
627eb5a3 3784 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3785 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3786 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3787 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3788
3789 POSTING_READ(reg);
c98e9dcf
JB		 3790 udelay(200);
3791
3792 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp | FDI_PCDCLK);
3795
3796 POSTING_READ(reg);
c98e9dcf
JB		 3797 udelay(200);
3798
20749730
PZ		 3799 /* Enable CPU FDI TX PLL, always on for Ironlake */
3800 reg = FDI_TX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3803 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3804
20749730
PZ		 3805 POSTING_READ(reg);
3806 udelay(100);
6be4a607 3807 }
0e23b99d
JB		 3808}
3809
88cefb6c
DV		 3810static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3811{
3812 struct drm_device *dev = intel_crtc->base.dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 int pipe = intel_crtc->pipe;
3815 u32 reg, temp;
3816
3817 /* Switch from PCDclk to Rawclk */
3818 reg = FDI_RX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3821
3822 /* Disable CPU FDI TX PLL */
3823 reg = FDI_TX_CTL(pipe);
3824 temp = I915_READ(reg);
3825 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3826
3827 POSTING_READ(reg);
3828 udelay(100);
3829
3830 reg = FDI_RX_CTL(pipe);
3831 temp = I915_READ(reg);
3832 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3833
3834 /* Wait for the clocks to turn off. */
3835 POSTING_READ(reg);
3836 udelay(100);
3837}
3838
0fc932b8
JB		 3839static void ironlake_fdi_disable(struct drm_crtc *crtc)
3840{
3841 struct drm_device *dev = crtc->dev;
3842 struct drm_i915_private *dev_priv = dev->dev_private;
3843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3844 int pipe = intel_crtc->pipe;
3845 u32 reg, temp;
3846
3847 /* disable CPU FDI tx and PCH FDI rx */
3848 reg = FDI_TX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3851 POSTING_READ(reg);
3852
3853 reg = FDI_RX_CTL(pipe);
3854 temp = I915_READ(reg);
3855 temp &= ~(0x7 << 16);
dfd07d72 3856 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3857 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3858
3859 POSTING_READ(reg);
3860 udelay(100);
3861
3862 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3863 if (HAS_PCH_IBX(dev))
6f06ce18 3864 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3865
3866 /* still set train pattern 1 */
3867 reg = FDI_TX_CTL(pipe);
3868 temp = I915_READ(reg);
3869 temp &= ~FDI_LINK_TRAIN_NONE;
3870 temp |= FDI_LINK_TRAIN_PATTERN_1;
3871 I915_WRITE(reg, temp);
3872
3873 reg = FDI_RX_CTL(pipe);
3874 temp = I915_READ(reg);
3875 if (HAS_PCH_CPT(dev)) {
3876 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3877 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3878 } else {
3879 temp &= ~FDI_LINK_TRAIN_NONE;
3880 temp |= FDI_LINK_TRAIN_PATTERN_1;
3881 }
3882 /* BPC in FDI rx is consistent with that in PIPECONF */
3883 temp &= ~(0x07 << 16);
dfd07d72 3884 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3885 I915_WRITE(reg, temp);
3886
3887 POSTING_READ(reg);
3888 udelay(100);
3889}
3890
5dce5b93
CW		 3891bool intel_has_pending_fb_unpin(struct drm_device *dev)
3892{
3893 struct intel_crtc *crtc;
3894
3895 /* Note that we don't need to be called with mode_config.lock here
3896 * as our list of CRTC objects is static for the lifetime of the
3897 * device and so cannot disappear as we iterate. Similarly, we can
3898 * happily treat the predicates as racy, atomic checks as userspace
3899 * cannot claim and pin a new fb without at least acquring the
3900 * struct_mutex and so serialising with us.
3901 */
d3fcc808 3902 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3903 if (atomic_read(&crtc->unpin_work_count) == 0)
3904 continue;
3905
3906 if (crtc->unpin_work)
3907 intel_wait_for_vblank(dev, crtc->pipe);
3908
3909 return true;
3910 }
3911
3912 return false;
3913}
3914
d6bbafa1
CW		 3915static void page_flip_completed(struct intel_crtc *intel_crtc)
3916{
3917 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3918 struct intel_unpin_work *work = intel_crtc->unpin_work;
3919
3920 /* ensure that the unpin work is consistent wrt ->pending. */
3921 smp_rmb();
3922 intel_crtc->unpin_work = NULL;
3923
3924 if (work->event)
3925 drm_send_vblank_event(intel_crtc->base.dev,
3926 intel_crtc->pipe,
3927 work->event);
3928
3929 drm_crtc_vblank_put(&intel_crtc->base);
3930
3931 wake_up_all(&dev_priv->pending_flip_queue);
3932 queue_work(dev_priv->wq, &work->work);
3933
3934 trace_i915_flip_complete(intel_crtc->plane,
3935 work->pending_flip_obj);
3936}
3937
46a55d30 3938void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3939{
0f91128d 3940 struct drm_device *dev = crtc->dev;
5bb61643 3941 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3942
2c10d571 3943 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3944 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3945 !intel_crtc_has_pending_flip(crtc),
3946 60*HZ) == 0)) {
3947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3948
5e2d7afc 3949 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3950 if (intel_crtc->unpin_work) {
3951 WARN_ONCE(1, "Removing stuck page flip\n");
3952 page_flip_completed(intel_crtc);
3953 }
5e2d7afc 3954 spin_unlock_irq(&dev->event_lock);
9c787942 3955 }
5bb61643 3956
975d568a
CW		 3957 if (crtc->primary->fb) {
3958 mutex_lock(&dev->struct_mutex);
3959 intel_finish_fb(crtc->primary->fb);
3960 mutex_unlock(&dev->struct_mutex);
3961 }
e6c3a2a6
CW		 3962}
3963
e615efe4
ED		 3964/* Program iCLKIP clock to the desired frequency */
3965static void lpt_program_iclkip(struct drm_crtc *crtc)
3966{
3967 struct drm_device *dev = crtc->dev;
3968 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3969 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3970 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3971 u32 temp;
3972
09153000
DV		 3973 mutex_lock(&dev_priv->dpio_lock);
3974
e615efe4
ED		 3975 /* It is necessary to ungate the pixclk gate prior to programming
3976 * the divisors, and gate it back when it is done.
3977 */
3978 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3979
3980 /* Disable SSCCTL */
3981 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3982 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3983 SBI_SSCCTL_DISABLE,
3984 SBI_ICLK);
e615efe4
ED		 3985
3986 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3987 if (clock == 20000) {
e615efe4
ED		 3988 auxdiv = 1;
3989 divsel = 0x41;
3990 phaseinc = 0x20;
3991 } else {
3992 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3993 * but the adjusted_mode->crtc_clock in in KHz. To get the
3994 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3995 * convert the virtual clock precision to KHz here for higher
3996 * precision.
3997 */
3998 u32 iclk_virtual_root_freq = 172800 * 1000;
3999 u32 iclk_pi_range = 64;
4000 u32 desired_divisor, msb_divisor_value, pi_value;
4001
12d7ceed 4002 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 4003 msb_divisor_value = desired_divisor / iclk_pi_range;
4004 pi_value = desired_divisor % iclk_pi_range;
4005
4006 auxdiv = 0;
4007 divsel = msb_divisor_value - 2;
4008 phaseinc = pi_value;
4009 }
4010
4011 /* This should not happen with any sane values */
4012 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4013 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4014 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4015 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4016
4017 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4018 clock,
e615efe4
ED		 4019 auxdiv,
4020 divsel,
4021 phasedir,
4022 phaseinc);
4023
4024 /* Program SSCDIVINTPHASE6 */
988d6ee8 4025 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 4026 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4027 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4028 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4029 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4030 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4031 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4032 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4033
4034 /* Program SSCAUXDIV */
988d6ee8 4035 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4036 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4037 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4038 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4039
4040 /* Enable modulator and associated divider */
988d6ee8 4041 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4042 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4043 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4044
4045 /* Wait for initialization time */
4046 udelay(24);
4047
4048 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 4049
4050 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 4051}
4052
275f01b2
DV		 4053static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4054 enum pipe pch_transcoder)
4055{
4056 struct drm_device *dev = crtc->base.dev;
4057 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4058 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4059
4060 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4061 I915_READ(HTOTAL(cpu_transcoder)));
4062 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4063 I915_READ(HBLANK(cpu_transcoder)));
4064 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4065 I915_READ(HSYNC(cpu_transcoder)));
4066
4067 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4068 I915_READ(VTOTAL(cpu_transcoder)));
4069 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4070 I915_READ(VBLANK(cpu_transcoder)));
4071 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4072 I915_READ(VSYNC(cpu_transcoder)));
4073 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4074 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4075}
4076
003632d9 4077static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4078{
4079 struct drm_i915_private *dev_priv = dev->dev_private;
4080 uint32_t temp;
4081
4082 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4083 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4084 return;
4085
4086 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4087 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4088
003632d9
ACO		 4089 temp &= ~FDI_BC_BIFURCATION_SELECT;
4090 if (enable)
4091 temp |= FDI_BC_BIFURCATION_SELECT;
4092
4093 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4094 I915_WRITE(SOUTH_CHICKEN1, temp);
4095 POSTING_READ(SOUTH_CHICKEN1);
4096}
4097
4098static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4099{
4100 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4101
4102 switch (intel_crtc->pipe) {
4103 case PIPE_A:
4104 break;
4105 case PIPE_B:
6e3c9717 4106 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4107 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4108 else
003632d9 4109 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4110
4111 break;
4112 case PIPE_C:
003632d9 4113 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4114
4115 break;
4116 default:
4117 BUG();
4118 }
4119}
4120
f67a559d
JB		 4121/*
4122 * Enable PCH resources required for PCH ports:
4123 * - PCH PLLs
4124 * - FDI training & RX/TX
4125 * - update transcoder timings
4126 * - DP transcoding bits
4127 * - transcoder
4128 */
4129static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4130{
4131 struct drm_device *dev = crtc->dev;
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4134 int pipe = intel_crtc->pipe;
ee7b9f93 4135 u32 reg, temp;
2c07245f 4136
ab9412ba 4137 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4138
1fbc0d78
DV		 4139 if (IS_IVYBRIDGE(dev))
4140 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4141
cd986abb
DV		 4142 /* Write the TU size bits before fdi link training, so that error
4143 * detection works. */
4144 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4145 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4146
c98e9dcf 4147 /* For PCH output, training FDI link */
674cf967 4148 dev_priv->display.fdi_link_train(crtc);
2c07245f 4149
3ad8a208
DV		 4150 /* We need to program the right clock selection before writing the pixel
4151 * mutliplier into the DPLL. */
303b81e0 4152 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4153 u32 sel;
4b645f14 4154
c98e9dcf 4155 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4156 temp |= TRANS_DPLL_ENABLE(pipe);
4157 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4158 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4159 temp |= sel;
4160 else
4161 temp &= ~sel;
c98e9dcf 4162 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4163 }
5eddb70b 4164
3ad8a208
DV		 4165 /* XXX: pch pll's can be enabled any time before we enable the PCH
4166 * transcoder, and we actually should do this to not upset any PCH
4167 * transcoder that already use the clock when we share it.
4168 *
4169 * Note that enable_shared_dpll tries to do the right thing, but
4170 * get_shared_dpll unconditionally resets the pll - we need that to have
4171 * the right LVDS enable sequence. */
85b3894f 4172 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4173
d9b6cb56
JB		 4174 /* set transcoder timing, panel must allow it */
4175 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4176 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4177
303b81e0 4178 intel_fdi_normal_train(crtc);
5e84e1a4 4179
c98e9dcf 4180 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4181 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4182 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4183 reg = TRANS_DP_CTL(pipe);
4184 temp = I915_READ(reg);
4185 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4186 TRANS_DP_SYNC_MASK |
4187 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4188 temp |= (TRANS_DP_OUTPUT_ENABLE |
4189 TRANS_DP_ENH_FRAMING);
9325c9f0 4190 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4191
4192 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4193 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4194 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4195 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4196
4197 switch (intel_trans_dp_port_sel(crtc)) {
4198 case PCH_DP_B:
5eddb70b 4199 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4200 break;
4201 case PCH_DP_C:
5eddb70b 4202 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4203 break;
4204 case PCH_DP_D:
5eddb70b 4205 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4206 break;
4207 default:
e95d41e1 4208 BUG();
32f9d658 4209 }
2c07245f 4210
5eddb70b 4211 I915_WRITE(reg, temp);
6be4a607 4212 }
b52eb4dc 4213
b8a4f404 4214 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4215}
4216
1507e5bd
PZ		 4217static void lpt_pch_enable(struct drm_crtc *crtc)
4218{
4219 struct drm_device *dev = crtc->dev;
4220 struct drm_i915_private *dev_priv = dev->dev_private;
4221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4222 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4223
ab9412ba 4224 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4225
8c52b5e8 4226 lpt_program_iclkip(crtc);
1507e5bd 4227
0540e488 4228 /* Set transcoder timing. */
275f01b2 4229 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4230
937bb610 4231 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4232}
4233
716c2e55 4234void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4235{
e2b78267 4236 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4237
4238 if (pll == NULL)
4239 return;
4240
3e369b76 4241 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4242 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4243 return;
4244 }
4245
3e369b76
ACO		 4246 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4247 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4248 WARN_ON(pll->on);
4249 WARN_ON(pll->active);
4250 }
4251
6e3c9717 4252 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4253}
4254
190f68c5
ACO		 4255struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4256 struct intel_crtc_state *crtc_state)
ee7b9f93 4257{
e2b78267 4258 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4259 struct intel_shared_dpll *pll;
e2b78267 4260 enum intel_dpll_id i;
ee7b9f93 4261
98b6bd99
DV		 4262 if (HAS_PCH_IBX(dev_priv->dev)) {
4263 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4264 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4265 pll = &dev_priv->shared_dplls[i];
98b6bd99 4266
46edb027
DV		 4267 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4268 crtc->base.base.id, pll->name);
98b6bd99 4269
8bd31e67 4270 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4271
98b6bd99
DV		 4272 goto found;
4273 }
4274
bcddf610
S		 4275 if (IS_BROXTON(dev_priv->dev)) {
4276 /* PLL is attached to port in bxt */
4277 struct intel_encoder *encoder;
4278 struct intel_digital_port *intel_dig_port;
4279
4280 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4281 if (WARN_ON(!encoder))
4282 return NULL;
4283
4284 intel_dig_port = enc_to_dig_port(&encoder->base);
4285 /* 1:1 mapping between ports and PLLs */
4286 i = (enum intel_dpll_id)intel_dig_port->port;
4287 pll = &dev_priv->shared_dplls[i];
4288 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4289 crtc->base.base.id, pll->name);
4290 WARN_ON(pll->new_config->crtc_mask);
4291
4292 goto found;
4293 }
4294
e72f9fbf
DV		 4295 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4296 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4297
4298 /* Only want to check enabled timings first */
8bd31e67 4299 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4300 continue;
4301
190f68c5 4302 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4303 &pll->new_config->hw_state,
4304 sizeof(pll->new_config->hw_state)) == 0) {
4305 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4306 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4307 pll->new_config->crtc_mask,
4308 pll->active);
ee7b9f93
JB		 4309 goto found;
4310 }
4311 }
4312
4313 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4314 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4315 pll = &dev_priv->shared_dplls[i];
8bd31e67 4316 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4317 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4318 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4319 goto found;
4320 }
4321 }
4322
4323 return NULL;
4324
4325found:
8bd31e67 4326 if (pll->new_config->crtc_mask == 0)
190f68c5 4327 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4328
190f68c5 4329 crtc_state->shared_dpll = i;
46edb027
DV		 4330 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4331 pipe_name(crtc->pipe));
ee7b9f93 4332
8bd31e67 4333 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4334
ee7b9f93
JB		 4335 return pll;
4336}
4337
8bd31e67
ACO		 4338/**
4339 * intel_shared_dpll_start_config - start a new PLL staged config
4340 * @dev_priv: DRM device
4341 * @clear_pipes: mask of pipes that will have their PLLs freed
4342 *
4343 * Starts a new PLL staged config, copying the current config but
4344 * releasing the references of pipes specified in clear_pipes.
4345 */
4346static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4347 unsigned clear_pipes)
4348{
4349 struct intel_shared_dpll *pll;
4350 enum intel_dpll_id i;
4351
4352 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4353 pll = &dev_priv->shared_dplls[i];
4354
4355 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4356 GFP_KERNEL);
4357 if (!pll->new_config)
4358 goto cleanup;
4359
4360 pll->new_config->crtc_mask &= ~clear_pipes;
4361 }
4362
4363 return 0;
4364
4365cleanup:
4366 while (--i >= 0) {
4367 pll = &dev_priv->shared_dplls[i];
f354d733 4368 kfree(pll->new_config);
8bd31e67
ACO		 4369 pll->new_config = NULL;
4370 }
4371
4372 return -ENOMEM;
4373}
4374
4375static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4376{
4377 struct intel_shared_dpll *pll;
4378 enum intel_dpll_id i;
4379
4380 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4381 pll = &dev_priv->shared_dplls[i];
4382
4383 WARN_ON(pll->new_config == &pll->config);
4384
4385 pll->config = *pll->new_config;
4386 kfree(pll->new_config);
4387 pll->new_config = NULL;
4388 }
4389}
4390
4391static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4392{
4393 struct intel_shared_dpll *pll;
4394 enum intel_dpll_id i;
4395
4396 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4397 pll = &dev_priv->shared_dplls[i];
4398
4399 WARN_ON(pll->new_config == &pll->config);
4400
4401 kfree(pll->new_config);
4402 pll->new_config = NULL;
4403 }
4404}
4405
a1520318 4406static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4407{
4408 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4409 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4410 u32 temp;
4411
4412 temp = I915_READ(dslreg);
4413 udelay(500);
4414 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4415 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4416 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4417 }
4418}
4419
a1b2278e
CK		 4420/**
4421 * skl_update_scaler_users - Stages update to crtc's scaler state
4422 * @intel_crtc: crtc
4423 * @crtc_state: crtc_state
4424 * @plane: plane (NULL indicates crtc is requesting update)
4425 * @plane_state: plane's state
4426 * @force_detach: request unconditional detachment of scaler
4427 *
4428 * This function updates scaler state for requested plane or crtc.
4429 * To request scaler usage update for a plane, caller shall pass plane pointer.
4430 * To request scaler usage update for crtc, caller shall pass plane pointer
4431 * as NULL.
4432 *
4433 * Return
4434 * 0 - scaler_usage updated successfully
4435 * error - requested scaling cannot be supported or other error condition
4436 */
4437int
4438skl_update_scaler_users(
4439 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4440 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4441 int force_detach)
4442{
4443 int need_scaling;
4444 int idx;
4445 int src_w, src_h, dst_w, dst_h;
4446 int *scaler_id;
4447 struct drm_framebuffer *fb;
4448 struct intel_crtc_scaler_state *scaler_state;
6156a456 4449 unsigned int rotation;
a1b2278e
CK		 4450
4451 if (!intel_crtc || !crtc_state)
4452 return 0;
4453
4454 scaler_state = &crtc_state->scaler_state;
4455
4456 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4457 fb = intel_plane ? plane_state->base.fb : NULL;
4458
4459 if (intel_plane) {
4460 src_w = drm_rect_width(&plane_state->src) >> 16;
4461 src_h = drm_rect_height(&plane_state->src) >> 16;
4462 dst_w = drm_rect_width(&plane_state->dst);
4463 dst_h = drm_rect_height(&plane_state->dst);
4464 scaler_id = &plane_state->scaler_id;
6156a456 4465 rotation = plane_state->base.rotation;
a1b2278e
CK		 4466 } else {
4467 struct drm_display_mode *adjusted_mode =
4468 &crtc_state->base.adjusted_mode;
4469 src_w = crtc_state->pipe_src_w;
4470 src_h = crtc_state->pipe_src_h;
4471 dst_w = adjusted_mode->hdisplay;
4472 dst_h = adjusted_mode->vdisplay;
4473 scaler_id = &scaler_state->scaler_id;
6156a456 4474 rotation = DRM_ROTATE_0;
a1b2278e 4475 }
6156a456
CK		 4476
4477 need_scaling = intel_rotation_90_or_270(rotation) ?
4478 (src_h != dst_w || src_w != dst_h):
4479 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4480
4481 /*
4482 * if plane is being disabled or scaler is no more required or force detach
4483 * - free scaler binded to this plane/crtc
4484 * - in order to do this, update crtc->scaler_usage
4485 *
4486 * Here scaler state in crtc_state is set free so that
4487 * scaler can be assigned to other user. Actual register
4488 * update to free the scaler is done in plane/panel-fit programming.
4489 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4490 */
4491 if (force_detach || !need_scaling || (intel_plane &&
4492 (!fb || !plane_state->visible))) {
4493 if (*scaler_id >= 0) {
4494 scaler_state->scaler_users &= ~(1 << idx);
4495 scaler_state->scalers[*scaler_id].in_use = 0;
4496
4497 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4498 "crtc_state = %p scaler_users = 0x%x\n",
4499 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4500 intel_plane ? intel_plane->base.base.id :
4501 intel_crtc->base.base.id, crtc_state,
4502 scaler_state->scaler_users);
4503 *scaler_id = -1;
4504 }
4505 return 0;
4506 }
4507
4508 /* range checks */
4509 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4510 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4511
4512 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4513 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4514 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4515 "size is out of scaler range\n",
4516 intel_plane ? "PLANE" : "CRTC",
4517 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4518 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4519 return -EINVAL;
4520 }
4521
4522 /* check colorkey */
4523 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4524 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4525 intel_plane->base.base.id);
4526 return -EINVAL;
4527 }
4528
4529 /* Check src format */
4530 if (intel_plane) {
4531 switch (fb->pixel_format) {
4532 case DRM_FORMAT_RGB565:
4533 case DRM_FORMAT_XBGR8888:
4534 case DRM_FORMAT_XRGB8888:
4535 case DRM_FORMAT_ABGR8888:
4536 case DRM_FORMAT_ARGB8888:
4537 case DRM_FORMAT_XRGB2101010:
4538 case DRM_FORMAT_ARGB2101010:
4539 case DRM_FORMAT_XBGR2101010:
4540 case DRM_FORMAT_ABGR2101010:
4541 case DRM_FORMAT_YUYV:
4542 case DRM_FORMAT_YVYU:
4543 case DRM_FORMAT_UYVY:
4544 case DRM_FORMAT_VYUY:
4545 break;
4546 default:
4547 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4548 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4549 return -EINVAL;
4550 }
4551 }
4552
4553 /* mark this plane as a scaler user in crtc_state */
4554 scaler_state->scaler_users |= (1 << idx);
4555 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4556 "crtc_state = %p scaler_users = 0x%x\n",
4557 intel_plane ? "PLANE" : "CRTC",
4558 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4559 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4560 return 0;
4561}
4562
4563static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4564{
4565 struct drm_device *dev = crtc->base.dev;
4566 struct drm_i915_private *dev_priv = dev->dev_private;
4567 int pipe = crtc->pipe;
a1b2278e
CK		 4568 struct intel_crtc_scaler_state *scaler_state =
4569 &crtc->config->scaler_state;
4570
4571 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4572
4573 /* To update pfit, first update scaler state */
4574 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4575 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4576 skl_detach_scalers(crtc);
4577 if (!enable)
4578 return;
bd2e244f 4579
6e3c9717 4580 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4581 int id;
4582
4583 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4584 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4585 return;
4586 }
4587
4588 id = scaler_state->scaler_id;
4589 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4590 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4591 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4592 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4593
4594 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4595 }
4596}
4597
b074cec8
JB		 4598static void ironlake_pfit_enable(struct intel_crtc *crtc)
4599{
4600 struct drm_device *dev = crtc->base.dev;
4601 struct drm_i915_private *dev_priv = dev->dev_private;
4602 int pipe = crtc->pipe;
4603
6e3c9717 4604 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4605 /* Force use of hard-coded filter coefficients
4606 * as some pre-programmed values are broken,
4607 * e.g. x201.
4608 */
4609 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4610 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4611 PF_PIPE_SEL_IVB(pipe));
4612 else
4613 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4614 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4615 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4616 }
4617}
4618
4a3b8769 4619static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4620{
4621 struct drm_device *dev = crtc->dev;
4622 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4623 struct drm_plane *plane;
bb53d4ae
VS		 4624 struct intel_plane *intel_plane;
4625
af2b653b
MR		 4626 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4627 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4628 if (intel_plane->pipe == pipe)
4629 intel_plane_restore(&intel_plane->base);
af2b653b 4630 }
bb53d4ae
VS		 4631}
4632
20bc8673 4633void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4634{
cea165c3
VS		 4635 struct drm_device *dev = crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4637
6e3c9717 4638 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4639 return;
4640
cea165c3
VS		 4641 /* We can only enable IPS after we enable a plane and wait for a vblank */
4642 intel_wait_for_vblank(dev, crtc->pipe);
4643
d77e4531 4644 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4645 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4646 mutex_lock(&dev_priv->rps.hw_lock);
4647 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4648 mutex_unlock(&dev_priv->rps.hw_lock);
4649 /* Quoting Art Runyan: "its not safe to expect any particular
4650 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4651 * mailbox." Moreover, the mailbox may return a bogus state,
4652 * so we need to just enable it and continue on.
2a114cc1
BW		 4653 */
4654 } else {
4655 I915_WRITE(IPS_CTL, IPS_ENABLE);
4656 /* The bit only becomes 1 in the next vblank, so this wait here
4657 * is essentially intel_wait_for_vblank. If we don't have this
4658 * and don't wait for vblanks until the end of crtc_enable, then
4659 * the HW state readout code will complain that the expected
4660 * IPS_CTL value is not the one we read. */
4661 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4662 DRM_ERROR("Timed out waiting for IPS enable\n");
4663 }
d77e4531
PZ		 4664}
4665
20bc8673 4666void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4667{
4668 struct drm_device *dev = crtc->base.dev;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670
6e3c9717 4671 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4672 return;
4673
4674 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4675 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4676 mutex_lock(&dev_priv->rps.hw_lock);
4677 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4678 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4679 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4680 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4681 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4682 } else {
2a114cc1 4683 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4684 POSTING_READ(IPS_CTL);
4685 }
d77e4531
PZ		 4686
4687 /* We need to wait for a vblank before we can disable the plane. */
4688 intel_wait_for_vblank(dev, crtc->pipe);
4689}
4690
4691/** Loads the palette/gamma unit for the CRTC with the prepared values */
4692static void intel_crtc_load_lut(struct drm_crtc *crtc)
4693{
4694 struct drm_device *dev = crtc->dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4697 enum pipe pipe = intel_crtc->pipe;
4698 int palreg = PALETTE(pipe);
4699 int i;
4700 bool reenable_ips = false;
4701
4702 /* The clocks have to be on to load the palette. */
83d65738 4703 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4704 return;
4705
50360403 4706 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4707 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4708 assert_dsi_pll_enabled(dev_priv);
4709 else
4710 assert_pll_enabled(dev_priv, pipe);
4711 }
4712
4713 /* use legacy palette for Ironlake */
7a1db49a 4714 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4715 palreg = LGC_PALETTE(pipe);
4716
4717 /* Workaround : Do not read or write the pipe palette/gamma data while
4718 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4719 */
6e3c9717 4720 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4721 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4722 GAMMA_MODE_MODE_SPLIT)) {
4723 hsw_disable_ips(intel_crtc);
4724 reenable_ips = true;
4725 }
4726
4727 for (i = 0; i < 256; i++) {
4728 I915_WRITE(palreg + 4 * i,
4729 (intel_crtc->lut_r[i] << 16) |
4730 (intel_crtc->lut_g[i] << 8) |
4731 intel_crtc->lut_b[i]);
4732 }
4733
4734 if (reenable_ips)
4735 hsw_enable_ips(intel_crtc);
4736}
4737
7cac945f 4738static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4739{
7cac945f 4740 if (intel_crtc->overlay) {
d3eedb1a
VS		 4741 struct drm_device *dev = intel_crtc->base.dev;
4742 struct drm_i915_private *dev_priv = dev->dev_private;
4743
4744 mutex_lock(&dev->struct_mutex);
4745 dev_priv->mm.interruptible = false;
4746 (void) intel_overlay_switch_off(intel_crtc->overlay);
4747 dev_priv->mm.interruptible = true;
4748 mutex_unlock(&dev->struct_mutex);
4749 }
4750
4751 /* Let userspace switch the overlay on again. In most cases userspace
4752 * has to recompute where to put it anyway.
4753 */
4754}
4755
87d4300a
ML		 4756/**
4757 * intel_post_enable_primary - Perform operations after enabling primary plane
4758 * @crtc: the CRTC whose primary plane was just enabled
4759 *
4760 * Performs potentially sleeping operations that must be done after the primary
4761 * plane is enabled, such as updating FBC and IPS. Note that this may be
4762 * called due to an explicit primary plane update, or due to an implicit
4763 * re-enable that is caused when a sprite plane is updated to no longer
4764 * completely hide the primary plane.
4765 */
4766static void
4767intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4768{
4769 struct drm_device *dev = crtc->dev;
87d4300a 4770 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4772 int pipe = intel_crtc->pipe;
a5c4d7bc 4773
87d4300a
ML		 4774 /*
4775 * BDW signals flip done immediately if the plane
4776 * is disabled, even if the plane enable is already
4777 * armed to occur at the next vblank :(
4778 */
4779 if (IS_BROADWELL(dev))
4780 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4781
87d4300a
ML		 4782 /*
4783 * FIXME IPS should be fine as long as one plane is
4784 * enabled, but in practice it seems to have problems
4785 * when going from primary only to sprite only and vice
4786 * versa.
4787 */
a5c4d7bc
VS		 4788 hsw_enable_ips(intel_crtc);
4789
4790 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4791 intel_fbc_update(dev);
a5c4d7bc 4792 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4793
4794 /*
87d4300a
ML		 4795 * Gen2 reports pipe underruns whenever all planes are disabled.
4796 * So don't enable underrun reporting before at least some planes
4797 * are enabled.
4798 * FIXME: Need to fix the logic to work when we turn off all planes
4799 * but leave the pipe running.
f99d7069 4800 */
87d4300a
ML		 4801 if (IS_GEN2(dev))
4802 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4803
4804 /* Underruns don't raise interrupts, so check manually. */
4805 if (HAS_GMCH_DISPLAY(dev))
4806 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4807}
4808
87d4300a
ML		 4809/**
4810 * intel_pre_disable_primary - Perform operations before disabling primary plane
4811 * @crtc: the CRTC whose primary plane is to be disabled
4812 *
4813 * Performs potentially sleeping operations that must be done before the
4814 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4815 * be called due to an explicit primary plane update, or due to an implicit
4816 * disable that is caused when a sprite plane completely hides the primary
4817 * plane.
4818 */
4819static void
4820intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4821{
4822 struct drm_device *dev = crtc->dev;
4823 struct drm_i915_private *dev_priv = dev->dev_private;
4824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4825 int pipe = intel_crtc->pipe;
a5c4d7bc 4826
87d4300a
ML		 4827 /*
4828 * Gen2 reports pipe underruns whenever all planes are disabled.
4829 * So diasble underrun reporting before all the planes get disabled.
4830 * FIXME: Need to fix the logic to work when we turn off all planes
4831 * but leave the pipe running.
4832 */
4833 if (IS_GEN2(dev))
4834 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4835
87d4300a
ML		 4836 /*
4837 * Vblank time updates from the shadow to live plane control register
4838 * are blocked if the memory self-refresh mode is active at that
4839 * moment. So to make sure the plane gets truly disabled, disable
4840 * first the self-refresh mode. The self-refresh enable bit in turn
4841 * will be checked/applied by the HW only at the next frame start
4842 * event which is after the vblank start event, so we need to have a
4843 * wait-for-vblank between disabling the plane and the pipe.
4844 */
4845 if (HAS_GMCH_DISPLAY(dev))
4846 intel_set_memory_cxsr(dev_priv, false);
4847
4848 mutex_lock(&dev->struct_mutex);
e35fef21 4849 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4850 intel_fbc_disable(dev);
87d4300a 4851 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4852
87d4300a
ML		 4853 /*
4854 * FIXME IPS should be fine as long as one plane is
4855 * enabled, but in practice it seems to have problems
4856 * when going from primary only to sprite only and vice
4857 * versa.
4858 */
a5c4d7bc 4859 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4860}
4861
4862static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4863{
87d4300a
ML		 4864 intel_enable_primary_hw_plane(crtc->primary, crtc);
4865 intel_enable_sprite_planes(crtc);
4866 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4867
4868 intel_post_enable_primary(crtc);
4869}
4870
4871static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4872{
4873 struct drm_device *dev = crtc->dev;
4874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4875 struct intel_plane *intel_plane;
4876 int pipe = intel_crtc->pipe;
4877
4878 intel_crtc_wait_for_pending_flips(crtc);
4879
4880 intel_pre_disable_primary(crtc);
a5c4d7bc 4881
7cac945f 4882 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4883 for_each_intel_plane(dev, intel_plane) {
4884 if (intel_plane->pipe == pipe) {
4885 struct drm_crtc *from = intel_plane->base.crtc;
4886
4887 intel_plane->disable_plane(&intel_plane->base,
4888 from ?: crtc, true);
4889 }
4890 }
f98551ae 4891
f99d7069
DV		 4892 /*
4893 * FIXME: Once we grow proper nuclear flip support out of this we need
4894 * to compute the mask of flip planes precisely. For the time being
4895 * consider this a flip to a NULL plane.
4896 */
4897 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4898}
4899
f67a559d
JB		 4900static void ironlake_crtc_enable(struct drm_crtc *crtc)
4901{
4902 struct drm_device *dev = crtc->dev;
4903 struct drm_i915_private *dev_priv = dev->dev_private;
4904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4905 struct intel_encoder *encoder;
f67a559d 4906 int pipe = intel_crtc->pipe;
f67a559d 4907
83d65738 4908 WARN_ON(!crtc->state->enable);
08a48469 4909
f67a559d
JB		 4910 if (intel_crtc->active)
4911 return;
4912
6e3c9717 4913 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4914 intel_prepare_shared_dpll(intel_crtc);
4915
6e3c9717 4916 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4917 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4918
4919 intel_set_pipe_timings(intel_crtc);
4920
6e3c9717 4921 if (intel_crtc->config->has_pch_encoder) {
29407aab 4922 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4923 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4924 }
4925
4926 ironlake_set_pipeconf(crtc);
4927
f67a559d 4928 intel_crtc->active = true;
8664281b 4929
a72e4c9f
DV		 4930 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4931 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4932
f6736a1a 4933 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4934 if (encoder->pre_enable)
4935 encoder->pre_enable(encoder);
f67a559d 4936
6e3c9717 4937 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4938 /* Note: FDI PLL enabling _must_ be done before we enable the
4939 * cpu pipes, hence this is separate from all the other fdi/pch
4940 * enabling. */
88cefb6c 4941 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4942 } else {
4943 assert_fdi_tx_disabled(dev_priv, pipe);
4944 assert_fdi_rx_disabled(dev_priv, pipe);
4945 }
f67a559d 4946
b074cec8 4947 ironlake_pfit_enable(intel_crtc);
f67a559d 4948
9c54c0dd
JB		 4949 /*
4950 * On ILK+ LUT must be loaded before the pipe is running but with
4951 * clocks enabled
4952 */
4953 intel_crtc_load_lut(crtc);
4954
f37fcc2a 4955 intel_update_watermarks(crtc);
e1fdc473 4956 intel_enable_pipe(intel_crtc);
f67a559d 4957
6e3c9717 4958 if (intel_crtc->config->has_pch_encoder)
f67a559d 4959 ironlake_pch_enable(crtc);
c98e9dcf 4960
f9b61ff6
DV		 4961 assert_vblank_disabled(crtc);
4962 drm_crtc_vblank_on(crtc);
4963
fa5c73b1
DV		 4964 for_each_encoder_on_crtc(dev, crtc, encoder)
4965 encoder->enable(encoder);
61b77ddd
DV		 4966
4967 if (HAS_PCH_CPT(dev))
a1520318 4968 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4969}
4970
42db64ef
PZ		 4971/* IPS only exists on ULT machines and is tied to pipe A. */
4972static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4973{
f5adf94e 4974 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4975}
4976
e4916946
PZ		 4977/*
4978 * This implements the workaround described in the "notes" section of the mode
4979 * set sequence documentation. When going from no pipes or single pipe to
4980 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4981 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4982 */
4983static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4984{
4985 struct drm_device *dev = crtc->base.dev;
4986 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4987
4988 /* We want to get the other_active_crtc only if there's only 1 other
4989 * active crtc. */
d3fcc808 4990 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4991 if (!crtc_it->active || crtc_it == crtc)
4992 continue;
4993
4994 if (other_active_crtc)
4995 return;
4996
4997 other_active_crtc = crtc_it;
4998 }
4999 if (!other_active_crtc)
5000 return;
5001
5002 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5003 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5004}
5005
4f771f10
PZ		 5006static void haswell_crtc_enable(struct drm_crtc *crtc)
5007{
5008 struct drm_device *dev = crtc->dev;
5009 struct drm_i915_private *dev_priv = dev->dev_private;
5010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5011 struct intel_encoder *encoder;
5012 int pipe = intel_crtc->pipe;
4f771f10 5013
83d65738 5014 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 5015
5016 if (intel_crtc->active)
5017 return;
5018
df8ad70c
DV		 5019 if (intel_crtc_to_shared_dpll(intel_crtc))
5020 intel_enable_shared_dpll(intel_crtc);
5021
6e3c9717 5022 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5023 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 5024
5025 intel_set_pipe_timings(intel_crtc);
5026
6e3c9717
ACO		 5027 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5028 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5029 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 5030 }
5031
6e3c9717 5032 if (intel_crtc->config->has_pch_encoder) {
229fca97 5033 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5034 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 5035 }
5036
5037 haswell_set_pipeconf(crtc);
5038
5039 intel_set_pipe_csc(crtc);
5040
4f771f10 5041 intel_crtc->active = true;
8664281b 5042
a72e4c9f 5043 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5044 for_each_encoder_on_crtc(dev, crtc, encoder)
5045 if (encoder->pre_enable)
5046 encoder->pre_enable(encoder);
5047
6e3c9717 5048 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5049 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5050 true);
4fe9467d
ID		 5051 dev_priv->display.fdi_link_train(crtc);
5052 }
5053
1f544388 5054 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5055
ff6d9f55 5056 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5057 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5058 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5059 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5060 else
5061 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5062
5063 /*
5064 * On ILK+ LUT must be loaded before the pipe is running but with
5065 * clocks enabled
5066 */
5067 intel_crtc_load_lut(crtc);
5068
1f544388 5069 intel_ddi_set_pipe_settings(crtc);
8228c251 5070 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5071
f37fcc2a 5072 intel_update_watermarks(crtc);
e1fdc473 5073 intel_enable_pipe(intel_crtc);
42db64ef 5074
6e3c9717 5075 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5076 lpt_pch_enable(crtc);
4f771f10 5077
6e3c9717 5078 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5079 intel_ddi_set_vc_payload_alloc(crtc, true);
5080
f9b61ff6
DV		 5081 assert_vblank_disabled(crtc);
5082 drm_crtc_vblank_on(crtc);
5083
8807e55b 5084 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5085 encoder->enable(encoder);
8807e55b
JN		 5086 intel_opregion_notify_encoder(encoder, true);
5087 }
4f771f10 5088
e4916946
PZ		 5089 /* If we change the relative order between pipe/planes enabling, we need
5090 * to change the workaround. */
5091 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5092}
5093
3f8dce3a
DV		 5094static void ironlake_pfit_disable(struct intel_crtc *crtc)
5095{
5096 struct drm_device *dev = crtc->base.dev;
5097 struct drm_i915_private *dev_priv = dev->dev_private;
5098 int pipe = crtc->pipe;
5099
5100 /* To avoid upsetting the power well on haswell only disable the pfit if
5101 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5102 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5103 I915_WRITE(PF_CTL(pipe), 0);
5104 I915_WRITE(PF_WIN_POS(pipe), 0);
5105 I915_WRITE(PF_WIN_SZ(pipe), 0);
5106 }
5107}
5108
6be4a607
JB		 5109static void ironlake_crtc_disable(struct drm_crtc *crtc)
5110{
5111 struct drm_device *dev = crtc->dev;
5112 struct drm_i915_private *dev_priv = dev->dev_private;
5113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5114 struct intel_encoder *encoder;
6be4a607 5115 int pipe = intel_crtc->pipe;
5eddb70b 5116 u32 reg, temp;
b52eb4dc 5117
f7abfe8b
CW		 5118 if (!intel_crtc->active)
5119 return;
5120
ea9d758d
DV		 5121 for_each_encoder_on_crtc(dev, crtc, encoder)
5122 encoder->disable(encoder);
5123
f9b61ff6
DV		 5124 drm_crtc_vblank_off(crtc);
5125 assert_vblank_disabled(crtc);
5126
6e3c9717 5127 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5128 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5129
575f7ab7 5130 intel_disable_pipe(intel_crtc);
32f9d658 5131
3f8dce3a 5132 ironlake_pfit_disable(intel_crtc);
2c07245f 5133
bf49ec8c
DV		 5134 for_each_encoder_on_crtc(dev, crtc, encoder)
5135 if (encoder->post_disable)
5136 encoder->post_disable(encoder);
2c07245f 5137
6e3c9717 5138 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5139 ironlake_fdi_disable(crtc);
913d8d11 5140
d925c59a 5141 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5142
d925c59a
DV		 5143 if (HAS_PCH_CPT(dev)) {
5144 /* disable TRANS_DP_CTL */
5145 reg = TRANS_DP_CTL(pipe);
5146 temp = I915_READ(reg);
5147 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5148 TRANS_DP_PORT_SEL_MASK);
5149 temp |= TRANS_DP_PORT_SEL_NONE;
5150 I915_WRITE(reg, temp);
5151
5152 /* disable DPLL_SEL */
5153 temp = I915_READ(PCH_DPLL_SEL);
11887397 5154 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5155 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5156 }
e3421a18 5157
d925c59a 5158 /* disable PCH DPLL */
e72f9fbf 5159 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5160
d925c59a
DV		 5161 ironlake_fdi_pll_disable(intel_crtc);
5162 }
6b383a7f 5163
f7abfe8b 5164 intel_crtc->active = false;
46ba614c 5165 intel_update_watermarks(crtc);
d1ebd816
BW		 5166
5167 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5168 intel_fbc_update(dev);
d1ebd816 5169 mutex_unlock(&dev->struct_mutex);
6be4a607 5170}
1b3c7a47 5171
4f771f10 5172static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5173{
4f771f10
PZ		 5174 struct drm_device *dev = crtc->dev;
5175 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5177 struct intel_encoder *encoder;
6e3c9717 5178 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5179
4f771f10
PZ		 5180 if (!intel_crtc->active)
5181 return;
5182
8807e55b
JN		 5183 for_each_encoder_on_crtc(dev, crtc, encoder) {
5184 intel_opregion_notify_encoder(encoder, false);
4f771f10 5185 encoder->disable(encoder);
8807e55b 5186 }
4f771f10 5187
f9b61ff6
DV		 5188 drm_crtc_vblank_off(crtc);
5189 assert_vblank_disabled(crtc);
5190
6e3c9717 5191 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5192 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5193 false);
575f7ab7 5194 intel_disable_pipe(intel_crtc);
4f771f10 5195
6e3c9717 5196 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5197 intel_ddi_set_vc_payload_alloc(crtc, false);
5198
ad80a810 5199 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5200
ff6d9f55 5201 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5202 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5203 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5204 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5205 else
5206 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5207
1f544388 5208 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5209
6e3c9717 5210 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5211 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5212 intel_ddi_fdi_disable(crtc);
83616634 5213 }
4f771f10 5214
97b040aa
ID		 5215 for_each_encoder_on_crtc(dev, crtc, encoder)
5216 if (encoder->post_disable)
5217 encoder->post_disable(encoder);
5218
4f771f10 5219 intel_crtc->active = false;
46ba614c 5220 intel_update_watermarks(crtc);
4f771f10
PZ		 5221
5222 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5223 intel_fbc_update(dev);
4f771f10 5224 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5225
5226 if (intel_crtc_to_shared_dpll(intel_crtc))
5227 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5228}
5229
ee7b9f93
JB		 5230static void ironlake_crtc_off(struct drm_crtc *crtc)
5231{
5232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5233 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5234}
5235
6441ab5f 5236
2dd24552
JB		 5237static void i9xx_pfit_enable(struct intel_crtc *crtc)
5238{
5239 struct drm_device *dev = crtc->base.dev;
5240 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5241 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5242
681a8504 5243 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5244 return;
5245
2dd24552 5246 /*
c0b03411
DV		 5247 * The panel fitter should only be adjusted whilst the pipe is disabled,
5248 * according to register description and PRM.
2dd24552 5249 */
c0b03411
DV		 5250 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5251 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5252
b074cec8
JB		 5253 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5254 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5255
5256 /* Border color in case we don't scale up to the full screen. Black by
5257 * default, change to something else for debugging. */
5258 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5259}
5260
d05410f9
DA		 5261static enum intel_display_power_domain port_to_power_domain(enum port port)
5262{
5263 switch (port) {
5264 case PORT_A:
5265 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5266 case PORT_B:
5267 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5268 case PORT_C:
5269 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5270 case PORT_D:
5271 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5272 default:
5273 WARN_ON_ONCE(1);
5274 return POWER_DOMAIN_PORT_OTHER;
5275 }
5276}
5277
77d22dca
ID		 5278#define for_each_power_domain(domain, mask) \
5279 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5280 if ((1 << (domain)) & (mask))
5281
319be8ae
ID		 5282enum intel_display_power_domain
5283intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5284{
5285 struct drm_device *dev = intel_encoder->base.dev;
5286 struct intel_digital_port *intel_dig_port;
5287
5288 switch (intel_encoder->type) {
5289 case INTEL_OUTPUT_UNKNOWN:
5290 /* Only DDI platforms should ever use this output type */
5291 WARN_ON_ONCE(!HAS_DDI(dev));
5292 case INTEL_OUTPUT_DISPLAYPORT:
5293 case INTEL_OUTPUT_HDMI:
5294 case INTEL_OUTPUT_EDP:
5295 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5296 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5297 case INTEL_OUTPUT_DP_MST:
5298 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5299 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5300 case INTEL_OUTPUT_ANALOG:
5301 return POWER_DOMAIN_PORT_CRT;
5302 case INTEL_OUTPUT_DSI:
5303 return POWER_DOMAIN_PORT_DSI;
5304 default:
5305 return POWER_DOMAIN_PORT_OTHER;
5306 }
5307}
5308
5309static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5310{
319be8ae
ID		 5311 struct drm_device *dev = crtc->dev;
5312 struct intel_encoder *intel_encoder;
5313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5314 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5315 unsigned long mask;
5316 enum transcoder transcoder;
5317
5318 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5319
5320 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5321 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5322 if (intel_crtc->config->pch_pfit.enabled ||
5323 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5324 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5325
319be8ae
ID		 5326 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5327 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5328
77d22dca
ID		 5329 return mask;
5330}
5331
679dacd4 5332static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5333{
679dacd4 5334 struct drm_device *dev = state->dev;
77d22dca
ID		 5335 struct drm_i915_private *dev_priv = dev->dev_private;
5336 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5337 struct intel_crtc *crtc;
5338
5339 /*
5340 * First get all needed power domains, then put all unneeded, to avoid
5341 * any unnecessary toggling of the power wells.
5342 */
d3fcc808 5343 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5344 enum intel_display_power_domain domain;
5345
83d65738 5346 if (!crtc->base.state->enable)
77d22dca
ID		 5347 continue;
5348
319be8ae 5349 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5350
5351 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5352 intel_display_power_get(dev_priv, domain);
5353 }
5354
50f6e502 5355 if (dev_priv->display.modeset_global_resources)
679dacd4 5356 dev_priv->display.modeset_global_resources(state);
50f6e502 5357
d3fcc808 5358 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5359 enum intel_display_power_domain domain;
5360
5361 for_each_power_domain(domain, crtc->enabled_power_domains)
5362 intel_display_power_put(dev_priv, domain);
5363
5364 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5365 }
5366
5367 intel_display_set_init_power(dev_priv, false);
5368}
5369
f8437dd1
VK		 5370void broxton_set_cdclk(struct drm_device *dev, int frequency)
5371{
5372 struct drm_i915_private *dev_priv = dev->dev_private;
5373 uint32_t divider;
5374 uint32_t ratio;
5375 uint32_t current_freq;
5376 int ret;
5377
5378 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5379 switch (frequency) {
5380 case 144000:
5381 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5382 ratio = BXT_DE_PLL_RATIO(60);
5383 break;
5384 case 288000:
5385 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5386 ratio = BXT_DE_PLL_RATIO(60);
5387 break;
5388 case 384000:
5389 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5390 ratio = BXT_DE_PLL_RATIO(60);
5391 break;
5392 case 576000:
5393 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5394 ratio = BXT_DE_PLL_RATIO(60);
5395 break;
5396 case 624000:
5397 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5398 ratio = BXT_DE_PLL_RATIO(65);
5399 break;
5400 case 19200:
5401 /*
5402 * Bypass frequency with DE PLL disabled. Init ratio, divider
5403 * to suppress GCC warning.
5404 */
5405 ratio = 0;
5406 divider = 0;
5407 break;
5408 default:
5409 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5410
5411 return;
5412 }
5413
5414 mutex_lock(&dev_priv->rps.hw_lock);
5415 /* Inform power controller of upcoming frequency change */
5416 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5417 0x80000000);
5418 mutex_unlock(&dev_priv->rps.hw_lock);
5419
5420 if (ret) {
5421 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5422 ret, frequency);
5423 return;
5424 }
5425
5426 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5427 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5428 current_freq = current_freq * 500 + 1000;
5429
5430 /*
5431 * DE PLL has to be disabled when
5432 * - setting to 19.2MHz (bypass, PLL isn't used)
5433 * - before setting to 624MHz (PLL needs toggling)
5434 * - before setting to any frequency from 624MHz (PLL needs toggling)
5435 */
5436 if (frequency == 19200 || frequency == 624000 ||
5437 current_freq == 624000) {
5438 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5439 /* Timeout 200us */
5440 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5441 1))
5442 DRM_ERROR("timout waiting for DE PLL unlock\n");
5443 }
5444
5445 if (frequency != 19200) {
5446 uint32_t val;
5447
5448 val = I915_READ(BXT_DE_PLL_CTL);
5449 val &= ~BXT_DE_PLL_RATIO_MASK;
5450 val |= ratio;
5451 I915_WRITE(BXT_DE_PLL_CTL, val);
5452
5453 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5454 /* Timeout 200us */
5455 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5456 DRM_ERROR("timeout waiting for DE PLL lock\n");
5457
5458 val = I915_READ(CDCLK_CTL);
5459 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5460 val |= divider;
5461 /*
5462 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5463 * enable otherwise.
5464 */
5465 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5466 if (frequency >= 500000)
5467 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5468
5469 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5470 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5471 val |= (frequency - 1000) / 500;
5472 I915_WRITE(CDCLK_CTL, val);
5473 }
5474
5475 mutex_lock(&dev_priv->rps.hw_lock);
5476 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5477 DIV_ROUND_UP(frequency, 25000));
5478 mutex_unlock(&dev_priv->rps.hw_lock);
5479
5480 if (ret) {
5481 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5482 ret, frequency);
5483 return;
5484 }
5485
5486 dev_priv->cdclk_freq = frequency;
5487}
5488
5489void broxton_init_cdclk(struct drm_device *dev)
5490{
5491 struct drm_i915_private *dev_priv = dev->dev_private;
5492 uint32_t val;
5493
5494 /*
5495 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5496 * or else the reset will hang because there is no PCH to respond.
5497 * Move the handshake programming to initialization sequence.
5498 * Previously was left up to BIOS.
5499 */
5500 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5501 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5502 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5503
5504 /* Enable PG1 for cdclk */
5505 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5506
5507 /* check if cd clock is enabled */
5508 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5509 DRM_DEBUG_KMS("Display already initialized\n");
5510 return;
5511 }
5512
5513 /*
5514 * FIXME:
5515 * - The initial CDCLK needs to be read from VBT.
5516 * Need to make this change after VBT has changes for BXT.
5517 * - check if setting the max (or any) cdclk freq is really necessary
5518 * here, it belongs to modeset time
5519 */
5520 broxton_set_cdclk(dev, 624000);
5521
5522 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5523 POSTING_READ(DBUF_CTL);
5524
f8437dd1
VK		 5525 udelay(10);
5526
5527 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5528 DRM_ERROR("DBuf power enable timeout!\n");
5529}
5530
5531void broxton_uninit_cdclk(struct drm_device *dev)
5532{
5533 struct drm_i915_private *dev_priv = dev->dev_private;
5534
5535 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5536 POSTING_READ(DBUF_CTL);
5537
f8437dd1
VK		 5538 udelay(10);
5539
5540 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5541 DRM_ERROR("DBuf power disable timeout!\n");
5542
5543 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5544 broxton_set_cdclk(dev, 19200);
5545
5546 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5547}
5548
dfcab17e 5549/* returns HPLL frequency in kHz */
f8bf63fd 5550static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5551{
586f49dc 5552 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5553
586f49dc
JB		 5554 /* Obtain SKU information */
5555 mutex_lock(&dev_priv->dpio_lock);
5556 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5557 CCK_FUSE_HPLL_FREQ_MASK;
5558 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5559
dfcab17e 5560 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5561}
5562
f8bf63fd
VS		 5563static void vlv_update_cdclk(struct drm_device *dev)
5564{
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566
164dfd28 5567 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5568 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5569 dev_priv->cdclk_freq);
f8bf63fd
VS		 5570
5571 /*
5572 * Program the gmbus_freq based on the cdclk frequency.
5573 * BSpec erroneously claims we should aim for 4MHz, but
5574 * in fact 1MHz is the correct frequency.
5575 */
164dfd28 5576 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5577}
5578
30a970c6
JB		 5579/* Adjust CDclk dividers to allow high res or save power if possible */
5580static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5581{
5582 struct drm_i915_private *dev_priv = dev->dev_private;
5583 u32 val, cmd;
5584
164dfd28
VK		 5585 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5586 != dev_priv->cdclk_freq);
d60c4473 5587
dfcab17e 5588 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5589 cmd = 2;
dfcab17e 5590 else if (cdclk == 266667)
30a970c6
JB		 5591 cmd = 1;
5592 else
5593 cmd = 0;
5594
5595 mutex_lock(&dev_priv->rps.hw_lock);
5596 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5597 val &= ~DSPFREQGUAR_MASK;
5598 val |= (cmd << DSPFREQGUAR_SHIFT);
5599 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5600 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5601 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5602 50)) {
5603 DRM_ERROR("timed out waiting for CDclk change\n");
5604 }
5605 mutex_unlock(&dev_priv->rps.hw_lock);
5606
dfcab17e 5607 if (cdclk == 400000) {
6bcda4f0 5608 u32 divider;
30a970c6 5609
6bcda4f0 5610 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5611
5612 mutex_lock(&dev_priv->dpio_lock);
5613 /* adjust cdclk divider */
5614 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5615 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5616 val |= divider;
5617 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5618
5619 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5620 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5621 50))
5622 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5623 mutex_unlock(&dev_priv->dpio_lock);
5624 }
5625
5626 mutex_lock(&dev_priv->dpio_lock);
5627 /* adjust self-refresh exit latency value */
5628 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5629 val &= ~0x7f;
5630
5631 /*
5632 * For high bandwidth configs, we set a higher latency in the bunit
5633 * so that the core display fetch happens in time to avoid underruns.
5634 */
dfcab17e 5635 if (cdclk == 400000)
30a970c6
JB		 5636 val |= 4500 / 250; /* 4.5 usec */
5637 else
5638 val |= 3000 / 250; /* 3.0 usec */
5639 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5640 mutex_unlock(&dev_priv->dpio_lock);
5641
f8bf63fd 5642 vlv_update_cdclk(dev);
30a970c6
JB		 5643}
5644
383c5a6a
VS		 5645static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5646{
5647 struct drm_i915_private *dev_priv = dev->dev_private;
5648 u32 val, cmd;
5649
164dfd28
VK		 5650 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5651 != dev_priv->cdclk_freq);
383c5a6a
VS		 5652
5653 switch (cdclk) {
383c5a6a
VS		 5654 case 333333:
5655 case 320000:
383c5a6a 5656 case 266667:
383c5a6a 5657 case 200000:
383c5a6a
VS		 5658 break;
5659 default:
5f77eeb0 5660 MISSING_CASE(cdclk);
383c5a6a
VS		 5661 return;
5662 }
5663
9d0d3fda
VS		 5664 /*
5665 * Specs are full of misinformation, but testing on actual
5666 * hardware has shown that we just need to write the desired
5667 * CCK divider into the Punit register.
5668 */
5669 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5670
383c5a6a
VS		 5671 mutex_lock(&dev_priv->rps.hw_lock);
5672 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5673 val &= ~DSPFREQGUAR_MASK_CHV;
5674 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5675 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5676 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5677 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5678 50)) {
5679 DRM_ERROR("timed out waiting for CDclk change\n");
5680 }
5681 mutex_unlock(&dev_priv->rps.hw_lock);
5682
5683 vlv_update_cdclk(dev);
5684}
5685
30a970c6
JB		 5686static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5687 int max_pixclk)
5688{
6bcda4f0 5689 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5690 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5691
30a970c6
JB		 5692 /*
5693 * Really only a few cases to deal with, as only 4 CDclks are supported:
5694 * 200MHz
5695 * 267MHz
29dc7ef3 5696 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5697 * 400MHz (VLV only)
5698 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5699 * of the lower bin and adjust if needed.
e37c67a1
VS		 5700 *
5701 * We seem to get an unstable or solid color picture at 200MHz.
5702 * Not sure what's wrong. For now use 200MHz only when all pipes
5703 * are off.
30a970c6 5704 */
6cca3195
VS		 5705 if (!IS_CHERRYVIEW(dev_priv) &&
5706 max_pixclk > freq_320*limit/100)
dfcab17e 5707 return 400000;
6cca3195 5708 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5709 return freq_320;
e37c67a1 5710 else if (max_pixclk > 0)
dfcab17e 5711 return 266667;
e37c67a1
VS		 5712 else
5713 return 200000;
30a970c6
JB		 5714}
5715
f8437dd1
VK		 5716static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5717 int max_pixclk)
5718{
5719 /*
5720 * FIXME:
5721 * - remove the guardband, it's not needed on BXT
5722 * - set 19.2MHz bypass frequency if there are no active pipes
5723 */
5724 if (max_pixclk > 576000*9/10)
5725 return 624000;
5726 else if (max_pixclk > 384000*9/10)
5727 return 576000;
5728 else if (max_pixclk > 288000*9/10)
5729 return 384000;
5730 else if (max_pixclk > 144000*9/10)
5731 return 288000;
5732 else
5733 return 144000;
5734}
5735
a821fc46
ACO		 5736/* Compute the max pixel clock for new configuration. Uses atomic state if
5737 * that's non-NULL, look at current state otherwise. */
5738static int intel_mode_max_pixclk(struct drm_device *dev,
5739 struct drm_atomic_state *state)
30a970c6 5740{
30a970c6 5741 struct intel_crtc *intel_crtc;
304603f4 5742 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5743 int max_pixclk = 0;
5744
d3fcc808 5745 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5746 if (state)
5747 crtc_state =
5748 intel_atomic_get_crtc_state(state, intel_crtc);
5749 else
5750 crtc_state = intel_crtc->config;
304603f4
ACO		 5751 if (IS_ERR(crtc_state))
5752 return PTR_ERR(crtc_state);
5753
5754 if (!crtc_state->base.enable)
5755 continue;
5756
5757 max_pixclk = max(max_pixclk,
5758 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5759 }
5760
5761 return max_pixclk;
5762}
5763
0a9ab303 5764static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5765{
304603f4 5766 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5767 struct drm_crtc *crtc;
5768 struct drm_crtc_state *crtc_state;
a821fc46 5769 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5770 int cdclk, i;
30a970c6 5771
304603f4
ACO		 5772 if (max_pixclk < 0)
5773 return max_pixclk;
30a970c6 5774
f8437dd1
VK		 5775 if (IS_VALLEYVIEW(dev_priv))
5776 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5777 else
5778 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5779
5780 if (cdclk == dev_priv->cdclk_freq)
304603f4 5781 return 0;
30a970c6 5782
0a9ab303
ACO		 5783 /* add all active pipes to the state */
5784 for_each_crtc(state->dev, crtc) {
5785 if (!crtc->state->enable)
5786 continue;
5787
5788 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5789 if (IS_ERR(crtc_state))
5790 return PTR_ERR(crtc_state);
5791 }
5792
2f2d7aa1 5793 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 5794 for_each_crtc_in_state(state, crtc, crtc_state, i)
5795 if (crtc_state->enable)
5796 crtc_state->mode_changed = true;
304603f4
ACO		 5797
5798 return 0;
30a970c6
JB		 5799}
5800
1e69cd74
VS		 5801static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5802{
5803 unsigned int credits, default_credits;
5804
5805 if (IS_CHERRYVIEW(dev_priv))
5806 default_credits = PFI_CREDIT(12);
5807 else
5808 default_credits = PFI_CREDIT(8);
5809
164dfd28 5810 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5811 /* CHV suggested value is 31 or 63 */
5812 if (IS_CHERRYVIEW(dev_priv))
5813 credits = PFI_CREDIT_31;
5814 else
5815 credits = PFI_CREDIT(15);
5816 } else {
5817 credits = default_credits;
5818 }
5819
5820 /*
5821 * WA - write default credits before re-programming
5822 * FIXME: should we also set the resend bit here?
5823 */
5824 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5825 default_credits);
5826
5827 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5828 credits | PFI_CREDIT_RESEND);
5829
5830 /*
5831 * FIXME is this guaranteed to clear
5832 * immediately or should we poll for it?
5833 */
5834 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5835}
5836
a821fc46 5837static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 5838{
a821fc46 5839 struct drm_device *dev = old_state->dev;
30a970c6 5840 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 5841 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 5842 int req_cdclk;
5843
a821fc46
ACO		 5844 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5845 * never fail. */
304603f4
ACO		 5846 if (WARN_ON(max_pixclk < 0))
5847 return;
30a970c6 5848
304603f4 5849 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5850
164dfd28 5851 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5852 /*
5853 * FIXME: We can end up here with all power domains off, yet
5854 * with a CDCLK frequency other than the minimum. To account
5855 * for this take the PIPE-A power domain, which covers the HW
5856 * blocks needed for the following programming. This can be
5857 * removed once it's guaranteed that we get here either with
5858 * the minimum CDCLK set, or the required power domains
5859 * enabled.
5860 */
5861 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5862
383c5a6a
VS		 5863 if (IS_CHERRYVIEW(dev))
5864 cherryview_set_cdclk(dev, req_cdclk);
5865 else
5866 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5867
1e69cd74
VS		 5868 vlv_program_pfi_credits(dev_priv);
5869
738c05c0 5870 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5871 }
30a970c6
JB		 5872}
5873
89b667f8
JB		 5874static void valleyview_crtc_enable(struct drm_crtc *crtc)
5875{
5876 struct drm_device *dev = crtc->dev;
a72e4c9f 5877 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5879 struct intel_encoder *encoder;
5880 int pipe = intel_crtc->pipe;
23538ef1 5881 bool is_dsi;
89b667f8 5882
83d65738 5883 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5884
5885 if (intel_crtc->active)
5886 return;
5887
409ee761 5888 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5889
1ae0d137
VS		 5890 if (!is_dsi) {
5891 if (IS_CHERRYVIEW(dev))
6e3c9717 5892 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5893 else
6e3c9717 5894 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5895 }
5b18e57c 5896
6e3c9717 5897 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5898 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5899
5900 intel_set_pipe_timings(intel_crtc);
5901
c14b0485
VS		 5902 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5903 struct drm_i915_private *dev_priv = dev->dev_private;
5904
5905 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5906 I915_WRITE(CHV_CANVAS(pipe), 0);
5907 }
5908
5b18e57c
DV		 5909 i9xx_set_pipeconf(intel_crtc);
5910
89b667f8 5911 intel_crtc->active = true;
89b667f8 5912
a72e4c9f 5913 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5914
89b667f8
JB		 5915 for_each_encoder_on_crtc(dev, crtc, encoder)
5916 if (encoder->pre_pll_enable)
5917 encoder->pre_pll_enable(encoder);
5918
9d556c99
CML		 5919 if (!is_dsi) {
5920 if (IS_CHERRYVIEW(dev))
6e3c9717 5921 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5922 else
6e3c9717 5923 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5924 }
89b667f8
JB		 5925
5926 for_each_encoder_on_crtc(dev, crtc, encoder)
5927 if (encoder->pre_enable)
5928 encoder->pre_enable(encoder);
5929
2dd24552
JB		 5930 i9xx_pfit_enable(intel_crtc);
5931
63cbb074
VS		 5932 intel_crtc_load_lut(crtc);
5933
f37fcc2a 5934 intel_update_watermarks(crtc);
e1fdc473 5935 intel_enable_pipe(intel_crtc);
be6a6f8e 5936
4b3a9526
VS		 5937 assert_vblank_disabled(crtc);
5938 drm_crtc_vblank_on(crtc);
5939
f9b61ff6
DV		 5940 for_each_encoder_on_crtc(dev, crtc, encoder)
5941 encoder->enable(encoder);
89b667f8
JB		 5942}
5943
f13c2ef3
DV		 5944static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5945{
5946 struct drm_device *dev = crtc->base.dev;
5947 struct drm_i915_private *dev_priv = dev->dev_private;
5948
6e3c9717
ACO		 5949 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5950 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5951}
5952
0b8765c6 5953static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5954{
5955 struct drm_device *dev = crtc->dev;
a72e4c9f 5956 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5958 struct intel_encoder *encoder;
79e53945 5959 int pipe = intel_crtc->pipe;
79e53945 5960
83d65738 5961 WARN_ON(!crtc->state->enable);
08a48469 5962
f7abfe8b
CW		 5963 if (intel_crtc->active)
5964 return;
5965
f13c2ef3
DV		 5966 i9xx_set_pll_dividers(intel_crtc);
5967
6e3c9717 5968 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5969 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5970
5971 intel_set_pipe_timings(intel_crtc);
5972
5b18e57c
DV		 5973 i9xx_set_pipeconf(intel_crtc);
5974
f7abfe8b 5975 intel_crtc->active = true;
6b383a7f 5976
4a3436e8 5977 if (!IS_GEN2(dev))
a72e4c9f 5978 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5979
9d6d9f19
MK		 5980 for_each_encoder_on_crtc(dev, crtc, encoder)
5981 if (encoder->pre_enable)
5982 encoder->pre_enable(encoder);
5983
f6736a1a
DV		 5984 i9xx_enable_pll(intel_crtc);
5985
2dd24552
JB		 5986 i9xx_pfit_enable(intel_crtc);
5987
63cbb074
VS		 5988 intel_crtc_load_lut(crtc);
5989
f37fcc2a 5990 intel_update_watermarks(crtc);
e1fdc473 5991 intel_enable_pipe(intel_crtc);
be6a6f8e 5992
4b3a9526
VS		 5993 assert_vblank_disabled(crtc);
5994 drm_crtc_vblank_on(crtc);
5995
f9b61ff6
DV		 5996 for_each_encoder_on_crtc(dev, crtc, encoder)
5997 encoder->enable(encoder);
0b8765c6 5998}
79e53945 5999
87476d63
DV		 6000static void i9xx_pfit_disable(struct intel_crtc *crtc)
6001{
6002 struct drm_device *dev = crtc->base.dev;
6003 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6004
6e3c9717 6005 if (!crtc->config->gmch_pfit.control)
328d8e82 6006 return;
87476d63 6007
328d8e82 6008 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6009
328d8e82
DV		 6010 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6011 I915_READ(PFIT_CONTROL));
6012 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6013}
6014
0b8765c6
JB		 6015static void i9xx_crtc_disable(struct drm_crtc *crtc)
6016{
6017 struct drm_device *dev = crtc->dev;
6018 struct drm_i915_private *dev_priv = dev->dev_private;
6019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6020 struct intel_encoder *encoder;
0b8765c6 6021 int pipe = intel_crtc->pipe;
ef9c3aee 6022
f7abfe8b
CW		 6023 if (!intel_crtc->active)
6024 return;
6025
6304cd91
VS		 6026 /*
6027 * On gen2 planes are double buffered but the pipe isn't, so we must
6028 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6029 * We also need to wait on all gmch platforms because of the
6030 * self-refresh mode constraint explained above.
6304cd91 6031 */
564ed191 6032 intel_wait_for_vblank(dev, pipe);
6304cd91 6033
4b3a9526
VS		 6034 for_each_encoder_on_crtc(dev, crtc, encoder)
6035 encoder->disable(encoder);
6036
f9b61ff6
DV		 6037 drm_crtc_vblank_off(crtc);
6038 assert_vblank_disabled(crtc);
6039
575f7ab7 6040 intel_disable_pipe(intel_crtc);
24a1f16d 6041
87476d63 6042 i9xx_pfit_disable(intel_crtc);
24a1f16d 6043
89b667f8
JB		 6044 for_each_encoder_on_crtc(dev, crtc, encoder)
6045 if (encoder->post_disable)
6046 encoder->post_disable(encoder);
6047
409ee761 6048 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6049 if (IS_CHERRYVIEW(dev))
6050 chv_disable_pll(dev_priv, pipe);
6051 else if (IS_VALLEYVIEW(dev))
6052 vlv_disable_pll(dev_priv, pipe);
6053 else
1c4e0274 6054 i9xx_disable_pll(intel_crtc);
076ed3b2 6055 }
0b8765c6 6056
4a3436e8 6057 if (!IS_GEN2(dev))
a72e4c9f 6058 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6059
f7abfe8b 6060 intel_crtc->active = false;
46ba614c 6061 intel_update_watermarks(crtc);
f37fcc2a 6062
efa9624e 6063 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6064 intel_fbc_update(dev);
efa9624e 6065 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6066}
6067
ee7b9f93
JB		 6068static void i9xx_crtc_off(struct drm_crtc *crtc)
6069{
6070}
6071
b04c5bd6
BF		 6072/* Master function to enable/disable CRTC and corresponding power wells */
6073void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6074{
6075 struct drm_device *dev = crtc->dev;
6076 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6078 enum intel_display_power_domain domain;
6079 unsigned long domains;
976f8a20 6080
0e572fe7
DV		 6081 if (enable) {
6082 if (!intel_crtc->active) {
e1e9fb84
DV		 6083 domains = get_crtc_power_domains(crtc);
6084 for_each_power_domain(domain, domains)
6085 intel_display_power_get(dev_priv, domain);
6086 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6087
6088 dev_priv->display.crtc_enable(crtc);
ce22dba9 6089 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6090 }
6091 } else {
6092 if (intel_crtc->active) {
ce22dba9 6093 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6094 dev_priv->display.crtc_disable(crtc);
6095
e1e9fb84
DV		 6096 domains = intel_crtc->enabled_power_domains;
6097 for_each_power_domain(domain, domains)
6098 intel_display_power_put(dev_priv, domain);
6099 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6100 }
6101 }
b04c5bd6
BF		 6102}
6103
6104/**
6105 * Sets the power management mode of the pipe and plane.
6106 */
6107void intel_crtc_update_dpms(struct drm_crtc *crtc)
6108{
6109 struct drm_device *dev = crtc->dev;
6110 struct intel_encoder *intel_encoder;
6111 bool enable = false;
6112
6113 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6114 enable |= intel_encoder->connectors_active;
6115
6116 intel_crtc_control(crtc, enable);
0f63cca2
ACO		 6117
6118 crtc->state->active = enable;
976f8a20
DV		 6119}
6120
cdd59983
CW		 6121static void intel_crtc_disable(struct drm_crtc *crtc)
6122{
cdd59983 6123 struct drm_device *dev = crtc->dev;
976f8a20 6124 struct drm_connector *connector;
ee7b9f93 6125 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6126
976f8a20 6127 /* crtc should still be enabled when we disable it. */
83d65738 6128 WARN_ON(!crtc->state->enable);
976f8a20 6129
ce22dba9 6130 intel_crtc_disable_planes(crtc);
976f8a20 6131 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6132 dev_priv->display.off(crtc);
6133
70a101f8 6134 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6135
6136 /* Update computed state. */
6137 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6138 if (!connector->encoder || !connector->encoder->crtc)
6139 continue;
6140
6141 if (connector->encoder->crtc != crtc)
6142 continue;
6143
6144 connector->dpms = DRM_MODE_DPMS_OFF;
6145 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6146 }
6147}
6148
ea5b213a 6149void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6150{
4ef69c7a 6151 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6152
ea5b213a
CW		 6153 drm_encoder_cleanup(encoder);
6154 kfree(intel_encoder);
7e7d76c3
JB		 6155}
6156
9237329d 6157/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6158 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6159 * state of the entire output pipe. */
9237329d 6160static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6161{
5ab432ef
DV		 6162 if (mode == DRM_MODE_DPMS_ON) {
6163 encoder->connectors_active = true;
6164
b2cabb0e 6165 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6166 } else {
6167 encoder->connectors_active = false;
6168
b2cabb0e 6169 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6170 }
79e53945
JB		 6171}
6172
0a91ca29
DV		 6173/* Cross check the actual hw state with our own modeset state tracking (and it's
6174 * internal consistency). */
b980514c 6175static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6176{
0a91ca29
DV		 6177 if (connector->get_hw_state(connector)) {
6178 struct intel_encoder *encoder = connector->encoder;
6179 struct drm_crtc *crtc;
6180 bool encoder_enabled;
6181 enum pipe pipe;
6182
6183 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6184 connector->base.base.id,
c23cc417 6185 connector->base.name);
0a91ca29 6186
0e32b39c
DA		 6187 /* there is no real hw state for MST connectors */
6188 if (connector->mst_port)
6189 return;
6190
e2c719b7 6191 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6192 "wrong connector dpms state\n");
e2c719b7 6193 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6194 "active connector not linked to encoder\n");
0a91ca29 6195
36cd7444 6196 if (encoder) {
e2c719b7 6197 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6198 "encoder->connectors_active not set\n");
6199
6200 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6201 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6202 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6203 return;
0a91ca29 6204
36cd7444 6205 crtc = encoder->base.crtc;
0a91ca29 6206
83d65738
MR		 6207 I915_STATE_WARN(!crtc->state->enable,
6208 "crtc not enabled\n");
e2c719b7
RC		 6209 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6210 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6211 "encoder active on the wrong pipe\n");
6212 }
0a91ca29 6213 }
79e53945
JB		 6214}
6215
08d9bc92
ACO		 6216int intel_connector_init(struct intel_connector *connector)
6217{
6218 struct drm_connector_state *connector_state;
6219
6220 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6221 if (!connector_state)
6222 return -ENOMEM;
6223
6224 connector->base.state = connector_state;
6225 return 0;
6226}
6227
6228struct intel_connector *intel_connector_alloc(void)
6229{
6230 struct intel_connector *connector;
6231
6232 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6233 if (!connector)
6234 return NULL;
6235
6236 if (intel_connector_init(connector) < 0) {
6237 kfree(connector);
6238 return NULL;
6239 }
6240
6241 return connector;
6242}
6243
5ab432ef
DV		 6244/* Even simpler default implementation, if there's really no special case to
6245 * consider. */
6246void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6247{
5ab432ef
DV		 6248 /* All the simple cases only support two dpms states. */
6249 if (mode != DRM_MODE_DPMS_ON)
6250 mode = DRM_MODE_DPMS_OFF;
d4270e57 6251
5ab432ef
DV		 6252 if (mode == connector->dpms)
6253 return;
6254
6255 connector->dpms = mode;
6256
6257 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6258 if (connector->encoder)
6259 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6260
b980514c 6261 intel_modeset_check_state(connector->dev);
79e53945
JB		 6262}
6263
f0947c37
DV		 6264/* Simple connector->get_hw_state implementation for encoders that support only
6265 * one connector and no cloning and hence the encoder state determines the state
6266 * of the connector. */
6267bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6268{
24929352 6269 enum pipe pipe = 0;
f0947c37 6270 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6271
f0947c37 6272 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6273}
6274
6d293983 6275static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6276{
6d293983
ACO		 6277 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6278 return crtc_state->fdi_lanes;
d272ddfa
VS		 6279
6280 return 0;
6281}
6282
6d293983 6283static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6284 struct intel_crtc_state *pipe_config)
1857e1da 6285{
6d293983
ACO		 6286 struct drm_atomic_state *state = pipe_config->base.state;
6287 struct intel_crtc *other_crtc;
6288 struct intel_crtc_state *other_crtc_state;
6289
1857e1da
DV		 6290 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6291 pipe_name(pipe), pipe_config->fdi_lanes);
6292 if (pipe_config->fdi_lanes > 4) {
6293 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6294 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6295 return -EINVAL;
1857e1da
DV		 6296 }
6297
bafb6553 6298 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6299 if (pipe_config->fdi_lanes > 2) {
6300 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6301 pipe_config->fdi_lanes);
6d293983 6302 return -EINVAL;
1857e1da 6303 } else {
6d293983 6304 return 0;
1857e1da
DV		 6305 }
6306 }
6307
6308 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6309 return 0;
1857e1da
DV		 6310
6311 /* Ivybridge 3 pipe is really complicated */
6312 switch (pipe) {
6313 case PIPE_A:
6d293983 6314 return 0;
1857e1da 6315 case PIPE_B:
6d293983
ACO		 6316 if (pipe_config->fdi_lanes <= 2)
6317 return 0;
6318
6319 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6320 other_crtc_state =
6321 intel_atomic_get_crtc_state(state, other_crtc);
6322 if (IS_ERR(other_crtc_state))
6323 return PTR_ERR(other_crtc_state);
6324
6325 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6326 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6327 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6328 return -EINVAL;
1857e1da 6329 }
6d293983 6330 return 0;
1857e1da 6331 case PIPE_C:
251cc67c
VS		 6332 if (pipe_config->fdi_lanes > 2) {
6333 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6334 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6335 return -EINVAL;
251cc67c 6336 }
6d293983
ACO		 6337
6338 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6339 other_crtc_state =
6340 intel_atomic_get_crtc_state(state, other_crtc);
6341 if (IS_ERR(other_crtc_state))
6342 return PTR_ERR(other_crtc_state);
6343
6344 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6345 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6346 return -EINVAL;
1857e1da 6347 }
6d293983 6348 return 0;
1857e1da
DV		 6349 default:
6350 BUG();
6351 }
6352}
6353
e29c22c0
DV		 6354#define RETRY 1
6355static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6356 struct intel_crtc_state *pipe_config)
877d48d5 6357{
1857e1da 6358 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6359 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6360 int lane, link_bw, fdi_dotclock, ret;
6361 bool needs_recompute = false;
877d48d5 6362
e29c22c0 6363retry:
877d48d5
DV		 6364 /* FDI is a binary signal running at ~2.7GHz, encoding
6365 * each output octet as 10 bits. The actual frequency
6366 * is stored as a divider into a 100MHz clock, and the
6367 * mode pixel clock is stored in units of 1KHz.
6368 * Hence the bw of each lane in terms of the mode signal
6369 * is:
6370 */
6371 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6372
241bfc38 6373 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6374
2bd89a07 6375 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6376 pipe_config->pipe_bpp);
6377
6378 pipe_config->fdi_lanes = lane;
6379
2bd89a07 6380 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6381 link_bw, &pipe_config->fdi_m_n);
1857e1da 6382
6d293983
ACO		 6383 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6384 intel_crtc->pipe, pipe_config);
6385 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6386 pipe_config->pipe_bpp -= 2*3;
6387 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6388 pipe_config->pipe_bpp);
6389 needs_recompute = true;
6390 pipe_config->bw_constrained = true;
6391
6392 goto retry;
6393 }
6394
6395 if (needs_recompute)
6396 return RETRY;
6397
6d293983 6398 return ret;
877d48d5
DV		 6399}
6400
42db64ef 6401static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6402 struct intel_crtc_state *pipe_config)
42db64ef 6403{
d330a953 6404 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6405 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6406 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6407}
6408
a43f6e0f 6409static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6410 struct intel_crtc_state *pipe_config)
79e53945 6411{
a43f6e0f 6412 struct drm_device *dev = crtc->base.dev;
8bd31e67 6413 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6414 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6415 int ret;
89749350 6416
ad3a4479 6417 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6418 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6419 int clock_limit =
6420 dev_priv->display.get_display_clock_speed(dev);
6421
6422 /*
6423 * Enable pixel doubling when the dot clock
6424 * is > 90% of the (display) core speed.
6425 *
b397c96b
VS		 6426 * GDG double wide on either pipe,
6427 * otherwise pipe A only.
cf532bb2 6428 */
b397c96b 6429 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6430 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6431 clock_limit *= 2;
cf532bb2 6432 pipe_config->double_wide = true;
ad3a4479
VS		 6433 }
6434
241bfc38 6435 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6436 return -EINVAL;
2c07245f 6437 }
89749350 6438
1d1d0e27
VS		 6439 /*
6440 * Pipe horizontal size must be even in:
6441 * - DVO ganged mode
6442 * - LVDS dual channel mode
6443 * - Double wide pipe
6444 */
a93e255f 6445 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6446 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6447 pipe_config->pipe_src_w &= ~1;
6448
8693a824
DL		 6449 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6450 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6451 */
6452 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6453 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6454 return -EINVAL;
44f46b42 6455
f5adf94e 6456 if (HAS_IPS(dev))
a43f6e0f
DV		 6457 hsw_compute_ips_config(crtc, pipe_config);
6458
877d48d5 6459 if (pipe_config->has_pch_encoder)
a43f6e0f 6460 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6461
d03c93d4
CK		 6462 /* FIXME: remove below call once atomic mode set is place and all crtc
6463 * related checks called from atomic_crtc_check function */
6464 ret = 0;
6465 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6466 crtc, pipe_config->base.state);
6467 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6468
6469 return ret;
79e53945
JB		 6470}
6471
1652d19e
VS		 6472static int skylake_get_display_clock_speed(struct drm_device *dev)
6473{
6474 struct drm_i915_private *dev_priv = to_i915(dev);
6475 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6476 uint32_t cdctl = I915_READ(CDCLK_CTL);
6477 uint32_t linkrate;
6478
6479 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6480 WARN(1, "LCPLL1 not enabled\n");
6481 return 24000; /* 24MHz is the cd freq with NSSC ref */
6482 }
6483
6484 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6485 return 540000;
6486
6487 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6488 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6489
71cd8423
DL		 6490 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6491 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6492 /* vco 8640 */
6493 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6494 case CDCLK_FREQ_450_432:
6495 return 432000;
6496 case CDCLK_FREQ_337_308:
6497 return 308570;
6498 case CDCLK_FREQ_675_617:
6499 return 617140;
6500 default:
6501 WARN(1, "Unknown cd freq selection\n");
6502 }
6503 } else {
6504 /* vco 8100 */
6505 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6506 case CDCLK_FREQ_450_432:
6507 return 450000;
6508 case CDCLK_FREQ_337_308:
6509 return 337500;
6510 case CDCLK_FREQ_675_617:
6511 return 675000;
6512 default:
6513 WARN(1, "Unknown cd freq selection\n");
6514 }
6515 }
6516
6517 /* error case, do as if DPLL0 isn't enabled */
6518 return 24000;
6519}
6520
6521static int broadwell_get_display_clock_speed(struct drm_device *dev)
6522{
6523 struct drm_i915_private *dev_priv = dev->dev_private;
6524 uint32_t lcpll = I915_READ(LCPLL_CTL);
6525 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6526
6527 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6528 return 800000;
6529 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6530 return 450000;
6531 else if (freq == LCPLL_CLK_FREQ_450)
6532 return 450000;
6533 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6534 return 540000;
6535 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6536 return 337500;
6537 else
6538 return 675000;
6539}
6540
6541static int haswell_get_display_clock_speed(struct drm_device *dev)
6542{
6543 struct drm_i915_private *dev_priv = dev->dev_private;
6544 uint32_t lcpll = I915_READ(LCPLL_CTL);
6545 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6546
6547 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6548 return 800000;
6549 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6550 return 450000;
6551 else if (freq == LCPLL_CLK_FREQ_450)
6552 return 450000;
6553 else if (IS_HSW_ULT(dev))
6554 return 337500;
6555 else
6556 return 540000;
79e53945
JB		 6557}
6558
25eb05fc
JB		 6559static int valleyview_get_display_clock_speed(struct drm_device *dev)
6560{
d197b7d3 6561 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6562 u32 val;
6563 int divider;
6564
6bcda4f0
VS		 6565 if (dev_priv->hpll_freq == 0)
6566 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6567
d197b7d3
VS		 6568 mutex_lock(&dev_priv->dpio_lock);
6569 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6570 mutex_unlock(&dev_priv->dpio_lock);
6571
6572 divider = val & DISPLAY_FREQUENCY_VALUES;
6573
7d007f40
VS		 6574 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6575 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6576 "cdclk change in progress\n");
6577
6bcda4f0 6578 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6579}
6580
b37a6434
VS		 6581static int ilk_get_display_clock_speed(struct drm_device *dev)
6582{
6583 return 450000;
6584}
6585
e70236a8
JB		 6586static int i945_get_display_clock_speed(struct drm_device *dev)
6587{
6588 return 400000;
6589}
79e53945 6590
e70236a8 6591static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6592{
e907f170 6593 return 333333;
e70236a8 6594}
79e53945 6595
e70236a8
JB		 6596static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6597{
6598 return 200000;
6599}
79e53945 6600
257a7ffc
DV		 6601static int pnv_get_display_clock_speed(struct drm_device *dev)
6602{
6603 u16 gcfgc = 0;
6604
6605 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6606
6607 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6608 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6609 return 266667;
257a7ffc 6610 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6611 return 333333;
257a7ffc 6612 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6613 return 444444;
257a7ffc
DV		 6614 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6615 return 200000;
6616 default:
6617 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6618 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6619 return 133333;
257a7ffc 6620 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6621 return 166667;
257a7ffc
DV		 6622 }
6623}
6624
e70236a8
JB		 6625static int i915gm_get_display_clock_speed(struct drm_device *dev)
6626{
6627 u16 gcfgc = 0;
79e53945 6628
e70236a8
JB		 6629 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6630
6631 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6632 return 133333;
e70236a8
JB		 6633 else {
6634 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6635 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6636 return 333333;
e70236a8
JB		 6637 default:
6638 case GC_DISPLAY_CLOCK_190_200_MHZ:
6639 return 190000;
79e53945 6640 }
e70236a8
JB		 6641 }
6642}
6643
6644static int i865_get_display_clock_speed(struct drm_device *dev)
6645{
e907f170 6646 return 266667;
e70236a8
JB		 6647}
6648
6649static int i855_get_display_clock_speed(struct drm_device *dev)
6650{
6651 u16 hpllcc = 0;
6652 /* Assume that the hardware is in the high speed state. This
6653 * should be the default.
6654 */
6655 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6656 case GC_CLOCK_133_200:
6657 case GC_CLOCK_100_200:
6658 return 200000;
6659 case GC_CLOCK_166_250:
6660 return 250000;
6661 case GC_CLOCK_100_133:
e907f170 6662 return 133333;
e70236a8 6663 }
79e53945 6664
e70236a8
JB		 6665 /* Shouldn't happen */
6666 return 0;
6667}
79e53945 6668
e70236a8
JB		 6669static int i830_get_display_clock_speed(struct drm_device *dev)
6670{
e907f170 6671 return 133333;
79e53945
JB		 6672}
6673
2c07245f 6674static void
a65851af 6675intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6676{
a65851af
VS		 6677 while (*num > DATA_LINK_M_N_MASK ||
6678 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6679 *num >>= 1;
6680 *den >>= 1;
6681 }
6682}
6683
a65851af
VS		 6684static void compute_m_n(unsigned int m, unsigned int n,
6685 uint32_t *ret_m, uint32_t *ret_n)
6686{
6687 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6688 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6689 intel_reduce_m_n_ratio(ret_m, ret_n);
6690}
6691
e69d0bc1
DV		 6692void
6693intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6694 int pixel_clock, int link_clock,
6695 struct intel_link_m_n *m_n)
2c07245f 6696{
e69d0bc1 6697 m_n->tu = 64;
a65851af
VS		 6698
6699 compute_m_n(bits_per_pixel * pixel_clock,
6700 link_clock * nlanes * 8,
6701 &m_n->gmch_m, &m_n->gmch_n);
6702
6703 compute_m_n(pixel_clock, link_clock,
6704 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6705}
6706
a7615030
CW		 6707static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6708{
d330a953
JN		 6709 if (i915.panel_use_ssc >= 0)
6710 return i915.panel_use_ssc != 0;
41aa3448 6711 return dev_priv->vbt.lvds_use_ssc
435793df 6712 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6713}
6714
a93e255f
ACO		 6715static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6716 int num_connectors)
c65d77d8 6717{
a93e255f 6718 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6719 struct drm_i915_private *dev_priv = dev->dev_private;
6720 int refclk;
6721
a93e255f
ACO		 6722 WARN_ON(!crtc_state->base.state);
6723
5ab7b0b7 6724 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6725 refclk = 100000;
a93e255f 6726 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6727 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6728 refclk = dev_priv->vbt.lvds_ssc_freq;
6729 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6730 } else if (!IS_GEN2(dev)) {
6731 refclk = 96000;
6732 } else {
6733 refclk = 48000;
6734 }
6735
6736 return refclk;
6737}
6738
7429e9d4 6739static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6740{
7df00d7a 6741 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6742}
f47709a9 6743
7429e9d4
DV		 6744static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6745{
6746 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6747}
6748
f47709a9 6749static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6750 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6751 intel_clock_t *reduced_clock)
6752{
f47709a9 6753 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6754 u32 fp, fp2 = 0;
6755
6756 if (IS_PINEVIEW(dev)) {
190f68c5 6757 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6758 if (reduced_clock)
7429e9d4 6759 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6760 } else {
190f68c5 6761 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6762 if (reduced_clock)
7429e9d4 6763 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6764 }
6765
190f68c5 6766 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6767
f47709a9 6768 crtc->lowfreq_avail = false;
a93e255f 6769 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6770 reduced_clock) {
190f68c5 6771 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6772 crtc->lowfreq_avail = true;
a7516a05 6773 } else {
190f68c5 6774 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6775 }
6776}
6777
5e69f97f
CML		 6778static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6779 pipe)
89b667f8
JB		 6780{
6781 u32 reg_val;
6782
6783 /*
6784 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6785 * and set it to a reasonable value instead.
6786 */
ab3c759a 6787 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6788 reg_val &= 0xffffff00;
6789 reg_val |= 0x00000030;
ab3c759a 6790 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6791
ab3c759a 6792 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6793 reg_val &= 0x8cffffff;
6794 reg_val = 0x8c000000;
ab3c759a 6795 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6796
ab3c759a 6797 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6798 reg_val &= 0xffffff00;
ab3c759a 6799 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6800
ab3c759a 6801 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6802 reg_val &= 0x00ffffff;
6803 reg_val |= 0xb0000000;
ab3c759a 6804 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6805}
6806
b551842d
DV		 6807static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6808 struct intel_link_m_n *m_n)
6809{
6810 struct drm_device *dev = crtc->base.dev;
6811 struct drm_i915_private *dev_priv = dev->dev_private;
6812 int pipe = crtc->pipe;
6813
e3b95f1e
DV		 6814 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6815 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6816 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6817 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6818}
6819
6820static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6821 struct intel_link_m_n *m_n,
6822 struct intel_link_m_n *m2_n2)
b551842d
DV		 6823{
6824 struct drm_device *dev = crtc->base.dev;
6825 struct drm_i915_private *dev_priv = dev->dev_private;
6826 int pipe = crtc->pipe;
6e3c9717 6827 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6828
6829 if (INTEL_INFO(dev)->gen >= 5) {
6830 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6831 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6832 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6833 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6834 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6835 * for gen < 8) and if DRRS is supported (to make sure the
6836 * registers are not unnecessarily accessed).
6837 */
44395bfe 6838 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6839 crtc->config->has_drrs) {
f769cd24
VK		 6840 I915_WRITE(PIPE_DATA_M2(transcoder),
6841 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6842 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6843 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6844 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6845 }
b551842d 6846 } else {
e3b95f1e
DV		 6847 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6848 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6849 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6850 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6851 }
6852}
6853
fe3cd48d 6854void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6855{
fe3cd48d
R		 6856 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6857
6858 if (m_n == M1_N1) {
6859 dp_m_n = &crtc->config->dp_m_n;
6860 dp_m2_n2 = &crtc->config->dp_m2_n2;
6861 } else if (m_n == M2_N2) {
6862
6863 /*
6864 * M2_N2 registers are not supported. Hence m2_n2 divider value
6865 * needs to be programmed into M1_N1.
6866 */
6867 dp_m_n = &crtc->config->dp_m2_n2;
6868 } else {
6869 DRM_ERROR("Unsupported divider value\n");
6870 return;
6871 }
6872
6e3c9717
ACO		 6873 if (crtc->config->has_pch_encoder)
6874 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6875 else
fe3cd48d 6876 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6877}
6878
d288f65f 6879static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6880 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6881{
6882 u32 dpll, dpll_md;
6883
6884 /*
6885 * Enable DPIO clock input. We should never disable the reference
6886 * clock for pipe B, since VGA hotplug / manual detection depends
6887 * on it.
6888 */
6889 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6890 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6891 /* We should never disable this, set it here for state tracking */
6892 if (crtc->pipe == PIPE_B)
6893 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6894 dpll |= DPLL_VCO_ENABLE;
d288f65f 6895 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6896
d288f65f 6897 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6898 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6899 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6900}
6901
d288f65f 6902static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6903 const struct intel_crtc_state *pipe_config)
a0c4da24 6904{
f47709a9 6905 struct drm_device *dev = crtc->base.dev;
a0c4da24 6906 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6907 int pipe = crtc->pipe;
bdd4b6a6 6908 u32 mdiv;
a0c4da24 6909 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6910 u32 coreclk, reg_val;
a0c4da24 6911
09153000
DV		 6912 mutex_lock(&dev_priv->dpio_lock);
6913
d288f65f
VS		 6914 bestn = pipe_config->dpll.n;
6915 bestm1 = pipe_config->dpll.m1;
6916 bestm2 = pipe_config->dpll.m2;
6917 bestp1 = pipe_config->dpll.p1;
6918 bestp2 = pipe_config->dpll.p2;
a0c4da24 6919
89b667f8
JB		 6920 /* See eDP HDMI DPIO driver vbios notes doc */
6921
6922 /* PLL B needs special handling */
bdd4b6a6 6923 if (pipe == PIPE_B)
5e69f97f 6924 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6925
6926 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6927 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6928
6929 /* Disable target IRef on PLL */
ab3c759a 6930 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6931 reg_val &= 0x00ffffff;
ab3c759a 6932 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6933
6934 /* Disable fast lock */
ab3c759a 6935 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6936
6937 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6938 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6939 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6940 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6941 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6942
6943 /*
6944 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6945 * but we don't support that).
6946 * Note: don't use the DAC post divider as it seems unstable.
6947 */
6948 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6949 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6950
a0c4da24 6951 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6952 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6953
89b667f8 6954 /* Set HBR and RBR LPF coefficients */
d288f65f 6955 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6956 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6957 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6958 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6959 0x009f0003);
89b667f8 6960 else
ab3c759a 6961 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6962 0x00d0000f);
6963
681a8504 6964 if (pipe_config->has_dp_encoder) {
89b667f8 6965 /* Use SSC source */
bdd4b6a6 6966 if (pipe == PIPE_A)
ab3c759a 6967 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6968 0x0df40000);
6969 else
ab3c759a 6970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6971 0x0df70000);
6972 } else { /* HDMI or VGA */
6973 /* Use bend source */
bdd4b6a6 6974 if (pipe == PIPE_A)
ab3c759a 6975 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6976 0x0df70000);
6977 else
ab3c759a 6978 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6979 0x0df40000);
6980 }
a0c4da24 6981
ab3c759a 6982 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6983 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6984 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6985 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6986 coreclk |= 0x01000000;
ab3c759a 6987 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6988
ab3c759a 6989 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6990 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6991}
6992
d288f65f 6993static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6994 struct intel_crtc_state *pipe_config)
1ae0d137 6995{
d288f65f 6996 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6997 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6998 DPLL_VCO_ENABLE;
6999 if (crtc->pipe != PIPE_A)
d288f65f 7000 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7001
d288f65f
VS		 7002 pipe_config->dpll_hw_state.dpll_md =
7003 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7004}
7005
d288f65f 7006static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7007 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7008{
7009 struct drm_device *dev = crtc->base.dev;
7010 struct drm_i915_private *dev_priv = dev->dev_private;
7011 int pipe = crtc->pipe;
7012 int dpll_reg = DPLL(crtc->pipe);
7013 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7014 u32 loopfilter, tribuf_calcntr;
9d556c99 7015 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7016 u32 dpio_val;
9cbe40c1 7017 int vco;
9d556c99 7018
d288f65f
VS		 7019 bestn = pipe_config->dpll.n;
7020 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7021 bestm1 = pipe_config->dpll.m1;
7022 bestm2 = pipe_config->dpll.m2 >> 22;
7023 bestp1 = pipe_config->dpll.p1;
7024 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7025 vco = pipe_config->dpll.vco;
a945ce7e 7026 dpio_val = 0;
9cbe40c1 7027 loopfilter = 0;
9d556c99
CML		 7028
7029 /*
7030 * Enable Refclk and SSC
7031 */
a11b0703 7032 I915_WRITE(dpll_reg,
d288f65f 7033 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 7034
7035 mutex_lock(&dev_priv->dpio_lock);
9d556c99 7036
9d556c99
CML		 7037 /* p1 and p2 divider */
7038 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7039 5 << DPIO_CHV_S1_DIV_SHIFT |
7040 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7041 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7042 1 << DPIO_CHV_K_DIV_SHIFT);
7043
7044 /* Feedback post-divider - m2 */
7045 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7046
7047 /* Feedback refclk divider - n and m1 */
7048 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7049 DPIO_CHV_M1_DIV_BY_2 |
7050 1 << DPIO_CHV_N_DIV_SHIFT);
7051
7052 /* M2 fraction division */
a945ce7e
VP		 7053 if (bestm2_frac)
7054 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7055
7056 /* M2 fraction division enable */
a945ce7e
VP		 7057 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7058 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7059 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7060 if (bestm2_frac)
7061 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7062 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7063
de3a0fde
VP		 7064 /* Program digital lock detect threshold */
7065 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7066 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7067 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7068 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7069 if (!bestm2_frac)
7070 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7071 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7072
9d556c99 7073 /* Loop filter */
9cbe40c1
VP		 7074 if (vco == 5400000) {
7075 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7076 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7077 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7078 tribuf_calcntr = 0x9;
7079 } else if (vco <= 6200000) {
7080 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7081 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7082 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7083 tribuf_calcntr = 0x9;
7084 } else if (vco <= 6480000) {
7085 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7086 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7087 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7088 tribuf_calcntr = 0x8;
7089 } else {
7090 /* Not supported. Apply the same limits as in the max case */
7091 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7092 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7093 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7094 tribuf_calcntr = 0;
7095 }
9d556c99
CML		 7096 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7097
968040b2 7098 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7099 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7100 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7101 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7102
9d556c99
CML		 7103 /* AFC Recal */
7104 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7105 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7106 DPIO_AFC_RECAL);
7107
7108 mutex_unlock(&dev_priv->dpio_lock);
7109}
7110
d288f65f
VS		 7111/**
7112 * vlv_force_pll_on - forcibly enable just the PLL
7113 * @dev_priv: i915 private structure
7114 * @pipe: pipe PLL to enable
7115 * @dpll: PLL configuration
7116 *
7117 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7118 * in cases where we need the PLL enabled even when @pipe is not going to
7119 * be enabled.
7120 */
7121void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7122 const struct dpll *dpll)
7123{
7124 struct intel_crtc *crtc =
7125 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7126 struct intel_crtc_state pipe_config = {
a93e255f 7127 .base.crtc = &crtc->base,
d288f65f
VS		 7128 .pixel_multiplier = 1,
7129 .dpll = *dpll,
7130 };
7131
7132 if (IS_CHERRYVIEW(dev)) {
7133 chv_update_pll(crtc, &pipe_config);
7134 chv_prepare_pll(crtc, &pipe_config);
7135 chv_enable_pll(crtc, &pipe_config);
7136 } else {
7137 vlv_update_pll(crtc, &pipe_config);
7138 vlv_prepare_pll(crtc, &pipe_config);
7139 vlv_enable_pll(crtc, &pipe_config);
7140 }
7141}
7142
7143/**
7144 * vlv_force_pll_off - forcibly disable just the PLL
7145 * @dev_priv: i915 private structure
7146 * @pipe: pipe PLL to disable
7147 *
7148 * Disable the PLL for @pipe. To be used in cases where we need
7149 * the PLL enabled even when @pipe is not going to be enabled.
7150 */
7151void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7152{
7153 if (IS_CHERRYVIEW(dev))
7154 chv_disable_pll(to_i915(dev), pipe);
7155 else
7156 vlv_disable_pll(to_i915(dev), pipe);
7157}
7158
f47709a9 7159static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7160 struct intel_crtc_state *crtc_state,
f47709a9 7161 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7162 int num_connectors)
7163{
f47709a9 7164 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7165 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7166 u32 dpll;
7167 bool is_sdvo;
190f68c5 7168 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7169
190f68c5 7170 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7171
a93e255f
ACO		 7172 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7173 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7174
7175 dpll = DPLL_VGA_MODE_DIS;
7176
a93e255f 7177 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7178 dpll |= DPLLB_MODE_LVDS;
7179 else
7180 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7181
ef1b460d 7182 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7183 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7184 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7185 }
198a037f
DV		 7186
7187 if (is_sdvo)
4a33e48d 7188 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7189
190f68c5 7190 if (crtc_state->has_dp_encoder)
4a33e48d 7191 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7192
7193 /* compute bitmask from p1 value */
7194 if (IS_PINEVIEW(dev))
7195 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7196 else {
7197 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7198 if (IS_G4X(dev) && reduced_clock)
7199 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7200 }
7201 switch (clock->p2) {
7202 case 5:
7203 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7204 break;
7205 case 7:
7206 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7207 break;
7208 case 10:
7209 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7210 break;
7211 case 14:
7212 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7213 break;
7214 }
7215 if (INTEL_INFO(dev)->gen >= 4)
7216 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7217
190f68c5 7218 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7219 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7220 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7221 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7222 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7223 else
7224 dpll |= PLL_REF_INPUT_DREFCLK;
7225
7226 dpll |= DPLL_VCO_ENABLE;
190f68c5 7227 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7228
eb1cbe48 7229 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7230 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7231 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7232 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7233 }
7234}
7235
f47709a9 7236static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7237 struct intel_crtc_state *crtc_state,
f47709a9 7238 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7239 int num_connectors)
7240{
f47709a9 7241 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7242 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7243 u32 dpll;
190f68c5 7244 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7245
190f68c5 7246 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7247
eb1cbe48
DV		 7248 dpll = DPLL_VGA_MODE_DIS;
7249
a93e255f 7250 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7251 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7252 } else {
7253 if (clock->p1 == 2)
7254 dpll |= PLL_P1_DIVIDE_BY_TWO;
7255 else
7256 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7257 if (clock->p2 == 4)
7258 dpll |= PLL_P2_DIVIDE_BY_4;
7259 }
7260
a93e255f 7261 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7262 dpll |= DPLL_DVO_2X_MODE;
7263
a93e255f 7264 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7265 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7266 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7267 else
7268 dpll |= PLL_REF_INPUT_DREFCLK;
7269
7270 dpll |= DPLL_VCO_ENABLE;
190f68c5 7271 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7272}
7273
8a654f3b 7274static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7275{
7276 struct drm_device *dev = intel_crtc->base.dev;
7277 struct drm_i915_private *dev_priv = dev->dev_private;
7278 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7279 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7280 struct drm_display_mode *adjusted_mode =
6e3c9717 7281 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7282 uint32_t crtc_vtotal, crtc_vblank_end;
7283 int vsyncshift = 0;
4d8a62ea
DV		 7284
7285 /* We need to be careful not to changed the adjusted mode, for otherwise
7286 * the hw state checker will get angry at the mismatch. */
7287 crtc_vtotal = adjusted_mode->crtc_vtotal;
7288 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7289
609aeaca 7290 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7291 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7292 crtc_vtotal -= 1;
7293 crtc_vblank_end -= 1;
609aeaca 7294
409ee761 7295 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7296 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7297 else
7298 vsyncshift = adjusted_mode->crtc_hsync_start -
7299 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7300 if (vsyncshift < 0)
7301 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7302 }
7303
7304 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7305 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7306
fe2b8f9d 7307 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7308 (adjusted_mode->crtc_hdisplay - 1) |
7309 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7310 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7311 (adjusted_mode->crtc_hblank_start - 1) |
7312 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7313 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7314 (adjusted_mode->crtc_hsync_start - 1) |
7315 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7316
fe2b8f9d 7317 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7318 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7319 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7320 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7321 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7322 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7323 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7324 (adjusted_mode->crtc_vsync_start - 1) |
7325 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7326
b5e508d4
PZ		 7327 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7328 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7329 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7330 * bits. */
7331 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7332 (pipe == PIPE_B || pipe == PIPE_C))
7333 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7334
b0e77b9c
PZ		 7335 /* pipesrc controls the size that is scaled from, which should
7336 * always be the user's requested size.
7337 */
7338 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7339 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7340 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7341}
7342
1bd1bd80 7343static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7344 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7345{
7346 struct drm_device *dev = crtc->base.dev;
7347 struct drm_i915_private *dev_priv = dev->dev_private;
7348 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7349 uint32_t tmp;
7350
7351 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7352 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7353 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7354 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7355 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7356 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7357 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7358 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7359 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7360
7361 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7362 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7363 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7364 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7365 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7366 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7367 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7368 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7369 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7370
7371 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7372 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7373 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7374 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7375 }
7376
7377 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7378 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7379 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7380
2d112de7
ACO		 7381 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7382 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7383}
7384
f6a83288 7385void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7386 struct intel_crtc_state *pipe_config)
babea61d 7387{
2d112de7
ACO		 7388 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7389 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7390 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7391 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7392
2d112de7
ACO		 7393 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7394 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7395 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7396 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7397
2d112de7 7398 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7399
2d112de7
ACO		 7400 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7401 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7402}
7403
84b046f3
DV		 7404static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7405{
7406 struct drm_device *dev = intel_crtc->base.dev;
7407 struct drm_i915_private *dev_priv = dev->dev_private;
7408 uint32_t pipeconf;
7409
9f11a9e4 7410 pipeconf = 0;
84b046f3 7411
b6b5d049
VS		 7412 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7413 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7414 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7415
6e3c9717 7416 if (intel_crtc->config->double_wide)
cf532bb2 7417 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7418
ff9ce46e
DV		 7419 /* only g4x and later have fancy bpc/dither controls */
7420 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7421 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7422 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7423 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7424 PIPECONF_DITHER_TYPE_SP;
84b046f3 7425
6e3c9717 7426 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7427 case 18:
7428 pipeconf |= PIPECONF_6BPC;
7429 break;
7430 case 24:
7431 pipeconf |= PIPECONF_8BPC;
7432 break;
7433 case 30:
7434 pipeconf |= PIPECONF_10BPC;
7435 break;
7436 default:
7437 /* Case prevented by intel_choose_pipe_bpp_dither. */
7438 BUG();
84b046f3
DV		 7439 }
7440 }
7441
7442 if (HAS_PIPE_CXSR(dev)) {
7443 if (intel_crtc->lowfreq_avail) {
7444 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7445 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7446 } else {
7447 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7448 }
7449 }
7450
6e3c9717 7451 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7452 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7453 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7454 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7455 else
7456 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7457 } else
84b046f3
DV		 7458 pipeconf |= PIPECONF_PROGRESSIVE;
7459
6e3c9717 7460 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7461 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7462
84b046f3
DV		 7463 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7464 POSTING_READ(PIPECONF(intel_crtc->pipe));
7465}
7466
190f68c5
ACO		 7467static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7468 struct intel_crtc_state *crtc_state)
79e53945 7469{
c7653199 7470 struct drm_device *dev = crtc->base.dev;
79e53945 7471 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7472 int refclk, num_connectors = 0;
652c393a 7473 intel_clock_t clock, reduced_clock;
a16af721 7474 bool ok, has_reduced_clock = false;
e9fd1c02 7475 bool is_lvds = false, is_dsi = false;
5eddb70b 7476 struct intel_encoder *encoder;
d4906093 7477 const intel_limit_t *limit;
55bb9992 7478 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7479 struct drm_connector *connector;
55bb9992
ACO		 7480 struct drm_connector_state *connector_state;
7481 int i;
79e53945 7482
da3ced29 7483 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7484 if (connector_state->crtc != &crtc->base)
7485 continue;
7486
7487 encoder = to_intel_encoder(connector_state->best_encoder);
7488
5eddb70b 7489 switch (encoder->type) {
79e53945
JB		 7490 case INTEL_OUTPUT_LVDS:
7491 is_lvds = true;
7492 break;
e9fd1c02
JN		 7493 case INTEL_OUTPUT_DSI:
7494 is_dsi = true;
7495 break;
6847d71b
PZ		 7496 default:
7497 break;
79e53945 7498 }
43565a06 7499
c751ce4f 7500 num_connectors++;
79e53945
JB		 7501 }
7502
f2335330 7503 if (is_dsi)
5b18e57c 7504 return 0;
f2335330 7505
190f68c5 7506 if (!crtc_state->clock_set) {
a93e255f 7507 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7508
e9fd1c02
JN		 7509 /*
7510 * Returns a set of divisors for the desired target clock with
7511 * the given refclk, or FALSE. The returned values represent
7512 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7513 * 2) / p1 / p2.
7514 */
a93e255f
ACO		 7515 limit = intel_limit(crtc_state, refclk);
7516 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7517 crtc_state->port_clock,
e9fd1c02 7518 refclk, NULL, &clock);
f2335330 7519 if (!ok) {
e9fd1c02
JN		 7520 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7521 return -EINVAL;
7522 }
79e53945 7523
f2335330
JN		 7524 if (is_lvds && dev_priv->lvds_downclock_avail) {
7525 /*
7526 * Ensure we match the reduced clock's P to the target
7527 * clock. If the clocks don't match, we can't switch
7528 * the display clock by using the FP0/FP1. In such case
7529 * we will disable the LVDS downclock feature.
7530 */
7531 has_reduced_clock =
a93e255f 7532 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7533 dev_priv->lvds_downclock,
7534 refclk, &clock,
7535 &reduced_clock);
7536 }
7537 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7538 crtc_state->dpll.n = clock.n;
7539 crtc_state->dpll.m1 = clock.m1;
7540 crtc_state->dpll.m2 = clock.m2;
7541 crtc_state->dpll.p1 = clock.p1;
7542 crtc_state->dpll.p2 = clock.p2;
f47709a9 7543 }
7026d4ac 7544
e9fd1c02 7545 if (IS_GEN2(dev)) {
190f68c5 7546 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7547 has_reduced_clock ? &reduced_clock : NULL,
7548 num_connectors);
9d556c99 7549 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7550 chv_update_pll(crtc, crtc_state);
e9fd1c02 7551 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7552 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7553 } else {
190f68c5 7554 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7555 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7556 num_connectors);
e9fd1c02 7557 }
79e53945 7558
c8f7a0db 7559 return 0;
f564048e
EA		 7560}
7561
2fa2fe9a 7562static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7563 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7564{
7565 struct drm_device *dev = crtc->base.dev;
7566 struct drm_i915_private *dev_priv = dev->dev_private;
7567 uint32_t tmp;
7568
dc9e7dec
VS		 7569 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7570 return;
7571
2fa2fe9a 7572 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7573 if (!(tmp & PFIT_ENABLE))
7574 return;
2fa2fe9a 7575
06922821 7576 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7577 if (INTEL_INFO(dev)->gen < 4) {
7578 if (crtc->pipe != PIPE_B)
7579 return;
2fa2fe9a
DV		 7580 } else {
7581 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7582 return;
7583 }
7584
06922821 7585 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7586 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7587 if (INTEL_INFO(dev)->gen < 5)
7588 pipe_config->gmch_pfit.lvds_border_bits =
7589 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7590}
7591
acbec814 7592static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7593 struct intel_crtc_state *pipe_config)
acbec814
JB		 7594{
7595 struct drm_device *dev = crtc->base.dev;
7596 struct drm_i915_private *dev_priv = dev->dev_private;
7597 int pipe = pipe_config->cpu_transcoder;
7598 intel_clock_t clock;
7599 u32 mdiv;
662c6ecb 7600 int refclk = 100000;
acbec814 7601
f573de5a
SK		 7602 /* In case of MIPI DPLL will not even be used */
7603 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7604 return;
7605
acbec814 7606 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7607 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7608 mutex_unlock(&dev_priv->dpio_lock);
7609
7610 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7611 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7612 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7613 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7614 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7615
f646628b 7616 vlv_clock(refclk, &clock);
acbec814 7617
f646628b
VS		 7618 /* clock.dot is the fast clock */
7619 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7620}
7621
5724dbd1
DL		 7622static void
7623i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7624 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7625{
7626 struct drm_device *dev = crtc->base.dev;
7627 struct drm_i915_private *dev_priv = dev->dev_private;
7628 u32 val, base, offset;
7629 int pipe = crtc->pipe, plane = crtc->plane;
7630 int fourcc, pixel_format;
6761dd31 7631 unsigned int aligned_height;
b113d5ee 7632 struct drm_framebuffer *fb;
1b842c89 7633 struct intel_framebuffer *intel_fb;
1ad292b5 7634
42a7b088
DL		 7635 val = I915_READ(DSPCNTR(plane));
7636 if (!(val & DISPLAY_PLANE_ENABLE))
7637 return;
7638
d9806c9f 7639 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7640 if (!intel_fb) {
1ad292b5
JB		 7641 DRM_DEBUG_KMS("failed to alloc fb\n");
7642 return;
7643 }
7644
1b842c89
DL		 7645 fb = &intel_fb->base;
7646
18c5247e
DV		 7647 if (INTEL_INFO(dev)->gen >= 4) {
7648 if (val & DISPPLANE_TILED) {
49af449b 7649 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7650 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7651 }
7652 }
1ad292b5
JB		 7653
7654 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7655 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7656 fb->pixel_format = fourcc;
7657 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7658
7659 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7660 if (plane_config->tiling)
1ad292b5
JB		 7661 offset = I915_READ(DSPTILEOFF(plane));
7662 else
7663 offset = I915_READ(DSPLINOFF(plane));
7664 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7665 } else {
7666 base = I915_READ(DSPADDR(plane));
7667 }
7668 plane_config->base = base;
7669
7670 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7671 fb->width = ((val >> 16) & 0xfff) + 1;
7672 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7673
7674 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7675 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7676
b113d5ee 7677 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7678 fb->pixel_format,
7679 fb->modifier[0]);
1ad292b5 7680
f37b5c2b 7681 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7682
2844a921
DL		 7683 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7684 pipe_name(pipe), plane, fb->width, fb->height,
7685 fb->bits_per_pixel, base, fb->pitches[0],
7686 plane_config->size);
1ad292b5 7687
2d14030b 7688 plane_config->fb = intel_fb;
1ad292b5
JB		 7689}
7690
70b23a98 7691static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7692 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7693{
7694 struct drm_device *dev = crtc->base.dev;
7695 struct drm_i915_private *dev_priv = dev->dev_private;
7696 int pipe = pipe_config->cpu_transcoder;
7697 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7698 intel_clock_t clock;
7699 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7700 int refclk = 100000;
7701
7702 mutex_lock(&dev_priv->dpio_lock);
7703 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7704 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7705 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7706 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7707 mutex_unlock(&dev_priv->dpio_lock);
7708
7709 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7710 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7711 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7712 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7713 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7714
7715 chv_clock(refclk, &clock);
7716
7717 /* clock.dot is the fast clock */
7718 pipe_config->port_clock = clock.dot / 5;
7719}
7720
0e8ffe1b 7721static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7722 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7723{
7724 struct drm_device *dev = crtc->base.dev;
7725 struct drm_i915_private *dev_priv = dev->dev_private;
7726 uint32_t tmp;
7727
f458ebbc
DV		 7728 if (!intel_display_power_is_enabled(dev_priv,
7729 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7730 return false;
7731
e143a21c 7732 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7733 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7734
0e8ffe1b
DV		 7735 tmp = I915_READ(PIPECONF(crtc->pipe));
7736 if (!(tmp & PIPECONF_ENABLE))
7737 return false;
7738
42571aef
VS		 7739 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7740 switch (tmp & PIPECONF_BPC_MASK) {
7741 case PIPECONF_6BPC:
7742 pipe_config->pipe_bpp = 18;
7743 break;
7744 case PIPECONF_8BPC:
7745 pipe_config->pipe_bpp = 24;
7746 break;
7747 case PIPECONF_10BPC:
7748 pipe_config->pipe_bpp = 30;
7749 break;
7750 default:
7751 break;
7752 }
7753 }
7754
b5a9fa09
DV		 7755 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7756 pipe_config->limited_color_range = true;
7757
282740f7
VS		 7758 if (INTEL_INFO(dev)->gen < 4)
7759 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7760
1bd1bd80
DV		 7761 intel_get_pipe_timings(crtc, pipe_config);
7762
2fa2fe9a
DV		 7763 i9xx_get_pfit_config(crtc, pipe_config);
7764
6c49f241
DV		 7765 if (INTEL_INFO(dev)->gen >= 4) {
7766 tmp = I915_READ(DPLL_MD(crtc->pipe));
7767 pipe_config->pixel_multiplier =
7768 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7769 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7770 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7771 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7772 tmp = I915_READ(DPLL(crtc->pipe));
7773 pipe_config->pixel_multiplier =
7774 ((tmp & SDVO_MULTIPLIER_MASK)
7775 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7776 } else {
7777 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7778 * port and will be fixed up in the encoder->get_config
7779 * function. */
7780 pipe_config->pixel_multiplier = 1;
7781 }
8bcc2795
DV		 7782 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7783 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7784 /*
7785 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7786 * on 830. Filter it out here so that we don't
7787 * report errors due to that.
7788 */
7789 if (IS_I830(dev))
7790 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7791
8bcc2795
DV		 7792 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7793 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7794 } else {
7795 /* Mask out read-only status bits. */
7796 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7797 DPLL_PORTC_READY_MASK |
7798 DPLL_PORTB_READY_MASK);
8bcc2795 7799 }
6c49f241 7800
70b23a98
VS		 7801 if (IS_CHERRYVIEW(dev))
7802 chv_crtc_clock_get(crtc, pipe_config);
7803 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7804 vlv_crtc_clock_get(crtc, pipe_config);
7805 else
7806 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7807
0e8ffe1b
DV		 7808 return true;
7809}
7810
dde86e2d 7811static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7812{
7813 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7814 struct intel_encoder *encoder;
74cfd7ac 7815 u32 val, final;
13d83a67 7816 bool has_lvds = false;
199e5d79 7817 bool has_cpu_edp = false;
199e5d79 7818 bool has_panel = false;
99eb6a01
KP		 7819 bool has_ck505 = false;
7820 bool can_ssc = false;
13d83a67
JB		 7821
7822 /* We need to take the global config into account */
b2784e15 7823 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7824 switch (encoder->type) {
7825 case INTEL_OUTPUT_LVDS:
7826 has_panel = true;
7827 has_lvds = true;
7828 break;
7829 case INTEL_OUTPUT_EDP:
7830 has_panel = true;
2de6905f 7831 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7832 has_cpu_edp = true;
7833 break;
6847d71b
PZ		 7834 default:
7835 break;
13d83a67
JB		 7836 }
7837 }
7838
99eb6a01 7839 if (HAS_PCH_IBX(dev)) {
41aa3448 7840 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7841 can_ssc = has_ck505;
7842 } else {
7843 has_ck505 = false;
7844 can_ssc = true;
7845 }
7846
2de6905f
ID		 7847 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7848 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7849
7850 /* Ironlake: try to setup display ref clock before DPLL
7851 * enabling. This is only under driver's control after
7852 * PCH B stepping, previous chipset stepping should be
7853 * ignoring this setting.
7854 */
74cfd7ac
CW		 7855 val = I915_READ(PCH_DREF_CONTROL);
7856
7857 /* As we must carefully and slowly disable/enable each source in turn,
7858 * compute the final state we want first and check if we need to
7859 * make any changes at all.
7860 */
7861 final = val;
7862 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7863 if (has_ck505)
7864 final |= DREF_NONSPREAD_CK505_ENABLE;
7865 else
7866 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7867
7868 final &= ~DREF_SSC_SOURCE_MASK;
7869 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7870 final &= ~DREF_SSC1_ENABLE;
7871
7872 if (has_panel) {
7873 final |= DREF_SSC_SOURCE_ENABLE;
7874
7875 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7876 final |= DREF_SSC1_ENABLE;
7877
7878 if (has_cpu_edp) {
7879 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7880 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7881 else
7882 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7883 } else
7884 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7885 } else {
7886 final |= DREF_SSC_SOURCE_DISABLE;
7887 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7888 }
7889
7890 if (final == val)
7891 return;
7892
13d83a67 7893 /* Always enable nonspread source */
74cfd7ac 7894 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7895
99eb6a01 7896 if (has_ck505)
74cfd7ac 7897 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7898 else
74cfd7ac 7899 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7900
199e5d79 7901 if (has_panel) {
74cfd7ac
CW		 7902 val &= ~DREF_SSC_SOURCE_MASK;
7903 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7904
199e5d79 7905 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7906 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7907 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7908 val |= DREF_SSC1_ENABLE;
e77166b5 7909 } else
74cfd7ac 7910 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7911
7912 /* Get SSC going before enabling the outputs */
74cfd7ac 7913 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7914 POSTING_READ(PCH_DREF_CONTROL);
7915 udelay(200);
7916
74cfd7ac 7917 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7918
7919 /* Enable CPU source on CPU attached eDP */
199e5d79 7920 if (has_cpu_edp) {
99eb6a01 7921 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7922 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7923 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7924 } else
74cfd7ac 7925 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7926 } else
74cfd7ac 7927 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7928
74cfd7ac 7929 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7930 POSTING_READ(PCH_DREF_CONTROL);
7931 udelay(200);
7932 } else {
7933 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7934
74cfd7ac 7935 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7936
7937 /* Turn off CPU output */
74cfd7ac 7938 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7939
74cfd7ac 7940 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7941 POSTING_READ(PCH_DREF_CONTROL);
7942 udelay(200);
7943
7944 /* Turn off the SSC source */
74cfd7ac
CW		 7945 val &= ~DREF_SSC_SOURCE_MASK;
7946 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7947
7948 /* Turn off SSC1 */
74cfd7ac 7949 val &= ~DREF_SSC1_ENABLE;
199e5d79 7950
74cfd7ac 7951 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7952 POSTING_READ(PCH_DREF_CONTROL);
7953 udelay(200);
7954 }
74cfd7ac
CW		 7955
7956 BUG_ON(val != final);
13d83a67
JB		 7957}
7958
f31f2d55 7959static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7960{
f31f2d55 7961 uint32_t tmp;
dde86e2d 7962
0ff066a9
PZ		 7963 tmp = I915_READ(SOUTH_CHICKEN2);
7964 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7965 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7966
0ff066a9
PZ		 7967 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7968 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7969 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7970
0ff066a9
PZ		 7971 tmp = I915_READ(SOUTH_CHICKEN2);
7972 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7973 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7974
0ff066a9
PZ		 7975 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7976 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7977 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7978}
7979
7980/* WaMPhyProgramming:hsw */
7981static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7982{
7983 uint32_t tmp;
dde86e2d
PZ		 7984
7985 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7986 tmp &= ~(0xFF << 24);
7987 tmp |= (0x12 << 24);
7988 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7989
dde86e2d
PZ		 7990 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7991 tmp |= (1 << 11);
7992 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7993
7994 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7995 tmp |= (1 << 11);
7996 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7997
dde86e2d
PZ		 7998 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7999 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8000 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8001
8002 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8003 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8004 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8005
0ff066a9
PZ		 8006 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8007 tmp &= ~(7 << 13);
8008 tmp |= (5 << 13);
8009 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8010
0ff066a9
PZ		 8011 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8012 tmp &= ~(7 << 13);
8013 tmp |= (5 << 13);
8014 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8015
8016 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8017 tmp &= ~0xFF;
8018 tmp |= 0x1C;
8019 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8020
8021 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8022 tmp &= ~0xFF;
8023 tmp |= 0x1C;
8024 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8025
8026 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8027 tmp &= ~(0xFF << 16);
8028 tmp |= (0x1C << 16);
8029 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8030
8031 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8032 tmp &= ~(0xFF << 16);
8033 tmp |= (0x1C << 16);
8034 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8035
0ff066a9
PZ		 8036 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8037 tmp |= (1 << 27);
8038 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8039
0ff066a9
PZ		 8040 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8041 tmp |= (1 << 27);
8042 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8043
0ff066a9
PZ		 8044 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8045 tmp &= ~(0xF << 28);
8046 tmp |= (4 << 28);
8047 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8048
0ff066a9
PZ		 8049 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8050 tmp &= ~(0xF << 28);
8051 tmp |= (4 << 28);
8052 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8053}
8054
2fa86a1f
PZ		 8055/* Implements 3 different sequences from BSpec chapter "Display iCLK
8056 * Programming" based on the parameters passed:
8057 * - Sequence to enable CLKOUT_DP
8058 * - Sequence to enable CLKOUT_DP without spread
8059 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8060 */
8061static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8062 bool with_fdi)
f31f2d55
PZ		 8063{
8064 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8065 uint32_t reg, tmp;
8066
8067 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8068 with_spread = true;
8069 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8070 with_fdi, "LP PCH doesn't have FDI\n"))
8071 with_fdi = false;
f31f2d55
PZ		 8072
8073 mutex_lock(&dev_priv->dpio_lock);
8074
8075 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8076 tmp &= ~SBI_SSCCTL_DISABLE;
8077 tmp |= SBI_SSCCTL_PATHALT;
8078 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8079
8080 udelay(24);
8081
2fa86a1f
PZ		 8082 if (with_spread) {
8083 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8084 tmp &= ~SBI_SSCCTL_PATHALT;
8085 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8086
2fa86a1f
PZ		 8087 if (with_fdi) {
8088 lpt_reset_fdi_mphy(dev_priv);
8089 lpt_program_fdi_mphy(dev_priv);
8090 }
8091 }
dde86e2d 8092
2fa86a1f
PZ		 8093 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8094 SBI_GEN0 : SBI_DBUFF0;
8095 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8096 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8097 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 8098
8099 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 8100}
8101
47701c3b
PZ		 8102/* Sequence to disable CLKOUT_DP */
8103static void lpt_disable_clkout_dp(struct drm_device *dev)
8104{
8105 struct drm_i915_private *dev_priv = dev->dev_private;
8106 uint32_t reg, tmp;
8107
8108 mutex_lock(&dev_priv->dpio_lock);
8109
8110 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8111 SBI_GEN0 : SBI_DBUFF0;
8112 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8113 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8114 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8115
8116 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8117 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8118 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8119 tmp |= SBI_SSCCTL_PATHALT;
8120 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8121 udelay(32);
8122 }
8123 tmp |= SBI_SSCCTL_DISABLE;
8124 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8125 }
8126
8127 mutex_unlock(&dev_priv->dpio_lock);
8128}
8129
bf8fa3d3
PZ		 8130static void lpt_init_pch_refclk(struct drm_device *dev)
8131{
bf8fa3d3
PZ		 8132 struct intel_encoder *encoder;
8133 bool has_vga = false;
8134
b2784e15 8135 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8136 switch (encoder->type) {
8137 case INTEL_OUTPUT_ANALOG:
8138 has_vga = true;
8139 break;
6847d71b
PZ		 8140 default:
8141 break;
bf8fa3d3
PZ		 8142 }
8143 }
8144
47701c3b
PZ		 8145 if (has_vga)
8146 lpt_enable_clkout_dp(dev, true, true);
8147 else
8148 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8149}
8150
dde86e2d
PZ		 8151/*
8152 * Initialize reference clocks when the driver loads
8153 */
8154void intel_init_pch_refclk(struct drm_device *dev)
8155{
8156 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8157 ironlake_init_pch_refclk(dev);
8158 else if (HAS_PCH_LPT(dev))
8159 lpt_init_pch_refclk(dev);
8160}
8161
55bb9992 8162static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8163{
55bb9992 8164 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8165 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8166 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8167 struct drm_connector *connector;
55bb9992 8168 struct drm_connector_state *connector_state;
d9d444cb 8169 struct intel_encoder *encoder;
55bb9992 8170 int num_connectors = 0, i;
d9d444cb
JB		 8171 bool is_lvds = false;
8172
da3ced29 8173 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8174 if (connector_state->crtc != crtc_state->base.crtc)
8175 continue;
8176
8177 encoder = to_intel_encoder(connector_state->best_encoder);
8178
d9d444cb
JB		 8179 switch (encoder->type) {
8180 case INTEL_OUTPUT_LVDS:
8181 is_lvds = true;
8182 break;
6847d71b
PZ		 8183 default:
8184 break;
d9d444cb
JB		 8185 }
8186 num_connectors++;
8187 }
8188
8189 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8190 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8191 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8192 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8193 }
8194
8195 return 120000;
8196}
8197
6ff93609 8198static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8199{
c8203565 8200 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8202 int pipe = intel_crtc->pipe;
c8203565
PZ		 8203 uint32_t val;
8204
78114071 8205 val = 0;
c8203565 8206
6e3c9717 8207 switch (intel_crtc->config->pipe_bpp) {
c8203565 8208 case 18:
dfd07d72 8209 val |= PIPECONF_6BPC;
c8203565
PZ		 8210 break;
8211 case 24:
dfd07d72 8212 val |= PIPECONF_8BPC;
c8203565
PZ		 8213 break;
8214 case 30:
dfd07d72 8215 val |= PIPECONF_10BPC;
c8203565
PZ		 8216 break;
8217 case 36:
dfd07d72 8218 val |= PIPECONF_12BPC;
c8203565
PZ		 8219 break;
8220 default:
cc769b62
PZ		 8221 /* Case prevented by intel_choose_pipe_bpp_dither. */
8222 BUG();
c8203565
PZ		 8223 }
8224
6e3c9717 8225 if (intel_crtc->config->dither)
c8203565
PZ		 8226 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8227
6e3c9717 8228 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8229 val |= PIPECONF_INTERLACED_ILK;
8230 else
8231 val |= PIPECONF_PROGRESSIVE;
8232
6e3c9717 8233 if (intel_crtc->config->limited_color_range)
3685a8f3 8234 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8235
c8203565
PZ		 8236 I915_WRITE(PIPECONF(pipe), val);
8237 POSTING_READ(PIPECONF(pipe));
8238}
8239
86d3efce
VS		 8240/*
8241 * Set up the pipe CSC unit.
8242 *
8243 * Currently only full range RGB to limited range RGB conversion
8244 * is supported, but eventually this should handle various
8245 * RGB<->YCbCr scenarios as well.
8246 */
50f3b016 8247static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8248{
8249 struct drm_device *dev = crtc->dev;
8250 struct drm_i915_private *dev_priv = dev->dev_private;
8251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8252 int pipe = intel_crtc->pipe;
8253 uint16_t coeff = 0x7800; /* 1.0 */
8254
8255 /*
8256 * TODO: Check what kind of values actually come out of the pipe
8257 * with these coeff/postoff values and adjust to get the best
8258 * accuracy. Perhaps we even need to take the bpc value into
8259 * consideration.
8260 */
8261
6e3c9717 8262 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8263 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8264
8265 /*
8266 * GY/GU and RY/RU should be the other way around according
8267 * to BSpec, but reality doesn't agree. Just set them up in
8268 * a way that results in the correct picture.
8269 */
8270 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8271 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8272
8273 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8274 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8275
8276 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8277 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8278
8279 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8280 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8281 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8282
8283 if (INTEL_INFO(dev)->gen > 6) {
8284 uint16_t postoff = 0;
8285
6e3c9717 8286 if (intel_crtc->config->limited_color_range)
32cf0cb0 8287 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8288
8289 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8290 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8291 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8292
8293 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8294 } else {
8295 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8296
6e3c9717 8297 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8298 mode |= CSC_BLACK_SCREEN_OFFSET;
8299
8300 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8301 }
8302}
8303
6ff93609 8304static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8305{
756f85cf
PZ		 8306 struct drm_device *dev = crtc->dev;
8307 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8309 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8310 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8311 uint32_t val;
8312
3eff4faa 8313 val = 0;
ee2b0b38 8314
6e3c9717 8315 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8316 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8317
6e3c9717 8318 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8319 val |= PIPECONF_INTERLACED_ILK;
8320 else
8321 val |= PIPECONF_PROGRESSIVE;
8322
702e7a56
PZ		 8323 I915_WRITE(PIPECONF(cpu_transcoder), val);
8324 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8325
8326 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8327 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8328
3cdf122c 8329 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8330 val = 0;
8331
6e3c9717 8332 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8333 case 18:
8334 val |= PIPEMISC_DITHER_6_BPC;
8335 break;
8336 case 24:
8337 val |= PIPEMISC_DITHER_8_BPC;
8338 break;
8339 case 30:
8340 val |= PIPEMISC_DITHER_10_BPC;
8341 break;
8342 case 36:
8343 val |= PIPEMISC_DITHER_12_BPC;
8344 break;
8345 default:
8346 /* Case prevented by pipe_config_set_bpp. */
8347 BUG();
8348 }
8349
6e3c9717 8350 if (intel_crtc->config->dither)
756f85cf
PZ		 8351 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8352
8353 I915_WRITE(PIPEMISC(pipe), val);
8354 }
ee2b0b38
PZ		 8355}
8356
6591c6e4 8357static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8358 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8359 intel_clock_t *clock,
8360 bool *has_reduced_clock,
8361 intel_clock_t *reduced_clock)
8362{
8363 struct drm_device *dev = crtc->dev;
8364 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8365 int refclk;
d4906093 8366 const intel_limit_t *limit;
a16af721 8367 bool ret, is_lvds = false;
79e53945 8368
a93e255f 8369 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8370
55bb9992 8371 refclk = ironlake_get_refclk(crtc_state);
79e53945 8372
d4906093
ML		 8373 /*
8374 * Returns a set of divisors for the desired target clock with the given
8375 * refclk, or FALSE. The returned values represent the clock equation:
8376 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8377 */
a93e255f
ACO		 8378 limit = intel_limit(crtc_state, refclk);
8379 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8380 crtc_state->port_clock,
ee9300bb 8381 refclk, NULL, clock);
6591c6e4
PZ		 8382 if (!ret)
8383 return false;
cda4b7d3 8384
ddc9003c 8385 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8386 /*
8387 * Ensure we match the reduced clock's P to the target clock.
8388 * If the clocks don't match, we can't switch the display clock
8389 * by using the FP0/FP1. In such case we will disable the LVDS
8390 * downclock feature.
8391 */
ee9300bb 8392 *has_reduced_clock =
a93e255f 8393 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8394 dev_priv->lvds_downclock,
8395 refclk, clock,
8396 reduced_clock);
652c393a 8397 }
61e9653f 8398
6591c6e4
PZ		 8399 return true;
8400}
8401
d4b1931c
PZ		 8402int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8403{
8404 /*
8405 * Account for spread spectrum to avoid
8406 * oversubscribing the link. Max center spread
8407 * is 2.5%; use 5% for safety's sake.
8408 */
8409 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8410 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8411}
8412
7429e9d4 8413static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8414{
7429e9d4 8415 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8416}
8417
de13a2e3 8418static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8419 struct intel_crtc_state *crtc_state,
7429e9d4 8420 u32 *fp,
9a7c7890 8421 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8422{
de13a2e3 8423 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8424 struct drm_device *dev = crtc->dev;
8425 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8426 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8427 struct drm_connector *connector;
55bb9992
ACO		 8428 struct drm_connector_state *connector_state;
8429 struct intel_encoder *encoder;
de13a2e3 8430 uint32_t dpll;
55bb9992 8431 int factor, num_connectors = 0, i;
09ede541 8432 bool is_lvds = false, is_sdvo = false;
79e53945 8433
da3ced29 8434 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8435 if (connector_state->crtc != crtc_state->base.crtc)
8436 continue;
8437
8438 encoder = to_intel_encoder(connector_state->best_encoder);
8439
8440 switch (encoder->type) {
79e53945
JB		 8441 case INTEL_OUTPUT_LVDS:
8442 is_lvds = true;
8443 break;
8444 case INTEL_OUTPUT_SDVO:
7d57382e 8445 case INTEL_OUTPUT_HDMI:
79e53945 8446 is_sdvo = true;
79e53945 8447 break;
6847d71b
PZ		 8448 default:
8449 break;
79e53945 8450 }
43565a06 8451
c751ce4f 8452 num_connectors++;
79e53945 8453 }
79e53945 8454
c1858123 8455 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8456 factor = 21;
8457 if (is_lvds) {
8458 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8459 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8460 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8461 factor = 25;
190f68c5 8462 } else if (crtc_state->sdvo_tv_clock)
8febb297 8463 factor = 20;
c1858123 8464
190f68c5 8465 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8466 *fp |= FP_CB_TUNE;
2c07245f 8467
9a7c7890
DV		 8468 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8469 *fp2 |= FP_CB_TUNE;
8470
5eddb70b 8471 dpll = 0;
2c07245f 8472
a07d6787
EA		 8473 if (is_lvds)
8474 dpll |= DPLLB_MODE_LVDS;
8475 else
8476 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8477
190f68c5 8478 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8479 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8480
8481 if (is_sdvo)
4a33e48d 8482 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8483 if (crtc_state->has_dp_encoder)
4a33e48d 8484 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8485
a07d6787 8486 /* compute bitmask from p1 value */
190f68c5 8487 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8488 /* also FPA1 */
190f68c5 8489 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8490
190f68c5 8491 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8492 case 5:
8493 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8494 break;
8495 case 7:
8496 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8497 break;
8498 case 10:
8499 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8500 break;
8501 case 14:
8502 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8503 break;
79e53945
JB		 8504 }
8505
b4c09f3b 8506 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8507 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8508 else
8509 dpll |= PLL_REF_INPUT_DREFCLK;
8510
959e16d6 8511 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8512}
8513
190f68c5
ACO		 8514static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8515 struct intel_crtc_state *crtc_state)
de13a2e3 8516{
c7653199 8517 struct drm_device *dev = crtc->base.dev;
de13a2e3 8518 intel_clock_t clock, reduced_clock;
cbbab5bd 8519 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8520 bool ok, has_reduced_clock = false;
8b47047b 8521 bool is_lvds = false;
e2b78267 8522 struct intel_shared_dpll *pll;
de13a2e3 8523
409ee761 8524 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8525
5dc5298b
PZ		 8526 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8527 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8528
190f68c5 8529 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8530 &has_reduced_clock, &reduced_clock);
190f68c5 8531 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8532 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8533 return -EINVAL;
79e53945 8534 }
f47709a9 8535 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8536 if (!crtc_state->clock_set) {
8537 crtc_state->dpll.n = clock.n;
8538 crtc_state->dpll.m1 = clock.m1;
8539 crtc_state->dpll.m2 = clock.m2;
8540 crtc_state->dpll.p1 = clock.p1;
8541 crtc_state->dpll.p2 = clock.p2;
f47709a9 8542 }
79e53945 8543
5dc5298b 8544 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8545 if (crtc_state->has_pch_encoder) {
8546 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8547 if (has_reduced_clock)
7429e9d4 8548 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8549
190f68c5 8550 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8551 &fp, &reduced_clock,
8552 has_reduced_clock ? &fp2 : NULL);
8553
190f68c5
ACO		 8554 crtc_state->dpll_hw_state.dpll = dpll;
8555 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8556 if (has_reduced_clock)
190f68c5 8557 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8558 else
190f68c5 8559 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8560
190f68c5 8561 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8562 if (pll == NULL) {
84f44ce7 8563 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8564 pipe_name(crtc->pipe));
4b645f14
JB		 8565 return -EINVAL;
8566 }
3fb37703 8567 }
79e53945 8568
ab585dea 8569 if (is_lvds && has_reduced_clock)
c7653199 8570 crtc->lowfreq_avail = true;
bcd644e0 8571 else
c7653199 8572 crtc->lowfreq_avail = false;
e2b78267 8573
c8f7a0db 8574 return 0;
79e53945
JB		 8575}
8576
eb14cb74
VS		 8577static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8578 struct intel_link_m_n *m_n)
8579{
8580 struct drm_device *dev = crtc->base.dev;
8581 struct drm_i915_private *dev_priv = dev->dev_private;
8582 enum pipe pipe = crtc->pipe;
8583
8584 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8585 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8586 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8587 & ~TU_SIZE_MASK;
8588 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8589 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8590 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8591}
8592
8593static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8594 enum transcoder transcoder,
b95af8be
VK		 8595 struct intel_link_m_n *m_n,
8596 struct intel_link_m_n *m2_n2)
72419203
DV		 8597{
8598 struct drm_device *dev = crtc->base.dev;
8599 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8600 enum pipe pipe = crtc->pipe;
72419203 8601
eb14cb74
VS		 8602 if (INTEL_INFO(dev)->gen >= 5) {
8603 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8604 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8605 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8606 & ~TU_SIZE_MASK;
8607 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8608 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8609 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8610 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8611 * gen < 8) and if DRRS is supported (to make sure the
8612 * registers are not unnecessarily read).
8613 */
8614 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8615 crtc->config->has_drrs) {
b95af8be
VK		 8616 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8617 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8618 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8619 & ~TU_SIZE_MASK;
8620 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8621 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8622 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8623 }
eb14cb74
VS		 8624 } else {
8625 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8626 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8627 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8628 & ~TU_SIZE_MASK;
8629 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8630 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8631 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8632 }
8633}
8634
8635void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8636 struct intel_crtc_state *pipe_config)
eb14cb74 8637{
681a8504 8638 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8639 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8640 else
8641 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8642 &pipe_config->dp_m_n,
8643 &pipe_config->dp_m2_n2);
eb14cb74 8644}
72419203 8645
eb14cb74 8646static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8647 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8648{
8649 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8650 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8651}
8652
bd2e244f 8653static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8654 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8655{
8656 struct drm_device *dev = crtc->base.dev;
8657 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8658 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8659 uint32_t ps_ctrl = 0;
8660 int id = -1;
8661 int i;
bd2e244f 8662
a1b2278e
CK		 8663 /* find scaler attached to this pipe */
8664 for (i = 0; i < crtc->num_scalers; i++) {
8665 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8666 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8667 id = i;
8668 pipe_config->pch_pfit.enabled = true;
8669 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8670 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8671 break;
8672 }
8673 }
bd2e244f 8674
a1b2278e
CK		 8675 scaler_state->scaler_id = id;
8676 if (id >= 0) {
8677 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8678 } else {
8679 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8680 }
8681}
8682
5724dbd1
DL		 8683static void
8684skylake_get_initial_plane_config(struct intel_crtc *crtc,
8685 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8686{
8687 struct drm_device *dev = crtc->base.dev;
8688 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8689 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8690 int pipe = crtc->pipe;
8691 int fourcc, pixel_format;
6761dd31 8692 unsigned int aligned_height;
bc8d7dff 8693 struct drm_framebuffer *fb;
1b842c89 8694 struct intel_framebuffer *intel_fb;
bc8d7dff 8695
d9806c9f 8696 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8697 if (!intel_fb) {
bc8d7dff
DL		 8698 DRM_DEBUG_KMS("failed to alloc fb\n");
8699 return;
8700 }
8701
1b842c89
DL		 8702 fb = &intel_fb->base;
8703
bc8d7dff 8704 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8705 if (!(val & PLANE_CTL_ENABLE))
8706 goto error;
8707
bc8d7dff
DL		 8708 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8709 fourcc = skl_format_to_fourcc(pixel_format,
8710 val & PLANE_CTL_ORDER_RGBX,
8711 val & PLANE_CTL_ALPHA_MASK);
8712 fb->pixel_format = fourcc;
8713 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8714
40f46283
DL		 8715 tiling = val & PLANE_CTL_TILED_MASK;
8716 switch (tiling) {
8717 case PLANE_CTL_TILED_LINEAR:
8718 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8719 break;
8720 case PLANE_CTL_TILED_X:
8721 plane_config->tiling = I915_TILING_X;
8722 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8723 break;
8724 case PLANE_CTL_TILED_Y:
8725 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8726 break;
8727 case PLANE_CTL_TILED_YF:
8728 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8729 break;
8730 default:
8731 MISSING_CASE(tiling);
8732 goto error;
8733 }
8734
bc8d7dff
DL		 8735 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8736 plane_config->base = base;
8737
8738 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8739
8740 val = I915_READ(PLANE_SIZE(pipe, 0));
8741 fb->height = ((val >> 16) & 0xfff) + 1;
8742 fb->width = ((val >> 0) & 0x1fff) + 1;
8743
8744 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8745 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8746 fb->pixel_format);
bc8d7dff
DL		 8747 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8748
8749 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8750 fb->pixel_format,
8751 fb->modifier[0]);
bc8d7dff 8752
f37b5c2b 8753 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8754
8755 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8756 pipe_name(pipe), fb->width, fb->height,
8757 fb->bits_per_pixel, base, fb->pitches[0],
8758 plane_config->size);
8759
2d14030b 8760 plane_config->fb = intel_fb;
bc8d7dff
DL		 8761 return;
8762
8763error:
8764 kfree(fb);
8765}
8766
2fa2fe9a 8767static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8768 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8769{
8770 struct drm_device *dev = crtc->base.dev;
8771 struct drm_i915_private *dev_priv = dev->dev_private;
8772 uint32_t tmp;
8773
8774 tmp = I915_READ(PF_CTL(crtc->pipe));
8775
8776 if (tmp & PF_ENABLE) {
fd4daa9c 8777 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8778 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8779 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8780
8781 /* We currently do not free assignements of panel fitters on
8782 * ivb/hsw (since we don't use the higher upscaling modes which
8783 * differentiates them) so just WARN about this case for now. */
8784 if (IS_GEN7(dev)) {
8785 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8786 PF_PIPE_SEL_IVB(crtc->pipe));
8787 }
2fa2fe9a 8788 }
79e53945
JB		 8789}
8790
5724dbd1
DL		 8791static void
8792ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8793 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8794{
8795 struct drm_device *dev = crtc->base.dev;
8796 struct drm_i915_private *dev_priv = dev->dev_private;
8797 u32 val, base, offset;
aeee5a49 8798 int pipe = crtc->pipe;
4c6baa59 8799 int fourcc, pixel_format;
6761dd31 8800 unsigned int aligned_height;
b113d5ee 8801 struct drm_framebuffer *fb;
1b842c89 8802 struct intel_framebuffer *intel_fb;
4c6baa59 8803
42a7b088
DL		 8804 val = I915_READ(DSPCNTR(pipe));
8805 if (!(val & DISPLAY_PLANE_ENABLE))
8806 return;
8807
d9806c9f 8808 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8809 if (!intel_fb) {
4c6baa59
JB		 8810 DRM_DEBUG_KMS("failed to alloc fb\n");
8811 return;
8812 }
8813
1b842c89
DL		 8814 fb = &intel_fb->base;
8815
18c5247e
DV		 8816 if (INTEL_INFO(dev)->gen >= 4) {
8817 if (val & DISPPLANE_TILED) {
49af449b 8818 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8819 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8820 }
8821 }
4c6baa59
JB		 8822
8823 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8824 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8825 fb->pixel_format = fourcc;
8826 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8827
aeee5a49 8828 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8829 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8830 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8831 } else {
49af449b 8832 if (plane_config->tiling)
aeee5a49 8833 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8834 else
aeee5a49 8835 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8836 }
8837 plane_config->base = base;
8838
8839 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8840 fb->width = ((val >> 16) & 0xfff) + 1;
8841 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8842
8843 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8844 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8845
b113d5ee 8846 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8847 fb->pixel_format,
8848 fb->modifier[0]);
4c6baa59 8849
f37b5c2b 8850 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8851
2844a921
DL		 8852 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8853 pipe_name(pipe), fb->width, fb->height,
8854 fb->bits_per_pixel, base, fb->pitches[0],
8855 plane_config->size);
b113d5ee 8856
2d14030b 8857 plane_config->fb = intel_fb;
4c6baa59
JB		 8858}
8859
0e8ffe1b 8860static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8861 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8862{
8863 struct drm_device *dev = crtc->base.dev;
8864 struct drm_i915_private *dev_priv = dev->dev_private;
8865 uint32_t tmp;
8866
f458ebbc
DV		 8867 if (!intel_display_power_is_enabled(dev_priv,
8868 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8869 return false;
8870
e143a21c 8871 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8872 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8873
0e8ffe1b
DV		 8874 tmp = I915_READ(PIPECONF(crtc->pipe));
8875 if (!(tmp & PIPECONF_ENABLE))
8876 return false;
8877
42571aef
VS		 8878 switch (tmp & PIPECONF_BPC_MASK) {
8879 case PIPECONF_6BPC:
8880 pipe_config->pipe_bpp = 18;
8881 break;
8882 case PIPECONF_8BPC:
8883 pipe_config->pipe_bpp = 24;
8884 break;
8885 case PIPECONF_10BPC:
8886 pipe_config->pipe_bpp = 30;
8887 break;
8888 case PIPECONF_12BPC:
8889 pipe_config->pipe_bpp = 36;
8890 break;
8891 default:
8892 break;
8893 }
8894
b5a9fa09
DV		 8895 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8896 pipe_config->limited_color_range = true;
8897
ab9412ba 8898 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8899 struct intel_shared_dpll *pll;
8900
88adfff1
DV		 8901 pipe_config->has_pch_encoder = true;
8902
627eb5a3
DV		 8903 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8904 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8905 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8906
8907 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8908
c0d43d62 8909 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8910 pipe_config->shared_dpll =
8911 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8912 } else {
8913 tmp = I915_READ(PCH_DPLL_SEL);
8914 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8915 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8916 else
8917 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8918 }
66e985c0
DV		 8919
8920 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8921
8922 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8923 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8924
8925 tmp = pipe_config->dpll_hw_state.dpll;
8926 pipe_config->pixel_multiplier =
8927 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8928 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8929
8930 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8931 } else {
8932 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8933 }
8934
1bd1bd80
DV		 8935 intel_get_pipe_timings(crtc, pipe_config);
8936
2fa2fe9a
DV		 8937 ironlake_get_pfit_config(crtc, pipe_config);
8938
0e8ffe1b
DV		 8939 return true;
8940}
8941
be256dc7
PZ		 8942static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8943{
8944 struct drm_device *dev = dev_priv->dev;
be256dc7 8945 struct intel_crtc *crtc;
be256dc7 8946
d3fcc808 8947 for_each_intel_crtc(dev, crtc)
e2c719b7 8948 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8949 pipe_name(crtc->pipe));
8950
e2c719b7
RC		 8951 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8952 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8953 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8954 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8955 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8956 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8957 "CPU PWM1 enabled\n");
c5107b87 8958 if (IS_HASWELL(dev))
e2c719b7 8959 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8960 "CPU PWM2 enabled\n");
e2c719b7 8961 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8962 "PCH PWM1 enabled\n");
e2c719b7 8963 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8964 "Utility pin enabled\n");
e2c719b7 8965 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8966
9926ada1
PZ		 8967 /*
8968 * In theory we can still leave IRQs enabled, as long as only the HPD
8969 * interrupts remain enabled. We used to check for that, but since it's
8970 * gen-specific and since we only disable LCPLL after we fully disable
8971 * the interrupts, the check below should be enough.
8972 */
e2c719b7 8973 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8974}
8975
9ccd5aeb
PZ		 8976static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8977{
8978 struct drm_device *dev = dev_priv->dev;
8979
8980 if (IS_HASWELL(dev))
8981 return I915_READ(D_COMP_HSW);
8982 else
8983 return I915_READ(D_COMP_BDW);
8984}
8985
3c4c9b81
PZ		 8986static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8987{
8988 struct drm_device *dev = dev_priv->dev;
8989
8990 if (IS_HASWELL(dev)) {
8991 mutex_lock(&dev_priv->rps.hw_lock);
8992 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8993 val))
f475dadf 8994 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8995 mutex_unlock(&dev_priv->rps.hw_lock);
8996 } else {
9ccd5aeb
PZ		 8997 I915_WRITE(D_COMP_BDW, val);
8998 POSTING_READ(D_COMP_BDW);
3c4c9b81 8999 }
be256dc7
PZ		 9000}
9001
9002/*
9003 * This function implements pieces of two sequences from BSpec:
9004 * - Sequence for display software to disable LCPLL
9005 * - Sequence for display software to allow package C8+
9006 * The steps implemented here are just the steps that actually touch the LCPLL
9007 * register. Callers should take care of disabling all the display engine
9008 * functions, doing the mode unset, fixing interrupts, etc.
9009 */
6ff58d53
PZ		 9010static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9011 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9012{
9013 uint32_t val;
9014
9015 assert_can_disable_lcpll(dev_priv);
9016
9017 val = I915_READ(LCPLL_CTL);
9018
9019 if (switch_to_fclk) {
9020 val |= LCPLL_CD_SOURCE_FCLK;
9021 I915_WRITE(LCPLL_CTL, val);
9022
9023 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9024 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9025 DRM_ERROR("Switching to FCLK failed\n");
9026
9027 val = I915_READ(LCPLL_CTL);
9028 }
9029
9030 val |= LCPLL_PLL_DISABLE;
9031 I915_WRITE(LCPLL_CTL, val);
9032 POSTING_READ(LCPLL_CTL);
9033
9034 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9035 DRM_ERROR("LCPLL still locked\n");
9036
9ccd5aeb 9037 val = hsw_read_dcomp(dev_priv);
be256dc7 9038 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9039 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9040 ndelay(100);
9041
9ccd5aeb
PZ		 9042 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9043 1))
be256dc7
PZ		 9044 DRM_ERROR("D_COMP RCOMP still in progress\n");
9045
9046 if (allow_power_down) {
9047 val = I915_READ(LCPLL_CTL);
9048 val |= LCPLL_POWER_DOWN_ALLOW;
9049 I915_WRITE(LCPLL_CTL, val);
9050 POSTING_READ(LCPLL_CTL);
9051 }
9052}
9053
9054/*
9055 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9056 * source.
9057 */
6ff58d53 9058static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9059{
9060 uint32_t val;
9061
9062 val = I915_READ(LCPLL_CTL);
9063
9064 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9065 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9066 return;
9067
a8a8bd54
PZ		 9068 /*
9069 * Make sure we're not on PC8 state before disabling PC8, otherwise
9070 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9071 */
59bad947 9072 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9073
be256dc7
PZ		 9074 if (val & LCPLL_POWER_DOWN_ALLOW) {
9075 val &= ~LCPLL_POWER_DOWN_ALLOW;
9076 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9077 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9078 }
9079
9ccd5aeb 9080 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9081 val |= D_COMP_COMP_FORCE;
9082 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9083 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9084
9085 val = I915_READ(LCPLL_CTL);
9086 val &= ~LCPLL_PLL_DISABLE;
9087 I915_WRITE(LCPLL_CTL, val);
9088
9089 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9090 DRM_ERROR("LCPLL not locked yet\n");
9091
9092 if (val & LCPLL_CD_SOURCE_FCLK) {
9093 val = I915_READ(LCPLL_CTL);
9094 val &= ~LCPLL_CD_SOURCE_FCLK;
9095 I915_WRITE(LCPLL_CTL, val);
9096
9097 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9098 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9099 DRM_ERROR("Switching back to LCPLL failed\n");
9100 }
215733fa 9101
59bad947 9102 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 9103}
9104
765dab67
PZ		 9105/*
9106 * Package states C8 and deeper are really deep PC states that can only be
9107 * reached when all the devices on the system allow it, so even if the graphics
9108 * device allows PC8+, it doesn't mean the system will actually get to these
9109 * states. Our driver only allows PC8+ when going into runtime PM.
9110 *
9111 * The requirements for PC8+ are that all the outputs are disabled, the power
9112 * well is disabled and most interrupts are disabled, and these are also
9113 * requirements for runtime PM. When these conditions are met, we manually do
9114 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9115 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9116 * hang the machine.
9117 *
9118 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9119 * the state of some registers, so when we come back from PC8+ we need to
9120 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9121 * need to take care of the registers kept by RC6. Notice that this happens even
9122 * if we don't put the device in PCI D3 state (which is what currently happens
9123 * because of the runtime PM support).
9124 *
9125 * For more, read "Display Sequences for Package C8" on the hardware
9126 * documentation.
9127 */
a14cb6fc 9128void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9129{
c67a470b
PZ		 9130 struct drm_device *dev = dev_priv->dev;
9131 uint32_t val;
9132
c67a470b
PZ		 9133 DRM_DEBUG_KMS("Enabling package C8+\n");
9134
c67a470b
PZ		 9135 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9136 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9137 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9138 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9139 }
9140
9141 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9142 hsw_disable_lcpll(dev_priv, true, true);
9143}
9144
a14cb6fc 9145void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9146{
9147 struct drm_device *dev = dev_priv->dev;
9148 uint32_t val;
9149
c67a470b
PZ		 9150 DRM_DEBUG_KMS("Disabling package C8+\n");
9151
9152 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9153 lpt_init_pch_refclk(dev);
9154
9155 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9156 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9157 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9158 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9159 }
9160
9161 intel_prepare_ddi(dev);
c67a470b
PZ		 9162}
9163
a821fc46 9164static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9165{
a821fc46 9166 struct drm_device *dev = old_state->dev;
f8437dd1 9167 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9168 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9169 int req_cdclk;
9170
9171 /* see the comment in valleyview_modeset_global_resources */
9172 if (WARN_ON(max_pixclk < 0))
9173 return;
9174
9175 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9176
9177 if (req_cdclk != dev_priv->cdclk_freq)
9178 broxton_set_cdclk(dev, req_cdclk);
9179}
9180
190f68c5
ACO		 9181static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9182 struct intel_crtc_state *crtc_state)
09b4ddf9 9183{
190f68c5 9184 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9185 return -EINVAL;
716c2e55 9186
c7653199 9187 crtc->lowfreq_avail = false;
644cef34 9188
c8f7a0db 9189 return 0;
79e53945
JB		 9190}
9191
3760b59c
S		 9192static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9193 enum port port,
9194 struct intel_crtc_state *pipe_config)
9195{
9196 switch (port) {
9197 case PORT_A:
9198 pipe_config->ddi_pll_sel = SKL_DPLL0;
9199 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9200 break;
9201 case PORT_B:
9202 pipe_config->ddi_pll_sel = SKL_DPLL1;
9203 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9204 break;
9205 case PORT_C:
9206 pipe_config->ddi_pll_sel = SKL_DPLL2;
9207 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9208 break;
9209 default:
9210 DRM_ERROR("Incorrect port type\n");
9211 }
9212}
9213
96b7dfb7
S		 9214static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9215 enum port port,
5cec258b 9216 struct intel_crtc_state *pipe_config)
96b7dfb7 9217{
3148ade7 9218 u32 temp, dpll_ctl1;
96b7dfb7
S		 9219
9220 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9221 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9222
9223 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9224 case SKL_DPLL0:
9225 /*
9226 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9227 * of the shared DPLL framework and thus needs to be read out
9228 * separately
9229 */
9230 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9231 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9232 break;
96b7dfb7
S		 9233 case SKL_DPLL1:
9234 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9235 break;
9236 case SKL_DPLL2:
9237 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9238 break;
9239 case SKL_DPLL3:
9240 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9241 break;
96b7dfb7
S		 9242 }
9243}
9244
7d2c8175
DL		 9245static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9246 enum port port,
5cec258b 9247 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9248{
9249 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9250
9251 switch (pipe_config->ddi_pll_sel) {
9252 case PORT_CLK_SEL_WRPLL1:
9253 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9254 break;
9255 case PORT_CLK_SEL_WRPLL2:
9256 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9257 break;
9258 }
9259}
9260
26804afd 9261static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9262 struct intel_crtc_state *pipe_config)
26804afd
DV		 9263{
9264 struct drm_device *dev = crtc->base.dev;
9265 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9266 struct intel_shared_dpll *pll;
26804afd
DV		 9267 enum port port;
9268 uint32_t tmp;
9269
9270 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9271
9272 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9273
96b7dfb7
S		 9274 if (IS_SKYLAKE(dev))
9275 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9276 else if (IS_BROXTON(dev))
9277 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9278 else
9279 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9280
d452c5b6
DV		 9281 if (pipe_config->shared_dpll >= 0) {
9282 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9283
9284 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9285 &pipe_config->dpll_hw_state));
9286 }
9287
26804afd
DV		 9288 /*
9289 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9290 * DDI E. So just check whether this pipe is wired to DDI E and whether
9291 * the PCH transcoder is on.
9292 */
ca370455
DL		 9293 if (INTEL_INFO(dev)->gen < 9 &&
9294 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9295 pipe_config->has_pch_encoder = true;
9296
9297 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9298 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9299 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9300
9301 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9302 }
9303}
9304
0e8ffe1b 9305static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9306 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9307{
9308 struct drm_device *dev = crtc->base.dev;
9309 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9310 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9311 uint32_t tmp;
9312
f458ebbc 9313 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9314 POWER_DOMAIN_PIPE(crtc->pipe)))
9315 return false;
9316
e143a21c 9317 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9318 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9319
eccb140b
DV		 9320 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9321 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9322 enum pipe trans_edp_pipe;
9323 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9324 default:
9325 WARN(1, "unknown pipe linked to edp transcoder\n");
9326 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9327 case TRANS_DDI_EDP_INPUT_A_ON:
9328 trans_edp_pipe = PIPE_A;
9329 break;
9330 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9331 trans_edp_pipe = PIPE_B;
9332 break;
9333 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9334 trans_edp_pipe = PIPE_C;
9335 break;
9336 }
9337
9338 if (trans_edp_pipe == crtc->pipe)
9339 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9340 }
9341
f458ebbc 9342 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9343 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9344 return false;
9345
eccb140b 9346 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9347 if (!(tmp & PIPECONF_ENABLE))
9348 return false;
9349
26804afd 9350 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9351
1bd1bd80
DV		 9352 intel_get_pipe_timings(crtc, pipe_config);
9353
a1b2278e
CK		 9354 if (INTEL_INFO(dev)->gen >= 9) {
9355 skl_init_scalers(dev, crtc, pipe_config);
9356 }
9357
2fa2fe9a 9358 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f 9359 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9360 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9361 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9362 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9363 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9364 else
9365 MISSING_CASE(INTEL_INFO(dev)->gen);
9366
a1b2278e
CK		 9367 } else {
9368 pipe_config->scaler_state.scaler_id = -1;
9369 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f 9370 }
88adfff1 9371
e59150dc
JB		 9372 if (IS_HASWELL(dev))
9373 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9374 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9375
ebb69c95
CT		 9376 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9377 pipe_config->pixel_multiplier =
9378 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9379 } else {
9380 pipe_config->pixel_multiplier = 1;
9381 }
6c49f241 9382
0e8ffe1b
DV		 9383 return true;
9384}
9385
560b85bb
CW		 9386static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9387{
9388 struct drm_device *dev = crtc->dev;
9389 struct drm_i915_private *dev_priv = dev->dev_private;
9390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9391 uint32_t cntl = 0, size = 0;
560b85bb 9392
dc41c154 9393 if (base) {
3dd512fb
MR		 9394 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9395 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9396 unsigned int stride = roundup_pow_of_two(width) * 4;
9397
9398 switch (stride) {
9399 default:
9400 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9401 width, stride);
9402 stride = 256;
9403 /* fallthrough */
9404 case 256:
9405 case 512:
9406 case 1024:
9407 case 2048:
9408 break;
4b0e333e
CW		 9409 }
9410
dc41c154
VS		 9411 cntl |= CURSOR_ENABLE |
9412 CURSOR_GAMMA_ENABLE |
9413 CURSOR_FORMAT_ARGB |
9414 CURSOR_STRIDE(stride);
9415
9416 size = (height << 12) | width;
4b0e333e 9417 }
560b85bb 9418
dc41c154
VS		 9419 if (intel_crtc->cursor_cntl != 0 &&
9420 (intel_crtc->cursor_base != base ||
9421 intel_crtc->cursor_size != size ||
9422 intel_crtc->cursor_cntl != cntl)) {
9423 /* On these chipsets we can only modify the base/size/stride
9424 * whilst the cursor is disabled.
9425 */
9426 I915_WRITE(_CURACNTR, 0);
4b0e333e 9427 POSTING_READ(_CURACNTR);
dc41c154 9428 intel_crtc->cursor_cntl = 0;
4b0e333e 9429 }
560b85bb 9430
99d1f387 9431 if (intel_crtc->cursor_base != base) {
9db4a9c7 9432 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9433 intel_crtc->cursor_base = base;
9434 }
4726e0b0 9435
dc41c154
VS		 9436 if (intel_crtc->cursor_size != size) {
9437 I915_WRITE(CURSIZE, size);
9438 intel_crtc->cursor_size = size;
4b0e333e 9439 }
560b85bb 9440
4b0e333e 9441 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9442 I915_WRITE(_CURACNTR, cntl);
9443 POSTING_READ(_CURACNTR);
4b0e333e 9444 intel_crtc->cursor_cntl = cntl;
560b85bb 9445 }
560b85bb
CW		 9446}
9447
560b85bb 9448static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9449{
9450 struct drm_device *dev = crtc->dev;
9451 struct drm_i915_private *dev_priv = dev->dev_private;
9452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9453 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9454 uint32_t cntl;
9455
9456 cntl = 0;
9457 if (base) {
9458 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9459 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9460 case 64:
9461 cntl |= CURSOR_MODE_64_ARGB_AX;
9462 break;
9463 case 128:
9464 cntl |= CURSOR_MODE_128_ARGB_AX;
9465 break;
9466 case 256:
9467 cntl |= CURSOR_MODE_256_ARGB_AX;
9468 break;
9469 default:
3dd512fb 9470 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9471 return;
65a21cd6 9472 }
4b0e333e 9473 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9474
9475 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9476 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9477 }
65a21cd6 9478
8e7d688b 9479 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9480 cntl |= CURSOR_ROTATE_180;
9481
4b0e333e
CW		 9482 if (intel_crtc->cursor_cntl != cntl) {
9483 I915_WRITE(CURCNTR(pipe), cntl);
9484 POSTING_READ(CURCNTR(pipe));
9485 intel_crtc->cursor_cntl = cntl;
65a21cd6 9486 }
4b0e333e 9487
65a21cd6 9488 /* and commit changes on next vblank */
5efb3e28
VS		 9489 I915_WRITE(CURBASE(pipe), base);
9490 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9491
9492 intel_crtc->cursor_base = base;
65a21cd6
JB		 9493}
9494
cda4b7d3 9495/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9496static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9497 bool on)
cda4b7d3
CW		 9498{
9499 struct drm_device *dev = crtc->dev;
9500 struct drm_i915_private *dev_priv = dev->dev_private;
9501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9502 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9503 int x = crtc->cursor_x;
9504 int y = crtc->cursor_y;
d6e4db15 9505 u32 base = 0, pos = 0;
cda4b7d3 9506
d6e4db15 9507 if (on)
cda4b7d3 9508 base = intel_crtc->cursor_addr;
cda4b7d3 9509
6e3c9717 9510 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9511 base = 0;
9512
6e3c9717 9513 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9514 base = 0;
9515
9516 if (x < 0) {
3dd512fb 9517 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9518 base = 0;
9519
9520 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9521 x = -x;
9522 }
9523 pos |= x << CURSOR_X_SHIFT;
9524
9525 if (y < 0) {
3dd512fb 9526 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9527 base = 0;
9528
9529 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9530 y = -y;
9531 }
9532 pos |= y << CURSOR_Y_SHIFT;
9533
4b0e333e 9534 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9535 return;
9536
5efb3e28
VS		 9537 I915_WRITE(CURPOS(pipe), pos);
9538
4398ad45
VS		 9539 /* ILK+ do this automagically */
9540 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9541 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9542 base += (intel_crtc->base.cursor->state->crtc_h *
9543 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9544 }
9545
8ac54669 9546 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9547 i845_update_cursor(crtc, base);
9548 else
9549 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9550}
9551
dc41c154
VS		 9552static bool cursor_size_ok(struct drm_device *dev,
9553 uint32_t width, uint32_t height)
9554{
9555 if (width == 0 || height == 0)
9556 return false;
9557
9558 /*
9559 * 845g/865g are special in that they are only limited by
9560 * the width of their cursors, the height is arbitrary up to
9561 * the precision of the register. Everything else requires
9562 * square cursors, limited to a few power-of-two sizes.
9563 */
9564 if (IS_845G(dev) || IS_I865G(dev)) {
9565 if ((width & 63) != 0)
9566 return false;
9567
9568 if (width > (IS_845G(dev) ? 64 : 512))
9569 return false;
9570
9571 if (height > 1023)
9572 return false;
9573 } else {
9574 switch (width | height) {
9575 case 256:
9576 case 128:
9577 if (IS_GEN2(dev))
9578 return false;
9579 case 64:
9580 break;
9581 default:
9582 return false;
9583 }
9584 }
9585
9586 return true;
9587}
9588
79e53945 9589static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9590 u16 *blue, uint32_t start, uint32_t size)
79e53945 9591{
7203425a 9592 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9594
7203425a 9595 for (i = start; i < end; i++) {
79e53945
JB		 9596 intel_crtc->lut_r[i] = red[i] >> 8;
9597 intel_crtc->lut_g[i] = green[i] >> 8;
9598 intel_crtc->lut_b[i] = blue[i] >> 8;
9599 }
9600
9601 intel_crtc_load_lut(crtc);
9602}
9603
79e53945
JB		 9604/* VESA 640x480x72Hz mode to set on the pipe */
9605static struct drm_display_mode load_detect_mode = {
9606 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9607 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9608};
9609
a8bb6818
DV		 9610struct drm_framebuffer *
9611__intel_framebuffer_create(struct drm_device *dev,
9612 struct drm_mode_fb_cmd2 *mode_cmd,
9613 struct drm_i915_gem_object *obj)
d2dff872
CW		 9614{
9615 struct intel_framebuffer *intel_fb;
9616 int ret;
9617
9618 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9619 if (!intel_fb) {
6ccb81f2 9620 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9621 return ERR_PTR(-ENOMEM);
9622 }
9623
9624 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9625 if (ret)
9626 goto err;
d2dff872
CW		 9627
9628 return &intel_fb->base;
dd4916c5 9629err:
6ccb81f2 9630 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9631 kfree(intel_fb);
9632
9633 return ERR_PTR(ret);
d2dff872
CW		 9634}
9635
b5ea642a 9636static struct drm_framebuffer *
a8bb6818
DV		 9637intel_framebuffer_create(struct drm_device *dev,
9638 struct drm_mode_fb_cmd2 *mode_cmd,
9639 struct drm_i915_gem_object *obj)
9640{
9641 struct drm_framebuffer *fb;
9642 int ret;
9643
9644 ret = i915_mutex_lock_interruptible(dev);
9645 if (ret)
9646 return ERR_PTR(ret);
9647 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9648 mutex_unlock(&dev->struct_mutex);
9649
9650 return fb;
9651}
9652
d2dff872
CW		 9653static u32
9654intel_framebuffer_pitch_for_width(int width, int bpp)
9655{
9656 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9657 return ALIGN(pitch, 64);
9658}
9659
9660static u32
9661intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9662{
9663 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9664 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9665}
9666
9667static struct drm_framebuffer *
9668intel_framebuffer_create_for_mode(struct drm_device *dev,
9669 struct drm_display_mode *mode,
9670 int depth, int bpp)
9671{
9672 struct drm_i915_gem_object *obj;
0fed39bd 9673 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9674
9675 obj = i915_gem_alloc_object(dev,
9676 intel_framebuffer_size_for_mode(mode, bpp));
9677 if (obj == NULL)
9678 return ERR_PTR(-ENOMEM);
9679
9680 mode_cmd.width = mode->hdisplay;
9681 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9682 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9683 bpp);
5ca0c34a 9684 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9685
9686 return intel_framebuffer_create(dev, &mode_cmd, obj);
9687}
9688
9689static struct drm_framebuffer *
9690mode_fits_in_fbdev(struct drm_device *dev,
9691 struct drm_display_mode *mode)
9692{
4520f53a 9693#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9694 struct drm_i915_private *dev_priv = dev->dev_private;
9695 struct drm_i915_gem_object *obj;
9696 struct drm_framebuffer *fb;
9697
4c0e5528 9698 if (!dev_priv->fbdev)
d2dff872
CW		 9699 return NULL;
9700
4c0e5528 9701 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9702 return NULL;
9703
4c0e5528
DV		 9704 obj = dev_priv->fbdev->fb->obj;
9705 BUG_ON(!obj);
9706
8bcd4553 9707 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9708 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9709 fb->bits_per_pixel))
d2dff872
CW		 9710 return NULL;
9711
01f2c773 9712 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9713 return NULL;
9714
9715 return fb;
4520f53a
DV		 9716#else
9717 return NULL;
9718#endif
d2dff872
CW		 9719}
9720
d3a40d1b
ACO		 9721static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9722 struct drm_crtc *crtc,
9723 struct drm_display_mode *mode,
9724 struct drm_framebuffer *fb,
9725 int x, int y)
9726{
9727 struct drm_plane_state *plane_state;
9728 int hdisplay, vdisplay;
9729 int ret;
9730
9731 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9732 if (IS_ERR(plane_state))
9733 return PTR_ERR(plane_state);
9734
9735 if (mode)
9736 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9737 else
9738 hdisplay = vdisplay = 0;
9739
9740 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9741 if (ret)
9742 return ret;
9743 drm_atomic_set_fb_for_plane(plane_state, fb);
9744 plane_state->crtc_x = 0;
9745 plane_state->crtc_y = 0;
9746 plane_state->crtc_w = hdisplay;
9747 plane_state->crtc_h = vdisplay;
9748 plane_state->src_x = x << 16;
9749 plane_state->src_y = y << 16;
9750 plane_state->src_w = hdisplay << 16;
9751 plane_state->src_h = vdisplay << 16;
9752
9753 return 0;
9754}
9755
d2434ab7 9756bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9757 struct drm_display_mode *mode,
51fd371b
RC		 9758 struct intel_load_detect_pipe *old,
9759 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9760{
9761 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9762 struct intel_encoder *intel_encoder =
9763 intel_attached_encoder(connector);
79e53945 9764 struct drm_crtc *possible_crtc;
4ef69c7a 9765 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9766 struct drm_crtc *crtc = NULL;
9767 struct drm_device *dev = encoder->dev;
94352cf9 9768 struct drm_framebuffer *fb;
51fd371b 9769 struct drm_mode_config *config = &dev->mode_config;
83a57153 9770 struct drm_atomic_state *state = NULL;
944b0c76 9771 struct drm_connector_state *connector_state;
4be07317 9772 struct intel_crtc_state *crtc_state;
51fd371b 9773 int ret, i = -1;
79e53945 9774
d2dff872 9775 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9776 connector->base.id, connector->name,
8e329a03 9777 encoder->base.id, encoder->name);
d2dff872 9778
51fd371b
RC		 9779retry:
9780 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9781 if (ret)
9782 goto fail_unlock;
6e9f798d 9783
79e53945
JB		 9784 /*
9785 * Algorithm gets a little messy:
7a5e4805 9786 *
79e53945
JB		 9787 * - if the connector already has an assigned crtc, use it (but make
9788 * sure it's on first)
7a5e4805 9789 *
79e53945
JB		 9790 * - try to find the first unused crtc that can drive this connector,
9791 * and use that if we find one
79e53945
JB		 9792 */
9793
9794 /* See if we already have a CRTC for this connector */
9795 if (encoder->crtc) {
9796 crtc = encoder->crtc;
8261b191 9797
51fd371b 9798 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9799 if (ret)
9800 goto fail_unlock;
9801 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9802 if (ret)
9803 goto fail_unlock;
7b24056b 9804
24218aac 9805 old->dpms_mode = connector->dpms;
8261b191
CW		 9806 old->load_detect_temp = false;
9807
9808 /* Make sure the crtc and connector are running */
24218aac
DV		 9809 if (connector->dpms != DRM_MODE_DPMS_ON)
9810 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9811
7173188d 9812 return true;
79e53945
JB		 9813 }
9814
9815 /* Find an unused one (if possible) */
70e1e0ec 9816 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9817 i++;
9818 if (!(encoder->possible_crtcs & (1 << i)))
9819 continue;
83d65738 9820 if (possible_crtc->state->enable)
a459249c
VS		 9821 continue;
9822 /* This can occur when applying the pipe A quirk on resume. */
9823 if (to_intel_crtc(possible_crtc)->new_enabled)
9824 continue;
9825
9826 crtc = possible_crtc;
9827 break;
79e53945
JB		 9828 }
9829
9830 /*
9831 * If we didn't find an unused CRTC, don't use any.
9832 */
9833 if (!crtc) {
7173188d 9834 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9835 goto fail_unlock;
79e53945
JB		 9836 }
9837
51fd371b
RC		 9838 ret = drm_modeset_lock(&crtc->mutex, ctx);
9839 if (ret)
4d02e2de
DV		 9840 goto fail_unlock;
9841 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9842 if (ret)
51fd371b 9843 goto fail_unlock;
fc303101
DV		 9844 intel_encoder->new_crtc = to_intel_crtc(crtc);
9845 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9846
9847 intel_crtc = to_intel_crtc(crtc);
412b61d8 9848 intel_crtc->new_enabled = true;
24218aac 9849 old->dpms_mode = connector->dpms;
8261b191 9850 old->load_detect_temp = true;
d2dff872 9851 old->release_fb = NULL;
79e53945 9852
83a57153
ACO		 9853 state = drm_atomic_state_alloc(dev);
9854 if (!state)
9855 return false;
9856
9857 state->acquire_ctx = ctx;
9858
944b0c76
ACO		 9859 connector_state = drm_atomic_get_connector_state(state, connector);
9860 if (IS_ERR(connector_state)) {
9861 ret = PTR_ERR(connector_state);
9862 goto fail;
9863 }
9864
9865 connector_state->crtc = crtc;
9866 connector_state->best_encoder = &intel_encoder->base;
9867
4be07317
ACO		 9868 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9869 if (IS_ERR(crtc_state)) {
9870 ret = PTR_ERR(crtc_state);
9871 goto fail;
9872 }
9873
49d6fa21 9874 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 9875
6492711d
CW		 9876 if (!mode)
9877 mode = &load_detect_mode;
79e53945 9878
d2dff872
CW		 9879 /* We need a framebuffer large enough to accommodate all accesses
9880 * that the plane may generate whilst we perform load detection.
9881 * We can not rely on the fbcon either being present (we get called
9882 * during its initialisation to detect all boot displays, or it may
9883 * not even exist) or that it is large enough to satisfy the
9884 * requested mode.
9885 */
94352cf9
DV		 9886 fb = mode_fits_in_fbdev(dev, mode);
9887 if (fb == NULL) {
d2dff872 9888 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9889 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9890 old->release_fb = fb;
d2dff872
CW		 9891 } else
9892 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9893 if (IS_ERR(fb)) {
d2dff872 9894 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9895 goto fail;
79e53945 9896 }
79e53945 9897
d3a40d1b
ACO		 9898 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9899 if (ret)
9900 goto fail;
9901
8c7b5ccb
ACO		 9902 drm_mode_copy(&crtc_state->base.mode, mode);
9903
9904 if (intel_set_mode(crtc, state)) {
6492711d 9905 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9906 if (old->release_fb)
9907 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9908 goto fail;
79e53945 9909 }
9128b040 9910 crtc->primary->crtc = crtc;
7173188d 9911
79e53945 9912 /* let the connector get through one full cycle before testing */
9d0498a2 9913 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9914 return true;
412b61d8
VS		 9915
9916 fail:
83d65738 9917 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9918fail_unlock:
e5d958ef
ACO		 9919 drm_atomic_state_free(state);
9920 state = NULL;
83a57153 9921
51fd371b
RC		 9922 if (ret == -EDEADLK) {
9923 drm_modeset_backoff(ctx);
9924 goto retry;
9925 }
9926
412b61d8 9927 return false;
79e53945
JB		 9928}
9929
d2434ab7 9930void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9931 struct intel_load_detect_pipe *old,
9932 struct drm_modeset_acquire_ctx *ctx)
79e53945 9933{
83a57153 9934 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9935 struct intel_encoder *intel_encoder =
9936 intel_attached_encoder(connector);
4ef69c7a 9937 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9938 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9940 struct drm_atomic_state *state;
944b0c76 9941 struct drm_connector_state *connector_state;
4be07317 9942 struct intel_crtc_state *crtc_state;
d3a40d1b 9943 int ret;
79e53945 9944
d2dff872 9945 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9946 connector->base.id, connector->name,
8e329a03 9947 encoder->base.id, encoder->name);
d2dff872 9948
8261b191 9949 if (old->load_detect_temp) {
83a57153 9950 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9951 if (!state)
9952 goto fail;
83a57153
ACO		 9953
9954 state->acquire_ctx = ctx;
9955
944b0c76
ACO		 9956 connector_state = drm_atomic_get_connector_state(state, connector);
9957 if (IS_ERR(connector_state))
9958 goto fail;
9959
4be07317
ACO		 9960 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9961 if (IS_ERR(crtc_state))
9962 goto fail;
9963
fc303101
DV		 9964 to_intel_connector(connector)->new_encoder = NULL;
9965 intel_encoder->new_crtc = NULL;
412b61d8 9966 intel_crtc->new_enabled = false;
944b0c76
ACO		 9967
9968 connector_state->best_encoder = NULL;
9969 connector_state->crtc = NULL;
9970
49d6fa21 9971 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 9972
d3a40d1b
ACO		 9973 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9974 0, 0);
9975 if (ret)
9976 goto fail;
9977
2bfb4627
ACO		 9978 ret = intel_set_mode(crtc, state);
9979 if (ret)
9980 goto fail;
d2dff872 9981
36206361
DV		 9982 if (old->release_fb) {
9983 drm_framebuffer_unregister_private(old->release_fb);
9984 drm_framebuffer_unreference(old->release_fb);
9985 }
d2dff872 9986
0622a53c 9987 return;
79e53945
JB		 9988 }
9989
c751ce4f 9990 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9991 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9992 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9993
9994 return;
9995fail:
9996 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9997 drm_atomic_state_free(state);
79e53945
JB		 9998}
9999
da4a1efa 10000static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10001 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10002{
10003 struct drm_i915_private *dev_priv = dev->dev_private;
10004 u32 dpll = pipe_config->dpll_hw_state.dpll;
10005
10006 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10007 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10008 else if (HAS_PCH_SPLIT(dev))
10009 return 120000;
10010 else if (!IS_GEN2(dev))
10011 return 96000;
10012 else
10013 return 48000;
10014}
10015
79e53945 10016/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10017static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10018 struct intel_crtc_state *pipe_config)
79e53945 10019{
f1f644dc 10020 struct drm_device *dev = crtc->base.dev;
79e53945 10021 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10022 int pipe = pipe_config->cpu_transcoder;
293623f7 10023 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10024 u32 fp;
10025 intel_clock_t clock;
da4a1efa 10026 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10027
10028 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10029 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10030 else
293623f7 10031 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10032
10033 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10034 if (IS_PINEVIEW(dev)) {
10035 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10036 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10037 } else {
10038 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10039 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10040 }
10041
a6c45cf0 10042 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10043 if (IS_PINEVIEW(dev))
10044 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10045 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10046 else
10047 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10048 DPLL_FPA01_P1_POST_DIV_SHIFT);
10049
10050 switch (dpll & DPLL_MODE_MASK) {
10051 case DPLLB_MODE_DAC_SERIAL:
10052 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10053 5 : 10;
10054 break;
10055 case DPLLB_MODE_LVDS:
10056 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10057 7 : 14;
10058 break;
10059 default:
28c97730 10060 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10061 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10062 return;
79e53945
JB		 10063 }
10064
ac58c3f0 10065 if (IS_PINEVIEW(dev))
da4a1efa 10066 pineview_clock(refclk, &clock);
ac58c3f0 10067 else
da4a1efa 10068 i9xx_clock(refclk, &clock);
79e53945 10069 } else {
0fb58223 10070 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10071 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10072
10073 if (is_lvds) {
10074 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10075 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10076
10077 if (lvds & LVDS_CLKB_POWER_UP)
10078 clock.p2 = 7;
10079 else
10080 clock.p2 = 14;
79e53945
JB		 10081 } else {
10082 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10083 clock.p1 = 2;
10084 else {
10085 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10086 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10087 }
10088 if (dpll & PLL_P2_DIVIDE_BY_4)
10089 clock.p2 = 4;
10090 else
10091 clock.p2 = 2;
79e53945 10092 }
da4a1efa
VS		 10093
10094 i9xx_clock(refclk, &clock);
79e53945
JB		 10095 }
10096
18442d08
VS		 10097 /*
10098 * This value includes pixel_multiplier. We will use
241bfc38 10099 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10100 * encoder's get_config() function.
10101 */
10102 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10103}
10104
6878da05
VS		 10105int intel_dotclock_calculate(int link_freq,
10106 const struct intel_link_m_n *m_n)
f1f644dc 10107{
f1f644dc
JB		 10108 /*
10109 * The calculation for the data clock is:
1041a02f 10110 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10111 * But we want to avoid losing precison if possible, so:
1041a02f 10112 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10113 *
10114 * and the link clock is simpler:
1041a02f 10115 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10116 */
10117
6878da05
VS		 10118 if (!m_n->link_n)
10119 return 0;
f1f644dc 10120
6878da05
VS		 10121 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10122}
f1f644dc 10123
18442d08 10124static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10125 struct intel_crtc_state *pipe_config)
6878da05
VS		 10126{
10127 struct drm_device *dev = crtc->base.dev;
79e53945 10128
18442d08
VS		 10129 /* read out port_clock from the DPLL */
10130 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10131
f1f644dc 10132 /*
18442d08 10133 * This value does not include pixel_multiplier.
241bfc38 10134 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10135 * agree once we know their relationship in the encoder's
10136 * get_config() function.
79e53945 10137 */
2d112de7 10138 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10139 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10140 &pipe_config->fdi_m_n);
79e53945
JB		 10141}
10142
10143/** Returns the currently programmed mode of the given pipe. */
10144struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10145 struct drm_crtc *crtc)
10146{
548f245b 10147 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10149 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10150 struct drm_display_mode *mode;
5cec258b 10151 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10152 int htot = I915_READ(HTOTAL(cpu_transcoder));
10153 int hsync = I915_READ(HSYNC(cpu_transcoder));
10154 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10155 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10156 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10157
10158 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10159 if (!mode)
10160 return NULL;
10161
f1f644dc
JB		 10162 /*
10163 * Construct a pipe_config sufficient for getting the clock info
10164 * back out of crtc_clock_get.
10165 *
10166 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10167 * to use a real value here instead.
10168 */
293623f7 10169 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10170 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10171 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10172 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10173 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10174 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10175
773ae034 10176 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10177 mode->hdisplay = (htot & 0xffff) + 1;
10178 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10179 mode->hsync_start = (hsync & 0xffff) + 1;
10180 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10181 mode->vdisplay = (vtot & 0xffff) + 1;
10182 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10183 mode->vsync_start = (vsync & 0xffff) + 1;
10184 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10185
10186 drm_mode_set_name(mode);
79e53945
JB		 10187
10188 return mode;
10189}
10190
652c393a
JB		 10191static void intel_decrease_pllclock(struct drm_crtc *crtc)
10192{
10193 struct drm_device *dev = crtc->dev;
fbee40df 10194 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10196
baff296c 10197 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10198 return;
10199
10200 if (!dev_priv->lvds_downclock_avail)
10201 return;
10202
10203 /*
10204 * Since this is called by a timer, we should never get here in
10205 * the manual case.
10206 */
10207 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10208 int pipe = intel_crtc->pipe;
10209 int dpll_reg = DPLL(pipe);
10210 int dpll;
f6e5b160 10211
44d98a61 10212 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10213
8ac5a6d5 10214 assert_panel_unlocked(dev_priv, pipe);
652c393a 10215
dc257cf1 10216 dpll = I915_READ(dpll_reg);
652c393a
JB		 10217 dpll |= DISPLAY_RATE_SELECT_FPA1;
10218 I915_WRITE(dpll_reg, dpll);
9d0498a2 10219 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10220 dpll = I915_READ(dpll_reg);
10221 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10222 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10223 }
10224
10225}
10226
f047e395
CW		 10227void intel_mark_busy(struct drm_device *dev)
10228{
c67a470b
PZ		 10229 struct drm_i915_private *dev_priv = dev->dev_private;
10230
f62a0076
CW		 10231 if (dev_priv->mm.busy)
10232 return;
10233
43694d69 10234 intel_runtime_pm_get(dev_priv);
c67a470b 10235 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10236 if (INTEL_INFO(dev)->gen >= 6)
10237 gen6_rps_busy(dev_priv);
f62a0076 10238 dev_priv->mm.busy = true;
f047e395
CW		 10239}
10240
10241void intel_mark_idle(struct drm_device *dev)
652c393a 10242{
c67a470b 10243 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10244 struct drm_crtc *crtc;
652c393a 10245
f62a0076
CW		 10246 if (!dev_priv->mm.busy)
10247 return;
10248
10249 dev_priv->mm.busy = false;
10250
70e1e0ec 10251 for_each_crtc(dev, crtc) {
f4510a27 10252 if (!crtc->primary->fb)
652c393a
JB		 10253 continue;
10254
725a5b54 10255 intel_decrease_pllclock(crtc);
652c393a 10256 }
b29c19b6 10257
3d13ef2e 10258 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10259 gen6_rps_idle(dev->dev_private);
bb4cdd53 10260
43694d69 10261 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10262}
10263
79e53945
JB		 10264static void intel_crtc_destroy(struct drm_crtc *crtc)
10265{
10266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10267 struct drm_device *dev = crtc->dev;
10268 struct intel_unpin_work *work;
67e77c5a 10269
5e2d7afc 10270 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10271 work = intel_crtc->unpin_work;
10272 intel_crtc->unpin_work = NULL;
5e2d7afc 10273 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10274
10275 if (work) {
10276 cancel_work_sync(&work->work);
10277 kfree(work);
10278 }
79e53945
JB		 10279
10280 drm_crtc_cleanup(crtc);
67e77c5a 10281
79e53945
JB		 10282 kfree(intel_crtc);
10283}
10284
6b95a207
KH		 10285static void intel_unpin_work_fn(struct work_struct *__work)
10286{
10287 struct intel_unpin_work *work =
10288 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10289 struct drm_device *dev = work->crtc->dev;
f99d7069 10290 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10291
b4a98e57 10292 mutex_lock(&dev->struct_mutex);
82bc3b2d 10293 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10294 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10295
7ff0ebcc 10296 intel_fbc_update(dev);
f06cc1b9
JH		 10297
10298 if (work->flip_queued_req)
146d84f0 10299 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10300 mutex_unlock(&dev->struct_mutex);
10301
f99d7069 10302 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10303 drm_framebuffer_unreference(work->old_fb);
f99d7069 10304
b4a98e57
CW		 10305 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10306 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10307
6b95a207
KH		 10308 kfree(work);
10309}
10310
1afe3e9d 10311static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10312 struct drm_crtc *crtc)
6b95a207 10313{
6b95a207
KH		 10314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10315 struct intel_unpin_work *work;
6b95a207
KH		 10316 unsigned long flags;
10317
10318 /* Ignore early vblank irqs */
10319 if (intel_crtc == NULL)
10320 return;
10321
f326038a
DV		 10322 /*
10323 * This is called both by irq handlers and the reset code (to complete
10324 * lost pageflips) so needs the full irqsave spinlocks.
10325 */
6b95a207
KH		 10326 spin_lock_irqsave(&dev->event_lock, flags);
10327 work = intel_crtc->unpin_work;
e7d841ca
CW		 10328
10329 /* Ensure we don't miss a work->pending update ... */
10330 smp_rmb();
10331
10332 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10333 spin_unlock_irqrestore(&dev->event_lock, flags);
10334 return;
10335 }
10336
d6bbafa1 10337 page_flip_completed(intel_crtc);
0af7e4df 10338
6b95a207 10339 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10340}
10341
1afe3e9d
JB		 10342void intel_finish_page_flip(struct drm_device *dev, int pipe)
10343{
fbee40df 10344 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10345 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10346
49b14a5c 10347 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10348}
10349
10350void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10351{
fbee40df 10352 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10353 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10354
49b14a5c 10355 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10356}
10357
75f7f3ec
VS		 10358/* Is 'a' after or equal to 'b'? */
10359static bool g4x_flip_count_after_eq(u32 a, u32 b)
10360{
10361 return !((a - b) & 0x80000000);
10362}
10363
10364static bool page_flip_finished(struct intel_crtc *crtc)
10365{
10366 struct drm_device *dev = crtc->base.dev;
10367 struct drm_i915_private *dev_priv = dev->dev_private;
10368
bdfa7542
VS		 10369 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10370 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10371 return true;
10372
75f7f3ec
VS		 10373 /*
10374 * The relevant registers doen't exist on pre-ctg.
10375 * As the flip done interrupt doesn't trigger for mmio
10376 * flips on gmch platforms, a flip count check isn't
10377 * really needed there. But since ctg has the registers,
10378 * include it in the check anyway.
10379 */
10380 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10381 return true;
10382
10383 /*
10384 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10385 * used the same base address. In that case the mmio flip might
10386 * have completed, but the CS hasn't even executed the flip yet.
10387 *
10388 * A flip count check isn't enough as the CS might have updated
10389 * the base address just after start of vblank, but before we
10390 * managed to process the interrupt. This means we'd complete the
10391 * CS flip too soon.
10392 *
10393 * Combining both checks should get us a good enough result. It may
10394 * still happen that the CS flip has been executed, but has not
10395 * yet actually completed. But in case the base address is the same
10396 * anyway, we don't really care.
10397 */
10398 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10399 crtc->unpin_work->gtt_offset &&
10400 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10401 crtc->unpin_work->flip_count);
10402}
10403
6b95a207
KH		 10404void intel_prepare_page_flip(struct drm_device *dev, int plane)
10405{
fbee40df 10406 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10407 struct intel_crtc *intel_crtc =
10408 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10409 unsigned long flags;
10410
f326038a
DV		 10411
10412 /*
10413 * This is called both by irq handlers and the reset code (to complete
10414 * lost pageflips) so needs the full irqsave spinlocks.
10415 *
10416 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10417 * generate a page-flip completion irq, i.e. every modeset
10418 * is also accompanied by a spurious intel_prepare_page_flip().
10419 */
6b95a207 10420 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10421 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10422 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10423 spin_unlock_irqrestore(&dev->event_lock, flags);
10424}
10425
eba905b2 10426static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10427{
10428 /* Ensure that the work item is consistent when activating it ... */
10429 smp_wmb();
10430 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10431 /* and that it is marked active as soon as the irq could fire. */
10432 smp_wmb();
10433}
10434
8c9f3aaf
JB		 10435static int intel_gen2_queue_flip(struct drm_device *dev,
10436 struct drm_crtc *crtc,
10437 struct drm_framebuffer *fb,
ed8d1975 10438 struct drm_i915_gem_object *obj,
a4872ba6 10439 struct intel_engine_cs *ring,
ed8d1975 10440 uint32_t flags)
8c9f3aaf 10441{
8c9f3aaf 10442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10443 u32 flip_mask;
10444 int ret;
10445
6d90c952 10446 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10447 if (ret)
4fa62c89 10448 return ret;
8c9f3aaf
JB		 10449
10450 /* Can't queue multiple flips, so wait for the previous
10451 * one to finish before executing the next.
10452 */
10453 if (intel_crtc->plane)
10454 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10455 else
10456 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10457 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10458 intel_ring_emit(ring, MI_NOOP);
10459 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10460 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10461 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10462 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10463 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10464
10465 intel_mark_page_flip_active(intel_crtc);
09246732 10466 __intel_ring_advance(ring);
83d4092b 10467 return 0;
8c9f3aaf
JB		 10468}
10469
10470static int intel_gen3_queue_flip(struct drm_device *dev,
10471 struct drm_crtc *crtc,
10472 struct drm_framebuffer *fb,
ed8d1975 10473 struct drm_i915_gem_object *obj,
a4872ba6 10474 struct intel_engine_cs *ring,
ed8d1975 10475 uint32_t flags)
8c9f3aaf 10476{
8c9f3aaf 10477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10478 u32 flip_mask;
10479 int ret;
10480
6d90c952 10481 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10482 if (ret)
4fa62c89 10483 return ret;
8c9f3aaf
JB		 10484
10485 if (intel_crtc->plane)
10486 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10487 else
10488 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10489 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10490 intel_ring_emit(ring, MI_NOOP);
10491 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10492 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10493 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10494 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10495 intel_ring_emit(ring, MI_NOOP);
10496
e7d841ca 10497 intel_mark_page_flip_active(intel_crtc);
09246732 10498 __intel_ring_advance(ring);
83d4092b 10499 return 0;
8c9f3aaf
JB		 10500}
10501
10502static int intel_gen4_queue_flip(struct drm_device *dev,
10503 struct drm_crtc *crtc,
10504 struct drm_framebuffer *fb,
ed8d1975 10505 struct drm_i915_gem_object *obj,
a4872ba6 10506 struct intel_engine_cs *ring,
ed8d1975 10507 uint32_t flags)
8c9f3aaf
JB		 10508{
10509 struct drm_i915_private *dev_priv = dev->dev_private;
10510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10511 uint32_t pf, pipesrc;
10512 int ret;
10513
6d90c952 10514 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10515 if (ret)
4fa62c89 10516 return ret;
8c9f3aaf
JB		 10517
10518 /* i965+ uses the linear or tiled offsets from the
10519 * Display Registers (which do not change across a page-flip)
10520 * so we need only reprogram the base address.
10521 */
6d90c952
DV		 10522 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10523 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10524 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10525 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10526 obj->tiling_mode);
8c9f3aaf
JB		 10527
10528 /* XXX Enabling the panel-fitter across page-flip is so far
10529 * untested on non-native modes, so ignore it for now.
10530 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10531 */
10532 pf = 0;
10533 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10534 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10535
10536 intel_mark_page_flip_active(intel_crtc);
09246732 10537 __intel_ring_advance(ring);
83d4092b 10538 return 0;
8c9f3aaf
JB		 10539}
10540
10541static int intel_gen6_queue_flip(struct drm_device *dev,
10542 struct drm_crtc *crtc,
10543 struct drm_framebuffer *fb,
ed8d1975 10544 struct drm_i915_gem_object *obj,
a4872ba6 10545 struct intel_engine_cs *ring,
ed8d1975 10546 uint32_t flags)
8c9f3aaf
JB		 10547{
10548 struct drm_i915_private *dev_priv = dev->dev_private;
10549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10550 uint32_t pf, pipesrc;
10551 int ret;
10552
6d90c952 10553 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10554 if (ret)
4fa62c89 10555 return ret;
8c9f3aaf 10556
6d90c952
DV		 10557 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10558 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10559 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10560 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10561
dc257cf1
DV		 10562 /* Contrary to the suggestions in the documentation,
10563 * "Enable Panel Fitter" does not seem to be required when page
10564 * flipping with a non-native mode, and worse causes a normal
10565 * modeset to fail.
10566 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10567 */
10568 pf = 0;
8c9f3aaf 10569 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10570 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10571
10572 intel_mark_page_flip_active(intel_crtc);
09246732 10573 __intel_ring_advance(ring);
83d4092b 10574 return 0;
8c9f3aaf
JB		 10575}
10576
7c9017e5
JB		 10577static int intel_gen7_queue_flip(struct drm_device *dev,
10578 struct drm_crtc *crtc,
10579 struct drm_framebuffer *fb,
ed8d1975 10580 struct drm_i915_gem_object *obj,
a4872ba6 10581 struct intel_engine_cs *ring,
ed8d1975 10582 uint32_t flags)
7c9017e5 10583{
7c9017e5 10584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10585 uint32_t plane_bit = 0;
ffe74d75
CW		 10586 int len, ret;
10587
eba905b2 10588 switch (intel_crtc->plane) {
cb05d8de
DV		 10589 case PLANE_A:
10590 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10591 break;
10592 case PLANE_B:
10593 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10594 break;
10595 case PLANE_C:
10596 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10597 break;
10598 default:
10599 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10600 return -ENODEV;
cb05d8de
DV		 10601 }
10602
ffe74d75 10603 len = 4;
f476828a 10604 if (ring->id == RCS) {
ffe74d75 10605 len += 6;
f476828a
DL		 10606 /*
10607 * On Gen 8, SRM is now taking an extra dword to accommodate
10608 * 48bits addresses, and we need a NOOP for the batch size to
10609 * stay even.
10610 */
10611 if (IS_GEN8(dev))
10612 len += 2;
10613 }
ffe74d75 10614
f66fab8e
VS		 10615 /*
10616 * BSpec MI_DISPLAY_FLIP for IVB:
10617 * "The full packet must be contained within the same cache line."
10618 *
10619 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10620 * cacheline, if we ever start emitting more commands before
10621 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10622 * then do the cacheline alignment, and finally emit the
10623 * MI_DISPLAY_FLIP.
10624 */
10625 ret = intel_ring_cacheline_align(ring);
10626 if (ret)
4fa62c89 10627 return ret;
f66fab8e 10628
ffe74d75 10629 ret = intel_ring_begin(ring, len);
7c9017e5 10630 if (ret)
4fa62c89 10631 return ret;
7c9017e5 10632
ffe74d75
CW		 10633 /* Unmask the flip-done completion message. Note that the bspec says that
10634 * we should do this for both the BCS and RCS, and that we must not unmask
10635 * more than one flip event at any time (or ensure that one flip message
10636 * can be sent by waiting for flip-done prior to queueing new flips).
10637 * Experimentation says that BCS works despite DERRMR masking all
10638 * flip-done completion events and that unmasking all planes at once
10639 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10640 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10641 */
10642 if (ring->id == RCS) {
10643 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10644 intel_ring_emit(ring, DERRMR);
10645 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10646 DERRMR_PIPEB_PRI_FLIP_DONE |
10647 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10648 if (IS_GEN8(dev))
10649 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10650 MI_SRM_LRM_GLOBAL_GTT);
10651 else
10652 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10653 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10654 intel_ring_emit(ring, DERRMR);
10655 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10656 if (IS_GEN8(dev)) {
10657 intel_ring_emit(ring, 0);
10658 intel_ring_emit(ring, MI_NOOP);
10659 }
ffe74d75
CW		 10660 }
10661
cb05d8de 10662 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10663 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10664 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10665 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10666
10667 intel_mark_page_flip_active(intel_crtc);
09246732 10668 __intel_ring_advance(ring);
83d4092b 10669 return 0;
7c9017e5
JB		 10670}
10671
84c33a64
SG		 10672static bool use_mmio_flip(struct intel_engine_cs *ring,
10673 struct drm_i915_gem_object *obj)
10674{
10675 /*
10676 * This is not being used for older platforms, because
10677 * non-availability of flip done interrupt forces us to use
10678 * CS flips. Older platforms derive flip done using some clever
10679 * tricks involving the flip_pending status bits and vblank irqs.
10680 * So using MMIO flips there would disrupt this mechanism.
10681 */
10682
8e09bf83
CW		 10683 if (ring == NULL)
10684 return true;
10685
84c33a64
SG		 10686 if (INTEL_INFO(ring->dev)->gen < 5)
10687 return false;
10688
10689 if (i915.use_mmio_flip < 0)
10690 return false;
10691 else if (i915.use_mmio_flip > 0)
10692 return true;
14bf993e
OM		 10693 else if (i915.enable_execlists)
10694 return true;
84c33a64 10695 else
41c52415 10696 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10697}
10698
ff944564
DL		 10699static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10700{
10701 struct drm_device *dev = intel_crtc->base.dev;
10702 struct drm_i915_private *dev_priv = dev->dev_private;
10703 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 10704 const enum pipe pipe = intel_crtc->pipe;
10705 u32 ctl, stride;
10706
10707 ctl = I915_READ(PLANE_CTL(pipe, 0));
10708 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 10709 switch (fb->modifier[0]) {
10710 case DRM_FORMAT_MOD_NONE:
10711 break;
10712 case I915_FORMAT_MOD_X_TILED:
ff944564 10713 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 10714 break;
10715 case I915_FORMAT_MOD_Y_TILED:
10716 ctl |= PLANE_CTL_TILED_Y;
10717 break;
10718 case I915_FORMAT_MOD_Yf_TILED:
10719 ctl |= PLANE_CTL_TILED_YF;
10720 break;
10721 default:
10722 MISSING_CASE(fb->modifier[0]);
10723 }
ff944564
DL		 10724
10725 /*
10726 * The stride is either expressed as a multiple of 64 bytes chunks for
10727 * linear buffers or in number of tiles for tiled buffers.
10728 */
2ebef630
TU		 10729 stride = fb->pitches[0] /
10730 intel_fb_stride_alignment(dev, fb->modifier[0],
10731 fb->pixel_format);
ff944564
DL		 10732
10733 /*
10734 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10735 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10736 */
10737 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10738 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10739
10740 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10741 POSTING_READ(PLANE_SURF(pipe, 0));
10742}
10743
10744static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10745{
10746 struct drm_device *dev = intel_crtc->base.dev;
10747 struct drm_i915_private *dev_priv = dev->dev_private;
10748 struct intel_framebuffer *intel_fb =
10749 to_intel_framebuffer(intel_crtc->base.primary->fb);
10750 struct drm_i915_gem_object *obj = intel_fb->obj;
10751 u32 dspcntr;
10752 u32 reg;
10753
84c33a64
SG		 10754 reg = DSPCNTR(intel_crtc->plane);
10755 dspcntr = I915_READ(reg);
10756
c5d97472
DL		 10757 if (obj->tiling_mode != I915_TILING_NONE)
10758 dspcntr |= DISPPLANE_TILED;
10759 else
10760 dspcntr &= ~DISPPLANE_TILED;
10761
84c33a64
SG		 10762 I915_WRITE(reg, dspcntr);
10763
10764 I915_WRITE(DSPSURF(intel_crtc->plane),
10765 intel_crtc->unpin_work->gtt_offset);
10766 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10767
ff944564
DL		 10768}
10769
10770/*
10771 * XXX: This is the temporary way to update the plane registers until we get
10772 * around to using the usual plane update functions for MMIO flips
10773 */
10774static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10775{
10776 struct drm_device *dev = intel_crtc->base.dev;
10777 bool atomic_update;
10778 u32 start_vbl_count;
10779
10780 intel_mark_page_flip_active(intel_crtc);
10781
10782 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10783
10784 if (INTEL_INFO(dev)->gen >= 9)
10785 skl_do_mmio_flip(intel_crtc);
10786 else
10787 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10788 ilk_do_mmio_flip(intel_crtc);
10789
9362c7c5
ACO		 10790 if (atomic_update)
10791 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10792}
10793
9362c7c5 10794static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10795{
cc8c4cc2 10796 struct intel_crtc *crtc =
9362c7c5 10797 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 10798 struct intel_mmio_flip *mmio_flip;
84c33a64 10799
cc8c4cc2
JH		 10800 mmio_flip = &crtc->mmio_flip;
10801 if (mmio_flip->req)
9c654818
JH		 10802 WARN_ON(__i915_wait_request(mmio_flip->req,
10803 crtc->reset_counter,
10804 false, NULL, NULL) != 0);
84c33a64 10805
cc8c4cc2
JH		 10806 intel_do_mmio_flip(crtc);
10807 if (mmio_flip->req) {
10808 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 10809 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 10810 mutex_unlock(&crtc->base.dev->struct_mutex);
10811 }
84c33a64
SG		 10812}
10813
10814static int intel_queue_mmio_flip(struct drm_device *dev,
10815 struct drm_crtc *crtc,
10816 struct drm_framebuffer *fb,
10817 struct drm_i915_gem_object *obj,
10818 struct intel_engine_cs *ring,
10819 uint32_t flags)
10820{
84c33a64 10821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 10822
cc8c4cc2
JH		 10823 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10824 obj->last_write_req);
536f5b5e
ACO		 10825
10826 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10827
84c33a64
SG		 10828 return 0;
10829}
10830
8c9f3aaf
JB		 10831static int intel_default_queue_flip(struct drm_device *dev,
10832 struct drm_crtc *crtc,
10833 struct drm_framebuffer *fb,
ed8d1975 10834 struct drm_i915_gem_object *obj,
a4872ba6 10835 struct intel_engine_cs *ring,
ed8d1975 10836 uint32_t flags)
8c9f3aaf
JB		 10837{
10838 return -ENODEV;
10839}
10840
d6bbafa1
CW		 10841static bool __intel_pageflip_stall_check(struct drm_device *dev,
10842 struct drm_crtc *crtc)
10843{
10844 struct drm_i915_private *dev_priv = dev->dev_private;
10845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10846 struct intel_unpin_work *work = intel_crtc->unpin_work;
10847 u32 addr;
10848
10849 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10850 return true;
10851
10852 if (!work->enable_stall_check)
10853 return false;
10854
10855 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10856 if (work->flip_queued_req &&
10857 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10858 return false;
10859
1e3feefd 10860 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10861 }
10862
1e3feefd 10863 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10864 return false;
10865
10866 /* Potential stall - if we see that the flip has happened,
10867 * assume a missed interrupt. */
10868 if (INTEL_INFO(dev)->gen >= 4)
10869 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10870 else
10871 addr = I915_READ(DSPADDR(intel_crtc->plane));
10872
10873 /* There is a potential issue here with a false positive after a flip
10874 * to the same address. We could address this by checking for a
10875 * non-incrementing frame counter.
10876 */
10877 return addr == work->gtt_offset;
10878}
10879
10880void intel_check_page_flip(struct drm_device *dev, int pipe)
10881{
10882 struct drm_i915_private *dev_priv = dev->dev_private;
10883 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10885 struct intel_unpin_work *work;
f326038a 10886
6c51d46f 10887 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10888
10889 if (crtc == NULL)
10890 return;
10891
f326038a 10892 spin_lock(&dev->event_lock);
6ad790c0
CW		 10893 work = intel_crtc->unpin_work;
10894 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10895 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10896 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10897 page_flip_completed(intel_crtc);
6ad790c0 10898 work = NULL;
d6bbafa1 10899 }
6ad790c0
CW		 10900 if (work != NULL &&
10901 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10902 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10903 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10904}
10905
6b95a207
KH		 10906static int intel_crtc_page_flip(struct drm_crtc *crtc,
10907 struct drm_framebuffer *fb,
ed8d1975
KP		 10908 struct drm_pending_vblank_event *event,
10909 uint32_t page_flip_flags)
6b95a207
KH		 10910{
10911 struct drm_device *dev = crtc->dev;
10912 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10913 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10914 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10916 struct drm_plane *primary = crtc->primary;
a071fa00 10917 enum pipe pipe = intel_crtc->pipe;
6b95a207 10918 struct intel_unpin_work *work;
a4872ba6 10919 struct intel_engine_cs *ring;
cf5d8a46 10920 bool mmio_flip;
52e68630 10921 int ret;
6b95a207 10922
2ff8fde1
MR		 10923 /*
10924 * drm_mode_page_flip_ioctl() should already catch this, but double
10925 * check to be safe. In the future we may enable pageflipping from
10926 * a disabled primary plane.
10927 */
10928 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10929 return -EBUSY;
10930
e6a595d2 10931 /* Can't change pixel format via MI display flips. */
f4510a27 10932 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10933 return -EINVAL;
10934
10935 /*
10936 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10937 * Note that pitch changes could also affect these register.
10938 */
10939 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10940 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10941 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10942 return -EINVAL;
10943
f900db47
CW		 10944 if (i915_terminally_wedged(&dev_priv->gpu_error))
10945 goto out_hang;
10946
b14c5679 10947 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10948 if (work == NULL)
10949 return -ENOMEM;
10950
6b95a207 10951 work->event = event;
b4a98e57 10952 work->crtc = crtc;
ab8d6675 10953 work->old_fb = old_fb;
6b95a207
KH		 10954 INIT_WORK(&work->work, intel_unpin_work_fn);
10955
87b6b101 10956 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10957 if (ret)
10958 goto free_work;
10959
6b95a207 10960 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10961 spin_lock_irq(&dev->event_lock);
6b95a207 10962 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10963 /* Before declaring the flip queue wedged, check if
10964 * the hardware completed the operation behind our backs.
10965 */
10966 if (__intel_pageflip_stall_check(dev, crtc)) {
10967 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10968 page_flip_completed(intel_crtc);
10969 } else {
10970 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10971 spin_unlock_irq(&dev->event_lock);
468f0b44 10972
d6bbafa1
CW		 10973 drm_crtc_vblank_put(crtc);
10974 kfree(work);
10975 return -EBUSY;
10976 }
6b95a207
KH		 10977 }
10978 intel_crtc->unpin_work = work;
5e2d7afc 10979 spin_unlock_irq(&dev->event_lock);
6b95a207 10980
b4a98e57
CW		 10981 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10982 flush_workqueue(dev_priv->wq);
10983
75dfca80 10984 /* Reference the objects for the scheduled work. */
ab8d6675 10985 drm_framebuffer_reference(work->old_fb);
05394f39 10986 drm_gem_object_reference(&obj->base);
6b95a207 10987
f4510a27 10988 crtc->primary->fb = fb;
afd65eb4 10989 update_state_fb(crtc->primary);
1ed1f968 10990
e1f99ce6 10991 work->pending_flip_obj = obj;
e1f99ce6 10992
89ed88ba
CW		 10993 ret = i915_mutex_lock_interruptible(dev);
10994 if (ret)
10995 goto cleanup;
10996
b4a98e57 10997 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10998 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10999
75f7f3ec 11000 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11001 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11002
4fa62c89
VS		 11003 if (IS_VALLEYVIEW(dev)) {
11004 ring = &dev_priv->ring[BCS];
ab8d6675 11005 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11006 /* vlv: DISPLAY_FLIP fails to change tiling */
11007 ring = NULL;
48bf5b2d 11008 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11009 ring = &dev_priv->ring[BCS];
4fa62c89 11010 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 11011 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 11012 if (ring == NULL || ring->id != RCS)
11013 ring = &dev_priv->ring[BCS];
11014 } else {
11015 ring = &dev_priv->ring[RCS];
11016 }
11017
cf5d8a46
CW		 11018 mmio_flip = use_mmio_flip(ring, obj);
11019
11020 /* When using CS flips, we want to emit semaphores between rings.
11021 * However, when using mmio flips we will create a task to do the
11022 * synchronisation, so all we want here is to pin the framebuffer
11023 * into the display plane and skip any waits.
11024 */
82bc3b2d 11025 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 11026 crtc->primary->state,
11027 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 11028 if (ret)
11029 goto cleanup_pending;
6b95a207 11030
121920fa
TU		 11031 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11032 + intel_crtc->dspaddr_offset;
4fa62c89 11033
cf5d8a46 11034 if (mmio_flip) {
84c33a64
SG		 11035 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11036 page_flip_flags);
d6bbafa1
CW		 11037 if (ret)
11038 goto cleanup_unpin;
11039
f06cc1b9
JH		 11040 i915_gem_request_assign(&work->flip_queued_req,
11041 obj->last_write_req);
d6bbafa1 11042 } else {
d94b5030
CW		 11043 if (obj->last_write_req) {
11044 ret = i915_gem_check_olr(obj->last_write_req);
11045 if (ret)
11046 goto cleanup_unpin;
11047 }
11048
84c33a64 11049 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11050 page_flip_flags);
11051 if (ret)
11052 goto cleanup_unpin;
11053
f06cc1b9
JH		 11054 i915_gem_request_assign(&work->flip_queued_req,
11055 intel_ring_get_request(ring));
d6bbafa1
CW		 11056 }
11057
1e3feefd 11058 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11059 work->enable_stall_check = true;
4fa62c89 11060
ab8d6675 11061 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11062 INTEL_FRONTBUFFER_PRIMARY(pipe));
11063
7ff0ebcc 11064 intel_fbc_disable(dev);
f99d7069 11065 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11066 mutex_unlock(&dev->struct_mutex);
11067
e5510fac
JB		 11068 trace_i915_flip_request(intel_crtc->plane, obj);
11069
6b95a207 11070 return 0;
96b099fd 11071
4fa62c89 11072cleanup_unpin:
82bc3b2d 11073 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11074cleanup_pending:
b4a98e57 11075 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11076 mutex_unlock(&dev->struct_mutex);
11077cleanup:
f4510a27 11078 crtc->primary->fb = old_fb;
afd65eb4 11079 update_state_fb(crtc->primary);
89ed88ba
CW		 11080
11081 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11082 drm_framebuffer_unreference(work->old_fb);
96b099fd 11083
5e2d7afc 11084 spin_lock_irq(&dev->event_lock);
96b099fd 11085 intel_crtc->unpin_work = NULL;
5e2d7afc 11086 spin_unlock_irq(&dev->event_lock);
96b099fd 11087
87b6b101 11088 drm_crtc_vblank_put(crtc);
7317c75e 11089free_work:
96b099fd
CW		 11090 kfree(work);
11091
f900db47
CW		 11092 if (ret == -EIO) {
11093out_hang:
53a366b9 11094 ret = intel_plane_restore(primary);
f0d3dad3 11095 if (ret == 0 && event) {
5e2d7afc 11096 spin_lock_irq(&dev->event_lock);
a071fa00 11097 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11098 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11099 }
f900db47 11100 }
96b099fd 11101 return ret;
6b95a207
KH		 11102}
11103
65b38e0d 11104static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11105 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11106 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11107 .atomic_begin = intel_begin_crtc_commit,
11108 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11109};
11110
9a935856
DV		 11111/**
11112 * intel_modeset_update_staged_output_state
11113 *
11114 * Updates the staged output configuration state, e.g. after we've read out the
11115 * current hw state.
11116 */
11117static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11118{
7668851f 11119 struct intel_crtc *crtc;
9a935856
DV		 11120 struct intel_encoder *encoder;
11121 struct intel_connector *connector;
f6e5b160 11122
3a3371ff 11123 for_each_intel_connector(dev, connector) {
9a935856
DV		 11124 connector->new_encoder =
11125 to_intel_encoder(connector->base.encoder);
11126 }
f6e5b160 11127
b2784e15 11128 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11129 encoder->new_crtc =
11130 to_intel_crtc(encoder->base.crtc);
11131 }
7668851f 11132
d3fcc808 11133 for_each_intel_crtc(dev, crtc) {
83d65738 11134 crtc->new_enabled = crtc->base.state->enable;
7668851f 11135 }
f6e5b160
CW		 11136}
11137
d29b2f9d
ACO		 11138/* Transitional helper to copy current connector/encoder state to
11139 * connector->state. This is needed so that code that is partially
11140 * converted to atomic does the right thing.
11141 */
11142static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11143{
11144 struct intel_connector *connector;
11145
11146 for_each_intel_connector(dev, connector) {
11147 if (connector->base.encoder) {
11148 connector->base.state->best_encoder =
11149 connector->base.encoder;
11150 connector->base.state->crtc =
11151 connector->base.encoder->crtc;
11152 } else {
11153 connector->base.state->best_encoder = NULL;
11154 connector->base.state->crtc = NULL;
11155 }
11156 }
11157}
11158
a821fc46 11159/* Fixup legacy state after an atomic state swap.
9a935856 11160 */
a821fc46 11161static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11162{
a821fc46 11163 struct intel_crtc *crtc;
9a935856 11164 struct intel_encoder *encoder;
a821fc46 11165 struct intel_connector *connector;
d5432a9d 11166
a821fc46
ACO		 11167 for_each_intel_connector(state->dev, connector) {
11168 connector->base.encoder = connector->base.state->best_encoder;
11169 if (connector->base.encoder)
11170 connector->base.encoder->crtc =
11171 connector->base.state->crtc;
9a935856 11172 }
f6e5b160 11173
d5432a9d
ACO		 11174 /* Update crtc of disabled encoders */
11175 for_each_intel_encoder(state->dev, encoder) {
11176 int num_connectors = 0;
11177
a821fc46
ACO		 11178 for_each_intel_connector(state->dev, connector)
11179 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO		 11180 num_connectors++;
11181
11182 if (num_connectors == 0)
11183 encoder->base.crtc = NULL;
9a935856 11184 }
7668851f 11185
a821fc46
ACO		 11186 for_each_intel_crtc(state->dev, crtc) {
11187 crtc->base.enabled = crtc->base.state->enable;
11188 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11189 }
d29b2f9d 11190
d5432a9d
ACO		 11191 /* Copy the new configuration to the staged state, to keep the few
11192 * pieces of code that haven't been converted yet happy */
11193 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV		 11194}
11195
050f7aeb 11196static void
eba905b2 11197connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11198 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11199{
11200 int bpp = pipe_config->pipe_bpp;
11201
11202 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11203 connector->base.base.id,
c23cc417 11204 connector->base.name);
050f7aeb
DV		 11205
11206 /* Don't use an invalid EDID bpc value */
11207 if (connector->base.display_info.bpc &&
11208 connector->base.display_info.bpc * 3 < bpp) {
11209 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11210 bpp, connector->base.display_info.bpc*3);
11211 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11212 }
11213
11214 /* Clamp bpp to 8 on screens without EDID 1.4 */
11215 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11216 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11217 bpp);
11218 pipe_config->pipe_bpp = 24;
11219 }
11220}
11221
4e53c2e0 11222static int
050f7aeb 11223compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11224 struct intel_crtc_state *pipe_config)
4e53c2e0 11225{
050f7aeb 11226 struct drm_device *dev = crtc->base.dev;
1486017f 11227 struct drm_atomic_state *state;
da3ced29
ACO		 11228 struct drm_connector *connector;
11229 struct drm_connector_state *connector_state;
1486017f 11230 int bpp, i;
4e53c2e0 11231
d328c9d7 11232 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11233 bpp = 10*3;
d328c9d7
DV		 11234 else if (INTEL_INFO(dev)->gen >= 5)
11235 bpp = 12*3;
11236 else
11237 bpp = 8*3;
11238
4e53c2e0 11239
4e53c2e0
DV		 11240 pipe_config->pipe_bpp = bpp;
11241
1486017f
ACO		 11242 state = pipe_config->base.state;
11243
4e53c2e0 11244 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11245 for_each_connector_in_state(state, connector, connector_state, i) {
11246 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11247 continue;
11248
da3ced29
ACO		 11249 connected_sink_compute_bpp(to_intel_connector(connector),
11250 pipe_config);
4e53c2e0
DV		 11251 }
11252
11253 return bpp;
11254}
11255
644db711
DV		 11256static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11257{
11258 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11259 "type: 0x%x flags: 0x%x\n",
1342830c 11260 mode->crtc_clock,
644db711
DV		 11261 mode->crtc_hdisplay, mode->crtc_hsync_start,
11262 mode->crtc_hsync_end, mode->crtc_htotal,
11263 mode->crtc_vdisplay, mode->crtc_vsync_start,
11264 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11265}
11266
c0b03411 11267static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11268 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11269 const char *context)
11270{
6a60cd87
CK		 11271 struct drm_device *dev = crtc->base.dev;
11272 struct drm_plane *plane;
11273 struct intel_plane *intel_plane;
11274 struct intel_plane_state *state;
11275 struct drm_framebuffer *fb;
11276
11277 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11278 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11279
11280 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11281 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11282 pipe_config->pipe_bpp, pipe_config->dither);
11283 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11284 pipe_config->has_pch_encoder,
11285 pipe_config->fdi_lanes,
11286 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11287 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11288 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11289 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11290 pipe_config->has_dp_encoder,
11291 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11292 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11293 pipe_config->dp_m_n.tu);
b95af8be
VK		 11294
11295 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11296 pipe_config->has_dp_encoder,
11297 pipe_config->dp_m2_n2.gmch_m,
11298 pipe_config->dp_m2_n2.gmch_n,
11299 pipe_config->dp_m2_n2.link_m,
11300 pipe_config->dp_m2_n2.link_n,
11301 pipe_config->dp_m2_n2.tu);
11302
55072d19
DV		 11303 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11304 pipe_config->has_audio,
11305 pipe_config->has_infoframe);
11306
c0b03411 11307 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11308 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11309 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11310 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11311 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11312 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11313 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11314 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
6a60cd87
CK		 11315 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11316 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11317 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11318 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11319 pipe_config->gmch_pfit.control,
11320 pipe_config->gmch_pfit.pgm_ratios,
11321 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11322 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11323 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11324 pipe_config->pch_pfit.size,
11325 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11326 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11327 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87
CK		 11328
11329 DRM_DEBUG_KMS("planes on this crtc\n");
11330 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11331 intel_plane = to_intel_plane(plane);
11332 if (intel_plane->pipe != crtc->pipe)
11333 continue;
11334
11335 state = to_intel_plane_state(plane->state);
11336 fb = state->base.fb;
11337 if (!fb) {
11338 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11339 "disabled, scaler_id = %d\n",
11340 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11341 plane->base.id, intel_plane->pipe,
11342 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11343 drm_plane_index(plane), state->scaler_id);
11344 continue;
11345 }
11346
11347 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11348 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11349 plane->base.id, intel_plane->pipe,
11350 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11351 drm_plane_index(plane));
11352 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11353 fb->base.id, fb->width, fb->height, fb->pixel_format);
11354 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11355 state->scaler_id,
11356 state->src.x1 >> 16, state->src.y1 >> 16,
11357 drm_rect_width(&state->src) >> 16,
11358 drm_rect_height(&state->src) >> 16,
11359 state->dst.x1, state->dst.y1,
11360 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11361 }
c0b03411
DV		 11362}
11363
bc079e8b
VS		 11364static bool encoders_cloneable(const struct intel_encoder *a,
11365 const struct intel_encoder *b)
accfc0c5 11366{
bc079e8b
VS		 11367 /* masks could be asymmetric, so check both ways */
11368 return a == b || (a->cloneable & (1 << b->type) &&
11369 b->cloneable & (1 << a->type));
11370}
11371
98a221da
ACO		 11372static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11373 struct intel_crtc *crtc,
bc079e8b
VS		 11374 struct intel_encoder *encoder)
11375{
bc079e8b 11376 struct intel_encoder *source_encoder;
da3ced29 11377 struct drm_connector *connector;
98a221da
ACO		 11378 struct drm_connector_state *connector_state;
11379 int i;
bc079e8b 11380
da3ced29 11381 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11382 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11383 continue;
11384
98a221da
ACO		 11385 source_encoder =
11386 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11387 if (!encoders_cloneable(encoder, source_encoder))
11388 return false;
11389 }
11390
11391 return true;
11392}
11393
98a221da
ACO		 11394static bool check_encoder_cloning(struct drm_atomic_state *state,
11395 struct intel_crtc *crtc)
bc079e8b 11396{
accfc0c5 11397 struct intel_encoder *encoder;
da3ced29 11398 struct drm_connector *connector;
98a221da
ACO		 11399 struct drm_connector_state *connector_state;
11400 int i;
accfc0c5 11401
da3ced29 11402 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11403 if (connector_state->crtc != &crtc->base)
11404 continue;
11405
11406 encoder = to_intel_encoder(connector_state->best_encoder);
11407 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11408 return false;
accfc0c5
DV		 11409 }
11410
bc079e8b 11411 return true;
accfc0c5
DV		 11412}
11413
5448a00d 11414static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11415{
5448a00d
ACO		 11416 struct drm_device *dev = state->dev;
11417 struct intel_encoder *encoder;
da3ced29 11418 struct drm_connector *connector;
5448a00d 11419 struct drm_connector_state *connector_state;
00f0b378 11420 unsigned int used_ports = 0;
5448a00d 11421 int i;
00f0b378
VS		 11422
11423 /*
11424 * Walk the connector list instead of the encoder
11425 * list to detect the problem on ddi platforms
11426 * where there's just one encoder per digital port.
11427 */
da3ced29 11428 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 11429 if (!connector_state->best_encoder)
00f0b378
VS		 11430 continue;
11431
5448a00d
ACO		 11432 encoder = to_intel_encoder(connector_state->best_encoder);
11433
11434 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11435
11436 switch (encoder->type) {
11437 unsigned int port_mask;
11438 case INTEL_OUTPUT_UNKNOWN:
11439 if (WARN_ON(!HAS_DDI(dev)))
11440 break;
11441 case INTEL_OUTPUT_DISPLAYPORT:
11442 case INTEL_OUTPUT_HDMI:
11443 case INTEL_OUTPUT_EDP:
11444 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11445
11446 /* the same port mustn't appear more than once */
11447 if (used_ports & port_mask)
11448 return false;
11449
11450 used_ports |= port_mask;
11451 default:
11452 break;
11453 }
11454 }
11455
11456 return true;
11457}
11458
83a57153
ACO		 11459static void
11460clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11461{
11462 struct drm_crtc_state tmp_state;
663a3640 11463 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 11464 struct intel_dpll_hw_state dpll_hw_state;
11465 enum intel_dpll_id shared_dpll;
83a57153 11466
663a3640 11467 /* Clear only the intel specific part of the crtc state excluding scalers */
83a57153 11468 tmp_state = crtc_state->base;
663a3640 11469 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 11470 shared_dpll = crtc_state->shared_dpll;
11471 dpll_hw_state = crtc_state->dpll_hw_state;
11472
83a57153 11473 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 11474
83a57153 11475 crtc_state->base = tmp_state;
663a3640 11476 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 11477 crtc_state->shared_dpll = shared_dpll;
11478 crtc_state->dpll_hw_state = dpll_hw_state;
83a57153
ACO		 11479}
11480
548ee15b 11481static int
b8cecdf5 11482intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 11483 struct drm_atomic_state *state,
11484 struct intel_crtc_state *pipe_config)
ee7b9f93 11485{
7758a113 11486 struct intel_encoder *encoder;
da3ced29 11487 struct drm_connector *connector;
0b901879 11488 struct drm_connector_state *connector_state;
d328c9d7 11489 int base_bpp, ret = -EINVAL;
0b901879 11490 int i;
e29c22c0 11491 bool retry = true;
ee7b9f93 11492
98a221da 11493 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 11494 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 11495 return -EINVAL;
accfc0c5
DV		 11496 }
11497
5448a00d 11498 if (!check_digital_port_conflicts(state)) {
00f0b378 11499 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 11500 return -EINVAL;
00f0b378
VS		 11501 }
11502
83a57153 11503 clear_intel_crtc_state(pipe_config);
7758a113 11504
e143a21c
DV		 11505 pipe_config->cpu_transcoder =
11506 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 11507
2960bc9c
ID		 11508 /*
11509 * Sanitize sync polarity flags based on requested ones. If neither
11510 * positive or negative polarity is requested, treat this as meaning
11511 * negative polarity.
11512 */
2d112de7 11513 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11514 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11515 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11516
2d112de7 11517 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11518 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11519 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11520
050f7aeb
DV		 11521 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11522 * plane pixel format and any sink constraints into account. Returns the
11523 * source plane bpp so that dithering can be selected on mismatches
11524 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11525 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11526 pipe_config);
11527 if (base_bpp < 0)
4e53c2e0
DV		 11528 goto fail;
11529
e41a56be
VS		 11530 /*
11531 * Determine the real pipe dimensions. Note that stereo modes can
11532 * increase the actual pipe size due to the frame doubling and
11533 * insertion of additional space for blanks between the frame. This
11534 * is stored in the crtc timings. We use the requested mode to do this
11535 * computation to clearly distinguish it from the adjusted mode, which
11536 * can be changed by the connectors in the below retry loop.
11537 */
2d112de7 11538 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11539 &pipe_config->pipe_src_w,
11540 &pipe_config->pipe_src_h);
e41a56be 11541
e29c22c0 11542encoder_retry:
ef1b460d 11543 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11544 pipe_config->port_clock = 0;
ef1b460d 11545 pipe_config->pixel_multiplier = 1;
ff9a6750 11546
135c81b8 11547 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11548 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11549 CRTC_STEREO_DOUBLE);
135c81b8 11550
7758a113
DV		 11551 /* Pass our mode to the connectors and the CRTC to give them a chance to
11552 * adjust it according to limitations or connector properties, and also
11553 * a chance to reject the mode entirely.
47f1c6c9 11554 */
da3ced29 11555 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 11556 if (connector_state->crtc != crtc)
7758a113 11557 continue;
7ae89233 11558
0b901879
ACO		 11559 encoder = to_intel_encoder(connector_state->best_encoder);
11560
efea6e8e
DV		 11561 if (!(encoder->compute_config(encoder, pipe_config))) {
11562 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11563 goto fail;
11564 }
ee7b9f93 11565 }
47f1c6c9 11566
ff9a6750
DV		 11567 /* Set default port clock if not overwritten by the encoder. Needs to be
11568 * done afterwards in case the encoder adjusts the mode. */
11569 if (!pipe_config->port_clock)
2d112de7 11570 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11571 * pipe_config->pixel_multiplier;
ff9a6750 11572
a43f6e0f 11573 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11574 if (ret < 0) {
7758a113
DV		 11575 DRM_DEBUG_KMS("CRTC fixup failed\n");
11576 goto fail;
ee7b9f93 11577 }
e29c22c0
DV		 11578
11579 if (ret == RETRY) {
11580 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11581 ret = -EINVAL;
11582 goto fail;
11583 }
11584
11585 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11586 retry = false;
11587 goto encoder_retry;
11588 }
11589
d328c9d7 11590 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11591 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11592 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11593
548ee15b 11594 return 0;
7758a113 11595fail:
548ee15b 11596 return ret;
ee7b9f93 11597}
47f1c6c9 11598
ea9d758d 11599static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11600{
ea9d758d 11601 struct drm_encoder *encoder;
f6e5b160 11602 struct drm_device *dev = crtc->dev;
f6e5b160 11603
ea9d758d
DV		 11604 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11605 if (encoder->crtc == crtc)
11606 return true;
11607
11608 return false;
11609}
11610
0a9ab303
ACO		 11611static bool
11612needs_modeset(struct drm_crtc_state *state)
11613{
11614 return state->mode_changed || state->active_changed;
11615}
11616
ea9d758d 11617static void
0a9ab303 11618intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 11619{
0a9ab303 11620 struct drm_device *dev = state->dev;
ba41c0de 11621 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 11622 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 11623 struct drm_crtc *crtc;
11624 struct drm_crtc_state *crtc_state;
ea9d758d 11625 struct drm_connector *connector;
0a9ab303 11626 int i;
ea9d758d 11627
ba41c0de
DV		 11628 intel_shared_dpll_commit(dev_priv);
11629
b2784e15 11630 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11631 if (!intel_encoder->base.crtc)
11632 continue;
11633
0a9ab303
ACO		 11634 for_each_crtc_in_state(state, crtc, crtc_state, i)
11635 if (crtc == intel_encoder->base.crtc)
11636 break;
11637
11638 if (crtc != intel_encoder->base.crtc)
11639 continue;
ea9d758d 11640
0a9ab303 11641 if (crtc_state->enable && needs_modeset(crtc_state))
ea9d758d
DV		 11642 intel_encoder->connectors_active = false;
11643 }
11644
a821fc46
ACO		 11645 drm_atomic_helper_swap_state(state->dev, state);
11646 intel_modeset_fixup_state(state);
ea9d758d 11647
7668851f 11648 /* Double check state. */
0a9ab303
ACO		 11649 for_each_crtc(dev, crtc) {
11650 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV		 11651 }
11652
11653 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11654 if (!connector->encoder || !connector->encoder->crtc)
11655 continue;
11656
0a9ab303
ACO		 11657 for_each_crtc_in_state(state, crtc, crtc_state, i)
11658 if (crtc == connector->encoder->crtc)
11659 break;
11660
11661 if (crtc != connector->encoder->crtc)
11662 continue;
ea9d758d 11663
a821fc46 11664 if (crtc->state->enable && needs_modeset(crtc->state)) {
68d34720
DV		 11665 struct drm_property *dpms_property =
11666 dev->mode_config.dpms_property;
11667
ea9d758d 11668 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11669 drm_object_property_set_value(&connector->base,
68d34720
DV		 11670 dpms_property,
11671 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11672
11673 intel_encoder = to_intel_encoder(connector->encoder);
11674 intel_encoder->connectors_active = true;
11675 }
11676 }
11677
11678}
11679
3bd26263 11680static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11681{
3bd26263 11682 int diff;
f1f644dc
JB		 11683
11684 if (clock1 == clock2)
11685 return true;
11686
11687 if (!clock1 || !clock2)
11688 return false;
11689
11690 diff = abs(clock1 - clock2);
11691
11692 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11693 return true;
11694
11695 return false;
11696}
11697
25c5b266
DV		 11698#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11699 list_for_each_entry((intel_crtc), \
11700 &(dev)->mode_config.crtc_list, \
11701 base.head) \
0973f18f 11702 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11703
0e8ffe1b 11704static bool
2fa2fe9a 11705intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11706 struct intel_crtc_state *current_config,
11707 struct intel_crtc_state *pipe_config)
0e8ffe1b 11708{
66e985c0
DV		 11709#define PIPE_CONF_CHECK_X(name) \
11710 if (current_config->name != pipe_config->name) { \
11711 DRM_ERROR("mismatch in " #name " " \
11712 "(expected 0x%08x, found 0x%08x)\n", \
11713 current_config->name, \
11714 pipe_config->name); \
11715 return false; \
11716 }
11717
08a24034
DV		 11718#define PIPE_CONF_CHECK_I(name) \
11719 if (current_config->name != pipe_config->name) { \
11720 DRM_ERROR("mismatch in " #name " " \
11721 "(expected %i, found %i)\n", \
11722 current_config->name, \
11723 pipe_config->name); \
11724 return false; \
88adfff1
DV		 11725 }
11726
b95af8be
VK		 11727/* This is required for BDW+ where there is only one set of registers for
11728 * switching between high and low RR.
11729 * This macro can be used whenever a comparison has to be made between one
11730 * hw state and multiple sw state variables.
11731 */
11732#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11733 if ((current_config->name != pipe_config->name) && \
11734 (current_config->alt_name != pipe_config->name)) { \
11735 DRM_ERROR("mismatch in " #name " " \
11736 "(expected %i or %i, found %i)\n", \
11737 current_config->name, \
11738 current_config->alt_name, \
11739 pipe_config->name); \
11740 return false; \
11741 }
11742
1bd1bd80
DV		 11743#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11744 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11745 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11746 "(expected %i, found %i)\n", \
11747 current_config->name & (mask), \
11748 pipe_config->name & (mask)); \
11749 return false; \
11750 }
11751
5e550656
VS		 11752#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11753 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11754 DRM_ERROR("mismatch in " #name " " \
11755 "(expected %i, found %i)\n", \
11756 current_config->name, \
11757 pipe_config->name); \
11758 return false; \
11759 }
11760
bb760063
DV		 11761#define PIPE_CONF_QUIRK(quirk) \
11762 ((current_config->quirks | pipe_config->quirks) & (quirk))
11763
eccb140b
DV		 11764 PIPE_CONF_CHECK_I(cpu_transcoder);
11765
08a24034
DV		 11766 PIPE_CONF_CHECK_I(has_pch_encoder);
11767 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11768 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11769 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11770 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11771 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11772 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11773
eb14cb74 11774 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11775
11776 if (INTEL_INFO(dev)->gen < 8) {
11777 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11778 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11779 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11780 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11781 PIPE_CONF_CHECK_I(dp_m_n.tu);
11782
11783 if (current_config->has_drrs) {
11784 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11785 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11786 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11787 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11788 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11789 }
11790 } else {
11791 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11792 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11793 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11794 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11795 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11796 }
eb14cb74 11797
2d112de7
ACO		 11798 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11799 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11800 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11801 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11802 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11803 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11804
2d112de7
ACO		 11805 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11806 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11807 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11808 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11809 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11810 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11811
c93f54cf 11812 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11813 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11814 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11815 IS_VALLEYVIEW(dev))
11816 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11817 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11818
9ed109a7
DV		 11819 PIPE_CONF_CHECK_I(has_audio);
11820
2d112de7 11821 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11822 DRM_MODE_FLAG_INTERLACE);
11823
bb760063 11824 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11825 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11826 DRM_MODE_FLAG_PHSYNC);
2d112de7 11827 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11828 DRM_MODE_FLAG_NHSYNC);
2d112de7 11829 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11830 DRM_MODE_FLAG_PVSYNC);
2d112de7 11831 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11832 DRM_MODE_FLAG_NVSYNC);
11833 }
045ac3b5 11834
37327abd
VS		 11835 PIPE_CONF_CHECK_I(pipe_src_w);
11836 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11837
9953599b
DV		 11838 /*
11839 * FIXME: BIOS likes to set up a cloned config with lvds+external
11840 * screen. Since we don't yet re-compute the pipe config when moving
11841 * just the lvds port away to another pipe the sw tracking won't match.
11842 *
11843 * Proper atomic modesets with recomputed global state will fix this.
11844 * Until then just don't check gmch state for inherited modes.
11845 */
11846 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11847 PIPE_CONF_CHECK_I(gmch_pfit.control);
11848 /* pfit ratios are autocomputed by the hw on gen4+ */
11849 if (INTEL_INFO(dev)->gen < 4)
11850 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11851 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11852 }
11853
fd4daa9c
CW		 11854 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11855 if (current_config->pch_pfit.enabled) {
11856 PIPE_CONF_CHECK_I(pch_pfit.pos);
11857 PIPE_CONF_CHECK_I(pch_pfit.size);
11858 }
2fa2fe9a 11859
a1b2278e
CK		 11860 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11861
e59150dc
JB		 11862 /* BDW+ don't expose a synchronous way to read the state */
11863 if (IS_HASWELL(dev))
11864 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11865
282740f7
VS		 11866 PIPE_CONF_CHECK_I(double_wide);
11867
26804afd
DV		 11868 PIPE_CONF_CHECK_X(ddi_pll_sel);
11869
c0d43d62 11870 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11871 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11872 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11873 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11874 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11875 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11876 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11877 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11878 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11879
42571aef
VS		 11880 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11881 PIPE_CONF_CHECK_I(pipe_bpp);
11882
2d112de7 11883 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11884 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11885
66e985c0 11886#undef PIPE_CONF_CHECK_X
08a24034 11887#undef PIPE_CONF_CHECK_I
b95af8be 11888#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11889#undef PIPE_CONF_CHECK_FLAGS
5e550656 11890#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11891#undef PIPE_CONF_QUIRK
88adfff1 11892
0e8ffe1b
DV		 11893 return true;
11894}
11895
08db6652
DL		 11896static void check_wm_state(struct drm_device *dev)
11897{
11898 struct drm_i915_private *dev_priv = dev->dev_private;
11899 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11900 struct intel_crtc *intel_crtc;
11901 int plane;
11902
11903 if (INTEL_INFO(dev)->gen < 9)
11904 return;
11905
11906 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11907 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11908
11909 for_each_intel_crtc(dev, intel_crtc) {
11910 struct skl_ddb_entry *hw_entry, *sw_entry;
11911 const enum pipe pipe = intel_crtc->pipe;
11912
11913 if (!intel_crtc->active)
11914 continue;
11915
11916 /* planes */
dd740780 11917 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11918 hw_entry = &hw_ddb.plane[pipe][plane];
11919 sw_entry = &sw_ddb->plane[pipe][plane];
11920
11921 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11922 continue;
11923
11924 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11925 "(expected (%u,%u), found (%u,%u))\n",
11926 pipe_name(pipe), plane + 1,
11927 sw_entry->start, sw_entry->end,
11928 hw_entry->start, hw_entry->end);
11929 }
11930
11931 /* cursor */
11932 hw_entry = &hw_ddb.cursor[pipe];
11933 sw_entry = &sw_ddb->cursor[pipe];
11934
11935 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11936 continue;
11937
11938 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11939 "(expected (%u,%u), found (%u,%u))\n",
11940 pipe_name(pipe),
11941 sw_entry->start, sw_entry->end,
11942 hw_entry->start, hw_entry->end);
11943 }
11944}
11945
91d1b4bd
DV		 11946static void
11947check_connector_state(struct drm_device *dev)
8af6cf88 11948{
8af6cf88
DV		 11949 struct intel_connector *connector;
11950
3a3371ff 11951 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11952 /* This also checks the encoder/connector hw state with the
11953 * ->get_hw_state callbacks. */
11954 intel_connector_check_state(connector);
11955
e2c719b7 11956 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11957 "connector's staged encoder doesn't match current encoder\n");
11958 }
91d1b4bd
DV		 11959}
11960
11961static void
11962check_encoder_state(struct drm_device *dev)
11963{
11964 struct intel_encoder *encoder;
11965 struct intel_connector *connector;
8af6cf88 11966
b2784e15 11967 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11968 bool enabled = false;
11969 bool active = false;
11970 enum pipe pipe, tracked_pipe;
11971
11972 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11973 encoder->base.base.id,
8e329a03 11974 encoder->base.name);
8af6cf88 11975
e2c719b7 11976 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11977 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11978 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11979 "encoder's active_connectors set, but no crtc\n");
11980
3a3371ff 11981 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11982 if (connector->base.encoder != &encoder->base)
11983 continue;
11984 enabled = true;
11985 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11986 active = true;
11987 }
0e32b39c
DA		 11988 /*
11989 * for MST connectors if we unplug the connector is gone
11990 * away but the encoder is still connected to a crtc
11991 * until a modeset happens in response to the hotplug.
11992 */
11993 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11994 continue;
11995
e2c719b7 11996 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11997 "encoder's enabled state mismatch "
11998 "(expected %i, found %i)\n",
11999 !!encoder->base.crtc, enabled);
e2c719b7 12000 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12001 "active encoder with no crtc\n");
12002
e2c719b7 12003 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12004 "encoder's computed active state doesn't match tracked active state "
12005 "(expected %i, found %i)\n", active, encoder->connectors_active);
12006
12007 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12008 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12009 "encoder's hw state doesn't match sw tracking "
12010 "(expected %i, found %i)\n",
12011 encoder->connectors_active, active);
12012
12013 if (!encoder->base.crtc)
12014 continue;
12015
12016 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12017 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12018 "active encoder's pipe doesn't match"
12019 "(expected %i, found %i)\n",
12020 tracked_pipe, pipe);
12021
12022 }
91d1b4bd
DV		 12023}
12024
12025static void
12026check_crtc_state(struct drm_device *dev)
12027{
fbee40df 12028 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12029 struct intel_crtc *crtc;
12030 struct intel_encoder *encoder;
5cec258b 12031 struct intel_crtc_state pipe_config;
8af6cf88 12032
d3fcc808 12033 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12034 bool enabled = false;
12035 bool active = false;
12036
045ac3b5
JB		 12037 memset(&pipe_config, 0, sizeof(pipe_config));
12038
8af6cf88
DV		 12039 DRM_DEBUG_KMS("[CRTC:%d]\n",
12040 crtc->base.base.id);
12041
83d65738 12042 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12043 "active crtc, but not enabled in sw tracking\n");
12044
b2784e15 12045 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12046 if (encoder->base.crtc != &crtc->base)
12047 continue;
12048 enabled = true;
12049 if (encoder->connectors_active)
12050 active = true;
12051 }
6c49f241 12052
e2c719b7 12053 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12054 "crtc's computed active state doesn't match tracked active state "
12055 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12056 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12057 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12058 "(expected %i, found %i)\n", enabled,
12059 crtc->base.state->enable);
8af6cf88 12060
0e8ffe1b
DV		 12061 active = dev_priv->display.get_pipe_config(crtc,
12062 &pipe_config);
d62cf62a 12063
b6b5d049
VS		 12064 /* hw state is inconsistent with the pipe quirk */
12065 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12066 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12067 active = crtc->active;
12068
b2784e15 12069 for_each_intel_encoder(dev, encoder) {
3eaba51c 12070 enum pipe pipe;
6c49f241
DV		 12071 if (encoder->base.crtc != &crtc->base)
12072 continue;
1d37b689 12073 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12074 encoder->get_config(encoder, &pipe_config);
12075 }
12076
e2c719b7 12077 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12078 "crtc active state doesn't match with hw state "
12079 "(expected %i, found %i)\n", crtc->active, active);
12080
c0b03411 12081 if (active &&
6e3c9717 12082 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12083 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12084 intel_dump_pipe_config(crtc, &pipe_config,
12085 "[hw state]");
6e3c9717 12086 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12087 "[sw state]");
12088 }
8af6cf88
DV		 12089 }
12090}
12091
91d1b4bd
DV		 12092static void
12093check_shared_dpll_state(struct drm_device *dev)
12094{
fbee40df 12095 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12096 struct intel_crtc *crtc;
12097 struct intel_dpll_hw_state dpll_hw_state;
12098 int i;
5358901f
DV		 12099
12100 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12101 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12102 int enabled_crtcs = 0, active_crtcs = 0;
12103 bool active;
12104
12105 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12106
12107 DRM_DEBUG_KMS("%s\n", pll->name);
12108
12109 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12110
e2c719b7 12111 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12112 "more active pll users than references: %i vs %i\n",
3e369b76 12113 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12114 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12115 "pll in active use but not on in sw tracking\n");
e2c719b7 12116 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12117 "pll in on but not on in use in sw tracking\n");
e2c719b7 12118 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12119 "pll on state mismatch (expected %i, found %i)\n",
12120 pll->on, active);
12121
d3fcc808 12122 for_each_intel_crtc(dev, crtc) {
83d65738 12123 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12124 enabled_crtcs++;
12125 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12126 active_crtcs++;
12127 }
e2c719b7 12128 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12129 "pll active crtcs mismatch (expected %i, found %i)\n",
12130 pll->active, active_crtcs);
e2c719b7 12131 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12132 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12133 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12134
e2c719b7 12135 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12136 sizeof(dpll_hw_state)),
12137 "pll hw state mismatch\n");
5358901f 12138 }
8af6cf88
DV		 12139}
12140
91d1b4bd
DV		 12141void
12142intel_modeset_check_state(struct drm_device *dev)
12143{
08db6652 12144 check_wm_state(dev);
91d1b4bd
DV		 12145 check_connector_state(dev);
12146 check_encoder_state(dev);
12147 check_crtc_state(dev);
12148 check_shared_dpll_state(dev);
12149}
12150
5cec258b 12151void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12152 int dotclock)
12153{
12154 /*
12155 * FDI already provided one idea for the dotclock.
12156 * Yell if the encoder disagrees.
12157 */
2d112de7 12158 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12159 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12160 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12161}
12162
80715b2f
VS		 12163static void update_scanline_offset(struct intel_crtc *crtc)
12164{
12165 struct drm_device *dev = crtc->base.dev;
12166
12167 /*
12168 * The scanline counter increments at the leading edge of hsync.
12169 *
12170 * On most platforms it starts counting from vtotal-1 on the
12171 * first active line. That means the scanline counter value is
12172 * always one less than what we would expect. Ie. just after
12173 * start of vblank, which also occurs at start of hsync (on the
12174 * last active line), the scanline counter will read vblank_start-1.
12175 *
12176 * On gen2 the scanline counter starts counting from 1 instead
12177 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12178 * to keep the value positive), instead of adding one.
12179 *
12180 * On HSW+ the behaviour of the scanline counter depends on the output
12181 * type. For DP ports it behaves like most other platforms, but on HDMI
12182 * there's an extra 1 line difference. So we need to add two instead of
12183 * one to the value.
12184 */
12185 if (IS_GEN2(dev)) {
6e3c9717 12186 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12187 int vtotal;
12188
12189 vtotal = mode->crtc_vtotal;
12190 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12191 vtotal /= 2;
12192
12193 crtc->scanline_offset = vtotal - 1;
12194 } else if (HAS_DDI(dev) &&
409ee761 12195 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12196 crtc->scanline_offset = 2;
12197 } else
12198 crtc->scanline_offset = 1;
12199}
12200
5cec258b 12201static struct intel_crtc_state *
7f27126e 12202intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12203 struct drm_atomic_state *state)
7f27126e 12204{
548ee15b 12205 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12206 int ret = 0;
12207
12208 ret = drm_atomic_add_affected_connectors(state, crtc);
12209 if (ret)
12210 return ERR_PTR(ret);
7f27126e 12211
8c7b5ccb
ACO		 12212 ret = drm_atomic_helper_check_modeset(state->dev, state);
12213 if (ret)
12214 return ERR_PTR(ret);
7f27126e 12215
7f27126e
JB		 12216 /*
12217 * Note this needs changes when we start tracking multiple modes
12218 * and crtcs. At that point we'll need to compute the whole config
12219 * (i.e. one pipe_config for each crtc) rather than just the one
12220 * for this crtc.
12221 */
548ee15b
ACO		 12222 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12223 if (IS_ERR(pipe_config))
12224 return pipe_config;
83a57153 12225
4fed33f6 12226 if (!pipe_config->base.enable)
548ee15b 12227 return pipe_config;
7f27126e 12228
8c7b5ccb 12229 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12230 if (ret)
12231 return ERR_PTR(ret);
12232
8d8c9b51
ACO		 12233 /* Check things that can only be changed through modeset */
12234 if (pipe_config->has_audio !=
12235 to_intel_crtc(crtc)->config->has_audio)
12236 pipe_config->base.mode_changed = true;
12237
12238 /*
12239 * Note we have an issue here with infoframes: current code
12240 * only updates them on the full mode set path per hw
12241 * requirements. So here we should be checking for any
12242 * required changes and forcing a mode set.
12243 */
12244
548ee15b 12245 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12246
8c7b5ccb
ACO		 12247 ret = drm_atomic_helper_check_planes(state->dev, state);
12248 if (ret)
12249 return ERR_PTR(ret);
12250
548ee15b 12251 return pipe_config;
7f27126e
JB		 12252}
12253
0a9ab303 12254static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12255{
225da59b 12256 struct drm_device *dev = state->dev;
ed6739ef 12257 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12258 unsigned clear_pipes = 0;
ed6739ef 12259 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12260 struct intel_crtc_state *intel_crtc_state;
12261 struct drm_crtc *crtc;
12262 struct drm_crtc_state *crtc_state;
ed6739ef 12263 int ret = 0;
0a9ab303 12264 int i;
ed6739ef
ACO		 12265
12266 if (!dev_priv->display.crtc_compute_clock)
12267 return 0;
12268
0a9ab303
ACO		 12269 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12270 intel_crtc = to_intel_crtc(crtc);
4978cc93 12271 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12272
4978cc93 12273 if (needs_modeset(crtc_state)) {
0a9ab303 12274 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93
ACO		 12275 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12276 memset(&intel_crtc_state->dpll_hw_state, 0,
12277 sizeof(intel_crtc_state->dpll_hw_state));
12278 }
0a9ab303
ACO		 12279 }
12280
ed6739ef
ACO		 12281 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12282 if (ret)
12283 goto done;
12284
0a9ab303
ACO		 12285 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12286 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12287 continue;
12288
0a9ab303
ACO		 12289 intel_crtc = to_intel_crtc(crtc);
12290 intel_crtc_state = to_intel_crtc_state(crtc_state);
12291
ed6739ef 12292 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12293 intel_crtc_state);
ed6739ef
ACO		 12294 if (ret) {
12295 intel_shared_dpll_abort_config(dev_priv);
12296 goto done;
12297 }
12298 }
12299
12300done:
12301 return ret;
12302}
12303
054518dd
ACO		 12304/* Code that should eventually be part of atomic_check() */
12305static int __intel_set_mode_checks(struct drm_atomic_state *state)
12306{
12307 struct drm_device *dev = state->dev;
12308 int ret;
12309
12310 /*
12311 * See if the config requires any additional preparation, e.g.
12312 * to adjust global state with pipes off. We need to do this
12313 * here so we can get the modeset_pipe updated config for the new
12314 * mode set on this crtc. For other crtcs we need to use the
12315 * adjusted_mode bits in the crtc directly.
12316 */
12317 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12318 ret = valleyview_modeset_global_pipes(state);
12319 if (ret)
12320 return ret;
12321 }
12322
12323 ret = __intel_set_mode_setup_plls(state);
12324 if (ret)
12325 return ret;
12326
12327 return 0;
12328}
12329
0a9ab303 12330static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12331 struct intel_crtc_state *pipe_config)
a6778b3c 12332{
0a9ab303 12333 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12334 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12335 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 12336 struct drm_crtc *crtc;
12337 struct drm_crtc_state *crtc_state;
c0c36b94 12338 int ret = 0;
0a9ab303 12339 int i;
a6778b3c 12340
054518dd
ACO		 12341 ret = __intel_set_mode_checks(state);
12342 if (ret < 0)
12343 return ret;
12344
d4afb8cc
ACO		 12345 ret = drm_atomic_helper_prepare_planes(dev, state);
12346 if (ret)
12347 return ret;
12348
0a9ab303
ACO		 12349 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12350 if (!needs_modeset(crtc_state))
12351 continue;
460da916 12352
0a9ab303
ACO		 12353 if (!crtc_state->enable) {
12354 intel_crtc_disable(crtc);
12355 } else if (crtc->state->enable) {
12356 intel_crtc_disable_planes(crtc);
12357 dev_priv->display.crtc_disable(crtc);
ce22dba9 12358 }
ea9d758d 12359 }
a6778b3c 12360
6c4c86f5
DV		 12361 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12362 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12363 *
12364 * Note we'll need to fix this up when we start tracking multiple
12365 * pipes; here we assume a single modeset_pipe and only track the
12366 * single crtc and mode.
f6e5b160 12367 */
0a9ab303 12368 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 12369 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS		 12370
12371 /*
12372 * Calculate and store various constants which
12373 * are later needed by vblank and swap-completion
12374 * timestamping. They are derived from true hwmode.
12375 */
0a9ab303 12376 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 12377 &pipe_config->base.adjusted_mode);
b8cecdf5 12378 }
7758a113 12379
ea9d758d
DV		 12380 /* Only after disabling all output pipelines that will be changed can we
12381 * update the the output configuration. */
0a9ab303 12382 intel_modeset_update_state(state);
f6e5b160 12383
a821fc46
ACO		 12384 /* The state has been swaped above, so state actually contains the
12385 * old state now. */
12386
304603f4 12387 modeset_update_crtc_power_domains(state);
47fab737 12388
d4afb8cc 12389 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12390
12391 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12392 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 12393 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 12394 continue;
12395
12396 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12397
0a9ab303
ACO		 12398 dev_priv->display.crtc_enable(crtc);
12399 intel_crtc_enable_planes(crtc);
80715b2f 12400 }
a6778b3c 12401
a6778b3c 12402 /* FIXME: add subpixel order */
83a57153 12403
d4afb8cc
ACO		 12404 drm_atomic_helper_cleanup_planes(dev, state);
12405
2bfb4627
ACO		 12406 drm_atomic_state_free(state);
12407
9eb45f22 12408 return 0;
f6e5b160
CW		 12409}
12410
0a9ab303 12411static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12412 struct intel_crtc_state *pipe_config)
f30da187
DV		 12413{
12414 int ret;
12415
8c7b5ccb 12416 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 12417
12418 if (ret == 0)
12419 intel_modeset_check_state(crtc->dev);
12420
12421 return ret;
12422}
12423
7f27126e 12424static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12425 struct drm_atomic_state *state)
7f27126e 12426{
5cec258b 12427 struct intel_crtc_state *pipe_config;
83a57153 12428 int ret = 0;
7f27126e 12429
8c7b5ccb 12430 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 12431 if (IS_ERR(pipe_config)) {
12432 ret = PTR_ERR(pipe_config);
12433 goto out;
12434 }
12435
8c7b5ccb 12436 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 12437 if (ret)
12438 goto out;
7f27126e 12439
83a57153
ACO		 12440out:
12441 return ret;
7f27126e
JB		 12442}
12443
c0c36b94
CW		 12444void intel_crtc_restore_mode(struct drm_crtc *crtc)
12445{
83a57153
ACO		 12446 struct drm_device *dev = crtc->dev;
12447 struct drm_atomic_state *state;
4be07317 12448 struct intel_crtc *intel_crtc;
83a57153
ACO		 12449 struct intel_encoder *encoder;
12450 struct intel_connector *connector;
12451 struct drm_connector_state *connector_state;
4be07317 12452 struct intel_crtc_state *crtc_state;
2bfb4627 12453 int ret;
83a57153
ACO		 12454
12455 state = drm_atomic_state_alloc(dev);
12456 if (!state) {
12457 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12458 crtc->base.id);
12459 return;
12460 }
12461
12462 state->acquire_ctx = dev->mode_config.acquire_ctx;
12463
12464 /* The force restore path in the HW readout code relies on the staged
12465 * config still keeping the user requested config while the actual
12466 * state has been overwritten by the configuration read from HW. We
12467 * need to copy the staged config to the atomic state, otherwise the
12468 * mode set will just reapply the state the HW is already in. */
12469 for_each_intel_encoder(dev, encoder) {
12470 if (&encoder->new_crtc->base != crtc)
12471 continue;
12472
12473 for_each_intel_connector(dev, connector) {
12474 if (connector->new_encoder != encoder)
12475 continue;
12476
12477 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12478 if (IS_ERR(connector_state)) {
12479 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12480 connector->base.base.id,
12481 connector->base.name,
12482 PTR_ERR(connector_state));
12483 continue;
12484 }
12485
12486 connector_state->crtc = crtc;
12487 connector_state->best_encoder = &encoder->base;
12488 }
12489 }
12490
4be07317
ACO		 12491 for_each_intel_crtc(dev, intel_crtc) {
12492 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12493 continue;
12494
12495 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12496 if (IS_ERR(crtc_state)) {
12497 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12498 intel_crtc->base.base.id,
12499 PTR_ERR(crtc_state));
12500 continue;
12501 }
12502
49d6fa21
ML		 12503 crtc_state->base.active = crtc_state->base.enable =
12504 intel_crtc->new_enabled;
8c7b5ccb
ACO		 12505
12506 if (&intel_crtc->base == crtc)
12507 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 12508 }
12509
d3a40d1b
ACO		 12510 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12511 crtc->primary->fb, crtc->x, crtc->y);
12512
2bfb4627
ACO		 12513 ret = intel_set_mode(crtc, state);
12514 if (ret)
12515 drm_atomic_state_free(state);
c0c36b94
CW		 12516}
12517
25c5b266
DV		 12518#undef for_each_intel_crtc_masked
12519
b7885264
ACO		 12520static bool intel_connector_in_mode_set(struct intel_connector *connector,
12521 struct drm_mode_set *set)
12522{
12523 int ro;
12524
12525 for (ro = 0; ro < set->num_connectors; ro++)
12526 if (set->connectors[ro] == &connector->base)
12527 return true;
12528
12529 return false;
12530}
12531
2e431051 12532static int
9a935856
DV		 12533intel_modeset_stage_output_state(struct drm_device *dev,
12534 struct drm_mode_set *set,
944b0c76 12535 struct drm_atomic_state *state)
50f56119 12536{
9a935856 12537 struct intel_connector *connector;
d5432a9d 12538 struct drm_connector *drm_connector;
944b0c76 12539 struct drm_connector_state *connector_state;
d5432a9d
ACO		 12540 struct drm_crtc *crtc;
12541 struct drm_crtc_state *crtc_state;
12542 int i, ret;
50f56119 12543
9abdda74 12544 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12545 * of connectors. For paranoia, double-check this. */
12546 WARN_ON(!set->fb && (set->num_connectors != 0));
12547 WARN_ON(set->fb && (set->num_connectors == 0));
12548
3a3371ff 12549 for_each_intel_connector(dev, connector) {
b7885264
ACO		 12550 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12551
d5432a9d
ACO		 12552 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12553 continue;
12554
12555 connector_state =
12556 drm_atomic_get_connector_state(state, &connector->base);
12557 if (IS_ERR(connector_state))
12558 return PTR_ERR(connector_state);
12559
b7885264
ACO		 12560 if (in_mode_set) {
12561 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 12562 connector_state->best_encoder =
12563 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 12564 }
12565
d5432a9d 12566 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 12567 continue;
12568
9a935856
DV		 12569 /* If we disable the crtc, disable all its connectors. Also, if
12570 * the connector is on the changing crtc but not on the new
12571 * connector list, disable it. */
b7885264 12572 if (!set->fb || !in_mode_set) {
d5432a9d 12573 connector_state->best_encoder = NULL;
9a935856
DV		 12574
12575 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12576 connector->base.base.id,
c23cc417 12577 connector->base.name);
9a935856 12578 }
50f56119 12579 }
9a935856 12580 /* connector->new_encoder is now updated for all connectors. */
50f56119 12581
d5432a9d
ACO		 12582 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12583 connector = to_intel_connector(drm_connector);
12584
12585 if (!connector_state->best_encoder) {
12586 ret = drm_atomic_set_crtc_for_connector(connector_state,
12587 NULL);
12588 if (ret)
12589 return ret;
7668851f 12590
50f56119 12591 continue;
d5432a9d 12592 }
50f56119 12593
d5432a9d
ACO		 12594 if (intel_connector_in_mode_set(connector, set)) {
12595 struct drm_crtc *crtc = connector->base.state->crtc;
12596
12597 /* If this connector was in a previous crtc, add it
12598 * to the state. We might need to disable it. */
12599 if (crtc) {
12600 crtc_state =
12601 drm_atomic_get_crtc_state(state, crtc);
12602 if (IS_ERR(crtc_state))
12603 return PTR_ERR(crtc_state);
12604 }
12605
12606 ret = drm_atomic_set_crtc_for_connector(connector_state,
12607 set->crtc);
12608 if (ret)
12609 return ret;
12610 }
50f56119
DV		 12611
12612 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 12613 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12614 connector_state->crtc)) {
5e2b584e 12615 return -EINVAL;
50f56119 12616 }
944b0c76 12617
9a935856
DV		 12618 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12619 connector->base.base.id,
c23cc417 12620 connector->base.name,
d5432a9d 12621 connector_state->crtc->base.id);
944b0c76 12622
d5432a9d
ACO		 12623 if (connector_state->best_encoder != &connector->encoder->base)
12624 connector->encoder =
12625 to_intel_encoder(connector_state->best_encoder);
0e32b39c 12626 }
7668851f 12627
d5432a9d 12628 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 12629 bool has_connectors;
12630
d5432a9d
ACO		 12631 ret = drm_atomic_add_affected_connectors(state, crtc);
12632 if (ret)
12633 return ret;
4be07317 12634
49d6fa21
ML		 12635 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12636 if (has_connectors != crtc_state->enable)
12637 crtc_state->enable =
12638 crtc_state->active = has_connectors;
7668851f
VS		 12639 }
12640
8c7b5ccb
ACO		 12641 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12642 set->fb, set->x, set->y);
12643 if (ret)
12644 return ret;
12645
12646 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12647 if (IS_ERR(crtc_state))
12648 return PTR_ERR(crtc_state);
12649
12650 if (set->mode)
12651 drm_mode_copy(&crtc_state->mode, set->mode);
12652
12653 if (set->num_connectors)
12654 crtc_state->active = true;
12655
2e431051
DV		 12656 return 0;
12657}
12658
bb546623
ACO		 12659static bool primary_plane_visible(struct drm_crtc *crtc)
12660{
12661 struct intel_plane_state *plane_state =
12662 to_intel_plane_state(crtc->primary->state);
12663
12664 return plane_state->visible;
12665}
12666
2e431051
DV		 12667static int intel_crtc_set_config(struct drm_mode_set *set)
12668{
12669 struct drm_device *dev;
83a57153 12670 struct drm_atomic_state *state = NULL;
5cec258b 12671 struct intel_crtc_state *pipe_config;
bb546623 12672 bool primary_plane_was_visible;
2e431051 12673 int ret;
2e431051 12674
8d3e375e
DV		 12675 BUG_ON(!set);
12676 BUG_ON(!set->crtc);
12677 BUG_ON(!set->crtc->helper_private);
2e431051 12678
7e53f3a4
DV		 12679 /* Enforce sane interface api - has been abused by the fb helper. */
12680 BUG_ON(!set->mode && set->fb);
12681 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12682
2e431051
DV		 12683 if (set->fb) {
12684 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12685 set->crtc->base.id, set->fb->base.id,
12686 (int)set->num_connectors, set->x, set->y);
12687 } else {
12688 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12689 }
12690
12691 dev = set->crtc->dev;
12692
83a57153 12693 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 12694 if (!state)
12695 return -ENOMEM;
83a57153
ACO		 12696
12697 state->acquire_ctx = dev->mode_config.acquire_ctx;
12698
462a425a 12699 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 12700 if (ret)
7cbf41d6 12701 goto out;
2e431051 12702
8c7b5ccb 12703 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 12704 if (IS_ERR(pipe_config)) {
6ac0483b 12705 ret = PTR_ERR(pipe_config);
7cbf41d6 12706 goto out;
20664591 12707 }
50f52756 12708
1f9954d0
JB		 12709 intel_update_pipe_size(to_intel_crtc(set->crtc));
12710
bb546623
ACO		 12711 primary_plane_was_visible = primary_plane_visible(set->crtc);
12712
8c7b5ccb 12713 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 12714
12715 if (ret == 0 &&
12716 pipe_config->base.enable &&
12717 pipe_config->base.planes_changed &&
12718 !needs_modeset(&pipe_config->base)) {
3b150f08 12719 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 12720
12721 /*
12722 * We need to make sure the primary plane is re-enabled if it
12723 * has previously been turned off.
12724 */
bb546623
ACO		 12725 if (ret == 0 && !primary_plane_was_visible &&
12726 primary_plane_visible(set->crtc)) {
3b150f08 12727 WARN_ON(!intel_crtc->active);
87d4300a 12728 intel_post_enable_primary(set->crtc);
3b150f08
MR		 12729 }
12730
7ca51a3a
JB		 12731 /*
12732 * In the fastboot case this may be our only check of the
12733 * state after boot. It would be better to only do it on
12734 * the first update, but we don't have a nice way of doing that
12735 * (and really, set_config isn't used much for high freq page
12736 * flipping, so increasing its cost here shouldn't be a big
12737 * deal).
12738 */
d330a953 12739 if (i915.fastboot && ret == 0)
7ca51a3a 12740 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12741 }
12742
2d05eae1 12743 if (ret) {
bf67dfeb
DV		 12744 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12745 set->crtc->base.id, ret);
2d05eae1 12746 }
50f56119 12747
7cbf41d6 12748out:
2bfb4627
ACO		 12749 if (ret)
12750 drm_atomic_state_free(state);
50f56119
DV		 12751 return ret;
12752}
f6e5b160
CW		 12753
12754static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12755 .gamma_set = intel_crtc_gamma_set,
50f56119 12756 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12757 .destroy = intel_crtc_destroy,
12758 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12759 .atomic_duplicate_state = intel_crtc_duplicate_state,
12760 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12761};
12762
5358901f
DV		 12763static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12764 struct intel_shared_dpll *pll,
12765 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12766{
5358901f 12767 uint32_t val;
ee7b9f93 12768
f458ebbc 12769 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12770 return false;
12771
5358901f 12772 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12773 hw_state->dpll = val;
12774 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12775 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12776
12777 return val & DPLL_VCO_ENABLE;
12778}
12779
15bdd4cf
DV		 12780static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12781 struct intel_shared_dpll *pll)
12782{
3e369b76
ACO		 12783 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12784 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12785}
12786
e7b903d2
DV		 12787static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12788 struct intel_shared_dpll *pll)
12789{
e7b903d2 12790 /* PCH refclock must be enabled first */
89eff4be 12791 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12792
3e369b76 12793 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12794
12795 /* Wait for the clocks to stabilize. */
12796 POSTING_READ(PCH_DPLL(pll->id));
12797 udelay(150);
12798
12799 /* The pixel multiplier can only be updated once the
12800 * DPLL is enabled and the clocks are stable.
12801 *
12802 * So write it again.
12803 */
3e369b76 12804 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12805 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12806 udelay(200);
12807}
12808
12809static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12810 struct intel_shared_dpll *pll)
12811{
12812 struct drm_device *dev = dev_priv->dev;
12813 struct intel_crtc *crtc;
e7b903d2
DV		 12814
12815 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12816 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12817 if (intel_crtc_to_shared_dpll(crtc) == pll)
12818 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12819 }
12820
15bdd4cf
DV		 12821 I915_WRITE(PCH_DPLL(pll->id), 0);
12822 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12823 udelay(200);
12824}
12825
46edb027
DV		 12826static char *ibx_pch_dpll_names[] = {
12827 "PCH DPLL A",
12828 "PCH DPLL B",
12829};
12830
7c74ade1 12831static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12832{
e7b903d2 12833 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12834 int i;
12835
7c74ade1 12836 dev_priv->num_shared_dpll = 2;
ee7b9f93 12837
e72f9fbf 12838 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12839 dev_priv->shared_dplls[i].id = i;
12840 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12841 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12842 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12843 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12844 dev_priv->shared_dplls[i].get_hw_state =
12845 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12846 }
12847}
12848
7c74ade1
DV		 12849static void intel_shared_dpll_init(struct drm_device *dev)
12850{
e7b903d2 12851 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12852
9cd86933
DV		 12853 if (HAS_DDI(dev))
12854 intel_ddi_pll_init(dev);
12855 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12856 ibx_pch_dpll_init(dev);
12857 else
12858 dev_priv->num_shared_dpll = 0;
12859
12860 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12861}
12862
1fc0a8f7
TU		 12863/**
12864 * intel_wm_need_update - Check whether watermarks need updating
12865 * @plane: drm plane
12866 * @state: new plane state
12867 *
12868 * Check current plane state versus the new one to determine whether
12869 * watermarks need to be recalculated.
12870 *
12871 * Returns true or false.
12872 */
12873bool intel_wm_need_update(struct drm_plane *plane,
12874 struct drm_plane_state *state)
12875{
12876 /* Update watermarks on tiling changes. */
12877 if (!plane->state->fb || !state->fb ||
12878 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12879 plane->state->rotation != state->rotation)
12880 return true;
12881
12882 return false;
12883}
12884
6beb8c23
MR		 12885/**
12886 * intel_prepare_plane_fb - Prepare fb for usage on plane
12887 * @plane: drm plane to prepare for
12888 * @fb: framebuffer to prepare for presentation
12889 *
12890 * Prepares a framebuffer for usage on a display plane. Generally this
12891 * involves pinning the underlying object and updating the frontbuffer tracking
12892 * bits. Some older platforms need special physical address handling for
12893 * cursor planes.
12894 *
12895 * Returns 0 on success, negative error code on failure.
12896 */
12897int
12898intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12899 struct drm_framebuffer *fb,
12900 const struct drm_plane_state *new_state)
465c120c
MR		 12901{
12902 struct drm_device *dev = plane->dev;
6beb8c23
MR		 12903 struct intel_plane *intel_plane = to_intel_plane(plane);
12904 enum pipe pipe = intel_plane->pipe;
12905 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12906 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12907 unsigned frontbuffer_bits = 0;
12908 int ret = 0;
465c120c 12909
ea2c67bb 12910 if (!obj)
465c120c
MR		 12911 return 0;
12912
6beb8c23
MR		 12913 switch (plane->type) {
12914 case DRM_PLANE_TYPE_PRIMARY:
12915 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12916 break;
12917 case DRM_PLANE_TYPE_CURSOR:
12918 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12919 break;
12920 case DRM_PLANE_TYPE_OVERLAY:
12921 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12922 break;
12923 }
465c120c 12924
6beb8c23 12925 mutex_lock(&dev->struct_mutex);
465c120c 12926
6beb8c23
MR		 12927 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12928 INTEL_INFO(dev)->cursor_needs_physical) {
12929 int align = IS_I830(dev) ? 16 * 1024 : 256;
12930 ret = i915_gem_object_attach_phys(obj, align);
12931 if (ret)
12932 DRM_DEBUG_KMS("failed to attach phys object\n");
12933 } else {
82bc3b2d 12934 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 12935 }
465c120c 12936
6beb8c23
MR		 12937 if (ret == 0)
12938 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 12939
4c34574f 12940 mutex_unlock(&dev->struct_mutex);
465c120c 12941
6beb8c23
MR		 12942 return ret;
12943}
12944
38f3ce3a
MR		 12945/**
12946 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12947 * @plane: drm plane to clean up for
12948 * @fb: old framebuffer that was on plane
12949 *
12950 * Cleans up a framebuffer that has just been removed from a plane.
12951 */
12952void
12953intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12954 struct drm_framebuffer *fb,
12955 const struct drm_plane_state *old_state)
38f3ce3a
MR		 12956{
12957 struct drm_device *dev = plane->dev;
12958 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12959
12960 if (WARN_ON(!obj))
12961 return;
12962
12963 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12964 !INTEL_INFO(dev)->cursor_needs_physical) {
12965 mutex_lock(&dev->struct_mutex);
82bc3b2d 12966 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 12967 mutex_unlock(&dev->struct_mutex);
12968 }
465c120c
MR		 12969}
12970
6156a456
CK		 12971int
12972skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12973{
12974 int max_scale;
12975 struct drm_device *dev;
12976 struct drm_i915_private *dev_priv;
12977 int crtc_clock, cdclk;
12978
12979 if (!intel_crtc || !crtc_state)
12980 return DRM_PLANE_HELPER_NO_SCALING;
12981
12982 dev = intel_crtc->base.dev;
12983 dev_priv = dev->dev_private;
12984 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12985 cdclk = dev_priv->display.get_display_clock_speed(dev);
12986
12987 if (!crtc_clock || !cdclk)
12988 return DRM_PLANE_HELPER_NO_SCALING;
12989
12990 /*
12991 * skl max scale is lower of:
12992 * close to 3 but not 3, -1 is for that purpose
12993 * or
12994 * cdclk/crtc_clock
12995 */
12996 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
12997
12998 return max_scale;
12999}
13000
465c120c 13001static int
3c692a41
GP		 13002intel_check_primary_plane(struct drm_plane *plane,
13003 struct intel_plane_state *state)
13004{
32b7eeec
MR		 13005 struct drm_device *dev = plane->dev;
13006 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13007 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13008 struct intel_crtc *intel_crtc;
6156a456 13009 struct intel_crtc_state *crtc_state;
2b875c22 13010 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13011 struct drm_rect *dest = &state->dst;
13012 struct drm_rect *src = &state->src;
13013 const struct drm_rect *clip = &state->clip;
d8106366 13014 bool can_position = false;
6156a456
CK		 13015 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13016 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13017 int ret;
13018
ea2c67bb
MR		 13019 crtc = crtc ? crtc : plane->crtc;
13020 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13021 crtc_state = state->base.state ?
13022 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13023
6156a456
CK		 13024 if (INTEL_INFO(dev)->gen >= 9) {
13025 min_scale = 1;
13026 max_scale = skl_max_scale(intel_crtc, crtc_state);
d8106366 13027 can_position = true;
6156a456 13028 }
d8106366 13029
c59cb179
MR		 13030 ret = drm_plane_helper_check_update(plane, crtc, fb,
13031 src, dest, clip,
6156a456
CK		 13032 min_scale,
13033 max_scale,
d8106366
SJ		 13034 can_position, true,
13035 &state->visible);
c59cb179
MR		 13036 if (ret)
13037 return ret;
465c120c 13038
32b7eeec 13039 if (intel_crtc->active) {
b70709a6
ML		 13040 struct intel_plane_state *old_state =
13041 to_intel_plane_state(plane->state);
13042
32b7eeec
MR		 13043 intel_crtc->atomic.wait_for_flips = true;
13044
13045 /*
13046 * FBC does not work on some platforms for rotated
13047 * planes, so disable it when rotation is not 0 and
13048 * update it when rotation is set back to 0.
13049 *
13050 * FIXME: This is redundant with the fbc update done in
13051 * the primary plane enable function except that that
13052 * one is done too late. We eventually need to unify
13053 * this.
13054 */
b70709a6 13055 if (state->visible &&
32b7eeec 13056 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13057 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13058 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13059 intel_crtc->atomic.disable_fbc = true;
13060 }
13061
b70709a6 13062 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13063 /*
13064 * BDW signals flip done immediately if the plane
13065 * is disabled, even if the plane enable is already
13066 * armed to occur at the next vblank :(
13067 */
b70709a6 13068 if (IS_BROADWELL(dev))
32b7eeec
MR		 13069 intel_crtc->atomic.wait_vblank = true;
13070 }
13071
13072 intel_crtc->atomic.fb_bits |=
13073 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13074
13075 intel_crtc->atomic.update_fbc = true;
0fda6568 13076
1fc0a8f7 13077 if (intel_wm_need_update(plane, &state->base))
0fda6568 13078 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13079 }
13080
6156a456
CK		 13081 if (INTEL_INFO(dev)->gen >= 9) {
13082 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13083 to_intel_plane(plane), state, 0);
13084 if (ret)
13085 return ret;
13086 }
13087
14af293f
GP		 13088 return 0;
13089}
13090
13091static void
13092intel_commit_primary_plane(struct drm_plane *plane,
13093 struct intel_plane_state *state)
13094{
2b875c22
MR		 13095 struct drm_crtc *crtc = state->base.crtc;
13096 struct drm_framebuffer *fb = state->base.fb;
13097 struct drm_device *dev = plane->dev;
14af293f 13098 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13099 struct intel_crtc *intel_crtc;
14af293f
GP		 13100 struct drm_rect *src = &state->src;
13101
ea2c67bb
MR		 13102 crtc = crtc ? crtc : plane->crtc;
13103 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13104
13105 plane->fb = fb;
9dc806fc
MR		 13106 crtc->x = src->x1 >> 16;
13107 crtc->y = src->y1 >> 16;
ccc759dc 13108
ccc759dc 13109 if (intel_crtc->active) {
27321ae8 13110 if (state->visible)
ccc759dc
GP		 13111 /* FIXME: kill this fastboot hack */
13112 intel_update_pipe_size(intel_crtc);
465c120c 13113
27321ae8
ML		 13114 dev_priv->display.update_primary_plane(crtc, plane->fb,
13115 crtc->x, crtc->y);
ccc759dc 13116 }
465c120c
MR		 13117}
13118
a8ad0d8e
ML		 13119static void
13120intel_disable_primary_plane(struct drm_plane *plane,
13121 struct drm_crtc *crtc,
13122 bool force)
13123{
13124 struct drm_device *dev = plane->dev;
13125 struct drm_i915_private *dev_priv = dev->dev_private;
13126
a8ad0d8e
ML		 13127 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13128}
13129
32b7eeec 13130static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13131{
32b7eeec 13132 struct drm_device *dev = crtc->dev;
140fd38d 13133 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13135 struct intel_plane *intel_plane;
13136 struct drm_plane *p;
13137 unsigned fb_bits = 0;
13138
13139 /* Track fb's for any planes being disabled */
13140 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13141 intel_plane = to_intel_plane(p);
13142
13143 if (intel_crtc->atomic.disabled_planes &
13144 (1 << drm_plane_index(p))) {
13145 switch (p->type) {
13146 case DRM_PLANE_TYPE_PRIMARY:
13147 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13148 break;
13149 case DRM_PLANE_TYPE_CURSOR:
13150 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13151 break;
13152 case DRM_PLANE_TYPE_OVERLAY:
13153 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13154 break;
13155 }
3c692a41 13156
ea2c67bb
MR		 13157 mutex_lock(&dev->struct_mutex);
13158 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13159 mutex_unlock(&dev->struct_mutex);
13160 }
13161 }
3c692a41 13162
32b7eeec
MR		 13163 if (intel_crtc->atomic.wait_for_flips)
13164 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13165
32b7eeec
MR		 13166 if (intel_crtc->atomic.disable_fbc)
13167 intel_fbc_disable(dev);
3c692a41 13168
32b7eeec
MR		 13169 if (intel_crtc->atomic.pre_disable_primary)
13170 intel_pre_disable_primary(crtc);
3c692a41 13171
32b7eeec
MR		 13172 if (intel_crtc->atomic.update_wm)
13173 intel_update_watermarks(crtc);
3c692a41 13174
32b7eeec 13175 intel_runtime_pm_get(dev_priv);
3c692a41 13176
c34c9ee4
MR		 13177 /* Perform vblank evasion around commit operation */
13178 if (intel_crtc->active)
13179 intel_crtc->atomic.evade =
13180 intel_pipe_update_start(intel_crtc,
13181 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13182}
13183
13184static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13185{
13186 struct drm_device *dev = crtc->dev;
13187 struct drm_i915_private *dev_priv = dev->dev_private;
13188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13189 struct drm_plane *p;
13190
c34c9ee4
MR		 13191 if (intel_crtc->atomic.evade)
13192 intel_pipe_update_end(intel_crtc,
13193 intel_crtc->atomic.start_vbl_count);
3c692a41 13194
140fd38d 13195 intel_runtime_pm_put(dev_priv);
3c692a41 13196
32b7eeec
MR		 13197 if (intel_crtc->atomic.wait_vblank)
13198 intel_wait_for_vblank(dev, intel_crtc->pipe);
13199
13200 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13201
13202 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13203 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13204 intel_fbc_update(dev);
ccc759dc 13205 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13206 }
3c692a41 13207
32b7eeec
MR		 13208 if (intel_crtc->atomic.post_enable_primary)
13209 intel_post_enable_primary(crtc);
3c692a41 13210
32b7eeec
MR		 13211 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13212 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13213 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13214 false, false);
13215
13216 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13217}
13218
cf4c7c12 13219/**
4a3b8769
MR		 13220 * intel_plane_destroy - destroy a plane
13221 * @plane: plane to destroy
cf4c7c12 13222 *
4a3b8769
MR		 13223 * Common destruction function for all types of planes (primary, cursor,
13224 * sprite).
cf4c7c12 13225 */
4a3b8769 13226void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13227{
13228 struct intel_plane *intel_plane = to_intel_plane(plane);
13229 drm_plane_cleanup(plane);
13230 kfree(intel_plane);
13231}
13232
65a3fea0 13233const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13234 .update_plane = drm_atomic_helper_update_plane,
13235 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13236 .destroy = intel_plane_destroy,
c196e1d6 13237 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13238 .atomic_get_property = intel_plane_atomic_get_property,
13239 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13240 .atomic_duplicate_state = intel_plane_duplicate_state,
13241 .atomic_destroy_state = intel_plane_destroy_state,
13242
465c120c
MR		 13243};
13244
13245static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13246 int pipe)
13247{
13248 struct intel_plane *primary;
8e7d688b 13249 struct intel_plane_state *state;
465c120c
MR		 13250 const uint32_t *intel_primary_formats;
13251 int num_formats;
13252
13253 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13254 if (primary == NULL)
13255 return NULL;
13256
8e7d688b
MR		 13257 state = intel_create_plane_state(&primary->base);
13258 if (!state) {
ea2c67bb
MR		 13259 kfree(primary);
13260 return NULL;
13261 }
8e7d688b 13262 primary->base.state = &state->base;
ea2c67bb 13263
465c120c
MR		 13264 primary->can_scale = false;
13265 primary->max_downscale = 1;
6156a456
CK		 13266 if (INTEL_INFO(dev)->gen >= 9) {
13267 primary->can_scale = true;
13268 }
549e2bfb 13269 state->scaler_id = -1;
465c120c
MR		 13270 primary->pipe = pipe;
13271 primary->plane = pipe;
c59cb179
MR		 13272 primary->check_plane = intel_check_primary_plane;
13273 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13274 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13275 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13276 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13277 primary->plane = !pipe;
13278
13279 if (INTEL_INFO(dev)->gen <= 3) {
13280 intel_primary_formats = intel_primary_formats_gen2;
13281 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13282 } else {
13283 intel_primary_formats = intel_primary_formats_gen4;
13284 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13285 }
13286
13287 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13288 &intel_plane_funcs,
465c120c
MR		 13289 intel_primary_formats, num_formats,
13290 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13291
3b7a5119
SJ		 13292 if (INTEL_INFO(dev)->gen >= 4)
13293 intel_create_rotation_property(dev, primary);
48404c1e 13294
ea2c67bb
MR		 13295 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13296
465c120c
MR		 13297 return &primary->base;
13298}
13299
3b7a5119
SJ		 13300void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13301{
13302 if (!dev->mode_config.rotation_property) {
13303 unsigned long flags = BIT(DRM_ROTATE_0) |
13304 BIT(DRM_ROTATE_180);
13305
13306 if (INTEL_INFO(dev)->gen >= 9)
13307 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13308
13309 dev->mode_config.rotation_property =
13310 drm_mode_create_rotation_property(dev, flags);
13311 }
13312 if (dev->mode_config.rotation_property)
13313 drm_object_attach_property(&plane->base.base,
13314 dev->mode_config.rotation_property,
13315 plane->base.state->rotation);
13316}
13317
3d7d6510 13318static int
852e787c
GP		 13319intel_check_cursor_plane(struct drm_plane *plane,
13320 struct intel_plane_state *state)
3d7d6510 13321{
2b875c22 13322 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13323 struct drm_device *dev = plane->dev;
2b875c22 13324 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13325 struct drm_rect *dest = &state->dst;
13326 struct drm_rect *src = &state->src;
13327 const struct drm_rect *clip = &state->clip;
757f9a3e 13328 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13329 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13330 unsigned stride;
13331 int ret;
3d7d6510 13332
ea2c67bb
MR		 13333 crtc = crtc ? crtc : plane->crtc;
13334 intel_crtc = to_intel_crtc(crtc);
13335
757f9a3e 13336 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13337 src, dest, clip,
3d7d6510
MR		 13338 DRM_PLANE_HELPER_NO_SCALING,
13339 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13340 true, true, &state->visible);
757f9a3e
GP		 13341 if (ret)
13342 return ret;
13343
13344
13345 /* if we want to turn off the cursor ignore width and height */
13346 if (!obj)
32b7eeec 13347 goto finish;
757f9a3e 13348
757f9a3e 13349 /* Check for which cursor types we support */
ea2c67bb
MR		 13350 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13351 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13352 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13353 return -EINVAL;
13354 }
13355
ea2c67bb
MR		 13356 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13357 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13358 DRM_DEBUG_KMS("buffer is too small\n");
13359 return -ENOMEM;
13360 }
13361
3a656b54 13362 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13363 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13364 ret = -EINVAL;
13365 }
757f9a3e 13366
32b7eeec
MR		 13367finish:
13368 if (intel_crtc->active) {
3749f463 13369 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13370 intel_crtc->atomic.update_wm = true;
13371
13372 intel_crtc->atomic.fb_bits |=
13373 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13374 }
13375
757f9a3e 13376 return ret;
852e787c 13377}
3d7d6510 13378
a8ad0d8e
ML		 13379static void
13380intel_disable_cursor_plane(struct drm_plane *plane,
13381 struct drm_crtc *crtc,
13382 bool force)
13383{
13384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13385
13386 if (!force) {
13387 plane->fb = NULL;
13388 intel_crtc->cursor_bo = NULL;
13389 intel_crtc->cursor_addr = 0;
13390 }
13391
13392 intel_crtc_update_cursor(crtc, false);
13393}
13394
f4a2cf29 13395static void
852e787c
GP		 13396intel_commit_cursor_plane(struct drm_plane *plane,
13397 struct intel_plane_state *state)
13398{
2b875c22 13399 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13400 struct drm_device *dev = plane->dev;
13401 struct intel_crtc *intel_crtc;
2b875c22 13402 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13403 uint32_t addr;
852e787c 13404
ea2c67bb
MR		 13405 crtc = crtc ? crtc : plane->crtc;
13406 intel_crtc = to_intel_crtc(crtc);
13407
2b875c22 13408 plane->fb = state->base.fb;
ea2c67bb
MR		 13409 crtc->cursor_x = state->base.crtc_x;
13410 crtc->cursor_y = state->base.crtc_y;
13411
a912f12f
GP		 13412 if (intel_crtc->cursor_bo == obj)
13413 goto update;
4ed91096 13414
f4a2cf29 13415 if (!obj)
a912f12f 13416 addr = 0;
f4a2cf29 13417 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13418 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13419 else
a912f12f 13420 addr = obj->phys_handle->busaddr;
852e787c 13421
a912f12f
GP		 13422 intel_crtc->cursor_addr = addr;
13423 intel_crtc->cursor_bo = obj;
13424update:
852e787c 13425
32b7eeec 13426 if (intel_crtc->active)
a912f12f 13427 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13428}
13429
3d7d6510
MR		 13430static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13431 int pipe)
13432{
13433 struct intel_plane *cursor;
8e7d688b 13434 struct intel_plane_state *state;
3d7d6510
MR		 13435
13436 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13437 if (cursor == NULL)
13438 return NULL;
13439
8e7d688b
MR		 13440 state = intel_create_plane_state(&cursor->base);
13441 if (!state) {
ea2c67bb
MR		 13442 kfree(cursor);
13443 return NULL;
13444 }
8e7d688b 13445 cursor->base.state = &state->base;
ea2c67bb 13446
3d7d6510
MR		 13447 cursor->can_scale = false;
13448 cursor->max_downscale = 1;
13449 cursor->pipe = pipe;
13450 cursor->plane = pipe;
549e2bfb 13451 state->scaler_id = -1;
c59cb179
MR		 13452 cursor->check_plane = intel_check_cursor_plane;
13453 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13454 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13455
13456 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13457 &intel_plane_funcs,
3d7d6510
MR		 13458 intel_cursor_formats,
13459 ARRAY_SIZE(intel_cursor_formats),
13460 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13461
13462 if (INTEL_INFO(dev)->gen >= 4) {
13463 if (!dev->mode_config.rotation_property)
13464 dev->mode_config.rotation_property =
13465 drm_mode_create_rotation_property(dev,
13466 BIT(DRM_ROTATE_0) |
13467 BIT(DRM_ROTATE_180));
13468 if (dev->mode_config.rotation_property)
13469 drm_object_attach_property(&cursor->base.base,
13470 dev->mode_config.rotation_property,
8e7d688b 13471 state->base.rotation);
4398ad45
VS		 13472 }
13473
ea2c67bb
MR		 13474 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13475
3d7d6510
MR		 13476 return &cursor->base;
13477}
13478
549e2bfb
CK		 13479static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13480 struct intel_crtc_state *crtc_state)
13481{
13482 int i;
13483 struct intel_scaler *intel_scaler;
13484 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13485
13486 for (i = 0; i < intel_crtc->num_scalers; i++) {
13487 intel_scaler = &scaler_state->scalers[i];
13488 intel_scaler->in_use = 0;
13489 intel_scaler->id = i;
13490
13491 intel_scaler->mode = PS_SCALER_MODE_DYN;
13492 }
13493
13494 scaler_state->scaler_id = -1;
13495}
13496
b358d0a6 13497static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13498{
fbee40df 13499 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13500 struct intel_crtc *intel_crtc;
f5de6e07 13501 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13502 struct drm_plane *primary = NULL;
13503 struct drm_plane *cursor = NULL;
465c120c 13504 int i, ret;
79e53945 13505
955382f3 13506 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13507 if (intel_crtc == NULL)
13508 return;
13509
f5de6e07
ACO		 13510 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13511 if (!crtc_state)
13512 goto fail;
550acefd
ACO		 13513 intel_crtc->config = crtc_state;
13514 intel_crtc->base.state = &crtc_state->base;
07878248 13515 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13516
549e2bfb
CK		 13517 /* initialize shared scalers */
13518 if (INTEL_INFO(dev)->gen >= 9) {
13519 if (pipe == PIPE_C)
13520 intel_crtc->num_scalers = 1;
13521 else
13522 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13523
13524 skl_init_scalers(dev, intel_crtc, crtc_state);
13525 }
13526
465c120c 13527 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13528 if (!primary)
13529 goto fail;
13530
13531 cursor = intel_cursor_plane_create(dev, pipe);
13532 if (!cursor)
13533 goto fail;
13534
465c120c 13535 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13536 cursor, &intel_crtc_funcs);
13537 if (ret)
13538 goto fail;
79e53945
JB		 13539
13540 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13541 for (i = 0; i < 256; i++) {
13542 intel_crtc->lut_r[i] = i;
13543 intel_crtc->lut_g[i] = i;
13544 intel_crtc->lut_b[i] = i;
13545 }
13546
1f1c2e24
VS		 13547 /*
13548 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13549 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13550 */
80824003
JB		 13551 intel_crtc->pipe = pipe;
13552 intel_crtc->plane = pipe;
3a77c4c4 13553 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13554 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13555 intel_crtc->plane = !pipe;
80824003
JB		 13556 }
13557
4b0e333e
CW		 13558 intel_crtc->cursor_base = ~0;
13559 intel_crtc->cursor_cntl = ~0;
dc41c154 13560 intel_crtc->cursor_size = ~0;
8d7849db 13561
22fd0fab
JB		 13562 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13563 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13564 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13565 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13566
9362c7c5
ACO		 13567 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13568
79e53945 13569 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13570
13571 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13572 return;
13573
13574fail:
13575 if (primary)
13576 drm_plane_cleanup(primary);
13577 if (cursor)
13578 drm_plane_cleanup(cursor);
f5de6e07 13579 kfree(crtc_state);
3d7d6510 13580 kfree(intel_crtc);
79e53945
JB		 13581}
13582
752aa88a
JB		 13583enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13584{
13585 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13586 struct drm_device *dev = connector->base.dev;
752aa88a 13587
51fd371b 13588 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13589
d3babd3f 13590 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13591 return INVALID_PIPE;
13592
13593 return to_intel_crtc(encoder->crtc)->pipe;
13594}
13595
08d7b3d1 13596int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13597 struct drm_file *file)
08d7b3d1 13598{
08d7b3d1 13599 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13600 struct drm_crtc *drmmode_crtc;
c05422d5 13601 struct intel_crtc *crtc;
08d7b3d1 13602
7707e653 13603 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13604
7707e653 13605 if (!drmmode_crtc) {
08d7b3d1 13606 DRM_ERROR("no such CRTC id\n");
3f2c2057 13607 return -ENOENT;
08d7b3d1
CW		 13608 }
13609
7707e653 13610 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13611 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13612
c05422d5 13613 return 0;
08d7b3d1
CW		 13614}
13615
66a9278e 13616static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13617{
66a9278e
DV		 13618 struct drm_device *dev = encoder->base.dev;
13619 struct intel_encoder *source_encoder;
79e53945 13620 int index_mask = 0;
79e53945
JB		 13621 int entry = 0;
13622
b2784e15 13623 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13624 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13625 index_mask |= (1 << entry);
13626
79e53945
JB		 13627 entry++;
13628 }
4ef69c7a 13629
79e53945
JB		 13630 return index_mask;
13631}
13632
4d302442
CW		 13633static bool has_edp_a(struct drm_device *dev)
13634{
13635 struct drm_i915_private *dev_priv = dev->dev_private;
13636
13637 if (!IS_MOBILE(dev))
13638 return false;
13639
13640 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13641 return false;
13642
e3589908 13643 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13644 return false;
13645
13646 return true;
13647}
13648
84b4e042
JB		 13649static bool intel_crt_present(struct drm_device *dev)
13650{
13651 struct drm_i915_private *dev_priv = dev->dev_private;
13652
884497ed
DL		 13653 if (INTEL_INFO(dev)->gen >= 9)
13654 return false;
13655
cf404ce4 13656 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13657 return false;
13658
13659 if (IS_CHERRYVIEW(dev))
13660 return false;
13661
13662 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13663 return false;
13664
13665 return true;
13666}
13667
79e53945
JB		 13668static void intel_setup_outputs(struct drm_device *dev)
13669{
725e30ad 13670 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13671 struct intel_encoder *encoder;
cb0953d7 13672 bool dpd_is_edp = false;
79e53945 13673
c9093354 13674 intel_lvds_init(dev);
79e53945 13675
84b4e042 13676 if (intel_crt_present(dev))
79935fca 13677 intel_crt_init(dev);
cb0953d7 13678
c776eb2e
VK		 13679 if (IS_BROXTON(dev)) {
13680 /*
13681 * FIXME: Broxton doesn't support port detection via the
13682 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13683 * detect the ports.
13684 */
13685 intel_ddi_init(dev, PORT_A);
13686 intel_ddi_init(dev, PORT_B);
13687 intel_ddi_init(dev, PORT_C);
13688 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13689 int found;
13690
de31facd
JB		 13691 /*
13692 * Haswell uses DDI functions to detect digital outputs.
13693 * On SKL pre-D0 the strap isn't connected, so we assume
13694 * it's there.
13695 */
0e72a5b5 13696 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13697 /* WaIgnoreDDIAStrap: skl */
13698 if (found ||
13699 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13700 intel_ddi_init(dev, PORT_A);
13701
13702 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13703 * register */
13704 found = I915_READ(SFUSE_STRAP);
13705
13706 if (found & SFUSE_STRAP_DDIB_DETECTED)
13707 intel_ddi_init(dev, PORT_B);
13708 if (found & SFUSE_STRAP_DDIC_DETECTED)
13709 intel_ddi_init(dev, PORT_C);
13710 if (found & SFUSE_STRAP_DDID_DETECTED)
13711 intel_ddi_init(dev, PORT_D);
13712 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13713 int found;
5d8a7752 13714 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13715
13716 if (has_edp_a(dev))
13717 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13718
dc0fa718 13719 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13720 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13721 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13722 if (!found)
e2debe91 13723 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13724 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13725 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13726 }
13727
dc0fa718 13728 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13729 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13730
dc0fa718 13731 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13732 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13733
5eb08b69 13734 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13735 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13736
270b3042 13737 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13738 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13739 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13740 /*
13741 * The DP_DETECTED bit is the latched state of the DDC
13742 * SDA pin at boot. However since eDP doesn't require DDC
13743 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13744 * eDP ports may have been muxed to an alternate function.
13745 * Thus we can't rely on the DP_DETECTED bit alone to detect
13746 * eDP ports. Consult the VBT as well as DP_DETECTED to
13747 * detect eDP ports.
13748 */
d2182a66
VS		 13749 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13750 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13751 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13752 PORT_B);
e17ac6db
VS		 13753 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13754 intel_dp_is_edp(dev, PORT_B))
13755 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13756
d2182a66
VS		 13757 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13758 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13759 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13760 PORT_C);
e17ac6db
VS		 13761 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13762 intel_dp_is_edp(dev, PORT_C))
13763 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13764
9418c1f1 13765 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13766 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13767 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13768 PORT_D);
e17ac6db
VS		 13769 /* eDP not supported on port D, so don't check VBT */
13770 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13771 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13772 }
13773
3cfca973 13774 intel_dsi_init(dev);
103a196f 13775 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13776 bool found = false;
7d57382e 13777
e2debe91 13778 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13779 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13780 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13781 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13782 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13783 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13784 }
27185ae1 13785
e7281eab 13786 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13787 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13788 }
13520b05
KH		 13789
13790 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13791
e2debe91 13792 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13793 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13794 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13795 }
27185ae1 13796
e2debe91 13797 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13798
b01f2c3a
JB		 13799 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13800 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13801 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13802 }
e7281eab 13803 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13804 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13805 }
27185ae1 13806
b01f2c3a 13807 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13808 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13809 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13810 } else if (IS_GEN2(dev))
79e53945
JB		 13811 intel_dvo_init(dev);
13812
103a196f 13813 if (SUPPORTS_TV(dev))
79e53945
JB		 13814 intel_tv_init(dev);
13815
0bc12bcb 13816 intel_psr_init(dev);
7c8f8a70 13817
b2784e15 13818 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13819 encoder->base.possible_crtcs = encoder->crtc_mask;
13820 encoder->base.possible_clones =
66a9278e 13821 intel_encoder_clones(encoder);
79e53945 13822 }
47356eb6 13823
dde86e2d 13824 intel_init_pch_refclk(dev);
270b3042
DV		 13825
13826 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13827}
13828
13829static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13830{
60a5ca01 13831 struct drm_device *dev = fb->dev;
79e53945 13832 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13833
ef2d633e 13834 drm_framebuffer_cleanup(fb);
60a5ca01 13835 mutex_lock(&dev->struct_mutex);
ef2d633e 13836 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13837 drm_gem_object_unreference(&intel_fb->obj->base);
13838 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13839 kfree(intel_fb);
13840}
13841
13842static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13843 struct drm_file *file,
79e53945
JB		 13844 unsigned int *handle)
13845{
13846 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13847 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13848
05394f39 13849 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13850}
13851
13852static const struct drm_framebuffer_funcs intel_fb_funcs = {
13853 .destroy = intel_user_framebuffer_destroy,
13854 .create_handle = intel_user_framebuffer_create_handle,
13855};
13856
b321803d
DL		 13857static
13858u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13859 uint32_t pixel_format)
13860{
13861 u32 gen = INTEL_INFO(dev)->gen;
13862
13863 if (gen >= 9) {
13864 /* "The stride in bytes must not exceed the of the size of 8K
13865 * pixels and 32K bytes."
13866 */
13867 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13868 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13869 return 32*1024;
13870 } else if (gen >= 4) {
13871 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13872 return 16*1024;
13873 else
13874 return 32*1024;
13875 } else if (gen >= 3) {
13876 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13877 return 8*1024;
13878 else
13879 return 16*1024;
13880 } else {
13881 /* XXX DSPC is limited to 4k tiled */
13882 return 8*1024;
13883 }
13884}
13885
b5ea642a
DV		 13886static int intel_framebuffer_init(struct drm_device *dev,
13887 struct intel_framebuffer *intel_fb,
13888 struct drm_mode_fb_cmd2 *mode_cmd,
13889 struct drm_i915_gem_object *obj)
79e53945 13890{
6761dd31 13891 unsigned int aligned_height;
79e53945 13892 int ret;
b321803d 13893 u32 pitch_limit, stride_alignment;
79e53945 13894
dd4916c5
DV		 13895 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13896
2a80eada
DV		 13897 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13898 /* Enforce that fb modifier and tiling mode match, but only for
13899 * X-tiled. This is needed for FBC. */
13900 if (!!(obj->tiling_mode == I915_TILING_X) !=
13901 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13902 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13903 return -EINVAL;
13904 }
13905 } else {
13906 if (obj->tiling_mode == I915_TILING_X)
13907 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13908 else if (obj->tiling_mode == I915_TILING_Y) {
13909 DRM_DEBUG("No Y tiling for legacy addfb\n");
13910 return -EINVAL;
13911 }
13912 }
13913
9a8f0a12
TU		 13914 /* Passed in modifier sanity checking. */
13915 switch (mode_cmd->modifier[0]) {
13916 case I915_FORMAT_MOD_Y_TILED:
13917 case I915_FORMAT_MOD_Yf_TILED:
13918 if (INTEL_INFO(dev)->gen < 9) {
13919 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13920 mode_cmd->modifier[0]);
13921 return -EINVAL;
13922 }
13923 case DRM_FORMAT_MOD_NONE:
13924 case I915_FORMAT_MOD_X_TILED:
13925 break;
13926 default:
c0f40428
JB		 13927 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13928 mode_cmd->modifier[0]);
57cd6508 13929 return -EINVAL;
c16ed4be 13930 }
57cd6508 13931
b321803d
DL		 13932 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13933 mode_cmd->pixel_format);
13934 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13935 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13936 mode_cmd->pitches[0], stride_alignment);
57cd6508 13937 return -EINVAL;
c16ed4be 13938 }
57cd6508 13939
b321803d
DL		 13940 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13941 mode_cmd->pixel_format);
a35cdaa0 13942 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13943 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13944 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13945 "tiled" : "linear",
a35cdaa0 13946 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13947 return -EINVAL;
c16ed4be 13948 }
5d7bd705 13949
2a80eada 13950 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13951 mode_cmd->pitches[0] != obj->stride) {
13952 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13953 mode_cmd->pitches[0], obj->stride);
5d7bd705 13954 return -EINVAL;
c16ed4be 13955 }
5d7bd705 13956
57779d06 13957 /* Reject formats not supported by any plane early. */
308e5bcb 13958 switch (mode_cmd->pixel_format) {
57779d06 13959 case DRM_FORMAT_C8:
04b3924d
VS		 13960 case DRM_FORMAT_RGB565:
13961 case DRM_FORMAT_XRGB8888:
13962 case DRM_FORMAT_ARGB8888:
57779d06
VS		 13963 break;
13964 case DRM_FORMAT_XRGB1555:
13965 case DRM_FORMAT_ARGB1555:
c16ed4be 13966 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 13967 DRM_DEBUG("unsupported pixel format: %s\n",
13968 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13969 return -EINVAL;
c16ed4be 13970 }
57779d06
VS		 13971 break;
13972 case DRM_FORMAT_XBGR8888:
13973 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 13974 case DRM_FORMAT_XRGB2101010:
13975 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 13976 case DRM_FORMAT_XBGR2101010:
13977 case DRM_FORMAT_ABGR2101010:
c16ed4be 13978 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 13979 DRM_DEBUG("unsupported pixel format: %s\n",
13980 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13981 return -EINVAL;
c16ed4be 13982 }
b5626747 13983 break;
04b3924d
VS		 13984 case DRM_FORMAT_YUYV:
13985 case DRM_FORMAT_UYVY:
13986 case DRM_FORMAT_YVYU:
13987 case DRM_FORMAT_VYUY:
c16ed4be 13988 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 13989 DRM_DEBUG("unsupported pixel format: %s\n",
13990 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13991 return -EINVAL;
c16ed4be 13992 }
57cd6508
CW		 13993 break;
13994 default:
4ee62c76
VS		 13995 DRM_DEBUG("unsupported pixel format: %s\n",
13996 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 13997 return -EINVAL;
13998 }
13999
90f9a336
VS		 14000 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14001 if (mode_cmd->offsets[0] != 0)
14002 return -EINVAL;
14003
ec2c981e 14004 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14005 mode_cmd->pixel_format,
14006 mode_cmd->modifier[0]);
53155c0a
DV		 14007 /* FIXME drm helper for size checks (especially planar formats)? */
14008 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14009 return -EINVAL;
14010
c7d73f6a
DV		 14011 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14012 intel_fb->obj = obj;
80075d49 14013 intel_fb->obj->framebuffer_references++;
c7d73f6a 14014
79e53945
JB		 14015 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14016 if (ret) {
14017 DRM_ERROR("framebuffer init failed %d\n", ret);
14018 return ret;
14019 }
14020
79e53945
JB		 14021 return 0;
14022}
14023
79e53945
JB		 14024static struct drm_framebuffer *
14025intel_user_framebuffer_create(struct drm_device *dev,
14026 struct drm_file *filp,
308e5bcb 14027 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14028{
05394f39 14029 struct drm_i915_gem_object *obj;
79e53945 14030
308e5bcb
JB		 14031 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14032 mode_cmd->handles[0]));
c8725226 14033 if (&obj->base == NULL)
cce13ff7 14034 return ERR_PTR(-ENOENT);
79e53945 14035
d2dff872 14036 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14037}
14038
4520f53a 14039#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14040static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14041{
14042}
14043#endif
14044
79e53945 14045static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14046 .fb_create = intel_user_framebuffer_create,
0632fef6 14047 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14048 .atomic_check = intel_atomic_check,
14049 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14050};
14051
e70236a8
JB		 14052/* Set up chip specific display functions */
14053static void intel_init_display(struct drm_device *dev)
14054{
14055 struct drm_i915_private *dev_priv = dev->dev_private;
14056
ee9300bb
DV		 14057 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14058 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14059 else if (IS_CHERRYVIEW(dev))
14060 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14061 else if (IS_VALLEYVIEW(dev))
14062 dev_priv->display.find_dpll = vlv_find_best_dpll;
14063 else if (IS_PINEVIEW(dev))
14064 dev_priv->display.find_dpll = pnv_find_best_dpll;
14065 else
14066 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14067
bc8d7dff
DL		 14068 if (INTEL_INFO(dev)->gen >= 9) {
14069 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14070 dev_priv->display.get_initial_plane_config =
14071 skylake_get_initial_plane_config;
bc8d7dff
DL		 14072 dev_priv->display.crtc_compute_clock =
14073 haswell_crtc_compute_clock;
14074 dev_priv->display.crtc_enable = haswell_crtc_enable;
14075 dev_priv->display.crtc_disable = haswell_crtc_disable;
14076 dev_priv->display.off = ironlake_crtc_off;
14077 dev_priv->display.update_primary_plane =
14078 skylake_update_primary_plane;
14079 } else if (HAS_DDI(dev)) {
0e8ffe1b 14080 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14081 dev_priv->display.get_initial_plane_config =
14082 ironlake_get_initial_plane_config;
797d0259
ACO		 14083 dev_priv->display.crtc_compute_clock =
14084 haswell_crtc_compute_clock;
4f771f10
PZ		 14085 dev_priv->display.crtc_enable = haswell_crtc_enable;
14086 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14087 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14088 dev_priv->display.update_primary_plane =
14089 ironlake_update_primary_plane;
09b4ddf9 14090 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14091 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14092 dev_priv->display.get_initial_plane_config =
14093 ironlake_get_initial_plane_config;
3fb37703
ACO		 14094 dev_priv->display.crtc_compute_clock =
14095 ironlake_crtc_compute_clock;
76e5a89c
DV		 14096 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14097 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14098 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14099 dev_priv->display.update_primary_plane =
14100 ironlake_update_primary_plane;
89b667f8
JB		 14101 } else if (IS_VALLEYVIEW(dev)) {
14102 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14103 dev_priv->display.get_initial_plane_config =
14104 i9xx_get_initial_plane_config;
d6dfee7a 14105 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14106 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14107 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14108 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14109 dev_priv->display.update_primary_plane =
14110 i9xx_update_primary_plane;
f564048e 14111 } else {
0e8ffe1b 14112 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14113 dev_priv->display.get_initial_plane_config =
14114 i9xx_get_initial_plane_config;
d6dfee7a 14115 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14116 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14117 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14118 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14119 dev_priv->display.update_primary_plane =
14120 i9xx_update_primary_plane;
f564048e 14121 }
e70236a8 14122
e70236a8 14123 /* Returns the core display clock speed */
1652d19e
VS		 14124 if (IS_SKYLAKE(dev))
14125 dev_priv->display.get_display_clock_speed =
14126 skylake_get_display_clock_speed;
14127 else if (IS_BROADWELL(dev))
14128 dev_priv->display.get_display_clock_speed =
14129 broadwell_get_display_clock_speed;
14130 else if (IS_HASWELL(dev))
14131 dev_priv->display.get_display_clock_speed =
14132 haswell_get_display_clock_speed;
14133 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14134 dev_priv->display.get_display_clock_speed =
14135 valleyview_get_display_clock_speed;
b37a6434
VS		 14136 else if (IS_GEN5(dev))
14137 dev_priv->display.get_display_clock_speed =
14138 ilk_get_display_clock_speed;
a7c66cd8
VS		 14139 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14140 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14141 dev_priv->display.get_display_clock_speed =
14142 i945_get_display_clock_speed;
14143 else if (IS_I915G(dev))
14144 dev_priv->display.get_display_clock_speed =
14145 i915_get_display_clock_speed;
257a7ffc 14146 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14147 dev_priv->display.get_display_clock_speed =
14148 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14149 else if (IS_PINEVIEW(dev))
14150 dev_priv->display.get_display_clock_speed =
14151 pnv_get_display_clock_speed;
e70236a8
JB		 14152 else if (IS_I915GM(dev))
14153 dev_priv->display.get_display_clock_speed =
14154 i915gm_get_display_clock_speed;
14155 else if (IS_I865G(dev))
14156 dev_priv->display.get_display_clock_speed =
14157 i865_get_display_clock_speed;
f0f8a9ce 14158 else if (IS_I85X(dev))
e70236a8
JB		 14159 dev_priv->display.get_display_clock_speed =
14160 i855_get_display_clock_speed;
14161 else /* 852, 830 */
14162 dev_priv->display.get_display_clock_speed =
14163 i830_get_display_clock_speed;
14164
7c10a2b5 14165 if (IS_GEN5(dev)) {
3bb11b53 14166 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14167 } else if (IS_GEN6(dev)) {
14168 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14169 } else if (IS_IVYBRIDGE(dev)) {
14170 /* FIXME: detect B0+ stepping and use auto training */
14171 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14172 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14173 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14174 } else if (IS_VALLEYVIEW(dev)) {
14175 dev_priv->display.modeset_global_resources =
14176 valleyview_modeset_global_resources;
f8437dd1
VK		 14177 } else if (IS_BROXTON(dev)) {
14178 dev_priv->display.modeset_global_resources =
14179 broxton_modeset_global_resources;
e70236a8 14180 }
8c9f3aaf 14181
8c9f3aaf
JB		 14182 switch (INTEL_INFO(dev)->gen) {
14183 case 2:
14184 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14185 break;
14186
14187 case 3:
14188 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14189 break;
14190
14191 case 4:
14192 case 5:
14193 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14194 break;
14195
14196 case 6:
14197 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14198 break;
7c9017e5 14199 case 7:
4e0bbc31 14200 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14201 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14202 break;
830c81db 14203 case 9:
ba343e02
TU		 14204 /* Drop through - unsupported since execlist only. */
14205 default:
14206 /* Default just returns -ENODEV to indicate unsupported */
14207 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14208 }
7bd688cd
JN		 14209
14210 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14211
14212 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14213}
14214
b690e96c
JB		 14215/*
14216 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14217 * resume, or other times. This quirk makes sure that's the case for
14218 * affected systems.
14219 */
0206e353 14220static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14221{
14222 struct drm_i915_private *dev_priv = dev->dev_private;
14223
14224 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14225 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14226}
14227
b6b5d049
VS		 14228static void quirk_pipeb_force(struct drm_device *dev)
14229{
14230 struct drm_i915_private *dev_priv = dev->dev_private;
14231
14232 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14233 DRM_INFO("applying pipe b force quirk\n");
14234}
14235
435793df
KP		 14236/*
14237 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14238 */
14239static void quirk_ssc_force_disable(struct drm_device *dev)
14240{
14241 struct drm_i915_private *dev_priv = dev->dev_private;
14242 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14243 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14244}
14245
4dca20ef 14246/*
5a15ab5b
CE		 14247 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14248 * brightness value
4dca20ef
CE		 14249 */
14250static void quirk_invert_brightness(struct drm_device *dev)
14251{
14252 struct drm_i915_private *dev_priv = dev->dev_private;
14253 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14254 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14255}
14256
9c72cc6f
SD		 14257/* Some VBT's incorrectly indicate no backlight is present */
14258static void quirk_backlight_present(struct drm_device *dev)
14259{
14260 struct drm_i915_private *dev_priv = dev->dev_private;
14261 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14262 DRM_INFO("applying backlight present quirk\n");
14263}
14264
b690e96c
JB		 14265struct intel_quirk {
14266 int device;
14267 int subsystem_vendor;
14268 int subsystem_device;
14269 void (*hook)(struct drm_device *dev);
14270};
14271
5f85f176
EE		 14272/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14273struct intel_dmi_quirk {
14274 void (*hook)(struct drm_device *dev);
14275 const struct dmi_system_id (*dmi_id_list)[];
14276};
14277
14278static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14279{
14280 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14281 return 1;
14282}
14283
14284static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14285 {
14286 .dmi_id_list = &(const struct dmi_system_id[]) {
14287 {
14288 .callback = intel_dmi_reverse_brightness,
14289 .ident = "NCR Corporation",
14290 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14291 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14292 },
14293 },
14294 { } /* terminating entry */
14295 },
14296 .hook = quirk_invert_brightness,
14297 },
14298};
14299
c43b5634 14300static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14301 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14302 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14303
b690e96c
JB		 14304 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14305 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14306
5f080c0f
VS		 14307 /* 830 needs to leave pipe A & dpll A up */
14308 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14309
b6b5d049
VS		 14310 /* 830 needs to leave pipe B & dpll B up */
14311 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14312
435793df
KP		 14313 /* Lenovo U160 cannot use SSC on LVDS */
14314 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14315
14316 /* Sony Vaio Y cannot use SSC on LVDS */
14317 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14318
be505f64
AH		 14319 /* Acer Aspire 5734Z must invert backlight brightness */
14320 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14321
14322 /* Acer/eMachines G725 */
14323 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14324
14325 /* Acer/eMachines e725 */
14326 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14327
14328 /* Acer/Packard Bell NCL20 */
14329 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14330
14331 /* Acer Aspire 4736Z */
14332 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14333
14334 /* Acer Aspire 5336 */
14335 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14336
14337 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14338 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14339
dfb3d47b
SD		 14340 /* Acer C720 Chromebook (Core i3 4005U) */
14341 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14342
b2a9601c 14343 /* Apple Macbook 2,1 (Core 2 T7400) */
14344 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14345
d4967d8c
SD		 14346 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14347 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14348
14349 /* HP Chromebook 14 (Celeron 2955U) */
14350 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14351
14352 /* Dell Chromebook 11 */
14353 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14354};
14355
14356static void intel_init_quirks(struct drm_device *dev)
14357{
14358 struct pci_dev *d = dev->pdev;
14359 int i;
14360
14361 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14362 struct intel_quirk *q = &intel_quirks[i];
14363
14364 if (d->device == q->device &&
14365 (d->subsystem_vendor == q->subsystem_vendor ||
14366 q->subsystem_vendor == PCI_ANY_ID) &&
14367 (d->subsystem_device == q->subsystem_device ||
14368 q->subsystem_device == PCI_ANY_ID))
14369 q->hook(dev);
14370 }
5f85f176
EE		 14371 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14372 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14373 intel_dmi_quirks[i].hook(dev);
14374 }
b690e96c
JB		 14375}
14376
9cce37f4
JB		 14377/* Disable the VGA plane that we never use */
14378static void i915_disable_vga(struct drm_device *dev)
14379{
14380 struct drm_i915_private *dev_priv = dev->dev_private;
14381 u8 sr1;
766aa1c4 14382 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14383
2b37c616 14384 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14385 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14386 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14387 sr1 = inb(VGA_SR_DATA);
14388 outb(sr1 | 1<<5, VGA_SR_DATA);
14389 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14390 udelay(300);
14391
01f5a626 14392 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14393 POSTING_READ(vga_reg);
14394}
14395
f817586c
DV		 14396void intel_modeset_init_hw(struct drm_device *dev)
14397{
a8f78b58
ED		 14398 intel_prepare_ddi(dev);
14399
f8bf63fd
VS		 14400 if (IS_VALLEYVIEW(dev))
14401 vlv_update_cdclk(dev);
14402
f817586c
DV		 14403 intel_init_clock_gating(dev);
14404
8090c6b9 14405 intel_enable_gt_powersave(dev);
f817586c
DV		 14406}
14407
79e53945
JB		 14408void intel_modeset_init(struct drm_device *dev)
14409{
652c393a 14410 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14411 int sprite, ret;
8cc87b75 14412 enum pipe pipe;
46f297fb 14413 struct intel_crtc *crtc;
79e53945
JB		 14414
14415 drm_mode_config_init(dev);
14416
14417 dev->mode_config.min_width = 0;
14418 dev->mode_config.min_height = 0;
14419
019d96cb
DA		 14420 dev->mode_config.preferred_depth = 24;
14421 dev->mode_config.prefer_shadow = 1;
14422
25bab385
TU		 14423 dev->mode_config.allow_fb_modifiers = true;
14424
e6ecefaa 14425 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14426
b690e96c
JB		 14427 intel_init_quirks(dev);
14428
1fa61106
ED		 14429 intel_init_pm(dev);
14430
e3c74757
BW		 14431 if (INTEL_INFO(dev)->num_pipes == 0)
14432 return;
14433
e70236a8 14434 intel_init_display(dev);
7c10a2b5 14435 intel_init_audio(dev);
e70236a8 14436
a6c45cf0
CW		 14437 if (IS_GEN2(dev)) {
14438 dev->mode_config.max_width = 2048;
14439 dev->mode_config.max_height = 2048;
14440 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14441 dev->mode_config.max_width = 4096;
14442 dev->mode_config.max_height = 4096;
79e53945 14443 } else {
a6c45cf0
CW		 14444 dev->mode_config.max_width = 8192;
14445 dev->mode_config.max_height = 8192;
79e53945 14446 }
068be561 14447
dc41c154
VS		 14448 if (IS_845G(dev) || IS_I865G(dev)) {
14449 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14450 dev->mode_config.cursor_height = 1023;
14451 } else if (IS_GEN2(dev)) {
068be561
DL		 14452 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14453 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14454 } else {
14455 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14456 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14457 }
14458
5d4545ae 14459 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14460
28c97730 14461 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14462 INTEL_INFO(dev)->num_pipes,
14463 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14464
055e393f 14465 for_each_pipe(dev_priv, pipe) {
8cc87b75 14466 intel_crtc_init(dev, pipe);
3bdcfc0c 14467 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14468 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14469 if (ret)
06da8da2 14470 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14471 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14472 }
79e53945
JB		 14473 }
14474
f42bb70d
JB		 14475 intel_init_dpio(dev);
14476
e72f9fbf 14477 intel_shared_dpll_init(dev);
ee7b9f93 14478
9cce37f4
JB		 14479 /* Just disable it once at startup */
14480 i915_disable_vga(dev);
79e53945 14481 intel_setup_outputs(dev);
11be49eb
CW		 14482
14483 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14484 intel_fbc_disable(dev);
fa9fa083 14485
6e9f798d 14486 drm_modeset_lock_all(dev);
fa9fa083 14487 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14488 drm_modeset_unlock_all(dev);
46f297fb 14489
d3fcc808 14490 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14491 if (!crtc->active)
14492 continue;
14493
46f297fb 14494 /*
46f297fb
JB		 14495 * Note that reserving the BIOS fb up front prevents us
14496 * from stuffing other stolen allocations like the ring
14497 * on top. This prevents some ugliness at boot time, and
14498 * can even allow for smooth boot transitions if the BIOS
14499 * fb is large enough for the active pipe configuration.
14500 */
5724dbd1
DL		 14501 if (dev_priv->display.get_initial_plane_config) {
14502 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14503 &crtc->plane_config);
14504 /*
14505 * If the fb is shared between multiple heads, we'll
14506 * just get the first one.
14507 */
f6936e29 14508 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14509 }
46f297fb 14510 }
2c7111db
CW		 14511}
14512
7fad798e
DV		 14513static void intel_enable_pipe_a(struct drm_device *dev)
14514{
14515 struct intel_connector *connector;
14516 struct drm_connector *crt = NULL;
14517 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14518 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14519
14520 /* We can't just switch on the pipe A, we need to set things up with a
14521 * proper mode and output configuration. As a gross hack, enable pipe A
14522 * by enabling the load detect pipe once. */
3a3371ff 14523 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14524 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14525 crt = &connector->base;
14526 break;
14527 }
14528 }
14529
14530 if (!crt)
14531 return;
14532
208bf9fd 14533 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14534 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14535}
14536
fa555837
DV		 14537static bool
14538intel_check_plane_mapping(struct intel_crtc *crtc)
14539{
7eb552ae
BW		 14540 struct drm_device *dev = crtc->base.dev;
14541 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14542 u32 reg, val;
14543
7eb552ae 14544 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14545 return true;
14546
14547 reg = DSPCNTR(!crtc->plane);
14548 val = I915_READ(reg);
14549
14550 if ((val & DISPLAY_PLANE_ENABLE) &&
14551 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14552 return false;
14553
14554 return true;
14555}
14556
24929352
DV		 14557static void intel_sanitize_crtc(struct intel_crtc *crtc)
14558{
14559 struct drm_device *dev = crtc->base.dev;
14560 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14561 u32 reg;
24929352 14562
24929352 14563 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14564 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14565 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14566
d3eaf884 14567 /* restore vblank interrupts to correct state */
9625604c 14568 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14569 if (crtc->active) {
14570 update_scanline_offset(crtc);
9625604c
DV		 14571 drm_crtc_vblank_on(&crtc->base);
14572 }
d3eaf884 14573
24929352 14574 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14575 * disable the crtc (and hence change the state) if it is wrong. Note
14576 * that gen4+ has a fixed plane -> pipe mapping. */
14577 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14578 struct intel_connector *connector;
14579 bool plane;
14580
24929352
DV		 14581 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14582 crtc->base.base.id);
14583
14584 /* Pipe has the wrong plane attached and the plane is active.
14585 * Temporarily change the plane mapping and disable everything
14586 * ... */
14587 plane = crtc->plane;
b70709a6 14588 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14589 crtc->plane = !plane;
ce22dba9 14590 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 14591 dev_priv->display.crtc_disable(&crtc->base);
14592 crtc->plane = plane;
14593
14594 /* ... and break all links. */
3a3371ff 14595 for_each_intel_connector(dev, connector) {
24929352
DV		 14596 if (connector->encoder->base.crtc != &crtc->base)
14597 continue;
14598
7f1950fb
EE		 14599 connector->base.dpms = DRM_MODE_DPMS_OFF;
14600 connector->base.encoder = NULL;
24929352 14601 }
7f1950fb
EE		 14602 /* multiple connectors may have the same encoder:
14603 * handle them and break crtc link separately */
3a3371ff 14604 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14605 if (connector->encoder->base.crtc == &crtc->base) {
14606 connector->encoder->base.crtc = NULL;
14607 connector->encoder->connectors_active = false;
14608 }
24929352
DV		 14609
14610 WARN_ON(crtc->active);
83d65738 14611 crtc->base.state->enable = false;
49d6fa21 14612 crtc->base.state->active = false;
24929352
DV		 14613 crtc->base.enabled = false;
14614 }
24929352 14615
7fad798e
DV		 14616 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14617 crtc->pipe == PIPE_A && !crtc->active) {
14618 /* BIOS forgot to enable pipe A, this mostly happens after
14619 * resume. Force-enable the pipe to fix this, the update_dpms
14620 * call below we restore the pipe to the right state, but leave
14621 * the required bits on. */
14622 intel_enable_pipe_a(dev);
14623 }
14624
24929352
DV		 14625 /* Adjust the state of the output pipe according to whether we
14626 * have active connectors/encoders. */
14627 intel_crtc_update_dpms(&crtc->base);
14628
83d65738 14629 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14630 struct intel_encoder *encoder;
14631
14632 /* This can happen either due to bugs in the get_hw_state
14633 * functions or because the pipe is force-enabled due to the
14634 * pipe A quirk. */
14635 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14636 crtc->base.base.id,
83d65738 14637 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14638 crtc->active ? "enabled" : "disabled");
14639
83d65738 14640 crtc->base.state->enable = crtc->active;
49d6fa21 14641 crtc->base.state->active = crtc->active;
24929352
DV		 14642 crtc->base.enabled = crtc->active;
14643
14644 /* Because we only establish the connector -> encoder ->
14645 * crtc links if something is active, this means the
14646 * crtc is now deactivated. Break the links. connector
14647 * -> encoder links are only establish when things are
14648 * actually up, hence no need to break them. */
14649 WARN_ON(crtc->active);
14650
14651 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14652 WARN_ON(encoder->connectors_active);
14653 encoder->base.crtc = NULL;
14654 }
14655 }
c5ab3bc0 14656
a3ed6aad 14657 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14658 /*
14659 * We start out with underrun reporting disabled to avoid races.
14660 * For correct bookkeeping mark this on active crtcs.
14661 *
c5ab3bc0
DV		 14662 * Also on gmch platforms we dont have any hardware bits to
14663 * disable the underrun reporting. Which means we need to start
14664 * out with underrun reporting disabled also on inactive pipes,
14665 * since otherwise we'll complain about the garbage we read when
14666 * e.g. coming up after runtime pm.
14667 *
4cc31489
DV		 14668 * No protection against concurrent access is required - at
14669 * worst a fifo underrun happens which also sets this to false.
14670 */
14671 crtc->cpu_fifo_underrun_disabled = true;
14672 crtc->pch_fifo_underrun_disabled = true;
14673 }
24929352
DV		 14674}
14675
14676static void intel_sanitize_encoder(struct intel_encoder *encoder)
14677{
14678 struct intel_connector *connector;
14679 struct drm_device *dev = encoder->base.dev;
14680
14681 /* We need to check both for a crtc link (meaning that the
14682 * encoder is active and trying to read from a pipe) and the
14683 * pipe itself being active. */
14684 bool has_active_crtc = encoder->base.crtc &&
14685 to_intel_crtc(encoder->base.crtc)->active;
14686
14687 if (encoder->connectors_active && !has_active_crtc) {
14688 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14689 encoder->base.base.id,
8e329a03 14690 encoder->base.name);
24929352
DV		 14691
14692 /* Connector is active, but has no active pipe. This is
14693 * fallout from our resume register restoring. Disable
14694 * the encoder manually again. */
14695 if (encoder->base.crtc) {
14696 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14697 encoder->base.base.id,
8e329a03 14698 encoder->base.name);
24929352 14699 encoder->disable(encoder);
a62d1497
VS		 14700 if (encoder->post_disable)
14701 encoder->post_disable(encoder);
24929352 14702 }
7f1950fb
EE		 14703 encoder->base.crtc = NULL;
14704 encoder->connectors_active = false;
24929352
DV		 14705
14706 /* Inconsistent output/port/pipe state happens presumably due to
14707 * a bug in one of the get_hw_state functions. Or someplace else
14708 * in our code, like the register restore mess on resume. Clamp
14709 * things to off as a safer default. */
3a3371ff 14710 for_each_intel_connector(dev, connector) {
24929352
DV		 14711 if (connector->encoder != encoder)
14712 continue;
7f1950fb
EE		 14713 connector->base.dpms = DRM_MODE_DPMS_OFF;
14714 connector->base.encoder = NULL;
24929352
DV		 14715 }
14716 }
14717 /* Enabled encoders without active connectors will be fixed in
14718 * the crtc fixup. */
14719}
14720
04098753 14721void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14722{
14723 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14724 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14725
04098753
ID		 14726 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14727 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14728 i915_disable_vga(dev);
14729 }
14730}
14731
14732void i915_redisable_vga(struct drm_device *dev)
14733{
14734 struct drm_i915_private *dev_priv = dev->dev_private;
14735
8dc8a27c
PZ		 14736 /* This function can be called both from intel_modeset_setup_hw_state or
14737 * at a very early point in our resume sequence, where the power well
14738 * structures are not yet restored. Since this function is at a very
14739 * paranoid "someone might have enabled VGA while we were not looking"
14740 * level, just check if the power well is enabled instead of trying to
14741 * follow the "don't touch the power well if we don't need it" policy
14742 * the rest of the driver uses. */
f458ebbc 14743 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14744 return;
14745
04098753 14746 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14747}
14748
98ec7739
VS		 14749static bool primary_get_hw_state(struct intel_crtc *crtc)
14750{
14751 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14752
14753 if (!crtc->active)
14754 return false;
14755
14756 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14757}
14758
30e984df 14759static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14760{
14761 struct drm_i915_private *dev_priv = dev->dev_private;
14762 enum pipe pipe;
24929352
DV		 14763 struct intel_crtc *crtc;
14764 struct intel_encoder *encoder;
14765 struct intel_connector *connector;
5358901f 14766 int i;
24929352 14767
d3fcc808 14768 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 14769 struct drm_plane *primary = crtc->base.primary;
14770 struct intel_plane_state *plane_state;
14771
6e3c9717 14772 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14773
6e3c9717 14774 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14775
0e8ffe1b 14776 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14777 crtc->config);
24929352 14778
83d65738 14779 crtc->base.state->enable = crtc->active;
49d6fa21 14780 crtc->base.state->active = crtc->active;
24929352 14781 crtc->base.enabled = crtc->active;
b70709a6
ML		 14782
14783 plane_state = to_intel_plane_state(primary->state);
14784 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 14785
14786 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14787 crtc->base.base.id,
14788 crtc->active ? "enabled" : "disabled");
14789 }
14790
5358901f
DV		 14791 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14792 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14793
3e369b76
ACO		 14794 pll->on = pll->get_hw_state(dev_priv, pll,
14795 &pll->config.hw_state);
5358901f 14796 pll->active = 0;
3e369b76 14797 pll->config.crtc_mask = 0;
d3fcc808 14798 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14799 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14800 pll->active++;
3e369b76 14801 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14802 }
5358901f 14803 }
5358901f 14804
1e6f2ddc 14805 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14806 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14807
3e369b76 14808 if (pll->config.crtc_mask)
bd2bb1b9 14809 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14810 }
14811
b2784e15 14812 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14813 pipe = 0;
14814
14815 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14816 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14817 encoder->base.crtc = &crtc->base;
6e3c9717 14818 encoder->get_config(encoder, crtc->config);
24929352
DV		 14819 } else {
14820 encoder->base.crtc = NULL;
14821 }
14822
14823 encoder->connectors_active = false;
6f2bcceb 14824 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14825 encoder->base.base.id,
8e329a03 14826 encoder->base.name,
24929352 14827 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14828 pipe_name(pipe));
24929352
DV		 14829 }
14830
3a3371ff 14831 for_each_intel_connector(dev, connector) {
24929352
DV		 14832 if (connector->get_hw_state(connector)) {
14833 connector->base.dpms = DRM_MODE_DPMS_ON;
14834 connector->encoder->connectors_active = true;
14835 connector->base.encoder = &connector->encoder->base;
14836 } else {
14837 connector->base.dpms = DRM_MODE_DPMS_OFF;
14838 connector->base.encoder = NULL;
14839 }
14840 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14841 connector->base.base.id,
c23cc417 14842 connector->base.name,
24929352
DV		 14843 connector->base.encoder ? "enabled" : "disabled");
14844 }
30e984df
DV		 14845}
14846
14847/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14848 * and i915 state tracking structures. */
14849void intel_modeset_setup_hw_state(struct drm_device *dev,
14850 bool force_restore)
14851{
14852 struct drm_i915_private *dev_priv = dev->dev_private;
14853 enum pipe pipe;
30e984df
DV		 14854 struct intel_crtc *crtc;
14855 struct intel_encoder *encoder;
35c95375 14856 int i;
30e984df
DV		 14857
14858 intel_modeset_readout_hw_state(dev);
24929352 14859
babea61d
JB		 14860 /*
14861 * Now that we have the config, copy it to each CRTC struct
14862 * Note that this could go away if we move to using crtc_config
14863 * checking everywhere.
14864 */
d3fcc808 14865 for_each_intel_crtc(dev, crtc) {
d330a953 14866 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14867 intel_mode_from_pipe_config(&crtc->base.mode,
14868 crtc->config);
babea61d
JB		 14869 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14870 crtc->base.base.id);
14871 drm_mode_debug_printmodeline(&crtc->base.mode);
14872 }
14873 }
14874
24929352 14875 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14876 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14877 intel_sanitize_encoder(encoder);
14878 }
14879
055e393f 14880 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14881 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14882 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14883 intel_dump_pipe_config(crtc, crtc->config,
14884 "[setup_hw_state]");
24929352 14885 }
9a935856 14886
d29b2f9d
ACO		 14887 intel_modeset_update_connector_atomic_state(dev);
14888
35c95375
DV		 14889 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14890 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14891
14892 if (!pll->on || pll->active)
14893 continue;
14894
14895 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14896
14897 pll->disable(dev_priv, pll);
14898 pll->on = false;
14899 }
14900
3078999f
PB		 14901 if (IS_GEN9(dev))
14902 skl_wm_get_hw_state(dev);
14903 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14904 ilk_wm_get_hw_state(dev);
14905
45e2b5f6 14906 if (force_restore) {
7d0bc1ea
VS		 14907 i915_redisable_vga(dev);
14908
f30da187
DV		 14909 /*
14910 * We need to use raw interfaces for restoring state to avoid
14911 * checking (bogus) intermediate states.
14912 */
055e393f 14913 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14914 struct drm_crtc *crtc =
14915 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14916
83a57153 14917 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14918 }
14919 } else {
14920 intel_modeset_update_staged_output_state(dev);
14921 }
8af6cf88
DV		 14922
14923 intel_modeset_check_state(dev);
2c7111db
CW		 14924}
14925
14926void intel_modeset_gem_init(struct drm_device *dev)
14927{
92122789 14928 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 14929 struct drm_crtc *c;
2ff8fde1 14930 struct drm_i915_gem_object *obj;
e0d6149b 14931 int ret;
484b41dd 14932
ae48434c
ID		 14933 mutex_lock(&dev->struct_mutex);
14934 intel_init_gt_powersave(dev);
14935 mutex_unlock(&dev->struct_mutex);
14936
92122789
JB		 14937 /*
14938 * There may be no VBT; and if the BIOS enabled SSC we can
14939 * just keep using it to avoid unnecessary flicker. Whereas if the
14940 * BIOS isn't using it, don't assume it will work even if the VBT
14941 * indicates as much.
14942 */
14943 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14944 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14945 DREF_SSC1_ENABLE);
14946
1833b134 14947 intel_modeset_init_hw(dev);
02e792fb
DV		 14948
14949 intel_setup_overlay(dev);
484b41dd
JB		 14950
14951 /*
14952 * Make sure any fbs we allocated at startup are properly
14953 * pinned & fenced. When we do the allocation it's too early
14954 * for this.
14955 */
70e1e0ec 14956 for_each_crtc(dev, c) {
2ff8fde1
MR		 14957 obj = intel_fb_obj(c->primary->fb);
14958 if (obj == NULL)
484b41dd
JB		 14959 continue;
14960
e0d6149b
TU		 14961 mutex_lock(&dev->struct_mutex);
14962 ret = intel_pin_and_fence_fb_obj(c->primary,
14963 c->primary->fb,
14964 c->primary->state,
14965 NULL);
14966 mutex_unlock(&dev->struct_mutex);
14967 if (ret) {
484b41dd
JB		 14968 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14969 to_intel_crtc(c)->pipe);
66e514c1
DA		 14970 drm_framebuffer_unreference(c->primary->fb);
14971 c->primary->fb = NULL;
afd65eb4 14972 update_state_fb(c->primary);
484b41dd
JB		 14973 }
14974 }
0962c3c9
VS		 14975
14976 intel_backlight_register(dev);
79e53945
JB		 14977}
14978
4932e2c3
ID		 14979void intel_connector_unregister(struct intel_connector *intel_connector)
14980{
14981 struct drm_connector *connector = &intel_connector->base;
14982
14983 intel_panel_destroy_backlight(connector);
34ea3d38 14984 drm_connector_unregister(connector);
4932e2c3
ID		 14985}
14986
79e53945
JB		 14987void intel_modeset_cleanup(struct drm_device *dev)
14988{
652c393a 14989 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 14990 struct drm_connector *connector;
652c393a 14991
2eb5252e
ID		 14992 intel_disable_gt_powersave(dev);
14993
0962c3c9
VS		 14994 intel_backlight_unregister(dev);
14995
fd0c0642
DV		 14996 /*
14997 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 14998 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 14999 * experience fancy races otherwise.
15000 */
2aeb7d3a 15001 intel_irq_uninstall(dev_priv);
eb21b92b 15002
fd0c0642
DV		 15003 /*
15004 * Due to the hpd irq storm handling the hotplug work can re-arm the
15005 * poll handlers. Hence disable polling after hpd handling is shut down.
15006 */
f87ea761 15007 drm_kms_helper_poll_fini(dev);
fd0c0642 15008
652c393a
JB		 15009 mutex_lock(&dev->struct_mutex);
15010
723bfd70
JB		 15011 intel_unregister_dsm_handler();
15012
7ff0ebcc 15013 intel_fbc_disable(dev);
e70236a8 15014
69341a5e
KH		 15015 mutex_unlock(&dev->struct_mutex);
15016
1630fe75
CW		 15017 /* flush any delayed tasks or pending work */
15018 flush_scheduled_work();
15019
db31af1d
JN		 15020 /* destroy the backlight and sysfs files before encoders/connectors */
15021 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15022 struct intel_connector *intel_connector;
15023
15024 intel_connector = to_intel_connector(connector);
15025 intel_connector->unregister(intel_connector);
db31af1d 15026 }
d9255d57 15027
79e53945 15028 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15029
15030 intel_cleanup_overlay(dev);
ae48434c
ID		 15031
15032 mutex_lock(&dev->struct_mutex);
15033 intel_cleanup_gt_powersave(dev);
15034 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15035}
15036
f1c79df3
ZW		 15037/*
15038 * Return which encoder is currently attached for connector.
15039 */
df0e9248 15040struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15041{
df0e9248
CW		 15042 return &intel_attached_encoder(connector)->base;
15043}
f1c79df3 15044
df0e9248
CW		 15045void intel_connector_attach_encoder(struct intel_connector *connector,
15046 struct intel_encoder *encoder)
15047{
15048 connector->encoder = encoder;
15049 drm_mode_connector_attach_encoder(&connector->base,
15050 &encoder->base);
79e53945 15051}
28d52043
DA		 15052
15053/*
15054 * set vga decode state - true == enable VGA decode
15055 */
15056int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15057{
15058 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15059 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15060 u16 gmch_ctrl;
15061
75fa041d
CW		 15062 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15063 DRM_ERROR("failed to read control word\n");
15064 return -EIO;
15065 }
15066
c0cc8a55
CW		 15067 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15068 return 0;
15069
28d52043
DA		 15070 if (state)
15071 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15072 else
15073 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15074
15075 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15076 DRM_ERROR("failed to write control word\n");
15077 return -EIO;
15078 }
15079
28d52043
DA		 15080 return 0;
15081}
c4a1d9e4 15082
c4a1d9e4 15083struct intel_display_error_state {
ff57f1b0
PZ		 15084
15085 u32 power_well_driver;
15086
63b66e5b
CW		 15087 int num_transcoders;
15088
c4a1d9e4
CW		 15089 struct intel_cursor_error_state {
15090 u32 control;
15091 u32 position;
15092 u32 base;
15093 u32 size;
52331309 15094 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15095
15096 struct intel_pipe_error_state {
ddf9c536 15097 bool power_domain_on;
c4a1d9e4 15098 u32 source;
f301b1e1 15099 u32 stat;
52331309 15100 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15101
15102 struct intel_plane_error_state {
15103 u32 control;
15104 u32 stride;
15105 u32 size;
15106 u32 pos;
15107 u32 addr;
15108 u32 surface;
15109 u32 tile_offset;
52331309 15110 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15111
15112 struct intel_transcoder_error_state {
ddf9c536 15113 bool power_domain_on;
63b66e5b
CW		 15114 enum transcoder cpu_transcoder;
15115
15116 u32 conf;
15117
15118 u32 htotal;
15119 u32 hblank;
15120 u32 hsync;
15121 u32 vtotal;
15122 u32 vblank;
15123 u32 vsync;
15124 } transcoder[4];
c4a1d9e4
CW		 15125};
15126
15127struct intel_display_error_state *
15128intel_display_capture_error_state(struct drm_device *dev)
15129{
fbee40df 15130 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15131 struct intel_display_error_state *error;
63b66e5b
CW		 15132 int transcoders[] = {
15133 TRANSCODER_A,
15134 TRANSCODER_B,
15135 TRANSCODER_C,
15136 TRANSCODER_EDP,
15137 };
c4a1d9e4
CW		 15138 int i;
15139
63b66e5b
CW		 15140 if (INTEL_INFO(dev)->num_pipes == 0)
15141 return NULL;
15142
9d1cb914 15143 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15144 if (error == NULL)
15145 return NULL;
15146
190be112 15147 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15148 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15149
055e393f 15150 for_each_pipe(dev_priv, i) {
ddf9c536 15151 error->pipe[i].power_domain_on =
f458ebbc
DV		 15152 __intel_display_power_is_enabled(dev_priv,
15153 POWER_DOMAIN_PIPE(i));
ddf9c536 15154 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15155 continue;
15156
5efb3e28
VS		 15157 error->cursor[i].control = I915_READ(CURCNTR(i));
15158 error->cursor[i].position = I915_READ(CURPOS(i));
15159 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15160
15161 error->plane[i].control = I915_READ(DSPCNTR(i));
15162 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15163 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15164 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15165 error->plane[i].pos = I915_READ(DSPPOS(i));
15166 }
ca291363
PZ		 15167 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15168 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15169 if (INTEL_INFO(dev)->gen >= 4) {
15170 error->plane[i].surface = I915_READ(DSPSURF(i));
15171 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15172 }
15173
c4a1d9e4 15174 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15175
3abfce77 15176 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15177 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15178 }
15179
15180 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15181 if (HAS_DDI(dev_priv->dev))
15182 error->num_transcoders++; /* Account for eDP. */
15183
15184 for (i = 0; i < error->num_transcoders; i++) {
15185 enum transcoder cpu_transcoder = transcoders[i];
15186
ddf9c536 15187 error->transcoder[i].power_domain_on =
f458ebbc 15188 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15189 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15190 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15191 continue;
15192
63b66e5b
CW		 15193 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15194
15195 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15196 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15197 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15198 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15199 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15200 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15201 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15202 }
15203
15204 return error;
15205}
15206
edc3d884
MK		 15207#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15208
c4a1d9e4 15209void
edc3d884 15210intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15211 struct drm_device *dev,
15212 struct intel_display_error_state *error)
15213{
055e393f 15214 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15215 int i;
15216
63b66e5b
CW		 15217 if (!error)
15218 return;
15219
edc3d884 15220 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15221 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15222 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15223 error->power_well_driver);
055e393f 15224 for_each_pipe(dev_priv, i) {
edc3d884 15225 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15226 err_printf(m, " Power: %s\n",
15227 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15228 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15229 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15230
15231 err_printf(m, "Plane [%d]:\n", i);
15232 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15233 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15234 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15235 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15236 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15237 }
4b71a570 15238 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15239 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15240 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15241 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15242 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15243 }
15244
edc3d884
MK		 15245 err_printf(m, "Cursor [%d]:\n", i);
15246 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15247 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15248 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15249 }
63b66e5b
CW		 15250
15251 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15252 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15253 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15254 err_printf(m, " Power: %s\n",
15255 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15256 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15257 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15258 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15259 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15260 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15261 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15262 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15263 }
c4a1d9e4 15264}
e2fcdaa9
VS		 15265
15266void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15267{
15268 struct intel_crtc *crtc;
15269
15270 for_each_intel_crtc(dev, crtc) {
15271 struct intel_unpin_work *work;
e2fcdaa9 15272
5e2d7afc 15273 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15274
15275 work = crtc->unpin_work;
15276
15277 if (work && work->event &&
15278 work->event->base.file_priv == file) {
15279 kfree(work->event);
15280 work->event = NULL;
15281 }
15282
5e2d7afc 15283 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15284 }
15285}
Linux kernel - Deliverables
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