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drm/i915: show interrupt info on IVB
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
79e53945
JB		 34#include "drmP.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
e5510fac 38#include "i915_trace.h"
ab2c0672 39#include "drm_dp_helper.h"
79e53945
JB		 40
41#include "drm_crtc_helper.h"
42
32f9d658
ZW		 43#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44
79e53945 45bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 46static void intel_update_watermarks(struct drm_device *dev);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60} intel_clock_t;
61
62typedef struct {
63 int min, max;
64} intel_range_t;
65
66typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
79e53945
JB		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
d4906093
ML		 76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
86static bool
87intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
79e53945 89
a4fc5ed6
KP		 90static bool
91intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 93static bool
f2b115e6
AJ		 94intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 96
021357ac
CW		 97static inline u32 /* units of 100MHz */
98intel_fdi_link_freq(struct drm_device *dev)
99{
8b99e68c
CW		 100 if (IS_GEN5(dev)) {
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
103 } else
104 return 27;
021357ac
CW		 105}
106
e4b36699 107static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
d4906093 118 .find_pll = intel_find_best_PLL,
e4b36699
KP		 119};
120
121static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
d4906093 132 .find_pll = intel_find_best_PLL,
e4b36699 133};
273e27ca 134
e4b36699 135static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
d4906093 146 .find_pll = intel_find_best_PLL,
e4b36699
KP		 147};
148
149static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
d4906093 160 .find_pll = intel_find_best_PLL,
e4b36699
KP		 161};
162
273e27ca 163
e4b36699 164static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
174 .p2_slow = 10,
175 .p2_fast = 10
044c7c41 176 },
d4906093 177 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 178};
179
180static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
d4906093 191 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 192};
193
194static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
044c7c41 205 },
d4906093 206 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 207};
208
209static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
044c7c41 220 },
d4906093 221 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 222};
223
224static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 235 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 236};
237
f2b115e6 238static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
6115707b 251 .find_pll = intel_find_best_PLL,
e4b36699
KP		 252};
253
f2b115e6 254static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
6115707b 265 .find_pll = intel_find_best_PLL,
e4b36699
KP		 266};
267
273e27ca
EA		 268/* Ironlake / Sandybridge
269 *
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
272 */
b91ad0ec 273static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
4547668a 284 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 285};
286
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298 .find_pll = intel_g4x_find_best_PLL,
299};
300
301static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 312 .find_pll = intel_g4x_find_best_PLL,
313};
314
273e27ca 315/* LVDS 100mhz refclk limits. */
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327 .find_pll = intel_g4x_find_best_PLL,
328};
329
330static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 341 .find_pll = intel_g4x_find_best_PLL,
342};
343
344static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
4547668a 355 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 356};
357
1b894b59
CW		 358static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359 int refclk)
2c07245f 360{
b91ad0ec
ZW		 361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 363 const intel_limit_t *limit;
b91ad0ec
ZW		 364
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
1b894b59 369 if (refclk == 100000)
b91ad0ec
ZW		 370 limit = &intel_limits_ironlake_dual_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_dual_lvds;
373 } else {
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_single_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_single_lvds;
378 }
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 380 HAS_eDP)
381 limit = &intel_limits_ironlake_display_port;
2c07245f 382 else
b91ad0ec 383 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 384
385 return limit;
386}
387
044c7c41
ML		 388static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
389{
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
393
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
396 LVDS_CLKB_POWER_UP)
397 /* LVDS with dual channel */
e4b36699 398 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 399 else
400 /* LVDS with dual channel */
e4b36699 401 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 404 limit = &intel_limits_g4x_hdmi;
044c7c41 405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 406 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 408 limit = &intel_limits_g4x_display_port;
044c7c41 409 } else /* The option is for other outputs */
e4b36699 410 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 411
412 return limit;
413}
414
1b894b59 415static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 416{
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
419
bad720ff 420 if (HAS_PCH_SPLIT(dev))
1b894b59 421 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 422 else if (IS_G4X(dev)) {
044c7c41 423 limit = intel_g4x_limit(crtc);
f2b115e6 424 } else if (IS_PINEVIEW(dev)) {
2177832f 425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 426 limit = &intel_limits_pineview_lvds;
2177832f 427 else
f2b115e6 428 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
432 else
433 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 434 } else {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 436 limit = &intel_limits_i8xx_lvds;
79e53945 437 else
e4b36699 438 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 439 }
440 return limit;
441}
442
f2b115e6
AJ		 443/* m1 is reserved as 0 in Pineview, n is a ring counter */
444static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 445{
2177832f
SL		 446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
450}
451
452static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
453{
f2b115e6
AJ		 454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
2177832f
SL		 456 return;
457 }
79e53945
JB		 458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
462}
463
79e53945
JB		 464/**
465 * Returns whether any output on the specified pipe is of the specified type
466 */
4ef69c7a 467bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 468{
4ef69c7a
CW		 469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
472
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
475 return true;
476
477 return false;
79e53945
JB		 478}
479
7c04d1d9 480#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 481/**
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
484 */
485
1b894b59
CW		 486static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
79e53945 489{
79e53945
JB		 490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
f2b115e6 498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
508 */
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
511
512 return true;
513}
514
d4906093
ML		 515static bool
516intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
518
79e53945
JB		 519{
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
522 intel_clock_t clock;
79e53945
JB		 523 int err = target;
524
bc5e5718 525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 526 (I915_READ(LVDS)) != 0) {
79e53945
JB		 527 /*
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
531 * even can.
532 */
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534 LVDS_CLKB_POWER_UP)
535 clock.p2 = limit->p2.p2_fast;
536 else
537 clock.p2 = limit->p2.p2_slow;
538 } else {
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
541 else
542 clock.p2 = limit->p2.p2_fast;
543 }
544
545 memset (best_clock, 0, sizeof (*best_clock));
546
42158660
ZY		 547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548 clock.m1++) {
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 553 break;
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 558 int this_err;
559
2177832f 560 intel_clock(dev, refclk, &clock);
1b894b59
CW		 561 if (!intel_PLL_is_valid(dev, limit,
562 &clock))
79e53945
JB		 563 continue;
564
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
567 *best_clock = clock;
568 err = this_err;
569 }
570 }
571 }
572 }
573 }
574
575 return (err != target);
576}
577
d4906093
ML		 578static bool
579intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
581{
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 intel_clock_t clock;
585 int max_n;
586 bool found;
6ba770dc
AJ		 587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 589 found = false;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 592 int lvds_reg;
593
c619eed4 594 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 595 lvds_reg = PCH_LVDS;
596 else
597 lvds_reg = LVDS;
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 599 LVDS_CLKB_POWER_UP)
600 clock.p2 = limit->p2.p2_fast;
601 else
602 clock.p2 = limit->p2.p2_slow;
603 } else {
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
606 else
607 clock.p2 = limit->p2.p2_fast;
608 }
609
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
f77f13e2 612 /* based on hardware requirement, prefer smaller n to precision */
d4906093 613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 614 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
621 int this_err;
622
2177832f 623 intel_clock(dev, refclk, &clock);
1b894b59
CW		 624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
d4906093 626 continue;
1b894b59
CW		 627
628 this_err = abs(clock.dot - target);
d4906093
ML		 629 if (this_err < err_most) {
630 *best_clock = clock;
631 err_most = this_err;
632 max_n = clock.n;
633 found = true;
634 }
635 }
636 }
637 }
638 }
2c07245f
ZW		 639 return found;
640}
641
5eb08b69 642static bool
f2b115e6
AJ		 643intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 645{
646 struct drm_device *dev = crtc->dev;
647 intel_clock_t clock;
4547668a 648
5eb08b69
ZW		 649 if (target < 200000) {
650 clock.n = 1;
651 clock.p1 = 2;
652 clock.p2 = 10;
653 clock.m1 = 12;
654 clock.m2 = 9;
655 } else {
656 clock.n = 2;
657 clock.p1 = 1;
658 clock.p2 = 10;
659 clock.m1 = 14;
660 clock.m2 = 8;
661 }
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
664 return true;
665}
666
a4fc5ed6
KP		 667/* DisplayPort has only two frequencies, 162MHz and 270MHz */
668static bool
669intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
671{
5eddb70b
CW		 672 intel_clock_t clock;
673 if (target < 200000) {
674 clock.p1 = 2;
675 clock.p2 = 10;
676 clock.n = 2;
677 clock.m1 = 23;
678 clock.m2 = 8;
679 } else {
680 clock.p1 = 1;
681 clock.p2 = 10;
682 clock.n = 1;
683 clock.m1 = 14;
684 clock.m2 = 2;
685 }
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
689 clock.vco = 0;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
691 return true;
a4fc5ed6
KP		 692}
693
9d0498a2
JB		 694/**
695 * intel_wait_for_vblank - wait for vblank on a given pipe
696 * @dev: drm device
697 * @pipe: pipe to wait for
698 *
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
700 * mode setting code.
701 */
702void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 703{
9d0498a2 704 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 705 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 706
300387c0
CW		 707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
709 *
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
716 * vblanks...
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
719 */
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
722
9d0498a2 723 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
726 50))
9d0498a2
JB		 727 DRM_DEBUG_KMS("vblank wait timed out\n");
728}
729
ab7ad7f6
KP		 730/*
731 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 732 * @dev: drm device
733 * @pipe: pipe to wait for
734 *
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
738 *
ab7ad7f6
KP		 739 * On Gen4 and above:
740 * wait for the pipe register state bit to turn off
741 *
742 * Otherwise:
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
58e10eb9 745 *
9d0498a2 746 */
58e10eb9 747void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 748{
749 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 750
751 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 752 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 753
754 /* Wait for the Pipe State to go off */
58e10eb9
CW		 755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
756 100))
ab7ad7f6
KP		 757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
758 } else {
759 u32 last_line;
58e10eb9 760 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
762
763 /* Wait for the display line to settle */
764 do {
58e10eb9 765 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 766 mdelay(5);
58e10eb9 767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
771 }
79e53945
JB		 772}
773
b24e7179
JB		 774static const char *state_string(bool enabled)
775{
776 return enabled ? "on" : "off";
777}
778
779/* Only for pre-ILK configs */
780static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
782{
783 int reg;
784 u32 val;
785 bool cur_state;
786
787 reg = DPLL(pipe);
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
793}
794#define assert_pll_enabled(d, p) assert_pll(d, p, true)
795#define assert_pll_disabled(d, p) assert_pll(d, p, false)
796
040484af
JB		 797/* For ILK+ */
798static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
800{
801 int reg;
802 u32 val;
803 bool cur_state;
804
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
811}
812#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814
815static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
817{
818 int reg;
819 u32 val;
820 bool cur_state;
821
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
828}
829#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831
832static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
834{
835 int reg;
836 u32 val;
837 bool cur_state;
838
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
845}
846#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848
849static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
850 enum pipe pipe)
851{
852 int reg;
853 u32 val;
854
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
857 return;
858
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
862}
863
864static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
865 enum pipe pipe)
866{
867 int reg;
868 u32 val;
869
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
873}
874
ea0760cf
JB		 875static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
876 enum pipe pipe)
877{
878 int pp_reg, lvds_reg;
879 u32 val;
880 enum pipe panel_pipe = PIPE_A;
881 bool locked = locked;
882
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
885 lvds_reg = PCH_LVDS;
886 } else {
887 pp_reg = PP_CONTROL;
888 lvds_reg = LVDS;
889 }
890
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
894 locked = false;
895
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
897 panel_pipe = PIPE_B;
898
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 901 pipe_name(pipe));
ea0760cf
JB		 902}
903
63d7bbe9
JB		 904static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
b24e7179
JB		 906{
907 int reg;
908 u32 val;
63d7bbe9 909 bool cur_state;
b24e7179
JB		 910
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
63d7bbe9
JB		 913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 916 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 917}
63d7bbe9
JB		 918#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 920
921static void assert_plane_enabled(struct drm_i915_private *dev_priv,
922 enum plane plane)
923{
924 int reg;
925 u32 val;
926
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 931 plane_name(plane));
b24e7179
JB		 932}
933
934static void assert_planes_disabled(struct drm_i915_private *dev_priv,
935 enum pipe pipe)
936{
937 int reg, i;
938 u32 val;
939 int cur_pipe;
940
19ec1358
JB		 941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
943 return;
944
b24e7179
JB		 945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
947 reg = DSPCNTR(i);
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
b24e7179
JB		 954 }
955}
956
92f2584a
JB		 957static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
958{
959 u32 val;
960 bool enabled;
961
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
966}
967
968static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
969 enum pipe pipe)
970{
971 int reg;
972 u32 val;
973 bool enabled;
974
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 978 WARN(enabled,
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
980 pipe_name(pipe));
92f2584a
JB		 981}
982
4e634389
KP		 983static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
984 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 985{
986 if ((val & DP_PORT_EN) == 0)
987 return false;
988
989 if (HAS_PCH_CPT(dev_priv->dev)) {
990 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
991 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
992 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
993 return false;
994 } else {
995 if ((val & DP_PIPE_MASK) != (pipe << 30))
996 return false;
997 }
998 return true;
999}
1000
1519b995
KP		 1001static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe, u32 val)
1003{
1004 if ((val & PORT_ENABLE) == 0)
1005 return false;
1006
1007 if (HAS_PCH_CPT(dev_priv->dev)) {
1008 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1009 return false;
1010 } else {
1011 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1012 return false;
1013 }
1014 return true;
1015}
1016
1017static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, u32 val)
1019{
1020 if ((val & LVDS_PORT_EN) == 0)
1021 return false;
1022
1023 if (HAS_PCH_CPT(dev_priv->dev)) {
1024 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1025 return false;
1026 } else {
1027 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1028 return false;
1029 }
1030 return true;
1031}
1032
1033static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, u32 val)
1035{
1036 if ((val & ADPA_DAC_ENABLE) == 0)
1037 return false;
1038 if (HAS_PCH_CPT(dev_priv->dev)) {
1039 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1040 return false;
1041 } else {
1042 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1043 return false;
1044 }
1045 return true;
1046}
1047
291906f1 1048static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1049 enum pipe pipe, int reg, u32 port_sel)
291906f1 1050{
47a05eca 1051 u32 val = I915_READ(reg);
4e634389 1052 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1053 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1054 reg, pipe_name(pipe));
291906f1
JB		 1055}
1056
1057static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1058 enum pipe pipe, int reg)
1059{
47a05eca 1060 u32 val = I915_READ(reg);
1519b995 1061 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
291906f1 1062 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1063 reg, pipe_name(pipe));
291906f1
JB		 1064}
1065
1066static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1067 enum pipe pipe)
1068{
1069 int reg;
1070 u32 val;
291906f1 1071
f0575e92
KP		 1072 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1073 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1074 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1075
1076 reg = PCH_ADPA;
1077 val = I915_READ(reg);
1519b995 1078 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1079 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1080 pipe_name(pipe));
291906f1
JB		 1081
1082 reg = PCH_LVDS;
1083 val = I915_READ(reg);
1519b995 1084 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1085 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1086 pipe_name(pipe));
291906f1
JB		 1087
1088 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1089 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1090 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1091}
1092
63d7bbe9
JB		 1093/**
1094 * intel_enable_pll - enable a PLL
1095 * @dev_priv: i915 private structure
1096 * @pipe: pipe PLL to enable
1097 *
1098 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1099 * make sure the PLL reg is writable first though, since the panel write
1100 * protect mechanism may be enabled.
1101 *
1102 * Note! This is for pre-ILK only.
1103 */
1104static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1105{
1106 int reg;
1107 u32 val;
1108
1109 /* No really, not for ILK+ */
1110 BUG_ON(dev_priv->info->gen >= 5);
1111
1112 /* PLL is protected by panel, make sure we can write it */
1113 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1114 assert_panel_unlocked(dev_priv, pipe);
1115
1116 reg = DPLL(pipe);
1117 val = I915_READ(reg);
1118 val |= DPLL_VCO_ENABLE;
1119
1120 /* We do this three times for luck */
1121 I915_WRITE(reg, val);
1122 POSTING_READ(reg);
1123 udelay(150); /* wait for warmup */
1124 I915_WRITE(reg, val);
1125 POSTING_READ(reg);
1126 udelay(150); /* wait for warmup */
1127 I915_WRITE(reg, val);
1128 POSTING_READ(reg);
1129 udelay(150); /* wait for warmup */
1130}
1131
1132/**
1133 * intel_disable_pll - disable a PLL
1134 * @dev_priv: i915 private structure
1135 * @pipe: pipe PLL to disable
1136 *
1137 * Disable the PLL for @pipe, making sure the pipe is off first.
1138 *
1139 * Note! This is for pre-ILK only.
1140 */
1141static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1142{
1143 int reg;
1144 u32 val;
1145
1146 /* Don't disable pipe A or pipe A PLLs if needed */
1147 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1148 return;
1149
1150 /* Make sure the pipe isn't still relying on us */
1151 assert_pipe_disabled(dev_priv, pipe);
1152
1153 reg = DPLL(pipe);
1154 val = I915_READ(reg);
1155 val &= ~DPLL_VCO_ENABLE;
1156 I915_WRITE(reg, val);
1157 POSTING_READ(reg);
1158}
1159
92f2584a
JB		 1160/**
1161 * intel_enable_pch_pll - enable PCH PLL
1162 * @dev_priv: i915 private structure
1163 * @pipe: pipe PLL to enable
1164 *
1165 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1166 * drives the transcoder clock.
1167 */
1168static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1169 enum pipe pipe)
1170{
1171 int reg;
1172 u32 val;
1173
1174 /* PCH only available on ILK+ */
1175 BUG_ON(dev_priv->info->gen < 5);
1176
1177 /* PCH refclock must be enabled first */
1178 assert_pch_refclk_enabled(dev_priv);
1179
1180 reg = PCH_DPLL(pipe);
1181 val = I915_READ(reg);
1182 val |= DPLL_VCO_ENABLE;
1183 I915_WRITE(reg, val);
1184 POSTING_READ(reg);
1185 udelay(200);
1186}
1187
1188static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
1194 /* PCH only available on ILK+ */
1195 BUG_ON(dev_priv->info->gen < 5);
1196
1197 /* Make sure transcoder isn't still depending on us */
1198 assert_transcoder_disabled(dev_priv, pipe);
1199
1200 reg = PCH_DPLL(pipe);
1201 val = I915_READ(reg);
1202 val &= ~DPLL_VCO_ENABLE;
1203 I915_WRITE(reg, val);
1204 POSTING_READ(reg);
1205 udelay(200);
1206}
1207
040484af
JB		 1208static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1209 enum pipe pipe)
1210{
1211 int reg;
1212 u32 val;
1213
1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1216
1217 /* Make sure PCH DPLL is enabled */
1218 assert_pch_pll_enabled(dev_priv, pipe);
1219
1220 /* FDI must be feeding us bits for PCH ports */
1221 assert_fdi_tx_enabled(dev_priv, pipe);
1222 assert_fdi_rx_enabled(dev_priv, pipe);
1223
1224 reg = TRANSCONF(pipe);
1225 val = I915_READ(reg);
e9bcff5c
JB		 1226
1227 if (HAS_PCH_IBX(dev_priv->dev)) {
1228 /*
1229 * make the BPC in transcoder be consistent with
1230 * that in pipeconf reg.
1231 */
1232 val &= ~PIPE_BPC_MASK;
1233 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1234 }
040484af
JB		 1235 I915_WRITE(reg, val | TRANS_ENABLE);
1236 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1237 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1238}
1239
1240static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1241 enum pipe pipe)
1242{
1243 int reg;
1244 u32 val;
1245
1246 /* FDI relies on the transcoder */
1247 assert_fdi_tx_disabled(dev_priv, pipe);
1248 assert_fdi_rx_disabled(dev_priv, pipe);
1249
291906f1
JB		 1250 /* Ports must be off as well */
1251 assert_pch_ports_disabled(dev_priv, pipe);
1252
040484af
JB		 1253 reg = TRANSCONF(pipe);
1254 val = I915_READ(reg);
1255 val &= ~TRANS_ENABLE;
1256 I915_WRITE(reg, val);
1257 /* wait for PCH transcoder off, transcoder state */
1258 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1259 DRM_ERROR("failed to disable transcoder\n");
1260}
1261
b24e7179 1262/**
309cfea8 1263 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1264 * @dev_priv: i915 private structure
1265 * @pipe: pipe to enable
040484af 1266 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1267 *
1268 * Enable @pipe, making sure that various hardware specific requirements
1269 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1270 *
1271 * @pipe should be %PIPE_A or %PIPE_B.
1272 *
1273 * Will wait until the pipe is actually running (i.e. first vblank) before
1274 * returning.
1275 */
040484af
JB		 1276static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1277 bool pch_port)
b24e7179
JB		 1278{
1279 int reg;
1280 u32 val;
1281
1282 /*
1283 * A pipe without a PLL won't actually be able to drive bits from
1284 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1285 * need the check.
1286 */
1287 if (!HAS_PCH_SPLIT(dev_priv->dev))
1288 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1289 else {
1290 if (pch_port) {
1291 /* if driving the PCH, we need FDI enabled */
1292 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1293 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1294 }
1295 /* FIXME: assert CPU port conditions for SNB+ */
1296 }
b24e7179
JB		 1297
1298 reg = PIPECONF(pipe);
1299 val = I915_READ(reg);
00d70b15
CW		 1300 if (val & PIPECONF_ENABLE)
1301 return;
1302
1303 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1304 intel_wait_for_vblank(dev_priv->dev, pipe);
1305}
1306
1307/**
309cfea8 1308 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1309 * @dev_priv: i915 private structure
1310 * @pipe: pipe to disable
1311 *
1312 * Disable @pipe, making sure that various hardware specific requirements
1313 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1314 *
1315 * @pipe should be %PIPE_A or %PIPE_B.
1316 *
1317 * Will wait until the pipe has shut down before returning.
1318 */
1319static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1320 enum pipe pipe)
1321{
1322 int reg;
1323 u32 val;
1324
1325 /*
1326 * Make sure planes won't keep trying to pump pixels to us,
1327 * or we might hang the display.
1328 */
1329 assert_planes_disabled(dev_priv, pipe);
1330
1331 /* Don't disable pipe A or pipe A PLLs if needed */
1332 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1333 return;
1334
1335 reg = PIPECONF(pipe);
1336 val = I915_READ(reg);
00d70b15
CW		 1337 if ((val & PIPECONF_ENABLE) == 0)
1338 return;
1339
1340 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1341 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1342}
1343
d74362c9
KP		 1344/*
1345 * Plane regs are double buffered, going from enabled->disabled needs a
1346 * trigger in order to latch. The display address reg provides this.
1347 */
1348static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1349 enum plane plane)
1350{
1351 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1352 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1353}
1354
b24e7179
JB		 1355/**
1356 * intel_enable_plane - enable a display plane on a given pipe
1357 * @dev_priv: i915 private structure
1358 * @plane: plane to enable
1359 * @pipe: pipe being fed
1360 *
1361 * Enable @plane on @pipe, making sure that @pipe is running first.
1362 */
1363static void intel_enable_plane(struct drm_i915_private *dev_priv,
1364 enum plane plane, enum pipe pipe)
1365{
1366 int reg;
1367 u32 val;
1368
1369 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1370 assert_pipe_enabled(dev_priv, pipe);
1371
1372 reg = DSPCNTR(plane);
1373 val = I915_READ(reg);
00d70b15
CW		 1374 if (val & DISPLAY_PLANE_ENABLE)
1375 return;
1376
1377 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1378 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1379 intel_wait_for_vblank(dev_priv->dev, pipe);
1380}
1381
b24e7179
JB		 1382/**
1383 * intel_disable_plane - disable a display plane
1384 * @dev_priv: i915 private structure
1385 * @plane: plane to disable
1386 * @pipe: pipe consuming the data
1387 *
1388 * Disable @plane; should be an independent operation.
1389 */
1390static void intel_disable_plane(struct drm_i915_private *dev_priv,
1391 enum plane plane, enum pipe pipe)
1392{
1393 int reg;
1394 u32 val;
1395
1396 reg = DSPCNTR(plane);
1397 val = I915_READ(reg);
00d70b15
CW		 1398 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1399 return;
1400
1401 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1402 intel_flush_display_plane(dev_priv, plane);
1403 intel_wait_for_vblank(dev_priv->dev, pipe);
1404}
1405
47a05eca 1406static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1407 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1408{
1409 u32 val = I915_READ(reg);
4e634389 1410 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1411 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1412 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1413 }
47a05eca
JB		 1414}
1415
1416static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, int reg)
1418{
1419 u32 val = I915_READ(reg);
1519b995 1420 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1421 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1422 reg, pipe);
47a05eca 1423 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1424 }
47a05eca
JB		 1425}
1426
1427/* Disable any ports connected to this transcoder */
1428static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1429 enum pipe pipe)
1430{
1431 u32 reg, val;
1432
1433 val = I915_READ(PCH_PP_CONTROL);
1434 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1435
f0575e92
KP		 1436 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1437 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1438 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1439
1440 reg = PCH_ADPA;
1441 val = I915_READ(reg);
1519b995 1442 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1443 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1444
1445 reg = PCH_LVDS;
1446 val = I915_READ(reg);
1519b995
KP		 1447 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1448 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1449 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1450 POSTING_READ(reg);
1451 udelay(100);
1452 }
1453
1454 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1455 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1456 disable_pch_hdmi(dev_priv, pipe, HDMID);
1457}
1458
43a9539f
CW		 1459static void i8xx_disable_fbc(struct drm_device *dev)
1460{
1461 struct drm_i915_private *dev_priv = dev->dev_private;
1462 u32 fbc_ctl;
1463
1464 /* Disable compression */
1465 fbc_ctl = I915_READ(FBC_CONTROL);
1466 if ((fbc_ctl & FBC_CTL_EN) == 0)
1467 return;
1468
1469 fbc_ctl &= ~FBC_CTL_EN;
1470 I915_WRITE(FBC_CONTROL, fbc_ctl);
1471
1472 /* Wait for compressing bit to clear */
1473 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1474 DRM_DEBUG_KMS("FBC idle timed out\n");
1475 return;
1476 }
1477
1478 DRM_DEBUG_KMS("disabled FBC\n");
1479}
1480
80824003
JB		 1481static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1482{
1483 struct drm_device *dev = crtc->dev;
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 struct drm_framebuffer *fb = crtc->fb;
1486 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1487 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1489 int cfb_pitch;
80824003
JB		 1490 int plane, i;
1491 u32 fbc_ctl, fbc_ctl2;
1492
016b9b61
CW		 1493 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1494 if (fb->pitch < cfb_pitch)
1495 cfb_pitch = fb->pitch;
80824003
JB		 1496
1497 /* FBC_CTL wants 64B units */
016b9b61
CW		 1498 cfb_pitch = (cfb_pitch / 64) - 1;
1499 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1500
1501 /* Clear old tags */
1502 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1503 I915_WRITE(FBC_TAG + (i * 4), 0);
1504
1505 /* Set it up... */
de568510
CW		 1506 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1507 fbc_ctl2 |= plane;
80824003
JB		 1508 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1509 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1510
1511 /* enable it... */
1512 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1513 if (IS_I945GM(dev))
49677901 1514 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1515 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1516 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1517 fbc_ctl |= obj->fence_reg;
80824003
JB		 1518 I915_WRITE(FBC_CONTROL, fbc_ctl);
1519
016b9b61
CW		 1520 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1521 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1522}
1523
ee5382ae 1524static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1525{
80824003
JB		 1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527
1528 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1529}
1530
74dff282
JB		 1531static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1532{
1533 struct drm_device *dev = crtc->dev;
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 struct drm_framebuffer *fb = crtc->fb;
1536 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1537 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1539 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1540 unsigned long stall_watermark = 200;
1541 u32 dpfc_ctl;
1542
74dff282 1543 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1544 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1545 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1546
74dff282
JB		 1547 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1548 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1549 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1550 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1551
1552 /* enable it... */
1553 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1554
28c97730 1555 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1556}
1557
43a9539f 1558static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1559{
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 u32 dpfc_ctl;
1562
1563 /* Disable compression */
1564 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1565 if (dpfc_ctl & DPFC_CTL_EN) {
1566 dpfc_ctl &= ~DPFC_CTL_EN;
1567 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1568
bed4a673
CW		 1569 DRM_DEBUG_KMS("disabled FBC\n");
1570 }
74dff282
JB		 1571}
1572
ee5382ae 1573static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1574{
74dff282
JB		 1575 struct drm_i915_private *dev_priv = dev->dev_private;
1576
1577 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1578}
1579
4efe0708
JB		 1580static void sandybridge_blit_fbc_update(struct drm_device *dev)
1581{
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 u32 blt_ecoskpd;
1584
1585 /* Make sure blitter notifies FBC of writes */
fcca7926 1586 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1587 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1588 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1589 GEN6_BLITTER_LOCK_SHIFT;
1590 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1591 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1592 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1593 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1594 GEN6_BLITTER_LOCK_SHIFT);
1595 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1596 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1597 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1598}
1599
b52eb4dc
ZY		 1600static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1601{
1602 struct drm_device *dev = crtc->dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 struct drm_framebuffer *fb = crtc->fb;
1605 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1606 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1608 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1609 unsigned long stall_watermark = 200;
1610 u32 dpfc_ctl;
1611
bed4a673 1612 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1613 dpfc_ctl &= DPFC_RESERVED;
1614 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1615 /* Set persistent mode for front-buffer rendering, ala X. */
1616 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1617 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1618 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1619
b52eb4dc
ZY		 1620 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1621 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1622 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1623 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1624 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1625 /* enable it... */
bed4a673 1626 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1627
9c04f015
YL		 1628 if (IS_GEN6(dev)) {
1629 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1630 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1631 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1632 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1633 }
1634
b52eb4dc
ZY		 1635 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1636}
1637
43a9539f 1638static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1639{
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 u32 dpfc_ctl;
1642
1643 /* Disable compression */
1644 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1645 if (dpfc_ctl & DPFC_CTL_EN) {
1646 dpfc_ctl &= ~DPFC_CTL_EN;
1647 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1648
bed4a673
CW		 1649 DRM_DEBUG_KMS("disabled FBC\n");
1650 }
b52eb4dc
ZY		 1651}
1652
1653static bool ironlake_fbc_enabled(struct drm_device *dev)
1654{
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656
1657 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1658}
1659
ee5382ae
AJ		 1660bool intel_fbc_enabled(struct drm_device *dev)
1661{
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663
1664 if (!dev_priv->display.fbc_enabled)
1665 return false;
1666
1667 return dev_priv->display.fbc_enabled(dev);
1668}
1669
1630fe75
CW		 1670static void intel_fbc_work_fn(struct work_struct *__work)
1671{
1672 struct intel_fbc_work *work =
1673 container_of(to_delayed_work(__work),
1674 struct intel_fbc_work, work);
1675 struct drm_device *dev = work->crtc->dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677
1678 mutex_lock(&dev->struct_mutex);
1679 if (work == dev_priv->fbc_work) {
1680 /* Double check that we haven't switched fb without cancelling
1681 * the prior work.
1682 */
016b9b61 1683 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1684 dev_priv->display.enable_fbc(work->crtc,
1685 work->interval);
1686
016b9b61
CW		 1687 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1688 dev_priv->cfb_fb = work->crtc->fb->base.id;
1689 dev_priv->cfb_y = work->crtc->y;
1690 }
1691
1630fe75
CW		 1692 dev_priv->fbc_work = NULL;
1693 }
1694 mutex_unlock(&dev->struct_mutex);
1695
1696 kfree(work);
1697}
1698
1699static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1700{
1701 if (dev_priv->fbc_work == NULL)
1702 return;
1703
1704 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1705
1706 /* Synchronisation is provided by struct_mutex and checking of
1707 * dev_priv->fbc_work, so we can perform the cancellation
1708 * entirely asynchronously.
1709 */
1710 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1711 /* tasklet was killed before being run, clean up */
1712 kfree(dev_priv->fbc_work);
1713
1714 /* Mark the work as no longer wanted so that if it does
1715 * wake-up (because the work was already running and waiting
1716 * for our mutex), it will discover that is no longer
1717 * necessary to run.
1718 */
1719 dev_priv->fbc_work = NULL;
1720}
1721
43a9539f 1722static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1723{
1630fe75
CW		 1724 struct intel_fbc_work *work;
1725 struct drm_device *dev = crtc->dev;
1726 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1727
1728 if (!dev_priv->display.enable_fbc)
1729 return;
1730
1630fe75
CW		 1731 intel_cancel_fbc_work(dev_priv);
1732
1733 work = kzalloc(sizeof *work, GFP_KERNEL);
1734 if (work == NULL) {
1735 dev_priv->display.enable_fbc(crtc, interval);
1736 return;
1737 }
1738
1739 work->crtc = crtc;
1740 work->fb = crtc->fb;
1741 work->interval = interval;
1742 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1743
1744 dev_priv->fbc_work = work;
1745
1746 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1747
1748 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1749 * display to settle before starting the compression. Note that
1750 * this delay also serves a second purpose: it allows for a
1751 * vblank to pass after disabling the FBC before we attempt
1752 * to modify the control registers.
1630fe75
CW		 1753 *
1754 * A more complicated solution would involve tracking vblanks
1755 * following the termination of the page-flipping sequence
1756 * and indeed performing the enable as a co-routine and not
1757 * waiting synchronously upon the vblank.
1758 */
1759 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1760}
1761
1762void intel_disable_fbc(struct drm_device *dev)
1763{
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765
1630fe75
CW		 1766 intel_cancel_fbc_work(dev_priv);
1767
ee5382ae
AJ		 1768 if (!dev_priv->display.disable_fbc)
1769 return;
1770
1771 dev_priv->display.disable_fbc(dev);
016b9b61 1772 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1773}
1774
80824003
JB		 1775/**
1776 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1777 * @dev: the drm_device
80824003
JB		 1778 *
1779 * Set up the framebuffer compression hardware at mode set time. We
1780 * enable it if possible:
1781 * - plane A only (on pre-965)
1782 * - no pixel mulitply/line duplication
1783 * - no alpha buffer discard
1784 * - no dual wide
1785 * - framebuffer <= 2048 in width, 1536 in height
1786 *
1787 * We can't assume that any compression will take place (worst case),
1788 * so the compressed buffer has to be the same size as the uncompressed
1789 * one. It also must reside (along with the line length buffer) in
1790 * stolen memory.
1791 *
1792 * We need to enable/disable FBC on a global basis.
1793 */
bed4a673 1794static void intel_update_fbc(struct drm_device *dev)
80824003 1795{
80824003 1796 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1797 struct drm_crtc *crtc = NULL, *tmp_crtc;
1798 struct intel_crtc *intel_crtc;
1799 struct drm_framebuffer *fb;
80824003 1800 struct intel_framebuffer *intel_fb;
05394f39 1801 struct drm_i915_gem_object *obj;
9c928d16
JB		 1802
1803 DRM_DEBUG_KMS("\n");
80824003
JB		 1804
1805 if (!i915_powersave)
1806 return;
1807
ee5382ae 1808 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1809 return;
1810
80824003
JB		 1811 /*
1812 * If FBC is already on, we just have to verify that we can
1813 * keep it that way...
1814 * Need to disable if:
9c928d16 1815 * - more than one pipe is active
80824003
JB		 1816 * - changing FBC params (stride, fence, mode)
1817 * - new fb is too large to fit in compressed buffer
1818 * - going to an unsupported config (interlace, pixel multiply, etc.)
1819 */
9c928d16 1820 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1821 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1822 if (crtc) {
1823 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1824 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1825 goto out_disable;
1826 }
1827 crtc = tmp_crtc;
1828 }
9c928d16 1829 }
bed4a673
CW		 1830
1831 if (!crtc || crtc->fb == NULL) {
1832 DRM_DEBUG_KMS("no output, disabling\n");
1833 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1834 goto out_disable;
1835 }
bed4a673
CW		 1836
1837 intel_crtc = to_intel_crtc(crtc);
1838 fb = crtc->fb;
1839 intel_fb = to_intel_framebuffer(fb);
05394f39 1840 obj = intel_fb->obj;
bed4a673 1841
c1a9f047
JB		 1842 if (!i915_enable_fbc) {
1843 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1844 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1845 goto out_disable;
1846 }
05394f39 1847 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1848 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1849 "compression\n");
b5e50c3f 1850 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1851 goto out_disable;
1852 }
bed4a673
CW		 1853 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1854 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1855 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1856 "disabling\n");
b5e50c3f 1857 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1858 goto out_disable;
1859 }
bed4a673
CW		 1860 if ((crtc->mode.hdisplay > 2048) ||
1861 (crtc->mode.vdisplay > 1536)) {
28c97730 1862 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1863 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1864 goto out_disable;
1865 }
bed4a673 1866 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1867 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1868 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1869 goto out_disable;
1870 }
de568510
CW		 1871
1872 /* The use of a CPU fence is mandatory in order to detect writes
1873 * by the CPU to the scanout and trigger updates to the FBC.
1874 */
1875 if (obj->tiling_mode != I915_TILING_X ||
1876 obj->fence_reg == I915_FENCE_REG_NONE) {
1877 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1878 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1879 goto out_disable;
1880 }
1881
c924b934
JW		 1882 /* If the kernel debugger is active, always disable compression */
1883 if (in_dbg_master())
1884 goto out_disable;
1885
016b9b61
CW		 1886 /* If the scanout has not changed, don't modify the FBC settings.
1887 * Note that we make the fundamental assumption that the fb->obj
1888 * cannot be unpinned (and have its GTT offset and fence revoked)
1889 * without first being decoupled from the scanout and FBC disabled.
1890 */
1891 if (dev_priv->cfb_plane == intel_crtc->plane &&
1892 dev_priv->cfb_fb == fb->base.id &&
1893 dev_priv->cfb_y == crtc->y)
1894 return;
1895
1896 if (intel_fbc_enabled(dev)) {
1897 /* We update FBC along two paths, after changing fb/crtc
1898 * configuration (modeswitching) and after page-flipping
1899 * finishes. For the latter, we know that not only did
1900 * we disable the FBC at the start of the page-flip
1901 * sequence, but also more than one vblank has passed.
1902 *
1903 * For the former case of modeswitching, it is possible
1904 * to switch between two FBC valid configurations
1905 * instantaneously so we do need to disable the FBC
1906 * before we can modify its control registers. We also
1907 * have to wait for the next vblank for that to take
1908 * effect. However, since we delay enabling FBC we can
1909 * assume that a vblank has passed since disabling and
1910 * that we can safely alter the registers in the deferred
1911 * callback.
1912 *
1913 * In the scenario that we go from a valid to invalid
1914 * and then back to valid FBC configuration we have
1915 * no strict enforcement that a vblank occurred since
1916 * disabling the FBC. However, along all current pipe
1917 * disabling paths we do need to wait for a vblank at
1918 * some point. And we wait before enabling FBC anyway.
1919 */
1920 DRM_DEBUG_KMS("disabling active FBC for update\n");
1921 intel_disable_fbc(dev);
1922 }
1923
bed4a673 1924 intel_enable_fbc(crtc, 500);
80824003
JB		 1925 return;
1926
1927out_disable:
80824003 1928 /* Multiple disables should be harmless */
a939406f
CW		 1929 if (intel_fbc_enabled(dev)) {
1930 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1931 intel_disable_fbc(dev);
a939406f 1932 }
80824003
JB		 1933}
1934
127bd2ac 1935int
48b956c5 1936intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1937 struct drm_i915_gem_object *obj,
919926ae 1938 struct intel_ring_buffer *pipelined)
6b95a207 1939{
ce453d81 1940 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1941 u32 alignment;
1942 int ret;
1943
05394f39 1944 switch (obj->tiling_mode) {
6b95a207 1945 case I915_TILING_NONE:
534843da
CW		 1946 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1947 alignment = 128 * 1024;
a6c45cf0 1948 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1949 alignment = 4 * 1024;
1950 else
1951 alignment = 64 * 1024;
6b95a207
KH		 1952 break;
1953 case I915_TILING_X:
1954 /* pin() will align the object as required by fence */
1955 alignment = 0;
1956 break;
1957 case I915_TILING_Y:
1958 /* FIXME: Is this true? */
1959 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1960 return -EINVAL;
1961 default:
1962 BUG();
1963 }
1964
ce453d81 1965 dev_priv->mm.interruptible = false;
2da3b9b9 1966 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1967 if (ret)
ce453d81 1968 goto err_interruptible;
6b95a207
KH		 1969
1970 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1971 * fence, whereas 965+ only requires a fence if using
1972 * framebuffer compression. For simplicity, we always install
1973 * a fence as the cost is not that onerous.
1974 */
05394f39 1975 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1976 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1977 if (ret)
1978 goto err_unpin;
6b95a207
KH		 1979 }
1980
ce453d81 1981 dev_priv->mm.interruptible = true;
6b95a207 1982 return 0;
48b956c5
CW		 1983
1984err_unpin:
1985 i915_gem_object_unpin(obj);
ce453d81
CW		 1986err_interruptible:
1987 dev_priv->mm.interruptible = true;
48b956c5 1988 return ret;
6b95a207
KH		 1989}
1990
17638cd6
JB		 1991static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1992 int x, int y)
81255565
JB		 1993{
1994 struct drm_device *dev = crtc->dev;
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1997 struct intel_framebuffer *intel_fb;
05394f39 1998 struct drm_i915_gem_object *obj;
81255565
JB		 1999 int plane = intel_crtc->plane;
2000 unsigned long Start, Offset;
81255565 2001 u32 dspcntr;
5eddb70b 2002 u32 reg;
81255565
JB		 2003
2004 switch (plane) {
2005 case 0:
2006 case 1:
2007 break;
2008 default:
2009 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2010 return -EINVAL;
2011 }
2012
2013 intel_fb = to_intel_framebuffer(fb);
2014 obj = intel_fb->obj;
81255565 2015
5eddb70b
CW		 2016 reg = DSPCNTR(plane);
2017 dspcntr = I915_READ(reg);
81255565
JB		 2018 /* Mask out pixel format bits in case we change it */
2019 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2020 switch (fb->bits_per_pixel) {
2021 case 8:
2022 dspcntr |= DISPPLANE_8BPP;
2023 break;
2024 case 16:
2025 if (fb->depth == 15)
2026 dspcntr |= DISPPLANE_15_16BPP;
2027 else
2028 dspcntr |= DISPPLANE_16BPP;
2029 break;
2030 case 24:
2031 case 32:
2032 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2033 break;
2034 default:
17638cd6 2035 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2036 return -EINVAL;
2037 }
a6c45cf0 2038 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2039 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2040 dspcntr |= DISPPLANE_TILED;
2041 else
2042 dspcntr &= ~DISPPLANE_TILED;
2043 }
2044
5eddb70b 2045 I915_WRITE(reg, dspcntr);
81255565 2046
05394f39 2047 Start = obj->gtt_offset;
81255565
JB		 2048 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2049
4e6cfefc
CW		 2050 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2051 Start, Offset, x, y, fb->pitch);
5eddb70b 2052 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 2053 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2054 I915_WRITE(DSPSURF(plane), Start);
2055 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2056 I915_WRITE(DSPADDR(plane), Offset);
2057 } else
2058 I915_WRITE(DSPADDR(plane), Start + Offset);
2059 POSTING_READ(reg);
81255565 2060
17638cd6
JB		 2061 return 0;
2062}
2063
2064static int ironlake_update_plane(struct drm_crtc *crtc,
2065 struct drm_framebuffer *fb, int x, int y)
2066{
2067 struct drm_device *dev = crtc->dev;
2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2070 struct intel_framebuffer *intel_fb;
2071 struct drm_i915_gem_object *obj;
2072 int plane = intel_crtc->plane;
2073 unsigned long Start, Offset;
2074 u32 dspcntr;
2075 u32 reg;
2076
2077 switch (plane) {
2078 case 0:
2079 case 1:
2080 break;
2081 default:
2082 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2083 return -EINVAL;
2084 }
2085
2086 intel_fb = to_intel_framebuffer(fb);
2087 obj = intel_fb->obj;
2088
2089 reg = DSPCNTR(plane);
2090 dspcntr = I915_READ(reg);
2091 /* Mask out pixel format bits in case we change it */
2092 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2093 switch (fb->bits_per_pixel) {
2094 case 8:
2095 dspcntr |= DISPPLANE_8BPP;
2096 break;
2097 case 16:
2098 if (fb->depth != 16)
2099 return -EINVAL;
2100
2101 dspcntr |= DISPPLANE_16BPP;
2102 break;
2103 case 24:
2104 case 32:
2105 if (fb->depth == 24)
2106 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2107 else if (fb->depth == 30)
2108 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2109 else
2110 return -EINVAL;
2111 break;
2112 default:
2113 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2114 return -EINVAL;
2115 }
2116
2117 if (obj->tiling_mode != I915_TILING_NONE)
2118 dspcntr |= DISPPLANE_TILED;
2119 else
2120 dspcntr &= ~DISPPLANE_TILED;
2121
2122 /* must disable */
2123 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2124
2125 I915_WRITE(reg, dspcntr);
2126
2127 Start = obj->gtt_offset;
2128 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2129
2130 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2131 Start, Offset, x, y, fb->pitch);
2132 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2133 I915_WRITE(DSPSURF(plane), Start);
2134 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2135 I915_WRITE(DSPADDR(plane), Offset);
2136 POSTING_READ(reg);
2137
2138 return 0;
2139}
2140
2141/* Assume fb object is pinned & idle & fenced and just update base pointers */
2142static int
2143intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2144 int x, int y, enum mode_set_atomic state)
2145{
2146 struct drm_device *dev = crtc->dev;
2147 struct drm_i915_private *dev_priv = dev->dev_private;
2148 int ret;
2149
2150 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2151 if (ret)
2152 return ret;
2153
bed4a673 2154 intel_update_fbc(dev);
3dec0095 2155 intel_increase_pllclock(crtc);
81255565
JB		 2156
2157 return 0;
2158}
2159
5c3b82e2 2160static int
3c4fdcfb
KH		 2161intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2162 struct drm_framebuffer *old_fb)
79e53945
JB		 2163{
2164 struct drm_device *dev = crtc->dev;
79e53945
JB		 2165 struct drm_i915_master_private *master_priv;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2167 int ret;
79e53945
JB		 2168
2169 /* no fb bound */
2170 if (!crtc->fb) {
a5071c2f 2171 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2172 return 0;
2173 }
2174
265db958 2175 switch (intel_crtc->plane) {
5c3b82e2
CW		 2176 case 0:
2177 case 1:
2178 break;
2179 default:
a5071c2f 2180 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2181 return -EINVAL;
79e53945
JB		 2182 }
2183
5c3b82e2 2184 mutex_lock(&dev->struct_mutex);
265db958
CW		 2185 ret = intel_pin_and_fence_fb_obj(dev,
2186 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2187 NULL);
5c3b82e2
CW		 2188 if (ret != 0) {
2189 mutex_unlock(&dev->struct_mutex);
a5071c2f 2190 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2191 return ret;
2192 }
79e53945 2193
265db958 2194 if (old_fb) {
e6c3a2a6 2195 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2196 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2197
e6c3a2a6 2198 wait_event(dev_priv->pending_flip_queue,
01eec727 2199 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2200 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2201
2202 /* Big Hammer, we also need to ensure that any pending
2203 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2204 * current scanout is retired before unpinning the old
2205 * framebuffer.
01eec727
CW		 2206 *
2207 * This should only fail upon a hung GPU, in which case we
2208 * can safely continue.
85345517 2209 */
a8198eea 2210 ret = i915_gem_object_finish_gpu(obj);
01eec727 2211 (void) ret;
265db958
CW		 2212 }
2213
21c74a8e
JW		 2214 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2215 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2216 if (ret) {
265db958 2217 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2218 mutex_unlock(&dev->struct_mutex);
a5071c2f 2219 DRM_ERROR("failed to update base address\n");
4e6cfefc 2220 return ret;
79e53945 2221 }
3c4fdcfb 2222
b7f1de28
CW		 2223 if (old_fb) {
2224 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2225 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2226 }
652c393a 2227
5c3b82e2 2228 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2229
2230 if (!dev->primary->master)
5c3b82e2 2231 return 0;
79e53945
JB		 2232
2233 master_priv = dev->primary->master->driver_priv;
2234 if (!master_priv->sarea_priv)
5c3b82e2 2235 return 0;
79e53945 2236
265db958 2237 if (intel_crtc->pipe) {
79e53945
JB		 2238 master_priv->sarea_priv->pipeB_x = x;
2239 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2240 } else {
2241 master_priv->sarea_priv->pipeA_x = x;
2242 master_priv->sarea_priv->pipeA_y = y;
79e53945 2243 }
5c3b82e2
CW		 2244
2245 return 0;
79e53945
JB		 2246}
2247
5eddb70b 2248static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2249{
2250 struct drm_device *dev = crtc->dev;
2251 struct drm_i915_private *dev_priv = dev->dev_private;
2252 u32 dpa_ctl;
2253
28c97730 2254 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2255 dpa_ctl = I915_READ(DP_A);
2256 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2257
2258 if (clock < 200000) {
2259 u32 temp;
2260 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2261 /* workaround for 160Mhz:
2262 1) program 0x4600c bits 15:0 = 0x8124
2263 2) program 0x46010 bit 0 = 1
2264 3) program 0x46034 bit 24 = 1
2265 4) program 0x64000 bit 14 = 1
2266 */
2267 temp = I915_READ(0x4600c);
2268 temp &= 0xffff0000;
2269 I915_WRITE(0x4600c, temp | 0x8124);
2270
2271 temp = I915_READ(0x46010);
2272 I915_WRITE(0x46010, temp | 1);
2273
2274 temp = I915_READ(0x46034);
2275 I915_WRITE(0x46034, temp | (1 << 24));
2276 } else {
2277 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2278 }
2279 I915_WRITE(DP_A, dpa_ctl);
2280
5eddb70b 2281 POSTING_READ(DP_A);
32f9d658
ZW		 2282 udelay(500);
2283}
2284
5e84e1a4
ZW		 2285static void intel_fdi_normal_train(struct drm_crtc *crtc)
2286{
2287 struct drm_device *dev = crtc->dev;
2288 struct drm_i915_private *dev_priv = dev->dev_private;
2289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290 int pipe = intel_crtc->pipe;
2291 u32 reg, temp;
2292
2293 /* enable normal train */
2294 reg = FDI_TX_CTL(pipe);
2295 temp = I915_READ(reg);
61e499bf 2296 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2297 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2298 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2299 } else {
2300 temp &= ~FDI_LINK_TRAIN_NONE;
2301 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2302 }
5e84e1a4
ZW		 2303 I915_WRITE(reg, temp);
2304
2305 reg = FDI_RX_CTL(pipe);
2306 temp = I915_READ(reg);
2307 if (HAS_PCH_CPT(dev)) {
2308 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2309 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2310 } else {
2311 temp &= ~FDI_LINK_TRAIN_NONE;
2312 temp |= FDI_LINK_TRAIN_NONE;
2313 }
2314 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2315
2316 /* wait one idle pattern time */
2317 POSTING_READ(reg);
2318 udelay(1000);
357555c0
JB		 2319
2320 /* IVB wants error correction enabled */
2321 if (IS_IVYBRIDGE(dev))
2322 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2323 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2324}
2325
291427f5
JB		 2326static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2327{
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 u32 flags = I915_READ(SOUTH_CHICKEN1);
2330
2331 flags |= FDI_PHASE_SYNC_OVR(pipe);
2332 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2333 flags |= FDI_PHASE_SYNC_EN(pipe);
2334 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2335 POSTING_READ(SOUTH_CHICKEN1);
2336}
2337
8db9d77b
ZW		 2338/* The FDI link training functions for ILK/Ibexpeak. */
2339static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2340{
2341 struct drm_device *dev = crtc->dev;
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2344 int pipe = intel_crtc->pipe;
0fc932b8 2345 int plane = intel_crtc->plane;
5eddb70b 2346 u32 reg, temp, tries;
8db9d77b 2347
0fc932b8
JB		 2348 /* FDI needs bits from pipe & plane first */
2349 assert_pipe_enabled(dev_priv, pipe);
2350 assert_plane_enabled(dev_priv, plane);
2351
e1a44743
AJ		 2352 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2353 for train result */
5eddb70b
CW		 2354 reg = FDI_RX_IMR(pipe);
2355 temp = I915_READ(reg);
e1a44743
AJ		 2356 temp &= ~FDI_RX_SYMBOL_LOCK;
2357 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2358 I915_WRITE(reg, temp);
2359 I915_READ(reg);
e1a44743
AJ		 2360 udelay(150);
2361
8db9d77b 2362 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2363 reg = FDI_TX_CTL(pipe);
2364 temp = I915_READ(reg);
77ffb597
AJ		 2365 temp &= ~(7 << 19);
2366 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2367 temp &= ~FDI_LINK_TRAIN_NONE;
2368 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2369 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2370
5eddb70b
CW		 2371 reg = FDI_RX_CTL(pipe);
2372 temp = I915_READ(reg);
8db9d77b
ZW		 2373 temp &= ~FDI_LINK_TRAIN_NONE;
2374 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2375 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2376
2377 POSTING_READ(reg);
8db9d77b
ZW		 2378 udelay(150);
2379
5b2adf89 2380 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2381 if (HAS_PCH_IBX(dev)) {
2382 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2383 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2384 FDI_RX_PHASE_SYNC_POINTER_EN);
2385 }
5b2adf89 2386
5eddb70b 2387 reg = FDI_RX_IIR(pipe);
e1a44743 2388 for (tries = 0; tries < 5; tries++) {
5eddb70b 2389 temp = I915_READ(reg);
8db9d77b
ZW		 2390 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2391
2392 if ((temp & FDI_RX_BIT_LOCK)) {
2393 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2394 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2395 break;
2396 }
8db9d77b 2397 }
e1a44743 2398 if (tries == 5)
5eddb70b 2399 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2400
2401 /* Train 2 */
5eddb70b
CW		 2402 reg = FDI_TX_CTL(pipe);
2403 temp = I915_READ(reg);
8db9d77b
ZW		 2404 temp &= ~FDI_LINK_TRAIN_NONE;
2405 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2406 I915_WRITE(reg, temp);
8db9d77b 2407
5eddb70b
CW		 2408 reg = FDI_RX_CTL(pipe);
2409 temp = I915_READ(reg);
8db9d77b
ZW		 2410 temp &= ~FDI_LINK_TRAIN_NONE;
2411 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2412 I915_WRITE(reg, temp);
8db9d77b 2413
5eddb70b
CW		 2414 POSTING_READ(reg);
2415 udelay(150);
8db9d77b 2416
5eddb70b 2417 reg = FDI_RX_IIR(pipe);
e1a44743 2418 for (tries = 0; tries < 5; tries++) {
5eddb70b 2419 temp = I915_READ(reg);
8db9d77b
ZW		 2420 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2421
2422 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2423 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2424 DRM_DEBUG_KMS("FDI train 2 done.\n");
2425 break;
2426 }
8db9d77b 2427 }
e1a44743 2428 if (tries == 5)
5eddb70b 2429 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2430
2431 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2432
8db9d77b
ZW		 2433}
2434
311bd68e 2435static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2436 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2437 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2438 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2439 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2440};
2441
2442/* The FDI link training functions for SNB/Cougarpoint. */
2443static void gen6_fdi_link_train(struct drm_crtc *crtc)
2444{
2445 struct drm_device *dev = crtc->dev;
2446 struct drm_i915_private *dev_priv = dev->dev_private;
2447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2448 int pipe = intel_crtc->pipe;
5eddb70b 2449 u32 reg, temp, i;
8db9d77b 2450
e1a44743
AJ		 2451 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2452 for train result */
5eddb70b
CW		 2453 reg = FDI_RX_IMR(pipe);
2454 temp = I915_READ(reg);
e1a44743
AJ		 2455 temp &= ~FDI_RX_SYMBOL_LOCK;
2456 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2457 I915_WRITE(reg, temp);
2458
2459 POSTING_READ(reg);
e1a44743
AJ		 2460 udelay(150);
2461
8db9d77b 2462 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2463 reg = FDI_TX_CTL(pipe);
2464 temp = I915_READ(reg);
77ffb597
AJ		 2465 temp &= ~(7 << 19);
2466 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_1;
2469 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470 /* SNB-B */
2471 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2472 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2473
5eddb70b
CW		 2474 reg = FDI_RX_CTL(pipe);
2475 temp = I915_READ(reg);
8db9d77b
ZW		 2476 if (HAS_PCH_CPT(dev)) {
2477 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2478 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2479 } else {
2480 temp &= ~FDI_LINK_TRAIN_NONE;
2481 temp |= FDI_LINK_TRAIN_PATTERN_1;
2482 }
5eddb70b
CW		 2483 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2484
2485 POSTING_READ(reg);
8db9d77b
ZW		 2486 udelay(150);
2487
291427f5
JB		 2488 if (HAS_PCH_CPT(dev))
2489 cpt_phase_pointer_enable(dev, pipe);
2490
8db9d77b 2491 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2492 reg = FDI_TX_CTL(pipe);
2493 temp = I915_READ(reg);
8db9d77b
ZW		 2494 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2495 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2496 I915_WRITE(reg, temp);
2497
2498 POSTING_READ(reg);
8db9d77b
ZW		 2499 udelay(500);
2500
5eddb70b
CW		 2501 reg = FDI_RX_IIR(pipe);
2502 temp = I915_READ(reg);
8db9d77b
ZW		 2503 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2504
2505 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2506 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2507 DRM_DEBUG_KMS("FDI train 1 done.\n");
2508 break;
2509 }
2510 }
2511 if (i == 4)
5eddb70b 2512 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2513
2514 /* Train 2 */
5eddb70b
CW		 2515 reg = FDI_TX_CTL(pipe);
2516 temp = I915_READ(reg);
8db9d77b
ZW		 2517 temp &= ~FDI_LINK_TRAIN_NONE;
2518 temp |= FDI_LINK_TRAIN_PATTERN_2;
2519 if (IS_GEN6(dev)) {
2520 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2521 /* SNB-B */
2522 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2523 }
5eddb70b 2524 I915_WRITE(reg, temp);
8db9d77b 2525
5eddb70b
CW		 2526 reg = FDI_RX_CTL(pipe);
2527 temp = I915_READ(reg);
8db9d77b
ZW		 2528 if (HAS_PCH_CPT(dev)) {
2529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2530 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2531 } else {
2532 temp &= ~FDI_LINK_TRAIN_NONE;
2533 temp |= FDI_LINK_TRAIN_PATTERN_2;
2534 }
5eddb70b
CW		 2535 I915_WRITE(reg, temp);
2536
2537 POSTING_READ(reg);
8db9d77b
ZW		 2538 udelay(150);
2539
2540 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
8db9d77b
ZW		 2543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2544 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2545 I915_WRITE(reg, temp);
2546
2547 POSTING_READ(reg);
8db9d77b
ZW		 2548 udelay(500);
2549
5eddb70b
CW		 2550 reg = FDI_RX_IIR(pipe);
2551 temp = I915_READ(reg);
8db9d77b
ZW		 2552 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2553
2554 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2555 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2556 DRM_DEBUG_KMS("FDI train 2 done.\n");
2557 break;
2558 }
2559 }
2560 if (i == 4)
5eddb70b 2561 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2562
2563 DRM_DEBUG_KMS("FDI train done.\n");
2564}
2565
357555c0
JB		 2566/* Manual link training for Ivy Bridge A0 parts */
2567static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2568{
2569 struct drm_device *dev = crtc->dev;
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2572 int pipe = intel_crtc->pipe;
2573 u32 reg, temp, i;
2574
2575 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2576 for train result */
2577 reg = FDI_RX_IMR(pipe);
2578 temp = I915_READ(reg);
2579 temp &= ~FDI_RX_SYMBOL_LOCK;
2580 temp &= ~FDI_RX_BIT_LOCK;
2581 I915_WRITE(reg, temp);
2582
2583 POSTING_READ(reg);
2584 udelay(150);
2585
2586 /* enable CPU FDI TX and PCH FDI RX */
2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 temp &= ~(7 << 19);
2590 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2591 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2592 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2593 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2594 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2595 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2596
2597 reg = FDI_RX_CTL(pipe);
2598 temp = I915_READ(reg);
2599 temp &= ~FDI_LINK_TRAIN_AUTO;
2600 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2601 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2602 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2603
2604 POSTING_READ(reg);
2605 udelay(150);
2606
291427f5
JB		 2607 if (HAS_PCH_CPT(dev))
2608 cpt_phase_pointer_enable(dev, pipe);
2609
357555c0
JB		 2610 for (i = 0; i < 4; i++ ) {
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614 temp |= snb_b_fdi_train_param[i];
2615 I915_WRITE(reg, temp);
2616
2617 POSTING_READ(reg);
2618 udelay(500);
2619
2620 reg = FDI_RX_IIR(pipe);
2621 temp = I915_READ(reg);
2622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623
2624 if (temp & FDI_RX_BIT_LOCK ||
2625 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2626 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2627 DRM_DEBUG_KMS("FDI train 1 done.\n");
2628 break;
2629 }
2630 }
2631 if (i == 4)
2632 DRM_ERROR("FDI train 1 fail!\n");
2633
2634 /* Train 2 */
2635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
2637 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2638 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2639 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2641 I915_WRITE(reg, temp);
2642
2643 reg = FDI_RX_CTL(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
2650 udelay(150);
2651
2652 for (i = 0; i < 4; i++ ) {
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2656 temp |= snb_b_fdi_train_param[i];
2657 I915_WRITE(reg, temp);
2658
2659 POSTING_READ(reg);
2660 udelay(500);
2661
2662 reg = FDI_RX_IIR(pipe);
2663 temp = I915_READ(reg);
2664 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2665
2666 if (temp & FDI_RX_SYMBOL_LOCK) {
2667 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2668 DRM_DEBUG_KMS("FDI train 2 done.\n");
2669 break;
2670 }
2671 }
2672 if (i == 4)
2673 DRM_ERROR("FDI train 2 fail!\n");
2674
2675 DRM_DEBUG_KMS("FDI train done.\n");
2676}
2677
2678static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2679{
2680 struct drm_device *dev = crtc->dev;
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2683 int pipe = intel_crtc->pipe;
5eddb70b 2684 u32 reg, temp;
79e53945 2685
c64e311e 2686 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2687 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2688 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2689
c98e9dcf 2690 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2691 reg = FDI_RX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2694 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2695 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2696 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2697
2698 POSTING_READ(reg);
c98e9dcf
JB		 2699 udelay(200);
2700
2701 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2702 temp = I915_READ(reg);
2703 I915_WRITE(reg, temp | FDI_PCDCLK);
2704
2705 POSTING_READ(reg);
c98e9dcf
JB		 2706 udelay(200);
2707
2708 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2709 reg = FDI_TX_CTL(pipe);
2710 temp = I915_READ(reg);
c98e9dcf 2711 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2712 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2713
2714 POSTING_READ(reg);
c98e9dcf 2715 udelay(100);
6be4a607 2716 }
0e23b99d
JB		 2717}
2718
291427f5
JB		 2719static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2720{
2721 struct drm_i915_private *dev_priv = dev->dev_private;
2722 u32 flags = I915_READ(SOUTH_CHICKEN1);
2723
2724 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2725 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2726 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2727 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2728 POSTING_READ(SOUTH_CHICKEN1);
2729}
0fc932b8
JB		 2730static void ironlake_fdi_disable(struct drm_crtc *crtc)
2731{
2732 struct drm_device *dev = crtc->dev;
2733 struct drm_i915_private *dev_priv = dev->dev_private;
2734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2735 int pipe = intel_crtc->pipe;
2736 u32 reg, temp;
2737
2738 /* disable CPU FDI tx and PCH FDI rx */
2739 reg = FDI_TX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2742 POSTING_READ(reg);
2743
2744 reg = FDI_RX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 temp &= ~(0x7 << 16);
2747 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2748 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2749
2750 POSTING_READ(reg);
2751 udelay(100);
2752
2753 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2754 if (HAS_PCH_IBX(dev)) {
2755 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2756 I915_WRITE(FDI_RX_CHICKEN(pipe),
2757 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2758 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2759 } else if (HAS_PCH_CPT(dev)) {
2760 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2761 }
0fc932b8
JB		 2762
2763 /* still set train pattern 1 */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_NONE;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1;
2768 I915_WRITE(reg, temp);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 if (HAS_PCH_CPT(dev)) {
2773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2775 } else {
2776 temp &= ~FDI_LINK_TRAIN_NONE;
2777 temp |= FDI_LINK_TRAIN_PATTERN_1;
2778 }
2779 /* BPC in FDI rx is consistent with that in PIPECONF */
2780 temp &= ~(0x07 << 16);
2781 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2782 I915_WRITE(reg, temp);
2783
2784 POSTING_READ(reg);
2785 udelay(100);
2786}
2787
6b383a7f
CW		 2788/*
2789 * When we disable a pipe, we need to clear any pending scanline wait events
2790 * to avoid hanging the ring, which we assume we are waiting on.
2791 */
2792static void intel_clear_scanline_wait(struct drm_device *dev)
2793{
2794 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2795 struct intel_ring_buffer *ring;
6b383a7f
CW		 2796 u32 tmp;
2797
2798 if (IS_GEN2(dev))
2799 /* Can't break the hang on i8xx */
2800 return;
2801
1ec14ad3 2802 ring = LP_RING(dev_priv);
8168bd48
CW		 2803 tmp = I915_READ_CTL(ring);
2804 if (tmp & RING_WAIT)
2805 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2806}
2807
e6c3a2a6
CW		 2808static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2809{
05394f39 2810 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2811 struct drm_i915_private *dev_priv;
2812
2813 if (crtc->fb == NULL)
2814 return;
2815
05394f39 2816 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2817 dev_priv = crtc->dev->dev_private;
2818 wait_event(dev_priv->pending_flip_queue,
05394f39 2819 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2820}
2821
040484af
JB		 2822static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2823{
2824 struct drm_device *dev = crtc->dev;
2825 struct drm_mode_config *mode_config = &dev->mode_config;
2826 struct intel_encoder *encoder;
2827
2828 /*
2829 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2830 * must be driven by its own crtc; no sharing is possible.
2831 */
2832 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2833 if (encoder->base.crtc != crtc)
2834 continue;
2835
2836 switch (encoder->type) {
2837 case INTEL_OUTPUT_EDP:
2838 if (!intel_encoder_is_pch_edp(&encoder->base))
2839 return false;
2840 continue;
2841 }
2842 }
2843
2844 return true;
2845}
2846
f67a559d
JB		 2847/*
2848 * Enable PCH resources required for PCH ports:
2849 * - PCH PLLs
2850 * - FDI training & RX/TX
2851 * - update transcoder timings
2852 * - DP transcoding bits
2853 * - transcoder
2854 */
2855static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2856{
2857 struct drm_device *dev = crtc->dev;
2858 struct drm_i915_private *dev_priv = dev->dev_private;
2859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2860 int pipe = intel_crtc->pipe;
5eddb70b 2861 u32 reg, temp;
2c07245f 2862
c98e9dcf 2863 /* For PCH output, training FDI link */
674cf967 2864 dev_priv->display.fdi_link_train(crtc);
2c07245f 2865
92f2584a 2866 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2867
c98e9dcf
JB		 2868 if (HAS_PCH_CPT(dev)) {
2869 /* Be sure PCH DPLL SEL is set */
2870 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2871 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2872 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2873 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2874 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2875 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2876 }
5eddb70b 2877
d9b6cb56
JB		 2878 /* set transcoder timing, panel must allow it */
2879 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2880 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2881 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2882 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2883
5eddb70b
CW		 2884 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2885 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2886 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2887
5e84e1a4
ZW		 2888 intel_fdi_normal_train(crtc);
2889
c98e9dcf
JB		 2890 /* For PCH DP, enable TRANS_DP_CTL */
2891 if (HAS_PCH_CPT(dev) &&
2892 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
9325c9f0 2893 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2894 reg = TRANS_DP_CTL(pipe);
2895 temp = I915_READ(reg);
2896 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2897 TRANS_DP_SYNC_MASK |
2898 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2899 temp |= (TRANS_DP_OUTPUT_ENABLE |
2900 TRANS_DP_ENH_FRAMING);
9325c9f0 2901 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2902
2903 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2904 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2905 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2906 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2907
2908 switch (intel_trans_dp_port_sel(crtc)) {
2909 case PCH_DP_B:
5eddb70b 2910 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2911 break;
2912 case PCH_DP_C:
5eddb70b 2913 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2914 break;
2915 case PCH_DP_D:
5eddb70b 2916 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2917 break;
2918 default:
2919 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2920 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2921 break;
32f9d658 2922 }
2c07245f 2923
5eddb70b 2924 I915_WRITE(reg, temp);
6be4a607 2925 }
b52eb4dc 2926
040484af 2927 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2928}
2929
2930static void ironlake_crtc_enable(struct drm_crtc *crtc)
2931{
2932 struct drm_device *dev = crtc->dev;
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935 int pipe = intel_crtc->pipe;
2936 int plane = intel_crtc->plane;
2937 u32 temp;
2938 bool is_pch_port;
2939
2940 if (intel_crtc->active)
2941 return;
2942
2943 intel_crtc->active = true;
2944 intel_update_watermarks(dev);
2945
2946 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2947 temp = I915_READ(PCH_LVDS);
2948 if ((temp & LVDS_PORT_EN) == 0)
2949 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2950 }
2951
2952 is_pch_port = intel_crtc_driving_pch(crtc);
2953
2954 if (is_pch_port)
357555c0 2955 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2956 else
2957 ironlake_fdi_disable(crtc);
2958
2959 /* Enable panel fitting for LVDS */
2960 if (dev_priv->pch_pf_size &&
2961 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2962 /* Force use of hard-coded filter coefficients
2963 * as some pre-programmed values are broken,
2964 * e.g. x201.
2965 */
9db4a9c7
JB		 2966 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2967 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2968 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2969 }
2970
9c54c0dd
JB		 2971 /*
2972 * On ILK+ LUT must be loaded before the pipe is running but with
2973 * clocks enabled
2974 */
2975 intel_crtc_load_lut(crtc);
2976
f67a559d
JB		 2977 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2978 intel_enable_plane(dev_priv, plane, pipe);
2979
2980 if (is_pch_port)
2981 ironlake_pch_enable(crtc);
c98e9dcf 2982
d1ebd816 2983 mutex_lock(&dev->struct_mutex);
bed4a673 2984 intel_update_fbc(dev);
d1ebd816
BW		 2985 mutex_unlock(&dev->struct_mutex);
2986
6b383a7f 2987 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2988}
2989
2990static void ironlake_crtc_disable(struct drm_crtc *crtc)
2991{
2992 struct drm_device *dev = crtc->dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2995 int pipe = intel_crtc->pipe;
2996 int plane = intel_crtc->plane;
5eddb70b 2997 u32 reg, temp;
b52eb4dc 2998
f7abfe8b
CW		 2999 if (!intel_crtc->active)
3000 return;
3001
e6c3a2a6 3002 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3003 drm_vblank_off(dev, pipe);
6b383a7f 3004 intel_crtc_update_cursor(crtc, false);
5eddb70b 3005
b24e7179 3006 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3007
973d04f9
CW		 3008 if (dev_priv->cfb_plane == plane)
3009 intel_disable_fbc(dev);
2c07245f 3010
b24e7179 3011 intel_disable_pipe(dev_priv, pipe);
32f9d658 3012
6be4a607 3013 /* Disable PF */
9db4a9c7
JB		 3014 I915_WRITE(PF_CTL(pipe), 0);
3015 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3016
0fc932b8 3017 ironlake_fdi_disable(crtc);
2c07245f 3018
47a05eca
JB		 3019 /* This is a horrible layering violation; we should be doing this in
3020 * the connector/encoder ->prepare instead, but we don't always have
3021 * enough information there about the config to know whether it will
3022 * actually be necessary or just cause undesired flicker.
3023 */
3024 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3025
040484af 3026 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3027
6be4a607
JB		 3028 if (HAS_PCH_CPT(dev)) {
3029 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3030 reg = TRANS_DP_CTL(pipe);
3031 temp = I915_READ(reg);
3032 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3033 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3034 I915_WRITE(reg, temp);
6be4a607
JB		 3035
3036 /* disable DPLL_SEL */
3037 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3038 switch (pipe) {
3039 case 0:
3040 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3041 break;
3042 case 1:
6be4a607 3043 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3044 break;
3045 case 2:
3046 /* FIXME: manage transcoder PLLs? */
3047 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3048 break;
3049 default:
3050 BUG(); /* wtf */
3051 }
6be4a607 3052 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3053 }
e3421a18 3054
6be4a607 3055 /* disable PCH DPLL */
92f2584a 3056 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3057
6be4a607 3058 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3059 reg = FDI_RX_CTL(pipe);
3060 temp = I915_READ(reg);
3061 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3062
6be4a607 3063 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3064 reg = FDI_TX_CTL(pipe);
3065 temp = I915_READ(reg);
3066 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3067
3068 POSTING_READ(reg);
6be4a607 3069 udelay(100);
8db9d77b 3070
5eddb70b
CW		 3071 reg = FDI_RX_CTL(pipe);
3072 temp = I915_READ(reg);
3073 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3074
6be4a607 3075 /* Wait for the clocks to turn off. */
5eddb70b 3076 POSTING_READ(reg);
6be4a607 3077 udelay(100);
6b383a7f 3078
f7abfe8b 3079 intel_crtc->active = false;
6b383a7f 3080 intel_update_watermarks(dev);
d1ebd816
BW		 3081
3082 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3083 intel_update_fbc(dev);
3084 intel_clear_scanline_wait(dev);
d1ebd816 3085 mutex_unlock(&dev->struct_mutex);
6be4a607 3086}
1b3c7a47 3087
6be4a607
JB		 3088static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3089{
3090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3091 int pipe = intel_crtc->pipe;
3092 int plane = intel_crtc->plane;
8db9d77b 3093
6be4a607
JB		 3094 /* XXX: When our outputs are all unaware of DPMS modes other than off
3095 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3096 */
3097 switch (mode) {
3098 case DRM_MODE_DPMS_ON:
3099 case DRM_MODE_DPMS_STANDBY:
3100 case DRM_MODE_DPMS_SUSPEND:
3101 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3102 ironlake_crtc_enable(crtc);
3103 break;
1b3c7a47 3104
6be4a607
JB		 3105 case DRM_MODE_DPMS_OFF:
3106 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3107 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3108 break;
3109 }
3110}
3111
02e792fb
DV		 3112static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3113{
02e792fb 3114 if (!enable && intel_crtc->overlay) {
23f09ce3 3115 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3116 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3117
23f09ce3 3118 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3119 dev_priv->mm.interruptible = false;
3120 (void) intel_overlay_switch_off(intel_crtc->overlay);
3121 dev_priv->mm.interruptible = true;
23f09ce3 3122 mutex_unlock(&dev->struct_mutex);
02e792fb 3123 }
02e792fb 3124
5dcdbcb0
CW		 3125 /* Let userspace switch the overlay on again. In most cases userspace
3126 * has to recompute where to put it anyway.
3127 */
02e792fb
DV		 3128}
3129
0b8765c6 3130static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3131{
3132 struct drm_device *dev = crtc->dev;
79e53945
JB		 3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3135 int pipe = intel_crtc->pipe;
80824003 3136 int plane = intel_crtc->plane;
79e53945 3137
f7abfe8b
CW		 3138 if (intel_crtc->active)
3139 return;
3140
3141 intel_crtc->active = true;
6b383a7f
CW		 3142 intel_update_watermarks(dev);
3143
63d7bbe9 3144 intel_enable_pll(dev_priv, pipe);
040484af 3145 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3146 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3147
0b8765c6 3148 intel_crtc_load_lut(crtc);
bed4a673 3149 intel_update_fbc(dev);
79e53945 3150
0b8765c6
JB		 3151 /* Give the overlay scaler a chance to enable if it's on this pipe */
3152 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3153 intel_crtc_update_cursor(crtc, true);
0b8765c6 3154}
79e53945 3155
0b8765c6
JB		 3156static void i9xx_crtc_disable(struct drm_crtc *crtc)
3157{
3158 struct drm_device *dev = crtc->dev;
3159 struct drm_i915_private *dev_priv = dev->dev_private;
3160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3161 int pipe = intel_crtc->pipe;
3162 int plane = intel_crtc->plane;
b690e96c 3163
f7abfe8b
CW		 3164 if (!intel_crtc->active)
3165 return;
3166
0b8765c6 3167 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3168 intel_crtc_wait_for_pending_flips(crtc);
3169 drm_vblank_off(dev, pipe);
0b8765c6 3170 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3171 intel_crtc_update_cursor(crtc, false);
0b8765c6 3172
973d04f9
CW		 3173 if (dev_priv->cfb_plane == plane)
3174 intel_disable_fbc(dev);
79e53945 3175
b24e7179 3176 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3177 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3178 intel_disable_pll(dev_priv, pipe);
0b8765c6 3179
f7abfe8b 3180 intel_crtc->active = false;
6b383a7f
CW		 3181 intel_update_fbc(dev);
3182 intel_update_watermarks(dev);
3183 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3184}
3185
3186static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3187{
3188 /* XXX: When our outputs are all unaware of DPMS modes other than off
3189 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3190 */
3191 switch (mode) {
3192 case DRM_MODE_DPMS_ON:
3193 case DRM_MODE_DPMS_STANDBY:
3194 case DRM_MODE_DPMS_SUSPEND:
3195 i9xx_crtc_enable(crtc);
3196 break;
3197 case DRM_MODE_DPMS_OFF:
3198 i9xx_crtc_disable(crtc);
79e53945
JB		 3199 break;
3200 }
2c07245f
ZW		 3201}
3202
3203/**
3204 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3205 */
3206static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3207{
3208 struct drm_device *dev = crtc->dev;
e70236a8 3209 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3210 struct drm_i915_master_private *master_priv;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212 int pipe = intel_crtc->pipe;
3213 bool enabled;
3214
032d2a0d
CW		 3215 if (intel_crtc->dpms_mode == mode)
3216 return;
3217
65655d4a 3218 intel_crtc->dpms_mode = mode;
debcaddc 3219
e70236a8 3220 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3221
3222 if (!dev->primary->master)
3223 return;
3224
3225 master_priv = dev->primary->master->driver_priv;
3226 if (!master_priv->sarea_priv)
3227 return;
3228
3229 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3230
3231 switch (pipe) {
3232 case 0:
3233 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3234 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3235 break;
3236 case 1:
3237 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3238 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3239 break;
3240 default:
9db4a9c7 3241 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3242 break;
3243 }
79e53945
JB		 3244}
3245
cdd59983
CW		 3246static void intel_crtc_disable(struct drm_crtc *crtc)
3247{
3248 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3249 struct drm_device *dev = crtc->dev;
3250
3251 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3252
3253 if (crtc->fb) {
3254 mutex_lock(&dev->struct_mutex);
3255 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3256 mutex_unlock(&dev->struct_mutex);
3257 }
3258}
3259
7e7d76c3
JB		 3260/* Prepare for a mode set.
3261 *
3262 * Note we could be a lot smarter here. We need to figure out which outputs
3263 * will be enabled, which disabled (in short, how the config will changes)
3264 * and perform the minimum necessary steps to accomplish that, e.g. updating
3265 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3266 * panel fitting is in the proper state, etc.
3267 */
3268static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3269{
7e7d76c3 3270 i9xx_crtc_disable(crtc);
79e53945
JB		 3271}
3272
7e7d76c3 3273static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3274{
7e7d76c3 3275 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3276}
3277
3278static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3279{
7e7d76c3 3280 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3281}
3282
3283static void ironlake_crtc_commit(struct drm_crtc *crtc)
3284{
7e7d76c3 3285 ironlake_crtc_enable(crtc);
79e53945
JB		 3286}
3287
3288void intel_encoder_prepare (struct drm_encoder *encoder)
3289{
3290 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3291 /* lvds has its own version of prepare see intel_lvds_prepare */
3292 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3293}
3294
3295void intel_encoder_commit (struct drm_encoder *encoder)
3296{
3297 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3298 /* lvds has its own version of commit see intel_lvds_commit */
3299 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3300}
3301
ea5b213a
CW		 3302void intel_encoder_destroy(struct drm_encoder *encoder)
3303{
4ef69c7a 3304 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3305
ea5b213a
CW		 3306 drm_encoder_cleanup(encoder);
3307 kfree(intel_encoder);
3308}
3309
79e53945
JB		 3310static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3311 struct drm_display_mode *mode,
3312 struct drm_display_mode *adjusted_mode)
3313{
2c07245f 3314 struct drm_device *dev = crtc->dev;
89749350 3315
bad720ff 3316 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3317 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3318 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3319 return false;
2c07245f 3320 }
89749350
CW		 3321
3322 /* XXX some encoders set the crtcinfo, others don't.
3323 * Obviously we need some form of conflict resolution here...
3324 */
3325 if (adjusted_mode->crtc_htotal == 0)
3326 drm_mode_set_crtcinfo(adjusted_mode, 0);
3327
79e53945
JB		 3328 return true;
3329}
3330
e70236a8
JB		 3331static int i945_get_display_clock_speed(struct drm_device *dev)
3332{
3333 return 400000;
3334}
79e53945 3335
e70236a8 3336static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3337{
e70236a8
JB		 3338 return 333000;
3339}
79e53945 3340
e70236a8
JB		 3341static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3342{
3343 return 200000;
3344}
79e53945 3345
e70236a8
JB		 3346static int i915gm_get_display_clock_speed(struct drm_device *dev)
3347{
3348 u16 gcfgc = 0;
79e53945 3349
e70236a8
JB		 3350 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3351
3352 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3353 return 133000;
3354 else {
3355 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3356 case GC_DISPLAY_CLOCK_333_MHZ:
3357 return 333000;
3358 default:
3359 case GC_DISPLAY_CLOCK_190_200_MHZ:
3360 return 190000;
79e53945 3361 }
e70236a8
JB		 3362 }
3363}
3364
3365static int i865_get_display_clock_speed(struct drm_device *dev)
3366{
3367 return 266000;
3368}
3369
3370static int i855_get_display_clock_speed(struct drm_device *dev)
3371{
3372 u16 hpllcc = 0;
3373 /* Assume that the hardware is in the high speed state. This
3374 * should be the default.
3375 */
3376 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3377 case GC_CLOCK_133_200:
3378 case GC_CLOCK_100_200:
3379 return 200000;
3380 case GC_CLOCK_166_250:
3381 return 250000;
3382 case GC_CLOCK_100_133:
79e53945 3383 return 133000;
e70236a8 3384 }
79e53945 3385
e70236a8
JB		 3386 /* Shouldn't happen */
3387 return 0;
3388}
79e53945 3389
e70236a8
JB		 3390static int i830_get_display_clock_speed(struct drm_device *dev)
3391{
3392 return 133000;
79e53945
JB		 3393}
3394
2c07245f
ZW		 3395struct fdi_m_n {
3396 u32 tu;
3397 u32 gmch_m;
3398 u32 gmch_n;
3399 u32 link_m;
3400 u32 link_n;
3401};
3402
3403static void
3404fdi_reduce_ratio(u32 *num, u32 *den)
3405{
3406 while (*num > 0xffffff || *den > 0xffffff) {
3407 *num >>= 1;
3408 *den >>= 1;
3409 }
3410}
3411
2c07245f 3412static void
f2b115e6
AJ		 3413ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3414 int link_clock, struct fdi_m_n *m_n)
2c07245f 3415{
2c07245f
ZW		 3416 m_n->tu = 64; /* default size */
3417
22ed1113
CW		 3418 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3419 m_n->gmch_m = bits_per_pixel * pixel_clock;
3420 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3421 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3422
22ed1113
CW		 3423 m_n->link_m = pixel_clock;
3424 m_n->link_n = link_clock;
2c07245f
ZW		 3425 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3426}
3427
3428
7662c8bd
SL		 3429struct intel_watermark_params {
3430 unsigned long fifo_size;
3431 unsigned long max_wm;
3432 unsigned long default_wm;
3433 unsigned long guard_size;
3434 unsigned long cacheline_size;
3435};
3436
f2b115e6 3437/* Pineview has different values for various configs */
d210246a 3438static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3439 PINEVIEW_DISPLAY_FIFO,
3440 PINEVIEW_MAX_WM,
3441 PINEVIEW_DFT_WM,
3442 PINEVIEW_GUARD_WM,
3443 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3444};
d210246a 3445static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3446 PINEVIEW_DISPLAY_FIFO,
3447 PINEVIEW_MAX_WM,
3448 PINEVIEW_DFT_HPLLOFF_WM,
3449 PINEVIEW_GUARD_WM,
3450 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3451};
d210246a 3452static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3453 PINEVIEW_CURSOR_FIFO,
3454 PINEVIEW_CURSOR_MAX_WM,
3455 PINEVIEW_CURSOR_DFT_WM,
3456 PINEVIEW_CURSOR_GUARD_WM,
3457 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3458};
d210246a 3459static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3460 PINEVIEW_CURSOR_FIFO,
3461 PINEVIEW_CURSOR_MAX_WM,
3462 PINEVIEW_CURSOR_DFT_WM,
3463 PINEVIEW_CURSOR_GUARD_WM,
3464 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3465};
d210246a 3466static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3467 G4X_FIFO_SIZE,
3468 G4X_MAX_WM,
3469 G4X_MAX_WM,
3470 2,
3471 G4X_FIFO_LINE_SIZE,
3472};
d210246a 3473static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3474 I965_CURSOR_FIFO,
3475 I965_CURSOR_MAX_WM,
3476 I965_CURSOR_DFT_WM,
3477 2,
3478 G4X_FIFO_LINE_SIZE,
3479};
d210246a 3480static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3481 I965_CURSOR_FIFO,
3482 I965_CURSOR_MAX_WM,
3483 I965_CURSOR_DFT_WM,
3484 2,
3485 I915_FIFO_LINE_SIZE,
3486};
d210246a 3487static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3488 I945_FIFO_SIZE,
7662c8bd
SL		 3489 I915_MAX_WM,
3490 1,
dff33cfc
JB		 3491 2,
3492 I915_FIFO_LINE_SIZE
7662c8bd 3493};
d210246a 3494static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3495 I915_FIFO_SIZE,
7662c8bd
SL		 3496 I915_MAX_WM,
3497 1,
dff33cfc 3498 2,
7662c8bd
SL		 3499 I915_FIFO_LINE_SIZE
3500};
d210246a 3501static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3502 I855GM_FIFO_SIZE,
3503 I915_MAX_WM,
3504 1,
dff33cfc 3505 2,
7662c8bd
SL		 3506 I830_FIFO_LINE_SIZE
3507};
d210246a 3508static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3509 I830_FIFO_SIZE,
3510 I915_MAX_WM,
3511 1,
dff33cfc 3512 2,
7662c8bd
SL		 3513 I830_FIFO_LINE_SIZE
3514};
3515
d210246a 3516static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3517 ILK_DISPLAY_FIFO,
3518 ILK_DISPLAY_MAXWM,
3519 ILK_DISPLAY_DFTWM,
3520 2,
3521 ILK_FIFO_LINE_SIZE
3522};
d210246a 3523static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3524 ILK_CURSOR_FIFO,
3525 ILK_CURSOR_MAXWM,
3526 ILK_CURSOR_DFTWM,
3527 2,
3528 ILK_FIFO_LINE_SIZE
3529};
d210246a 3530static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3531 ILK_DISPLAY_SR_FIFO,
3532 ILK_DISPLAY_MAX_SRWM,
3533 ILK_DISPLAY_DFT_SRWM,
3534 2,
3535 ILK_FIFO_LINE_SIZE
3536};
d210246a 3537static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3538 ILK_CURSOR_SR_FIFO,
3539 ILK_CURSOR_MAX_SRWM,
3540 ILK_CURSOR_DFT_SRWM,
3541 2,
3542 ILK_FIFO_LINE_SIZE
3543};
3544
d210246a 3545static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3546 SNB_DISPLAY_FIFO,
3547 SNB_DISPLAY_MAXWM,
3548 SNB_DISPLAY_DFTWM,
3549 2,
3550 SNB_FIFO_LINE_SIZE
3551};
d210246a 3552static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3553 SNB_CURSOR_FIFO,
3554 SNB_CURSOR_MAXWM,
3555 SNB_CURSOR_DFTWM,
3556 2,
3557 SNB_FIFO_LINE_SIZE
3558};
d210246a 3559static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3560 SNB_DISPLAY_SR_FIFO,
3561 SNB_DISPLAY_MAX_SRWM,
3562 SNB_DISPLAY_DFT_SRWM,
3563 2,
3564 SNB_FIFO_LINE_SIZE
3565};
d210246a 3566static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3567 SNB_CURSOR_SR_FIFO,
3568 SNB_CURSOR_MAX_SRWM,
3569 SNB_CURSOR_DFT_SRWM,
3570 2,
3571 SNB_FIFO_LINE_SIZE
3572};
3573
3574
dff33cfc
JB		 3575/**
3576 * intel_calculate_wm - calculate watermark level
3577 * @clock_in_khz: pixel clock
3578 * @wm: chip FIFO params
3579 * @pixel_size: display pixel size
3580 * @latency_ns: memory latency for the platform
3581 *
3582 * Calculate the watermark level (the level at which the display plane will
3583 * start fetching from memory again). Each chip has a different display
3584 * FIFO size and allocation, so the caller needs to figure that out and pass
3585 * in the correct intel_watermark_params structure.
3586 *
3587 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3588 * on the pixel size. When it reaches the watermark level, it'll start
3589 * fetching FIFO line sized based chunks from memory until the FIFO fills
3590 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3591 * will occur, and a display engine hang could result.
3592 */
7662c8bd 3593static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3594 const struct intel_watermark_params *wm,
3595 int fifo_size,
7662c8bd
SL		 3596 int pixel_size,
3597 unsigned long latency_ns)
3598{
390c4dd4 3599 long entries_required, wm_size;
dff33cfc 3600
d660467c
JB		 3601 /*
3602 * Note: we need to make sure we don't overflow for various clock &
3603 * latency values.
3604 * clocks go from a few thousand to several hundred thousand.
3605 * latency is usually a few thousand
3606 */
3607 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3608 1000;
8de9b311 3609 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3610
bbb0aef5 3611 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3612
d210246a 3613 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3614
bbb0aef5 3615 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3616
390c4dd4
JB		 3617 /* Don't promote wm_size to unsigned... */
3618 if (wm_size > (long)wm->max_wm)
7662c8bd 3619 wm_size = wm->max_wm;
c3add4b6 3620 if (wm_size <= 0)
7662c8bd
SL		 3621 wm_size = wm->default_wm;
3622 return wm_size;
3623}
3624
3625struct cxsr_latency {
3626 int is_desktop;
95534263 3627 int is_ddr3;
7662c8bd
SL		 3628 unsigned long fsb_freq;
3629 unsigned long mem_freq;
3630 unsigned long display_sr;
3631 unsigned long display_hpll_disable;
3632 unsigned long cursor_sr;
3633 unsigned long cursor_hpll_disable;
3634};
3635
403c89ff 3636static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3637 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3638 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3639 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3640 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3641 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3642
3643 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3644 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3645 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3646 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3647 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3648
3649 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3650 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3651 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3652 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3653 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3654
3655 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3656 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3657 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3658 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3659 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3660
3661 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3662 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3663 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3664 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3665 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3666
3667 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3668 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3669 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3670 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3671 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3672};
3673
403c89ff
CW		 3674static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3675 int is_ddr3,
3676 int fsb,
3677 int mem)
7662c8bd 3678{
403c89ff 3679 const struct cxsr_latency *latency;
7662c8bd 3680 int i;
7662c8bd
SL		 3681
3682 if (fsb == 0 || mem == 0)
3683 return NULL;
3684
3685 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3686 latency = &cxsr_latency_table[i];
3687 if (is_desktop == latency->is_desktop &&
95534263 3688 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3689 fsb == latency->fsb_freq && mem == latency->mem_freq)
3690 return latency;
7662c8bd 3691 }
decbbcda 3692
28c97730 3693 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3694
3695 return NULL;
7662c8bd
SL		 3696}
3697
f2b115e6 3698static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3699{
3700 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3701
3702 /* deactivate cxsr */
3e33d94d 3703 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3704}
3705
bcc24fb4
JB		 3706/*
3707 * Latency for FIFO fetches is dependent on several factors:
3708 * - memory configuration (speed, channels)
3709 * - chipset
3710 * - current MCH state
3711 * It can be fairly high in some situations, so here we assume a fairly
3712 * pessimal value. It's a tradeoff between extra memory fetches (if we
3713 * set this value too high, the FIFO will fetch frequently to stay full)
3714 * and power consumption (set it too low to save power and we might see
3715 * FIFO underruns and display "flicker").
3716 *
3717 * A value of 5us seems to be a good balance; safe for very low end
3718 * platforms but not overly aggressive on lower latency configs.
3719 */
69e302a9 3720static const int latency_ns = 5000;
7662c8bd 3721
e70236a8 3722static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3723{
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 uint32_t dsparb = I915_READ(DSPARB);
3726 int size;
3727
8de9b311
CW		 3728 size = dsparb & 0x7f;
3729 if (plane)
3730 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3731
28c97730 3732 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3733 plane ? "B" : "A", size);
dff33cfc
JB		 3734
3735 return size;
3736}
7662c8bd 3737
e70236a8
JB		 3738static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3739{
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741 uint32_t dsparb = I915_READ(DSPARB);
3742 int size;
3743
8de9b311
CW		 3744 size = dsparb & 0x1ff;
3745 if (plane)
3746 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3747 size >>= 1; /* Convert to cachelines */
dff33cfc 3748
28c97730 3749 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3750 plane ? "B" : "A", size);
dff33cfc
JB		 3751
3752 return size;
3753}
7662c8bd 3754
e70236a8
JB		 3755static int i845_get_fifo_size(struct drm_device *dev, int plane)
3756{
3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758 uint32_t dsparb = I915_READ(DSPARB);
3759 int size;
3760
3761 size = dsparb & 0x7f;
3762 size >>= 2; /* Convert to cachelines */
3763
28c97730 3764 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3765 plane ? "B" : "A",
3766 size);
e70236a8
JB		 3767
3768 return size;
3769}
3770
3771static int i830_get_fifo_size(struct drm_device *dev, int plane)
3772{
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774 uint32_t dsparb = I915_READ(DSPARB);
3775 int size;
3776
3777 size = dsparb & 0x7f;
3778 size >>= 1; /* Convert to cachelines */
3779
28c97730 3780 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3781 plane ? "B" : "A", size);
e70236a8
JB		 3782
3783 return size;
3784}
3785
d210246a
CW		 3786static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3787{
3788 struct drm_crtc *crtc, *enabled = NULL;
3789
3790 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3791 if (crtc->enabled && crtc->fb) {
3792 if (enabled)
3793 return NULL;
3794 enabled = crtc;
3795 }
3796 }
3797
3798 return enabled;
3799}
3800
3801static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3802{
3803 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3804 struct drm_crtc *crtc;
403c89ff 3805 const struct cxsr_latency *latency;
d4294342
ZY		 3806 u32 reg;
3807 unsigned long wm;
d4294342 3808
403c89ff 3809 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3810 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3811 if (!latency) {
3812 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3813 pineview_disable_cxsr(dev);
3814 return;
3815 }
3816
d210246a
CW		 3817 crtc = single_enabled_crtc(dev);
3818 if (crtc) {
3819 int clock = crtc->mode.clock;
3820 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3821
3822 /* Display SR */
d210246a
CW		 3823 wm = intel_calculate_wm(clock, &pineview_display_wm,
3824 pineview_display_wm.fifo_size,
d4294342
ZY		 3825 pixel_size, latency->display_sr);
3826 reg = I915_READ(DSPFW1);
3827 reg &= ~DSPFW_SR_MASK;
3828 reg |= wm << DSPFW_SR_SHIFT;
3829 I915_WRITE(DSPFW1, reg);
3830 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3831
3832 /* cursor SR */
d210246a
CW		 3833 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3834 pineview_display_wm.fifo_size,
d4294342
ZY		 3835 pixel_size, latency->cursor_sr);
3836 reg = I915_READ(DSPFW3);
3837 reg &= ~DSPFW_CURSOR_SR_MASK;
3838 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3839 I915_WRITE(DSPFW3, reg);
3840
3841 /* Display HPLL off SR */
d210246a
CW		 3842 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3843 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3844 pixel_size, latency->display_hpll_disable);
3845 reg = I915_READ(DSPFW3);
3846 reg &= ~DSPFW_HPLL_SR_MASK;
3847 reg |= wm & DSPFW_HPLL_SR_MASK;
3848 I915_WRITE(DSPFW3, reg);
3849
3850 /* cursor HPLL off SR */
d210246a
CW		 3851 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3852 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3853 pixel_size, latency->cursor_hpll_disable);
3854 reg = I915_READ(DSPFW3);
3855 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3856 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3857 I915_WRITE(DSPFW3, reg);
3858 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3859
3860 /* activate cxsr */
3e33d94d
CW		 3861 I915_WRITE(DSPFW3,
3862 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3863 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3864 } else {
3865 pineview_disable_cxsr(dev);
3866 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3867 }
3868}
3869
417ae147
CW		 3870static bool g4x_compute_wm0(struct drm_device *dev,
3871 int plane,
3872 const struct intel_watermark_params *display,
3873 int display_latency_ns,
3874 const struct intel_watermark_params *cursor,
3875 int cursor_latency_ns,
3876 int *plane_wm,
3877 int *cursor_wm)
3878{
3879 struct drm_crtc *crtc;
3880 int htotal, hdisplay, clock, pixel_size;
3881 int line_time_us, line_count;
3882 int entries, tlb_miss;
3883
3884 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3885 if (crtc->fb == NULL || !crtc->enabled) {
3886 *cursor_wm = cursor->guard_size;
3887 *plane_wm = display->guard_size;
417ae147 3888 return false;
5c72d064 3889 }
417ae147
CW		 3890
3891 htotal = crtc->mode.htotal;
3892 hdisplay = crtc->mode.hdisplay;
3893 clock = crtc->mode.clock;
3894 pixel_size = crtc->fb->bits_per_pixel / 8;
3895
3896 /* Use the small buffer method to calculate plane watermark */
3897 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3898 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3899 if (tlb_miss > 0)
3900 entries += tlb_miss;
3901 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3902 *plane_wm = entries + display->guard_size;
3903 if (*plane_wm > (int)display->max_wm)
3904 *plane_wm = display->max_wm;
3905
3906 /* Use the large buffer method to calculate cursor watermark */
3907 line_time_us = ((htotal * 1000) / clock);
3908 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3909 entries = line_count * 64 * pixel_size;
3910 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3911 if (tlb_miss > 0)
3912 entries += tlb_miss;
3913 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3914 *cursor_wm = entries + cursor->guard_size;
3915 if (*cursor_wm > (int)cursor->max_wm)
3916 *cursor_wm = (int)cursor->max_wm;
3917
3918 return true;
3919}
3920
3921/*
3922 * Check the wm result.
3923 *
3924 * If any calculated watermark values is larger than the maximum value that
3925 * can be programmed into the associated watermark register, that watermark
3926 * must be disabled.
3927 */
3928static bool g4x_check_srwm(struct drm_device *dev,
3929 int display_wm, int cursor_wm,
3930 const struct intel_watermark_params *display,
3931 const struct intel_watermark_params *cursor)
652c393a 3932{
417ae147
CW		 3933 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3934 display_wm, cursor_wm);
652c393a 3935
417ae147 3936 if (display_wm > display->max_wm) {
bbb0aef5 3937 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3938 display_wm, display->max_wm);
3939 return false;
3940 }
0e442c60 3941
417ae147 3942 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3943 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3944 cursor_wm, cursor->max_wm);
3945 return false;
3946 }
0e442c60 3947
417ae147
CW		 3948 if (!(display_wm || cursor_wm)) {
3949 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3950 return false;
3951 }
0e442c60 3952
417ae147
CW		 3953 return true;
3954}
0e442c60 3955
417ae147 3956static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3957 int plane,
3958 int latency_ns,
417ae147
CW		 3959 const struct intel_watermark_params *display,
3960 const struct intel_watermark_params *cursor,
3961 int *display_wm, int *cursor_wm)
3962{
d210246a
CW		 3963 struct drm_crtc *crtc;
3964 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3965 unsigned long line_time_us;
3966 int line_count, line_size;
3967 int small, large;
3968 int entries;
0e442c60 3969
417ae147
CW		 3970 if (!latency_ns) {
3971 *display_wm = *cursor_wm = 0;
3972 return false;
3973 }
0e442c60 3974
d210246a
CW		 3975 crtc = intel_get_crtc_for_plane(dev, plane);
3976 hdisplay = crtc->mode.hdisplay;
3977 htotal = crtc->mode.htotal;
3978 clock = crtc->mode.clock;
3979 pixel_size = crtc->fb->bits_per_pixel / 8;
3980
417ae147
CW		 3981 line_time_us = (htotal * 1000) / clock;
3982 line_count = (latency_ns / line_time_us + 1000) / 1000;
3983 line_size = hdisplay * pixel_size;
0e442c60 3984
417ae147
CW		 3985 /* Use the minimum of the small and large buffer method for primary */
3986 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3987 large = line_count * line_size;
0e442c60 3988
417ae147
CW		 3989 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3990 *display_wm = entries + display->guard_size;
4fe5e611 3991
417ae147
CW		 3992 /* calculate the self-refresh watermark for display cursor */
3993 entries = line_count * pixel_size * 64;
3994 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3995 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3996
417ae147
CW		 3997 return g4x_check_srwm(dev,
3998 *display_wm, *cursor_wm,
3999 display, cursor);
4000}
4fe5e611 4001
7ccb4a53 4002#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4003
4004static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4005{
4006 static const int sr_latency_ns = 12000;
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4009 int plane_sr, cursor_sr;
4010 unsigned int enabled = 0;
417ae147
CW		 4011
4012 if (g4x_compute_wm0(dev, 0,
4013 &g4x_wm_info, latency_ns,
4014 &g4x_cursor_wm_info, latency_ns,
4015 &planea_wm, &cursora_wm))
d210246a 4016 enabled |= 1;
417ae147
CW		 4017
4018 if (g4x_compute_wm0(dev, 1,
4019 &g4x_wm_info, latency_ns,
4020 &g4x_cursor_wm_info, latency_ns,
4021 &planeb_wm, &cursorb_wm))
d210246a 4022 enabled |= 2;
417ae147
CW		 4023
4024 plane_sr = cursor_sr = 0;
d210246a
CW		 4025 if (single_plane_enabled(enabled) &&
4026 g4x_compute_srwm(dev, ffs(enabled) - 1,
4027 sr_latency_ns,
417ae147
CW		 4028 &g4x_wm_info,
4029 &g4x_cursor_wm_info,
4030 &plane_sr, &cursor_sr))
0e442c60 4031 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4032 else
4033 I915_WRITE(FW_BLC_SELF,
4034 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4035
308977ac
CW		 4036 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4037 planea_wm, cursora_wm,
4038 planeb_wm, cursorb_wm,
4039 plane_sr, cursor_sr);
0e442c60 4040
417ae147
CW		 4041 I915_WRITE(DSPFW1,
4042 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4043 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4044 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4045 planea_wm);
4046 I915_WRITE(DSPFW2,
4047 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4048 (cursora_wm << DSPFW_CURSORA_SHIFT));
4049 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4050 I915_WRITE(DSPFW3,
4051 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4052 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4053}
4054
d210246a 4055static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4056{
4057 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4058 struct drm_crtc *crtc;
4059 int srwm = 1;
4fe5e611 4060 int cursor_sr = 16;
1dc7546d
JB		 4061
4062 /* Calc sr entries for one plane configs */
d210246a
CW		 4063 crtc = single_enabled_crtc(dev);
4064 if (crtc) {
1dc7546d 4065 /* self-refresh has much higher latency */
69e302a9 4066 static const int sr_latency_ns = 12000;
d210246a
CW		 4067 int clock = crtc->mode.clock;
4068 int htotal = crtc->mode.htotal;
4069 int hdisplay = crtc->mode.hdisplay;
4070 int pixel_size = crtc->fb->bits_per_pixel / 8;
4071 unsigned long line_time_us;
4072 int entries;
1dc7546d 4073
d210246a 4074 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4075
4076 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4077 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4078 pixel_size * hdisplay;
4079 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4080 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4081 if (srwm < 0)
4082 srwm = 1;
1b07e04e 4083 srwm &= 0x1ff;
308977ac
CW		 4084 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4085 entries, srwm);
4fe5e611 4086
d210246a 4087 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4088 pixel_size * 64;
d210246a 4089 entries = DIV_ROUND_UP(entries,
8de9b311 4090 i965_cursor_wm_info.cacheline_size);
4fe5e611 4091 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4092 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4093
4094 if (cursor_sr > i965_cursor_wm_info.max_wm)
4095 cursor_sr = i965_cursor_wm_info.max_wm;
4096
4097 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4098 "cursor %d\n", srwm, cursor_sr);
4099
a6c45cf0 4100 if (IS_CRESTLINE(dev))
adcdbc66 4101 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4102 } else {
4103 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4104 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4105 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4106 & ~FW_BLC_SELF_EN);
1dc7546d 4107 }
7662c8bd 4108
1dc7546d
JB		 4109 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4110 srwm);
7662c8bd
SL		 4111
4112 /* 965 has limitations... */
417ae147
CW		 4113 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4114 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4115 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4116 /* update cursor SR watermark */
4117 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4118}
4119
d210246a 4120static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4121{
4122 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4123 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4124 uint32_t fwater_lo;
4125 uint32_t fwater_hi;
d210246a
CW		 4126 int cwm, srwm = 1;
4127 int fifo_size;
dff33cfc 4128 int planea_wm, planeb_wm;
d210246a 4129 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4130
72557b4f 4131 if (IS_I945GM(dev))
d210246a 4132 wm_info = &i945_wm_info;
a6c45cf0 4133 else if (!IS_GEN2(dev))
d210246a 4134 wm_info = &i915_wm_info;
7662c8bd 4135 else
d210246a
CW		 4136 wm_info = &i855_wm_info;
4137
4138 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4139 crtc = intel_get_crtc_for_plane(dev, 0);
4140 if (crtc->enabled && crtc->fb) {
4141 planea_wm = intel_calculate_wm(crtc->mode.clock,
4142 wm_info, fifo_size,
4143 crtc->fb->bits_per_pixel / 8,
4144 latency_ns);
4145 enabled = crtc;
4146 } else
4147 planea_wm = fifo_size - wm_info->guard_size;
4148
4149 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4150 crtc = intel_get_crtc_for_plane(dev, 1);
4151 if (crtc->enabled && crtc->fb) {
4152 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4153 wm_info, fifo_size,
4154 crtc->fb->bits_per_pixel / 8,
4155 latency_ns);
4156 if (enabled == NULL)
4157 enabled = crtc;
4158 else
4159 enabled = NULL;
4160 } else
4161 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4162
28c97730 4163 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4164
4165 /*
4166 * Overlay gets an aggressive default since video jitter is bad.
4167 */
4168 cwm = 2;
4169
18b2190c
AL		 4170 /* Play safe and disable self-refresh before adjusting watermarks. */
4171 if (IS_I945G(dev) || IS_I945GM(dev))
4172 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4173 else if (IS_I915GM(dev))
4174 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4175
dff33cfc 4176 /* Calc sr entries for one plane configs */
d210246a 4177 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4178 /* self-refresh has much higher latency */
69e302a9 4179 static const int sr_latency_ns = 6000;
d210246a
CW		 4180 int clock = enabled->mode.clock;
4181 int htotal = enabled->mode.htotal;
4182 int hdisplay = enabled->mode.hdisplay;
4183 int pixel_size = enabled->fb->bits_per_pixel / 8;
4184 unsigned long line_time_us;
4185 int entries;
dff33cfc 4186
d210246a 4187 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4188
4189 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4190 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4191 pixel_size * hdisplay;
4192 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4193 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4194 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4195 if (srwm < 0)
4196 srwm = 1;
ee980b80
LP		 4197
4198 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4199 I915_WRITE(FW_BLC_SELF,
4200 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4201 else if (IS_I915GM(dev))
ee980b80 4202 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4203 }
4204
28c97730 4205 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4206 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4207
dff33cfc
JB		 4208 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4209 fwater_hi = (cwm & 0x1f);
4210
4211 /* Set request length to 8 cachelines per fetch */
4212 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4213 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4214
4215 I915_WRITE(FW_BLC, fwater_lo);
4216 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4217
d210246a
CW		 4218 if (HAS_FW_BLC(dev)) {
4219 if (enabled) {
4220 if (IS_I945G(dev) || IS_I945GM(dev))
4221 I915_WRITE(FW_BLC_SELF,
4222 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4223 else if (IS_I915GM(dev))
4224 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4225 DRM_DEBUG_KMS("memory self refresh enabled\n");
4226 } else
4227 DRM_DEBUG_KMS("memory self refresh disabled\n");
4228 }
7662c8bd
SL		 4229}
4230
d210246a 4231static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4232{
4233 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4234 struct drm_crtc *crtc;
4235 uint32_t fwater_lo;
dff33cfc 4236 int planea_wm;
7662c8bd 4237
d210246a
CW		 4238 crtc = single_enabled_crtc(dev);
4239 if (crtc == NULL)
4240 return;
7662c8bd 4241
d210246a
CW		 4242 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4243 dev_priv->display.get_fifo_size(dev, 0),
4244 crtc->fb->bits_per_pixel / 8,
4245 latency_ns);
4246 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4247 fwater_lo |= (3<<8) | planea_wm;
4248
28c97730 4249 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4250
4251 I915_WRITE(FW_BLC, fwater_lo);
4252}
4253
7f8a8569 4254#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4255#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4256
1398261a
YL		 4257/*
4258 * Check the wm result.
4259 *
4260 * If any calculated watermark values is larger than the maximum value that
4261 * can be programmed into the associated watermark register, that watermark
4262 * must be disabled.
1398261a 4263 */
b79d4990
JB		 4264static bool ironlake_check_srwm(struct drm_device *dev, int level,
4265 int fbc_wm, int display_wm, int cursor_wm,
4266 const struct intel_watermark_params *display,
4267 const struct intel_watermark_params *cursor)
1398261a
YL		 4268{
4269 struct drm_i915_private *dev_priv = dev->dev_private;
4270
4271 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4272 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4273
4274 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4275 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4276 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4277
4278 /* fbc has it's own way to disable FBC WM */
4279 I915_WRITE(DISP_ARB_CTL,
4280 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4281 return false;
4282 }
4283
b79d4990 4284 if (display_wm > display->max_wm) {
1398261a 4285 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4286 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4287 return false;
4288 }
4289
b79d4990 4290 if (cursor_wm > cursor->max_wm) {
1398261a 4291 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4292 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4293 return false;
4294 }
4295
4296 if (!(fbc_wm || display_wm || cursor_wm)) {
4297 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4298 return false;
4299 }
4300
4301 return true;
4302}
4303
4304/*
4305 * Compute watermark values of WM[1-3],
4306 */
d210246a
CW		 4307static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4308 int latency_ns,
b79d4990
JB		 4309 const struct intel_watermark_params *display,
4310 const struct intel_watermark_params *cursor,
4311 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4312{
d210246a 4313 struct drm_crtc *crtc;
1398261a 4314 unsigned long line_time_us;
d210246a 4315 int hdisplay, htotal, pixel_size, clock;
b79d4990 4316 int line_count, line_size;
1398261a
YL		 4317 int small, large;
4318 int entries;
1398261a
YL		 4319
4320 if (!latency_ns) {
4321 *fbc_wm = *display_wm = *cursor_wm = 0;
4322 return false;
4323 }
4324
d210246a
CW		 4325 crtc = intel_get_crtc_for_plane(dev, plane);
4326 hdisplay = crtc->mode.hdisplay;
4327 htotal = crtc->mode.htotal;
4328 clock = crtc->mode.clock;
4329 pixel_size = crtc->fb->bits_per_pixel / 8;
4330
1398261a
YL		 4331 line_time_us = (htotal * 1000) / clock;
4332 line_count = (latency_ns / line_time_us + 1000) / 1000;
4333 line_size = hdisplay * pixel_size;
4334
4335 /* Use the minimum of the small and large buffer method for primary */
4336 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4337 large = line_count * line_size;
4338
b79d4990
JB		 4339 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4340 *display_wm = entries + display->guard_size;
1398261a
YL		 4341
4342 /*
b79d4990 4343 * Spec says:
1398261a
YL		 4344 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4345 */
4346 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4347
4348 /* calculate the self-refresh watermark for display cursor */
4349 entries = line_count * pixel_size * 64;
b79d4990
JB		 4350 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4351 *cursor_wm = entries + cursor->guard_size;
1398261a 4352
b79d4990
JB		 4353 return ironlake_check_srwm(dev, level,
4354 *fbc_wm, *display_wm, *cursor_wm,
4355 display, cursor);
4356}
4357
d210246a 4358static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4359{
4360 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4361 int fbc_wm, plane_wm, cursor_wm;
4362 unsigned int enabled;
b79d4990
JB		 4363
4364 enabled = 0;
9f405100
CW		 4365 if (g4x_compute_wm0(dev, 0,
4366 &ironlake_display_wm_info,
4367 ILK_LP0_PLANE_LATENCY,
4368 &ironlake_cursor_wm_info,
4369 ILK_LP0_CURSOR_LATENCY,
4370 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4371 I915_WRITE(WM0_PIPEA_ILK,
4372 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4373 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4374 " plane %d, " "cursor: %d\n",
4375 plane_wm, cursor_wm);
d210246a 4376 enabled |= 1;
b79d4990
JB		 4377 }
4378
9f405100
CW		 4379 if (g4x_compute_wm0(dev, 1,
4380 &ironlake_display_wm_info,
4381 ILK_LP0_PLANE_LATENCY,
4382 &ironlake_cursor_wm_info,
4383 ILK_LP0_CURSOR_LATENCY,
4384 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4385 I915_WRITE(WM0_PIPEB_ILK,
4386 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4387 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4388 " plane %d, cursor: %d\n",
4389 plane_wm, cursor_wm);
d210246a 4390 enabled |= 2;
b79d4990
JB		 4391 }
4392
4393 /*
4394 * Calculate and update the self-refresh watermark only when one
4395 * display plane is used.
4396 */
4397 I915_WRITE(WM3_LP_ILK, 0);
4398 I915_WRITE(WM2_LP_ILK, 0);
4399 I915_WRITE(WM1_LP_ILK, 0);
4400
d210246a 4401 if (!single_plane_enabled(enabled))
b79d4990 4402 return;
d210246a 4403 enabled = ffs(enabled) - 1;
b79d4990
JB		 4404
4405 /* WM1 */
d210246a
CW		 4406 if (!ironlake_compute_srwm(dev, 1, enabled,
4407 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4408 &ironlake_display_srwm_info,
4409 &ironlake_cursor_srwm_info,
4410 &fbc_wm, &plane_wm, &cursor_wm))
4411 return;
4412
4413 I915_WRITE(WM1_LP_ILK,
4414 WM1_LP_SR_EN |
4415 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4416 (fbc_wm << WM1_LP_FBC_SHIFT) |
4417 (plane_wm << WM1_LP_SR_SHIFT) |
4418 cursor_wm);
4419
4420 /* WM2 */
d210246a
CW		 4421 if (!ironlake_compute_srwm(dev, 2, enabled,
4422 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4423 &ironlake_display_srwm_info,
4424 &ironlake_cursor_srwm_info,
4425 &fbc_wm, &plane_wm, &cursor_wm))
4426 return;
4427
4428 I915_WRITE(WM2_LP_ILK,
4429 WM2_LP_EN |
4430 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4431 (fbc_wm << WM1_LP_FBC_SHIFT) |
4432 (plane_wm << WM1_LP_SR_SHIFT) |
4433 cursor_wm);
4434
4435 /*
4436 * WM3 is unsupported on ILK, probably because we don't have latency
4437 * data for that power state
4438 */
1398261a
YL		 4439}
4440
d210246a 4441static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4442{
4443 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4444 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4445 int fbc_wm, plane_wm, cursor_wm;
4446 unsigned int enabled;
1398261a
YL		 4447
4448 enabled = 0;
9f405100
CW		 4449 if (g4x_compute_wm0(dev, 0,
4450 &sandybridge_display_wm_info, latency,
4451 &sandybridge_cursor_wm_info, latency,
4452 &plane_wm, &cursor_wm)) {
1398261a
YL		 4453 I915_WRITE(WM0_PIPEA_ILK,
4454 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4455 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4456 " plane %d, " "cursor: %d\n",
4457 plane_wm, cursor_wm);
d210246a 4458 enabled |= 1;
1398261a
YL		 4459 }
4460
9f405100
CW		 4461 if (g4x_compute_wm0(dev, 1,
4462 &sandybridge_display_wm_info, latency,
4463 &sandybridge_cursor_wm_info, latency,
4464 &plane_wm, &cursor_wm)) {
1398261a
YL		 4465 I915_WRITE(WM0_PIPEB_ILK,
4466 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4467 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4468 " plane %d, cursor: %d\n",
4469 plane_wm, cursor_wm);
d210246a 4470 enabled |= 2;
1398261a
YL		 4471 }
4472
4473 /*
4474 * Calculate and update the self-refresh watermark only when one
4475 * display plane is used.
4476 *
4477 * SNB support 3 levels of watermark.
4478 *
4479 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4480 * and disabled in the descending order
4481 *
4482 */
4483 I915_WRITE(WM3_LP_ILK, 0);
4484 I915_WRITE(WM2_LP_ILK, 0);
4485 I915_WRITE(WM1_LP_ILK, 0);
4486
d210246a 4487 if (!single_plane_enabled(enabled))
1398261a 4488 return;
d210246a 4489 enabled = ffs(enabled) - 1;
1398261a
YL		 4490
4491 /* WM1 */
d210246a
CW		 4492 if (!ironlake_compute_srwm(dev, 1, enabled,
4493 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4494 &sandybridge_display_srwm_info,
4495 &sandybridge_cursor_srwm_info,
4496 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4497 return;
4498
4499 I915_WRITE(WM1_LP_ILK,
4500 WM1_LP_SR_EN |
4501 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4502 (fbc_wm << WM1_LP_FBC_SHIFT) |
4503 (plane_wm << WM1_LP_SR_SHIFT) |
4504 cursor_wm);
4505
4506 /* WM2 */
d210246a
CW		 4507 if (!ironlake_compute_srwm(dev, 2, enabled,
4508 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4509 &sandybridge_display_srwm_info,
4510 &sandybridge_cursor_srwm_info,
4511 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4512 return;
4513
4514 I915_WRITE(WM2_LP_ILK,
4515 WM2_LP_EN |
4516 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4517 (fbc_wm << WM1_LP_FBC_SHIFT) |
4518 (plane_wm << WM1_LP_SR_SHIFT) |
4519 cursor_wm);
4520
4521 /* WM3 */
d210246a
CW		 4522 if (!ironlake_compute_srwm(dev, 3, enabled,
4523 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4524 &sandybridge_display_srwm_info,
4525 &sandybridge_cursor_srwm_info,
4526 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4527 return;
4528
4529 I915_WRITE(WM3_LP_ILK,
4530 WM3_LP_EN |
4531 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4532 (fbc_wm << WM1_LP_FBC_SHIFT) |
4533 (plane_wm << WM1_LP_SR_SHIFT) |
4534 cursor_wm);
4535}
4536
7662c8bd
SL		 4537/**
4538 * intel_update_watermarks - update FIFO watermark values based on current modes
4539 *
4540 * Calculate watermark values for the various WM regs based on current mode
4541 * and plane configuration.
4542 *
4543 * There are several cases to deal with here:
4544 * - normal (i.e. non-self-refresh)
4545 * - self-refresh (SR) mode
4546 * - lines are large relative to FIFO size (buffer can hold up to 2)
4547 * - lines are small relative to FIFO size (buffer can hold more than 2
4548 * lines), so need to account for TLB latency
4549 *
4550 * The normal calculation is:
4551 * watermark = dotclock * bytes per pixel * latency
4552 * where latency is platform & configuration dependent (we assume pessimal
4553 * values here).
4554 *
4555 * The SR calculation is:
4556 * watermark = (trunc(latency/line time)+1) * surface width *
4557 * bytes per pixel
4558 * where
4559 * line time = htotal / dotclock
fa143215 4560 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4561 * and latency is assumed to be high, as above.
4562 *
4563 * The final value programmed to the register should always be rounded up,
4564 * and include an extra 2 entries to account for clock crossings.
4565 *
4566 * We don't use the sprite, so we can ignore that. And on Crestline we have
4567 * to set the non-SR watermarks to 8.
5eddb70b 4568 */
7662c8bd
SL		 4569static void intel_update_watermarks(struct drm_device *dev)
4570{
e70236a8 4571 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4572
d210246a
CW		 4573 if (dev_priv->display.update_wm)
4574 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4575}
4576
a7615030
CW		 4577static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4578{
435793df
KP		 4579 return dev_priv->lvds_use_ssc && i915_panel_use_ssc
4580 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4581}
4582
5a354204
JB		 4583/**
4584 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4585 * @crtc: CRTC structure
4586 *
4587 * A pipe may be connected to one or more outputs. Based on the depth of the
4588 * attached framebuffer, choose a good color depth to use on the pipe.
4589 *
4590 * If possible, match the pipe depth to the fb depth. In some cases, this
4591 * isn't ideal, because the connected output supports a lesser or restricted
4592 * set of depths. Resolve that here:
4593 * LVDS typically supports only 6bpc, so clamp down in that case
4594 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4595 * Displays may support a restricted set as well, check EDID and clamp as
4596 * appropriate.
4597 *
4598 * RETURNS:
4599 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4600 * true if they don't match).
4601 */
4602static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4603 unsigned int *pipe_bpp)
4604{
4605 struct drm_device *dev = crtc->dev;
4606 struct drm_i915_private *dev_priv = dev->dev_private;
4607 struct drm_encoder *encoder;
4608 struct drm_connector *connector;
4609 unsigned int display_bpc = UINT_MAX, bpc;
4610
4611 /* Walk the encoders & connectors on this crtc, get min bpc */
4612 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4613 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4614
4615 if (encoder->crtc != crtc)
4616 continue;
4617
4618 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4619 unsigned int lvds_bpc;
4620
4621 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4622 LVDS_A3_POWER_UP)
4623 lvds_bpc = 8;
4624 else
4625 lvds_bpc = 6;
4626
4627 if (lvds_bpc < display_bpc) {
4628 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4629 display_bpc = lvds_bpc;
4630 }
4631 continue;
4632 }
4633
4634 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4635 /* Use VBT settings if we have an eDP panel */
4636 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4637
4638 if (edp_bpc < display_bpc) {
4639 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4640 display_bpc = edp_bpc;
4641 }
4642 continue;
4643 }
4644
4645 /* Not one of the known troublemakers, check the EDID */
4646 list_for_each_entry(connector, &dev->mode_config.connector_list,
4647 head) {
4648 if (connector->encoder != encoder)
4649 continue;
4650
62ac41a6
JB		 4651 /* Don't use an invalid EDID bpc value */
4652 if (connector->display_info.bpc &&
4653 connector->display_info.bpc < display_bpc) {
5a354204
JB		 4654 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4655 display_bpc = connector->display_info.bpc;
4656 }
4657 }
4658
4659 /*
4660 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4661 * through, clamp it down. (Note: >12bpc will be caught below.)
4662 */
4663 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4664 if (display_bpc > 8 && display_bpc < 12) {
4665 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4666 display_bpc = 12;
4667 } else {
4668 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4669 display_bpc = 8;
4670 }
4671 }
4672 }
4673
4674 /*
4675 * We could just drive the pipe at the highest bpc all the time and
4676 * enable dithering as needed, but that costs bandwidth. So choose
4677 * the minimum value that expresses the full color range of the fb but
4678 * also stays within the max display bpc discovered above.
4679 */
4680
4681 switch (crtc->fb->depth) {
4682 case 8:
4683 bpc = 8; /* since we go through a colormap */
4684 break;
4685 case 15:
4686 case 16:
4687 bpc = 6; /* min is 18bpp */
4688 break;
4689 case 24:
4690 bpc = min((unsigned int)8, display_bpc);
4691 break;
4692 case 30:
4693 bpc = min((unsigned int)10, display_bpc);
4694 break;
4695 case 48:
4696 bpc = min((unsigned int)12, display_bpc);
4697 break;
4698 default:
4699 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4700 bpc = min((unsigned int)8, display_bpc);
4701 break;
4702 }
4703
4704 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4705 bpc, display_bpc);
4706
4707 *pipe_bpp = bpc * 3;
4708
4709 return display_bpc != bpc;
4710}
4711
f564048e
EA		 4712static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4713 struct drm_display_mode *mode,
4714 struct drm_display_mode *adjusted_mode,
4715 int x, int y,
4716 struct drm_framebuffer *old_fb)
79e53945
JB		 4717{
4718 struct drm_device *dev = crtc->dev;
4719 struct drm_i915_private *dev_priv = dev->dev_private;
4720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4721 int pipe = intel_crtc->pipe;
80824003 4722 int plane = intel_crtc->plane;
c751ce4f 4723 int refclk, num_connectors = 0;
652c393a 4724 intel_clock_t clock, reduced_clock;
5eddb70b 4725 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4726 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4727 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4728 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4729 struct intel_encoder *encoder;
d4906093 4730 const intel_limit_t *limit;
5c3b82e2 4731 int ret;
fae14981 4732 u32 temp;
aa9b500d 4733 u32 lvds_sync = 0;
79e53945 4734
5eddb70b
CW		 4735 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4736 if (encoder->base.crtc != crtc)
79e53945
JB		 4737 continue;
4738
5eddb70b 4739 switch (encoder->type) {
79e53945
JB		 4740 case INTEL_OUTPUT_LVDS:
4741 is_lvds = true;
4742 break;
4743 case INTEL_OUTPUT_SDVO:
7d57382e 4744 case INTEL_OUTPUT_HDMI:
79e53945 4745 is_sdvo = true;
5eddb70b 4746 if (encoder->needs_tv_clock)
e2f0ba97 4747 is_tv = true;
79e53945
JB		 4748 break;
4749 case INTEL_OUTPUT_DVO:
4750 is_dvo = true;
4751 break;
4752 case INTEL_OUTPUT_TVOUT:
4753 is_tv = true;
4754 break;
4755 case INTEL_OUTPUT_ANALOG:
4756 is_crt = true;
4757 break;
a4fc5ed6
KP		 4758 case INTEL_OUTPUT_DISPLAYPORT:
4759 is_dp = true;
4760 break;
79e53945 4761 }
43565a06 4762
c751ce4f 4763 num_connectors++;
79e53945
JB		 4764 }
4765
a7615030 4766 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4767 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4768 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4769 refclk / 1000);
a6c45cf0 4770 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4771 refclk = 96000;
4772 } else {
4773 refclk = 48000;
4774 }
4775
d4906093
ML		 4776 /*
4777 * Returns a set of divisors for the desired target clock with the given
4778 * refclk, or FALSE. The returned values represent the clock equation:
4779 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4780 */
1b894b59 4781 limit = intel_limit(crtc, refclk);
d4906093 4782 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4783 if (!ok) {
4784 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4785 return -EINVAL;
79e53945
JB		 4786 }
4787
cda4b7d3 4788 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4789 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4790
ddc9003c
ZY		 4791 if (is_lvds && dev_priv->lvds_downclock_avail) {
4792 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4793 dev_priv->lvds_downclock,
4794 refclk,
4795 &reduced_clock);
18f9ed12
ZY		 4796 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4797 /*
4798 * If the different P is found, it means that we can't
4799 * switch the display clock by using the FP0/FP1.
4800 * In such case we will disable the LVDS downclock
4801 * feature.
4802 */
4803 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4804 "LVDS clock/downclock\n");
18f9ed12
ZY		 4805 has_reduced_clock = 0;
4806 }
652c393a 4807 }
7026d4ac
ZW		 4808 /* SDVO TV has fixed PLL values depend on its clock range,
4809 this mirrors vbios setting. */
4810 if (is_sdvo && is_tv) {
4811 if (adjusted_mode->clock >= 100000
5eddb70b 4812 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4813 clock.p1 = 2;
4814 clock.p2 = 10;
4815 clock.n = 3;
4816 clock.m1 = 16;
4817 clock.m2 = 8;
4818 } else if (adjusted_mode->clock >= 140500
5eddb70b 4819 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4820 clock.p1 = 1;
4821 clock.p2 = 10;
4822 clock.n = 6;
4823 clock.m1 = 12;
4824 clock.m2 = 8;
4825 }
4826 }
4827
f2b115e6 4828 if (IS_PINEVIEW(dev)) {
2177832f 4829 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4830 if (has_reduced_clock)
4831 fp2 = (1 << reduced_clock.n) << 16 |
4832 reduced_clock.m1 << 8 | reduced_clock.m2;
4833 } else {
2177832f 4834 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4835 if (has_reduced_clock)
4836 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4837 reduced_clock.m2;
4838 }
79e53945 4839
929c77fb 4840 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4841
a6c45cf0 4842 if (!IS_GEN2(dev)) {
79e53945
JB		 4843 if (is_lvds)
4844 dpll |= DPLLB_MODE_LVDS;
4845 else
4846 dpll |= DPLLB_MODE_DAC_SERIAL;
4847 if (is_sdvo) {
6c9547ff
CW		 4848 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4849 if (pixel_multiplier > 1) {
4850 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4851 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4852 }
79e53945 4853 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4854 }
929c77fb 4855 if (is_dp)
a4fc5ed6 4856 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4857
4858 /* compute bitmask from p1 value */
f2b115e6
AJ		 4859 if (IS_PINEVIEW(dev))
4860 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4861 else {
2177832f 4862 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4863 if (IS_G4X(dev) && has_reduced_clock)
4864 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4865 }
79e53945
JB		 4866 switch (clock.p2) {
4867 case 5:
4868 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4869 break;
4870 case 7:
4871 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4872 break;
4873 case 10:
4874 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4875 break;
4876 case 14:
4877 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4878 break;
4879 }
929c77fb 4880 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4881 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4882 } else {
4883 if (is_lvds) {
4884 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4885 } else {
4886 if (clock.p1 == 2)
4887 dpll |= PLL_P1_DIVIDE_BY_TWO;
4888 else
4889 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4890 if (clock.p2 == 4)
4891 dpll |= PLL_P2_DIVIDE_BY_4;
4892 }
4893 }
4894
43565a06
KH		 4895 if (is_sdvo && is_tv)
4896 dpll |= PLL_REF_INPUT_TVCLKINBC;
4897 else if (is_tv)
79e53945 4898 /* XXX: just matching BIOS for now */
43565a06 4899 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4900 dpll |= 3;
a7615030 4901 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4902 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4903 else
4904 dpll |= PLL_REF_INPUT_DREFCLK;
4905
4906 /* setup pipeconf */
5eddb70b 4907 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4908
4909 /* Set up the display plane register */
4910 dspcntr = DISPPLANE_GAMMA_ENABLE;
4911
f2b115e6 4912 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4913 enable color space conversion */
929c77fb
EA		 4914 if (pipe == 0)
4915 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4916 else
4917 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4918
a6c45cf0 4919 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4920 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4921 * core speed.
4922 *
4923 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4924 * pipe == 0 check?
4925 */
e70236a8
JB		 4926 if (mode->clock >
4927 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4928 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4929 else
5eddb70b 4930 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4931 }
4932
929c77fb 4933 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4934
28c97730 4935 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4936 drm_mode_debug_printmodeline(mode);
4937
fae14981
EA		 4938 I915_WRITE(FP0(pipe), fp);
4939 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4940
fae14981 4941 POSTING_READ(DPLL(pipe));
c713bb08 4942 udelay(150);
8db9d77b 4943
79e53945
JB		 4944 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4945 * This is an exception to the general rule that mode_set doesn't turn
4946 * things on.
4947 */
4948 if (is_lvds) {
fae14981 4949 temp = I915_READ(LVDS);
5eddb70b 4950 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4951 if (pipe == 1) {
929c77fb 4952 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4953 } else {
929c77fb 4954 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4955 }
a3e17eb8 4956 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4957 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4958 /* Set the B0-B3 data pairs corresponding to whether we're going to
4959 * set the DPLLs for dual-channel mode or not.
4960 */
4961 if (clock.p2 == 7)
5eddb70b 4962 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4963 else
5eddb70b 4964 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4965
4966 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4967 * appropriately here, but we need to look more thoroughly into how
4968 * panels behave in the two modes.
4969 */
929c77fb
EA		 4970 /* set the dithering flag on LVDS as needed */
4971 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 4972 if (dev_priv->lvds_dither)
5eddb70b 4973 temp |= LVDS_ENABLE_DITHER;
434ed097 4974 else
5eddb70b 4975 temp &= ~LVDS_ENABLE_DITHER;
898822ce 4976 }
aa9b500d
BF		 4977 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4978 lvds_sync |= LVDS_HSYNC_POLARITY;
4979 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4980 lvds_sync |= LVDS_VSYNC_POLARITY;
4981 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4982 != lvds_sync) {
4983 char flags[2] = "-+";
4984 DRM_INFO("Changing LVDS panel from "
4985 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4986 flags[!(temp & LVDS_HSYNC_POLARITY)],
4987 flags[!(temp & LVDS_VSYNC_POLARITY)],
4988 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4989 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4990 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4991 temp |= lvds_sync;
4992 }
fae14981 4993 I915_WRITE(LVDS, temp);
79e53945 4994 }
434ed097 4995
929c77fb 4996 if (is_dp) {
a4fc5ed6 4997 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 4998 }
4999
fae14981 5000 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5001
c713bb08 5002 /* Wait for the clocks to stabilize. */
fae14981 5003 POSTING_READ(DPLL(pipe));
c713bb08 5004 udelay(150);
32f9d658 5005
c713bb08
EA		 5006 if (INTEL_INFO(dev)->gen >= 4) {
5007 temp = 0;
5008 if (is_sdvo) {
5009 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5010 if (temp > 1)
5011 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5012 else
5013 temp = 0;
32f9d658 5014 }
c713bb08
EA		 5015 I915_WRITE(DPLL_MD(pipe), temp);
5016 } else {
5017 /* The pixel multiplier can only be updated once the
5018 * DPLL is enabled and the clocks are stable.
5019 *
5020 * So write it again.
5021 */
fae14981 5022 I915_WRITE(DPLL(pipe), dpll);
79e53945 5023 }
79e53945 5024
5eddb70b 5025 intel_crtc->lowfreq_avail = false;
652c393a 5026 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5027 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 5028 intel_crtc->lowfreq_avail = true;
5029 if (HAS_PIPE_CXSR(dev)) {
28c97730 5030 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5031 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5032 }
5033 } else {
fae14981 5034 I915_WRITE(FP1(pipe), fp);
652c393a 5035 if (HAS_PIPE_CXSR(dev)) {
28c97730 5036 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5037 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5038 }
5039 }
5040
734b4157
KH		 5041 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5042 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5043 /* the chip adds 2 halflines automatically */
5044 adjusted_mode->crtc_vdisplay -= 1;
5045 adjusted_mode->crtc_vtotal -= 1;
5046 adjusted_mode->crtc_vblank_start -= 1;
5047 adjusted_mode->crtc_vblank_end -= 1;
5048 adjusted_mode->crtc_vsync_end -= 1;
5049 adjusted_mode->crtc_vsync_start -= 1;
5050 } else
5051 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5052
5eddb70b
CW		 5053 I915_WRITE(HTOTAL(pipe),
5054 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5055 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5056 I915_WRITE(HBLANK(pipe),
5057 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5058 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5059 I915_WRITE(HSYNC(pipe),
5060 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5061 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5062
5063 I915_WRITE(VTOTAL(pipe),
5064 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5065 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5066 I915_WRITE(VBLANK(pipe),
5067 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5068 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5069 I915_WRITE(VSYNC(pipe),
5070 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5071 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5072
5073 /* pipesrc and dspsize control the size that is scaled from,
5074 * which should always be the user's requested size.
79e53945 5075 */
929c77fb
EA		 5076 I915_WRITE(DSPSIZE(plane),
5077 ((mode->vdisplay - 1) << 16) |
5078 (mode->hdisplay - 1));
5079 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5080 I915_WRITE(PIPESRC(pipe),
5081 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5082
f564048e
EA		 5083 I915_WRITE(PIPECONF(pipe), pipeconf);
5084 POSTING_READ(PIPECONF(pipe));
929c77fb 5085 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5086
5087 intel_wait_for_vblank(dev, pipe);
5088
f564048e
EA		 5089 I915_WRITE(DSPCNTR(plane), dspcntr);
5090 POSTING_READ(DSPCNTR(plane));
284d9529 5091 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5092
5093 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5094
5095 intel_update_watermarks(dev);
5096
f564048e
EA		 5097 return ret;
5098}
5099
5100static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5101 struct drm_display_mode *mode,
5102 struct drm_display_mode *adjusted_mode,
5103 int x, int y,
5104 struct drm_framebuffer *old_fb)
79e53945
JB		 5105{
5106 struct drm_device *dev = crtc->dev;
5107 struct drm_i915_private *dev_priv = dev->dev_private;
5108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5109 int pipe = intel_crtc->pipe;
80824003 5110 int plane = intel_crtc->plane;
c751ce4f 5111 int refclk, num_connectors = 0;
652c393a 5112 intel_clock_t clock, reduced_clock;
5eddb70b 5113 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5114 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5115 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5116 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5117 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5118 struct intel_encoder *encoder;
d4906093 5119 const intel_limit_t *limit;
5c3b82e2 5120 int ret;
2c07245f 5121 struct fdi_m_n m_n = {0};
fae14981 5122 u32 temp;
aa9b500d 5123 u32 lvds_sync = 0;
5a354204
JB		 5124 int target_clock, pixel_multiplier, lane, link_bw, factor;
5125 unsigned int pipe_bpp;
5126 bool dither;
79e53945 5127
5eddb70b
CW		 5128 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5129 if (encoder->base.crtc != crtc)
79e53945
JB		 5130 continue;
5131
5eddb70b 5132 switch (encoder->type) {
79e53945
JB		 5133 case INTEL_OUTPUT_LVDS:
5134 is_lvds = true;
5135 break;
5136 case INTEL_OUTPUT_SDVO:
7d57382e 5137 case INTEL_OUTPUT_HDMI:
79e53945 5138 is_sdvo = true;
5eddb70b 5139 if (encoder->needs_tv_clock)
e2f0ba97 5140 is_tv = true;
79e53945 5141 break;
79e53945
JB		 5142 case INTEL_OUTPUT_TVOUT:
5143 is_tv = true;
5144 break;
5145 case INTEL_OUTPUT_ANALOG:
5146 is_crt = true;
5147 break;
a4fc5ed6
KP		 5148 case INTEL_OUTPUT_DISPLAYPORT:
5149 is_dp = true;
5150 break;
32f9d658 5151 case INTEL_OUTPUT_EDP:
5eddb70b 5152 has_edp_encoder = encoder;
32f9d658 5153 break;
79e53945 5154 }
43565a06 5155
c751ce4f 5156 num_connectors++;
79e53945
JB		 5157 }
5158
a7615030 5159 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 5160 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 5161 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 5162 refclk / 1000);
a07d6787 5163 } else {
79e53945 5164 refclk = 96000;
8febb297
EA		 5165 if (!has_edp_encoder ||
5166 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 5167 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 5168 }
5169
d4906093
ML		 5170 /*
5171 * Returns a set of divisors for the desired target clock with the given
5172 * refclk, or FALSE. The returned values represent the clock equation:
5173 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5174 */
1b894b59 5175 limit = intel_limit(crtc, refclk);
d4906093 5176 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 5177 if (!ok) {
5178 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5179 return -EINVAL;
79e53945
JB		 5180 }
5181
cda4b7d3 5182 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5183 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5184
ddc9003c
ZY		 5185 if (is_lvds && dev_priv->lvds_downclock_avail) {
5186 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5187 dev_priv->lvds_downclock,
5188 refclk,
5189 &reduced_clock);
18f9ed12
ZY		 5190 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5191 /*
5192 * If the different P is found, it means that we can't
5193 * switch the display clock by using the FP0/FP1.
5194 * In such case we will disable the LVDS downclock
5195 * feature.
5196 */
5197 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 5198 "LVDS clock/downclock\n");
18f9ed12
ZY		 5199 has_reduced_clock = 0;
5200 }
652c393a 5201 }
7026d4ac
ZW		 5202 /* SDVO TV has fixed PLL values depend on its clock range,
5203 this mirrors vbios setting. */
5204 if (is_sdvo && is_tv) {
5205 if (adjusted_mode->clock >= 100000
5eddb70b 5206 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5207 clock.p1 = 2;
5208 clock.p2 = 10;
5209 clock.n = 3;
5210 clock.m1 = 16;
5211 clock.m2 = 8;
5212 } else if (adjusted_mode->clock >= 140500
5eddb70b 5213 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5214 clock.p1 = 1;
5215 clock.p2 = 10;
5216 clock.n = 6;
5217 clock.m1 = 12;
5218 clock.m2 = 8;
5219 }
5220 }
5221
2c07245f 5222 /* FDI link */
8febb297
EA		 5223 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5224 lane = 0;
5225 /* CPU eDP doesn't require FDI link, so just set DP M/N
5226 according to current link config */
5227 if (has_edp_encoder &&
5228 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5229 target_clock = mode->clock;
5230 intel_edp_link_config(has_edp_encoder,
5231 &lane, &link_bw);
5232 } else {
5233 /* [e]DP over FDI requires target mode clock
5234 instead of link clock */
5235 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5236 target_clock = mode->clock;
8febb297
EA		 5237 else
5238 target_clock = adjusted_mode->clock;
5239
5240 /* FDI is a binary signal running at ~2.7GHz, encoding
5241 * each output octet as 10 bits. The actual frequency
5242 * is stored as a divider into a 100MHz clock, and the
5243 * mode pixel clock is stored in units of 1KHz.
5244 * Hence the bw of each lane in terms of the mode signal
5245 * is:
5246 */
5247 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5248 }
58a27471 5249
8febb297
EA		 5250 /* determine panel color depth */
5251 temp = I915_READ(PIPECONF(pipe));
5252 temp &= ~PIPE_BPC_MASK;
5a354204
JB		 5253 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5254 switch (pipe_bpp) {
5255 case 18:
5256 temp |= PIPE_6BPC;
8febb297 5257 break;
5a354204
JB		 5258 case 24:
5259 temp |= PIPE_8BPC;
8febb297 5260 break;
5a354204
JB		 5261 case 30:
5262 temp |= PIPE_10BPC;
8febb297 5263 break;
5a354204
JB		 5264 case 36:
5265 temp |= PIPE_12BPC;
8febb297
EA		 5266 break;
5267 default:
62ac41a6
JB		 5268 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5269 pipe_bpp);
5a354204
JB		 5270 temp |= PIPE_8BPC;
5271 pipe_bpp = 24;
5272 break;
8febb297 5273 }
77ffb597 5274
5a354204
JB		 5275 intel_crtc->bpp = pipe_bpp;
5276 I915_WRITE(PIPECONF(pipe), temp);
5277
8febb297
EA		 5278 if (!lane) {
5279 /*
5280 * Account for spread spectrum to avoid
5281 * oversubscribing the link. Max center spread
5282 * is 2.5%; use 5% for safety's sake.
5283 */
5a354204 5284 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5285 lane = bps / (link_bw * 8) + 1;
5eb08b69 5286 }
2c07245f 5287
8febb297
EA		 5288 intel_crtc->fdi_lanes = lane;
5289
5290 if (pixel_multiplier > 1)
5291 link_bw *= pixel_multiplier;
5a354204
JB		 5292 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5293 &m_n);
8febb297 5294
c038e51e
ZW		 5295 /* Ironlake: try to setup display ref clock before DPLL
5296 * enabling. This is only under driver's control after
5297 * PCH B stepping, previous chipset stepping should be
5298 * ignoring this setting.
5299 */
8febb297
EA		 5300 temp = I915_READ(PCH_DREF_CONTROL);
5301 /* Always enable nonspread source */
5302 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5303 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5304 temp &= ~DREF_SSC_SOURCE_MASK;
5305 temp |= DREF_SSC_SOURCE_ENABLE;
5306 I915_WRITE(PCH_DREF_CONTROL, temp);
5307
5308 POSTING_READ(PCH_DREF_CONTROL);
5309 udelay(200);
fc9a2228 5310
8febb297
EA		 5311 if (has_edp_encoder) {
5312 if (intel_panel_use_ssc(dev_priv)) {
5313 temp |= DREF_SSC1_ENABLE;
fc9a2228 5314 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 5315
fc9a2228
CW		 5316 POSTING_READ(PCH_DREF_CONTROL);
5317 udelay(200);
5318 }
8febb297
EA		 5319 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5320
5321 /* Enable CPU source on CPU attached eDP */
5322 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5323 if (intel_panel_use_ssc(dev_priv))
5324 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5325 else
5326 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5327 } else {
5328 /* Enable SSC on PCH eDP if needed */
5329 if (intel_panel_use_ssc(dev_priv)) {
5330 DRM_ERROR("enabling SSC on PCH\n");
5331 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
5332 }
5333 }
5334 I915_WRITE(PCH_DREF_CONTROL, temp);
5335 POSTING_READ(PCH_DREF_CONTROL);
5336 udelay(200);
fc9a2228 5337 }
c038e51e 5338
a07d6787
EA		 5339 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5340 if (has_reduced_clock)
5341 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5342 reduced_clock.m2;
79e53945 5343
c1858123 5344 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5345 factor = 21;
5346 if (is_lvds) {
5347 if ((intel_panel_use_ssc(dev_priv) &&
5348 dev_priv->lvds_ssc_freq == 100) ||
5349 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5350 factor = 25;
5351 } else if (is_sdvo && is_tv)
5352 factor = 20;
c1858123 5353
cb0e0931 5354 if (clock.m < factor * clock.n)
8febb297 5355 fp |= FP_CB_TUNE;
2c07245f 5356
5eddb70b 5357 dpll = 0;
2c07245f 5358
a07d6787
EA		 5359 if (is_lvds)
5360 dpll |= DPLLB_MODE_LVDS;
5361 else
5362 dpll |= DPLLB_MODE_DAC_SERIAL;
5363 if (is_sdvo) {
5364 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5365 if (pixel_multiplier > 1) {
5366 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5367 }
a07d6787
EA		 5368 dpll |= DPLL_DVO_HIGH_SPEED;
5369 }
5370 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5371 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5372
a07d6787
EA		 5373 /* compute bitmask from p1 value */
5374 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5375 /* also FPA1 */
5376 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5377
5378 switch (clock.p2) {
5379 case 5:
5380 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5381 break;
5382 case 7:
5383 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5384 break;
5385 case 10:
5386 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5387 break;
5388 case 14:
5389 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5390 break;
79e53945
JB		 5391 }
5392
43565a06
KH		 5393 if (is_sdvo && is_tv)
5394 dpll |= PLL_REF_INPUT_TVCLKINBC;
5395 else if (is_tv)
79e53945 5396 /* XXX: just matching BIOS for now */
43565a06 5397 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5398 dpll |= 3;
a7615030 5399 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5400 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5401 else
5402 dpll |= PLL_REF_INPUT_DREFCLK;
5403
5404 /* setup pipeconf */
5eddb70b 5405 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5406
5407 /* Set up the display plane register */
5408 dspcntr = DISPPLANE_GAMMA_ENABLE;
5409
28c97730 5410 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5411 drm_mode_debug_printmodeline(mode);
5412
5c5313c8
JB		 5413 /* PCH eDP needs FDI, but CPU eDP does not */
5414 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 5415 I915_WRITE(PCH_FP0(pipe), fp);
5416 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5417
fae14981 5418 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 5419 udelay(150);
5420 }
5421
8db9d77b
ZW		 5422 /* enable transcoder DPLL */
5423 if (HAS_PCH_CPT(dev)) {
5424 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5425 switch (pipe) {
5426 case 0:
5eddb70b 5427 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5428 break;
5429 case 1:
5eddb70b 5430 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5431 break;
5432 case 2:
5433 /* FIXME: manage transcoder PLLs? */
5434 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5435 break;
5436 default:
5437 BUG();
32f9d658 5438 }
8db9d77b 5439 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5440
5441 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5442 udelay(150);
5443 }
5444
79e53945
JB		 5445 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5446 * This is an exception to the general rule that mode_set doesn't turn
5447 * things on.
5448 */
5449 if (is_lvds) {
fae14981 5450 temp = I915_READ(PCH_LVDS);
5eddb70b 5451 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 5452 if (pipe == 1) {
5453 if (HAS_PCH_CPT(dev))
5eddb70b 5454 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 5455 else
5eddb70b 5456 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 5457 } else {
5458 if (HAS_PCH_CPT(dev))
5eddb70b 5459 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5460 else
5eddb70b 5461 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5462 }
a3e17eb8 5463 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5464 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5465 /* Set the B0-B3 data pairs corresponding to whether we're going to
5466 * set the DPLLs for dual-channel mode or not.
5467 */
5468 if (clock.p2 == 7)
5eddb70b 5469 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5470 else
5eddb70b 5471 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5472
5473 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5474 * appropriately here, but we need to look more thoroughly into how
5475 * panels behave in the two modes.
5476 */
aa9b500d
BF		 5477 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5478 lvds_sync |= LVDS_HSYNC_POLARITY;
5479 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5480 lvds_sync |= LVDS_VSYNC_POLARITY;
5481 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5482 != lvds_sync) {
5483 char flags[2] = "-+";
5484 DRM_INFO("Changing LVDS panel from "
5485 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5486 flags[!(temp & LVDS_HSYNC_POLARITY)],
5487 flags[!(temp & LVDS_VSYNC_POLARITY)],
5488 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5489 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5490 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5491 temp |= lvds_sync;
5492 }
fae14981 5493 I915_WRITE(PCH_LVDS, temp);
79e53945 5494 }
434ed097 5495
8febb297
EA		 5496 pipeconf &= ~PIPECONF_DITHER_EN;
5497 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5498 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297
EA		 5499 pipeconf |= PIPECONF_DITHER_EN;
5500 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097 5501 }
5c5313c8 5502 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5503 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5504 } else {
8db9d77b 5505 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5506 I915_WRITE(TRANSDATA_M1(pipe), 0);
5507 I915_WRITE(TRANSDATA_N1(pipe), 0);
5508 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5509 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5510 }
79e53945 5511
8febb297
EA		 5512 if (!has_edp_encoder ||
5513 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5514 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5515
32f9d658 5516 /* Wait for the clocks to stabilize. */
fae14981 5517 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5518 udelay(150);
5519
8febb297
EA		 5520 /* The pixel multiplier can only be updated once the
5521 * DPLL is enabled and the clocks are stable.
5522 *
5523 * So write it again.
5524 */
fae14981 5525 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5526 }
79e53945 5527
5eddb70b 5528 intel_crtc->lowfreq_avail = false;
652c393a 5529 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5530 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5531 intel_crtc->lowfreq_avail = true;
5532 if (HAS_PIPE_CXSR(dev)) {
28c97730 5533 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5534 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5535 }
5536 } else {
fae14981 5537 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5538 if (HAS_PIPE_CXSR(dev)) {
28c97730 5539 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5540 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5541 }
5542 }
5543
734b4157
KH		 5544 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5545 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5546 /* the chip adds 2 halflines automatically */
5547 adjusted_mode->crtc_vdisplay -= 1;
5548 adjusted_mode->crtc_vtotal -= 1;
5549 adjusted_mode->crtc_vblank_start -= 1;
5550 adjusted_mode->crtc_vblank_end -= 1;
5551 adjusted_mode->crtc_vsync_end -= 1;
5552 adjusted_mode->crtc_vsync_start -= 1;
5553 } else
5554 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5555
5eddb70b
CW		 5556 I915_WRITE(HTOTAL(pipe),
5557 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5558 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5559 I915_WRITE(HBLANK(pipe),
5560 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5561 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5562 I915_WRITE(HSYNC(pipe),
5563 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5564 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5565
5566 I915_WRITE(VTOTAL(pipe),
5567 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5568 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5569 I915_WRITE(VBLANK(pipe),
5570 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5571 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5572 I915_WRITE(VSYNC(pipe),
5573 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5574 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5575
8febb297
EA		 5576 /* pipesrc controls the size that is scaled from, which should
5577 * always be the user's requested size.
79e53945 5578 */
5eddb70b
CW		 5579 I915_WRITE(PIPESRC(pipe),
5580 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5581
8febb297
EA		 5582 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5583 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5584 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5585 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5586
8febb297
EA		 5587 if (has_edp_encoder &&
5588 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5589 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5590 }
5591
5eddb70b
CW		 5592 I915_WRITE(PIPECONF(pipe), pipeconf);
5593 POSTING_READ(PIPECONF(pipe));
79e53945 5594
9d0498a2 5595 intel_wait_for_vblank(dev, pipe);
79e53945 5596
f00a3ddf 5597 if (IS_GEN5(dev)) {
553bd149
ZW		 5598 /* enable address swizzle for tiling buffer */
5599 temp = I915_READ(DISP_ARB_CTL);
5600 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5601 }
5602
5eddb70b 5603 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5604 POSTING_READ(DSPCNTR(plane));
79e53945 5605
5c3b82e2 5606 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5607
5608 intel_update_watermarks(dev);
5609
1f803ee5 5610 return ret;
79e53945
JB		 5611}
5612
f564048e
EA		 5613static int intel_crtc_mode_set(struct drm_crtc *crtc,
5614 struct drm_display_mode *mode,
5615 struct drm_display_mode *adjusted_mode,
5616 int x, int y,
5617 struct drm_framebuffer *old_fb)
5618{
5619 struct drm_device *dev = crtc->dev;
5620 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5622 int pipe = intel_crtc->pipe;
f564048e
EA		 5623 int ret;
5624
0b701d27 5625 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5626
f564048e
EA		 5627 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5628 x, y, old_fb);
7662c8bd 5629
79e53945 5630 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5631
120eced9
KP		 5632 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5633
1f803ee5 5634 return ret;
79e53945
JB		 5635}
5636
5637/** Loads the palette/gamma unit for the CRTC with the prepared values */
5638void intel_crtc_load_lut(struct drm_crtc *crtc)
5639{
5640 struct drm_device *dev = crtc->dev;
5641 struct drm_i915_private *dev_priv = dev->dev_private;
5642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5643 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5644 int i;
5645
5646 /* The clocks have to be on to load the palette. */
5647 if (!crtc->enabled)
5648 return;
5649
f2b115e6 5650 /* use legacy palette for Ironlake */
bad720ff 5651 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5652 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5653
79e53945
JB		 5654 for (i = 0; i < 256; i++) {
5655 I915_WRITE(palreg + 4 * i,
5656 (intel_crtc->lut_r[i] << 16) |
5657 (intel_crtc->lut_g[i] << 8) |
5658 intel_crtc->lut_b[i]);
5659 }
5660}
5661
560b85bb
CW		 5662static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5663{
5664 struct drm_device *dev = crtc->dev;
5665 struct drm_i915_private *dev_priv = dev->dev_private;
5666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5667 bool visible = base != 0;
5668 u32 cntl;
5669
5670 if (intel_crtc->cursor_visible == visible)
5671 return;
5672
9db4a9c7 5673 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5674 if (visible) {
5675 /* On these chipsets we can only modify the base whilst
5676 * the cursor is disabled.
5677 */
9db4a9c7 5678 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5679
5680 cntl &= ~(CURSOR_FORMAT_MASK);
5681 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5682 cntl |= CURSOR_ENABLE |
5683 CURSOR_GAMMA_ENABLE |
5684 CURSOR_FORMAT_ARGB;
5685 } else
5686 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5687 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5688
5689 intel_crtc->cursor_visible = visible;
5690}
5691
5692static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5693{
5694 struct drm_device *dev = crtc->dev;
5695 struct drm_i915_private *dev_priv = dev->dev_private;
5696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5697 int pipe = intel_crtc->pipe;
5698 bool visible = base != 0;
5699
5700 if (intel_crtc->cursor_visible != visible) {
548f245b 5701 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5702 if (base) {
5703 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5704 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5705 cntl |= pipe << 28; /* Connect to correct pipe */
5706 } else {
5707 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5708 cntl |= CURSOR_MODE_DISABLE;
5709 }
9db4a9c7 5710 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5711
5712 intel_crtc->cursor_visible = visible;
5713 }
5714 /* and commit changes on next vblank */
9db4a9c7 5715 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5716}
5717
cda4b7d3 5718/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5719static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5720 bool on)
cda4b7d3
CW		 5721{
5722 struct drm_device *dev = crtc->dev;
5723 struct drm_i915_private *dev_priv = dev->dev_private;
5724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5725 int pipe = intel_crtc->pipe;
5726 int x = intel_crtc->cursor_x;
5727 int y = intel_crtc->cursor_y;
560b85bb 5728 u32 base, pos;
cda4b7d3
CW		 5729 bool visible;
5730
5731 pos = 0;
5732
6b383a7f 5733 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5734 base = intel_crtc->cursor_addr;
5735 if (x > (int) crtc->fb->width)
5736 base = 0;
5737
5738 if (y > (int) crtc->fb->height)
5739 base = 0;
5740 } else
5741 base = 0;
5742
5743 if (x < 0) {
5744 if (x + intel_crtc->cursor_width < 0)
5745 base = 0;
5746
5747 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5748 x = -x;
5749 }
5750 pos |= x << CURSOR_X_SHIFT;
5751
5752 if (y < 0) {
5753 if (y + intel_crtc->cursor_height < 0)
5754 base = 0;
5755
5756 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5757 y = -y;
5758 }
5759 pos |= y << CURSOR_Y_SHIFT;
5760
5761 visible = base != 0;
560b85bb 5762 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5763 return;
5764
9db4a9c7 5765 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5766 if (IS_845G(dev) || IS_I865G(dev))
5767 i845_update_cursor(crtc, base);
5768 else
5769 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5770
5771 if (visible)
5772 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5773}
5774
79e53945 5775static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5776 struct drm_file *file,
79e53945
JB		 5777 uint32_t handle,
5778 uint32_t width, uint32_t height)
5779{
5780 struct drm_device *dev = crtc->dev;
5781 struct drm_i915_private *dev_priv = dev->dev_private;
5782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5783 struct drm_i915_gem_object *obj;
cda4b7d3 5784 uint32_t addr;
3f8bc370 5785 int ret;
79e53945 5786
28c97730 5787 DRM_DEBUG_KMS("\n");
79e53945
JB		 5788
5789 /* if we want to turn off the cursor ignore width and height */
5790 if (!handle) {
28c97730 5791 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5792 addr = 0;
05394f39 5793 obj = NULL;
5004417d 5794 mutex_lock(&dev->struct_mutex);
3f8bc370 5795 goto finish;
79e53945
JB		 5796 }
5797
5798 /* Currently we only support 64x64 cursors */
5799 if (width != 64 || height != 64) {
5800 DRM_ERROR("we currently only support 64x64 cursors\n");
5801 return -EINVAL;
5802 }
5803
05394f39 5804 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5805 if (&obj->base == NULL)
79e53945
JB		 5806 return -ENOENT;
5807
05394f39 5808 if (obj->base.size < width * height * 4) {
79e53945 5809 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5810 ret = -ENOMEM;
5811 goto fail;
79e53945
JB		 5812 }
5813
71acb5eb 5814 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5815 mutex_lock(&dev->struct_mutex);
b295d1b6 5816 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5817 if (obj->tiling_mode) {
5818 DRM_ERROR("cursor cannot be tiled\n");
5819 ret = -EINVAL;
5820 goto fail_locked;
5821 }
5822
2da3b9b9 5823 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5824 if (ret) {
5825 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5826 goto fail_locked;
e7b526bb
CW		 5827 }
5828
d9e86c0e
CW		 5829 ret = i915_gem_object_put_fence(obj);
5830 if (ret) {
2da3b9b9 5831 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5832 goto fail_unpin;
5833 }
5834
05394f39 5835 addr = obj->gtt_offset;
71acb5eb 5836 } else {
6eeefaf3 5837 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5838 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5839 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5840 align);
71acb5eb
DA		 5841 if (ret) {
5842 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5843 goto fail_locked;
71acb5eb 5844 }
05394f39 5845 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5846 }
5847
a6c45cf0 5848 if (IS_GEN2(dev))
14b60391
JB		 5849 I915_WRITE(CURSIZE, (height << 12) | width);
5850
3f8bc370 5851 finish:
3f8bc370 5852 if (intel_crtc->cursor_bo) {
b295d1b6 5853 if (dev_priv->info->cursor_needs_physical) {
05394f39 5854 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5855 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5856 } else
5857 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5858 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5859 }
80824003 5860
7f9872e0 5861 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5862
5863 intel_crtc->cursor_addr = addr;
05394f39 5864 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5865 intel_crtc->cursor_width = width;
5866 intel_crtc->cursor_height = height;
5867
6b383a7f 5868 intel_crtc_update_cursor(crtc, true);
3f8bc370 5869
79e53945 5870 return 0;
e7b526bb 5871fail_unpin:
05394f39 5872 i915_gem_object_unpin(obj);
7f9872e0 5873fail_locked:
34b8686e 5874 mutex_unlock(&dev->struct_mutex);
bc9025bd 5875fail:
05394f39 5876 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5877 return ret;
79e53945
JB		 5878}
5879
5880static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5881{
79e53945 5882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5883
cda4b7d3
CW		 5884 intel_crtc->cursor_x = x;
5885 intel_crtc->cursor_y = y;
652c393a 5886
6b383a7f 5887 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5888
5889 return 0;
5890}
5891
5892/** Sets the color ramps on behalf of RandR */
5893void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5894 u16 blue, int regno)
5895{
5896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5897
5898 intel_crtc->lut_r[regno] = red >> 8;
5899 intel_crtc->lut_g[regno] = green >> 8;
5900 intel_crtc->lut_b[regno] = blue >> 8;
5901}
5902
b8c00ac5
DA		 5903void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5904 u16 *blue, int regno)
5905{
5906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5907
5908 *red = intel_crtc->lut_r[regno] << 8;
5909 *green = intel_crtc->lut_g[regno] << 8;
5910 *blue = intel_crtc->lut_b[regno] << 8;
5911}
5912
79e53945 5913static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5914 u16 *blue, uint32_t start, uint32_t size)
79e53945 5915{
7203425a 5916 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5918
7203425a 5919 for (i = start; i < end; i++) {
79e53945
JB		 5920 intel_crtc->lut_r[i] = red[i] >> 8;
5921 intel_crtc->lut_g[i] = green[i] >> 8;
5922 intel_crtc->lut_b[i] = blue[i] >> 8;
5923 }
5924
5925 intel_crtc_load_lut(crtc);
5926}
5927
5928/**
5929 * Get a pipe with a simple mode set on it for doing load-based monitor
5930 * detection.
5931 *
5932 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5933 * its requirements. The pipe will be connected to no other encoders.
79e53945 5934 *
c751ce4f 5935 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5936 * configured for it. In the future, it could choose to temporarily disable
5937 * some outputs to free up a pipe for its use.
5938 *
5939 * \return crtc, or NULL if no pipes are available.
5940 */
5941
5942/* VESA 640x480x72Hz mode to set on the pipe */
5943static struct drm_display_mode load_detect_mode = {
5944 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5945 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5946};
5947
d2dff872
CW		 5948static struct drm_framebuffer *
5949intel_framebuffer_create(struct drm_device *dev,
5950 struct drm_mode_fb_cmd *mode_cmd,
5951 struct drm_i915_gem_object *obj)
5952{
5953 struct intel_framebuffer *intel_fb;
5954 int ret;
5955
5956 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5957 if (!intel_fb) {
5958 drm_gem_object_unreference_unlocked(&obj->base);
5959 return ERR_PTR(-ENOMEM);
5960 }
5961
5962 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5963 if (ret) {
5964 drm_gem_object_unreference_unlocked(&obj->base);
5965 kfree(intel_fb);
5966 return ERR_PTR(ret);
5967 }
5968
5969 return &intel_fb->base;
5970}
5971
5972static u32
5973intel_framebuffer_pitch_for_width(int width, int bpp)
5974{
5975 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5976 return ALIGN(pitch, 64);
5977}
5978
5979static u32
5980intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5981{
5982 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5983 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5984}
5985
5986static struct drm_framebuffer *
5987intel_framebuffer_create_for_mode(struct drm_device *dev,
5988 struct drm_display_mode *mode,
5989 int depth, int bpp)
5990{
5991 struct drm_i915_gem_object *obj;
5992 struct drm_mode_fb_cmd mode_cmd;
5993
5994 obj = i915_gem_alloc_object(dev,
5995 intel_framebuffer_size_for_mode(mode, bpp));
5996 if (obj == NULL)
5997 return ERR_PTR(-ENOMEM);
5998
5999 mode_cmd.width = mode->hdisplay;
6000 mode_cmd.height = mode->vdisplay;
6001 mode_cmd.depth = depth;
6002 mode_cmd.bpp = bpp;
6003 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6004
6005 return intel_framebuffer_create(dev, &mode_cmd, obj);
6006}
6007
6008static struct drm_framebuffer *
6009mode_fits_in_fbdev(struct drm_device *dev,
6010 struct drm_display_mode *mode)
6011{
6012 struct drm_i915_private *dev_priv = dev->dev_private;
6013 struct drm_i915_gem_object *obj;
6014 struct drm_framebuffer *fb;
6015
6016 if (dev_priv->fbdev == NULL)
6017 return NULL;
6018
6019 obj = dev_priv->fbdev->ifb.obj;
6020 if (obj == NULL)
6021 return NULL;
6022
6023 fb = &dev_priv->fbdev->ifb.base;
6024 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6025 fb->bits_per_pixel))
6026 return NULL;
6027
6028 if (obj->base.size < mode->vdisplay * fb->pitch)
6029 return NULL;
6030
6031 return fb;
6032}
6033
7173188d
CW		 6034bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6035 struct drm_connector *connector,
6036 struct drm_display_mode *mode,
8261b191 6037 struct intel_load_detect_pipe *old)
79e53945
JB		 6038{
6039 struct intel_crtc *intel_crtc;
6040 struct drm_crtc *possible_crtc;
4ef69c7a 6041 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6042 struct drm_crtc *crtc = NULL;
6043 struct drm_device *dev = encoder->dev;
d2dff872 6044 struct drm_framebuffer *old_fb;
79e53945
JB		 6045 int i = -1;
6046
d2dff872
CW		 6047 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6048 connector->base.id, drm_get_connector_name(connector),
6049 encoder->base.id, drm_get_encoder_name(encoder));
6050
79e53945
JB		 6051 /*
6052 * Algorithm gets a little messy:
7a5e4805 6053 *
79e53945
JB		 6054 * - if the connector already has an assigned crtc, use it (but make
6055 * sure it's on first)
7a5e4805 6056 *
79e53945
JB		 6057 * - try to find the first unused crtc that can drive this connector,
6058 * and use that if we find one
79e53945
JB		 6059 */
6060
6061 /* See if we already have a CRTC for this connector */
6062 if (encoder->crtc) {
6063 crtc = encoder->crtc;
8261b191 6064
79e53945 6065 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6066 old->dpms_mode = intel_crtc->dpms_mode;
6067 old->load_detect_temp = false;
6068
6069 /* Make sure the crtc and connector are running */
79e53945 6070 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6071 struct drm_encoder_helper_funcs *encoder_funcs;
6072 struct drm_crtc_helper_funcs *crtc_funcs;
6073
79e53945
JB		 6074 crtc_funcs = crtc->helper_private;
6075 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6076
6077 encoder_funcs = encoder->helper_private;
79e53945
JB		 6078 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6079 }
8261b191 6080
7173188d 6081 return true;
79e53945
JB		 6082 }
6083
6084 /* Find an unused one (if possible) */
6085 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6086 i++;
6087 if (!(encoder->possible_crtcs & (1 << i)))
6088 continue;
6089 if (!possible_crtc->enabled) {
6090 crtc = possible_crtc;
6091 break;
6092 }
79e53945
JB		 6093 }
6094
6095 /*
6096 * If we didn't find an unused CRTC, don't use any.
6097 */
6098 if (!crtc) {
7173188d
CW		 6099 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6100 return false;
79e53945
JB		 6101 }
6102
6103 encoder->crtc = crtc;
c1c43977 6104 connector->encoder = encoder;
79e53945
JB		 6105
6106 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6107 old->dpms_mode = intel_crtc->dpms_mode;
6108 old->load_detect_temp = true;
d2dff872 6109 old->release_fb = NULL;
79e53945 6110
6492711d
CW		 6111 if (!mode)
6112 mode = &load_detect_mode;
79e53945 6113
d2dff872
CW		 6114 old_fb = crtc->fb;
6115
6116 /* We need a framebuffer large enough to accommodate all accesses
6117 * that the plane may generate whilst we perform load detection.
6118 * We can not rely on the fbcon either being present (we get called
6119 * during its initialisation to detect all boot displays, or it may
6120 * not even exist) or that it is large enough to satisfy the
6121 * requested mode.
6122 */
6123 crtc->fb = mode_fits_in_fbdev(dev, mode);
6124 if (crtc->fb == NULL) {
6125 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6126 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6127 old->release_fb = crtc->fb;
6128 } else
6129 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6130 if (IS_ERR(crtc->fb)) {
6131 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6132 crtc->fb = old_fb;
6133 return false;
79e53945 6134 }
79e53945 6135
d2dff872 6136 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6137 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6138 if (old->release_fb)
6139 old->release_fb->funcs->destroy(old->release_fb);
6140 crtc->fb = old_fb;
6492711d 6141 return false;
79e53945 6142 }
7173188d 6143
79e53945 6144 /* let the connector get through one full cycle before testing */
9d0498a2 6145 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6146
7173188d 6147 return true;
79e53945
JB		 6148}
6149
c1c43977 6150void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6151 struct drm_connector *connector,
6152 struct intel_load_detect_pipe *old)
79e53945 6153{
4ef69c7a 6154 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6155 struct drm_device *dev = encoder->dev;
6156 struct drm_crtc *crtc = encoder->crtc;
6157 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6158 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6159
d2dff872
CW		 6160 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6161 connector->base.id, drm_get_connector_name(connector),
6162 encoder->base.id, drm_get_encoder_name(encoder));
6163
8261b191 6164 if (old->load_detect_temp) {
c1c43977 6165 connector->encoder = NULL;
79e53945 6166 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6167
6168 if (old->release_fb)
6169 old->release_fb->funcs->destroy(old->release_fb);
6170
0622a53c 6171 return;
79e53945
JB		 6172 }
6173
c751ce4f 6174 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6175 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6176 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6177 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6178 }
6179}
6180
6181/* Returns the clock of the currently programmed mode of the given pipe. */
6182static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6183{
6184 struct drm_i915_private *dev_priv = dev->dev_private;
6185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6186 int pipe = intel_crtc->pipe;
548f245b 6187 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6188 u32 fp;
6189 intel_clock_t clock;
6190
6191 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6192 fp = I915_READ(FP0(pipe));
79e53945 6193 else
39adb7a5 6194 fp = I915_READ(FP1(pipe));
79e53945
JB		 6195
6196 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6197 if (IS_PINEVIEW(dev)) {
6198 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6199 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6200 } else {
6201 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6202 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6203 }
6204
a6c45cf0 6205 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6206 if (IS_PINEVIEW(dev))
6207 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6208 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6209 else
6210 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6211 DPLL_FPA01_P1_POST_DIV_SHIFT);
6212
6213 switch (dpll & DPLL_MODE_MASK) {
6214 case DPLLB_MODE_DAC_SERIAL:
6215 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6216 5 : 10;
6217 break;
6218 case DPLLB_MODE_LVDS:
6219 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6220 7 : 14;
6221 break;
6222 default:
28c97730 6223 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6224 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6225 return 0;
6226 }
6227
6228 /* XXX: Handle the 100Mhz refclk */
2177832f 6229 intel_clock(dev, 96000, &clock);
79e53945
JB		 6230 } else {
6231 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6232
6233 if (is_lvds) {
6234 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6235 DPLL_FPA01_P1_POST_DIV_SHIFT);
6236 clock.p2 = 14;
6237
6238 if ((dpll & PLL_REF_INPUT_MASK) ==
6239 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6240 /* XXX: might not be 66MHz */
2177832f 6241 intel_clock(dev, 66000, &clock);
79e53945 6242 } else
2177832f 6243 intel_clock(dev, 48000, &clock);
79e53945
JB		 6244 } else {
6245 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6246 clock.p1 = 2;
6247 else {
6248 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6249 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6250 }
6251 if (dpll & PLL_P2_DIVIDE_BY_4)
6252 clock.p2 = 4;
6253 else
6254 clock.p2 = 2;
6255
2177832f 6256 intel_clock(dev, 48000, &clock);
79e53945
JB		 6257 }
6258 }
6259
6260 /* XXX: It would be nice to validate the clocks, but we can't reuse
6261 * i830PllIsValid() because it relies on the xf86_config connector
6262 * configuration being accurate, which it isn't necessarily.
6263 */
6264
6265 return clock.dot;
6266}
6267
6268/** Returns the currently programmed mode of the given pipe. */
6269struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6270 struct drm_crtc *crtc)
6271{
548f245b 6272 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6274 int pipe = intel_crtc->pipe;
6275 struct drm_display_mode *mode;
548f245b
JB		 6276 int htot = I915_READ(HTOTAL(pipe));
6277 int hsync = I915_READ(HSYNC(pipe));
6278 int vtot = I915_READ(VTOTAL(pipe));
6279 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6280
6281 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6282 if (!mode)
6283 return NULL;
6284
6285 mode->clock = intel_crtc_clock_get(dev, crtc);
6286 mode->hdisplay = (htot & 0xffff) + 1;
6287 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6288 mode->hsync_start = (hsync & 0xffff) + 1;
6289 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6290 mode->vdisplay = (vtot & 0xffff) + 1;
6291 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6292 mode->vsync_start = (vsync & 0xffff) + 1;
6293 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6294
6295 drm_mode_set_name(mode);
6296 drm_mode_set_crtcinfo(mode, 0);
6297
6298 return mode;
6299}
6300
652c393a
JB		 6301#define GPU_IDLE_TIMEOUT 500 /* ms */
6302
6303/* When this timer fires, we've been idle for awhile */
6304static void intel_gpu_idle_timer(unsigned long arg)
6305{
6306 struct drm_device *dev = (struct drm_device *)arg;
6307 drm_i915_private_t *dev_priv = dev->dev_private;
6308
ff7ea4c0
CW		 6309 if (!list_empty(&dev_priv->mm.active_list)) {
6310 /* Still processing requests, so just re-arm the timer. */
6311 mod_timer(&dev_priv->idle_timer, jiffies +
6312 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6313 return;
6314 }
652c393a 6315
ff7ea4c0 6316 dev_priv->busy = false;
01dfba93 6317 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6318}
6319
652c393a
JB		 6320#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6321
6322static void intel_crtc_idle_timer(unsigned long arg)
6323{
6324 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6325 struct drm_crtc *crtc = &intel_crtc->base;
6326 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6327 struct intel_framebuffer *intel_fb;
652c393a 6328
ff7ea4c0
CW		 6329 intel_fb = to_intel_framebuffer(crtc->fb);
6330 if (intel_fb && intel_fb->obj->active) {
6331 /* The framebuffer is still being accessed by the GPU. */
6332 mod_timer(&intel_crtc->idle_timer, jiffies +
6333 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6334 return;
6335 }
652c393a 6336
ff7ea4c0 6337 intel_crtc->busy = false;
01dfba93 6338 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6339}
6340
3dec0095 6341static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6342{
6343 struct drm_device *dev = crtc->dev;
6344 drm_i915_private_t *dev_priv = dev->dev_private;
6345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6346 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6347 int dpll_reg = DPLL(pipe);
6348 int dpll;
652c393a 6349
bad720ff 6350 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6351 return;
6352
6353 if (!dev_priv->lvds_downclock_avail)
6354 return;
6355
dbdc6479 6356 dpll = I915_READ(dpll_reg);
652c393a 6357 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6358 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6359
6360 /* Unlock panel regs */
dbdc6479
JB		 6361 I915_WRITE(PP_CONTROL,
6362 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6363
6364 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6365 I915_WRITE(dpll_reg, dpll);
9d0498a2 6366 intel_wait_for_vblank(dev, pipe);
dbdc6479 6367
652c393a
JB		 6368 dpll = I915_READ(dpll_reg);
6369 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6370 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6371
6372 /* ...and lock them again */
6373 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6374 }
6375
6376 /* Schedule downclock */
3dec0095
DV		 6377 mod_timer(&intel_crtc->idle_timer, jiffies +
6378 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6379}
6380
6381static void intel_decrease_pllclock(struct drm_crtc *crtc)
6382{
6383 struct drm_device *dev = crtc->dev;
6384 drm_i915_private_t *dev_priv = dev->dev_private;
6385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386 int pipe = intel_crtc->pipe;
9db4a9c7 6387 int dpll_reg = DPLL(pipe);
652c393a
JB		 6388 int dpll = I915_READ(dpll_reg);
6389
bad720ff 6390 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6391 return;
6392
6393 if (!dev_priv->lvds_downclock_avail)
6394 return;
6395
6396 /*
6397 * Since this is called by a timer, we should never get here in
6398 * the manual case.
6399 */
6400 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6401 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6402
6403 /* Unlock panel regs */
4a655f04
JB		 6404 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6405 PANEL_UNLOCK_REGS);
652c393a
JB		 6406
6407 dpll |= DISPLAY_RATE_SELECT_FPA1;
6408 I915_WRITE(dpll_reg, dpll);
9d0498a2 6409 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6410 dpll = I915_READ(dpll_reg);
6411 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6412 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6413
6414 /* ...and lock them again */
6415 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6416 }
6417
6418}
6419
6420/**
6421 * intel_idle_update - adjust clocks for idleness
6422 * @work: work struct
6423 *
6424 * Either the GPU or display (or both) went idle. Check the busy status
6425 * here and adjust the CRTC and GPU clocks as necessary.
6426 */
6427static void intel_idle_update(struct work_struct *work)
6428{
6429 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6430 idle_work);
6431 struct drm_device *dev = dev_priv->dev;
6432 struct drm_crtc *crtc;
6433 struct intel_crtc *intel_crtc;
6434
6435 if (!i915_powersave)
6436 return;
6437
6438 mutex_lock(&dev->struct_mutex);
6439
7648fa99
JB		 6440 i915_update_gfx_val(dev_priv);
6441
652c393a
JB		 6442 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6443 /* Skip inactive CRTCs */
6444 if (!crtc->fb)
6445 continue;
6446
6447 intel_crtc = to_intel_crtc(crtc);
6448 if (!intel_crtc->busy)
6449 intel_decrease_pllclock(crtc);
6450 }
6451
45ac22c8 6452
652c393a
JB		 6453 mutex_unlock(&dev->struct_mutex);
6454}
6455
6456/**
6457 * intel_mark_busy - mark the GPU and possibly the display busy
6458 * @dev: drm device
6459 * @obj: object we're operating on
6460 *
6461 * Callers can use this function to indicate that the GPU is busy processing
6462 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6463 * buffer), we'll also mark the display as busy, so we know to increase its
6464 * clock frequency.
6465 */
05394f39 6466void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6467{
6468 drm_i915_private_t *dev_priv = dev->dev_private;
6469 struct drm_crtc *crtc = NULL;
6470 struct intel_framebuffer *intel_fb;
6471 struct intel_crtc *intel_crtc;
6472
5e17ee74
ZW		 6473 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6474 return;
6475
18b2190c 6476 if (!dev_priv->busy)
28cf798f 6477 dev_priv->busy = true;
18b2190c 6478 else
28cf798f
CW		 6479 mod_timer(&dev_priv->idle_timer, jiffies +
6480 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6481
6482 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6483 if (!crtc->fb)
6484 continue;
6485
6486 intel_crtc = to_intel_crtc(crtc);
6487 intel_fb = to_intel_framebuffer(crtc->fb);
6488 if (intel_fb->obj == obj) {
6489 if (!intel_crtc->busy) {
6490 /* Non-busy -> busy, upclock */
3dec0095 6491 intel_increase_pllclock(crtc);
652c393a
JB		 6492 intel_crtc->busy = true;
6493 } else {
6494 /* Busy -> busy, put off timer */
6495 mod_timer(&intel_crtc->idle_timer, jiffies +
6496 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6497 }
6498 }
6499 }
6500}
6501
79e53945
JB		 6502static void intel_crtc_destroy(struct drm_crtc *crtc)
6503{
6504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6505 struct drm_device *dev = crtc->dev;
6506 struct intel_unpin_work *work;
6507 unsigned long flags;
6508
6509 spin_lock_irqsave(&dev->event_lock, flags);
6510 work = intel_crtc->unpin_work;
6511 intel_crtc->unpin_work = NULL;
6512 spin_unlock_irqrestore(&dev->event_lock, flags);
6513
6514 if (work) {
6515 cancel_work_sync(&work->work);
6516 kfree(work);
6517 }
79e53945
JB		 6518
6519 drm_crtc_cleanup(crtc);
67e77c5a 6520
79e53945
JB		 6521 kfree(intel_crtc);
6522}
6523
6b95a207
KH		 6524static void intel_unpin_work_fn(struct work_struct *__work)
6525{
6526 struct intel_unpin_work *work =
6527 container_of(__work, struct intel_unpin_work, work);
6528
6529 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6530 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6531 drm_gem_object_unreference(&work->pending_flip_obj->base);
6532 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6533
7782de3b 6534 intel_update_fbc(work->dev);
6b95a207
KH		 6535 mutex_unlock(&work->dev->struct_mutex);
6536 kfree(work);
6537}
6538
1afe3e9d 6539static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6540 struct drm_crtc *crtc)
6b95a207
KH		 6541{
6542 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6544 struct intel_unpin_work *work;
05394f39 6545 struct drm_i915_gem_object *obj;
6b95a207 6546 struct drm_pending_vblank_event *e;
49b14a5c 6547 struct timeval tnow, tvbl;
6b95a207
KH		 6548 unsigned long flags;
6549
6550 /* Ignore early vblank irqs */
6551 if (intel_crtc == NULL)
6552 return;
6553
49b14a5c
MK		 6554 do_gettimeofday(&tnow);
6555
6b95a207
KH		 6556 spin_lock_irqsave(&dev->event_lock, flags);
6557 work = intel_crtc->unpin_work;
6558 if (work == NULL || !work->pending) {
6559 spin_unlock_irqrestore(&dev->event_lock, flags);
6560 return;
6561 }
6562
6563 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6564
6565 if (work->event) {
6566 e = work->event;
49b14a5c 6567 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6568
6569 /* Called before vblank count and timestamps have
6570 * been updated for the vblank interval of flip
6571 * completion? Need to increment vblank count and
6572 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6573 * to account for this. We assume this happened if we
6574 * get called over 0.9 frame durations after the last
6575 * timestamped vblank.
6576 *
6577 * This calculation can not be used with vrefresh rates
6578 * below 5Hz (10Hz to be on the safe side) without
6579 * promoting to 64 integers.
0af7e4df 6580 */
49b14a5c
MK		 6581 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6582 9 * crtc->framedur_ns) {
0af7e4df 6583 e->event.sequence++;
49b14a5c
MK		 6584 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6585 crtc->framedur_ns);
0af7e4df
MK		 6586 }
6587
49b14a5c
MK		 6588 e->event.tv_sec = tvbl.tv_sec;
6589 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6590
6b95a207
KH		 6591 list_add_tail(&e->base.link,
6592 &e->base.file_priv->event_list);
6593 wake_up_interruptible(&e->base.file_priv->event_wait);
6594 }
6595
0af7e4df
MK		 6596 drm_vblank_put(dev, intel_crtc->pipe);
6597
6b95a207
KH		 6598 spin_unlock_irqrestore(&dev->event_lock, flags);
6599
05394f39 6600 obj = work->old_fb_obj;
d9e86c0e 6601
e59f2bac 6602 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6603 &obj->pending_flip.counter);
6604 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6605 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6606
6b95a207 6607 schedule_work(&work->work);
e5510fac
JB		 6608
6609 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6610}
6611
1afe3e9d
JB		 6612void intel_finish_page_flip(struct drm_device *dev, int pipe)
6613{
6614 drm_i915_private_t *dev_priv = dev->dev_private;
6615 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6616
49b14a5c 6617 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6618}
6619
6620void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6621{
6622 drm_i915_private_t *dev_priv = dev->dev_private;
6623 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6624
49b14a5c 6625 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6626}
6627
6b95a207
KH		 6628void intel_prepare_page_flip(struct drm_device *dev, int plane)
6629{
6630 drm_i915_private_t *dev_priv = dev->dev_private;
6631 struct intel_crtc *intel_crtc =
6632 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6633 unsigned long flags;
6634
6635 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6636 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6637 if ((++intel_crtc->unpin_work->pending) > 1)
6638 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6639 } else {
6640 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6641 }
6b95a207
KH		 6642 spin_unlock_irqrestore(&dev->event_lock, flags);
6643}
6644
8c9f3aaf
JB		 6645static int intel_gen2_queue_flip(struct drm_device *dev,
6646 struct drm_crtc *crtc,
6647 struct drm_framebuffer *fb,
6648 struct drm_i915_gem_object *obj)
6649{
6650 struct drm_i915_private *dev_priv = dev->dev_private;
6651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6652 unsigned long offset;
6653 u32 flip_mask;
6654 int ret;
6655
6656 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6657 if (ret)
6658 goto out;
6659
6660 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6661 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6662
6663 ret = BEGIN_LP_RING(6);
6664 if (ret)
6665 goto out;
6666
6667 /* Can't queue multiple flips, so wait for the previous
6668 * one to finish before executing the next.
6669 */
6670 if (intel_crtc->plane)
6671 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6672 else
6673 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6674 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6675 OUT_RING(MI_NOOP);
6676 OUT_RING(MI_DISPLAY_FLIP |
6677 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6678 OUT_RING(fb->pitch);
6679 OUT_RING(obj->gtt_offset + offset);
6680 OUT_RING(MI_NOOP);
6681 ADVANCE_LP_RING();
6682out:
6683 return ret;
6684}
6685
6686static int intel_gen3_queue_flip(struct drm_device *dev,
6687 struct drm_crtc *crtc,
6688 struct drm_framebuffer *fb,
6689 struct drm_i915_gem_object *obj)
6690{
6691 struct drm_i915_private *dev_priv = dev->dev_private;
6692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6693 unsigned long offset;
6694 u32 flip_mask;
6695 int ret;
6696
6697 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6698 if (ret)
6699 goto out;
6700
6701 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6702 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6703
6704 ret = BEGIN_LP_RING(6);
6705 if (ret)
6706 goto out;
6707
6708 if (intel_crtc->plane)
6709 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6710 else
6711 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6712 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6713 OUT_RING(MI_NOOP);
6714 OUT_RING(MI_DISPLAY_FLIP_I915 |
6715 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6716 OUT_RING(fb->pitch);
6717 OUT_RING(obj->gtt_offset + offset);
6718 OUT_RING(MI_NOOP);
6719
6720 ADVANCE_LP_RING();
6721out:
6722 return ret;
6723}
6724
6725static int intel_gen4_queue_flip(struct drm_device *dev,
6726 struct drm_crtc *crtc,
6727 struct drm_framebuffer *fb,
6728 struct drm_i915_gem_object *obj)
6729{
6730 struct drm_i915_private *dev_priv = dev->dev_private;
6731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6732 uint32_t pf, pipesrc;
6733 int ret;
6734
6735 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6736 if (ret)
6737 goto out;
6738
6739 ret = BEGIN_LP_RING(4);
6740 if (ret)
6741 goto out;
6742
6743 /* i965+ uses the linear or tiled offsets from the
6744 * Display Registers (which do not change across a page-flip)
6745 * so we need only reprogram the base address.
6746 */
6747 OUT_RING(MI_DISPLAY_FLIP |
6748 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6749 OUT_RING(fb->pitch);
6750 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6751
6752 /* XXX Enabling the panel-fitter across page-flip is so far
6753 * untested on non-native modes, so ignore it for now.
6754 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6755 */
6756 pf = 0;
6757 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6758 OUT_RING(pf | pipesrc);
6759 ADVANCE_LP_RING();
6760out:
6761 return ret;
6762}
6763
6764static int intel_gen6_queue_flip(struct drm_device *dev,
6765 struct drm_crtc *crtc,
6766 struct drm_framebuffer *fb,
6767 struct drm_i915_gem_object *obj)
6768{
6769 struct drm_i915_private *dev_priv = dev->dev_private;
6770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6771 uint32_t pf, pipesrc;
6772 int ret;
6773
6774 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6775 if (ret)
6776 goto out;
6777
6778 ret = BEGIN_LP_RING(4);
6779 if (ret)
6780 goto out;
6781
6782 OUT_RING(MI_DISPLAY_FLIP |
6783 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6784 OUT_RING(fb->pitch | obj->tiling_mode);
6785 OUT_RING(obj->gtt_offset);
6786
6787 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6788 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6789 OUT_RING(pf | pipesrc);
6790 ADVANCE_LP_RING();
6791out:
6792 return ret;
6793}
6794
7c9017e5
JB		 6795/*
6796 * On gen7 we currently use the blit ring because (in early silicon at least)
6797 * the render ring doesn't give us interrpts for page flip completion, which
6798 * means clients will hang after the first flip is queued. Fortunately the
6799 * blit ring generates interrupts properly, so use it instead.
6800 */
6801static int intel_gen7_queue_flip(struct drm_device *dev,
6802 struct drm_crtc *crtc,
6803 struct drm_framebuffer *fb,
6804 struct drm_i915_gem_object *obj)
6805{
6806 struct drm_i915_private *dev_priv = dev->dev_private;
6807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6808 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6809 int ret;
6810
6811 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6812 if (ret)
6813 goto out;
6814
6815 ret = intel_ring_begin(ring, 4);
6816 if (ret)
6817 goto out;
6818
6819 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6820 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6821 intel_ring_emit(ring, (obj->gtt_offset));
6822 intel_ring_emit(ring, (MI_NOOP));
6823 intel_ring_advance(ring);
6824out:
6825 return ret;
6826}
6827
8c9f3aaf
JB		 6828static int intel_default_queue_flip(struct drm_device *dev,
6829 struct drm_crtc *crtc,
6830 struct drm_framebuffer *fb,
6831 struct drm_i915_gem_object *obj)
6832{
6833 return -ENODEV;
6834}
6835
6b95a207
KH		 6836static int intel_crtc_page_flip(struct drm_crtc *crtc,
6837 struct drm_framebuffer *fb,
6838 struct drm_pending_vblank_event *event)
6839{
6840 struct drm_device *dev = crtc->dev;
6841 struct drm_i915_private *dev_priv = dev->dev_private;
6842 struct intel_framebuffer *intel_fb;
05394f39 6843 struct drm_i915_gem_object *obj;
6b95a207
KH		 6844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6845 struct intel_unpin_work *work;
8c9f3aaf 6846 unsigned long flags;
52e68630 6847 int ret;
6b95a207
KH		 6848
6849 work = kzalloc(sizeof *work, GFP_KERNEL);
6850 if (work == NULL)
6851 return -ENOMEM;
6852
6b95a207
KH		 6853 work->event = event;
6854 work->dev = crtc->dev;
6855 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6856 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6857 INIT_WORK(&work->work, intel_unpin_work_fn);
6858
6859 /* We borrow the event spin lock for protecting unpin_work */
6860 spin_lock_irqsave(&dev->event_lock, flags);
6861 if (intel_crtc->unpin_work) {
6862 spin_unlock_irqrestore(&dev->event_lock, flags);
6863 kfree(work);
468f0b44
CW		 6864
6865 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6866 return -EBUSY;
6867 }
6868 intel_crtc->unpin_work = work;
6869 spin_unlock_irqrestore(&dev->event_lock, flags);
6870
6871 intel_fb = to_intel_framebuffer(fb);
6872 obj = intel_fb->obj;
6873
468f0b44 6874 mutex_lock(&dev->struct_mutex);
6b95a207 6875
75dfca80 6876 /* Reference the objects for the scheduled work. */
05394f39
CW		 6877 drm_gem_object_reference(&work->old_fb_obj->base);
6878 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6879
6880 crtc->fb = fb;
96b099fd
CW		 6881
6882 ret = drm_vblank_get(dev, intel_crtc->pipe);
6883 if (ret)
6884 goto cleanup_objs;
6885
e1f99ce6 6886 work->pending_flip_obj = obj;
e1f99ce6 6887
4e5359cd
SF		 6888 work->enable_stall_check = true;
6889
e1f99ce6
CW		 6890 /* Block clients from rendering to the new back buffer until
6891 * the flip occurs and the object is no longer visible.
6892 */
05394f39 6893 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6894
8c9f3aaf
JB		 6895 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6896 if (ret)
6897 goto cleanup_pending;
6b95a207 6898
7782de3b 6899 intel_disable_fbc(dev);
6b95a207
KH		 6900 mutex_unlock(&dev->struct_mutex);
6901
e5510fac
JB		 6902 trace_i915_flip_request(intel_crtc->plane, obj);
6903
6b95a207 6904 return 0;
96b099fd 6905
8c9f3aaf
JB		 6906cleanup_pending:
6907 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 6908cleanup_objs:
05394f39
CW		 6909 drm_gem_object_unreference(&work->old_fb_obj->base);
6910 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6911 mutex_unlock(&dev->struct_mutex);
6912
6913 spin_lock_irqsave(&dev->event_lock, flags);
6914 intel_crtc->unpin_work = NULL;
6915 spin_unlock_irqrestore(&dev->event_lock, flags);
6916
6917 kfree(work);
6918
6919 return ret;
6b95a207
KH		 6920}
6921
47f1c6c9
CW		 6922static void intel_sanitize_modesetting(struct drm_device *dev,
6923 int pipe, int plane)
6924{
6925 struct drm_i915_private *dev_priv = dev->dev_private;
6926 u32 reg, val;
6927
6928 if (HAS_PCH_SPLIT(dev))
6929 return;
6930
6931 /* Who knows what state these registers were left in by the BIOS or
6932 * grub?
6933 *
6934 * If we leave the registers in a conflicting state (e.g. with the
6935 * display plane reading from the other pipe than the one we intend
6936 * to use) then when we attempt to teardown the active mode, we will
6937 * not disable the pipes and planes in the correct order -- leaving
6938 * a plane reading from a disabled pipe and possibly leading to
6939 * undefined behaviour.
6940 */
6941
6942 reg = DSPCNTR(plane);
6943 val = I915_READ(reg);
6944
6945 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6946 return;
6947 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6948 return;
6949
6950 /* This display plane is active and attached to the other CPU pipe. */
6951 pipe = !pipe;
6952
6953 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6954 intel_disable_plane(dev_priv, plane, pipe);
6955 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6956}
79e53945 6957
f6e5b160
CW		 6958static void intel_crtc_reset(struct drm_crtc *crtc)
6959{
6960 struct drm_device *dev = crtc->dev;
6961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6962
6963 /* Reset flags back to the 'unknown' status so that they
6964 * will be correctly set on the initial modeset.
6965 */
6966 intel_crtc->dpms_mode = -1;
6967
6968 /* We need to fix up any BIOS configuration that conflicts with
6969 * our expectations.
6970 */
6971 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6972}
6973
6974static struct drm_crtc_helper_funcs intel_helper_funcs = {
6975 .dpms = intel_crtc_dpms,
6976 .mode_fixup = intel_crtc_mode_fixup,
6977 .mode_set = intel_crtc_mode_set,
6978 .mode_set_base = intel_pipe_set_base,
6979 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6980 .load_lut = intel_crtc_load_lut,
6981 .disable = intel_crtc_disable,
6982};
6983
6984static const struct drm_crtc_funcs intel_crtc_funcs = {
6985 .reset = intel_crtc_reset,
6986 .cursor_set = intel_crtc_cursor_set,
6987 .cursor_move = intel_crtc_cursor_move,
6988 .gamma_set = intel_crtc_gamma_set,
6989 .set_config = drm_crtc_helper_set_config,
6990 .destroy = intel_crtc_destroy,
6991 .page_flip = intel_crtc_page_flip,
6992};
6993
b358d0a6 6994static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6995{
22fd0fab 6996 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6997 struct intel_crtc *intel_crtc;
6998 int i;
6999
7000 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7001 if (intel_crtc == NULL)
7002 return;
7003
7004 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7005
7006 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7007 for (i = 0; i < 256; i++) {
7008 intel_crtc->lut_r[i] = i;
7009 intel_crtc->lut_g[i] = i;
7010 intel_crtc->lut_b[i] = i;
7011 }
7012
80824003
JB		 7013 /* Swap pipes & planes for FBC on pre-965 */
7014 intel_crtc->pipe = pipe;
7015 intel_crtc->plane = pipe;
e2e767ab 7016 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7017 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7018 intel_crtc->plane = !pipe;
80824003
JB		 7019 }
7020
22fd0fab
JB		 7021 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7022 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7023 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7024 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7025
5d1d0cc8 7026 intel_crtc_reset(&intel_crtc->base);
04dbff52 7027 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7028 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7029
7030 if (HAS_PCH_SPLIT(dev)) {
7031 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7032 intel_helper_funcs.commit = ironlake_crtc_commit;
7033 } else {
7034 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7035 intel_helper_funcs.commit = i9xx_crtc_commit;
7036 }
7037
79e53945
JB		 7038 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7039
652c393a
JB		 7040 intel_crtc->busy = false;
7041
7042 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7043 (unsigned long)intel_crtc);
79e53945
JB		 7044}
7045
08d7b3d1 7046int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7047 struct drm_file *file)
08d7b3d1
CW		 7048{
7049 drm_i915_private_t *dev_priv = dev->dev_private;
7050 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7051 struct drm_mode_object *drmmode_obj;
7052 struct intel_crtc *crtc;
08d7b3d1
CW		 7053
7054 if (!dev_priv) {
7055 DRM_ERROR("called with no initialization\n");
7056 return -EINVAL;
7057 }
7058
c05422d5
DV		 7059 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7060 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7061
c05422d5 7062 if (!drmmode_obj) {
08d7b3d1
CW		 7063 DRM_ERROR("no such CRTC id\n");
7064 return -EINVAL;
7065 }
7066
c05422d5
DV		 7067 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7068 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7069
c05422d5 7070 return 0;
08d7b3d1
CW		 7071}
7072
c5e4df33 7073static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7074{
4ef69c7a 7075 struct intel_encoder *encoder;
79e53945 7076 int index_mask = 0;
79e53945
JB		 7077 int entry = 0;
7078
4ef69c7a
CW		 7079 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7080 if (type_mask & encoder->clone_mask)
79e53945
JB		 7081 index_mask |= (1 << entry);
7082 entry++;
7083 }
4ef69c7a 7084
79e53945
JB		 7085 return index_mask;
7086}
7087
4d302442
CW		 7088static bool has_edp_a(struct drm_device *dev)
7089{
7090 struct drm_i915_private *dev_priv = dev->dev_private;
7091
7092 if (!IS_MOBILE(dev))
7093 return false;
7094
7095 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7096 return false;
7097
7098 if (IS_GEN5(dev) &&
7099 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7100 return false;
7101
7102 return true;
7103}
7104
79e53945
JB		 7105static void intel_setup_outputs(struct drm_device *dev)
7106{
725e30ad 7107 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7108 struct intel_encoder *encoder;
cb0953d7 7109 bool dpd_is_edp = false;
c5d1b51d 7110 bool has_lvds = false;
79e53945 7111
541998a1 7112 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 7113 has_lvds = intel_lvds_init(dev);
7114 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7115 /* disable the panel fitter on everything but LVDS */
7116 I915_WRITE(PFIT_CONTROL, 0);
7117 }
79e53945 7118
bad720ff 7119 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7120 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7121
4d302442 7122 if (has_edp_a(dev))
32f9d658
ZW		 7123 intel_dp_init(dev, DP_A);
7124
cb0953d7
AJ		 7125 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7126 intel_dp_init(dev, PCH_DP_D);
7127 }
7128
7129 intel_crt_init(dev);
7130
7131 if (HAS_PCH_SPLIT(dev)) {
7132 int found;
7133
30ad48b7 7134 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7135 /* PCH SDVOB multiplex with HDMIB */
7136 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7137 if (!found)
7138 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7139 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7140 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7141 }
7142
7143 if (I915_READ(HDMIC) & PORT_DETECTED)
7144 intel_hdmi_init(dev, HDMIC);
7145
7146 if (I915_READ(HDMID) & PORT_DETECTED)
7147 intel_hdmi_init(dev, HDMID);
7148
5eb08b69
ZW		 7149 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7150 intel_dp_init(dev, PCH_DP_C);
7151
cb0953d7 7152 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7153 intel_dp_init(dev, PCH_DP_D);
7154
103a196f 7155 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7156 bool found = false;
7d57382e 7157
725e30ad 7158 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7159 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7160 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7161 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7162 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7163 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7164 }
27185ae1 7165
b01f2c3a
JB		 7166 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7167 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7168 intel_dp_init(dev, DP_B);
b01f2c3a 7169 }
725e30ad 7170 }
13520b05
KH		 7171
7172 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7173
b01f2c3a
JB		 7174 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7175 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7176 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7177 }
27185ae1
ML		 7178
7179 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7180
b01f2c3a
JB		 7181 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7182 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7183 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7184 }
7185 if (SUPPORTS_INTEGRATED_DP(dev)) {
7186 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7187 intel_dp_init(dev, DP_C);
b01f2c3a 7188 }
725e30ad 7189 }
27185ae1 7190
b01f2c3a
JB		 7191 if (SUPPORTS_INTEGRATED_DP(dev) &&
7192 (I915_READ(DP_D) & DP_DETECTED)) {
7193 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7194 intel_dp_init(dev, DP_D);
b01f2c3a 7195 }
bad720ff 7196 } else if (IS_GEN2(dev))
79e53945
JB		 7197 intel_dvo_init(dev);
7198
103a196f 7199 if (SUPPORTS_TV(dev))
79e53945
JB		 7200 intel_tv_init(dev);
7201
4ef69c7a
CW		 7202 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7203 encoder->base.possible_crtcs = encoder->crtc_mask;
7204 encoder->base.possible_clones =
7205 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7206 }
47356eb6
CW		 7207
7208 intel_panel_setup_backlight(dev);
2c7111db
CW		 7209
7210 /* disable all the possible outputs/crtcs before entering KMS mode */
7211 drm_helper_disable_unused_functions(dev);
79e53945
JB		 7212}
7213
7214static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7215{
7216 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7217
7218 drm_framebuffer_cleanup(fb);
05394f39 7219 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7220
7221 kfree(intel_fb);
7222}
7223
7224static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7225 struct drm_file *file,
79e53945
JB		 7226 unsigned int *handle)
7227{
7228 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7229 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7230
05394f39 7231 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7232}
7233
7234static const struct drm_framebuffer_funcs intel_fb_funcs = {
7235 .destroy = intel_user_framebuffer_destroy,
7236 .create_handle = intel_user_framebuffer_create_handle,
7237};
7238
38651674
DA		 7239int intel_framebuffer_init(struct drm_device *dev,
7240 struct intel_framebuffer *intel_fb,
7241 struct drm_mode_fb_cmd *mode_cmd,
05394f39 7242 struct drm_i915_gem_object *obj)
79e53945 7243{
79e53945
JB		 7244 int ret;
7245
05394f39 7246 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7247 return -EINVAL;
7248
7249 if (mode_cmd->pitch & 63)
7250 return -EINVAL;
7251
7252 switch (mode_cmd->bpp) {
7253 case 8:
7254 case 16:
b5626747
JB		 7255 /* Only pre-ILK can handle 5:5:5 */
7256 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7257 return -EINVAL;
7258 break;
7259
57cd6508
CW		 7260 case 24:
7261 case 32:
7262 break;
7263 default:
7264 return -EINVAL;
7265 }
7266
79e53945
JB		 7267 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7268 if (ret) {
7269 DRM_ERROR("framebuffer init failed %d\n", ret);
7270 return ret;
7271 }
7272
7273 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7274 intel_fb->obj = obj;
79e53945
JB		 7275 return 0;
7276}
7277
79e53945
JB		 7278static struct drm_framebuffer *
7279intel_user_framebuffer_create(struct drm_device *dev,
7280 struct drm_file *filp,
7281 struct drm_mode_fb_cmd *mode_cmd)
7282{
05394f39 7283 struct drm_i915_gem_object *obj;
79e53945 7284
05394f39 7285 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 7286 if (&obj->base == NULL)
cce13ff7 7287 return ERR_PTR(-ENOENT);
79e53945 7288
d2dff872 7289 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7290}
7291
79e53945 7292static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7293 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7294 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7295};
7296
05394f39 7297static struct drm_i915_gem_object *
aa40d6bb 7298intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7299{
05394f39 7300 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7301 int ret;
7302
2c34b850
BW		 7303 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7304
aa40d6bb
ZN		 7305 ctx = i915_gem_alloc_object(dev, 4096);
7306 if (!ctx) {
9ea8d059
CW		 7307 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7308 return NULL;
7309 }
7310
75e9e915 7311 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7312 if (ret) {
7313 DRM_ERROR("failed to pin power context: %d\n", ret);
7314 goto err_unref;
7315 }
7316
aa40d6bb 7317 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7318 if (ret) {
7319 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7320 goto err_unpin;
7321 }
9ea8d059 7322
aa40d6bb 7323 return ctx;
9ea8d059
CW		 7324
7325err_unpin:
aa40d6bb 7326 i915_gem_object_unpin(ctx);
9ea8d059 7327err_unref:
05394f39 7328 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7329 mutex_unlock(&dev->struct_mutex);
7330 return NULL;
7331}
7332
7648fa99
JB		 7333bool ironlake_set_drps(struct drm_device *dev, u8 val)
7334{
7335 struct drm_i915_private *dev_priv = dev->dev_private;
7336 u16 rgvswctl;
7337
7338 rgvswctl = I915_READ16(MEMSWCTL);
7339 if (rgvswctl & MEMCTL_CMD_STS) {
7340 DRM_DEBUG("gpu busy, RCS change rejected\n");
7341 return false; /* still busy with another command */
7342 }
7343
7344 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7345 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7346 I915_WRITE16(MEMSWCTL, rgvswctl);
7347 POSTING_READ16(MEMSWCTL);
7348
7349 rgvswctl |= MEMCTL_CMD_STS;
7350 I915_WRITE16(MEMSWCTL, rgvswctl);
7351
7352 return true;
7353}
7354
f97108d1
JB		 7355void ironlake_enable_drps(struct drm_device *dev)
7356{
7357 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7358 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7359 u8 fmax, fmin, fstart, vstart;
f97108d1 7360
ea056c14
JB		 7361 /* Enable temp reporting */
7362 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7363 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7364
f97108d1
JB		 7365 /* 100ms RC evaluation intervals */
7366 I915_WRITE(RCUPEI, 100000);
7367 I915_WRITE(RCDNEI, 100000);
7368
7369 /* Set max/min thresholds to 90ms and 80ms respectively */
7370 I915_WRITE(RCBMAXAVG, 90000);
7371 I915_WRITE(RCBMINAVG, 80000);
7372
7373 I915_WRITE(MEMIHYST, 1);
7374
7375 /* Set up min, max, and cur for interrupt handling */
7376 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7377 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7378 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7379 MEMMODE_FSTART_SHIFT;
7648fa99 7380
f97108d1
JB		 7381 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7382 PXVFREQ_PX_SHIFT;
7383
80dbf4b7 7384 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7385 dev_priv->fstart = fstart;
7386
80dbf4b7 7387 dev_priv->max_delay = fstart;
f97108d1
JB		 7388 dev_priv->min_delay = fmin;
7389 dev_priv->cur_delay = fstart;
7390
80dbf4b7
JB		 7391 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7392 fmax, fmin, fstart);
7648fa99 7393
f97108d1
JB		 7394 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7395
7396 /*
7397 * Interrupts will be enabled in ironlake_irq_postinstall
7398 */
7399
7400 I915_WRITE(VIDSTART, vstart);
7401 POSTING_READ(VIDSTART);
7402
7403 rgvmodectl |= MEMMODE_SWMODE_EN;
7404 I915_WRITE(MEMMODECTL, rgvmodectl);
7405
481b6af3 7406 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7407 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7408 msleep(1);
7409
7648fa99 7410 ironlake_set_drps(dev, fstart);
f97108d1 7411
7648fa99
JB		 7412 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7413 I915_READ(0x112e0);
7414 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7415 dev_priv->last_count2 = I915_READ(0x112f4);
7416 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7417}
7418
7419void ironlake_disable_drps(struct drm_device *dev)
7420{
7421 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7422 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7423
7424 /* Ack interrupts, disable EFC interrupt */
7425 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7426 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7427 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7428 I915_WRITE(DEIIR, DE_PCU_EVENT);
7429 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7430
7431 /* Go back to the starting frequency */
7648fa99 7432 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7433 msleep(1);
7434 rgvswctl |= MEMCTL_CMD_STS;
7435 I915_WRITE(MEMSWCTL, rgvswctl);
7436 msleep(1);
7437
7438}
7439
3b8d8d91
JB		 7440void gen6_set_rps(struct drm_device *dev, u8 val)
7441{
7442 struct drm_i915_private *dev_priv = dev->dev_private;
7443 u32 swreq;
7444
7445 swreq = (val & 0x3ff) << 25;
7446 I915_WRITE(GEN6_RPNSWREQ, swreq);
7447}
7448
7449void gen6_disable_rps(struct drm_device *dev)
7450{
7451 struct drm_i915_private *dev_priv = dev->dev_private;
7452
7453 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7454 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7455 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 7456
7457 spin_lock_irq(&dev_priv->rps_lock);
7458 dev_priv->pm_iir = 0;
7459 spin_unlock_irq(&dev_priv->rps_lock);
7460
3b8d8d91
JB		 7461 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7462}
7463
7648fa99
JB		 7464static unsigned long intel_pxfreq(u32 vidfreq)
7465{
7466 unsigned long freq;
7467 int div = (vidfreq & 0x3f0000) >> 16;
7468 int post = (vidfreq & 0x3000) >> 12;
7469 int pre = (vidfreq & 0x7);
7470
7471 if (!pre)
7472 return 0;
7473
7474 freq = ((div * 133333) / ((1<<post) * pre));
7475
7476 return freq;
7477}
7478
7479void intel_init_emon(struct drm_device *dev)
7480{
7481 struct drm_i915_private *dev_priv = dev->dev_private;
7482 u32 lcfuse;
7483 u8 pxw[16];
7484 int i;
7485
7486 /* Disable to program */
7487 I915_WRITE(ECR, 0);
7488 POSTING_READ(ECR);
7489
7490 /* Program energy weights for various events */
7491 I915_WRITE(SDEW, 0x15040d00);
7492 I915_WRITE(CSIEW0, 0x007f0000);
7493 I915_WRITE(CSIEW1, 0x1e220004);
7494 I915_WRITE(CSIEW2, 0x04000004);
7495
7496 for (i = 0; i < 5; i++)
7497 I915_WRITE(PEW + (i * 4), 0);
7498 for (i = 0; i < 3; i++)
7499 I915_WRITE(DEW + (i * 4), 0);
7500
7501 /* Program P-state weights to account for frequency power adjustment */
7502 for (i = 0; i < 16; i++) {
7503 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7504 unsigned long freq = intel_pxfreq(pxvidfreq);
7505 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7506 PXVFREQ_PX_SHIFT;
7507 unsigned long val;
7508
7509 val = vid * vid;
7510 val *= (freq / 1000);
7511 val *= 255;
7512 val /= (127*127*900);
7513 if (val > 0xff)
7514 DRM_ERROR("bad pxval: %ld\n", val);
7515 pxw[i] = val;
7516 }
7517 /* Render standby states get 0 weight */
7518 pxw[14] = 0;
7519 pxw[15] = 0;
7520
7521 for (i = 0; i < 4; i++) {
7522 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7523 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7524 I915_WRITE(PXW + (i * 4), val);
7525 }
7526
7527 /* Adjust magic regs to magic values (more experimental results) */
7528 I915_WRITE(OGW0, 0);
7529 I915_WRITE(OGW1, 0);
7530 I915_WRITE(EG0, 0x00007f00);
7531 I915_WRITE(EG1, 0x0000000e);
7532 I915_WRITE(EG2, 0x000e0000);
7533 I915_WRITE(EG3, 0x68000300);
7534 I915_WRITE(EG4, 0x42000000);
7535 I915_WRITE(EG5, 0x00140031);
7536 I915_WRITE(EG6, 0);
7537 I915_WRITE(EG7, 0);
7538
7539 for (i = 0; i < 8; i++)
7540 I915_WRITE(PXWL + (i * 4), 0);
7541
7542 /* Enable PMON + select events */
7543 I915_WRITE(ECR, 0x80000019);
7544
7545 lcfuse = I915_READ(LCFUSE02);
7546
7547 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7548}
7549
3b8d8d91 7550void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7551{
a6044e23
JB		 7552 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7553 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7554 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7555 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7556 int i;
7557
7558 /* Here begins a magic sequence of register writes to enable
7559 * auto-downclocking.
7560 *
7561 * Perhaps there might be some value in exposing these to
7562 * userspace...
7563 */
7564 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7565 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7566 gen6_gt_force_wake_get(dev_priv);
8fd26859 7567
3b8d8d91 7568 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7569 I915_WRITE(GEN6_RC_CONTROL, 0);
7570
7571 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7572 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7573 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7574 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7575 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7576
7577 for (i = 0; i < I915_NUM_RINGS; i++)
7578 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7579
7580 I915_WRITE(GEN6_RC_SLEEP, 0);
7581 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7582 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7583 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7584 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7585
7df8721b
JB		 7586 if (i915_enable_rc6)
7587 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7588 GEN6_RC_CTL_RC6_ENABLE;
7589
8fd26859 7590 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7591 rc6_mask |
9c3d2f7f 7592 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7593 GEN6_RC_CTL_HW_ENABLE);
7594
3b8d8d91 7595 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7596 GEN6_FREQUENCY(10) |
7597 GEN6_OFFSET(0) |
7598 GEN6_AGGRESSIVE_TURBO);
7599 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7600 GEN6_FREQUENCY(12));
7601
7602 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7603 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7604 18 << 24 |
7605 6 << 16);
ccab5c82
JB		 7606 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7607 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7608 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7609 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7610 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7611 I915_WRITE(GEN6_RP_CONTROL,
7612 GEN6_RP_MEDIA_TURBO |
7613 GEN6_RP_USE_NORMAL_FREQ |
7614 GEN6_RP_MEDIA_IS_GFX |
7615 GEN6_RP_ENABLE |
ccab5c82
JB		 7616 GEN6_RP_UP_BUSY_AVG |
7617 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7618
7619 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7620 500))
7621 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7622
7623 I915_WRITE(GEN6_PCODE_DATA, 0);
7624 I915_WRITE(GEN6_PCODE_MAILBOX,
7625 GEN6_PCODE_READY |
7626 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7627 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7628 500))
7629 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7630
a6044e23
JB		 7631 min_freq = (rp_state_cap & 0xff0000) >> 16;
7632 max_freq = rp_state_cap & 0xff;
7633 cur_freq = (gt_perf_status & 0xff00) >> 8;
7634
7635 /* Check for overclock support */
7636 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7637 500))
7638 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7639 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7640 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7641 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7642 500))
7643 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7644 if (pcu_mbox & (1<<31)) { /* OC supported */
7645 max_freq = pcu_mbox & 0xff;
e281fcaa 7646 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7647 }
7648
7649 /* In units of 100MHz */
7650 dev_priv->max_delay = max_freq;
7651 dev_priv->min_delay = min_freq;
7652 dev_priv->cur_delay = cur_freq;
7653
8fd26859
CW		 7654 /* requires MSI enabled */
7655 I915_WRITE(GEN6_PMIER,
7656 GEN6_PM_MBOX_EVENT |
7657 GEN6_PM_THERMAL_EVENT |
7658 GEN6_PM_RP_DOWN_TIMEOUT |
7659 GEN6_PM_RP_UP_THRESHOLD |
7660 GEN6_PM_RP_DOWN_THRESHOLD |
7661 GEN6_PM_RP_UP_EI_EXPIRED |
7662 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7663 spin_lock_irq(&dev_priv->rps_lock);
7664 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7665 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7666 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7667 /* enable all PM interrupts */
7668 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7669
fcca7926 7670 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7671 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7672}
7673
23b2f8bb
JB		 7674void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7675{
7676 int min_freq = 15;
7677 int gpu_freq, ia_freq, max_ia_freq;
7678 int scaling_factor = 180;
7679
7680 max_ia_freq = cpufreq_quick_get_max(0);
7681 /*
7682 * Default to measured freq if none found, PCU will ensure we don't go
7683 * over
7684 */
7685 if (!max_ia_freq)
7686 max_ia_freq = tsc_khz;
7687
7688 /* Convert from kHz to MHz */
7689 max_ia_freq /= 1000;
7690
7691 mutex_lock(&dev_priv->dev->struct_mutex);
7692
7693 /*
7694 * For each potential GPU frequency, load a ring frequency we'd like
7695 * to use for memory access. We do this by specifying the IA frequency
7696 * the PCU should use as a reference to determine the ring frequency.
7697 */
7698 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7699 gpu_freq--) {
7700 int diff = dev_priv->max_delay - gpu_freq;
7701
7702 /*
7703 * For GPU frequencies less than 750MHz, just use the lowest
7704 * ring freq.
7705 */
7706 if (gpu_freq < min_freq)
7707 ia_freq = 800;
7708 else
7709 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7710 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7711
7712 I915_WRITE(GEN6_PCODE_DATA,
7713 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7714 gpu_freq);
7715 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7716 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7717 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7718 GEN6_PCODE_READY) == 0, 10)) {
7719 DRM_ERROR("pcode write of freq table timed out\n");
7720 continue;
7721 }
7722 }
7723
7724 mutex_unlock(&dev_priv->dev->struct_mutex);
7725}
7726
6067aaea
JB		 7727static void ironlake_init_clock_gating(struct drm_device *dev)
7728{
7729 struct drm_i915_private *dev_priv = dev->dev_private;
7730 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7731
7732 /* Required for FBC */
7733 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7734 DPFCRUNIT_CLOCK_GATE_DISABLE |
7735 DPFDUNIT_CLOCK_GATE_DISABLE;
7736 /* Required for CxSR */
7737 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7738
7739 I915_WRITE(PCH_3DCGDIS0,
7740 MARIUNIT_CLOCK_GATE_DISABLE |
7741 SVSMUNIT_CLOCK_GATE_DISABLE);
7742 I915_WRITE(PCH_3DCGDIS1,
7743 VFMUNIT_CLOCK_GATE_DISABLE);
7744
7745 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7746
6067aaea
JB		 7747 /*
7748 * According to the spec the following bits should be set in
7749 * order to enable memory self-refresh
7750 * The bit 22/21 of 0x42004
7751 * The bit 5 of 0x42020
7752 * The bit 15 of 0x45000
7753 */
7754 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7755 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7756 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7757 I915_WRITE(ILK_DSPCLK_GATE,
7758 (I915_READ(ILK_DSPCLK_GATE) |
7759 ILK_DPARB_CLK_GATE));
7760 I915_WRITE(DISP_ARB_CTL,
7761 (I915_READ(DISP_ARB_CTL) |
7762 DISP_FBC_WM_DIS));
7763 I915_WRITE(WM3_LP_ILK, 0);
7764 I915_WRITE(WM2_LP_ILK, 0);
7765 I915_WRITE(WM1_LP_ILK, 0);
7766
7767 /*
7768 * Based on the document from hardware guys the following bits
7769 * should be set unconditionally in order to enable FBC.
7770 * The bit 22 of 0x42000
7771 * The bit 22 of 0x42004
7772 * The bit 7,8,9 of 0x42020.
7773 */
7774 if (IS_IRONLAKE_M(dev)) {
7775 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7776 I915_READ(ILK_DISPLAY_CHICKEN1) |
7777 ILK_FBCQ_DIS);
7778 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7779 I915_READ(ILK_DISPLAY_CHICKEN2) |
7780 ILK_DPARB_GATE);
7781 I915_WRITE(ILK_DSPCLK_GATE,
7782 I915_READ(ILK_DSPCLK_GATE) |
7783 ILK_DPFC_DIS1 |
7784 ILK_DPFC_DIS2 |
7785 ILK_CLK_FBC);
7786 }
7787
7788 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7789 I915_READ(ILK_DISPLAY_CHICKEN2) |
7790 ILK_ELPIN_409_SELECT);
7791 I915_WRITE(_3D_CHICKEN2,
7792 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7793 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 7794}
7795
6067aaea 7796static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 7797{
7798 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7799 int pipe;
6067aaea
JB		 7800 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7801
7802 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 7803
6067aaea
JB		 7804 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7805 I915_READ(ILK_DISPLAY_CHICKEN2) |
7806 ILK_ELPIN_409_SELECT);
8956c8bb 7807
6067aaea
JB		 7808 I915_WRITE(WM3_LP_ILK, 0);
7809 I915_WRITE(WM2_LP_ILK, 0);
7810 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 7811
7812 /*
6067aaea
JB		 7813 * According to the spec the following bits should be
7814 * set in order to enable memory self-refresh and fbc:
7815 * The bit21 and bit22 of 0x42000
7816 * The bit21 and bit22 of 0x42004
7817 * The bit5 and bit7 of 0x42020
7818 * The bit14 of 0x70180
7819 * The bit14 of 0x71180
652c393a 7820 */
6067aaea
JB		 7821 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7822 I915_READ(ILK_DISPLAY_CHICKEN1) |
7823 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7824 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7825 I915_READ(ILK_DISPLAY_CHICKEN2) |
7826 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7827 I915_WRITE(ILK_DSPCLK_GATE,
7828 I915_READ(ILK_DSPCLK_GATE) |
7829 ILK_DPARB_CLK_GATE |
7830 ILK_DPFD_CLK_GATE);
8956c8bb 7831
d74362c9 7832 for_each_pipe(pipe) {
6067aaea
JB		 7833 I915_WRITE(DSPCNTR(pipe),
7834 I915_READ(DSPCNTR(pipe)) |
7835 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 7836 intel_flush_display_plane(dev_priv, pipe);
7837 }
6067aaea 7838}
8956c8bb 7839
28963a3e
JB		 7840static void ivybridge_init_clock_gating(struct drm_device *dev)
7841{
7842 struct drm_i915_private *dev_priv = dev->dev_private;
7843 int pipe;
7844 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 7845
28963a3e 7846 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 7847
28963a3e
JB		 7848 I915_WRITE(WM3_LP_ILK, 0);
7849 I915_WRITE(WM2_LP_ILK, 0);
7850 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 7851
28963a3e 7852 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 7853
d74362c9 7854 for_each_pipe(pipe) {
28963a3e
JB		 7855 I915_WRITE(DSPCNTR(pipe),
7856 I915_READ(DSPCNTR(pipe)) |
7857 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 7858 intel_flush_display_plane(dev_priv, pipe);
7859 }
28963a3e
JB		 7860}
7861
6067aaea
JB		 7862static void g4x_init_clock_gating(struct drm_device *dev)
7863{
7864 struct drm_i915_private *dev_priv = dev->dev_private;
7865 uint32_t dspclk_gate;
8fd26859 7866
6067aaea
JB		 7867 I915_WRITE(RENCLK_GATE_D1, 0);
7868 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7869 GS_UNIT_CLOCK_GATE_DISABLE |
7870 CL_UNIT_CLOCK_GATE_DISABLE);
7871 I915_WRITE(RAMCLK_GATE_D, 0);
7872 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7873 OVRUNIT_CLOCK_GATE_DISABLE |
7874 OVCUNIT_CLOCK_GATE_DISABLE;
7875 if (IS_GM45(dev))
7876 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7877 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7878}
1398261a 7879
6067aaea
JB		 7880static void crestline_init_clock_gating(struct drm_device *dev)
7881{
7882 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7883
6067aaea
JB		 7884 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7885 I915_WRITE(RENCLK_GATE_D2, 0);
7886 I915_WRITE(DSPCLK_GATE_D, 0);
7887 I915_WRITE(RAMCLK_GATE_D, 0);
7888 I915_WRITE16(DEUC, 0);
7889}
652c393a 7890
6067aaea
JB		 7891static void broadwater_init_clock_gating(struct drm_device *dev)
7892{
7893 struct drm_i915_private *dev_priv = dev->dev_private;
7894
7895 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7896 I965_RCC_CLOCK_GATE_DISABLE |
7897 I965_RCPB_CLOCK_GATE_DISABLE |
7898 I965_ISC_CLOCK_GATE_DISABLE |
7899 I965_FBC_CLOCK_GATE_DISABLE);
7900 I915_WRITE(RENCLK_GATE_D2, 0);
7901}
7902
7903static void gen3_init_clock_gating(struct drm_device *dev)
7904{
7905 struct drm_i915_private *dev_priv = dev->dev_private;
7906 u32 dstate = I915_READ(D_STATE);
7907
7908 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7909 DSTATE_DOT_CLOCK_GATING;
7910 I915_WRITE(D_STATE, dstate);
7911}
7912
7913static void i85x_init_clock_gating(struct drm_device *dev)
7914{
7915 struct drm_i915_private *dev_priv = dev->dev_private;
7916
7917 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7918}
7919
7920static void i830_init_clock_gating(struct drm_device *dev)
7921{
7922 struct drm_i915_private *dev_priv = dev->dev_private;
7923
7924 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 7925}
7926
645c62a5
JB		 7927static void ibx_init_clock_gating(struct drm_device *dev)
7928{
7929 struct drm_i915_private *dev_priv = dev->dev_private;
7930
7931 /*
7932 * On Ibex Peak and Cougar Point, we need to disable clock
7933 * gating for the panel power sequencer or it will fail to
7934 * start up when no ports are active.
7935 */
7936 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7937}
7938
7939static void cpt_init_clock_gating(struct drm_device *dev)
7940{
7941 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 7942 int pipe;
645c62a5
JB		 7943
7944 /*
7945 * On Ibex Peak and Cougar Point, we need to disable clock
7946 * gating for the panel power sequencer or it will fail to
7947 * start up when no ports are active.
7948 */
7949 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7950 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7951 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 7952 /* Without this, mode sets may fail silently on FDI */
7953 for_each_pipe(pipe)
7954 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 7955}
7956
ac668088 7957static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7958{
7959 struct drm_i915_private *dev_priv = dev->dev_private;
7960
7961 if (dev_priv->renderctx) {
ac668088
CW		 7962 i915_gem_object_unpin(dev_priv->renderctx);
7963 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7964 dev_priv->renderctx = NULL;
7965 }
7966
7967 if (dev_priv->pwrctx) {
ac668088
CW		 7968 i915_gem_object_unpin(dev_priv->pwrctx);
7969 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7970 dev_priv->pwrctx = NULL;
7971 }
7972}
7973
7974static void ironlake_disable_rc6(struct drm_device *dev)
7975{
7976 struct drm_i915_private *dev_priv = dev->dev_private;
7977
7978 if (I915_READ(PWRCTXA)) {
7979 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7980 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7981 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7982 50);
0cdab21f
CW		 7983
7984 I915_WRITE(PWRCTXA, 0);
7985 POSTING_READ(PWRCTXA);
7986
ac668088
CW		 7987 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7988 POSTING_READ(RSTDBYCTL);
0cdab21f 7989 }
ac668088 7990
99507307 7991 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7992}
7993
ac668088 7994static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7995{
7996 struct drm_i915_private *dev_priv = dev->dev_private;
7997
ac668088
CW		 7998 if (dev_priv->renderctx == NULL)
7999 dev_priv->renderctx = intel_alloc_context_page(dev);
8000 if (!dev_priv->renderctx)
8001 return -ENOMEM;
8002
8003 if (dev_priv->pwrctx == NULL)
8004 dev_priv->pwrctx = intel_alloc_context_page(dev);
8005 if (!dev_priv->pwrctx) {
8006 ironlake_teardown_rc6(dev);
8007 return -ENOMEM;
8008 }
8009
8010 return 0;
d5bb081b
JB		 8011}
8012
8013void ironlake_enable_rc6(struct drm_device *dev)
8014{
8015 struct drm_i915_private *dev_priv = dev->dev_private;
8016 int ret;
8017
ac668088
CW		 8018 /* rc6 disabled by default due to repeated reports of hanging during
8019 * boot and resume.
8020 */
8021 if (!i915_enable_rc6)
8022 return;
8023
2c34b850 8024 mutex_lock(&dev->struct_mutex);
ac668088 8025 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8026 if (ret) {
8027 mutex_unlock(&dev->struct_mutex);
ac668088 8028 return;
2c34b850 8029 }
ac668088 8030
d5bb081b
JB		 8031 /*
8032 * GPU can automatically power down the render unit if given a page
8033 * to save state.
8034 */
8035 ret = BEGIN_LP_RING(6);
8036 if (ret) {
ac668088 8037 ironlake_teardown_rc6(dev);
2c34b850 8038 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8039 return;
8040 }
ac668088 8041
d5bb081b
JB		 8042 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8043 OUT_RING(MI_SET_CONTEXT);
8044 OUT_RING(dev_priv->renderctx->gtt_offset |
8045 MI_MM_SPACE_GTT |
8046 MI_SAVE_EXT_STATE_EN |
8047 MI_RESTORE_EXT_STATE_EN |
8048 MI_RESTORE_INHIBIT);
8049 OUT_RING(MI_SUSPEND_FLUSH);
8050 OUT_RING(MI_NOOP);
8051 OUT_RING(MI_FLUSH);
8052 ADVANCE_LP_RING();
8053
4a246cfc
BW		 8054 /*
8055 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8056 * does an implicit flush, combined with MI_FLUSH above, it should be
8057 * safe to assume that renderctx is valid
8058 */
8059 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8060 if (ret) {
8061 DRM_ERROR("failed to enable ironlake power power savings\n");
8062 ironlake_teardown_rc6(dev);
8063 mutex_unlock(&dev->struct_mutex);
8064 return;
8065 }
8066
d5bb081b
JB		 8067 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8068 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8069 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8070}
8071
645c62a5
JB		 8072void intel_init_clock_gating(struct drm_device *dev)
8073{
8074 struct drm_i915_private *dev_priv = dev->dev_private;
8075
8076 dev_priv->display.init_clock_gating(dev);
8077
8078 if (dev_priv->display.init_pch_clock_gating)
8079 dev_priv->display.init_pch_clock_gating(dev);
8080}
ac668088 8081
e70236a8
JB		 8082/* Set up chip specific display functions */
8083static void intel_init_display(struct drm_device *dev)
8084{
8085 struct drm_i915_private *dev_priv = dev->dev_private;
8086
8087 /* We always want a DPMS function */
f564048e 8088 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8089 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8090 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8091 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8092 } else {
e70236a8 8093 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8094 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8095 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8096 }
e70236a8 8097
ee5382ae 8098 if (I915_HAS_FBC(dev)) {
9c04f015 8099 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8100 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8101 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8102 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8103 } else if (IS_GM45(dev)) {
74dff282
JB		 8104 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8105 dev_priv->display.enable_fbc = g4x_enable_fbc;
8106 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8107 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8108 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8109 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8110 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8111 }
74dff282 8112 /* 855GM needs testing */
e70236a8
JB		 8113 }
8114
8115 /* Returns the core display clock speed */
f2b115e6 8116 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 8117 dev_priv->display.get_display_clock_speed =
8118 i945_get_display_clock_speed;
8119 else if (IS_I915G(dev))
8120 dev_priv->display.get_display_clock_speed =
8121 i915_get_display_clock_speed;
f2b115e6 8122 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8123 dev_priv->display.get_display_clock_speed =
8124 i9xx_misc_get_display_clock_speed;
8125 else if (IS_I915GM(dev))
8126 dev_priv->display.get_display_clock_speed =
8127 i915gm_get_display_clock_speed;
8128 else if (IS_I865G(dev))
8129 dev_priv->display.get_display_clock_speed =
8130 i865_get_display_clock_speed;
f0f8a9ce 8131 else if (IS_I85X(dev))
e70236a8
JB		 8132 dev_priv->display.get_display_clock_speed =
8133 i855_get_display_clock_speed;
8134 else /* 852, 830 */
8135 dev_priv->display.get_display_clock_speed =
8136 i830_get_display_clock_speed;
8137
8138 /* For FIFO watermark updates */
7f8a8569 8139 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 8140 if (HAS_PCH_IBX(dev))
8141 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8142 else if (HAS_PCH_CPT(dev))
8143 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8144
f00a3ddf 8145 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8146 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8147 dev_priv->display.update_wm = ironlake_update_wm;
8148 else {
8149 DRM_DEBUG_KMS("Failed to get proper latency. "
8150 "Disable CxSR\n");
8151 dev_priv->display.update_wm = NULL;
1398261a 8152 }
674cf967 8153 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8154 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
1398261a
YL		 8155 } else if (IS_GEN6(dev)) {
8156 if (SNB_READ_WM0_LATENCY()) {
8157 dev_priv->display.update_wm = sandybridge_update_wm;
8158 } else {
8159 DRM_DEBUG_KMS("Failed to read display plane latency. "
8160 "Disable CxSR\n");
8161 dev_priv->display.update_wm = NULL;
7f8a8569 8162 }
674cf967 8163 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8164 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
357555c0
JB		 8165 } else if (IS_IVYBRIDGE(dev)) {
8166 /* FIXME: detect B0+ stepping and use auto training */
8167 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8168 if (SNB_READ_WM0_LATENCY()) {
8169 dev_priv->display.update_wm = sandybridge_update_wm;
8170 } else {
8171 DRM_DEBUG_KMS("Failed to read display plane latency. "
8172 "Disable CxSR\n");
8173 dev_priv->display.update_wm = NULL;
8174 }
28963a3e 8175 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6067aaea 8176
7f8a8569
ZW		 8177 } else
8178 dev_priv->display.update_wm = NULL;
8179 } else if (IS_PINEVIEW(dev)) {
d4294342 8180 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8181 dev_priv->is_ddr3,
d4294342
ZY		 8182 dev_priv->fsb_freq,
8183 dev_priv->mem_freq)) {
8184 DRM_INFO("failed to find known CxSR latency "
95534263 8185 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8186 "disabling CxSR\n",
95534263 8187 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 8188 dev_priv->fsb_freq, dev_priv->mem_freq);
8189 /* Disable CxSR and never update its watermark again */
8190 pineview_disable_cxsr(dev);
8191 dev_priv->display.update_wm = NULL;
8192 } else
8193 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8194 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8195 } else if (IS_G4X(dev)) {
e70236a8 8196 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8197 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8198 } else if (IS_GEN4(dev)) {
e70236a8 8199 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8200 if (IS_CRESTLINE(dev))
8201 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8202 else if (IS_BROADWATER(dev))
8203 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8204 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8205 dev_priv->display.update_wm = i9xx_update_wm;
8206 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8207 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8208 } else if (IS_I865G(dev)) {
8209 dev_priv->display.update_wm = i830_update_wm;
8210 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8211 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8212 } else if (IS_I85X(dev)) {
8213 dev_priv->display.update_wm = i9xx_update_wm;
8214 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8215 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8216 } else {
8f4695ed 8217 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8218 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8219 if (IS_845G(dev))
e70236a8
JB		 8220 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8221 else
8222 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8223 }
8c9f3aaf
JB		 8224
8225 /* Default just returns -ENODEV to indicate unsupported */
8226 dev_priv->display.queue_flip = intel_default_queue_flip;
8227
8228 switch (INTEL_INFO(dev)->gen) {
8229 case 2:
8230 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8231 break;
8232
8233 case 3:
8234 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8235 break;
8236
8237 case 4:
8238 case 5:
8239 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8240 break;
8241
8242 case 6:
8243 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8244 break;
7c9017e5
JB		 8245 case 7:
8246 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8247 break;
8c9f3aaf 8248 }
e70236a8
JB		 8249}
8250
b690e96c
JB		 8251/*
8252 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8253 * resume, or other times. This quirk makes sure that's the case for
8254 * affected systems.
8255 */
8256static void quirk_pipea_force (struct drm_device *dev)
8257{
8258 struct drm_i915_private *dev_priv = dev->dev_private;
8259
8260 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8261 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8262}
8263
435793df
KP		 8264/*
8265 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8266 */
8267static void quirk_ssc_force_disable(struct drm_device *dev)
8268{
8269 struct drm_i915_private *dev_priv = dev->dev_private;
8270 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8271}
8272
b690e96c
JB		 8273struct intel_quirk {
8274 int device;
8275 int subsystem_vendor;
8276 int subsystem_device;
8277 void (*hook)(struct drm_device *dev);
8278};
8279
8280struct intel_quirk intel_quirks[] = {
8281 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8282 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8283 /* HP Mini needs pipe A force quirk (LP: #322104) */
8284 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
8285
8286 /* Thinkpad R31 needs pipe A force quirk */
8287 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8288 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8289 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8290
8291 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8292 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8293 /* ThinkPad X40 needs pipe A force quirk */
8294
8295 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8296 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8297
8298 /* 855 & before need to leave pipe A & dpll A up */
8299 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8300 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8301
8302 /* Lenovo U160 cannot use SSC on LVDS */
8303 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8304
8305 /* Sony Vaio Y cannot use SSC on LVDS */
8306 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 8307};
8308
8309static void intel_init_quirks(struct drm_device *dev)
8310{
8311 struct pci_dev *d = dev->pdev;
8312 int i;
8313
8314 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8315 struct intel_quirk *q = &intel_quirks[i];
8316
8317 if (d->device == q->device &&
8318 (d->subsystem_vendor == q->subsystem_vendor ||
8319 q->subsystem_vendor == PCI_ANY_ID) &&
8320 (d->subsystem_device == q->subsystem_device ||
8321 q->subsystem_device == PCI_ANY_ID))
8322 q->hook(dev);
8323 }
8324}
8325
9cce37f4
JB		 8326/* Disable the VGA plane that we never use */
8327static void i915_disable_vga(struct drm_device *dev)
8328{
8329 struct drm_i915_private *dev_priv = dev->dev_private;
8330 u8 sr1;
8331 u32 vga_reg;
8332
8333 if (HAS_PCH_SPLIT(dev))
8334 vga_reg = CPU_VGACNTRL;
8335 else
8336 vga_reg = VGACNTRL;
8337
8338 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8339 outb(1, VGA_SR_INDEX);
8340 sr1 = inb(VGA_SR_DATA);
8341 outb(sr1 | 1<<5, VGA_SR_DATA);
8342 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8343 udelay(300);
8344
8345 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8346 POSTING_READ(vga_reg);
8347}
8348
79e53945
JB		 8349void intel_modeset_init(struct drm_device *dev)
8350{
652c393a 8351 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 8352 int i;
8353
8354 drm_mode_config_init(dev);
8355
8356 dev->mode_config.min_width = 0;
8357 dev->mode_config.min_height = 0;
8358
8359 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8360
b690e96c
JB		 8361 intel_init_quirks(dev);
8362
e70236a8
JB		 8363 intel_init_display(dev);
8364
a6c45cf0
CW		 8365 if (IS_GEN2(dev)) {
8366 dev->mode_config.max_width = 2048;
8367 dev->mode_config.max_height = 2048;
8368 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8369 dev->mode_config.max_width = 4096;
8370 dev->mode_config.max_height = 4096;
79e53945 8371 } else {
a6c45cf0
CW		 8372 dev->mode_config.max_width = 8192;
8373 dev->mode_config.max_height = 8192;
79e53945 8374 }
35c3047a 8375 dev->mode_config.fb_base = dev->agp->base;
79e53945 8376
28c97730 8377 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8378 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8379
a3524f1b 8380 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 8381 intel_crtc_init(dev, i);
8382 }
8383
9cce37f4
JB		 8384 /* Just disable it once at startup */
8385 i915_disable_vga(dev);
79e53945 8386 intel_setup_outputs(dev);
652c393a 8387
645c62a5 8388 intel_init_clock_gating(dev);
9cce37f4 8389
7648fa99 8390 if (IS_IRONLAKE_M(dev)) {
f97108d1 8391 ironlake_enable_drps(dev);
7648fa99
JB		 8392 intel_init_emon(dev);
8393 }
f97108d1 8394
1c70c0ce 8395 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 8396 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 8397 gen6_update_ring_freq(dev_priv);
8398 }
3b8d8d91 8399
652c393a
JB		 8400 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8401 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8402 (unsigned long)dev);
2c7111db
CW		 8403}
8404
8405void intel_modeset_gem_init(struct drm_device *dev)
8406{
8407 if (IS_IRONLAKE_M(dev))
8408 ironlake_enable_rc6(dev);
02e792fb
DV		 8409
8410 intel_setup_overlay(dev);
79e53945
JB		 8411}
8412
8413void intel_modeset_cleanup(struct drm_device *dev)
8414{
652c393a
JB		 8415 struct drm_i915_private *dev_priv = dev->dev_private;
8416 struct drm_crtc *crtc;
8417 struct intel_crtc *intel_crtc;
8418
f87ea761 8419 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8420 mutex_lock(&dev->struct_mutex);
8421
723bfd70
JB		 8422 intel_unregister_dsm_handler();
8423
8424
652c393a
JB		 8425 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8426 /* Skip inactive CRTCs */
8427 if (!crtc->fb)
8428 continue;
8429
8430 intel_crtc = to_intel_crtc(crtc);
3dec0095 8431 intel_increase_pllclock(crtc);
652c393a
JB		 8432 }
8433
973d04f9 8434 intel_disable_fbc(dev);
e70236a8 8435
f97108d1
JB		 8436 if (IS_IRONLAKE_M(dev))
8437 ironlake_disable_drps(dev);
1c70c0ce 8438 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 8439 gen6_disable_rps(dev);
f97108d1 8440
d5bb081b
JB		 8441 if (IS_IRONLAKE_M(dev))
8442 ironlake_disable_rc6(dev);
0cdab21f 8443
69341a5e
KH		 8444 mutex_unlock(&dev->struct_mutex);
8445
6c0d9350
DV		 8446 /* Disable the irq before mode object teardown, for the irq might
8447 * enqueue unpin/hotplug work. */
8448 drm_irq_uninstall(dev);
8449 cancel_work_sync(&dev_priv->hotplug_work);
8450
1630fe75
CW		 8451 /* flush any delayed tasks or pending work */
8452 flush_scheduled_work();
8453
3dec0095
DV		 8454 /* Shut off idle work before the crtcs get freed. */
8455 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8456 intel_crtc = to_intel_crtc(crtc);
8457 del_timer_sync(&intel_crtc->idle_timer);
8458 }
8459 del_timer_sync(&dev_priv->idle_timer);
8460 cancel_work_sync(&dev_priv->idle_work);
8461
79e53945
JB		 8462 drm_mode_config_cleanup(dev);
8463}
8464
f1c79df3
ZW		 8465/*
8466 * Return which encoder is currently attached for connector.
8467 */
df0e9248 8468struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8469{
df0e9248
CW		 8470 return &intel_attached_encoder(connector)->base;
8471}
f1c79df3 8472
df0e9248
CW		 8473void intel_connector_attach_encoder(struct intel_connector *connector,
8474 struct intel_encoder *encoder)
8475{
8476 connector->encoder = encoder;
8477 drm_mode_connector_attach_encoder(&connector->base,
8478 &encoder->base);
79e53945 8479}
28d52043
DA		 8480
8481/*
8482 * set vga decode state - true == enable VGA decode
8483 */
8484int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8485{
8486 struct drm_i915_private *dev_priv = dev->dev_private;
8487 u16 gmch_ctrl;
8488
8489 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8490 if (state)
8491 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8492 else
8493 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8494 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8495 return 0;
8496}
c4a1d9e4
CW		 8497
8498#ifdef CONFIG_DEBUG_FS
8499#include <linux/seq_file.h>
8500
8501struct intel_display_error_state {
8502 struct intel_cursor_error_state {
8503 u32 control;
8504 u32 position;
8505 u32 base;
8506 u32 size;
8507 } cursor[2];
8508
8509 struct intel_pipe_error_state {
8510 u32 conf;
8511 u32 source;
8512
8513 u32 htotal;
8514 u32 hblank;
8515 u32 hsync;
8516 u32 vtotal;
8517 u32 vblank;
8518 u32 vsync;
8519 } pipe[2];
8520
8521 struct intel_plane_error_state {
8522 u32 control;
8523 u32 stride;
8524 u32 size;
8525 u32 pos;
8526 u32 addr;
8527 u32 surface;
8528 u32 tile_offset;
8529 } plane[2];
8530};
8531
8532struct intel_display_error_state *
8533intel_display_capture_error_state(struct drm_device *dev)
8534{
8535 drm_i915_private_t *dev_priv = dev->dev_private;
8536 struct intel_display_error_state *error;
8537 int i;
8538
8539 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8540 if (error == NULL)
8541 return NULL;
8542
8543 for (i = 0; i < 2; i++) {
8544 error->cursor[i].control = I915_READ(CURCNTR(i));
8545 error->cursor[i].position = I915_READ(CURPOS(i));
8546 error->cursor[i].base = I915_READ(CURBASE(i));
8547
8548 error->plane[i].control = I915_READ(DSPCNTR(i));
8549 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8550 error->plane[i].size = I915_READ(DSPSIZE(i));
8551 error->plane[i].pos= I915_READ(DSPPOS(i));
8552 error->plane[i].addr = I915_READ(DSPADDR(i));
8553 if (INTEL_INFO(dev)->gen >= 4) {
8554 error->plane[i].surface = I915_READ(DSPSURF(i));
8555 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8556 }
8557
8558 error->pipe[i].conf = I915_READ(PIPECONF(i));
8559 error->pipe[i].source = I915_READ(PIPESRC(i));
8560 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8561 error->pipe[i].hblank = I915_READ(HBLANK(i));
8562 error->pipe[i].hsync = I915_READ(HSYNC(i));
8563 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8564 error->pipe[i].vblank = I915_READ(VBLANK(i));
8565 error->pipe[i].vsync = I915_READ(VSYNC(i));
8566 }
8567
8568 return error;
8569}
8570
8571void
8572intel_display_print_error_state(struct seq_file *m,
8573 struct drm_device *dev,
8574 struct intel_display_error_state *error)
8575{
8576 int i;
8577
8578 for (i = 0; i < 2; i++) {
8579 seq_printf(m, "Pipe [%d]:\n", i);
8580 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8581 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8582 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8583 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8584 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8585 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8586 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8587 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8588
8589 seq_printf(m, "Plane [%d]:\n", i);
8590 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8591 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8592 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8593 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8594 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8595 if (INTEL_INFO(dev)->gen >= 4) {
8596 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8597 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8598 }
8599
8600 seq_printf(m, "Cursor [%d]:\n", i);
8601 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8602 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8603 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8604 }
8605}
8606#endif
Linux kernel - Deliverables
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