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drm/i915: Preallocate the drm_mm_node prior to manipulating the GTT drm_mm manager
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
419 unsigned long flags;
420 u32 val = 0;
421
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
425 goto out_unlock;
426 }
427
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430 DPIO_BYTE);
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
433 goto out_unlock;
434 }
435 val = I915_READ(DPIO_DATA);
436
437out_unlock:
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439 return val;
440}
441
a0c4da24
JB		 442static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443 u32 val)
444{
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
450 goto out_unlock;
451 }
452
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456 DPIO_BYTE);
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
459
460out_unlock:
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462}
463
57f350b6
JB		 464static void vlv_init_dpio(struct drm_device *dev)
465{
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
473}
474
618563e3
DV		 475static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
476{
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
478 return 1;
479}
480
481static const struct dmi_system_id intel_dual_link_lvds[] = {
482 {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
485 .matches = {
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
488 },
489 },
490 { } /* terminating entry */
491};
492
b0354385
TI		 493static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
494 unsigned int reg)
495{
496 unsigned int val;
497
121d527a
TI		 498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
501
618563e3
DV		 502 if (dmi_check_system(intel_dual_link_lvds))
503 return true;
504
b0354385
TI		 505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
507 else {
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
512 */
513 val = I915_READ(reg);
14d94a3d 514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
517 }
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
519}
520
1b894b59
CW		 521static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
522 int refclk)
2c07245f 523{
b91ad0ec
ZW		 524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 526 const intel_limit_t *limit;
b91ad0ec
ZW		 527
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 530 /* LVDS dual channel */
1b894b59 531 if (refclk == 100000)
b91ad0ec
ZW		 532 limit = &intel_limits_ironlake_dual_lvds_100m;
533 else
534 limit = &intel_limits_ironlake_dual_lvds;
535 } else {
1b894b59 536 if (refclk == 100000)
b91ad0ec
ZW		 537 limit = &intel_limits_ironlake_single_lvds_100m;
538 else
539 limit = &intel_limits_ironlake_single_lvds;
540 }
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 543 limit = &intel_limits_ironlake_display_port;
2c07245f 544 else
b91ad0ec 545 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 546
547 return limit;
548}
549
044c7c41
ML		 550static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
551{
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 557 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 558 /* LVDS with dual channel */
e4b36699 559 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 560 else
561 /* LVDS with dual channel */
e4b36699 562 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 565 limit = &intel_limits_g4x_hdmi;
044c7c41 566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 567 limit = &intel_limits_g4x_sdvo;
0206e353 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 569 limit = &intel_limits_g4x_display_port;
044c7c41 570 } else /* The option is for other outputs */
e4b36699 571 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 572
573 return limit;
574}
575
1b894b59 576static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 577{
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
580
bad720ff 581 if (HAS_PCH_SPLIT(dev))
1b894b59 582 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 583 else if (IS_G4X(dev)) {
044c7c41 584 limit = intel_g4x_limit(crtc);
f2b115e6 585 } else if (IS_PINEVIEW(dev)) {
2177832f 586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 587 limit = &intel_limits_pineview_lvds;
2177832f 588 else
f2b115e6 589 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
595 else
596 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
600 else
601 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 602 } else {
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 604 limit = &intel_limits_i8xx_lvds;
79e53945 605 else
e4b36699 606 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 607 }
608 return limit;
609}
610
f2b115e6
AJ		 611/* m1 is reserved as 0 in Pineview, n is a ring counter */
612static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 613{
2177832f
SL		 614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
618}
619
620static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
621{
f2b115e6
AJ		 622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
2177832f
SL		 624 return;
625 }
79e53945
JB		 626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
630}
631
79e53945
JB		 632/**
633 * Returns whether any output on the specified pipe is of the specified type
634 */
4ef69c7a 635bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 636{
4ef69c7a 637 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 638 struct intel_encoder *encoder;
639
6c2b7c12
DV		 640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
4ef69c7a
CW		 642 return true;
643
644 return false;
79e53945
JB		 645}
646
7c04d1d9 647#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 648/**
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
651 */
652
1b894b59
CW		 653static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
79e53945 656{
79e53945 657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 658 INTELPllInvalid("p1 out of range\n");
79e53945 659 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 660 INTELPllInvalid("p out of range\n");
79e53945 661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 662 INTELPllInvalid("m2 out of range\n");
79e53945 663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 664 INTELPllInvalid("m1 out of range\n");
f2b115e6 665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 666 INTELPllInvalid("m1 <= m2\n");
79e53945 667 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 668 INTELPllInvalid("m out of range\n");
79e53945 669 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 670 INTELPllInvalid("n out of range\n");
79e53945 671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 672 INTELPllInvalid("vco out of range\n");
79e53945
JB		 673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
675 */
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 677 INTELPllInvalid("dot out of range\n");
79e53945
JB		 678
679 return true;
680}
681
d4906093
ML		 682static bool
683intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
d4906093 686
79e53945
JB		 687{
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 intel_clock_t clock;
79e53945
JB		 691 int err = target;
692
bc5e5718 693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 694 (I915_READ(LVDS)) != 0) {
79e53945
JB		 695 /*
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
699 * even can.
700 */
b0354385 701 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
0206e353 712 memset(best_clock, 0, sizeof(*best_clock));
79e53945 713
42158660
ZY		 714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 718 /* m1 is always 0 in Pineview */
719 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 720 break;
721 for (clock.n = limit->n.min;
722 clock.n <= limit->n.max; clock.n++) {
723 for (clock.p1 = limit->p1.min;
724 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 725 int this_err;
726
2177832f 727 intel_clock(dev, refclk, &clock);
1b894b59
CW		 728 if (!intel_PLL_is_valid(dev, limit,
729 &clock))
79e53945 730 continue;
cec2f356
SP		 731 if (match_clock &&
732 clock.p != match_clock->p)
733 continue;
79e53945
JB		 734
735 this_err = abs(clock.dot - target);
736 if (this_err < err) {
737 *best_clock = clock;
738 err = this_err;
739 }
740 }
741 }
742 }
743 }
744
745 return (err != target);
746}
747
d4906093
ML		 748static bool
749intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
d4906093
ML		 752{
753 struct drm_device *dev = crtc->dev;
754 struct drm_i915_private *dev_priv = dev->dev_private;
755 intel_clock_t clock;
756 int max_n;
757 bool found;
6ba770dc
AJ		 758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 760 found = false;
761
762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 763 int lvds_reg;
764
c619eed4 765 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 766 lvds_reg = PCH_LVDS;
767 else
768 lvds_reg = LVDS;
769 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 770 LVDS_CLKB_POWER_UP)
771 clock.p2 = limit->p2.p2_fast;
772 else
773 clock.p2 = limit->p2.p2_slow;
774 } else {
775 if (target < limit->p2.dot_limit)
776 clock.p2 = limit->p2.p2_slow;
777 else
778 clock.p2 = limit->p2.p2_fast;
779 }
780
781 memset(best_clock, 0, sizeof(*best_clock));
782 max_n = limit->n.max;
f77f13e2 783 /* based on hardware requirement, prefer smaller n to precision */
d4906093 784 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 785 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 786 for (clock.m1 = limit->m1.max;
787 clock.m1 >= limit->m1.min; clock.m1--) {
788 for (clock.m2 = limit->m2.max;
789 clock.m2 >= limit->m2.min; clock.m2--) {
790 for (clock.p1 = limit->p1.max;
791 clock.p1 >= limit->p1.min; clock.p1--) {
792 int this_err;
793
2177832f 794 intel_clock(dev, refclk, &clock);
1b894b59
CW		 795 if (!intel_PLL_is_valid(dev, limit,
796 &clock))
d4906093 797 continue;
cec2f356
SP		 798 if (match_clock &&
799 clock.p != match_clock->p)
800 continue;
1b894b59
CW		 801
802 this_err = abs(clock.dot - target);
d4906093
ML		 803 if (this_err < err_most) {
804 *best_clock = clock;
805 err_most = this_err;
806 max_n = clock.n;
807 found = true;
808 }
809 }
810 }
811 }
812 }
2c07245f
ZW		 813 return found;
814}
815
5eb08b69 816static bool
f2b115e6 817intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
5eb08b69
ZW		 820{
821 struct drm_device *dev = crtc->dev;
822 intel_clock_t clock;
4547668a 823
5eb08b69
ZW		 824 if (target < 200000) {
825 clock.n = 1;
826 clock.p1 = 2;
827 clock.p2 = 10;
828 clock.m1 = 12;
829 clock.m2 = 9;
830 } else {
831 clock.n = 2;
832 clock.p1 = 1;
833 clock.p2 = 10;
834 clock.m1 = 14;
835 clock.m2 = 8;
836 }
837 intel_clock(dev, refclk, &clock);
838 memcpy(best_clock, &clock, sizeof(intel_clock_t));
839 return true;
840}
841
a4fc5ed6
KP		 842/* DisplayPort has only two frequencies, 162MHz and 270MHz */
843static bool
844intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 845 int target, int refclk, intel_clock_t *match_clock,
846 intel_clock_t *best_clock)
a4fc5ed6 847{
5eddb70b
CW		 848 intel_clock_t clock;
849 if (target < 200000) {
850 clock.p1 = 2;
851 clock.p2 = 10;
852 clock.n = 2;
853 clock.m1 = 23;
854 clock.m2 = 8;
855 } else {
856 clock.p1 = 1;
857 clock.p2 = 10;
858 clock.n = 1;
859 clock.m1 = 14;
860 clock.m2 = 2;
861 }
862 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863 clock.p = (clock.p1 * clock.p2);
864 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
865 clock.vco = 0;
866 memcpy(best_clock, &clock, sizeof(intel_clock_t));
867 return true;
a4fc5ed6 868}
a0c4da24
JB		 869static bool
870intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *match_clock,
872 intel_clock_t *best_clock)
873{
874 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
875 u32 m, n, fastclk;
876 u32 updrate, minupdate, fracbits, p;
877 unsigned long bestppm, ppm, absppm;
878 int dotclk, flag;
879
af447bd3 880 flag = 0;
a0c4da24
JB		 881 dotclk = target * 1000;
882 bestppm = 1000000;
883 ppm = absppm = 0;
884 fastclk = dotclk / (2*100);
885 updrate = 0;
886 minupdate = 19200;
887 fracbits = 1;
888 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889 bestm1 = bestm2 = bestp1 = bestp2 = 0;
890
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893 updrate = refclk / n;
894 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
896 if (p2 > 10)
897 p2 = p2 - 1;
898 p = p1 * p2;
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901 m2 = (((2*(fastclk * p * n / m1 )) +
902 refclk) / (2*refclk));
903 m = m1 * m2;
904 vco = updrate * m;
905 if (vco >= limit->vco.min && vco < limit->vco.max) {
906 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907 absppm = (ppm > 0) ? ppm : (-ppm);
908 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
909 bestppm = 0;
910 flag = 1;
911 }
912 if (absppm < bestppm - 10) {
913 bestppm = absppm;
914 flag = 1;
915 }
916 if (flag) {
917 bestn = n;
918 bestm1 = m1;
919 bestm2 = m2;
920 bestp1 = p1;
921 bestp2 = p2;
922 flag = 0;
923 }
924 }
925 }
926 }
927 }
928 }
929 best_clock->n = bestn;
930 best_clock->m1 = bestm1;
931 best_clock->m2 = bestm2;
932 best_clock->p1 = bestp1;
933 best_clock->p2 = bestp2;
934
935 return true;
936}
a4fc5ed6 937
a5c961d1
PZ		 938enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
939 enum pipe pipe)
940{
941 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
943
944 return intel_crtc->cpu_transcoder;
945}
946
a928d536
PZ		 947static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
948{
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 frame, frame_reg = PIPEFRAME(pipe);
951
952 frame = I915_READ(frame_reg);
953
954 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
956}
957
9d0498a2
JB		 958/**
959 * intel_wait_for_vblank - wait for vblank on a given pipe
960 * @dev: drm device
961 * @pipe: pipe to wait for
962 *
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
964 * mode setting code.
965 */
966void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 967{
9d0498a2 968 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 969 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 970
a928d536
PZ		 971 if (INTEL_INFO(dev)->gen >= 5) {
972 ironlake_wait_for_vblank(dev, pipe);
973 return;
974 }
975
300387c0
CW		 976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
978 *
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
985 * vblanks...
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
988 */
989 I915_WRITE(pipestat_reg,
990 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
991
9d0498a2 992 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 993 if (wait_for(I915_READ(pipestat_reg) &
994 PIPE_VBLANK_INTERRUPT_STATUS,
995 50))
9d0498a2
JB		 996 DRM_DEBUG_KMS("vblank wait timed out\n");
997}
998
ab7ad7f6
KP		 999/*
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1001 * @dev: drm device
1002 * @pipe: pipe to wait for
1003 *
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1007 *
ab7ad7f6
KP		 1008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1010 *
1011 * Otherwise:
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
58e10eb9 1014 *
9d0498a2 1015 */
58e10eb9 1016void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1017{
1018 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020 pipe);
ab7ad7f6
KP		 1021
1022 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1023 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1024
1025 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1026 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027 100))
284637d9 1028 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1029 } else {
837ba00f 1030 u32 last_line, line_mask;
58e10eb9 1031 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
837ba00f
PZ		 1034 if (IS_GEN2(dev))
1035 line_mask = DSL_LINEMASK_GEN2;
1036 else
1037 line_mask = DSL_LINEMASK_GEN3;
1038
ab7ad7f6
KP		 1039 /* Wait for the display line to settle */
1040 do {
837ba00f 1041 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1042 mdelay(5);
837ba00f 1043 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1044 time_after(timeout, jiffies));
1045 if (time_after(jiffies, timeout))
284637d9 1046 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1047 }
79e53945
JB		 1048}
1049
b24e7179
JB		 1050static const char *state_string(bool enabled)
1051{
1052 return enabled ? "on" : "off";
1053}
1054
1055/* Only for pre-ILK configs */
1056static void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058{
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069}
1070#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
040484af
JB		 1073/* For ILK+ */
1074static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1075 struct intel_pch_pll *pll,
1076 struct intel_crtc *crtc,
1077 bool state)
040484af 1078{
040484af
JB		 1079 u32 val;
1080 bool cur_state;
1081
9d82aa17
ED		 1082 if (HAS_PCH_LPT(dev_priv->dev)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 return;
1085 }
1086
92b27b08
CW		 1087 if (WARN (!pll,
1088 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1089 return;
ee7b9f93 1090
92b27b08
CW		 1091 val = I915_READ(pll->pll_reg);
1092 cur_state = !!(val & DPLL_VCO_ENABLE);
1093 WARN(cur_state != state,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1099 u32 pch_dpll;
1100
1101 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1102 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state, crtc->pipe, pch_dpll)) {
1106 cur_state = !!(val >> (4*crtc->pipe + 3));
1107 WARN(cur_state != state,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll->pll_reg == _PCH_DPLL_B,
1110 state_string(state),
1111 crtc->pipe,
1112 val);
1113 }
d3ccbe86 1114 }
040484af 1115}
92b27b08
CW		 1116#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1118
1119static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121{
1122 int reg;
1123 u32 val;
1124 bool cur_state;
ad80a810
PZ		 1125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126 pipe);
040484af 1127
bf507ef7
ED		 1128 if (IS_HASWELL(dev_priv->dev)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1130 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1131 val = I915_READ(reg);
ad80a810 1132 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1133 } else {
1134 reg = FDI_TX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147{
1148 int reg;
1149 u32 val;
1150 bool cur_state;
1151
d63fa0dc
PZ		 1152 reg = FDI_RX_CTL(pipe);
1153 val = I915_READ(reg);
1154 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1155 WARN(cur_state != state,
1156 "FDI RX state assertion failure (expected %s, current %s)\n",
1157 state_string(state), state_string(cur_state));
1158}
1159#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161
1162static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1163 enum pipe pipe)
1164{
1165 int reg;
1166 u32 val;
1167
1168 /* ILK FDI PLL is always enabled */
1169 if (dev_priv->info->gen == 5)
1170 return;
1171
bf507ef7
ED		 1172 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173 if (IS_HASWELL(dev_priv->dev))
1174 return;
1175
040484af
JB		 1176 reg = FDI_TX_CTL(pipe);
1177 val = I915_READ(reg);
1178 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1179}
1180
1181static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe)
1183{
1184 int reg;
1185 u32 val;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1190}
1191
ea0760cf
JB		 1192static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
1194{
1195 int pp_reg, lvds_reg;
1196 u32 val;
1197 enum pipe panel_pipe = PIPE_A;
0de3b485 1198 bool locked = true;
ea0760cf
JB		 1199
1200 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201 pp_reg = PCH_PP_CONTROL;
1202 lvds_reg = PCH_LVDS;
1203 } else {
1204 pp_reg = PP_CONTROL;
1205 lvds_reg = LVDS;
1206 }
1207
1208 val = I915_READ(pp_reg);
1209 if (!(val & PANEL_POWER_ON) ||
1210 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211 locked = false;
1212
1213 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214 panel_pipe = PIPE_B;
1215
1216 WARN(panel_pipe == pipe && locked,
1217 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1218 pipe_name(pipe));
ea0760cf
JB		 1219}
1220
b840d907
JB		 1221void assert_pipe(struct drm_i915_private *dev_priv,
1222 enum pipe pipe, bool state)
b24e7179
JB		 1223{
1224 int reg;
1225 u32 val;
63d7bbe9 1226 bool cur_state;
702e7a56
PZ		 1227 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228 pipe);
b24e7179 1229
8e636784
DV		 1230 /* if we need the pipe A quirk it must be always on */
1231 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1232 state = true;
1233
702e7a56 1234 reg = PIPECONF(cpu_transcoder);
b24e7179 1235 val = I915_READ(reg);
63d7bbe9
JB		 1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 WARN(cur_state != state,
1238 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1239 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1240}
1241
931872fc
CW		 1242static void assert_plane(struct drm_i915_private *dev_priv,
1243 enum plane plane, bool state)
b24e7179
JB		 1244{
1245 int reg;
1246 u32 val;
931872fc 1247 bool cur_state;
b24e7179
JB		 1248
1249 reg = DSPCNTR(plane);
1250 val = I915_READ(reg);
931872fc
CW		 1251 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252 WARN(cur_state != state,
1253 "plane %c assertion failure (expected %s, current %s)\n",
1254 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1255}
1256
931872fc
CW		 1257#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1259
b24e7179
JB		 1260static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1261 enum pipe pipe)
1262{
1263 int reg, i;
1264 u32 val;
1265 int cur_pipe;
1266
19ec1358 1267 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1268 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269 reg = DSPCNTR(pipe);
1270 val = I915_READ(reg);
1271 WARN((val & DISPLAY_PLANE_ENABLE),
1272 "plane %c assertion failure, should be disabled but not\n",
1273 plane_name(pipe));
19ec1358 1274 return;
28c05794 1275 }
19ec1358 1276
b24e7179
JB		 1277 /* Need to check both planes against the pipe */
1278 for (i = 0; i < 2; i++) {
1279 reg = DSPCNTR(i);
1280 val = I915_READ(reg);
1281 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282 DISPPLANE_SEL_PIPE_SHIFT;
1283 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1284 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1286 }
1287}
1288
92f2584a
JB		 1289static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1290{
1291 u32 val;
1292 bool enabled;
1293
9d82aa17
ED		 1294 if (HAS_PCH_LPT(dev_priv->dev)) {
1295 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1296 return;
1297 }
1298
92f2584a
JB		 1299 val = I915_READ(PCH_DREF_CONTROL);
1300 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301 DREF_SUPERSPREAD_SOURCE_MASK));
1302 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1303}
1304
1305static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1306 enum pipe pipe)
1307{
1308 int reg;
1309 u32 val;
1310 bool enabled;
1311
1312 reg = TRANSCONF(pipe);
1313 val = I915_READ(reg);
1314 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1315 WARN(enabled,
1316 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1317 pipe_name(pipe));
92f2584a
JB		 1318}
1319
4e634389
KP		 1320static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1322{
1323 if ((val & DP_PORT_EN) == 0)
1324 return false;
1325
1326 if (HAS_PCH_CPT(dev_priv->dev)) {
1327 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1330 return false;
1331 } else {
1332 if ((val & DP_PIPE_MASK) != (pipe << 30))
1333 return false;
1334 }
1335 return true;
1336}
1337
1519b995
KP		 1338static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe, u32 val)
1340{
1341 if ((val & PORT_ENABLE) == 0)
1342 return false;
1343
1344 if (HAS_PCH_CPT(dev_priv->dev)) {
1345 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1346 return false;
1347 } else {
1348 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1349 return false;
1350 }
1351 return true;
1352}
1353
1354static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355 enum pipe pipe, u32 val)
1356{
1357 if ((val & LVDS_PORT_EN) == 0)
1358 return false;
1359
1360 if (HAS_PCH_CPT(dev_priv->dev)) {
1361 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1362 return false;
1363 } else {
1364 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1365 return false;
1366 }
1367 return true;
1368}
1369
1370static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 val)
1372{
1373 if ((val & ADPA_DAC_ENABLE) == 0)
1374 return false;
1375 if (HAS_PCH_CPT(dev_priv->dev)) {
1376 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377 return false;
1378 } else {
1379 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1380 return false;
1381 }
1382 return true;
1383}
1384
291906f1 1385static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1386 enum pipe pipe, int reg, u32 port_sel)
291906f1 1387{
47a05eca 1388 u32 val = I915_READ(reg);
4e634389 1389 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1390 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1391 reg, pipe_name(pipe));
de9a35ab 1392
75c5da27
DV		 1393 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394 && (val & DP_PIPEB_SELECT),
de9a35ab 1395 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1396}
1397
1398static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399 enum pipe pipe, int reg)
1400{
47a05eca 1401 u32 val = I915_READ(reg);
b70ad586 1402 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1403 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1404 reg, pipe_name(pipe));
de9a35ab 1405
75c5da27
DV		 1406 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1408 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1409}
1410
1411static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413{
1414 int reg;
1415 u32 val;
291906f1 1416
f0575e92
KP		 1417 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1420
1421 reg = PCH_ADPA;
1422 val = I915_READ(reg);
b70ad586 1423 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1424 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1425 pipe_name(pipe));
291906f1
JB		 1426
1427 reg = PCH_LVDS;
1428 val = I915_READ(reg);
b70ad586 1429 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1430 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1431 pipe_name(pipe));
291906f1
JB		 1432
1433 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1436}
1437
63d7bbe9
JB		 1438/**
1439 * intel_enable_pll - enable a PLL
1440 * @dev_priv: i915 private structure
1441 * @pipe: pipe PLL to enable
1442 *
1443 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1444 * make sure the PLL reg is writable first though, since the panel write
1445 * protect mechanism may be enabled.
1446 *
1447 * Note! This is for pre-ILK only.
7434a255
TR		 1448 *
1449 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1450 */
1451static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1452{
1453 int reg;
1454 u32 val;
1455
1456 /* No really, not for ILK+ */
a0c4da24 1457 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1458
1459 /* PLL is protected by panel, make sure we can write it */
1460 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461 assert_panel_unlocked(dev_priv, pipe);
1462
1463 reg = DPLL(pipe);
1464 val = I915_READ(reg);
1465 val |= DPLL_VCO_ENABLE;
1466
1467 /* We do this three times for luck */
1468 I915_WRITE(reg, val);
1469 POSTING_READ(reg);
1470 udelay(150); /* wait for warmup */
1471 I915_WRITE(reg, val);
1472 POSTING_READ(reg);
1473 udelay(150); /* wait for warmup */
1474 I915_WRITE(reg, val);
1475 POSTING_READ(reg);
1476 udelay(150); /* wait for warmup */
1477}
1478
1479/**
1480 * intel_disable_pll - disable a PLL
1481 * @dev_priv: i915 private structure
1482 * @pipe: pipe PLL to disable
1483 *
1484 * Disable the PLL for @pipe, making sure the pipe is off first.
1485 *
1486 * Note! This is for pre-ILK only.
1487 */
1488static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1489{
1490 int reg;
1491 u32 val;
1492
1493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495 return;
1496
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv, pipe);
1499
1500 reg = DPLL(pipe);
1501 val = I915_READ(reg);
1502 val &= ~DPLL_VCO_ENABLE;
1503 I915_WRITE(reg, val);
1504 POSTING_READ(reg);
1505}
1506
a416edef
ED		 1507/* SBI access */
1508static void
988d6ee8
PZ		 1509intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1510 enum intel_sbi_destination destination)
a416edef
ED		 1511{
1512 unsigned long flags;
988d6ee8 1513 u32 tmp;
a416edef
ED		 1514
1515 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
988d6ee8 1516 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
a416edef
ED		 1517 DRM_ERROR("timeout waiting for SBI to become ready\n");
1518 goto out_unlock;
1519 }
1520
988d6ee8
PZ		 1521 I915_WRITE(SBI_ADDR, (reg << 16));
1522 I915_WRITE(SBI_DATA, value);
1523
1524 if (destination == SBI_ICLK)
1525 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1526 else
1527 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1528 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1529
39fb50f6 1530 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1531 100)) {
1532 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1533 goto out_unlock;
1534 }
1535
1536out_unlock:
1537 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1538}
1539
1540static u32
988d6ee8
PZ		 1541intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1542 enum intel_sbi_destination destination)
a416edef
ED		 1543{
1544 unsigned long flags;
39fb50f6 1545 u32 value = 0;
a416edef
ED		 1546
1547 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
988d6ee8 1548 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
a416edef
ED		 1549 DRM_ERROR("timeout waiting for SBI to become ready\n");
1550 goto out_unlock;
1551 }
1552
988d6ee8
PZ		 1553 I915_WRITE(SBI_ADDR, (reg << 16));
1554
1555 if (destination == SBI_ICLK)
1556 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1557 else
1558 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1559 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1560
39fb50f6 1561 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1562 100)) {
1563 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1564 goto out_unlock;
1565 }
1566
1567 value = I915_READ(SBI_DATA);
1568
1569out_unlock:
1570 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1571 return value;
1572}
1573
92f2584a 1574/**
b6b4e185 1575 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1576 * @dev_priv: i915 private structure
1577 * @pipe: pipe PLL to enable
1578 *
1579 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1580 * drives the transcoder clock.
1581 */
b6b4e185 1582static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1583{
ee7b9f93 1584 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1585 struct intel_pch_pll *pll;
92f2584a
JB		 1586 int reg;
1587 u32 val;
1588
48da64a8 1589 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1590 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1591 pll = intel_crtc->pch_pll;
1592 if (pll == NULL)
1593 return;
1594
1595 if (WARN_ON(pll->refcount == 0))
1596 return;
ee7b9f93
JB		 1597
1598 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1599 pll->pll_reg, pll->active, pll->on,
1600 intel_crtc->base.base.id);
92f2584a
JB		 1601
1602 /* PCH refclock must be enabled first */
1603 assert_pch_refclk_enabled(dev_priv);
1604
ee7b9f93 1605 if (pll->active++ && pll->on) {
92b27b08 1606 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1607 return;
1608 }
1609
1610 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1611
1612 reg = pll->pll_reg;
92f2584a
JB		 1613 val = I915_READ(reg);
1614 val |= DPLL_VCO_ENABLE;
1615 I915_WRITE(reg, val);
1616 POSTING_READ(reg);
1617 udelay(200);
ee7b9f93
JB		 1618
1619 pll->on = true;
92f2584a
JB		 1620}
1621
ee7b9f93 1622static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1623{
ee7b9f93
JB		 1624 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1625 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1626 int reg;
ee7b9f93 1627 u32 val;
4c609cb8 1628
92f2584a
JB		 1629 /* PCH only available on ILK+ */
1630 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1631 if (pll == NULL)
1632 return;
92f2584a 1633
48da64a8
CW		 1634 if (WARN_ON(pll->refcount == 0))
1635 return;
7a419866 1636
ee7b9f93
JB		 1637 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1638 pll->pll_reg, pll->active, pll->on,
1639 intel_crtc->base.base.id);
7a419866 1640
48da64a8 1641 if (WARN_ON(pll->active == 0)) {
92b27b08 1642 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1643 return;
1644 }
1645
ee7b9f93 1646 if (--pll->active) {
92b27b08 1647 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1648 return;
ee7b9f93
JB		 1649 }
1650
1651 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1652
1653 /* Make sure transcoder isn't still depending on us */
1654 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1655
ee7b9f93 1656 reg = pll->pll_reg;
92f2584a
JB		 1657 val = I915_READ(reg);
1658 val &= ~DPLL_VCO_ENABLE;
1659 I915_WRITE(reg, val);
1660 POSTING_READ(reg);
1661 udelay(200);
ee7b9f93
JB		 1662
1663 pll->on = false;
92f2584a
JB		 1664}
1665
b8a4f404
PZ		 1666static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1667 enum pipe pipe)
040484af 1668{
23670b32 1669 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1670 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1671 uint32_t reg, val, pipeconf_val;
040484af
JB		 1672
1673 /* PCH only available on ILK+ */
1674 BUG_ON(dev_priv->info->gen < 5);
1675
1676 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1677 assert_pch_pll_enabled(dev_priv,
1678 to_intel_crtc(crtc)->pch_pll,
1679 to_intel_crtc(crtc));
040484af
JB		 1680
1681 /* FDI must be feeding us bits for PCH ports */
1682 assert_fdi_tx_enabled(dev_priv, pipe);
1683 assert_fdi_rx_enabled(dev_priv, pipe);
1684
23670b32
DV		 1685 if (HAS_PCH_CPT(dev)) {
1686 /* Workaround: Set the timing override bit before enabling the
1687 * pch transcoder. */
1688 reg = TRANS_CHICKEN2(pipe);
1689 val = I915_READ(reg);
1690 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1691 I915_WRITE(reg, val);
59c859d6 1692 }
23670b32 1693
040484af
JB		 1694 reg = TRANSCONF(pipe);
1695 val = I915_READ(reg);
5f7f726d 1696 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1697
1698 if (HAS_PCH_IBX(dev_priv->dev)) {
1699 /*
1700 * make the BPC in transcoder be consistent with
1701 * that in pipeconf reg.
1702 */
1703 val &= ~PIPE_BPC_MASK;
5f7f726d 1704 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1705 }
5f7f726d
PZ		 1706
1707 val &= ~TRANS_INTERLACE_MASK;
1708 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1709 if (HAS_PCH_IBX(dev_priv->dev) &&
1710 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1711 val |= TRANS_LEGACY_INTERLACED_ILK;
1712 else
1713 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1714 else
1715 val |= TRANS_PROGRESSIVE;
1716
040484af
JB		 1717 I915_WRITE(reg, val | TRANS_ENABLE);
1718 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1719 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1720}
1721
8fb033d7 1722static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1723 enum transcoder cpu_transcoder)
040484af 1724{
8fb033d7 1725 u32 val, pipeconf_val;
8fb033d7
PZ		 1726
1727 /* PCH only available on ILK+ */
1728 BUG_ON(dev_priv->info->gen < 5);
1729
8fb033d7 1730 /* FDI must be feeding us bits for PCH ports */
937bb610
PZ		 1731 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1732 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1733
223a6fdf
PZ		 1734 /* Workaround: set timing override bit. */
1735 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1736 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1737 I915_WRITE(_TRANSA_CHICKEN2, val);
1738
25f3ef11 1739 val = TRANS_ENABLE;
937bb610 1740 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1741
9a76b1c6
PZ		 1742 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1743 PIPECONF_INTERLACED_ILK)
a35f2679 1744 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1745 else
1746 val |= TRANS_PROGRESSIVE;
1747
25f3ef11 1748 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1749 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1750 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1751}
1752
b8a4f404
PZ		 1753static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1754 enum pipe pipe)
040484af 1755{
23670b32
DV		 1756 struct drm_device *dev = dev_priv->dev;
1757 uint32_t reg, val;
040484af
JB		 1758
1759 /* FDI relies on the transcoder */
1760 assert_fdi_tx_disabled(dev_priv, pipe);
1761 assert_fdi_rx_disabled(dev_priv, pipe);
1762
291906f1
JB		 1763 /* Ports must be off as well */
1764 assert_pch_ports_disabled(dev_priv, pipe);
1765
040484af
JB		 1766 reg = TRANSCONF(pipe);
1767 val = I915_READ(reg);
1768 val &= ~TRANS_ENABLE;
1769 I915_WRITE(reg, val);
1770 /* wait for PCH transcoder off, transcoder state */
1771 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1772 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1773
1774 if (!HAS_PCH_IBX(dev)) {
1775 /* Workaround: Clear the timing override chicken bit again. */
1776 reg = TRANS_CHICKEN2(pipe);
1777 val = I915_READ(reg);
1778 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1779 I915_WRITE(reg, val);
1780 }
040484af
JB		 1781}
1782
ab4d966c 1783static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1784{
8fb033d7
PZ		 1785 u32 val;
1786
8a52fd9f 1787 val = I915_READ(_TRANSACONF);
8fb033d7 1788 val &= ~TRANS_ENABLE;
8a52fd9f 1789 I915_WRITE(_TRANSACONF, val);
8fb033d7 1790 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1791 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1792 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1793
1794 /* Workaround: clear timing override bit. */
1795 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1796 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1797 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1798}
1799
b24e7179 1800/**
309cfea8 1801 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1802 * @dev_priv: i915 private structure
1803 * @pipe: pipe to enable
040484af 1804 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1805 *
1806 * Enable @pipe, making sure that various hardware specific requirements
1807 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1808 *
1809 * @pipe should be %PIPE_A or %PIPE_B.
1810 *
1811 * Will wait until the pipe is actually running (i.e. first vblank) before
1812 * returning.
1813 */
040484af
JB		 1814static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1815 bool pch_port)
b24e7179 1816{
702e7a56
PZ		 1817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1818 pipe);
cc391bbb 1819 enum transcoder pch_transcoder;
b24e7179
JB		 1820 int reg;
1821 u32 val;
1822
cc391bbb
PZ		 1823 if (IS_HASWELL(dev_priv->dev))
1824 pch_transcoder = TRANSCODER_A;
1825 else
1826 pch_transcoder = pipe;
1827
b24e7179
JB		 1828 /*
1829 * A pipe without a PLL won't actually be able to drive bits from
1830 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1831 * need the check.
1832 */
1833 if (!HAS_PCH_SPLIT(dev_priv->dev))
1834 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1835 else {
1836 if (pch_port) {
1837 /* if driving the PCH, we need FDI enabled */
cc391bbb
PZ		 1838 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1839 assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
040484af
JB		 1840 }
1841 /* FIXME: assert CPU port conditions for SNB+ */
1842 }
b24e7179 1843
702e7a56 1844 reg = PIPECONF(cpu_transcoder);
b24e7179 1845 val = I915_READ(reg);
00d70b15
CW		 1846 if (val & PIPECONF_ENABLE)
1847 return;
1848
1849 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1850 intel_wait_for_vblank(dev_priv->dev, pipe);
1851}
1852
1853/**
309cfea8 1854 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1855 * @dev_priv: i915 private structure
1856 * @pipe: pipe to disable
1857 *
1858 * Disable @pipe, making sure that various hardware specific requirements
1859 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1860 *
1861 * @pipe should be %PIPE_A or %PIPE_B.
1862 *
1863 * Will wait until the pipe has shut down before returning.
1864 */
1865static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1866 enum pipe pipe)
1867{
702e7a56
PZ		 1868 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1869 pipe);
b24e7179
JB		 1870 int reg;
1871 u32 val;
1872
1873 /*
1874 * Make sure planes won't keep trying to pump pixels to us,
1875 * or we might hang the display.
1876 */
1877 assert_planes_disabled(dev_priv, pipe);
1878
1879 /* Don't disable pipe A or pipe A PLLs if needed */
1880 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1881 return;
1882
702e7a56 1883 reg = PIPECONF(cpu_transcoder);
b24e7179 1884 val = I915_READ(reg);
00d70b15
CW		 1885 if ((val & PIPECONF_ENABLE) == 0)
1886 return;
1887
1888 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1889 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1890}
1891
d74362c9
KP		 1892/*
1893 * Plane regs are double buffered, going from enabled->disabled needs a
1894 * trigger in order to latch. The display address reg provides this.
1895 */
6f1d69b0 1896void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1897 enum plane plane)
1898{
14f86147
DL		 1899 if (dev_priv->info->gen >= 4)
1900 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1901 else
1902 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1903}
1904
b24e7179
JB		 1905/**
1906 * intel_enable_plane - enable a display plane on a given pipe
1907 * @dev_priv: i915 private structure
1908 * @plane: plane to enable
1909 * @pipe: pipe being fed
1910 *
1911 * Enable @plane on @pipe, making sure that @pipe is running first.
1912 */
1913static void intel_enable_plane(struct drm_i915_private *dev_priv,
1914 enum plane plane, enum pipe pipe)
1915{
1916 int reg;
1917 u32 val;
1918
1919 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1920 assert_pipe_enabled(dev_priv, pipe);
1921
1922 reg = DSPCNTR(plane);
1923 val = I915_READ(reg);
00d70b15
CW		 1924 if (val & DISPLAY_PLANE_ENABLE)
1925 return;
1926
1927 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1928 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1929 intel_wait_for_vblank(dev_priv->dev, pipe);
1930}
1931
b24e7179
JB		 1932/**
1933 * intel_disable_plane - disable a display plane
1934 * @dev_priv: i915 private structure
1935 * @plane: plane to disable
1936 * @pipe: pipe consuming the data
1937 *
1938 * Disable @plane; should be an independent operation.
1939 */
1940static void intel_disable_plane(struct drm_i915_private *dev_priv,
1941 enum plane plane, enum pipe pipe)
1942{
1943 int reg;
1944 u32 val;
1945
1946 reg = DSPCNTR(plane);
1947 val = I915_READ(reg);
00d70b15
CW		 1948 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1949 return;
1950
1951 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1952 intel_flush_display_plane(dev_priv, plane);
1953 intel_wait_for_vblank(dev_priv->dev, pipe);
1954}
1955
127bd2ac 1956int
48b956c5 1957intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1958 struct drm_i915_gem_object *obj,
919926ae 1959 struct intel_ring_buffer *pipelined)
6b95a207 1960{
ce453d81 1961 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1962 u32 alignment;
1963 int ret;
1964
05394f39 1965 switch (obj->tiling_mode) {
6b95a207 1966 case I915_TILING_NONE:
534843da
CW		 1967 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1968 alignment = 128 * 1024;
a6c45cf0 1969 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1970 alignment = 4 * 1024;
1971 else
1972 alignment = 64 * 1024;
6b95a207
KH		 1973 break;
1974 case I915_TILING_X:
1975 /* pin() will align the object as required by fence */
1976 alignment = 0;
1977 break;
1978 case I915_TILING_Y:
1979 /* FIXME: Is this true? */
1980 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1981 return -EINVAL;
1982 default:
1983 BUG();
1984 }
1985
ce453d81 1986 dev_priv->mm.interruptible = false;
2da3b9b9 1987 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1988 if (ret)
ce453d81 1989 goto err_interruptible;
6b95a207
KH		 1990
1991 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1992 * fence, whereas 965+ only requires a fence if using
1993 * framebuffer compression. For simplicity, we always install
1994 * a fence as the cost is not that onerous.
1995 */
06d98131 1996 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1997 if (ret)
1998 goto err_unpin;
1690e1eb 1999
9a5a53b3 2000 i915_gem_object_pin_fence(obj);
6b95a207 2001
ce453d81 2002 dev_priv->mm.interruptible = true;
6b95a207 2003 return 0;
48b956c5
CW		 2004
2005err_unpin:
2006 i915_gem_object_unpin(obj);
ce453d81
CW		 2007err_interruptible:
2008 dev_priv->mm.interruptible = true;
48b956c5 2009 return ret;
6b95a207
KH		 2010}
2011
1690e1eb
CW		 2012void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2013{
2014 i915_gem_object_unpin_fence(obj);
2015 i915_gem_object_unpin(obj);
2016}
2017
c2c75131
DV		 2018/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2019 * is assumed to be a power-of-two. */
5a35e99e
DL		 2020unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2021 unsigned int bpp,
2022 unsigned int pitch)
c2c75131
DV		 2023{
2024 int tile_rows, tiles;
2025
2026 tile_rows = *y / 8;
2027 *y %= 8;
2028 tiles = *x / (512/bpp);
2029 *x %= 512/bpp;
2030
2031 return tile_rows * pitch * 8 + tiles * 4096;
2032}
2033
17638cd6
JB		 2034static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2035 int x, int y)
81255565
JB		 2036{
2037 struct drm_device *dev = crtc->dev;
2038 struct drm_i915_private *dev_priv = dev->dev_private;
2039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2040 struct intel_framebuffer *intel_fb;
05394f39 2041 struct drm_i915_gem_object *obj;
81255565 2042 int plane = intel_crtc->plane;
e506a0c6 2043 unsigned long linear_offset;
81255565 2044 u32 dspcntr;
5eddb70b 2045 u32 reg;
81255565
JB		 2046
2047 switch (plane) {
2048 case 0:
2049 case 1:
2050 break;
2051 default:
2052 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2053 return -EINVAL;
2054 }
2055
2056 intel_fb = to_intel_framebuffer(fb);
2057 obj = intel_fb->obj;
81255565 2058
5eddb70b
CW		 2059 reg = DSPCNTR(plane);
2060 dspcntr = I915_READ(reg);
81255565
JB		 2061 /* Mask out pixel format bits in case we change it */
2062 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2063 switch (fb->pixel_format) {
2064 case DRM_FORMAT_C8:
81255565
JB		 2065 dspcntr |= DISPPLANE_8BPP;
2066 break;
57779d06
VS		 2067 case DRM_FORMAT_XRGB1555:
2068 case DRM_FORMAT_ARGB1555:
2069 dspcntr |= DISPPLANE_BGRX555;
81255565 2070 break;
57779d06
VS		 2071 case DRM_FORMAT_RGB565:
2072 dspcntr |= DISPPLANE_BGRX565;
2073 break;
2074 case DRM_FORMAT_XRGB8888:
2075 case DRM_FORMAT_ARGB8888:
2076 dspcntr |= DISPPLANE_BGRX888;
2077 break;
2078 case DRM_FORMAT_XBGR8888:
2079 case DRM_FORMAT_ABGR8888:
2080 dspcntr |= DISPPLANE_RGBX888;
2081 break;
2082 case DRM_FORMAT_XRGB2101010:
2083 case DRM_FORMAT_ARGB2101010:
2084 dspcntr |= DISPPLANE_BGRX101010;
2085 break;
2086 case DRM_FORMAT_XBGR2101010:
2087 case DRM_FORMAT_ABGR2101010:
2088 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2089 break;
2090 default:
57779d06 2091 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2092 return -EINVAL;
2093 }
57779d06 2094
a6c45cf0 2095 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2096 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2097 dspcntr |= DISPPLANE_TILED;
2098 else
2099 dspcntr &= ~DISPPLANE_TILED;
2100 }
2101
5eddb70b 2102 I915_WRITE(reg, dspcntr);
81255565 2103
e506a0c6 2104 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2105
c2c75131
DV		 2106 if (INTEL_INFO(dev)->gen >= 4) {
2107 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2108 intel_gen4_compute_offset_xtiled(&x, &y,
2109 fb->bits_per_pixel / 8,
2110 fb->pitches[0]);
c2c75131
DV		 2111 linear_offset -= intel_crtc->dspaddr_offset;
2112 } else {
e506a0c6 2113 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2114 }
e506a0c6
DV		 2115
2116 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2117 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2118 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2119 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2120 I915_MODIFY_DISPBASE(DSPSURF(plane),
2121 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2122 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2123 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2124 } else
e506a0c6 2125 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2126 POSTING_READ(reg);
81255565 2127
17638cd6
JB		 2128 return 0;
2129}
2130
2131static int ironlake_update_plane(struct drm_crtc *crtc,
2132 struct drm_framebuffer *fb, int x, int y)
2133{
2134 struct drm_device *dev = crtc->dev;
2135 struct drm_i915_private *dev_priv = dev->dev_private;
2136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137 struct intel_framebuffer *intel_fb;
2138 struct drm_i915_gem_object *obj;
2139 int plane = intel_crtc->plane;
e506a0c6 2140 unsigned long linear_offset;
17638cd6
JB		 2141 u32 dspcntr;
2142 u32 reg;
2143
2144 switch (plane) {
2145 case 0:
2146 case 1:
27f8227b 2147 case 2:
17638cd6
JB		 2148 break;
2149 default:
2150 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2151 return -EINVAL;
2152 }
2153
2154 intel_fb = to_intel_framebuffer(fb);
2155 obj = intel_fb->obj;
2156
2157 reg = DSPCNTR(plane);
2158 dspcntr = I915_READ(reg);
2159 /* Mask out pixel format bits in case we change it */
2160 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2161 switch (fb->pixel_format) {
2162 case DRM_FORMAT_C8:
17638cd6
JB		 2163 dspcntr |= DISPPLANE_8BPP;
2164 break;
57779d06
VS		 2165 case DRM_FORMAT_RGB565:
2166 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2167 break;
57779d06
VS		 2168 case DRM_FORMAT_XRGB8888:
2169 case DRM_FORMAT_ARGB8888:
2170 dspcntr |= DISPPLANE_BGRX888;
2171 break;
2172 case DRM_FORMAT_XBGR8888:
2173 case DRM_FORMAT_ABGR8888:
2174 dspcntr |= DISPPLANE_RGBX888;
2175 break;
2176 case DRM_FORMAT_XRGB2101010:
2177 case DRM_FORMAT_ARGB2101010:
2178 dspcntr |= DISPPLANE_BGRX101010;
2179 break;
2180 case DRM_FORMAT_XBGR2101010:
2181 case DRM_FORMAT_ABGR2101010:
2182 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2183 break;
2184 default:
57779d06 2185 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2186 return -EINVAL;
2187 }
2188
2189 if (obj->tiling_mode != I915_TILING_NONE)
2190 dspcntr |= DISPPLANE_TILED;
2191 else
2192 dspcntr &= ~DISPPLANE_TILED;
2193
2194 /* must disable */
2195 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2196
2197 I915_WRITE(reg, dspcntr);
2198
e506a0c6 2199 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2200 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2201 intel_gen4_compute_offset_xtiled(&x, &y,
2202 fb->bits_per_pixel / 8,
2203 fb->pitches[0]);
c2c75131 2204 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2205
e506a0c6
DV		 2206 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2207 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2208 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2209 I915_MODIFY_DISPBASE(DSPSURF(plane),
2210 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2211 if (IS_HASWELL(dev)) {
2212 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2213 } else {
2214 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2215 I915_WRITE(DSPLINOFF(plane), linear_offset);
2216 }
17638cd6
JB		 2217 POSTING_READ(reg);
2218
2219 return 0;
2220}
2221
2222/* Assume fb object is pinned & idle & fenced and just update base pointers */
2223static int
2224intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2225 int x, int y, enum mode_set_atomic state)
2226{
2227 struct drm_device *dev = crtc->dev;
2228 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2229
6b8e6ed0
CW		 2230 if (dev_priv->display.disable_fbc)
2231 dev_priv->display.disable_fbc(dev);
3dec0095 2232 intel_increase_pllclock(crtc);
81255565 2233
6b8e6ed0 2234 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2235}
2236
14667a4b
CW		 2237static int
2238intel_finish_fb(struct drm_framebuffer *old_fb)
2239{
2240 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2241 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2242 bool was_interruptible = dev_priv->mm.interruptible;
2243 int ret;
2244
2245 wait_event(dev_priv->pending_flip_queue,
2246 atomic_read(&dev_priv->mm.wedged) ||
2247 atomic_read(&obj->pending_flip) == 0);
2248
2249 /* Big Hammer, we also need to ensure that any pending
2250 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251 * current scanout is retired before unpinning the old
2252 * framebuffer.
2253 *
2254 * This should only fail upon a hung GPU, in which case we
2255 * can safely continue.
2256 */
2257 dev_priv->mm.interruptible = false;
2258 ret = i915_gem_object_finish_gpu(obj);
2259 dev_priv->mm.interruptible = was_interruptible;
2260
2261 return ret;
2262}
2263
198598d0
VS		 2264static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2265{
2266 struct drm_device *dev = crtc->dev;
2267 struct drm_i915_master_private *master_priv;
2268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269
2270 if (!dev->primary->master)
2271 return;
2272
2273 master_priv = dev->primary->master->driver_priv;
2274 if (!master_priv->sarea_priv)
2275 return;
2276
2277 switch (intel_crtc->pipe) {
2278 case 0:
2279 master_priv->sarea_priv->pipeA_x = x;
2280 master_priv->sarea_priv->pipeA_y = y;
2281 break;
2282 case 1:
2283 master_priv->sarea_priv->pipeB_x = x;
2284 master_priv->sarea_priv->pipeB_y = y;
2285 break;
2286 default:
2287 break;
2288 }
2289}
2290
5c3b82e2 2291static int
3c4fdcfb 2292intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2293 struct drm_framebuffer *fb)
79e53945
JB		 2294{
2295 struct drm_device *dev = crtc->dev;
6b8e6ed0 2296 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2298 struct drm_framebuffer *old_fb;
5c3b82e2 2299 int ret;
79e53945
JB		 2300
2301 /* no fb bound */
94352cf9 2302 if (!fb) {
a5071c2f 2303 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2304 return 0;
2305 }
2306
5826eca5
ED		 2307 if(intel_crtc->plane > dev_priv->num_pipe) {
2308 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2309 intel_crtc->plane,
2310 dev_priv->num_pipe);
5c3b82e2 2311 return -EINVAL;
79e53945
JB		 2312 }
2313
5c3b82e2 2314 mutex_lock(&dev->struct_mutex);
265db958 2315 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2316 to_intel_framebuffer(fb)->obj,
919926ae 2317 NULL);
5c3b82e2
CW		 2318 if (ret != 0) {
2319 mutex_unlock(&dev->struct_mutex);
a5071c2f 2320 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2321 return ret;
2322 }
79e53945 2323
94352cf9
DV		 2324 if (crtc->fb)
2325 intel_finish_fb(crtc->fb);
265db958 2326
94352cf9 2327 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2328 if (ret) {
94352cf9 2329 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2330 mutex_unlock(&dev->struct_mutex);
a5071c2f 2331 DRM_ERROR("failed to update base address\n");
4e6cfefc 2332 return ret;
79e53945 2333 }
3c4fdcfb 2334
94352cf9
DV		 2335 old_fb = crtc->fb;
2336 crtc->fb = fb;
6c4c86f5
DV		 2337 crtc->x = x;
2338 crtc->y = y;
94352cf9 2339
b7f1de28
CW		 2340 if (old_fb) {
2341 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2342 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2343 }
652c393a 2344
6b8e6ed0 2345 intel_update_fbc(dev);
5c3b82e2 2346 mutex_unlock(&dev->struct_mutex);
79e53945 2347
198598d0 2348 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2349
2350 return 0;
79e53945
JB		 2351}
2352
5eddb70b 2353static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2354{
2355 struct drm_device *dev = crtc->dev;
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357 u32 dpa_ctl;
2358
28c97730 2359 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2360 dpa_ctl = I915_READ(DP_A);
2361 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2362
2363 if (clock < 200000) {
2364 u32 temp;
2365 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2366 /* workaround for 160Mhz:
2367 1) program 0x4600c bits 15:0 = 0x8124
2368 2) program 0x46010 bit 0 = 1
2369 3) program 0x46034 bit 24 = 1
2370 4) program 0x64000 bit 14 = 1
2371 */
2372 temp = I915_READ(0x4600c);
2373 temp &= 0xffff0000;
2374 I915_WRITE(0x4600c, temp | 0x8124);
2375
2376 temp = I915_READ(0x46010);
2377 I915_WRITE(0x46010, temp | 1);
2378
2379 temp = I915_READ(0x46034);
2380 I915_WRITE(0x46034, temp | (1 << 24));
2381 } else {
2382 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2383 }
2384 I915_WRITE(DP_A, dpa_ctl);
2385
5eddb70b 2386 POSTING_READ(DP_A);
32f9d658
ZW		 2387 udelay(500);
2388}
2389
5e84e1a4
ZW		 2390static void intel_fdi_normal_train(struct drm_crtc *crtc)
2391{
2392 struct drm_device *dev = crtc->dev;
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2395 int pipe = intel_crtc->pipe;
2396 u32 reg, temp;
2397
2398 /* enable normal train */
2399 reg = FDI_TX_CTL(pipe);
2400 temp = I915_READ(reg);
61e499bf 2401 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2402 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2403 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2404 } else {
2405 temp &= ~FDI_LINK_TRAIN_NONE;
2406 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2407 }
5e84e1a4
ZW		 2408 I915_WRITE(reg, temp);
2409
2410 reg = FDI_RX_CTL(pipe);
2411 temp = I915_READ(reg);
2412 if (HAS_PCH_CPT(dev)) {
2413 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2414 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2415 } else {
2416 temp &= ~FDI_LINK_TRAIN_NONE;
2417 temp |= FDI_LINK_TRAIN_NONE;
2418 }
2419 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2420
2421 /* wait one idle pattern time */
2422 POSTING_READ(reg);
2423 udelay(1000);
357555c0
JB		 2424
2425 /* IVB wants error correction enabled */
2426 if (IS_IVYBRIDGE(dev))
2427 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2428 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2429}
2430
01a415fd
DV		 2431static void ivb_modeset_global_resources(struct drm_device *dev)
2432{
2433 struct drm_i915_private *dev_priv = dev->dev_private;
2434 struct intel_crtc *pipe_B_crtc =
2435 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2436 struct intel_crtc *pipe_C_crtc =
2437 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2438 uint32_t temp;
2439
2440 /* When everything is off disable fdi C so that we could enable fdi B
2441 * with all lanes. XXX: This misses the case where a pipe is not using
2442 * any pch resources and so doesn't need any fdi lanes. */
2443 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2444 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2445 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2446
2447 temp = I915_READ(SOUTH_CHICKEN1);
2448 temp &= ~FDI_BC_BIFURCATION_SELECT;
2449 DRM_DEBUG_KMS("disabling fdi C rx\n");
2450 I915_WRITE(SOUTH_CHICKEN1, temp);
2451 }
2452}
2453
8db9d77b
ZW		 2454/* The FDI link training functions for ILK/Ibexpeak. */
2455static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2456{
2457 struct drm_device *dev = crtc->dev;
2458 struct drm_i915_private *dev_priv = dev->dev_private;
2459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2460 int pipe = intel_crtc->pipe;
0fc932b8 2461 int plane = intel_crtc->plane;
5eddb70b 2462 u32 reg, temp, tries;
8db9d77b 2463
0fc932b8
JB		 2464 /* FDI needs bits from pipe & plane first */
2465 assert_pipe_enabled(dev_priv, pipe);
2466 assert_plane_enabled(dev_priv, plane);
2467
e1a44743
AJ		 2468 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2469 for train result */
5eddb70b
CW		 2470 reg = FDI_RX_IMR(pipe);
2471 temp = I915_READ(reg);
e1a44743
AJ		 2472 temp &= ~FDI_RX_SYMBOL_LOCK;
2473 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2474 I915_WRITE(reg, temp);
2475 I915_READ(reg);
e1a44743
AJ		 2476 udelay(150);
2477
8db9d77b 2478 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2479 reg = FDI_TX_CTL(pipe);
2480 temp = I915_READ(reg);
77ffb597
AJ		 2481 temp &= ~(7 << 19);
2482 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2483 temp &= ~FDI_LINK_TRAIN_NONE;
2484 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2485 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2486
5eddb70b
CW		 2487 reg = FDI_RX_CTL(pipe);
2488 temp = I915_READ(reg);
8db9d77b
ZW		 2489 temp &= ~FDI_LINK_TRAIN_NONE;
2490 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2491 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2492
2493 POSTING_READ(reg);
8db9d77b
ZW		 2494 udelay(150);
2495
5b2adf89 2496 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2497 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2498 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2499 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2500
5eddb70b 2501 reg = FDI_RX_IIR(pipe);
e1a44743 2502 for (tries = 0; tries < 5; tries++) {
5eddb70b 2503 temp = I915_READ(reg);
8db9d77b
ZW		 2504 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2505
2506 if ((temp & FDI_RX_BIT_LOCK)) {
2507 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2508 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2509 break;
2510 }
8db9d77b 2511 }
e1a44743 2512 if (tries == 5)
5eddb70b 2513 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2514
2515 /* Train 2 */
5eddb70b
CW		 2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
8db9d77b
ZW		 2518 temp &= ~FDI_LINK_TRAIN_NONE;
2519 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2520 I915_WRITE(reg, temp);
8db9d77b 2521
5eddb70b
CW		 2522 reg = FDI_RX_CTL(pipe);
2523 temp = I915_READ(reg);
8db9d77b
ZW		 2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2526 I915_WRITE(reg, temp);
8db9d77b 2527
5eddb70b
CW		 2528 POSTING_READ(reg);
2529 udelay(150);
8db9d77b 2530
5eddb70b 2531 reg = FDI_RX_IIR(pipe);
e1a44743 2532 for (tries = 0; tries < 5; tries++) {
5eddb70b 2533 temp = I915_READ(reg);
8db9d77b
ZW		 2534 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2535
2536 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2537 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2538 DRM_DEBUG_KMS("FDI train 2 done.\n");
2539 break;
2540 }
8db9d77b 2541 }
e1a44743 2542 if (tries == 5)
5eddb70b 2543 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2544
2545 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2546
8db9d77b
ZW		 2547}
2548
0206e353 2549static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2550 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2551 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2552 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2553 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2554};
2555
2556/* The FDI link training functions for SNB/Cougarpoint. */
2557static void gen6_fdi_link_train(struct drm_crtc *crtc)
2558{
2559 struct drm_device *dev = crtc->dev;
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2562 int pipe = intel_crtc->pipe;
fa37d39e 2563 u32 reg, temp, i, retry;
8db9d77b 2564
e1a44743
AJ		 2565 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2566 for train result */
5eddb70b
CW		 2567 reg = FDI_RX_IMR(pipe);
2568 temp = I915_READ(reg);
e1a44743
AJ		 2569 temp &= ~FDI_RX_SYMBOL_LOCK;
2570 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2571 I915_WRITE(reg, temp);
2572
2573 POSTING_READ(reg);
e1a44743
AJ		 2574 udelay(150);
2575
8db9d77b 2576 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2577 reg = FDI_TX_CTL(pipe);
2578 temp = I915_READ(reg);
77ffb597
AJ		 2579 temp &= ~(7 << 19);
2580 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2581 temp &= ~FDI_LINK_TRAIN_NONE;
2582 temp |= FDI_LINK_TRAIN_PATTERN_1;
2583 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2584 /* SNB-B */
2585 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2586 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2587
d74cf324
DV		 2588 I915_WRITE(FDI_RX_MISC(pipe),
2589 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2590
5eddb70b
CW		 2591 reg = FDI_RX_CTL(pipe);
2592 temp = I915_READ(reg);
8db9d77b
ZW		 2593 if (HAS_PCH_CPT(dev)) {
2594 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2595 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2596 } else {
2597 temp &= ~FDI_LINK_TRAIN_NONE;
2598 temp |= FDI_LINK_TRAIN_PATTERN_1;
2599 }
5eddb70b
CW		 2600 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2601
2602 POSTING_READ(reg);
8db9d77b
ZW		 2603 udelay(150);
2604
0206e353 2605 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2606 reg = FDI_TX_CTL(pipe);
2607 temp = I915_READ(reg);
8db9d77b
ZW		 2608 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2609 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
8db9d77b
ZW		 2613 udelay(500);
2614
fa37d39e
SP		 2615 for (retry = 0; retry < 5; retry++) {
2616 reg = FDI_RX_IIR(pipe);
2617 temp = I915_READ(reg);
2618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2619 if (temp & FDI_RX_BIT_LOCK) {
2620 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2621 DRM_DEBUG_KMS("FDI train 1 done.\n");
2622 break;
2623 }
2624 udelay(50);
8db9d77b 2625 }
fa37d39e
SP		 2626 if (retry < 5)
2627 break;
8db9d77b
ZW		 2628 }
2629 if (i == 4)
5eddb70b 2630 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2631
2632 /* Train 2 */
5eddb70b
CW		 2633 reg = FDI_TX_CTL(pipe);
2634 temp = I915_READ(reg);
8db9d77b
ZW		 2635 temp &= ~FDI_LINK_TRAIN_NONE;
2636 temp |= FDI_LINK_TRAIN_PATTERN_2;
2637 if (IS_GEN6(dev)) {
2638 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639 /* SNB-B */
2640 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2641 }
5eddb70b 2642 I915_WRITE(reg, temp);
8db9d77b 2643
5eddb70b
CW		 2644 reg = FDI_RX_CTL(pipe);
2645 temp = I915_READ(reg);
8db9d77b
ZW		 2646 if (HAS_PCH_CPT(dev)) {
2647 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2648 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2649 } else {
2650 temp &= ~FDI_LINK_TRAIN_NONE;
2651 temp |= FDI_LINK_TRAIN_PATTERN_2;
2652 }
5eddb70b
CW		 2653 I915_WRITE(reg, temp);
2654
2655 POSTING_READ(reg);
8db9d77b
ZW		 2656 udelay(150);
2657
0206e353 2658 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2659 reg = FDI_TX_CTL(pipe);
2660 temp = I915_READ(reg);
8db9d77b
ZW		 2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2663 I915_WRITE(reg, temp);
2664
2665 POSTING_READ(reg);
8db9d77b
ZW		 2666 udelay(500);
2667
fa37d39e
SP		 2668 for (retry = 0; retry < 5; retry++) {
2669 reg = FDI_RX_IIR(pipe);
2670 temp = I915_READ(reg);
2671 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2672 if (temp & FDI_RX_SYMBOL_LOCK) {
2673 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2674 DRM_DEBUG_KMS("FDI train 2 done.\n");
2675 break;
2676 }
2677 udelay(50);
8db9d77b 2678 }
fa37d39e
SP		 2679 if (retry < 5)
2680 break;
8db9d77b
ZW		 2681 }
2682 if (i == 4)
5eddb70b 2683 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2684
2685 DRM_DEBUG_KMS("FDI train done.\n");
2686}
2687
357555c0
JB		 2688/* Manual link training for Ivy Bridge A0 parts */
2689static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2690{
2691 struct drm_device *dev = crtc->dev;
2692 struct drm_i915_private *dev_priv = dev->dev_private;
2693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2694 int pipe = intel_crtc->pipe;
2695 u32 reg, temp, i;
2696
2697 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2698 for train result */
2699 reg = FDI_RX_IMR(pipe);
2700 temp = I915_READ(reg);
2701 temp &= ~FDI_RX_SYMBOL_LOCK;
2702 temp &= ~FDI_RX_BIT_LOCK;
2703 I915_WRITE(reg, temp);
2704
2705 POSTING_READ(reg);
2706 udelay(150);
2707
01a415fd
DV		 2708 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2709 I915_READ(FDI_RX_IIR(pipe)));
2710
357555c0
JB		 2711 /* enable CPU FDI TX and PCH FDI RX */
2712 reg = FDI_TX_CTL(pipe);
2713 temp = I915_READ(reg);
2714 temp &= ~(7 << 19);
2715 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2716 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2717 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2718 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2719 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2720 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2721 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2722
d74cf324
DV		 2723 I915_WRITE(FDI_RX_MISC(pipe),
2724 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2725
357555c0
JB		 2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 temp &= ~FDI_LINK_TRAIN_AUTO;
2729 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2730 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2731 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2732 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2733
2734 POSTING_READ(reg);
2735 udelay(150);
2736
0206e353 2737 for (i = 0; i < 4; i++) {
357555c0
JB		 2738 reg = FDI_TX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2741 temp |= snb_b_fdi_train_param[i];
2742 I915_WRITE(reg, temp);
2743
2744 POSTING_READ(reg);
2745 udelay(500);
2746
2747 reg = FDI_RX_IIR(pipe);
2748 temp = I915_READ(reg);
2749 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2750
2751 if (temp & FDI_RX_BIT_LOCK ||
2752 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2753 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2754 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2755 break;
2756 }
2757 }
2758 if (i == 4)
2759 DRM_ERROR("FDI train 1 fail!\n");
2760
2761 /* Train 2 */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2765 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2766 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2767 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2768 I915_WRITE(reg, temp);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2773 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2774 I915_WRITE(reg, temp);
2775
2776 POSTING_READ(reg);
2777 udelay(150);
2778
0206e353 2779 for (i = 0; i < 4; i++) {
357555c0
JB		 2780 reg = FDI_TX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2783 temp |= snb_b_fdi_train_param[i];
2784 I915_WRITE(reg, temp);
2785
2786 POSTING_READ(reg);
2787 udelay(500);
2788
2789 reg = FDI_RX_IIR(pipe);
2790 temp = I915_READ(reg);
2791 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2792
2793 if (temp & FDI_RX_SYMBOL_LOCK) {
2794 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2795 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2796 break;
2797 }
2798 }
2799 if (i == 4)
2800 DRM_ERROR("FDI train 2 fail!\n");
2801
2802 DRM_DEBUG_KMS("FDI train done.\n");
2803}
2804
88cefb6c 2805static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2806{
88cefb6c 2807 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2808 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2809 int pipe = intel_crtc->pipe;
5eddb70b 2810 u32 reg, temp;
79e53945 2811
c64e311e 2812
c98e9dcf 2813 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2817 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2818 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821 POSTING_READ(reg);
c98e9dcf
JB		 2822 udelay(200);
2823
2824 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2825 temp = I915_READ(reg);
2826 I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828 POSTING_READ(reg);
c98e9dcf
JB		 2829 udelay(200);
2830
bf507ef7
ED		 2831 /* On Haswell, the PLL configuration for ports and pipes is handled
2832 * separately, as part of DDI setup */
2833 if (!IS_HASWELL(dev)) {
2834 /* Enable CPU FDI TX PLL, always on for Ironlake */
2835 reg = FDI_TX_CTL(pipe);
2836 temp = I915_READ(reg);
2837 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2839
bf507ef7
ED		 2840 POSTING_READ(reg);
2841 udelay(100);
2842 }
6be4a607 2843 }
0e23b99d
JB		 2844}
2845
88cefb6c
DV		 2846static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847{
2848 struct drm_device *dev = intel_crtc->base.dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 int pipe = intel_crtc->pipe;
2851 u32 reg, temp;
2852
2853 /* Switch from PCDclk to Rawclk */
2854 reg = FDI_RX_CTL(pipe);
2855 temp = I915_READ(reg);
2856 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858 /* Disable CPU FDI TX PLL */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865
2866 reg = FDI_RX_CTL(pipe);
2867 temp = I915_READ(reg);
2868 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870 /* Wait for the clocks to turn off. */
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
0fc932b8
JB		 2875static void ironlake_fdi_disable(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2880 int pipe = intel_crtc->pipe;
2881 u32 reg, temp;
2882
2883 /* disable CPU FDI tx and PCH FDI rx */
2884 reg = FDI_TX_CTL(pipe);
2885 temp = I915_READ(reg);
2886 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2887 POSTING_READ(reg);
2888
2889 reg = FDI_RX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 temp &= ~(0x7 << 16);
2892 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2893 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2894
2895 POSTING_READ(reg);
2896 udelay(100);
2897
2898 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2899 if (HAS_PCH_IBX(dev)) {
2900 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2901 }
0fc932b8
JB		 2902
2903 /* still set train pattern 1 */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908 I915_WRITE(reg, temp);
2909
2910 reg = FDI_RX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 if (HAS_PCH_CPT(dev)) {
2913 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2914 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2915 } else {
2916 temp &= ~FDI_LINK_TRAIN_NONE;
2917 temp |= FDI_LINK_TRAIN_PATTERN_1;
2918 }
2919 /* BPC in FDI rx is consistent with that in PIPECONF */
2920 temp &= ~(0x07 << 16);
2921 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2922 I915_WRITE(reg, temp);
2923
2924 POSTING_READ(reg);
2925 udelay(100);
2926}
2927
5bb61643
CW		 2928static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2929{
2930 struct drm_device *dev = crtc->dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 unsigned long flags;
2933 bool pending;
2934
2935 if (atomic_read(&dev_priv->mm.wedged))
2936 return false;
2937
2938 spin_lock_irqsave(&dev->event_lock, flags);
2939 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2940 spin_unlock_irqrestore(&dev->event_lock, flags);
2941
2942 return pending;
2943}
2944
e6c3a2a6
CW		 2945static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2946{
0f91128d 2947 struct drm_device *dev = crtc->dev;
5bb61643 2948 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2949
2950 if (crtc->fb == NULL)
2951 return;
2952
5bb61643
CW		 2953 wait_event(dev_priv->pending_flip_queue,
2954 !intel_crtc_has_pending_flip(crtc));
2955
0f91128d
CW		 2956 mutex_lock(&dev->struct_mutex);
2957 intel_finish_fb(crtc->fb);
2958 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2959}
2960
fc316cbe 2961static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2962{
2963 struct drm_device *dev = crtc->dev;
228d3e36 2964 struct intel_encoder *intel_encoder;
040484af
JB		 2965
2966 /*
2967 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2968 * must be driven by its own crtc; no sharing is possible.
2969 */
228d3e36 2970 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2971 switch (intel_encoder->type) {
040484af 2972 case INTEL_OUTPUT_EDP:
228d3e36 2973 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2974 return false;
2975 continue;
2976 }
2977 }
2978
2979 return true;
2980}
2981
fc316cbe
PZ		 2982static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2983{
2984 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2985}
2986
e615efe4
ED		 2987/* Program iCLKIP clock to the desired frequency */
2988static void lpt_program_iclkip(struct drm_crtc *crtc)
2989{
2990 struct drm_device *dev = crtc->dev;
2991 struct drm_i915_private *dev_priv = dev->dev_private;
2992 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2993 u32 temp;
2994
2995 /* It is necessary to ungate the pixclk gate prior to programming
2996 * the divisors, and gate it back when it is done.
2997 */
2998 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2999
3000 /* Disable SSCCTL */
3001 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3002 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3003 SBI_SSCCTL_DISABLE,
3004 SBI_ICLK);
e615efe4
ED		 3005
3006 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3007 if (crtc->mode.clock == 20000) {
3008 auxdiv = 1;
3009 divsel = 0x41;
3010 phaseinc = 0x20;
3011 } else {
3012 /* The iCLK virtual clock root frequency is in MHz,
3013 * but the crtc->mode.clock in in KHz. To get the divisors,
3014 * it is necessary to divide one by another, so we
3015 * convert the virtual clock precision to KHz here for higher
3016 * precision.
3017 */
3018 u32 iclk_virtual_root_freq = 172800 * 1000;
3019 u32 iclk_pi_range = 64;
3020 u32 desired_divisor, msb_divisor_value, pi_value;
3021
3022 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3023 msb_divisor_value = desired_divisor / iclk_pi_range;
3024 pi_value = desired_divisor % iclk_pi_range;
3025
3026 auxdiv = 0;
3027 divsel = msb_divisor_value - 2;
3028 phaseinc = pi_value;
3029 }
3030
3031 /* This should not happen with any sane values */
3032 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3033 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3034 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3035 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3036
3037 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3038 crtc->mode.clock,
3039 auxdiv,
3040 divsel,
3041 phasedir,
3042 phaseinc);
3043
3044 /* Program SSCDIVINTPHASE6 */
988d6ee8 3045 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3046 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3047 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3048 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3049 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3050 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3051 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3052 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3053
3054 /* Program SSCAUXDIV */
988d6ee8 3055 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3056 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3057 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3058 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3059
3060 /* Enable modulator and associated divider */
988d6ee8 3061 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3062 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3063 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3064
3065 /* Wait for initialization time */
3066 udelay(24);
3067
3068 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3069}
3070
f67a559d
JB		 3071/*
3072 * Enable PCH resources required for PCH ports:
3073 * - PCH PLLs
3074 * - FDI training & RX/TX
3075 * - update transcoder timings
3076 * - DP transcoding bits
3077 * - transcoder
3078 */
3079static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3080{
3081 struct drm_device *dev = crtc->dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084 int pipe = intel_crtc->pipe;
ee7b9f93 3085 u32 reg, temp;
2c07245f 3086
e7e164db
CW		 3087 assert_transcoder_disabled(dev_priv, pipe);
3088
cd986abb
DV		 3089 /* Write the TU size bits before fdi link training, so that error
3090 * detection works. */
3091 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3092 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3093
c98e9dcf 3094 /* For PCH output, training FDI link */
674cf967 3095 dev_priv->display.fdi_link_train(crtc);
2c07245f 3096
572deb37
DV		 3097 /* XXX: pch pll's can be enabled any time before we enable the PCH
3098 * transcoder, and we actually should do this to not upset any PCH
3099 * transcoder that already use the clock when we share it.
3100 *
3101 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3102 * unconditionally resets the pll - we need that to have the right LVDS
3103 * enable sequence. */
b6b4e185 3104 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3105
303b81e0 3106 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3107 u32 sel;
4b645f14 3108
c98e9dcf 3109 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3110 switch (pipe) {
3111 default:
3112 case 0:
3113 temp |= TRANSA_DPLL_ENABLE;
3114 sel = TRANSA_DPLLB_SEL;
3115 break;
3116 case 1:
3117 temp |= TRANSB_DPLL_ENABLE;
3118 sel = TRANSB_DPLLB_SEL;
3119 break;
3120 case 2:
3121 temp |= TRANSC_DPLL_ENABLE;
3122 sel = TRANSC_DPLLB_SEL;
3123 break;
d64311ab 3124 }
ee7b9f93
JB		 3125 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3126 temp |= sel;
3127 else
3128 temp &= ~sel;
c98e9dcf 3129 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3130 }
5eddb70b 3131
d9b6cb56
JB		 3132 /* set transcoder timing, panel must allow it */
3133 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3134 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3135 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3136 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3137
5eddb70b
CW		 3138 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3139 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3140 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3141 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3142
303b81e0 3143 intel_fdi_normal_train(crtc);
5e84e1a4 3144
c98e9dcf
JB		 3145 /* For PCH DP, enable TRANS_DP_CTL */
3146 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3147 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3148 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3149 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3150 reg = TRANS_DP_CTL(pipe);
3151 temp = I915_READ(reg);
3152 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3153 TRANS_DP_SYNC_MASK |
3154 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3155 temp |= (TRANS_DP_OUTPUT_ENABLE |
3156 TRANS_DP_ENH_FRAMING);
9325c9f0 3157 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3158
3159 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3160 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3161 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3162 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3163
3164 switch (intel_trans_dp_port_sel(crtc)) {
3165 case PCH_DP_B:
5eddb70b 3166 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3167 break;
3168 case PCH_DP_C:
5eddb70b 3169 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3170 break;
3171 case PCH_DP_D:
5eddb70b 3172 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3173 break;
3174 default:
e95d41e1 3175 BUG();
32f9d658 3176 }
2c07245f 3177
5eddb70b 3178 I915_WRITE(reg, temp);
6be4a607 3179 }
b52eb4dc 3180
b8a4f404 3181 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3182}
3183
1507e5bd
PZ		 3184static void lpt_pch_enable(struct drm_crtc *crtc)
3185{
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3189 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3190
daed2dbb 3191 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3192
8c52b5e8 3193 lpt_program_iclkip(crtc);
1507e5bd 3194
0540e488 3195 /* Set transcoder timing. */
daed2dbb
PZ		 3196 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3197 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3198 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3199
daed2dbb
PZ		 3200 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3201 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3202 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3203 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3204
937bb610 3205 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3206}
3207
ee7b9f93
JB		 3208static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3209{
3210 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3211
3212 if (pll == NULL)
3213 return;
3214
3215 if (pll->refcount == 0) {
3216 WARN(1, "bad PCH PLL refcount\n");
3217 return;
3218 }
3219
3220 --pll->refcount;
3221 intel_crtc->pch_pll = NULL;
3222}
3223
3224static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3225{
3226 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3227 struct intel_pch_pll *pll;
3228 int i;
3229
3230 pll = intel_crtc->pch_pll;
3231 if (pll) {
3232 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3233 intel_crtc->base.base.id, pll->pll_reg);
3234 goto prepare;
3235 }
3236
98b6bd99
DV		 3237 if (HAS_PCH_IBX(dev_priv->dev)) {
3238 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3239 i = intel_crtc->pipe;
3240 pll = &dev_priv->pch_plls[i];
3241
3242 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3243 intel_crtc->base.base.id, pll->pll_reg);
3244
3245 goto found;
3246 }
3247
ee7b9f93
JB		 3248 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3249 pll = &dev_priv->pch_plls[i];
3250
3251 /* Only want to check enabled timings first */
3252 if (pll->refcount == 0)
3253 continue;
3254
3255 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3256 fp == I915_READ(pll->fp0_reg)) {
3257 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3258 intel_crtc->base.base.id,
3259 pll->pll_reg, pll->refcount, pll->active);
3260
3261 goto found;
3262 }
3263 }
3264
3265 /* Ok no matching timings, maybe there's a free one? */
3266 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3267 pll = &dev_priv->pch_plls[i];
3268 if (pll->refcount == 0) {
3269 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3270 intel_crtc->base.base.id, pll->pll_reg);
3271 goto found;
3272 }
3273 }
3274
3275 return NULL;
3276
3277found:
3278 intel_crtc->pch_pll = pll;
3279 pll->refcount++;
3280 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3281prepare: /* separate function? */
3282 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3283
e04c7350
CW		 3284 /* Wait for the clocks to stabilize before rewriting the regs */
3285 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3286 POSTING_READ(pll->pll_reg);
3287 udelay(150);
e04c7350
CW		 3288
3289 I915_WRITE(pll->fp0_reg, fp);
3290 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3291 pll->on = false;
3292 return pll;
3293}
3294
d4270e57
JB		 3295void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3296{
3297 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3298 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3299 u32 temp;
3300
3301 temp = I915_READ(dslreg);
3302 udelay(500);
3303 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3304 if (wait_for(I915_READ(dslreg) != temp, 5))
3305 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3306 }
3307}
3308
f67a559d
JB		 3309static void ironlake_crtc_enable(struct drm_crtc *crtc)
3310{
3311 struct drm_device *dev = crtc->dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3314 struct intel_encoder *encoder;
f67a559d
JB		 3315 int pipe = intel_crtc->pipe;
3316 int plane = intel_crtc->plane;
3317 u32 temp;
3318 bool is_pch_port;
3319
08a48469
DV		 3320 WARN_ON(!crtc->enabled);
3321
f67a559d
JB		 3322 if (intel_crtc->active)
3323 return;
3324
3325 intel_crtc->active = true;
3326 intel_update_watermarks(dev);
3327
3328 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3329 temp = I915_READ(PCH_LVDS);
3330 if ((temp & LVDS_PORT_EN) == 0)
3331 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3332 }
3333
fc316cbe 3334 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3335
46b6f814 3336 if (is_pch_port) {
fff367c7
DV		 3337 /* Note: FDI PLL enabling _must_ be done before we enable the
3338 * cpu pipes, hence this is separate from all the other fdi/pch
3339 * enabling. */
88cefb6c 3340 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3341 } else {
3342 assert_fdi_tx_disabled(dev_priv, pipe);
3343 assert_fdi_rx_disabled(dev_priv, pipe);
3344 }
f67a559d 3345
bf49ec8c
DV		 3346 for_each_encoder_on_crtc(dev, crtc, encoder)
3347 if (encoder->pre_enable)
3348 encoder->pre_enable(encoder);
f67a559d
JB		 3349
3350 /* Enable panel fitting for LVDS */
3351 if (dev_priv->pch_pf_size &&
547dc041
JN		 3352 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3353 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3354 /* Force use of hard-coded filter coefficients
3355 * as some pre-programmed values are broken,
3356 * e.g. x201.
3357 */
13888d78
PZ		 3358 if (IS_IVYBRIDGE(dev))
3359 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3360 PF_PIPE_SEL_IVB(pipe));
3361 else
3362 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3363 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3364 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3365 }
3366
9c54c0dd
JB		 3367 /*
3368 * On ILK+ LUT must be loaded before the pipe is running but with
3369 * clocks enabled
3370 */
3371 intel_crtc_load_lut(crtc);
3372
f67a559d
JB		 3373 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3374 intel_enable_plane(dev_priv, plane, pipe);
3375
3376 if (is_pch_port)
3377 ironlake_pch_enable(crtc);
c98e9dcf 3378
d1ebd816 3379 mutex_lock(&dev->struct_mutex);
bed4a673 3380 intel_update_fbc(dev);
d1ebd816
BW		 3381 mutex_unlock(&dev->struct_mutex);
3382
6b383a7f 3383 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3384
fa5c73b1
DV		 3385 for_each_encoder_on_crtc(dev, crtc, encoder)
3386 encoder->enable(encoder);
61b77ddd
DV		 3387
3388 if (HAS_PCH_CPT(dev))
3389 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3390
3391 /*
3392 * There seems to be a race in PCH platform hw (at least on some
3393 * outputs) where an enabled pipe still completes any pageflip right
3394 * away (as if the pipe is off) instead of waiting for vblank. As soon
3395 * as the first vblank happend, everything works as expected. Hence just
3396 * wait for one vblank before returning to avoid strange things
3397 * happening.
3398 */
3399 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3400}
3401
4f771f10
PZ		 3402static void haswell_crtc_enable(struct drm_crtc *crtc)
3403{
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407 struct intel_encoder *encoder;
3408 int pipe = intel_crtc->pipe;
3409 int plane = intel_crtc->plane;
4f771f10
PZ		 3410 bool is_pch_port;
3411
3412 WARN_ON(!crtc->enabled);
3413
3414 if (intel_crtc->active)
3415 return;
3416
3417 intel_crtc->active = true;
3418 intel_update_watermarks(dev);
3419
fc316cbe 3420 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3421
83616634 3422 if (is_pch_port)
04945641 3423 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3424
3425 for_each_encoder_on_crtc(dev, crtc, encoder)
3426 if (encoder->pre_enable)
3427 encoder->pre_enable(encoder);
3428
1f544388 3429 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3430
1f544388 3431 /* Enable panel fitting for eDP */
547dc041
JN		 3432 if (dev_priv->pch_pf_size &&
3433 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3434 /* Force use of hard-coded filter coefficients
3435 * as some pre-programmed values are broken,
3436 * e.g. x201.
3437 */
54075a7d
PZ		 3438 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3439 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3440 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3441 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3442 }
3443
3444 /*
3445 * On ILK+ LUT must be loaded before the pipe is running but with
3446 * clocks enabled
3447 */
3448 intel_crtc_load_lut(crtc);
3449
1f544388
PZ		 3450 intel_ddi_set_pipe_settings(crtc);
3451 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3452
3453 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3454 intel_enable_plane(dev_priv, plane, pipe);
3455
3456 if (is_pch_port)
1507e5bd 3457 lpt_pch_enable(crtc);
4f771f10
PZ		 3458
3459 mutex_lock(&dev->struct_mutex);
3460 intel_update_fbc(dev);
3461 mutex_unlock(&dev->struct_mutex);
3462
3463 intel_crtc_update_cursor(crtc, true);
3464
3465 for_each_encoder_on_crtc(dev, crtc, encoder)
3466 encoder->enable(encoder);
3467
4f771f10
PZ		 3468 /*
3469 * There seems to be a race in PCH platform hw (at least on some
3470 * outputs) where an enabled pipe still completes any pageflip right
3471 * away (as if the pipe is off) instead of waiting for vblank. As soon
3472 * as the first vblank happend, everything works as expected. Hence just
3473 * wait for one vblank before returning to avoid strange things
3474 * happening.
3475 */
3476 intel_wait_for_vblank(dev, intel_crtc->pipe);
3477}
3478
6be4a607
JB		 3479static void ironlake_crtc_disable(struct drm_crtc *crtc)
3480{
3481 struct drm_device *dev = crtc->dev;
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3484 struct intel_encoder *encoder;
6be4a607
JB		 3485 int pipe = intel_crtc->pipe;
3486 int plane = intel_crtc->plane;
5eddb70b 3487 u32 reg, temp;
b52eb4dc 3488
ef9c3aee 3489
f7abfe8b
CW		 3490 if (!intel_crtc->active)
3491 return;
3492
ea9d758d
DV		 3493 for_each_encoder_on_crtc(dev, crtc, encoder)
3494 encoder->disable(encoder);
3495
e6c3a2a6 3496 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3497 drm_vblank_off(dev, pipe);
6b383a7f 3498 intel_crtc_update_cursor(crtc, false);
5eddb70b 3499
b24e7179 3500 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3501
973d04f9
CW		 3502 if (dev_priv->cfb_plane == plane)
3503 intel_disable_fbc(dev);
2c07245f 3504
b24e7179 3505 intel_disable_pipe(dev_priv, pipe);
32f9d658 3506
6be4a607 3507 /* Disable PF */
9db4a9c7
JB		 3508 I915_WRITE(PF_CTL(pipe), 0);
3509 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3510
bf49ec8c
DV		 3511 for_each_encoder_on_crtc(dev, crtc, encoder)
3512 if (encoder->post_disable)
3513 encoder->post_disable(encoder);
2c07245f 3514
0fc932b8 3515 ironlake_fdi_disable(crtc);
249c0e64 3516
b8a4f404 3517 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3518
6be4a607
JB		 3519 if (HAS_PCH_CPT(dev)) {
3520 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3521 reg = TRANS_DP_CTL(pipe);
3522 temp = I915_READ(reg);
3523 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3524 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3525 I915_WRITE(reg, temp);
6be4a607
JB		 3526
3527 /* disable DPLL_SEL */
3528 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3529 switch (pipe) {
3530 case 0:
d64311ab 3531 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3532 break;
3533 case 1:
6be4a607 3534 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3535 break;
3536 case 2:
4b645f14 3537 /* C shares PLL A or B */
d64311ab 3538 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3539 break;
3540 default:
3541 BUG(); /* wtf */
3542 }
6be4a607 3543 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3544 }
e3421a18 3545
6be4a607 3546 /* disable PCH DPLL */
ee7b9f93 3547 intel_disable_pch_pll(intel_crtc);
8db9d77b 3548
88cefb6c 3549 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3550
f7abfe8b 3551 intel_crtc->active = false;
6b383a7f 3552 intel_update_watermarks(dev);
d1ebd816
BW		 3553
3554 mutex_lock(&dev->struct_mutex);
6b383a7f 3555 intel_update_fbc(dev);
d1ebd816 3556 mutex_unlock(&dev->struct_mutex);
6be4a607 3557}
1b3c7a47 3558
4f771f10 3559static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3560{
4f771f10
PZ		 3561 struct drm_device *dev = crtc->dev;
3562 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3564 struct intel_encoder *encoder;
3565 int pipe = intel_crtc->pipe;
3566 int plane = intel_crtc->plane;
ad80a810 3567 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3568 bool is_pch_port;
ee7b9f93 3569
4f771f10
PZ		 3570 if (!intel_crtc->active)
3571 return;
3572
83616634
PZ		 3573 is_pch_port = haswell_crtc_driving_pch(crtc);
3574
4f771f10
PZ		 3575 for_each_encoder_on_crtc(dev, crtc, encoder)
3576 encoder->disable(encoder);
3577
3578 intel_crtc_wait_for_pending_flips(crtc);
3579 drm_vblank_off(dev, pipe);
3580 intel_crtc_update_cursor(crtc, false);
3581
3582 intel_disable_plane(dev_priv, plane, pipe);
3583
3584 if (dev_priv->cfb_plane == plane)
3585 intel_disable_fbc(dev);
3586
3587 intel_disable_pipe(dev_priv, pipe);
3588
ad80a810 3589 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3590
3591 /* Disable PF */
3592 I915_WRITE(PF_CTL(pipe), 0);
3593 I915_WRITE(PF_WIN_SZ(pipe), 0);
3594
1f544388 3595 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3596
3597 for_each_encoder_on_crtc(dev, crtc, encoder)
3598 if (encoder->post_disable)
3599 encoder->post_disable(encoder);
3600
83616634 3601 if (is_pch_port) {
ab4d966c 3602 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3603 intel_ddi_fdi_disable(crtc);
83616634 3604 }
4f771f10
PZ		 3605
3606 intel_crtc->active = false;
3607 intel_update_watermarks(dev);
3608
3609 mutex_lock(&dev->struct_mutex);
3610 intel_update_fbc(dev);
3611 mutex_unlock(&dev->struct_mutex);
3612}
3613
ee7b9f93
JB		 3614static void ironlake_crtc_off(struct drm_crtc *crtc)
3615{
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 intel_put_pch_pll(intel_crtc);
3618}
3619
6441ab5f
PZ		 3620static void haswell_crtc_off(struct drm_crtc *crtc)
3621{
a5c961d1
PZ		 3622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3623
3624 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3625 * start using it. */
3626 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3627
6441ab5f
PZ		 3628 intel_ddi_put_crtc_pll(crtc);
3629}
3630
02e792fb
DV		 3631static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3632{
02e792fb 3633 if (!enable && intel_crtc->overlay) {
23f09ce3 3634 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3635 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3636
23f09ce3 3637 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3638 dev_priv->mm.interruptible = false;
3639 (void) intel_overlay_switch_off(intel_crtc->overlay);
3640 dev_priv->mm.interruptible = true;
23f09ce3 3641 mutex_unlock(&dev->struct_mutex);
02e792fb 3642 }
02e792fb 3643
5dcdbcb0
CW		 3644 /* Let userspace switch the overlay on again. In most cases userspace
3645 * has to recompute where to put it anyway.
3646 */
02e792fb
DV		 3647}
3648
0b8765c6 3649static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3650{
3651 struct drm_device *dev = crtc->dev;
79e53945
JB		 3652 struct drm_i915_private *dev_priv = dev->dev_private;
3653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3654 struct intel_encoder *encoder;
79e53945 3655 int pipe = intel_crtc->pipe;
80824003 3656 int plane = intel_crtc->plane;
79e53945 3657
08a48469
DV		 3658 WARN_ON(!crtc->enabled);
3659
f7abfe8b
CW		 3660 if (intel_crtc->active)
3661 return;
3662
3663 intel_crtc->active = true;
6b383a7f
CW		 3664 intel_update_watermarks(dev);
3665
63d7bbe9 3666 intel_enable_pll(dev_priv, pipe);
040484af 3667 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3668 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3669
0b8765c6 3670 intel_crtc_load_lut(crtc);
bed4a673 3671 intel_update_fbc(dev);
79e53945 3672
0b8765c6
JB		 3673 /* Give the overlay scaler a chance to enable if it's on this pipe */
3674 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3675 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3676
fa5c73b1
DV		 3677 for_each_encoder_on_crtc(dev, crtc, encoder)
3678 encoder->enable(encoder);
0b8765c6 3679}
79e53945 3680
0b8765c6
JB		 3681static void i9xx_crtc_disable(struct drm_crtc *crtc)
3682{
3683 struct drm_device *dev = crtc->dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3686 struct intel_encoder *encoder;
0b8765c6
JB		 3687 int pipe = intel_crtc->pipe;
3688 int plane = intel_crtc->plane;
b690e96c 3689
ef9c3aee 3690
f7abfe8b
CW		 3691 if (!intel_crtc->active)
3692 return;
3693
ea9d758d
DV		 3694 for_each_encoder_on_crtc(dev, crtc, encoder)
3695 encoder->disable(encoder);
3696
0b8765c6 3697 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3698 intel_crtc_wait_for_pending_flips(crtc);
3699 drm_vblank_off(dev, pipe);
0b8765c6 3700 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3701 intel_crtc_update_cursor(crtc, false);
0b8765c6 3702
973d04f9
CW		 3703 if (dev_priv->cfb_plane == plane)
3704 intel_disable_fbc(dev);
79e53945 3705
b24e7179 3706 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3707 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3708 intel_disable_pll(dev_priv, pipe);
0b8765c6 3709
f7abfe8b 3710 intel_crtc->active = false;
6b383a7f
CW		 3711 intel_update_fbc(dev);
3712 intel_update_watermarks(dev);
0b8765c6
JB		 3713}
3714
ee7b9f93
JB		 3715static void i9xx_crtc_off(struct drm_crtc *crtc)
3716{
3717}
3718
976f8a20
DV		 3719static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3720 bool enabled)
2c07245f
ZW		 3721{
3722 struct drm_device *dev = crtc->dev;
3723 struct drm_i915_master_private *master_priv;
3724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3725 int pipe = intel_crtc->pipe;
79e53945
JB		 3726
3727 if (!dev->primary->master)
3728 return;
3729
3730 master_priv = dev->primary->master->driver_priv;
3731 if (!master_priv->sarea_priv)
3732 return;
3733
79e53945
JB		 3734 switch (pipe) {
3735 case 0:
3736 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3737 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3738 break;
3739 case 1:
3740 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3741 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3742 break;
3743 default:
9db4a9c7 3744 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3745 break;
3746 }
79e53945
JB		 3747}
3748
976f8a20
DV		 3749/**
3750 * Sets the power management mode of the pipe and plane.
3751 */
3752void intel_crtc_update_dpms(struct drm_crtc *crtc)
3753{
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct intel_encoder *intel_encoder;
3757 bool enable = false;
3758
3759 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3760 enable |= intel_encoder->connectors_active;
3761
3762 if (enable)
3763 dev_priv->display.crtc_enable(crtc);
3764 else
3765 dev_priv->display.crtc_disable(crtc);
3766
3767 intel_crtc_update_sarea(crtc, enable);
3768}
3769
3770static void intel_crtc_noop(struct drm_crtc *crtc)
3771{
3772}
3773
cdd59983
CW		 3774static void intel_crtc_disable(struct drm_crtc *crtc)
3775{
cdd59983 3776 struct drm_device *dev = crtc->dev;
976f8a20 3777 struct drm_connector *connector;
ee7b9f93 3778 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3779
976f8a20
DV		 3780 /* crtc should still be enabled when we disable it. */
3781 WARN_ON(!crtc->enabled);
3782
3783 dev_priv->display.crtc_disable(crtc);
3784 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3785 dev_priv->display.off(crtc);
3786
931872fc
CW		 3787 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3788 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3789
3790 if (crtc->fb) {
3791 mutex_lock(&dev->struct_mutex);
1690e1eb 3792 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3793 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3794 crtc->fb = NULL;
3795 }
3796
3797 /* Update computed state. */
3798 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3799 if (!connector->encoder || !connector->encoder->crtc)
3800 continue;
3801
3802 if (connector->encoder->crtc != crtc)
3803 continue;
3804
3805 connector->dpms = DRM_MODE_DPMS_OFF;
3806 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3807 }
3808}
3809
a261b246 3810void intel_modeset_disable(struct drm_device *dev)
79e53945 3811{
a261b246
DV		 3812 struct drm_crtc *crtc;
3813
3814 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3815 if (crtc->enabled)
3816 intel_crtc_disable(crtc);
3817 }
79e53945
JB		 3818}
3819
1f703855 3820void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3821{
7e7d76c3
JB		 3822}
3823
ea5b213a 3824void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3825{
4ef69c7a 3826 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3827
ea5b213a
CW		 3828 drm_encoder_cleanup(encoder);
3829 kfree(intel_encoder);
7e7d76c3
JB		 3830}
3831
5ab432ef
DV		 3832/* Simple dpms helper for encodres with just one connector, no cloning and only
3833 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3834 * state of the entire output pipe. */
3835void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3836{
5ab432ef
DV		 3837 if (mode == DRM_MODE_DPMS_ON) {
3838 encoder->connectors_active = true;
3839
b2cabb0e 3840 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3841 } else {
3842 encoder->connectors_active = false;
3843
b2cabb0e 3844 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3845 }
79e53945
JB		 3846}
3847
0a91ca29
DV		 3848/* Cross check the actual hw state with our own modeset state tracking (and it's
3849 * internal consistency). */
b980514c 3850static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3851{
0a91ca29
DV		 3852 if (connector->get_hw_state(connector)) {
3853 struct intel_encoder *encoder = connector->encoder;
3854 struct drm_crtc *crtc;
3855 bool encoder_enabled;
3856 enum pipe pipe;
3857
3858 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3859 connector->base.base.id,
3860 drm_get_connector_name(&connector->base));
3861
3862 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3863 "wrong connector dpms state\n");
3864 WARN(connector->base.encoder != &encoder->base,
3865 "active connector not linked to encoder\n");
3866 WARN(!encoder->connectors_active,
3867 "encoder->connectors_active not set\n");
3868
3869 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3870 WARN(!encoder_enabled, "encoder not enabled\n");
3871 if (WARN_ON(!encoder->base.crtc))
3872 return;
3873
3874 crtc = encoder->base.crtc;
3875
3876 WARN(!crtc->enabled, "crtc not enabled\n");
3877 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3878 WARN(pipe != to_intel_crtc(crtc)->pipe,
3879 "encoder active on the wrong pipe\n");
3880 }
79e53945
JB		 3881}
3882
5ab432ef
DV		 3883/* Even simpler default implementation, if there's really no special case to
3884 * consider. */
3885void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3886{
5ab432ef 3887 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3888
5ab432ef
DV		 3889 /* All the simple cases only support two dpms states. */
3890 if (mode != DRM_MODE_DPMS_ON)
3891 mode = DRM_MODE_DPMS_OFF;
d4270e57 3892
5ab432ef
DV		 3893 if (mode == connector->dpms)
3894 return;
3895
3896 connector->dpms = mode;
3897
3898 /* Only need to change hw state when actually enabled */
3899 if (encoder->base.crtc)
3900 intel_encoder_dpms(encoder, mode);
3901 else
8af6cf88 3902 WARN_ON(encoder->connectors_active != false);
0a91ca29 3903
b980514c 3904 intel_modeset_check_state(connector->dev);
79e53945
JB		 3905}
3906
f0947c37
DV		 3907/* Simple connector->get_hw_state implementation for encoders that support only
3908 * one connector and no cloning and hence the encoder state determines the state
3909 * of the connector. */
3910bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3911{
24929352 3912 enum pipe pipe = 0;
f0947c37 3913 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3914
f0947c37 3915 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3916}
3917
79e53945 3918static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3919 const struct drm_display_mode *mode,
79e53945
JB		 3920 struct drm_display_mode *adjusted_mode)
3921{
2c07245f 3922 struct drm_device *dev = crtc->dev;
89749350 3923
bad720ff 3924 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3925 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3926 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3927 return false;
2c07245f 3928 }
89749350 3929
f9bef081
DV		 3930 /* All interlaced capable intel hw wants timings in frames. Note though
3931 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3932 * timings, so we need to be careful not to clobber these.*/
3933 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3934 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3935
44f46b42
CW		 3936 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3937 * with a hsync front porch of 0.
3938 */
3939 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3940 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3941 return false;
3942
79e53945
JB		 3943 return true;
3944}
3945
25eb05fc
JB		 3946static int valleyview_get_display_clock_speed(struct drm_device *dev)
3947{
3948 return 400000; /* FIXME */
3949}
3950
e70236a8
JB		 3951static int i945_get_display_clock_speed(struct drm_device *dev)
3952{
3953 return 400000;
3954}
79e53945 3955
e70236a8 3956static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3957{
e70236a8
JB		 3958 return 333000;
3959}
79e53945 3960
e70236a8
JB		 3961static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3962{
3963 return 200000;
3964}
79e53945 3965
e70236a8
JB		 3966static int i915gm_get_display_clock_speed(struct drm_device *dev)
3967{
3968 u16 gcfgc = 0;
79e53945 3969
e70236a8
JB		 3970 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3971
3972 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3973 return 133000;
3974 else {
3975 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3976 case GC_DISPLAY_CLOCK_333_MHZ:
3977 return 333000;
3978 default:
3979 case GC_DISPLAY_CLOCK_190_200_MHZ:
3980 return 190000;
79e53945 3981 }
e70236a8
JB		 3982 }
3983}
3984
3985static int i865_get_display_clock_speed(struct drm_device *dev)
3986{
3987 return 266000;
3988}
3989
3990static int i855_get_display_clock_speed(struct drm_device *dev)
3991{
3992 u16 hpllcc = 0;
3993 /* Assume that the hardware is in the high speed state. This
3994 * should be the default.
3995 */
3996 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3997 case GC_CLOCK_133_200:
3998 case GC_CLOCK_100_200:
3999 return 200000;
4000 case GC_CLOCK_166_250:
4001 return 250000;
4002 case GC_CLOCK_100_133:
79e53945 4003 return 133000;
e70236a8 4004 }
79e53945 4005
e70236a8
JB		 4006 /* Shouldn't happen */
4007 return 0;
4008}
79e53945 4009
e70236a8
JB		 4010static int i830_get_display_clock_speed(struct drm_device *dev)
4011{
4012 return 133000;
79e53945
JB		 4013}
4014
2c07245f
ZW		 4015struct fdi_m_n {
4016 u32 tu;
4017 u32 gmch_m;
4018 u32 gmch_n;
4019 u32 link_m;
4020 u32 link_n;
4021};
4022
4023static void
4024fdi_reduce_ratio(u32 *num, u32 *den)
4025{
4026 while (*num > 0xffffff || *den > 0xffffff) {
4027 *num >>= 1;
4028 *den >>= 1;
4029 }
4030}
4031
2c07245f 4032static void
f2b115e6
AJ		 4033ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4034 int link_clock, struct fdi_m_n *m_n)
2c07245f 4035{
2c07245f
ZW		 4036 m_n->tu = 64; /* default size */
4037
22ed1113
CW		 4038 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4039 m_n->gmch_m = bits_per_pixel * pixel_clock;
4040 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4041 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4042
22ed1113
CW		 4043 m_n->link_m = pixel_clock;
4044 m_n->link_n = link_clock;
2c07245f
ZW		 4045 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4046}
4047
a7615030
CW		 4048static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4049{
72bbe58c
KP		 4050 if (i915_panel_use_ssc >= 0)
4051 return i915_panel_use_ssc != 0;
4052 return dev_priv->lvds_use_ssc
435793df 4053 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4054}
4055
5a354204
JB		 4056/**
4057 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4058 * @crtc: CRTC structure
3b5c78a3 4059 * @mode: requested mode
5a354204
JB		 4060 *
4061 * A pipe may be connected to one or more outputs. Based on the depth of the
4062 * attached framebuffer, choose a good color depth to use on the pipe.
4063 *
4064 * If possible, match the pipe depth to the fb depth. In some cases, this
4065 * isn't ideal, because the connected output supports a lesser or restricted
4066 * set of depths. Resolve that here:
4067 * LVDS typically supports only 6bpc, so clamp down in that case
4068 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4069 * Displays may support a restricted set as well, check EDID and clamp as
4070 * appropriate.
3b5c78a3 4071 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4072 *
4073 * RETURNS:
4074 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4075 * true if they don't match).
4076 */
4077static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4078 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4079 unsigned int *pipe_bpp,
4080 struct drm_display_mode *mode)
5a354204
JB		 4081{
4082 struct drm_device *dev = crtc->dev;
4083 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4084 struct drm_connector *connector;
6c2b7c12 4085 struct intel_encoder *intel_encoder;
5a354204
JB		 4086 unsigned int display_bpc = UINT_MAX, bpc;
4087
4088 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4089 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4090
4091 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4092 unsigned int lvds_bpc;
4093
4094 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4095 LVDS_A3_POWER_UP)
4096 lvds_bpc = 8;
4097 else
4098 lvds_bpc = 6;
4099
4100 if (lvds_bpc < display_bpc) {
82820490 4101 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4102 display_bpc = lvds_bpc;
4103 }
4104 continue;
4105 }
4106
5a354204
JB		 4107 /* Not one of the known troublemakers, check the EDID */
4108 list_for_each_entry(connector, &dev->mode_config.connector_list,
4109 head) {
6c2b7c12 4110 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4111 continue;
4112
62ac41a6
JB		 4113 /* Don't use an invalid EDID bpc value */
4114 if (connector->display_info.bpc &&
4115 connector->display_info.bpc < display_bpc) {
82820490 4116 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4117 display_bpc = connector->display_info.bpc;
4118 }
4119 }
4120
4121 /*
4122 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4123 * through, clamp it down. (Note: >12bpc will be caught below.)
4124 */
4125 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4126 if (display_bpc > 8 && display_bpc < 12) {
82820490 4127 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4128 display_bpc = 12;
4129 } else {
82820490 4130 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4131 display_bpc = 8;
4132 }
4133 }
4134 }
4135
3b5c78a3
AJ		 4136 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4137 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4138 display_bpc = 6;
4139 }
4140
5a354204
JB		 4141 /*
4142 * We could just drive the pipe at the highest bpc all the time and
4143 * enable dithering as needed, but that costs bandwidth. So choose
4144 * the minimum value that expresses the full color range of the fb but
4145 * also stays within the max display bpc discovered above.
4146 */
4147
94352cf9 4148 switch (fb->depth) {
5a354204
JB		 4149 case 8:
4150 bpc = 8; /* since we go through a colormap */
4151 break;
4152 case 15:
4153 case 16:
4154 bpc = 6; /* min is 18bpp */
4155 break;
4156 case 24:
578393cd 4157 bpc = 8;
5a354204
JB		 4158 break;
4159 case 30:
578393cd 4160 bpc = 10;
5a354204
JB		 4161 break;
4162 case 48:
578393cd 4163 bpc = 12;
5a354204
JB		 4164 break;
4165 default:
4166 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4167 bpc = min((unsigned int)8, display_bpc);
4168 break;
4169 }
4170
578393cd
KP		 4171 display_bpc = min(display_bpc, bpc);
4172
82820490
AJ		 4173 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4174 bpc, display_bpc);
5a354204 4175
578393cd 4176 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4177
4178 return display_bpc != bpc;
4179}
4180
a0c4da24
JB		 4181static int vlv_get_refclk(struct drm_crtc *crtc)
4182{
4183 struct drm_device *dev = crtc->dev;
4184 struct drm_i915_private *dev_priv = dev->dev_private;
4185 int refclk = 27000; /* for DP & HDMI */
4186
4187 return 100000; /* only one validated so far */
4188
4189 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4190 refclk = 96000;
4191 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4192 if (intel_panel_use_ssc(dev_priv))
4193 refclk = 100000;
4194 else
4195 refclk = 96000;
4196 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4197 refclk = 100000;
4198 }
4199
4200 return refclk;
4201}
4202
c65d77d8
JB		 4203static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4204{
4205 struct drm_device *dev = crtc->dev;
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4207 int refclk;
4208
a0c4da24
JB		 4209 if (IS_VALLEYVIEW(dev)) {
4210 refclk = vlv_get_refclk(crtc);
4211 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4212 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4213 refclk = dev_priv->lvds_ssc_freq * 1000;
4214 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4215 refclk / 1000);
4216 } else if (!IS_GEN2(dev)) {
4217 refclk = 96000;
4218 } else {
4219 refclk = 48000;
4220 }
4221
4222 return refclk;
4223}
4224
4225static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4226 intel_clock_t *clock)
4227{
4228 /* SDVO TV has fixed PLL values depend on its clock range,
4229 this mirrors vbios setting. */
4230 if (adjusted_mode->clock >= 100000
4231 && adjusted_mode->clock < 140500) {
4232 clock->p1 = 2;
4233 clock->p2 = 10;
4234 clock->n = 3;
4235 clock->m1 = 16;
4236 clock->m2 = 8;
4237 } else if (adjusted_mode->clock >= 140500
4238 && adjusted_mode->clock <= 200000) {
4239 clock->p1 = 1;
4240 clock->p2 = 10;
4241 clock->n = 6;
4242 clock->m1 = 12;
4243 clock->m2 = 8;
4244 }
4245}
4246
a7516a05
JB		 4247static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4248 intel_clock_t *clock,
4249 intel_clock_t *reduced_clock)
4250{
4251 struct drm_device *dev = crtc->dev;
4252 struct drm_i915_private *dev_priv = dev->dev_private;
4253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4254 int pipe = intel_crtc->pipe;
4255 u32 fp, fp2 = 0;
4256
4257 if (IS_PINEVIEW(dev)) {
4258 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4259 if (reduced_clock)
4260 fp2 = (1 << reduced_clock->n) << 16 |
4261 reduced_clock->m1 << 8 | reduced_clock->m2;
4262 } else {
4263 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4264 if (reduced_clock)
4265 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4266 reduced_clock->m2;
4267 }
4268
4269 I915_WRITE(FP0(pipe), fp);
4270
4271 intel_crtc->lowfreq_avail = false;
4272 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4273 reduced_clock && i915_powersave) {
4274 I915_WRITE(FP1(pipe), fp2);
4275 intel_crtc->lowfreq_avail = true;
4276 } else {
4277 I915_WRITE(FP1(pipe), fp);
4278 }
4279}
4280
93e537a1
DV		 4281static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4282 struct drm_display_mode *adjusted_mode)
4283{
4284 struct drm_device *dev = crtc->dev;
4285 struct drm_i915_private *dev_priv = dev->dev_private;
4286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4287 int pipe = intel_crtc->pipe;
284d5df5 4288 u32 temp;
93e537a1
DV		 4289
4290 temp = I915_READ(LVDS);
4291 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4292 if (pipe == 1) {
4293 temp |= LVDS_PIPEB_SELECT;
4294 } else {
4295 temp &= ~LVDS_PIPEB_SELECT;
4296 }
4297 /* set the corresponsding LVDS_BORDER bit */
4298 temp |= dev_priv->lvds_border_bits;
4299 /* Set the B0-B3 data pairs corresponding to whether we're going to
4300 * set the DPLLs for dual-channel mode or not.
4301 */
4302 if (clock->p2 == 7)
4303 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4304 else
4305 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4306
4307 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4308 * appropriately here, but we need to look more thoroughly into how
4309 * panels behave in the two modes.
4310 */
4311 /* set the dithering flag on LVDS as needed */
4312 if (INTEL_INFO(dev)->gen >= 4) {
4313 if (dev_priv->lvds_dither)
4314 temp |= LVDS_ENABLE_DITHER;
4315 else
4316 temp &= ~LVDS_ENABLE_DITHER;
4317 }
284d5df5 4318 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4319 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4320 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4321 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4322 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4323 I915_WRITE(LVDS, temp);
4324}
4325
a0c4da24
JB		 4326static void vlv_update_pll(struct drm_crtc *crtc,
4327 struct drm_display_mode *mode,
4328 struct drm_display_mode *adjusted_mode,
4329 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4330 int num_connectors)
a0c4da24
JB		 4331{
4332 struct drm_device *dev = crtc->dev;
4333 struct drm_i915_private *dev_priv = dev->dev_private;
4334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4335 int pipe = intel_crtc->pipe;
4336 u32 dpll, mdiv, pdiv;
4337 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4338 bool is_sdvo;
4339 u32 temp;
a0c4da24 4340
2a8f64ca
VP		 4341 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4342 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4343
2a8f64ca
VP		 4344 dpll = DPLL_VGA_MODE_DIS;
4345 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4346 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4347 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4348
4349 I915_WRITE(DPLL(pipe), dpll);
4350 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4351
4352 bestn = clock->n;
4353 bestm1 = clock->m1;
4354 bestm2 = clock->m2;
4355 bestp1 = clock->p1;
4356 bestp2 = clock->p2;
4357
2a8f64ca
VP		 4358 /*
4359 * In Valleyview PLL and program lane counter registers are exposed
4360 * through DPIO interface
4361 */
a0c4da24
JB		 4362 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4363 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4364 mdiv |= ((bestn << DPIO_N_SHIFT));
4365 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4366 mdiv |= (1 << DPIO_K_SHIFT);
4367 mdiv |= DPIO_ENABLE_CALIBRATION;
4368 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4369
4370 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4371
2a8f64ca 4372 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4373 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4374 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4375 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4376 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4377
2a8f64ca 4378 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4379
4380 dpll |= DPLL_VCO_ENABLE;
4381 I915_WRITE(DPLL(pipe), dpll);
4382 POSTING_READ(DPLL(pipe));
4383 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4384 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4385
2a8f64ca
VP		 4386 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4387
4388 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4389 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4390
4391 I915_WRITE(DPLL(pipe), dpll);
4392
4393 /* Wait for the clocks to stabilize. */
4394 POSTING_READ(DPLL(pipe));
4395 udelay(150);
a0c4da24 4396
2a8f64ca
VP		 4397 temp = 0;
4398 if (is_sdvo) {
4399 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4400 if (temp > 1)
4401 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4402 else
4403 temp = 0;
a0c4da24 4404 }
2a8f64ca
VP		 4405 I915_WRITE(DPLL_MD(pipe), temp);
4406 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4407
2a8f64ca
VP		 4408 /* Now program lane control registers */
4409 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4410 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4411 {
4412 temp = 0x1000C4;
4413 if(pipe == 1)
4414 temp |= (1 << 21);
4415 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4416 }
4417 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4418 {
4419 temp = 0x1000C4;
4420 if(pipe == 1)
4421 temp |= (1 << 21);
4422 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4423 }
a0c4da24
JB		 4424}
4425
eb1cbe48
DV		 4426static void i9xx_update_pll(struct drm_crtc *crtc,
4427 struct drm_display_mode *mode,
4428 struct drm_display_mode *adjusted_mode,
4429 intel_clock_t *clock, intel_clock_t *reduced_clock,
4430 int num_connectors)
4431{
4432 struct drm_device *dev = crtc->dev;
4433 struct drm_i915_private *dev_priv = dev->dev_private;
4434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4435 int pipe = intel_crtc->pipe;
4436 u32 dpll;
4437 bool is_sdvo;
4438
2a8f64ca
VP		 4439 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4440
eb1cbe48
DV		 4441 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4442 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4443
4444 dpll = DPLL_VGA_MODE_DIS;
4445
4446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4447 dpll |= DPLLB_MODE_LVDS;
4448 else
4449 dpll |= DPLLB_MODE_DAC_SERIAL;
4450 if (is_sdvo) {
4451 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4452 if (pixel_multiplier > 1) {
4453 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4454 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4455 }
4456 dpll |= DPLL_DVO_HIGH_SPEED;
4457 }
4458 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4459 dpll |= DPLL_DVO_HIGH_SPEED;
4460
4461 /* compute bitmask from p1 value */
4462 if (IS_PINEVIEW(dev))
4463 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4464 else {
4465 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4466 if (IS_G4X(dev) && reduced_clock)
4467 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4468 }
4469 switch (clock->p2) {
4470 case 5:
4471 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4472 break;
4473 case 7:
4474 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4475 break;
4476 case 10:
4477 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4478 break;
4479 case 14:
4480 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4481 break;
4482 }
4483 if (INTEL_INFO(dev)->gen >= 4)
4484 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4485
4486 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4487 dpll |= PLL_REF_INPUT_TVCLKINBC;
4488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4489 /* XXX: just matching BIOS for now */
4490 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4491 dpll |= 3;
4492 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4493 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4494 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4495 else
4496 dpll |= PLL_REF_INPUT_DREFCLK;
4497
4498 dpll |= DPLL_VCO_ENABLE;
4499 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4500 POSTING_READ(DPLL(pipe));
4501 udelay(150);
4502
4503 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4504 * This is an exception to the general rule that mode_set doesn't turn
4505 * things on.
4506 */
4507 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4508 intel_update_lvds(crtc, clock, adjusted_mode);
4509
4510 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4511 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4512
4513 I915_WRITE(DPLL(pipe), dpll);
4514
4515 /* Wait for the clocks to stabilize. */
4516 POSTING_READ(DPLL(pipe));
4517 udelay(150);
4518
4519 if (INTEL_INFO(dev)->gen >= 4) {
4520 u32 temp = 0;
4521 if (is_sdvo) {
4522 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4523 if (temp > 1)
4524 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4525 else
4526 temp = 0;
4527 }
4528 I915_WRITE(DPLL_MD(pipe), temp);
4529 } else {
4530 /* The pixel multiplier can only be updated once the
4531 * DPLL is enabled and the clocks are stable.
4532 *
4533 * So write it again.
4534 */
4535 I915_WRITE(DPLL(pipe), dpll);
4536 }
4537}
4538
4539static void i8xx_update_pll(struct drm_crtc *crtc,
4540 struct drm_display_mode *adjusted_mode,
2a8f64ca 4541 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4542 int num_connectors)
4543{
4544 struct drm_device *dev = crtc->dev;
4545 struct drm_i915_private *dev_priv = dev->dev_private;
4546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4547 int pipe = intel_crtc->pipe;
4548 u32 dpll;
4549
2a8f64ca
VP		 4550 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4551
eb1cbe48
DV		 4552 dpll = DPLL_VGA_MODE_DIS;
4553
4554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4555 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4556 } else {
4557 if (clock->p1 == 2)
4558 dpll |= PLL_P1_DIVIDE_BY_TWO;
4559 else
4560 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4561 if (clock->p2 == 4)
4562 dpll |= PLL_P2_DIVIDE_BY_4;
4563 }
4564
4565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4566 /* XXX: just matching BIOS for now */
4567 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4568 dpll |= 3;
4569 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4570 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4571 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4572 else
4573 dpll |= PLL_REF_INPUT_DREFCLK;
4574
4575 dpll |= DPLL_VCO_ENABLE;
4576 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4577 POSTING_READ(DPLL(pipe));
4578 udelay(150);
4579
eb1cbe48
DV		 4580 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4581 * This is an exception to the general rule that mode_set doesn't turn
4582 * things on.
4583 */
4584 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4585 intel_update_lvds(crtc, clock, adjusted_mode);
4586
5b5896e4
DV		 4587 I915_WRITE(DPLL(pipe), dpll);
4588
4589 /* Wait for the clocks to stabilize. */
4590 POSTING_READ(DPLL(pipe));
4591 udelay(150);
4592
eb1cbe48
DV		 4593 /* The pixel multiplier can only be updated once the
4594 * DPLL is enabled and the clocks are stable.
4595 *
4596 * So write it again.
4597 */
4598 I915_WRITE(DPLL(pipe), dpll);
4599}
4600
b0e77b9c
PZ		 4601static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4602 struct drm_display_mode *mode,
4603 struct drm_display_mode *adjusted_mode)
4604{
4605 struct drm_device *dev = intel_crtc->base.dev;
4606 struct drm_i915_private *dev_priv = dev->dev_private;
4607 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4608 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4609 uint32_t vsyncshift;
4610
4611 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4612 /* the chip adds 2 halflines automatically */
4613 adjusted_mode->crtc_vtotal -= 1;
4614 adjusted_mode->crtc_vblank_end -= 1;
4615 vsyncshift = adjusted_mode->crtc_hsync_start
4616 - adjusted_mode->crtc_htotal / 2;
4617 } else {
4618 vsyncshift = 0;
4619 }
4620
4621 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4622 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4623
fe2b8f9d 4624 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4625 (adjusted_mode->crtc_hdisplay - 1) |
4626 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4627 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4628 (adjusted_mode->crtc_hblank_start - 1) |
4629 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4630 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4631 (adjusted_mode->crtc_hsync_start - 1) |
4632 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4633
fe2b8f9d 4634 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4635 (adjusted_mode->crtc_vdisplay - 1) |
4636 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4637 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4638 (adjusted_mode->crtc_vblank_start - 1) |
4639 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4640 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4641 (adjusted_mode->crtc_vsync_start - 1) |
4642 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4643
b5e508d4
PZ		 4644 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4645 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4646 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4647 * bits. */
4648 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4649 (pipe == PIPE_B || pipe == PIPE_C))
4650 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4651
b0e77b9c
PZ		 4652 /* pipesrc controls the size that is scaled from, which should
4653 * always be the user's requested size.
4654 */
4655 I915_WRITE(PIPESRC(pipe),
4656 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4657}
4658
f564048e
EA		 4659static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4660 struct drm_display_mode *mode,
4661 struct drm_display_mode *adjusted_mode,
4662 int x, int y,
94352cf9 4663 struct drm_framebuffer *fb)
79e53945
JB		 4664{
4665 struct drm_device *dev = crtc->dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4668 int pipe = intel_crtc->pipe;
80824003 4669 int plane = intel_crtc->plane;
c751ce4f 4670 int refclk, num_connectors = 0;
652c393a 4671 intel_clock_t clock, reduced_clock;
b0e77b9c 4672 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4673 bool ok, has_reduced_clock = false, is_sdvo = false;
4674 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4675 struct intel_encoder *encoder;
d4906093 4676 const intel_limit_t *limit;
5c3b82e2 4677 int ret;
79e53945 4678
6c2b7c12 4679 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4680 switch (encoder->type) {
79e53945
JB		 4681 case INTEL_OUTPUT_LVDS:
4682 is_lvds = true;
4683 break;
4684 case INTEL_OUTPUT_SDVO:
7d57382e 4685 case INTEL_OUTPUT_HDMI:
79e53945 4686 is_sdvo = true;
5eddb70b 4687 if (encoder->needs_tv_clock)
e2f0ba97 4688 is_tv = true;
79e53945 4689 break;
79e53945
JB		 4690 case INTEL_OUTPUT_TVOUT:
4691 is_tv = true;
4692 break;
a4fc5ed6
KP		 4693 case INTEL_OUTPUT_DISPLAYPORT:
4694 is_dp = true;
4695 break;
79e53945 4696 }
43565a06 4697
c751ce4f 4698 num_connectors++;
79e53945
JB		 4699 }
4700
c65d77d8 4701 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4702
d4906093
ML		 4703 /*
4704 * Returns a set of divisors for the desired target clock with the given
4705 * refclk, or FALSE. The returned values represent the clock equation:
4706 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4707 */
1b894b59 4708 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4709 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4710 &clock);
79e53945
JB		 4711 if (!ok) {
4712 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4713 return -EINVAL;
79e53945
JB		 4714 }
4715
cda4b7d3 4716 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4717 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4718
ddc9003c 4719 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4720 /*
4721 * Ensure we match the reduced clock's P to the target clock.
4722 * If the clocks don't match, we can't switch the display clock
4723 * by using the FP0/FP1. In such case we will disable the LVDS
4724 * downclock feature.
4725 */
ddc9003c 4726 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4727 dev_priv->lvds_downclock,
4728 refclk,
cec2f356 4729 &clock,
5eddb70b 4730 &reduced_clock);
7026d4ac
ZW		 4731 }
4732
c65d77d8
JB		 4733 if (is_sdvo && is_tv)
4734 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4735
eb1cbe48 4736 if (IS_GEN2(dev))
2a8f64ca
VP		 4737 i8xx_update_pll(crtc, adjusted_mode, &clock,
4738 has_reduced_clock ? &reduced_clock : NULL,
4739 num_connectors);
a0c4da24 4740 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4741 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4742 has_reduced_clock ? &reduced_clock : NULL,
4743 num_connectors);
79e53945 4744 else
eb1cbe48
DV		 4745 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4746 has_reduced_clock ? &reduced_clock : NULL,
4747 num_connectors);
79e53945
JB		 4748
4749 /* setup pipeconf */
5eddb70b 4750 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4751
4752 /* Set up the display plane register */
4753 dspcntr = DISPPLANE_GAMMA_ENABLE;
4754
929c77fb
EA		 4755 if (pipe == 0)
4756 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4757 else
4758 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4759
a6c45cf0 4760 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4761 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4762 * core speed.
4763 *
4764 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4765 * pipe == 0 check?
4766 */
e70236a8
JB		 4767 if (mode->clock >
4768 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4769 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4770 else
5eddb70b 4771 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4772 }
4773
3b5c78a3
AJ		 4774 /* default to 8bpc */
4775 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4776 if (is_dp) {
0c96c65b 4777 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4778 pipeconf |= PIPECONF_BPP_6 |
4779 PIPECONF_DITHER_EN |
4780 PIPECONF_DITHER_TYPE_SP;
4781 }
4782 }
4783
19c03924
GB		 4784 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4785 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4786 pipeconf |= PIPECONF_BPP_6 |
4787 PIPECONF_ENABLE |
4788 I965_PIPECONF_ACTIVE;
4789 }
4790 }
4791
28c97730 4792 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4793 drm_mode_debug_printmodeline(mode);
4794
a7516a05
JB		 4795 if (HAS_PIPE_CXSR(dev)) {
4796 if (intel_crtc->lowfreq_avail) {
28c97730 4797 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4798 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4799 } else {
28c97730 4800 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4801 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4802 }
4803 }
4804
617cf884 4805 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4806 if (!IS_GEN2(dev) &&
b0e77b9c 4807 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4808 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4809 else
617cf884 4810 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4811
b0e77b9c 4812 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4813
4814 /* pipesrc and dspsize control the size that is scaled from,
4815 * which should always be the user's requested size.
79e53945 4816 */
929c77fb
EA		 4817 I915_WRITE(DSPSIZE(plane),
4818 ((mode->vdisplay - 1) << 16) |
4819 (mode->hdisplay - 1));
4820 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4821
f564048e
EA		 4822 I915_WRITE(PIPECONF(pipe), pipeconf);
4823 POSTING_READ(PIPECONF(pipe));
929c77fb 4824 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4825
4826 intel_wait_for_vblank(dev, pipe);
4827
f564048e
EA		 4828 I915_WRITE(DSPCNTR(plane), dspcntr);
4829 POSTING_READ(DSPCNTR(plane));
4830
94352cf9 4831 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4832
4833 intel_update_watermarks(dev);
4834
f564048e
EA		 4835 return ret;
4836}
4837
dde86e2d 4838static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4839{
4840 struct drm_i915_private *dev_priv = dev->dev_private;
4841 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4842 struct intel_encoder *encoder;
13d83a67
JB		 4843 u32 temp;
4844 bool has_lvds = false;
199e5d79
KP		 4845 bool has_cpu_edp = false;
4846 bool has_pch_edp = false;
4847 bool has_panel = false;
99eb6a01
KP		 4848 bool has_ck505 = false;
4849 bool can_ssc = false;
13d83a67
JB		 4850
4851 /* We need to take the global config into account */
199e5d79
KP		 4852 list_for_each_entry(encoder, &mode_config->encoder_list,
4853 base.head) {
4854 switch (encoder->type) {
4855 case INTEL_OUTPUT_LVDS:
4856 has_panel = true;
4857 has_lvds = true;
4858 break;
4859 case INTEL_OUTPUT_EDP:
4860 has_panel = true;
4861 if (intel_encoder_is_pch_edp(&encoder->base))
4862 has_pch_edp = true;
4863 else
4864 has_cpu_edp = true;
4865 break;
13d83a67
JB		 4866 }
4867 }
4868
99eb6a01
KP		 4869 if (HAS_PCH_IBX(dev)) {
4870 has_ck505 = dev_priv->display_clock_mode;
4871 can_ssc = has_ck505;
4872 } else {
4873 has_ck505 = false;
4874 can_ssc = true;
4875 }
4876
4877 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4878 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4879 has_ck505);
13d83a67
JB		 4880
4881 /* Ironlake: try to setup display ref clock before DPLL
4882 * enabling. This is only under driver's control after
4883 * PCH B stepping, previous chipset stepping should be
4884 * ignoring this setting.
4885 */
4886 temp = I915_READ(PCH_DREF_CONTROL);
4887 /* Always enable nonspread source */
4888 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4889
99eb6a01
KP		 4890 if (has_ck505)
4891 temp |= DREF_NONSPREAD_CK505_ENABLE;
4892 else
4893 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4894
199e5d79
KP		 4895 if (has_panel) {
4896 temp &= ~DREF_SSC_SOURCE_MASK;
4897 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4898
199e5d79 4899 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4900 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4901 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4902 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4903 } else
4904 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4905
4906 /* Get SSC going before enabling the outputs */
4907 I915_WRITE(PCH_DREF_CONTROL, temp);
4908 POSTING_READ(PCH_DREF_CONTROL);
4909 udelay(200);
4910
13d83a67
JB		 4911 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4912
4913 /* Enable CPU source on CPU attached eDP */
199e5d79 4914 if (has_cpu_edp) {
99eb6a01 4915 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4916 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4917 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4918 }
13d83a67
JB		 4919 else
4920 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4921 } else
4922 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4923
4924 I915_WRITE(PCH_DREF_CONTROL, temp);
4925 POSTING_READ(PCH_DREF_CONTROL);
4926 udelay(200);
4927 } else {
4928 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4929
4930 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4931
4932 /* Turn off CPU output */
4933 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4934
4935 I915_WRITE(PCH_DREF_CONTROL, temp);
4936 POSTING_READ(PCH_DREF_CONTROL);
4937 udelay(200);
4938
4939 /* Turn off the SSC source */
4940 temp &= ~DREF_SSC_SOURCE_MASK;
4941 temp |= DREF_SSC_SOURCE_DISABLE;
4942
4943 /* Turn off SSC1 */
4944 temp &= ~ DREF_SSC1_ENABLE;
4945
13d83a67
JB		 4946 I915_WRITE(PCH_DREF_CONTROL, temp);
4947 POSTING_READ(PCH_DREF_CONTROL);
4948 udelay(200);
4949 }
4950}
4951
dde86e2d
PZ		 4952/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4953static void lpt_init_pch_refclk(struct drm_device *dev)
4954{
4955 struct drm_i915_private *dev_priv = dev->dev_private;
4956 struct drm_mode_config *mode_config = &dev->mode_config;
4957 struct intel_encoder *encoder;
4958 bool has_vga = false;
4959 bool is_sdv = false;
4960 u32 tmp;
4961
4962 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4963 switch (encoder->type) {
4964 case INTEL_OUTPUT_ANALOG:
4965 has_vga = true;
4966 break;
4967 }
4968 }
4969
4970 if (!has_vga)
4971 return;
4972
4973 /* XXX: Rip out SDV support once Haswell ships for real. */
4974 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4975 is_sdv = true;
4976
4977 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4978 tmp &= ~SBI_SSCCTL_DISABLE;
4979 tmp |= SBI_SSCCTL_PATHALT;
4980 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4981
4982 udelay(24);
4983
4984 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4985 tmp &= ~SBI_SSCCTL_PATHALT;
4986 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4987
4988 if (!is_sdv) {
4989 tmp = I915_READ(SOUTH_CHICKEN2);
4990 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4991 I915_WRITE(SOUTH_CHICKEN2, tmp);
4992
4993 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4994 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4995 DRM_ERROR("FDI mPHY reset assert timeout\n");
4996
4997 tmp = I915_READ(SOUTH_CHICKEN2);
4998 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4999 I915_WRITE(SOUTH_CHICKEN2, tmp);
5000
5001 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5002 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5003 100))
5004 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5005 }
5006
5007 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5008 tmp &= ~(0xFF << 24);
5009 tmp |= (0x12 << 24);
5010 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5011
5012 if (!is_sdv) {
5013 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
5014 tmp &= ~(0x3 << 6);
5015 tmp |= (1 << 6) | (1 << 0);
5016 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
5017 }
5018
5019 if (is_sdv) {
5020 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5021 tmp |= 0x7FFF;
5022 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5023 }
5024
5025 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5026 tmp |= (1 << 11);
5027 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5028
5029 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5030 tmp |= (1 << 11);
5031 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5032
5033 if (is_sdv) {
5034 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5035 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5036 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5037
5038 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5039 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5040 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5041
5042 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5043 tmp |= (0x3F << 8);
5044 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5045
5046 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5047 tmp |= (0x3F << 8);
5048 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5049 }
5050
5051 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5052 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5053 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5054
5055 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5056 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5057 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5058
5059 if (!is_sdv) {
5060 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5061 tmp &= ~(7 << 13);
5062 tmp |= (5 << 13);
5063 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5064
5065 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5066 tmp &= ~(7 << 13);
5067 tmp |= (5 << 13);
5068 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5069 }
5070
5071 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5072 tmp &= ~0xFF;
5073 tmp |= 0x1C;
5074 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5075
5076 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5077 tmp &= ~0xFF;
5078 tmp |= 0x1C;
5079 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5080
5081 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5082 tmp &= ~(0xFF << 16);
5083 tmp |= (0x1C << 16);
5084 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5085
5086 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5087 tmp &= ~(0xFF << 16);
5088 tmp |= (0x1C << 16);
5089 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5090
5091 if (!is_sdv) {
5092 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5093 tmp |= (1 << 27);
5094 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5095
5096 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5097 tmp |= (1 << 27);
5098 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5099
5100 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5101 tmp &= ~(0xF << 28);
5102 tmp |= (4 << 28);
5103 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5104
5105 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5106 tmp &= ~(0xF << 28);
5107 tmp |= (4 << 28);
5108 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5109 }
5110
5111 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5112 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5113 tmp |= SBI_DBUFF0_ENABLE;
5114 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5115}
5116
5117/*
5118 * Initialize reference clocks when the driver loads
5119 */
5120void intel_init_pch_refclk(struct drm_device *dev)
5121{
5122 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5123 ironlake_init_pch_refclk(dev);
5124 else if (HAS_PCH_LPT(dev))
5125 lpt_init_pch_refclk(dev);
5126}
5127
d9d444cb
JB		 5128static int ironlake_get_refclk(struct drm_crtc *crtc)
5129{
5130 struct drm_device *dev = crtc->dev;
5131 struct drm_i915_private *dev_priv = dev->dev_private;
5132 struct intel_encoder *encoder;
d9d444cb
JB		 5133 struct intel_encoder *edp_encoder = NULL;
5134 int num_connectors = 0;
5135 bool is_lvds = false;
5136
6c2b7c12 5137 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5138 switch (encoder->type) {
5139 case INTEL_OUTPUT_LVDS:
5140 is_lvds = true;
5141 break;
5142 case INTEL_OUTPUT_EDP:
5143 edp_encoder = encoder;
5144 break;
5145 }
5146 num_connectors++;
5147 }
5148
5149 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5150 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5151 dev_priv->lvds_ssc_freq);
5152 return dev_priv->lvds_ssc_freq * 1000;
5153 }
5154
5155 return 120000;
5156}
5157
c8203565 5158static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5159 struct drm_display_mode *adjusted_mode,
c8203565 5160 bool dither)
79e53945 5161{
c8203565 5162 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5164 int pipe = intel_crtc->pipe;
c8203565
PZ		 5165 uint32_t val;
5166
5167 val = I915_READ(PIPECONF(pipe));
5168
5169 val &= ~PIPE_BPC_MASK;
5170 switch (intel_crtc->bpp) {
5171 case 18:
5172 val |= PIPE_6BPC;
5173 break;
5174 case 24:
5175 val |= PIPE_8BPC;
5176 break;
5177 case 30:
5178 val |= PIPE_10BPC;
5179 break;
5180 case 36:
5181 val |= PIPE_12BPC;
5182 break;
5183 default:
cc769b62
PZ		 5184 /* Case prevented by intel_choose_pipe_bpp_dither. */
5185 BUG();
c8203565
PZ		 5186 }
5187
5188 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5189 if (dither)
5190 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5191
5192 val &= ~PIPECONF_INTERLACE_MASK;
5193 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5194 val |= PIPECONF_INTERLACED_ILK;
5195 else
5196 val |= PIPECONF_PROGRESSIVE;
5197
5198 I915_WRITE(PIPECONF(pipe), val);
5199 POSTING_READ(PIPECONF(pipe));
5200}
5201
ee2b0b38
PZ		 5202static void haswell_set_pipeconf(struct drm_crtc *crtc,
5203 struct drm_display_mode *adjusted_mode,
5204 bool dither)
5205{
5206 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5208 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5209 uint32_t val;
5210
702e7a56 5211 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5212
5213 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5214 if (dither)
5215 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5216
5217 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5218 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5219 val |= PIPECONF_INTERLACED_ILK;
5220 else
5221 val |= PIPECONF_PROGRESSIVE;
5222
702e7a56
PZ		 5223 I915_WRITE(PIPECONF(cpu_transcoder), val);
5224 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5225}
5226
6591c6e4
PZ		 5227static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5228 struct drm_display_mode *adjusted_mode,
5229 intel_clock_t *clock,
5230 bool *has_reduced_clock,
5231 intel_clock_t *reduced_clock)
5232{
5233 struct drm_device *dev = crtc->dev;
5234 struct drm_i915_private *dev_priv = dev->dev_private;
5235 struct intel_encoder *intel_encoder;
5236 int refclk;
d4906093 5237 const intel_limit_t *limit;
6591c6e4 5238 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5239
6591c6e4
PZ		 5240 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5241 switch (intel_encoder->type) {
79e53945
JB		 5242 case INTEL_OUTPUT_LVDS:
5243 is_lvds = true;
5244 break;
5245 case INTEL_OUTPUT_SDVO:
7d57382e 5246 case INTEL_OUTPUT_HDMI:
79e53945 5247 is_sdvo = true;
6591c6e4 5248 if (intel_encoder->needs_tv_clock)
e2f0ba97 5249 is_tv = true;
79e53945 5250 break;
79e53945
JB		 5251 case INTEL_OUTPUT_TVOUT:
5252 is_tv = true;
5253 break;
79e53945
JB		 5254 }
5255 }
5256
d9d444cb 5257 refclk = ironlake_get_refclk(crtc);
79e53945 5258
d4906093
ML		 5259 /*
5260 * Returns a set of divisors for the desired target clock with the given
5261 * refclk, or FALSE. The returned values represent the clock equation:
5262 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5263 */
1b894b59 5264 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5265 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5266 clock);
5267 if (!ret)
5268 return false;
cda4b7d3 5269
ddc9003c 5270 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5271 /*
5272 * Ensure we match the reduced clock's P to the target clock.
5273 * If the clocks don't match, we can't switch the display clock
5274 * by using the FP0/FP1. In such case we will disable the LVDS
5275 * downclock feature.
5276 */
6591c6e4
PZ		 5277 *has_reduced_clock = limit->find_pll(limit, crtc,
5278 dev_priv->lvds_downclock,
5279 refclk,
5280 clock,
5281 reduced_clock);
652c393a 5282 }
61e9653f
DV		 5283
5284 if (is_sdvo && is_tv)
6591c6e4
PZ		 5285 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5286
5287 return true;
5288}
5289
01a415fd
DV		 5290static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5291{
5292 struct drm_i915_private *dev_priv = dev->dev_private;
5293 uint32_t temp;
5294
5295 temp = I915_READ(SOUTH_CHICKEN1);
5296 if (temp & FDI_BC_BIFURCATION_SELECT)
5297 return;
5298
5299 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5300 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5301
5302 temp |= FDI_BC_BIFURCATION_SELECT;
5303 DRM_DEBUG_KMS("enabling fdi C rx\n");
5304 I915_WRITE(SOUTH_CHICKEN1, temp);
5305 POSTING_READ(SOUTH_CHICKEN1);
5306}
5307
5308static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5309{
5310 struct drm_device *dev = intel_crtc->base.dev;
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312 struct intel_crtc *pipe_B_crtc =
5313 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5314
5315 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5316 intel_crtc->pipe, intel_crtc->fdi_lanes);
5317 if (intel_crtc->fdi_lanes > 4) {
5318 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5319 intel_crtc->pipe, intel_crtc->fdi_lanes);
5320 /* Clamp lanes to avoid programming the hw with bogus values. */
5321 intel_crtc->fdi_lanes = 4;
5322
5323 return false;
5324 }
5325
5326 if (dev_priv->num_pipe == 2)
5327 return true;
5328
5329 switch (intel_crtc->pipe) {
5330 case PIPE_A:
5331 return true;
5332 case PIPE_B:
5333 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5334 intel_crtc->fdi_lanes > 2) {
5335 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5336 intel_crtc->pipe, intel_crtc->fdi_lanes);
5337 /* Clamp lanes to avoid programming the hw with bogus values. */
5338 intel_crtc->fdi_lanes = 2;
5339
5340 return false;
5341 }
5342
5343 if (intel_crtc->fdi_lanes > 2)
5344 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5345 else
5346 cpt_enable_fdi_bc_bifurcation(dev);
5347
5348 return true;
5349 case PIPE_C:
5350 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5351 if (intel_crtc->fdi_lanes > 2) {
5352 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5353 intel_crtc->pipe, intel_crtc->fdi_lanes);
5354 /* Clamp lanes to avoid programming the hw with bogus values. */
5355 intel_crtc->fdi_lanes = 2;
5356
5357 return false;
5358 }
5359 } else {
5360 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5361 return false;
5362 }
5363
5364 cpt_enable_fdi_bc_bifurcation(dev);
5365
5366 return true;
5367 default:
5368 BUG();
5369 }
5370}
5371
d4b1931c
PZ		 5372int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5373{
5374 /*
5375 * Account for spread spectrum to avoid
5376 * oversubscribing the link. Max center spread
5377 * is 2.5%; use 5% for safety's sake.
5378 */
5379 u32 bps = target_clock * bpp * 21 / 20;
5380 return bps / (link_bw * 8) + 1;
5381}
5382
f48d8f23
PZ		 5383static void ironlake_set_m_n(struct drm_crtc *crtc,
5384 struct drm_display_mode *mode,
5385 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5386{
5387 struct drm_device *dev = crtc->dev;
5388 struct drm_i915_private *dev_priv = dev->dev_private;
5389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5390 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5391 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
2c07245f 5392 struct fdi_m_n m_n = {0};
f48d8f23
PZ		 5393 int target_clock, pixel_multiplier, lane, link_bw;
5394 bool is_dp = false, is_cpu_edp = false;
79e53945 5395
f48d8f23
PZ		 5396 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5397 switch (intel_encoder->type) {
a4fc5ed6
KP		 5398 case INTEL_OUTPUT_DISPLAYPORT:
5399 is_dp = true;
5400 break;
32f9d658 5401 case INTEL_OUTPUT_EDP:
e3aef172 5402 is_dp = true;
f48d8f23 5403 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5404 is_cpu_edp = true;
f48d8f23 5405 edp_encoder = intel_encoder;
32f9d658 5406 break;
79e53945 5407 }
79e53945 5408 }
61e9653f 5409
2c07245f 5410 /* FDI link */
8febb297
EA		 5411 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5412 lane = 0;
5413 /* CPU eDP doesn't require FDI link, so just set DP M/N
5414 according to current link config */
e3aef172 5415 if (is_cpu_edp) {
e3aef172 5416 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5417 } else {
8febb297
EA		 5418 /* FDI is a binary signal running at ~2.7GHz, encoding
5419 * each output octet as 10 bits. The actual frequency
5420 * is stored as a divider into a 100MHz clock, and the
5421 * mode pixel clock is stored in units of 1KHz.
5422 * Hence the bw of each lane in terms of the mode signal
5423 * is:
5424 */
5425 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5426 }
58a27471 5427
94bf2ced
DV		 5428 /* [e]DP over FDI requires target mode clock instead of link clock. */
5429 if (edp_encoder)
5430 target_clock = intel_edp_target_clock(edp_encoder, mode);
5431 else if (is_dp)
5432 target_clock = mode->clock;
5433 else
5434 target_clock = adjusted_mode->clock;
5435
d4b1931c
PZ		 5436 if (!lane)
5437 lane = ironlake_get_lanes_required(target_clock, link_bw,
5438 intel_crtc->bpp);
2c07245f 5439
8febb297
EA		 5440 intel_crtc->fdi_lanes = lane;
5441
5442 if (pixel_multiplier > 1)
5443 link_bw *= pixel_multiplier;
5a354204
JB		 5444 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5445 &m_n);
8febb297 5446
afe2fcf5
PZ		 5447 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5448 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5449 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5450 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5451}
5452
de13a2e3
PZ		 5453static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5454 struct drm_display_mode *adjusted_mode,
5455 intel_clock_t *clock, u32 fp)
79e53945 5456{
de13a2e3 5457 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5458 struct drm_device *dev = crtc->dev;
5459 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5460 struct intel_encoder *intel_encoder;
5461 uint32_t dpll;
5462 int factor, pixel_multiplier, num_connectors = 0;
5463 bool is_lvds = false, is_sdvo = false, is_tv = false;
5464 bool is_dp = false, is_cpu_edp = false;
79e53945 5465
de13a2e3
PZ		 5466 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5467 switch (intel_encoder->type) {
79e53945
JB		 5468 case INTEL_OUTPUT_LVDS:
5469 is_lvds = true;
5470 break;
5471 case INTEL_OUTPUT_SDVO:
7d57382e 5472 case INTEL_OUTPUT_HDMI:
79e53945 5473 is_sdvo = true;
de13a2e3 5474 if (intel_encoder->needs_tv_clock)
e2f0ba97 5475 is_tv = true;
79e53945 5476 break;
79e53945
JB		 5477 case INTEL_OUTPUT_TVOUT:
5478 is_tv = true;
5479 break;
a4fc5ed6
KP		 5480 case INTEL_OUTPUT_DISPLAYPORT:
5481 is_dp = true;
5482 break;
32f9d658 5483 case INTEL_OUTPUT_EDP:
e3aef172 5484 is_dp = true;
de13a2e3 5485 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5486 is_cpu_edp = true;
32f9d658 5487 break;
79e53945 5488 }
43565a06 5489
c751ce4f 5490 num_connectors++;
79e53945 5491 }
79e53945 5492
c1858123 5493 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5494 factor = 21;
5495 if (is_lvds) {
5496 if ((intel_panel_use_ssc(dev_priv) &&
5497 dev_priv->lvds_ssc_freq == 100) ||
5498 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5499 factor = 25;
5500 } else if (is_sdvo && is_tv)
5501 factor = 20;
c1858123 5502
de13a2e3 5503 if (clock->m < factor * clock->n)
8febb297 5504 fp |= FP_CB_TUNE;
2c07245f 5505
5eddb70b 5506 dpll = 0;
2c07245f 5507
a07d6787
EA		 5508 if (is_lvds)
5509 dpll |= DPLLB_MODE_LVDS;
5510 else
5511 dpll |= DPLLB_MODE_DAC_SERIAL;
5512 if (is_sdvo) {
de13a2e3 5513 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5514 if (pixel_multiplier > 1) {
5515 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5516 }
a07d6787
EA		 5517 dpll |= DPLL_DVO_HIGH_SPEED;
5518 }
e3aef172 5519 if (is_dp && !is_cpu_edp)
a07d6787 5520 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5521
a07d6787 5522 /* compute bitmask from p1 value */
de13a2e3 5523 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5524 /* also FPA1 */
de13a2e3 5525 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5526
de13a2e3 5527 switch (clock->p2) {
a07d6787
EA		 5528 case 5:
5529 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5530 break;
5531 case 7:
5532 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5533 break;
5534 case 10:
5535 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5536 break;
5537 case 14:
5538 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5539 break;
79e53945
JB		 5540 }
5541
43565a06
KH		 5542 if (is_sdvo && is_tv)
5543 dpll |= PLL_REF_INPUT_TVCLKINBC;
5544 else if (is_tv)
79e53945 5545 /* XXX: just matching BIOS for now */
43565a06 5546 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5547 dpll |= 3;
a7615030 5548 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5549 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5550 else
5551 dpll |= PLL_REF_INPUT_DREFCLK;
5552
de13a2e3
PZ		 5553 return dpll;
5554}
5555
5556static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5557 struct drm_display_mode *mode,
5558 struct drm_display_mode *adjusted_mode,
5559 int x, int y,
5560 struct drm_framebuffer *fb)
5561{
5562 struct drm_device *dev = crtc->dev;
5563 struct drm_i915_private *dev_priv = dev->dev_private;
5564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5565 int pipe = intel_crtc->pipe;
5566 int plane = intel_crtc->plane;
5567 int num_connectors = 0;
5568 intel_clock_t clock, reduced_clock;
5569 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5570 bool ok, has_reduced_clock = false;
5571 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5572 struct intel_encoder *encoder;
5573 u32 temp;
5574 int ret;
01a415fd 5575 bool dither, fdi_config_ok;
de13a2e3
PZ		 5576
5577 for_each_encoder_on_crtc(dev, crtc, encoder) {
5578 switch (encoder->type) {
5579 case INTEL_OUTPUT_LVDS:
5580 is_lvds = true;
5581 break;
de13a2e3
PZ		 5582 case INTEL_OUTPUT_DISPLAYPORT:
5583 is_dp = true;
5584 break;
5585 case INTEL_OUTPUT_EDP:
5586 is_dp = true;
e2f12b07 5587 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5588 is_cpu_edp = true;
5589 break;
5590 }
5591
5592 num_connectors++;
a07d6787 5593 }
79e53945 5594
5dc5298b
PZ		 5595 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5596 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5597
de13a2e3
PZ		 5598 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5599 &has_reduced_clock, &reduced_clock);
5600 if (!ok) {
5601 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5602 return -EINVAL;
79e53945
JB		 5603 }
5604
de13a2e3
PZ		 5605 /* Ensure that the cursor is valid for the new mode before changing... */
5606 intel_crtc_update_cursor(crtc, true);
5607
5608 /* determine panel color depth */
c8241969
JN		 5609 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5610 adjusted_mode);
de13a2e3
PZ		 5611 if (is_lvds && dev_priv->lvds_dither)
5612 dither = true;
5613
5614 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5615 if (has_reduced_clock)
5616 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5617 reduced_clock.m2;
5618
5619 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5620
f7cb34d4 5621 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5622 drm_mode_debug_printmodeline(mode);
5623
5dc5298b
PZ		 5624 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5625 if (!is_cpu_edp) {
ee7b9f93 5626 struct intel_pch_pll *pll;
4b645f14 5627
ee7b9f93
JB		 5628 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5629 if (pll == NULL) {
5630 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5631 pipe);
4b645f14
JB		 5632 return -EINVAL;
5633 }
ee7b9f93
JB		 5634 } else
5635 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5636
5637 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5638 * This is an exception to the general rule that mode_set doesn't turn
5639 * things on.
5640 */
5641 if (is_lvds) {
fae14981 5642 temp = I915_READ(PCH_LVDS);
5eddb70b 5643 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5644 if (HAS_PCH_CPT(dev)) {
5645 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5646 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5647 } else {
5648 if (pipe == 1)
5649 temp |= LVDS_PIPEB_SELECT;
5650 else
5651 temp &= ~LVDS_PIPEB_SELECT;
5652 }
4b645f14 5653
a3e17eb8 5654 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5655 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5656 /* Set the B0-B3 data pairs corresponding to whether we're going to
5657 * set the DPLLs for dual-channel mode or not.
5658 */
5659 if (clock.p2 == 7)
5eddb70b 5660 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5661 else
5eddb70b 5662 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5663
5664 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5665 * appropriately here, but we need to look more thoroughly into how
5666 * panels behave in the two modes.
5667 */
284d5df5 5668 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5669 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5670 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5671 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5672 temp |= LVDS_VSYNC_POLARITY;
fae14981 5673 I915_WRITE(PCH_LVDS, temp);
79e53945 5674 }
434ed097 5675
e3aef172 5676 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5677 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5678 } else {
8db9d77b 5679 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5680 I915_WRITE(TRANSDATA_M1(pipe), 0);
5681 I915_WRITE(TRANSDATA_N1(pipe), 0);
5682 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5683 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5684 }
79e53945 5685
ee7b9f93
JB		 5686 if (intel_crtc->pch_pll) {
5687 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5688
32f9d658 5689 /* Wait for the clocks to stabilize. */
ee7b9f93 5690 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5691 udelay(150);
5692
8febb297
EA		 5693 /* The pixel multiplier can only be updated once the
5694 * DPLL is enabled and the clocks are stable.
5695 *
5696 * So write it again.
5697 */
ee7b9f93 5698 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5699 }
79e53945 5700
5eddb70b 5701 intel_crtc->lowfreq_avail = false;
ee7b9f93 5702 if (intel_crtc->pch_pll) {
4b645f14 5703 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5704 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5705 intel_crtc->lowfreq_avail = true;
4b645f14 5706 } else {
ee7b9f93 5707 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5708 }
5709 }
5710
b0e77b9c 5711 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5712
01a415fd
DV		 5713 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5714 * ironlake_check_fdi_lanes. */
f48d8f23 5715 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5716
01a415fd 5717 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5718
e3aef172 5719 if (is_cpu_edp)
8febb297 5720 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5721
c8203565 5722 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5723
9d0498a2 5724 intel_wait_for_vblank(dev, pipe);
79e53945 5725
a1f9e77e
PZ		 5726 /* Set up the display plane register */
5727 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5728 POSTING_READ(DSPCNTR(plane));
79e53945 5729
94352cf9 5730 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5731
5732 intel_update_watermarks(dev);
5733
1f8eeabf
ED		 5734 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5735
01a415fd 5736 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5737}
5738
09b4ddf9
PZ		 5739static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5740 struct drm_display_mode *mode,
5741 struct drm_display_mode *adjusted_mode,
5742 int x, int y,
5743 struct drm_framebuffer *fb)
5744{
5745 struct drm_device *dev = crtc->dev;
5746 struct drm_i915_private *dev_priv = dev->dev_private;
5747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5748 int pipe = intel_crtc->pipe;
5749 int plane = intel_crtc->plane;
5750 int num_connectors = 0;
5751 intel_clock_t clock, reduced_clock;
5dc5298b 5752 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5753 bool ok, has_reduced_clock = false;
5754 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5755 struct intel_encoder *encoder;
5756 u32 temp;
5757 int ret;
5758 bool dither;
5759
5760 for_each_encoder_on_crtc(dev, crtc, encoder) {
5761 switch (encoder->type) {
5762 case INTEL_OUTPUT_LVDS:
5763 is_lvds = true;
5764 break;
5765 case INTEL_OUTPUT_DISPLAYPORT:
5766 is_dp = true;
5767 break;
5768 case INTEL_OUTPUT_EDP:
5769 is_dp = true;
5770 if (!intel_encoder_is_pch_edp(&encoder->base))
5771 is_cpu_edp = true;
5772 break;
5773 }
5774
5775 num_connectors++;
5776 }
5777
a5c961d1
PZ		 5778 if (is_cpu_edp)
5779 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5780 else
5781 intel_crtc->cpu_transcoder = pipe;
5782
5dc5298b
PZ		 5783 /* We are not sure yet this won't happen. */
5784 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5785 INTEL_PCH_TYPE(dev));
5786
5787 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5788 num_connectors, pipe_name(pipe));
5789
702e7a56 5790 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5791 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5792
5793 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5794
6441ab5f
PZ		 5795 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5796 return -EINVAL;
5797
5dc5298b
PZ		 5798 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5799 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5800 &has_reduced_clock,
5801 &reduced_clock);
5802 if (!ok) {
5803 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5804 return -EINVAL;
5805 }
09b4ddf9
PZ		 5806 }
5807
5808 /* Ensure that the cursor is valid for the new mode before changing... */
5809 intel_crtc_update_cursor(crtc, true);
5810
5811 /* determine panel color depth */
c8241969
JN		 5812 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5813 adjusted_mode);
09b4ddf9
PZ		 5814 if (is_lvds && dev_priv->lvds_dither)
5815 dither = true;
5816
09b4ddf9
PZ		 5817 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5818 drm_mode_debug_printmodeline(mode);
5819
5dc5298b
PZ		 5820 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5821 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5822 if (has_reduced_clock)
5823 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5824 reduced_clock.m2;
5825
5826 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5827 fp);
5828
5829 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5830 * own on pre-Haswell/LPT generation */
5831 if (!is_cpu_edp) {
5832 struct intel_pch_pll *pll;
5833
5834 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5835 if (pll == NULL) {
5836 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5837 pipe);
5838 return -EINVAL;
5839 }
5840 } else
5841 intel_put_pch_pll(intel_crtc);
09b4ddf9 5842
5dc5298b
PZ		 5843 /* The LVDS pin pair needs to be on before the DPLLs are
5844 * enabled. This is an exception to the general rule that
5845 * mode_set doesn't turn things on.
5846 */
5847 if (is_lvds) {
5848 temp = I915_READ(PCH_LVDS);
5849 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5850 if (HAS_PCH_CPT(dev)) {
5851 temp &= ~PORT_TRANS_SEL_MASK;
5852 temp |= PORT_TRANS_SEL_CPT(pipe);
5853 } else {
5854 if (pipe == 1)
5855 temp |= LVDS_PIPEB_SELECT;
5856 else
5857 temp &= ~LVDS_PIPEB_SELECT;
5858 }
09b4ddf9 5859
5dc5298b
PZ		 5860 /* set the corresponsding LVDS_BORDER bit */
5861 temp |= dev_priv->lvds_border_bits;
5862 /* Set the B0-B3 data pairs corresponding to whether
5863 * we're going to set the DPLLs for dual-channel mode or
5864 * not.
5865 */
5866 if (clock.p2 == 7)
5867 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5868 else
5dc5298b
PZ		 5869 temp &= ~(LVDS_B0B3_POWER_UP |
5870 LVDS_CLKB_POWER_UP);
5871
5872 /* It would be nice to set 24 vs 18-bit mode
5873 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5874 * look more thoroughly into how panels behave in the
5875 * two modes.
5876 */
5877 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5878 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5879 temp |= LVDS_HSYNC_POLARITY;
5880 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5881 temp |= LVDS_VSYNC_POLARITY;
5882 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5883 }
09b4ddf9
PZ		 5884 }
5885
5886 if (is_dp && !is_cpu_edp) {
5887 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5888 } else {
5dc5298b
PZ		 5889 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5890 /* For non-DP output, clear any trans DP clock recovery
5891 * setting.*/
5892 I915_WRITE(TRANSDATA_M1(pipe), 0);
5893 I915_WRITE(TRANSDATA_N1(pipe), 0);
5894 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5895 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5896 }
09b4ddf9
PZ		 5897 }
5898
5899 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5900 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5901 if (intel_crtc->pch_pll) {
5902 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5903
5904 /* Wait for the clocks to stabilize. */
5905 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5906 udelay(150);
5907
5908 /* The pixel multiplier can only be updated once the
5909 * DPLL is enabled and the clocks are stable.
5910 *
5911 * So write it again.
5912 */
5913 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5914 }
5915
5916 if (intel_crtc->pch_pll) {
5917 if (is_lvds && has_reduced_clock && i915_powersave) {
5918 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5919 intel_crtc->lowfreq_avail = true;
5920 } else {
5921 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5922 }
09b4ddf9
PZ		 5923 }
5924 }
5925
5926 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5927
1eb8dfec
PZ		 5928 if (!is_dp || is_cpu_edp)
5929 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5930
5dc5298b
PZ		 5931 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5932 if (is_cpu_edp)
5933 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5934
ee2b0b38 5935 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5936
09b4ddf9
PZ		 5937 /* Set up the display plane register */
5938 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5939 POSTING_READ(DSPCNTR(plane));
5940
5941 ret = intel_pipe_set_base(crtc, x, y, fb);
5942
5943 intel_update_watermarks(dev);
5944
5945 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5946
1f803ee5 5947 return ret;
79e53945
JB		 5948}
5949
f564048e
EA		 5950static int intel_crtc_mode_set(struct drm_crtc *crtc,
5951 struct drm_display_mode *mode,
5952 struct drm_display_mode *adjusted_mode,
5953 int x, int y,
94352cf9 5954 struct drm_framebuffer *fb)
f564048e
EA		 5955{
5956 struct drm_device *dev = crtc->dev;
5957 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5958 struct drm_encoder_helper_funcs *encoder_funcs;
5959 struct intel_encoder *encoder;
0b701d27
EA		 5960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5961 int pipe = intel_crtc->pipe;
f564048e
EA		 5962 int ret;
5963
0b701d27 5964 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5965
f564048e 5966 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5967 x, y, fb);
79e53945 5968 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5969
9256aa19
DV		 5970 if (ret != 0)
5971 return ret;
5972
5973 for_each_encoder_on_crtc(dev, crtc, encoder) {
5974 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5975 encoder->base.base.id,
5976 drm_get_encoder_name(&encoder->base),
5977 mode->base.id, mode->name);
5978 encoder_funcs = encoder->base.helper_private;
5979 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5980 }
5981
5982 return 0;
79e53945
JB		 5983}
5984
3a9627f4
WF		 5985static bool intel_eld_uptodate(struct drm_connector *connector,
5986 int reg_eldv, uint32_t bits_eldv,
5987 int reg_elda, uint32_t bits_elda,
5988 int reg_edid)
5989{
5990 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5991 uint8_t *eld = connector->eld;
5992 uint32_t i;
5993
5994 i = I915_READ(reg_eldv);
5995 i &= bits_eldv;
5996
5997 if (!eld[0])
5998 return !i;
5999
6000 if (!i)
6001 return false;
6002
6003 i = I915_READ(reg_elda);
6004 i &= ~bits_elda;
6005 I915_WRITE(reg_elda, i);
6006
6007 for (i = 0; i < eld[2]; i++)
6008 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6009 return false;
6010
6011 return true;
6012}
6013
e0dac65e
WF		 6014static void g4x_write_eld(struct drm_connector *connector,
6015 struct drm_crtc *crtc)
6016{
6017 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6018 uint8_t *eld = connector->eld;
6019 uint32_t eldv;
6020 uint32_t len;
6021 uint32_t i;
6022
6023 i = I915_READ(G4X_AUD_VID_DID);
6024
6025 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6026 eldv = G4X_ELDV_DEVCL_DEVBLC;
6027 else
6028 eldv = G4X_ELDV_DEVCTG;
6029
3a9627f4
WF		 6030 if (intel_eld_uptodate(connector,
6031 G4X_AUD_CNTL_ST, eldv,
6032 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6033 G4X_HDMIW_HDMIEDID))
6034 return;
6035
e0dac65e
WF		 6036 i = I915_READ(G4X_AUD_CNTL_ST);
6037 i &= ~(eldv | G4X_ELD_ADDR);
6038 len = (i >> 9) & 0x1f; /* ELD buffer size */
6039 I915_WRITE(G4X_AUD_CNTL_ST, i);
6040
6041 if (!eld[0])
6042 return;
6043
6044 len = min_t(uint8_t, eld[2], len);
6045 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6046 for (i = 0; i < len; i++)
6047 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6048
6049 i = I915_READ(G4X_AUD_CNTL_ST);
6050 i |= eldv;
6051 I915_WRITE(G4X_AUD_CNTL_ST, i);
6052}
6053
83358c85
WX		 6054static void haswell_write_eld(struct drm_connector *connector,
6055 struct drm_crtc *crtc)
6056{
6057 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6058 uint8_t *eld = connector->eld;
6059 struct drm_device *dev = crtc->dev;
6060 uint32_t eldv;
6061 uint32_t i;
6062 int len;
6063 int pipe = to_intel_crtc(crtc)->pipe;
6064 int tmp;
6065
6066 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6067 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6068 int aud_config = HSW_AUD_CFG(pipe);
6069 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6070
6071
6072 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6073
6074 /* Audio output enable */
6075 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6076 tmp = I915_READ(aud_cntrl_st2);
6077 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6078 I915_WRITE(aud_cntrl_st2, tmp);
6079
6080 /* Wait for 1 vertical blank */
6081 intel_wait_for_vblank(dev, pipe);
6082
6083 /* Set ELD valid state */
6084 tmp = I915_READ(aud_cntrl_st2);
6085 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6086 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6087 I915_WRITE(aud_cntrl_st2, tmp);
6088 tmp = I915_READ(aud_cntrl_st2);
6089 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6090
6091 /* Enable HDMI mode */
6092 tmp = I915_READ(aud_config);
6093 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6094 /* clear N_programing_enable and N_value_index */
6095 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6096 I915_WRITE(aud_config, tmp);
6097
6098 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6099
6100 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6101
6102 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6103 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6104 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6105 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6106 } else
6107 I915_WRITE(aud_config, 0);
6108
6109 if (intel_eld_uptodate(connector,
6110 aud_cntrl_st2, eldv,
6111 aud_cntl_st, IBX_ELD_ADDRESS,
6112 hdmiw_hdmiedid))
6113 return;
6114
6115 i = I915_READ(aud_cntrl_st2);
6116 i &= ~eldv;
6117 I915_WRITE(aud_cntrl_st2, i);
6118
6119 if (!eld[0])
6120 return;
6121
6122 i = I915_READ(aud_cntl_st);
6123 i &= ~IBX_ELD_ADDRESS;
6124 I915_WRITE(aud_cntl_st, i);
6125 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6126 DRM_DEBUG_DRIVER("port num:%d\n", i);
6127
6128 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6129 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6130 for (i = 0; i < len; i++)
6131 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6132
6133 i = I915_READ(aud_cntrl_st2);
6134 i |= eldv;
6135 I915_WRITE(aud_cntrl_st2, i);
6136
6137}
6138
e0dac65e
WF		 6139static void ironlake_write_eld(struct drm_connector *connector,
6140 struct drm_crtc *crtc)
6141{
6142 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6143 uint8_t *eld = connector->eld;
6144 uint32_t eldv;
6145 uint32_t i;
6146 int len;
6147 int hdmiw_hdmiedid;
b6daa025 6148 int aud_config;
e0dac65e
WF		 6149 int aud_cntl_st;
6150 int aud_cntrl_st2;
9b138a83 6151 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6152
b3f33cbf 6153 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6154 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6155 aud_config = IBX_AUD_CFG(pipe);
6156 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6157 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6158 } else {
9b138a83
WX		 6159 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6160 aud_config = CPT_AUD_CFG(pipe);
6161 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6162 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6163 }
6164
9b138a83 6165 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6166
6167 i = I915_READ(aud_cntl_st);
9b138a83 6168 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6169 if (!i) {
6170 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6171 /* operate blindly on all ports */
1202b4c6
WF		 6172 eldv = IBX_ELD_VALIDB;
6173 eldv |= IBX_ELD_VALIDB << 4;
6174 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6175 } else {
6176 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6177 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6178 }
6179
3a9627f4
WF		 6180 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6181 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6182 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6183 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6184 } else
6185 I915_WRITE(aud_config, 0);
e0dac65e 6186
3a9627f4
WF		 6187 if (intel_eld_uptodate(connector,
6188 aud_cntrl_st2, eldv,
6189 aud_cntl_st, IBX_ELD_ADDRESS,
6190 hdmiw_hdmiedid))
6191 return;
6192
e0dac65e
WF		 6193 i = I915_READ(aud_cntrl_st2);
6194 i &= ~eldv;
6195 I915_WRITE(aud_cntrl_st2, i);
6196
6197 if (!eld[0])
6198 return;
6199
e0dac65e 6200 i = I915_READ(aud_cntl_st);
1202b4c6 6201 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6202 I915_WRITE(aud_cntl_st, i);
6203
6204 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6205 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6206 for (i = 0; i < len; i++)
6207 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6208
6209 i = I915_READ(aud_cntrl_st2);
6210 i |= eldv;
6211 I915_WRITE(aud_cntrl_st2, i);
6212}
6213
6214void intel_write_eld(struct drm_encoder *encoder,
6215 struct drm_display_mode *mode)
6216{
6217 struct drm_crtc *crtc = encoder->crtc;
6218 struct drm_connector *connector;
6219 struct drm_device *dev = encoder->dev;
6220 struct drm_i915_private *dev_priv = dev->dev_private;
6221
6222 connector = drm_select_eld(encoder, mode);
6223 if (!connector)
6224 return;
6225
6226 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6227 connector->base.id,
6228 drm_get_connector_name(connector),
6229 connector->encoder->base.id,
6230 drm_get_encoder_name(connector->encoder));
6231
6232 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6233
6234 if (dev_priv->display.write_eld)
6235 dev_priv->display.write_eld(connector, crtc);
6236}
6237
79e53945
JB		 6238/** Loads the palette/gamma unit for the CRTC with the prepared values */
6239void intel_crtc_load_lut(struct drm_crtc *crtc)
6240{
6241 struct drm_device *dev = crtc->dev;
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6244 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6245 int i;
6246
6247 /* The clocks have to be on to load the palette. */
aed3f09d 6248 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6249 return;
6250
f2b115e6 6251 /* use legacy palette for Ironlake */
bad720ff 6252 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6253 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6254
79e53945
JB		 6255 for (i = 0; i < 256; i++) {
6256 I915_WRITE(palreg + 4 * i,
6257 (intel_crtc->lut_r[i] << 16) |
6258 (intel_crtc->lut_g[i] << 8) |
6259 intel_crtc->lut_b[i]);
6260 }
6261}
6262
560b85bb
CW		 6263static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6264{
6265 struct drm_device *dev = crtc->dev;
6266 struct drm_i915_private *dev_priv = dev->dev_private;
6267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6268 bool visible = base != 0;
6269 u32 cntl;
6270
6271 if (intel_crtc->cursor_visible == visible)
6272 return;
6273
9db4a9c7 6274 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6275 if (visible) {
6276 /* On these chipsets we can only modify the base whilst
6277 * the cursor is disabled.
6278 */
9db4a9c7 6279 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6280
6281 cntl &= ~(CURSOR_FORMAT_MASK);
6282 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6283 cntl |= CURSOR_ENABLE |
6284 CURSOR_GAMMA_ENABLE |
6285 CURSOR_FORMAT_ARGB;
6286 } else
6287 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6288 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6289
6290 intel_crtc->cursor_visible = visible;
6291}
6292
6293static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6294{
6295 struct drm_device *dev = crtc->dev;
6296 struct drm_i915_private *dev_priv = dev->dev_private;
6297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6298 int pipe = intel_crtc->pipe;
6299 bool visible = base != 0;
6300
6301 if (intel_crtc->cursor_visible != visible) {
548f245b 6302 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6303 if (base) {
6304 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6305 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6306 cntl |= pipe << 28; /* Connect to correct pipe */
6307 } else {
6308 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6309 cntl |= CURSOR_MODE_DISABLE;
6310 }
9db4a9c7 6311 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6312
6313 intel_crtc->cursor_visible = visible;
6314 }
6315 /* and commit changes on next vblank */
9db4a9c7 6316 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6317}
6318
65a21cd6
JB		 6319static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6320{
6321 struct drm_device *dev = crtc->dev;
6322 struct drm_i915_private *dev_priv = dev->dev_private;
6323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6324 int pipe = intel_crtc->pipe;
6325 bool visible = base != 0;
6326
6327 if (intel_crtc->cursor_visible != visible) {
6328 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6329 if (base) {
6330 cntl &= ~CURSOR_MODE;
6331 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6332 } else {
6333 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6334 cntl |= CURSOR_MODE_DISABLE;
6335 }
6336 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6337
6338 intel_crtc->cursor_visible = visible;
6339 }
6340 /* and commit changes on next vblank */
6341 I915_WRITE(CURBASE_IVB(pipe), base);
6342}
6343
cda4b7d3 6344/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6345static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6346 bool on)
cda4b7d3
CW		 6347{
6348 struct drm_device *dev = crtc->dev;
6349 struct drm_i915_private *dev_priv = dev->dev_private;
6350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6351 int pipe = intel_crtc->pipe;
6352 int x = intel_crtc->cursor_x;
6353 int y = intel_crtc->cursor_y;
560b85bb 6354 u32 base, pos;
cda4b7d3
CW		 6355 bool visible;
6356
6357 pos = 0;
6358
6b383a7f 6359 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6360 base = intel_crtc->cursor_addr;
6361 if (x > (int) crtc->fb->width)
6362 base = 0;
6363
6364 if (y > (int) crtc->fb->height)
6365 base = 0;
6366 } else
6367 base = 0;
6368
6369 if (x < 0) {
6370 if (x + intel_crtc->cursor_width < 0)
6371 base = 0;
6372
6373 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6374 x = -x;
6375 }
6376 pos |= x << CURSOR_X_SHIFT;
6377
6378 if (y < 0) {
6379 if (y + intel_crtc->cursor_height < 0)
6380 base = 0;
6381
6382 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6383 y = -y;
6384 }
6385 pos |= y << CURSOR_Y_SHIFT;
6386
6387 visible = base != 0;
560b85bb 6388 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6389 return;
6390
0cd83aa9 6391 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6392 I915_WRITE(CURPOS_IVB(pipe), pos);
6393 ivb_update_cursor(crtc, base);
6394 } else {
6395 I915_WRITE(CURPOS(pipe), pos);
6396 if (IS_845G(dev) || IS_I865G(dev))
6397 i845_update_cursor(crtc, base);
6398 else
6399 i9xx_update_cursor(crtc, base);
6400 }
cda4b7d3
CW		 6401}
6402
79e53945 6403static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6404 struct drm_file *file,
79e53945
JB		 6405 uint32_t handle,
6406 uint32_t width, uint32_t height)
6407{
6408 struct drm_device *dev = crtc->dev;
6409 struct drm_i915_private *dev_priv = dev->dev_private;
6410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6411 struct drm_i915_gem_object *obj;
cda4b7d3 6412 uint32_t addr;
3f8bc370 6413 int ret;
79e53945 6414
79e53945
JB		 6415 /* if we want to turn off the cursor ignore width and height */
6416 if (!handle) {
28c97730 6417 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6418 addr = 0;
05394f39 6419 obj = NULL;
5004417d 6420 mutex_lock(&dev->struct_mutex);
3f8bc370 6421 goto finish;
79e53945
JB		 6422 }
6423
6424 /* Currently we only support 64x64 cursors */
6425 if (width != 64 || height != 64) {
6426 DRM_ERROR("we currently only support 64x64 cursors\n");
6427 return -EINVAL;
6428 }
6429
05394f39 6430 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6431 if (&obj->base == NULL)
79e53945
JB		 6432 return -ENOENT;
6433
05394f39 6434 if (obj->base.size < width * height * 4) {
79e53945 6435 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6436 ret = -ENOMEM;
6437 goto fail;
79e53945
JB		 6438 }
6439
71acb5eb 6440 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6441 mutex_lock(&dev->struct_mutex);
b295d1b6 6442 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6443 if (obj->tiling_mode) {
6444 DRM_ERROR("cursor cannot be tiled\n");
6445 ret = -EINVAL;
6446 goto fail_locked;
6447 }
6448
2da3b9b9 6449 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6450 if (ret) {
6451 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6452 goto fail_locked;
e7b526bb
CW		 6453 }
6454
d9e86c0e
CW		 6455 ret = i915_gem_object_put_fence(obj);
6456 if (ret) {
2da3b9b9 6457 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6458 goto fail_unpin;
6459 }
6460
05394f39 6461 addr = obj->gtt_offset;
71acb5eb 6462 } else {
6eeefaf3 6463 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6464 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6465 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6466 align);
71acb5eb
DA		 6467 if (ret) {
6468 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6469 goto fail_locked;
71acb5eb 6470 }
05394f39 6471 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6472 }
6473
a6c45cf0 6474 if (IS_GEN2(dev))
14b60391
JB		 6475 I915_WRITE(CURSIZE, (height << 12) | width);
6476
3f8bc370 6477 finish:
3f8bc370 6478 if (intel_crtc->cursor_bo) {
b295d1b6 6479 if (dev_priv->info->cursor_needs_physical) {
05394f39 6480 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6481 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6482 } else
6483 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6484 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6485 }
80824003 6486
7f9872e0 6487 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6488
6489 intel_crtc->cursor_addr = addr;
05394f39 6490 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6491 intel_crtc->cursor_width = width;
6492 intel_crtc->cursor_height = height;
6493
6b383a7f 6494 intel_crtc_update_cursor(crtc, true);
3f8bc370 6495
79e53945 6496 return 0;
e7b526bb 6497fail_unpin:
05394f39 6498 i915_gem_object_unpin(obj);
7f9872e0 6499fail_locked:
34b8686e 6500 mutex_unlock(&dev->struct_mutex);
bc9025bd 6501fail:
05394f39 6502 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6503 return ret;
79e53945
JB		 6504}
6505
6506static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6507{
79e53945 6508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6509
cda4b7d3
CW		 6510 intel_crtc->cursor_x = x;
6511 intel_crtc->cursor_y = y;
652c393a 6512
6b383a7f 6513 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6514
6515 return 0;
6516}
6517
6518/** Sets the color ramps on behalf of RandR */
6519void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6520 u16 blue, int regno)
6521{
6522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6523
6524 intel_crtc->lut_r[regno] = red >> 8;
6525 intel_crtc->lut_g[regno] = green >> 8;
6526 intel_crtc->lut_b[regno] = blue >> 8;
6527}
6528
b8c00ac5
DA		 6529void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6530 u16 *blue, int regno)
6531{
6532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6533
6534 *red = intel_crtc->lut_r[regno] << 8;
6535 *green = intel_crtc->lut_g[regno] << 8;
6536 *blue = intel_crtc->lut_b[regno] << 8;
6537}
6538
79e53945 6539static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6540 u16 *blue, uint32_t start, uint32_t size)
79e53945 6541{
7203425a 6542 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6544
7203425a 6545 for (i = start; i < end; i++) {
79e53945
JB		 6546 intel_crtc->lut_r[i] = red[i] >> 8;
6547 intel_crtc->lut_g[i] = green[i] >> 8;
6548 intel_crtc->lut_b[i] = blue[i] >> 8;
6549 }
6550
6551 intel_crtc_load_lut(crtc);
6552}
6553
6554/**
6555 * Get a pipe with a simple mode set on it for doing load-based monitor
6556 * detection.
6557 *
6558 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6559 * its requirements. The pipe will be connected to no other encoders.
79e53945 6560 *
c751ce4f 6561 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6562 * configured for it. In the future, it could choose to temporarily disable
6563 * some outputs to free up a pipe for its use.
6564 *
6565 * \return crtc, or NULL if no pipes are available.
6566 */
6567
6568/* VESA 640x480x72Hz mode to set on the pipe */
6569static struct drm_display_mode load_detect_mode = {
6570 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6571 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6572};
6573
d2dff872
CW		 6574static struct drm_framebuffer *
6575intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6576 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6577 struct drm_i915_gem_object *obj)
6578{
6579 struct intel_framebuffer *intel_fb;
6580 int ret;
6581
6582 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6583 if (!intel_fb) {
6584 drm_gem_object_unreference_unlocked(&obj->base);
6585 return ERR_PTR(-ENOMEM);
6586 }
6587
6588 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6589 if (ret) {
6590 drm_gem_object_unreference_unlocked(&obj->base);
6591 kfree(intel_fb);
6592 return ERR_PTR(ret);
6593 }
6594
6595 return &intel_fb->base;
6596}
6597
6598static u32
6599intel_framebuffer_pitch_for_width(int width, int bpp)
6600{
6601 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6602 return ALIGN(pitch, 64);
6603}
6604
6605static u32
6606intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6607{
6608 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6609 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6610}
6611
6612static struct drm_framebuffer *
6613intel_framebuffer_create_for_mode(struct drm_device *dev,
6614 struct drm_display_mode *mode,
6615 int depth, int bpp)
6616{
6617 struct drm_i915_gem_object *obj;
0fed39bd 6618 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6619
6620 obj = i915_gem_alloc_object(dev,
6621 intel_framebuffer_size_for_mode(mode, bpp));
6622 if (obj == NULL)
6623 return ERR_PTR(-ENOMEM);
6624
6625 mode_cmd.width = mode->hdisplay;
6626 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6627 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6628 bpp);
5ca0c34a 6629 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6630
6631 return intel_framebuffer_create(dev, &mode_cmd, obj);
6632}
6633
6634static struct drm_framebuffer *
6635mode_fits_in_fbdev(struct drm_device *dev,
6636 struct drm_display_mode *mode)
6637{
6638 struct drm_i915_private *dev_priv = dev->dev_private;
6639 struct drm_i915_gem_object *obj;
6640 struct drm_framebuffer *fb;
6641
6642 if (dev_priv->fbdev == NULL)
6643 return NULL;
6644
6645 obj = dev_priv->fbdev->ifb.obj;
6646 if (obj == NULL)
6647 return NULL;
6648
6649 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6650 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6651 fb->bits_per_pixel))
d2dff872
CW		 6652 return NULL;
6653
01f2c773 6654 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6655 return NULL;
6656
6657 return fb;
6658}
6659
d2434ab7 6660bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6661 struct drm_display_mode *mode,
8261b191 6662 struct intel_load_detect_pipe *old)
79e53945
JB		 6663{
6664 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6665 struct intel_encoder *intel_encoder =
6666 intel_attached_encoder(connector);
79e53945 6667 struct drm_crtc *possible_crtc;
4ef69c7a 6668 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6669 struct drm_crtc *crtc = NULL;
6670 struct drm_device *dev = encoder->dev;
94352cf9 6671 struct drm_framebuffer *fb;
79e53945
JB		 6672 int i = -1;
6673
d2dff872
CW		 6674 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6675 connector->base.id, drm_get_connector_name(connector),
6676 encoder->base.id, drm_get_encoder_name(encoder));
6677
79e53945
JB		 6678 /*
6679 * Algorithm gets a little messy:
7a5e4805 6680 *
79e53945
JB		 6681 * - if the connector already has an assigned crtc, use it (but make
6682 * sure it's on first)
7a5e4805 6683 *
79e53945
JB		 6684 * - try to find the first unused crtc that can drive this connector,
6685 * and use that if we find one
79e53945
JB		 6686 */
6687
6688 /* See if we already have a CRTC for this connector */
6689 if (encoder->crtc) {
6690 crtc = encoder->crtc;
8261b191 6691
24218aac 6692 old->dpms_mode = connector->dpms;
8261b191
CW		 6693 old->load_detect_temp = false;
6694
6695 /* Make sure the crtc and connector are running */
24218aac
DV		 6696 if (connector->dpms != DRM_MODE_DPMS_ON)
6697 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6698
7173188d 6699 return true;
79e53945
JB		 6700 }
6701
6702 /* Find an unused one (if possible) */
6703 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6704 i++;
6705 if (!(encoder->possible_crtcs & (1 << i)))
6706 continue;
6707 if (!possible_crtc->enabled) {
6708 crtc = possible_crtc;
6709 break;
6710 }
79e53945
JB		 6711 }
6712
6713 /*
6714 * If we didn't find an unused CRTC, don't use any.
6715 */
6716 if (!crtc) {
7173188d
CW		 6717 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6718 return false;
79e53945
JB		 6719 }
6720
fc303101
DV		 6721 intel_encoder->new_crtc = to_intel_crtc(crtc);
6722 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6723
6724 intel_crtc = to_intel_crtc(crtc);
24218aac 6725 old->dpms_mode = connector->dpms;
8261b191 6726 old->load_detect_temp = true;
d2dff872 6727 old->release_fb = NULL;
79e53945 6728
6492711d
CW		 6729 if (!mode)
6730 mode = &load_detect_mode;
79e53945 6731
d2dff872
CW		 6732 /* We need a framebuffer large enough to accommodate all accesses
6733 * that the plane may generate whilst we perform load detection.
6734 * We can not rely on the fbcon either being present (we get called
6735 * during its initialisation to detect all boot displays, or it may
6736 * not even exist) or that it is large enough to satisfy the
6737 * requested mode.
6738 */
94352cf9
DV		 6739 fb = mode_fits_in_fbdev(dev, mode);
6740 if (fb == NULL) {
d2dff872 6741 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6742 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6743 old->release_fb = fb;
d2dff872
CW		 6744 } else
6745 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6746 if (IS_ERR(fb)) {
d2dff872 6747 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
0e8b3d3e 6748 return false;
79e53945 6749 }
79e53945 6750
94352cf9 6751 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6752 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6753 if (old->release_fb)
6754 old->release_fb->funcs->destroy(old->release_fb);
0e8b3d3e 6755 return false;
79e53945 6756 }
7173188d 6757
79e53945 6758 /* let the connector get through one full cycle before testing */
9d0498a2 6759 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6760 return true;
79e53945
JB		 6761}
6762
d2434ab7 6763void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6764 struct intel_load_detect_pipe *old)
79e53945 6765{
d2434ab7
DV		 6766 struct intel_encoder *intel_encoder =
6767 intel_attached_encoder(connector);
4ef69c7a 6768 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6769
d2dff872
CW		 6770 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6771 connector->base.id, drm_get_connector_name(connector),
6772 encoder->base.id, drm_get_encoder_name(encoder));
6773
8261b191 6774 if (old->load_detect_temp) {
fc303101
DV		 6775 struct drm_crtc *crtc = encoder->crtc;
6776
6777 to_intel_connector(connector)->new_encoder = NULL;
6778 intel_encoder->new_crtc = NULL;
6779 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6780
6781 if (old->release_fb)
6782 old->release_fb->funcs->destroy(old->release_fb);
6783
0622a53c 6784 return;
79e53945
JB		 6785 }
6786
c751ce4f 6787 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6788 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6789 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6790}
6791
6792/* Returns the clock of the currently programmed mode of the given pipe. */
6793static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6794{
6795 struct drm_i915_private *dev_priv = dev->dev_private;
6796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6797 int pipe = intel_crtc->pipe;
548f245b 6798 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6799 u32 fp;
6800 intel_clock_t clock;
6801
6802 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6803 fp = I915_READ(FP0(pipe));
79e53945 6804 else
39adb7a5 6805 fp = I915_READ(FP1(pipe));
79e53945
JB		 6806
6807 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6808 if (IS_PINEVIEW(dev)) {
6809 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6810 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6811 } else {
6812 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6813 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6814 }
6815
a6c45cf0 6816 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6817 if (IS_PINEVIEW(dev))
6818 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6819 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6820 else
6821 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6822 DPLL_FPA01_P1_POST_DIV_SHIFT);
6823
6824 switch (dpll & DPLL_MODE_MASK) {
6825 case DPLLB_MODE_DAC_SERIAL:
6826 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6827 5 : 10;
6828 break;
6829 case DPLLB_MODE_LVDS:
6830 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6831 7 : 14;
6832 break;
6833 default:
28c97730 6834 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6835 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6836 return 0;
6837 }
6838
6839 /* XXX: Handle the 100Mhz refclk */
2177832f 6840 intel_clock(dev, 96000, &clock);
79e53945
JB		 6841 } else {
6842 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6843
6844 if (is_lvds) {
6845 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6846 DPLL_FPA01_P1_POST_DIV_SHIFT);
6847 clock.p2 = 14;
6848
6849 if ((dpll & PLL_REF_INPUT_MASK) ==
6850 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6851 /* XXX: might not be 66MHz */
2177832f 6852 intel_clock(dev, 66000, &clock);
79e53945 6853 } else
2177832f 6854 intel_clock(dev, 48000, &clock);
79e53945
JB		 6855 } else {
6856 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6857 clock.p1 = 2;
6858 else {
6859 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6860 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6861 }
6862 if (dpll & PLL_P2_DIVIDE_BY_4)
6863 clock.p2 = 4;
6864 else
6865 clock.p2 = 2;
6866
2177832f 6867 intel_clock(dev, 48000, &clock);
79e53945
JB		 6868 }
6869 }
6870
6871 /* XXX: It would be nice to validate the clocks, but we can't reuse
6872 * i830PllIsValid() because it relies on the xf86_config connector
6873 * configuration being accurate, which it isn't necessarily.
6874 */
6875
6876 return clock.dot;
6877}
6878
6879/** Returns the currently programmed mode of the given pipe. */
6880struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6881 struct drm_crtc *crtc)
6882{
548f245b 6883 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6885 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6886 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6887 int htot = I915_READ(HTOTAL(cpu_transcoder));
6888 int hsync = I915_READ(HSYNC(cpu_transcoder));
6889 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6890 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6891
6892 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6893 if (!mode)
6894 return NULL;
6895
6896 mode->clock = intel_crtc_clock_get(dev, crtc);
6897 mode->hdisplay = (htot & 0xffff) + 1;
6898 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6899 mode->hsync_start = (hsync & 0xffff) + 1;
6900 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6901 mode->vdisplay = (vtot & 0xffff) + 1;
6902 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6903 mode->vsync_start = (vsync & 0xffff) + 1;
6904 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6905
6906 drm_mode_set_name(mode);
79e53945
JB		 6907
6908 return mode;
6909}
6910
3dec0095 6911static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6912{
6913 struct drm_device *dev = crtc->dev;
6914 drm_i915_private_t *dev_priv = dev->dev_private;
6915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6916 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6917 int dpll_reg = DPLL(pipe);
6918 int dpll;
652c393a 6919
bad720ff 6920 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6921 return;
6922
6923 if (!dev_priv->lvds_downclock_avail)
6924 return;
6925
dbdc6479 6926 dpll = I915_READ(dpll_reg);
652c393a 6927 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6928 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6929
8ac5a6d5 6930 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6931
6932 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6933 I915_WRITE(dpll_reg, dpll);
9d0498a2 6934 intel_wait_for_vblank(dev, pipe);
dbdc6479 6935
652c393a
JB		 6936 dpll = I915_READ(dpll_reg);
6937 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6938 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6939 }
652c393a
JB		 6940}
6941
6942static void intel_decrease_pllclock(struct drm_crtc *crtc)
6943{
6944 struct drm_device *dev = crtc->dev;
6945 drm_i915_private_t *dev_priv = dev->dev_private;
6946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6947
bad720ff 6948 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6949 return;
6950
6951 if (!dev_priv->lvds_downclock_avail)
6952 return;
6953
6954 /*
6955 * Since this is called by a timer, we should never get here in
6956 * the manual case.
6957 */
6958 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6959 int pipe = intel_crtc->pipe;
6960 int dpll_reg = DPLL(pipe);
6961 int dpll;
f6e5b160 6962
44d98a61 6963 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6964
8ac5a6d5 6965 assert_panel_unlocked(dev_priv, pipe);
652c393a 6966
dc257cf1 6967 dpll = I915_READ(dpll_reg);
652c393a
JB		 6968 dpll |= DISPLAY_RATE_SELECT_FPA1;
6969 I915_WRITE(dpll_reg, dpll);
9d0498a2 6970 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6971 dpll = I915_READ(dpll_reg);
6972 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6973 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6974 }
6975
6976}
6977
f047e395
CW		 6978void intel_mark_busy(struct drm_device *dev)
6979{
f047e395
CW		 6980 i915_update_gfx_val(dev->dev_private);
6981}
6982
6983void intel_mark_idle(struct drm_device *dev)
652c393a 6984{
f047e395
CW		 6985}
6986
6987void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6988{
6989 struct drm_device *dev = obj->base.dev;
652c393a 6990 struct drm_crtc *crtc;
652c393a
JB		 6991
6992 if (!i915_powersave)
6993 return;
6994
652c393a 6995 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6996 if (!crtc->fb)
6997 continue;
6998
f047e395
CW		 6999 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7000 intel_increase_pllclock(crtc);
652c393a 7001 }
652c393a
JB		 7002}
7003
f047e395 7004void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 7005{
f047e395
CW		 7006 struct drm_device *dev = obj->base.dev;
7007 struct drm_crtc *crtc;
652c393a 7008
f047e395 7009 if (!i915_powersave)
acb87dfb
CW		 7010 return;
7011
652c393a
JB		 7012 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7013 if (!crtc->fb)
7014 continue;
7015
f047e395
CW		 7016 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7017 intel_decrease_pllclock(crtc);
652c393a
JB		 7018 }
7019}
7020
79e53945
JB		 7021static void intel_crtc_destroy(struct drm_crtc *crtc)
7022{
7023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7024 struct drm_device *dev = crtc->dev;
7025 struct intel_unpin_work *work;
7026 unsigned long flags;
7027
7028 spin_lock_irqsave(&dev->event_lock, flags);
7029 work = intel_crtc->unpin_work;
7030 intel_crtc->unpin_work = NULL;
7031 spin_unlock_irqrestore(&dev->event_lock, flags);
7032
7033 if (work) {
7034 cancel_work_sync(&work->work);
7035 kfree(work);
7036 }
79e53945
JB		 7037
7038 drm_crtc_cleanup(crtc);
67e77c5a 7039
79e53945
JB		 7040 kfree(intel_crtc);
7041}
7042
6b95a207
KH		 7043static void intel_unpin_work_fn(struct work_struct *__work)
7044{
7045 struct intel_unpin_work *work =
7046 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7047 struct drm_device *dev = work->crtc->dev;
6b95a207 7048
b4a98e57 7049 mutex_lock(&dev->struct_mutex);
1690e1eb 7050 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7051 drm_gem_object_unreference(&work->pending_flip_obj->base);
7052 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7053
b4a98e57
CW		 7054 intel_update_fbc(dev);
7055 mutex_unlock(&dev->struct_mutex);
7056
7057 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7058 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7059
6b95a207
KH		 7060 kfree(work);
7061}
7062
1afe3e9d 7063static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7064 struct drm_crtc *crtc)
6b95a207
KH		 7065{
7066 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7068 struct intel_unpin_work *work;
05394f39 7069 struct drm_i915_gem_object *obj;
6b95a207
KH		 7070 unsigned long flags;
7071
7072 /* Ignore early vblank irqs */
7073 if (intel_crtc == NULL)
7074 return;
7075
7076 spin_lock_irqsave(&dev->event_lock, flags);
7077 work = intel_crtc->unpin_work;
e7d841ca
CW		 7078
7079 /* Ensure we don't miss a work->pending update ... */
7080 smp_rmb();
7081
7082 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7083 spin_unlock_irqrestore(&dev->event_lock, flags);
7084 return;
7085 }
7086
e7d841ca
CW		 7087 /* and that the unpin work is consistent wrt ->pending. */
7088 smp_rmb();
7089
6b95a207 7090 intel_crtc->unpin_work = NULL;
6b95a207 7091
45a066eb
RC		 7092 if (work->event)
7093 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7094
0af7e4df
MK		 7095 drm_vblank_put(dev, intel_crtc->pipe);
7096
6b95a207
KH		 7097 spin_unlock_irqrestore(&dev->event_lock, flags);
7098
05394f39 7099 obj = work->old_fb_obj;
d9e86c0e 7100
e59f2bac 7101 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 7102 &obj->pending_flip.counter);
5bb61643 7103 wake_up(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7104
7105 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7106
7107 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7108}
7109
1afe3e9d
JB		 7110void intel_finish_page_flip(struct drm_device *dev, int pipe)
7111{
7112 drm_i915_private_t *dev_priv = dev->dev_private;
7113 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7114
49b14a5c 7115 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7116}
7117
7118void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7119{
7120 drm_i915_private_t *dev_priv = dev->dev_private;
7121 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7122
49b14a5c 7123 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7124}
7125
6b95a207
KH		 7126void intel_prepare_page_flip(struct drm_device *dev, int plane)
7127{
7128 drm_i915_private_t *dev_priv = dev->dev_private;
7129 struct intel_crtc *intel_crtc =
7130 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7131 unsigned long flags;
7132
e7d841ca
CW		 7133 /* NB: An MMIO update of the plane base pointer will also
7134 * generate a page-flip completion irq, i.e. every modeset
7135 * is also accompanied by a spurious intel_prepare_page_flip().
7136 */
6b95a207 7137 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7138 if (intel_crtc->unpin_work)
7139 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7140 spin_unlock_irqrestore(&dev->event_lock, flags);
7141}
7142
e7d841ca
CW		 7143inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7144{
7145 /* Ensure that the work item is consistent when activating it ... */
7146 smp_wmb();
7147 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7148 /* and that it is marked active as soon as the irq could fire. */
7149 smp_wmb();
7150}
7151
8c9f3aaf
JB		 7152static int intel_gen2_queue_flip(struct drm_device *dev,
7153 struct drm_crtc *crtc,
7154 struct drm_framebuffer *fb,
7155 struct drm_i915_gem_object *obj)
7156{
7157 struct drm_i915_private *dev_priv = dev->dev_private;
7158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7159 u32 flip_mask;
6d90c952 7160 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7161 int ret;
7162
6d90c952 7163 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7164 if (ret)
83d4092b 7165 goto err;
8c9f3aaf 7166
6d90c952 7167 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7168 if (ret)
83d4092b 7169 goto err_unpin;
8c9f3aaf
JB		 7170
7171 /* Can't queue multiple flips, so wait for the previous
7172 * one to finish before executing the next.
7173 */
7174 if (intel_crtc->plane)
7175 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7176 else
7177 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7178 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7179 intel_ring_emit(ring, MI_NOOP);
7180 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7181 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7182 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7183 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7184 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7185
7186 intel_mark_page_flip_active(intel_crtc);
6d90c952 7187 intel_ring_advance(ring);
83d4092b
CW		 7188 return 0;
7189
7190err_unpin:
7191 intel_unpin_fb_obj(obj);
7192err:
8c9f3aaf
JB		 7193 return ret;
7194}
7195
7196static int intel_gen3_queue_flip(struct drm_device *dev,
7197 struct drm_crtc *crtc,
7198 struct drm_framebuffer *fb,
7199 struct drm_i915_gem_object *obj)
7200{
7201 struct drm_i915_private *dev_priv = dev->dev_private;
7202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7203 u32 flip_mask;
6d90c952 7204 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7205 int ret;
7206
6d90c952 7207 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7208 if (ret)
83d4092b 7209 goto err;
8c9f3aaf 7210
6d90c952 7211 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7212 if (ret)
83d4092b 7213 goto err_unpin;
8c9f3aaf
JB		 7214
7215 if (intel_crtc->plane)
7216 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7217 else
7218 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7219 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7220 intel_ring_emit(ring, MI_NOOP);
7221 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7222 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7223 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7224 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7225 intel_ring_emit(ring, MI_NOOP);
7226
e7d841ca 7227 intel_mark_page_flip_active(intel_crtc);
6d90c952 7228 intel_ring_advance(ring);
83d4092b
CW		 7229 return 0;
7230
7231err_unpin:
7232 intel_unpin_fb_obj(obj);
7233err:
8c9f3aaf
JB		 7234 return ret;
7235}
7236
7237static int intel_gen4_queue_flip(struct drm_device *dev,
7238 struct drm_crtc *crtc,
7239 struct drm_framebuffer *fb,
7240 struct drm_i915_gem_object *obj)
7241{
7242 struct drm_i915_private *dev_priv = dev->dev_private;
7243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7244 uint32_t pf, pipesrc;
6d90c952 7245 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7246 int ret;
7247
6d90c952 7248 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7249 if (ret)
83d4092b 7250 goto err;
8c9f3aaf 7251
6d90c952 7252 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7253 if (ret)
83d4092b 7254 goto err_unpin;
8c9f3aaf
JB		 7255
7256 /* i965+ uses the linear or tiled offsets from the
7257 * Display Registers (which do not change across a page-flip)
7258 * so we need only reprogram the base address.
7259 */
6d90c952
DV		 7260 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7261 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7262 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7263 intel_ring_emit(ring,
7264 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7265 obj->tiling_mode);
8c9f3aaf
JB		 7266
7267 /* XXX Enabling the panel-fitter across page-flip is so far
7268 * untested on non-native modes, so ignore it for now.
7269 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7270 */
7271 pf = 0;
7272 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7273 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7274
7275 intel_mark_page_flip_active(intel_crtc);
6d90c952 7276 intel_ring_advance(ring);
83d4092b
CW		 7277 return 0;
7278
7279err_unpin:
7280 intel_unpin_fb_obj(obj);
7281err:
8c9f3aaf
JB		 7282 return ret;
7283}
7284
7285static int intel_gen6_queue_flip(struct drm_device *dev,
7286 struct drm_crtc *crtc,
7287 struct drm_framebuffer *fb,
7288 struct drm_i915_gem_object *obj)
7289{
7290 struct drm_i915_private *dev_priv = dev->dev_private;
7291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7292 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7293 uint32_t pf, pipesrc;
7294 int ret;
7295
6d90c952 7296 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7297 if (ret)
83d4092b 7298 goto err;
8c9f3aaf 7299
6d90c952 7300 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7301 if (ret)
83d4092b 7302 goto err_unpin;
8c9f3aaf 7303
6d90c952
DV		 7304 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7305 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7306 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7307 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7308
dc257cf1
DV		 7309 /* Contrary to the suggestions in the documentation,
7310 * "Enable Panel Fitter" does not seem to be required when page
7311 * flipping with a non-native mode, and worse causes a normal
7312 * modeset to fail.
7313 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7314 */
7315 pf = 0;
8c9f3aaf 7316 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7317 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7318
7319 intel_mark_page_flip_active(intel_crtc);
6d90c952 7320 intel_ring_advance(ring);
83d4092b
CW		 7321 return 0;
7322
7323err_unpin:
7324 intel_unpin_fb_obj(obj);
7325err:
8c9f3aaf
JB		 7326 return ret;
7327}
7328
7c9017e5
JB		 7329/*
7330 * On gen7 we currently use the blit ring because (in early silicon at least)
7331 * the render ring doesn't give us interrpts for page flip completion, which
7332 * means clients will hang after the first flip is queued. Fortunately the
7333 * blit ring generates interrupts properly, so use it instead.
7334 */
7335static int intel_gen7_queue_flip(struct drm_device *dev,
7336 struct drm_crtc *crtc,
7337 struct drm_framebuffer *fb,
7338 struct drm_i915_gem_object *obj)
7339{
7340 struct drm_i915_private *dev_priv = dev->dev_private;
7341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7342 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7343 uint32_t plane_bit = 0;
7c9017e5
JB		 7344 int ret;
7345
7346 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7347 if (ret)
83d4092b 7348 goto err;
7c9017e5 7349
cb05d8de
DV		 7350 switch(intel_crtc->plane) {
7351 case PLANE_A:
7352 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7353 break;
7354 case PLANE_B:
7355 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7356 break;
7357 case PLANE_C:
7358 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7359 break;
7360 default:
7361 WARN_ONCE(1, "unknown plane in flip command\n");
7362 ret = -ENODEV;
ab3951eb 7363 goto err_unpin;
cb05d8de
DV		 7364 }
7365
7c9017e5
JB		 7366 ret = intel_ring_begin(ring, 4);
7367 if (ret)
83d4092b 7368 goto err_unpin;
7c9017e5 7369
cb05d8de 7370 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7371 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7372 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7373 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7374
7375 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7376 intel_ring_advance(ring);
83d4092b
CW		 7377 return 0;
7378
7379err_unpin:
7380 intel_unpin_fb_obj(obj);
7381err:
7c9017e5
JB		 7382 return ret;
7383}
7384
8c9f3aaf
JB		 7385static int intel_default_queue_flip(struct drm_device *dev,
7386 struct drm_crtc *crtc,
7387 struct drm_framebuffer *fb,
7388 struct drm_i915_gem_object *obj)
7389{
7390 return -ENODEV;
7391}
7392
6b95a207
KH		 7393static int intel_crtc_page_flip(struct drm_crtc *crtc,
7394 struct drm_framebuffer *fb,
7395 struct drm_pending_vblank_event *event)
7396{
7397 struct drm_device *dev = crtc->dev;
7398 struct drm_i915_private *dev_priv = dev->dev_private;
7399 struct intel_framebuffer *intel_fb;
05394f39 7400 struct drm_i915_gem_object *obj;
6b95a207
KH		 7401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7402 struct intel_unpin_work *work;
8c9f3aaf 7403 unsigned long flags;
52e68630 7404 int ret;
6b95a207 7405
e6a595d2
VS		 7406 /* Can't change pixel format via MI display flips. */
7407 if (fb->pixel_format != crtc->fb->pixel_format)
7408 return -EINVAL;
7409
7410 /*
7411 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7412 * Note that pitch changes could also affect these register.
7413 */
7414 if (INTEL_INFO(dev)->gen > 3 &&
7415 (fb->offsets[0] != crtc->fb->offsets[0] ||
7416 fb->pitches[0] != crtc->fb->pitches[0]))
7417 return -EINVAL;
7418
6b95a207
KH		 7419 work = kzalloc(sizeof *work, GFP_KERNEL);
7420 if (work == NULL)
7421 return -ENOMEM;
7422
6b95a207 7423 work->event = event;
b4a98e57 7424 work->crtc = crtc;
6b95a207 7425 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7426 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7427 INIT_WORK(&work->work, intel_unpin_work_fn);
7428
7317c75e
JB		 7429 ret = drm_vblank_get(dev, intel_crtc->pipe);
7430 if (ret)
7431 goto free_work;
7432
6b95a207
KH		 7433 /* We borrow the event spin lock for protecting unpin_work */
7434 spin_lock_irqsave(&dev->event_lock, flags);
7435 if (intel_crtc->unpin_work) {
7436 spin_unlock_irqrestore(&dev->event_lock, flags);
7437 kfree(work);
7317c75e 7438 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7439
7440 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7441 return -EBUSY;
7442 }
7443 intel_crtc->unpin_work = work;
7444 spin_unlock_irqrestore(&dev->event_lock, flags);
7445
7446 intel_fb = to_intel_framebuffer(fb);
7447 obj = intel_fb->obj;
7448
b4a98e57
CW		 7449 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7450 flush_workqueue(dev_priv->wq);
7451
79158103
CW		 7452 ret = i915_mutex_lock_interruptible(dev);
7453 if (ret)
7454 goto cleanup;
6b95a207 7455
75dfca80 7456 /* Reference the objects for the scheduled work. */
05394f39
CW		 7457 drm_gem_object_reference(&work->old_fb_obj->base);
7458 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7459
7460 crtc->fb = fb;
96b099fd 7461
e1f99ce6 7462 work->pending_flip_obj = obj;
e1f99ce6 7463
4e5359cd
SF		 7464 work->enable_stall_check = true;
7465
e1f99ce6
CW		 7466 /* Block clients from rendering to the new back buffer until
7467 * the flip occurs and the object is no longer visible.
7468 */
05394f39 7469 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
b4a98e57 7470 atomic_inc(&intel_crtc->unpin_work_count);
e1f99ce6 7471
8c9f3aaf
JB		 7472 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7473 if (ret)
7474 goto cleanup_pending;
6b95a207 7475
7782de3b 7476 intel_disable_fbc(dev);
f047e395 7477 intel_mark_fb_busy(obj);
6b95a207
KH		 7478 mutex_unlock(&dev->struct_mutex);
7479
e5510fac
JB		 7480 trace_i915_flip_request(intel_crtc->plane, obj);
7481
6b95a207 7482 return 0;
96b099fd 7483
8c9f3aaf 7484cleanup_pending:
b4a98e57 7485 atomic_dec(&intel_crtc->unpin_work_count);
8c9f3aaf 7486 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7487 drm_gem_object_unreference(&work->old_fb_obj->base);
7488 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7489 mutex_unlock(&dev->struct_mutex);
7490
79158103 7491cleanup:
96b099fd
CW		 7492 spin_lock_irqsave(&dev->event_lock, flags);
7493 intel_crtc->unpin_work = NULL;
7494 spin_unlock_irqrestore(&dev->event_lock, flags);
7495
7317c75e
JB		 7496 drm_vblank_put(dev, intel_crtc->pipe);
7497free_work:
96b099fd
CW		 7498 kfree(work);
7499
7500 return ret;
6b95a207
KH		 7501}
7502
f6e5b160 7503static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7504 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7505 .load_lut = intel_crtc_load_lut,
976f8a20 7506 .disable = intel_crtc_noop,
f6e5b160
CW		 7507};
7508
6ed0f796 7509bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7510{
6ed0f796
DV		 7511 struct intel_encoder *other_encoder;
7512 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7513
6ed0f796
DV		 7514 if (WARN_ON(!crtc))
7515 return false;
7516
7517 list_for_each_entry(other_encoder,
7518 &crtc->dev->mode_config.encoder_list,
7519 base.head) {
7520
7521 if (&other_encoder->new_crtc->base != crtc ||
7522 encoder == other_encoder)
7523 continue;
7524 else
7525 return true;
f47166d2
CW		 7526 }
7527
6ed0f796
DV		 7528 return false;
7529}
47f1c6c9 7530
50f56119
DV		 7531static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7532 struct drm_crtc *crtc)
7533{
7534 struct drm_device *dev;
7535 struct drm_crtc *tmp;
7536 int crtc_mask = 1;
47f1c6c9 7537
50f56119 7538 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7539
50f56119 7540 dev = crtc->dev;
47f1c6c9 7541
50f56119
DV		 7542 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7543 if (tmp == crtc)
7544 break;
7545 crtc_mask <<= 1;
7546 }
47f1c6c9 7547
50f56119
DV		 7548 if (encoder->possible_crtcs & crtc_mask)
7549 return true;
7550 return false;
47f1c6c9 7551}
79e53945 7552
9a935856
DV		 7553/**
7554 * intel_modeset_update_staged_output_state
7555 *
7556 * Updates the staged output configuration state, e.g. after we've read out the
7557 * current hw state.
7558 */
7559static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7560{
9a935856
DV		 7561 struct intel_encoder *encoder;
7562 struct intel_connector *connector;
f6e5b160 7563
9a935856
DV		 7564 list_for_each_entry(connector, &dev->mode_config.connector_list,
7565 base.head) {
7566 connector->new_encoder =
7567 to_intel_encoder(connector->base.encoder);
7568 }
f6e5b160 7569
9a935856
DV		 7570 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7571 base.head) {
7572 encoder->new_crtc =
7573 to_intel_crtc(encoder->base.crtc);
7574 }
f6e5b160
CW		 7575}
7576
9a935856
DV		 7577/**
7578 * intel_modeset_commit_output_state
7579 *
7580 * This function copies the stage display pipe configuration to the real one.
7581 */
7582static void intel_modeset_commit_output_state(struct drm_device *dev)
7583{
7584 struct intel_encoder *encoder;
7585 struct intel_connector *connector;
f6e5b160 7586
9a935856
DV		 7587 list_for_each_entry(connector, &dev->mode_config.connector_list,
7588 base.head) {
7589 connector->base.encoder = &connector->new_encoder->base;
7590 }
f6e5b160 7591
9a935856
DV		 7592 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7593 base.head) {
7594 encoder->base.crtc = &encoder->new_crtc->base;
7595 }
7596}
7597
7758a113
DV		 7598static struct drm_display_mode *
7599intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7600 struct drm_display_mode *mode)
ee7b9f93 7601{
7758a113
DV		 7602 struct drm_device *dev = crtc->dev;
7603 struct drm_display_mode *adjusted_mode;
7604 struct drm_encoder_helper_funcs *encoder_funcs;
7605 struct intel_encoder *encoder;
ee7b9f93 7606
7758a113
DV		 7607 adjusted_mode = drm_mode_duplicate(dev, mode);
7608 if (!adjusted_mode)
7609 return ERR_PTR(-ENOMEM);
7610
7611 /* Pass our mode to the connectors and the CRTC to give them a chance to
7612 * adjust it according to limitations or connector properties, and also
7613 * a chance to reject the mode entirely.
47f1c6c9 7614 */
7758a113
DV		 7615 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7616 base.head) {
47f1c6c9 7617
7758a113
DV		 7618 if (&encoder->new_crtc->base != crtc)
7619 continue;
7620 encoder_funcs = encoder->base.helper_private;
7621 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7622 adjusted_mode))) {
7623 DRM_DEBUG_KMS("Encoder fixup failed\n");
7624 goto fail;
7625 }
ee7b9f93 7626 }
47f1c6c9 7627
7758a113
DV		 7628 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7629 DRM_DEBUG_KMS("CRTC fixup failed\n");
7630 goto fail;
ee7b9f93 7631 }
7758a113 7632 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7633
7758a113
DV		 7634 return adjusted_mode;
7635fail:
7636 drm_mode_destroy(dev, adjusted_mode);
7637 return ERR_PTR(-EINVAL);
ee7b9f93 7638}
47f1c6c9 7639
e2e1ed41
DV		 7640/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7641 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7642static void
7643intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7644 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7645{
7646 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7647 struct drm_device *dev = crtc->dev;
7648 struct intel_encoder *encoder;
7649 struct intel_connector *connector;
7650 struct drm_crtc *tmp_crtc;
79e53945 7651
e2e1ed41 7652 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7653
e2e1ed41
DV		 7654 /* Check which crtcs have changed outputs connected to them, these need
7655 * to be part of the prepare_pipes mask. We don't (yet) support global
7656 * modeset across multiple crtcs, so modeset_pipes will only have one
7657 * bit set at most. */
7658 list_for_each_entry(connector, &dev->mode_config.connector_list,
7659 base.head) {
7660 if (connector->base.encoder == &connector->new_encoder->base)
7661 continue;
79e53945 7662
e2e1ed41
DV		 7663 if (connector->base.encoder) {
7664 tmp_crtc = connector->base.encoder->crtc;
7665
7666 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7667 }
7668
7669 if (connector->new_encoder)
7670 *prepare_pipes |=
7671 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7672 }
7673
e2e1ed41
DV		 7674 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7675 base.head) {
7676 if (encoder->base.crtc == &encoder->new_crtc->base)
7677 continue;
7678
7679 if (encoder->base.crtc) {
7680 tmp_crtc = encoder->base.crtc;
7681
7682 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7683 }
7684
7685 if (encoder->new_crtc)
7686 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7687 }
7688
e2e1ed41
DV		 7689 /* Check for any pipes that will be fully disabled ... */
7690 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7691 base.head) {
7692 bool used = false;
22fd0fab 7693
e2e1ed41
DV		 7694 /* Don't try to disable disabled crtcs. */
7695 if (!intel_crtc->base.enabled)
7696 continue;
7e7d76c3 7697
e2e1ed41
DV		 7698 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7699 base.head) {
7700 if (encoder->new_crtc == intel_crtc)
7701 used = true;
7702 }
7703
7704 if (!used)
7705 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7706 }
7707
e2e1ed41
DV		 7708
7709 /* set_mode is also used to update properties on life display pipes. */
7710 intel_crtc = to_intel_crtc(crtc);
7711 if (crtc->enabled)
7712 *prepare_pipes |= 1 << intel_crtc->pipe;
7713
7714 /* We only support modeset on one single crtc, hence we need to do that
7715 * only for the passed in crtc iff we change anything else than just
7716 * disable crtcs.
7717 *
7718 * This is actually not true, to be fully compatible with the old crtc
7719 * helper we automatically disable _any_ output (i.e. doesn't need to be
7720 * connected to the crtc we're modesetting on) if it's disconnected.
7721 * Which is a rather nutty api (since changed the output configuration
7722 * without userspace's explicit request can lead to confusion), but
7723 * alas. Hence we currently need to modeset on all pipes we prepare. */
7724 if (*prepare_pipes)
7725 *modeset_pipes = *prepare_pipes;
7726
7727 /* ... and mask these out. */
7728 *modeset_pipes &= ~(*disable_pipes);
7729 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7730}
79e53945 7731
ea9d758d 7732static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7733{
ea9d758d 7734 struct drm_encoder *encoder;
f6e5b160 7735 struct drm_device *dev = crtc->dev;
f6e5b160 7736
ea9d758d
DV		 7737 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7738 if (encoder->crtc == crtc)
7739 return true;
7740
7741 return false;
7742}
7743
7744static void
7745intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7746{
7747 struct intel_encoder *intel_encoder;
7748 struct intel_crtc *intel_crtc;
7749 struct drm_connector *connector;
7750
7751 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7752 base.head) {
7753 if (!intel_encoder->base.crtc)
7754 continue;
7755
7756 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7757
7758 if (prepare_pipes & (1 << intel_crtc->pipe))
7759 intel_encoder->connectors_active = false;
7760 }
7761
7762 intel_modeset_commit_output_state(dev);
7763
7764 /* Update computed state. */
7765 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7766 base.head) {
7767 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7768 }
7769
7770 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7771 if (!connector->encoder || !connector->encoder->crtc)
7772 continue;
7773
7774 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7775
7776 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7777 struct drm_property *dpms_property =
7778 dev->mode_config.dpms_property;
7779
ea9d758d 7780 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7781 drm_object_property_set_value(&connector->base,
68d34720
DV		 7782 dpms_property,
7783 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7784
7785 intel_encoder = to_intel_encoder(connector->encoder);
7786 intel_encoder->connectors_active = true;
7787 }
7788 }
7789
7790}
7791
25c5b266
DV		 7792#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7793 list_for_each_entry((intel_crtc), \
7794 &(dev)->mode_config.crtc_list, \
7795 base.head) \
7796 if (mask & (1 <<(intel_crtc)->pipe)) \
7797
b980514c 7798void
8af6cf88
DV		 7799intel_modeset_check_state(struct drm_device *dev)
7800{
7801 struct intel_crtc *crtc;
7802 struct intel_encoder *encoder;
7803 struct intel_connector *connector;
7804
7805 list_for_each_entry(connector, &dev->mode_config.connector_list,
7806 base.head) {
7807 /* This also checks the encoder/connector hw state with the
7808 * ->get_hw_state callbacks. */
7809 intel_connector_check_state(connector);
7810
7811 WARN(&connector->new_encoder->base != connector->base.encoder,
7812 "connector's staged encoder doesn't match current encoder\n");
7813 }
7814
7815 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7816 base.head) {
7817 bool enabled = false;
7818 bool active = false;
7819 enum pipe pipe, tracked_pipe;
7820
7821 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7822 encoder->base.base.id,
7823 drm_get_encoder_name(&encoder->base));
7824
7825 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7826 "encoder's stage crtc doesn't match current crtc\n");
7827 WARN(encoder->connectors_active && !encoder->base.crtc,
7828 "encoder's active_connectors set, but no crtc\n");
7829
7830 list_for_each_entry(connector, &dev->mode_config.connector_list,
7831 base.head) {
7832 if (connector->base.encoder != &encoder->base)
7833 continue;
7834 enabled = true;
7835 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7836 active = true;
7837 }
7838 WARN(!!encoder->base.crtc != enabled,
7839 "encoder's enabled state mismatch "
7840 "(expected %i, found %i)\n",
7841 !!encoder->base.crtc, enabled);
7842 WARN(active && !encoder->base.crtc,
7843 "active encoder with no crtc\n");
7844
7845 WARN(encoder->connectors_active != active,
7846 "encoder's computed active state doesn't match tracked active state "
7847 "(expected %i, found %i)\n", active, encoder->connectors_active);
7848
7849 active = encoder->get_hw_state(encoder, &pipe);
7850 WARN(active != encoder->connectors_active,
7851 "encoder's hw state doesn't match sw tracking "
7852 "(expected %i, found %i)\n",
7853 encoder->connectors_active, active);
7854
7855 if (!encoder->base.crtc)
7856 continue;
7857
7858 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7859 WARN(active && pipe != tracked_pipe,
7860 "active encoder's pipe doesn't match"
7861 "(expected %i, found %i)\n",
7862 tracked_pipe, pipe);
7863
7864 }
7865
7866 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7867 base.head) {
7868 bool enabled = false;
7869 bool active = false;
7870
7871 DRM_DEBUG_KMS("[CRTC:%d]\n",
7872 crtc->base.base.id);
7873
7874 WARN(crtc->active && !crtc->base.enabled,
7875 "active crtc, but not enabled in sw tracking\n");
7876
7877 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7878 base.head) {
7879 if (encoder->base.crtc != &crtc->base)
7880 continue;
7881 enabled = true;
7882 if (encoder->connectors_active)
7883 active = true;
7884 }
7885 WARN(active != crtc->active,
7886 "crtc's computed active state doesn't match tracked active state "
7887 "(expected %i, found %i)\n", active, crtc->active);
7888 WARN(enabled != crtc->base.enabled,
7889 "crtc's computed enabled state doesn't match tracked enabled state "
7890 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7891
7892 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7893 }
7894}
7895
a6778b3c
DV		 7896bool intel_set_mode(struct drm_crtc *crtc,
7897 struct drm_display_mode *mode,
94352cf9 7898 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7899{
7900 struct drm_device *dev = crtc->dev;
dbf2b54e 7901 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7902 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7903 struct intel_crtc *intel_crtc;
7904 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7905 bool ret = true;
7906
e2e1ed41 7907 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7908 &prepare_pipes, &disable_pipes);
7909
7910 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7911 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7912
976f8a20
DV		 7913 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7914 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7915
a6778b3c
DV		 7916 saved_hwmode = crtc->hwmode;
7917 saved_mode = crtc->mode;
a6778b3c 7918
25c5b266
DV		 7919 /* Hack: Because we don't (yet) support global modeset on multiple
7920 * crtcs, we don't keep track of the new mode for more than one crtc.
7921 * Hence simply check whether any bit is set in modeset_pipes in all the
7922 * pieces of code that are not yet converted to deal with mutliple crtcs
7923 * changing their mode at the same time. */
7924 adjusted_mode = NULL;
7925 if (modeset_pipes) {
7926 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7927 if (IS_ERR(adjusted_mode)) {
7928 return false;
7929 }
25c5b266 7930 }
a6778b3c 7931
ea9d758d
DV		 7932 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7933 if (intel_crtc->base.enabled)
7934 dev_priv->display.crtc_disable(&intel_crtc->base);
7935 }
a6778b3c 7936
6c4c86f5
DV		 7937 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7938 * to set it here already despite that we pass it down the callchain.
f6e5b160 7939 */
6c4c86f5 7940 if (modeset_pipes)
25c5b266 7941 crtc->mode = *mode;
7758a113 7942
ea9d758d
DV		 7943 /* Only after disabling all output pipelines that will be changed can we
7944 * update the the output configuration. */
7945 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7946
47fab737
DV		 7947 if (dev_priv->display.modeset_global_resources)
7948 dev_priv->display.modeset_global_resources(dev);
7949
a6778b3c
DV		 7950 /* Set up the DPLL and any encoders state that needs to adjust or depend
7951 * on the DPLL.
f6e5b160 7952 */
25c5b266
DV		 7953 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7954 ret = !intel_crtc_mode_set(&intel_crtc->base,
7955 mode, adjusted_mode,
7956 x, y, fb);
7957 if (!ret)
7958 goto done;
a6778b3c
DV		 7959 }
7960
7961 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7962 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7963 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7964
25c5b266
DV		 7965 if (modeset_pipes) {
7966 /* Store real post-adjustment hardware mode. */
7967 crtc->hwmode = *adjusted_mode;
a6778b3c 7968
25c5b266
DV		 7969 /* Calculate and store various constants which
7970 * are later needed by vblank and swap-completion
7971 * timestamping. They are derived from true hwmode.
7972 */
7973 drm_calc_timestamping_constants(crtc);
7974 }
a6778b3c
DV		 7975
7976 /* FIXME: add subpixel order */
7977done:
7978 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7979 if (!ret && crtc->enabled) {
a6778b3c
DV		 7980 crtc->hwmode = saved_hwmode;
7981 crtc->mode = saved_mode;
8af6cf88
DV		 7982 } else {
7983 intel_modeset_check_state(dev);
a6778b3c
DV		 7984 }
7985
7986 return ret;
f6e5b160
CW		 7987}
7988
25c5b266
DV		 7989#undef for_each_intel_crtc_masked
7990
d9e55608
DV		 7991static void intel_set_config_free(struct intel_set_config *config)
7992{
7993 if (!config)
7994 return;
7995
1aa4b628
DV		 7996 kfree(config->save_connector_encoders);
7997 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7998 kfree(config);
7999}
8000
85f9eb71
DV		 8001static int intel_set_config_save_state(struct drm_device *dev,
8002 struct intel_set_config *config)
8003{
85f9eb71
DV		 8004 struct drm_encoder *encoder;
8005 struct drm_connector *connector;
8006 int count;
8007
1aa4b628
DV		 8008 config->save_encoder_crtcs =
8009 kcalloc(dev->mode_config.num_encoder,
8010 sizeof(struct drm_crtc *), GFP_KERNEL);
8011 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8012 return -ENOMEM;
8013
1aa4b628
DV		 8014 config->save_connector_encoders =
8015 kcalloc(dev->mode_config.num_connector,
8016 sizeof(struct drm_encoder *), GFP_KERNEL);
8017 if (!config->save_connector_encoders)
85f9eb71
DV		 8018 return -ENOMEM;
8019
8020 /* Copy data. Note that driver private data is not affected.
8021 * Should anything bad happen only the expected state is
8022 * restored, not the drivers personal bookkeeping.
8023 */
85f9eb71
DV		 8024 count = 0;
8025 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8026 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8027 }
8028
8029 count = 0;
8030 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8031 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8032 }
8033
8034 return 0;
8035}
8036
8037static void intel_set_config_restore_state(struct drm_device *dev,
8038 struct intel_set_config *config)
8039{
9a935856
DV		 8040 struct intel_encoder *encoder;
8041 struct intel_connector *connector;
85f9eb71
DV		 8042 int count;
8043
85f9eb71 8044 count = 0;
9a935856
DV		 8045 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8046 encoder->new_crtc =
8047 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8048 }
8049
8050 count = 0;
9a935856
DV		 8051 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8052 connector->new_encoder =
8053 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8054 }
8055}
8056
5e2b584e
DV		 8057static void
8058intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8059 struct intel_set_config *config)
8060{
8061
8062 /* We should be able to check here if the fb has the same properties
8063 * and then just flip_or_move it */
8064 if (set->crtc->fb != set->fb) {
8065 /* If we have no fb then treat it as a full mode set */
8066 if (set->crtc->fb == NULL) {
8067 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8068 config->mode_changed = true;
8069 } else if (set->fb == NULL) {
8070 config->mode_changed = true;
8071 } else if (set->fb->depth != set->crtc->fb->depth) {
8072 config->mode_changed = true;
8073 } else if (set->fb->bits_per_pixel !=
8074 set->crtc->fb->bits_per_pixel) {
8075 config->mode_changed = true;
8076 } else
8077 config->fb_changed = true;
8078 }
8079
835c5873 8080 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8081 config->fb_changed = true;
8082
8083 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8084 DRM_DEBUG_KMS("modes are different, full mode set\n");
8085 drm_mode_debug_printmodeline(&set->crtc->mode);
8086 drm_mode_debug_printmodeline(set->mode);
8087 config->mode_changed = true;
8088 }
8089}
8090
2e431051 8091static int
9a935856
DV		 8092intel_modeset_stage_output_state(struct drm_device *dev,
8093 struct drm_mode_set *set,
8094 struct intel_set_config *config)
50f56119 8095{
85f9eb71 8096 struct drm_crtc *new_crtc;
9a935856
DV		 8097 struct intel_connector *connector;
8098 struct intel_encoder *encoder;
2e431051 8099 int count, ro;
50f56119 8100
9a935856
DV		 8101 /* The upper layers ensure that we either disabl a crtc or have a list
8102 * of connectors. For paranoia, double-check this. */
8103 WARN_ON(!set->fb && (set->num_connectors != 0));
8104 WARN_ON(set->fb && (set->num_connectors == 0));
8105
50f56119 8106 count = 0;
9a935856
DV		 8107 list_for_each_entry(connector, &dev->mode_config.connector_list,
8108 base.head) {
8109 /* Otherwise traverse passed in connector list and get encoders
8110 * for them. */
50f56119 8111 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8112 if (set->connectors[ro] == &connector->base) {
8113 connector->new_encoder = connector->encoder;
50f56119
DV		 8114 break;
8115 }
8116 }
8117
9a935856
DV		 8118 /* If we disable the crtc, disable all its connectors. Also, if
8119 * the connector is on the changing crtc but not on the new
8120 * connector list, disable it. */
8121 if ((!set->fb || ro == set->num_connectors) &&
8122 connector->base.encoder &&
8123 connector->base.encoder->crtc == set->crtc) {
8124 connector->new_encoder = NULL;
8125
8126 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8127 connector->base.base.id,
8128 drm_get_connector_name(&connector->base));
8129 }
8130
8131
8132 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8133 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8134 config->mode_changed = true;
50f56119
DV		 8135 }
8136 }
9a935856 8137 /* connector->new_encoder is now updated for all connectors. */
50f56119 8138
9a935856 8139 /* Update crtc of enabled connectors. */
50f56119 8140 count = 0;
9a935856
DV		 8141 list_for_each_entry(connector, &dev->mode_config.connector_list,
8142 base.head) {
8143 if (!connector->new_encoder)
50f56119
DV		 8144 continue;
8145
9a935856 8146 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8147
8148 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8149 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8150 new_crtc = set->crtc;
8151 }
8152
8153 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8154 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8155 new_crtc)) {
5e2b584e 8156 return -EINVAL;
50f56119 8157 }
9a935856
DV		 8158 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8159
8160 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8161 connector->base.base.id,
8162 drm_get_connector_name(&connector->base),
8163 new_crtc->base.id);
8164 }
8165
8166 /* Check for any encoders that needs to be disabled. */
8167 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8168 base.head) {
8169 list_for_each_entry(connector,
8170 &dev->mode_config.connector_list,
8171 base.head) {
8172 if (connector->new_encoder == encoder) {
8173 WARN_ON(!connector->new_encoder->new_crtc);
8174
8175 goto next_encoder;
8176 }
8177 }
8178 encoder->new_crtc = NULL;
8179next_encoder:
8180 /* Only now check for crtc changes so we don't miss encoders
8181 * that will be disabled. */
8182 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8183 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8184 config->mode_changed = true;
50f56119
DV		 8185 }
8186 }
9a935856 8187 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8188
2e431051
DV		 8189 return 0;
8190}
8191
8192static int intel_crtc_set_config(struct drm_mode_set *set)
8193{
8194 struct drm_device *dev;
2e431051
DV		 8195 struct drm_mode_set save_set;
8196 struct intel_set_config *config;
8197 int ret;
2e431051 8198
8d3e375e
DV		 8199 BUG_ON(!set);
8200 BUG_ON(!set->crtc);
8201 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8202
8203 if (!set->mode)
8204 set->fb = NULL;
8205
431e50f7
DV		 8206 /* The fb helper likes to play gross jokes with ->mode_set_config.
8207 * Unfortunately the crtc helper doesn't do much at all for this case,
8208 * so we have to cope with this madness until the fb helper is fixed up. */
8209 if (set->fb && set->num_connectors == 0)
8210 return 0;
8211
2e431051
DV		 8212 if (set->fb) {
8213 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8214 set->crtc->base.id, set->fb->base.id,
8215 (int)set->num_connectors, set->x, set->y);
8216 } else {
8217 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8218 }
8219
8220 dev = set->crtc->dev;
8221
8222 ret = -ENOMEM;
8223 config = kzalloc(sizeof(*config), GFP_KERNEL);
8224 if (!config)
8225 goto out_config;
8226
8227 ret = intel_set_config_save_state(dev, config);
8228 if (ret)
8229 goto out_config;
8230
8231 save_set.crtc = set->crtc;
8232 save_set.mode = &set->crtc->mode;
8233 save_set.x = set->crtc->x;
8234 save_set.y = set->crtc->y;
8235 save_set.fb = set->crtc->fb;
8236
8237 /* Compute whether we need a full modeset, only an fb base update or no
8238 * change at all. In the future we might also check whether only the
8239 * mode changed, e.g. for LVDS where we only change the panel fitter in
8240 * such cases. */
8241 intel_set_config_compute_mode_changes(set, config);
8242
9a935856 8243 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8244 if (ret)
8245 goto fail;
8246
5e2b584e 8247 if (config->mode_changed) {
87f1faa6 8248 if (set->mode) {
50f56119
DV		 8249 DRM_DEBUG_KMS("attempting to set mode from"
8250 " userspace\n");
8251 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8252 }
8253
8254 if (!intel_set_mode(set->crtc, set->mode,
8255 set->x, set->y, set->fb)) {
8256 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8257 set->crtc->base.id);
8258 ret = -EINVAL;
8259 goto fail;
8260 }
5e2b584e 8261 } else if (config->fb_changed) {
4f660f49 8262 ret = intel_pipe_set_base(set->crtc,
94352cf9 8263 set->x, set->y, set->fb);
50f56119
DV		 8264 }
8265
d9e55608
DV		 8266 intel_set_config_free(config);
8267
50f56119
DV		 8268 return 0;
8269
8270fail:
85f9eb71 8271 intel_set_config_restore_state(dev, config);
50f56119
DV		 8272
8273 /* Try to restore the config */
5e2b584e 8274 if (config->mode_changed &&
a6778b3c
DV		 8275 !intel_set_mode(save_set.crtc, save_set.mode,
8276 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8277 DRM_ERROR("failed to restore config after modeset failure\n");
8278
d9e55608
DV		 8279out_config:
8280 intel_set_config_free(config);
50f56119
DV		 8281 return ret;
8282}
f6e5b160
CW		 8283
8284static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8285 .cursor_set = intel_crtc_cursor_set,
8286 .cursor_move = intel_crtc_cursor_move,
8287 .gamma_set = intel_crtc_gamma_set,
50f56119 8288 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8289 .destroy = intel_crtc_destroy,
8290 .page_flip = intel_crtc_page_flip,
8291};
8292
79f689aa
PZ		 8293static void intel_cpu_pll_init(struct drm_device *dev)
8294{
8295 if (IS_HASWELL(dev))
8296 intel_ddi_pll_init(dev);
8297}
8298
ee7b9f93
JB		 8299static void intel_pch_pll_init(struct drm_device *dev)
8300{
8301 drm_i915_private_t *dev_priv = dev->dev_private;
8302 int i;
8303
8304 if (dev_priv->num_pch_pll == 0) {
8305 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8306 return;
8307 }
8308
8309 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8310 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8311 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8312 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8313 }
8314}
8315
b358d0a6 8316static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8317{
22fd0fab 8318 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8319 struct intel_crtc *intel_crtc;
8320 int i;
8321
8322 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8323 if (intel_crtc == NULL)
8324 return;
8325
8326 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8327
8328 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8329 for (i = 0; i < 256; i++) {
8330 intel_crtc->lut_r[i] = i;
8331 intel_crtc->lut_g[i] = i;
8332 intel_crtc->lut_b[i] = i;
8333 }
8334
80824003
JB		 8335 /* Swap pipes & planes for FBC on pre-965 */
8336 intel_crtc->pipe = pipe;
8337 intel_crtc->plane = pipe;
a5c961d1 8338 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8339 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8340 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8341 intel_crtc->plane = !pipe;
80824003
JB		 8342 }
8343
22fd0fab
JB		 8344 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8345 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8346 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8347 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8348
5a354204 8349 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8350
79e53945 8351 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8352}
8353
08d7b3d1 8354int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8355 struct drm_file *file)
08d7b3d1 8356{
08d7b3d1 8357 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8358 struct drm_mode_object *drmmode_obj;
8359 struct intel_crtc *crtc;
08d7b3d1 8360
1cff8f6b
DV		 8361 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8362 return -ENODEV;
08d7b3d1 8363
c05422d5
DV		 8364 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8365 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8366
c05422d5 8367 if (!drmmode_obj) {
08d7b3d1
CW		 8368 DRM_ERROR("no such CRTC id\n");
8369 return -EINVAL;
8370 }
8371
c05422d5
DV		 8372 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8373 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8374
c05422d5 8375 return 0;
08d7b3d1
CW		 8376}
8377
66a9278e 8378static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8379{
66a9278e
DV		 8380 struct drm_device *dev = encoder->base.dev;
8381 struct intel_encoder *source_encoder;
79e53945 8382 int index_mask = 0;
79e53945
JB		 8383 int entry = 0;
8384
66a9278e
DV		 8385 list_for_each_entry(source_encoder,
8386 &dev->mode_config.encoder_list, base.head) {
8387
8388 if (encoder == source_encoder)
79e53945 8389 index_mask |= (1 << entry);
66a9278e
DV		 8390
8391 /* Intel hw has only one MUX where enocoders could be cloned. */
8392 if (encoder->cloneable && source_encoder->cloneable)
8393 index_mask |= (1 << entry);
8394
79e53945
JB		 8395 entry++;
8396 }
4ef69c7a 8397
79e53945
JB		 8398 return index_mask;
8399}
8400
4d302442
CW		 8401static bool has_edp_a(struct drm_device *dev)
8402{
8403 struct drm_i915_private *dev_priv = dev->dev_private;
8404
8405 if (!IS_MOBILE(dev))
8406 return false;
8407
8408 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8409 return false;
8410
8411 if (IS_GEN5(dev) &&
8412 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8413 return false;
8414
8415 return true;
8416}
8417
79e53945
JB		 8418static void intel_setup_outputs(struct drm_device *dev)
8419{
725e30ad 8420 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8421 struct intel_encoder *encoder;
cb0953d7 8422 bool dpd_is_edp = false;
f3cfcba6 8423 bool has_lvds;
79e53945 8424
f3cfcba6 8425 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8426 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8427 /* disable the panel fitter on everything but LVDS */
8428 I915_WRITE(PFIT_CONTROL, 0);
8429 }
79e53945 8430
79935fca
PZ		 8431 if (!(IS_HASWELL(dev) &&
8432 (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8433 intel_crt_init(dev);
cb0953d7 8434
0e72a5b5
ED		 8435 if (IS_HASWELL(dev)) {
8436 int found;
8437
8438 /* Haswell uses DDI functions to detect digital outputs */
8439 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8440 /* DDI A only supports eDP */
8441 if (found)
8442 intel_ddi_init(dev, PORT_A);
8443
8444 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8445 * register */
8446 found = I915_READ(SFUSE_STRAP);
8447
8448 if (found & SFUSE_STRAP_DDIB_DETECTED)
8449 intel_ddi_init(dev, PORT_B);
8450 if (found & SFUSE_STRAP_DDIC_DETECTED)
8451 intel_ddi_init(dev, PORT_C);
8452 if (found & SFUSE_STRAP_DDID_DETECTED)
8453 intel_ddi_init(dev, PORT_D);
8454 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8455 int found;
270b3042
DV		 8456 dpd_is_edp = intel_dpd_is_edp(dev);
8457
8458 if (has_edp_a(dev))
8459 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8460
30ad48b7 8461 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8462 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8463 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8464 if (!found)
08d644ad 8465 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8466 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8467 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8468 }
8469
8470 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8471 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8472
b708a1d5 8473 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8474 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8475
5eb08b69 8476 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8477 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8478
270b3042 8479 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8480 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8481 } else if (IS_VALLEYVIEW(dev)) {
8482 int found;
8483
19c03924
GB		 8484 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8485 if (I915_READ(DP_C) & DP_DETECTED)
8486 intel_dp_init(dev, DP_C, PORT_C);
8487
4a87d65d
JB		 8488 if (I915_READ(SDVOB) & PORT_DETECTED) {
8489 /* SDVOB multiplex with HDMIB */
8490 found = intel_sdvo_init(dev, SDVOB, true);
8491 if (!found)
08d644ad 8492 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8493 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8494 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8495 }
8496
8497 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8498 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8499
103a196f 8500 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8501 bool found = false;
7d57382e 8502
725e30ad 8503 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8504 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8505 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8506 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8507 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8508 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8509 }
27185ae1 8510
b01f2c3a
JB		 8511 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8512 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8513 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8514 }
725e30ad 8515 }
13520b05
KH		 8516
8517 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8518
b01f2c3a
JB		 8519 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8520 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8521 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8522 }
27185ae1
ML		 8523
8524 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8525
b01f2c3a
JB		 8526 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8527 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8528 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8529 }
8530 if (SUPPORTS_INTEGRATED_DP(dev)) {
8531 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8532 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8533 }
725e30ad 8534 }
27185ae1 8535
b01f2c3a
JB		 8536 if (SUPPORTS_INTEGRATED_DP(dev) &&
8537 (I915_READ(DP_D) & DP_DETECTED)) {
8538 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8539 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8540 }
bad720ff 8541 } else if (IS_GEN2(dev))
79e53945
JB		 8542 intel_dvo_init(dev);
8543
103a196f 8544 if (SUPPORTS_TV(dev))
79e53945
JB		 8545 intel_tv_init(dev);
8546
4ef69c7a
CW		 8547 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8548 encoder->base.possible_crtcs = encoder->crtc_mask;
8549 encoder->base.possible_clones =
66a9278e 8550 intel_encoder_clones(encoder);
79e53945 8551 }
47356eb6 8552
dde86e2d 8553 intel_init_pch_refclk(dev);
270b3042
DV		 8554
8555 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8556}
8557
8558static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8559{
8560 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8561
8562 drm_framebuffer_cleanup(fb);
05394f39 8563 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8564
8565 kfree(intel_fb);
8566}
8567
8568static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8569 struct drm_file *file,
79e53945
JB		 8570 unsigned int *handle)
8571{
8572 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8573 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8574
05394f39 8575 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8576}
8577
8578static const struct drm_framebuffer_funcs intel_fb_funcs = {
8579 .destroy = intel_user_framebuffer_destroy,
8580 .create_handle = intel_user_framebuffer_create_handle,
8581};
8582
38651674
DA		 8583int intel_framebuffer_init(struct drm_device *dev,
8584 struct intel_framebuffer *intel_fb,
308e5bcb 8585 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8586 struct drm_i915_gem_object *obj)
79e53945 8587{
79e53945
JB		 8588 int ret;
8589
05394f39 8590 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8591 return -EINVAL;
8592
308e5bcb 8593 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8594 return -EINVAL;
8595
5d7bd705
VS		 8596 /* FIXME <= Gen4 stride limits are bit unclear */
8597 if (mode_cmd->pitches[0] > 32768)
8598 return -EINVAL;
8599
8600 if (obj->tiling_mode != I915_TILING_NONE &&
8601 mode_cmd->pitches[0] != obj->stride)
8602 return -EINVAL;
8603
57779d06 8604 /* Reject formats not supported by any plane early. */
308e5bcb 8605 switch (mode_cmd->pixel_format) {
57779d06 8606 case DRM_FORMAT_C8:
04b3924d
VS		 8607 case DRM_FORMAT_RGB565:
8608 case DRM_FORMAT_XRGB8888:
8609 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8610 break;
8611 case DRM_FORMAT_XRGB1555:
8612 case DRM_FORMAT_ARGB1555:
8613 if (INTEL_INFO(dev)->gen > 3)
8614 return -EINVAL;
8615 break;
8616 case DRM_FORMAT_XBGR8888:
8617 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8618 case DRM_FORMAT_XRGB2101010:
8619 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8620 case DRM_FORMAT_XBGR2101010:
8621 case DRM_FORMAT_ABGR2101010:
8622 if (INTEL_INFO(dev)->gen < 4)
8623 return -EINVAL;
b5626747 8624 break;
04b3924d
VS		 8625 case DRM_FORMAT_YUYV:
8626 case DRM_FORMAT_UYVY:
8627 case DRM_FORMAT_YVYU:
8628 case DRM_FORMAT_VYUY:
57779d06
VS		 8629 if (INTEL_INFO(dev)->gen < 6)
8630 return -EINVAL;
57cd6508
CW		 8631 break;
8632 default:
57779d06 8633 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8634 return -EINVAL;
8635 }
8636
90f9a336
VS		 8637 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8638 if (mode_cmd->offsets[0] != 0)
8639 return -EINVAL;
8640
79e53945
JB		 8641 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8642 if (ret) {
8643 DRM_ERROR("framebuffer init failed %d\n", ret);
8644 return ret;
8645 }
8646
8647 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8648 intel_fb->obj = obj;
79e53945
JB		 8649 return 0;
8650}
8651
79e53945
JB		 8652static struct drm_framebuffer *
8653intel_user_framebuffer_create(struct drm_device *dev,
8654 struct drm_file *filp,
308e5bcb 8655 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8656{
05394f39 8657 struct drm_i915_gem_object *obj;
79e53945 8658
308e5bcb
JB		 8659 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8660 mode_cmd->handles[0]));
c8725226 8661 if (&obj->base == NULL)
cce13ff7 8662 return ERR_PTR(-ENOENT);
79e53945 8663
d2dff872 8664 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8665}
8666
79e53945 8667static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8668 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8669 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8670};
8671
e70236a8
JB		 8672/* Set up chip specific display functions */
8673static void intel_init_display(struct drm_device *dev)
8674{
8675 struct drm_i915_private *dev_priv = dev->dev_private;
8676
8677 /* We always want a DPMS function */
09b4ddf9
PZ		 8678 if (IS_HASWELL(dev)) {
8679 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8680 dev_priv->display.crtc_enable = haswell_crtc_enable;
8681 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8682 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8683 dev_priv->display.update_plane = ironlake_update_plane;
8684 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8685 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8686 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8687 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8688 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8689 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8690 } else {
f564048e 8691 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8692 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8693 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8694 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8695 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8696 }
e70236a8 8697
e70236a8 8698 /* Returns the core display clock speed */
25eb05fc
JB		 8699 if (IS_VALLEYVIEW(dev))
8700 dev_priv->display.get_display_clock_speed =
8701 valleyview_get_display_clock_speed;
8702 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8703 dev_priv->display.get_display_clock_speed =
8704 i945_get_display_clock_speed;
8705 else if (IS_I915G(dev))
8706 dev_priv->display.get_display_clock_speed =
8707 i915_get_display_clock_speed;
f2b115e6 8708 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8709 dev_priv->display.get_display_clock_speed =
8710 i9xx_misc_get_display_clock_speed;
8711 else if (IS_I915GM(dev))
8712 dev_priv->display.get_display_clock_speed =
8713 i915gm_get_display_clock_speed;
8714 else if (IS_I865G(dev))
8715 dev_priv->display.get_display_clock_speed =
8716 i865_get_display_clock_speed;
f0f8a9ce 8717 else if (IS_I85X(dev))
e70236a8
JB		 8718 dev_priv->display.get_display_clock_speed =
8719 i855_get_display_clock_speed;
8720 else /* 852, 830 */
8721 dev_priv->display.get_display_clock_speed =
8722 i830_get_display_clock_speed;
8723
7f8a8569 8724 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8725 if (IS_GEN5(dev)) {
674cf967 8726 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8727 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8728 } else if (IS_GEN6(dev)) {
674cf967 8729 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8730 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8731 } else if (IS_IVYBRIDGE(dev)) {
8732 /* FIXME: detect B0+ stepping and use auto training */
8733 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8734 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8735 dev_priv->display.modeset_global_resources =
8736 ivb_modeset_global_resources;
c82e4d26
ED		 8737 } else if (IS_HASWELL(dev)) {
8738 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8739 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8740 } else
8741 dev_priv->display.update_wm = NULL;
6067aaea 8742 } else if (IS_G4X(dev)) {
e0dac65e 8743 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8744 }
8c9f3aaf
JB		 8745
8746 /* Default just returns -ENODEV to indicate unsupported */
8747 dev_priv->display.queue_flip = intel_default_queue_flip;
8748
8749 switch (INTEL_INFO(dev)->gen) {
8750 case 2:
8751 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8752 break;
8753
8754 case 3:
8755 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8756 break;
8757
8758 case 4:
8759 case 5:
8760 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8761 break;
8762
8763 case 6:
8764 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8765 break;
7c9017e5
JB		 8766 case 7:
8767 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8768 break;
8c9f3aaf 8769 }
e70236a8
JB		 8770}
8771
b690e96c
JB		 8772/*
8773 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8774 * resume, or other times. This quirk makes sure that's the case for
8775 * affected systems.
8776 */
0206e353 8777static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8778{
8779 struct drm_i915_private *dev_priv = dev->dev_private;
8780
8781 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8782 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8783}
8784
435793df
KP		 8785/*
8786 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8787 */
8788static void quirk_ssc_force_disable(struct drm_device *dev)
8789{
8790 struct drm_i915_private *dev_priv = dev->dev_private;
8791 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8792 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8793}
8794
4dca20ef 8795/*
5a15ab5b
CE		 8796 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8797 * brightness value
4dca20ef
CE		 8798 */
8799static void quirk_invert_brightness(struct drm_device *dev)
8800{
8801 struct drm_i915_private *dev_priv = dev->dev_private;
8802 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8803 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8804}
8805
b690e96c
JB		 8806struct intel_quirk {
8807 int device;
8808 int subsystem_vendor;
8809 int subsystem_device;
8810 void (*hook)(struct drm_device *dev);
8811};
8812
5f85f176
EE		 8813/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8814struct intel_dmi_quirk {
8815 void (*hook)(struct drm_device *dev);
8816 const struct dmi_system_id (*dmi_id_list)[];
8817};
8818
8819static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8820{
8821 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8822 return 1;
8823}
8824
8825static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8826 {
8827 .dmi_id_list = &(const struct dmi_system_id[]) {
8828 {
8829 .callback = intel_dmi_reverse_brightness,
8830 .ident = "NCR Corporation",
8831 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8832 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8833 },
8834 },
8835 { } /* terminating entry */
8836 },
8837 .hook = quirk_invert_brightness,
8838 },
8839};
8840
c43b5634 8841static struct intel_quirk intel_quirks[] = {
b690e96c 8842 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8843 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8844
b690e96c
JB		 8845 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8846 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8847
b690e96c
JB		 8848 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8849 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8850
ccd0d36e 8851 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8852 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8853 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8854
8855 /* Lenovo U160 cannot use SSC on LVDS */
8856 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8857
8858 /* Sony Vaio Y cannot use SSC on LVDS */
8859 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8860
8861 /* Acer Aspire 5734Z must invert backlight brightness */
8862 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8863};
8864
8865static void intel_init_quirks(struct drm_device *dev)
8866{
8867 struct pci_dev *d = dev->pdev;
8868 int i;
8869
8870 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8871 struct intel_quirk *q = &intel_quirks[i];
8872
8873 if (d->device == q->device &&
8874 (d->subsystem_vendor == q->subsystem_vendor ||
8875 q->subsystem_vendor == PCI_ANY_ID) &&
8876 (d->subsystem_device == q->subsystem_device ||
8877 q->subsystem_device == PCI_ANY_ID))
8878 q->hook(dev);
8879 }
5f85f176
EE		 8880 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8881 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8882 intel_dmi_quirks[i].hook(dev);
8883 }
b690e96c
JB		 8884}
8885
9cce37f4
JB		 8886/* Disable the VGA plane that we never use */
8887static void i915_disable_vga(struct drm_device *dev)
8888{
8889 struct drm_i915_private *dev_priv = dev->dev_private;
8890 u8 sr1;
8891 u32 vga_reg;
8892
8893 if (HAS_PCH_SPLIT(dev))
8894 vga_reg = CPU_VGACNTRL;
8895 else
8896 vga_reg = VGACNTRL;
8897
8898 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8899 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8900 sr1 = inb(VGA_SR_DATA);
8901 outb(sr1 | 1<<5, VGA_SR_DATA);
8902 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8903 udelay(300);
8904
8905 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8906 POSTING_READ(vga_reg);
8907}
8908
f817586c
DV		 8909void intel_modeset_init_hw(struct drm_device *dev)
8910{
0232e927
ED		 8911 /* We attempt to init the necessary power wells early in the initialization
8912 * time, so the subsystems that expect power to be enabled can work.
8913 */
8914 intel_init_power_wells(dev);
8915
a8f78b58
ED		 8916 intel_prepare_ddi(dev);
8917
f817586c
DV		 8918 intel_init_clock_gating(dev);
8919
79f5b2c7 8920 mutex_lock(&dev->struct_mutex);
8090c6b9 8921 intel_enable_gt_powersave(dev);
79f5b2c7 8922 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8923}
8924
79e53945
JB		 8925void intel_modeset_init(struct drm_device *dev)
8926{
652c393a 8927 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8928 int i, ret;
79e53945
JB		 8929
8930 drm_mode_config_init(dev);
8931
8932 dev->mode_config.min_width = 0;
8933 dev->mode_config.min_height = 0;
8934
019d96cb
DA		 8935 dev->mode_config.preferred_depth = 24;
8936 dev->mode_config.prefer_shadow = 1;
8937
e6ecefaa 8938 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8939
b690e96c
JB		 8940 intel_init_quirks(dev);
8941
1fa61106
ED		 8942 intel_init_pm(dev);
8943
e70236a8
JB		 8944 intel_init_display(dev);
8945
a6c45cf0
CW		 8946 if (IS_GEN2(dev)) {
8947 dev->mode_config.max_width = 2048;
8948 dev->mode_config.max_height = 2048;
8949 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8950 dev->mode_config.max_width = 4096;
8951 dev->mode_config.max_height = 4096;
79e53945 8952 } else {
a6c45cf0
CW		 8953 dev->mode_config.max_width = 8192;
8954 dev->mode_config.max_height = 8192;
79e53945 8955 }
dd2757f8 8956 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8957
28c97730 8958 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8959 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8960
a3524f1b 8961 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8962 intel_crtc_init(dev, i);
00c2064b
JB		 8963 ret = intel_plane_init(dev, i);
8964 if (ret)
8965 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8966 }
8967
79f689aa 8968 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8969 intel_pch_pll_init(dev);
8970
9cce37f4
JB		 8971 /* Just disable it once at startup */
8972 i915_disable_vga(dev);
79e53945 8973 intel_setup_outputs(dev);
2c7111db
CW		 8974}
8975
24929352
DV		 8976static void
8977intel_connector_break_all_links(struct intel_connector *connector)
8978{
8979 connector->base.dpms = DRM_MODE_DPMS_OFF;
8980 connector->base.encoder = NULL;
8981 connector->encoder->connectors_active = false;
8982 connector->encoder->base.crtc = NULL;
8983}
8984
7fad798e
DV		 8985static void intel_enable_pipe_a(struct drm_device *dev)
8986{
8987 struct intel_connector *connector;
8988 struct drm_connector *crt = NULL;
8989 struct intel_load_detect_pipe load_detect_temp;
8990
8991 /* We can't just switch on the pipe A, we need to set things up with a
8992 * proper mode and output configuration. As a gross hack, enable pipe A
8993 * by enabling the load detect pipe once. */
8994 list_for_each_entry(connector,
8995 &dev->mode_config.connector_list,
8996 base.head) {
8997 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8998 crt = &connector->base;
8999 break;
9000 }
9001 }
9002
9003 if (!crt)
9004 return;
9005
9006 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9007 intel_release_load_detect_pipe(crt, &load_detect_temp);
9008
652c393a 9009
7fad798e
DV		 9010}
9011
fa555837
DV		 9012static bool
9013intel_check_plane_mapping(struct intel_crtc *crtc)
9014{
9015 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
9016 u32 reg, val;
9017
9018 if (dev_priv->num_pipe == 1)
9019 return true;
9020
9021 reg = DSPCNTR(!crtc->plane);
9022 val = I915_READ(reg);
9023
9024 if ((val & DISPLAY_PLANE_ENABLE) &&
9025 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9026 return false;
9027
9028 return true;
9029}
9030
24929352
DV		 9031static void intel_sanitize_crtc(struct intel_crtc *crtc)
9032{
9033 struct drm_device *dev = crtc->base.dev;
9034 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9035 u32 reg;
24929352 9036
24929352 9037 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 9038 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 9039 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9040
9041 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9042 * disable the crtc (and hence change the state) if it is wrong. Note
9043 * that gen4+ has a fixed plane -> pipe mapping. */
9044 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9045 struct intel_connector *connector;
9046 bool plane;
9047
24929352
DV		 9048 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9049 crtc->base.base.id);
9050
9051 /* Pipe has the wrong plane attached and the plane is active.
9052 * Temporarily change the plane mapping and disable everything
9053 * ... */
9054 plane = crtc->plane;
9055 crtc->plane = !plane;
9056 dev_priv->display.crtc_disable(&crtc->base);
9057 crtc->plane = plane;
9058
9059 /* ... and break all links. */
9060 list_for_each_entry(connector, &dev->mode_config.connector_list,
9061 base.head) {
9062 if (connector->encoder->base.crtc != &crtc->base)
9063 continue;
9064
9065 intel_connector_break_all_links(connector);
9066 }
9067
9068 WARN_ON(crtc->active);
9069 crtc->base.enabled = false;
9070 }
24929352 9071
7fad798e
DV		 9072 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9073 crtc->pipe == PIPE_A && !crtc->active) {
9074 /* BIOS forgot to enable pipe A, this mostly happens after
9075 * resume. Force-enable the pipe to fix this, the update_dpms
9076 * call below we restore the pipe to the right state, but leave
9077 * the required bits on. */
9078 intel_enable_pipe_a(dev);
9079 }
9080
24929352
DV		 9081 /* Adjust the state of the output pipe according to whether we
9082 * have active connectors/encoders. */
9083 intel_crtc_update_dpms(&crtc->base);
9084
9085 if (crtc->active != crtc->base.enabled) {
9086 struct intel_encoder *encoder;
9087
9088 /* This can happen either due to bugs in the get_hw_state
9089 * functions or because the pipe is force-enabled due to the
9090 * pipe A quirk. */
9091 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9092 crtc->base.base.id,
9093 crtc->base.enabled ? "enabled" : "disabled",
9094 crtc->active ? "enabled" : "disabled");
9095
9096 crtc->base.enabled = crtc->active;
9097
9098 /* Because we only establish the connector -> encoder ->
9099 * crtc links if something is active, this means the
9100 * crtc is now deactivated. Break the links. connector
9101 * -> encoder links are only establish when things are
9102 * actually up, hence no need to break them. */
9103 WARN_ON(crtc->active);
9104
9105 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9106 WARN_ON(encoder->connectors_active);
9107 encoder->base.crtc = NULL;
9108 }
9109 }
9110}
9111
9112static void intel_sanitize_encoder(struct intel_encoder *encoder)
9113{
9114 struct intel_connector *connector;
9115 struct drm_device *dev = encoder->base.dev;
9116
9117 /* We need to check both for a crtc link (meaning that the
9118 * encoder is active and trying to read from a pipe) and the
9119 * pipe itself being active. */
9120 bool has_active_crtc = encoder->base.crtc &&
9121 to_intel_crtc(encoder->base.crtc)->active;
9122
9123 if (encoder->connectors_active && !has_active_crtc) {
9124 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9125 encoder->base.base.id,
9126 drm_get_encoder_name(&encoder->base));
9127
9128 /* Connector is active, but has no active pipe. This is
9129 * fallout from our resume register restoring. Disable
9130 * the encoder manually again. */
9131 if (encoder->base.crtc) {
9132 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9133 encoder->base.base.id,
9134 drm_get_encoder_name(&encoder->base));
9135 encoder->disable(encoder);
9136 }
9137
9138 /* Inconsistent output/port/pipe state happens presumably due to
9139 * a bug in one of the get_hw_state functions. Or someplace else
9140 * in our code, like the register restore mess on resume. Clamp
9141 * things to off as a safer default. */
9142 list_for_each_entry(connector,
9143 &dev->mode_config.connector_list,
9144 base.head) {
9145 if (connector->encoder != encoder)
9146 continue;
9147
9148 intel_connector_break_all_links(connector);
9149 }
9150 }
9151 /* Enabled encoders without active connectors will be fixed in
9152 * the crtc fixup. */
9153}
9154
9155/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9156 * and i915 state tracking structures. */
45e2b5f6
DV		 9157void intel_modeset_setup_hw_state(struct drm_device *dev,
9158 bool force_restore)
24929352
DV		 9159{
9160 struct drm_i915_private *dev_priv = dev->dev_private;
9161 enum pipe pipe;
9162 u32 tmp;
9163 struct intel_crtc *crtc;
9164 struct intel_encoder *encoder;
9165 struct intel_connector *connector;
9166
e28d54cb
PZ		 9167 if (IS_HASWELL(dev)) {
9168 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9169
9170 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9171 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9172 case TRANS_DDI_EDP_INPUT_A_ON:
9173 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9174 pipe = PIPE_A;
9175 break;
9176 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9177 pipe = PIPE_B;
9178 break;
9179 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9180 pipe = PIPE_C;
9181 break;
9182 }
9183
9184 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9185 crtc->cpu_transcoder = TRANSCODER_EDP;
9186
9187 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9188 pipe_name(pipe));
9189 }
9190 }
9191
24929352
DV		 9192 for_each_pipe(pipe) {
9193 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9194
702e7a56 9195 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9196 if (tmp & PIPECONF_ENABLE)
9197 crtc->active = true;
9198 else
9199 crtc->active = false;
9200
9201 crtc->base.enabled = crtc->active;
9202
9203 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9204 crtc->base.base.id,
9205 crtc->active ? "enabled" : "disabled");
9206 }
9207
6441ab5f
PZ		 9208 if (IS_HASWELL(dev))
9209 intel_ddi_setup_hw_pll_state(dev);
9210
24929352
DV		 9211 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9212 base.head) {
9213 pipe = 0;
9214
9215 if (encoder->get_hw_state(encoder, &pipe)) {
9216 encoder->base.crtc =
9217 dev_priv->pipe_to_crtc_mapping[pipe];
9218 } else {
9219 encoder->base.crtc = NULL;
9220 }
9221
9222 encoder->connectors_active = false;
9223 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9224 encoder->base.base.id,
9225 drm_get_encoder_name(&encoder->base),
9226 encoder->base.crtc ? "enabled" : "disabled",
9227 pipe);
9228 }
9229
9230 list_for_each_entry(connector, &dev->mode_config.connector_list,
9231 base.head) {
9232 if (connector->get_hw_state(connector)) {
9233 connector->base.dpms = DRM_MODE_DPMS_ON;
9234 connector->encoder->connectors_active = true;
9235 connector->base.encoder = &connector->encoder->base;
9236 } else {
9237 connector->base.dpms = DRM_MODE_DPMS_OFF;
9238 connector->base.encoder = NULL;
9239 }
9240 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9241 connector->base.base.id,
9242 drm_get_connector_name(&connector->base),
9243 connector->base.encoder ? "enabled" : "disabled");
9244 }
9245
9246 /* HW state is read out, now we need to sanitize this mess. */
9247 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9248 base.head) {
9249 intel_sanitize_encoder(encoder);
9250 }
9251
9252 for_each_pipe(pipe) {
9253 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9254 intel_sanitize_crtc(crtc);
9255 }
9a935856 9256
45e2b5f6
DV		 9257 if (force_restore) {
9258 for_each_pipe(pipe) {
9259 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9260 intel_set_mode(&crtc->base, &crtc->base.mode,
9261 crtc->base.x, crtc->base.y, crtc->base.fb);
9262 }
9263 } else {
9264 intel_modeset_update_staged_output_state(dev);
9265 }
8af6cf88
DV		 9266
9267 intel_modeset_check_state(dev);
2e938892
DV		 9268
9269 drm_mode_config_reset(dev);
2c7111db
CW		 9270}
9271
9272void intel_modeset_gem_init(struct drm_device *dev)
9273{
1833b134 9274 intel_modeset_init_hw(dev);
02e792fb
DV		 9275
9276 intel_setup_overlay(dev);
24929352 9277
45e2b5f6 9278 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9279}
9280
9281void intel_modeset_cleanup(struct drm_device *dev)
9282{
652c393a
JB		 9283 struct drm_i915_private *dev_priv = dev->dev_private;
9284 struct drm_crtc *crtc;
9285 struct intel_crtc *intel_crtc;
9286
f87ea761 9287 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9288 mutex_lock(&dev->struct_mutex);
9289
723bfd70
JB		 9290 intel_unregister_dsm_handler();
9291
9292
652c393a
JB		 9293 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9294 /* Skip inactive CRTCs */
9295 if (!crtc->fb)
9296 continue;
9297
9298 intel_crtc = to_intel_crtc(crtc);
3dec0095 9299 intel_increase_pllclock(crtc);
652c393a
JB		 9300 }
9301
973d04f9 9302 intel_disable_fbc(dev);
e70236a8 9303
8090c6b9 9304 intel_disable_gt_powersave(dev);
0cdab21f 9305
930ebb46
DV		 9306 ironlake_teardown_rc6(dev);
9307
57f350b6
JB		 9308 if (IS_VALLEYVIEW(dev))
9309 vlv_init_dpio(dev);
9310
69341a5e
KH		 9311 mutex_unlock(&dev->struct_mutex);
9312
6c0d9350
DV		 9313 /* Disable the irq before mode object teardown, for the irq might
9314 * enqueue unpin/hotplug work. */
9315 drm_irq_uninstall(dev);
9316 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9317 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9318
1630fe75
CW		 9319 /* flush any delayed tasks or pending work */
9320 flush_scheduled_work();
9321
79e53945
JB		 9322 drm_mode_config_cleanup(dev);
9323}
9324
f1c79df3
ZW		 9325/*
9326 * Return which encoder is currently attached for connector.
9327 */
df0e9248 9328struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9329{
df0e9248
CW		 9330 return &intel_attached_encoder(connector)->base;
9331}
f1c79df3 9332
df0e9248
CW		 9333void intel_connector_attach_encoder(struct intel_connector *connector,
9334 struct intel_encoder *encoder)
9335{
9336 connector->encoder = encoder;
9337 drm_mode_connector_attach_encoder(&connector->base,
9338 &encoder->base);
79e53945 9339}
28d52043
DA		 9340
9341/*
9342 * set vga decode state - true == enable VGA decode
9343 */
9344int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9345{
9346 struct drm_i915_private *dev_priv = dev->dev_private;
9347 u16 gmch_ctrl;
9348
9349 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9350 if (state)
9351 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9352 else
9353 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9354 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9355 return 0;
9356}
c4a1d9e4
CW		 9357
9358#ifdef CONFIG_DEBUG_FS
9359#include <linux/seq_file.h>
9360
9361struct intel_display_error_state {
9362 struct intel_cursor_error_state {
9363 u32 control;
9364 u32 position;
9365 u32 base;
9366 u32 size;
52331309 9367 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9368
9369 struct intel_pipe_error_state {
9370 u32 conf;
9371 u32 source;
9372
9373 u32 htotal;
9374 u32 hblank;
9375 u32 hsync;
9376 u32 vtotal;
9377 u32 vblank;
9378 u32 vsync;
52331309 9379 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9380
9381 struct intel_plane_error_state {
9382 u32 control;
9383 u32 stride;
9384 u32 size;
9385 u32 pos;
9386 u32 addr;
9387 u32 surface;
9388 u32 tile_offset;
52331309 9389 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9390};
9391
9392struct intel_display_error_state *
9393intel_display_capture_error_state(struct drm_device *dev)
9394{
0206e353 9395 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9396 struct intel_display_error_state *error;
702e7a56 9397 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9398 int i;
9399
9400 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9401 if (error == NULL)
9402 return NULL;
9403
52331309 9404 for_each_pipe(i) {
702e7a56
PZ		 9405 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9406
c4a1d9e4
CW		 9407 error->cursor[i].control = I915_READ(CURCNTR(i));
9408 error->cursor[i].position = I915_READ(CURPOS(i));
9409 error->cursor[i].base = I915_READ(CURBASE(i));
9410
9411 error->plane[i].control = I915_READ(DSPCNTR(i));
9412 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9413 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9414 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9415 error->plane[i].addr = I915_READ(DSPADDR(i));
9416 if (INTEL_INFO(dev)->gen >= 4) {
9417 error->plane[i].surface = I915_READ(DSPSURF(i));
9418 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9419 }
9420
702e7a56 9421 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9422 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9423 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9424 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9425 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9426 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9427 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9428 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9429 }
9430
9431 return error;
9432}
9433
9434void
9435intel_display_print_error_state(struct seq_file *m,
9436 struct drm_device *dev,
9437 struct intel_display_error_state *error)
9438{
52331309 9439 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9440 int i;
9441
52331309
DL		 9442 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9443 for_each_pipe(i) {
c4a1d9e4
CW		 9444 seq_printf(m, "Pipe [%d]:\n", i);
9445 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9446 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9447 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9448 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9449 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9450 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9451 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9452 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9453
9454 seq_printf(m, "Plane [%d]:\n", i);
9455 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9456 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9457 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9458 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9459 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9460 if (INTEL_INFO(dev)->gen >= 4) {
9461 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9462 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9463 }
9464
9465 seq_printf(m, "Cursor [%d]:\n", i);
9466 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9467 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9468 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9469 }
9470}
9471#endif
Linux kernel - Deliverables
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